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// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA driver for VIA VT82xx (South Bridge) * * VT82C686A/B/C, VT8233A/C, VT8235 * * Copyright (c) 2000 Jaroslav Kysela <[email protected]> * Tjeerd.Mulder <[email protected]> * 2002 Takashi Iwai <[email protected]> */ /* * Changes: * * Dec. 19, 2002 Takashi Iwai <[email protected]> * - use the DSX channels for the first pcm playback. * (on VIA8233, 8233C and 8235 only) * this will allow you play simultaneously up to 4 streams. * multi-channel playback is assigned to the second device * on these chips. * - support the secondary capture (on VIA8233/C,8235) * - SPDIF support * the DSX3 channel can be used for SPDIF output. * on VIA8233A, this channel is assigned to the second pcm * playback. * the card config of alsa-lib will assign the correct * device for applications. * - clean up the code, separate low-level initialization * routines for each chipset. * * Sep. 26, 2005 Karsten Wiese <[email protected]> * - Optimize position calculation for the 823x chips. */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/info.h> #include <sound/tlv.h> #include <sound/ac97_codec.h> #include <sound/mpu401.h> #include <sound/initval.h> #if 0 #define POINTER_DEBUG #endif MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("VIA VT82xx audio"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ static long mpu_port; #ifdef SUPPORT_JOYSTICK static bool joystick; #endif static int ac97_clock = 48000; static char *ac97_quirk; static int dxs_support; static int dxs_init_volume = 31; static int nodelay; module_param(index, int, 0444); MODULE_PARM_DESC(index, "Index value for VIA 82xx bridge."); module_param(id, charp, 0444); MODULE_PARM_DESC(id, "ID string for VIA 82xx bridge."); module_param_hw(mpu_port, long, ioport, 0444); MODULE_PARM_DESC(mpu_port, "MPU-401 port. (VT82C686x only)"); #ifdef SUPPORT_JOYSTICK module_param(joystick, bool, 0444); MODULE_PARM_DESC(joystick, "Enable joystick. (VT82C686x only)"); #endif module_param(ac97_clock, int, 0444); MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); module_param(ac97_quirk, charp, 0444); MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); module_param(dxs_support, int, 0444); MODULE_PARM_DESC(dxs_support, "Support for DXS channels (0 = auto, 1 = enable, 2 = disable, 3 = 48k only, 4 = no VRA, 5 = enable any sample rate)"); module_param(dxs_init_volume, int, 0644); MODULE_PARM_DESC(dxs_init_volume, "initial DXS volume (0-31)"); module_param(nodelay, int, 0444); MODULE_PARM_DESC(nodelay, "Disable 500ms init delay"); /* just for backward compatibility */ static bool enable; module_param(enable, bool, 0444); /* revision numbers for via686 */ #define VIA_REV_686_A 0x10 #define VIA_REV_686_B 0x11 #define VIA_REV_686_C 0x12 #define VIA_REV_686_D 0x13 #define VIA_REV_686_E 0x14 #define VIA_REV_686_H 0x20 /* revision numbers for via8233 */ #define VIA_REV_PRE_8233 0x10 /* not in market */ #define VIA_REV_8233C 0x20 /* 2 rec, 4 pb, 1 multi-pb */ #define VIA_REV_8233 0x30 /* 2 rec, 4 pb, 1 multi-pb, spdif */ #define VIA_REV_8233A 0x40 /* 1 rec, 1 multi-pb, spdf */ #define VIA_REV_8235 0x50 /* 2 rec, 4 pb, 1 multi-pb, spdif */ #define VIA_REV_8237 0x60 #define VIA_REV_8251 0x70 /* * Direct registers */ #define VIAREG(via, x) ((via)->port + VIA_REG_##x) #define VIADEV_REG(viadev, x) ((viadev)->port + VIA_REG_##x) /* common offsets */ #define VIA_REG_OFFSET_STATUS 0x00 /* byte - channel status */ #define VIA_REG_STAT_ACTIVE 0x80 /* RO */ #define VIA8233_SHADOW_STAT_ACTIVE 0x08 /* RO */ #define VIA_REG_STAT_PAUSED 0x40 /* RO */ #define VIA_REG_STAT_TRIGGER_QUEUED 0x08 /* RO */ #define VIA_REG_STAT_STOPPED 0x04 /* RWC */ #define VIA_REG_STAT_EOL 0x02 /* RWC */ #define VIA_REG_STAT_FLAG 0x01 /* RWC */ #define VIA_REG_OFFSET_CONTROL 0x01 /* byte - channel control */ #define VIA_REG_CTRL_START 0x80 /* WO */ #define VIA_REG_CTRL_TERMINATE 0x40 /* WO */ #define VIA_REG_CTRL_AUTOSTART 0x20 #define VIA_REG_CTRL_PAUSE 0x08 /* RW */ #define VIA_REG_CTRL_INT_STOP 0x04 #define VIA_REG_CTRL_INT_EOL 0x02 #define VIA_REG_CTRL_INT_FLAG 0x01 #define VIA_REG_CTRL_RESET 0x01 /* RW - probably reset? undocumented */ #define VIA_REG_CTRL_INT (VIA_REG_CTRL_INT_FLAG | VIA_REG_CTRL_INT_EOL | VIA_REG_CTRL_AUTOSTART) #define VIA_REG_OFFSET_TYPE 0x02 /* byte - channel type (686 only) */ #define VIA_REG_TYPE_AUTOSTART 0x80 /* RW - autostart at EOL */ #define VIA_REG_TYPE_16BIT 0x20 /* RW */ #define VIA_REG_TYPE_STEREO 0x10 /* RW */ #define VIA_REG_TYPE_INT_LLINE 0x00 #define VIA_REG_TYPE_INT_LSAMPLE 0x04 #define VIA_REG_TYPE_INT_LESSONE 0x08 #define VIA_REG_TYPE_INT_MASK 0x0c #define VIA_REG_TYPE_INT_EOL 0x02 #define VIA_REG_TYPE_INT_FLAG 0x01 #define VIA_REG_OFFSET_TABLE_PTR 0x04 /* dword - channel table pointer */ #define VIA_REG_OFFSET_CURR_PTR 0x04 /* dword - channel current pointer */ #define VIA_REG_OFFSET_STOP_IDX 0x08 /* dword - stop index, channel type, sample rate */ #define VIA8233_REG_TYPE_16BIT 0x00200000 /* RW */ #define VIA8233_REG_TYPE_STEREO 0x00100000 /* RW */ #define VIA_REG_OFFSET_CURR_COUNT 0x0c /* dword - channel current count (24 bit) */ #define VIA_REG_OFFSET_CURR_INDEX 0x0f /* byte - channel current index (for via8233 only) */ #define DEFINE_VIA_REGSET(name,val) \ enum {\ VIA_REG_##name##_STATUS = (val),\ VIA_REG_##name##_CONTROL = (val) + 0x01,\ VIA_REG_##name##_TYPE = (val) + 0x02,\ VIA_REG_##name##_TABLE_PTR = (val) + 0x04,\ VIA_REG_##name##_CURR_PTR = (val) + 0x04,\ VIA_REG_##name##_STOP_IDX = (val) + 0x08,\ VIA_REG_##name##_CURR_COUNT = (val) + 0x0c,\ } /* playback block */ DEFINE_VIA_REGSET(PLAYBACK, 0x00); DEFINE_VIA_REGSET(CAPTURE, 0x10); DEFINE_VIA_REGSET(FM, 0x20); /* AC'97 */ #define VIA_REG_AC97 0x80 /* dword */ #define VIA_REG_AC97_CODEC_ID_MASK (3<<30) #define VIA_REG_AC97_CODEC_ID_SHIFT 30 #define VIA_REG_AC97_CODEC_ID_PRIMARY 0x00 #define VIA_REG_AC97_CODEC_ID_SECONDARY 0x01 #define VIA_REG_AC97_SECONDARY_VALID (1<<27) #define VIA_REG_AC97_PRIMARY_VALID (1<<25) #define VIA_REG_AC97_BUSY (1<<24) #define VIA_REG_AC97_READ (1<<23) #define VIA_REG_AC97_CMD_SHIFT 16 #define VIA_REG_AC97_CMD_MASK 0x7e #define VIA_REG_AC97_DATA_SHIFT 0 #define VIA_REG_AC97_DATA_MASK 0xffff #define VIA_REG_SGD_SHADOW 0x84 /* dword */ /* via686 */ #define VIA_REG_SGD_STAT_PB_FLAG (1<<0) #define VIA_REG_SGD_STAT_CP_FLAG (1<<1) #define VIA_REG_SGD_STAT_FM_FLAG (1<<2) #define VIA_REG_SGD_STAT_PB_EOL (1<<4) #define VIA_REG_SGD_STAT_CP_EOL (1<<5) #define VIA_REG_SGD_STAT_FM_EOL (1<<6) #define VIA_REG_SGD_STAT_PB_STOP (1<<8) #define VIA_REG_SGD_STAT_CP_STOP (1<<9) #define VIA_REG_SGD_STAT_FM_STOP (1<<10) #define VIA_REG_SGD_STAT_PB_ACTIVE (1<<12) #define VIA_REG_SGD_STAT_CP_ACTIVE (1<<13) #define VIA_REG_SGD_STAT_FM_ACTIVE (1<<14) /* via8233 */ #define VIA8233_REG_SGD_STAT_FLAG (1<<0) #define VIA8233_REG_SGD_STAT_EOL (1<<1) #define VIA8233_REG_SGD_STAT_STOP (1<<2) #define VIA8233_REG_SGD_STAT_ACTIVE (1<<3) #define VIA8233_INTR_MASK(chan) ((VIA8233_REG_SGD_STAT_FLAG|VIA8233_REG_SGD_STAT_EOL) << ((chan) * 4)) #define VIA8233_REG_SGD_CHAN_SDX 0 #define VIA8233_REG_SGD_CHAN_MULTI 4 #define VIA8233_REG_SGD_CHAN_REC 6 #define VIA8233_REG_SGD_CHAN_REC1 7 #define VIA_REG_GPI_STATUS 0x88 #define VIA_REG_GPI_INTR 0x8c /* multi-channel and capture registers for via8233 */ DEFINE_VIA_REGSET(MULTPLAY, 0x40); DEFINE_VIA_REGSET(CAPTURE_8233, 0x60); /* via8233-specific registers */ #define VIA_REG_OFS_PLAYBACK_VOLUME_L 0x02 /* byte */ #define VIA_REG_OFS_PLAYBACK_VOLUME_R 0x03 /* byte */ #define VIA_REG_OFS_MULTPLAY_FORMAT 0x02 /* byte - format and channels */ #define VIA_REG_MULTPLAY_FMT_8BIT 0x00 #define VIA_REG_MULTPLAY_FMT_16BIT 0x80 #define VIA_REG_MULTPLAY_FMT_CH_MASK 0x70 /* # channels << 4 (valid = 1,2,4,6) */ #define VIA_REG_OFS_CAPTURE_FIFO 0x02 /* byte - bit 6 = fifo enable */ #define VIA_REG_CAPTURE_FIFO_ENABLE 0x40 #define VIA_DXS_MAX_VOLUME 31 /* max. volume (attenuation) of reg 0x32/33 */ #define VIA_REG_CAPTURE_CHANNEL 0x63 /* byte - input select */ #define VIA_REG_CAPTURE_CHANNEL_MIC 0x4 #define VIA_REG_CAPTURE_CHANNEL_LINE 0 #define VIA_REG_CAPTURE_SELECT_CODEC 0x03 /* recording source codec (0 = primary) */ #define VIA_TBL_BIT_FLAG 0x40000000 #define VIA_TBL_BIT_EOL 0x80000000 /* pci space */ #define VIA_ACLINK_STAT 0x40 #define VIA_ACLINK_C11_READY 0x20 #define VIA_ACLINK_C10_READY 0x10 #define VIA_ACLINK_C01_READY 0x04 /* secondary codec ready */ #define VIA_ACLINK_LOWPOWER 0x02 /* low-power state */ #define VIA_ACLINK_C00_READY 0x01 /* primary codec ready */ #define VIA_ACLINK_CTRL 0x41 #define VIA_ACLINK_CTRL_ENABLE 0x80 /* 0: disable, 1: enable */ #define VIA_ACLINK_CTRL_RESET 0x40 /* 0: assert, 1: de-assert */ #define VIA_ACLINK_CTRL_SYNC 0x20 /* 0: release SYNC, 1: force SYNC hi */ #define VIA_ACLINK_CTRL_SDO 0x10 /* 0: release SDO, 1: force SDO hi */ #define VIA_ACLINK_CTRL_VRA 0x08 /* 0: disable VRA, 1: enable VRA */ #define VIA_ACLINK_CTRL_PCM 0x04 /* 0: disable PCM, 1: enable PCM */ #define VIA_ACLINK_CTRL_FM 0x02 /* via686 only */ #define VIA_ACLINK_CTRL_SB 0x01 /* via686 only */ #define VIA_ACLINK_CTRL_INIT (VIA_ACLINK_CTRL_ENABLE|\ VIA_ACLINK_CTRL_RESET|\ VIA_ACLINK_CTRL_PCM|\ VIA_ACLINK_CTRL_VRA) #define VIA_FUNC_ENABLE 0x42 #define VIA_FUNC_MIDI_PNP 0x80 /* FIXME: it's 0x40 in the datasheet! */ #define VIA_FUNC_MIDI_IRQMASK 0x40 /* FIXME: not documented! */ #define VIA_FUNC_RX2C_WRITE 0x20 #define VIA_FUNC_SB_FIFO_EMPTY 0x10 #define VIA_FUNC_ENABLE_GAME 0x08 #define VIA_FUNC_ENABLE_FM 0x04 #define VIA_FUNC_ENABLE_MIDI 0x02 #define VIA_FUNC_ENABLE_SB 0x01 #define VIA_PNP_CONTROL 0x43 #define VIA_FM_NMI_CTRL 0x48 #define VIA8233_VOLCHG_CTRL 0x48 #define VIA8233_SPDIF_CTRL 0x49 #define VIA8233_SPDIF_DX3 0x08 #define VIA8233_SPDIF_SLOT_MASK 0x03 #define VIA8233_SPDIF_SLOT_1011 0x00 #define VIA8233_SPDIF_SLOT_34 0x01 #define VIA8233_SPDIF_SLOT_78 0x02 #define VIA8233_SPDIF_SLOT_69 0x03 /* */ #define VIA_DXS_AUTO 0 #define VIA_DXS_ENABLE 1 #define VIA_DXS_DISABLE 2 #define VIA_DXS_48K 3 #define VIA_DXS_NO_VRA 4 #define VIA_DXS_SRC 5 /* * pcm stream */ struct snd_via_sg_table { unsigned int offset; unsigned int size; } ; #define VIA_TABLE_SIZE 255 #define VIA_MAX_BUFSIZE (1<<24) struct viadev { unsigned int reg_offset; unsigned long port; int direction; /* playback = 0, capture = 1 */ struct snd_pcm_substream *substream; int running; unsigned int tbl_entries; /* # descriptors */ struct snd_dma_buffer table; struct snd_via_sg_table *idx_table; /* for recovery from the unexpected pointer */ unsigned int lastpos; unsigned int fragsize; unsigned int bufsize; unsigned int bufsize2; int hwptr_done; /* processed frame position in the buffer */ int in_interrupt; int shadow_shift; }; enum { TYPE_CARD_VIA686 = 1, TYPE_CARD_VIA8233 }; enum { TYPE_VIA686, TYPE_VIA8233, TYPE_VIA8233A }; #define VIA_MAX_DEVS 7 /* 4 playback, 1 multi, 2 capture */ struct via_rate_lock { spinlock_t lock; int rate; int used; }; struct via82xx { int irq; unsigned long port; struct resource *mpu_res; int chip_type; unsigned char revision; unsigned char old_legacy; unsigned char old_legacy_cfg; #ifdef CONFIG_PM_SLEEP unsigned char legacy_saved; unsigned char legacy_cfg_saved; unsigned char spdif_ctrl_saved; unsigned char capture_src_saved[2]; unsigned int mpu_port_saved; #endif unsigned char playback_volume[4][2]; /* for VIA8233/C/8235; default = 0 */ unsigned char playback_volume_c[2]; /* for VIA8233/C/8235; default = 0 */ unsigned int intr_mask; /* SGD_SHADOW mask to check interrupts */ struct pci_dev *pci; struct snd_card *card; unsigned int num_devs; unsigned int playback_devno, multi_devno, capture_devno; struct viadev devs[VIA_MAX_DEVS]; struct via_rate_lock rates[2]; /* playback and capture */ unsigned int dxs_fixed: 1; /* DXS channel accepts only 48kHz */ unsigned int no_vra: 1; /* no need to set VRA on DXS channels */ unsigned int dxs_src: 1; /* use full SRC capabilities of DXS */ unsigned int spdif_on: 1; /* only spdif rates work to external DACs */ struct snd_pcm *pcms[2]; struct snd_rawmidi *rmidi; struct snd_kcontrol *dxs_controls[4]; struct snd_ac97_bus *ac97_bus; struct snd_ac97 *ac97; unsigned int ac97_clock; unsigned int ac97_secondary; /* secondary AC'97 codec is present */ spinlock_t reg_lock; struct snd_info_entry *proc_entry; #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif }; static const struct pci_device_id snd_via82xx_ids[] = { /* 0x1106, 0x3058 */ { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C686_5), TYPE_CARD_VIA686, }, /* 686A */ /* 0x1106, 0x3059 */ { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8233_5), TYPE_CARD_VIA8233, }, /* VT8233 */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_via82xx_ids); /* */ /* * allocate and initialize the descriptor buffers * periods = number of periods * fragsize = period size in bytes */ static int build_via_table(struct viadev *dev, struct snd_pcm_substream *substream, struct pci_dev *pci, unsigned int periods, unsigned int fragsize) { unsigned int i, idx, ofs, rest; struct via82xx *chip = snd_pcm_substream_chip(substream); __le32 *pgtbl; if (dev->table.area == NULL) { /* the start of each lists must be aligned to 8 bytes, * but the kernel pages are much bigger, so we don't care */ if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, PAGE_ALIGN(VIA_TABLE_SIZE * 2 * 8), &dev->table) < 0) return -ENOMEM; } if (! dev->idx_table) { dev->idx_table = kmalloc_array(VIA_TABLE_SIZE, sizeof(*dev->idx_table), GFP_KERNEL); if (! dev->idx_table) return -ENOMEM; } /* fill the entries */ idx = 0; ofs = 0; pgtbl = (__le32 *)dev->table.area; for (i = 0; i < periods; i++) { rest = fragsize; /* fill descriptors for a period. * a period can be split to several descriptors if it's * over page boundary. */ do { unsigned int r; unsigned int flag; unsigned int addr; if (idx >= VIA_TABLE_SIZE) { dev_err(&pci->dev, "too much table size!\n"); return -EINVAL; } addr = snd_pcm_sgbuf_get_addr(substream, ofs); pgtbl[idx << 1] = cpu_to_le32(addr); r = snd_pcm_sgbuf_get_chunk_size(substream, ofs, rest); rest -= r; if (! rest) { if (i == periods - 1) flag = VIA_TBL_BIT_EOL; /* buffer boundary */ else flag = VIA_TBL_BIT_FLAG; /* period boundary */ } else flag = 0; /* period continues to the next */ /* dev_dbg(&pci->dev, "tbl %d: at %d size %d (rest %d)\n", idx, ofs, r, rest); */ pgtbl[(idx<<1) + 1] = cpu_to_le32(r | flag); dev->idx_table[idx].offset = ofs; dev->idx_table[idx].size = r; ofs += r; idx++; } while (rest > 0); } dev->tbl_entries = idx; dev->bufsize = periods * fragsize; dev->bufsize2 = dev->bufsize / 2; dev->fragsize = fragsize; return 0; } static int clean_via_table(struct viadev *dev, struct snd_pcm_substream *substream, struct pci_dev *pci) { if (dev->table.area) { snd_dma_free_pages(&dev->table); dev->table.area = NULL; } kfree(dev->idx_table); dev->idx_table = NULL; return 0; } /* * Basic I/O */ static inline unsigned int snd_via82xx_codec_xread(struct via82xx *chip) { return inl(VIAREG(chip, AC97)); } static inline void snd_via82xx_codec_xwrite(struct via82xx *chip, unsigned int val) { outl(val, VIAREG(chip, AC97)); } static int snd_via82xx_codec_ready(struct via82xx *chip, int secondary) { unsigned int timeout = 1000; /* 1ms */ unsigned int val; while (timeout-- > 0) { udelay(1); val = snd_via82xx_codec_xread(chip); if (!(val & VIA_REG_AC97_BUSY)) return val & 0xffff; } dev_err(chip->card->dev, "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_via82xx_codec_xread(chip)); return -EIO; } static int snd_via82xx_codec_valid(struct via82xx *chip, int secondary) { unsigned int timeout = 1000; /* 1ms */ unsigned int val, val1; unsigned int stat = !secondary ? VIA_REG_AC97_PRIMARY_VALID : VIA_REG_AC97_SECONDARY_VALID; while (timeout-- > 0) { val = snd_via82xx_codec_xread(chip); val1 = val & (VIA_REG_AC97_BUSY | stat); if (val1 == stat) return val & 0xffff; udelay(1); } return -EIO; } static void snd_via82xx_codec_wait(struct snd_ac97 *ac97) { struct via82xx *chip = ac97->private_data; __always_unused int err; err = snd_via82xx_codec_ready(chip, ac97->num); /* here we need to wait fairly for long time.. */ if (!nodelay) msleep(500); } static void snd_via82xx_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct via82xx *chip = ac97->private_data; unsigned int xval; xval = !ac97->num ? VIA_REG_AC97_CODEC_ID_PRIMARY : VIA_REG_AC97_CODEC_ID_SECONDARY; xval <<= VIA_REG_AC97_CODEC_ID_SHIFT; xval |= reg << VIA_REG_AC97_CMD_SHIFT; xval |= val << VIA_REG_AC97_DATA_SHIFT; snd_via82xx_codec_xwrite(chip, xval); snd_via82xx_codec_ready(chip, ac97->num); } static unsigned short snd_via82xx_codec_read(struct snd_ac97 *ac97, unsigned short reg) { struct via82xx *chip = ac97->private_data; unsigned int xval, val = 0xffff; int again = 0; xval = ac97->num << VIA_REG_AC97_CODEC_ID_SHIFT; xval |= ac97->num ? VIA_REG_AC97_SECONDARY_VALID : VIA_REG_AC97_PRIMARY_VALID; xval |= VIA_REG_AC97_READ; xval |= (reg & 0x7f) << VIA_REG_AC97_CMD_SHIFT; while (1) { if (again++ > 3) { dev_err(chip->card->dev, "codec_read: codec %i is not valid [0x%x]\n", ac97->num, snd_via82xx_codec_xread(chip)); return 0xffff; } snd_via82xx_codec_xwrite(chip, xval); udelay (20); if (snd_via82xx_codec_valid(chip, ac97->num) >= 0) { udelay(25); val = snd_via82xx_codec_xread(chip); break; } } return val & 0xffff; } static void snd_via82xx_channel_reset(struct via82xx *chip, struct viadev *viadev) { outb(VIA_REG_CTRL_PAUSE | VIA_REG_CTRL_TERMINATE | VIA_REG_CTRL_RESET, VIADEV_REG(viadev, OFFSET_CONTROL)); inb(VIADEV_REG(viadev, OFFSET_CONTROL)); udelay(50); /* disable interrupts */ outb(0x00, VIADEV_REG(viadev, OFFSET_CONTROL)); /* clear interrupts */ outb(0x03, VIADEV_REG(viadev, OFFSET_STATUS)); outb(0x00, VIADEV_REG(viadev, OFFSET_TYPE)); /* for via686 */ // outl(0, VIADEV_REG(viadev, OFFSET_CURR_PTR)); viadev->lastpos = 0; viadev->hwptr_done = 0; } /* * Interrupt handler * Used for 686 and 8233A */ static irqreturn_t snd_via686_interrupt(int irq, void *dev_id) { struct via82xx *chip = dev_id; unsigned int status; unsigned int i; status = inl(VIAREG(chip, SGD_SHADOW)); if (! (status & chip->intr_mask)) { if (chip->rmidi) /* check mpu401 interrupt */ return snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); return IRQ_NONE; } /* check status for each stream */ spin_lock(&chip->reg_lock); for (i = 0; i < chip->num_devs; i++) { struct viadev *viadev = &chip->devs[i]; unsigned char c_status = inb(VIADEV_REG(viadev, OFFSET_STATUS)); if (! (c_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG|VIA_REG_STAT_STOPPED))) continue; if (viadev->substream && viadev->running) { /* * Update hwptr_done based on 'period elapsed' * interrupts. We'll use it, when the chip returns 0 * for OFFSET_CURR_COUNT. */ if (c_status & VIA_REG_STAT_EOL) viadev->hwptr_done = 0; else viadev->hwptr_done += viadev->fragsize; viadev->in_interrupt = c_status; spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(viadev->substream); spin_lock(&chip->reg_lock); viadev->in_interrupt = 0; } outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */ } spin_unlock(&chip->reg_lock); return IRQ_HANDLED; } /* * Interrupt handler */ static irqreturn_t snd_via8233_interrupt(int irq, void *dev_id) { struct via82xx *chip = dev_id; unsigned int status; unsigned int i; int irqreturn = 0; /* check status for each stream */ spin_lock(&chip->reg_lock); status = inl(VIAREG(chip, SGD_SHADOW)); for (i = 0; i < chip->num_devs; i++) { struct viadev *viadev = &chip->devs[i]; struct snd_pcm_substream *substream; unsigned char c_status, shadow_status; shadow_status = (status >> viadev->shadow_shift) & (VIA8233_SHADOW_STAT_ACTIVE|VIA_REG_STAT_EOL| VIA_REG_STAT_FLAG); c_status = shadow_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG); if (!c_status) continue; substream = viadev->substream; if (substream && viadev->running) { /* * Update hwptr_done based on 'period elapsed' * interrupts. We'll use it, when the chip returns 0 * for OFFSET_CURR_COUNT. */ if (c_status & VIA_REG_STAT_EOL) viadev->hwptr_done = 0; else viadev->hwptr_done += viadev->fragsize; viadev->in_interrupt = c_status; if (shadow_status & VIA8233_SHADOW_STAT_ACTIVE) viadev->in_interrupt |= VIA_REG_STAT_ACTIVE; spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(substream); spin_lock(&chip->reg_lock); viadev->in_interrupt = 0; } outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */ irqreturn = 1; } spin_unlock(&chip->reg_lock); return IRQ_RETVAL(irqreturn); } /* * PCM callbacks */ /* * trigger callback */ static int snd_via82xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; unsigned char val; if (chip->chip_type != TYPE_VIA686) val = VIA_REG_CTRL_INT; else val = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: val |= VIA_REG_CTRL_START; viadev->running = 1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: val = VIA_REG_CTRL_TERMINATE; viadev->running = 0; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: val |= VIA_REG_CTRL_PAUSE; viadev->running = 0; break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: viadev->running = 1; break; default: return -EINVAL; } outb(val, VIADEV_REG(viadev, OFFSET_CONTROL)); if (cmd == SNDRV_PCM_TRIGGER_STOP) snd_via82xx_channel_reset(chip, viadev); return 0; } /* * pointer callbacks */ /* * calculate the linear position at the given sg-buffer index and the rest count */ #define check_invalid_pos(viadev,pos) \ ((pos) < viadev->lastpos && ((pos) >= viadev->bufsize2 ||\ viadev->lastpos < viadev->bufsize2)) static inline unsigned int calc_linear_pos(struct via82xx *chip, struct viadev *viadev, unsigned int idx, unsigned int count) { unsigned int size, base, res; size = viadev->idx_table[idx].size; base = viadev->idx_table[idx].offset; res = base + size - count; if (res >= viadev->bufsize) res -= viadev->bufsize; /* check the validity of the calculated position */ if (size < count) { dev_dbg(chip->card->dev, "invalid via82xx_cur_ptr (size = %d, count = %d)\n", (int)size, (int)count); res = viadev->lastpos; } else { if (! count) { /* Some mobos report count = 0 on the DMA boundary, * i.e. count = size indeed. * Let's check whether this step is above the expected size. */ int delta = res - viadev->lastpos; if (delta < 0) delta += viadev->bufsize; if ((unsigned int)delta > viadev->fragsize) res = base; } if (check_invalid_pos(viadev, res)) { #ifdef POINTER_DEBUG dev_dbg(chip->card->dev, "fail: idx = %i/%i, lastpos = 0x%x, bufsize2 = 0x%x, offsize = 0x%x, size = 0x%x, count = 0x%x\n", idx, viadev->tbl_entries, viadev->lastpos, viadev->bufsize2, viadev->idx_table[idx].offset, viadev->idx_table[idx].size, count); #endif /* count register returns full size when end of buffer is reached */ res = base + size; if (check_invalid_pos(viadev, res)) { dev_dbg(chip->card->dev, "invalid via82xx_cur_ptr (2), using last valid pointer\n"); res = viadev->lastpos; } } } return res; } /* * get the current pointer on via686 */ static snd_pcm_uframes_t snd_via686_pcm_pointer(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; unsigned int idx, ptr, count, res; if (snd_BUG_ON(!viadev->tbl_entries)) return 0; if (!(inb(VIADEV_REG(viadev, OFFSET_STATUS)) & VIA_REG_STAT_ACTIVE)) return 0; spin_lock(&chip->reg_lock); count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT)) & 0xffffff; /* The via686a does not have the current index register, * so we need to calculate the index from CURR_PTR. */ ptr = inl(VIADEV_REG(viadev, OFFSET_CURR_PTR)); if (ptr <= (unsigned int)viadev->table.addr) idx = 0; else /* CURR_PTR holds the address + 8 */ idx = ((ptr - (unsigned int)viadev->table.addr) / 8 - 1) % viadev->tbl_entries; res = calc_linear_pos(chip, viadev, idx, count); viadev->lastpos = res; /* remember the last position */ spin_unlock(&chip->reg_lock); return bytes_to_frames(substream->runtime, res); } /* * get the current pointer on via823x */ static snd_pcm_uframes_t snd_via8233_pcm_pointer(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; unsigned int idx, count, res; int status; if (snd_BUG_ON(!viadev->tbl_entries)) return 0; spin_lock(&chip->reg_lock); count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT)); status = viadev->in_interrupt; if (!status) status = inb(VIADEV_REG(viadev, OFFSET_STATUS)); /* An apparent bug in the 8251 is worked around by sending a * REG_CTRL_START. */ if (chip->revision == VIA_REV_8251 && (status & VIA_REG_STAT_EOL)) snd_via82xx_pcm_trigger(substream, SNDRV_PCM_TRIGGER_START); if (!(status & VIA_REG_STAT_ACTIVE)) { res = 0; goto unlock; } if (count & 0xffffff) { idx = count >> 24; if (idx >= viadev->tbl_entries) { #ifdef POINTER_DEBUG dev_dbg(chip->card->dev, "fail: invalid idx = %i/%i\n", idx, viadev->tbl_entries); #endif res = viadev->lastpos; } else { count &= 0xffffff; res = calc_linear_pos(chip, viadev, idx, count); } } else { res = viadev->hwptr_done; if (!viadev->in_interrupt) { if (status & VIA_REG_STAT_EOL) { res = 0; } else if (status & VIA_REG_STAT_FLAG) { res += viadev->fragsize; } } } unlock: viadev->lastpos = res; spin_unlock(&chip->reg_lock); return bytes_to_frames(substream->runtime, res); } /* * hw_params callback: * allocate the buffer and build up the buffer description table */ static int snd_via82xx_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; return build_via_table(viadev, substream, chip->pci, params_periods(hw_params), params_period_bytes(hw_params)); } /* * hw_free callback: * clean up the buffer description table and release the buffer */ static int snd_via82xx_hw_free(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; clean_via_table(viadev, substream, chip->pci); return 0; } /* * set up the table pointer */ static void snd_via82xx_set_table_ptr(struct via82xx *chip, struct viadev *viadev) { snd_via82xx_codec_ready(chip, 0); outl((u32)viadev->table.addr, VIADEV_REG(viadev, OFFSET_TABLE_PTR)); udelay(20); snd_via82xx_codec_ready(chip, 0); } /* * prepare callback for playback and capture on via686 */ static void via686_setup_format(struct via82xx *chip, struct viadev *viadev, struct snd_pcm_runtime *runtime) { snd_via82xx_channel_reset(chip, viadev); /* this must be set after channel_reset */ snd_via82xx_set_table_ptr(chip, viadev); outb(VIA_REG_TYPE_AUTOSTART | (runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA_REG_TYPE_16BIT : 0) | (runtime->channels > 1 ? VIA_REG_TYPE_STEREO : 0) | ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) | VIA_REG_TYPE_INT_EOL | VIA_REG_TYPE_INT_FLAG, VIADEV_REG(viadev, OFFSET_TYPE)); } static int snd_via686_playback_prepare(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct snd_pcm_runtime *runtime = substream->runtime; snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate); snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate); via686_setup_format(chip, viadev, runtime); return 0; } static int snd_via686_capture_prepare(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct snd_pcm_runtime *runtime = substream->runtime; snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); via686_setup_format(chip, viadev, runtime); return 0; } /* * lock the current rate */ static int via_lock_rate(struct via_rate_lock *rec, int rate) { int changed = 0; spin_lock_irq(&rec->lock); if (rec->rate != rate) { if (rec->rate && rec->used > 1) /* already set */ changed = -EINVAL; else { rec->rate = rate; changed = 1; } } spin_unlock_irq(&rec->lock); return changed; } /* * prepare callback for DSX playback on via823x */ static int snd_via8233_playback_prepare(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct snd_pcm_runtime *runtime = substream->runtime; int ac97_rate = chip->dxs_src ? 48000 : runtime->rate; int rate_changed; u32 rbits; rate_changed = via_lock_rate(&chip->rates[0], ac97_rate); if (rate_changed < 0) return rate_changed; if (rate_changed) snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, chip->no_vra ? 48000 : runtime->rate); if (chip->spdif_on && viadev->reg_offset == 0x30) snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate); if (runtime->rate == 48000) rbits = 0xfffff; else rbits = (0x100000 / 48000) * runtime->rate + ((0x100000 % 48000) * runtime->rate) / 48000; snd_BUG_ON(rbits & ~0xfffff); snd_via82xx_channel_reset(chip, viadev); snd_via82xx_set_table_ptr(chip, viadev); outb(chip->playback_volume[viadev->reg_offset / 0x10][0], VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_L)); outb(chip->playback_volume[viadev->reg_offset / 0x10][1], VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_R)); outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) | /* format */ (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) | /* stereo */ rbits | /* rate */ 0xff000000, /* STOP index is never reached */ VIADEV_REG(viadev, OFFSET_STOP_IDX)); udelay(20); snd_via82xx_codec_ready(chip, 0); return 0; } /* * prepare callback for multi-channel playback on via823x */ static int snd_via8233_multi_prepare(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct snd_pcm_runtime *runtime = substream->runtime; unsigned int slots; int fmt; if (via_lock_rate(&chip->rates[0], runtime->rate) < 0) return -EINVAL; snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate); snd_ac97_set_rate(chip->ac97, AC97_PCM_SURR_DAC_RATE, runtime->rate); snd_ac97_set_rate(chip->ac97, AC97_PCM_LFE_DAC_RATE, runtime->rate); snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate); snd_via82xx_channel_reset(chip, viadev); snd_via82xx_set_table_ptr(chip, viadev); fmt = (runtime->format == SNDRV_PCM_FORMAT_S16_LE) ? VIA_REG_MULTPLAY_FMT_16BIT : VIA_REG_MULTPLAY_FMT_8BIT; fmt |= runtime->channels << 4; outb(fmt, VIADEV_REG(viadev, OFS_MULTPLAY_FORMAT)); #if 0 if (chip->revision == VIA_REV_8233A) slots = 0; else #endif { /* set sample number to slot 3, 4, 7, 8, 6, 9 (for VIA8233/C,8235) */ /* corresponding to FL, FR, RL, RR, C, LFE ?? */ switch (runtime->channels) { case 1: slots = (1<<0) | (1<<4); break; case 2: slots = (1<<0) | (2<<4); break; case 3: slots = (1<<0) | (2<<4) | (5<<8); break; case 4: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12); break; case 5: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16); break; case 6: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16) | (6<<20); break; default: slots = 0; break; } } /* STOP index is never reached */ outl(0xff000000 | slots, VIADEV_REG(viadev, OFFSET_STOP_IDX)); udelay(20); snd_via82xx_codec_ready(chip, 0); return 0; } /* * prepare callback for capture on via823x */ static int snd_via8233_capture_prepare(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct snd_pcm_runtime *runtime = substream->runtime; if (via_lock_rate(&chip->rates[1], runtime->rate) < 0) return -EINVAL; snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); snd_via82xx_channel_reset(chip, viadev); snd_via82xx_set_table_ptr(chip, viadev); outb(VIA_REG_CAPTURE_FIFO_ENABLE, VIADEV_REG(viadev, OFS_CAPTURE_FIFO)); outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) | (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) | 0xff000000, /* STOP index is never reached */ VIADEV_REG(viadev, OFFSET_STOP_IDX)); udelay(20); snd_via82xx_codec_ready(chip, 0); return 0; } /* * pcm hardware definition, identical for both playback and capture */ static const struct snd_pcm_hardware snd_via82xx_hw = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | /* SNDRV_PCM_INFO_RESUME | */ SNDRV_PCM_INFO_PAUSE), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_48000, .rate_min = 48000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = VIA_MAX_BUFSIZE, .period_bytes_min = 32, .period_bytes_max = VIA_MAX_BUFSIZE / 2, .periods_min = 2, .periods_max = VIA_TABLE_SIZE / 2, .fifo_size = 0, }; /* * open callback skeleton */ static int snd_via82xx_pcm_open(struct via82xx *chip, struct viadev *viadev, struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; int err; struct via_rate_lock *ratep; bool use_src = false; runtime->hw = snd_via82xx_hw; /* set the hw rate condition */ ratep = &chip->rates[viadev->direction]; spin_lock_irq(&ratep->lock); ratep->used++; if (chip->spdif_on && viadev->reg_offset == 0x30) { /* DXS#3 and spdif is on */ runtime->hw.rates = chip->ac97->rates[AC97_RATES_SPDIF]; snd_pcm_limit_hw_rates(runtime); } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { /* fixed DXS playback rate */ runtime->hw.rates = SNDRV_PCM_RATE_48000; runtime->hw.rate_min = runtime->hw.rate_max = 48000; } else if (chip->dxs_src && viadev->reg_offset < 0x40) { /* use full SRC capabilities of DXS */ runtime->hw.rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000); runtime->hw.rate_min = 8000; runtime->hw.rate_max = 48000; use_src = true; } else if (! ratep->rate) { int idx = viadev->direction ? AC97_RATES_ADC : AC97_RATES_FRONT_DAC; runtime->hw.rates = chip->ac97->rates[idx]; snd_pcm_limit_hw_rates(runtime); } else { /* a fixed rate */ runtime->hw.rates = SNDRV_PCM_RATE_KNOT; runtime->hw.rate_max = runtime->hw.rate_min = ratep->rate; } spin_unlock_irq(&ratep->lock); /* we may remove following constaint when we modify table entries in interrupt */ err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (err < 0) return err; if (use_src) { err = snd_pcm_hw_rule_noresample(runtime, 48000); if (err < 0) return err; } runtime->private_data = viadev; viadev->substream = substream; return 0; } /* * open callback for playback on via686 */ static int snd_via686_playback_open(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = &chip->devs[chip->playback_devno + substream->number]; int err; err = snd_via82xx_pcm_open(chip, viadev, substream); if (err < 0) return err; return 0; } /* * open callback for playback on via823x DXS */ static int snd_via8233_playback_open(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev; unsigned int stream; int err; viadev = &chip->devs[chip->playback_devno + substream->number]; err = snd_via82xx_pcm_open(chip, viadev, substream); if (err < 0) return err; stream = viadev->reg_offset / 0x10; if (chip->dxs_controls[stream]) { chip->playback_volume[stream][0] = VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31); chip->playback_volume[stream][1] = VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31); chip->dxs_controls[stream]->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &chip->dxs_controls[stream]->id); } return 0; } /* * open callback for playback on via823x multi-channel */ static int snd_via8233_multi_open(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = &chip->devs[chip->multi_devno]; int err; /* channels constraint for VIA8233A * 3 and 5 channels are not supported */ static const unsigned int channels[] = { 1, 2, 4, 6 }; static const struct snd_pcm_hw_constraint_list hw_constraints_channels = { .count = ARRAY_SIZE(channels), .list = channels, .mask = 0, }; err = snd_via82xx_pcm_open(chip, viadev, substream); if (err < 0) return err; substream->runtime->hw.channels_max = 6; if (chip->revision == VIA_REV_8233A) snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels); return 0; } /* * open callback for capture on via686 and via823x */ static int snd_via82xx_capture_open(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = &chip->devs[chip->capture_devno + substream->pcm->device]; return snd_via82xx_pcm_open(chip, viadev, substream); } /* * close callback */ static int snd_via82xx_pcm_close(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; struct via_rate_lock *ratep; /* release the rate lock */ ratep = &chip->rates[viadev->direction]; spin_lock_irq(&ratep->lock); ratep->used--; if (! ratep->used) ratep->rate = 0; spin_unlock_irq(&ratep->lock); if (! ratep->rate) { if (! viadev->direction) { snd_ac97_update_power(chip->ac97, AC97_PCM_FRONT_DAC_RATE, 0); snd_ac97_update_power(chip->ac97, AC97_PCM_SURR_DAC_RATE, 0); snd_ac97_update_power(chip->ac97, AC97_PCM_LFE_DAC_RATE, 0); } else snd_ac97_update_power(chip->ac97, AC97_PCM_LR_ADC_RATE, 0); } viadev->substream = NULL; return 0; } static int snd_via8233_playback_close(struct snd_pcm_substream *substream) { struct via82xx *chip = snd_pcm_substream_chip(substream); struct viadev *viadev = substream->runtime->private_data; unsigned int stream; stream = viadev->reg_offset / 0x10; if (chip->dxs_controls[stream]) { chip->dxs_controls[stream]->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &chip->dxs_controls[stream]->id); } return snd_via82xx_pcm_close(substream); } /* via686 playback callbacks */ static const struct snd_pcm_ops snd_via686_playback_ops = { .open = snd_via686_playback_open, .close = snd_via82xx_pcm_close, .hw_params = snd_via82xx_hw_params, .hw_free = snd_via82xx_hw_free, .prepare = snd_via686_playback_prepare, .trigger = snd_via82xx_pcm_trigger, .pointer = snd_via686_pcm_pointer, }; /* via686 capture callbacks */ static const struct snd_pcm_ops snd_via686_capture_ops = { .open = snd_via82xx_capture_open, .close = snd_via82xx_pcm_close, .hw_params = snd_via82xx_hw_params, .hw_free = snd_via82xx_hw_free, .prepare = snd_via686_capture_prepare, .trigger = snd_via82xx_pcm_trigger, .pointer = snd_via686_pcm_pointer, }; /* via823x DSX playback callbacks */ static const struct snd_pcm_ops snd_via8233_playback_ops = { .open = snd_via8233_playback_open, .close = snd_via8233_playback_close, .hw_params = snd_via82xx_hw_params, .hw_free = snd_via82xx_hw_free, .prepare = snd_via8233_playback_prepare, .trigger = snd_via82xx_pcm_trigger, .pointer = snd_via8233_pcm_pointer, }; /* via823x multi-channel playback callbacks */ static const struct snd_pcm_ops snd_via8233_multi_ops = { .open = snd_via8233_multi_open, .close = snd_via82xx_pcm_close, .hw_params = snd_via82xx_hw_params, .hw_free = snd_via82xx_hw_free, .prepare = snd_via8233_multi_prepare, .trigger = snd_via82xx_pcm_trigger, .pointer = snd_via8233_pcm_pointer, }; /* via823x capture callbacks */ static const struct snd_pcm_ops snd_via8233_capture_ops = { .open = snd_via82xx_capture_open, .close = snd_via82xx_pcm_close, .hw_params = snd_via82xx_hw_params, .hw_free = snd_via82xx_hw_free, .prepare = snd_via8233_capture_prepare, .trigger = snd_via82xx_pcm_trigger, .pointer = snd_via8233_pcm_pointer, }; static void init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset, int shadow_pos, int direction) { chip->devs[idx].reg_offset = reg_offset; chip->devs[idx].shadow_shift = shadow_pos * 4; chip->devs[idx].direction = direction; chip->devs[idx].port = chip->port + reg_offset; } /* * create pcm instances for VIA8233, 8233C and 8235 (not 8233A) */ static int snd_via8233_pcm_new(struct via82xx *chip) { struct snd_pcm *pcm; struct snd_pcm_chmap *chmap; int i, err; chip->playback_devno = 0; /* x 4 */ chip->multi_devno = 4; /* x 1 */ chip->capture_devno = 5; /* x 2 */ chip->num_devs = 7; chip->intr_mask = 0x33033333; /* FLAG|EOL for rec0-1, mc, sdx0-3 */ /* PCM #0: 4 DSX playbacks and 1 capture */ err = snd_pcm_new(chip->card, chip->card->shortname, 0, 4, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops); pcm->private_data = chip; strcpy(pcm->name, chip->card->shortname); chip->pcms[0] = pcm; /* set up playbacks */ for (i = 0; i < 4; i++) init_viadev(chip, i, 0x10 * i, i, 0); /* capture */ init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64*1024, VIA_MAX_BUFSIZE); err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_std_chmaps, 2, 0, &chmap); if (err < 0) return err; /* PCM #1: multi-channel playback and 2nd capture */ err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops); pcm->private_data = chip; strcpy(pcm->name, chip->card->shortname); chip->pcms[1] = pcm; /* set up playback */ init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0); /* set up capture */ init_viadev(chip, chip->capture_devno + 1, VIA_REG_CAPTURE_8233_STATUS + 0x10, 7, 1); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64*1024, VIA_MAX_BUFSIZE); err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_alt_chmaps, 6, 0, &chmap); if (err < 0) return err; chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; return 0; } /* * create pcm instances for VIA8233A */ static int snd_via8233a_pcm_new(struct via82xx *chip) { struct snd_pcm *pcm; struct snd_pcm_chmap *chmap; int err; chip->multi_devno = 0; chip->playback_devno = 1; chip->capture_devno = 2; chip->num_devs = 3; chip->intr_mask = 0x03033000; /* FLAG|EOL for rec0, mc, sdx3 */ /* PCM #0: multi-channel playback and capture */ err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops); pcm->private_data = chip; strcpy(pcm->name, chip->card->shortname); chip->pcms[0] = pcm; /* set up playback */ init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0); /* capture */ init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64*1024, VIA_MAX_BUFSIZE); err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_alt_chmaps, 6, 0, &chmap); if (err < 0) return err; chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; /* SPDIF supported? */ if (! ac97_can_spdif(chip->ac97)) return 0; /* PCM #1: DXS3 playback (for spdif) */ err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 0, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops); pcm->private_data = chip; strcpy(pcm->name, chip->card->shortname); chip->pcms[1] = pcm; /* set up playback */ init_viadev(chip, chip->playback_devno, 0x30, 3, 0); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64*1024, VIA_MAX_BUFSIZE); return 0; } /* * create a pcm instance for via686a/b */ static int snd_via686_pcm_new(struct via82xx *chip) { struct snd_pcm *pcm; int err; chip->playback_devno = 0; chip->capture_devno = 1; chip->num_devs = 2; chip->intr_mask = 0x77; /* FLAG | EOL for PB, CP, FM */ err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via686_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via686_capture_ops); pcm->private_data = chip; strcpy(pcm->name, chip->card->shortname); chip->pcms[0] = pcm; init_viadev(chip, 0, VIA_REG_PLAYBACK_STATUS, 0, 0); init_viadev(chip, 1, VIA_REG_CAPTURE_STATUS, 0, 1); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64*1024, VIA_MAX_BUFSIZE); return 0; } /* * Mixer part */ static int snd_via8233_capture_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { /* formerly they were "Line" and "Mic", but it looks like that they * have nothing to do with the actual physical connections... */ static const char * const texts[2] = { "Input1", "Input2" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int snd_via8233_capture_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL); ucontrol->value.enumerated.item[0] = inb(port) & VIA_REG_CAPTURE_CHANNEL_MIC ? 1 : 0; return 0; } static int snd_via8233_capture_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL); u8 val, oval; spin_lock_irq(&chip->reg_lock); oval = inb(port); val = oval & ~VIA_REG_CAPTURE_CHANNEL_MIC; if (ucontrol->value.enumerated.item[0]) val |= VIA_REG_CAPTURE_CHANNEL_MIC; if (val != oval) outb(val, port); spin_unlock_irq(&chip->reg_lock); return val != oval; } static struct snd_kcontrol_new snd_via8233_capture_source = { .name = "Input Source Select", .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_via8233_capture_source_info, .get = snd_via8233_capture_source_get, .put = snd_via8233_capture_source_put, }; #define snd_via8233_dxs3_spdif_info snd_ctl_boolean_mono_info static int snd_via8233_dxs3_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); u8 val; pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val); ucontrol->value.integer.value[0] = (val & VIA8233_SPDIF_DX3) ? 1 : 0; return 0; } static int snd_via8233_dxs3_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); u8 val, oval; pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &oval); val = oval & ~VIA8233_SPDIF_DX3; if (ucontrol->value.integer.value[0]) val |= VIA8233_SPDIF_DX3; /* save the spdif flag for rate filtering */ chip->spdif_on = ucontrol->value.integer.value[0] ? 1 : 0; if (val != oval) { pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val); return 1; } return 0; } static const struct snd_kcontrol_new snd_via8233_dxs3_spdif_control = { .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_via8233_dxs3_spdif_info, .get = snd_via8233_dxs3_spdif_get, .put = snd_via8233_dxs3_spdif_put, }; static int snd_via8233_dxs_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = VIA_DXS_MAX_VOLUME; return 0; } static int snd_via8233_dxs_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); unsigned int idx = kcontrol->id.subdevice; ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][0]; ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][1]; return 0; } static int snd_via8233_pcmdxs_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[0]; ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[1]; return 0; } static int snd_via8233_dxs_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); unsigned int idx = kcontrol->id.subdevice; unsigned long port = chip->port + 0x10 * idx; unsigned char val; int i, change = 0; for (i = 0; i < 2; i++) { val = ucontrol->value.integer.value[i]; if (val > VIA_DXS_MAX_VOLUME) val = VIA_DXS_MAX_VOLUME; val = VIA_DXS_MAX_VOLUME - val; change |= val != chip->playback_volume[idx][i]; if (change) { chip->playback_volume[idx][i] = val; outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i); } } return change; } static int snd_via8233_pcmdxs_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct via82xx *chip = snd_kcontrol_chip(kcontrol); unsigned int idx; unsigned char val; int i, change = 0; for (i = 0; i < 2; i++) { val = ucontrol->value.integer.value[i]; if (val > VIA_DXS_MAX_VOLUME) val = VIA_DXS_MAX_VOLUME; val = VIA_DXS_MAX_VOLUME - val; if (val != chip->playback_volume_c[i]) { change = 1; chip->playback_volume_c[i] = val; for (idx = 0; idx < 4; idx++) { unsigned long port = chip->port + 0x10 * idx; chip->playback_volume[idx][i] = val; outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i); } } } return change; } static const DECLARE_TLV_DB_SCALE(db_scale_dxs, -4650, 150, 1); static const struct snd_kcontrol_new snd_via8233_pcmdxs_volume_control = { .name = "PCM Playback Volume", .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .info = snd_via8233_dxs_volume_info, .get = snd_via8233_pcmdxs_volume_get, .put = snd_via8233_pcmdxs_volume_put, .tlv = { .p = db_scale_dxs } }; static const struct snd_kcontrol_new snd_via8233_dxs_volume_control = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 0, /* .subdevice set later */ .name = "PCM Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .info = snd_via8233_dxs_volume_info, .get = snd_via8233_dxs_volume_get, .put = snd_via8233_dxs_volume_put, .tlv = { .p = db_scale_dxs } }; /* */ static void snd_via82xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) { struct via82xx *chip = bus->private_data; chip->ac97_bus = NULL; } static void snd_via82xx_mixer_free_ac97(struct snd_ac97 *ac97) { struct via82xx *chip = ac97->private_data; chip->ac97 = NULL; } static const struct ac97_quirk ac97_quirks[] = { { .subvendor = 0x1106, .subdevice = 0x4161, .codec_id = 0x56494161, /* VT1612A */ .name = "Soltek SL-75DRV5", .type = AC97_TUNE_NONE }, { /* FIXME: which codec? */ .subvendor = 0x1106, .subdevice = 0x4161, .name = "ASRock K7VT2", .type = AC97_TUNE_HP_ONLY }, { .subvendor = 0x110a, .subdevice = 0x0079, .name = "Fujitsu Siemens D1289", .type = AC97_TUNE_HP_ONLY }, { .subvendor = 0x1019, .subdevice = 0x0a81, .name = "ECS K7VTA3", .type = AC97_TUNE_HP_ONLY }, { .subvendor = 0x1019, .subdevice = 0x0a85, .name = "ECS L7VMM2", .type = AC97_TUNE_HP_ONLY }, { .subvendor = 0x1019, .subdevice = 0x1841, .name = "ECS K7VTA3", .type = AC97_TUNE_HP_ONLY }, { .subvendor = 0x1849, .subdevice = 0x3059, .name = "ASRock K7VM2", .type = AC97_TUNE_HP_ONLY /* VT1616 */ }, { .subvendor = 0x14cd, .subdevice = 0x7002, .name = "Unknown", .type = AC97_TUNE_ALC_JACK }, { .subvendor = 0x1071, .subdevice = 0x8590, .name = "Mitac Mobo", .type = AC97_TUNE_ALC_JACK }, { .subvendor = 0x161f, .subdevice = 0x202b, .name = "Arima Notebook", .type = AC97_TUNE_HP_ONLY, }, { .subvendor = 0x161f, .subdevice = 0x2032, .name = "Targa Traveller 811", .type = AC97_TUNE_HP_ONLY, }, { .subvendor = 0x161f, .subdevice = 0x2032, .name = "m680x", .type = AC97_TUNE_HP_ONLY, /* http://launchpad.net/bugs/38546 */ }, { .subvendor = 0x1297, .subdevice = 0xa232, .name = "Shuttle AK32VN", .type = AC97_TUNE_HP_ONLY }, { } /* terminator */ }; static int snd_via82xx_mixer_new(struct via82xx *chip, const char *quirk_override) { struct snd_ac97_template ac97; int err; static const struct snd_ac97_bus_ops ops = { .write = snd_via82xx_codec_write, .read = snd_via82xx_codec_read, .wait = snd_via82xx_codec_wait, }; err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus); if (err < 0) return err; chip->ac97_bus->private_free = snd_via82xx_mixer_free_ac97_bus; chip->ac97_bus->clock = chip->ac97_clock; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; ac97.private_free = snd_via82xx_mixer_free_ac97; ac97.pci = chip->pci; ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); if (err < 0) return err; snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override); if (chip->chip_type != TYPE_VIA686) { /* use slot 10/11 */ snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); } return 0; } #ifdef SUPPORT_JOYSTICK #define JOYSTICK_ADDR 0x200 static int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy) { struct gameport *gp; if (!joystick) return -ENODEV; if (!devm_request_region(chip->card->dev, JOYSTICK_ADDR, 8, "VIA686 gameport")) { dev_warn(chip->card->dev, "cannot reserve joystick port %#x\n", JOYSTICK_ADDR); return -EBUSY; } chip->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(chip->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "VIA686 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); gameport_set_dev_parent(gp, &chip->pci->dev); gp->io = JOYSTICK_ADDR; /* Enable legacy joystick port */ *legacy |= VIA_FUNC_ENABLE_GAME; pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, *legacy); gameport_register_port(chip->gameport); return 0; } static void snd_via686_free_gameport(struct via82xx *chip) { if (chip->gameport) { gameport_unregister_port(chip->gameport); chip->gameport = NULL; } } #else static inline int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy) { return -ENOSYS; } static inline void snd_via686_free_gameport(struct via82xx *chip) { } #endif /* * */ static int snd_via8233_init_misc(struct via82xx *chip) { int i, err, caps; unsigned char val; caps = chip->chip_type == TYPE_VIA8233A ? 1 : 2; for (i = 0; i < caps; i++) { snd_via8233_capture_source.index = i; err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_capture_source, chip)); if (err < 0) return err; } if (ac97_can_spdif(chip->ac97)) { err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_dxs3_spdif_control, chip)); if (err < 0) return err; } if (chip->chip_type != TYPE_VIA8233A) { /* when no h/w PCM volume control is found, use DXS volume control * as the PCM vol control */ if (!snd_ctl_find_id_mixer(chip->card, "PCM Playback Volume")) { dev_info(chip->card->dev, "Using DXS as PCM Playback\n"); err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_pcmdxs_volume_control, chip)); if (err < 0) return err; } else /* Using DXS when PCM emulation is enabled is really weird */ { for (i = 0; i < 4; ++i) { struct snd_kcontrol *kctl; kctl = snd_ctl_new1( &snd_via8233_dxs_volume_control, chip); if (!kctl) return -ENOMEM; kctl->id.subdevice = i; err = snd_ctl_add(chip->card, kctl); if (err < 0) return err; chip->dxs_controls[i] = kctl; } } } /* select spdif data slot 10/11 */ pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val); val = (val & ~VIA8233_SPDIF_SLOT_MASK) | VIA8233_SPDIF_SLOT_1011; val &= ~VIA8233_SPDIF_DX3; /* SPDIF off as default */ pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val); return 0; } static int snd_via686_init_misc(struct via82xx *chip) { unsigned char legacy, legacy_cfg; int rev_h = 0; legacy = chip->old_legacy; legacy_cfg = chip->old_legacy_cfg; legacy |= VIA_FUNC_MIDI_IRQMASK; /* FIXME: correct? (disable MIDI) */ legacy &= ~VIA_FUNC_ENABLE_GAME; /* disable joystick */ if (chip->revision >= VIA_REV_686_H) { rev_h = 1; if (mpu_port >= 0x200) { /* force MIDI */ mpu_port &= 0xfffc; pci_write_config_dword(chip->pci, 0x18, mpu_port | 0x01); #ifdef CONFIG_PM_SLEEP chip->mpu_port_saved = mpu_port; #endif } else { mpu_port = pci_resource_start(chip->pci, 2); } } else { switch (mpu_port) { /* force MIDI */ case 0x300: case 0x310: case 0x320: case 0x330: legacy_cfg &= ~(3 << 2); legacy_cfg |= (mpu_port & 0x0030) >> 2; break; default: /* no, use BIOS settings */ if (legacy & VIA_FUNC_ENABLE_MIDI) mpu_port = 0x300 + ((legacy_cfg & 0x000c) << 2); break; } } if (mpu_port >= 0x200) chip->mpu_res = devm_request_region(&chip->pci->dev, mpu_port, 2, "VIA82xx MPU401"); if (chip->mpu_res) { if (rev_h) legacy |= VIA_FUNC_MIDI_PNP; /* enable PCI I/O 2 */ legacy |= VIA_FUNC_ENABLE_MIDI; } else { if (rev_h) legacy &= ~VIA_FUNC_MIDI_PNP; /* disable PCI I/O 2 */ legacy &= ~VIA_FUNC_ENABLE_MIDI; mpu_port = 0; } pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy); pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, legacy_cfg); if (chip->mpu_res) { if (snd_mpu401_uart_new(chip->card, 0, MPU401_HW_VIA686A, mpu_port, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi) < 0) { dev_warn(chip->card->dev, "unable to initialize MPU-401 at 0x%lx, skipping\n", mpu_port); legacy &= ~VIA_FUNC_ENABLE_MIDI; } else { legacy &= ~VIA_FUNC_MIDI_IRQMASK; /* enable MIDI interrupt */ } pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy); } snd_via686_create_gameport(chip, &legacy); #ifdef CONFIG_PM_SLEEP chip->legacy_saved = legacy; chip->legacy_cfg_saved = legacy_cfg; #endif return 0; } /* * proc interface */ static void snd_via82xx_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct via82xx *chip = entry->private_data; int i; snd_iprintf(buffer, "%s\n\n", chip->card->longname); for (i = 0; i < 0xa0; i += 4) { snd_iprintf(buffer, "%02x: %08x\n", i, inl(chip->port + i)); } } static void snd_via82xx_proc_init(struct via82xx *chip) { snd_card_ro_proc_new(chip->card, "via82xx", chip, snd_via82xx_proc_read); } /* * */ static int snd_via82xx_chip_init(struct via82xx *chip) { unsigned int val; unsigned long end_time; unsigned char pval; #if 0 /* broken on K7M? */ if (chip->chip_type == TYPE_VIA686) /* disable all legacy ports */ pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, 0); #endif pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval); if (! (pval & VIA_ACLINK_C00_READY)) { /* codec not ready? */ /* deassert ACLink reset, force SYNC */ pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_ENABLE | VIA_ACLINK_CTRL_RESET | VIA_ACLINK_CTRL_SYNC); udelay(100); #if 1 /* FIXME: should we do full reset here for all chip models? */ pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, 0x00); udelay(100); #else /* deassert ACLink reset, force SYNC (warm AC'97 reset) */ pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_RESET|VIA_ACLINK_CTRL_SYNC); udelay(2); #endif /* ACLink on, deassert ACLink reset, VSR, SGD data out */ /* note - FM data out has trouble with non VRA codecs !! */ pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT); udelay(100); } /* Make sure VRA is enabled, in case we didn't do a * complete codec reset, above */ pci_read_config_byte(chip->pci, VIA_ACLINK_CTRL, &pval); if ((pval & VIA_ACLINK_CTRL_INIT) != VIA_ACLINK_CTRL_INIT) { /* ACLink on, deassert ACLink reset, VSR, SGD data out */ /* note - FM data out has trouble with non VRA codecs !! */ pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT); udelay(100); } /* wait until codec ready */ end_time = jiffies + msecs_to_jiffies(750); do { pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval); if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */ break; schedule_timeout_uninterruptible(1); } while (time_before(jiffies, end_time)); val = snd_via82xx_codec_xread(chip); if (val & VIA_REG_AC97_BUSY) dev_err(chip->card->dev, "AC'97 codec is not ready [0x%x]\n", val); #if 0 /* FIXME: we don't support the second codec yet so skip the detection now.. */ snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | VIA_REG_AC97_SECONDARY_VALID | (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); end_time = jiffies + msecs_to_jiffies(750); snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | VIA_REG_AC97_SECONDARY_VALID | (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); do { val = snd_via82xx_codec_xread(chip); if (val & VIA_REG_AC97_SECONDARY_VALID) { chip->ac97_secondary = 1; goto __ac97_ok2; } schedule_timeout_uninterruptible(1); } while (time_before(jiffies, end_time)); /* This is ok, the most of motherboards have only one codec */ __ac97_ok2: #endif if (chip->chip_type == TYPE_VIA686) { /* route FM trap to IRQ, disable FM trap */ pci_write_config_byte(chip->pci, VIA_FM_NMI_CTRL, 0); /* disable all GPI interrupts */ outl(0, VIAREG(chip, GPI_INTR)); } if (chip->chip_type != TYPE_VIA686) { /* Workaround for Award BIOS bug: * DXS channels don't work properly with VRA if MC97 is disabled. */ struct pci_dev *pci; pci = pci_get_device(0x1106, 0x3068, NULL); /* MC97 */ if (pci) { unsigned char data; pci_read_config_byte(pci, 0x44, &data); pci_write_config_byte(pci, 0x44, data | 0x40); pci_dev_put(pci); } } if (chip->chip_type != TYPE_VIA8233A) { int i, idx; for (idx = 0; idx < 4; idx++) { unsigned long port = chip->port + 0x10 * idx; for (i = 0; i < 2; i++) { chip->playback_volume[idx][i]=chip->playback_volume_c[i]; outb(chip->playback_volume_c[i], port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i); } } } return 0; } #ifdef CONFIG_PM_SLEEP /* * power management */ static int snd_via82xx_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct via82xx *chip = card->private_data; int i; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); for (i = 0; i < chip->num_devs; i++) snd_via82xx_channel_reset(chip, &chip->devs[i]); snd_ac97_suspend(chip->ac97); /* save misc values */ if (chip->chip_type != TYPE_VIA686) { pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &chip->spdif_ctrl_saved); chip->capture_src_saved[0] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL); chip->capture_src_saved[1] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10); } return 0; } static int snd_via82xx_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct via82xx *chip = card->private_data; int i; snd_via82xx_chip_init(chip); if (chip->chip_type == TYPE_VIA686) { if (chip->mpu_port_saved) pci_write_config_dword(chip->pci, 0x18, chip->mpu_port_saved | 0x01); pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->legacy_saved); pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->legacy_cfg_saved); } else { pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, chip->spdif_ctrl_saved); outb(chip->capture_src_saved[0], chip->port + VIA_REG_CAPTURE_CHANNEL); outb(chip->capture_src_saved[1], chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10); } snd_ac97_resume(chip->ac97); for (i = 0; i < chip->num_devs; i++) snd_via82xx_channel_reset(chip, &chip->devs[i]); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(snd_via82xx_pm, snd_via82xx_suspend, snd_via82xx_resume); #define SND_VIA82XX_PM_OPS &snd_via82xx_pm #else #define SND_VIA82XX_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static void snd_via82xx_free(struct snd_card *card) { struct via82xx *chip = card->private_data; unsigned int i; /* disable interrupts */ for (i = 0; i < chip->num_devs; i++) snd_via82xx_channel_reset(chip, &chip->devs[i]); if (chip->chip_type == TYPE_VIA686) { snd_via686_free_gameport(chip); pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->old_legacy); pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->old_legacy_cfg); } } static int snd_via82xx_create(struct snd_card *card, struct pci_dev *pci, int chip_type, int revision, unsigned int ac97_clock) { struct via82xx *chip = card->private_data; int err; err = pcim_enable_device(pci); if (err < 0) return err; chip->chip_type = chip_type; chip->revision = revision; spin_lock_init(&chip->reg_lock); spin_lock_init(&chip->rates[0].lock); spin_lock_init(&chip->rates[1].lock); chip->card = card; chip->pci = pci; chip->irq = -1; pci_read_config_byte(pci, VIA_FUNC_ENABLE, &chip->old_legacy); pci_read_config_byte(pci, VIA_PNP_CONTROL, &chip->old_legacy_cfg); pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->old_legacy & ~(VIA_FUNC_ENABLE_SB|VIA_FUNC_ENABLE_FM)); err = pci_request_regions(pci, card->driver); if (err < 0) return err; chip->port = pci_resource_start(pci, 0); if (devm_request_irq(&pci->dev, pci->irq, chip_type == TYPE_VIA8233 ? snd_via8233_interrupt : snd_via686_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_via82xx_free; if (ac97_clock >= 8000 && ac97_clock <= 48000) chip->ac97_clock = ac97_clock; err = snd_via82xx_chip_init(chip); if (err < 0) return err; /* The 8233 ac97 controller does not implement the master bit * in the pci command register. IMHO this is a violation of the PCI spec. * We call pci_set_master here because it does not hurt. */ pci_set_master(pci); return 0; } struct via823x_info { int revision; char *name; int type; }; static const struct via823x_info via823x_cards[] = { { VIA_REV_PRE_8233, "VIA 8233-Pre", TYPE_VIA8233 }, { VIA_REV_8233C, "VIA 8233C", TYPE_VIA8233 }, { VIA_REV_8233, "VIA 8233", TYPE_VIA8233 }, { VIA_REV_8233A, "VIA 8233A", TYPE_VIA8233A }, { VIA_REV_8235, "VIA 8235", TYPE_VIA8233 }, { VIA_REV_8237, "VIA 8237", TYPE_VIA8233 }, { VIA_REV_8251, "VIA 8251", TYPE_VIA8233 }, }; /* * auto detection of DXS channel supports. */ static const struct snd_pci_quirk dxs_allowlist[] = { SND_PCI_QUIRK(0x1005, 0x4710, "Avance Logic Mobo", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1019, 0x0996, "ESC Mobo", VIA_DXS_48K), SND_PCI_QUIRK(0x1019, 0x0a81, "ECS K7VTA3 v8.0", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x1019, 0x0a85, "ECS L7VMM2", VIA_DXS_NO_VRA), SND_PCI_QUIRK_VENDOR(0x1019, "ESC K8", VIA_DXS_SRC), SND_PCI_QUIRK(0x1019, 0xaa01, "ESC K8T890-A", VIA_DXS_SRC), SND_PCI_QUIRK(0x1025, 0x0033, "Acer Inspire 1353LM", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x1025, 0x0046, "Acer Aspire 1524 WLMi", VIA_DXS_SRC), SND_PCI_QUIRK_VENDOR(0x1043, "ASUS A7/A8", VIA_DXS_NO_VRA), SND_PCI_QUIRK_VENDOR(0x1071, "Diverse Notebook", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x10cf, 0x118e, "FSC Laptop", VIA_DXS_ENABLE), SND_PCI_QUIRK_VENDOR(0x1106, "ASRock", VIA_DXS_SRC), SND_PCI_QUIRK(0x1297, 0xa231, "Shuttle AK31v2", VIA_DXS_SRC), SND_PCI_QUIRK(0x1297, 0xa232, "Shuttle", VIA_DXS_SRC), SND_PCI_QUIRK(0x1297, 0xc160, "Shuttle Sk41G", VIA_DXS_SRC), SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte GA-7VAXP", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1462, 0x3800, "MSI KT266", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1462, 0x7120, "MSI KT4V", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1462, 0x7142, "MSI K8MM-V", VIA_DXS_ENABLE), SND_PCI_QUIRK_VENDOR(0x1462, "MSI Mobo", VIA_DXS_SRC), SND_PCI_QUIRK(0x147b, 0x1401, "ABIT KD7(-RAID)", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x147b, 0x1411, "ABIT VA-20", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x147b, 0x1413, "ABIT KV8 Pro", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x147b, 0x1415, "ABIT AV8", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x14ff, 0x0403, "Twinhead mobo", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x14ff, 0x0408, "Twinhead laptop", VIA_DXS_SRC), SND_PCI_QUIRK(0x1558, 0x4701, "Clevo D470", VIA_DXS_SRC), SND_PCI_QUIRK(0x1584, 0x8120, "Diverse Laptop", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1584, 0x8123, "Targa/Uniwill", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x161f, 0x202b, "Amira Notebook", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x161f, 0x2032, "m680x machines", VIA_DXS_48K), SND_PCI_QUIRK(0x1631, 0xe004, "PB EasyNote 3174", VIA_DXS_ENABLE), SND_PCI_QUIRK(0x1695, 0x3005, "EPoX EP-8K9A", VIA_DXS_ENABLE), SND_PCI_QUIRK_VENDOR(0x1695, "EPoX mobo", VIA_DXS_SRC), SND_PCI_QUIRK_VENDOR(0x16f3, "Jetway K8", VIA_DXS_SRC), SND_PCI_QUIRK_VENDOR(0x1734, "FSC Laptop", VIA_DXS_SRC), SND_PCI_QUIRK(0x1849, 0x3059, "ASRock K7VM2", VIA_DXS_NO_VRA), SND_PCI_QUIRK_VENDOR(0x1849, "ASRock mobo", VIA_DXS_SRC), SND_PCI_QUIRK(0x1919, 0x200a, "Soltek SL-K8", VIA_DXS_NO_VRA), SND_PCI_QUIRK(0x4005, 0x4710, "MSI K7T266", VIA_DXS_SRC), { } /* terminator */ }; static int check_dxs_list(struct pci_dev *pci, int revision) { const struct snd_pci_quirk *w; w = snd_pci_quirk_lookup(pci, dxs_allowlist); if (w) { dev_dbg(&pci->dev, "DXS allow list for %s found\n", snd_pci_quirk_name(w)); return w->value; } /* for newer revision, default to DXS_SRC */ if (revision >= VIA_REV_8235) return VIA_DXS_SRC; /* * not detected, try 48k rate only to be sure. */ dev_info(&pci->dev, "Assuming DXS channels with 48k fixed sample rate.\n"); dev_info(&pci->dev, " Please try dxs_support=5 option\n"); dev_info(&pci->dev, " and report if it works on your machine.\n"); dev_info(&pci->dev, " For more details, read ALSA-Configuration.txt.\n"); return VIA_DXS_48K; }; static int __snd_via82xx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { struct snd_card *card; struct via82xx *chip; int chip_type = 0, card_type; unsigned int i; int err; err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; card_type = pci_id->driver_data; switch (card_type) { case TYPE_CARD_VIA686: strcpy(card->driver, "VIA686A"); sprintf(card->shortname, "VIA 82C686A/B rev%x", pci->revision); chip_type = TYPE_VIA686; break; case TYPE_CARD_VIA8233: chip_type = TYPE_VIA8233; sprintf(card->shortname, "VIA 823x rev%x", pci->revision); for (i = 0; i < ARRAY_SIZE(via823x_cards); i++) { if (pci->revision == via823x_cards[i].revision) { chip_type = via823x_cards[i].type; strcpy(card->shortname, via823x_cards[i].name); break; } } if (chip_type != TYPE_VIA8233A) { if (dxs_support == VIA_DXS_AUTO) dxs_support = check_dxs_list(pci, pci->revision); /* force to use VIA8233 or 8233A model according to * dxs_support module option */ if (dxs_support == VIA_DXS_DISABLE) chip_type = TYPE_VIA8233A; else chip_type = TYPE_VIA8233; } if (chip_type == TYPE_VIA8233A) strcpy(card->driver, "VIA8233A"); else if (pci->revision >= VIA_REV_8237) strcpy(card->driver, "VIA8237"); /* no slog assignment */ else strcpy(card->driver, "VIA8233"); break; default: dev_err(card->dev, "invalid card type %d\n", card_type); return -EINVAL; } err = snd_via82xx_create(card, pci, chip_type, pci->revision, ac97_clock); if (err < 0) return err; err = snd_via82xx_mixer_new(chip, ac97_quirk); if (err < 0) return err; if (chip_type == TYPE_VIA686) { err = snd_via686_pcm_new(chip); if (err < 0) return err; err = snd_via686_init_misc(chip); if (err < 0) return err; } else { if (chip_type == TYPE_VIA8233A) { err = snd_via8233a_pcm_new(chip); if (err < 0) return err; // chip->dxs_fixed = 1; /* FIXME: use 48k for DXS #3? */ } else { err = snd_via8233_pcm_new(chip); if (err < 0) return err; if (dxs_support == VIA_DXS_48K) chip->dxs_fixed = 1; else if (dxs_support == VIA_DXS_NO_VRA) chip->no_vra = 1; else if (dxs_support == VIA_DXS_SRC) { chip->no_vra = 1; chip->dxs_src = 1; } } err = snd_via8233_init_misc(chip); if (err < 0) return err; } /* disable interrupts */ for (i = 0; i < chip->num_devs; i++) snd_via82xx_channel_reset(chip, &chip->devs[i]); snprintf(card->longname, sizeof(card->longname), "%s with %s at %#lx, irq %d", card->shortname, snd_ac97_get_short_name(chip->ac97), chip->port, chip->irq); snd_via82xx_proc_init(chip); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); return 0; } static int snd_via82xx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_via82xx_probe(pci, pci_id)); } static struct pci_driver via82xx_driver = { .name = KBUILD_MODNAME, .id_table = snd_via82xx_ids, .probe = snd_via82xx_probe, .driver = { .pm = SND_VIA82XX_PM_OPS, }, }; module_pci_driver(via82xx_driver);
linux-master
sound/pci/via82xx.c
// SPDX-License-Identifier: GPL-2.0-only /* * Driver for SiS7019 Audio Accelerator * * Copyright (C) 2004-2007, David Dillow * Written by David Dillow <[email protected]> * Inspired by the Trident 4D-WaveDX/NX driver. * * All rights reserved. */ #include <linux/init.h> #include <linux/pci.h> #include <linux/time.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <sound/core.h> #include <sound/ac97_codec.h> #include <sound/initval.h> #include "sis7019.h" MODULE_AUTHOR("David Dillow <[email protected]>"); MODULE_DESCRIPTION("SiS7019"); MODULE_LICENSE("GPL"); static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ static bool enable = 1; static int codecs = 1; module_param(index, int, 0444); MODULE_PARM_DESC(index, "Index value for SiS7019 Audio Accelerator."); module_param(id, charp, 0444); MODULE_PARM_DESC(id, "ID string for SiS7019 Audio Accelerator."); module_param(enable, bool, 0444); MODULE_PARM_DESC(enable, "Enable SiS7019 Audio Accelerator."); module_param(codecs, int, 0444); MODULE_PARM_DESC(codecs, "Set bit to indicate that codec number is expected to be present (default 1)"); static const struct pci_device_id snd_sis7019_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x7019) }, { 0, } }; MODULE_DEVICE_TABLE(pci, snd_sis7019_ids); /* There are three timing modes for the voices. * * For both playback and capture, when the buffer is one or two periods long, * we use the hardware's built-in Mid-Loop Interrupt and End-Loop Interrupt * to let us know when the periods have ended. * * When performing playback with more than two periods per buffer, we set * the "Stop Sample Offset" and tell the hardware to interrupt us when we * reach it. We then update the offset and continue on until we are * interrupted for the next period. * * Capture channels do not have a SSO, so we allocate a playback channel to * use as a timer for the capture periods. We use the SSO on the playback * channel to clock out virtual periods, and adjust the virtual period length * to maintain synchronization. This algorithm came from the Trident driver. * * FIXME: It'd be nice to make use of some of the synth features in the * hardware, but a woeful lack of documentation is a significant roadblock. */ struct voice { u16 flags; #define VOICE_IN_USE 1 #define VOICE_CAPTURE 2 #define VOICE_SSO_TIMING 4 #define VOICE_SYNC_TIMING 8 u16 sync_cso; u16 period_size; u16 buffer_size; u16 sync_period_size; u16 sync_buffer_size; u32 sso; u32 vperiod; struct snd_pcm_substream *substream; struct voice *timing; void __iomem *ctrl_base; void __iomem *wave_base; void __iomem *sync_base; int num; }; /* We need four pages to store our wave parameters during a suspend. If * we're not doing power management, we still need to allocate a page * for the silence buffer. */ #ifdef CONFIG_PM_SLEEP #define SIS_SUSPEND_PAGES 4 #else #define SIS_SUSPEND_PAGES 1 #endif struct sis7019 { unsigned long ioport; void __iomem *ioaddr; int irq; int codecs_present; struct pci_dev *pci; struct snd_pcm *pcm; struct snd_card *card; struct snd_ac97 *ac97[3]; /* Protect against more than one thread hitting the AC97 * registers (in a more polite manner than pounding the hardware * semaphore) */ struct mutex ac97_mutex; /* voice_lock protects allocation/freeing of the voice descriptions */ spinlock_t voice_lock; struct voice voices[64]; struct voice capture_voice; /* Allocate pages to store the internal wave state during * suspends. When we're operating, this can be used as a silence * buffer for a timing channel. */ void *suspend_state[SIS_SUSPEND_PAGES]; int silence_users; dma_addr_t silence_dma_addr; }; /* These values are also used by the module param 'codecs' to indicate * which codecs should be present. */ #define SIS_PRIMARY_CODEC_PRESENT 0x0001 #define SIS_SECONDARY_CODEC_PRESENT 0x0002 #define SIS_TERTIARY_CODEC_PRESENT 0x0004 /* The HW offset parameters (Loop End, Stop Sample, End Sample) have a * documented range of 8-0xfff8 samples. Given that they are 0-based, * that places our period/buffer range at 9-0xfff9 samples. That makes the * max buffer size 0xfff9 samples * 2 channels * 2 bytes per sample, and * max samples / min samples gives us the max periods in a buffer. * * We'll add a constraint upon open that limits the period and buffer sample * size to values that are legal for the hardware. */ static const struct snd_pcm_hardware sis_playback_hw_info = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME), .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (0xfff9 * 4), .period_bytes_min = 9, .period_bytes_max = (0xfff9 * 4), .periods_min = 1, .periods_max = (0xfff9 / 9), }; static const struct snd_pcm_hardware sis_capture_hw_info = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME), .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (0xfff9 * 4), .period_bytes_min = 9, .period_bytes_max = (0xfff9 * 4), .periods_min = 1, .periods_max = (0xfff9 / 9), }; static void sis_update_sso(struct voice *voice, u16 period) { void __iomem *base = voice->ctrl_base; voice->sso += period; if (voice->sso >= voice->buffer_size) voice->sso -= voice->buffer_size; /* Enforce the documented hardware minimum offset */ if (voice->sso < 8) voice->sso = 8; /* The SSO is in the upper 16 bits of the register. */ writew(voice->sso & 0xffff, base + SIS_PLAY_DMA_SSO_ESO + 2); } static void sis_update_voice(struct voice *voice) { if (voice->flags & VOICE_SSO_TIMING) { sis_update_sso(voice, voice->period_size); } else if (voice->flags & VOICE_SYNC_TIMING) { int sync; /* If we've not hit the end of the virtual period, update * our records and keep going. */ if (voice->vperiod > voice->period_size) { voice->vperiod -= voice->period_size; if (voice->vperiod < voice->period_size) sis_update_sso(voice, voice->vperiod); else sis_update_sso(voice, voice->period_size); return; } /* Calculate our relative offset between the target and * the actual CSO value. Since we're operating in a loop, * if the value is more than half way around, we can * consider ourselves wrapped. */ sync = voice->sync_cso; sync -= readw(voice->sync_base + SIS_CAPTURE_DMA_FORMAT_CSO); if (sync > (voice->sync_buffer_size / 2)) sync -= voice->sync_buffer_size; /* If sync is positive, then we interrupted too early, and * we'll need to come back in a few samples and try again. * There's a minimum wait, as it takes some time for the DMA * engine to startup, etc... */ if (sync > 0) { if (sync < 16) sync = 16; sis_update_sso(voice, sync); return; } /* Ok, we interrupted right on time, or (hopefully) just * a bit late. We'll adjst our next waiting period based * on how close we got. * * We need to stay just behind the actual channel to ensure * it really is past a period when we get our interrupt -- * otherwise we'll fall into the early code above and have * a minimum wait time, which makes us quite late here, * eating into the user's time to refresh the buffer, esp. * if using small periods. * * If we're less than 9 samples behind, we're on target. * Otherwise, shorten the next vperiod by the amount we've * been delayed. */ if (sync > -9) voice->vperiod = voice->sync_period_size + 1; else voice->vperiod = voice->sync_period_size + sync + 10; if (voice->vperiod < voice->buffer_size) { sis_update_sso(voice, voice->vperiod); voice->vperiod = 0; } else sis_update_sso(voice, voice->period_size); sync = voice->sync_cso + voice->sync_period_size; if (sync >= voice->sync_buffer_size) sync -= voice->sync_buffer_size; voice->sync_cso = sync; } snd_pcm_period_elapsed(voice->substream); } static void sis_voice_irq(u32 status, struct voice *voice) { int bit; while (status) { bit = __ffs(status); status >>= bit + 1; voice += bit; sis_update_voice(voice); voice++; } } static irqreturn_t sis_interrupt(int irq, void *dev) { struct sis7019 *sis = dev; unsigned long io = sis->ioport; struct voice *voice; u32 intr, status; /* We only use the DMA interrupts, and we don't enable any other * source of interrupts. But, it is possible to see an interrupt * status that didn't actually interrupt us, so eliminate anything * we're not expecting to avoid falsely claiming an IRQ, and an * ensuing endless loop. */ intr = inl(io + SIS_GISR); intr &= SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS | SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS; if (!intr) return IRQ_NONE; do { status = inl(io + SIS_PISR_A); if (status) { sis_voice_irq(status, sis->voices); outl(status, io + SIS_PISR_A); } status = inl(io + SIS_PISR_B); if (status) { sis_voice_irq(status, &sis->voices[32]); outl(status, io + SIS_PISR_B); } status = inl(io + SIS_RISR); if (status) { voice = &sis->capture_voice; if (!voice->timing) snd_pcm_period_elapsed(voice->substream); outl(status, io + SIS_RISR); } outl(intr, io + SIS_GISR); intr = inl(io + SIS_GISR); intr &= SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS | SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS; } while (intr); return IRQ_HANDLED; } static u32 sis_rate_to_delta(unsigned int rate) { u32 delta; /* This was copied from the trident driver, but it seems its gotten * around a bit... nevertheless, it works well. * * We special case 44100 and 8000 since rounding with the equation * does not give us an accurate enough value. For 11025 and 22050 * the equation gives us the best answer. All other frequencies will * also use the equation. JDW */ if (rate == 44100) delta = 0xeb3; else if (rate == 8000) delta = 0x2ab; else if (rate == 48000) delta = 0x1000; else delta = DIV_ROUND_CLOSEST(rate << 12, 48000) & 0x0000ffff; return delta; } static void __sis_map_silence(struct sis7019 *sis) { /* Helper function: must hold sis->voice_lock on entry */ if (!sis->silence_users) sis->silence_dma_addr = dma_map_single(&sis->pci->dev, sis->suspend_state[0], 4096, DMA_TO_DEVICE); sis->silence_users++; } static void __sis_unmap_silence(struct sis7019 *sis) { /* Helper function: must hold sis->voice_lock on entry */ sis->silence_users--; if (!sis->silence_users) dma_unmap_single(&sis->pci->dev, sis->silence_dma_addr, 4096, DMA_TO_DEVICE); } static void sis_free_voice(struct sis7019 *sis, struct voice *voice) { unsigned long flags; spin_lock_irqsave(&sis->voice_lock, flags); if (voice->timing) { __sis_unmap_silence(sis); voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | VOICE_SYNC_TIMING); voice->timing = NULL; } voice->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | VOICE_SYNC_TIMING); spin_unlock_irqrestore(&sis->voice_lock, flags); } static struct voice *__sis_alloc_playback_voice(struct sis7019 *sis) { /* Must hold the voice_lock on entry */ struct voice *voice; int i; for (i = 0; i < 64; i++) { voice = &sis->voices[i]; if (voice->flags & VOICE_IN_USE) continue; voice->flags |= VOICE_IN_USE; goto found_one; } voice = NULL; found_one: return voice; } static struct voice *sis_alloc_playback_voice(struct sis7019 *sis) { struct voice *voice; unsigned long flags; spin_lock_irqsave(&sis->voice_lock, flags); voice = __sis_alloc_playback_voice(sis); spin_unlock_irqrestore(&sis->voice_lock, flags); return voice; } static int sis_alloc_timing_voice(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct sis7019 *sis = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = runtime->private_data; unsigned int period_size, buffer_size; unsigned long flags; int needed; /* If there are one or two periods per buffer, we don't need a * timing voice, as we can use the capture channel's interrupts * to clock out the periods. */ period_size = params_period_size(hw_params); buffer_size = params_buffer_size(hw_params); needed = (period_size != buffer_size && period_size != (buffer_size / 2)); if (needed && !voice->timing) { spin_lock_irqsave(&sis->voice_lock, flags); voice->timing = __sis_alloc_playback_voice(sis); if (voice->timing) __sis_map_silence(sis); spin_unlock_irqrestore(&sis->voice_lock, flags); if (!voice->timing) return -ENOMEM; voice->timing->substream = substream; } else if (!needed && voice->timing) { sis_free_voice(sis, voice); voice->timing = NULL; } return 0; } static int sis_playback_open(struct snd_pcm_substream *substream) { struct sis7019 *sis = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice; voice = sis_alloc_playback_voice(sis); if (!voice) return -EAGAIN; voice->substream = substream; runtime->private_data = voice; runtime->hw = sis_playback_hw_info; snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 9, 0xfff9); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 9, 0xfff9); snd_pcm_set_sync(substream); return 0; } static int sis_substream_close(struct snd_pcm_substream *substream) { struct sis7019 *sis = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = runtime->private_data; sis_free_voice(sis, voice); return 0; } static int sis_pcm_playback_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = runtime->private_data; void __iomem *ctrl_base = voice->ctrl_base; void __iomem *wave_base = voice->wave_base; u32 format, dma_addr, control, sso_eso, delta, reg; u16 leo; /* We rely on the PCM core to ensure that the parameters for this * substream do not change on us while we're programming the HW. */ format = 0; if (snd_pcm_format_width(runtime->format) == 8) format |= SIS_PLAY_DMA_FORMAT_8BIT; if (!snd_pcm_format_signed(runtime->format)) format |= SIS_PLAY_DMA_FORMAT_UNSIGNED; if (runtime->channels == 1) format |= SIS_PLAY_DMA_FORMAT_MONO; /* The baseline setup is for a single period per buffer, and * we add bells and whistles as needed from there. */ dma_addr = runtime->dma_addr; leo = runtime->buffer_size - 1; control = leo | SIS_PLAY_DMA_LOOP | SIS_PLAY_DMA_INTR_AT_LEO; sso_eso = leo; if (runtime->period_size == (runtime->buffer_size / 2)) { control |= SIS_PLAY_DMA_INTR_AT_MLP; } else if (runtime->period_size != runtime->buffer_size) { voice->flags |= VOICE_SSO_TIMING; voice->sso = runtime->period_size - 1; voice->period_size = runtime->period_size; voice->buffer_size = runtime->buffer_size; control &= ~SIS_PLAY_DMA_INTR_AT_LEO; control |= SIS_PLAY_DMA_INTR_AT_SSO; sso_eso |= (runtime->period_size - 1) << 16; } delta = sis_rate_to_delta(runtime->rate); /* Ok, we're ready to go, set up the channel. */ writel(format, ctrl_base + SIS_PLAY_DMA_FORMAT_CSO); writel(dma_addr, ctrl_base + SIS_PLAY_DMA_BASE); writel(control, ctrl_base + SIS_PLAY_DMA_CONTROL); writel(sso_eso, ctrl_base + SIS_PLAY_DMA_SSO_ESO); for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4) writel(0, wave_base + reg); writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL); writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION); writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE | SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE | SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE, wave_base + SIS_WAVE_CHANNEL_CONTROL); /* Force PCI writes to post. */ readl(ctrl_base); return 0; } static int sis_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct sis7019 *sis = snd_pcm_substream_chip(substream); unsigned long io = sis->ioport; struct snd_pcm_substream *s; struct voice *voice; void *chip; int starting; u32 record = 0; u32 play[2] = { 0, 0 }; /* No locks needed, as the PCM core will hold the locks on the * substreams, and the HW will only start/stop the indicated voices * without changing the state of the others. */ switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: case SNDRV_PCM_TRIGGER_RESUME: starting = 1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_SUSPEND: starting = 0; break; default: return -EINVAL; } snd_pcm_group_for_each_entry(s, substream) { /* Make sure it is for us... */ chip = snd_pcm_substream_chip(s); if (chip != sis) continue; voice = s->runtime->private_data; if (voice->flags & VOICE_CAPTURE) { record |= 1 << voice->num; voice = voice->timing; } /* voice could be NULL if this a recording stream, and it * doesn't have an external timing channel. */ if (voice) play[voice->num / 32] |= 1 << (voice->num & 0x1f); snd_pcm_trigger_done(s, substream); } if (starting) { if (record) outl(record, io + SIS_RECORD_START_REG); if (play[0]) outl(play[0], io + SIS_PLAY_START_A_REG); if (play[1]) outl(play[1], io + SIS_PLAY_START_B_REG); } else { if (record) outl(record, io + SIS_RECORD_STOP_REG); if (play[0]) outl(play[0], io + SIS_PLAY_STOP_A_REG); if (play[1]) outl(play[1], io + SIS_PLAY_STOP_B_REG); } return 0; } static snd_pcm_uframes_t sis_pcm_pointer(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = runtime->private_data; u32 cso; cso = readl(voice->ctrl_base + SIS_PLAY_DMA_FORMAT_CSO); cso &= 0xffff; return cso; } static int sis_capture_open(struct snd_pcm_substream *substream) { struct sis7019 *sis = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = &sis->capture_voice; unsigned long flags; /* FIXME: The driver only supports recording from one channel * at the moment, but it could support more. */ spin_lock_irqsave(&sis->voice_lock, flags); if (voice->flags & VOICE_IN_USE) voice = NULL; else voice->flags |= VOICE_IN_USE; spin_unlock_irqrestore(&sis->voice_lock, flags); if (!voice) return -EAGAIN; voice->substream = substream; runtime->private_data = voice; runtime->hw = sis_capture_hw_info; runtime->hw.rates = sis->ac97[0]->rates[AC97_RATES_ADC]; snd_pcm_limit_hw_rates(runtime); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 9, 0xfff9); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 9, 0xfff9); snd_pcm_set_sync(substream); return 0; } static int sis_capture_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct sis7019 *sis = snd_pcm_substream_chip(substream); int rc; rc = snd_ac97_set_rate(sis->ac97[0], AC97_PCM_LR_ADC_RATE, params_rate(hw_params)); if (rc) goto out; rc = sis_alloc_timing_voice(substream, hw_params); out: return rc; } static void sis_prepare_timing_voice(struct voice *voice, struct snd_pcm_substream *substream) { struct sis7019 *sis = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct voice *timing = voice->timing; void __iomem *play_base = timing->ctrl_base; void __iomem *wave_base = timing->wave_base; u16 buffer_size, period_size; u32 format, control, sso_eso, delta; u32 vperiod, sso, reg; /* Set our initial buffer and period as large as we can given a * single page of silence. */ buffer_size = 4096 / runtime->channels; buffer_size /= snd_pcm_format_size(runtime->format, 1); period_size = buffer_size; /* Initially, we want to interrupt just a bit behind the end of * the period we're clocking out. 12 samples seems to give a good * delay. * * We want to spread our interrupts throughout the virtual period, * so that we don't end up with two interrupts back to back at the * end -- this helps minimize the effects of any jitter. Adjust our * clocking period size so that the last period is at least a fourth * of a full period. * * This is all moot if we don't need to use virtual periods. */ vperiod = runtime->period_size + 12; if (vperiod > period_size) { u16 tail = vperiod % period_size; u16 quarter_period = period_size / 4; if (tail && tail < quarter_period) { u16 loops = vperiod / period_size; tail = quarter_period - tail; tail += loops - 1; tail /= loops; period_size -= tail; } sso = period_size - 1; } else { /* The initial period will fit inside the buffer, so we * don't need to use virtual periods -- disable them. */ period_size = runtime->period_size; sso = vperiod - 1; vperiod = 0; } /* The interrupt handler implements the timing synchronization, so * setup its state. */ timing->flags |= VOICE_SYNC_TIMING; timing->sync_base = voice->ctrl_base; timing->sync_cso = runtime->period_size; timing->sync_period_size = runtime->period_size; timing->sync_buffer_size = runtime->buffer_size; timing->period_size = period_size; timing->buffer_size = buffer_size; timing->sso = sso; timing->vperiod = vperiod; /* Using unsigned samples with the all-zero silence buffer * forces the output to the lower rail, killing playback. * So ignore unsigned vs signed -- it doesn't change the timing. */ format = 0; if (snd_pcm_format_width(runtime->format) == 8) format = SIS_CAPTURE_DMA_FORMAT_8BIT; if (runtime->channels == 1) format |= SIS_CAPTURE_DMA_FORMAT_MONO; control = timing->buffer_size - 1; control |= SIS_PLAY_DMA_LOOP | SIS_PLAY_DMA_INTR_AT_SSO; sso_eso = timing->buffer_size - 1; sso_eso |= timing->sso << 16; delta = sis_rate_to_delta(runtime->rate); /* We've done the math, now configure the channel. */ writel(format, play_base + SIS_PLAY_DMA_FORMAT_CSO); writel(sis->silence_dma_addr, play_base + SIS_PLAY_DMA_BASE); writel(control, play_base + SIS_PLAY_DMA_CONTROL); writel(sso_eso, play_base + SIS_PLAY_DMA_SSO_ESO); for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4) writel(0, wave_base + reg); writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL); writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION); writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE | SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE | SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE, wave_base + SIS_WAVE_CHANNEL_CONTROL); } static int sis_pcm_capture_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct voice *voice = runtime->private_data; void __iomem *rec_base = voice->ctrl_base; u32 format, dma_addr, control; u16 leo; /* We rely on the PCM core to ensure that the parameters for this * substream do not change on us while we're programming the HW. */ format = 0; if (snd_pcm_format_width(runtime->format) == 8) format = SIS_CAPTURE_DMA_FORMAT_8BIT; if (!snd_pcm_format_signed(runtime->format)) format |= SIS_CAPTURE_DMA_FORMAT_UNSIGNED; if (runtime->channels == 1) format |= SIS_CAPTURE_DMA_FORMAT_MONO; dma_addr = runtime->dma_addr; leo = runtime->buffer_size - 1; control = leo | SIS_CAPTURE_DMA_LOOP; /* If we've got more than two periods per buffer, then we have * use a timing voice to clock out the periods. Otherwise, we can * use the capture channel's interrupts. */ if (voice->timing) { sis_prepare_timing_voice(voice, substream); } else { control |= SIS_CAPTURE_DMA_INTR_AT_LEO; if (runtime->period_size != runtime->buffer_size) control |= SIS_CAPTURE_DMA_INTR_AT_MLP; } writel(format, rec_base + SIS_CAPTURE_DMA_FORMAT_CSO); writel(dma_addr, rec_base + SIS_CAPTURE_DMA_BASE); writel(control, rec_base + SIS_CAPTURE_DMA_CONTROL); /* Force the writes to post. */ readl(rec_base); return 0; } static const struct snd_pcm_ops sis_playback_ops = { .open = sis_playback_open, .close = sis_substream_close, .prepare = sis_pcm_playback_prepare, .trigger = sis_pcm_trigger, .pointer = sis_pcm_pointer, }; static const struct snd_pcm_ops sis_capture_ops = { .open = sis_capture_open, .close = sis_substream_close, .hw_params = sis_capture_hw_params, .prepare = sis_pcm_capture_prepare, .trigger = sis_pcm_trigger, .pointer = sis_pcm_pointer, }; static int sis_pcm_create(struct sis7019 *sis) { struct snd_pcm *pcm; int rc; /* We have 64 voices, and the driver currently records from * only one channel, though that could change in the future. */ rc = snd_pcm_new(sis->card, "SiS7019", 0, 64, 1, &pcm); if (rc) return rc; pcm->private_data = sis; strcpy(pcm->name, "SiS7019"); sis->pcm = pcm; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &sis_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &sis_capture_ops); /* Try to preallocate some memory, but it's not the end of the * world if this fails. */ snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &sis->pci->dev, 64*1024, 128*1024); return 0; } static unsigned short sis_ac97_rw(struct sis7019 *sis, int codec, u32 cmd) { unsigned long io = sis->ioport; unsigned short val = 0xffff; u16 status; u16 rdy; int count; static const u16 codec_ready[3] = { SIS_AC97_STATUS_CODEC_READY, SIS_AC97_STATUS_CODEC2_READY, SIS_AC97_STATUS_CODEC3_READY, }; rdy = codec_ready[codec]; /* Get the AC97 semaphore -- software first, so we don't spin * pounding out IO reads on the hardware semaphore... */ mutex_lock(&sis->ac97_mutex); count = 0xffff; while ((inw(io + SIS_AC97_SEMA) & SIS_AC97_SEMA_BUSY) && --count) udelay(1); if (!count) goto timeout; /* ... and wait for any outstanding commands to complete ... */ count = 0xffff; do { status = inw(io + SIS_AC97_STATUS); if ((status & rdy) && !(status & SIS_AC97_STATUS_BUSY)) break; udelay(1); } while (--count); if (!count) goto timeout_sema; /* ... before sending our command and waiting for it to finish ... */ outl(cmd, io + SIS_AC97_CMD); udelay(10); count = 0xffff; while ((inw(io + SIS_AC97_STATUS) & SIS_AC97_STATUS_BUSY) && --count) udelay(1); /* ... and reading the results (if any). */ val = inl(io + SIS_AC97_CMD) >> 16; timeout_sema: outl(SIS_AC97_SEMA_RELEASE, io + SIS_AC97_SEMA); timeout: mutex_unlock(&sis->ac97_mutex); if (!count) { dev_err(&sis->pci->dev, "ac97 codec %d timeout cmd 0x%08x\n", codec, cmd); } return val; } static void sis_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { static const u32 cmd[3] = { SIS_AC97_CMD_CODEC_WRITE, SIS_AC97_CMD_CODEC2_WRITE, SIS_AC97_CMD_CODEC3_WRITE, }; sis_ac97_rw(ac97->private_data, ac97->num, (val << 16) | (reg << 8) | cmd[ac97->num]); } static unsigned short sis_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { static const u32 cmd[3] = { SIS_AC97_CMD_CODEC_READ, SIS_AC97_CMD_CODEC2_READ, SIS_AC97_CMD_CODEC3_READ, }; return sis_ac97_rw(ac97->private_data, ac97->num, (reg << 8) | cmd[ac97->num]); } static int sis_mixer_create(struct sis7019 *sis) { struct snd_ac97_bus *bus; struct snd_ac97_template ac97; static const struct snd_ac97_bus_ops ops = { .write = sis_ac97_write, .read = sis_ac97_read, }; int rc; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = sis; rc = snd_ac97_bus(sis->card, 0, &ops, NULL, &bus); if (!rc && sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT) rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[0]); ac97.num = 1; if (!rc && (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT)) rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[1]); ac97.num = 2; if (!rc && (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT)) rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[2]); /* If we return an error here, then snd_card_free() should * free up any ac97 codecs that got created, as well as the bus. */ return rc; } static void sis_chip_free(struct snd_card *card) { struct sis7019 *sis = card->private_data; /* Reset the chip, and disable all interrputs. */ outl(SIS_GCR_SOFTWARE_RESET, sis->ioport + SIS_GCR); udelay(25); outl(0, sis->ioport + SIS_GCR); outl(0, sis->ioport + SIS_GIER); /* Now, free everything we allocated. */ if (sis->irq >= 0) free_irq(sis->irq, sis); } static int sis_chip_init(struct sis7019 *sis) { unsigned long io = sis->ioport; void __iomem *ioaddr = sis->ioaddr; unsigned long timeout; u16 status; int count; int i; /* Reset the audio controller */ outl(SIS_GCR_SOFTWARE_RESET, io + SIS_GCR); udelay(25); outl(0, io + SIS_GCR); /* Get the AC-link semaphore, and reset the codecs */ count = 0xffff; while ((inw(io + SIS_AC97_SEMA) & SIS_AC97_SEMA_BUSY) && --count) udelay(1); if (!count) return -EIO; outl(SIS_AC97_CMD_CODEC_COLD_RESET, io + SIS_AC97_CMD); udelay(250); count = 0xffff; while ((inw(io + SIS_AC97_STATUS) & SIS_AC97_STATUS_BUSY) && --count) udelay(1); /* Command complete, we can let go of the semaphore now. */ outl(SIS_AC97_SEMA_RELEASE, io + SIS_AC97_SEMA); if (!count) return -EIO; /* Now that we've finished the reset, find out what's attached. * There are some codec/board combinations that take an extremely * long time to come up. 350+ ms has been observed in the field, * so we'll give them up to 500ms. */ sis->codecs_present = 0; timeout = msecs_to_jiffies(500) + jiffies; while (time_before_eq(jiffies, timeout)) { status = inl(io + SIS_AC97_STATUS); if (status & SIS_AC97_STATUS_CODEC_READY) sis->codecs_present |= SIS_PRIMARY_CODEC_PRESENT; if (status & SIS_AC97_STATUS_CODEC2_READY) sis->codecs_present |= SIS_SECONDARY_CODEC_PRESENT; if (status & SIS_AC97_STATUS_CODEC3_READY) sis->codecs_present |= SIS_TERTIARY_CODEC_PRESENT; if (sis->codecs_present == codecs) break; msleep(1); } /* All done, check for errors. */ if (!sis->codecs_present) { dev_err(&sis->pci->dev, "could not find any codecs\n"); return -EIO; } if (sis->codecs_present != codecs) { dev_warn(&sis->pci->dev, "missing codecs, found %0x, expected %0x\n", sis->codecs_present, codecs); } /* Let the hardware know that the audio driver is alive, * and enable PCM slots on the AC-link for L/R playback (3 & 4) and * record channels. We're going to want to use Variable Rate Audio * for recording, to avoid needlessly resampling from 48kHZ. */ outl(SIS_AC97_CONF_AUDIO_ALIVE, io + SIS_AC97_CONF); outl(SIS_AC97_CONF_AUDIO_ALIVE | SIS_AC97_CONF_PCM_LR_ENABLE | SIS_AC97_CONF_PCM_CAP_MIC_ENABLE | SIS_AC97_CONF_PCM_CAP_LR_ENABLE | SIS_AC97_CONF_CODEC_VRA_ENABLE, io + SIS_AC97_CONF); /* All AC97 PCM slots should be sourced from sub-mixer 0. */ outl(0, io + SIS_AC97_PSR); /* There is only one valid DMA setup for a PCI environment. */ outl(SIS_DMA_CSR_PCI_SETTINGS, io + SIS_DMA_CSR); /* Reset the synchronization groups for all of the channels * to be asynchronous. If we start doing SPDIF or 5.1 sound, etc. * we'll need to change how we handle these. Until then, we just * assign sub-mixer 0 to all playback channels, and avoid any * attenuation on the audio. */ outl(0, io + SIS_PLAY_SYNC_GROUP_A); outl(0, io + SIS_PLAY_SYNC_GROUP_B); outl(0, io + SIS_PLAY_SYNC_GROUP_C); outl(0, io + SIS_PLAY_SYNC_GROUP_D); outl(0, io + SIS_MIXER_SYNC_GROUP); for (i = 0; i < 64; i++) { writel(i, SIS_MIXER_START_ADDR(ioaddr, i)); writel(SIS_MIXER_RIGHT_NO_ATTEN | SIS_MIXER_LEFT_NO_ATTEN | SIS_MIXER_DEST_0, SIS_MIXER_ADDR(ioaddr, i)); } /* Don't attenuate any audio set for the wave amplifier. * * FIXME: Maximum attenuation is set for the music amp, which will * need to change if we start using the synth engine. */ outl(0xffff0000, io + SIS_WEVCR); /* Ensure that the wave engine is in normal operating mode. */ outl(0, io + SIS_WECCR); /* Go ahead and enable the DMA interrupts. They won't go live * until we start a channel. */ outl(SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE | SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE, io + SIS_GIER); return 0; } #ifdef CONFIG_PM_SLEEP static int sis_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct sis7019 *sis = card->private_data; void __iomem *ioaddr = sis->ioaddr; int i; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); if (sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT) snd_ac97_suspend(sis->ac97[0]); if (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT) snd_ac97_suspend(sis->ac97[1]); if (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT) snd_ac97_suspend(sis->ac97[2]); /* snd_pcm_suspend_all() stopped all channels, so we're quiescent. */ if (sis->irq >= 0) { free_irq(sis->irq, sis); sis->irq = -1; } /* Save the internal state away */ for (i = 0; i < 4; i++) { memcpy_fromio(sis->suspend_state[i], ioaddr, 4096); ioaddr += 4096; } return 0; } static int sis_resume(struct device *dev) { struct pci_dev *pci = to_pci_dev(dev); struct snd_card *card = dev_get_drvdata(dev); struct sis7019 *sis = card->private_data; void __iomem *ioaddr = sis->ioaddr; int i; if (sis_chip_init(sis)) { dev_err(&pci->dev, "unable to re-init controller\n"); goto error; } if (request_irq(pci->irq, sis_interrupt, IRQF_SHARED, KBUILD_MODNAME, sis)) { dev_err(&pci->dev, "unable to regain IRQ %d\n", pci->irq); goto error; } /* Restore saved state, then clear out the page we use for the * silence buffer. */ for (i = 0; i < 4; i++) { memcpy_toio(ioaddr, sis->suspend_state[i], 4096); ioaddr += 4096; } memset(sis->suspend_state[0], 0, 4096); sis->irq = pci->irq; if (sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT) snd_ac97_resume(sis->ac97[0]); if (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT) snd_ac97_resume(sis->ac97[1]); if (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT) snd_ac97_resume(sis->ac97[2]); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; error: snd_card_disconnect(card); return -EIO; } static SIMPLE_DEV_PM_OPS(sis_pm, sis_suspend, sis_resume); #define SIS_PM_OPS &sis_pm #else #define SIS_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static int sis_alloc_suspend(struct sis7019 *sis) { int i; /* We need 16K to store the internal wave engine state during a * suspend, but we don't need it to be contiguous, so play nice * with the memory system. We'll also use this area for a silence * buffer. */ for (i = 0; i < SIS_SUSPEND_PAGES; i++) { sis->suspend_state[i] = devm_kmalloc(&sis->pci->dev, 4096, GFP_KERNEL); if (!sis->suspend_state[i]) return -ENOMEM; } memset(sis->suspend_state[0], 0, 4096); return 0; } static int sis_chip_create(struct snd_card *card, struct pci_dev *pci) { struct sis7019 *sis = card->private_data; struct voice *voice; int rc; int i; rc = pcim_enable_device(pci); if (rc) return rc; rc = dma_set_mask(&pci->dev, DMA_BIT_MASK(30)); if (rc < 0) { dev_err(&pci->dev, "architecture does not support 30-bit PCI busmaster DMA"); return -ENXIO; } mutex_init(&sis->ac97_mutex); spin_lock_init(&sis->voice_lock); sis->card = card; sis->pci = pci; sis->irq = -1; sis->ioport = pci_resource_start(pci, 0); rc = pci_request_regions(pci, "SiS7019"); if (rc) { dev_err(&pci->dev, "unable request regions\n"); return rc; } sis->ioaddr = devm_ioremap(&pci->dev, pci_resource_start(pci, 1), 0x4000); if (!sis->ioaddr) { dev_err(&pci->dev, "unable to remap MMIO, aborting\n"); return -EIO; } rc = sis_alloc_suspend(sis); if (rc < 0) { dev_err(&pci->dev, "unable to allocate state storage\n"); return rc; } rc = sis_chip_init(sis); if (rc) return rc; card->private_free = sis_chip_free; rc = request_irq(pci->irq, sis_interrupt, IRQF_SHARED, KBUILD_MODNAME, sis); if (rc) { dev_err(&pci->dev, "unable to allocate irq %d\n", sis->irq); return rc; } sis->irq = pci->irq; card->sync_irq = sis->irq; pci_set_master(pci); for (i = 0; i < 64; i++) { voice = &sis->voices[i]; voice->num = i; voice->ctrl_base = SIS_PLAY_DMA_ADDR(sis->ioaddr, i); voice->wave_base = SIS_WAVE_ADDR(sis->ioaddr, i); } voice = &sis->capture_voice; voice->flags = VOICE_CAPTURE; voice->num = SIS_CAPTURE_CHAN_AC97_PCM_IN; voice->ctrl_base = SIS_CAPTURE_DMA_ADDR(sis->ioaddr, voice->num); return 0; } static int __snd_sis7019_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { struct snd_card *card; struct sis7019 *sis; int rc; if (!enable) return -ENOENT; /* The user can specify which codecs should be present so that we * can wait for them to show up if they are slow to recover from * the AC97 cold reset. We default to a single codec, the primary. * * We assume that SIS_PRIMARY_*_PRESENT matches bits 0-2. */ codecs &= SIS_PRIMARY_CODEC_PRESENT | SIS_SECONDARY_CODEC_PRESENT | SIS_TERTIARY_CODEC_PRESENT; if (!codecs) codecs = SIS_PRIMARY_CODEC_PRESENT; rc = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, sizeof(*sis), &card); if (rc < 0) return rc; strcpy(card->driver, "SiS7019"); strcpy(card->shortname, "SiS7019"); rc = sis_chip_create(card, pci); if (rc) return rc; sis = card->private_data; rc = sis_mixer_create(sis); if (rc) return rc; rc = sis_pcm_create(sis); if (rc) return rc; snprintf(card->longname, sizeof(card->longname), "%s Audio Accelerator with %s at 0x%lx, irq %d", card->shortname, snd_ac97_get_short_name(sis->ac97[0]), sis->ioport, sis->irq); rc = snd_card_register(card); if (rc) return rc; pci_set_drvdata(pci, card); return 0; } static int snd_sis7019_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_sis7019_probe(pci, pci_id)); } static struct pci_driver sis7019_driver = { .name = KBUILD_MODNAME, .id_table = snd_sis7019_ids, .probe = snd_sis7019_probe, .driver = { .pm = SIS_PM_OPS, }, }; module_pci_driver(sis7019_driver);
linux-master
sound/pci/sis7019.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for ESS Solo-1 (ES1938, ES1946, ES1969) soundcard * Copyright (c) by Jaromir Koutek <[email protected]>, * Jaroslav Kysela <[email protected]>, * Thomas Sailer <[email protected]>, * Abramo Bagnara <[email protected]>, * Markus Gruber <[email protected]> * * Rewritten from sonicvibes.c source. * * TODO: * Rewrite better spinlocks */ /* NOTES: - Capture data is written unaligned starting from dma_base + 1 so I need to disable mmap and to add a copy callback. - After several cycle of the following: while : ; do arecord -d1 -f cd -t raw | aplay -f cd ; done a "playback write error (DMA or IRQ trouble?)" may happen. This is due to playback interrupts not generated. I suspect a timing issue. - Sometimes the interrupt handler is invoked wrongly during playback. This generates some harmless "Unexpected hw_pointer: wrong interrupt acknowledge". I've seen that using small period sizes. Reproducible with: mpg123 test.mp3 & hdparm -t -T /dev/hda */ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <sound/core.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/opl3.h> #include <sound/mpu401.h> #include <sound/initval.h> #include <sound/tlv.h> MODULE_AUTHOR("Jaromir Koutek <[email protected]>"); MODULE_DESCRIPTION("ESS Solo-1"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for ESS Solo-1 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for ESS Solo-1 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable ESS Solo-1 soundcard."); #define SLIO_REG(chip, x) ((chip)->io_port + ESSIO_REG_##x) #define SLDM_REG(chip, x) ((chip)->ddma_port + ESSDM_REG_##x) #define SLSB_REG(chip, x) ((chip)->sb_port + ESSSB_REG_##x) #define SL_PCI_LEGACYCONTROL 0x40 #define SL_PCI_CONFIG 0x50 #define SL_PCI_DDMACONTROL 0x60 #define ESSIO_REG_AUDIO2DMAADDR 0 #define ESSIO_REG_AUDIO2DMACOUNT 4 #define ESSIO_REG_AUDIO2MODE 6 #define ESSIO_REG_IRQCONTROL 7 #define ESSDM_REG_DMAADDR 0x00 #define ESSDM_REG_DMACOUNT 0x04 #define ESSDM_REG_DMACOMMAND 0x08 #define ESSDM_REG_DMASTATUS 0x08 #define ESSDM_REG_DMAMODE 0x0b #define ESSDM_REG_DMACLEAR 0x0d #define ESSDM_REG_DMAMASK 0x0f #define ESSSB_REG_FMLOWADDR 0x00 #define ESSSB_REG_FMHIGHADDR 0x02 #define ESSSB_REG_MIXERADDR 0x04 #define ESSSB_REG_MIXERDATA 0x05 #define ESSSB_IREG_AUDIO1 0x14 #define ESSSB_IREG_MICMIX 0x1a #define ESSSB_IREG_RECSRC 0x1c #define ESSSB_IREG_MASTER 0x32 #define ESSSB_IREG_FM 0x36 #define ESSSB_IREG_AUXACD 0x38 #define ESSSB_IREG_AUXB 0x3a #define ESSSB_IREG_PCSPEAKER 0x3c #define ESSSB_IREG_LINE 0x3e #define ESSSB_IREG_SPATCONTROL 0x50 #define ESSSB_IREG_SPATLEVEL 0x52 #define ESSSB_IREG_MASTER_LEFT 0x60 #define ESSSB_IREG_MASTER_RIGHT 0x62 #define ESSSB_IREG_MPU401CONTROL 0x64 #define ESSSB_IREG_MICMIXRECORD 0x68 #define ESSSB_IREG_AUDIO2RECORD 0x69 #define ESSSB_IREG_AUXACDRECORD 0x6a #define ESSSB_IREG_FMRECORD 0x6b #define ESSSB_IREG_AUXBRECORD 0x6c #define ESSSB_IREG_MONO 0x6d #define ESSSB_IREG_LINERECORD 0x6e #define ESSSB_IREG_MONORECORD 0x6f #define ESSSB_IREG_AUDIO2SAMPLE 0x70 #define ESSSB_IREG_AUDIO2MODE 0x71 #define ESSSB_IREG_AUDIO2FILTER 0x72 #define ESSSB_IREG_AUDIO2TCOUNTL 0x74 #define ESSSB_IREG_AUDIO2TCOUNTH 0x76 #define ESSSB_IREG_AUDIO2CONTROL1 0x78 #define ESSSB_IREG_AUDIO2CONTROL2 0x7a #define ESSSB_IREG_AUDIO2 0x7c #define ESSSB_REG_RESET 0x06 #define ESSSB_REG_READDATA 0x0a #define ESSSB_REG_WRITEDATA 0x0c #define ESSSB_REG_READSTATUS 0x0c #define ESSSB_REG_STATUS 0x0e #define ESS_CMD_EXTSAMPLERATE 0xa1 #define ESS_CMD_FILTERDIV 0xa2 #define ESS_CMD_DMACNTRELOADL 0xa4 #define ESS_CMD_DMACNTRELOADH 0xa5 #define ESS_CMD_ANALOGCONTROL 0xa8 #define ESS_CMD_IRQCONTROL 0xb1 #define ESS_CMD_DRQCONTROL 0xb2 #define ESS_CMD_RECLEVEL 0xb4 #define ESS_CMD_SETFORMAT 0xb6 #define ESS_CMD_SETFORMAT2 0xb7 #define ESS_CMD_DMACONTROL 0xb8 #define ESS_CMD_DMATYPE 0xb9 #define ESS_CMD_OFFSETLEFT 0xba #define ESS_CMD_OFFSETRIGHT 0xbb #define ESS_CMD_READREG 0xc0 #define ESS_CMD_ENABLEEXT 0xc6 #define ESS_CMD_PAUSEDMA 0xd0 #define ESS_CMD_ENABLEAUDIO1 0xd1 #define ESS_CMD_STOPAUDIO1 0xd3 #define ESS_CMD_AUDIO1STATUS 0xd8 #define ESS_CMD_CONTDMA 0xd4 #define ESS_CMD_TESTIRQ 0xf2 #define ESS_RECSRC_MIC 0 #define ESS_RECSRC_AUXACD 2 #define ESS_RECSRC_AUXB 5 #define ESS_RECSRC_LINE 6 #define ESS_RECSRC_NONE 7 #define DAC1 0x01 #define ADC1 0x02 #define DAC2 0x04 /* */ #define SAVED_REG_SIZE 32 /* max. number of registers to save */ struct es1938 { int irq; unsigned long io_port; unsigned long sb_port; unsigned long vc_port; unsigned long mpu_port; unsigned long game_port; unsigned long ddma_port; unsigned char irqmask; unsigned char revision; struct snd_kcontrol *hw_volume; struct snd_kcontrol *hw_switch; struct snd_kcontrol *master_volume; struct snd_kcontrol *master_switch; struct pci_dev *pci; struct snd_card *card; struct snd_pcm *pcm; struct snd_pcm_substream *capture_substream; struct snd_pcm_substream *playback1_substream; struct snd_pcm_substream *playback2_substream; struct snd_rawmidi *rmidi; unsigned int dma1_size; unsigned int dma2_size; unsigned int dma1_start; unsigned int dma2_start; unsigned int dma1_shift; unsigned int dma2_shift; unsigned int last_capture_dmaaddr; unsigned int active; spinlock_t reg_lock; spinlock_t mixer_lock; struct snd_info_entry *proc_entry; #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif #ifdef CONFIG_PM_SLEEP unsigned char saved_regs[SAVED_REG_SIZE]; #endif }; static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id); static const struct pci_device_id snd_es1938_ids[] = { { PCI_VDEVICE(ESS, 0x1969), 0, }, /* Solo-1 */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_es1938_ids); #define RESET_LOOP_TIMEOUT 0x10000 #define WRITE_LOOP_TIMEOUT 0x10000 #define GET_LOOP_TIMEOUT 0x01000 /* ----------------------------------------------------------------- * Write to a mixer register * -----------------------------------------------------------------*/ static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val) { unsigned long flags; spin_lock_irqsave(&chip->mixer_lock, flags); outb(reg, SLSB_REG(chip, MIXERADDR)); outb(val, SLSB_REG(chip, MIXERDATA)); spin_unlock_irqrestore(&chip->mixer_lock, flags); dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val); } /* ----------------------------------------------------------------- * Read from a mixer register * -----------------------------------------------------------------*/ static int snd_es1938_mixer_read(struct es1938 *chip, unsigned char reg) { int data; unsigned long flags; spin_lock_irqsave(&chip->mixer_lock, flags); outb(reg, SLSB_REG(chip, MIXERADDR)); data = inb(SLSB_REG(chip, MIXERDATA)); spin_unlock_irqrestore(&chip->mixer_lock, flags); dev_dbg(chip->card->dev, "Mixer reg %02x now is %02x\n", reg, data); return data; } /* ----------------------------------------------------------------- * Write to some bits of a mixer register (return old value) * -----------------------------------------------------------------*/ static int snd_es1938_mixer_bits(struct es1938 *chip, unsigned char reg, unsigned char mask, unsigned char val) { unsigned long flags; unsigned char old, new, oval; spin_lock_irqsave(&chip->mixer_lock, flags); outb(reg, SLSB_REG(chip, MIXERADDR)); old = inb(SLSB_REG(chip, MIXERDATA)); oval = old & mask; if (val != oval) { new = (old & ~mask) | (val & mask); outb(new, SLSB_REG(chip, MIXERDATA)); dev_dbg(chip->card->dev, "Mixer reg %02x was %02x, set to %02x\n", reg, old, new); } spin_unlock_irqrestore(&chip->mixer_lock, flags); return oval; } /* ----------------------------------------------------------------- * Write command to Controller Registers * -----------------------------------------------------------------*/ static void snd_es1938_write_cmd(struct es1938 *chip, unsigned char cmd) { int i; unsigned char v; for (i = 0; i < WRITE_LOOP_TIMEOUT; i++) { v = inb(SLSB_REG(chip, READSTATUS)); if (!(v & 0x80)) { outb(cmd, SLSB_REG(chip, WRITEDATA)); return; } } dev_err(chip->card->dev, "snd_es1938_write_cmd timeout (0x02%x/0x02%x)\n", cmd, v); } /* ----------------------------------------------------------------- * Read the Read Data Buffer * -----------------------------------------------------------------*/ static int snd_es1938_get_byte(struct es1938 *chip) { int i; unsigned char v; for (i = GET_LOOP_TIMEOUT; i; i--) { v = inb(SLSB_REG(chip, STATUS)); if (v & 0x80) return inb(SLSB_REG(chip, READDATA)); } dev_err(chip->card->dev, "get_byte timeout: status 0x02%x\n", v); return -ENODEV; } /* ----------------------------------------------------------------- * Write value cmd register * -----------------------------------------------------------------*/ static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); snd_es1938_write_cmd(chip, reg); snd_es1938_write_cmd(chip, val); spin_unlock_irqrestore(&chip->reg_lock, flags); dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val); } /* ----------------------------------------------------------------- * Read data from cmd register and return it * -----------------------------------------------------------------*/ static unsigned char snd_es1938_read(struct es1938 *chip, unsigned char reg) { unsigned char val; unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); snd_es1938_write_cmd(chip, ESS_CMD_READREG); snd_es1938_write_cmd(chip, reg); val = snd_es1938_get_byte(chip); spin_unlock_irqrestore(&chip->reg_lock, flags); dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val); return val; } /* ----------------------------------------------------------------- * Write data to cmd register and return old value * -----------------------------------------------------------------*/ static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask, unsigned char val) { unsigned long flags; unsigned char old, new, oval; spin_lock_irqsave(&chip->reg_lock, flags); snd_es1938_write_cmd(chip, ESS_CMD_READREG); snd_es1938_write_cmd(chip, reg); old = snd_es1938_get_byte(chip); oval = old & mask; if (val != oval) { snd_es1938_write_cmd(chip, reg); new = (old & ~mask) | (val & mask); snd_es1938_write_cmd(chip, new); dev_dbg(chip->card->dev, "Reg %02x was %02x, set to %02x\n", reg, old, new); } spin_unlock_irqrestore(&chip->reg_lock, flags); return oval; } /* -------------------------------------------------------------------- * Reset the chip * --------------------------------------------------------------------*/ static void snd_es1938_reset(struct es1938 *chip) { int i; outb(3, SLSB_REG(chip, RESET)); inb(SLSB_REG(chip, RESET)); outb(0, SLSB_REG(chip, RESET)); for (i = 0; i < RESET_LOOP_TIMEOUT; i++) { if (inb(SLSB_REG(chip, STATUS)) & 0x80) { if (inb(SLSB_REG(chip, READDATA)) == 0xaa) goto __next; } } dev_err(chip->card->dev, "ESS Solo-1 reset failed\n"); __next: snd_es1938_write_cmd(chip, ESS_CMD_ENABLEEXT); /* Demand transfer DMA: 4 bytes per DMA request */ snd_es1938_write(chip, ESS_CMD_DMATYPE, 2); /* Change behaviour of register A1 4x oversampling 2nd channel DAC asynchronous */ snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2MODE, 0x32); /* enable/select DMA channel and IRQ channel */ snd_es1938_bits(chip, ESS_CMD_IRQCONTROL, 0xf0, 0x50); snd_es1938_bits(chip, ESS_CMD_DRQCONTROL, 0xf0, 0x50); snd_es1938_write_cmd(chip, ESS_CMD_ENABLEAUDIO1); /* Set spatializer parameters to recommended values */ snd_es1938_mixer_write(chip, 0x54, 0x8f); snd_es1938_mixer_write(chip, 0x56, 0x95); snd_es1938_mixer_write(chip, 0x58, 0x94); snd_es1938_mixer_write(chip, 0x5a, 0x80); } /* -------------------------------------------------------------------- * Reset the FIFOs * --------------------------------------------------------------------*/ static void snd_es1938_reset_fifo(struct es1938 *chip) { outb(2, SLSB_REG(chip, RESET)); outb(0, SLSB_REG(chip, RESET)); } static const struct snd_ratnum clocks[2] = { { .num = 793800, .den_min = 1, .den_max = 128, .den_step = 1, }, { .num = 768000, .den_min = 1, .den_max = 128, .den_step = 1, } }; static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clocks = { .nrats = 2, .rats = clocks, }; static void snd_es1938_rate_set(struct es1938 *chip, struct snd_pcm_substream *substream, int mode) { unsigned int bits, div0; struct snd_pcm_runtime *runtime = substream->runtime; if (runtime->rate_num == clocks[0].num) bits = 128 - runtime->rate_den; else bits = 256 - runtime->rate_den; /* set filter register */ div0 = 256 - 7160000*20/(8*82*runtime->rate); if (mode == DAC2) { snd_es1938_mixer_write(chip, 0x70, bits); snd_es1938_mixer_write(chip, 0x72, div0); } else { snd_es1938_write(chip, 0xA1, bits); snd_es1938_write(chip, 0xA2, div0); } } /* -------------------------------------------------------------------- * Configure Solo1 builtin DMA Controller * --------------------------------------------------------------------*/ static void snd_es1938_playback1_setdma(struct es1938 *chip) { outb(0x00, SLIO_REG(chip, AUDIO2MODE)); outl(chip->dma2_start, SLIO_REG(chip, AUDIO2DMAADDR)); outw(0, SLIO_REG(chip, AUDIO2DMACOUNT)); outw(chip->dma2_size, SLIO_REG(chip, AUDIO2DMACOUNT)); } static void snd_es1938_playback2_setdma(struct es1938 *chip) { /* Enable DMA controller */ outb(0xc4, SLDM_REG(chip, DMACOMMAND)); /* 1. Master reset */ outb(0, SLDM_REG(chip, DMACLEAR)); /* 2. Mask DMA */ outb(1, SLDM_REG(chip, DMAMASK)); outb(0x18, SLDM_REG(chip, DMAMODE)); outl(chip->dma1_start, SLDM_REG(chip, DMAADDR)); outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT)); /* 3. Unmask DMA */ outb(0, SLDM_REG(chip, DMAMASK)); } static void snd_es1938_capture_setdma(struct es1938 *chip) { /* Enable DMA controller */ outb(0xc4, SLDM_REG(chip, DMACOMMAND)); /* 1. Master reset */ outb(0, SLDM_REG(chip, DMACLEAR)); /* 2. Mask DMA */ outb(1, SLDM_REG(chip, DMAMASK)); outb(0x14, SLDM_REG(chip, DMAMODE)); outl(chip->dma1_start, SLDM_REG(chip, DMAADDR)); chip->last_capture_dmaaddr = chip->dma1_start; outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT)); /* 3. Unmask DMA */ outb(0, SLDM_REG(chip, DMAMASK)); } /* ---------------------------------------------------------------------- * * *** PCM part *** */ static int snd_es1938_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct es1938 *chip = snd_pcm_substream_chip(substream); int val; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: val = 0x0f; chip->active |= ADC1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: val = 0x00; chip->active &= ~ADC1; break; default: return -EINVAL; } snd_es1938_write(chip, ESS_CMD_DMACONTROL, val); return 0; } static int snd_es1938_playback1_trigger(struct snd_pcm_substream *substream, int cmd) { struct es1938 *chip = snd_pcm_substream_chip(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: /* According to the documentation this should be: 0x13 but that value may randomly swap stereo channels */ snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x92); udelay(10); snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x93); /* This two stage init gives the FIFO -> DAC connection time to * settle before first data from DMA flows in. This should ensure * no swapping of stereo channels. Report a bug if otherwise :-) */ outb(0x0a, SLIO_REG(chip, AUDIO2MODE)); chip->active |= DAC2; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: outb(0, SLIO_REG(chip, AUDIO2MODE)); snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0); chip->active &= ~DAC2; break; default: return -EINVAL; } return 0; } static int snd_es1938_playback2_trigger(struct snd_pcm_substream *substream, int cmd) { struct es1938 *chip = snd_pcm_substream_chip(substream); int val; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: val = 5; chip->active |= DAC1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: val = 0; chip->active &= ~DAC1; break; default: return -EINVAL; } snd_es1938_write(chip, ESS_CMD_DMACONTROL, val); return 0; } static int snd_es1938_playback_trigger(struct snd_pcm_substream *substream, int cmd) { switch (substream->number) { case 0: return snd_es1938_playback1_trigger(substream, cmd); case 1: return snd_es1938_playback2_trigger(substream, cmd); } snd_BUG(); return -EINVAL; } /* -------------------------------------------------------------------- * First channel for Extended Mode Audio 1 ADC Operation * --------------------------------------------------------------------*/ static int snd_es1938_capture_prepare(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int u, is8, mono; unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); chip->dma1_size = size; chip->dma1_start = runtime->dma_addr; mono = (runtime->channels > 1) ? 0 : 1; is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1; u = snd_pcm_format_unsigned(runtime->format); chip->dma1_shift = 2 - mono - is8; snd_es1938_reset_fifo(chip); /* program type */ snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1)); /* set clock and counters */ snd_es1938_rate_set(chip, substream, ADC1); count = 0x10000 - count; snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff); snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8); /* initialize and configure ADC */ snd_es1938_write(chip, ESS_CMD_SETFORMAT2, u ? 0x51 : 0x71); snd_es1938_write(chip, ESS_CMD_SETFORMAT2, 0x90 | (u ? 0x00 : 0x20) | (is8 ? 0x00 : 0x04) | (mono ? 0x40 : 0x08)); // snd_es1938_reset_fifo(chip); /* 11. configure system interrupt controller and DMA controller */ snd_es1938_capture_setdma(chip); return 0; } /* ------------------------------------------------------------------------------ * Second Audio channel DAC Operation * ------------------------------------------------------------------------------*/ static int snd_es1938_playback1_prepare(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int u, is8, mono; unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); chip->dma2_size = size; chip->dma2_start = runtime->dma_addr; mono = (runtime->channels > 1) ? 0 : 1; is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1; u = snd_pcm_format_unsigned(runtime->format); chip->dma2_shift = 2 - mono - is8; snd_es1938_reset_fifo(chip); /* set clock and counters */ snd_es1938_rate_set(chip, substream, DAC2); count >>= 1; count = 0x10000 - count; snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTL, count & 0xff); snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTH, count >> 8); /* initialize and configure Audio 2 DAC */ snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x40 | (u ? 0 : 4) | (mono ? 0 : 2) | (is8 ? 0 : 1)); /* program DMA */ snd_es1938_playback1_setdma(chip); return 0; } static int snd_es1938_playback2_prepare(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int u, is8, mono; unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); chip->dma1_size = size; chip->dma1_start = runtime->dma_addr; mono = (runtime->channels > 1) ? 0 : 1; is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1; u = snd_pcm_format_unsigned(runtime->format); chip->dma1_shift = 2 - mono - is8; count = 0x10000 - count; /* reset */ snd_es1938_reset_fifo(chip); snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1)); /* set clock and counters */ snd_es1938_rate_set(chip, substream, DAC1); snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff); snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8); /* initialized and configure DAC */ snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x80 : 0x00); snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x51 : 0x71); snd_es1938_write(chip, ESS_CMD_SETFORMAT2, 0x90 | (mono ? 0x40 : 0x08) | (is8 ? 0x00 : 0x04) | (u ? 0x00 : 0x20)); /* program DMA */ snd_es1938_playback2_setdma(chip); return 0; } static int snd_es1938_playback_prepare(struct snd_pcm_substream *substream) { switch (substream->number) { case 0: return snd_es1938_playback1_prepare(substream); case 1: return snd_es1938_playback2_prepare(substream); } snd_BUG(); return -EINVAL; } /* during the incrementing of dma counters the DMA register reads sometimes returns garbage. To ensure a valid hw pointer, the following checks which should be very unlikely to fail are used: - is the current DMA address in the valid DMA range ? - is the sum of DMA address and DMA counter pointing to the last DMA byte ? One can argue this could differ by one byte depending on which register is updated first, so the implementation below allows for that. */ static snd_pcm_uframes_t snd_es1938_capture_pointer(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); size_t ptr; #if 0 size_t old, new; /* This stuff is *needed*, don't ask why - AB */ old = inw(SLDM_REG(chip, DMACOUNT)); while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old) old = new; ptr = chip->dma1_size - 1 - new; #else size_t count; unsigned int diff; ptr = inl(SLDM_REG(chip, DMAADDR)); count = inw(SLDM_REG(chip, DMACOUNT)); diff = chip->dma1_start + chip->dma1_size - ptr - count; if (diff > 3 || ptr < chip->dma1_start || ptr >= chip->dma1_start+chip->dma1_size) ptr = chip->last_capture_dmaaddr; /* bad, use last saved */ else chip->last_capture_dmaaddr = ptr; /* good, remember it */ ptr -= chip->dma1_start; #endif return ptr >> chip->dma1_shift; } static snd_pcm_uframes_t snd_es1938_playback1_pointer(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); size_t ptr; #if 1 ptr = chip->dma2_size - inw(SLIO_REG(chip, AUDIO2DMACOUNT)); #else ptr = inl(SLIO_REG(chip, AUDIO2DMAADDR)) - chip->dma2_start; #endif return ptr >> chip->dma2_shift; } static snd_pcm_uframes_t snd_es1938_playback2_pointer(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); size_t ptr; size_t old, new; #if 1 /* This stuff is *needed*, don't ask why - AB */ old = inw(SLDM_REG(chip, DMACOUNT)); while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old) old = new; ptr = chip->dma1_size - 1 - new; #else ptr = inl(SLDM_REG(chip, DMAADDR)) - chip->dma1_start; #endif return ptr >> chip->dma1_shift; } static snd_pcm_uframes_t snd_es1938_playback_pointer(struct snd_pcm_substream *substream) { switch (substream->number) { case 0: return snd_es1938_playback1_pointer(substream); case 1: return snd_es1938_playback2_pointer(substream); } snd_BUG(); return -EINVAL; } static int snd_es1938_capture_copy(struct snd_pcm_substream *substream, int channel, unsigned long pos, struct iov_iter *dst, unsigned long count) { struct snd_pcm_runtime *runtime = substream->runtime; struct es1938 *chip = snd_pcm_substream_chip(substream); if (snd_BUG_ON(pos + count > chip->dma1_size)) return -EINVAL; if (pos + count < chip->dma1_size) { if (copy_to_iter(runtime->dma_area + pos + 1, count, dst) != count) return -EFAULT; } else { if (copy_to_iter(runtime->dma_area + pos + 1, count - 1, dst) != count - 1) return -EFAULT; if (copy_to_iter(runtime->dma_area, 1, dst) != 1) return -EFAULT; } return 0; } /* ---------------------------------------------------------------------- * Audio1 Capture (ADC) * ----------------------------------------------------------------------*/ static const struct snd_pcm_hardware snd_es1938_capture = { .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 6000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */ .period_bytes_min = 64, .period_bytes_max = 0x8000, .periods_min = 1, .periods_max = 1024, .fifo_size = 256, }; /* ----------------------------------------------------------------------- * Audio2 Playback (DAC) * -----------------------------------------------------------------------*/ static const struct snd_pcm_hardware snd_es1938_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 6000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */ .period_bytes_min = 64, .period_bytes_max = 0x8000, .periods_min = 1, .periods_max = 1024, .fifo_size = 256, }; static int snd_es1938_capture_open(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; if (chip->playback2_substream) return -EAGAIN; chip->capture_substream = substream; runtime->hw = snd_es1938_capture; snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_clocks); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00); return 0; } static int snd_es1938_playback_open(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; switch (substream->number) { case 0: chip->playback1_substream = substream; break; case 1: if (chip->capture_substream) return -EAGAIN; chip->playback2_substream = substream; break; default: snd_BUG(); return -EINVAL; } runtime->hw = snd_es1938_playback; snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_clocks); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00); return 0; } static int snd_es1938_capture_close(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); chip->capture_substream = NULL; return 0; } static int snd_es1938_playback_close(struct snd_pcm_substream *substream) { struct es1938 *chip = snd_pcm_substream_chip(substream); switch (substream->number) { case 0: chip->playback1_substream = NULL; break; case 1: chip->playback2_substream = NULL; break; default: snd_BUG(); return -EINVAL; } return 0; } static const struct snd_pcm_ops snd_es1938_playback_ops = { .open = snd_es1938_playback_open, .close = snd_es1938_playback_close, .prepare = snd_es1938_playback_prepare, .trigger = snd_es1938_playback_trigger, .pointer = snd_es1938_playback_pointer, }; static const struct snd_pcm_ops snd_es1938_capture_ops = { .open = snd_es1938_capture_open, .close = snd_es1938_capture_close, .prepare = snd_es1938_capture_prepare, .trigger = snd_es1938_capture_trigger, .pointer = snd_es1938_capture_pointer, .copy = snd_es1938_capture_copy, }; static int snd_es1938_new_pcm(struct es1938 *chip, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, "es-1938-1946", device, 2, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1938_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1938_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, "ESS Solo-1"); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 64*1024); chip->pcm = pcm; return 0; } /* ------------------------------------------------------------------- * * *** Mixer part *** */ static int snd_es1938_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[8] = { "Mic", "Mic Master", "CD", "AOUT", "Mic1", "Mix", "Line", "Master" }; return snd_ctl_enum_info(uinfo, 1, 8, texts); } static int snd_es1938_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = snd_es1938_mixer_read(chip, 0x1c) & 0x07; return 0; } static int snd_es1938_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); unsigned char val = ucontrol->value.enumerated.item[0]; if (val > 7) return -EINVAL; return snd_es1938_mixer_bits(chip, 0x1c, 0x07, val) != val; } #define snd_es1938_info_spatializer_enable snd_ctl_boolean_mono_info static int snd_es1938_get_spatializer_enable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); unsigned char val = snd_es1938_mixer_read(chip, 0x50); ucontrol->value.integer.value[0] = !!(val & 8); return 0; } static int snd_es1938_put_spatializer_enable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); unsigned char oval, nval; int change; nval = ucontrol->value.integer.value[0] ? 0x0c : 0x04; oval = snd_es1938_mixer_read(chip, 0x50) & 0x0c; change = nval != oval; if (change) { snd_es1938_mixer_write(chip, 0x50, nval & ~0x04); snd_es1938_mixer_write(chip, 0x50, nval); } return change; } static int snd_es1938_info_hw_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = 63; return 0; } static int snd_es1938_get_hw_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = snd_es1938_mixer_read(chip, 0x61) & 0x3f; ucontrol->value.integer.value[1] = snd_es1938_mixer_read(chip, 0x63) & 0x3f; return 0; } #define snd_es1938_info_hw_switch snd_ctl_boolean_stereo_info static int snd_es1938_get_hw_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = !(snd_es1938_mixer_read(chip, 0x61) & 0x40); ucontrol->value.integer.value[1] = !(snd_es1938_mixer_read(chip, 0x63) & 0x40); return 0; } static void snd_es1938_hwv_free(struct snd_kcontrol *kcontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); chip->master_volume = NULL; chip->master_switch = NULL; chip->hw_volume = NULL; chip->hw_switch = NULL; } static int snd_es1938_reg_bits(struct es1938 *chip, unsigned char reg, unsigned char mask, unsigned char val) { if (reg < 0xa0) return snd_es1938_mixer_bits(chip, reg, mask, val); else return snd_es1938_bits(chip, reg, mask, val); } static int snd_es1938_reg_read(struct es1938 *chip, unsigned char reg) { if (reg < 0xa0) return snd_es1938_mixer_read(chip, reg); else return snd_es1938_read(chip, reg); } #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\ .name = xname, .index = xindex, \ .info = snd_es1938_info_single, \ .get = snd_es1938_get_single, .put = snd_es1938_put_single, \ .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ .tlv = { .p = xtlv } } #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_es1938_info_single, \ .get = snd_es1938_get_single, .put = snd_es1938_put_single, \ .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } static int snd_es1938_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 16) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_es1938_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0xff; int val; val = snd_es1938_reg_read(chip, reg); ucontrol->value.integer.value[0] = (val >> shift) & mask; if (invert) ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; return 0; } static int snd_es1938_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0xff; unsigned char val; val = (ucontrol->value.integer.value[0] & mask); if (invert) val = mask - val; mask <<= shift; val <<= shift; return snd_es1938_reg_bits(chip, reg, mask, val) != val; } #define ES1938_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\ .name = xname, .index = xindex, \ .info = snd_es1938_info_double, \ .get = snd_es1938_get_double, .put = snd_es1938_put_double, \ .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \ .tlv = { .p = xtlv } } #define ES1938_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_es1938_info_double, \ .get = snd_es1938_get_double, .put = snd_es1938_put_double, \ .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } static int snd_es1938_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 24) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_es1938_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int shift_left = (kcontrol->private_value >> 16) & 0x07; int shift_right = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; unsigned char left, right; left = snd_es1938_reg_read(chip, left_reg); if (left_reg != right_reg) right = snd_es1938_reg_read(chip, right_reg); else right = left; ucontrol->value.integer.value[0] = (left >> shift_left) & mask; ucontrol->value.integer.value[1] = (right >> shift_right) & mask; if (invert) { ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; } return 0; } static int snd_es1938_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct es1938 *chip = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int shift_left = (kcontrol->private_value >> 16) & 0x07; int shift_right = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int change; unsigned char val1, val2, mask1, mask2; val1 = ucontrol->value.integer.value[0] & mask; val2 = ucontrol->value.integer.value[1] & mask; if (invert) { val1 = mask - val1; val2 = mask - val2; } val1 <<= shift_left; val2 <<= shift_right; mask1 = mask << shift_left; mask2 = mask << shift_right; if (left_reg != right_reg) { change = 0; if (snd_es1938_reg_bits(chip, left_reg, mask1, val1) != val1) change = 1; if (snd_es1938_reg_bits(chip, right_reg, mask2, val2) != val2) change = 1; } else { change = (snd_es1938_reg_bits(chip, left_reg, mask1 | mask2, val1 | val2) != (val1 | val2)); } return change; } static const DECLARE_TLV_DB_RANGE(db_scale_master, 0, 54, TLV_DB_SCALE_ITEM(-3600, 50, 1), 54, 63, TLV_DB_SCALE_ITEM(-900, 100, 0), ); static const DECLARE_TLV_DB_RANGE(db_scale_audio1, 0, 8, TLV_DB_SCALE_ITEM(-3300, 300, 1), 8, 15, TLV_DB_SCALE_ITEM(-900, 150, 0), ); static const DECLARE_TLV_DB_RANGE(db_scale_audio2, 0, 8, TLV_DB_SCALE_ITEM(-3450, 300, 1), 8, 15, TLV_DB_SCALE_ITEM(-1050, 150, 0), ); static const DECLARE_TLV_DB_RANGE(db_scale_mic, 0, 8, TLV_DB_SCALE_ITEM(-2400, 300, 1), 8, 15, TLV_DB_SCALE_ITEM(0, 150, 0), ); static const DECLARE_TLV_DB_RANGE(db_scale_line, 0, 8, TLV_DB_SCALE_ITEM(-3150, 300, 1), 8, 15, TLV_DB_SCALE_ITEM(-750, 150, 0), ); static const DECLARE_TLV_DB_SCALE(db_scale_capture, 0, 150, 0); static const struct snd_kcontrol_new snd_es1938_controls[] = { ES1938_DOUBLE_TLV("Master Playback Volume", 0, 0x60, 0x62, 0, 0, 63, 0, db_scale_master), ES1938_DOUBLE("Master Playback Switch", 0, 0x60, 0x62, 6, 6, 1, 1), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Hardware Master Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READ, .info = snd_es1938_info_hw_volume, .get = snd_es1938_get_hw_volume, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Hardware Master Playback Switch", .info = snd_es1938_info_hw_switch, .get = snd_es1938_get_hw_switch, .tlv = { .p = db_scale_master }, }, ES1938_SINGLE("Hardware Volume Split", 0, 0x64, 7, 1, 0), ES1938_DOUBLE_TLV("Line Playback Volume", 0, 0x3e, 0x3e, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE("CD Playback Volume", 0, 0x38, 0x38, 4, 0, 15, 0), ES1938_DOUBLE_TLV("FM Playback Volume", 0, 0x36, 0x36, 4, 0, 15, 0, db_scale_mic), ES1938_DOUBLE_TLV("Mono Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("Mic Playback Volume", 0, 0x1a, 0x1a, 4, 0, 15, 0, db_scale_mic), ES1938_DOUBLE_TLV("Aux Playback Volume", 0, 0x3a, 0x3a, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("Capture Volume", 0, 0xb4, 0xb4, 4, 0, 15, 0, db_scale_capture), ES1938_SINGLE("Beep Volume", 0, 0x3c, 0, 7, 0), ES1938_SINGLE("Record Monitor", 0, 0xa8, 3, 1, 0), ES1938_SINGLE("Capture Switch", 0, 0x1c, 4, 1, 1), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Capture Source", .info = snd_es1938_info_mux, .get = snd_es1938_get_mux, .put = snd_es1938_put_mux, }, ES1938_DOUBLE_TLV("Mono Input Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("PCM Capture Volume", 0, 0x69, 0x69, 4, 0, 15, 0, db_scale_audio2), ES1938_DOUBLE_TLV("Mic Capture Volume", 0, 0x68, 0x68, 4, 0, 15, 0, db_scale_mic), ES1938_DOUBLE_TLV("Line Capture Volume", 0, 0x6e, 0x6e, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("FM Capture Volume", 0, 0x6b, 0x6b, 4, 0, 15, 0, db_scale_mic), ES1938_DOUBLE_TLV("Mono Capture Volume", 0, 0x6f, 0x6f, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("CD Capture Volume", 0, 0x6a, 0x6a, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("Aux Capture Volume", 0, 0x6c, 0x6c, 4, 0, 15, 0, db_scale_line), ES1938_DOUBLE_TLV("PCM Playback Volume", 0, 0x7c, 0x7c, 4, 0, 15, 0, db_scale_audio2), ES1938_DOUBLE_TLV("PCM Playback Volume", 1, 0x14, 0x14, 4, 0, 15, 0, db_scale_audio1), ES1938_SINGLE("3D Control - Level", 0, 0x52, 0, 63, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "3D Control - Switch", .info = snd_es1938_info_spatializer_enable, .get = snd_es1938_get_spatializer_enable, .put = snd_es1938_put_spatializer_enable, }, ES1938_SINGLE("Mic Boost (+26dB)", 0, 0x7d, 3, 1, 0) }; /* ---------------------------------------------------------------------------- */ /* ---------------------------------------------------------------------------- */ /* * initialize the chip - used by resume callback, too */ static void snd_es1938_chip_init(struct es1938 *chip) { /* reset chip */ snd_es1938_reset(chip); /* configure native mode */ /* enable bus master */ pci_set_master(chip->pci); /* disable legacy audio */ pci_write_config_word(chip->pci, SL_PCI_LEGACYCONTROL, 0x805f); /* set DDMA base */ pci_write_config_word(chip->pci, SL_PCI_DDMACONTROL, chip->ddma_port | 1); /* set DMA/IRQ policy */ pci_write_config_dword(chip->pci, SL_PCI_CONFIG, 0); /* enable Audio 1, Audio 2, MPU401 IRQ and HW volume IRQ*/ outb(0xf0, SLIO_REG(chip, IRQCONTROL)); /* reset DMA */ outb(0, SLDM_REG(chip, DMACLEAR)); } #ifdef CONFIG_PM_SLEEP /* * PM support */ static const unsigned char saved_regs[SAVED_REG_SIZE+1] = { 0x14, 0x1a, 0x1c, 0x3a, 0x3c, 0x3e, 0x36, 0x38, 0x50, 0x52, 0x60, 0x61, 0x62, 0x63, 0x64, 0x68, 0x69, 0x6a, 0x6b, 0x6d, 0x6e, 0x6f, 0x7c, 0x7d, 0xa8, 0xb4, }; static int es1938_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct es1938 *chip = card->private_data; const unsigned char *s; unsigned char *d; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); /* save mixer-related registers */ for (s = saved_regs, d = chip->saved_regs; *s; s++, d++) *d = snd_es1938_reg_read(chip, *s); outb(0x00, SLIO_REG(chip, IRQCONTROL)); /* disable irqs */ if (chip->irq >= 0) { free_irq(chip->irq, chip); chip->irq = -1; card->sync_irq = -1; } return 0; } static int es1938_resume(struct device *dev) { struct pci_dev *pci = to_pci_dev(dev); struct snd_card *card = dev_get_drvdata(dev); struct es1938 *chip = card->private_data; const unsigned char *s; unsigned char *d; if (request_irq(pci->irq, snd_es1938_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(dev, "unable to grab IRQ %d, disabling device\n", pci->irq); snd_card_disconnect(card); return -EIO; } chip->irq = pci->irq; card->sync_irq = chip->irq; snd_es1938_chip_init(chip); /* restore mixer-related registers */ for (s = saved_regs, d = chip->saved_regs; *s; s++, d++) { if (*s < 0xa0) snd_es1938_mixer_write(chip, *s, *d); else snd_es1938_write(chip, *s, *d); } snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(es1938_pm, es1938_suspend, es1938_resume); #define ES1938_PM_OPS &es1938_pm #else #define ES1938_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ #ifdef SUPPORT_JOYSTICK static int snd_es1938_create_gameport(struct es1938 *chip) { struct gameport *gp; chip->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(chip->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "ES1938"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); gameport_set_dev_parent(gp, &chip->pci->dev); gp->io = chip->game_port; gameport_register_port(gp); return 0; } static void snd_es1938_free_gameport(struct es1938 *chip) { if (chip->gameport) { gameport_unregister_port(chip->gameport); chip->gameport = NULL; } } #else static inline int snd_es1938_create_gameport(struct es1938 *chip) { return -ENOSYS; } static inline void snd_es1938_free_gameport(struct es1938 *chip) { } #endif /* SUPPORT_JOYSTICK */ static void snd_es1938_free(struct snd_card *card) { struct es1938 *chip = card->private_data; /* disable irqs */ outb(0x00, SLIO_REG(chip, IRQCONTROL)); if (chip->rmidi) snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0); snd_es1938_free_gameport(chip); if (chip->irq >= 0) free_irq(chip->irq, chip); } static int snd_es1938_create(struct snd_card *card, struct pci_dev *pci) { struct es1938 *chip = card->private_data; int err; /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; /* check, if we can restrict PCI DMA transfers to 24 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { dev_err(card->dev, "architecture does not support 24bit PCI busmaster DMA\n"); return -ENXIO; } spin_lock_init(&chip->reg_lock); spin_lock_init(&chip->mixer_lock); chip->card = card; chip->pci = pci; chip->irq = -1; err = pci_request_regions(pci, "ESS Solo-1"); if (err < 0) return err; chip->io_port = pci_resource_start(pci, 0); chip->sb_port = pci_resource_start(pci, 1); chip->vc_port = pci_resource_start(pci, 2); chip->mpu_port = pci_resource_start(pci, 3); chip->game_port = pci_resource_start(pci, 4); /* still use non-managed irq handler as it's re-acquired at PM resume */ if (request_irq(pci->irq, snd_es1938_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_es1938_free; dev_dbg(card->dev, "create: io: 0x%lx, sb: 0x%lx, vc: 0x%lx, mpu: 0x%lx, game: 0x%lx\n", chip->io_port, chip->sb_port, chip->vc_port, chip->mpu_port, chip->game_port); chip->ddma_port = chip->vc_port + 0x00; /* fix from Thomas Sailer */ snd_es1938_chip_init(chip); return 0; } /* -------------------------------------------------------------------- * Interrupt handler * -------------------------------------------------------------------- */ static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id) { struct es1938 *chip = dev_id; unsigned char status; __always_unused unsigned char audiostatus; int handled = 0; status = inb(SLIO_REG(chip, IRQCONTROL)); #if 0 dev_dbg(chip->card->dev, "Es1938debug - interrupt status: =0x%x\n", status); #endif /* AUDIO 1 */ if (status & 0x10) { #if 0 dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 1 interrupt\n"); dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 1 DMAC DMA count: %u\n", inw(SLDM_REG(chip, DMACOUNT))); dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 1 DMAC DMA base: %u\n", inl(SLDM_REG(chip, DMAADDR))); dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 1 DMAC DMA status: 0x%x\n", inl(SLDM_REG(chip, DMASTATUS))); #endif /* clear irq */ handled = 1; audiostatus = inb(SLSB_REG(chip, STATUS)); if (chip->active & ADC1) snd_pcm_period_elapsed(chip->capture_substream); else if (chip->active & DAC1) snd_pcm_period_elapsed(chip->playback2_substream); } /* AUDIO 2 */ if (status & 0x20) { #if 0 dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 2 interrupt\n"); dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 2 DMAC DMA count: %u\n", inw(SLIO_REG(chip, AUDIO2DMACOUNT))); dev_dbg(chip->card->dev, "Es1938debug - AUDIO channel 2 DMAC DMA base: %u\n", inl(SLIO_REG(chip, AUDIO2DMAADDR))); #endif /* clear irq */ handled = 1; snd_es1938_mixer_bits(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x80, 0); if (chip->active & DAC2) snd_pcm_period_elapsed(chip->playback1_substream); } /* Hardware volume */ if (status & 0x40) { int split = snd_es1938_mixer_read(chip, 0x64) & 0x80; handled = 1; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_switch->id); snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_volume->id); if (!split) { snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->master_switch->id); snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->master_volume->id); } /* ack interrupt */ snd_es1938_mixer_write(chip, 0x66, 0x00); } /* MPU401 */ if (status & 0x80) { // the following line is evil! It switches off MIDI interrupt handling after the first interrupt received. // replacing the last 0 by 0x40 works for ESS-Solo1, but just doing nothing works as well! // [email protected] // snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0); /* ack? */ if (chip->rmidi) { handled = 1; snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); } } return IRQ_RETVAL(handled); } #define ES1938_DMA_SIZE 64 static int snd_es1938_mixer(struct es1938 *chip) { struct snd_card *card; unsigned int idx; int err; card = chip->card; strcpy(card->mixername, "ESS Solo-1"); for (idx = 0; idx < ARRAY_SIZE(snd_es1938_controls); idx++) { struct snd_kcontrol *kctl; kctl = snd_ctl_new1(&snd_es1938_controls[idx], chip); switch (idx) { case 0: chip->master_volume = kctl; kctl->private_free = snd_es1938_hwv_free; break; case 1: chip->master_switch = kctl; kctl->private_free = snd_es1938_hwv_free; break; case 2: chip->hw_volume = kctl; kctl->private_free = snd_es1938_hwv_free; break; case 3: chip->hw_switch = kctl; kctl->private_free = snd_es1938_hwv_free; break; } err = snd_ctl_add(card, kctl); if (err < 0) return err; } return 0; } static int __snd_es1938_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct es1938 *chip; struct snd_opl3 *opl3; int idx, err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; for (idx = 0; idx < 5; idx++) if (pci_resource_start(pci, idx) == 0 || !(pci_resource_flags(pci, idx) & IORESOURCE_IO)) return -ENODEV; err = snd_es1938_create(card, pci); if (err < 0) return err; strcpy(card->driver, "ES1938"); strcpy(card->shortname, "ESS ES1938 (Solo-1)"); sprintf(card->longname, "%s rev %i, irq %i", card->shortname, chip->revision, chip->irq); err = snd_es1938_new_pcm(chip, 0); if (err < 0) return err; err = snd_es1938_mixer(chip); if (err < 0) return err; if (snd_opl3_create(card, SLSB_REG(chip, FMLOWADDR), SLSB_REG(chip, FMHIGHADDR), OPL3_HW_OPL3, 1, &opl3) < 0) { dev_err(card->dev, "OPL3 not detected at 0x%lx\n", SLSB_REG(chip, FMLOWADDR)); } else { err = snd_opl3_timer_new(opl3, 0, 1); if (err < 0) return err; err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) return err; } if (snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, chip->mpu_port, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi) < 0) { dev_err(card->dev, "unable to initialize MPU-401\n"); } else { // this line is vital for MIDI interrupt handling on ess-solo1 // [email protected] snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0x40); } snd_es1938_create_gameport(chip); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_es1938_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_es1938_probe(pci, pci_id)); } static struct pci_driver es1938_driver = { .name = KBUILD_MODNAME, .id_table = snd_es1938_ids, .probe = snd_es1938_probe, .driver = { .pm = ES1938_PM_OPS, }, }; module_pci_driver(es1938_driver);
linux-master
sound/pci/es1938.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for ESS Maestro3/Allegro (ES1988) soundcards. * Copyright (c) 2000 by Zach Brown <[email protected]> * Takashi Iwai <[email protected]> * * Most of the hardware init stuffs are based on maestro3 driver for * OSS/Free by Zach Brown. Many thanks to Zach! * * ChangeLog: * Aug. 27, 2001 * - Fixed deadlock on capture * - Added Canyon3D-2 support by Rob Riggs <[email protected]> */ #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" #define DRIVER_NAME "Maestro3" #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/module.h> #include <linux/firmware.h> #include <linux/input.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/mpu401.h> #include <sound/ac97_codec.h> #include <sound/initval.h> #include <asm/byteorder.h> MODULE_AUTHOR("Zach Brown <[email protected]>, Takashi Iwai <[email protected]>"); MODULE_DESCRIPTION("ESS Maestro3 PCI"); MODULE_LICENSE("GPL"); MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw"); MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable this soundcard."); module_param_array(external_amp, bool, NULL, 0444); MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); module_param_array(amp_gpio, int, NULL, 0444); MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); #define MAX_PLAYBACKS 2 #define MAX_CAPTURES 1 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) /* * maestro3 registers */ /* Allegro PCI configuration registers */ #define PCI_LEGACY_AUDIO_CTRL 0x40 #define SOUND_BLASTER_ENABLE 0x00000001 #define FM_SYNTHESIS_ENABLE 0x00000002 #define GAME_PORT_ENABLE 0x00000004 #define MPU401_IO_ENABLE 0x00000008 #define MPU401_IRQ_ENABLE 0x00000010 #define ALIAS_10BIT_IO 0x00000020 #define SB_DMA_MASK 0x000000C0 #define SB_DMA_0 0x00000040 #define SB_DMA_1 0x00000040 #define SB_DMA_R 0x00000080 #define SB_DMA_3 0x000000C0 #define SB_IRQ_MASK 0x00000700 #define SB_IRQ_5 0x00000000 #define SB_IRQ_7 0x00000100 #define SB_IRQ_9 0x00000200 #define SB_IRQ_10 0x00000300 #define MIDI_IRQ_MASK 0x00003800 #define SERIAL_IRQ_ENABLE 0x00004000 #define DISABLE_LEGACY 0x00008000 #define PCI_ALLEGRO_CONFIG 0x50 #define SB_ADDR_240 0x00000004 #define MPU_ADDR_MASK 0x00000018 #define MPU_ADDR_330 0x00000000 #define MPU_ADDR_300 0x00000008 #define MPU_ADDR_320 0x00000010 #define MPU_ADDR_340 0x00000018 #define USE_PCI_TIMING 0x00000040 #define POSTED_WRITE_ENABLE 0x00000080 #define DMA_POLICY_MASK 0x00000700 #define DMA_DDMA 0x00000000 #define DMA_TDMA 0x00000100 #define DMA_PCPCI 0x00000200 #define DMA_WBDMA16 0x00000400 #define DMA_WBDMA4 0x00000500 #define DMA_WBDMA2 0x00000600 #define DMA_WBDMA1 0x00000700 #define DMA_SAFE_GUARD 0x00000800 #define HI_PERF_GP_ENABLE 0x00001000 #define PIC_SNOOP_MODE_0 0x00002000 #define PIC_SNOOP_MODE_1 0x00004000 #define SOUNDBLASTER_IRQ_MASK 0x00008000 #define RING_IN_ENABLE 0x00010000 #define SPDIF_TEST_MODE 0x00020000 #define CLK_MULT_MODE_SELECT_2 0x00040000 #define EEPROM_WRITE_ENABLE 0x00080000 #define CODEC_DIR_IN 0x00100000 #define HV_BUTTON_FROM_GD 0x00200000 #define REDUCED_DEBOUNCE 0x00400000 #define HV_CTRL_ENABLE 0x00800000 #define SPDIF_ENABLE 0x01000000 #define CLK_DIV_SELECT 0x06000000 #define CLK_DIV_BY_48 0x00000000 #define CLK_DIV_BY_49 0x02000000 #define CLK_DIV_BY_50 0x04000000 #define CLK_DIV_RESERVED 0x06000000 #define PM_CTRL_ENABLE 0x08000000 #define CLK_MULT_MODE_SELECT 0x30000000 #define CLK_MULT_MODE_SHIFT 28 #define CLK_MULT_MODE_0 0x00000000 #define CLK_MULT_MODE_1 0x10000000 #define CLK_MULT_MODE_2 0x20000000 #define CLK_MULT_MODE_3 0x30000000 #define INT_CLK_SELECT 0x40000000 #define INT_CLK_MULT_RESET 0x80000000 /* M3 */ #define INT_CLK_SRC_NOT_PCI 0x00100000 #define INT_CLK_MULT_ENABLE 0x80000000 #define PCI_ACPI_CONTROL 0x54 #define PCI_ACPI_D0 0x00000000 #define PCI_ACPI_D1 0xB4F70000 #define PCI_ACPI_D2 0xB4F7B4F7 #define PCI_USER_CONFIG 0x58 #define EXT_PCI_MASTER_ENABLE 0x00000001 #define SPDIF_OUT_SELECT 0x00000002 #define TEST_PIN_DIR_CTRL 0x00000004 #define AC97_CODEC_TEST 0x00000020 #define TRI_STATE_BUFFER 0x00000080 #define IN_CLK_12MHZ_SELECT 0x00000100 #define MULTI_FUNC_DISABLE 0x00000200 #define EXT_MASTER_PAIR_SEL 0x00000400 #define PCI_MASTER_SUPPORT 0x00000800 #define STOP_CLOCK_ENABLE 0x00001000 #define EAPD_DRIVE_ENABLE 0x00002000 #define REQ_TRI_STATE_ENABLE 0x00004000 #define REQ_LOW_ENABLE 0x00008000 #define MIDI_1_ENABLE 0x00010000 #define MIDI_2_ENABLE 0x00020000 #define SB_AUDIO_SYNC 0x00040000 #define HV_CTRL_TEST 0x00100000 #define SOUNDBLASTER_TEST 0x00400000 #define PCI_USER_CONFIG_C 0x5C #define PCI_DDMA_CTRL 0x60 #define DDMA_ENABLE 0x00000001 /* Allegro registers */ #define HOST_INT_CTRL 0x18 #define SB_INT_ENABLE 0x0001 #define MPU401_INT_ENABLE 0x0002 #define ASSP_INT_ENABLE 0x0010 #define RING_INT_ENABLE 0x0020 #define HV_INT_ENABLE 0x0040 #define CLKRUN_GEN_ENABLE 0x0100 #define HV_CTRL_TO_PME 0x0400 #define SOFTWARE_RESET_ENABLE 0x8000 /* * should be using the above defines, probably. */ #define REGB_ENABLE_RESET 0x01 #define REGB_STOP_CLOCK 0x10 #define HOST_INT_STATUS 0x1A #define SB_INT_PENDING 0x01 #define MPU401_INT_PENDING 0x02 #define ASSP_INT_PENDING 0x10 #define RING_INT_PENDING 0x20 #define HV_INT_PENDING 0x40 #define HARDWARE_VOL_CTRL 0x1B #define SHADOW_MIX_REG_VOICE 0x1C #define HW_VOL_COUNTER_VOICE 0x1D #define SHADOW_MIX_REG_MASTER 0x1E #define HW_VOL_COUNTER_MASTER 0x1F #define CODEC_COMMAND 0x30 #define CODEC_READ_B 0x80 #define CODEC_STATUS 0x30 #define CODEC_BUSY_B 0x01 #define CODEC_DATA 0x32 #define RING_BUS_CTRL_A 0x36 #define RAC_PME_ENABLE 0x0100 #define RAC_SDFS_ENABLE 0x0200 #define LAC_PME_ENABLE 0x0400 #define LAC_SDFS_ENABLE 0x0800 #define SERIAL_AC_LINK_ENABLE 0x1000 #define IO_SRAM_ENABLE 0x2000 #define IIS_INPUT_ENABLE 0x8000 #define RING_BUS_CTRL_B 0x38 #define SECOND_CODEC_ID_MASK 0x0003 #define SPDIF_FUNC_ENABLE 0x0010 #define SECOND_AC_ENABLE 0x0020 #define SB_MODULE_INTF_ENABLE 0x0040 #define SSPE_ENABLE 0x0040 #define M3I_DOCK_ENABLE 0x0080 #define SDO_OUT_DEST_CTRL 0x3A #define COMMAND_ADDR_OUT 0x0003 #define PCM_LR_OUT_LOCAL 0x0000 #define PCM_LR_OUT_REMOTE 0x0004 #define PCM_LR_OUT_MUTE 0x0008 #define PCM_LR_OUT_BOTH 0x000C #define LINE1_DAC_OUT_LOCAL 0x0000 #define LINE1_DAC_OUT_REMOTE 0x0010 #define LINE1_DAC_OUT_MUTE 0x0020 #define LINE1_DAC_OUT_BOTH 0x0030 #define PCM_CLS_OUT_LOCAL 0x0000 #define PCM_CLS_OUT_REMOTE 0x0040 #define PCM_CLS_OUT_MUTE 0x0080 #define PCM_CLS_OUT_BOTH 0x00C0 #define PCM_RLF_OUT_LOCAL 0x0000 #define PCM_RLF_OUT_REMOTE 0x0100 #define PCM_RLF_OUT_MUTE 0x0200 #define PCM_RLF_OUT_BOTH 0x0300 #define LINE2_DAC_OUT_LOCAL 0x0000 #define LINE2_DAC_OUT_REMOTE 0x0400 #define LINE2_DAC_OUT_MUTE 0x0800 #define LINE2_DAC_OUT_BOTH 0x0C00 #define HANDSET_OUT_LOCAL 0x0000 #define HANDSET_OUT_REMOTE 0x1000 #define HANDSET_OUT_MUTE 0x2000 #define HANDSET_OUT_BOTH 0x3000 #define IO_CTRL_OUT_LOCAL 0x0000 #define IO_CTRL_OUT_REMOTE 0x4000 #define IO_CTRL_OUT_MUTE 0x8000 #define IO_CTRL_OUT_BOTH 0xC000 #define SDO_IN_DEST_CTRL 0x3C #define STATUS_ADDR_IN 0x0003 #define PCM_LR_IN_LOCAL 0x0000 #define PCM_LR_IN_REMOTE 0x0004 #define PCM_LR_RESERVED 0x0008 #define PCM_LR_IN_BOTH 0x000C #define LINE1_ADC_IN_LOCAL 0x0000 #define LINE1_ADC_IN_REMOTE 0x0010 #define LINE1_ADC_IN_MUTE 0x0020 #define MIC_ADC_IN_LOCAL 0x0000 #define MIC_ADC_IN_REMOTE 0x0040 #define MIC_ADC_IN_MUTE 0x0080 #define LINE2_DAC_IN_LOCAL 0x0000 #define LINE2_DAC_IN_REMOTE 0x0400 #define LINE2_DAC_IN_MUTE 0x0800 #define HANDSET_IN_LOCAL 0x0000 #define HANDSET_IN_REMOTE 0x1000 #define HANDSET_IN_MUTE 0x2000 #define IO_STATUS_IN_LOCAL 0x0000 #define IO_STATUS_IN_REMOTE 0x4000 #define SPDIF_IN_CTRL 0x3E #define SPDIF_IN_ENABLE 0x0001 #define GPIO_DATA 0x60 #define GPIO_DATA_MASK 0x0FFF #define GPIO_HV_STATUS 0x3000 #define GPIO_PME_STATUS 0x4000 #define GPIO_MASK 0x64 #define GPIO_DIRECTION 0x68 #define GPO_PRIMARY_AC97 0x0001 #define GPI_LINEOUT_SENSE 0x0004 #define GPO_SECONDARY_AC97 0x0008 #define GPI_VOL_DOWN 0x0010 #define GPI_VOL_UP 0x0020 #define GPI_IIS_CLK 0x0040 #define GPI_IIS_LRCLK 0x0080 #define GPI_IIS_DATA 0x0100 #define GPI_DOCKING_STATUS 0x0100 #define GPI_HEADPHONE_SENSE 0x0200 #define GPO_EXT_AMP_SHUTDOWN 0x1000 #define GPO_EXT_AMP_M3 1 /* default m3 amp */ #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ /* M3 */ #define GPO_M3_EXT_AMP_SHUTDN 0x0002 #define ASSP_INDEX_PORT 0x80 #define ASSP_MEMORY_PORT 0x82 #define ASSP_DATA_PORT 0x84 #define MPU401_DATA_PORT 0x98 #define MPU401_STATUS_PORT 0x99 #define CLK_MULT_DATA_PORT 0x9C #define ASSP_CONTROL_A 0xA2 #define ASSP_0_WS_ENABLE 0x01 #define ASSP_CTRL_A_RESERVED1 0x02 #define ASSP_CTRL_A_RESERVED2 0x04 #define ASSP_CLK_49MHZ_SELECT 0x08 #define FAST_PLU_ENABLE 0x10 #define ASSP_CTRL_A_RESERVED3 0x20 #define DSP_CLK_36MHZ_SELECT 0x40 #define ASSP_CONTROL_B 0xA4 #define RESET_ASSP 0x00 #define RUN_ASSP 0x01 #define ENABLE_ASSP_CLOCK 0x00 #define STOP_ASSP_CLOCK 0x10 #define RESET_TOGGLE 0x40 #define ASSP_CONTROL_C 0xA6 #define ASSP_HOST_INT_ENABLE 0x01 #define FM_ADDR_REMAP_DISABLE 0x02 #define HOST_WRITE_PORT_ENABLE 0x08 #define ASSP_HOST_INT_STATUS 0xAC #define DSP2HOST_REQ_PIORECORD 0x01 #define DSP2HOST_REQ_I2SRATE 0x02 #define DSP2HOST_REQ_TIMER 0x04 /* * ASSP control regs */ #define DSP_PORT_TIMER_COUNT 0x06 #define DSP_PORT_MEMORY_INDEX 0x80 #define DSP_PORT_MEMORY_TYPE 0x82 #define MEMTYPE_INTERNAL_CODE 0x0002 #define MEMTYPE_INTERNAL_DATA 0x0003 #define MEMTYPE_MASK 0x0003 #define DSP_PORT_MEMORY_DATA 0x84 #define DSP_PORT_CONTROL_REG_A 0xA2 #define DSP_PORT_CONTROL_REG_B 0xA4 #define DSP_PORT_CONTROL_REG_C 0xA6 #define REV_A_CODE_MEMORY_BEGIN 0x0000 #define REV_A_CODE_MEMORY_END 0x0FFF #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) #define REV_B_CODE_MEMORY_BEGIN 0x0000 #define REV_B_CODE_MEMORY_END 0x0BFF #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) #define REV_A_DATA_MEMORY_BEGIN 0x1000 #define REV_A_DATA_MEMORY_END 0x2FFF #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) #define REV_B_DATA_MEMORY_BEGIN 0x1000 #define REV_B_DATA_MEMORY_END 0x2BFF #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) #define NUM_UNITS_KERNEL_CODE 16 #define NUM_UNITS_KERNEL_DATA 2 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 /* * Kernel data layout */ #define DP_SHIFT_COUNT 7 #define KDATA_BASE_ADDR 0x1000 #define KDATA_BASE_ADDR2 0x1080 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) /* * second 'segment' (?) reserved for mixer * buffers.. */ #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) /* * client data area offsets */ #define CDATA_INSTANCE_READY 0x00 #define CDATA_HOST_SRC_ADDRL 0x01 #define CDATA_HOST_SRC_ADDRH 0x02 #define CDATA_HOST_SRC_END_PLUS_1L 0x03 #define CDATA_HOST_SRC_END_PLUS_1H 0x04 #define CDATA_HOST_SRC_CURRENTL 0x05 #define CDATA_HOST_SRC_CURRENTH 0x06 #define CDATA_IN_BUF_CONNECT 0x07 #define CDATA_OUT_BUF_CONNECT 0x08 #define CDATA_IN_BUF_BEGIN 0x09 #define CDATA_IN_BUF_END_PLUS_1 0x0A #define CDATA_IN_BUF_HEAD 0x0B #define CDATA_IN_BUF_TAIL 0x0C #define CDATA_OUT_BUF_BEGIN 0x0D #define CDATA_OUT_BUF_END_PLUS_1 0x0E #define CDATA_OUT_BUF_HEAD 0x0F #define CDATA_OUT_BUF_TAIL 0x10 #define CDATA_DMA_CONTROL 0x11 #define CDATA_RESERVED 0x12 #define CDATA_FREQUENCY 0x13 #define CDATA_LEFT_VOLUME 0x14 #define CDATA_RIGHT_VOLUME 0x15 #define CDATA_LEFT_SUR_VOL 0x16 #define CDATA_RIGHT_SUR_VOL 0x17 #define CDATA_HEADER_LEN 0x18 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) #define MINISRC_BIQUAD_STAGE 2 #define MINISRC_COEF_LOC 0x175 #define DMACONTROL_BLOCK_MASK 0x000F #define DMAC_BLOCK0_SELECTOR 0x0000 #define DMAC_BLOCK1_SELECTOR 0x0001 #define DMAC_BLOCK2_SELECTOR 0x0002 #define DMAC_BLOCK3_SELECTOR 0x0003 #define DMAC_BLOCK4_SELECTOR 0x0004 #define DMAC_BLOCK5_SELECTOR 0x0005 #define DMAC_BLOCK6_SELECTOR 0x0006 #define DMAC_BLOCK7_SELECTOR 0x0007 #define DMAC_BLOCK8_SELECTOR 0x0008 #define DMAC_BLOCK9_SELECTOR 0x0009 #define DMAC_BLOCKA_SELECTOR 0x000A #define DMAC_BLOCKB_SELECTOR 0x000B #define DMAC_BLOCKC_SELECTOR 0x000C #define DMAC_BLOCKD_SELECTOR 0x000D #define DMAC_BLOCKE_SELECTOR 0x000E #define DMAC_BLOCKF_SELECTOR 0x000F #define DMACONTROL_PAGE_MASK 0x00F0 #define DMAC_PAGE0_SELECTOR 0x0030 #define DMAC_PAGE1_SELECTOR 0x0020 #define DMAC_PAGE2_SELECTOR 0x0010 #define DMAC_PAGE3_SELECTOR 0x0000 #define DMACONTROL_AUTOREPEAT 0x1000 #define DMACONTROL_STOPPED 0x2000 #define DMACONTROL_DIRECTION 0x0100 /* * an arbitrary volume we set the internal * volume settings to so that the ac97 volume * range is a little less insane. 0x7fff is * max. */ #define ARB_VOLUME ( 0x6800 ) /* */ struct m3_list { int curlen; int mem_addr; int max; }; struct m3_dma { int number; struct snd_pcm_substream *substream; struct assp_instance { unsigned short code, data; } inst; int running; int opened; unsigned long buffer_addr; int dma_size; int period_size; unsigned int hwptr; int count; int index[3]; struct m3_list *index_list[3]; int in_lists; struct list_head list; }; struct snd_m3 { struct snd_card *card; unsigned long iobase; int irq; unsigned int allegro_flag : 1; struct snd_ac97 *ac97; struct snd_pcm *pcm; struct pci_dev *pci; int dacs_active; int timer_users; struct m3_list msrc_list; struct m3_list mixer_list; struct m3_list adc1_list; struct m3_list dma_list; /* for storing reset state..*/ u8 reset_state; int external_amp; int amp_gpio; /* gpio pin # for external amp, -1 = default */ unsigned int hv_config; /* hardware-volume config bits */ unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION (e.g. for IrDA on Dell Inspirons) */ unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */ /* midi */ struct snd_rawmidi *rmidi; /* pcm streams */ int num_substreams; struct m3_dma *substreams; spinlock_t reg_lock; #ifdef CONFIG_SND_MAESTRO3_INPUT struct input_dev *input_dev; char phys[64]; /* physical device path */ #else struct snd_kcontrol *master_switch; struct snd_kcontrol *master_volume; #endif struct work_struct hwvol_work; unsigned int in_suspend; #ifdef CONFIG_PM_SLEEP u16 *suspend_mem; #endif const struct firmware *assp_kernel_image; const struct firmware *assp_minisrc_image; }; /* * pci ids */ static const struct pci_device_id snd_m3_ids[] = { {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, {0,}, }; MODULE_DEVICE_TABLE(pci, snd_m3_ids); static const struct snd_pci_quirk m3_amp_quirk_list[] = { SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c), SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d), SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d), SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03), SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03), { } /* END */ }; static const struct snd_pci_quirk m3_irda_quirk_list[] = { SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1), SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1), SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1), { } /* END */ }; /* hardware volume quirks */ static const struct snd_pci_quirk m3_hv_quirk_list[] = { /* Allegro chips */ SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), SND_PCI_QUIRK(0x1033, 0x80F1, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */ HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x107B, 0x340A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x107B, 0x3450, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x109F, 0x3134, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x109F, 0x3161, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0x3280, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0x3281, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0xC002, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0xC003, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x1509, 0x1740, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x1610, 0x0010, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE), /* Maestro3 chips */ SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE), SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), { } /* END */ }; /* HP Omnibook quirks */ static const struct snd_pci_quirk m3_omnibook_quirk_list[] = { SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */ SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */ { } /* END */ }; /* * lowlevel functions */ static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) { outw(value, chip->iobase + reg); } static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) { return inw(chip->iobase + reg); } static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) { outb(value, chip->iobase + reg); } static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) { return inb(chip->iobase + reg); } /* * access 16bit words to the code or data regions of the dsp's memory. * index addresses 16bit words. */ static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index) { snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); } static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data) { snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); } static void snd_m3_assp_halt(struct snd_m3 *chip) { chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; msleep(10); snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); } static void snd_m3_assp_continue(struct snd_m3 *chip) { snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); } /* * This makes me sad. the maestro3 has lists * internally that must be packed.. 0 terminates, * apparently, or maybe all unused entries have * to be 0, the lists have static lengths set * by the binary code images. */ static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) { snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, list->mem_addr + list->curlen, val); return list->curlen++; } static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index) { u16 val; int lastindex = list->curlen - 1; if (index != lastindex) { val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, list->mem_addr + lastindex); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, list->mem_addr + index, val); } snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, list->mem_addr + lastindex, 0); list->curlen--; } static void snd_m3_inc_timer_users(struct snd_m3 *chip) { chip->timer_users++; if (chip->timer_users != 1) return; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_TIMER_COUNT_RELOAD, 240); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_TIMER_COUNT_CURRENT, 240); snd_m3_outw(chip, snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, HOST_INT_CTRL); } static void snd_m3_dec_timer_users(struct snd_m3 *chip) { chip->timer_users--; if (chip->timer_users > 0) return; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_TIMER_COUNT_RELOAD, 0); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_TIMER_COUNT_CURRENT, 0); snd_m3_outw(chip, snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, HOST_INT_CTRL); } /* * start/stop */ /* spinlock held! */ static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { if (! s || ! subs) return -EINVAL; snd_m3_inc_timer_users(chip); switch (subs->stream) { case SNDRV_PCM_STREAM_PLAYBACK: chip->dacs_active++; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_INSTANCE_READY, 1); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_MIXER_TASK_NUMBER, chip->dacs_active); break; case SNDRV_PCM_STREAM_CAPTURE: snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_ADC1_REQUEST, 1); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_INSTANCE_READY, 1); break; } return 0; } /* spinlock held! */ static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { if (! s || ! subs) return -EINVAL; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_INSTANCE_READY, 0); snd_m3_dec_timer_users(chip); switch (subs->stream) { case SNDRV_PCM_STREAM_PLAYBACK: chip->dacs_active--; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_MIXER_TASK_NUMBER, chip->dacs_active); break; case SNDRV_PCM_STREAM_CAPTURE: snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_ADC1_REQUEST, 0); break; } return 0; } static int snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); struct m3_dma *s = subs->runtime->private_data; int err = -EINVAL; if (snd_BUG_ON(!s)) return -ENXIO; spin_lock(&chip->reg_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: if (s->running) err = -EBUSY; else { s->running = 1; err = snd_m3_pcm_start(chip, s, subs); } break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: if (! s->running) err = 0; /* should return error? */ else { s->running = 0; err = snd_m3_pcm_stop(chip, s, subs); } break; } spin_unlock(&chip->reg_lock); return err; } /* * setup */ static void snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; struct snd_pcm_runtime *runtime = subs->runtime; if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); } else { dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); } dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); s->period_size = frames_to_bytes(runtime, runtime->period_size); s->hwptr = 0; s->count = 0; #define LO(x) ((x) & 0xffff) #define HI(x) LO((x) >> 16) /* host dma buffer pointers */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_ADDRL, LO(s->buffer_addr)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_ADDRH, HI(s->buffer_addr)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, LO(s->buffer_addr + s->dma_size)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, HI(s->buffer_addr + s->dma_size)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_CURRENTL, LO(s->buffer_addr)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_CURRENTH, HI(s->buffer_addr)); #undef LO #undef HI /* dsp buffers */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_IN_BUF_BEGIN, dsp_in_buffer); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_IN_BUF_END_PLUS_1, dsp_in_buffer + (dsp_in_size / 2)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_IN_BUF_HEAD, dsp_in_buffer); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_IN_BUF_TAIL, dsp_in_buffer); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_OUT_BUF_BEGIN, dsp_out_buffer); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_OUT_BUF_END_PLUS_1, dsp_out_buffer + (dsp_out_size / 2)); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_OUT_BUF_HEAD, dsp_out_buffer); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_OUT_BUF_TAIL, dsp_out_buffer); } static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_runtime *runtime) { u32 freq; /* * put us in the lists if we're not already there */ if (! s->in_lists) { s->index[0] = snd_m3_add_list(chip, s->index_list[0], s->inst.data >> DP_SHIFT_COUNT); s->index[1] = snd_m3_add_list(chip, s->index_list[1], s->inst.data >> DP_SHIFT_COUNT); s->index[2] = snd_m3_add_list(chip, s->index_list[2], s->inst.data >> DP_SHIFT_COUNT); s->in_lists = 1; } /* write to 'mono' word */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 1, runtime->channels == 2 ? 0 : 1); /* write to '8bit' word */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 2, snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); /* set up dac/adc rate */ freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000); if (freq) freq--; snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_FREQUENCY, freq); } static const struct play_vals { u16 addr, val; } pv[] = { {CDATA_LEFT_VOLUME, ARB_VOLUME}, {CDATA_RIGHT_VOLUME, ARB_VOLUME}, {SRC3_DIRECTION_OFFSET, 0} , /* +1, +2 are stereo/16 bit */ {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ }; /* the mode passed should be already shifted and masked */ static void snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { unsigned int i; /* * some per client initializers */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 12, s->inst.data + 40 + 8); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 19, s->inst.code + MINISRC_COEF_LOC); /* enable or disable low pass filter? */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 22, subs->runtime->rate > 45000 ? 0xff : 0); /* tell it which way dma is going? */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_DMA_CONTROL, DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); /* * set an armload of static initializers */ for (i = 0; i < ARRAY_SIZE(pv); i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + pv[i].addr, pv[i].val); } /* * Native record driver */ static const struct rec_vals { u16 addr, val; } rv[] = { {CDATA_LEFT_VOLUME, ARB_VOLUME}, {CDATA_RIGHT_VOLUME, ARB_VOLUME}, {SRC3_DIRECTION_OFFSET, 1} , /* +1, +2 are stereo/16 bit */ {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ }; static void snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { unsigned int i; /* * some per client initializers */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + SRC3_DIRECTION_OFFSET + 12, s->inst.data + 40 + 8); /* tell it which way dma is going? */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_DMA_CONTROL, DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); /* * set an armload of static initializers */ for (i = 0; i < ARRAY_SIZE(rv); i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + rv[i].addr, rv[i].val); } static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct m3_dma *s = substream->runtime->private_data; /* set buffer address */ s->buffer_addr = substream->runtime->dma_addr; if (s->buffer_addr & 0x3) { dev_err(substream->pcm->card->dev, "oh my, not aligned\n"); s->buffer_addr = s->buffer_addr & ~0x3; } return 0; } static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream) { struct m3_dma *s; if (substream->runtime->private_data == NULL) return 0; s = substream->runtime->private_data; s->buffer_addr = 0; return 0; } static int snd_m3_pcm_prepare(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); struct snd_pcm_runtime *runtime = subs->runtime; struct m3_dma *s = runtime->private_data; if (snd_BUG_ON(!s)) return -ENXIO; if (runtime->format != SNDRV_PCM_FORMAT_U8 && runtime->format != SNDRV_PCM_FORMAT_S16_LE) return -EINVAL; if (runtime->rate > 48000 || runtime->rate < 8000) return -EINVAL; spin_lock_irq(&chip->reg_lock); snd_m3_pcm_setup1(chip, s, subs); if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) snd_m3_playback_setup(chip, s, subs); else snd_m3_capture_setup(chip, s, subs); snd_m3_pcm_setup2(chip, s, runtime); spin_unlock_irq(&chip->reg_lock); return 0; } /* * get current pointer */ static unsigned int snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) { u16 hi = 0, lo = 0; int retry = 10; u32 addr; /* * try and get a valid answer */ while (retry--) { hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_CURRENTH); lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_CURRENTL); if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, s->inst.data + CDATA_HOST_SRC_CURRENTH)) break; } addr = lo | ((u32)hi<<16); return (unsigned int)(addr - s->buffer_addr); } static snd_pcm_uframes_t snd_m3_pcm_pointer(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); unsigned int ptr; struct m3_dma *s = subs->runtime->private_data; if (snd_BUG_ON(!s)) return 0; spin_lock(&chip->reg_lock); ptr = snd_m3_get_pointer(chip, s, subs); spin_unlock(&chip->reg_lock); return bytes_to_frames(subs->runtime, ptr); } /* update pointer */ /* spinlock held! */ static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s) { struct snd_pcm_substream *subs = s->substream; unsigned int hwptr; int diff; if (! s->running) return; hwptr = snd_m3_get_pointer(chip, s, subs); /* try to avoid expensive modulo divisions */ if (hwptr >= s->dma_size) hwptr %= s->dma_size; diff = s->dma_size + hwptr - s->hwptr; if (diff >= s->dma_size) diff %= s->dma_size; s->hwptr = hwptr; s->count += diff; if (s->count >= (signed)s->period_size) { if (s->count < 2 * (signed)s->period_size) s->count -= (signed)s->period_size; else s->count %= s->period_size; spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(subs); spin_lock(&chip->reg_lock); } } /* The m3's hardware volume works by incrementing / decrementing 2 counters (without wrap around) in response to volume button presses and then generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 of a byte wide register. The meaning of bits 0 and 4 is unknown. */ static void snd_m3_update_hw_volume(struct work_struct *work) { struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work); int x, val; /* Figure out which volume control button was pushed, based on differences from the default register values. */ x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; /* Reset the volume counters to 4. Tests on the allegro integrated into a Compaq N600C laptop, have revealed that: 1) Writing any value will result in the 2 counters being reset to 4 so writing 0x88 is not strictly necessary 2) Writing to any of the 4 involved registers will reset all 4 of them (and reading them always returns the same value for all of them) It could be that a maestro deviates from this, so leave the code as is. */ outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); /* Ignore spurious HV interrupts during suspend / resume, this avoids mistaking them for a mute button press. */ if (chip->in_suspend) return; #ifndef CONFIG_SND_MAESTRO3_INPUT if (!chip->master_switch || !chip->master_volume) return; val = snd_ac97_read(chip->ac97, AC97_MASTER); switch (x) { case 0x88: /* The counters have not changed, yet we've received a HV interrupt. According to tests run by various people this happens when pressing the mute button. */ val ^= 0x8000; break; case 0xaa: /* counters increased by 1 -> volume up */ if ((val & 0x7f) > 0) val--; if ((val & 0x7f00) > 0) val -= 0x0100; break; case 0x66: /* counters decreased by 1 -> volume down */ if ((val & 0x7f) < 0x1f) val++; if ((val & 0x7f00) < 0x1f00) val += 0x0100; break; } if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->master_switch->id); #else if (!chip->input_dev) return; val = 0; switch (x) { case 0x88: /* The counters have not changed, yet we've received a HV interrupt. According to tests run by various people this happens when pressing the mute button. */ val = KEY_MUTE; break; case 0xaa: /* counters increased by 1 -> volume up */ val = KEY_VOLUMEUP; break; case 0x66: /* counters decreased by 1 -> volume down */ val = KEY_VOLUMEDOWN; break; } if (val) { input_report_key(chip->input_dev, val, 1); input_sync(chip->input_dev); input_report_key(chip->input_dev, val, 0); input_sync(chip->input_dev); } #endif } static irqreturn_t snd_m3_interrupt(int irq, void *dev_id) { struct snd_m3 *chip = dev_id; u8 status; int i; status = inb(chip->iobase + HOST_INT_STATUS); if (status == 0xff) return IRQ_NONE; if (status & HV_INT_PENDING) schedule_work(&chip->hwvol_work); /* * ack an assp int if its running * and has an int pending */ if (status & ASSP_INT_PENDING) { u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); if (!(ctl & STOP_ASSP_CLOCK)) { ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); if (ctl & DSP2HOST_REQ_TIMER) { outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); /* update adc/dac info if it was a timer int */ spin_lock(&chip->reg_lock); for (i = 0; i < chip->num_substreams; i++) { struct m3_dma *s = &chip->substreams[i]; if (s->running) snd_m3_update_ptr(chip, s); } spin_unlock(&chip->reg_lock); } } } #if 0 /* TODO: not supported yet */ if ((status & MPU401_INT_PENDING) && chip->rmidi) snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); #endif /* ack ints */ outb(status, chip->iobase + HOST_INT_STATUS); return IRQ_HANDLED; } /* */ static const struct snd_pcm_hardware snd_m3_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER | /*SNDRV_PCM_INFO_PAUSE |*/ SNDRV_PCM_INFO_RESUME), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 8000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (512*1024), .period_bytes_min = 64, .period_bytes_max = (512*1024), .periods_min = 1, .periods_max = 1024, }; static const struct snd_pcm_hardware snd_m3_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER | /*SNDRV_PCM_INFO_PAUSE |*/ SNDRV_PCM_INFO_RESUME), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 8000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (512*1024), .period_bytes_min = 64, .period_bytes_max = (512*1024), .periods_min = 1, .periods_max = 1024, }; /* */ static int snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs) { int i; struct m3_dma *s; spin_lock_irq(&chip->reg_lock); for (i = 0; i < chip->num_substreams; i++) { s = &chip->substreams[i]; if (! s->opened) goto __found; } spin_unlock_irq(&chip->reg_lock); return -ENOMEM; __found: s->opened = 1; s->running = 0; spin_unlock_irq(&chip->reg_lock); subs->runtime->private_data = s; s->substream = subs; /* set list owners */ if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { s->index_list[0] = &chip->mixer_list; } else s->index_list[0] = &chip->adc1_list; s->index_list[1] = &chip->msrc_list; s->index_list[2] = &chip->dma_list; return 0; } static void snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs) { struct m3_dma *s = subs->runtime->private_data; if (s == NULL) return; /* not opened properly */ spin_lock_irq(&chip->reg_lock); if (s->substream && s->running) snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ if (s->in_lists) { snd_m3_remove_list(chip, s->index_list[0], s->index[0]); snd_m3_remove_list(chip, s->index_list[1], s->index[1]); snd_m3_remove_list(chip, s->index_list[2], s->index[2]); s->in_lists = 0; } s->running = 0; s->opened = 0; spin_unlock_irq(&chip->reg_lock); } static int snd_m3_playback_open(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); struct snd_pcm_runtime *runtime = subs->runtime; int err; err = snd_m3_substream_open(chip, subs); if (err < 0) return err; runtime->hw = snd_m3_playback; return 0; } static int snd_m3_playback_close(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); snd_m3_substream_close(chip, subs); return 0; } static int snd_m3_capture_open(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); struct snd_pcm_runtime *runtime = subs->runtime; int err; err = snd_m3_substream_open(chip, subs); if (err < 0) return err; runtime->hw = snd_m3_capture; return 0; } static int snd_m3_capture_close(struct snd_pcm_substream *subs) { struct snd_m3 *chip = snd_pcm_substream_chip(subs); snd_m3_substream_close(chip, subs); return 0; } /* * create pcm instance */ static const struct snd_pcm_ops snd_m3_playback_ops = { .open = snd_m3_playback_open, .close = snd_m3_playback_close, .hw_params = snd_m3_pcm_hw_params, .hw_free = snd_m3_pcm_hw_free, .prepare = snd_m3_pcm_prepare, .trigger = snd_m3_pcm_trigger, .pointer = snd_m3_pcm_pointer, }; static const struct snd_pcm_ops snd_m3_capture_ops = { .open = snd_m3_capture_open, .close = snd_m3_capture_close, .hw_params = snd_m3_pcm_hw_params, .hw_free = snd_m3_pcm_hw_free, .prepare = snd_m3_pcm_prepare, .trigger = snd_m3_pcm_trigger, .pointer = snd_m3_pcm_pointer, }; static int snd_m3_pcm(struct snd_m3 * chip, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, chip->card->driver, device, MAX_PLAYBACKS, MAX_CAPTURES, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, chip->card->driver); chip->pcm = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 64*1024); return 0; } /* * ac97 interface */ /* * Wait for the ac97 serial bus to be free. * return nonzero if the bus is still busy. */ static int snd_m3_ac97_wait(struct snd_m3 *chip) { int i = 10000; do { if (! (snd_m3_inb(chip, 0x30) & 1)) return 0; cpu_relax(); } while (i-- > 0); dev_err(chip->card->dev, "ac97 serial bus busy\n"); return 1; } static unsigned short snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { struct snd_m3 *chip = ac97->private_data; unsigned short data = 0xffff; if (snd_m3_ac97_wait(chip)) goto fail; snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); if (snd_m3_ac97_wait(chip)) goto fail; data = snd_m3_inw(chip, CODEC_DATA); fail: return data; } static void snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct snd_m3 *chip = ac97->private_data; if (snd_m3_ac97_wait(chip)) return; snd_m3_outw(chip, val, CODEC_DATA); snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); /* * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent * until the MASTER volume or mute is touched (alsactl restore does not * work). */ if (ac97->id == 0x45838308 && reg == AC97_MASTER) { snd_m3_ac97_wait(chip); snd_m3_outw(chip, val, CODEC_DATA); snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); } } static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote) { int io = chip->iobase; u16 tmp; isremote = isremote ? 1 : 0; tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK; /* enable dock on Dell Latitude C810 */ if (chip->pci->subsystem_vendor == 0x1028 && chip->pci->subsystem_device == 0x00e5) tmp |= M3I_DOCK_ENABLE; outw(tmp | isremote, io + RING_BUS_CTRL_B); outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, io + SDO_OUT_DEST_CTRL); outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, io + SDO_IN_DEST_CTRL); } /* * hack, returns non zero on err */ static int snd_m3_try_read_vendor(struct snd_m3 *chip) { u16 ret; if (snd_m3_ac97_wait(chip)) return 1; snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); if (snd_m3_ac97_wait(chip)) return 1; ret = snd_m3_inw(chip, 0x32); return (ret == 0) || (ret == 0xffff); } static void snd_m3_ac97_reset(struct snd_m3 *chip) { u16 dir; int delay1 = 0, delay2 = 0, i; int io = chip->iobase; if (chip->allegro_flag) { /* * the onboard codec on the allegro seems * to want to wait a very long time before * coming back to life */ delay1 = 50; delay2 = 800; } else { /* maestro3 */ delay1 = 20; delay2 = 500; } for (i = 0; i < 5; i++) { dir = inw(io + GPIO_DIRECTION); if (!chip->irda_workaround) dir |= 0x10; /* assuming pci bus master? */ snd_m3_remote_codec_config(chip, 0); outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); udelay(20); outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); outw(0, io + GPIO_DATA); outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); schedule_timeout_uninterruptible(msecs_to_jiffies(delay1)); outw(GPO_PRIMARY_AC97, io + GPIO_DATA); udelay(5); /* ok, bring back the ac-link */ outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); outw(~0, io + GPIO_MASK); schedule_timeout_uninterruptible(msecs_to_jiffies(delay2)); if (! snd_m3_try_read_vendor(chip)) break; delay1 += 10; delay2 += 100; dev_dbg(chip->card->dev, "retrying codec reset with delays of %d and %d ms\n", delay1, delay2); } #if 0 /* more gung-ho reset that doesn't * seem to work anywhere :) */ tmp = inw(io + RING_BUS_CTRL_A); outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); msleep(20); outw(tmp, io + RING_BUS_CTRL_A); msleep(50); #endif } static int snd_m3_mixer(struct snd_m3 *chip) { struct snd_ac97_bus *pbus; struct snd_ac97_template ac97; int err; static const struct snd_ac97_bus_ops ops = { .write = snd_m3_ac97_write, .read = snd_m3_ac97_read, }; err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus); if (err < 0) return err; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); if (err < 0) return err; /* seems ac97 PCM needs initialization.. hack hack.. */ snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); schedule_timeout_uninterruptible(msecs_to_jiffies(100)); snd_ac97_write(chip->ac97, AC97_PCM, 0); #ifndef CONFIG_SND_MAESTRO3_INPUT chip->master_switch = snd_ctl_find_id_mixer(chip->card, "Master Playback Switch"); chip->master_volume = snd_ctl_find_id_mixer(chip->card, "Master Playback Volume"); #endif return 0; } /* * initialize ASSP */ #define MINISRC_LPF_LEN 10 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = { 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F }; static void snd_m3_assp_init(struct snd_m3 *chip) { unsigned int i; const __le16 *data; /* zero kernel data */ for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_BASE_ADDR + i, 0); /* zero mixer data? */ for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_BASE_ADDR2 + i, 0); /* init dma pointer */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_CURRENT_DMA, KDATA_DMA_XFER0); /* write kernel into code memory.. */ data = (const __le16 *)chip->assp_kernel_image->data; for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, REV_B_CODE_MEMORY_BEGIN + i, le16_to_cpu(data[i])); } /* * We only have this one client and we know that 0x400 * is free in our kernel's mem map, so lets just * drop it there. It seems that the minisrc doesn't * need vectors, so we won't bother with them.. */ data = (const __le16 *)chip->assp_minisrc_image->data; for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 0x400 + i, le16_to_cpu(data[i])); } /* * write the coefficients for the low pass filter? */ for (i = 0; i < MINISRC_LPF_LEN ; i++) { snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 0x400 + MINISRC_COEF_LOC + i, minisrc_lpf[i]); } snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, 0x8000); /* * the minisrc is the only thing on * our task list.. */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_TASK0, 0x400); /* * init the mixer number.. */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_MIXER_TASK_NUMBER,0); /* * EXTREME KERNEL MASTER VOLUME */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); chip->mixer_list.curlen = 0; chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; chip->adc1_list.curlen = 0; chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; chip->dma_list.curlen = 0; chip->dma_list.mem_addr = KDATA_DMA_XFER0; chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; chip->msrc_list.curlen = 0; chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; chip->msrc_list.max = MAX_INSTANCE_MINISRC; } static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index) { int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + MINISRC_IN_BUFFER_SIZE / 2 + 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); int address, i; /* * the revb memory map has 0x1100 through 0x1c00 * free. */ /* * align instance address to 256 bytes so that its * shifted list address is aligned. * list address = (mem address >> 1) >> 7; */ data_bytes = ALIGN(data_bytes, 256); address = 0x1100 + ((data_bytes/2) * index); if ((address + (data_bytes/2)) >= 0x1c00) { dev_err(chip->card->dev, "no memory for %d bytes at ind %d (addr 0x%x)\n", data_bytes, index, address); return -ENOMEM; } s->number = index; s->inst.code = 0x400; s->inst.data = address; for (i = data_bytes / 2; i > 0; address++, i--) { snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, address, 0); } return 0; } /* * this works for the reference board, have to find * out about others * * this needs more magic for 4 speaker, but.. */ static void snd_m3_amp_enable(struct snd_m3 *chip, int enable) { int io = chip->iobase; u16 gpo, polarity; if (! chip->external_amp) return; polarity = enable ? 0 : 1; polarity = polarity << chip->amp_gpio; gpo = 1 << chip->amp_gpio; outw(~gpo, io + GPIO_MASK); outw(inw(io + GPIO_DIRECTION) | gpo, io + GPIO_DIRECTION); outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), io + GPIO_DATA); outw(0xffff, io + GPIO_MASK); } static void snd_m3_hv_init(struct snd_m3 *chip) { unsigned long io = chip->iobase; u16 val = GPI_VOL_DOWN | GPI_VOL_UP; if (!chip->is_omnibook) return; /* * Volume buttons on some HP OmniBook laptops * require some GPIO magic to work correctly. */ outw(0xffff, io + GPIO_MASK); outw(0x0000, io + GPIO_DATA); outw(~val, io + GPIO_MASK); outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION); outw(val, io + GPIO_MASK); outw(0xffff, io + GPIO_MASK); } static int snd_m3_chip_init(struct snd_m3 *chip) { struct pci_dev *pcidev = chip->pci; unsigned long io = chip->iobase; u32 n; u16 w; u8 t; /* makes as much sense as 'n', no? */ pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| DISABLE_LEGACY); pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); n |= chip->hv_config; /* For some reason we must always use reduced debounce. */ n |= REDUCED_DEBOUNCE; n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); n &= ~INT_CLK_SELECT; if (!chip->allegro_flag) { n &= ~INT_CLK_MULT_ENABLE; n |= INT_CLK_SRC_NOT_PCI; } n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); if (chip->allegro_flag) { pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); n |= IN_CLK_12MHZ_SELECT; pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); } t = inb(chip->iobase + ASSP_CONTROL_A); t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); t |= ASSP_CLK_49MHZ_SELECT; t |= ASSP_0_WS_ENABLE; outb(t, chip->iobase + ASSP_CONTROL_A); snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */ outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); outb(0x00, io + HARDWARE_VOL_CTRL); outb(0x88, io + SHADOW_MIX_REG_VOICE); outb(0x88, io + HW_VOL_COUNTER_VOICE); outb(0x88, io + SHADOW_MIX_REG_MASTER); outb(0x88, io + HW_VOL_COUNTER_MASTER); return 0; } static void snd_m3_enable_ints(struct snd_m3 *chip) { unsigned long io = chip->iobase; unsigned short val; /* TODO: MPU401 not supported yet */ val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; if (chip->hv_config & HV_CTRL_ENABLE) val |= HV_INT_ENABLE; outb(val, chip->iobase + HOST_INT_STATUS); outw(val, io + HOST_INT_CTRL); outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, io + ASSP_CONTROL_C); } /* */ static void snd_m3_free(struct snd_card *card) { struct snd_m3 *chip = card->private_data; struct m3_dma *s; int i; cancel_work_sync(&chip->hwvol_work); if (chip->substreams) { spin_lock_irq(&chip->reg_lock); for (i = 0; i < chip->num_substreams; i++) { s = &chip->substreams[i]; /* check surviving pcms; this should not happen though.. */ if (s->substream && s->running) snd_m3_pcm_stop(chip, s, s->substream); } spin_unlock_irq(&chip->reg_lock); } if (chip->iobase) { outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ } #ifdef CONFIG_PM_SLEEP vfree(chip->suspend_mem); #endif release_firmware(chip->assp_kernel_image); release_firmware(chip->assp_minisrc_image); } /* * APM support */ #ifdef CONFIG_PM_SLEEP static int m3_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_m3 *chip = card->private_data; int i, dsp_index; if (chip->suspend_mem == NULL) return 0; chip->in_suspend = 1; cancel_work_sync(&chip->hwvol_work); snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_ac97_suspend(chip->ac97); msleep(10); /* give the assp a chance to idle.. */ snd_m3_assp_halt(chip); /* save dsp image */ dsp_index = 0; for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) chip->suspend_mem[dsp_index++] = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) chip->suspend_mem[dsp_index++] = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); return 0; } static int m3_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_m3 *chip = card->private_data; int i, dsp_index; if (chip->suspend_mem == NULL) return 0; /* first lets just bring everything back. .*/ snd_m3_outw(chip, 0, 0x54); snd_m3_outw(chip, 0, 0x56); snd_m3_chip_init(chip); snd_m3_assp_halt(chip); snd_m3_ac97_reset(chip); /* restore dsp image */ dsp_index = 0; for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, chip->suspend_mem[dsp_index++]); for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, chip->suspend_mem[dsp_index++]); /* tell the dma engine to restart itself */ snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, KDATA_DMA_ACTIVE, 0); /* restore ac97 registers */ snd_ac97_resume(chip->ac97); snd_m3_assp_continue(chip); snd_m3_enable_ints(chip); snd_m3_amp_enable(chip, 1); snd_m3_hv_init(chip); snd_power_change_state(card, SNDRV_CTL_POWER_D0); chip->in_suspend = 0; return 0; } static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume); #define M3_PM_OPS &m3_pm #else #define M3_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_SND_MAESTRO3_INPUT static int snd_m3_input_register(struct snd_m3 *chip) { struct input_dev *input_dev; int err; input_dev = devm_input_allocate_device(&chip->pci->dev); if (!input_dev) return -ENOMEM; snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", pci_name(chip->pci)); input_dev->name = chip->card->driver; input_dev->phys = chip->phys; input_dev->id.bustype = BUS_PCI; input_dev->id.vendor = chip->pci->vendor; input_dev->id.product = chip->pci->device; input_dev->dev.parent = &chip->pci->dev; __set_bit(EV_KEY, input_dev->evbit); __set_bit(KEY_MUTE, input_dev->keybit); __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); __set_bit(KEY_VOLUMEUP, input_dev->keybit); err = input_register_device(input_dev); if (err) return err; chip->input_dev = input_dev; return 0; } #endif /* CONFIG_INPUT */ /* */ static int snd_m3_create(struct snd_card *card, struct pci_dev *pci, int enable_amp, int amp_gpio) { struct snd_m3 *chip = card->private_data; int i, err; const struct snd_pci_quirk *quirk; if (pcim_enable_device(pci)) return -EIO; /* check, if we can restrict PCI DMA transfers to 28 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) { dev_err(card->dev, "architecture does not support 28bit PCI busmaster DMA\n"); return -ENXIO; } spin_lock_init(&chip->reg_lock); switch (pci->device) { case PCI_DEVICE_ID_ESS_ALLEGRO: case PCI_DEVICE_ID_ESS_ALLEGRO_1: case PCI_DEVICE_ID_ESS_CANYON3D_2LE: case PCI_DEVICE_ID_ESS_CANYON3D_2: chip->allegro_flag = 1; break; } chip->card = card; chip->pci = pci; chip->irq = -1; INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume); card->private_free = snd_m3_free; chip->external_amp = enable_amp; if (amp_gpio >= 0 && amp_gpio <= 0x0f) chip->amp_gpio = amp_gpio; else { quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list); if (quirk) { dev_info(card->dev, "set amp-gpio for '%s'\n", snd_pci_quirk_name(quirk)); chip->amp_gpio = quirk->value; } else if (chip->allegro_flag) chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; else /* presumably this is for all 'maestro3's.. */ chip->amp_gpio = GPO_EXT_AMP_M3; } quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list); if (quirk) { dev_info(card->dev, "enabled irda workaround for '%s'\n", snd_pci_quirk_name(quirk)); chip->irda_workaround = 1; } quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list); if (quirk) chip->hv_config = quirk->value; if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list)) chip->is_omnibook = 1; chip->num_substreams = NR_DSPS; chip->substreams = devm_kcalloc(&pci->dev, chip->num_substreams, sizeof(struct m3_dma), GFP_KERNEL); if (!chip->substreams) return -ENOMEM; err = request_firmware(&chip->assp_kernel_image, "ess/maestro3_assp_kernel.fw", &pci->dev); if (err < 0) return err; err = request_firmware(&chip->assp_minisrc_image, "ess/maestro3_assp_minisrc.fw", &pci->dev); if (err < 0) return err; err = pci_request_regions(pci, card->driver); if (err < 0) return err; chip->iobase = pci_resource_start(pci, 0); /* just to be sure */ pci_set_master(pci); snd_m3_chip_init(chip); snd_m3_assp_halt(chip); snd_m3_ac97_reset(chip); snd_m3_amp_enable(chip, 1); snd_m3_hv_init(chip); if (devm_request_irq(&pci->dev, pci->irq, snd_m3_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -ENOMEM; } chip->irq = pci->irq; card->sync_irq = chip->irq; #ifdef CONFIG_PM_SLEEP chip->suspend_mem = vmalloc(array_size(sizeof(u16), REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH)); if (chip->suspend_mem == NULL) dev_warn(card->dev, "can't allocate apm buffer\n"); #endif err = snd_m3_mixer(chip); if (err < 0) return err; for (i = 0; i < chip->num_substreams; i++) { struct m3_dma *s = &chip->substreams[i]; err = snd_m3_assp_client_init(chip, s, i); if (err < 0) return err; } err = snd_m3_pcm(chip, 0); if (err < 0) return err; #ifdef CONFIG_SND_MAESTRO3_INPUT if (chip->hv_config & HV_CTRL_ENABLE) { err = snd_m3_input_register(chip); if (err) dev_warn(card->dev, "Input device registration failed with error %i", err); } #endif snd_m3_enable_ints(chip); snd_m3_assp_continue(chip); return 0; } /* */ static int __snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct snd_m3 *chip; int err; /* don't pick up modems */ if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) return -ENODEV; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; switch (pci->device) { case PCI_DEVICE_ID_ESS_ALLEGRO: case PCI_DEVICE_ID_ESS_ALLEGRO_1: strcpy(card->driver, "Allegro"); break; case PCI_DEVICE_ID_ESS_CANYON3D_2LE: case PCI_DEVICE_ID_ESS_CANYON3D_2: strcpy(card->driver, "Canyon3D-2"); break; default: strcpy(card->driver, "Maestro3"); break; } err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev]); if (err < 0) return err; sprintf(card->shortname, "ESS %s PCI", card->driver); sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, chip->iobase, chip->irq); err = snd_card_register(card); if (err < 0) return err; #if 0 /* TODO: not supported yet */ /* TODO enable MIDI IRQ and I/O */ err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, chip->iobase + MPU401_DATA_PORT, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi); if (err < 0) dev_warn(card->dev, "no MIDI support.\n"); #endif pci_set_drvdata(pci, card); dev++; return 0; } static int snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_m3_probe(pci, pci_id)); } static struct pci_driver m3_driver = { .name = KBUILD_MODNAME, .id_table = snd_m3_ids, .probe = snd_m3_probe, .driver = { .pm = M3_PM_OPS, }, }; module_pci_driver(m3_driver);
linux-master
sound/pci/maestro3.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Universal routines for AK4531 codec */ #include <linux/delay.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/mutex.h> #include <linux/module.h> #include <sound/core.h> #include <sound/ak4531_codec.h> #include <sound/tlv.h> /* MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("Universal routines for AK4531 codec"); MODULE_LICENSE("GPL"); */ static void snd_ak4531_proc_init(struct snd_card *card, struct snd_ak4531 *ak4531); /* * */ #if 0 static void snd_ak4531_dump(struct snd_ak4531 *ak4531) { int idx; for (idx = 0; idx < 0x19; idx++) printk(KERN_DEBUG "ak4531 0x%x: 0x%x\n", idx, ak4531->regs[idx]); } #endif /* * */ #define AK4531_SINGLE(xname, xindex, reg, shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_ak4531_info_single, \ .get = snd_ak4531_get_single, .put = snd_ak4531_put_single, \ .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22) } #define AK4531_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ .name = xname, .index = xindex, \ .info = snd_ak4531_info_single, \ .get = snd_ak4531_get_single, .put = snd_ak4531_put_single, \ .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22), \ .tlv = { .p = (xtlv) } } static int snd_ak4531_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 24) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_ak4531_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 16) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int val; mutex_lock(&ak4531->reg_mutex); val = (ak4531->regs[reg] >> shift) & mask; mutex_unlock(&ak4531->reg_mutex); if (invert) { val = mask - val; } ucontrol->value.integer.value[0] = val; return 0; } static int snd_ak4531_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 16) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int change; int val; val = ucontrol->value.integer.value[0] & mask; if (invert) { val = mask - val; } val <<= shift; mutex_lock(&ak4531->reg_mutex); val = (ak4531->regs[reg] & ~(mask << shift)) | val; change = val != ak4531->regs[reg]; ak4531->write(ak4531, reg, ak4531->regs[reg] = val); mutex_unlock(&ak4531->reg_mutex); return change; } #define AK4531_DOUBLE(xname, xindex, left_reg, right_reg, left_shift, right_shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_ak4531_info_double, \ .get = snd_ak4531_get_double, .put = snd_ak4531_put_double, \ .private_value = left_reg | (right_reg << 8) | (left_shift << 16) | (right_shift << 19) | (mask << 24) | (invert << 22) } #define AK4531_DOUBLE_TLV(xname, xindex, left_reg, right_reg, left_shift, right_shift, mask, invert, xtlv) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ .name = xname, .index = xindex, \ .info = snd_ak4531_info_double, \ .get = snd_ak4531_get_double, .put = snd_ak4531_put_double, \ .private_value = left_reg | (right_reg << 8) | (left_shift << 16) | (right_shift << 19) | (mask << 24) | (invert << 22), \ .tlv = { .p = (xtlv) } } static int snd_ak4531_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 24) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_ak4531_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int left_shift = (kcontrol->private_value >> 16) & 0x07; int right_shift = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int left, right; mutex_lock(&ak4531->reg_mutex); left = (ak4531->regs[left_reg] >> left_shift) & mask; right = (ak4531->regs[right_reg] >> right_shift) & mask; mutex_unlock(&ak4531->reg_mutex); if (invert) { left = mask - left; right = mask - right; } ucontrol->value.integer.value[0] = left; ucontrol->value.integer.value[1] = right; return 0; } static int snd_ak4531_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int left_shift = (kcontrol->private_value >> 16) & 0x07; int right_shift = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int change; int left, right; left = ucontrol->value.integer.value[0] & mask; right = ucontrol->value.integer.value[1] & mask; if (invert) { left = mask - left; right = mask - right; } left <<= left_shift; right <<= right_shift; mutex_lock(&ak4531->reg_mutex); if (left_reg == right_reg) { left = (ak4531->regs[left_reg] & ~((mask << left_shift) | (mask << right_shift))) | left | right; change = left != ak4531->regs[left_reg]; ak4531->write(ak4531, left_reg, ak4531->regs[left_reg] = left); } else { left = (ak4531->regs[left_reg] & ~(mask << left_shift)) | left; right = (ak4531->regs[right_reg] & ~(mask << right_shift)) | right; change = left != ak4531->regs[left_reg] || right != ak4531->regs[right_reg]; ak4531->write(ak4531, left_reg, ak4531->regs[left_reg] = left); ak4531->write(ak4531, right_reg, ak4531->regs[right_reg] = right); } mutex_unlock(&ak4531->reg_mutex); return change; } #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_ak4531_info_input_sw, \ .get = snd_ak4531_get_input_sw, .put = snd_ak4531_put_input_sw, \ .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) } static int snd_ak4531_info_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; uinfo->count = 4; uinfo->value.integer.min = 0; uinfo->value.integer.max = 1; return 0; } static int snd_ak4531_get_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int reg1 = kcontrol->private_value & 0xff; int reg2 = (kcontrol->private_value >> 8) & 0xff; int left_shift = (kcontrol->private_value >> 16) & 0x0f; int right_shift = (kcontrol->private_value >> 24) & 0x0f; mutex_lock(&ak4531->reg_mutex); ucontrol->value.integer.value[0] = (ak4531->regs[reg1] >> left_shift) & 1; ucontrol->value.integer.value[1] = (ak4531->regs[reg2] >> left_shift) & 1; ucontrol->value.integer.value[2] = (ak4531->regs[reg1] >> right_shift) & 1; ucontrol->value.integer.value[3] = (ak4531->regs[reg2] >> right_shift) & 1; mutex_unlock(&ak4531->reg_mutex); return 0; } static int snd_ak4531_put_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ak4531 *ak4531 = snd_kcontrol_chip(kcontrol); int reg1 = kcontrol->private_value & 0xff; int reg2 = (kcontrol->private_value >> 8) & 0xff; int left_shift = (kcontrol->private_value >> 16) & 0x0f; int right_shift = (kcontrol->private_value >> 24) & 0x0f; int change; int val1, val2; mutex_lock(&ak4531->reg_mutex); val1 = ak4531->regs[reg1] & ~((1 << left_shift) | (1 << right_shift)); val2 = ak4531->regs[reg2] & ~((1 << left_shift) | (1 << right_shift)); val1 |= (ucontrol->value.integer.value[0] & 1) << left_shift; val2 |= (ucontrol->value.integer.value[1] & 1) << left_shift; val1 |= (ucontrol->value.integer.value[2] & 1) << right_shift; val2 |= (ucontrol->value.integer.value[3] & 1) << right_shift; change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; ak4531->write(ak4531, reg1, ak4531->regs[reg1] = val1); ak4531->write(ak4531, reg2, ak4531->regs[reg2] = val2); mutex_unlock(&ak4531->reg_mutex); return change; } static const DECLARE_TLV_DB_SCALE(db_scale_master, -6200, 200, 0); static const DECLARE_TLV_DB_SCALE(db_scale_mono, -2800, 400, 0); static const DECLARE_TLV_DB_SCALE(db_scale_input, -5000, 200, 0); static const struct snd_kcontrol_new snd_ak4531_controls[] = { AK4531_DOUBLE_TLV("Master Playback Switch", 0, AK4531_LMASTER, AK4531_RMASTER, 7, 7, 1, 1, db_scale_master), AK4531_DOUBLE("Master Playback Volume", 0, AK4531_LMASTER, AK4531_RMASTER, 0, 0, 0x1f, 1), AK4531_SINGLE_TLV("Master Mono Playback Switch", 0, AK4531_MONO_OUT, 7, 1, 1, db_scale_mono), AK4531_SINGLE("Master Mono Playback Volume", 0, AK4531_MONO_OUT, 0, 0x07, 1), AK4531_DOUBLE("PCM Switch", 0, AK4531_LVOICE, AK4531_RVOICE, 7, 7, 1, 1), AK4531_DOUBLE_TLV("PCM Volume", 0, AK4531_LVOICE, AK4531_RVOICE, 0, 0, 0x1f, 1, db_scale_input), AK4531_DOUBLE("PCM Playback Switch", 0, AK4531_OUT_SW2, AK4531_OUT_SW2, 3, 2, 1, 0), AK4531_DOUBLE("PCM Capture Switch", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 2, 2, 1, 0), AK4531_DOUBLE("PCM Switch", 1, AK4531_LFM, AK4531_RFM, 7, 7, 1, 1), AK4531_DOUBLE_TLV("PCM Volume", 1, AK4531_LFM, AK4531_RFM, 0, 0, 0x1f, 1, db_scale_input), AK4531_DOUBLE("PCM Playback Switch", 1, AK4531_OUT_SW1, AK4531_OUT_SW1, 6, 5, 1, 0), AK4531_INPUT_SW("PCM Capture Route", 1, AK4531_LIN_SW1, AK4531_RIN_SW1, 6, 5), AK4531_DOUBLE("CD Switch", 0, AK4531_LCD, AK4531_RCD, 7, 7, 1, 1), AK4531_DOUBLE_TLV("CD Volume", 0, AK4531_LCD, AK4531_RCD, 0, 0, 0x1f, 1, db_scale_input), AK4531_DOUBLE("CD Playback Switch", 0, AK4531_OUT_SW1, AK4531_OUT_SW1, 2, 1, 1, 0), AK4531_INPUT_SW("CD Capture Route", 0, AK4531_LIN_SW1, AK4531_RIN_SW1, 2, 1), AK4531_DOUBLE("Line Switch", 0, AK4531_LLINE, AK4531_RLINE, 7, 7, 1, 1), AK4531_DOUBLE_TLV("Line Volume", 0, AK4531_LLINE, AK4531_RLINE, 0, 0, 0x1f, 1, db_scale_input), AK4531_DOUBLE("Line Playback Switch", 0, AK4531_OUT_SW1, AK4531_OUT_SW1, 4, 3, 1, 0), AK4531_INPUT_SW("Line Capture Route", 0, AK4531_LIN_SW1, AK4531_RIN_SW1, 4, 3), AK4531_DOUBLE("Aux Switch", 0, AK4531_LAUXA, AK4531_RAUXA, 7, 7, 1, 1), AK4531_DOUBLE_TLV("Aux Volume", 0, AK4531_LAUXA, AK4531_RAUXA, 0, 0, 0x1f, 1, db_scale_input), AK4531_DOUBLE("Aux Playback Switch", 0, AK4531_OUT_SW2, AK4531_OUT_SW2, 5, 4, 1, 0), AK4531_INPUT_SW("Aux Capture Route", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 4, 3), AK4531_SINGLE("Mono Switch", 0, AK4531_MONO1, 7, 1, 1), AK4531_SINGLE_TLV("Mono Volume", 0, AK4531_MONO1, 0, 0x1f, 1, db_scale_input), AK4531_SINGLE("Mono Playback Switch", 0, AK4531_OUT_SW2, 0, 1, 0), AK4531_DOUBLE("Mono Capture Switch", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 0, 0, 1, 0), AK4531_SINGLE("Mono Switch", 1, AK4531_MONO2, 7, 1, 1), AK4531_SINGLE_TLV("Mono Volume", 1, AK4531_MONO2, 0, 0x1f, 1, db_scale_input), AK4531_SINGLE("Mono Playback Switch", 1, AK4531_OUT_SW2, 1, 1, 0), AK4531_DOUBLE("Mono Capture Switch", 1, AK4531_LIN_SW2, AK4531_RIN_SW2, 1, 1, 1, 0), AK4531_SINGLE_TLV("Mic Volume", 0, AK4531_MIC, 0, 0x1f, 1, db_scale_input), AK4531_SINGLE("Mic Switch", 0, AK4531_MIC, 7, 1, 1), AK4531_SINGLE("Mic Playback Switch", 0, AK4531_OUT_SW1, 0, 1, 0), AK4531_DOUBLE("Mic Capture Switch", 0, AK4531_LIN_SW1, AK4531_RIN_SW1, 0, 0, 1, 0), AK4531_DOUBLE("Mic Bypass Capture Switch", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 7, 7, 1, 0), AK4531_DOUBLE("Mono1 Bypass Capture Switch", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 6, 6, 1, 0), AK4531_DOUBLE("Mono2 Bypass Capture Switch", 0, AK4531_LIN_SW2, AK4531_RIN_SW2, 5, 5, 1, 0), AK4531_SINGLE("AD Input Select", 0, AK4531_AD_IN, 0, 1, 0), AK4531_SINGLE("Mic Boost (+30dB)", 0, AK4531_MIC_GAIN, 0, 1, 0) }; static int snd_ak4531_free(struct snd_ak4531 *ak4531) { if (ak4531) { if (ak4531->private_free) ak4531->private_free(ak4531); kfree(ak4531); } return 0; } static int snd_ak4531_dev_free(struct snd_device *device) { struct snd_ak4531 *ak4531 = device->device_data; return snd_ak4531_free(ak4531); } static const u8 snd_ak4531_initial_map[0x19 + 1] = { 0x9f, /* 00: Master Volume Lch */ 0x9f, /* 01: Master Volume Rch */ 0x9f, /* 02: Voice Volume Lch */ 0x9f, /* 03: Voice Volume Rch */ 0x9f, /* 04: FM Volume Lch */ 0x9f, /* 05: FM Volume Rch */ 0x9f, /* 06: CD Audio Volume Lch */ 0x9f, /* 07: CD Audio Volume Rch */ 0x9f, /* 08: Line Volume Lch */ 0x9f, /* 09: Line Volume Rch */ 0x9f, /* 0a: Aux Volume Lch */ 0x9f, /* 0b: Aux Volume Rch */ 0x9f, /* 0c: Mono1 Volume */ 0x9f, /* 0d: Mono2 Volume */ 0x9f, /* 0e: Mic Volume */ 0x87, /* 0f: Mono-out Volume */ 0x00, /* 10: Output Mixer SW1 */ 0x00, /* 11: Output Mixer SW2 */ 0x00, /* 12: Lch Input Mixer SW1 */ 0x00, /* 13: Rch Input Mixer SW1 */ 0x00, /* 14: Lch Input Mixer SW2 */ 0x00, /* 15: Rch Input Mixer SW2 */ 0x00, /* 16: Reset & Power Down */ 0x00, /* 17: Clock Select */ 0x00, /* 18: AD Input Select */ 0x01 /* 19: Mic Amp Setup */ }; int snd_ak4531_mixer(struct snd_card *card, struct snd_ak4531 *_ak4531, struct snd_ak4531 **rak4531) { unsigned int idx; int err; struct snd_ak4531 *ak4531; static const struct snd_device_ops ops = { .dev_free = snd_ak4531_dev_free, }; if (snd_BUG_ON(!card || !_ak4531)) return -EINVAL; if (rak4531) *rak4531 = NULL; ak4531 = kzalloc(sizeof(*ak4531), GFP_KERNEL); if (ak4531 == NULL) return -ENOMEM; *ak4531 = *_ak4531; mutex_init(&ak4531->reg_mutex); err = snd_component_add(card, "AK4531"); if (err < 0) { snd_ak4531_free(ak4531); return err; } strcpy(card->mixername, "Asahi Kasei AK4531"); ak4531->write(ak4531, AK4531_RESET, 0x03); /* no RST, PD */ udelay(100); ak4531->write(ak4531, AK4531_CLOCK, 0x00); /* CODEC ADC and CODEC DAC use {LR,B}CLK2 and run off LRCLK2 PLL */ for (idx = 0; idx <= 0x19; idx++) { if (idx == AK4531_RESET || idx == AK4531_CLOCK) continue; ak4531->write(ak4531, idx, ak4531->regs[idx] = snd_ak4531_initial_map[idx]); /* recording source is mixer */ } for (idx = 0; idx < ARRAY_SIZE(snd_ak4531_controls); idx++) { err = snd_ctl_add(card, snd_ctl_new1(&snd_ak4531_controls[idx], ak4531)); if (err < 0) { snd_ak4531_free(ak4531); return err; } } snd_ak4531_proc_init(card, ak4531); err = snd_device_new(card, SNDRV_DEV_CODEC, ak4531, &ops); if (err < 0) { snd_ak4531_free(ak4531); return err; } #if 0 snd_ak4531_dump(ak4531); #endif if (rak4531) *rak4531 = ak4531; return 0; } /* * power management */ #ifdef CONFIG_PM void snd_ak4531_suspend(struct snd_ak4531 *ak4531) { /* mute */ ak4531->write(ak4531, AK4531_LMASTER, 0x9f); ak4531->write(ak4531, AK4531_RMASTER, 0x9f); /* powerdown */ ak4531->write(ak4531, AK4531_RESET, 0x01); } void snd_ak4531_resume(struct snd_ak4531 *ak4531) { int idx; /* initialize */ ak4531->write(ak4531, AK4531_RESET, 0x03); udelay(100); ak4531->write(ak4531, AK4531_CLOCK, 0x00); /* restore mixer registers */ for (idx = 0; idx <= 0x19; idx++) { if (idx == AK4531_RESET || idx == AK4531_CLOCK) continue; ak4531->write(ak4531, idx, ak4531->regs[idx]); } } #endif /* * /proc interface */ static void snd_ak4531_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_ak4531 *ak4531 = entry->private_data; snd_iprintf(buffer, "Asahi Kasei AK4531\n\n"); snd_iprintf(buffer, "Recording source : %s\n" "MIC gain : %s\n", ak4531->regs[AK4531_AD_IN] & 1 ? "external" : "mixer", ak4531->regs[AK4531_MIC_GAIN] & 1 ? "+30dB" : "+0dB"); } static void snd_ak4531_proc_init(struct snd_card *card, struct snd_ak4531 *ak4531) { snd_card_ro_proc_new(card, "ak4531", ak4531, snd_ak4531_proc_read); }
linux-master
sound/pci/ak4531_codec.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for C-Media CMI8338 and 8738 PCI soundcards. * Copyright (c) 2000 by Takashi Iwai <[email protected]> */ /* Does not work. Warning may block system in capture mode */ /* #define USE_VAR48KRATE */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/mutex.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/rawmidi.h> #include <sound/mpu401.h> #include <sound/opl3.h> #include <sound/sb.h> #include <sound/asoundef.h> #include <sound/initval.h> MODULE_AUTHOR("Takashi Iwai <[email protected]>"); MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1}; static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; #ifdef SUPPORT_JOYSTICK static int joystick_port[SNDRV_CARDS]; #endif module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); module_param_hw_array(mpu_port, long, ioport, NULL, 0444); MODULE_PARM_DESC(mpu_port, "MPU-401 port."); module_param_hw_array(fm_port, long, ioport, NULL, 0444); MODULE_PARM_DESC(fm_port, "FM port."); module_param_array(soft_ac3, bool, NULL, 0444); MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only)."); #ifdef SUPPORT_JOYSTICK module_param_hw_array(joystick_port, int, ioport, NULL, 0444); MODULE_PARM_DESC(joystick_port, "Joystick port address."); #endif /* * CM8x38 registers definition */ #define CM_REG_FUNCTRL0 0x00 #define CM_RST_CH1 0x00080000 #define CM_RST_CH0 0x00040000 #define CM_CHEN1 0x00020000 /* ch1: enable */ #define CM_CHEN0 0x00010000 /* ch0: enable */ #define CM_PAUSE1 0x00000008 /* ch1: pause */ #define CM_PAUSE0 0x00000004 /* ch0: pause */ #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ #define CM_REG_FUNCTRL1 0x04 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */ #define CM_DSFC_SHIFT 13 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */ #define CM_ASFC_SHIFT 10 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */ #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ #define CM_BREQ 0x00000010 /* bus master enabled */ #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ #define CM_UART_EN 0x00000004 /* legacy UART */ #define CM_JYSTK_EN 0x00000002 /* legacy joystick */ #define CM_ZVPORT 0x00000001 /* ZVPORT */ #define CM_REG_CHFORMAT 0x08 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */ #define CM_CHB3D 0x20000000 /* 4 channels */ #define CM_CHIP_MASK1 0x1f000000 #define CM_CHIP_037 0x01000000 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */ #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */ #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */ #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ #define CM_ADCBITLEN_MASK 0x0000C000 #define CM_ADCBITLEN_16 0x00000000 #define CM_ADCBITLEN_15 0x00004000 #define CM_ADCBITLEN_14 0x00008000 #define CM_ADCBITLEN_13 0x0000C000 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */ #define CM_ADCDACLEN_060 0x00000000 #define CM_ADCDACLEN_066 0x00001000 #define CM_ADCDACLEN_130 0x00002000 #define CM_ADCDACLEN_280 0x00003000 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */ #define CM_ADCDLEN_ORIGINAL 0x00000000 #define CM_ADCDLEN_EXTRA 0x00001000 #define CM_ADCDLEN_24K 0x00002000 #define CM_ADCDLEN_WEIGHT 0x00003000 #define CM_CH1_SRATE_176K 0x00000800 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */ #define CM_CH1_SRATE_88K 0x00000400 #define CM_CH0_SRATE_176K 0x00000200 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */ #define CM_CH0_SRATE_88K 0x00000100 #define CM_CH0_SRATE_128K 0x00000300 #define CM_CH0_SRATE_MASK 0x00000300 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */ #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */ #define CM_SPDLOCKED 0x00000010 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */ #define CM_CH1FMT_SHIFT 2 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */ #define CM_CH0FMT_SHIFT 0 #define CM_REG_INT_HLDCLR 0x0C #define CM_CHIP_MASK2 0xff000000 #define CM_CHIP_8768 0x20000000 #define CM_CHIP_055 0x08000000 #define CM_CHIP_039 0x04000000 #define CM_CHIP_039_6CH 0x01000000 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */ #define CM_TDMA_INT_EN 0x00040000 #define CM_CH1_INT_EN 0x00020000 #define CM_CH0_INT_EN 0x00010000 #define CM_REG_INT_STATUS 0x10 #define CM_INTR 0x80000000 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ #define CM_UARTINT 0x00010000 #define CM_LTDMAINT 0x00008000 #define CM_HTDMAINT 0x00004000 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ #define CM_CH1BUSY 0x00000008 #define CM_CH0BUSY 0x00000004 #define CM_CHINT1 0x00000002 #define CM_CHINT0 0x00000001 #define CM_REG_LEGACY_CTRL 0x14 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */ #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ #define CM_VMPU_330 0x00000000 #define CM_VMPU_320 0x20000000 #define CM_VMPU_310 0x40000000 #define CM_VMPU_300 0x60000000 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */ #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ #define CM_VSBSEL_220 0x00000000 #define CM_VSBSEL_240 0x04000000 #define CM_VSBSEL_260 0x08000000 #define CM_VSBSEL_280 0x0C000000 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ #define CM_FMSEL_388 0x00000000 #define CM_FMSEL_3C8 0x01000000 #define CM_FMSEL_3E0 0x02000000 #define CM_FMSEL_3E8 0x03000000 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */ #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */ #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */ #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */ #define CM_C_EECS 0x00040000 #define CM_C_EEDI46 0x00020000 #define CM_C_EECK46 0x00010000 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ #define CM_CENTR2LIN 0x00004000 /* line-in as center out */ #define CM_BASE2LIN 0x00002000 /* line-in as bass out */ #define CM_EXBASEN 0x00001000 /* external bass input enable */ #define CM_REG_MISC_CTRL 0x18 #define CM_PWD 0x80000000 /* power down */ #define CM_RESET 0x40000000 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */ #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */ #define CM_TXVX 0x08000000 /* model 037? */ #define CM_N4SPK3D 0x04000000 /* copy front to rear */ #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ #define CM_SPDIF48K 0x01000000 /* write */ #define CM_SPATUS48K 0x01000000 /* read */ #define CM_ENDBDAC 0x00800000 /* enable double dac */ #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */ #define CM_FM_EN 0x00080000 /* enable legacy FM */ #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */ #define CM_VIDWPDSB 0x00010000 /* model 037? */ #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */ #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */ #define CM_VIDWPPRT 0x00002000 /* model 037? */ #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */ #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */ #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ #define CM_ENCENTER 0x00000080 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */ #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */ #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */ #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */ #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */ #define CM_UPDDMA_2048 0x00000000 #define CM_UPDDMA_1024 0x00000004 #define CM_UPDDMA_512 0x00000008 #define CM_UPDDMA_256 0x0000000C #define CM_TWAIT_MASK 0x00000003 /* model 037 */ #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */ #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */ #define CM_REG_TDMA_POSITION 0x1C #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */ #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */ /* byte */ #define CM_REG_MIXER0 0x20 #define CM_REG_SBVR 0x20 /* write: sb16 version */ #define CM_REG_DEV 0x20 /* read: hardware device version */ #define CM_REG_MIXER21 0x21 #define CM_UNKNOWN_21_MASK 0x78 /* ? */ #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */ #define CM_PROINV 0x02 /* SBPro left/right channel switching */ #define CM_X_SB16 0x01 /* SB16 compatible */ #define CM_REG_SB16_DATA 0x22 #define CM_REG_SB16_ADDR 0x23 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ #define CM_REG_MIXER1 0x24 #define CM_FMMUTE 0x80 /* mute FM */ #define CM_FMMUTE_SHIFT 7 #define CM_WSMUTE 0x40 /* mute PCM */ #define CM_WSMUTE_SHIFT 6 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */ #define CM_REAR2LIN_SHIFT 5 #define CM_REAR2FRONT 0x10 /* exchange rear/front */ #define CM_REAR2FRONT_SHIFT 4 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ #define CM_WAVEINL_SHIFT 3 #define CM_WAVEINR 0x04 /* digical wave rec. right */ #define CM_WAVEINR_SHIFT 2 #define CM_X3DEN 0x02 /* 3D surround enable */ #define CM_X3DEN_SHIFT 1 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ #define CM_CDPLAY_SHIFT 0 #define CM_REG_MIXER2 0x25 #define CM_RAUXREN 0x80 /* AUX right capture */ #define CM_RAUXREN_SHIFT 7 #define CM_RAUXLEN 0x40 /* AUX left capture */ #define CM_RAUXLEN_SHIFT 6 #define CM_VAUXRM 0x20 /* AUX right mute */ #define CM_VAUXRM_SHIFT 5 #define CM_VAUXLM 0x10 /* AUX left mute */ #define CM_VAUXLM_SHIFT 4 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ #define CM_VADMIC_SHIFT 1 #define CM_MICGAINZ 0x01 /* mic boost */ #define CM_MICGAINZ_SHIFT 0 #define CM_REG_AUX_VOL 0x26 #define CM_VAUXL_MASK 0xf0 #define CM_VAUXR_MASK 0x0f #define CM_REG_MISC 0x27 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */ #define CM_XGPO1 0x20 // #define CM_XGPBIO 0x04 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ #define CM_SPDVALID 0x02 /* spdif input valid check */ #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */ #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ /* * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 * or identical with AC97 codec? */ #define CM_REG_EXTERN_CODEC CM_REG_AC97 /* * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) */ #define CM_REG_MPU_PCI 0x40 /* * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) */ #define CM_REG_FM_PCI 0x50 /* * access from SB-mixer port */ #define CM_REG_EXTENT_IND 0xf0 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ #define CM_VPHONE_SHIFT 5 #define CM_VPHOM 0x10 /* Phone mute control */ #define CM_VSPKM 0x08 /* Speaker mute control, default high */ #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ #define CM_VADMIC3 0x01 /* Mic record boost */ /* * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL * unit (readonly?). */ #define CM_REG_PLL 0xf8 /* * extended registers */ #define CM_REG_CH0_FRAME1 0x80 /* write: base address */ #define CM_REG_CH0_FRAME2 0x84 /* read: current address */ #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ #define CM_REG_EXT_MISC 0x90 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */ #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */ #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */ #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */ #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */ #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */ #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */ #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */ /* * size of i/o region */ #define CM_EXTENT_CODEC 0x100 #define CM_EXTENT_MIDI 0x2 #define CM_EXTENT_SYNTH 0x4 /* * channels for playback / capture */ #define CM_CH_PLAY 0 #define CM_CH_CAPT 1 /* * flags to check device open/close */ #define CM_OPEN_NONE 0 #define CM_OPEN_CH_MASK 0x01 #define CM_OPEN_DAC 0x10 #define CM_OPEN_ADC 0x20 #define CM_OPEN_SPDIF 0x40 #define CM_OPEN_MCHAN 0x80 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) #if CM_CH_PLAY == 1 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K #define CM_PLAYBACK_SPDF CM_SPDF_1 #define CM_CAPTURE_SPDF CM_SPDF_0 #else #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K #define CM_PLAYBACK_SPDF CM_SPDF_0 #define CM_CAPTURE_SPDF CM_SPDF_1 #endif /* * driver data */ struct cmipci_pcm { struct snd_pcm_substream *substream; u8 running; /* dac/adc running? */ u8 fmt; /* format bits */ u8 is_dac; u8 needs_silencing; unsigned int dma_size; /* in frames */ unsigned int shift; unsigned int ch; /* channel (0/1) */ unsigned int offset; /* physical address of the buffer */ }; /* mixer elements toggled/resumed during ac3 playback */ struct cmipci_mixer_auto_switches { const char *name; /* switch to toggle */ int toggle_on; /* value to change when ac3 mode */ }; static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { {"PCM Playback Switch", 0}, {"IEC958 Output Switch", 1}, {"IEC958 Mix Analog", 0}, // {"IEC958 Out To DAC", 1}, // no longer used {"IEC958 Loop", 0}, }; #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) struct cmipci { struct snd_card *card; struct pci_dev *pci; unsigned int device; /* device ID */ int irq; unsigned long iobase; unsigned int ctrl; /* FUNCTRL0 current value */ struct snd_pcm *pcm; /* DAC/ADC PCM */ struct snd_pcm *pcm2; /* 2nd DAC */ struct snd_pcm *pcm_spdif; /* SPDIF */ int chip_version; int max_channels; unsigned int can_ac3_sw: 1; unsigned int can_ac3_hw: 1; unsigned int can_multi_ch: 1; unsigned int can_96k: 1; /* samplerate above 48k */ unsigned int do_soft_ac3: 1; unsigned int spdif_playback_avail: 1; /* spdif ready? */ unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ int spdif_counter; /* for software AC3 */ unsigned int dig_status; unsigned int dig_pcm_status; struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ int opened[2]; /* open mode */ struct mutex open_mutex; unsigned int mixer_insensitive: 1; struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; int mixer_res_status[CM_SAVED_MIXERS]; struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ /* external MIDI */ struct snd_rawmidi *rmidi; #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif spinlock_t reg_lock; #ifdef CONFIG_PM_SLEEP unsigned int saved_regs[0x20]; unsigned char saved_mixers[0x20]; #endif }; /* read/write operations for dword register */ static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) { outl(data, cm->iobase + cmd); } static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) { return inl(cm->iobase + cmd); } /* read/write operations for word register */ static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) { outw(data, cm->iobase + cmd); } static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) { return inw(cm->iobase + cmd); } /* read/write operations for byte register */ static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) { outb(data, cm->iobase + cmd); } static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) { return inb(cm->iobase + cmd); } /* bit operations for dword register */ static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) { unsigned int val, oval; val = oval = inl(cm->iobase + cmd); val |= flag; if (val == oval) return 0; outl(val, cm->iobase + cmd); return 1; } static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) { unsigned int val, oval; val = oval = inl(cm->iobase + cmd); val &= ~flag; if (val == oval) return 0; outl(val, cm->iobase + cmd); return 1; } /* bit operations for byte register */ static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) { unsigned char val, oval; val = oval = inb(cm->iobase + cmd); val |= flag; if (val == oval) return 0; outb(val, cm->iobase + cmd); return 1; } static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) { unsigned char val, oval; val = oval = inb(cm->iobase + cmd); val &= ~flag; if (val == oval) return 0; outb(val, cm->iobase + cmd); return 1; } /* * PCM interface */ /* * calculate frequency */ static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; static unsigned int snd_cmipci_rate_freq(unsigned int rate) { unsigned int i; for (i = 0; i < ARRAY_SIZE(rates); i++) { if (rates[i] == rate) return i; } snd_BUG(); return 0; } #ifdef USE_VAR48KRATE /* * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) * does it this way .. maybe not. Never get any information from C-Media about * that <[email protected]>. */ static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) { unsigned int delta, tolerance; int xm, xn, xr; for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) rate <<= 1; *n = -1; if (*r > 0xff) goto out; tolerance = rate*CM_TOLERANCE_RATE; for (xn = (1+2); xn < (0x1f+2); xn++) { for (xm = (1+2); xm < (0xff+2); xm++) { xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; if (xr < rate) delta = rate - xr; else delta = xr - rate; /* * If we found one, remember this, * and try to find a closer one */ if (delta < tolerance) { tolerance = delta; *m = xm - 2; *n = xn - 2; } } } out: return (*n > -1); } /* * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen * at the register CM_REG_FUNCTRL1 (0x04). * Problem: other ways are also possible (any information about that?) */ static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) { unsigned int reg = CM_REG_PLL + slot; /* * Guess that this programs at reg. 0x04 the pos 15:13/12:10 * for DSFC/ASFC (000 up to 111). */ /* FIXME: Init (Do we've to set an other register first before programming?) */ /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ snd_cmipci_write_b(cm, reg, rate>>8); snd_cmipci_write_b(cm, reg, rate&0xff); /* FIXME: Setup (Do we've to set an other register first to enable this?) */ } #endif /* USE_VAR48KRATE */ static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct cmipci *cm = snd_pcm_substream_chip(substream); if (params_channels(hw_params) > 2) { mutex_lock(&cm->open_mutex); if (cm->opened[CM_CH_PLAY]) { mutex_unlock(&cm->open_mutex); return -EBUSY; } /* reserve the channel A */ cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; mutex_unlock(&cm->open_mutex); } return 0; } static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) { int reset = CM_RST_CH0 << (cm->channel[ch].ch); snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); udelay(10); } /* */ static const unsigned int hw_channels[] = {1, 2, 4, 6, 8}; static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { .count = 3, .list = hw_channels, .mask = 0, }; static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { .count = 4, .list = hw_channels, .mask = 0, }; static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { .count = 5, .list = hw_channels, .mask = 0, }; static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) { if (channels > 2) { if (!cm->can_multi_ch || !rec->ch) return -EINVAL; if (rec->fmt != 0x03) /* stereo 16bit only */ return -EINVAL; } if (cm->can_multi_ch) { spin_lock_irq(&cm->reg_lock); if (channels > 2) { snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); } else { snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); } if (channels == 8) snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); else snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); if (channels == 6) { snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); } else { snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); } if (channels == 4) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); else snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); spin_unlock_irq(&cm->reg_lock); } return 0; } /* * prepare playback/capture channel * channel to be used must have been set in rec->ch. */ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, struct snd_pcm_substream *substream) { unsigned int reg, freq, freq_ext, val; unsigned int period_size; struct snd_pcm_runtime *runtime = substream->runtime; rec->fmt = 0; rec->shift = 0; if (snd_pcm_format_width(runtime->format) >= 16) { rec->fmt |= 0x02; if (snd_pcm_format_width(runtime->format) > 16) rec->shift++; /* 24/32bit */ } if (runtime->channels > 1) rec->fmt |= 0x01; if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { dev_dbg(cm->card->dev, "cannot set dac channels\n"); return -EINVAL; } rec->offset = runtime->dma_addr; /* buffer and period sizes in frame */ rec->dma_size = runtime->buffer_size << rec->shift; period_size = runtime->period_size << rec->shift; if (runtime->channels > 2) { /* multi-channels */ rec->dma_size = (rec->dma_size * runtime->channels) / 2; period_size = (period_size * runtime->channels) / 2; } spin_lock_irq(&cm->reg_lock); /* set buffer address */ reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; snd_cmipci_write(cm, reg, rec->offset); /* program sample counts */ reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; snd_cmipci_write_w(cm, reg, rec->dma_size - 1); snd_cmipci_write_w(cm, reg + 2, period_size - 1); /* set adc/dac flag */ val = rec->ch ? CM_CHADC1 : CM_CHADC0; if (rec->is_dac) cm->ctrl &= ~val; else cm->ctrl |= val; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */ /* set sample rate */ freq = 0; freq_ext = 0; if (runtime->rate > 48000) switch (runtime->rate) { case 88200: freq_ext = CM_CH0_SRATE_88K; break; case 96000: freq_ext = CM_CH0_SRATE_96K; break; case 128000: freq_ext = CM_CH0_SRATE_128K; break; default: snd_BUG(); break; } else freq = snd_cmipci_rate_freq(runtime->rate); val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); if (rec->ch) { val &= ~CM_DSFC_MASK; val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; } else { val &= ~CM_ASFC_MASK; val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; } snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); dev_dbg(cm->card->dev, "functrl1 = %08x\n", val); /* set format */ val = snd_cmipci_read(cm, CM_REG_CHFORMAT); if (rec->ch) { val &= ~CM_CH1FMT_MASK; val |= rec->fmt << CM_CH1FMT_SHIFT; } else { val &= ~CM_CH0FMT_MASK; val |= rec->fmt << CM_CH0FMT_SHIFT; } if (cm->can_96k) { val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); val |= freq_ext << (rec->ch * 2); } snd_cmipci_write(cm, CM_REG_CHFORMAT, val); dev_dbg(cm->card->dev, "chformat = %08x\n", val); if (!rec->is_dac && cm->chip_version) { if (runtime->rate > 44100) snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); else snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); } rec->running = 0; spin_unlock_irq(&cm->reg_lock); return 0; } /* * PCM trigger/stop */ static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, int cmd) { unsigned int inthld, chen, reset, pause; int result = 0; inthld = CM_CH0_INT_EN << rec->ch; chen = CM_CHEN0 << rec->ch; reset = CM_RST_CH0 << rec->ch; pause = CM_PAUSE0 << rec->ch; spin_lock(&cm->reg_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: rec->running = 1; /* set interrupt */ snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); cm->ctrl |= chen; /* enable channel */ snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); break; case SNDRV_PCM_TRIGGER_STOP: rec->running = 0; /* disable interrupt */ snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); /* reset */ cm->ctrl &= ~chen; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); rec->needs_silencing = rec->is_dac; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_SUSPEND: cm->ctrl |= pause; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: case SNDRV_PCM_TRIGGER_RESUME: cm->ctrl &= ~pause; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); break; default: result = -EINVAL; break; } spin_unlock(&cm->reg_lock); return result; } /* * return the current pointer */ static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, struct snd_pcm_substream *substream) { size_t ptr; unsigned int reg, rem, tries; if (!rec->running) return 0; #if 1 // this seems better.. reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; for (tries = 0; tries < 3; tries++) { rem = snd_cmipci_read_w(cm, reg); if (rem < rec->dma_size) goto ok; } dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem); return SNDRV_PCM_POS_XRUN; ok: ptr = (rec->dma_size - (rem + 1)) >> rec->shift; #else reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; ptr = snd_cmipci_read(cm, reg) - rec->offset; ptr = bytes_to_frames(substream->runtime, ptr); #endif if (substream->runtime->channels > 2) ptr = (ptr * 2) / substream->runtime->channels; return ptr; } /* * playback */ static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct cmipci *cm = snd_pcm_substream_chip(substream); return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd); } static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); } /* * capture */ static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct cmipci *cm = snd_pcm_substream_chip(substream); return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd); } static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); } /* * hw preparation for spdif */ static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *chip = snd_kcontrol_chip(kcontrol); int i; spin_lock_irq(&chip->reg_lock); for (i = 0; i < 4; i++) ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *chip = snd_kcontrol_chip(kcontrol); int i, change; unsigned int val; val = 0; spin_lock_irq(&chip->reg_lock); for (i = 0; i < 4; i++) val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); change = val != chip->dig_status; chip->dig_status = val; spin_unlock_irq(&chip->reg_lock); return change; } static const struct snd_kcontrol_new snd_cmipci_spdif_default = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = snd_cmipci_spdif_default_info, .get = snd_cmipci_spdif_default_get, .put = snd_cmipci_spdif_default_put }; static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = 0xff; ucontrol->value.iec958.status[1] = 0xff; ucontrol->value.iec958.status[2] = 0xff; ucontrol->value.iec958.status[3] = 0xff; return 0; } static const struct snd_kcontrol_new snd_cmipci_spdif_mask = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), .info = snd_cmipci_spdif_mask_info, .get = snd_cmipci_spdif_mask_get, }; static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *chip = snd_kcontrol_chip(kcontrol); int i; spin_lock_irq(&chip->reg_lock); for (i = 0; i < 4; i++) ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *chip = snd_kcontrol_chip(kcontrol); int i, change; unsigned int val; val = 0; spin_lock_irq(&chip->reg_lock); for (i = 0; i < 4; i++) val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); change = val != chip->dig_pcm_status; chip->dig_pcm_status = val; spin_unlock_irq(&chip->reg_lock); return change; } static const struct snd_kcontrol_new snd_cmipci_spdif_stream = { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), .info = snd_cmipci_spdif_stream_info, .get = snd_cmipci_spdif_stream_get, .put = snd_cmipci_spdif_stream_put }; /* */ /* save mixer setting and mute for AC3 playback */ static int save_mixer_state(struct cmipci *cm) { if (! cm->mixer_insensitive) { struct snd_ctl_elem_value *val; unsigned int i; val = kmalloc(sizeof(*val), GFP_KERNEL); if (!val) return -ENOMEM; for (i = 0; i < CM_SAVED_MIXERS; i++) { struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; if (ctl) { int event; memset(val, 0, sizeof(*val)); ctl->get(ctl, val); cm->mixer_res_status[i] = val->value.integer.value[0]; val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; event = SNDRV_CTL_EVENT_MASK_INFO; if (cm->mixer_res_status[i] != val->value.integer.value[0]) { ctl->put(ctl, val); /* toggle */ event |= SNDRV_CTL_EVENT_MASK_VALUE; } ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(cm->card, event, &ctl->id); } } kfree(val); cm->mixer_insensitive = 1; } return 0; } /* restore the previously saved mixer status */ static void restore_mixer_state(struct cmipci *cm) { if (cm->mixer_insensitive) { struct snd_ctl_elem_value *val; unsigned int i; val = kmalloc(sizeof(*val), GFP_KERNEL); if (!val) return; cm->mixer_insensitive = 0; /* at first clear this; otherwise the changes will be ignored */ for (i = 0; i < CM_SAVED_MIXERS; i++) { struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; if (ctl) { int event; memset(val, 0, sizeof(*val)); ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; ctl->get(ctl, val); event = SNDRV_CTL_EVENT_MASK_INFO; if (val->value.integer.value[0] != cm->mixer_res_status[i]) { val->value.integer.value[0] = cm->mixer_res_status[i]; ctl->put(ctl, val); event |= SNDRV_CTL_EVENT_MASK_VALUE; } snd_ctl_notify(cm->card, event, &ctl->id); } } kfree(val); } } /* spinlock held! */ static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) { if (do_ac3) { /* AC3EN for 037 */ snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); /* AC3EN for 039 */ snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); if (cm->can_ac3_hw) { /* SPD24SEL for 037, 0x02 */ /* SPD24SEL for 039, 0x20, but cannot be set */ snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); } else { /* can_ac3_sw */ /* SPD32SEL for 037 & 039, 0x20 */ snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); /* set 176K sample rate to fix 033 HW bug */ if (cm->chip_version == 33) { if (rate >= 48000) { snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); } else { snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); } } } } else { snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); if (cm->can_ac3_hw) { /* chip model >= 37 */ if (snd_pcm_format_width(subs->runtime->format) > 16) { snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); } else { snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); } } else { snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); } } } static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) { int rate, err; rate = subs->runtime->rate; if (up && do_ac3) { err = save_mixer_state(cm); if (err < 0) return err; } spin_lock_irq(&cm->reg_lock); cm->spdif_playback_avail = up; if (up) { /* they are controlled via "IEC958 Output Switch" */ /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ if (cm->spdif_playback_enabled) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); setup_ac3(cm, subs, do_ac3, rate); if (rate == 48000 || rate == 96000) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); else snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); if (rate > 48000) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); else snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); } else { /* they are controlled via "IEC958 Output Switch" */ /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); setup_ac3(cm, subs, 0, 0); } spin_unlock_irq(&cm->reg_lock); return 0; } /* * preparation */ /* playback - enable spdif only on the certain condition */ static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); int rate = substream->runtime->rate; int err, do_spdif, do_ac3 = 0; do_spdif = (rate >= 44100 && rate <= 96000 && substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && substream->runtime->channels == 2); if (do_spdif && cm->can_ac3_hw) do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; err = setup_spdif_playback(cm, substream, do_spdif, do_ac3); if (err < 0) return err; return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); } /* playback (via device #2) - enable spdif always */ static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); int err, do_ac3; if (cm->can_ac3_hw) do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; else do_ac3 = 1; /* doesn't matter */ err = setup_spdif_playback(cm, substream, 1, do_ac3); if (err < 0) return err; return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); } /* * Apparently, the samples last played on channel A stay in some buffer, even * after the channel is reset, and get added to the data for the rear DACs when * playing a multichannel stream on channel B. This is likely to generate * wraparounds and thus distortions. * To avoid this, we play at least one zero sample after the actual stream has * stopped. */ static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec) { struct snd_pcm_runtime *runtime = rec->substream->runtime; unsigned int reg, val; if (rec->needs_silencing && runtime && runtime->dma_area) { /* set up a small silence buffer */ memset(runtime->dma_area, 0, PAGE_SIZE); reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16); snd_cmipci_write(cm, reg, val); /* configure for 16 bits, 2 channels, 8 kHz */ if (runtime->channels > 2) set_dac_channels(cm, rec, 2); spin_lock_irq(&cm->reg_lock); val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); val &= ~(CM_ASFC_MASK << (rec->ch * 3)); val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3); snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); val = snd_cmipci_read(cm, CM_REG_CHFORMAT); val &= ~(CM_CH0FMT_MASK << (rec->ch * 2)); val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2); if (cm->can_96k) val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); snd_cmipci_write(cm, CM_REG_CHFORMAT, val); /* start stream (we don't need interrupts) */ cm->ctrl |= CM_CHEN0 << rec->ch; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); spin_unlock_irq(&cm->reg_lock); msleep(1); /* stop and reset stream */ spin_lock_irq(&cm->reg_lock); cm->ctrl &= ~(CM_CHEN0 << rec->ch); val = CM_RST_CH0 << rec->ch; snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val); snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val); spin_unlock_irq(&cm->reg_lock); rec->needs_silencing = 0; } } static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); setup_spdif_playback(cm, substream, 0, 0); restore_mixer_state(cm); snd_cmipci_silence_hack(cm, &cm->channel[0]); return 0; } static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); snd_cmipci_silence_hack(cm, &cm->channel[1]); return 0; } /* capture */ static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); } /* capture with spdif (via device #2) */ static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); spin_lock_irq(&cm->reg_lock); snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); if (cm->can_96k) { if (substream->runtime->rate > 48000) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); else snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); } if (snd_pcm_format_width(substream->runtime->format) > 16) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); else snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); spin_unlock_irq(&cm->reg_lock); return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); } static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) { struct cmipci *cm = snd_pcm_substream_chip(subs); spin_lock_irq(&cm->reg_lock); snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); spin_unlock_irq(&cm->reg_lock); return 0; } /* * interrupt handler */ static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) { struct cmipci *cm = dev_id; unsigned int status, mask = 0; /* fastpath out, to ease interrupt sharing */ status = snd_cmipci_read(cm, CM_REG_INT_STATUS); if (!(status & CM_INTR)) return IRQ_NONE; /* acknowledge interrupt */ spin_lock(&cm->reg_lock); if (status & CM_CHINT0) mask |= CM_CH0_INT_EN; if (status & CM_CHINT1) mask |= CM_CH1_INT_EN; snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); spin_unlock(&cm->reg_lock); if (cm->rmidi && (status & CM_UARTINT)) snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); if (cm->pcm) { if ((status & CM_CHINT0) && cm->channel[0].running) snd_pcm_period_elapsed(cm->channel[0].substream); if ((status & CM_CHINT1) && cm->channel[1].running) snd_pcm_period_elapsed(cm->channel[1].substream); } return IRQ_HANDLED; } /* * h/w infos */ /* playback on channel A */ static const struct snd_pcm_hardware snd_cmipci_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, .rate_min = 5512, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* capture on channel B */ static const struct snd_pcm_hardware snd_cmipci_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, .rate_min = 5512, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* playback on channel B - stereo 16bit only? */ static const struct snd_pcm_hardware snd_cmipci_playback2 = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, .rate_min = 5512, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* spdif playback on channel A */ static const struct snd_pcm_hardware snd_cmipci_playback_spdif = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, .rate_min = 44100, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* spdif playback on channel A (32bit, IEC958 subframes) */ static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, .rate_min = 44100, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* spdif capture on channel B */ static const struct snd_pcm_hardware snd_cmipci_capture_spdif = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, .rate_min = 44100, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 88200, 96000, 128000 }; static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { .count = ARRAY_SIZE(rate_constraints), .list = rate_constraints, .mask = 0, }; /* * check device open/close */ static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) { int ch = mode & CM_OPEN_CH_MASK; /* FIXME: a file should wait until the device becomes free * when it's opened on blocking mode. however, since the current * pcm framework doesn't pass file pointer before actually opened, * we can't know whether blocking mode or not in open callback.. */ mutex_lock(&cm->open_mutex); if (cm->opened[ch]) { mutex_unlock(&cm->open_mutex); return -EBUSY; } cm->opened[ch] = mode; cm->channel[ch].substream = subs; if (! (mode & CM_OPEN_DAC)) { /* disable dual DAC mode */ cm->channel[ch].is_dac = 0; spin_lock_irq(&cm->reg_lock); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); spin_unlock_irq(&cm->reg_lock); } mutex_unlock(&cm->open_mutex); return 0; } static void close_device_check(struct cmipci *cm, int mode) { int ch = mode & CM_OPEN_CH_MASK; mutex_lock(&cm->open_mutex); if (cm->opened[ch] == mode) { if (cm->channel[ch].substream) { snd_cmipci_ch_reset(cm, ch); cm->channel[ch].running = 0; cm->channel[ch].substream = NULL; } cm->opened[ch] = 0; if (! cm->channel[ch].is_dac) { /* enable dual DAC mode again */ cm->channel[ch].is_dac = 1; spin_lock_irq(&cm->reg_lock); snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); spin_unlock_irq(&cm->reg_lock); } } mutex_unlock(&cm->open_mutex); } /* */ static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; err = open_device_check(cm, CM_OPEN_PLAYBACK, substream); if (err < 0) return err; runtime->hw = snd_cmipci_playback; if (cm->chip_version == 68) { runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } else if (cm->chip_version == 55) { err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); if (err < 0) return err; runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; runtime->hw.rate_max = 128000; } snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); cm->dig_pcm_status = cm->dig_status; return 0; } static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; err = open_device_check(cm, CM_OPEN_CAPTURE, substream); if (err < 0) return err; runtime->hw = snd_cmipci_capture; if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording runtime->hw.rate_min = 41000; runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; } else if (cm->chip_version == 55) { err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); if (err < 0) return err; runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; runtime->hw.rate_max = 128000; } snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); return 0; } static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; /* use channel B */ err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream); if (err < 0) return err; runtime->hw = snd_cmipci_playback2; mutex_lock(&cm->open_mutex); if (! cm->opened[CM_CH_PLAY]) { if (cm->can_multi_ch) { runtime->hw.channels_max = cm->max_channels; if (cm->max_channels == 4) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); else if (cm->max_channels == 6) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); else if (cm->max_channels == 8) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); } } mutex_unlock(&cm->open_mutex); if (cm->chip_version == 68) { runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } else if (cm->chip_version == 55) { err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); if (err < 0) return err; runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; runtime->hw.rate_max = 128000; } snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); return 0; } static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; /* use channel A */ err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream); if (err < 0) return err; if (cm->can_ac3_hw) { runtime->hw = snd_cmipci_playback_spdif; if (cm->chip_version >= 37) { runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); } if (cm->can_96k) { runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } } else { runtime->hw = snd_cmipci_playback_iec958_subframe; } snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); cm->dig_pcm_status = cm->dig_status; return 0; } static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; /* use channel B */ err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream); if (err < 0) return err; runtime->hw = snd_cmipci_capture_spdif; if (cm->can_96k && !(cm->chip_version == 68)) { runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); return 0; } /* */ static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); close_device_check(cm, CM_OPEN_PLAYBACK); return 0; } static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); close_device_check(cm, CM_OPEN_CAPTURE); return 0; } static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); close_device_check(cm, CM_OPEN_PLAYBACK2); close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); return 0; } static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); return 0; } static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) { struct cmipci *cm = snd_pcm_substream_chip(substream); close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); return 0; } /* */ static const struct snd_pcm_ops snd_cmipci_playback_ops = { .open = snd_cmipci_playback_open, .close = snd_cmipci_playback_close, .hw_free = snd_cmipci_playback_hw_free, .prepare = snd_cmipci_playback_prepare, .trigger = snd_cmipci_playback_trigger, .pointer = snd_cmipci_playback_pointer, }; static const struct snd_pcm_ops snd_cmipci_capture_ops = { .open = snd_cmipci_capture_open, .close = snd_cmipci_capture_close, .prepare = snd_cmipci_capture_prepare, .trigger = snd_cmipci_capture_trigger, .pointer = snd_cmipci_capture_pointer, }; static const struct snd_pcm_ops snd_cmipci_playback2_ops = { .open = snd_cmipci_playback2_open, .close = snd_cmipci_playback2_close, .hw_params = snd_cmipci_playback2_hw_params, .hw_free = snd_cmipci_playback2_hw_free, .prepare = snd_cmipci_capture_prepare, /* channel B */ .trigger = snd_cmipci_capture_trigger, /* channel B */ .pointer = snd_cmipci_capture_pointer, /* channel B */ }; static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { .open = snd_cmipci_playback_spdif_open, .close = snd_cmipci_playback_spdif_close, .hw_free = snd_cmipci_playback_hw_free, .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ .trigger = snd_cmipci_playback_trigger, .pointer = snd_cmipci_playback_pointer, }; static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { .open = snd_cmipci_capture_spdif_open, .close = snd_cmipci_capture_spdif_close, .hw_free = snd_cmipci_capture_spdif_hw_free, .prepare = snd_cmipci_capture_spdif_prepare, .trigger = snd_cmipci_capture_trigger, .pointer = snd_cmipci_capture_pointer, }; /* */ static int snd_cmipci_pcm_new(struct cmipci *cm, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); pcm->private_data = cm; pcm->info_flags = 0; strcpy(pcm->name, "C-Media PCI DAC/ADC"); cm->pcm = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &cm->pci->dev, 64*1024, 128*1024); return 0; } static int snd_cmipci_pcm2_new(struct cmipci *cm, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); pcm->private_data = cm; pcm->info_flags = 0; strcpy(pcm->name, "C-Media PCI 2nd DAC"); cm->pcm2 = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &cm->pci->dev, 64*1024, 128*1024); return 0; } static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); pcm->private_data = cm; pcm->info_flags = 0; strcpy(pcm->name, "C-Media PCI IEC958"); cm->pcm_spdif = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &cm->pci->dev, 64*1024, 128*1024); err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_alt_chmaps, cm->max_channels, 0, NULL); if (err < 0) return err; return 0; } /* * mixer interface: * - CM8338/8738 has a compatible mixer interface with SB16, but * lack of some elements like tone control, i/o gain and AGC. * - Access to native registers: * - A 3D switch * - Output mute switches */ static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) { outb(idx, s->iobase + CM_REG_SB16_ADDR); outb(data, s->iobase + CM_REG_SB16_DATA); } static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) { unsigned char v; outb(idx, s->iobase + CM_REG_SB16_ADDR); v = inb(s->iobase + CM_REG_SB16_DATA); return v; } /* * general mixer element */ struct cmipci_sb_reg { unsigned int left_reg, right_reg; unsigned int left_shift, right_shift; unsigned int mask; unsigned int invert: 1; unsigned int stereo: 1; }; #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_volume, \ .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ } #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) { r->left_reg = val & 0xff; r->right_reg = (val >> 8) & 0xff; r->left_shift = (val >> 16) & 0x07; r->right_shift = (val >> 19) & 0x07; r->invert = (val >> 22) & 1; r->stereo = (val >> 23) & 1; r->mask = (val >> 24) & 0xff; } static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct cmipci_sb_reg reg; cmipci_sb_reg_decode(&reg, kcontrol->private_value); uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = reg.stereo + 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = reg.mask; return 0; } static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; int val; cmipci_sb_reg_decode(&reg, kcontrol->private_value); spin_lock_irq(&cm->reg_lock); val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[0] = val; if (reg.stereo) { val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[1] = val; } spin_unlock_irq(&cm->reg_lock); return 0; } static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; int change; int left, right, oleft, oright; cmipci_sb_reg_decode(&reg, kcontrol->private_value); left = ucontrol->value.integer.value[0] & reg.mask; if (reg.invert) left = reg.mask - left; left <<= reg.left_shift; if (reg.stereo) { right = ucontrol->value.integer.value[1] & reg.mask; if (reg.invert) right = reg.mask - right; right <<= reg.right_shift; } else right = 0; spin_lock_irq(&cm->reg_lock); oleft = snd_cmipci_mixer_read(cm, reg.left_reg); left |= oleft & ~(reg.mask << reg.left_shift); change = left != oleft; if (reg.stereo) { if (reg.left_reg != reg.right_reg) { snd_cmipci_mixer_write(cm, reg.left_reg, left); oright = snd_cmipci_mixer_read(cm, reg.right_reg); } else oright = left; right |= oright & ~(reg.mask << reg.right_shift); change |= right != oright; snd_cmipci_mixer_write(cm, reg.right_reg, right); } else snd_cmipci_mixer_write(cm, reg.left_reg, left); spin_unlock_irq(&cm->reg_lock); return change; } /* * input route (left,right) -> (left,right) */ #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_input_sw, \ .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ } static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; uinfo->count = 4; uinfo->value.integer.min = 0; uinfo->value.integer.max = 1; return 0; } static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; int val1, val2; cmipci_sb_reg_decode(&reg, kcontrol->private_value); spin_lock_irq(&cm->reg_lock); val1 = snd_cmipci_mixer_read(cm, reg.left_reg); val2 = snd_cmipci_mixer_read(cm, reg.right_reg); spin_unlock_irq(&cm->reg_lock); ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; return 0; } static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; int change; int val1, val2, oval1, oval2; cmipci_sb_reg_decode(&reg, kcontrol->private_value); spin_lock_irq(&cm->reg_lock); oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; change = val1 != oval1 || val2 != oval2; snd_cmipci_mixer_write(cm, reg.left_reg, val1); snd_cmipci_mixer_write(cm, reg.right_reg, val2); spin_unlock_irq(&cm->reg_lock); return change; } /* * native mixer switches/volumes */ #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_native_mixer, \ .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ } #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_native_mixer, \ .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ } #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_native_mixer, \ .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ } #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_cmipci_info_native_mixer, \ .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ } static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct cmipci_sb_reg reg; cmipci_sb_reg_decode(&reg, kcontrol->private_value); uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = reg.stereo + 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = reg.mask; return 0; } static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; unsigned char oreg, val; cmipci_sb_reg_decode(&reg, kcontrol->private_value); spin_lock_irq(&cm->reg_lock); oreg = inb(cm->iobase + reg.left_reg); val = (oreg >> reg.left_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[0] = val; if (reg.stereo) { val = (oreg >> reg.right_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[1] = val; } spin_unlock_irq(&cm->reg_lock); return 0; } static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); struct cmipci_sb_reg reg; unsigned char oreg, nreg, val; cmipci_sb_reg_decode(&reg, kcontrol->private_value); spin_lock_irq(&cm->reg_lock); oreg = inb(cm->iobase + reg.left_reg); val = ucontrol->value.integer.value[0] & reg.mask; if (reg.invert) val = reg.mask - val; nreg = oreg & ~(reg.mask << reg.left_shift); nreg |= (val << reg.left_shift); if (reg.stereo) { val = ucontrol->value.integer.value[1] & reg.mask; if (reg.invert) val = reg.mask - val; nreg &= ~(reg.mask << reg.right_shift); nreg |= (val << reg.right_shift); } outb(nreg, cm->iobase + reg.left_reg); spin_unlock_irq(&cm->reg_lock); return (nreg != oreg); } /* * special case - check mixer sensitivity */ static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { //struct cmipci *cm = snd_kcontrol_chip(kcontrol); return snd_cmipci_get_native_mixer(kcontrol, ucontrol); } static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); if (cm->mixer_insensitive) { /* ignored */ return 0; } return snd_cmipci_put_native_mixer(kcontrol, ucontrol); } static const struct snd_kcontrol_new snd_cmipci_mixers[] = { CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), { /* switch with sensitivity */ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "PCM Playback Switch", .info = snd_cmipci_info_native_mixer, .get = snd_cmipci_get_native_mixer_sensitive, .put = snd_cmipci_put_native_mixer_sensitive, .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), }, CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), }; /* * other switches */ struct cmipci_switch_args { int reg; /* register index */ unsigned int mask; /* mask bits */ unsigned int mask_on; /* mask bits to turn on */ unsigned int is_byte: 1; /* byte access? */ unsigned int ac3_sensitive: 1; /* access forbidden during * non-audio operation? */ }; #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol, struct cmipci_switch_args *args) { unsigned int val; struct cmipci *cm = snd_kcontrol_chip(kcontrol); spin_lock_irq(&cm->reg_lock); if (args->ac3_sensitive && cm->mixer_insensitive) { ucontrol->value.integer.value[0] = 0; spin_unlock_irq(&cm->reg_lock); return 0; } if (args->is_byte) val = inb(cm->iobase + args->reg); else val = snd_cmipci_read(cm, args->reg); ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; spin_unlock_irq(&cm->reg_lock); return 0; } static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci_switch_args *args; args = (struct cmipci_switch_args *)kcontrol->private_value; if (snd_BUG_ON(!args)) return -EINVAL; return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); } static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol, struct cmipci_switch_args *args) { unsigned int val; int change; struct cmipci *cm = snd_kcontrol_chip(kcontrol); spin_lock_irq(&cm->reg_lock); if (args->ac3_sensitive && cm->mixer_insensitive) { /* ignored */ spin_unlock_irq(&cm->reg_lock); return 0; } if (args->is_byte) val = inb(cm->iobase + args->reg); else val = snd_cmipci_read(cm, args->reg); change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask_on : (args->mask & ~args->mask_on)); if (change) { val &= ~args->mask; if (ucontrol->value.integer.value[0]) val |= args->mask_on; else val |= (args->mask & ~args->mask_on); if (args->is_byte) outb((unsigned char)val, cm->iobase + args->reg); else snd_cmipci_write(cm, args->reg, val); } spin_unlock_irq(&cm->reg_lock); return change; } static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci_switch_args *args; args = (struct cmipci_switch_args *)kcontrol->private_value; if (snd_BUG_ON(!args)) return -EINVAL; return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); } #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ .reg = xreg, \ .mask = xmask, \ .mask_on = xmask_on, \ .is_byte = xis_byte, \ .ac3_sensitive = xac3, \ } #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) #if 0 /* these will be controlled in pcm device */ DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); #endif DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); #if CM_CH_PLAY == 1 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ #else DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); #endif DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0); // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0); // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); #define DEFINE_SWITCH(sname, stype, sarg) \ { .name = sname, \ .iface = stype, \ .info = snd_cmipci_uswitch_info, \ .get = snd_cmipci_uswitch_get, \ .put = snd_cmipci_uswitch_put, \ .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ } #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) /* * callbacks for spdif output switch * needs toggle two registers.. */ static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int changed; changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); return changed; } static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *chip = snd_kcontrol_chip(kcontrol); int changed; changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); if (changed) { if (ucontrol->value.integer.value[0]) { if (chip->spdif_playback_avail) snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); } else { if (chip->spdif_playback_avail) snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); } } chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; return changed; } static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); static const char *const texts[3] = { "Line-In", "Rear Output", "Bass Output" }; return snd_ctl_enum_info(uinfo, 1, cm->chip_version >= 39 ? 3 : 2, texts); } static inline unsigned int get_line_in_mode(struct cmipci *cm) { unsigned int val; if (cm->chip_version >= 39) { val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); if (val & (CM_CENTR2LIN | CM_BASE2LIN)) return 2; } val = snd_cmipci_read_b(cm, CM_REG_MIXER1); if (val & CM_REAR2LIN) return 1; return 0; } static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); spin_lock_irq(&cm->reg_lock); ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); spin_unlock_irq(&cm->reg_lock); return 0; } static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); int change; spin_lock_irq(&cm->reg_lock); if (ucontrol->value.enumerated.item[0] == 2) change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); else change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); if (ucontrol->value.enumerated.item[0] == 1) change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); else change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); spin_unlock_irq(&cm->reg_lock); return change; } static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char *const texts[2] = { "Mic-In", "Center/LFE Output" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); /* same bit as spdi_phase */ spin_lock_irq(&cm->reg_lock); ucontrol->value.enumerated.item[0] = (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; spin_unlock_irq(&cm->reg_lock); return 0; } static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cmipci *cm = snd_kcontrol_chip(kcontrol); int change; spin_lock_irq(&cm->reg_lock); if (ucontrol->value.enumerated.item[0]) change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); else change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); spin_unlock_irq(&cm->reg_lock); return change; } /* both for CM8338/8738 */ static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = { DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), { .name = "Line-In Mode", .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_cmipci_line_in_mode_info, .get = snd_cmipci_line_in_mode_get, .put = snd_cmipci_line_in_mode_put, }, }; /* for non-multichannel chips */ static const struct snd_kcontrol_new snd_cmipci_nomulti_switch = DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); /* only for CM8738 */ static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = { #if 0 /* controlled in pcm device */ DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), #endif // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), { .name = "IEC958 Output Switch", .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_cmipci_uswitch_info, .get = snd_cmipci_spdout_enable_get, .put = snd_cmipci_spdout_enable_put, }, DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), }; /* only for model 033/037 */ static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = { DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), }; /* only for model 039 or later */ static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = { DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), { .name = "Mic-In Mode", .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_cmipci_mic_in_mode_info, .get = snd_cmipci_mic_in_mode_get, .put = snd_cmipci_mic_in_mode_put, } }; /* card control switches */ static const struct snd_kcontrol_new snd_cmipci_modem_switch = DEFINE_CARD_SWITCH("Modem", modem); static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) { struct snd_card *card; const struct snd_kcontrol_new *sw; struct snd_kcontrol *kctl; unsigned int idx; int err; if (snd_BUG_ON(!cm || !cm->card)) return -EINVAL; card = cm->card; strcpy(card->mixername, "CMedia PCI"); spin_lock_irq(&cm->reg_lock); snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ spin_unlock_irq(&cm->reg_lock); for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { if (cm->chip_version == 68) { // 8768 has no PCM volume if (!strcmp(snd_cmipci_mixers[idx].name, "PCM Playback Volume")) continue; } err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm)); if (err < 0) return err; } /* mixer switches */ sw = snd_cmipci_mixer_switches; for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); if (err < 0) return err; } if (! cm->can_multi_ch) { err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); if (err < 0) return err; } if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { sw = snd_cmipci_8738_mixer_switches; for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); if (err < 0) return err; } if (cm->can_ac3_hw) { kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm); kctl->id.device = pcm_spdif_device; err = snd_ctl_add(card, kctl); if (err < 0) return err; kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm); kctl->id.device = pcm_spdif_device; err = snd_ctl_add(card, kctl); if (err < 0) return err; kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm); kctl->id.device = pcm_spdif_device; err = snd_ctl_add(card, kctl); if (err < 0) return err; } if (cm->chip_version <= 37) { sw = snd_cmipci_old_mixer_switches; for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); if (err < 0) return err; } } } if (cm->chip_version >= 39) { sw = snd_cmipci_extra_mixer_switches; for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); if (err < 0) return err; } } /* card switches */ /* * newer chips don't have the register bits to force modem link * detection; the bit that was FLINKON now mutes CH1 */ if (cm->chip_version < 39) { err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_modem_switch, cm)); if (err < 0) return err; } for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { struct snd_kcontrol *ctl; ctl = snd_ctl_find_id_mixer(cm->card, cm_saved_mixer[idx].name); if (ctl) cm->mixer_res_ctl[idx] = ctl; } return 0; } /* * proc interface */ static void snd_cmipci_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct cmipci *cm = entry->private_data; int i, v; snd_iprintf(buffer, "%s\n", cm->card->longname); for (i = 0; i < 0x94; i++) { if (i == 0x28) i = 0x90; v = inb(cm->iobase + i); if (i % 4 == 0) snd_iprintf(buffer, "\n%02x:", i); snd_iprintf(buffer, " %02x", v); } snd_iprintf(buffer, "\n"); } static void snd_cmipci_proc_init(struct cmipci *cm) { snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read); } static const struct pci_device_id snd_cmipci_ids[] = { {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0}, {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0}, {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0}, {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, {0,}, }; /* * check chip version and capabilities * driver name is modified according to the chip model */ static void query_chip(struct cmipci *cm) { unsigned int detect; /* check reg 0Ch, bit 24-31 */ detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; if (! detect) { /* check reg 08h, bit 24-28 */ detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; switch (detect) { case 0: cm->chip_version = 33; if (cm->do_soft_ac3) cm->can_ac3_sw = 1; else cm->can_ac3_hw = 1; break; case CM_CHIP_037: cm->chip_version = 37; cm->can_ac3_hw = 1; break; default: cm->chip_version = 39; cm->can_ac3_hw = 1; break; } cm->max_channels = 2; } else { if (detect & CM_CHIP_039) { cm->chip_version = 39; if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ cm->max_channels = 6; else cm->max_channels = 4; } else if (detect & CM_CHIP_8768) { cm->chip_version = 68; cm->max_channels = 8; cm->can_96k = 1; } else { cm->chip_version = 55; cm->max_channels = 6; cm->can_96k = 1; } cm->can_ac3_hw = 1; cm->can_multi_ch = 1; } } #ifdef SUPPORT_JOYSTICK static int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ struct gameport *gp; struct resource *r = NULL; int i, io_port = 0; if (joystick_port[dev] == 0) return -ENODEV; if (joystick_port[dev] == 1) { /* auto-detect */ for (i = 0; ports[i]; i++) { io_port = ports[i]; r = devm_request_region(&cm->pci->dev, io_port, 1, "CMIPCI gameport"); if (r) break; } } else { io_port = joystick_port[dev]; r = devm_request_region(&cm->pci->dev, io_port, 1, "CMIPCI gameport"); } if (!r) { dev_warn(cm->card->dev, "cannot reserve joystick ports\n"); return -EBUSY; } cm->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(cm->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "C-Media Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); gameport_set_dev_parent(gp, &cm->pci->dev); gp->io = io_port; snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); gameport_register_port(cm->gameport); return 0; } static void snd_cmipci_free_gameport(struct cmipci *cm) { if (cm->gameport) { gameport_unregister_port(cm->gameport); cm->gameport = NULL; snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); } } #else static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } #endif static void snd_cmipci_free(struct snd_card *card) { struct cmipci *cm = card->private_data; snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ snd_cmipci_ch_reset(cm, CM_CH_PLAY); snd_cmipci_ch_reset(cm, CM_CH_CAPT); snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); /* reset mixer */ snd_cmipci_mixer_write(cm, 0, 0); snd_cmipci_free_gameport(cm); } static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port) { long iosynth; unsigned int val; struct snd_opl3 *opl3; int err; if (!fm_port) goto disable_fm; if (cm->chip_version >= 39) { /* first try FM regs in PCI port range */ iosynth = cm->iobase + CM_REG_FM_PCI; err = snd_opl3_create(cm->card, iosynth, iosynth + 2, OPL3_HW_OPL3, 1, &opl3); } else { err = -EIO; } if (err < 0) { /* then try legacy ports */ val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; iosynth = fm_port; switch (iosynth) { case 0x3E8: val |= CM_FMSEL_3E8; break; case 0x3E0: val |= CM_FMSEL_3E0; break; case 0x3C8: val |= CM_FMSEL_3C8; break; case 0x388: val |= CM_FMSEL_388; break; default: goto disable_fm; } snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); /* enable FM */ snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); if (snd_opl3_create(cm->card, iosynth, iosynth + 2, OPL3_HW_OPL3, 0, &opl3) < 0) { dev_err(cm->card->dev, "no OPL device at %#lx, skipping...\n", iosynth); goto disable_fm; } } err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) { dev_err(cm->card->dev, "cannot create OPL3 hwdep\n"); return err; } return 0; disable_fm: snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); return 0; } static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, int dev) { struct cmipci *cm = card->private_data; int err; unsigned int val; long iomidi = 0; int integrated_midi = 0; char modelstr[16]; int pcm_index, pcm_spdif_index; static const struct pci_device_id intel_82437vx[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, { }, }; err = pcim_enable_device(pci); if (err < 0) return err; spin_lock_init(&cm->reg_lock); mutex_init(&cm->open_mutex); cm->device = pci->device; cm->card = card; cm->pci = pci; cm->irq = -1; cm->channel[0].ch = 0; cm->channel[1].ch = 1; cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ err = pci_request_regions(pci, card->driver); if (err < 0) return err; cm->iobase = pci_resource_start(pci, 0); if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt, IRQF_SHARED, KBUILD_MODNAME, cm)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } cm->irq = pci->irq; card->sync_irq = cm->irq; card->private_free = snd_cmipci_free; pci_set_master(cm->pci); /* * check chip version, max channels and capabilities */ cm->chip_version = 0; cm->max_channels = 2; cm->do_soft_ac3 = soft_ac3[dev]; if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) query_chip(cm); /* added -MCx suffix for chip supporting multi-channels */ if (cm->can_multi_ch) sprintf(cm->card->driver + strlen(cm->card->driver), "-MC%d", cm->max_channels); else if (cm->can_ac3_sw) strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; #if CM_CH_PLAY == 1 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ #else cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ #endif /* initialize codec registers */ snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET); snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET); snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ snd_cmipci_ch_reset(cm, CM_CH_PLAY); snd_cmipci_ch_reset(cm, CM_CH_CAPT); snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); #if CM_CH_PLAY == 1 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); #else snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); #endif if (cm->chip_version) { snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */ snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */ } /* Set Bus Master Request */ snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ switch (pci->device) { case PCI_DEVICE_ID_CMEDIA_CM8738: case PCI_DEVICE_ID_CMEDIA_CM8738B: if (!pci_dev_present(intel_82437vx)) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); break; default: break; } if (cm->chip_version < 68) { val = pci->device < 0x110 ? 8338 : 8738; } else { switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) { case 0: val = 8769; break; case 2: val = 8762; break; default: switch ((pci->subsystem_vendor << 16) | pci->subsystem_device) { case 0x13f69761: case 0x584d3741: case 0x584d3751: case 0x584d3761: case 0x584d3771: case 0x72848384: val = 8770; break; default: val = 8768; break; } } } sprintf(card->shortname, "C-Media CMI%d", val); if (cm->chip_version < 68) scnprintf(modelstr, sizeof(modelstr), " (model %d)", cm->chip_version); else modelstr[0] = '\0'; scnprintf(card->longname, sizeof(card->longname), "%s%s at %#lx, irq %i", card->shortname, modelstr, cm->iobase, cm->irq); if (cm->chip_version >= 39) { val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); if (val != 0x00 && val != 0xff) { if (mpu_port[dev]) iomidi = cm->iobase + CM_REG_MPU_PCI; integrated_midi = 1; } } if (!integrated_midi) { val = 0; iomidi = mpu_port[dev]; switch (iomidi) { case 0x320: val = CM_VMPU_320; break; case 0x310: val = CM_VMPU_310; break; case 0x300: val = CM_VMPU_300; break; case 0x330: val = CM_VMPU_330; break; default: iomidi = 0; break; } if (iomidi > 0) { snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); /* enable UART */ snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); if (inb(iomidi + 1) == 0xff) { dev_err(cm->card->dev, "cannot enable MPU-401 port at %#lx\n", iomidi); snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); iomidi = 0; } } } if (cm->chip_version < 68) { err = snd_cmipci_create_fm(cm, fm_port[dev]); if (err < 0) return err; } /* reset mixer */ snd_cmipci_mixer_write(cm, 0, 0); snd_cmipci_proc_init(cm); /* create pcm devices */ pcm_index = pcm_spdif_index = 0; err = snd_cmipci_pcm_new(cm, pcm_index); if (err < 0) return err; pcm_index++; err = snd_cmipci_pcm2_new(cm, pcm_index); if (err < 0) return err; pcm_index++; if (cm->can_ac3_hw || cm->can_ac3_sw) { pcm_spdif_index = pcm_index; err = snd_cmipci_pcm_spdif_new(cm, pcm_index); if (err < 0) return err; } /* create mixer interface & switches */ err = snd_cmipci_mixer_new(cm, pcm_spdif_index); if (err < 0) return err; if (iomidi > 0) { err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, iomidi, (integrated_midi ? MPU401_INFO_INTEGRATED : 0) | MPU401_INFO_IRQ_HOOK, -1, &cm->rmidi); if (err < 0) dev_err(cm->card->dev, "no UART401 device at 0x%lx\n", iomidi); } #ifdef USE_VAR48KRATE for (val = 0; val < ARRAY_SIZE(rates); val++) snd_cmipci_set_pll(cm, rates[val], val); /* * (Re-)Enable external switch spdo_48k */ snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); #endif /* USE_VAR48KRATE */ if (snd_cmipci_create_gameport(cm, dev) < 0) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); return 0; } /* */ MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); static int snd_cmipci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (! enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(struct cmipci), &card); if (err < 0) return err; switch (pci->device) { case PCI_DEVICE_ID_CMEDIA_CM8738: case PCI_DEVICE_ID_CMEDIA_CM8738B: strcpy(card->driver, "CMI8738"); break; case PCI_DEVICE_ID_CMEDIA_CM8338A: case PCI_DEVICE_ID_CMEDIA_CM8338B: strcpy(card->driver, "CMI8338"); break; default: strcpy(card->driver, "CMIPCI"); break; } err = snd_cmipci_create(card, pci, dev); if (err < 0) goto error; err = snd_card_register(card); if (err < 0) goto error; pci_set_drvdata(pci, card); dev++; return 0; error: snd_card_free(card); return err; } #ifdef CONFIG_PM_SLEEP /* * power management */ static const unsigned char saved_regs[] = { CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL, CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, }; static const unsigned char saved_mixers[] = { SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, }; static int snd_cmipci_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct cmipci *cm = card->private_data; int i; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); /* save registers */ for (i = 0; i < ARRAY_SIZE(saved_regs); i++) cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); /* disable ints */ snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); return 0; } static int snd_cmipci_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct cmipci *cm = card->private_data; int i; /* reset / initialize to a sane state */ snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); snd_cmipci_ch_reset(cm, CM_CH_PLAY); snd_cmipci_ch_reset(cm, CM_CH_CAPT); snd_cmipci_mixer_write(cm, 0, 0); /* restore registers */ for (i = 0; i < ARRAY_SIZE(saved_regs); i++) snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume); #define SND_CMIPCI_PM_OPS &snd_cmipci_pm #else #define SND_CMIPCI_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static struct pci_driver cmipci_driver = { .name = KBUILD_MODNAME, .id_table = snd_cmipci_ids, .probe = snd_cmipci_probe, .driver = { .pm = SND_CMIPCI_PM_OPS, }, }; module_pci_driver(cmipci_driver);
linux-master
sound/pci/cmipci.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio * interfaces * * Copyright (c) 2000, 2001 Anders Torger <[email protected]> * * Thanks to Henk Hesselink <[email protected]> for the analog volume control * code. */ #include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/module.h> #include <linux/vmalloc.h> #include <linux/io.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/asoundef.h> #include <sound/initval.h> /* note, two last pcis should be equal, it is not a bug */ MODULE_AUTHOR("Anders Torger <[email protected]>"); MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " "Digi96/8 PAD"); MODULE_LICENSE("GPL"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); /* * Defines for RME Digi96 series, from internal RME reference documents * dated 12.01.00 */ #define RME96_SPDIF_NCHANNELS 2 /* Playback and capture buffer size */ #define RME96_BUFFER_SIZE 0x10000 /* IO area size */ #define RME96_IO_SIZE 0x60000 /* IO area offsets */ #define RME96_IO_PLAY_BUFFER 0x0 #define RME96_IO_REC_BUFFER 0x10000 #define RME96_IO_CONTROL_REGISTER 0x20000 #define RME96_IO_ADDITIONAL_REG 0x20004 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C #define RME96_IO_SET_PLAY_POS 0x40000 #define RME96_IO_RESET_PLAY_POS 0x4FFFC #define RME96_IO_SET_REC_POS 0x50000 #define RME96_IO_RESET_REC_POS 0x5FFFC #define RME96_IO_GET_PLAY_POS 0x20000 #define RME96_IO_GET_REC_POS 0x30000 /* Write control register bits */ #define RME96_WCR_START (1 << 0) #define RME96_WCR_START_2 (1 << 1) #define RME96_WCR_GAIN_0 (1 << 2) #define RME96_WCR_GAIN_1 (1 << 3) #define RME96_WCR_MODE24 (1 << 4) #define RME96_WCR_MODE24_2 (1 << 5) #define RME96_WCR_BM (1 << 6) #define RME96_WCR_BM_2 (1 << 7) #define RME96_WCR_ADAT (1 << 8) #define RME96_WCR_FREQ_0 (1 << 9) #define RME96_WCR_FREQ_1 (1 << 10) #define RME96_WCR_DS (1 << 11) #define RME96_WCR_PRO (1 << 12) #define RME96_WCR_EMP (1 << 13) #define RME96_WCR_SEL (1 << 14) #define RME96_WCR_MASTER (1 << 15) #define RME96_WCR_PD (1 << 16) #define RME96_WCR_INP_0 (1 << 17) #define RME96_WCR_INP_1 (1 << 18) #define RME96_WCR_THRU_0 (1 << 19) #define RME96_WCR_THRU_1 (1 << 20) #define RME96_WCR_THRU_2 (1 << 21) #define RME96_WCR_THRU_3 (1 << 22) #define RME96_WCR_THRU_4 (1 << 23) #define RME96_WCR_THRU_5 (1 << 24) #define RME96_WCR_THRU_6 (1 << 25) #define RME96_WCR_THRU_7 (1 << 26) #define RME96_WCR_DOLBY (1 << 27) #define RME96_WCR_MONITOR_0 (1 << 28) #define RME96_WCR_MONITOR_1 (1 << 29) #define RME96_WCR_ISEL (1 << 30) #define RME96_WCR_IDIS (1 << 31) #define RME96_WCR_BITPOS_GAIN_0 2 #define RME96_WCR_BITPOS_GAIN_1 3 #define RME96_WCR_BITPOS_FREQ_0 9 #define RME96_WCR_BITPOS_FREQ_1 10 #define RME96_WCR_BITPOS_INP_0 17 #define RME96_WCR_BITPOS_INP_1 18 #define RME96_WCR_BITPOS_MONITOR_0 28 #define RME96_WCR_BITPOS_MONITOR_1 29 /* Read control register bits */ #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF #define RME96_RCR_IRQ_2 (1 << 16) #define RME96_RCR_T_OUT (1 << 17) #define RME96_RCR_DEV_ID_0 (1 << 21) #define RME96_RCR_DEV_ID_1 (1 << 22) #define RME96_RCR_LOCK (1 << 23) #define RME96_RCR_VERF (1 << 26) #define RME96_RCR_F0 (1 << 27) #define RME96_RCR_F1 (1 << 28) #define RME96_RCR_F2 (1 << 29) #define RME96_RCR_AUTOSYNC (1 << 30) #define RME96_RCR_IRQ (1 << 31) #define RME96_RCR_BITPOS_F0 27 #define RME96_RCR_BITPOS_F1 28 #define RME96_RCR_BITPOS_F2 29 /* Additional register bits */ #define RME96_AR_WSEL (1 << 0) #define RME96_AR_ANALOG (1 << 1) #define RME96_AR_FREQPAD_0 (1 << 2) #define RME96_AR_FREQPAD_1 (1 << 3) #define RME96_AR_FREQPAD_2 (1 << 4) #define RME96_AR_PD2 (1 << 5) #define RME96_AR_DAC_EN (1 << 6) #define RME96_AR_CLATCH (1 << 7) #define RME96_AR_CCLK (1 << 8) #define RME96_AR_CDATA (1 << 9) #define RME96_AR_BITPOS_F0 2 #define RME96_AR_BITPOS_F1 3 #define RME96_AR_BITPOS_F2 4 /* Monitor tracks */ #define RME96_MONITOR_TRACKS_1_2 0 #define RME96_MONITOR_TRACKS_3_4 1 #define RME96_MONITOR_TRACKS_5_6 2 #define RME96_MONITOR_TRACKS_7_8 3 /* Attenuation */ #define RME96_ATTENUATION_0 0 #define RME96_ATTENUATION_6 1 #define RME96_ATTENUATION_12 2 #define RME96_ATTENUATION_18 3 /* Input types */ #define RME96_INPUT_OPTICAL 0 #define RME96_INPUT_COAXIAL 1 #define RME96_INPUT_INTERNAL 2 #define RME96_INPUT_XLR 3 #define RME96_INPUT_ANALOG 4 /* Clock modes */ #define RME96_CLOCKMODE_SLAVE 0 #define RME96_CLOCKMODE_MASTER 1 #define RME96_CLOCKMODE_WORDCLOCK 2 /* Block sizes in bytes */ #define RME96_SMALL_BLOCK_SIZE 2048 #define RME96_LARGE_BLOCK_SIZE 8192 /* Volume control */ #define RME96_AD1852_VOL_BITS 14 #define RME96_AD1855_VOL_BITS 10 /* Defines for snd_rme96_trigger */ #define RME96_TB_START_PLAYBACK 1 #define RME96_TB_START_CAPTURE 2 #define RME96_TB_STOP_PLAYBACK 4 #define RME96_TB_STOP_CAPTURE 8 #define RME96_TB_RESET_PLAYPOS 16 #define RME96_TB_RESET_CAPTUREPOS 32 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ | RME96_RESUME_CAPTURE) #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ | RME96_TB_RESET_PLAYPOS) #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ | RME96_TB_RESET_CAPTUREPOS) #define RME96_START_BOTH (RME96_START_PLAYBACK \ | RME96_START_CAPTURE) #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ | RME96_TB_CLEAR_PLAYBACK_IRQ) #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ | RME96_TB_CLEAR_CAPTURE_IRQ) #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ | RME96_STOP_CAPTURE) struct rme96 { spinlock_t lock; int irq; unsigned long port; void __iomem *iobase; u32 wcreg; /* cached write control register value */ u32 wcreg_spdif; /* S/PDIF setup */ u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ u32 rcreg; /* cached read control register value */ u32 areg; /* cached additional register value */ u16 vol[2]; /* cached volume of analog output */ u8 rev; /* card revision number */ #ifdef CONFIG_PM_SLEEP u32 playback_pointer; u32 capture_pointer; void *playback_suspend_buffer; void *capture_suspend_buffer; #endif struct snd_pcm_substream *playback_substream; struct snd_pcm_substream *capture_substream; int playback_frlog; /* log2 of framesize */ int capture_frlog; size_t playback_periodsize; /* in bytes, zero if not used */ size_t capture_periodsize; /* in bytes, zero if not used */ struct snd_card *card; struct snd_pcm *spdif_pcm; struct snd_pcm *adat_pcm; struct pci_dev *pci; struct snd_kcontrol *spdif_ctl; }; static const struct pci_device_id snd_rme96_ids[] = { { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, { 0, } }; MODULE_DEVICE_TABLE(pci, snd_rme96_ids); #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) static int snd_rme96_playback_prepare(struct snd_pcm_substream *substream); static int snd_rme96_capture_prepare(struct snd_pcm_substream *substream); static int snd_rme96_playback_trigger(struct snd_pcm_substream *substream, int cmd); static int snd_rme96_capture_trigger(struct snd_pcm_substream *substream, int cmd); static snd_pcm_uframes_t snd_rme96_playback_pointer(struct snd_pcm_substream *substream); static snd_pcm_uframes_t snd_rme96_capture_pointer(struct snd_pcm_substream *substream); static void snd_rme96_proc_init(struct rme96 *rme96); static int snd_rme96_create_switches(struct snd_card *card, struct rme96 *rme96); static int snd_rme96_getinputtype(struct rme96 *rme96); static inline unsigned int snd_rme96_playback_ptr(struct rme96 *rme96) { return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; } static inline unsigned int snd_rme96_capture_ptr(struct rme96 *rme96) { return (readl(rme96->iobase + RME96_IO_GET_REC_POS) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; } static int snd_rme96_playback_silence(struct snd_pcm_substream *substream, int channel, unsigned long pos, unsigned long count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 0, count); return 0; } static int snd_rme96_playback_copy(struct snd_pcm_substream *substream, int channel, unsigned long pos, struct iov_iter *src, unsigned long count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return copy_from_iter_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count); } static int snd_rme96_capture_copy(struct snd_pcm_substream *substream, int channel, unsigned long pos, struct iov_iter *dst, unsigned long count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return copy_to_iter_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count); } /* * Digital output capabilities (S/PDIF) */ static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000), .rate_min = 32000, .rate_max = 96000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital input capabilities (S/PDIF) */ static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000), .rate_min = 32000, .rate_max = 96000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital output capabilities (ADAT) */ static const struct snd_pcm_hardware snd_rme96_playback_adat_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital input capabilities (ADAT) */ static const struct snd_pcm_hardware snd_rme96_capture_adat_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up * on the falling edge of CCLK and be stable on the rising edge. The rising * edge of CLATCH after the last data bit clocks in the whole data word. * A fast processor could probably drive the SPI interface faster than the * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) * limits the data rate to 500KHz and only causes a delay of 33 microsecs. * * NOTE: increased delay from 1 to 10, since there where problems setting * the volume. */ static void snd_rme96_write_SPI(struct rme96 *rme96, u16 val) { int i; for (i = 0; i < 16; i++) { if (val & 0x8000) { rme96->areg |= RME96_AR_CDATA; } else { rme96->areg &= ~RME96_AR_CDATA; } rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); rme96->areg |= RME96_AR_CCLK; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); val <<= 1; } rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); rme96->areg |= RME96_AR_CLATCH; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); rme96->areg &= ~RME96_AR_CLATCH; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); } static void snd_rme96_apply_dac_volume(struct rme96 *rme96) { if (RME96_DAC_IS_1852(rme96)) { snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); } else if (RME96_DAC_IS_1855(rme96)) { snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); } } static void snd_rme96_reset_dac(struct rme96 *rme96) { writel(rme96->wcreg | RME96_WCR_PD, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static int snd_rme96_getmontracks(struct rme96 *rme96) { return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); } static int snd_rme96_setmontracks(struct rme96 *rme96, int montracks) { if (montracks & 1) { rme96->wcreg |= RME96_WCR_MONITOR_0; } else { rme96->wcreg &= ~RME96_WCR_MONITOR_0; } if (montracks & 2) { rme96->wcreg |= RME96_WCR_MONITOR_1; } else { rme96->wcreg &= ~RME96_WCR_MONITOR_1; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_getattenuation(struct rme96 *rme96) { return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); } static int snd_rme96_setattenuation(struct rme96 *rme96, int attenuation) { switch (attenuation) { case 0: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & ~RME96_WCR_GAIN_1; break; case 1: rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & ~RME96_WCR_GAIN_1; break; case 2: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | RME96_WCR_GAIN_1; break; case 3: rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | RME96_WCR_GAIN_1; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_capture_getrate(struct rme96 *rme96, int *is_adat) { int n, rate; *is_adat = 0; if (rme96->areg & RME96_AR_ANALOG) { /* Analog input, overrides S/PDIF setting */ n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); switch (n) { case 1: rate = 32000; break; case 2: rate = 44100; break; case 3: rate = 48000; break; default: return -1; } return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; } rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_LOCK) { /* ADAT rate */ *is_adat = 1; if (rme96->rcreg & RME96_RCR_T_OUT) { return 48000; } return 44100; } if (rme96->rcreg & RME96_RCR_VERF) { return -1; } /* S/PDIF rate */ n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); switch (n) { case 0: if (rme96->rcreg & RME96_RCR_T_OUT) { return 64000; } return -1; case 3: return 96000; case 4: return 88200; case 5: return 48000; case 6: return 44100; case 7: return 32000; default: break; } return -1; } static int snd_rme96_playback_getrate(struct rme96 *rme96) { int rate, dummy; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { rate = snd_rme96_capture_getrate(rme96, &dummy); if (rate > 0) { /* slave clock */ return rate; } } rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); switch (rate) { case 1: rate = 32000; break; case 2: rate = 44100; break; case 3: rate = 48000; break; default: return -1; } return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; } static int snd_rme96_playback_setrate(struct rme96 *rme96, int rate) { int ds; ds = rme96->wcreg & RME96_WCR_DS; switch (rate) { case 32000: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & ~RME96_WCR_FREQ_1; break; case 44100: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & ~RME96_WCR_FREQ_0; break; case 48000: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | RME96_WCR_FREQ_1; break; case 64000: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & ~RME96_WCR_FREQ_1; break; case 88200: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & ~RME96_WCR_FREQ_0; break; case 96000: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | RME96_WCR_FREQ_1; break; default: return -EINVAL; } if ((!ds && rme96->wcreg & RME96_WCR_DS) || (ds && !(rme96->wcreg & RME96_WCR_DS))) { /* change to/from double-speed: reset the DAC (if available) */ snd_rme96_reset_dac(rme96); return 1; /* need to restore volume */ } else { writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } } static int snd_rme96_capture_analog_setrate(struct rme96 *rme96, int rate) { switch (rate) { case 32000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 44100: rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 48000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 64000: if (rme96->rev < 4) { return -EINVAL; } rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; case 88200: if (rme96->rev < 4) { return -EINVAL; } rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; case 96000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; default: return -EINVAL; } writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); return 0; } static int snd_rme96_setclockmode(struct rme96 *rme96, int mode) { switch (mode) { case RME96_CLOCKMODE_SLAVE: /* AutoSync */ rme96->wcreg &= ~RME96_WCR_MASTER; rme96->areg &= ~RME96_AR_WSEL; break; case RME96_CLOCKMODE_MASTER: /* Internal */ rme96->wcreg |= RME96_WCR_MASTER; rme96->areg &= ~RME96_AR_WSEL; break; case RME96_CLOCKMODE_WORDCLOCK: /* Word clock is a master mode */ rme96->wcreg |= RME96_WCR_MASTER; rme96->areg |= RME96_AR_WSEL; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); return 0; } static int snd_rme96_getclockmode(struct rme96 *rme96) { if (rme96->areg & RME96_AR_WSEL) { return RME96_CLOCKMODE_WORDCLOCK; } return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : RME96_CLOCKMODE_SLAVE; } static int snd_rme96_setinputtype(struct rme96 *rme96, int type) { int n; switch (type) { case RME96_INPUT_OPTICAL: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & ~RME96_WCR_INP_1; break; case RME96_INPUT_COAXIAL: rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & ~RME96_WCR_INP_1; break; case RME96_INPUT_INTERNAL: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | RME96_WCR_INP_1; break; case RME96_INPUT_XLR: if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4)) { /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ return -EINVAL; } rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | RME96_WCR_INP_1; break; case RME96_INPUT_ANALOG: if (!RME96_HAS_ANALOG_IN(rme96)) { return -EINVAL; } rme96->areg |= RME96_AR_ANALOG; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); if (rme96->rev < 4) { /* * Revision less than 004 does not support 64 and * 88.2 kHz */ if (snd_rme96_capture_getrate(rme96, &n) == 88200) { snd_rme96_capture_analog_setrate(rme96, 44100); } if (snd_rme96_capture_getrate(rme96, &n) == 64000) { snd_rme96_capture_analog_setrate(rme96, 32000); } } return 0; default: return -EINVAL; } if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { rme96->areg &= ~RME96_AR_ANALOG; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_getinputtype(struct rme96 *rme96) { if (rme96->areg & RME96_AR_ANALOG) { return RME96_INPUT_ANALOG; } return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); } static void snd_rme96_setframelog(struct rme96 *rme96, int n_channels, int is_playback) { int frlog; if (n_channels == 2) { frlog = 1; } else { /* assume 8 channels */ frlog = 3; } if (is_playback) { frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; rme96->playback_frlog = frlog; } else { frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; rme96->capture_frlog = frlog; } } static int snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) { switch (format) { case SNDRV_PCM_FORMAT_S16_LE: rme96->wcreg &= ~RME96_WCR_MODE24; break; case SNDRV_PCM_FORMAT_S32_LE: rme96->wcreg |= RME96_WCR_MODE24; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) { switch (format) { case SNDRV_PCM_FORMAT_S16_LE: rme96->wcreg &= ~RME96_WCR_MODE24_2; break; case SNDRV_PCM_FORMAT_S32_LE: rme96->wcreg |= RME96_WCR_MODE24_2; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static void snd_rme96_set_period_properties(struct rme96 *rme96, size_t period_bytes) { switch (period_bytes) { case RME96_LARGE_BLOCK_SIZE: rme96->wcreg &= ~RME96_WCR_ISEL; break; case RME96_SMALL_BLOCK_SIZE: rme96->wcreg |= RME96_WCR_ISEL; break; default: snd_BUG(); break; } rme96->wcreg &= ~RME96_WCR_IDIS; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static int snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err, rate, dummy; bool apply_dac_volume = false; runtime->dma_area = (void __force *)(rme96->iobase + RME96_IO_PLAY_BUFFER); runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; runtime->dma_bytes = RME96_BUFFER_SIZE; spin_lock_irq(&rme96->lock); rate = 0; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) rate = snd_rme96_capture_getrate(rme96, &dummy); if (rate > 0) { /* slave clock */ if ((int)params_rate(params) != rate) { err = -EIO; goto error; } } else { err = snd_rme96_playback_setrate(rme96, params_rate(params)); if (err < 0) goto error; apply_dac_volume = err > 0; /* need to restore volume later? */ } err = snd_rme96_playback_setformat(rme96, params_format(params)); if (err < 0) goto error; snd_rme96_setframelog(rme96, params_channels(params), 1); if (rme96->capture_periodsize != 0) { if (params_period_size(params) << rme96->playback_frlog != rme96->capture_periodsize) { err = -EBUSY; goto error; } } rme96->playback_periodsize = params_period_size(params) << rme96->playback_frlog; snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); /* S/PDIF setup */ if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); } err = 0; error: spin_unlock_irq(&rme96->lock); if (apply_dac_volume) { usleep_range(3000, 10000); snd_rme96_apply_dac_volume(rme96); } return err; } static int snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err, isadat, rate; runtime->dma_area = (void __force *)(rme96->iobase + RME96_IO_REC_BUFFER); runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; runtime->dma_bytes = RME96_BUFFER_SIZE; spin_lock_irq(&rme96->lock); err = snd_rme96_capture_setformat(rme96, params_format(params)); if (err < 0) { spin_unlock_irq(&rme96->lock); return err; } if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { err = snd_rme96_capture_analog_setrate(rme96, params_rate(params)); if (err < 0) { spin_unlock_irq(&rme96->lock); return err; } } else { rate = snd_rme96_capture_getrate(rme96, &isadat); if (rate > 0) { if ((int)params_rate(params) != rate) { spin_unlock_irq(&rme96->lock); return -EIO; } if ((isadat && runtime->hw.channels_min == 2) || (!isadat && runtime->hw.channels_min == 8)) { spin_unlock_irq(&rme96->lock); return -EIO; } } } snd_rme96_setframelog(rme96, params_channels(params), 0); if (rme96->playback_periodsize != 0) { if (params_period_size(params) << rme96->capture_frlog != rme96->playback_periodsize) { spin_unlock_irq(&rme96->lock); return -EBUSY; } } rme96->capture_periodsize = params_period_size(params) << rme96->capture_frlog; snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); spin_unlock_irq(&rme96->lock); return 0; } static void snd_rme96_trigger(struct rme96 *rme96, int op) { if (op & RME96_TB_RESET_PLAYPOS) writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); if (op & RME96_TB_RESET_CAPTUREPOS) writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_IRQ) writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); } if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_IRQ_2) writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); } if (op & RME96_TB_START_PLAYBACK) rme96->wcreg |= RME96_WCR_START; if (op & RME96_TB_STOP_PLAYBACK) rme96->wcreg &= ~RME96_WCR_START; if (op & RME96_TB_START_CAPTURE) rme96->wcreg |= RME96_WCR_START_2; if (op & RME96_TB_STOP_CAPTURE) rme96->wcreg &= ~RME96_WCR_START_2; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static irqreturn_t snd_rme96_interrupt(int irq, void *dev_id) { struct rme96 *rme96 = (struct rme96 *)dev_id; rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); /* fastpath out, to ease interrupt sharing */ if (!((rme96->rcreg & RME96_RCR_IRQ) || (rme96->rcreg & RME96_RCR_IRQ_2))) { return IRQ_NONE; } if (rme96->rcreg & RME96_RCR_IRQ) { /* playback */ snd_pcm_period_elapsed(rme96->playback_substream); writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); } if (rme96->rcreg & RME96_RCR_IRQ_2) { /* capture */ snd_pcm_period_elapsed(rme96->capture_substream); writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); } return IRQ_HANDLED; } static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { .count = ARRAY_SIZE(period_bytes), .list = period_bytes, .mask = 0 }; static void rme96_set_buffer_size_constraint(struct rme96 *rme96, struct snd_pcm_runtime *runtime) { unsigned int size; snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE); size = rme96->playback_periodsize; if (!size) size = rme96->capture_periodsize; if (size) snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, size); else snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); } static int snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); spin_lock_irq(&rme96->lock); if (rme96->playback_substream) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->wcreg &= ~RME96_WCR_ADAT; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); rme96->playback_substream = substream; spin_unlock_irq(&rme96->lock); runtime->hw = snd_rme96_playback_spdif_info; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { rate = snd_rme96_capture_getrate(rme96, &dummy); if (rate > 0) { /* slave clock */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } } rme96_set_buffer_size_constraint(rme96, runtime); rme96->wcreg_spdif_stream = rme96->wcreg_spdif; rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); return 0; } static int snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); runtime->hw = snd_rme96_capture_spdif_info; if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { rate = snd_rme96_capture_getrate(rme96, &isadat); if (rate > 0) { if (isadat) return -EIO; runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } } spin_lock_irq(&rme96->lock); if (rme96->capture_substream) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->capture_substream = substream; spin_unlock_irq(&rme96->lock); rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); spin_lock_irq(&rme96->lock); if (rme96->playback_substream) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->wcreg |= RME96_WCR_ADAT; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); rme96->playback_substream = substream; spin_unlock_irq(&rme96->lock); runtime->hw = snd_rme96_playback_adat_info; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { rate = snd_rme96_capture_getrate(rme96, &dummy); if (rate > 0) { /* slave clock */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } } rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); runtime->hw = snd_rme96_capture_adat_info; if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { /* makes no sense to use analog input. Note that analog expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ return -EIO; } rate = snd_rme96_capture_getrate(rme96, &isadat); if (rate > 0) { if (!isadat) { return -EIO; } runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } spin_lock_irq(&rme96->lock); if (rme96->capture_substream) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->capture_substream = substream; spin_unlock_irq(&rme96->lock); rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_playback_close(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); int spdif = 0; spin_lock_irq(&rme96->lock); if (RME96_ISPLAYING(rme96)) { snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); } rme96->playback_substream = NULL; rme96->playback_periodsize = 0; spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; spin_unlock_irq(&rme96->lock); if (spdif) { rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); } return 0; } static int snd_rme96_capture_close(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISRECORDING(rme96)) { snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); } rme96->capture_substream = NULL; rme96->capture_periodsize = 0; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_playback_prepare(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISPLAYING(rme96)) { snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); } writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_capture_prepare(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISRECORDING(rme96)) { snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); } writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; bool sync; snd_pcm_group_for_each_entry(s, substream) { if (snd_pcm_substream_chip(s) == rme96) snd_pcm_trigger_done(s, substream); } sync = (rme96->playback_substream && rme96->capture_substream) && (rme96->playback_substream->group == rme96->capture_substream->group); switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (!RME96_ISPLAYING(rme96)) { if (substream != rme96->playback_substream) return -EBUSY; snd_rme96_trigger(rme96, sync ? RME96_START_BOTH : RME96_START_PLAYBACK); } break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_STOP: if (RME96_ISPLAYING(rme96)) { if (substream != rme96->playback_substream) return -EBUSY; snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH : RME96_STOP_PLAYBACK); } break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (RME96_ISPLAYING(rme96)) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH : RME96_STOP_PLAYBACK); break; case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!RME96_ISPLAYING(rme96)) snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH : RME96_RESUME_PLAYBACK); break; default: return -EINVAL; } return 0; } static int snd_rme96_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; bool sync; snd_pcm_group_for_each_entry(s, substream) { if (snd_pcm_substream_chip(s) == rme96) snd_pcm_trigger_done(s, substream); } sync = (rme96->playback_substream && rme96->capture_substream) && (rme96->playback_substream->group == rme96->capture_substream->group); switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (!RME96_ISRECORDING(rme96)) { if (substream != rme96->capture_substream) return -EBUSY; snd_rme96_trigger(rme96, sync ? RME96_START_BOTH : RME96_START_CAPTURE); } break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_STOP: if (RME96_ISRECORDING(rme96)) { if (substream != rme96->capture_substream) return -EBUSY; snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH : RME96_STOP_CAPTURE); } break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (RME96_ISRECORDING(rme96)) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH : RME96_STOP_CAPTURE); break; case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!RME96_ISRECORDING(rme96)) snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH : RME96_RESUME_CAPTURE); break; default: return -EINVAL; } return 0; } static snd_pcm_uframes_t snd_rme96_playback_pointer(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return snd_rme96_playback_ptr(rme96); } static snd_pcm_uframes_t snd_rme96_capture_pointer(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return snd_rme96_capture_ptr(rme96); } static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { .open = snd_rme96_playback_spdif_open, .close = snd_rme96_playback_close, .hw_params = snd_rme96_playback_hw_params, .prepare = snd_rme96_playback_prepare, .trigger = snd_rme96_playback_trigger, .pointer = snd_rme96_playback_pointer, .copy = snd_rme96_playback_copy, .fill_silence = snd_rme96_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { .open = snd_rme96_capture_spdif_open, .close = snd_rme96_capture_close, .hw_params = snd_rme96_capture_hw_params, .prepare = snd_rme96_capture_prepare, .trigger = snd_rme96_capture_trigger, .pointer = snd_rme96_capture_pointer, .copy = snd_rme96_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { .open = snd_rme96_playback_adat_open, .close = snd_rme96_playback_close, .hw_params = snd_rme96_playback_hw_params, .prepare = snd_rme96_playback_prepare, .trigger = snd_rme96_playback_trigger, .pointer = snd_rme96_playback_pointer, .copy = snd_rme96_playback_copy, .fill_silence = snd_rme96_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { .open = snd_rme96_capture_adat_open, .close = snd_rme96_capture_close, .hw_params = snd_rme96_capture_hw_params, .prepare = snd_rme96_capture_prepare, .trigger = snd_rme96_capture_trigger, .pointer = snd_rme96_capture_pointer, .copy = snd_rme96_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; static void snd_rme96_free(struct rme96 *rme96) { if (rme96->irq >= 0) { snd_rme96_trigger(rme96, RME96_STOP_BOTH); rme96->areg &= ~RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); } #ifdef CONFIG_PM_SLEEP vfree(rme96->playback_suspend_buffer); vfree(rme96->capture_suspend_buffer); #endif } static void snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) { struct rme96 *rme96 = pcm->private_data; rme96->spdif_pcm = NULL; } static void snd_rme96_free_adat_pcm(struct snd_pcm *pcm) { struct rme96 *rme96 = pcm->private_data; rme96->adat_pcm = NULL; } static int snd_rme96_create(struct rme96 *rme96) { struct pci_dev *pci = rme96->pci; int err; rme96->irq = -1; spin_lock_init(&rme96->lock); err = pcim_enable_device(pci); if (err < 0) return err; err = pci_request_regions(pci, "RME96"); if (err < 0) return err; rme96->port = pci_resource_start(rme96->pci, 0); rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE); if (!rme96->iobase) { dev_err(rme96->card->dev, "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1); return -EBUSY; } if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt, IRQF_SHARED, KBUILD_MODNAME, rme96)) { dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } rme96->irq = pci->irq; rme96->card->sync_irq = rme96->irq; /* read the card's revision number */ pci_read_config_byte(pci, 8, &rme96->rev); /* set up ALSA pcm device for S/PDIF */ err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1, 1, &rme96->spdif_pcm); if (err < 0) return err; rme96->spdif_pcm->private_data = rme96; rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); rme96->spdif_pcm->info_flags = 0; /* set up ALSA pcm device for ADAT */ if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { /* ADAT is not available on the base model */ rme96->adat_pcm = NULL; } else { err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1, 1, &rme96->adat_pcm); if (err < 0) return err; rme96->adat_pcm->private_data = rme96; rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); rme96->adat_pcm->info_flags = 0; } rme96->playback_periodsize = 0; rme96->capture_periodsize = 0; /* make sure playback/capture is stopped, if by some reason active */ snd_rme96_trigger(rme96, RME96_STOP_BOTH); /* set default values in registers */ rme96->wcreg = RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ RME96_WCR_SEL | /* normal playback */ RME96_WCR_MASTER | /* set to master clock mode */ RME96_WCR_INP_0; /* set coaxial input */ rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset the ADC */ writel(rme96->areg | RME96_AR_PD2, rme96->iobase + RME96_IO_ADDITIONAL_REG); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset and enable the DAC (order is important). */ snd_rme96_reset_dac(rme96); rme96->areg |= RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset playback and record buffer pointers */ writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); /* reset volume */ rme96->vol[0] = rme96->vol[1] = 0; if (RME96_HAS_ANALOG_OUT(rme96)) { snd_rme96_apply_dac_volume(rme96); } /* init switch interface */ err = snd_rme96_create_switches(rme96->card, rme96); if (err < 0) return err; /* init proc interface */ snd_rme96_proc_init(rme96); return 0; } /* * proc interface */ static void snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { int n; struct rme96 *rme96 = entry->private_data; rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_iprintf(buffer, rme96->card->longname); snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); snd_iprintf(buffer, "\nGeneral settings\n"); if (rme96->wcreg & RME96_WCR_IDIS) { snd_iprintf(buffer, " period size: N/A (interrupts " "disabled)\n"); } else if (rme96->wcreg & RME96_WCR_ISEL) { snd_iprintf(buffer, " period size: 2048 bytes\n"); } else { snd_iprintf(buffer, " period size: 8192 bytes\n"); } snd_iprintf(buffer, "\nInput settings\n"); switch (snd_rme96_getinputtype(rme96)) { case RME96_INPUT_OPTICAL: snd_iprintf(buffer, " input: optical"); break; case RME96_INPUT_COAXIAL: snd_iprintf(buffer, " input: coaxial"); break; case RME96_INPUT_INTERNAL: snd_iprintf(buffer, " input: internal"); break; case RME96_INPUT_XLR: snd_iprintf(buffer, " input: XLR"); break; case RME96_INPUT_ANALOG: snd_iprintf(buffer, " input: analog"); break; } if (snd_rme96_capture_getrate(rme96, &n) < 0) { snd_iprintf(buffer, "\n sample rate: no valid signal\n"); } else { if (n) { snd_iprintf(buffer, " (8 channels)\n"); } else { snd_iprintf(buffer, " (2 channels)\n"); } snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme96_capture_getrate(rme96, &n)); } if (rme96->wcreg & RME96_WCR_MODE24_2) { snd_iprintf(buffer, " sample format: 24 bit\n"); } else { snd_iprintf(buffer, " sample format: 16 bit\n"); } snd_iprintf(buffer, "\nOutput settings\n"); if (rme96->wcreg & RME96_WCR_SEL) { snd_iprintf(buffer, " output signal: normal playback\n"); } else { snd_iprintf(buffer, " output signal: same as input\n"); } snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme96_playback_getrate(rme96)); if (rme96->wcreg & RME96_WCR_MODE24) { snd_iprintf(buffer, " sample format: 24 bit\n"); } else { snd_iprintf(buffer, " sample format: 16 bit\n"); } if (rme96->areg & RME96_AR_WSEL) { snd_iprintf(buffer, " sample clock source: word clock\n"); } else if (rme96->wcreg & RME96_WCR_MASTER) { snd_iprintf(buffer, " sample clock source: internal\n"); } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); } else { snd_iprintf(buffer, " sample clock source: autosync\n"); } if (rme96->wcreg & RME96_WCR_PRO) { snd_iprintf(buffer, " format: AES/EBU (professional)\n"); } else { snd_iprintf(buffer, " format: IEC958 (consumer)\n"); } if (rme96->wcreg & RME96_WCR_EMP) { snd_iprintf(buffer, " emphasis: on\n"); } else { snd_iprintf(buffer, " emphasis: off\n"); } if (rme96->wcreg & RME96_WCR_DOLBY) { snd_iprintf(buffer, " non-audio (dolby): on\n"); } else { snd_iprintf(buffer, " non-audio (dolby): off\n"); } if (RME96_HAS_ANALOG_IN(rme96)) { snd_iprintf(buffer, "\nAnalog output settings\n"); switch (snd_rme96_getmontracks(rme96)) { case RME96_MONITOR_TRACKS_1_2: snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); break; case RME96_MONITOR_TRACKS_3_4: snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); break; case RME96_MONITOR_TRACKS_5_6: snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); break; case RME96_MONITOR_TRACKS_7_8: snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); break; } switch (snd_rme96_getattenuation(rme96)) { case RME96_ATTENUATION_0: snd_iprintf(buffer, " attenuation: 0 dB\n"); break; case RME96_ATTENUATION_6: snd_iprintf(buffer, " attenuation: -6 dB\n"); break; case RME96_ATTENUATION_12: snd_iprintf(buffer, " attenuation: -12 dB\n"); break; case RME96_ATTENUATION_18: snd_iprintf(buffer, " attenuation: -18 dB\n"); break; } snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); } } static void snd_rme96_proc_init(struct rme96 *rme96) { snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read); } /* * control interface */ #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info static int snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; spin_lock_irq(&rme96->lock); val = (rme96->wcreg & ~RME96_WCR_SEL) | val; change = val != rme96->wcreg; rme96->wcreg = val; writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const _texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" }; struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); const char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] }; int num_items; switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: num_items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: num_items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { /* PST */ num_items = 4; texts[3] = _texts[4]; /* Analog instead of XLR */ } else { /* PAD */ num_items = 5; } break; default: snd_BUG(); return -EINVAL; } return snd_ctl_enum_info(uinfo, 1, num_items, texts); } static int snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int items = 3; spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; } items = 4; } else { items = 5; } break; default: snd_BUG(); break; } if (ucontrol->value.enumerated.item[0] >= items) { ucontrol->value.enumerated.item[0] = items - 1; } spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change, items = 3; switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { items = 4; } else { items = 5; } break; default: snd_BUG(); break; } val = ucontrol->value.enumerated.item[0] % items; /* special case for PST */ if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { if (val == RME96_INPUT_XLR) { val = RME96_INPUT_ANALOG; } } spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getinputtype(rme96); snd_rme96_setinputtype(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 3; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getclockmode(rme96); snd_rme96_setclockmode(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" }; return snd_ctl_enum_info(uinfo, 1, 4, texts); } static int snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 4; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getattenuation(rme96); snd_rme96_setattenuation(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; return snd_ctl_enum_info(uinfo, 1, 4, texts); } static int snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 4; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getmontracks(rme96); snd_rme96_setmontracks(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) { u32 val = 0; val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; if (val & RME96_WCR_PRO) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; else val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; return val; } static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) { aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); if (val & RME96_WCR_PRO) aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; else aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; } static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); return 0; } static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme96->lock); change = val != rme96->wcreg_spdif; rme96->wcreg_spdif = val; spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); return 0; } static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme96->lock); change = val != rme96->wcreg_spdif_stream; rme96->wcreg_spdif_stream = val; rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); rme96->wcreg |= val; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = kcontrol->private_value; return 0; } static int snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); return 0; } static int snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); u->value.integer.value[0] = rme96->vol[0]; u->value.integer.value[1] = rme96->vol[1]; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change = 0; unsigned int vol, maxvol; if (!RME96_HAS_ANALOG_OUT(rme96)) return -EINVAL; maxvol = RME96_185X_MAX_OUT(rme96); spin_lock_irq(&rme96->lock); vol = u->value.integer.value[0]; if (vol != rme96->vol[0] && vol <= maxvol) { rme96->vol[0] = vol; change = 1; } vol = u->value.integer.value[1]; if (vol != rme96->vol[1] && vol <= maxvol) { rme96->vol[1] = vol; change = 1; } if (change) snd_rme96_apply_dac_volume(rme96); spin_unlock_irq(&rme96->lock); return change; } static const struct snd_kcontrol_new snd_rme96_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = snd_rme96_control_spdif_info, .get = snd_rme96_control_spdif_get, .put = snd_rme96_control_spdif_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), .info = snd_rme96_control_spdif_stream_info, .get = snd_rme96_control_spdif_stream_get, .put = snd_rme96_control_spdif_stream_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), .info = snd_rme96_control_spdif_mask_info, .get = snd_rme96_control_spdif_mask_get, .private_value = IEC958_AES0_NONAUDIO | IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), .info = snd_rme96_control_spdif_mask_info, .get = snd_rme96_control_spdif_mask_get, .private_value = IEC958_AES0_NONAUDIO | IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Input Connector", .info = snd_rme96_info_inputtype_control, .get = snd_rme96_get_inputtype_control, .put = snd_rme96_put_inputtype_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Loopback Input", .info = snd_rme96_info_loopback_control, .get = snd_rme96_get_loopback_control, .put = snd_rme96_put_loopback_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Sample Clock Source", .info = snd_rme96_info_clockmode_control, .get = snd_rme96_get_clockmode_control, .put = snd_rme96_put_clockmode_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Monitor Tracks", .info = snd_rme96_info_montracks_control, .get = snd_rme96_get_montracks_control, .put = snd_rme96_put_montracks_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Attenuation", .info = snd_rme96_info_attenuation_control, .get = snd_rme96_get_attenuation_control, .put = snd_rme96_put_attenuation_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DAC Playback Volume", .info = snd_rme96_dac_volume_info, .get = snd_rme96_dac_volume_get, .put = snd_rme96_dac_volume_put } }; static int snd_rme96_create_switches(struct snd_card *card, struct rme96 *rme96) { int idx, err; struct snd_kcontrol *kctl; for (idx = 0; idx < 7; idx++) { kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96); err = snd_ctl_add(card, kctl); if (err < 0) return err; if (idx == 1) /* IEC958 (S/PDIF) Stream */ rme96->spdif_ctl = kctl; } if (RME96_HAS_ANALOG_OUT(rme96)) { for (idx = 7; idx < 10; idx++) { err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96)); if (err < 0) return err; } } return 0; } /* * Card initialisation */ #ifdef CONFIG_PM_SLEEP static int rme96_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct rme96 *rme96 = card->private_data; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); /* save capture & playback pointers */ rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) & RME96_RCR_AUDIO_ADDR_MASK; rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) & RME96_RCR_AUDIO_ADDR_MASK; /* save playback and capture buffers */ memcpy_fromio(rme96->playback_suspend_buffer, rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); memcpy_fromio(rme96->capture_suspend_buffer, rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); /* disable the DAC */ rme96->areg &= ~RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); return 0; } static int rme96_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct rme96 *rme96 = card->private_data; /* reset playback and record buffer pointers */ writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS + rme96->playback_pointer); writel(0, rme96->iobase + RME96_IO_SET_REC_POS + rme96->capture_pointer); /* restore playback and capture buffers */ memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); /* reset the ADC */ writel(rme96->areg | RME96_AR_PD2, rme96->iobase + RME96_IO_ADDITIONAL_REG); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset and enable DAC, restore analog volume */ snd_rme96_reset_dac(rme96); rme96->areg |= RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); if (RME96_HAS_ANALOG_OUT(rme96)) { usleep_range(3000, 10000); snd_rme96_apply_dac_volume(rme96); } snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); #define RME96_PM_OPS &rme96_pm #else #define RME96_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static void snd_rme96_card_free(struct snd_card *card) { snd_rme96_free(card->private_data); } static int __snd_rme96_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct rme96 *rme96; struct snd_card *card; int err; u8 val; if (dev >= SNDRV_CARDS) { return -ENODEV; } if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*rme96), &card); if (err < 0) return err; card->private_free = snd_rme96_card_free; rme96 = card->private_data; rme96->card = card; rme96->pci = pci; err = snd_rme96_create(rme96); if (err) return err; #ifdef CONFIG_PM_SLEEP rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); if (!rme96->playback_suspend_buffer) return -ENOMEM; rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); if (!rme96->capture_suspend_buffer) return -ENOMEM; #endif strcpy(card->driver, "Digi96"); switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: strcpy(card->shortname, "RME Digi96"); break; case PCI_DEVICE_ID_RME_DIGI96_8: strcpy(card->shortname, "RME Digi96/8"); break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: strcpy(card->shortname, "RME Digi96/8 PRO"); break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: pci_read_config_byte(rme96->pci, 8, &val); if (val < 5) { strcpy(card->shortname, "RME Digi96/8 PAD"); } else { strcpy(card->shortname, "RME Digi96/8 PST"); } break; } sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, rme96->port, rme96->irq); err = snd_card_register(card); if (err) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_rme96_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id)); } static struct pci_driver rme96_driver = { .name = KBUILD_MODNAME, .id_table = snd_rme96_ids, .probe = snd_rme96_probe, .driver = { .pm = RME96_PM_OPS, }, }; module_pci_driver(rme96_driver);
linux-master
sound/pci/rme96.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Cirrus Logic CS4281 based PCI soundcard * Copyright (c) by Jaroslav Kysela <[email protected]>, */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <sound/core.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/rawmidi.h> #include <sound/ac97_codec.h> #include <sound/tlv.h> #include <sound/opl3.h> #include <sound/initval.h> MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("Cirrus Logic CS4281"); MODULE_LICENSE("GPL"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ static bool dual_codec[SNDRV_CARDS]; /* dual codec */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); module_param_array(dual_codec, bool, NULL, 0444); MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); /* * Direct registers */ #define CS4281_BA0_SIZE 0x1000 #define CS4281_BA1_SIZE 0x10000 /* * BA0 registers */ #define BA0_HISR 0x0000 /* Host Interrupt Status Register */ #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */ #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */ #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */ #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */ #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */ #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */ #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */ #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */ #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */ #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */ #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */ #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */ #define BA0_HICR 0x0008 /* Host Interrupt Control Register */ #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */ #define BA0_HICR_IEV (1<<0) /* INTENA Value */ #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */ #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ /* Use same contants as for BA0_HISR */ #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */ #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */ #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */ #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */ #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */ #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */ #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */ #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */ #define BA0_HDSR_DRUN (1<<15) /* DMA Running */ #define BA0_HDSR_RQ (1<<7) /* Pending Request */ #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */ #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */ #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */ #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */ #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */ #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */ #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */ #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */ #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */ #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */ #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */ #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */ #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */ #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */ #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */ #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */ #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */ #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */ #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */ #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */ #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */ #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */ #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */ #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */ #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */ #define BA0_DMR_POLL (1<<28) /* Enable poll mode */ #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */ #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */ #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */ #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */ #define BA0_DMR_USIGN (1<<19) /* Unsigned */ #define BA0_DMR_BEND (1<<18) /* Big Endian */ #define BA0_DMR_MONO (1<<17) /* Mono */ #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */ #define BA0_DMR_TYPE_DEMAND (0<<6) #define BA0_DMR_TYPE_SINGLE (1<<6) #define BA0_DMR_TYPE_BLOCK (2<<6) #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */ #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */ #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */ #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */ #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */ #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */ #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */ #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */ #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */ #define BA0_FCR0 0x0180 /* FIFO Control 0 */ #define BA0_FCR1 0x0184 /* FIFO Control 1 */ #define BA0_FCR2 0x0188 /* FIFO Control 2 */ #define BA0_FCR3 0x018c /* FIFO Control 3 */ #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */ #define BA0_FCR_DACZ (1<<30) /* DAC Zero */ #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */ #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */ #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */ #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */ #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */ #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */ #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */ #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */ #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */ #define BA0_FCHS 0x020c /* FIFO Channel Status */ #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */ #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */ #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */ #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */ #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */ #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */ #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */ #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */ #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */ #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */ #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */ #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */ #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */ #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */ #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */ #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */ #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */ #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */ #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */ #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */ #define BA0_PMCS 0x0344 /* Power Management Control/Status */ #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */ #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */ #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */ #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */ #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */ #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */ #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */ #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */ #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */ #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */ #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ #define BA0_IISR 0x03f4 /* ISA Interrupt Select */ #define BA0_TMS 0x03f8 /* Test Register */ #define BA0_SSVID 0x03fc /* Subsystem ID register */ #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */ #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */ #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */ #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */ #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */ #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */ #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */ #define BA0_FRR 0x0410 /* Feature Reporting Register */ #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */ #define BA0_SERMC 0x0420 /* Serial Port Master Control */ #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */ #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */ #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */ #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */ #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */ #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */ #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */ #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */ #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */ #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */ #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */ #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */ #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */ #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */ #define BA0_SERC1_AC97 (1<<1) #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */ #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */ #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */ #define BA0_SERC2_AC97 (1<<1) #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */ #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */ #define BA0_ACCTL 0x0460 /* AC'97 Control */ #define BA0_ACCTL_TC (1<<6) /* Target Codec */ #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */ #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */ #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */ #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */ #define BA0_ACSTS 0x0464 /* AC'97 Status */ #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */ #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */ #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */ #define BA0_ACOSV_SLV(x) (1<<((x)-3)) #define BA0_ACCAD 0x046c /* AC'97 Command Address */ #define BA0_ACCDA 0x0470 /* AC'97 Command Data */ #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */ #define BA0_ACISV_SLV(x) (1<<((x)-3)) #define BA0_ACSAD 0x0478 /* AC'97 Status Address */ #define BA0_ACSDA 0x047c /* AC'97 Status Data */ #define BA0_JSPT 0x0480 /* Joystick poll/trigger */ #define BA0_JSCTL 0x0484 /* Joystick control */ #define BA0_JSC1 0x0488 /* Joystick control */ #define BA0_JSC2 0x048c /* Joystick control */ #define BA0_JSIO 0x04a0 #define BA0_MIDCR 0x0490 /* MIDI Control */ #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */ #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */ #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */ #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */ #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */ #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */ #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */ #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */ #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */ #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */ #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */ #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */ #define BA0_MIDWP 0x0498 /* MIDI Write */ #define BA0_MIDRP 0x049c /* MIDI Read (ro) */ #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */ #define BA0_AODSD1_NDS(x) (1<<((x)-3)) #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */ #define BA0_AODSD2_NDS(x) (1<<((x)-3)) #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */ #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */ #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */ #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */ #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */ #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */ #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */ #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */ #define BA0_FMDP 0x0734 /* FM Data Port */ #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */ #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */ #define BA0_SSPM 0x0740 /* Sound System Power Management */ #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */ #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */ #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */ #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */ #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */ #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */ #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */ #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */ #define BA0_SSCR 0x074c /* Sound System Control Register */ #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */ #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */ #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */ #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */ #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */ #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */ #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */ #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */ #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */ #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */ #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */ #define BA0_SRCSA 0x075c /* SRC Slot Assignments */ #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */ #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */ #define BA0_PASR 0x0768 /* playback sample rate */ #define BA0_CASR 0x076C /* capture sample rate */ /* Source Slot Numbers - Playback */ #define SRCSLOT_LEFT_PCM_PLAYBACK 0 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1 #define SRCSLOT_PHONE_LINE_1_DAC 2 #define SRCSLOT_CENTER_PCM_PLAYBACK 3 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5 #define SRCSLOT_LFE_PCM_PLAYBACK 6 #define SRCSLOT_PHONE_LINE_2_DAC 7 #define SRCSLOT_HEADSET_DAC 8 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */ #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */ /* Source Slot Numbers - Capture */ #define SRCSLOT_LEFT_PCM_RECORD 10 #define SRCSLOT_RIGHT_PCM_RECORD 11 #define SRCSLOT_PHONE_LINE_1_ADC 12 #define SRCSLOT_MIC_ADC 13 #define SRCSLOT_PHONE_LINE_2_ADC 17 #define SRCSLOT_HEADSET_ADC 18 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22 #define SRCSLOT_SECONDARY_MIC_ADC 23 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27 #define SRCSLOT_SECONDARY_HEADSET_ADC 28 /* Source Slot Numbers - Others */ #define SRCSLOT_POWER_DOWN 31 /* MIDI modes */ #define CS4281_MODE_OUTPUT (1<<0) #define CS4281_MODE_INPUT (1<<1) /* joystick bits */ /* Bits for JSPT */ #define JSPT_CAX 0x00000001 #define JSPT_CAY 0x00000002 #define JSPT_CBX 0x00000004 #define JSPT_CBY 0x00000008 #define JSPT_BA1 0x00000010 #define JSPT_BA2 0x00000020 #define JSPT_BB1 0x00000040 #define JSPT_BB2 0x00000080 /* Bits for JSCTL */ #define JSCTL_SP_MASK 0x00000003 #define JSCTL_SP_SLOW 0x00000000 #define JSCTL_SP_MEDIUM_SLOW 0x00000001 #define JSCTL_SP_MEDIUM_FAST 0x00000002 #define JSCTL_SP_FAST 0x00000003 #define JSCTL_ARE 0x00000004 /* Data register pairs masks */ #define JSC1_Y1V_MASK 0x0000FFFF #define JSC1_X1V_MASK 0xFFFF0000 #define JSC1_Y1V_SHIFT 0 #define JSC1_X1V_SHIFT 16 #define JSC2_Y2V_MASK 0x0000FFFF #define JSC2_X2V_MASK 0xFFFF0000 #define JSC2_Y2V_SHIFT 0 #define JSC2_X2V_SHIFT 16 /* JS GPIO */ #define JSIO_DAX 0x00000001 #define JSIO_DAY 0x00000002 #define JSIO_DBX 0x00000004 #define JSIO_DBY 0x00000008 #define JSIO_AXOE 0x00000010 #define JSIO_AYOE 0x00000020 #define JSIO_BXOE 0x00000040 #define JSIO_BYOE 0x00000080 /* * */ struct cs4281_dma { struct snd_pcm_substream *substream; unsigned int regDBA; /* offset to DBA register */ unsigned int regDCA; /* offset to DCA register */ unsigned int regDBC; /* offset to DBC register */ unsigned int regDCC; /* offset to DCC register */ unsigned int regDMR; /* offset to DMR register */ unsigned int regDCR; /* offset to DCR register */ unsigned int regHDSR; /* offset to HDSR register */ unsigned int regFCR; /* offset to FCR register */ unsigned int regFSIC; /* offset to FSIC register */ unsigned int valDMR; /* DMA mode */ unsigned int valDCR; /* DMA command */ unsigned int valFCR; /* FIFO control */ unsigned int fifo_offset; /* FIFO offset within BA1 */ unsigned char left_slot; /* FIFO left slot */ unsigned char right_slot; /* FIFO right slot */ int frag; /* period number */ }; #define SUSPEND_REGISTERS 20 struct cs4281 { int irq; void __iomem *ba0; /* virtual (accessible) address */ void __iomem *ba1; /* virtual (accessible) address */ unsigned long ba0_addr; unsigned long ba1_addr; int dual_codec; struct snd_ac97_bus *ac97_bus; struct snd_ac97 *ac97; struct snd_ac97 *ac97_secondary; struct pci_dev *pci; struct snd_card *card; struct snd_pcm *pcm; struct snd_rawmidi *rmidi; struct snd_rawmidi_substream *midi_input; struct snd_rawmidi_substream *midi_output; struct cs4281_dma dma[4]; unsigned char src_left_play_slot; unsigned char src_right_play_slot; unsigned char src_left_rec_slot; unsigned char src_right_rec_slot; unsigned int spurious_dhtc_irq; unsigned int spurious_dtc_irq; spinlock_t reg_lock; unsigned int midcr; unsigned int uartm; struct gameport *gameport; #ifdef CONFIG_PM_SLEEP u32 suspend_regs[SUSPEND_REGISTERS]; #endif }; static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id); static const struct pci_device_id snd_cs4281_ids[] = { { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_cs4281_ids); /* * constants */ #define CS4281_FIFO_SIZE 32 /* * common I/O routines */ static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset, unsigned int val) { writel(val, chip->ba0 + offset); } static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset) { return readl(chip->ba0 + offset); } static void snd_cs4281_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { /* * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 * 3. Write ACCTL = Control Register = 460h for initiating the write * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h * 5. if DCV not cleared, break and return error */ struct cs4281 *chip = ac97->private_data; int count; /* * Setup the AC97 control registers on the CS461x to send the * appropriate command to the AC97 to perform the read. * ACCAD = Command Address Register = 46Ch * ACCDA = Command Data Register = 470h * ACCTL = Control Register = 460h * set DCV - will clear when process completed * reset CRW - Write command * set VFRM - valid frame enabled * set ESYN - ASYNC generation enabled * set RSTN - ARST# inactive, AC97 codec not reset */ snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); for (count = 0; count < 2000; count++) { /* * First, we want to wait for a short time. */ udelay(10); /* * Now, check to see if the write has completed. * ACCTL = 460h, DCV should be reset by now and 460h = 07h */ if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { return; } } dev_err(chip->card->dev, "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); } static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { struct cs4281 *chip = ac97->private_data; int count; unsigned short result; // FIXME: volatile is necessary in the following due to a bug of // some gcc versions volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num; /* * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 * 3. Write ACCTL = Control Register = 460h for initiating the write * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h * 5. if DCV not cleared, break and return error * 6. Read ACSTS = Status Register = 464h, check VSTS bit */ snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); /* * Setup the AC97 control registers on the CS461x to send the * appropriate command to the AC97 to perform the read. * ACCAD = Command Address Register = 46Ch * ACCDA = Command Data Register = 470h * ACCTL = Control Register = 460h * set DCV - will clear when process completed * set CRW - Read command * set VFRM - valid frame enabled * set ESYN - ASYNC generation enabled * set RSTN - ARST# inactive, AC97 codec not reset */ snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | (ac97_num ? BA0_ACCTL_TC : 0)); /* * Wait for the read to occur. */ for (count = 0; count < 500; count++) { /* * First, we want to wait for a short time. */ udelay(10); /* * Now, check to see if the read has completed. * ACCTL = 460h, DCV should be reset by now and 460h = 17h */ if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) goto __ok1; } dev_err(chip->card->dev, "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); result = 0xffff; goto __end; __ok1: /* * Wait for the valid status bit to go active. */ for (count = 0; count < 100; count++) { /* * Read the AC97 status register. * ACSTS = Status Register = 464h * VSTS - Valid Status */ if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) goto __ok2; udelay(10); } dev_err(chip->card->dev, "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); result = 0xffff; goto __end; __ok2: /* * Read the data returned from the AC97 register. * ACSDA = Status Data Register = 474h */ result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); __end: return result; } /* * PCM part */ static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd) { struct cs4281_dma *dma = substream->runtime->private_data; struct cs4281 *chip = snd_pcm_substream_chip(substream); spin_lock(&chip->reg_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_PAUSE_PUSH: dma->valDCR |= BA0_DCR_MSK; dma->valFCR |= BA0_FCR_FEN; break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: dma->valDCR &= ~BA0_DCR_MSK; dma->valFCR &= ~BA0_FCR_FEN; break; case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); dma->valDMR |= BA0_DMR_DMA; dma->valDCR &= ~BA0_DCR_MSK; dma->valFCR |= BA0_FCR_FEN; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); dma->valDCR |= BA0_DCR_MSK; dma->valFCR &= ~BA0_FCR_FEN; /* Leave wave playback FIFO enabled for FM */ if (dma->regFCR != BA0_FCR0) dma->valFCR &= ~BA0_FCR_FEN; break; default: spin_unlock(&chip->reg_lock); return -EINVAL; } snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); spin_unlock(&chip->reg_lock); return 0; } static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) { unsigned int val; if (real_rate) *real_rate = rate; /* special "hardcoded" rates */ switch (rate) { case 8000: return 5; case 11025: return 4; case 16000: return 3; case 22050: return 2; case 44100: return 1; case 48000: return 0; default: break; } val = 1536000 / rate; if (real_rate) *real_rate = 1536000 / val; return val; } static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, struct snd_pcm_runtime *runtime, int capture, int src) { int rec_mono; dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); if (runtime->channels == 1) dma->valDMR |= BA0_DMR_MONO; if (snd_pcm_format_unsigned(runtime->format) > 0) dma->valDMR |= BA0_DMR_USIGN; if (snd_pcm_format_big_endian(runtime->format) > 0) dma->valDMR |= BA0_DMR_BEND; switch (snd_pcm_format_width(runtime->format)) { case 8: dma->valDMR |= BA0_DMR_SIZE8; if (runtime->channels == 1) dma->valDMR |= BA0_DMR_SWAPC; break; case 32: dma->valDMR |= BA0_DMR_SIZE20; break; } dma->frag = 0; /* for workaround */ dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; if (runtime->buffer_size != runtime->period_size) dma->valDCR |= BA0_DCR_HTCIE; /* Initialize DMA */ snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | (chip->src_right_play_slot << 8) | (chip->src_left_rec_slot << 16) | ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); if (!src) goto __skip_src; if (!capture) { if (dma->left_slot == chip->src_left_play_slot) { unsigned int val = snd_cs4281_rate(runtime->rate, NULL); snd_BUG_ON(dma->right_slot != chip->src_right_play_slot); snd_cs4281_pokeBA0(chip, BA0_DACSR, val); } } else { if (dma->left_slot == chip->src_left_rec_slot) { unsigned int val = snd_cs4281_rate(runtime->rate, NULL); snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot); snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); } } __skip_src: /* Deactivate wave playback FIFO before changing slot assignments */ if (dma->regFCR == BA0_FCR0) snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); /* Initialize FIFO */ dma->valFCR = BA0_FCR_LS(dma->left_slot) | BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | BA0_FCR_SZ(CS4281_FIFO_SIZE) | BA0_FCR_OF(dma->fifo_offset); snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); /* Activate FIFO again for FM playback */ if (dma->regFCR == BA0_FCR0) snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); /* Clear FIFO Status and Interrupt Control Register */ snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); } static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct cs4281_dma *dma = runtime->private_data; struct cs4281 *chip = snd_pcm_substream_chip(substream); spin_lock_irq(&chip->reg_lock); snd_cs4281_mode(chip, dma, runtime, 0, 1); spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct cs4281_dma *dma = runtime->private_data; struct cs4281 *chip = snd_pcm_substream_chip(substream); spin_lock_irq(&chip->reg_lock); snd_cs4281_mode(chip, dma, runtime, 1, 1); spin_unlock_irq(&chip->reg_lock); return 0; } static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct cs4281_dma *dma = runtime->private_data; struct cs4281 *chip = snd_pcm_substream_chip(substream); /* dev_dbg(chip->card->dev, "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); */ return runtime->buffer_size - snd_cs4281_peekBA0(chip, dma->regDCC) - 1; } static const struct snd_pcm_hardware snd_cs4281_playback = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (512*1024), .period_bytes_min = 64, .period_bytes_max = (512*1024), .periods_min = 1, .periods_max = 2, .fifo_size = CS4281_FIFO_SIZE, }; static const struct snd_pcm_hardware snd_cs4281_capture = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (512*1024), .period_bytes_min = 64, .period_bytes_max = (512*1024), .periods_min = 1, .periods_max = 2, .fifo_size = CS4281_FIFO_SIZE, }; static int snd_cs4281_playback_open(struct snd_pcm_substream *substream) { struct cs4281 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct cs4281_dma *dma; dma = &chip->dma[0]; dma->substream = substream; dma->left_slot = 0; dma->right_slot = 1; runtime->private_data = dma; runtime->hw = snd_cs4281_playback; /* should be detected from the AC'97 layer, but it seems that although CS4297A rev B reports 18-bit ADC resolution, samples are 20-bit */ snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); return 0; } static int snd_cs4281_capture_open(struct snd_pcm_substream *substream) { struct cs4281 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct cs4281_dma *dma; dma = &chip->dma[1]; dma->substream = substream; dma->left_slot = 10; dma->right_slot = 11; runtime->private_data = dma; runtime->hw = snd_cs4281_capture; /* should be detected from the AC'97 layer, but it seems that although CS4297A rev B reports 18-bit ADC resolution, samples are 20-bit */ snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); return 0; } static int snd_cs4281_playback_close(struct snd_pcm_substream *substream) { struct cs4281_dma *dma = substream->runtime->private_data; dma->substream = NULL; return 0; } static int snd_cs4281_capture_close(struct snd_pcm_substream *substream) { struct cs4281_dma *dma = substream->runtime->private_data; dma->substream = NULL; return 0; } static const struct snd_pcm_ops snd_cs4281_playback_ops = { .open = snd_cs4281_playback_open, .close = snd_cs4281_playback_close, .prepare = snd_cs4281_playback_prepare, .trigger = snd_cs4281_trigger, .pointer = snd_cs4281_pointer, }; static const struct snd_pcm_ops snd_cs4281_capture_ops = { .open = snd_cs4281_capture_open, .close = snd_cs4281_capture_close, .prepare = snd_cs4281_capture_prepare, .trigger = snd_cs4281_trigger, .pointer = snd_cs4281_pointer, }; static int snd_cs4281_pcm(struct cs4281 *chip, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, "CS4281"); chip->pcm = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 512*1024); return 0; } /* * Mixer section */ #define CS_VOL_MASK 0x1f static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = CS_VOL_MASK; return 0; } static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cs4281 *chip = snd_kcontrol_chip(kcontrol); int regL = (kcontrol->private_value >> 16) & 0xffff; int regR = kcontrol->private_value & 0xffff; int volL, volR; volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); ucontrol->value.integer.value[0] = volL; ucontrol->value.integer.value[1] = volR; return 0; } static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct cs4281 *chip = snd_kcontrol_chip(kcontrol); int change = 0; int regL = (kcontrol->private_value >> 16) & 0xffff; int regR = kcontrol->private_value & 0xffff; int volL, volR; volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); if (ucontrol->value.integer.value[0] != volL) { volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); snd_cs4281_pokeBA0(chip, regL, volL); change = 1; } if (ucontrol->value.integer.value[1] != volR) { volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); snd_cs4281_pokeBA0(chip, regR, volR); change = 1; } return change; } static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0); static const struct snd_kcontrol_new snd_cs4281_fm_vol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Synth Playback Volume", .info = snd_cs4281_info_volume, .get = snd_cs4281_get_volume, .put = snd_cs4281_put_volume, .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), .tlv = { .p = db_scale_dsp }, }; static const struct snd_kcontrol_new snd_cs4281_pcm_vol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "PCM Stream Playback Volume", .info = snd_cs4281_info_volume, .get = snd_cs4281_get_volume, .put = snd_cs4281_put_volume, .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), .tlv = { .p = db_scale_dsp }, }; static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus) { struct cs4281 *chip = bus->private_data; chip->ac97_bus = NULL; } static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97) { struct cs4281 *chip = ac97->private_data; if (ac97->num) chip->ac97_secondary = NULL; else chip->ac97 = NULL; } static int snd_cs4281_mixer(struct cs4281 *chip) { struct snd_card *card = chip->card; struct snd_ac97_template ac97; int err; static const struct snd_ac97_bus_ops ops = { .write = snd_cs4281_ac97_write, .read = snd_cs4281_ac97_read, }; err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus); if (err < 0) return err; chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; ac97.private_free = snd_cs4281_mixer_free_ac97; err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); if (err < 0) return err; if (chip->dual_codec) { ac97.num = 1; err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary); if (err < 0) return err; } err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip)); if (err < 0) return err; err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip)); if (err < 0) return err; return 0; } /* * proc interface */ static void snd_cs4281_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct cs4281 *chip = entry->private_data; snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); } static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry, void *file_private_data, struct file *file, char __user *buf, size_t count, loff_t pos) { struct cs4281 *chip = entry->private_data; if (copy_to_user_fromio(buf, chip->ba0 + pos, count)) return -EFAULT; return count; } static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry, void *file_private_data, struct file *file, char __user *buf, size_t count, loff_t pos) { struct cs4281 *chip = entry->private_data; if (copy_to_user_fromio(buf, chip->ba1 + pos, count)) return -EFAULT; return count; } static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = { .read = snd_cs4281_BA0_read, }; static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = { .read = snd_cs4281_BA1_read, }; static void snd_cs4281_proc_init(struct cs4281 *chip) { struct snd_info_entry *entry; snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read); if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { entry->content = SNDRV_INFO_CONTENT_DATA; entry->private_data = chip; entry->c.ops = &snd_cs4281_proc_ops_BA0; entry->size = CS4281_BA0_SIZE; } if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { entry->content = SNDRV_INFO_CONTENT_DATA; entry->private_data = chip; entry->c.ops = &snd_cs4281_proc_ops_BA1; entry->size = CS4281_BA1_SIZE; } } /* * joystick support */ #if IS_REACHABLE(CONFIG_GAMEPORT) static void snd_cs4281_gameport_trigger(struct gameport *gameport) { struct cs4281 *chip = gameport_get_port_data(gameport); if (snd_BUG_ON(!chip)) return; snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); } static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) { struct cs4281 *chip = gameport_get_port_data(gameport); if (snd_BUG_ON(!chip)) return 0; return snd_cs4281_peekBA0(chip, BA0_JSPT); } #ifdef COOKED_MODE static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) { struct cs4281 *chip = gameport_get_port_data(gameport); unsigned js1, js2, jst; if (snd_BUG_ON(!chip)) return 0; js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); jst = snd_cs4281_peekBA0(chip, BA0_JSPT); *buttons = (~jst >> 4) & 0x0F; axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; for (jst = 0; jst < 4; ++jst) if (axes[jst] == 0xFFFF) axes[jst] = -1; return 0; } #else #define snd_cs4281_gameport_cooked_read NULL #endif static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) { switch (mode) { #ifdef COOKED_MODE case GAMEPORT_MODE_COOKED: return 0; #endif case GAMEPORT_MODE_RAW: return 0; default: return -1; } return 0; } static int snd_cs4281_create_gameport(struct cs4281 *chip) { struct gameport *gp; chip->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(chip->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "CS4281 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); gameport_set_dev_parent(gp, &chip->pci->dev); gp->open = snd_cs4281_gameport_open; gp->read = snd_cs4281_gameport_read; gp->trigger = snd_cs4281_gameport_trigger; gp->cooked_read = snd_cs4281_gameport_cooked_read; gameport_set_port_data(gp, chip); snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); gameport_register_port(gp); return 0; } static void snd_cs4281_free_gameport(struct cs4281 *chip) { if (chip->gameport) { gameport_unregister_port(chip->gameport); chip->gameport = NULL; } } #else static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; } static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { } #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */ static void snd_cs4281_free(struct snd_card *card) { struct cs4281 *chip = card->private_data; snd_cs4281_free_gameport(chip); /* Mask interrupts */ snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); /* Stop the DLL Clock logic. */ snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); /* Sound System Power Management - Turn Everything OFF */ snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); } static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */ static int snd_cs4281_create(struct snd_card *card, struct pci_dev *pci, int dual_codec) { struct cs4281 *chip = card->private_data; int err; err = pcim_enable_device(pci); if (err < 0) return err; spin_lock_init(&chip->reg_lock); chip->card = card; chip->pci = pci; chip->irq = -1; pci_set_master(pci); if (dual_codec < 0 || dual_codec > 3) { dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec); dual_codec = 0; } chip->dual_codec = dual_codec; err = pcim_iomap_regions(pci, 0x03, "CS4281"); /* 2 BARs */ if (err < 0) return err; chip->ba0_addr = pci_resource_start(pci, 0); chip->ba1_addr = pci_resource_start(pci, 1); chip->ba0 = pcim_iomap_table(pci)[0]; chip->ba1 = pcim_iomap_table(pci)[1]; if (devm_request_irq(&pci->dev, pci->irq, snd_cs4281_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -ENOMEM; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_cs4281_free; err = snd_cs4281_chip_init(chip); if (err) return err; snd_cs4281_proc_init(chip); return 0; } static int snd_cs4281_chip_init(struct cs4281 *chip) { unsigned int tmp; unsigned long end_time; int retry_count = 2; /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); if (tmp & BA0_EPPMC_FPDN) snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); __retry: tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); if (tmp != BA0_CFLR_DEFAULT) { snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); if (tmp != BA0_CFLR_DEFAULT) { dev_err(chip->card->dev, "CFLR setup failed (0x%x)\n", tmp); return -EIO; } } /* Set the 'Configuration Write Protect' register * to 4281h. Allows vendor-defined configuration * space between 0e4h and 0ffh to be written. */ snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); tmp = snd_cs4281_peekBA0(chip, BA0_SERC1); if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { dev_err(chip->card->dev, "SERC1 AC'97 check failed (0x%x)\n", tmp); return -EIO; } tmp = snd_cs4281_peekBA0(chip, BA0_SERC2); if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { dev_err(chip->card->dev, "SERC2 AC'97 check failed (0x%x)\n", tmp); return -EIO; } /* Sound System Power Management */ snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | BA0_SSPM_ACLEN | BA0_SSPM_FMEN); /* Serial Port Power Management */ /* Blast the clock control register to zero so that the * PLL starts out in a known state, and blast the master serial * port control register to zero so that the serial ports also * start out in a known state. */ snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); /* Make ESYN go to zero to turn off * the Sync pulse on the AC97 link. */ snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); udelay(50); /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 * spec) and then drive it high. This is done for non AC97 modes since * there might be logic external to the CS4281 that uses the ARST# line * for a reset. */ snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); udelay(50); snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); msleep(50); if (chip->dual_codec) snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); /* * Set the serial port timing configuration. */ snd_cs4281_pokeBA0(chip, BA0_SERMC, (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); /* * Start the DLL Clock logic. */ snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); msleep(50); snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); /* * Wait for the DLL ready signal from the clock logic. */ end_time = jiffies + HZ; do { /* * Read the AC97 status register to see if we've seen a CODEC * signal from the AC97 codec. */ if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) goto __ok0; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); dev_err(chip->card->dev, "DLLRDY not seen\n"); return -EIO; __ok0: /* * The first thing we do here is to enable sync generation. As soon * as we start receiving bit clock, we'll start producing the SYNC * signal. */ snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); /* * Wait for the codec ready signal from the AC97 codec. */ end_time = jiffies + HZ; do { /* * Read the AC97 status register to see if we've seen a CODEC * signal from the AC97 codec. */ if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) goto __ok1; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); dev_err(chip->card->dev, "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); return -EIO; __ok1: if (chip->dual_codec) { end_time = jiffies + HZ; do { if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) goto __codec2_ok; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); dev_info(chip->card->dev, "secondary codec doesn't respond. disable it...\n"); chip->dual_codec = 0; __codec2_ok: ; } /* * Assert the valid frame signal so that we can start sending commands * to the AC97 codec. */ snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); /* * Wait until we've sampled input slots 3 and 4 as valid, meaning that * the codec is pumping ADC data across the AC-link. */ end_time = jiffies + HZ; do { /* * Read the input slot valid register and see if input slots 3 * 4 are valid yet. */ if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) goto __ok2; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); if (--retry_count > 0) goto __retry; dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n"); return -EIO; __ok2: /* * Now, assert valid frame and the slot 3 and 4 valid bits. This will * commense the transfer of digital audio data to the AC97 codec. */ snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); /* * Initialize DMA structures */ for (tmp = 0; tmp < 4; tmp++) { struct cs4281_dma *dma = &chip->dma[tmp]; dma->regDBA = BA0_DBA0 + (tmp * 0x10); dma->regDCA = BA0_DCA0 + (tmp * 0x10); dma->regDBC = BA0_DBC0 + (tmp * 0x10); dma->regDCC = BA0_DCC0 + (tmp * 0x10); dma->regDMR = BA0_DMR0 + (tmp * 8); dma->regDCR = BA0_DCR0 + (tmp * 8); dma->regHDSR = BA0_HDSR0 + (tmp * 4); dma->regFCR = BA0_FCR0 + (tmp * 4); dma->regFSIC = BA0_FSIC0 + (tmp * 4); dma->fifo_offset = tmp * CS4281_FIFO_SIZE; snd_cs4281_pokeBA0(chip, dma->regFCR, BA0_FCR_LS(31) | BA0_FCR_RS(31) | BA0_FCR_SZ(CS4281_FIFO_SIZE) | BA0_FCR_OF(dma->fifo_offset)); } chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ /* Activate wave playback FIFO for FM playback */ chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | BA0_FCR_RS(1) | BA0_FCR_SZ(CS4281_FIFO_SIZE) | BA0_FCR_OF(chip->dma[0].fifo_offset); snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | (chip->src_right_play_slot << 8) | (chip->src_left_rec_slot << 16) | (chip->src_right_rec_slot << 24)); /* Initialize digital volume */ snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); /* Enable IRQs */ snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); /* Unmask interrupts */ snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( BA0_HISR_MIDI | BA0_HISR_DMAI | BA0_HISR_DMA(0) | BA0_HISR_DMA(1) | BA0_HISR_DMA(2) | BA0_HISR_DMA(3))); return 0; } /* * MIDI section */ static void snd_cs4281_midi_reset(struct cs4281 *chip) { snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); udelay(100); snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream) { struct cs4281 *chip = substream->rmidi->private_data; spin_lock_irq(&chip->reg_lock); chip->midcr |= BA0_MIDCR_RXE; chip->midi_input = substream; if (!(chip->uartm & CS4281_MODE_OUTPUT)) { snd_cs4281_midi_reset(chip); } else { snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream) { struct cs4281 *chip = substream->rmidi->private_data; spin_lock_irq(&chip->reg_lock); chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); chip->midi_input = NULL; if (!(chip->uartm & CS4281_MODE_OUTPUT)) { snd_cs4281_midi_reset(chip); } else { snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } chip->uartm &= ~CS4281_MODE_INPUT; spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream) { struct cs4281 *chip = substream->rmidi->private_data; spin_lock_irq(&chip->reg_lock); chip->uartm |= CS4281_MODE_OUTPUT; chip->midcr |= BA0_MIDCR_TXE; chip->midi_output = substream; if (!(chip->uartm & CS4281_MODE_INPUT)) { snd_cs4281_midi_reset(chip); } else { snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream) { struct cs4281 *chip = substream->rmidi->private_data; spin_lock_irq(&chip->reg_lock); chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); chip->midi_output = NULL; if (!(chip->uartm & CS4281_MODE_INPUT)) { snd_cs4281_midi_reset(chip); } else { snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } chip->uartm &= ~CS4281_MODE_OUTPUT; spin_unlock_irq(&chip->reg_lock); return 0; } static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) { unsigned long flags; struct cs4281 *chip = substream->rmidi->private_data; spin_lock_irqsave(&chip->reg_lock, flags); if (up) { if ((chip->midcr & BA0_MIDCR_RIE) == 0) { chip->midcr |= BA0_MIDCR_RIE; snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } } else { if (chip->midcr & BA0_MIDCR_RIE) { chip->midcr &= ~BA0_MIDCR_RIE; snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } } spin_unlock_irqrestore(&chip->reg_lock, flags); } static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) { unsigned long flags; struct cs4281 *chip = substream->rmidi->private_data; unsigned char byte; spin_lock_irqsave(&chip->reg_lock, flags); if (up) { if ((chip->midcr & BA0_MIDCR_TIE) == 0) { chip->midcr |= BA0_MIDCR_TIE; /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ while ((chip->midcr & BA0_MIDCR_TIE) && (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { chip->midcr &= ~BA0_MIDCR_TIE; } else { snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); } } snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } } else { if (chip->midcr & BA0_MIDCR_TIE) { chip->midcr &= ~BA0_MIDCR_TIE; snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); } } spin_unlock_irqrestore(&chip->reg_lock, flags); } static const struct snd_rawmidi_ops snd_cs4281_midi_output = { .open = snd_cs4281_midi_output_open, .close = snd_cs4281_midi_output_close, .trigger = snd_cs4281_midi_output_trigger, }; static const struct snd_rawmidi_ops snd_cs4281_midi_input = { .open = snd_cs4281_midi_input_open, .close = snd_cs4281_midi_input_close, .trigger = snd_cs4281_midi_input_trigger, }; static int snd_cs4281_midi(struct cs4281 *chip, int device) { struct snd_rawmidi *rmidi; int err; err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi); if (err < 0) return err; strcpy(rmidi->name, "CS4281"); snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; rmidi->private_data = chip; chip->rmidi = rmidi; return 0; } /* * Interrupt handler */ static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id) { struct cs4281 *chip = dev_id; unsigned int status, dma, val; struct cs4281_dma *cdma; if (chip == NULL) return IRQ_NONE; status = snd_cs4281_peekBA0(chip, BA0_HISR); if ((status & 0x7fffffff) == 0) { snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); return IRQ_NONE; } if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { for (dma = 0; dma < 4; dma++) if (status & BA0_HISR_DMA(dma)) { cdma = &chip->dma[dma]; spin_lock(&chip->reg_lock); /* ack DMA IRQ */ val = snd_cs4281_peekBA0(chip, cdma->regHDSR); /* workaround, sometimes CS4281 acknowledges */ /* end or middle transfer position twice */ cdma->frag++; if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { cdma->frag--; chip->spurious_dhtc_irq++; spin_unlock(&chip->reg_lock); continue; } if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { cdma->frag--; chip->spurious_dtc_irq++; spin_unlock(&chip->reg_lock); continue; } spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(cdma->substream); } } if ((status & BA0_HISR_MIDI) && chip->rmidi) { unsigned char c; spin_lock(&chip->reg_lock); while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { c = snd_cs4281_peekBA0(chip, BA0_MIDRP); if ((chip->midcr & BA0_MIDCR_RIE) == 0) continue; snd_rawmidi_receive(chip->midi_input, &c, 1); } while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { if ((chip->midcr & BA0_MIDCR_TIE) == 0) break; if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { chip->midcr &= ~BA0_MIDCR_TIE; snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); break; } snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); } spin_unlock(&chip->reg_lock); } /* EOI to the PCI part... reenables interrupts */ snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); return IRQ_HANDLED; } /* * OPL3 command */ static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd, unsigned char val) { unsigned long flags; struct cs4281 *chip = opl3->private_data; void __iomem *port; if (cmd & OPL3_RIGHT) port = chip->ba0 + BA0_B1AP; /* right port */ else port = chip->ba0 + BA0_B0AP; /* left port */ spin_lock_irqsave(&opl3->reg_lock, flags); writel((unsigned int)cmd, port); udelay(10); writel((unsigned int)val, port + 4); udelay(30); spin_unlock_irqrestore(&opl3->reg_lock, flags); } static int __snd_cs4281_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct cs4281 *chip; struct snd_opl3 *opl3; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; err = snd_cs4281_create(card, pci, dual_codec[dev]); if (err < 0) return err; err = snd_cs4281_mixer(chip); if (err < 0) return err; err = snd_cs4281_pcm(chip, 0); if (err < 0) return err; err = snd_cs4281_midi(chip, 0); if (err < 0) return err; err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3); if (err < 0) return err; opl3->private_data = chip; opl3->command = snd_cs4281_opl3_command; snd_opl3_init(opl3); err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) return err; snd_cs4281_create_gameport(chip); strcpy(card->driver, "CS4281"); strcpy(card->shortname, "Cirrus Logic CS4281"); sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, chip->ba0_addr, chip->irq); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_cs4281_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_cs4281_probe(pci, pci_id)); } /* * Power Management */ #ifdef CONFIG_PM_SLEEP static const int saved_regs[SUSPEND_REGISTERS] = { BA0_JSCTL, BA0_GPIOR, BA0_SSCR, BA0_MIDCR, BA0_SRCSA, BA0_PASR, BA0_CASR, BA0_DACSR, BA0_ADCSR, BA0_FMLVC, BA0_FMRVC, BA0_PPLVC, BA0_PPRVC, }; #define CLKCR1_CKRA 0x00010000L static int cs4281_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct cs4281 *chip = card->private_data; u32 ulCLK; unsigned int i; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_ac97_suspend(chip->ac97); snd_ac97_suspend(chip->ac97_secondary); ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); ulCLK |= CLKCR1_CKRA; snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); /* Disable interrupts. */ snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); /* remember the status registers */ for (i = 0; i < ARRAY_SIZE(saved_regs); i++) if (saved_regs[i]) chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); /* Turn off the serial ports. */ snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); /* Power off FM, Joystick, AC link, */ snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); /* DLL off. */ snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); /* AC link off. */ snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); ulCLK &= ~CLKCR1_CKRA; snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); return 0; } static int cs4281_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct cs4281 *chip = card->private_data; unsigned int i; u32 ulCLK; ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); ulCLK |= CLKCR1_CKRA; snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); snd_cs4281_chip_init(chip); /* restore the status registers */ for (i = 0; i < ARRAY_SIZE(saved_regs); i++) if (saved_regs[i]) snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); snd_ac97_resume(chip->ac97); snd_ac97_resume(chip->ac97_secondary); ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); ulCLK &= ~CLKCR1_CKRA; snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume); #define CS4281_PM_OPS &cs4281_pm #else #define CS4281_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static struct pci_driver cs4281_driver = { .name = KBUILD_MODNAME, .id_table = snd_cs4281_ids, .probe = snd_cs4281_probe, .driver = { .pm = CS4281_PM_OPS, }, }; module_pci_driver(cs4281_driver);
linux-master
sound/pci/cs4281.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * card-als4000.c - driver for Avance Logic ALS4000 based soundcards. * Copyright (C) 2000 by Bart Hartgers <[email protected]>, * Jaroslav Kysela <[email protected]> * Copyright (C) 2002, 2008 by Andreas Mohr <[email protected]> * * Framework borrowed from Massimo Piccioni's card-als100.c. * * NOTES * * Since Avance does not provide any meaningful documentation, and I * bought an ALS4000 based soundcard, I was forced to base this driver * on reverse engineering. * * Note: this is no longer true (thank you!): * pretty verbose chip docu (ALS4000a.PDF) can be found on the ALSA web site. * Page numbers stated anywhere below with the "SPECS_PAGE:" tag * refer to: ALS4000a.PDF specs Ver 1.0, May 28th, 1998. * * The ALS4000 seems to be the PCI-cousin of the ALS100. It contains an * ALS100-like SB DSP/mixer, an OPL3 synth, a MPU401 and a gameport * interface. These subsystems can be mapped into ISA io-port space, * using the PCI-interface. In addition, the PCI-bit provides DMA and IRQ * services to the subsystems. * * While ALS4000 is very similar to a SoundBlaster, the differences in * DMA and capturing require more changes to the SoundBlaster than * desirable, so I made this separate driver. * * The ALS4000 can do real full duplex playback/capture. * * FMDAC: * - 0x4f -> port 0x14 * - port 0x15 |= 1 * * Enable/disable 3D sound: * - 0x50 -> port 0x14 * - change bit 6 (0x40) of port 0x15 * * Set QSound: * - 0xdb -> port 0x14 * - set port 0x15: * 0x3e (mode 3), 0x3c (mode 2), 0x3a (mode 1), 0x38 (mode 0) * * Set KSound: * - value -> some port 0x0c0d * * ToDo: * - by default, don't enable legacy game and use PCI game I/O * - power management? (card can do voice wakeup according to datasheet!!) */ #include <linux/io.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/rawmidi.h> #include <sound/mpu401.h> #include <sound/opl3.h> #include <sound/sb.h> #include <sound/initval.h> MODULE_AUTHOR("Bart Hartgers <[email protected]>, Andreas Mohr"); MODULE_DESCRIPTION("Avance Logic ALS4000"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ #ifdef SUPPORT_JOYSTICK static int joystick_port[SNDRV_CARDS]; #endif module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for ALS4000 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for ALS4000 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable ALS4000 soundcard."); #ifdef SUPPORT_JOYSTICK module_param_hw_array(joystick_port, int, ioport, NULL, 0444); MODULE_PARM_DESC(joystick_port, "Joystick port address for ALS4000 soundcard. (0 = disabled)"); #endif struct snd_card_als4000 { /* most frequent access first */ unsigned long iobase; struct pci_dev *pci; struct snd_sb *chip; #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif }; static const struct pci_device_id snd_als4000_ids[] = { { 0x4005, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ALS4000 */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_als4000_ids); enum als4k_iobase_t { /* IOx: B == Byte, W = Word, D = DWord; SPECS_PAGE: 37 */ ALS4K_IOD_00_AC97_ACCESS = 0x00, ALS4K_IOW_04_AC97_READ = 0x04, ALS4K_IOB_06_AC97_STATUS = 0x06, ALS4K_IOB_07_IRQSTATUS = 0x07, ALS4K_IOD_08_GCR_DATA = 0x08, ALS4K_IOB_0C_GCR_INDEX = 0x0c, ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU = 0x0e, ALS4K_IOB_10_ADLIB_ADDR0 = 0x10, ALS4K_IOB_11_ADLIB_ADDR1 = 0x11, ALS4K_IOB_12_ADLIB_ADDR2 = 0x12, ALS4K_IOB_13_ADLIB_ADDR3 = 0x13, ALS4K_IOB_14_MIXER_INDEX = 0x14, ALS4K_IOB_15_MIXER_DATA = 0x15, ALS4K_IOB_16_ESP_RESET = 0x16, ALS4K_IOB_16_ACK_FOR_CR1E = 0x16, /* 2nd function */ ALS4K_IOB_18_OPL_ADDR0 = 0x18, ALS4K_IOB_19_OPL_ADDR1 = 0x19, ALS4K_IOB_1A_ESP_RD_DATA = 0x1a, ALS4K_IOB_1C_ESP_CMD_DATA = 0x1c, ALS4K_IOB_1C_ESP_WR_STATUS = 0x1c, /* 2nd function */ ALS4K_IOB_1E_ESP_RD_STATUS8 = 0x1e, ALS4K_IOB_1F_ESP_RD_STATUS16 = 0x1f, ALS4K_IOB_20_ESP_GAMEPORT_200 = 0x20, ALS4K_IOB_21_ESP_GAMEPORT_201 = 0x21, ALS4K_IOB_30_MIDI_DATA = 0x30, ALS4K_IOB_31_MIDI_STATUS = 0x31, ALS4K_IOB_31_MIDI_COMMAND = 0x31, /* 2nd function */ }; enum als4k_iobase_0e_t { ALS4K_IOB_0E_MPU_IRQ = 0x10, ALS4K_IOB_0E_CR1E_IRQ = 0x40, ALS4K_IOB_0E_SB_DMA_IRQ = 0x80, }; enum als4k_gcr_t { /* all registers 32bit wide; SPECS_PAGE: 38 to 42 */ ALS4K_GCR8C_MISC_CTRL = 0x8c, ALS4K_GCR90_TEST_MODE_REG = 0x90, ALS4K_GCR91_DMA0_ADDR = 0x91, ALS4K_GCR92_DMA0_MODE_COUNT = 0x92, ALS4K_GCR93_DMA1_ADDR = 0x93, ALS4K_GCR94_DMA1_MODE_COUNT = 0x94, ALS4K_GCR95_DMA3_ADDR = 0x95, ALS4K_GCR96_DMA3_MODE_COUNT = 0x96, ALS4K_GCR99_DMA_EMULATION_CTRL = 0x99, ALS4K_GCRA0_FIFO1_CURRENT_ADDR = 0xa0, ALS4K_GCRA1_FIFO1_STATUS_BYTECOUNT = 0xa1, ALS4K_GCRA2_FIFO2_PCIADDR = 0xa2, ALS4K_GCRA3_FIFO2_COUNT = 0xa3, ALS4K_GCRA4_FIFO2_CURRENT_ADDR = 0xa4, ALS4K_GCRA5_FIFO1_STATUS_BYTECOUNT = 0xa5, ALS4K_GCRA6_PM_CTRL = 0xa6, ALS4K_GCRA7_PCI_ACCESS_STORAGE = 0xa7, ALS4K_GCRA8_LEGACY_CFG1 = 0xa8, ALS4K_GCRA9_LEGACY_CFG2 = 0xa9, ALS4K_GCRFF_DUMMY_SCRATCH = 0xff, }; enum als4k_gcr8c_t { ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE = 0x8000, ALS4K_GCR8C_CHIP_REV_MASK = 0xf0000 }; static inline void snd_als4k_iobase_writeb(unsigned long iobase, enum als4k_iobase_t reg, u8 val) { outb(val, iobase + reg); } static inline void snd_als4k_iobase_writel(unsigned long iobase, enum als4k_iobase_t reg, u32 val) { outl(val, iobase + reg); } static inline u8 snd_als4k_iobase_readb(unsigned long iobase, enum als4k_iobase_t reg) { return inb(iobase + reg); } static inline u32 snd_als4k_iobase_readl(unsigned long iobase, enum als4k_iobase_t reg) { return inl(iobase + reg); } static inline void snd_als4k_gcr_write_addr(unsigned long iobase, enum als4k_gcr_t reg, u32 val) { snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg); snd_als4k_iobase_writel(iobase, ALS4K_IOD_08_GCR_DATA, val); } static inline void snd_als4k_gcr_write(struct snd_sb *sb, enum als4k_gcr_t reg, u32 val) { snd_als4k_gcr_write_addr(sb->alt_port, reg, val); } static inline u32 snd_als4k_gcr_read_addr(unsigned long iobase, enum als4k_gcr_t reg) { /* SPECS_PAGE: 37/38 */ snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg); return snd_als4k_iobase_readl(iobase, ALS4K_IOD_08_GCR_DATA); } static inline u32 snd_als4k_gcr_read(struct snd_sb *sb, enum als4k_gcr_t reg) { return snd_als4k_gcr_read_addr(sb->alt_port, reg); } enum als4k_cr_t { /* all registers 8bit wide; SPECS_PAGE: 20 to 23 */ ALS4K_CR0_SB_CONFIG = 0x00, ALS4K_CR2_MISC_CONTROL = 0x02, ALS4K_CR3_CONFIGURATION = 0x03, ALS4K_CR17_FIFO_STATUS = 0x17, ALS4K_CR18_ESP_MAJOR_VERSION = 0x18, ALS4K_CR19_ESP_MINOR_VERSION = 0x19, ALS4K_CR1A_MPU401_UART_MODE_CONTROL = 0x1a, ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO = 0x1c, ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI = 0x1d, ALS4K_CR1E_FIFO2_CONTROL = 0x1e, /* secondary PCM FIFO (recording) */ ALS4K_CR3A_MISC_CONTROL = 0x3a, ALS4K_CR3B_CRC32_BYTE0 = 0x3b, /* for testing, activate via CR3A */ ALS4K_CR3C_CRC32_BYTE1 = 0x3c, ALS4K_CR3D_CRC32_BYTE2 = 0x3d, ALS4K_CR3E_CRC32_BYTE3 = 0x3e, }; enum als4k_cr0_t { ALS4K_CR0_DMA_CONTIN_MODE_CTRL = 0x02, /* IRQ/FIFO controlled for 0/1 */ ALS4K_CR0_DMA_90H_MODE_CTRL = 0x04, /* IRQ/FIFO controlled for 0/1 */ ALS4K_CR0_MX80_81_REG_WRITE_ENABLE = 0x80, }; static inline void snd_als4_cr_write(struct snd_sb *chip, enum als4k_cr_t reg, u8 data) { /* Control Register is reg | 0xc0 (bit 7, 6 set) on sbmixer_index * NOTE: assumes chip->mixer_lock to be locked externally already! * SPECS_PAGE: 6 */ snd_sbmixer_write(chip, reg | 0xc0, data); } static inline u8 snd_als4_cr_read(struct snd_sb *chip, enum als4k_cr_t reg) { /* NOTE: assumes chip->mixer_lock to be locked externally already! */ return snd_sbmixer_read(chip, reg | 0xc0); } static void snd_als4000_set_rate(struct snd_sb *chip, unsigned int rate) { if (!(chip->mode & SB_RATE_LOCK)) { snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_OUT); snd_sbdsp_command(chip, rate>>8); snd_sbdsp_command(chip, rate); } } static inline void snd_als4000_set_capture_dma(struct snd_sb *chip, dma_addr_t addr, unsigned size) { /* SPECS_PAGE: 40 */ snd_als4k_gcr_write(chip, ALS4K_GCRA2_FIFO2_PCIADDR, addr); snd_als4k_gcr_write(chip, ALS4K_GCRA3_FIFO2_COUNT, (size-1)); } static inline void snd_als4000_set_playback_dma(struct snd_sb *chip, dma_addr_t addr, unsigned size) { /* SPECS_PAGE: 38 */ snd_als4k_gcr_write(chip, ALS4K_GCR91_DMA0_ADDR, addr); snd_als4k_gcr_write(chip, ALS4K_GCR92_DMA0_MODE_COUNT, (size-1)|0x180000); } #define ALS4000_FORMAT_SIGNED (1<<0) #define ALS4000_FORMAT_16BIT (1<<1) #define ALS4000_FORMAT_STEREO (1<<2) static int snd_als4000_get_format(struct snd_pcm_runtime *runtime) { int result; result = 0; if (snd_pcm_format_signed(runtime->format)) result |= ALS4000_FORMAT_SIGNED; if (snd_pcm_format_physical_width(runtime->format) == 16) result |= ALS4000_FORMAT_16BIT; if (runtime->channels > 1) result |= ALS4000_FORMAT_STEREO; return result; } /* structure for setting up playback */ static const struct { unsigned char dsp_cmd, dma_on, dma_off, format; } playback_cmd_vals[]={ /* ALS4000_FORMAT_U8_MONO */ { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_MONO }, /* ALS4000_FORMAT_S8_MONO */ { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_MONO }, /* ALS4000_FORMAT_U16L_MONO */ { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_MONO }, /* ALS4000_FORMAT_S16L_MONO */ { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_MONO }, /* ALS4000_FORMAT_U8_STEREO */ { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_STEREO }, /* ALS4000_FORMAT_S8_STEREO */ { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_STEREO }, /* ALS4000_FORMAT_U16L_STEREO */ { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_STEREO }, /* ALS4000_FORMAT_S16L_STEREO */ { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_STEREO }, }; #define playback_cmd(chip) (playback_cmd_vals[(chip)->playback_format]) /* structure for setting up capture */ enum { CMD_WIDTH8=0x04, CMD_SIGNED=0x10, CMD_MONO=0x80, CMD_STEREO=0xA0 }; static const unsigned char capture_cmd_vals[]= { CMD_WIDTH8|CMD_MONO, /* ALS4000_FORMAT_U8_MONO */ CMD_WIDTH8|CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S8_MONO */ CMD_MONO, /* ALS4000_FORMAT_U16L_MONO */ CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S16L_MONO */ CMD_WIDTH8|CMD_STEREO, /* ALS4000_FORMAT_U8_STEREO */ CMD_WIDTH8|CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S8_STEREO */ CMD_STEREO, /* ALS4000_FORMAT_U16L_STEREO */ CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S16L_STEREO */ }; #define capture_cmd(chip) (capture_cmd_vals[(chip)->capture_format]) static int snd_als4000_capture_prepare(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; unsigned long size; unsigned count; chip->capture_format = snd_als4000_get_format(runtime); size = snd_pcm_lib_buffer_bytes(substream); count = snd_pcm_lib_period_bytes(substream); if (chip->capture_format & ALS4000_FORMAT_16BIT) count >>= 1; count--; spin_lock_irq(&chip->reg_lock); snd_als4000_set_rate(chip, runtime->rate); snd_als4000_set_capture_dma(chip, runtime->dma_addr, size); spin_unlock_irq(&chip->reg_lock); spin_lock_irq(&chip->mixer_lock); snd_als4_cr_write(chip, ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO, count & 0xff); snd_als4_cr_write(chip, ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI, count >> 8); spin_unlock_irq(&chip->mixer_lock); return 0; } static int snd_als4000_playback_prepare(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; unsigned long size; unsigned count; chip->playback_format = snd_als4000_get_format(runtime); size = snd_pcm_lib_buffer_bytes(substream); count = snd_pcm_lib_period_bytes(substream); if (chip->playback_format & ALS4000_FORMAT_16BIT) count >>= 1; count--; /* FIXME: from second playback on, there's a lot more clicks and pops * involved here than on first playback. Fiddling with * tons of different settings didn't help (DMA, speaker on/off, * reordering, ...). Something seems to get enabled on playback * that I haven't found out how to disable again, which then causes * the switching pops to reach the speakers the next time here. */ spin_lock_irq(&chip->reg_lock); snd_als4000_set_rate(chip, runtime->rate); snd_als4000_set_playback_dma(chip, runtime->dma_addr, size); /* SPEAKER_ON not needed, since dma_on seems to also enable speaker */ /* snd_sbdsp_command(chip, SB_DSP_SPEAKER_ON); */ snd_sbdsp_command(chip, playback_cmd(chip).dsp_cmd); snd_sbdsp_command(chip, playback_cmd(chip).format); snd_sbdsp_command(chip, count & 0xff); snd_sbdsp_command(chip, count >> 8); snd_sbdsp_command(chip, playback_cmd(chip).dma_off); spin_unlock_irq(&chip->reg_lock); return 0; } static int snd_als4000_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_sb *chip = snd_pcm_substream_chip(substream); int result = 0; /* FIXME race condition in here!!! chip->mode non-atomic update gets consistently protected by reg_lock always, _except_ for this place!! Probably need to take reg_lock as outer (or inner??) lock, too. (or serialize both lock operations? probably not, though... - racy?) */ spin_lock(&chip->mixer_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: chip->mode |= SB_RATE_LOCK_CAPTURE; snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL, capture_cmd(chip)); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: chip->mode &= ~SB_RATE_LOCK_CAPTURE; snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL, capture_cmd(chip)); break; default: result = -EINVAL; break; } spin_unlock(&chip->mixer_lock); return result; } static int snd_als4000_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_sb *chip = snd_pcm_substream_chip(substream); int result = 0; spin_lock(&chip->reg_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: chip->mode |= SB_RATE_LOCK_PLAYBACK; snd_sbdsp_command(chip, playback_cmd(chip).dma_on); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: snd_sbdsp_command(chip, playback_cmd(chip).dma_off); chip->mode &= ~SB_RATE_LOCK_PLAYBACK; break; default: result = -EINVAL; break; } spin_unlock(&chip->reg_lock); return result; } static snd_pcm_uframes_t snd_als4000_capture_pointer(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); unsigned int result; spin_lock(&chip->reg_lock); result = snd_als4k_gcr_read(chip, ALS4K_GCRA4_FIFO2_CURRENT_ADDR); spin_unlock(&chip->reg_lock); result &= 0xffff; return bytes_to_frames( substream->runtime, result ); } static snd_pcm_uframes_t snd_als4000_playback_pointer(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); unsigned result; spin_lock(&chip->reg_lock); result = snd_als4k_gcr_read(chip, ALS4K_GCRA0_FIFO1_CURRENT_ADDR); spin_unlock(&chip->reg_lock); result &= 0xffff; return bytes_to_frames( substream->runtime, result ); } /* FIXME: this IRQ routine doesn't really support IRQ sharing (we always * return IRQ_HANDLED no matter whether we actually had an IRQ flag or not). * ALS4000a.PDF writes that while ACKing IRQ in PCI block will *not* ACK * the IRQ in the SB core, ACKing IRQ in SB block *will* ACK the PCI IRQ * register (alt_port + ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU). Probably something * could be optimized here to query/write one register only... * And even if both registers need to be queried, then there's still the * question of whether it's actually correct to ACK PCI IRQ before reading * SB IRQ like we do now, since ALS4000a.PDF mentions that PCI IRQ will *clear* * SB IRQ status. * (hmm, SPECS_PAGE: 38 mentions it the other way around!) * And do we *really* need the lock here for *reading* SB_DSP4_IRQSTATUS?? * */ static irqreturn_t snd_als4000_interrupt(int irq, void *dev_id) { struct snd_sb *chip = dev_id; unsigned pci_irqstatus; unsigned sb_irqstatus; /* find out which bit of the ALS4000 PCI block produced the interrupt, SPECS_PAGE: 38, 5 */ pci_irqstatus = snd_als4k_iobase_readb(chip->alt_port, ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU); if ((pci_irqstatus & ALS4K_IOB_0E_SB_DMA_IRQ) && (chip->playback_substream)) /* playback */ snd_pcm_period_elapsed(chip->playback_substream); if ((pci_irqstatus & ALS4K_IOB_0E_CR1E_IRQ) && (chip->capture_substream)) /* capturing */ snd_pcm_period_elapsed(chip->capture_substream); if ((pci_irqstatus & ALS4K_IOB_0E_MPU_IRQ) && (chip->rmidi)) /* MPU401 interrupt */ snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); /* ACK the PCI block IRQ */ snd_als4k_iobase_writeb(chip->alt_port, ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU, pci_irqstatus); spin_lock(&chip->mixer_lock); /* SPECS_PAGE: 20 */ sb_irqstatus = snd_sbmixer_read(chip, SB_DSP4_IRQSTATUS); spin_unlock(&chip->mixer_lock); if (sb_irqstatus & SB_IRQTYPE_8BIT) snd_sb_ack_8bit(chip); if (sb_irqstatus & SB_IRQTYPE_16BIT) snd_sb_ack_16bit(chip); if (sb_irqstatus & SB_IRQTYPE_MPUIN) inb(chip->mpu_port); if (sb_irqstatus & ALS4K_IRQTYPE_CR1E_DMA) snd_als4k_iobase_readb(chip->alt_port, ALS4K_IOB_16_ACK_FOR_CR1E); /* dev_dbg(chip->card->dev, "als4000: irq 0x%04x 0x%04x\n", pci_irqstatus, sb_irqstatus); */ /* only ack the things we actually handled above */ return IRQ_RETVAL( (pci_irqstatus & (ALS4K_IOB_0E_SB_DMA_IRQ|ALS4K_IOB_0E_CR1E_IRQ| ALS4K_IOB_0E_MPU_IRQ)) || (sb_irqstatus & (SB_IRQTYPE_8BIT|SB_IRQTYPE_16BIT| SB_IRQTYPE_MPUIN|ALS4K_IRQTYPE_CR1E_DMA)) ); } /*****************************************************************/ static const struct snd_pcm_hardware snd_als4000_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 65536, .period_bytes_min = 64, .period_bytes_max = 65536, .periods_min = 1, .periods_max = 1024, .fifo_size = 0 }; static const struct snd_pcm_hardware snd_als4000_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 65536, .period_bytes_min = 64, .period_bytes_max = 65536, .periods_min = 1, .periods_max = 1024, .fifo_size = 0 }; /*****************************************************************/ static int snd_als4000_playback_open(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; chip->playback_substream = substream; runtime->hw = snd_als4000_playback; return 0; } static int snd_als4000_playback_close(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); chip->playback_substream = NULL; return 0; } static int snd_als4000_capture_open(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; chip->capture_substream = substream; runtime->hw = snd_als4000_capture; return 0; } static int snd_als4000_capture_close(struct snd_pcm_substream *substream) { struct snd_sb *chip = snd_pcm_substream_chip(substream); chip->capture_substream = NULL; return 0; } /******************************************************************/ static const struct snd_pcm_ops snd_als4000_playback_ops = { .open = snd_als4000_playback_open, .close = snd_als4000_playback_close, .prepare = snd_als4000_playback_prepare, .trigger = snd_als4000_playback_trigger, .pointer = snd_als4000_playback_pointer }; static const struct snd_pcm_ops snd_als4000_capture_ops = { .open = snd_als4000_capture_open, .close = snd_als4000_capture_close, .prepare = snd_als4000_capture_prepare, .trigger = snd_als4000_capture_trigger, .pointer = snd_als4000_capture_pointer }; static int snd_als4000_pcm(struct snd_sb *chip, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, "ALS4000 DSP", device, 1, 1, &pcm); if (err < 0) return err; pcm->private_data = chip; pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_als4000_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_als4000_capture_ops); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 64*1024); chip->pcm = pcm; return 0; } /******************************************************************/ static void snd_als4000_set_addr(unsigned long iobase, unsigned int sb_io, unsigned int mpu_io, unsigned int opl_io, unsigned int game_io) { u32 cfg1 = 0; u32 cfg2 = 0; if (mpu_io > 0) cfg2 |= (mpu_io | 1) << 16; if (sb_io > 0) cfg2 |= (sb_io | 1); if (game_io > 0) cfg1 |= (game_io | 1) << 16; if (opl_io > 0) cfg1 |= (opl_io | 1); snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1); snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA9_LEGACY_CFG2, cfg2); } static void snd_als4000_configure(struct snd_sb *chip) { u8 tmp; int i; /* do some more configuration */ spin_lock_irq(&chip->mixer_lock); tmp = snd_als4_cr_read(chip, ALS4K_CR0_SB_CONFIG); snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG, tmp|ALS4K_CR0_MX80_81_REG_WRITE_ENABLE); /* always select DMA channel 0, since we do not actually use DMA * SPECS_PAGE: 19/20 */ snd_sbmixer_write(chip, SB_DSP4_DMASETUP, SB_DMASETUP_DMA0); snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG, tmp & ~ALS4K_CR0_MX80_81_REG_WRITE_ENABLE); spin_unlock_irq(&chip->mixer_lock); spin_lock_irq(&chip->reg_lock); /* enable interrupts */ snd_als4k_gcr_write(chip, ALS4K_GCR8C_MISC_CTRL, ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE); /* SPECS_PAGE: 39 */ for (i = ALS4K_GCR91_DMA0_ADDR; i <= ALS4K_GCR96_DMA3_MODE_COUNT; ++i) snd_als4k_gcr_write(chip, i, 0); /* enable burst mode to prevent dropouts during high PCI bus usage */ snd_als4k_gcr_write(chip, ALS4K_GCR99_DMA_EMULATION_CTRL, (snd_als4k_gcr_read(chip, ALS4K_GCR99_DMA_EMULATION_CTRL) & ~0x07) | 0x04); spin_unlock_irq(&chip->reg_lock); } #ifdef SUPPORT_JOYSTICK static int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev) { struct gameport *gp; struct resource *r; int io_port; if (joystick_port[dev] == 0) return -ENODEV; if (joystick_port[dev] == 1) { /* auto-detect */ for (io_port = 0x200; io_port <= 0x218; io_port += 8) { r = devm_request_region(&acard->pci->dev, io_port, 8, "ALS4000 gameport"); if (r) break; } } else { io_port = joystick_port[dev]; r = devm_request_region(&acard->pci->dev, io_port, 8, "ALS4000 gameport"); } if (!r) { dev_warn(&acard->pci->dev, "cannot reserve joystick ports\n"); return -EBUSY; } acard->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(&acard->pci->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "ALS4000 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(acard->pci)); gameport_set_dev_parent(gp, &acard->pci->dev); gp->io = io_port; /* Enable legacy joystick port */ snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1); gameport_register_port(acard->gameport); return 0; } static void snd_als4000_free_gameport(struct snd_card_als4000 *acard) { if (acard->gameport) { gameport_unregister_port(acard->gameport); acard->gameport = NULL; /* disable joystick */ snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0); } } #else static inline int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev) { return -ENOSYS; } static inline void snd_als4000_free_gameport(struct snd_card_als4000 *acard) { } #endif static void snd_card_als4000_free( struct snd_card *card ) { struct snd_card_als4000 *acard = card->private_data; /* make sure that interrupts are disabled */ snd_als4k_gcr_write_addr(acard->iobase, ALS4K_GCR8C_MISC_CTRL, 0); /* free resources */ snd_als4000_free_gameport(acard); } static int __snd_card_als4000_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct snd_card_als4000 *acard; unsigned long iobase; struct snd_sb *chip; struct snd_opl3 *opl3; unsigned short word; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; /* check, if we can restrict PCI DMA transfers to 24 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { dev_err(&pci->dev, "architecture does not support 24bit PCI busmaster DMA\n"); return -ENXIO; } err = pci_request_regions(pci, "ALS4000"); if (err < 0) return err; iobase = pci_resource_start(pci, 0); pci_read_config_word(pci, PCI_COMMAND, &word); pci_write_config_word(pci, PCI_COMMAND, word | PCI_COMMAND_IO); pci_set_master(pci); err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*acard) /* private_data: acard */, &card); if (err < 0) return err; acard = card->private_data; acard->pci = pci; acard->iobase = iobase; card->private_free = snd_card_als4000_free; /* disable all legacy ISA stuff */ snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0); err = snd_sbdsp_create(card, iobase + ALS4K_IOB_10_ADLIB_ADDR0, pci->irq, /* internally registered as IRQF_SHARED in case of ALS4000 SB */ snd_als4000_interrupt, -1, -1, SB_HW_ALS4000, &chip); if (err < 0) return err; acard->chip = chip; chip->pci = pci; chip->alt_port = iobase; snd_als4000_configure(chip); strcpy(card->driver, "ALS4000"); strcpy(card->shortname, "Avance Logic ALS4000"); sprintf(card->longname, "%s at 0x%lx, irq %i", card->shortname, chip->alt_port, chip->irq); err = snd_mpu401_uart_new(card, 0, MPU401_HW_ALS4000, iobase + ALS4K_IOB_30_MIDI_DATA, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi); if (err < 0) { dev_err(&pci->dev, "no MPU-401 device at 0x%lx?\n", iobase + ALS4K_IOB_30_MIDI_DATA); return err; } /* FIXME: ALS4000 has interesting MPU401 configuration features * at ALS4K_CR1A_MPU401_UART_MODE_CONTROL * (pass-thru / UART switching, fast MIDI clock, etc.), * however there doesn't seem to be an ALSA API for this... * SPECS_PAGE: 21 */ err = snd_als4000_pcm(chip, 0); if (err < 0) return err; err = snd_sbmixer_new(chip); if (err < 0) return err; if (snd_opl3_create(card, iobase + ALS4K_IOB_10_ADLIB_ADDR0, iobase + ALS4K_IOB_12_ADLIB_ADDR2, OPL3_HW_AUTO, 1, &opl3) < 0) { dev_err(&pci->dev, "no OPL device at 0x%lx-0x%lx?\n", iobase + ALS4K_IOB_10_ADLIB_ADDR0, iobase + ALS4K_IOB_12_ADLIB_ADDR2); } else { err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) return err; } snd_als4000_create_gameport(acard, dev); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_card_als4000_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_card_als4000_probe(pci, pci_id)); } #ifdef CONFIG_PM_SLEEP static int snd_als4000_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_card_als4000 *acard = card->private_data; struct snd_sb *chip = acard->chip; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_sbmixer_suspend(chip); return 0; } static int snd_als4000_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_card_als4000 *acard = card->private_data; struct snd_sb *chip = acard->chip; snd_als4000_configure(chip); snd_sbdsp_reset(chip); snd_sbmixer_resume(chip); #ifdef SUPPORT_JOYSTICK if (acard->gameport) snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1); #endif snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(snd_als4000_pm, snd_als4000_suspend, snd_als4000_resume); #define SND_ALS4000_PM_OPS &snd_als4000_pm #else #define SND_ALS4000_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static struct pci_driver als4000_driver = { .name = KBUILD_MODNAME, .id_table = snd_als4000_ids, .probe = snd_card_als4000_probe, .driver = { .pm = SND_ALS4000_PM_OPS, }, }; module_pci_driver(als4000_driver);
linux-master
sound/pci/als4000.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) * Copyright (c) by Matze Braun <[email protected]>. * Takashi Iwai <[email protected]> * * Most of the driver code comes from Zach Brown([email protected]) * Alan Cox OSS Driver * Rewritted from card-es1938.c source. * * TODO: * Perhaps Synth * * Notes from Zach Brown about the driver code * * Hardware Description * * A working Maestro setup contains the Maestro chip wired to a * codec or 2. In the Maestro we have the APUs, the ASSP, and the * Wavecache. The APUs can be though of as virtual audio routing * channels. They can take data from a number of sources and perform * basic encodings of the data. The wavecache is a storehouse for * PCM data. Typically it deals with PCI and interracts with the * APUs. The ASSP is a wacky DSP like device that ESS is loth * to release docs on. Thankfully it isn't required on the Maestro * until you start doing insane things like FM emulation and surround * encoding. The codecs are almost always AC-97 compliant codecs, * but it appears that early Maestros may have had PT101 (an ESS * part?) wired to them. The only real difference in the Maestro * families is external goop like docking capability, memory for * the ASSP, and initialization differences. * * Driver Operation * * We only drive the APU/Wavecache as typical DACs and drive the * mixers in the codecs. There are 64 APUs. We assign 6 to each * /dev/dsp? device. 2 channels for output, and 4 channels for * input. * * Each APU can do a number of things, but we only really use * 3 basic functions. For playback we use them to convert PCM * data fetched over PCI by the wavecahche into analog data that * is handed to the codec. One APU for mono, and a pair for stereo. * When in stereo, the combination of smarts in the APU and Wavecache * decide which wavecache gets the left or right channel. * * For record we still use the old overly mono system. For each in * coming channel the data comes in from the codec, through a 'input' * APU, through another rate converter APU, and then into memory via * the wavecache and PCI. If its stereo, we mash it back into LRLR in * software. The pass between the 2 APUs is supposedly what requires us * to have a 512 byte buffer sitting around in wavecache/memory. * * The wavecache makes our life even more fun. First off, it can * only address the first 28 bits of PCI address space, making it * useless on quite a few architectures. Secondly, its insane. * It claims to fetch from 4 regions of PCI space, each 4 meg in length. * But that doesn't really work. You can only use 1 region. So all our * allocations have to be in 4meg of each other. Booo. Hiss. * So we have a module parameter, dsps_order, that is the order of * the number of dsps to provide. All their buffer space is allocated * on open time. The sonicvibes OSS routines we inherited really want * power of 2 buffers, so we have all those next to each other, then * 512 byte regions for the recording wavecaches. This ends up * wasting quite a bit of memory. The only fixes I can see would be * getting a kernel allocator that could work in zones, or figuring out * just how to coerce the WP into doing what we want. * * The indirection of the various registers means we have to spinlock * nearly all register accesses. We have the main register indirection * like the wave cache, maestro registers, etc. Then we have beasts * like the APU interface that is indirect registers gotten at through * the main maestro indirection. Ouch. We spinlock around the actual * ports on a per card basis. This means spinlock activity at each IO * operation, but the only IO operation clusters are in non critical * paths and it makes the code far easier to follow. Interrupts are * blocked while holding the locks because the int handler has to * get at some of them :(. The mixer interface doesn't, however. * We also have an OSS state lock that is thrown around in a few * places. */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/input.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/mpu401.h> #include <sound/ac97_codec.h> #include <sound/initval.h> #ifdef CONFIG_SND_ES1968_RADIO #include <media/drv-intf/tea575x.h> #endif #define CARD_NAME "ESS Maestro1/2" #define DRIVER_NAME "ES1968" MODULE_DESCRIPTION("ESS Maestro"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; static int clock[SNDRV_CARDS]; static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; #ifdef SUPPORT_JOYSTICK static bool joystick[SNDRV_CARDS]; #endif static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); module_param_array(total_bufsize, int, NULL, 0444); MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); module_param_array(pcm_substreams_p, int, NULL, 0444); MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); module_param_array(pcm_substreams_c, int, NULL, 0444); MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); module_param_array(clock, int, NULL, 0444); MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); module_param_array(use_pm, int, NULL, 0444); MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); module_param_array(enable_mpu, int, NULL, 0444); MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); #ifdef SUPPORT_JOYSTICK module_param_array(joystick, bool, NULL, 0444); MODULE_PARM_DESC(joystick, "Enable joystick."); #endif module_param_array(radio_nr, int, NULL, 0444); MODULE_PARM_DESC(radio_nr, "Radio device numbers"); #define NR_APUS 64 #define NR_APU_REGS 16 /* NEC Versas ? */ #define NEC_VERSA_SUBID1 0x80581033 #define NEC_VERSA_SUBID2 0x803c1033 /* Mode Flags */ #define ESS_FMT_STEREO 0x01 #define ESS_FMT_16BIT 0x02 #define DAC_RUNNING 1 #define ADC_RUNNING 2 /* Values for the ESM_LEGACY_AUDIO_CONTROL */ #define ESS_DISABLE_AUDIO 0x8000 #define ESS_ENABLE_SERIAL_IRQ 0x4000 #define IO_ADRESS_ALIAS 0x0020 #define MPU401_IRQ_ENABLE 0x0010 #define MPU401_IO_ENABLE 0x0008 #define GAME_IO_ENABLE 0x0004 #define FM_IO_ENABLE 0x0002 #define SB_IO_ENABLE 0x0001 /* Values for the ESM_CONFIG_A */ #define PIC_SNOOP1 0x4000 #define PIC_SNOOP2 0x2000 #define SAFEGUARD 0x0800 #define DMA_CLEAR 0x0700 #define DMA_DDMA 0x0000 #define DMA_TDMA 0x0100 #define DMA_PCPCI 0x0200 #define POST_WRITE 0x0080 #define PCI_TIMING 0x0040 #define SWAP_LR 0x0020 #define SUBTR_DECODE 0x0002 /* Values for the ESM_CONFIG_B */ #define SPDIF_CONFB 0x0100 #define HWV_CONFB 0x0080 #define DEBOUNCE 0x0040 #define GPIO_CONFB 0x0020 #define CHI_CONFB 0x0010 #define IDMA_CONFB 0x0008 /*undoc */ #define MIDI_FIX 0x0004 /*undoc */ #define IRQ_TO_ISA 0x0001 /*undoc */ /* Values for Ring Bus Control B */ #define RINGB_2CODEC_ID_MASK 0x0003 #define RINGB_DIS_VALIDATION 0x0008 #define RINGB_EN_SPDIF 0x0010 #define RINGB_EN_2CODEC 0x0020 #define RINGB_SING_BIT_DUAL 0x0040 /* ****Port Addresses**** */ /* Write & Read */ #define ESM_INDEX 0x02 #define ESM_DATA 0x00 /* AC97 + RingBus */ #define ESM_AC97_INDEX 0x30 #define ESM_AC97_DATA 0x32 #define ESM_RING_BUS_DEST 0x34 #define ESM_RING_BUS_CONTR_A 0x36 #define ESM_RING_BUS_CONTR_B 0x38 #define ESM_RING_BUS_SDO 0x3A /* WaveCache*/ #define WC_INDEX 0x10 #define WC_DATA 0x12 #define WC_CONTROL 0x14 /* ASSP*/ #define ASSP_INDEX 0x80 #define ASSP_MEMORY 0x82 #define ASSP_DATA 0x84 #define ASSP_CONTROL_A 0xA2 #define ASSP_CONTROL_B 0xA4 #define ASSP_CONTROL_C 0xA6 #define ASSP_HOSTW_INDEX 0xA8 #define ASSP_HOSTW_DATA 0xAA #define ASSP_HOSTW_IRQ 0xAC /* Midi */ #define ESM_MPU401_PORT 0x98 /* Others */ #define ESM_PORT_HOST_IRQ 0x18 #define IDR0_DATA_PORT 0x00 #define IDR1_CRAM_POINTER 0x01 #define IDR2_CRAM_DATA 0x02 #define IDR3_WAVE_DATA 0x03 #define IDR4_WAVE_PTR_LOW 0x04 #define IDR5_WAVE_PTR_HI 0x05 #define IDR6_TIMER_CTRL 0x06 #define IDR7_WAVE_ROMRAM 0x07 #define WRITEABLE_MAP 0xEFFFFF #define READABLE_MAP 0x64003F /* PCI Register */ #define ESM_LEGACY_AUDIO_CONTROL 0x40 #define ESM_ACPI_COMMAND 0x54 #define ESM_CONFIG_A 0x50 #define ESM_CONFIG_B 0x52 #define ESM_DDMA 0x60 /* Bob Bits */ #define ESM_BOB_ENABLE 0x0001 #define ESM_BOB_START 0x0001 /* Host IRQ Control Bits */ #define ESM_RESET_MAESTRO 0x8000 #define ESM_RESET_DIRECTSOUND 0x4000 #define ESM_HIRQ_ClkRun 0x0100 #define ESM_HIRQ_HW_VOLUME 0x0040 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */ #define ESM_HIRQ_ASSP 0x0010 #define ESM_HIRQ_DSIE 0x0004 #define ESM_HIRQ_MPU401 0x0002 #define ESM_HIRQ_SB 0x0001 /* Host IRQ Status Bits */ #define ESM_MPU401_IRQ 0x02 #define ESM_SB_IRQ 0x01 #define ESM_SOUND_IRQ 0x04 #define ESM_ASSP_IRQ 0x10 #define ESM_HWVOL_IRQ 0x40 #define ESS_SYSCLK 50000000 #define ESM_BOB_FREQ 200 #define ESM_BOB_FREQ_MAX 800 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ #define ESM_FREQ_ESM2 (50000000L / 1024L) /* APU Modes: reg 0x00, bit 4-7 */ #define ESM_APU_MODE_SHIFT 4 #define ESM_APU_MODE_MASK (0xf << 4) #define ESM_APU_OFF 0x00 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ #define ESM_APU_CORRELATOR 0x08 /* Correlator */ #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ /* reg 0x00 */ #define ESM_APU_FILTER_Q_SHIFT 0 #define ESM_APU_FILTER_Q_MASK (3 << 0) /* APU Filtey Q Control */ #define ESM_APU_FILTER_LESSQ 0x00 #define ESM_APU_FILTER_MOREQ 0x03 #define ESM_APU_FILTER_TYPE_SHIFT 2 #define ESM_APU_FILTER_TYPE_MASK (3 << 2) #define ESM_APU_ENV_TYPE_SHIFT 8 #define ESM_APU_ENV_TYPE_MASK (3 << 8) #define ESM_APU_ENV_STATE_SHIFT 10 #define ESM_APU_ENV_STATE_MASK (3 << 10) #define ESM_APU_END_CURVE (1 << 12) #define ESM_APU_INT_ON_LOOP (1 << 13) #define ESM_APU_DMA_ENABLE (1 << 14) /* reg 0x02 */ #define ESM_APU_SUBMIX_GROUP_SHIRT 0 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) #define ESM_APU_SUBMIX_MODE (1 << 3) #define ESM_APU_6dB (1 << 4) #define ESM_APU_DUAL_EFFECT (1 << 5) #define ESM_APU_EFFECT_CHANNELS_SHIFT 6 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) /* reg 0x03 */ #define ESM_APU_STEP_SIZE_MASK 0x0fff /* reg 0x04 */ #define ESM_APU_PHASE_SHIFT 0 #define ESM_APU_PHASE_MASK (0xff << 0) #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) /* reg 0x05 - wave start offset */ /* reg 0x06 - wave end offset */ /* reg 0x07 - wave loop length */ /* reg 0x08 */ #define ESM_APU_EFFECT_GAIN_SHIFT 0 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) #define ESM_APU_TREMOLO_DEPTH_SHIFT 8 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) #define ESM_APU_TREMOLO_RATE_SHIFT 12 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) /* reg 0x09 */ /* bit 0-7 amplitude dest? */ #define ESM_APU_AMPLITUDE_NOW_SHIFT 8 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) /* reg 0x0a */ #define ESM_APU_POLAR_PAN_SHIFT 0 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0) /* Polar Pan Control */ #define ESM_APU_PAN_CENTER_CIRCLE 0x00 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 #define ESM_APU_FILTER_TUNING_SHIFT 8 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8) /* reg 0x0b */ #define ESM_APU_DATA_SRC_A_SHIFT 0 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) #define ESM_APU_INV_POL_A (1 << 7) #define ESM_APU_DATA_SRC_B_SHIFT 8 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) #define ESM_APU_INV_POL_B (1 << 15) #define ESM_APU_VIBRATO_RATE_SHIFT 0 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) #define ESM_APU_VIBRATO_DEPTH_SHIFT 4 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) #define ESM_APU_VIBRATO_PHASE_SHIFT 8 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) /* reg 0x0c */ #define ESM_APU_RADIUS_SELECT (1 << 6) /* APU Filter Control */ #define ESM_APU_FILTER_2POLE_LOPASS 0x00 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01 #define ESM_APU_FILTER_2POLE_HIPASS 0x02 #define ESM_APU_FILTER_1POLE_LOPASS 0x03 #define ESM_APU_FILTER_1POLE_HIPASS 0x04 #define ESM_APU_FILTER_OFF 0x05 /* APU ATFP Type */ #define ESM_APU_ATFP_AMPLITUDE 0x00 #define ESM_APU_ATFP_TREMELO 0x01 #define ESM_APU_ATFP_FILTER 0x02 #define ESM_APU_ATFP_PAN 0x03 /* APU ATFP Flags */ #define ESM_APU_ATFP_FLG_OFF 0x00 #define ESM_APU_ATFP_FLG_WAIT 0x01 #define ESM_APU_ATFP_FLG_DONE 0x02 #define ESM_APU_ATFP_FLG_INPROCESS 0x03 /* capture mixing buffer size */ #define ESM_MEM_ALIGN 0x1000 #define ESM_MIXBUF_SIZE 0x400 #define ESM_MODE_PLAY 0 #define ESM_MODE_CAPTURE 1 /* APU use in the driver */ enum snd_enum_apu_type { ESM_APU_PCM_PLAY, ESM_APU_PCM_CAPTURE, ESM_APU_PCM_RATECONV, ESM_APU_FREE }; /* chip type */ enum { TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E }; /* DMA Hack! */ struct esm_memory { struct snd_dma_buffer buf; int empty; /* status */ struct list_head list; }; /* Playback Channel */ struct esschan { int running; u8 apu[4]; u8 apu_mode[4]; /* playback/capture pcm buffer */ struct esm_memory *memory; /* capture mixer buffer */ struct esm_memory *mixbuf; unsigned int hwptr; /* current hw pointer in bytes */ unsigned int count; /* sample counter in bytes */ unsigned int dma_size; /* total buffer size in bytes */ unsigned int frag_size; /* period size in bytes */ unsigned int wav_shift; u16 base[4]; /* offset for ptr */ /* stereo/16bit flag */ unsigned char fmt; int mode; /* playback / capture */ int bob_freq; /* required timer frequency */ struct snd_pcm_substream *substream; /* linked list */ struct list_head list; #ifdef CONFIG_PM_SLEEP u16 wc_map[4]; #endif }; struct es1968 { /* Module Config */ int total_bufsize; /* in bytes */ int playback_streams, capture_streams; unsigned int clock; /* clock */ /* for clock measurement */ unsigned int in_measurement: 1; unsigned int measure_apu; unsigned int measure_lastpos; unsigned int measure_count; /* buffer */ struct snd_dma_buffer dma; /* Resources... */ int irq; unsigned long io_port; int type; struct pci_dev *pci; struct snd_card *card; struct snd_pcm *pcm; int do_pm; /* power-management enabled */ /* DMA memory block */ struct list_head buf_list; /* ALSA Stuff */ struct snd_ac97 *ac97; struct snd_rawmidi *rmidi; spinlock_t reg_lock; unsigned int in_suspend; /* Maestro Stuff */ u16 maestro_map[32]; int bobclient; /* active timer instancs */ int bob_freq; /* timer frequency */ struct mutex memory_mutex; /* memory lock */ /* APU states */ unsigned char apu[NR_APUS]; /* active substreams */ struct list_head substream_list; spinlock_t substream_lock; #ifdef CONFIG_PM_SLEEP u16 apu_map[NR_APUS][NR_APU_REGS]; #endif #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif #ifdef CONFIG_SND_ES1968_INPUT struct input_dev *input_dev; char phys[64]; /* physical device path */ #else struct snd_kcontrol *master_switch; /* for h/w volume control */ struct snd_kcontrol *master_volume; #endif struct work_struct hwvol_work; #ifdef CONFIG_SND_ES1968_RADIO struct v4l2_device v4l2_dev; struct snd_tea575x tea; unsigned int tea575x_tuner; #endif }; static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id); static const struct pci_device_id snd_es1968_ids[] = { /* Maestro 1 */ { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, /* Maestro 2 */ { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, /* Maestro 2E */ { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, { 0, } }; MODULE_DEVICE_TABLE(pci, snd_es1968_ids); /* ********************* * Low Level Funcs! * *********************/ /* no spinlock */ static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) { outw(reg, chip->io_port + ESM_INDEX); outw(data, chip->io_port + ESM_DATA); chip->maestro_map[reg] = data; } static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); __maestro_write(chip, reg, data); spin_unlock_irqrestore(&chip->reg_lock, flags); } /* no spinlock */ static u16 __maestro_read(struct es1968 *chip, u16 reg) { if (READABLE_MAP & (1 << reg)) { outw(reg, chip->io_port + ESM_INDEX); chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); } return chip->maestro_map[reg]; } static inline u16 maestro_read(struct es1968 *chip, u16 reg) { unsigned long flags; u16 result; spin_lock_irqsave(&chip->reg_lock, flags); result = __maestro_read(chip, reg); spin_unlock_irqrestore(&chip->reg_lock, flags); return result; } /* Wait for the codec bus to be free */ static int snd_es1968_ac97_wait(struct es1968 *chip) { int timeout = 100000; while (timeout-- > 0) { if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) return 0; cond_resched(); } dev_dbg(chip->card->dev, "ac97 timeout\n"); return 1; /* timeout */ } static int snd_es1968_ac97_wait_poll(struct es1968 *chip) { int timeout = 100000; while (timeout-- > 0) { if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) return 0; } dev_dbg(chip->card->dev, "ac97 timeout\n"); return 1; /* timeout */ } static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct es1968 *chip = ac97->private_data; snd_es1968_ac97_wait(chip); /* Write the bus */ outw(val, chip->io_port + ESM_AC97_DATA); /*msleep(1);*/ outb(reg, chip->io_port + ESM_AC97_INDEX); /*msleep(1);*/ } static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { u16 data = 0; struct es1968 *chip = ac97->private_data; snd_es1968_ac97_wait(chip); outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); /*msleep(1);*/ if (!snd_es1968_ac97_wait_poll(chip)) { data = inw(chip->io_port + ESM_AC97_DATA); /*msleep(1);*/ } return data; } /* no spinlock */ static void apu_index_set(struct es1968 *chip, u16 index) { int i; __maestro_write(chip, IDR1_CRAM_POINTER, index); for (i = 0; i < 1000; i++) if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) return; dev_dbg(chip->card->dev, "APU register select failed. (Timeout)\n"); } /* no spinlock */ static void apu_data_set(struct es1968 *chip, u16 data) { int i; for (i = 0; i < 1000; i++) { if (__maestro_read(chip, IDR0_DATA_PORT) == data) return; __maestro_write(chip, IDR0_DATA_PORT, data); } dev_dbg(chip->card->dev, "APU register set probably failed (Timeout)!\n"); } /* no spinlock */ static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) { if (snd_BUG_ON(channel >= NR_APUS)) return; #ifdef CONFIG_PM_SLEEP chip->apu_map[channel][reg] = data; #endif reg |= (channel << 4); apu_index_set(chip, reg); apu_data_set(chip, data); } static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); __apu_set_register(chip, channel, reg, data); spin_unlock_irqrestore(&chip->reg_lock, flags); } static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) { if (snd_BUG_ON(channel >= NR_APUS)) return 0; reg |= (channel << 4); apu_index_set(chip, reg); return __maestro_read(chip, IDR0_DATA_PORT); } static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) { unsigned long flags; u16 v; spin_lock_irqsave(&chip->reg_lock, flags); v = __apu_get_register(chip, channel, reg); spin_unlock_irqrestore(&chip->reg_lock, flags); return v; } #if 0 /* ASSP is not supported */ static void assp_set_register(struct es1968 *chip, u32 reg, u32 value) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); outl(reg, chip->io_port + ASSP_INDEX); outl(value, chip->io_port + ASSP_DATA); spin_unlock_irqrestore(&chip->reg_lock, flags); } static u32 assp_get_register(struct es1968 *chip, u32 reg) { unsigned long flags; u32 value; spin_lock_irqsave(&chip->reg_lock, flags); outl(reg, chip->io_port + ASSP_INDEX); value = inl(chip->io_port + ASSP_DATA); spin_unlock_irqrestore(&chip->reg_lock, flags); return value; } #endif static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); outw(reg, chip->io_port + WC_INDEX); outw(value, chip->io_port + WC_DATA); spin_unlock_irqrestore(&chip->reg_lock, flags); } static u16 wave_get_register(struct es1968 *chip, u16 reg) { unsigned long flags; u16 value; spin_lock_irqsave(&chip->reg_lock, flags); outw(reg, chip->io_port + WC_INDEX); value = inw(chip->io_port + WC_DATA); spin_unlock_irqrestore(&chip->reg_lock, flags); return value; } /* ******************* * Bob the Timer! * *******************/ static void snd_es1968_bob_stop(struct es1968 *chip) { u16 reg; reg = __maestro_read(chip, 0x11); reg &= ~ESM_BOB_ENABLE; __maestro_write(chip, 0x11, reg); reg = __maestro_read(chip, 0x17); reg &= ~ESM_BOB_START; __maestro_write(chip, 0x17, reg); } static void snd_es1968_bob_start(struct es1968 *chip) { int prescale; int divide; /* compute ideal interrupt frequency for buffer size & play rate */ /* first, find best prescaler value to match freq */ for (prescale = 5; prescale < 12; prescale++) if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) break; /* next, back off prescaler whilst getting divider into optimum range */ divide = 1; while ((prescale > 5) && (divide < 32)) { prescale--; divide <<= 1; } divide >>= 1; /* now fine-tune the divider for best match */ for (; divide < 31; divide++) if (chip->bob_freq > ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; /* divide = 0 is illegal, but don't let prescale = 4! */ if (divide == 0) { divide++; if (prescale > 5) prescale--; } else if (divide > 1) divide--; __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ /* Now set IDR 11/17 */ __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); } /* call with substream spinlock */ static void snd_es1968_bob_inc(struct es1968 *chip, int freq) { chip->bobclient++; if (chip->bobclient == 1) { chip->bob_freq = freq; snd_es1968_bob_start(chip); } else if (chip->bob_freq < freq) { snd_es1968_bob_stop(chip); chip->bob_freq = freq; snd_es1968_bob_start(chip); } } /* call with substream spinlock */ static void snd_es1968_bob_dec(struct es1968 *chip) { chip->bobclient--; if (chip->bobclient <= 0) snd_es1968_bob_stop(chip); else if (chip->bob_freq > ESM_BOB_FREQ) { /* check reduction of timer frequency */ int max_freq = ESM_BOB_FREQ; struct esschan *es; list_for_each_entry(es, &chip->substream_list, list) { if (max_freq < es->bob_freq) max_freq = es->bob_freq; } if (max_freq != chip->bob_freq) { snd_es1968_bob_stop(chip); chip->bob_freq = max_freq; snd_es1968_bob_start(chip); } } } static int snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es, struct snd_pcm_runtime *runtime) { /* we acquire 4 interrupts per period for precise control.. */ int freq = runtime->rate * 4; if (es->fmt & ESS_FMT_STEREO) freq <<= 1; if (es->fmt & ESS_FMT_16BIT) freq <<= 1; freq /= es->frag_size; if (freq < ESM_BOB_FREQ) freq = ESM_BOB_FREQ; else if (freq > ESM_BOB_FREQ_MAX) freq = ESM_BOB_FREQ_MAX; return freq; } /************* * PCM Part * *************/ static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq) { u32 rate = (freq << 16) / chip->clock; #if 0 /* XXX: do we need this? */ if (rate > 0x10000) rate = 0x10000; #endif return rate; } /* get current pointer */ static inline unsigned int snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es) { unsigned int offset; offset = apu_get_register(chip, es->apu[0], 5); offset -= es->base[0]; return (offset & 0xFFFE); /* hardware is in words */ } static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq) { apu_set_register(chip, apu, 2, (apu_get_register(chip, apu, 2) & 0x00FF) | ((freq & 0xff) << 8) | 0x10); apu_set_register(chip, apu, 3, freq >> 8); } /* spin lock held */ static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode) { /* set the APU mode */ __apu_set_register(esm, apu, 0, (__apu_get_register(esm, apu, 0) & 0xff0f) | (mode << 4)); } static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es) { spin_lock(&chip->reg_lock); __apu_set_register(chip, es->apu[0], 5, es->base[0]); snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); if (es->mode == ESM_MODE_CAPTURE) { __apu_set_register(chip, es->apu[2], 5, es->base[2]); snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); } if (es->fmt & ESS_FMT_STEREO) { __apu_set_register(chip, es->apu[1], 5, es->base[1]); snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); if (es->mode == ESM_MODE_CAPTURE) { __apu_set_register(chip, es->apu[3], 5, es->base[3]); snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); } } spin_unlock(&chip->reg_lock); } static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es) { spin_lock(&chip->reg_lock); snd_es1968_trigger_apu(chip, es->apu[0], 0); snd_es1968_trigger_apu(chip, es->apu[1], 0); if (es->mode == ESM_MODE_CAPTURE) { snd_es1968_trigger_apu(chip, es->apu[2], 0); snd_es1968_trigger_apu(chip, es->apu[3], 0); } spin_unlock(&chip->reg_lock); } /* set the wavecache control reg */ static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es, int channel, u32 addr, int capture) { u32 tmpval = (addr - 0x10) & 0xFFF8; if (! capture) { if (!(es->fmt & ESS_FMT_16BIT)) tmpval |= 4; /* 8bit */ if (es->fmt & ESS_FMT_STEREO) tmpval |= 2; /* stereo */ } /* set the wavecache control reg */ wave_set_register(chip, es->apu[channel] << 3, tmpval); #ifdef CONFIG_PM_SLEEP es->wc_map[channel] = tmpval; #endif } static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es, struct snd_pcm_runtime *runtime) { u32 pa; int high_apu = 0; int channel, apu; int i, size; unsigned long flags; u32 freq; size = es->dma_size >> es->wav_shift; if (es->fmt & ESS_FMT_STEREO) high_apu++; for (channel = 0; channel <= high_apu; channel++) { apu = es->apu[channel]; snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); /* Offset to PCMBAR */ pa = es->memory->buf.addr; pa -= chip->dma.addr; pa >>= 1; /* words */ pa |= 0x00400000; /* System RAM (Bit 22) */ if (es->fmt & ESS_FMT_STEREO) { /* Enable stereo */ if (channel) pa |= 0x00800000; /* (Bit 23) */ if (es->fmt & ESS_FMT_16BIT) pa >>= 1; } /* base offset of dma calcs when reading the pointer on this left one */ es->base[channel] = pa & 0xFFFF; for (i = 0; i < 16; i++) apu_set_register(chip, apu, i, 0x0000); /* Load the buffer into the wave engine */ apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); apu_set_register(chip, apu, 5, pa & 0xFFFF); apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); /* setting loop == sample len */ apu_set_register(chip, apu, 7, size); /* clear effects/env.. */ apu_set_register(chip, apu, 8, 0x0000); /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ apu_set_register(chip, apu, 9, 0xD000); /* clear routing stuff */ apu_set_register(chip, apu, 11, 0x0000); /* dma on, no envelopes, filter to all 1s) */ apu_set_register(chip, apu, 0, 0x400F); if (es->fmt & ESS_FMT_16BIT) es->apu_mode[channel] = ESM_APU_16BITLINEAR; else es->apu_mode[channel] = ESM_APU_8BITLINEAR; if (es->fmt & ESS_FMT_STEREO) { /* set panning: left or right */ /* Check: different panning. On my Canyon 3D Chipset the Channels are swapped. I don't know, about the output to the SPDif Link. Perhaps you have to change this and not the APU Regs 4-5. */ apu_set_register(chip, apu, 10, 0x8F00 | (channel ? 0 : 0x10)); es->apu_mode[channel] += 1; /* stereo */ } else apu_set_register(chip, apu, 10, 0x8F08); } spin_lock_irqsave(&chip->reg_lock, flags); /* clear WP interrupts */ outw(1, chip->io_port + 0x04); /* enable WP ints */ outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); spin_unlock_irqrestore(&chip->reg_lock, flags); freq = runtime->rate; /* set frequency */ if (freq > 48000) freq = 48000; if (freq < 4000) freq = 4000; /* hmmm.. */ if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) freq >>= 1; freq = snd_es1968_compute_rate(chip, freq); /* Load the frequency, turn on 6dB */ snd_es1968_apu_set_freq(chip, es->apu[0], freq); snd_es1968_apu_set_freq(chip, es->apu[1], freq); } static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel, unsigned int pa, unsigned int bsize, int mode, int route) { int i, apu = es->apu[channel]; es->apu_mode[channel] = mode; /* set the wavecache control reg */ snd_es1968_program_wavecache(chip, es, channel, pa, 1); /* Offset to PCMBAR */ pa -= chip->dma.addr; pa >>= 1; /* words */ /* base offset of dma calcs when reading the pointer on this left one */ es->base[channel] = pa & 0xFFFF; pa |= 0x00400000; /* bit 22 -> System RAM */ /* Begin loading the APU */ for (i = 0; i < 16; i++) apu_set_register(chip, apu, i, 0x0000); /* need to enable subgroups.. and we should probably have different groups for different /dev/dsps.. */ apu_set_register(chip, apu, 2, 0x8); /* Load the buffer into the wave engine */ apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); apu_set_register(chip, apu, 5, pa & 0xFFFF); apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); apu_set_register(chip, apu, 7, bsize); /* clear effects/env.. */ apu_set_register(chip, apu, 8, 0x00F0); /* amplitude now? sure. why not. */ apu_set_register(chip, apu, 9, 0x0000); /* set filter tune, radius, polar pan */ apu_set_register(chip, apu, 10, 0x8F08); /* route input */ apu_set_register(chip, apu, 11, route); /* dma on, no envelopes, filter to all 1s) */ apu_set_register(chip, apu, 0, 0x400F); } static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es, struct snd_pcm_runtime *runtime) { int size; u32 freq; unsigned long flags; size = es->dma_size >> es->wav_shift; /* APU assignments: 0 = mono/left SRC 1 = right SRC 2 = mono/left Input Mixer 3 = right Input Mixer */ /* data seems to flow from the codec, through an apu into the 'mixbuf' bit of page, then through the SRC apu and out to the real 'buffer'. ok. sure. */ /* input mixer (left/mono) */ /* parallel in crap, see maestro reg 0xC [8-11] */ init_capture_apu(chip, es, 2, es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ ESM_APU_INPUTMIXER, 0x14); /* SRC (left/mono); get input from inputing apu */ init_capture_apu(chip, es, 0, es->memory->buf.addr, size, ESM_APU_SRCONVERTOR, es->apu[2]); if (es->fmt & ESS_FMT_STEREO) { /* input mixer (right) */ init_capture_apu(chip, es, 3, es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, ESM_MIXBUF_SIZE/4, /* in words */ ESM_APU_INPUTMIXER, 0x15); /* SRC (right) */ init_capture_apu(chip, es, 1, es->memory->buf.addr + size*2, size, ESM_APU_SRCONVERTOR, es->apu[3]); } freq = runtime->rate; /* Sample Rate conversion APUs don't like 0x10000 for their rate */ if (freq > 47999) freq = 47999; if (freq < 4000) freq = 4000; freq = snd_es1968_compute_rate(chip, freq); /* Load the frequency, turn on 6dB */ snd_es1968_apu_set_freq(chip, es->apu[0], freq); snd_es1968_apu_set_freq(chip, es->apu[1], freq); /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ freq = 0x10000; snd_es1968_apu_set_freq(chip, es->apu[2], freq); snd_es1968_apu_set_freq(chip, es->apu[3], freq); spin_lock_irqsave(&chip->reg_lock, flags); /* clear WP interrupts */ outw(1, chip->io_port + 0x04); /* enable WP ints */ outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); spin_unlock_irqrestore(&chip->reg_lock, flags); } /******************* * ALSA Interface * *******************/ static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct esschan *es = runtime->private_data; es->dma_size = snd_pcm_lib_buffer_bytes(substream); es->frag_size = snd_pcm_lib_period_bytes(substream); es->wav_shift = 1; /* maestro handles always 16bit */ es->fmt = 0; if (snd_pcm_format_width(runtime->format) == 16) es->fmt |= ESS_FMT_16BIT; if (runtime->channels > 1) { es->fmt |= ESS_FMT_STEREO; if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ es->wav_shift++; } es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); switch (es->mode) { case ESM_MODE_PLAY: snd_es1968_playback_setup(chip, es, runtime); break; case ESM_MODE_CAPTURE: snd_es1968_capture_setup(chip, es, runtime); break; } return 0; } static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct esschan *es = substream->runtime->private_data; spin_lock(&chip->substream_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: if (es->running) break; snd_es1968_bob_inc(chip, es->bob_freq); es->count = 0; es->hwptr = 0; snd_es1968_pcm_start(chip, es); es->running = 1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: if (! es->running) break; snd_es1968_pcm_stop(chip, es); es->running = 0; snd_es1968_bob_dec(chip); break; } spin_unlock(&chip->substream_lock); return 0; } static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct esschan *es = substream->runtime->private_data; unsigned int ptr; ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; return bytes_to_frames(substream->runtime, ptr % es->dma_size); } static const struct snd_pcm_hardware snd_es1968_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | /*SNDRV_PCM_INFO_PAUSE |*/ SNDRV_PCM_INFO_RESUME), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 65536, .period_bytes_min = 256, .period_bytes_max = 65536, .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static const struct snd_pcm_hardware snd_es1968_capture = { .info = (SNDRV_PCM_INFO_NONINTERLEAVED | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER | /*SNDRV_PCM_INFO_PAUSE |*/ SNDRV_PCM_INFO_RESUME), .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 65536, .period_bytes_min = 256, .period_bytes_max = 65536, .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; /* ************************* * DMA memory management * *************************/ /* Because the Maestro can only take addresses relative to the PCM base address register :( */ static int calc_available_memory_size(struct es1968 *chip) { int max_size = 0; struct esm_memory *buf; mutex_lock(&chip->memory_mutex); list_for_each_entry(buf, &chip->buf_list, list) { if (buf->empty && buf->buf.bytes > max_size) max_size = buf->buf.bytes; } mutex_unlock(&chip->memory_mutex); if (max_size >= 128*1024) max_size = 127*1024; return max_size; } /* allocate a new memory chunk with the specified size */ static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size) { struct esm_memory *buf; size = ALIGN(size, ESM_MEM_ALIGN); mutex_lock(&chip->memory_mutex); list_for_each_entry(buf, &chip->buf_list, list) { if (buf->empty && buf->buf.bytes >= size) goto __found; } mutex_unlock(&chip->memory_mutex); return NULL; __found: if (buf->buf.bytes > size) { struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); if (chunk == NULL) { mutex_unlock(&chip->memory_mutex); return NULL; } chunk->buf = buf->buf; chunk->buf.bytes -= size; chunk->buf.area += size; chunk->buf.addr += size; chunk->empty = 1; buf->buf.bytes = size; list_add(&chunk->list, &buf->list); } buf->empty = 0; mutex_unlock(&chip->memory_mutex); return buf; } /* free a memory chunk */ static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf) { struct esm_memory *chunk; mutex_lock(&chip->memory_mutex); buf->empty = 1; if (buf->list.prev != &chip->buf_list) { chunk = list_entry(buf->list.prev, struct esm_memory, list); if (chunk->empty) { chunk->buf.bytes += buf->buf.bytes; list_del(&buf->list); kfree(buf); buf = chunk; } } if (buf->list.next != &chip->buf_list) { chunk = list_entry(buf->list.next, struct esm_memory, list); if (chunk->empty) { buf->buf.bytes += chunk->buf.bytes; list_del(&chunk->list); kfree(chunk); } } mutex_unlock(&chip->memory_mutex); } static void snd_es1968_free_dmabuf(struct es1968 *chip) { struct list_head *p; if (! chip->dma.area) return; snd_dma_free_pages(&chip->dma); while ((p = chip->buf_list.next) != &chip->buf_list) { struct esm_memory *chunk = list_entry(p, struct esm_memory, list); list_del(p); kfree(chunk); } } static int snd_es1968_init_dmabuf(struct es1968 *chip) { int err; struct esm_memory *chunk; err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, chip->total_bufsize, &chip->dma); if (err < 0 || ! chip->dma.area) { dev_err(chip->card->dev, "can't allocate dma pages for size %d\n", chip->total_bufsize); return -ENOMEM; } if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { snd_dma_free_pages(&chip->dma); dev_err(chip->card->dev, "DMA buffer beyond 256MB.\n"); return -ENOMEM; } INIT_LIST_HEAD(&chip->buf_list); /* allocate an empty chunk */ chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); if (chunk == NULL) { snd_es1968_free_dmabuf(chip); return -ENOMEM; } memset(chip->dma.area, 0, ESM_MEM_ALIGN); chunk->buf = chip->dma; chunk->buf.area += ESM_MEM_ALIGN; chunk->buf.addr += ESM_MEM_ALIGN; chunk->buf.bytes -= ESM_MEM_ALIGN; chunk->empty = 1; list_add(&chunk->list, &chip->buf_list); return 0; } /* setup the dma_areas */ /* buffer is extracted from the pre-allocated memory chunk */ static int snd_es1968_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct esschan *chan = runtime->private_data; int size = params_buffer_bytes(hw_params); if (chan->memory) { if (chan->memory->buf.bytes >= size) { runtime->dma_bytes = size; return 0; } snd_es1968_free_memory(chip, chan->memory); } chan->memory = snd_es1968_new_memory(chip, size); if (chan->memory == NULL) { dev_dbg(chip->card->dev, "cannot allocate dma buffer: size = %d\n", size); return -ENOMEM; } snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); return 1; /* area was changed */ } /* remove dma areas if allocated */ static int snd_es1968_hw_free(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct esschan *chan; if (runtime->private_data == NULL) return 0; chan = runtime->private_data; if (chan->memory) { snd_es1968_free_memory(chip, chan->memory); chan->memory = NULL; } return 0; } /* * allocate APU pair */ static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type) { int apu; for (apu = 0; apu < NR_APUS; apu += 2) { if (chip->apu[apu] == ESM_APU_FREE && chip->apu[apu + 1] == ESM_APU_FREE) { chip->apu[apu] = chip->apu[apu + 1] = type; return apu; } } return -EBUSY; } /* * release APU pair */ static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu) { chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; } /****************** * PCM open/close * ******************/ static int snd_es1968_playback_open(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct esschan *es; int apu1; /* search 2 APUs */ apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); if (apu1 < 0) return apu1; es = kzalloc(sizeof(*es), GFP_KERNEL); if (!es) { snd_es1968_free_apu_pair(chip, apu1); return -ENOMEM; } es->apu[0] = apu1; es->apu[1] = apu1 + 1; es->apu_mode[0] = 0; es->apu_mode[1] = 0; es->running = 0; es->substream = substream; es->mode = ESM_MODE_PLAY; runtime->private_data = es; runtime->hw = snd_es1968_playback; runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = calc_available_memory_size(chip); spin_lock_irq(&chip->substream_lock); list_add(&es->list, &chip->substream_list); spin_unlock_irq(&chip->substream_lock); return 0; } static int snd_es1968_capture_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct es1968 *chip = snd_pcm_substream_chip(substream); struct esschan *es; int apu1, apu2; apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); if (apu1 < 0) return apu1; apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); if (apu2 < 0) { snd_es1968_free_apu_pair(chip, apu1); return apu2; } es = kzalloc(sizeof(*es), GFP_KERNEL); if (!es) { snd_es1968_free_apu_pair(chip, apu1); snd_es1968_free_apu_pair(chip, apu2); return -ENOMEM; } es->apu[0] = apu1; es->apu[1] = apu1 + 1; es->apu[2] = apu2; es->apu[3] = apu2 + 1; es->apu_mode[0] = 0; es->apu_mode[1] = 0; es->apu_mode[2] = 0; es->apu_mode[3] = 0; es->running = 0; es->substream = substream; es->mode = ESM_MODE_CAPTURE; /* get mixbuffer */ es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE); if (!es->mixbuf) { snd_es1968_free_apu_pair(chip, apu1); snd_es1968_free_apu_pair(chip, apu2); kfree(es); return -ENOMEM; } memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); runtime->private_data = es; runtime->hw = snd_es1968_capture; runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); spin_lock_irq(&chip->substream_lock); list_add(&es->list, &chip->substream_list); spin_unlock_irq(&chip->substream_lock); return 0; } static int snd_es1968_playback_close(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct esschan *es; if (substream->runtime->private_data == NULL) return 0; es = substream->runtime->private_data; spin_lock_irq(&chip->substream_lock); list_del(&es->list); spin_unlock_irq(&chip->substream_lock); snd_es1968_free_apu_pair(chip, es->apu[0]); kfree(es); return 0; } static int snd_es1968_capture_close(struct snd_pcm_substream *substream) { struct es1968 *chip = snd_pcm_substream_chip(substream); struct esschan *es; if (substream->runtime->private_data == NULL) return 0; es = substream->runtime->private_data; spin_lock_irq(&chip->substream_lock); list_del(&es->list); spin_unlock_irq(&chip->substream_lock); snd_es1968_free_memory(chip, es->mixbuf); snd_es1968_free_apu_pair(chip, es->apu[0]); snd_es1968_free_apu_pair(chip, es->apu[2]); kfree(es); return 0; } static const struct snd_pcm_ops snd_es1968_playback_ops = { .open = snd_es1968_playback_open, .close = snd_es1968_playback_close, .hw_params = snd_es1968_hw_params, .hw_free = snd_es1968_hw_free, .prepare = snd_es1968_pcm_prepare, .trigger = snd_es1968_pcm_trigger, .pointer = snd_es1968_pcm_pointer, }; static const struct snd_pcm_ops snd_es1968_capture_ops = { .open = snd_es1968_capture_open, .close = snd_es1968_capture_close, .hw_params = snd_es1968_hw_params, .hw_free = snd_es1968_hw_free, .prepare = snd_es1968_pcm_prepare, .trigger = snd_es1968_pcm_trigger, .pointer = snd_es1968_pcm_pointer, }; /* * measure clock */ #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ static void es1968_measure_clock(struct es1968 *chip) { int i, apu; unsigned int pa, offset, t; struct esm_memory *memory; ktime_t start_time, stop_time; ktime_t diff; if (chip->clock == 0) chip->clock = 48000; /* default clock value */ /* search 2 APUs (although one apu is enough) */ apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); if (apu < 0) { dev_err(chip->card->dev, "Hmm, cannot find empty APU pair!?\n"); return; } memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE); if (!memory) { dev_warn(chip->card->dev, "cannot allocate dma buffer - using default clock %d\n", chip->clock); snd_es1968_free_apu_pair(chip, apu); return; } memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); pa |= 0x00400000; /* System RAM (Bit 22) */ /* initialize apu */ for (i = 0; i < 16; i++) apu_set_register(chip, apu, i, 0x0000); apu_set_register(chip, apu, 0, 0x400f); apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); apu_set_register(chip, apu, 5, pa & 0xffff); apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); apu_set_register(chip, apu, 8, 0x0000); apu_set_register(chip, apu, 9, 0xD000); apu_set_register(chip, apu, 10, 0x8F08); apu_set_register(chip, apu, 11, 0x0000); spin_lock_irq(&chip->reg_lock); outw(1, chip->io_port + 0x04); /* clear WP interrupts */ outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ spin_unlock_irq(&chip->reg_lock); snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ chip->in_measurement = 1; chip->measure_apu = apu; spin_lock_irq(&chip->reg_lock); snd_es1968_bob_inc(chip, ESM_BOB_FREQ); __apu_set_register(chip, apu, 5, pa & 0xffff); snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); start_time = ktime_get(); spin_unlock_irq(&chip->reg_lock); msleep(50); spin_lock_irq(&chip->reg_lock); offset = __apu_get_register(chip, apu, 5); stop_time = ktime_get(); snd_es1968_trigger_apu(chip, apu, 0); /* stop */ snd_es1968_bob_dec(chip); chip->in_measurement = 0; spin_unlock_irq(&chip->reg_lock); /* check the current position */ offset -= (pa & 0xffff); offset &= 0xfffe; offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); diff = ktime_sub(stop_time, start_time); t = ktime_to_us(diff); if (t == 0) { dev_err(chip->card->dev, "?? calculation error..\n"); } else { offset *= 1000; offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; if (offset < 47500 || offset > 48500) { if (offset >= 40000 && offset <= 50000) chip->clock = (chip->clock * offset) / 48000; } dev_info(chip->card->dev, "clocking to %d\n", chip->clock); } snd_es1968_free_memory(chip, memory); snd_es1968_free_apu_pair(chip, apu); } /* */ static void snd_es1968_pcm_free(struct snd_pcm *pcm) { struct es1968 *esm = pcm->private_data; snd_es1968_free_dmabuf(esm); esm->pcm = NULL; } static int snd_es1968_pcm(struct es1968 *chip, int device) { struct snd_pcm *pcm; int err; /* get DMA buffer */ err = snd_es1968_init_dmabuf(chip); if (err < 0) return err; /* set PCMBAR */ wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); err = snd_pcm_new(chip->card, "ESS Maestro", device, chip->playback_streams, chip->capture_streams, &pcm); if (err < 0) return err; pcm->private_data = chip; pcm->private_free = snd_es1968_pcm_free; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); pcm->info_flags = 0; strcpy(pcm->name, "ESS Maestro"); chip->pcm = pcm; return 0; } /* * suppress jitter on some maestros when playing stereo */ static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es) { unsigned int cp1; unsigned int cp2; unsigned int diff; cp1 = __apu_get_register(chip, 0, 5); cp2 = __apu_get_register(chip, 1, 5); diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1); if (diff > 1) __maestro_write(chip, IDR0_DATA_PORT, cp1); } /* * update pointer */ static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es) { unsigned int hwptr; unsigned int diff; struct snd_pcm_substream *subs = es->substream; if (subs == NULL || !es->running) return; hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; hwptr %= es->dma_size; diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; es->hwptr = hwptr; es->count += diff; if (es->count > es->frag_size) { spin_unlock(&chip->substream_lock); snd_pcm_period_elapsed(subs); spin_lock(&chip->substream_lock); es->count %= es->frag_size; } } /* The hardware volume works by incrementing / decrementing 2 counters (without wrap around) in response to volume button presses and then generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 of a byte wide register. The meaning of bits 0 and 4 is unknown. */ static void es1968_update_hw_volume(struct work_struct *work) { struct es1968 *chip = container_of(work, struct es1968, hwvol_work); int x, val; /* Figure out which volume control button was pushed, based on differences from the default register values. */ x = inb(chip->io_port + 0x1c) & 0xee; /* Reset the volume control registers. */ outb(0x88, chip->io_port + 0x1c); outb(0x88, chip->io_port + 0x1d); outb(0x88, chip->io_port + 0x1e); outb(0x88, chip->io_port + 0x1f); if (chip->in_suspend) return; #ifndef CONFIG_SND_ES1968_INPUT if (! chip->master_switch || ! chip->master_volume) return; val = snd_ac97_read(chip->ac97, AC97_MASTER); switch (x) { case 0x88: /* mute */ val ^= 0x8000; break; case 0xaa: /* volume up */ if ((val & 0x7f) > 0) val--; if ((val & 0x7f00) > 0) val -= 0x0100; break; case 0x66: /* volume down */ if ((val & 0x7f) < 0x1f) val++; if ((val & 0x7f00) < 0x1f00) val += 0x0100; break; } if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->master_volume->id); #else if (!chip->input_dev) return; val = 0; switch (x) { case 0x88: /* The counters have not changed, yet we've received a HV interrupt. According to tests run by various people this happens when pressing the mute button. */ val = KEY_MUTE; break; case 0xaa: /* counters increased by 1 -> volume up */ val = KEY_VOLUMEUP; break; case 0x66: /* counters decreased by 1 -> volume down */ val = KEY_VOLUMEDOWN; break; } if (val) { input_report_key(chip->input_dev, val, 1); input_sync(chip->input_dev); input_report_key(chip->input_dev, val, 0); input_sync(chip->input_dev); } #endif } /* * interrupt handler */ static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id) { struct es1968 *chip = dev_id; u32 event; event = inb(chip->io_port + 0x1A); if (!event) return IRQ_NONE; outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); if (event & ESM_HWVOL_IRQ) schedule_work(&chip->hwvol_work); /* else ack 'em all, i imagine */ outb(0xFF, chip->io_port + 0x1A); if ((event & ESM_MPU401_IRQ) && chip->rmidi) { snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); } if (event & ESM_SOUND_IRQ) { struct esschan *es; spin_lock(&chip->substream_lock); list_for_each_entry(es, &chip->substream_list, list) { if (es->running) { snd_es1968_update_pcm(chip, es); if (es->fmt & ESS_FMT_STEREO) snd_es1968_suppress_jitter(chip, es); } } spin_unlock(&chip->substream_lock); if (chip->in_measurement) { unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); if (curp < chip->measure_lastpos) chip->measure_count++; chip->measure_lastpos = curp; } } return IRQ_HANDLED; } /* * Mixer stuff */ static int snd_es1968_mixer(struct es1968 *chip) { struct snd_ac97_bus *pbus; struct snd_ac97_template ac97; int err; static const struct snd_ac97_bus_ops ops = { .write = snd_es1968_ac97_write, .read = snd_es1968_ac97_read, }; err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus); if (err < 0) return err; pbus->no_vra = 1; /* ES1968 doesn't need VRA */ memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); if (err < 0) return err; #ifndef CONFIG_SND_ES1968_INPUT /* attach master switch / volumes for h/w volume control */ chip->master_switch = snd_ctl_find_id_mixer(chip->card, "Master Playback Switch"); chip->master_volume = snd_ctl_find_id_mixer(chip->card, "Master Playback Volume"); #endif return 0; } /* * reset ac97 codec */ static void snd_es1968_ac97_reset(struct es1968 *chip) { unsigned long ioaddr = chip->io_port; unsigned short save_ringbus_a; unsigned short save_68; unsigned short w; unsigned int vend; /* save configuration */ save_ringbus_a = inw(ioaddr + 0x36); //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ /* set command/status address i/o to 1st codec */ outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); /* disable ac link */ outw(0x0000, ioaddr + 0x36); save_68 = inw(ioaddr + 0x68); pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); if (w & 1) save_68 |= 0x10; outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ outw(0x0001, ioaddr + 0x68); /* gpio write */ outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ udelay(20); outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ msleep(20); outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); /* now the second codec */ /* disable ac link */ outw(0x0000, ioaddr + 0x36); outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ save_68 = inw(ioaddr + 0x68); outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ udelay(20); outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ msleep(500); //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); #if 0 /* the loop here needs to be much better if we want it.. */ dev_info(chip->card->dev, "trying software reset\n"); /* try and do a software reset */ outb(0x80 | 0x7c, ioaddr + 0x30); for (w = 0;; w++) { if ((inw(ioaddr + 0x30) & 1) == 0) { if (inb(ioaddr + 0x32) != 0) break; outb(0x80 | 0x7d, ioaddr + 0x30); if (((inw(ioaddr + 0x30) & 1) == 0) && (inb(ioaddr + 0x32) != 0)) break; outb(0x80 | 0x7f, ioaddr + 0x30); if (((inw(ioaddr + 0x30) & 1) == 0) && (inb(ioaddr + 0x32) != 0)) break; } if (w > 10000) { outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */ msleep(500); /* oh my.. */ outb(inb(ioaddr + 0x37) & ~0x08, ioaddr + 0x37); udelay(1); outw(0x80, ioaddr + 0x30); for (w = 0; w < 10000; w++) { if ((inw(ioaddr + 0x30) & 1) == 0) break; } } } #endif if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { /* turn on external amp? */ outw(0xf9ff, ioaddr + 0x64); outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); outw(0x0209, ioaddr + 0x60); } /* restore.. */ outw(save_ringbus_a, ioaddr + 0x36); /* Turn on the 978 docking chip. First frob the "master output enable" bit, then set most of the playback volume control registers to max. */ outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); outb(0xff, ioaddr+0xc3); outb(0xff, ioaddr+0xc4); outb(0xff, ioaddr+0xc6); outb(0xff, ioaddr+0xc8); outb(0x3f, ioaddr+0xcf); outb(0x3f, ioaddr+0xd0); } static void snd_es1968_reset(struct es1968 *chip) { /* Reset */ outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, chip->io_port + ESM_PORT_HOST_IRQ); udelay(10); outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); udelay(10); } /* * initialize maestro chip */ static void snd_es1968_chip_init(struct es1968 *chip) { struct pci_dev *pci = chip->pci; int i; unsigned long iobase = chip->io_port; u16 w; u32 n; /* We used to muck around with pci config space that * we had no business messing with. We don't know enough * about the machine to know which DMA mode is appropriate, * etc. We were guessing wrong on some machines and making * them unhappy. We now trust in the BIOS to do things right, * which almost certainly means a new host of problems will * arise with broken BIOS implementations. screw 'em. * We're already intolerant of machines that don't assign * IRQs. */ /* Config Reg A */ pci_read_config_word(pci, ESM_CONFIG_A, &w); w &= ~DMA_CLEAR; /* Clear DMA bits */ w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ w &= ~SAFEGUARD; /* Safeguard off */ w |= POST_WRITE; /* Posted write */ w |= PCI_TIMING; /* PCI timing on */ /* XXX huh? claims to be reserved.. */ w &= ~SWAP_LR; /* swap left/right seems to only have effect on SB Emulation */ w &= ~SUBTR_DECODE; /* Subtractive decode off */ pci_write_config_word(pci, ESM_CONFIG_A, w); /* Config Reg B */ pci_read_config_word(pci, ESM_CONFIG_B, &w); w &= ~(1 << 15); /* Turn off internal clock multiplier */ /* XXX how do we know which to use? */ w &= ~(1 << 14); /* External clock */ w &= ~SPDIF_CONFB; /* disable S/PDIF output */ w |= HWV_CONFB; /* HWV on */ w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ w &= ~GPIO_CONFB; /* GPIO 4:5 */ w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ w &= ~(1 << 1); /* reserved, always write 0 */ w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ pci_write_config_word(pci, ESM_CONFIG_B, w); /* DDMA off */ pci_read_config_word(pci, ESM_DDMA, &w); w &= ~(1 << 0); pci_write_config_word(pci, ESM_DDMA, w); /* * Legacy mode */ pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */ w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); /* Set up 978 docking control chip. */ pci_read_config_word(pci, 0x58, &w); w|=1<<2; /* Enable 978. */ w|=1<<3; /* Turn on 978 hardware volume control. */ w&=~(1<<11); /* Turn on 978 mixer volume control. */ pci_write_config_word(pci, 0x58, w); /* Sound Reset */ snd_es1968_reset(chip); /* * Ring Bus Setup */ /* setup usual 0x34 stuff.. 0x36 may be chip specific */ outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ udelay(20); outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ udelay(20); /* * Reset the CODEC */ snd_es1968_ac97_reset(chip); /* Ring Bus Control B */ n = inl(iobase + ESM_RING_BUS_CONTR_B); n &= ~RINGB_EN_SPDIF; /* SPDIF off */ //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ outl(n, iobase + ESM_RING_BUS_CONTR_B); /* Set hardware volume control registers to midpoints. We can tell which button was pushed based on how they change. */ outb(0x88, iobase+0x1c); outb(0x88, iobase+0x1d); outb(0x88, iobase+0x1e); outb(0x88, iobase+0x1f); /* it appears some maestros (dell 7500) only work if these are set, regardless of whether we use the assp or not. */ outb(0, iobase + ASSP_CONTROL_B); outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ /* * set up wavecache */ for (i = 0; i < 16; i++) { /* Write 0 into the buffer area 0x1E0->1EF */ outw(0x01E0 + i, iobase + WC_INDEX); outw(0x0000, iobase + WC_DATA); /* The 1.10 test program seem to write 0 into the buffer area * 0x1D0-0x1DF too.*/ outw(0x01D0 + i, iobase + WC_INDEX); outw(0x0000, iobase + WC_DATA); } wave_set_register(chip, IDR7_WAVE_ROMRAM, (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); wave_set_register(chip, IDR7_WAVE_ROMRAM, wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); wave_set_register(chip, IDR7_WAVE_ROMRAM, wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); wave_set_register(chip, IDR7_WAVE_ROMRAM, wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); maestro_write(chip, IDR2_CRAM_DATA, 0x0000); /* Now back to the DirectSound stuff */ /* audio serial configuration.. ? */ maestro_write(chip, 0x08, 0xB004); maestro_write(chip, 0x09, 0x001B); maestro_write(chip, 0x0A, 0x8000); maestro_write(chip, 0x0B, 0x3F37); maestro_write(chip, 0x0C, 0x0098); /* parallel in, has something to do with recording :) */ maestro_write(chip, 0x0C, (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); /* parallel out */ maestro_write(chip, 0x0C, (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); maestro_write(chip, 0x0D, 0x7632); /* Wave cache control on - test off, sg off, enable, enable extra chans 1Mb */ w = inw(iobase + WC_CONTROL); w &= ~0xFA00; /* Seems to be reserved? I don't know */ w |= 0xA000; /* reserved... I don't know */ w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable Seems to crash the Computer if enabled... */ w |= 0x0100; /* Wave Cache Operation Enabled */ w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ w &= ~0x0060; /* Clear Wavtable Size */ w |= 0x0020; /* Wavetable Size : 1MB */ /* Bit 4 is reserved */ w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ /* Bit 1 is reserved */ w &= ~0x0001; /* Test Mode off */ outw(w, iobase + WC_CONTROL); /* Now clear the APU control ram */ for (i = 0; i < NR_APUS; i++) { for (w = 0; w < NR_APU_REGS; w++) apu_set_register(chip, i, w, 0); } } /* Enable IRQ's */ static void snd_es1968_start_irq(struct es1968 *chip) { unsigned short w; w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; if (chip->rmidi) w |= ESM_HIRQ_MPU401; outb(w, chip->io_port + 0x1A); outw(w, chip->io_port + ESM_PORT_HOST_IRQ); } #ifdef CONFIG_PM_SLEEP /* * PM support */ static int es1968_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct es1968 *chip = card->private_data; if (! chip->do_pm) return 0; chip->in_suspend = 1; cancel_work_sync(&chip->hwvol_work); snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_ac97_suspend(chip->ac97); snd_es1968_bob_stop(chip); return 0; } static int es1968_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct es1968 *chip = card->private_data; struct esschan *es; if (! chip->do_pm) return 0; snd_es1968_chip_init(chip); /* need to restore the base pointers.. */ if (chip->dma.addr) { /* set PCMBAR */ wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); } snd_es1968_start_irq(chip); /* restore ac97 state */ snd_ac97_resume(chip->ac97); list_for_each_entry(es, &chip->substream_list, list) { switch (es->mode) { case ESM_MODE_PLAY: snd_es1968_playback_setup(chip, es, es->substream->runtime); break; case ESM_MODE_CAPTURE: snd_es1968_capture_setup(chip, es, es->substream->runtime); break; } } /* start timer again */ if (chip->bobclient) snd_es1968_bob_start(chip); snd_power_change_state(card, SNDRV_CTL_POWER_D0); chip->in_suspend = 0; return 0; } static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume); #define ES1968_PM_OPS &es1968_pm #else #define ES1968_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ #ifdef SUPPORT_JOYSTICK #define JOYSTICK_ADDR 0x200 static int snd_es1968_create_gameport(struct es1968 *chip, int dev) { struct gameport *gp; struct resource *r; u16 val; if (!joystick[dev]) return -ENODEV; r = devm_request_region(&chip->pci->dev, JOYSTICK_ADDR, 8, "ES1968 gameport"); if (!r) return -EBUSY; chip->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(chip->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); gameport_set_name(gp, "ES1968 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); gameport_set_dev_parent(gp, &chip->pci->dev); gp->io = JOYSTICK_ADDR; gameport_register_port(gp); return 0; } static void snd_es1968_free_gameport(struct es1968 *chip) { if (chip->gameport) { gameport_unregister_port(chip->gameport); chip->gameport = NULL; } } #else static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; } static inline void snd_es1968_free_gameport(struct es1968 *chip) { } #endif #ifdef CONFIG_SND_ES1968_INPUT static int snd_es1968_input_register(struct es1968 *chip) { struct input_dev *input_dev; int err; input_dev = devm_input_allocate_device(&chip->pci->dev); if (!input_dev) return -ENOMEM; snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", pci_name(chip->pci)); input_dev->name = chip->card->driver; input_dev->phys = chip->phys; input_dev->id.bustype = BUS_PCI; input_dev->id.vendor = chip->pci->vendor; input_dev->id.product = chip->pci->device; input_dev->dev.parent = &chip->pci->dev; __set_bit(EV_KEY, input_dev->evbit); __set_bit(KEY_MUTE, input_dev->keybit); __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); __set_bit(KEY_VOLUMEUP, input_dev->keybit); err = input_register_device(input_dev); if (err) return err; chip->input_dev = input_dev; return 0; } #endif /* CONFIG_SND_ES1968_INPUT */ #ifdef CONFIG_SND_ES1968_RADIO #define GPIO_DATA 0x60 #define IO_MASK 4 /* mask register offset from GPIO_DATA bits 1=unmask write to given bit */ #define IO_DIR 8 /* direction register offset from GPIO_DATA bits 0/1=read/write direction */ /* GPIO to TEA575x maps */ struct snd_es1968_tea575x_gpio { u8 data, clk, wren, most; char *name; }; static const struct snd_es1968_tea575x_gpio snd_es1968_tea575x_gpios[] = { { .data = 6, .clk = 7, .wren = 8, .most = 9, .name = "SF64-PCE2" }, { .data = 7, .clk = 8, .wren = 6, .most = 10, .name = "M56VAP" }, }; #define get_tea575x_gpio(chip) \ (&snd_es1968_tea575x_gpios[(chip)->tea575x_tuner]) static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins) { struct es1968 *chip = tea->private_data; struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip); u16 val = 0; val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0; val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0; val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0; outw(val, chip->io_port + GPIO_DATA); } static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea) { struct es1968 *chip = tea->private_data; struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip); u16 val = inw(chip->io_port + GPIO_DATA); u8 ret = 0; if (val & (1 << gpio.data)) ret |= TEA575X_DATA; if (val & (1 << gpio.most)) ret |= TEA575X_MOST; return ret; } static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output) { struct es1968 *chip = tea->private_data; unsigned long io = chip->io_port + GPIO_DATA; u16 odir = inw(io + IO_DIR); struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip); if (output) { outw(~((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren)), io + IO_MASK); outw(odir | (1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR); } else { outw(~((1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | (1 << gpio.most)), io + IO_MASK); outw((odir & ~((1 << gpio.data) | (1 << gpio.most))) | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR); } } static const struct snd_tea575x_ops snd_es1968_tea_ops = { .set_pins = snd_es1968_tea575x_set_pins, .get_pins = snd_es1968_tea575x_get_pins, .set_direction = snd_es1968_tea575x_set_direction, }; #endif static void snd_es1968_free(struct snd_card *card) { struct es1968 *chip = card->private_data; cancel_work_sync(&chip->hwvol_work); if (chip->io_port) { outw(1, chip->io_port + 0x04); /* clear WP interrupts */ outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ } #ifdef CONFIG_SND_ES1968_RADIO snd_tea575x_exit(&chip->tea); v4l2_device_unregister(&chip->v4l2_dev); #endif snd_es1968_free_gameport(chip); } struct ess_device_list { unsigned short type; /* chip type */ unsigned short vendor; /* subsystem vendor id */ }; static const struct ess_device_list pm_allowlist[] = { { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ { TYPE_MAESTRO2E, 0x1028 }, { TYPE_MAESTRO2E, 0x103c }, { TYPE_MAESTRO2E, 0x1179 }, { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ { TYPE_MAESTRO2E, 0x1558 }, { TYPE_MAESTRO2E, 0x125d }, /* a PCI card, e.g. Terratec DMX */ { TYPE_MAESTRO2, 0x125d }, /* a PCI card, e.g. SF64-PCE2 */ }; static const struct ess_device_list mpu_denylist[] = { { TYPE_MAESTRO2, 0x125d }, }; static int snd_es1968_create(struct snd_card *card, struct pci_dev *pci, int total_bufsize, int play_streams, int capt_streams, int chip_type, int do_pm, int radio_nr) { struct es1968 *chip = card->private_data; int i, err; /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; /* check, if we can restrict PCI DMA transfers to 28 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) { dev_err(card->dev, "architecture does not support 28bit PCI busmaster DMA\n"); return -ENXIO; } /* Set Vars */ chip->type = chip_type; spin_lock_init(&chip->reg_lock); spin_lock_init(&chip->substream_lock); INIT_LIST_HEAD(&chip->buf_list); INIT_LIST_HEAD(&chip->substream_list); mutex_init(&chip->memory_mutex); INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume); chip->card = card; chip->pci = pci; chip->irq = -1; chip->total_bufsize = total_bufsize; /* in bytes */ chip->playback_streams = play_streams; chip->capture_streams = capt_streams; err = pci_request_regions(pci, "ESS Maestro"); if (err < 0) return err; chip->io_port = pci_resource_start(pci, 0); if (devm_request_irq(&pci->dev, pci->irq, snd_es1968_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_es1968_free; /* Clear Maestro_map */ for (i = 0; i < 32; i++) chip->maestro_map[i] = 0; /* Clear Apu Map */ for (i = 0; i < NR_APUS; i++) chip->apu[i] = ESM_APU_FREE; /* just to be sure */ pci_set_master(pci); if (do_pm > 1) { /* disable power-management if not on the allowlist */ unsigned short vend; pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); for (i = 0; i < (int)ARRAY_SIZE(pm_allowlist); i++) { if (chip->type == pm_allowlist[i].type && vend == pm_allowlist[i].vendor) { do_pm = 1; break; } } if (do_pm > 1) { /* not matched; disabling pm */ dev_info(card->dev, "not attempting power management.\n"); do_pm = 0; } } chip->do_pm = do_pm; snd_es1968_chip_init(chip); #ifdef CONFIG_SND_ES1968_RADIO /* don't play with GPIOs on laptops */ if (chip->pci->subsystem_vendor != 0x125d) return 0; err = v4l2_device_register(&pci->dev, &chip->v4l2_dev); if (err < 0) return err; chip->tea.v4l2_dev = &chip->v4l2_dev; chip->tea.private_data = chip; chip->tea.radio_nr = radio_nr; chip->tea.ops = &snd_es1968_tea_ops; sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci)); for (i = 0; i < ARRAY_SIZE(snd_es1968_tea575x_gpios); i++) { chip->tea575x_tuner = i; if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) { dev_info(card->dev, "detected TEA575x radio type %s\n", get_tea575x_gpio(chip)->name); strscpy(chip->tea.card, get_tea575x_gpio(chip)->name, sizeof(chip->tea.card)); break; } } #endif return 0; } /* */ static int __snd_es1968_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct es1968 *chip; unsigned int i; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; if (total_bufsize[dev] < 128) total_bufsize[dev] = 128; if (total_bufsize[dev] > 4096) total_bufsize[dev] = 4096; err = snd_es1968_create(card, pci, total_bufsize[dev] * 1024, /* in bytes */ pcm_substreams_p[dev], pcm_substreams_c[dev], pci_id->driver_data, use_pm[dev], radio_nr[dev]); if (err < 0) return err; switch (chip->type) { case TYPE_MAESTRO2E: strcpy(card->driver, "ES1978"); strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); break; case TYPE_MAESTRO2: strcpy(card->driver, "ES1968"); strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); break; case TYPE_MAESTRO: strcpy(card->driver, "ESM1"); strcpy(card->shortname, "ESS Maestro 1"); break; } err = snd_es1968_pcm(chip, 0); if (err < 0) return err; err = snd_es1968_mixer(chip); if (err < 0) return err; if (enable_mpu[dev] == 2) { /* check the deny list */ unsigned short vend; pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); for (i = 0; i < ARRAY_SIZE(mpu_denylist); i++) { if (chip->type == mpu_denylist[i].type && vend == mpu_denylist[i].vendor) { enable_mpu[dev] = 0; break; } } } if (enable_mpu[dev]) { err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, chip->io_port + ESM_MPU401_PORT, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi); if (err < 0) dev_warn(card->dev, "skipping MPU-401 MIDI support..\n"); } snd_es1968_create_gameport(chip, dev); #ifdef CONFIG_SND_ES1968_INPUT err = snd_es1968_input_register(chip); if (err) dev_warn(card->dev, "Input device registration failed with error %i", err); #endif snd_es1968_start_irq(chip); chip->clock = clock[dev]; if (! chip->clock) es1968_measure_clock(chip); sprintf(card->longname, "%s at 0x%lx, irq %i", card->shortname, chip->io_port, chip->irq); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_es1968_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_es1968_probe(pci, pci_id)); } static struct pci_driver es1968_driver = { .name = KBUILD_MODNAME, .id_table = snd_es1968_ids, .probe = snd_es1968_probe, .driver = { .pm = ES1968_PM_OPS, }, }; module_pci_driver(es1968_driver);
linux-master
sound/pci/es1968.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for S3 SonicVibes soundcard * Copyright (c) by Jaroslav Kysela <[email protected]> * * BUGS: * It looks like 86c617 rev 3 doesn't supports DDMA buffers above 16MB? * Driver sometimes hangs... Nobody knows why at this moment... */ #include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/info.h> #include <sound/control.h> #include <sound/mpu401.h> #include <sound/opl3.h> #include <sound/initval.h> MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("S3 SonicVibes PCI"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ static bool reverb[SNDRV_CARDS]; static bool mge[SNDRV_CARDS]; static unsigned int dmaio = 0x7a00; /* DDMA i/o address */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for S3 SonicVibes soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for S3 SonicVibes soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable S3 SonicVibes soundcard."); module_param_array(reverb, bool, NULL, 0444); MODULE_PARM_DESC(reverb, "Enable reverb (SRAM is present) for S3 SonicVibes soundcard."); module_param_array(mge, bool, NULL, 0444); MODULE_PARM_DESC(mge, "MIC Gain Enable for S3 SonicVibes soundcard."); module_param_hw(dmaio, uint, ioport, 0444); MODULE_PARM_DESC(dmaio, "DDMA i/o base address for S3 SonicVibes soundcard."); /* * Enhanced port direct registers */ #define SV_REG(sonic, x) ((sonic)->enh_port + SV_REG_##x) #define SV_REG_CONTROL 0x00 /* R/W: CODEC/Mixer control register */ #define SV_ENHANCED 0x01 /* audio mode select - enhanced mode */ #define SV_TEST 0x02 /* test bit */ #define SV_REVERB 0x04 /* reverb enable */ #define SV_WAVETABLE 0x08 /* wavetable active / FM active if not set */ #define SV_INTA 0x20 /* INTA driving - should be always 1 */ #define SV_RESET 0x80 /* reset chip */ #define SV_REG_IRQMASK 0x01 /* R/W: CODEC/Mixer interrupt mask register */ #define SV_DMAA_MASK 0x01 /* mask DMA-A interrupt */ #define SV_DMAC_MASK 0x04 /* mask DMA-C interrupt */ #define SV_SPEC_MASK 0x08 /* special interrupt mask - should be always masked */ #define SV_UD_MASK 0x40 /* Up/Down button interrupt mask */ #define SV_MIDI_MASK 0x80 /* mask MIDI interrupt */ #define SV_REG_STATUS 0x02 /* R/O: CODEC/Mixer status register */ #define SV_DMAA_IRQ 0x01 /* DMA-A interrupt */ #define SV_DMAC_IRQ 0x04 /* DMA-C interrupt */ #define SV_SPEC_IRQ 0x08 /* special interrupt */ #define SV_UD_IRQ 0x40 /* Up/Down interrupt */ #define SV_MIDI_IRQ 0x80 /* MIDI interrupt */ #define SV_REG_INDEX 0x04 /* R/W: CODEC/Mixer index address register */ #define SV_MCE 0x40 /* mode change enable */ #define SV_TRD 0x80 /* DMA transfer request disabled */ #define SV_REG_DATA 0x05 /* R/W: CODEC/Mixer index data register */ /* * Enhanced port indirect registers */ #define SV_IREG_LEFT_ADC 0x00 /* Left ADC Input Control */ #define SV_IREG_RIGHT_ADC 0x01 /* Right ADC Input Control */ #define SV_IREG_LEFT_AUX1 0x02 /* Left AUX1 Input Control */ #define SV_IREG_RIGHT_AUX1 0x03 /* Right AUX1 Input Control */ #define SV_IREG_LEFT_CD 0x04 /* Left CD Input Control */ #define SV_IREG_RIGHT_CD 0x05 /* Right CD Input Control */ #define SV_IREG_LEFT_LINE 0x06 /* Left Line Input Control */ #define SV_IREG_RIGHT_LINE 0x07 /* Right Line Input Control */ #define SV_IREG_MIC 0x08 /* MIC Input Control */ #define SV_IREG_GAME_PORT 0x09 /* Game Port Control */ #define SV_IREG_LEFT_SYNTH 0x0a /* Left Synth Input Control */ #define SV_IREG_RIGHT_SYNTH 0x0b /* Right Synth Input Control */ #define SV_IREG_LEFT_AUX2 0x0c /* Left AUX2 Input Control */ #define SV_IREG_RIGHT_AUX2 0x0d /* Right AUX2 Input Control */ #define SV_IREG_LEFT_ANALOG 0x0e /* Left Analog Mixer Output Control */ #define SV_IREG_RIGHT_ANALOG 0x0f /* Right Analog Mixer Output Control */ #define SV_IREG_LEFT_PCM 0x10 /* Left PCM Input Control */ #define SV_IREG_RIGHT_PCM 0x11 /* Right PCM Input Control */ #define SV_IREG_DMA_DATA_FMT 0x12 /* DMA Data Format */ #define SV_IREG_PC_ENABLE 0x13 /* Playback/Capture Enable Register */ #define SV_IREG_UD_BUTTON 0x14 /* Up/Down Button Register */ #define SV_IREG_REVISION 0x15 /* Revision */ #define SV_IREG_ADC_OUTPUT_CTRL 0x16 /* ADC Output Control */ #define SV_IREG_DMA_A_UPPER 0x18 /* DMA A Upper Base Count */ #define SV_IREG_DMA_A_LOWER 0x19 /* DMA A Lower Base Count */ #define SV_IREG_DMA_C_UPPER 0x1c /* DMA C Upper Base Count */ #define SV_IREG_DMA_C_LOWER 0x1d /* DMA C Lower Base Count */ #define SV_IREG_PCM_RATE_LOW 0x1e /* PCM Sampling Rate Low Byte */ #define SV_IREG_PCM_RATE_HIGH 0x1f /* PCM Sampling Rate High Byte */ #define SV_IREG_SYNTH_RATE_LOW 0x20 /* Synthesizer Sampling Rate Low Byte */ #define SV_IREG_SYNTH_RATE_HIGH 0x21 /* Synthesizer Sampling Rate High Byte */ #define SV_IREG_ADC_CLOCK 0x22 /* ADC Clock Source Selection */ #define SV_IREG_ADC_ALT_RATE 0x23 /* ADC Alternative Sampling Rate Selection */ #define SV_IREG_ADC_PLL_M 0x24 /* ADC PLL M Register */ #define SV_IREG_ADC_PLL_N 0x25 /* ADC PLL N Register */ #define SV_IREG_SYNTH_PLL_M 0x26 /* Synthesizer PLL M Register */ #define SV_IREG_SYNTH_PLL_N 0x27 /* Synthesizer PLL N Register */ #define SV_IREG_MPU401 0x2a /* MPU-401 UART Operation */ #define SV_IREG_DRIVE_CTRL 0x2b /* Drive Control */ #define SV_IREG_SRS_SPACE 0x2c /* SRS Space Control */ #define SV_IREG_SRS_CENTER 0x2d /* SRS Center Control */ #define SV_IREG_WAVE_SOURCE 0x2e /* Wavetable Sample Source Select */ #define SV_IREG_ANALOG_POWER 0x30 /* Analog Power Down Control */ #define SV_IREG_DIGITAL_POWER 0x31 /* Digital Power Down Control */ #define SV_IREG_ADC_PLL SV_IREG_ADC_PLL_M #define SV_IREG_SYNTH_PLL SV_IREG_SYNTH_PLL_M /* * DMA registers */ #define SV_DMA_ADDR0 0x00 #define SV_DMA_ADDR1 0x01 #define SV_DMA_ADDR2 0x02 #define SV_DMA_ADDR3 0x03 #define SV_DMA_COUNT0 0x04 #define SV_DMA_COUNT1 0x05 #define SV_DMA_COUNT2 0x06 #define SV_DMA_MODE 0x0b #define SV_DMA_RESET 0x0d #define SV_DMA_MASK 0x0f /* * Record sources */ #define SV_RECSRC_RESERVED (0x00<<5) #define SV_RECSRC_CD (0x01<<5) #define SV_RECSRC_DAC (0x02<<5) #define SV_RECSRC_AUX2 (0x03<<5) #define SV_RECSRC_LINE (0x04<<5) #define SV_RECSRC_AUX1 (0x05<<5) #define SV_RECSRC_MIC (0x06<<5) #define SV_RECSRC_OUT (0x07<<5) /* * constants */ #define SV_FULLRATE 48000 #define SV_REFFREQUENCY 24576000 #define SV_ADCMULT 512 #define SV_MODE_PLAY 1 #define SV_MODE_CAPTURE 2 /* */ struct sonicvibes { unsigned long dma1size; unsigned long dma2size; int irq; unsigned long sb_port; unsigned long enh_port; unsigned long synth_port; unsigned long midi_port; unsigned long game_port; unsigned int dmaa_port; struct resource *res_dmaa; unsigned int dmac_port; struct resource *res_dmac; unsigned char enable; unsigned char irqmask; unsigned char revision; unsigned char format; unsigned char srs_space; unsigned char srs_center; unsigned char mpu_switch; unsigned char wave_source; unsigned int mode; struct pci_dev *pci; struct snd_card *card; struct snd_pcm *pcm; struct snd_pcm_substream *playback_substream; struct snd_pcm_substream *capture_substream; struct snd_rawmidi *rmidi; struct snd_hwdep *fmsynth; /* S3FM */ spinlock_t reg_lock; unsigned int p_dma_size; unsigned int c_dma_size; struct snd_kcontrol *master_mute; struct snd_kcontrol *master_volume; #ifdef SUPPORT_JOYSTICK struct gameport *gameport; #endif }; static const struct pci_device_id snd_sonic_ids[] = { { PCI_VDEVICE(S3, 0xca00), 0, }, { 0, } }; MODULE_DEVICE_TABLE(pci, snd_sonic_ids); static const struct snd_ratden sonicvibes_adc_clock = { .num_min = 4000 * 65536, .num_max = 48000UL * 65536, .num_step = 1, .den = 65536, }; static const struct snd_pcm_hw_constraint_ratdens snd_sonicvibes_hw_constraints_adc_clock = { .nrats = 1, .rats = &sonicvibes_adc_clock, }; /* * common I/O routines */ static inline void snd_sonicvibes_setdmaa(struct sonicvibes * sonic, unsigned int addr, unsigned int count) { count--; outl(addr, sonic->dmaa_port + SV_DMA_ADDR0); outl(count, sonic->dmaa_port + SV_DMA_COUNT0); outb(0x18, sonic->dmaa_port + SV_DMA_MODE); #if 0 dev_dbg(sonic->card->dev, "program dmaa: addr = 0x%x, paddr = 0x%x\n", addr, inl(sonic->dmaa_port + SV_DMA_ADDR0)); #endif } static inline void snd_sonicvibes_setdmac(struct sonicvibes * sonic, unsigned int addr, unsigned int count) { /* note: dmac is working in word mode!!! */ count >>= 1; count--; outl(addr, sonic->dmac_port + SV_DMA_ADDR0); outl(count, sonic->dmac_port + SV_DMA_COUNT0); outb(0x14, sonic->dmac_port + SV_DMA_MODE); #if 0 dev_dbg(sonic->card->dev, "program dmac: addr = 0x%x, paddr = 0x%x\n", addr, inl(sonic->dmac_port + SV_DMA_ADDR0)); #endif } static inline unsigned int snd_sonicvibes_getdmaa(struct sonicvibes * sonic) { return (inl(sonic->dmaa_port + SV_DMA_COUNT0) & 0xffffff) + 1; } static inline unsigned int snd_sonicvibes_getdmac(struct sonicvibes * sonic) { /* note: dmac is working in word mode!!! */ return ((inl(sonic->dmac_port + SV_DMA_COUNT0) & 0xffffff) + 1) << 1; } static void snd_sonicvibes_out1(struct sonicvibes * sonic, unsigned char reg, unsigned char value) { outb(reg, SV_REG(sonic, INDEX)); udelay(10); outb(value, SV_REG(sonic, DATA)); udelay(10); } static void snd_sonicvibes_out(struct sonicvibes * sonic, unsigned char reg, unsigned char value) { unsigned long flags; spin_lock_irqsave(&sonic->reg_lock, flags); outb(reg, SV_REG(sonic, INDEX)); udelay(10); outb(value, SV_REG(sonic, DATA)); udelay(10); spin_unlock_irqrestore(&sonic->reg_lock, flags); } static unsigned char snd_sonicvibes_in1(struct sonicvibes * sonic, unsigned char reg) { unsigned char value; outb(reg, SV_REG(sonic, INDEX)); udelay(10); value = inb(SV_REG(sonic, DATA)); udelay(10); return value; } static unsigned char snd_sonicvibes_in(struct sonicvibes * sonic, unsigned char reg) { unsigned long flags; unsigned char value; spin_lock_irqsave(&sonic->reg_lock, flags); outb(reg, SV_REG(sonic, INDEX)); udelay(10); value = inb(SV_REG(sonic, DATA)); udelay(10); spin_unlock_irqrestore(&sonic->reg_lock, flags); return value; } #if 0 static void snd_sonicvibes_debug(struct sonicvibes * sonic) { dev_dbg(sonic->card->dev, "SV REGS: INDEX = 0x%02x STATUS = 0x%02x\n", inb(SV_REG(sonic, INDEX)), inb(SV_REG(sonic, STATUS))); dev_dbg(sonic->card->dev, " 0x00: left input = 0x%02x 0x20: synth rate low = 0x%02x\n", snd_sonicvibes_in(sonic, 0x00), snd_sonicvibes_in(sonic, 0x20)); dev_dbg(sonic->card->dev, " 0x01: right input = 0x%02x 0x21: synth rate high = 0x%02x\n", snd_sonicvibes_in(sonic, 0x01), snd_sonicvibes_in(sonic, 0x21)); dev_dbg(sonic->card->dev, " 0x02: left AUX1 = 0x%02x 0x22: ADC clock = 0x%02x\n", snd_sonicvibes_in(sonic, 0x02), snd_sonicvibes_in(sonic, 0x22)); dev_dbg(sonic->card->dev, " 0x03: right AUX1 = 0x%02x 0x23: ADC alt rate = 0x%02x\n", snd_sonicvibes_in(sonic, 0x03), snd_sonicvibes_in(sonic, 0x23)); dev_dbg(sonic->card->dev, " 0x04: left CD = 0x%02x 0x24: ADC pll M = 0x%02x\n", snd_sonicvibes_in(sonic, 0x04), snd_sonicvibes_in(sonic, 0x24)); dev_dbg(sonic->card->dev, " 0x05: right CD = 0x%02x 0x25: ADC pll N = 0x%02x\n", snd_sonicvibes_in(sonic, 0x05), snd_sonicvibes_in(sonic, 0x25)); dev_dbg(sonic->card->dev, " 0x06: left line = 0x%02x 0x26: Synth pll M = 0x%02x\n", snd_sonicvibes_in(sonic, 0x06), snd_sonicvibes_in(sonic, 0x26)); dev_dbg(sonic->card->dev, " 0x07: right line = 0x%02x 0x27: Synth pll N = 0x%02x\n", snd_sonicvibes_in(sonic, 0x07), snd_sonicvibes_in(sonic, 0x27)); dev_dbg(sonic->card->dev, " 0x08: MIC = 0x%02x 0x28: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x08), snd_sonicvibes_in(sonic, 0x28)); dev_dbg(sonic->card->dev, " 0x09: Game port = 0x%02x 0x29: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x09), snd_sonicvibes_in(sonic, 0x29)); dev_dbg(sonic->card->dev, " 0x0a: left synth = 0x%02x 0x2a: MPU401 = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0a), snd_sonicvibes_in(sonic, 0x2a)); dev_dbg(sonic->card->dev, " 0x0b: right synth = 0x%02x 0x2b: drive ctrl = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0b), snd_sonicvibes_in(sonic, 0x2b)); dev_dbg(sonic->card->dev, " 0x0c: left AUX2 = 0x%02x 0x2c: SRS space = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0c), snd_sonicvibes_in(sonic, 0x2c)); dev_dbg(sonic->card->dev, " 0x0d: right AUX2 = 0x%02x 0x2d: SRS center = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0d), snd_sonicvibes_in(sonic, 0x2d)); dev_dbg(sonic->card->dev, " 0x0e: left analog = 0x%02x 0x2e: wave source = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0e), snd_sonicvibes_in(sonic, 0x2e)); dev_dbg(sonic->card->dev, " 0x0f: right analog = 0x%02x 0x2f: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x0f), snd_sonicvibes_in(sonic, 0x2f)); dev_dbg(sonic->card->dev, " 0x10: left PCM = 0x%02x 0x30: analog power = 0x%02x\n", snd_sonicvibes_in(sonic, 0x10), snd_sonicvibes_in(sonic, 0x30)); dev_dbg(sonic->card->dev, " 0x11: right PCM = 0x%02x 0x31: analog power = 0x%02x\n", snd_sonicvibes_in(sonic, 0x11), snd_sonicvibes_in(sonic, 0x31)); dev_dbg(sonic->card->dev, " 0x12: DMA data format = 0x%02x 0x32: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x12), snd_sonicvibes_in(sonic, 0x32)); dev_dbg(sonic->card->dev, " 0x13: P/C enable = 0x%02x 0x33: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x13), snd_sonicvibes_in(sonic, 0x33)); dev_dbg(sonic->card->dev, " 0x14: U/D button = 0x%02x 0x34: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x14), snd_sonicvibes_in(sonic, 0x34)); dev_dbg(sonic->card->dev, " 0x15: revision = 0x%02x 0x35: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x15), snd_sonicvibes_in(sonic, 0x35)); dev_dbg(sonic->card->dev, " 0x16: ADC output ctrl = 0x%02x 0x36: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x16), snd_sonicvibes_in(sonic, 0x36)); dev_dbg(sonic->card->dev, " 0x17: --- = 0x%02x 0x37: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x17), snd_sonicvibes_in(sonic, 0x37)); dev_dbg(sonic->card->dev, " 0x18: DMA A upper cnt = 0x%02x 0x38: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x18), snd_sonicvibes_in(sonic, 0x38)); dev_dbg(sonic->card->dev, " 0x19: DMA A lower cnt = 0x%02x 0x39: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x19), snd_sonicvibes_in(sonic, 0x39)); dev_dbg(sonic->card->dev, " 0x1a: --- = 0x%02x 0x3a: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1a), snd_sonicvibes_in(sonic, 0x3a)); dev_dbg(sonic->card->dev, " 0x1b: --- = 0x%02x 0x3b: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1b), snd_sonicvibes_in(sonic, 0x3b)); dev_dbg(sonic->card->dev, " 0x1c: DMA C upper cnt = 0x%02x 0x3c: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1c), snd_sonicvibes_in(sonic, 0x3c)); dev_dbg(sonic->card->dev, " 0x1d: DMA C upper cnt = 0x%02x 0x3d: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1d), snd_sonicvibes_in(sonic, 0x3d)); dev_dbg(sonic->card->dev, " 0x1e: PCM rate low = 0x%02x 0x3e: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1e), snd_sonicvibes_in(sonic, 0x3e)); dev_dbg(sonic->card->dev, " 0x1f: PCM rate high = 0x%02x 0x3f: --- = 0x%02x\n", snd_sonicvibes_in(sonic, 0x1f), snd_sonicvibes_in(sonic, 0x3f)); } #endif static void snd_sonicvibes_setfmt(struct sonicvibes * sonic, unsigned char mask, unsigned char value) { unsigned long flags; spin_lock_irqsave(&sonic->reg_lock, flags); outb(SV_MCE | SV_IREG_DMA_DATA_FMT, SV_REG(sonic, INDEX)); if (mask) { sonic->format = inb(SV_REG(sonic, DATA)); udelay(10); } sonic->format = (sonic->format & mask) | value; outb(sonic->format, SV_REG(sonic, DATA)); udelay(10); outb(0, SV_REG(sonic, INDEX)); udelay(10); spin_unlock_irqrestore(&sonic->reg_lock, flags); } static void snd_sonicvibes_pll(unsigned int rate, unsigned int *res_r, unsigned int *res_m, unsigned int *res_n) { unsigned int r, m = 0, n = 0; unsigned int xm, xn, xr, xd, metric = ~0U; if (rate < 625000 / SV_ADCMULT) rate = 625000 / SV_ADCMULT; if (rate > 150000000 / SV_ADCMULT) rate = 150000000 / SV_ADCMULT; /* slight violation of specs, needed for continuous sampling rates */ for (r = 0; rate < 75000000 / SV_ADCMULT; r += 0x20, rate <<= 1); for (xn = 3; xn < 33; xn++) /* 35 */ for (xm = 3; xm < 257; xm++) { xr = ((SV_REFFREQUENCY / SV_ADCMULT) * xm) / xn; if (xr >= rate) xd = xr - rate; else xd = rate - xr; if (xd < metric) { metric = xd; m = xm - 2; n = xn - 2; } } *res_r = r; *res_m = m; *res_n = n; #if 0 dev_dbg(sonic->card->dev, "metric = %i, xm = %i, xn = %i\n", metric, xm, xn); dev_dbg(sonic->card->dev, "pll: m = 0x%x, r = 0x%x, n = 0x%x\n", reg, m, r, n); #endif } static void snd_sonicvibes_setpll(struct sonicvibes * sonic, unsigned char reg, unsigned int rate) { unsigned long flags; unsigned int r, m, n; snd_sonicvibes_pll(rate, &r, &m, &n); if (sonic != NULL) { spin_lock_irqsave(&sonic->reg_lock, flags); snd_sonicvibes_out1(sonic, reg, m); snd_sonicvibes_out1(sonic, reg + 1, r | n); spin_unlock_irqrestore(&sonic->reg_lock, flags); } } static void snd_sonicvibes_set_adc_rate(struct sonicvibes * sonic, unsigned int rate) { unsigned long flags; unsigned int div; unsigned char clock; div = 48000 / rate; if (div > 8) div = 8; if ((48000 / div) == rate) { /* use the alternate clock */ clock = 0x10; } else { /* use the PLL source */ clock = 0x00; snd_sonicvibes_setpll(sonic, SV_IREG_ADC_PLL, rate); } spin_lock_irqsave(&sonic->reg_lock, flags); snd_sonicvibes_out1(sonic, SV_IREG_ADC_ALT_RATE, (div - 1) << 4); snd_sonicvibes_out1(sonic, SV_IREG_ADC_CLOCK, clock); spin_unlock_irqrestore(&sonic->reg_lock, flags); } static int snd_sonicvibes_hw_constraint_dac_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { unsigned int rate, div, r, m, n; if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->min == hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->max) { rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->min; div = 48000 / rate; if (div > 8) div = 8; if ((48000 / div) == rate) { params->rate_num = rate; params->rate_den = 1; } else { snd_sonicvibes_pll(rate, &r, &m, &n); snd_BUG_ON(SV_REFFREQUENCY % 16); snd_BUG_ON(SV_ADCMULT % 512); params->rate_num = (SV_REFFREQUENCY/16) * (n+2) * r; params->rate_den = (SV_ADCMULT/512) * (m+2); } } return 0; } static void snd_sonicvibes_set_dac_rate(struct sonicvibes * sonic, unsigned int rate) { unsigned int div; unsigned long flags; div = DIV_ROUND_CLOSEST(rate * 65536, SV_FULLRATE); if (div > 65535) div = 65535; spin_lock_irqsave(&sonic->reg_lock, flags); snd_sonicvibes_out1(sonic, SV_IREG_PCM_RATE_HIGH, div >> 8); snd_sonicvibes_out1(sonic, SV_IREG_PCM_RATE_LOW, div); spin_unlock_irqrestore(&sonic->reg_lock, flags); } static int snd_sonicvibes_trigger(struct sonicvibes * sonic, int what, int cmd) { int result = 0; spin_lock(&sonic->reg_lock); if (cmd == SNDRV_PCM_TRIGGER_START) { if (!(sonic->enable & what)) { sonic->enable |= what; snd_sonicvibes_out1(sonic, SV_IREG_PC_ENABLE, sonic->enable); } } else if (cmd == SNDRV_PCM_TRIGGER_STOP) { if (sonic->enable & what) { sonic->enable &= ~what; snd_sonicvibes_out1(sonic, SV_IREG_PC_ENABLE, sonic->enable); } } else { result = -EINVAL; } spin_unlock(&sonic->reg_lock); return result; } static irqreturn_t snd_sonicvibes_interrupt(int irq, void *dev_id) { struct sonicvibes *sonic = dev_id; unsigned char status; status = inb(SV_REG(sonic, STATUS)); if (!(status & (SV_DMAA_IRQ | SV_DMAC_IRQ | SV_MIDI_IRQ))) return IRQ_NONE; if (status == 0xff) { /* failure */ outb(sonic->irqmask = ~0, SV_REG(sonic, IRQMASK)); dev_err(sonic->card->dev, "IRQ failure - interrupts disabled!!\n"); return IRQ_HANDLED; } if (sonic->pcm) { if (status & SV_DMAA_IRQ) snd_pcm_period_elapsed(sonic->playback_substream); if (status & SV_DMAC_IRQ) snd_pcm_period_elapsed(sonic->capture_substream); } if (sonic->rmidi) { if (status & SV_MIDI_IRQ) snd_mpu401_uart_interrupt(irq, sonic->rmidi->private_data); } if (status & SV_UD_IRQ) { unsigned char udreg; int vol, oleft, oright, mleft, mright; spin_lock(&sonic->reg_lock); udreg = snd_sonicvibes_in1(sonic, SV_IREG_UD_BUTTON); vol = udreg & 0x3f; if (!(udreg & 0x40)) vol = -vol; oleft = mleft = snd_sonicvibes_in1(sonic, SV_IREG_LEFT_ANALOG); oright = mright = snd_sonicvibes_in1(sonic, SV_IREG_RIGHT_ANALOG); oleft &= 0x1f; oright &= 0x1f; oleft += vol; if (oleft < 0) oleft = 0; if (oleft > 0x1f) oleft = 0x1f; oright += vol; if (oright < 0) oright = 0; if (oright > 0x1f) oright = 0x1f; if (udreg & 0x80) { mleft ^= 0x80; mright ^= 0x80; } oleft |= mleft & 0x80; oright |= mright & 0x80; snd_sonicvibes_out1(sonic, SV_IREG_LEFT_ANALOG, oleft); snd_sonicvibes_out1(sonic, SV_IREG_RIGHT_ANALOG, oright); spin_unlock(&sonic->reg_lock); snd_ctl_notify(sonic->card, SNDRV_CTL_EVENT_MASK_VALUE, &sonic->master_mute->id); snd_ctl_notify(sonic->card, SNDRV_CTL_EVENT_MASK_VALUE, &sonic->master_volume->id); } return IRQ_HANDLED; } /* * PCM part */ static int snd_sonicvibes_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); return snd_sonicvibes_trigger(sonic, 1, cmd); } static int snd_sonicvibes_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); return snd_sonicvibes_trigger(sonic, 2, cmd); } static int snd_sonicvibes_playback_prepare(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; unsigned char fmt = 0; unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); sonic->p_dma_size = size; count--; if (runtime->channels > 1) fmt |= 1; if (snd_pcm_format_width(runtime->format) == 16) fmt |= 2; snd_sonicvibes_setfmt(sonic, ~3, fmt); snd_sonicvibes_set_dac_rate(sonic, runtime->rate); spin_lock_irq(&sonic->reg_lock); snd_sonicvibes_setdmaa(sonic, runtime->dma_addr, size); snd_sonicvibes_out1(sonic, SV_IREG_DMA_A_UPPER, count >> 8); snd_sonicvibes_out1(sonic, SV_IREG_DMA_A_LOWER, count); spin_unlock_irq(&sonic->reg_lock); return 0; } static int snd_sonicvibes_capture_prepare(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; unsigned char fmt = 0; unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); sonic->c_dma_size = size; count >>= 1; count--; if (runtime->channels > 1) fmt |= 0x10; if (snd_pcm_format_width(runtime->format) == 16) fmt |= 0x20; snd_sonicvibes_setfmt(sonic, ~0x30, fmt); snd_sonicvibes_set_adc_rate(sonic, runtime->rate); spin_lock_irq(&sonic->reg_lock); snd_sonicvibes_setdmac(sonic, runtime->dma_addr, size); snd_sonicvibes_out1(sonic, SV_IREG_DMA_C_UPPER, count >> 8); snd_sonicvibes_out1(sonic, SV_IREG_DMA_C_LOWER, count); spin_unlock_irq(&sonic->reg_lock); return 0; } static snd_pcm_uframes_t snd_sonicvibes_playback_pointer(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); size_t ptr; if (!(sonic->enable & 1)) return 0; ptr = sonic->p_dma_size - snd_sonicvibes_getdmaa(sonic); return bytes_to_frames(substream->runtime, ptr); } static snd_pcm_uframes_t snd_sonicvibes_capture_pointer(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); size_t ptr; if (!(sonic->enable & 2)) return 0; ptr = sonic->c_dma_size - snd_sonicvibes_getdmac(sonic); return bytes_to_frames(substream->runtime, ptr); } static const struct snd_pcm_hardware snd_sonicvibes_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 32, .period_bytes_max = (128*1024), .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static const struct snd_pcm_hardware snd_sonicvibes_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 32, .period_bytes_max = (128*1024), .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static int snd_sonicvibes_playback_open(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; sonic->mode |= SV_MODE_PLAY; sonic->playback_substream = substream; runtime->hw = snd_sonicvibes_playback; snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, snd_sonicvibes_hw_constraint_dac_rate, NULL, SNDRV_PCM_HW_PARAM_RATE, -1); return 0; } static int snd_sonicvibes_capture_open(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; sonic->mode |= SV_MODE_CAPTURE; sonic->capture_substream = substream; runtime->hw = snd_sonicvibes_capture; snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &snd_sonicvibes_hw_constraints_adc_clock); return 0; } static int snd_sonicvibes_playback_close(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); sonic->playback_substream = NULL; sonic->mode &= ~SV_MODE_PLAY; return 0; } static int snd_sonicvibes_capture_close(struct snd_pcm_substream *substream) { struct sonicvibes *sonic = snd_pcm_substream_chip(substream); sonic->capture_substream = NULL; sonic->mode &= ~SV_MODE_CAPTURE; return 0; } static const struct snd_pcm_ops snd_sonicvibes_playback_ops = { .open = snd_sonicvibes_playback_open, .close = snd_sonicvibes_playback_close, .prepare = snd_sonicvibes_playback_prepare, .trigger = snd_sonicvibes_playback_trigger, .pointer = snd_sonicvibes_playback_pointer, }; static const struct snd_pcm_ops snd_sonicvibes_capture_ops = { .open = snd_sonicvibes_capture_open, .close = snd_sonicvibes_capture_close, .prepare = snd_sonicvibes_capture_prepare, .trigger = snd_sonicvibes_capture_trigger, .pointer = snd_sonicvibes_capture_pointer, }; static int snd_sonicvibes_pcm(struct sonicvibes *sonic, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(sonic->card, "s3_86c617", device, 1, 1, &pcm); if (err < 0) return err; if (snd_BUG_ON(!pcm)) return -EINVAL; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_sonicvibes_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_sonicvibes_capture_ops); pcm->private_data = sonic; pcm->info_flags = 0; strcpy(pcm->name, "S3 SonicVibes"); sonic->pcm = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &sonic->pci->dev, 64*1024, 128*1024); return 0; } /* * Mixer part */ #define SONICVIBES_MUX(xname, xindex) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_sonicvibes_info_mux, \ .get = snd_sonicvibes_get_mux, .put = snd_sonicvibes_put_mux } static int snd_sonicvibes_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[7] = { "CD", "PCM", "Aux1", "Line", "Aux0", "Mic", "Mix" }; return snd_ctl_enum_info(uinfo, 2, 7, texts); } static int snd_sonicvibes_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); spin_lock_irq(&sonic->reg_lock); ucontrol->value.enumerated.item[0] = ((snd_sonicvibes_in1(sonic, SV_IREG_LEFT_ADC) & SV_RECSRC_OUT) >> 5) - 1; ucontrol->value.enumerated.item[1] = ((snd_sonicvibes_in1(sonic, SV_IREG_RIGHT_ADC) & SV_RECSRC_OUT) >> 5) - 1; spin_unlock_irq(&sonic->reg_lock); return 0; } static int snd_sonicvibes_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); unsigned short left, right, oval1, oval2; int change; if (ucontrol->value.enumerated.item[0] >= 7 || ucontrol->value.enumerated.item[1] >= 7) return -EINVAL; left = (ucontrol->value.enumerated.item[0] + 1) << 5; right = (ucontrol->value.enumerated.item[1] + 1) << 5; spin_lock_irq(&sonic->reg_lock); oval1 = snd_sonicvibes_in1(sonic, SV_IREG_LEFT_ADC); oval2 = snd_sonicvibes_in1(sonic, SV_IREG_RIGHT_ADC); left = (oval1 & ~SV_RECSRC_OUT) | left; right = (oval2 & ~SV_RECSRC_OUT) | right; change = left != oval1 || right != oval2; snd_sonicvibes_out1(sonic, SV_IREG_LEFT_ADC, left); snd_sonicvibes_out1(sonic, SV_IREG_RIGHT_ADC, right); spin_unlock_irq(&sonic->reg_lock); return change; } #define SONICVIBES_SINGLE(xname, xindex, reg, shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_sonicvibes_info_single, \ .get = snd_sonicvibes_get_single, .put = snd_sonicvibes_put_single, \ .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } static int snd_sonicvibes_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 16) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_sonicvibes_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0xff; spin_lock_irq(&sonic->reg_lock); ucontrol->value.integer.value[0] = (snd_sonicvibes_in1(sonic, reg)>> shift) & mask; spin_unlock_irq(&sonic->reg_lock); if (invert) ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; return 0; } static int snd_sonicvibes_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0xff; int change; unsigned short val, oval; val = (ucontrol->value.integer.value[0] & mask); if (invert) val = mask - val; val <<= shift; spin_lock_irq(&sonic->reg_lock); oval = snd_sonicvibes_in1(sonic, reg); val = (oval & ~(mask << shift)) | val; change = val != oval; snd_sonicvibes_out1(sonic, reg, val); spin_unlock_irq(&sonic->reg_lock); return change; } #define SONICVIBES_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ .info = snd_sonicvibes_info_double, \ .get = snd_sonicvibes_get_double, .put = snd_sonicvibes_put_double, \ .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } static int snd_sonicvibes_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 24) & 0xff; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_sonicvibes_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int shift_left = (kcontrol->private_value >> 16) & 0x07; int shift_right = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; spin_lock_irq(&sonic->reg_lock); ucontrol->value.integer.value[0] = (snd_sonicvibes_in1(sonic, left_reg) >> shift_left) & mask; ucontrol->value.integer.value[1] = (snd_sonicvibes_in1(sonic, right_reg) >> shift_right) & mask; spin_unlock_irq(&sonic->reg_lock); if (invert) { ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; } return 0; } static int snd_sonicvibes_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); int left_reg = kcontrol->private_value & 0xff; int right_reg = (kcontrol->private_value >> 8) & 0xff; int shift_left = (kcontrol->private_value >> 16) & 0x07; int shift_right = (kcontrol->private_value >> 19) & 0x07; int mask = (kcontrol->private_value >> 24) & 0xff; int invert = (kcontrol->private_value >> 22) & 1; int change; unsigned short val1, val2, oval1, oval2; val1 = ucontrol->value.integer.value[0] & mask; val2 = ucontrol->value.integer.value[1] & mask; if (invert) { val1 = mask - val1; val2 = mask - val2; } val1 <<= shift_left; val2 <<= shift_right; spin_lock_irq(&sonic->reg_lock); oval1 = snd_sonicvibes_in1(sonic, left_reg); oval2 = snd_sonicvibes_in1(sonic, right_reg); val1 = (oval1 & ~(mask << shift_left)) | val1; val2 = (oval2 & ~(mask << shift_right)) | val2; change = val1 != oval1 || val2 != oval2; snd_sonicvibes_out1(sonic, left_reg, val1); snd_sonicvibes_out1(sonic, right_reg, val2); spin_unlock_irq(&sonic->reg_lock); return change; } static const struct snd_kcontrol_new snd_sonicvibes_controls[] = { SONICVIBES_DOUBLE("Capture Volume", 0, SV_IREG_LEFT_ADC, SV_IREG_RIGHT_ADC, 0, 0, 15, 0), SONICVIBES_DOUBLE("Aux Playback Switch", 0, SV_IREG_LEFT_AUX1, SV_IREG_RIGHT_AUX1, 7, 7, 1, 1), SONICVIBES_DOUBLE("Aux Playback Volume", 0, SV_IREG_LEFT_AUX1, SV_IREG_RIGHT_AUX1, 0, 0, 31, 1), SONICVIBES_DOUBLE("CD Playback Switch", 0, SV_IREG_LEFT_CD, SV_IREG_RIGHT_CD, 7, 7, 1, 1), SONICVIBES_DOUBLE("CD Playback Volume", 0, SV_IREG_LEFT_CD, SV_IREG_RIGHT_CD, 0, 0, 31, 1), SONICVIBES_DOUBLE("Line Playback Switch", 0, SV_IREG_LEFT_LINE, SV_IREG_RIGHT_LINE, 7, 7, 1, 1), SONICVIBES_DOUBLE("Line Playback Volume", 0, SV_IREG_LEFT_LINE, SV_IREG_RIGHT_LINE, 0, 0, 31, 1), SONICVIBES_SINGLE("Mic Playback Switch", 0, SV_IREG_MIC, 7, 1, 1), SONICVIBES_SINGLE("Mic Playback Volume", 0, SV_IREG_MIC, 0, 15, 1), SONICVIBES_SINGLE("Mic Boost", 0, SV_IREG_LEFT_ADC, 4, 1, 0), SONICVIBES_DOUBLE("Synth Playback Switch", 0, SV_IREG_LEFT_SYNTH, SV_IREG_RIGHT_SYNTH, 7, 7, 1, 1), SONICVIBES_DOUBLE("Synth Playback Volume", 0, SV_IREG_LEFT_SYNTH, SV_IREG_RIGHT_SYNTH, 0, 0, 31, 1), SONICVIBES_DOUBLE("Aux Playback Switch", 1, SV_IREG_LEFT_AUX2, SV_IREG_RIGHT_AUX2, 7, 7, 1, 1), SONICVIBES_DOUBLE("Aux Playback Volume", 1, SV_IREG_LEFT_AUX2, SV_IREG_RIGHT_AUX2, 0, 0, 31, 1), SONICVIBES_DOUBLE("Master Playback Switch", 0, SV_IREG_LEFT_ANALOG, SV_IREG_RIGHT_ANALOG, 7, 7, 1, 1), SONICVIBES_DOUBLE("Master Playback Volume", 0, SV_IREG_LEFT_ANALOG, SV_IREG_RIGHT_ANALOG, 0, 0, 31, 1), SONICVIBES_DOUBLE("PCM Playback Switch", 0, SV_IREG_LEFT_PCM, SV_IREG_RIGHT_PCM, 7, 7, 1, 1), SONICVIBES_DOUBLE("PCM Playback Volume", 0, SV_IREG_LEFT_PCM, SV_IREG_RIGHT_PCM, 0, 0, 63, 1), SONICVIBES_SINGLE("Loopback Capture Switch", 0, SV_IREG_ADC_OUTPUT_CTRL, 0, 1, 0), SONICVIBES_SINGLE("Loopback Capture Volume", 0, SV_IREG_ADC_OUTPUT_CTRL, 2, 63, 1), SONICVIBES_MUX("Capture Source", 0) }; static void snd_sonicvibes_master_free(struct snd_kcontrol *kcontrol) { struct sonicvibes *sonic = snd_kcontrol_chip(kcontrol); sonic->master_mute = NULL; sonic->master_volume = NULL; } static int snd_sonicvibes_mixer(struct sonicvibes *sonic) { struct snd_card *card; struct snd_kcontrol *kctl; unsigned int idx; int err; if (snd_BUG_ON(!sonic || !sonic->card)) return -EINVAL; card = sonic->card; strcpy(card->mixername, "S3 SonicVibes"); for (idx = 0; idx < ARRAY_SIZE(snd_sonicvibes_controls); idx++) { kctl = snd_ctl_new1(&snd_sonicvibes_controls[idx], sonic); err = snd_ctl_add(card, kctl); if (err < 0) return err; switch (idx) { case 0: case 1: kctl->private_free = snd_sonicvibes_master_free; break; } } return 0; } /* */ static void snd_sonicvibes_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct sonicvibes *sonic = entry->private_data; unsigned char tmp; tmp = sonic->srs_space & 0x0f; snd_iprintf(buffer, "SRS 3D : %s\n", sonic->srs_space & 0x80 ? "off" : "on"); snd_iprintf(buffer, "SRS Space : %s\n", tmp == 0x00 ? "100%" : tmp == 0x01 ? "75%" : tmp == 0x02 ? "50%" : tmp == 0x03 ? "25%" : "0%"); tmp = sonic->srs_center & 0x0f; snd_iprintf(buffer, "SRS Center : %s\n", tmp == 0x00 ? "100%" : tmp == 0x01 ? "75%" : tmp == 0x02 ? "50%" : tmp == 0x03 ? "25%" : "0%"); tmp = sonic->wave_source & 0x03; snd_iprintf(buffer, "WaveTable Source : %s\n", tmp == 0x00 ? "on-board ROM" : tmp == 0x01 ? "PCI bus" : "on-board ROM + PCI bus"); tmp = sonic->mpu_switch; snd_iprintf(buffer, "Onboard synth : %s\n", tmp & 0x01 ? "on" : "off"); snd_iprintf(buffer, "Ext. Rx to synth : %s\n", tmp & 0x02 ? "on" : "off"); snd_iprintf(buffer, "MIDI to ext. Tx : %s\n", tmp & 0x04 ? "on" : "off"); } static void snd_sonicvibes_proc_init(struct sonicvibes *sonic) { snd_card_ro_proc_new(sonic->card, "sonicvibes", sonic, snd_sonicvibes_proc_read); } /* */ #ifdef SUPPORT_JOYSTICK static const struct snd_kcontrol_new snd_sonicvibes_game_control = SONICVIBES_SINGLE("Joystick Speed", 0, SV_IREG_GAME_PORT, 1, 15, 0); static int snd_sonicvibes_create_gameport(struct sonicvibes *sonic) { struct gameport *gp; int err; sonic->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(sonic->card->dev, "sonicvibes: cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "SonicVibes Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(sonic->pci)); gameport_set_dev_parent(gp, &sonic->pci->dev); gp->io = sonic->game_port; gameport_register_port(gp); err = snd_ctl_add(sonic->card, snd_ctl_new1(&snd_sonicvibes_game_control, sonic)); if (err < 0) return err; return 0; } static void snd_sonicvibes_free_gameport(struct sonicvibes *sonic) { if (sonic->gameport) { gameport_unregister_port(sonic->gameport); sonic->gameport = NULL; } } #else static inline int snd_sonicvibes_create_gameport(struct sonicvibes *sonic) { return -ENOSYS; } static inline void snd_sonicvibes_free_gameport(struct sonicvibes *sonic) { } #endif static void snd_sonicvibes_free(struct snd_card *card) { struct sonicvibes *sonic = card->private_data; snd_sonicvibes_free_gameport(sonic); pci_write_config_dword(sonic->pci, 0x40, sonic->dmaa_port); pci_write_config_dword(sonic->pci, 0x48, sonic->dmac_port); } static int snd_sonicvibes_create(struct snd_card *card, struct pci_dev *pci, int reverb, int mge) { struct sonicvibes *sonic = card->private_data; unsigned int dmaa, dmac; int err; /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; /* check, if we can restrict PCI DMA transfers to 24 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { dev_err(card->dev, "architecture does not support 24bit PCI busmaster DMA\n"); return -ENXIO; } spin_lock_init(&sonic->reg_lock); sonic->card = card; sonic->pci = pci; sonic->irq = -1; err = pci_request_regions(pci, "S3 SonicVibes"); if (err < 0) return err; sonic->sb_port = pci_resource_start(pci, 0); sonic->enh_port = pci_resource_start(pci, 1); sonic->synth_port = pci_resource_start(pci, 2); sonic->midi_port = pci_resource_start(pci, 3); sonic->game_port = pci_resource_start(pci, 4); if (devm_request_irq(&pci->dev, pci->irq, snd_sonicvibes_interrupt, IRQF_SHARED, KBUILD_MODNAME, sonic)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } sonic->irq = pci->irq; card->sync_irq = sonic->irq; card->private_free = snd_sonicvibes_free; pci_read_config_dword(pci, 0x40, &dmaa); pci_read_config_dword(pci, 0x48, &dmac); dmaio &= ~0x0f; dmaa &= ~0x0f; dmac &= ~0x0f; if (!dmaa) { dmaa = dmaio; dmaio += 0x10; dev_info(card->dev, "BIOS did not allocate DDMA channel A i/o, allocated at 0x%x\n", dmaa); } if (!dmac) { dmac = dmaio; dmaio += 0x10; dev_info(card->dev, "BIOS did not allocate DDMA channel C i/o, allocated at 0x%x\n", dmac); } pci_write_config_dword(pci, 0x40, dmaa); pci_write_config_dword(pci, 0x48, dmac); sonic->res_dmaa = devm_request_region(&pci->dev, dmaa, 0x10, "S3 SonicVibes DDMA-A"); if (!sonic->res_dmaa) { dev_err(card->dev, "unable to grab DDMA-A port at 0x%x-0x%x\n", dmaa, dmaa + 0x10 - 1); return -EBUSY; } sonic->res_dmac = devm_request_region(&pci->dev, dmac, 0x10, "S3 SonicVibes DDMA-C"); if (!sonic->res_dmac) { dev_err(card->dev, "unable to grab DDMA-C port at 0x%x-0x%x\n", dmac, dmac + 0x10 - 1); return -EBUSY; } pci_read_config_dword(pci, 0x40, &sonic->dmaa_port); pci_read_config_dword(pci, 0x48, &sonic->dmac_port); sonic->dmaa_port &= ~0x0f; sonic->dmac_port &= ~0x0f; pci_write_config_dword(pci, 0x40, sonic->dmaa_port | 9); /* enable + enhanced */ pci_write_config_dword(pci, 0x48, sonic->dmac_port | 9); /* enable */ /* ok.. initialize S3 SonicVibes chip */ outb(SV_RESET, SV_REG(sonic, CONTROL)); /* reset chip */ udelay(100); outb(0, SV_REG(sonic, CONTROL)); /* release reset */ udelay(100); outb(SV_ENHANCED | SV_INTA | (reverb ? SV_REVERB : 0), SV_REG(sonic, CONTROL)); inb(SV_REG(sonic, STATUS)); /* clear IRQs */ #if 1 snd_sonicvibes_out(sonic, SV_IREG_DRIVE_CTRL, 0); /* drive current 16mA */ #else snd_sonicvibes_out(sonic, SV_IREG_DRIVE_CTRL, 0x40); /* drive current 8mA */ #endif snd_sonicvibes_out(sonic, SV_IREG_PC_ENABLE, sonic->enable = 0); /* disable playback & capture */ outb(sonic->irqmask = ~(SV_DMAA_MASK | SV_DMAC_MASK | SV_UD_MASK), SV_REG(sonic, IRQMASK)); inb(SV_REG(sonic, STATUS)); /* clear IRQs */ snd_sonicvibes_out(sonic, SV_IREG_ADC_CLOCK, 0); /* use PLL as clock source */ snd_sonicvibes_out(sonic, SV_IREG_ANALOG_POWER, 0); /* power up analog parts */ snd_sonicvibes_out(sonic, SV_IREG_DIGITAL_POWER, 0); /* power up digital parts */ snd_sonicvibes_setpll(sonic, SV_IREG_ADC_PLL, 8000); snd_sonicvibes_out(sonic, SV_IREG_SRS_SPACE, sonic->srs_space = 0x80); /* SRS space off */ snd_sonicvibes_out(sonic, SV_IREG_SRS_CENTER, sonic->srs_center = 0x00);/* SRS center off */ snd_sonicvibes_out(sonic, SV_IREG_MPU401, sonic->mpu_switch = 0x05); /* MPU-401 switch */ snd_sonicvibes_out(sonic, SV_IREG_WAVE_SOURCE, sonic->wave_source = 0x00); /* onboard ROM */ snd_sonicvibes_out(sonic, SV_IREG_PCM_RATE_LOW, (8000 * 65536 / SV_FULLRATE) & 0xff); snd_sonicvibes_out(sonic, SV_IREG_PCM_RATE_HIGH, ((8000 * 65536 / SV_FULLRATE) >> 8) & 0xff); snd_sonicvibes_out(sonic, SV_IREG_LEFT_ADC, mge ? 0xd0 : 0xc0); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_ADC, 0xc0); snd_sonicvibes_out(sonic, SV_IREG_LEFT_AUX1, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_AUX1, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_CD, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_CD, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_LINE, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_LINE, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_MIC, 0x8f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_SYNTH, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_SYNTH, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_AUX2, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_AUX2, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_ANALOG, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_ANALOG, 0x9f); snd_sonicvibes_out(sonic, SV_IREG_LEFT_PCM, 0xbf); snd_sonicvibes_out(sonic, SV_IREG_RIGHT_PCM, 0xbf); snd_sonicvibes_out(sonic, SV_IREG_ADC_OUTPUT_CTRL, 0xfc); #if 0 snd_sonicvibes_debug(sonic); #endif sonic->revision = snd_sonicvibes_in(sonic, SV_IREG_REVISION); snd_sonicvibes_proc_init(sonic); return 0; } /* * MIDI section */ static const struct snd_kcontrol_new snd_sonicvibes_midi_controls[] = { SONICVIBES_SINGLE("SonicVibes Wave Source RAM", 0, SV_IREG_WAVE_SOURCE, 0, 1, 0), SONICVIBES_SINGLE("SonicVibes Wave Source RAM+ROM", 0, SV_IREG_WAVE_SOURCE, 1, 1, 0), SONICVIBES_SINGLE("SonicVibes Onboard Synth", 0, SV_IREG_MPU401, 0, 1, 0), SONICVIBES_SINGLE("SonicVibes External Rx to Synth", 0, SV_IREG_MPU401, 1, 1, 0), SONICVIBES_SINGLE("SonicVibes External Tx", 0, SV_IREG_MPU401, 2, 1, 0) }; static int snd_sonicvibes_midi_input_open(struct snd_mpu401 * mpu) { struct sonicvibes *sonic = mpu->private_data; outb(sonic->irqmask &= ~SV_MIDI_MASK, SV_REG(sonic, IRQMASK)); return 0; } static void snd_sonicvibes_midi_input_close(struct snd_mpu401 * mpu) { struct sonicvibes *sonic = mpu->private_data; outb(sonic->irqmask |= SV_MIDI_MASK, SV_REG(sonic, IRQMASK)); } static int snd_sonicvibes_midi(struct sonicvibes *sonic, struct snd_rawmidi *rmidi) { struct snd_mpu401 * mpu = rmidi->private_data; struct snd_card *card = sonic->card; unsigned int idx; int err; mpu->private_data = sonic; mpu->open_input = snd_sonicvibes_midi_input_open; mpu->close_input = snd_sonicvibes_midi_input_close; for (idx = 0; idx < ARRAY_SIZE(snd_sonicvibes_midi_controls); idx++) { err = snd_ctl_add(card, snd_ctl_new1(&snd_sonicvibes_midi_controls[idx], sonic)); if (err < 0) return err; } return 0; } static int __snd_sonic_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct sonicvibes *sonic; struct snd_rawmidi *midi_uart; struct snd_opl3 *opl3; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*sonic), &card); if (err < 0) return err; sonic = card->private_data; err = snd_sonicvibes_create(card, pci, reverb[dev] ? 1 : 0, mge[dev] ? 1 : 0); if (err < 0) return err; strcpy(card->driver, "SonicVibes"); strcpy(card->shortname, "S3 SonicVibes"); sprintf(card->longname, "%s rev %i at 0x%llx, irq %i", card->shortname, sonic->revision, (unsigned long long)pci_resource_start(pci, 1), sonic->irq); err = snd_sonicvibes_pcm(sonic, 0); if (err < 0) return err; err = snd_sonicvibes_mixer(sonic); if (err < 0) return err; err = snd_mpu401_uart_new(card, 0, MPU401_HW_SONICVIBES, sonic->midi_port, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &midi_uart); if (err < 0) return err; snd_sonicvibes_midi(sonic, midi_uart); err = snd_opl3_create(card, sonic->synth_port, sonic->synth_port + 2, OPL3_HW_OPL3_SV, 1, &opl3); if (err < 0) return err; err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) return err; err = snd_sonicvibes_create_gameport(sonic); if (err < 0) return err; err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_sonic_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_sonic_probe(pci, pci_id)); } static struct pci_driver sonicvibes_driver = { .name = KBUILD_MODNAME, .id_table = snd_sonic_ids, .probe = snd_sonic_probe, }; module_pci_driver(sonicvibes_driver);
linux-master
sound/pci/sonicvibes.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA modem driver for Intel ICH (i8x0) chipsets * * Copyright (c) 2000 Jaroslav Kysela <[email protected]> * * This is modified (by Sasha Khapyorsky <[email protected]>) version * of ALSA ICH sound driver intel8x0.c . */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/ac97_codec.h> #include <sound/info.h> #include <sound/initval.h> MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " "SiS 7013; NVidia MCP/2/2S/3 modems"); MODULE_LICENSE("GPL"); static int index = -2; /* Exclude the first card */ static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ static int ac97_clock; module_param(index, int, 0444); MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); module_param(id, charp, 0444); MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); module_param(ac97_clock, int, 0444); MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); /* just for backward compatibility */ static bool enable; module_param(enable, bool, 0444); /* * Direct registers */ enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; #define ICHREG(x) ICH_REG_##x #define DEFINE_REGSET(name,base) \ enum { \ ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ } /* busmaster blocks */ DEFINE_REGSET(OFF, 0); /* offset */ /* values for each busmaster block */ /* LVI */ #define ICH_REG_LVI_MASK 0x1f /* SR */ #define ICH_FIFOE 0x10 /* FIFO error */ #define ICH_BCIS 0x08 /* buffer completion interrupt status */ #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ #define ICH_CELV 0x02 /* current equals last valid */ #define ICH_DCH 0x01 /* DMA controller halted */ /* PIV */ #define ICH_REG_PIV_MASK 0x1f /* mask */ /* CR */ #define ICH_IOCE 0x10 /* interrupt on completion enable */ #define ICH_FEIE 0x08 /* fifo error interrupt enable */ #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ #define ICH_RESETREGS 0x02 /* reset busmaster registers */ #define ICH_STARTBM 0x01 /* start busmaster operation */ /* global block */ #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ #define ICH_ACLINK 0x00000008 /* AClink shut off */ #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ #define ICH_GIE 0x00000001 /* GPI interrupt enable */ #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ #define ICH_MD3 0x00020000 /* modem power down semaphore */ #define ICH_AD3 0x00010000 /* audio power down semaphore */ #define ICH_RCS 0x00008000 /* read completion status */ #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ #define ICH_POINT 0x00000040 /* playback interrupt */ #define ICH_PIINT 0x00000020 /* capture interrupt */ #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ #define ICH_MOINT 0x00000004 /* modem playback interrupt */ #define ICH_MIINT 0x00000002 /* modem capture interrupt */ #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ #define ICH_CAS 0x01 /* codec access semaphore */ #define ICH_MAX_FRAGS 32 /* max hw frags */ /* * */ enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; #define get_ichdev(substream) (substream->runtime->private_data) struct ichdev { unsigned int ichd; /* ich device number */ unsigned long reg_offset; /* offset to bmaddr */ __le32 *bdbar; /* CPU address (32bit) */ unsigned int bdbar_addr; /* PCI bus address (32bit) */ struct snd_pcm_substream *substream; unsigned int physbuf; /* physical address (32bit) */ unsigned int size; unsigned int fragsize; unsigned int fragsize1; unsigned int position; int frags; int lvi; int lvi_frag; int civ; int ack; int ack_reload; unsigned int ack_bit; unsigned int roff_sr; unsigned int roff_picb; unsigned int int_sta_mask; /* interrupt status mask */ unsigned int ali_slot; /* ALI DMA slot */ struct snd_ac97 *ac97; }; struct intel8x0m { unsigned int device_type; int irq; void __iomem *addr; void __iomem *bmaddr; struct pci_dev *pci; struct snd_card *card; int pcm_devs; struct snd_pcm *pcm[2]; struct ichdev ichd[2]; unsigned int in_ac97_init: 1; struct snd_ac97_bus *ac97_bus; struct snd_ac97 *ac97; spinlock_t reg_lock; struct snd_dma_buffer *bdbars; u32 bdbars_count; u32 int_sta_reg; /* interrupt status register */ u32 int_sta_mask; /* interrupt status mask */ unsigned int pcm_pos_shift; }; static const struct pci_device_id snd_intel8x0m_ids[] = { { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */ { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */ { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */ { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */ { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */ { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */ { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */ { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */ { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */ { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */ { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */ { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */ { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */ { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */ { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */ { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */ #if 0 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ #endif { 0, } }; MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); /* * Lowlevel I/O - busmaster */ static inline u8 igetbyte(struct intel8x0m *chip, u32 offset) { return ioread8(chip->bmaddr + offset); } static inline u16 igetword(struct intel8x0m *chip, u32 offset) { return ioread16(chip->bmaddr + offset); } static inline u32 igetdword(struct intel8x0m *chip, u32 offset) { return ioread32(chip->bmaddr + offset); } static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) { iowrite8(val, chip->bmaddr + offset); } static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) { iowrite16(val, chip->bmaddr + offset); } static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) { iowrite32(val, chip->bmaddr + offset); } /* * Lowlevel I/O - AC'97 registers */ static inline u16 iagetword(struct intel8x0m *chip, u32 offset) { return ioread16(chip->addr + offset); } static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) { iowrite16(val, chip->addr + offset); } /* * Basic I/O */ /* * access to AC97 codec via normal i/o (for ICH and SIS7013) */ /* return the GLOB_STA bit for the corresponding codec */ static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) { static const unsigned int codec_bit[3] = { ICH_PCR, ICH_SCR, ICH_TCR }; if (snd_BUG_ON(codec >= 3)) return ICH_PCR; return codec_bit[codec]; } static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) { int time; if (codec > 1) return -EIO; codec = get_ich_codec_bit(chip, codec); /* codec ready ? */ if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) return -EIO; /* Anyone holding a semaphore for 1 msec should be shot... */ time = 100; do { if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) return 0; udelay(10); } while (time--); /* access to some forbidden (non existent) ac97 registers will not * reset the semaphore. So even if you don't get the semaphore, still * continue the access. We don't need the semaphore anyway. */ dev_err(chip->card->dev, "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); iagetword(chip, 0); /* clear semaphore flag */ /* I don't care about the semaphore */ return -EBUSY; } static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct intel8x0m *chip = ac97->private_data; if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { if (! chip->in_ac97_init) dev_err(chip->card->dev, "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); } iaputword(chip, reg + ac97->num * 0x80, val); } static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97, unsigned short reg) { struct intel8x0m *chip = ac97->private_data; unsigned short res; unsigned int tmp; if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { if (! chip->in_ac97_init) dev_err(chip->card->dev, "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); res = 0xffff; } else { res = iagetword(chip, reg + ac97->num * 0x80); tmp = igetdword(chip, ICHREG(GLOB_STA)); if (tmp & ICH_RCS) { /* reset RCS and preserve other R/WC bits */ iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); if (! chip->in_ac97_init) dev_err(chip->card->dev, "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); res = 0xffff; } } if (reg == AC97_GPIO_STATUS) iagetword(chip, 0); /* clear semaphore */ return res; } /* * DMA I/O */ static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) { int idx; __le32 *bdbar = ichdev->bdbar; unsigned long port = ichdev->reg_offset; iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); if (ichdev->size == ichdev->fragsize) { ichdev->ack_reload = ichdev->ack = 2; ichdev->fragsize1 = ichdev->fragsize >> 1; for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ ichdev->fragsize1 >> chip->pcm_pos_shift); bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ ichdev->fragsize1 >> chip->pcm_pos_shift); } ichdev->frags = 2; } else { ichdev->ack_reload = ichdev->ack = 1; ichdev->fragsize1 = ichdev->fragsize; for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ ichdev->fragsize >> chip->pcm_pos_shift); /* dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); */ } ichdev->frags = ichdev->size / ichdev->fragsize; } iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); ichdev->civ = 0; iputbyte(chip, port + ICH_REG_OFF_CIV, 0); ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; ichdev->position = 0; #if 0 dev_dbg(chip->card->dev, "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); #endif /* clear interrupts */ iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); } /* * Interrupt handler */ static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev) { unsigned long port = ichdev->reg_offset; int civ, i, step; int ack = 0; civ = igetbyte(chip, port + ICH_REG_OFF_CIV); if (civ == ichdev->civ) { // snd_printd("civ same %d\n", civ); step = 1; ichdev->civ++; ichdev->civ &= ICH_REG_LVI_MASK; } else { step = civ - ichdev->civ; if (step < 0) step += ICH_REG_LVI_MASK + 1; // if (step != 1) // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); ichdev->civ = civ; } ichdev->position += step * ichdev->fragsize1; ichdev->position %= ichdev->size; ichdev->lvi += step; ichdev->lvi &= ICH_REG_LVI_MASK; iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); for (i = 0; i < step; i++) { ichdev->lvi_frag++; ichdev->lvi_frag %= ichdev->frags; ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); #if 0 dev_dbg(chip->card->dev, "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR)); #endif if (--ichdev->ack == 0) { ichdev->ack = ichdev->ack_reload; ack = 1; } } if (ack && ichdev->substream) { spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(ichdev->substream); spin_lock(&chip->reg_lock); } iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); } static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id) { struct intel8x0m *chip = dev_id; struct ichdev *ichdev; unsigned int status; unsigned int i; spin_lock(&chip->reg_lock); status = igetdword(chip, chip->int_sta_reg); if (status == 0xffffffff) { /* we are not yet resumed */ spin_unlock(&chip->reg_lock); return IRQ_NONE; } if ((status & chip->int_sta_mask) == 0) { if (status) iputdword(chip, chip->int_sta_reg, status); spin_unlock(&chip->reg_lock); return IRQ_NONE; } for (i = 0; i < chip->bdbars_count; i++) { ichdev = &chip->ichd[i]; if (status & ichdev->int_sta_mask) snd_intel8x0m_update(chip, ichdev); } /* ack them */ iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); spin_unlock(&chip->reg_lock); return IRQ_HANDLED; } /* * PCM part */ static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); struct ichdev *ichdev = get_ichdev(substream); unsigned char val = 0; unsigned long port = ichdev->reg_offset; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: val = ICH_IOCE | ICH_STARTBM; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: val = 0; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: val = ICH_IOCE; break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: val = ICH_IOCE | ICH_STARTBM; break; default: return -EINVAL; } iputbyte(chip, port + ICH_REG_OFF_CR, val); if (cmd == SNDRV_PCM_TRIGGER_STOP) { /* wait until DMA stopped */ while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; /* reset whole DMA things */ iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); } return 0; } static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); struct ichdev *ichdev = get_ichdev(substream); size_t ptr1, ptr; ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; if (ptr1 != 0) ptr = ichdev->fragsize1 - ptr1; else ptr = 0; ptr += ichdev->position; if (ptr >= ichdev->size) return 0; return bytes_to_frames(substream->runtime, ptr); } static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ichdev *ichdev = get_ichdev(substream); ichdev->physbuf = runtime->dma_addr; ichdev->size = snd_pcm_lib_buffer_bytes(substream); ichdev->fragsize = snd_pcm_lib_period_bytes(substream); snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); snd_intel8x0m_setup_periods(chip, ichdev); return 0; } static const struct snd_pcm_hardware snd_intel8x0m_stream = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, .rate_min = 8000, .rate_max = 16000, .channels_min = 1, .channels_max = 1, .buffer_bytes_max = 64 * 1024, .period_bytes_min = 32, .period_bytes_max = 64 * 1024, .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) { static const unsigned int rates[] = { 8000, 9600, 12000, 16000 }; static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { .count = ARRAY_SIZE(rates), .list = rates, .mask = 0, }; struct snd_pcm_runtime *runtime = substream->runtime; int err; ichdev->substream = substream; runtime->hw = snd_intel8x0m_stream; err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); if ( err < 0 ) return err; runtime->private_data = ichdev; return 0; } static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); } static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); chip->ichd[ICHD_MDMOUT].substream = NULL; return 0; } static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); } static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) { struct intel8x0m *chip = snd_pcm_substream_chip(substream); chip->ichd[ICHD_MDMIN].substream = NULL; return 0; } static const struct snd_pcm_ops snd_intel8x0m_playback_ops = { .open = snd_intel8x0m_playback_open, .close = snd_intel8x0m_playback_close, .prepare = snd_intel8x0m_pcm_prepare, .trigger = snd_intel8x0m_pcm_trigger, .pointer = snd_intel8x0m_pcm_pointer, }; static const struct snd_pcm_ops snd_intel8x0m_capture_ops = { .open = snd_intel8x0m_capture_open, .close = snd_intel8x0m_capture_close, .prepare = snd_intel8x0m_pcm_prepare, .trigger = snd_intel8x0m_pcm_trigger, .pointer = snd_intel8x0m_pcm_pointer, }; struct ich_pcm_table { char *suffix; const struct snd_pcm_ops *playback_ops; const struct snd_pcm_ops *capture_ops; size_t prealloc_size; size_t prealloc_max_size; int ac97_idx; }; static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device, const struct ich_pcm_table *rec) { struct snd_pcm *pcm; int err; char name[32]; if (rec->suffix) sprintf(name, "Intel ICH - %s", rec->suffix); else strcpy(name, "Intel ICH"); err = snd_pcm_new(chip->card, name, device, rec->playback_ops ? 1 : 0, rec->capture_ops ? 1 : 0, &pcm); if (err < 0) return err; if (rec->playback_ops) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); if (rec->capture_ops) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); pcm->private_data = chip; pcm->info_flags = 0; pcm->dev_class = SNDRV_PCM_CLASS_MODEM; if (rec->suffix) sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); else strcpy(pcm->name, chip->card->shortname); chip->pcm[device] = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, rec->prealloc_size, rec->prealloc_max_size); return 0; } static const struct ich_pcm_table intel_pcms[] = { { .suffix = "Modem", .playback_ops = &snd_intel8x0m_playback_ops, .capture_ops = &snd_intel8x0m_capture_ops, .prealloc_size = 32 * 1024, .prealloc_max_size = 64 * 1024, }, }; static int snd_intel8x0m_pcm(struct intel8x0m *chip) { int i, tblsize, device, err; const struct ich_pcm_table *tbl, *rec; #if 1 tbl = intel_pcms; tblsize = 1; #else switch (chip->device_type) { case DEVICE_NFORCE: tbl = nforce_pcms; tblsize = ARRAY_SIZE(nforce_pcms); break; case DEVICE_ALI: tbl = ali_pcms; tblsize = ARRAY_SIZE(ali_pcms); break; default: tbl = intel_pcms; tblsize = 2; break; } #endif device = 0; for (i = 0; i < tblsize; i++) { rec = tbl + i; if (i > 0 && rec->ac97_idx) { /* activate PCM only when associated AC'97 codec */ if (! chip->ichd[rec->ac97_idx].ac97) continue; } err = snd_intel8x0m_pcm1(chip, device, rec); if (err < 0) return err; device++; } chip->pcm_devs = device; return 0; } /* * Mixer part */ static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus) { struct intel8x0m *chip = bus->private_data; chip->ac97_bus = NULL; } static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97) { struct intel8x0m *chip = ac97->private_data; chip->ac97 = NULL; } static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock) { struct snd_ac97_bus *pbus; struct snd_ac97_template ac97; struct snd_ac97 *x97; int err; unsigned int glob_sta = 0; static const struct snd_ac97_bus_ops ops = { .write = snd_intel8x0m_codec_write, .read = snd_intel8x0m_codec_read, }; chip->in_ac97_init = 1; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; ac97.private_free = snd_intel8x0m_mixer_free_ac97; ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; glob_sta = igetdword(chip, ICHREG(GLOB_STA)); err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus); if (err < 0) goto __err; pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus; if (ac97_clock >= 8000 && ac97_clock <= 48000) pbus->clock = ac97_clock; chip->ac97_bus = pbus; ac97.pci = chip->pci; ac97.num = glob_sta & ICH_SCR ? 1 : 0; err = snd_ac97_mixer(pbus, &ac97, &x97); if (err < 0) { dev_err(chip->card->dev, "Unable to initialize codec #%d\n", ac97.num); if (ac97.num == 0) goto __err; return err; } chip->ac97 = x97; if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { chip->ichd[ICHD_MDMIN].ac97 = x97; chip->ichd[ICHD_MDMOUT].ac97 = x97; } chip->in_ac97_init = 0; return 0; __err: /* clear the cold-reset bit for the next chance */ if (chip->device_type != DEVICE_ALI) iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); return err; } /* * */ static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) { unsigned long end_time; unsigned int cnt, status, nstatus; /* put logic to right state */ /* first clear status bits */ status = ICH_RCS | ICH_MIINT | ICH_MOINT; cnt = igetdword(chip, ICHREG(GLOB_STA)); iputdword(chip, ICHREG(GLOB_STA), cnt & status); /* ACLink on, 2 channels */ cnt = igetdword(chip, ICHREG(GLOB_CNT)); cnt &= ~(ICH_ACLINK); /* finish cold or do warm reset */ cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; iputdword(chip, ICHREG(GLOB_CNT), cnt); usleep_range(500, 1000); /* give warm reset some time */ end_time = jiffies + HZ / 4; do { if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) goto __ok; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT))); return -EIO; __ok: if (probing) { /* wait for any codec ready status. * Once it becomes ready it should remain ready * as long as we do not disable the ac97 link. */ end_time = jiffies + HZ; do { status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); if (status) break; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); if (! status) { /* no codec is found */ dev_err(chip->card->dev, "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA))); return -EIO; } /* up to two codecs (modem cannot be tertiary with ICH4) */ nstatus = ICH_PCR | ICH_SCR; /* wait for other codecs ready status. */ end_time = jiffies + HZ / 4; while (status != nstatus && time_after_eq(end_time, jiffies)) { schedule_timeout_uninterruptible(1); status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; } } else { /* resume phase */ status = 0; if (chip->ac97) status |= get_ich_codec_bit(chip, chip->ac97->num); /* wait until all the probed codecs are ready */ end_time = jiffies + HZ; do { nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); if (status == nstatus) break; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); } if (chip->device_type == DEVICE_SIS) { /* unmute the output on SIS7012 */ iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); } return 0; } static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing) { unsigned int i; int err; err = snd_intel8x0m_ich_chip_init(chip, probing); if (err < 0) return err; iagetword(chip, 0); /* clear semaphore flag */ /* disable interrupts */ for (i = 0; i < chip->bdbars_count; i++) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); /* reset channels */ for (i = 0; i < chip->bdbars_count; i++) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); /* initialize Buffer Descriptor Lists */ for (i = 0; i < chip->bdbars_count; i++) iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); return 0; } static void snd_intel8x0m_free(struct snd_card *card) { struct intel8x0m *chip = card->private_data; unsigned int i; if (chip->irq < 0) goto __hw_end; /* disable interrupts */ for (i = 0; i < chip->bdbars_count; i++) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); /* reset channels */ for (i = 0; i < chip->bdbars_count; i++) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); __hw_end: if (chip->irq >= 0) free_irq(chip->irq, chip); } #ifdef CONFIG_PM_SLEEP /* * power management */ static int intel8x0m_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct intel8x0m *chip = card->private_data; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_ac97_suspend(chip->ac97); if (chip->irq >= 0) { free_irq(chip->irq, chip); chip->irq = -1; card->sync_irq = -1; } return 0; } static int intel8x0m_resume(struct device *dev) { struct pci_dev *pci = to_pci_dev(dev); struct snd_card *card = dev_get_drvdata(dev); struct intel8x0m *chip = card->private_data; if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(dev, "unable to grab IRQ %d, disabling device\n", pci->irq); snd_card_disconnect(card); return -EIO; } chip->irq = pci->irq; card->sync_irq = chip->irq; snd_intel8x0m_chip_init(chip, 0); snd_ac97_resume(chip->ac97); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume); #define INTEL8X0M_PM_OPS &intel8x0m_pm #else #define INTEL8X0M_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) { struct intel8x0m *chip = entry->private_data; unsigned int tmp; snd_iprintf(buffer, "Intel8x0m\n\n"); if (chip->device_type == DEVICE_ALI) return; tmp = igetdword(chip, ICHREG(GLOB_STA)); snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", tmp & ICH_PCR ? " primary" : "", tmp & ICH_SCR ? " secondary" : "", tmp & ICH_TCR ? " tertiary" : "", (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); } static void snd_intel8x0m_proc_init(struct intel8x0m *chip) { snd_card_ro_proc_new(chip->card, "intel8x0m", chip, snd_intel8x0m_proc_read); } struct ich_reg_info { unsigned int int_sta_mask; unsigned int offset; }; static int snd_intel8x0m_init(struct snd_card *card, struct pci_dev *pci, unsigned long device_type) { struct intel8x0m *chip = card->private_data; int err; unsigned int i; unsigned int int_sta_masks; struct ichdev *ichdev; static const struct ich_reg_info intel_regs[2] = { { ICH_MIINT, 0 }, { ICH_MOINT, 0x10 }, }; const struct ich_reg_info *tbl; err = pcim_enable_device(pci); if (err < 0) return err; spin_lock_init(&chip->reg_lock); chip->device_type = device_type; chip->card = card; chip->pci = pci; chip->irq = -1; err = pci_request_regions(pci, card->shortname); if (err < 0) return err; if (device_type == DEVICE_ALI) { /* ALI5455 has no ac97 region */ chip->bmaddr = pcim_iomap(pci, 0, 0); } else { if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ chip->addr = pcim_iomap(pci, 2, 0); else chip->addr = pcim_iomap(pci, 0, 0); if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ chip->bmaddr = pcim_iomap(pci, 3, 0); else chip->bmaddr = pcim_iomap(pci, 1, 0); } /* initialize offsets */ chip->bdbars_count = 2; tbl = intel_regs; for (i = 0; i < chip->bdbars_count; i++) { ichdev = &chip->ichd[i]; ichdev->ichd = i; ichdev->reg_offset = tbl[i].offset; ichdev->int_sta_mask = tbl[i].int_sta_mask; if (device_type == DEVICE_SIS) { /* SiS 7013 swaps the registers */ ichdev->roff_sr = ICH_REG_OFF_PICB; ichdev->roff_picb = ICH_REG_OFF_SR; } else { ichdev->roff_sr = ICH_REG_OFF_SR; ichdev->roff_picb = ICH_REG_OFF_PICB; } if (device_type == DEVICE_ALI) ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; } /* SIS7013 handles the pcm data in bytes, others are in words */ chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; /* allocate buffer descriptor lists */ /* the start of each lists must be aligned to 8 bytes */ chip->bdbars = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2); if (!chip->bdbars) return -ENOMEM; /* tables must be aligned to 8 bytes here, but the kernel pages are much bigger, so we don't care (on i386) */ int_sta_masks = 0; for (i = 0; i < chip->bdbars_count; i++) { ichdev = &chip->ichd[i]; ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2); ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); int_sta_masks |= ichdev->int_sta_mask; } chip->int_sta_reg = ICH_REG_GLOB_STA; chip->int_sta_mask = int_sta_masks; pci_set_master(pci); err = snd_intel8x0m_chip_init(chip, 1); if (err < 0) return err; /* NOTE: we don't use devm version here since it's released / * re-acquired in PM callbacks. * It's released explicitly in snd_intel8x0m_free(), too. */ if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_intel8x0m_free; return 0; } static struct shortname_table { unsigned int id; const char *s; } shortnames[] = { { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, { 0x7446, "AMD AMD768" }, { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, { 0x746e, "AMD AMD8111" }, #if 0 { 0x5455, "ALi M5455" }, #endif { 0 }, }; static int __snd_intel8x0m_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { struct snd_card *card; struct intel8x0m *chip; int err; struct shortname_table *name; err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; strcpy(card->driver, "ICH-MODEM"); strcpy(card->shortname, "Intel ICH"); for (name = shortnames; name->id; name++) { if (pci->device == name->id) { strcpy(card->shortname, name->s); break; } } strcat(card->shortname," Modem"); err = snd_intel8x0m_init(card, pci, pci_id->driver_data); if (err < 0) return err; err = snd_intel8x0m_mixer(chip, ac97_clock); if (err < 0) return err; err = snd_intel8x0m_pcm(chip); if (err < 0) return err; snd_intel8x0m_proc_init(chip); sprintf(card->longname, "%s at irq %i", card->shortname, chip->irq); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); return 0; } static int snd_intel8x0m_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_intel8x0m_probe(pci, pci_id)); } static struct pci_driver intel8x0m_driver = { .name = KBUILD_MODNAME, .id_table = snd_intel8x0m_ids, .probe = snd_intel8x0m_probe, .driver = { .pm = INTEL8X0M_PM_OPS, }, }; module_pci_driver(intel8x0m_driver);
linux-master
sound/pci/intel8x0m.c
// SPDX-License-Identifier: GPL-2.0-only /* Analog Devices 1889 audio driver * * This is a driver for the AD1889 PCI audio chipset found * on the HP PA-RISC [BCJ]-xxx0 workstations. * * Copyright (C) 2004-2005, Kyle McMartin <[email protected]> * Copyright (C) 2005, Thibaut Varene <[email protected]> * Based on the OSS AD1889 driver by Randolph Chung <[email protected]> * * TODO: * Do we need to take care of CCS register? * Maybe we could use finer grained locking (separate locks for pb/cap)? * Wishlist: * Control Interface (mixer) support * Better AC97 support (VSR...)? * PM support * MIDI support * Game Port support * SG DMA support (this will need *a lot* of work) */ #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/io.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/initval.h> #include <sound/ac97_codec.h> #include "ad1889.h" #include "ac97/ac97_id.h" #define AD1889_DRVVER "Version: 1.7" MODULE_AUTHOR("Kyle McMartin <[email protected]>, Thibaut Varene <[email protected]>"); MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver"); MODULE_LICENSE("GPL"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard."); static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard."); static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable AD1889 soundcard."); static char *ac97_quirk[SNDRV_CARDS]; module_param_array(ac97_quirk, charp, NULL, 0444); MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); #define DEVNAME "ad1889" #define PFX DEVNAME ": " /* keep track of some hw registers */ struct ad1889_register_state { u16 reg; /* reg setup */ u32 addr; /* dma base address */ unsigned long size; /* DMA buffer size */ }; struct snd_ad1889 { struct snd_card *card; struct pci_dev *pci; int irq; unsigned long bar; void __iomem *iobase; struct snd_ac97 *ac97; struct snd_ac97_bus *ac97_bus; struct snd_pcm *pcm; struct snd_info_entry *proc; struct snd_pcm_substream *psubs; struct snd_pcm_substream *csubs; /* playback register state */ struct ad1889_register_state wave; struct ad1889_register_state ramc; spinlock_t lock; }; static inline u16 ad1889_readw(struct snd_ad1889 *chip, unsigned reg) { return readw(chip->iobase + reg); } static inline void ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val) { writew(val, chip->iobase + reg); } static inline u32 ad1889_readl(struct snd_ad1889 *chip, unsigned reg) { return readl(chip->iobase + reg); } static inline void ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val) { writel(val, chip->iobase + reg); } static inline void ad1889_unmute(struct snd_ad1889 *chip) { u16 st; st = ad1889_readw(chip, AD_DS_WADA) & ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM); ad1889_writew(chip, AD_DS_WADA, st); ad1889_readw(chip, AD_DS_WADA); } static inline void ad1889_mute(struct snd_ad1889 *chip) { u16 st; st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM; ad1889_writew(chip, AD_DS_WADA, st); ad1889_readw(chip, AD_DS_WADA); } static inline void ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address) { ad1889_writel(chip, AD_DMA_ADCBA, address); ad1889_writel(chip, AD_DMA_ADCCA, address); } static inline void ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count) { ad1889_writel(chip, AD_DMA_ADCBC, count); ad1889_writel(chip, AD_DMA_ADCCC, count); } static inline void ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count) { ad1889_writel(chip, AD_DMA_ADCIB, count); ad1889_writel(chip, AD_DMA_ADCIC, count); } static inline void ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address) { ad1889_writel(chip, AD_DMA_WAVBA, address); ad1889_writel(chip, AD_DMA_WAVCA, address); } static inline void ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count) { ad1889_writel(chip, AD_DMA_WAVBC, count); ad1889_writel(chip, AD_DMA_WAVCC, count); } static inline void ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count) { ad1889_writel(chip, AD_DMA_WAVIB, count); ad1889_writel(chip, AD_DMA_WAVIC, count); } static void ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel) { u16 reg; if (channel & AD_CHAN_WAV) { /* Disable wave channel */ reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN; ad1889_writew(chip, AD_DS_WSMC, reg); chip->wave.reg = reg; /* disable IRQs */ reg = ad1889_readw(chip, AD_DMA_WAV); reg &= AD_DMA_IM_DIS; reg &= ~AD_DMA_LOOP; ad1889_writew(chip, AD_DMA_WAV, reg); /* clear IRQ and address counters and pointers */ ad1889_load_wave_buffer_address(chip, 0x0); ad1889_load_wave_buffer_count(chip, 0x0); ad1889_load_wave_interrupt_count(chip, 0x0); /* flush */ ad1889_readw(chip, AD_DMA_WAV); } if (channel & AD_CHAN_ADC) { /* Disable ADC channel */ reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN; ad1889_writew(chip, AD_DS_RAMC, reg); chip->ramc.reg = reg; reg = ad1889_readw(chip, AD_DMA_ADC); reg &= AD_DMA_IM_DIS; reg &= ~AD_DMA_LOOP; ad1889_writew(chip, AD_DMA_ADC, reg); ad1889_load_adc_buffer_address(chip, 0x0); ad1889_load_adc_buffer_count(chip, 0x0); ad1889_load_adc_interrupt_count(chip, 0x0); /* flush */ ad1889_readw(chip, AD_DMA_ADC); } } static u16 snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { struct snd_ad1889 *chip = ac97->private_data; return ad1889_readw(chip, AD_AC97_BASE + reg); } static void snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct snd_ad1889 *chip = ac97->private_data; ad1889_writew(chip, AD_AC97_BASE + reg, val); } static int snd_ad1889_ac97_ready(struct snd_ad1889 *chip) { int retry = 400; /* average needs 352 msec */ while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY) && --retry) usleep_range(1000, 2000); if (!retry) { dev_err(chip->card->dev, "[%s] Link is not ready.\n", __func__); return -EIO; } dev_dbg(chip->card->dev, "[%s] ready after %d ms\n", __func__, 400 - retry); return 0; } static const struct snd_pcm_hardware snd_ad1889_playback_hw = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER, .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 8000, /* docs say 7000, but we're lazy */ .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = BUFFER_BYTES_MAX, .period_bytes_min = PERIOD_BYTES_MIN, .period_bytes_max = PERIOD_BYTES_MAX, .periods_min = PERIODS_MIN, .periods_max = PERIODS_MAX, /*.fifo_size = 0,*/ }; static const struct snd_pcm_hardware snd_ad1889_capture_hw = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER, .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_48000, .rate_min = 48000, /* docs say we could to VSR, but we're lazy */ .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = BUFFER_BYTES_MAX, .period_bytes_min = PERIOD_BYTES_MIN, .period_bytes_max = PERIOD_BYTES_MAX, .periods_min = PERIODS_MIN, .periods_max = PERIODS_MAX, /*.fifo_size = 0,*/ }; static int snd_ad1889_playback_open(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); struct snd_pcm_runtime *rt = ss->runtime; chip->psubs = ss; rt->hw = snd_ad1889_playback_hw; return 0; } static int snd_ad1889_capture_open(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); struct snd_pcm_runtime *rt = ss->runtime; chip->csubs = ss; rt->hw = snd_ad1889_capture_hw; return 0; } static int snd_ad1889_playback_close(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); chip->psubs = NULL; return 0; } static int snd_ad1889_capture_close(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); chip->csubs = NULL; return 0; } static int snd_ad1889_playback_prepare(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); struct snd_pcm_runtime *rt = ss->runtime; unsigned int size = snd_pcm_lib_buffer_bytes(ss); unsigned int count = snd_pcm_lib_period_bytes(ss); u16 reg; ad1889_channel_reset(chip, AD_CHAN_WAV); reg = ad1889_readw(chip, AD_DS_WSMC); /* Mask out 16-bit / Stereo */ reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST); if (snd_pcm_format_width(rt->format) == 16) reg |= AD_DS_WSMC_WA16; if (rt->channels > 1) reg |= AD_DS_WSMC_WAST; /* let's make sure we don't clobber ourselves */ spin_lock_irq(&chip->lock); chip->wave.size = size; chip->wave.reg = reg; chip->wave.addr = rt->dma_addr; ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); /* Set sample rates on the codec */ ad1889_writew(chip, AD_DS_WAS, rt->rate); /* Set up DMA */ ad1889_load_wave_buffer_address(chip, chip->wave.addr); ad1889_load_wave_buffer_count(chip, size); ad1889_load_wave_interrupt_count(chip, count); /* writes flush */ ad1889_readw(chip, AD_DS_WSMC); spin_unlock_irq(&chip->lock); dev_dbg(chip->card->dev, "prepare playback: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n", chip->wave.addr, count, size, reg, rt->rate); return 0; } static int snd_ad1889_capture_prepare(struct snd_pcm_substream *ss) { struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); struct snd_pcm_runtime *rt = ss->runtime; unsigned int size = snd_pcm_lib_buffer_bytes(ss); unsigned int count = snd_pcm_lib_period_bytes(ss); u16 reg; ad1889_channel_reset(chip, AD_CHAN_ADC); reg = ad1889_readw(chip, AD_DS_RAMC); /* Mask out 16-bit / Stereo */ reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST); if (snd_pcm_format_width(rt->format) == 16) reg |= AD_DS_RAMC_AD16; if (rt->channels > 1) reg |= AD_DS_RAMC_ADST; /* let's make sure we don't clobber ourselves */ spin_lock_irq(&chip->lock); chip->ramc.size = size; chip->ramc.reg = reg; chip->ramc.addr = rt->dma_addr; ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg); /* Set up DMA */ ad1889_load_adc_buffer_address(chip, chip->ramc.addr); ad1889_load_adc_buffer_count(chip, size); ad1889_load_adc_interrupt_count(chip, count); /* writes flush */ ad1889_readw(chip, AD_DS_RAMC); spin_unlock_irq(&chip->lock); dev_dbg(chip->card->dev, "prepare capture: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n", chip->ramc.addr, count, size, reg, rt->rate); return 0; } /* this is called in atomic context with IRQ disabled. Must be as fast as possible and not sleep. DMA should be *triggered* by this call. The WSMC "WAEN" bit triggers DMA Wave On/Off */ static int snd_ad1889_playback_trigger(struct snd_pcm_substream *ss, int cmd) { u16 wsmc; struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); wsmc = ad1889_readw(chip, AD_DS_WSMC); switch (cmd) { case SNDRV_PCM_TRIGGER_START: /* enable DMA loop & interrupts */ ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT); wsmc |= AD_DS_WSMC_WAEN; /* 1 to clear CHSS bit */ ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS); ad1889_unmute(chip); break; case SNDRV_PCM_TRIGGER_STOP: ad1889_mute(chip); wsmc &= ~AD_DS_WSMC_WAEN; break; default: snd_BUG(); return -EINVAL; } chip->wave.reg = wsmc; ad1889_writew(chip, AD_DS_WSMC, wsmc); ad1889_readw(chip, AD_DS_WSMC); /* flush */ /* reset the chip when STOP - will disable IRQs */ if (cmd == SNDRV_PCM_TRIGGER_STOP) ad1889_channel_reset(chip, AD_CHAN_WAV); return 0; } /* this is called in atomic context with IRQ disabled. Must be as fast as possible and not sleep. DMA should be *triggered* by this call. The RAMC "ADEN" bit triggers DMA ADC On/Off */ static int snd_ad1889_capture_trigger(struct snd_pcm_substream *ss, int cmd) { u16 ramc; struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); ramc = ad1889_readw(chip, AD_DS_RAMC); switch (cmd) { case SNDRV_PCM_TRIGGER_START: /* enable DMA loop & interrupts */ ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT); ramc |= AD_DS_RAMC_ADEN; /* 1 to clear CHSS bit */ ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS); break; case SNDRV_PCM_TRIGGER_STOP: ramc &= ~AD_DS_RAMC_ADEN; break; default: return -EINVAL; } chip->ramc.reg = ramc; ad1889_writew(chip, AD_DS_RAMC, ramc); ad1889_readw(chip, AD_DS_RAMC); /* flush */ /* reset the chip when STOP - will disable IRQs */ if (cmd == SNDRV_PCM_TRIGGER_STOP) ad1889_channel_reset(chip, AD_CHAN_ADC); return 0; } /* Called in atomic context with IRQ disabled */ static snd_pcm_uframes_t snd_ad1889_playback_pointer(struct snd_pcm_substream *ss) { size_t ptr = 0; struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) return 0; ptr = ad1889_readl(chip, AD_DMA_WAVCA); ptr -= chip->wave.addr; if (snd_BUG_ON(ptr >= chip->wave.size)) return 0; return bytes_to_frames(ss->runtime, ptr); } /* Called in atomic context with IRQ disabled */ static snd_pcm_uframes_t snd_ad1889_capture_pointer(struct snd_pcm_substream *ss) { size_t ptr = 0; struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN))) return 0; ptr = ad1889_readl(chip, AD_DMA_ADCCA); ptr -= chip->ramc.addr; if (snd_BUG_ON(ptr >= chip->ramc.size)) return 0; return bytes_to_frames(ss->runtime, ptr); } static const struct snd_pcm_ops snd_ad1889_playback_ops = { .open = snd_ad1889_playback_open, .close = snd_ad1889_playback_close, .prepare = snd_ad1889_playback_prepare, .trigger = snd_ad1889_playback_trigger, .pointer = snd_ad1889_playback_pointer, }; static const struct snd_pcm_ops snd_ad1889_capture_ops = { .open = snd_ad1889_capture_open, .close = snd_ad1889_capture_close, .prepare = snd_ad1889_capture_prepare, .trigger = snd_ad1889_capture_trigger, .pointer = snd_ad1889_capture_pointer, }; static irqreturn_t snd_ad1889_interrupt(int irq, void *dev_id) { unsigned long st; struct snd_ad1889 *chip = dev_id; st = ad1889_readl(chip, AD_DMA_DISR); /* clear ISR */ ad1889_writel(chip, AD_DMA_DISR, st); st &= AD_INTR_MASK; if (unlikely(!st)) return IRQ_NONE; if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI)) dev_dbg(chip->card->dev, "Unexpected master or target abort interrupt!\n"); if ((st & AD_DMA_DISR_WAVI) && chip->psubs) snd_pcm_period_elapsed(chip->psubs); if ((st & AD_DMA_DISR_ADCI) && chip->csubs) snd_pcm_period_elapsed(chip->csubs); return IRQ_HANDLED; } static int snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device) { int err; struct snd_pcm *pcm; err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1889_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1889_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, chip->card->shortname); chip->pcm = pcm; chip->psubs = NULL; chip->csubs = NULL; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, BUFFER_BYTES_MAX / 2, BUFFER_BYTES_MAX); return 0; } static void snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_ad1889 *chip = entry->private_data; u16 reg; int tmp; reg = ad1889_readw(chip, AD_DS_WSMC); snd_iprintf(buffer, "Wave output: %s\n", (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled"); snd_iprintf(buffer, "Wave Channels: %s\n", (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); snd_iprintf(buffer, "Wave Quality: %d-bit linear\n", (reg & AD_DS_WSMC_WA16) ? 16 : 8); /* WARQ is at offset 12 */ tmp = (reg & AD_DS_WSMC_WARQ) ? ((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4; tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp, (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); snd_iprintf(buffer, "Synthesis output: %s\n", reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled"); /* SYRQ is at offset 4 */ tmp = (reg & AD_DS_WSMC_SYRQ) ? ((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4; tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp, (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); reg = ad1889_readw(chip, AD_DS_RAMC); snd_iprintf(buffer, "ADC input: %s\n", (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled"); snd_iprintf(buffer, "ADC Channels: %s\n", (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); snd_iprintf(buffer, "ADC Quality: %d-bit linear\n", (reg & AD_DS_RAMC_AD16) ? 16 : 8); /* ACRQ is at offset 4 */ tmp = (reg & AD_DS_RAMC_ACRQ) ? ((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4; tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp, (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); snd_iprintf(buffer, "Resampler input: %s\n", reg & AD_DS_RAMC_REEN ? "enabled" : "disabled"); /* RERQ is at offset 12 */ tmp = (reg & AD_DS_RAMC_RERQ) ? ((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4; tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp, (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); /* doc says LSB represents -1.5dB, but the max value (-94.5dB) suggests that LSB is -3dB, which is more coherent with the logarithmic nature of the dB scale */ reg = ad1889_readw(chip, AD_DS_WADA); snd_iprintf(buffer, "Left: %s, -%d dB\n", (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute", ((reg & AD_DS_WADA_LWAA) >> 8) * 3); reg = ad1889_readw(chip, AD_DS_WADA); snd_iprintf(buffer, "Right: %s, -%d dB\n", (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute", (reg & AD_DS_WADA_RWAA) * 3); reg = ad1889_readw(chip, AD_DS_WAS); snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg); reg = ad1889_readw(chip, AD_DS_RES); snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg); } static void snd_ad1889_proc_init(struct snd_ad1889 *chip) { snd_card_ro_proc_new(chip->card, chip->card->driver, chip, snd_ad1889_proc_read); } static const struct ac97_quirk ac97_quirks[] = { { .subvendor = 0x11d4, /* AD */ .subdevice = 0x1889, /* AD1889 */ .codec_id = AC97_ID_AD1819, .name = "AD1889", .type = AC97_TUNE_HP_ONLY }, { } /* terminator */ }; static void snd_ad1889_ac97_xinit(struct snd_ad1889 *chip) { u16 reg; reg = ad1889_readw(chip, AD_AC97_ACIC); reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */ ad1889_writew(chip, AD_AC97_ACIC, reg); ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */ udelay(10); /* Interface Enable */ reg |= AD_AC97_ACIC_ACIE; ad1889_writew(chip, AD_AC97_ACIC, reg); snd_ad1889_ac97_ready(chip); /* Audio Stream Output | Variable Sample Rate Mode */ reg = ad1889_readw(chip, AD_AC97_ACIC); reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM; ad1889_writew(chip, AD_AC97_ACIC, reg); ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */ } static int snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override) { int err; struct snd_ac97_template ac97; static const struct snd_ac97_bus_ops ops = { .write = snd_ad1889_ac97_write, .read = snd_ad1889_ac97_read, }; /* doing that here, it works. */ snd_ad1889_ac97_xinit(chip); err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus); if (err < 0) return err; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; ac97.pci = chip->pci; err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); if (err < 0) return err; snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override); return 0; } static void snd_ad1889_free(struct snd_card *card) { struct snd_ad1889 *chip = card->private_data; spin_lock_irq(&chip->lock); ad1889_mute(chip); /* Turn off interrupt on count and zero DMA registers */ ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC); /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */ ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI); ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */ spin_unlock_irq(&chip->lock); } static int snd_ad1889_create(struct snd_card *card, struct pci_dev *pci) { struct snd_ad1889 *chip = card->private_data; int err; err = pcim_enable_device(pci); if (err < 0) return err; /* check PCI availability (32bit DMA) */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32))) { dev_err(card->dev, "error setting 32-bit DMA mask.\n"); return -ENXIO; } chip->card = card; chip->pci = pci; chip->irq = -1; /* (1) PCI resource allocation */ err = pcim_iomap_regions(pci, 1 << 0, card->driver); if (err < 0) return err; chip->bar = pci_resource_start(pci, 0); chip->iobase = pcim_iomap_table(pci)[0]; pci_set_master(pci); spin_lock_init(&chip->lock); /* only now can we call ad1889_free */ if (devm_request_irq(&pci->dev, pci->irq, snd_ad1889_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "cannot obtain IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_ad1889_free; /* (2) initialization of the chip hardware */ ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */ ad1889_readw(chip, AD_DS_CCS); /* flush posted write */ usleep_range(10000, 11000); /* enable Master and Target abort interrupts */ ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE); return 0; } static int __snd_ad1889_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { int err; static int devno; struct snd_card *card; struct snd_ad1889 *chip; /* (1) */ if (devno >= SNDRV_CARDS) return -ENODEV; if (!enable[devno]) { devno++; return -ENOENT; } /* (2) */ err = snd_devm_card_new(&pci->dev, index[devno], id[devno], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; strcpy(card->driver, "AD1889"); strcpy(card->shortname, "Analog Devices AD1889"); /* (3) */ err = snd_ad1889_create(card, pci); if (err < 0) return err; /* (4) */ sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->bar, chip->irq); /* (5) */ /* register AC97 mixer */ err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]); if (err < 0) return err; err = snd_ad1889_pcm_init(chip, 0); if (err < 0) return err; /* register proc interface */ snd_ad1889_proc_init(chip); /* (6) */ err = snd_card_register(card); if (err < 0) return err; /* (7) */ pci_set_drvdata(pci, card); devno++; return 0; } static int snd_ad1889_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_ad1889_probe(pci, pci_id)); } static const struct pci_device_id snd_ad1889_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) }, { 0, }, }; MODULE_DEVICE_TABLE(pci, snd_ad1889_ids); static struct pci_driver ad1889_pci_driver = { .name = KBUILD_MODNAME, .id_table = snd_ad1889_ids, .probe = snd_ad1889_probe, }; module_pci_driver(ad1889_pci_driver);
linux-master
sound/pci/ad1889.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces * * Copyright (c) 2002-2004 Martin Langer <[email protected]>, * Pilo Chambert <[email protected]> * * Thanks to : Anders Torger <[email protected]>, * Henk Hesselink <[email protected]> * for writing the digi96-driver * and RME for all informations. * * **************************************************************************** * * Note #1 "Sek'd models" ................................... martin 2002-12-07 * * Identical soundcards by Sek'd were labeled: * RME Digi 32 = Sek'd Prodif 32 * RME Digi 32 Pro = Sek'd Prodif 96 * RME Digi 32/8 = Sek'd Prodif Gold * * **************************************************************************** * * Note #2 "full duplex mode" ............................... martin 2002-12-07 * * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical * in this mode. Rec data and play data are using the same buffer therefore. At * first you have got the playing bits in the buffer and then (after playing * them) they were overwitten by the captured sound of the CS8412/14. Both * modes (play/record) are running harmonically hand in hand in the same buffer * and you have only one start bit plus one interrupt bit to control this * paired action. * This is opposite to the latter rme96 where playing and capturing is totally * separated and so their full duplex mode is supported by alsa (using two * start bits and two interrupts for two different buffers). * But due to the wrong sequence of playing and capturing ALSA shows no solved * full duplex support for the rme32 at the moment. That's bad, but I'm not * able to solve it. Are you motivated enough to solve this problem now? Your * patch would be welcome! * * **************************************************************************** * * "The story after the long seeking" -- tiwai * * Ok, the situation regarding the full duplex is now improved a bit. * In the fullduplex mode (given by the module parameter), the hardware buffer * is split to halves for read and write directions at the DMA pointer. * That is, the half above the current DMA pointer is used for write, and * the half below is used for read. To mangle this strange behavior, an * software intermediate buffer is introduced. This is, of course, not good * from the viewpoint of the data transfer efficiency. However, this allows * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. * * **************************************************************************** */ #include <linux/delay.h> #include <linux/gfp.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/module.h> #include <linux/io.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/pcm-indirect.h> #include <sound/asoundef.h> #include <sound/initval.h> static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); module_param_array(fullduplex, bool, NULL, 0444); MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); MODULE_AUTHOR("Martin Langer <[email protected]>, Pilo Chambert <[email protected]>"); MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); MODULE_LICENSE("GPL"); /* Defines for RME Digi32 series */ #define RME32_SPDIF_NCHANNELS 2 /* Playback and capture buffer size */ #define RME32_BUFFER_SIZE 0x20000 /* IO area size */ #define RME32_IO_SIZE 0x30000 /* IO area offsets */ #define RME32_IO_DATA_BUFFER 0x0 #define RME32_IO_CONTROL_REGISTER 0x20000 #define RME32_IO_GET_POS 0x20000 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 #define RME32_IO_RESET_POS 0x20100 /* Write control register bits */ #define RME32_WCR_START (1 << 0) /* startbit */ #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono Setting the whole card to mono doesn't seem to be very useful. A software-solution can handle full-duplex with one direction in stereo and the other way in mono. So, the hardware should work all the time in stereo! */ #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ #define RME32_WCR_FREQ_1 (1 << 5) #define RME32_WCR_INP_0 (1 << 6) /* input switch */ #define RME32_WCR_INP_1 (1 << 7) #define RME32_WCR_RESET (1 << 8) /* Reset address */ #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ #define RME32_WCR_BITPOS_FREQ_0 4 #define RME32_WCR_BITPOS_FREQ_1 5 #define RME32_WCR_BITPOS_INP_0 6 #define RME32_WCR_BITPOS_INP_1 7 /* Read control register bits */ #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ #define RME32_RCR_FREQ_1 (1 << 28) #define RME32_RCR_FREQ_2 (1 << 29) #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ #define RME32_RCR_IRQ (1 << 31) /* interrupt */ #define RME32_RCR_BITPOS_F0 27 #define RME32_RCR_BITPOS_F1 28 #define RME32_RCR_BITPOS_F2 29 /* Input types */ #define RME32_INPUT_OPTICAL 0 #define RME32_INPUT_COAXIAL 1 #define RME32_INPUT_INTERNAL 2 #define RME32_INPUT_XLR 3 /* Clock modes */ #define RME32_CLOCKMODE_SLAVE 0 #define RME32_CLOCKMODE_MASTER_32 1 #define RME32_CLOCKMODE_MASTER_44 2 #define RME32_CLOCKMODE_MASTER_48 3 /* Block sizes in bytes */ #define RME32_BLOCK_SIZE 8192 /* Software intermediate buffer (max) size */ #define RME32_MID_BUFFER_SIZE (1024*1024) /* Hardware revisions */ #define RME32_32_REVISION 192 #define RME32_328_REVISION_OLD 100 #define RME32_328_REVISION_NEW 101 #define RME32_PRO_REVISION_WITH_8412 192 #define RME32_PRO_REVISION_WITH_8414 150 struct rme32 { spinlock_t lock; int irq; unsigned long port; void __iomem *iobase; u32 wcreg; /* cached write control register value */ u32 wcreg_spdif; /* S/PDIF setup */ u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ u32 rcreg; /* cached read control register value */ u8 rev; /* card revision number */ struct snd_pcm_substream *playback_substream; struct snd_pcm_substream *capture_substream; int playback_frlog; /* log2 of framesize */ int capture_frlog; size_t playback_periodsize; /* in bytes, zero if not used */ size_t capture_periodsize; /* in bytes, zero if not used */ unsigned int fullduplex_mode; int running; struct snd_pcm_indirect playback_pcm; struct snd_pcm_indirect capture_pcm; struct snd_card *card; struct snd_pcm *spdif_pcm; struct snd_pcm *adat_pcm; struct pci_dev *pci; struct snd_kcontrol *spdif_ctl; }; static const struct pci_device_id snd_rme32_ids[] = { {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, {0,} }; MODULE_DEVICE_TABLE(pci, snd_rme32_ids); #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); static void snd_rme32_proc_init(struct rme32 * rme32); static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) { return (readl(rme32->iobase + RME32_IO_GET_POS) & RME32_RCR_AUDIO_ADDR_MASK); } /* silence callback for halfduplex mode */ static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, unsigned long pos, unsigned long count) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); return 0; } /* copy callback for halfduplex mode */ static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, unsigned long pos, struct iov_iter *src, unsigned long count) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return copy_from_iter_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count); } /* copy callback for halfduplex mode */ static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, unsigned long pos, struct iov_iter *dst, unsigned long count) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return copy_to_iter_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count); } /* * SPDIF I/O capabilities (half-duplex mode) */ static const struct snd_pcm_hardware snd_rme32_spdif_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_SYNC_APPLPTR), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 32000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME32_BUFFER_SIZE, .period_bytes_min = RME32_BLOCK_SIZE, .period_bytes_max = RME32_BLOCK_SIZE, .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, .fifo_size = 0, }; /* * ADAT I/O capabilities (half-duplex mode) */ static const struct snd_pcm_hardware snd_rme32_adat_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_SYNC_APPLPTR), .formats= SNDRV_PCM_FMTBIT_S16_LE, .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME32_BUFFER_SIZE, .period_bytes_min = RME32_BLOCK_SIZE, .period_bytes_max = RME32_BLOCK_SIZE, .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, .fifo_size = 0, }; /* * SPDIF I/O capabilities (full-duplex mode) */ static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_SYNC_APPLPTR), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 32000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME32_MID_BUFFER_SIZE, .period_bytes_min = RME32_BLOCK_SIZE, .period_bytes_max = RME32_BLOCK_SIZE, .periods_min = 2, .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, .fifo_size = 0, }; /* * ADAT I/O capabilities (full-duplex mode) */ static const struct snd_pcm_hardware snd_rme32_adat_fd_info = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_SYNC_APPLPTR), .formats= SNDRV_PCM_FMTBIT_S16_LE, .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME32_MID_BUFFER_SIZE, .period_bytes_min = RME32_BLOCK_SIZE, .period_bytes_max = RME32_BLOCK_SIZE, .periods_min = 2, .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, .fifo_size = 0, }; static void snd_rme32_reset_dac(struct rme32 *rme32) { writel(rme32->wcreg | RME32_WCR_PD, rme32->iobase + RME32_IO_CONTROL_REGISTER); writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); } static int snd_rme32_playback_getrate(struct rme32 * rme32) { int rate; rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); switch (rate) { case 1: rate = 32000; break; case 2: rate = 44100; break; case 3: rate = 48000; break; default: return -1; } return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; } static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) { int n; *is_adat = 0; if (rme32->rcreg & RME32_RCR_LOCK) { /* ADAT rate */ *is_adat = 1; } if (rme32->rcreg & RME32_RCR_ERF) { return -1; } /* S/PDIF rate */ n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); if (RME32_PRO_WITH_8414(rme32)) switch (n) { /* supporting the CS8414 */ case 0: case 1: case 2: return -1; case 3: return 96000; case 4: return 88200; case 5: return 48000; case 6: return 44100; case 7: return 32000; default: return -1; } else switch (n) { /* supporting the CS8412 */ case 0: return -1; case 1: return 48000; case 2: return 44100; case 3: return 32000; case 4: return 48000; case 5: return 44100; case 6: return 44056; case 7: return 32000; default: break; } return -1; } static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) { int ds; ds = rme32->wcreg & RME32_WCR_DS_BM; switch (rate) { case 32000: rme32->wcreg &= ~RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & ~RME32_WCR_FREQ_1; break; case 44100: rme32->wcreg &= ~RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & ~RME32_WCR_FREQ_0; break; case 48000: rme32->wcreg &= ~RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | RME32_WCR_FREQ_1; break; case 64000: if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) return -EINVAL; rme32->wcreg |= RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & ~RME32_WCR_FREQ_1; break; case 88200: if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) return -EINVAL; rme32->wcreg |= RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & ~RME32_WCR_FREQ_0; break; case 96000: if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) return -EINVAL; rme32->wcreg |= RME32_WCR_DS_BM; rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | RME32_WCR_FREQ_1; break; default: return -EINVAL; } if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) { /* change to/from double-speed: reset the DAC (if available) */ snd_rme32_reset_dac(rme32); } else { writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); } return 0; } static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) { switch (mode) { case RME32_CLOCKMODE_SLAVE: /* AutoSync */ rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & ~RME32_WCR_FREQ_1; break; case RME32_CLOCKMODE_MASTER_32: /* Internal 32.0kHz */ rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & ~RME32_WCR_FREQ_1; break; case RME32_CLOCKMODE_MASTER_44: /* Internal 44.1kHz */ rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | RME32_WCR_FREQ_1; break; case RME32_CLOCKMODE_MASTER_48: /* Internal 48.0kHz */ rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | RME32_WCR_FREQ_1; break; default: return -EINVAL; } writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); return 0; } static int snd_rme32_getclockmode(struct rme32 * rme32) { return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); } static int snd_rme32_setinputtype(struct rme32 * rme32, int type) { switch (type) { case RME32_INPUT_OPTICAL: rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & ~RME32_WCR_INP_1; break; case RME32_INPUT_COAXIAL: rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & ~RME32_WCR_INP_1; break; case RME32_INPUT_INTERNAL: rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | RME32_WCR_INP_1; break; case RME32_INPUT_XLR: rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | RME32_WCR_INP_1; break; default: return -EINVAL; } writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); return 0; } static int snd_rme32_getinputtype(struct rme32 * rme32) { return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); } static void snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) { int frlog; if (n_channels == 2) { frlog = 1; } else { /* assume 8 channels */ frlog = 3; } if (is_playback) { frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; rme32->playback_frlog = frlog; } else { frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; rme32->capture_frlog = frlog; } } static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) { switch (format) { case SNDRV_PCM_FORMAT_S16_LE: rme32->wcreg &= ~RME32_WCR_MODE24; break; case SNDRV_PCM_FORMAT_S32_LE: rme32->wcreg |= RME32_WCR_MODE24; break; default: return -EINVAL; } writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); return 0; } static int snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int err, rate, dummy; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; if (!rme32->fullduplex_mode) { runtime->dma_area = (void __force *)(rme32->iobase + RME32_IO_DATA_BUFFER); runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; runtime->dma_bytes = RME32_BUFFER_SIZE; } spin_lock_irq(&rme32->lock); rate = 0; if (rme32->rcreg & RME32_RCR_KMODE) rate = snd_rme32_capture_getrate(rme32, &dummy); if (rate > 0) { /* AutoSync */ if ((int)params_rate(params) != rate) { spin_unlock_irq(&rme32->lock); return -EIO; } } else { err = snd_rme32_playback_setrate(rme32, params_rate(params)); if (err < 0) { spin_unlock_irq(&rme32->lock); return err; } } err = snd_rme32_setformat(rme32, params_format(params)); if (err < 0) { spin_unlock_irq(&rme32->lock); return err; } snd_rme32_setframelog(rme32, params_channels(params), 1); if (rme32->capture_periodsize != 0) { if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { spin_unlock_irq(&rme32->lock); return -EBUSY; } } rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; /* S/PDIF setup */ if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); rme32->wcreg |= rme32->wcreg_spdif_stream; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); } spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int err, isadat, rate; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; if (!rme32->fullduplex_mode) { runtime->dma_area = (void __force *)rme32->iobase + RME32_IO_DATA_BUFFER; runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; runtime->dma_bytes = RME32_BUFFER_SIZE; } spin_lock_irq(&rme32->lock); /* enable AutoSync for record-preparing */ rme32->wcreg |= RME32_WCR_AUTOSYNC; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); err = snd_rme32_setformat(rme32, params_format(params)); if (err < 0) { spin_unlock_irq(&rme32->lock); return err; } err = snd_rme32_playback_setrate(rme32, params_rate(params)); if (err < 0) { spin_unlock_irq(&rme32->lock); return err; } rate = snd_rme32_capture_getrate(rme32, &isadat); if (rate > 0) { if ((int)params_rate(params) != rate) { spin_unlock_irq(&rme32->lock); return -EIO; } if ((isadat && runtime->hw.channels_min == 2) || (!isadat && runtime->hw.channels_min == 8)) { spin_unlock_irq(&rme32->lock); return -EIO; } } /* AutoSync off for recording */ rme32->wcreg &= ~RME32_WCR_AUTOSYNC; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_setframelog(rme32, params_channels(params), 0); if (rme32->playback_periodsize != 0) { if (params_period_size(params) << rme32->capture_frlog != rme32->playback_periodsize) { spin_unlock_irq(&rme32->lock); return -EBUSY; } } rme32->capture_periodsize = params_period_size(params) << rme32->capture_frlog; spin_unlock_irq(&rme32->lock); return 0; } static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) { if (!from_pause) { writel(0, rme32->iobase + RME32_IO_RESET_POS); } rme32->wcreg |= RME32_WCR_START; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); } static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) { /* * Check if there is an unconfirmed IRQ, if so confirm it, or else * the hardware will not stop generating interrupts */ rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); if (rme32->rcreg & RME32_RCR_IRQ) { writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); } rme32->wcreg &= ~RME32_WCR_START; if (rme32->wcreg & RME32_WCR_SEL) rme32->wcreg |= RME32_WCR_MUTE; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); if (! to_pause) writel(0, rme32->iobase + RME32_IO_RESET_POS); } static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) { struct rme32 *rme32 = (struct rme32 *) dev_id; rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); if (!(rme32->rcreg & RME32_RCR_IRQ)) { return IRQ_NONE; } else { if (rme32->capture_substream) { snd_pcm_period_elapsed(rme32->capture_substream); } if (rme32->playback_substream) { snd_pcm_period_elapsed(rme32->playback_substream); } writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); } return IRQ_HANDLED; } static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { .count = ARRAY_SIZE(period_bytes), .list = period_bytes, .mask = 0 }; static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) { if (! rme32->fullduplex_mode) { snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME32_BUFFER_SIZE); snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); } } static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); spin_lock_irq(&rme32->lock); if (rme32->playback_substream != NULL) { spin_unlock_irq(&rme32->lock); return -EBUSY; } rme32->wcreg &= ~RME32_WCR_ADAT; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); rme32->playback_substream = substream; spin_unlock_irq(&rme32->lock); if (rme32->fullduplex_mode) runtime->hw = snd_rme32_spdif_fd_info; else runtime->hw = snd_rme32_spdif_info; if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } rate = 0; if (rme32->rcreg & RME32_RCR_KMODE) rate = snd_rme32_capture_getrate(rme32, &dummy); if (rate > 0) { /* AutoSync */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } snd_rme32_set_buffer_constraint(rme32, runtime); rme32->wcreg_spdif_stream = rme32->wcreg_spdif; rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); return 0; } static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); spin_lock_irq(&rme32->lock); if (rme32->capture_substream != NULL) { spin_unlock_irq(&rme32->lock); return -EBUSY; } rme32->capture_substream = substream; spin_unlock_irq(&rme32->lock); if (rme32->fullduplex_mode) runtime->hw = snd_rme32_spdif_fd_info; else runtime->hw = snd_rme32_spdif_info; if (RME32_PRO_WITH_8414(rme32)) { runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; runtime->hw.rate_max = 96000; } rate = snd_rme32_capture_getrate(rme32, &isadat); if (rate > 0) { if (isadat) { return -EIO; } runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } snd_rme32_set_buffer_constraint(rme32, runtime); return 0; } static int snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; snd_pcm_set_sync(substream); spin_lock_irq(&rme32->lock); if (rme32->playback_substream != NULL) { spin_unlock_irq(&rme32->lock); return -EBUSY; } rme32->wcreg |= RME32_WCR_ADAT; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); rme32->playback_substream = substream; spin_unlock_irq(&rme32->lock); if (rme32->fullduplex_mode) runtime->hw = snd_rme32_adat_fd_info; else runtime->hw = snd_rme32_adat_info; rate = 0; if (rme32->rcreg & RME32_RCR_KMODE) rate = snd_rme32_capture_getrate(rme32, &dummy); if (rate > 0) { /* AutoSync */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } snd_rme32_set_buffer_constraint(rme32, runtime); return 0; } static int snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; if (rme32->fullduplex_mode) runtime->hw = snd_rme32_adat_fd_info; else runtime->hw = snd_rme32_adat_info; rate = snd_rme32_capture_getrate(rme32, &isadat); if (rate > 0) { if (!isadat) { return -EIO; } runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } snd_pcm_set_sync(substream); spin_lock_irq(&rme32->lock); if (rme32->capture_substream != NULL) { spin_unlock_irq(&rme32->lock); return -EBUSY; } rme32->capture_substream = substream; spin_unlock_irq(&rme32->lock); snd_rme32_set_buffer_constraint(rme32, runtime); return 0; } static int snd_rme32_playback_close(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); int spdif = 0; spin_lock_irq(&rme32->lock); rme32->playback_substream = NULL; rme32->playback_periodsize = 0; spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; spin_unlock_irq(&rme32->lock); if (spdif) { rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); } return 0; } static int snd_rme32_capture_close(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme32->lock); rme32->capture_substream = NULL; rme32->capture_periodsize = 0; spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme32->lock); if (rme32->fullduplex_mode) { memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); } else { writel(0, rme32->iobase + RME32_IO_RESET_POS); } if (rme32->wcreg & RME32_WCR_SEL) rme32->wcreg &= ~RME32_WCR_MUTE; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme32->lock); if (rme32->fullduplex_mode) { memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); } else { writel(0, rme32->iobase + RME32_IO_RESET_POS); } spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; spin_lock(&rme32->lock); snd_pcm_group_for_each_entry(s, substream) { if (s != rme32->playback_substream && s != rme32->capture_substream) continue; switch (cmd) { case SNDRV_PCM_TRIGGER_START: rme32->running |= (1 << s->stream); if (rme32->fullduplex_mode) { /* remember the current DMA position */ if (s == rme32->playback_substream) { rme32->playback_pcm.hw_io = rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); } else { rme32->capture_pcm.hw_io = rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); } } break; case SNDRV_PCM_TRIGGER_STOP: rme32->running &= ~(1 << s->stream); break; } snd_pcm_trigger_done(s, substream); } switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (rme32->running && ! RME32_ISWORKING(rme32)) snd_rme32_pcm_start(rme32, 0); break; case SNDRV_PCM_TRIGGER_STOP: if (! rme32->running && RME32_ISWORKING(rme32)) snd_rme32_pcm_stop(rme32, 0); break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (rme32->running && RME32_ISWORKING(rme32)) snd_rme32_pcm_stop(rme32, 1); break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (rme32->running && ! RME32_ISWORKING(rme32)) snd_rme32_pcm_start(rme32, 1); break; } spin_unlock(&rme32->lock); return 0; } /* pointer callback for halfduplex mode */ static snd_pcm_uframes_t snd_rme32_playback_pointer(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; } static snd_pcm_uframes_t snd_rme32_capture_pointer(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; } /* ack and pointer callbacks for fullduplex mode */ static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, struct snd_pcm_indirect *rec, size_t bytes) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, substream->runtime->dma_area + rec->sw_data, bytes); } static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); struct snd_pcm_indirect *rec, *cprec; rec = &rme32->playback_pcm; cprec = &rme32->capture_pcm; spin_lock(&rme32->lock); rec->hw_queue_size = RME32_BUFFER_SIZE; if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) rec->hw_queue_size -= cprec->hw_ready; spin_unlock(&rme32->lock); return snd_pcm_indirect_playback_transfer(substream, rec, snd_rme32_pb_trans_copy); } static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, struct snd_pcm_indirect *rec, size_t bytes) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); memcpy_fromio(substream->runtime->dma_area + rec->sw_data, rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, bytes); } static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, snd_rme32_cp_trans_copy); } static snd_pcm_uframes_t snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, snd_rme32_pcm_byteptr(rme32)); } static snd_pcm_uframes_t snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) { struct rme32 *rme32 = snd_pcm_substream_chip(substream); return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, snd_rme32_pcm_byteptr(rme32)); } /* for halfduplex mode */ static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { .open = snd_rme32_playback_spdif_open, .close = snd_rme32_playback_close, .hw_params = snd_rme32_playback_hw_params, .prepare = snd_rme32_playback_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_playback_pointer, .copy = snd_rme32_playback_copy, .fill_silence = snd_rme32_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { .open = snd_rme32_capture_spdif_open, .close = snd_rme32_capture_close, .hw_params = snd_rme32_capture_hw_params, .prepare = snd_rme32_capture_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_capture_pointer, .copy = snd_rme32_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { .open = snd_rme32_playback_adat_open, .close = snd_rme32_playback_close, .hw_params = snd_rme32_playback_hw_params, .prepare = snd_rme32_playback_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_playback_pointer, .copy = snd_rme32_playback_copy, .fill_silence = snd_rme32_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { .open = snd_rme32_capture_adat_open, .close = snd_rme32_capture_close, .hw_params = snd_rme32_capture_hw_params, .prepare = snd_rme32_capture_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_capture_pointer, .copy = snd_rme32_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; /* for fullduplex mode */ static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { .open = snd_rme32_playback_spdif_open, .close = snd_rme32_playback_close, .hw_params = snd_rme32_playback_hw_params, .prepare = snd_rme32_playback_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_playback_fd_pointer, .ack = snd_rme32_playback_fd_ack, }; static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { .open = snd_rme32_capture_spdif_open, .close = snd_rme32_capture_close, .hw_params = snd_rme32_capture_hw_params, .prepare = snd_rme32_capture_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_capture_fd_pointer, .ack = snd_rme32_capture_fd_ack, }; static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { .open = snd_rme32_playback_adat_open, .close = snd_rme32_playback_close, .hw_params = snd_rme32_playback_hw_params, .prepare = snd_rme32_playback_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_playback_fd_pointer, .ack = snd_rme32_playback_fd_ack, }; static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { .open = snd_rme32_capture_adat_open, .close = snd_rme32_capture_close, .hw_params = snd_rme32_capture_hw_params, .prepare = snd_rme32_capture_prepare, .trigger = snd_rme32_pcm_trigger, .pointer = snd_rme32_capture_fd_pointer, .ack = snd_rme32_capture_fd_ack, }; static void snd_rme32_free(struct rme32 *rme32) { if (rme32->irq >= 0) snd_rme32_pcm_stop(rme32, 0); } static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) { struct rme32 *rme32 = (struct rme32 *) pcm->private_data; rme32->spdif_pcm = NULL; } static void snd_rme32_free_adat_pcm(struct snd_pcm *pcm) { struct rme32 *rme32 = (struct rme32 *) pcm->private_data; rme32->adat_pcm = NULL; } static int snd_rme32_create(struct rme32 *rme32) { struct pci_dev *pci = rme32->pci; int err; rme32->irq = -1; spin_lock_init(&rme32->lock); err = pcim_enable_device(pci); if (err < 0) return err; err = pci_request_regions(pci, "RME32"); if (err < 0) return err; rme32->port = pci_resource_start(rme32->pci, 0); rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE); if (!rme32->iobase) { dev_err(rme32->card->dev, "unable to remap memory region 0x%lx-0x%lx\n", rme32->port, rme32->port + RME32_IO_SIZE - 1); return -ENOMEM; } if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt, IRQF_SHARED, KBUILD_MODNAME, rme32)) { dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } rme32->irq = pci->irq; rme32->card->sync_irq = rme32->irq; /* read the card's revision number */ pci_read_config_byte(pci, 8, &rme32->rev); /* set up ALSA pcm device for S/PDIF */ err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm); if (err < 0) return err; rme32->spdif_pcm->private_data = rme32; rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); if (rme32->fullduplex_mode) { snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme32_playback_spdif_fd_ops); snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme32_capture_spdif_fd_ops); snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, NULL, 0, RME32_MID_BUFFER_SIZE); rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; } else { snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme32_playback_spdif_ops); snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme32_capture_spdif_ops); rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; } /* set up ALSA pcm device for ADAT */ if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { /* ADAT is not available on DIGI32 and DIGI32 Pro */ rme32->adat_pcm = NULL; } else { err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, 1, 1, &rme32->adat_pcm); if (err < 0) return err; rme32->adat_pcm->private_data = rme32; rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); if (rme32->fullduplex_mode) { snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme32_playback_adat_fd_ops); snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme32_capture_adat_fd_ops); snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, NULL, 0, RME32_MID_BUFFER_SIZE); rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; } else { snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme32_playback_adat_ops); snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme32_capture_adat_ops); rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; } } rme32->playback_periodsize = 0; rme32->capture_periodsize = 0; /* make sure playback/capture is stopped, if by some reason active */ snd_rme32_pcm_stop(rme32, 0); /* reset DAC */ snd_rme32_reset_dac(rme32); /* reset buffer pointer */ writel(0, rme32->iobase + RME32_IO_RESET_POS); /* set default values in registers */ rme32->wcreg = RME32_WCR_SEL | /* normal playback */ RME32_WCR_INP_0 | /* input select */ RME32_WCR_MUTE; /* muting on */ writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); /* init switch interface */ err = snd_rme32_create_switches(rme32->card, rme32); if (err < 0) return err; /* init proc interface */ snd_rme32_proc_init(rme32); rme32->capture_substream = NULL; rme32->playback_substream = NULL; return 0; } /* * proc interface */ static void snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) { int n; struct rme32 *rme32 = (struct rme32 *) entry->private_data; rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_iprintf(buffer, rme32->card->longname); snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); snd_iprintf(buffer, "\nGeneral settings\n"); if (rme32->fullduplex_mode) snd_iprintf(buffer, " Full-duplex mode\n"); else snd_iprintf(buffer, " Half-duplex mode\n"); if (RME32_PRO_WITH_8414(rme32)) { snd_iprintf(buffer, " receiver: CS8414\n"); } else { snd_iprintf(buffer, " receiver: CS8412\n"); } if (rme32->wcreg & RME32_WCR_MODE24) { snd_iprintf(buffer, " format: 24 bit"); } else { snd_iprintf(buffer, " format: 16 bit"); } if (rme32->wcreg & RME32_WCR_MONO) { snd_iprintf(buffer, ", Mono\n"); } else { snd_iprintf(buffer, ", Stereo\n"); } snd_iprintf(buffer, "\nInput settings\n"); switch (snd_rme32_getinputtype(rme32)) { case RME32_INPUT_OPTICAL: snd_iprintf(buffer, " input: optical"); break; case RME32_INPUT_COAXIAL: snd_iprintf(buffer, " input: coaxial"); break; case RME32_INPUT_INTERNAL: snd_iprintf(buffer, " input: internal"); break; case RME32_INPUT_XLR: snd_iprintf(buffer, " input: XLR"); break; } if (snd_rme32_capture_getrate(rme32, &n) < 0) { snd_iprintf(buffer, "\n sample rate: no valid signal\n"); } else { if (n) { snd_iprintf(buffer, " (8 channels)\n"); } else { snd_iprintf(buffer, " (2 channels)\n"); } snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme32_capture_getrate(rme32, &n)); } snd_iprintf(buffer, "\nOutput settings\n"); if (rme32->wcreg & RME32_WCR_SEL) { snd_iprintf(buffer, " output signal: normal playback"); } else { snd_iprintf(buffer, " output signal: same as input"); } if (rme32->wcreg & RME32_WCR_MUTE) { snd_iprintf(buffer, " (muted)\n"); } else { snd_iprintf(buffer, "\n"); } /* master output frequency */ if (! ((!(rme32->wcreg & RME32_WCR_FREQ_0)) && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme32_playback_getrate(rme32)); } if (rme32->rcreg & RME32_RCR_KMODE) { snd_iprintf(buffer, " sample clock source: AutoSync\n"); } else { snd_iprintf(buffer, " sample clock source: Internal\n"); } if (rme32->wcreg & RME32_WCR_PRO) { snd_iprintf(buffer, " format: AES/EBU (professional)\n"); } else { snd_iprintf(buffer, " format: IEC958 (consumer)\n"); } if (rme32->wcreg & RME32_WCR_EMP) { snd_iprintf(buffer, " emphasis: on\n"); } else { snd_iprintf(buffer, " emphasis: off\n"); } } static void snd_rme32_proc_init(struct rme32 *rme32) { snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); } /* * control interface */ #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info static int snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme32->lock); ucontrol->value.integer.value[0] = rme32->wcreg & RME32_WCR_SEL ? 0 : 1; spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; spin_lock_irq(&rme32->lock); val = (rme32->wcreg & ~RME32_WCR_SEL) | val; change = val != rme32->wcreg; if (ucontrol->value.integer.value[0]) val &= ~RME32_WCR_MUTE; else val |= RME32_WCR_MUTE; rme32->wcreg = val; writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); spin_unlock_irq(&rme32->lock); return change; } static int snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); static const char * const texts[4] = { "Optical", "Coaxial", "Internal", "XLR" }; int num_items; switch (rme32->pci->device) { case PCI_DEVICE_ID_RME_DIGI32: case PCI_DEVICE_ID_RME_DIGI32_8: num_items = 3; break; case PCI_DEVICE_ID_RME_DIGI32_PRO: num_items = 4; break; default: snd_BUG(); return -EINVAL; } return snd_ctl_enum_info(uinfo, 1, num_items, texts); } static int snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); unsigned int items = 3; spin_lock_irq(&rme32->lock); ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); switch (rme32->pci->device) { case PCI_DEVICE_ID_RME_DIGI32: case PCI_DEVICE_ID_RME_DIGI32_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI32_PRO: items = 4; break; default: snd_BUG(); break; } if (ucontrol->value.enumerated.item[0] >= items) { ucontrol->value.enumerated.item[0] = items - 1; } spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); unsigned int val; int change, items = 3; switch (rme32->pci->device) { case PCI_DEVICE_ID_RME_DIGI32: case PCI_DEVICE_ID_RME_DIGI32_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI32_PRO: items = 4; break; default: snd_BUG(); break; } val = ucontrol->value.enumerated.item[0] % items; spin_lock_irq(&rme32->lock); change = val != (unsigned int)snd_rme32_getinputtype(rme32); snd_rme32_setinputtype(rme32, val); spin_unlock_irq(&rme32->lock); return change; } static int snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[4] = { "AutoSync", "Internal 32.0kHz", "Internal 44.1kHz", "Internal 48.0kHz" }; return snd_ctl_enum_info(uinfo, 1, 4, texts); } static int snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme32->lock); ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); spin_unlock_irq(&rme32->lock); return 0; } static int snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 3; spin_lock_irq(&rme32->lock); change = val != (unsigned int)snd_rme32_getclockmode(rme32); snd_rme32_setclockmode(rme32, val); spin_unlock_irq(&rme32->lock); return change; } static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) { u32 val = 0; val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; if (val & RME32_WCR_PRO) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; else val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; return val; } static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) { aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); if (val & RME32_WCR_PRO) aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; else aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; } static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); snd_rme32_convert_to_aes(&ucontrol->value.iec958, rme32->wcreg_spdif); return 0; } static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme32->lock); change = val != rme32->wcreg_spdif; rme32->wcreg_spdif = val; spin_unlock_irq(&rme32->lock); return change; } static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value * ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); snd_rme32_convert_to_aes(&ucontrol->value.iec958, rme32->wcreg_spdif_stream); return 0; } static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value * ucontrol) { struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme32->lock); change = val != rme32->wcreg_spdif_stream; rme32->wcreg_spdif_stream = val; rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); rme32->wcreg |= val; writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); spin_unlock_irq(&rme32->lock); return change; } static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value * ucontrol) { ucontrol->value.iec958.status[0] = kcontrol->private_value; return 0; } static const struct snd_kcontrol_new snd_rme32_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), .info = snd_rme32_control_spdif_info, .get = snd_rme32_control_spdif_get, .put = snd_rme32_control_spdif_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), .info = snd_rme32_control_spdif_stream_info, .get = snd_rme32_control_spdif_stream_get, .put = snd_rme32_control_spdif_stream_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), .info = snd_rme32_control_spdif_mask_info, .get = snd_rme32_control_spdif_mask_get, .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), .info = snd_rme32_control_spdif_mask_info, .get = snd_rme32_control_spdif_mask_get, .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Input Connector", .info = snd_rme32_info_inputtype_control, .get = snd_rme32_get_inputtype_control, .put = snd_rme32_put_inputtype_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Loopback Input", .info = snd_rme32_info_loopback_control, .get = snd_rme32_get_loopback_control, .put = snd_rme32_put_loopback_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Sample Clock Source", .info = snd_rme32_info_clockmode_control, .get = snd_rme32_get_clockmode_control, .put = snd_rme32_put_clockmode_control } }; static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) { int idx, err; struct snd_kcontrol *kctl; for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32); err = snd_ctl_add(card, kctl); if (err < 0) return err; if (idx == 1) /* IEC958 (S/PDIF) Stream */ rme32->spdif_ctl = kctl; } return 0; } /* * Card initialisation */ static void snd_rme32_card_free(struct snd_card *card) { snd_rme32_free(card->private_data); } static int __snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct rme32 *rme32; struct snd_card *card; int err; if (dev >= SNDRV_CARDS) { return -ENODEV; } if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*rme32), &card); if (err < 0) return err; card->private_free = snd_rme32_card_free; rme32 = (struct rme32 *) card->private_data; rme32->card = card; rme32->pci = pci; if (fullduplex[dev]) rme32->fullduplex_mode = 1; err = snd_rme32_create(rme32); if (err < 0) return err; strcpy(card->driver, "Digi32"); switch (rme32->pci->device) { case PCI_DEVICE_ID_RME_DIGI32: strcpy(card->shortname, "RME Digi32"); break; case PCI_DEVICE_ID_RME_DIGI32_8: strcpy(card->shortname, "RME Digi32/8"); break; case PCI_DEVICE_ID_RME_DIGI32_PRO: strcpy(card->shortname, "RME Digi32 PRO"); break; } sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", card->shortname, rme32->rev, rme32->port, rme32->irq); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_rme32_probe(pci, pci_id)); } static struct pci_driver rme32_driver = { .name = KBUILD_MODNAME, .id_table = snd_rme32_ids, .probe = snd_rme32_probe, }; module_pci_driver(rme32_driver);
linux-master
sound/pci/rme32.c
#define CHIP1371 #include "ens1370.c"
linux-master
sound/pci/ens1371.c
// SPDX-License-Identifier: GPL-2.0-or-later /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de> * * Framework borrowed from Bart Hartgers's als4000.c. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). * Other versions are: * PCI168 A(W), sub ID 1800 * PCI168 A/AP, sub ID 8000 * Please give me feedback in case you try my driver with one of these!! * * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download * (XP/Vista do not support this card at all but every Linux distribution * has very good support out of the box; * just to make sure that the right people hit this and get to know that, * despite the high level of Internet ignorance - as usual :-P - * about very good support for this card - on Linux!) * * NOTES * Since Aztech does not provide any chipset documentation, * even on repeated request to various addresses, * and the answer that was finally given was negative * (and I was stupid enough to manage to get hold of a PCI168 soundcard * in the first place >:-P}), * I was forced to base this driver on reverse engineering * (3 weeks' worth of evenings filled with driver work). * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) * * It is quite likely that the AZF3328 chip is the PCI cousin of the * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. * * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, * Fincitec acquired by National Semiconductor in 2002, together with the * Fincitec-related company ARSmikro) has the following features: * * - compatibility & compliance: * - Microsoft PC 97 ("PC 97 Hardware Design Guide", * http://www.microsoft.com/whdc/archive/pcguides.mspx) * - Microsoft PC 98 Baseline Audio * - MPU401 UART * - Sound Blaster Emulation (DOS Box) * - builtin AC97 conformant codec (SNR over 80dB) * Note that "conformant" != "compliant"!! this chip's mixer register layout * *differs* from the standard AC97 layout: * they chose to not implement the headphone register (which is not a * problem since it's merely optional), yet when doing this, they committed * the grave sin of letting other registers follow immediately instead of * keeping a headphone dummy register, thereby shifting the mixer register * addresses illegally. So far unfortunately it looks like the very flexible * ALSA AC97 support is still not enough to easily compensate for such a * grave layout violation despite all tweaks and quirks mechanisms it offers. * Well, not quite: now ac97 layer is much improved (bus-specific ops!), * thus I was able to implement support - it's actually working quite well. * An interesting item might be Aztech AMR 2800-W, since it's an AC97 * modem card which might reveal the Aztech-specific codec ID which * we might want to pretend, too. Dito PCI168's brother, PCI368, * where the advertising datasheet says it's AC97-based and has a * Digital Enhanced Game Port. * - builtin genuine OPL3 - verified to work fine, 20080506 * - full duplex 16bit playback/record at independent sampling rate * - MPU401 (+ legacy address support, claimed by one official spec sheet) * FIXME: how to enable legacy addr?? * - game port (legacy address support) * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven * features supported). - See common term "Digital Enhanced Game Port"... * (probably DirectInput 3.0 spec - confirm) * - builtin 3D enhancement (said to be YAMAHA Ymersion) * - built-in General DirectX timer having a 20 bits counter * with 1us resolution (see below!) * - I2S serial output port for external DAC * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI * - supports hardware volume control * - single chip low cost solution (128 pin QFP) * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] * required for Microsoft's logo compliance (FIXME: where?) * At least the Trident 4D Wave DX has one bit somewhere * to enable writes to PCI subsystem VID registers, that should be it. * This might easily be in extended PCI reg space, since PCI168 also has * some custom data starting at 0x80. What kind of config settings * are located in our extended PCI space anyway?? * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms * [TDA1517P chip] * * Note that this driver now is actually *better* than the Windows driver, * since it additionally supports the card's 1MHz DirectX timer - just try * the following snd-seq module parameters etc.: * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 * - "timidity -iAv -B2,8 -Os -EFreverb=0" * - "pmidi -p 128:0 jazz.mid" * * OPL3 hardware playback testing, try something like: * cat /proc/asound/hwdep * and * aconnect -o * Then use * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 * where x,y is the xx-yy number as given in hwdep. * Then try * pmidi -p a:b jazz.mid * where a:b is the client number plus 0 usually, as given by aconnect above. * Oh, and make sure to unmute the FM mixer control (doh!) * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) * despite no CPU activity, possibly due to hindering ACPI idling somehow. * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. * Higher PCM / FM mixer levels seem to conflict (causes crackling), * at least sometimes. Maybe even use with hardware sequencer timer above :) * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. * * Certain PCI versions of this card are susceptible to DMA traffic underruns * in some systems (resulting in sound crackling/clicking/popping), * probably because they don't have a DMA FIFO buffer or so. * Overview (PCI ID/PCI subID/PCI rev.): * - no DMA crackling on SiS735: 0x50DC/0x1801/16 * - unknown performance: 0x50DC/0x1801/10 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) * * Crackling happens with VIA chipsets or, in my case, an SiS735, which is * supposed to be very fast and supposed to get rid of crackling much * better than a VIA, yet ironically I still get crackling, like many other * people with the same chipset. * Possible remedies: * - use speaker (amplifier) output instead of headphone output * (in case crackling is due to overloaded output clipping) * - plug card into a different PCI slot, preferably one that isn't shared * too much (this helps a lot, but not completely!) * - get rid of PCI VGA card, use AGP instead * - upgrade or downgrade BIOS * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) * Not too helpful. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS * * BUGS * - full-duplex might *still* be problematic, however a recent test was fine * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated * if you set PCM output switch to "pre 3D" instead of "post 3D". * If this can't be set, then get a mixer application that Isn't Stupid (tm) * (e.g. kmix, gamix) - unfortunately several are!! * - locking is not entirely clean, especially the audio stream activity * ints --> may be racy * - an _unconnected_ secondary joystick at the gameport will be reported * to be "active" (floating values, not precisely -1) due to the way we need * to read the Digital Enhanced Game Port. Not sure whether it is fixable. * * TODO * - use PCI_VDEVICE * - verify driver status on x86_64 * - test multi-card driver operation * - (ab)use 1MHz DirectX timer as kernel clocksource * - test MPU401 MIDI playback etc. * - add more power micro-management (disable various units of the card * as long as they're unused, to improve audio quality and save power). * However this requires more I/O ports which I haven't figured out yet * and which thus might not even exist... * The standard suspend/resume functionality could probably make use of * some improvement, too... * - figure out what all unknown port bits are responsible for * - figure out some cleverly evil scheme to possibly make ALSA AC97 code * fully accept our quite incompatible ""AC97"" mixer and thus save some * code (but I'm not too optimistic that doing this is possible at all) * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. */ #include <linux/io.h> #include <linux/init.h> #include <linux/bug.h> /* WARN_ONCE */ #include <linux/pci.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/gameport.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <sound/core.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/rawmidi.h> #include <sound/mpu401.h> #include <sound/opl3.h> #include <sound/initval.h> /* * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap. * If the AC97 compatibility parts we needed to implement locally turn out * to work nicely, then remove the old implementation eventually. */ #define AZF_USE_AC97_LAYER 1 #ifdef AZF_USE_AC97_LAYER #include <sound/ac97_codec.h> #endif #include "azt3328.h" MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); MODULE_LICENSE("GPL"); #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_GAMEPORT 1 #endif /* === Debug settings === Further diagnostic functionality than the settings below does not need to be provided, since one can easily write a POSIX shell script to dump the card's I/O ports (those listed in lspci -v -v): dump() { local descr=$1; local addr=$2; local count=$3 echo "${descr}: ${count} @ ${addr}:" dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ 2>/dev/null| hexdump -C } and then use something like "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", possibly within a "while true; do ... sleep 1; done" loop. Tweaking ports could be done using VALSTRING="`printf "%02x" $value`" printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ 2>/dev/null */ static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); static int seqtimer_scaling = 128; module_param(seqtimer_scaling, int, 0444); MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); enum snd_azf3328_codec_type { /* warning: fixed indices (also used for bitmask checks!) */ AZF_CODEC_PLAYBACK = 0, AZF_CODEC_CAPTURE = 1, AZF_CODEC_I2S_OUT = 2, }; struct snd_azf3328_codec_data { unsigned long io_base; /* keep first! (avoid offset calc) */ unsigned int dma_base; /* helper to avoid an indirection in hotpath */ spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ struct snd_pcm_substream *substream; bool running; enum snd_azf3328_codec_type type; const char *name; }; struct snd_azf3328 { /* often-used fields towards beginning, then grouped */ unsigned long ctrl_io; /* usually 0xb000, size 128 */ unsigned long game_io; /* usually 0xb400, size 8 */ unsigned long mpu_io; /* usually 0xb800, size 4 */ unsigned long opl3_io; /* usually 0xbc00, size 8 */ unsigned long mixer_io; /* usually 0xc000, size 64 */ spinlock_t reg_lock; struct snd_timer *timer; struct snd_pcm *pcm[3]; /* playback, recording and I2S out codecs */ struct snd_azf3328_codec_data codecs[3]; #ifdef AZF_USE_AC97_LAYER struct snd_ac97 *ac97; #endif struct snd_card *card; struct snd_rawmidi *rmidi; #ifdef SUPPORT_GAMEPORT struct gameport *gameport; u16 axes[4]; #endif struct pci_dev *pci; int irq; /* register 0x6a is write-only, thus need to remember setting. * If we need to add more registers here, then we might try to fold this * into some transparent combined shadow register handling with * CONFIG_PM register storage below, but that's slightly difficult. */ u16 shadow_reg_ctrl_6AH; #ifdef CONFIG_PM_SLEEP /* register value containers for power management * Note: not always full I/O range preserved (similar to Win driver!) */ u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; #endif }; static const struct pci_device_id snd_azf3328_ids[] = { { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); static int snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) { /* Well, strictly spoken, the inb/outb sequence isn't atomic and would need locking. However we currently don't care since it potentially complicates matters. */ u8 prev = inb(reg), new; new = (do_set) ? (prev|mask) : (prev & ~mask); /* we need to always write the new value no matter whether it differs * or not, since some register bits don't indicate their setting */ outb(new, reg); if (new != prev) return 1; return 0; } static inline void snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, unsigned reg, u8 value ) { outb(value, codec->io_base + reg); } static inline u8 snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) { return inb(codec->io_base + reg); } static inline void snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, unsigned reg, u16 value ) { outw(value, codec->io_base + reg); } static inline u16 snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) { return inw(codec->io_base + reg); } static inline void snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec, unsigned reg, const void *buffer, int count ) { unsigned long addr = codec->io_base + reg; if (count) { const u32 *buf = buffer; do { outl(*buf++, addr); addr += 4; } while (--count); } } static inline u32 snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) { return inl(codec->io_base + reg); } static inline void snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) { outb(value, chip->ctrl_io + reg); } static inline u8 snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) { return inb(chip->ctrl_io + reg); } static inline u16 snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) { return inw(chip->ctrl_io + reg); } static inline void snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) { outw(value, chip->ctrl_io + reg); } static inline void snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) { outl(value, chip->ctrl_io + reg); } static inline void snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) { outb(value, chip->game_io + reg); } static inline void snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) { outw(value, chip->game_io + reg); } static inline u8 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) { return inb(chip->game_io + reg); } static inline u16 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) { return inw(chip->game_io + reg); } static inline void snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) { outw(value, chip->mixer_io + reg); } static inline u16 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) { return inw(chip->mixer_io + reg); } #define AZF_MUTE_BIT 0x80 static bool snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip, unsigned reg, bool do_mute ) { unsigned long portbase = chip->mixer_io + reg + 1; bool updated; /* the mute bit is on the *second* (i.e. right) register of a * left/right channel setting */ updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); /* indicate whether it was muted before */ return (do_mute) ? !updated : updated; } static inline bool snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip, bool do_mute ) { return snd_azf3328_mixer_mute_control( chip, IDX_MIXER_PLAY_MASTER, do_mute ); } static inline bool snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip, bool do_mute ) { return snd_azf3328_mixer_mute_control( chip, IDX_MIXER_WAVEOUT, do_mute ); } static inline void snd_azf3328_mixer_reset(const struct snd_azf3328 *chip) { /* reset (close) mixer: * first mute master volume, then reset */ snd_azf3328_mixer_mute_control_master(chip, 1); snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); } #ifdef AZF_USE_AC97_LAYER static inline void snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip, unsigned short reg, const char *mode) { /* need to add some more or less clever emulation? */ dev_warn(chip->card->dev, "missing %s emulation for AC97 register 0x%02x!\n", mode, reg); } /* * Need to have _special_ AC97 mixer hardware register index mapper, * to compensate for the issue of a rather AC97-incompatible hardware layout. */ #define AZF_REG_MASK 0x3f #define AZF_AC97_REG_UNSUPPORTED 0x8000 #define AZF_AC97_REG_REAL_IO_READ 0x4000 #define AZF_AC97_REG_REAL_IO_WRITE 0x2000 #define AZF_AC97_REG_REAL_IO_RW \ (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE) #define AZF_AC97_REG_EMU_IO_READ 0x0400 #define AZF_AC97_REG_EMU_IO_WRITE 0x0200 #define AZF_AC97_REG_EMU_IO_RW \ (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE) static unsigned short snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) { static const struct { unsigned short azf_reg; } azf_reg_mapper[] = { /* Especially when taking into consideration * mono/stereo-based sequence of azf vs. AC97 control series, * it's quite obvious that azf simply got rid * of the AC97_HEADPHONE control at its intended offset, * thus shifted _all_ controls by one, * and _then_ simply added it as an FMSYNTH control at the end, * to make up for the offset. * This means we'll have to translate indices here as * needed and then do some tiny AC97 patch action * (snd_ac97_rename_vol_ctl() etc.) - that's it. */ { /* AC97_RESET */ IDX_MIXER_RESET | AZF_AC97_REG_REAL_IO_WRITE | AZF_AC97_REG_EMU_IO_READ }, { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER }, /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */ { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH }, { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT }, { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE }, { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP }, { /* AC97_PHONE */ IDX_MIXER_MODEMIN }, { /* AC97_MIC */ IDX_MIXER_MIC }, { /* AC97_LINE */ IDX_MIXER_LINEIN }, { /* AC97_CD */ IDX_MIXER_CDAUDIO }, { /* AC97_VIDEO */ IDX_MIXER_VIDEO }, { /* AC97_AUX */ IDX_MIXER_AUX }, { /* AC97_PCM */ IDX_MIXER_WAVEOUT }, { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT }, { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME }, { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW }, { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 }, { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 }, }; unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED; /* azf3328 supports the low-numbered and low-spec:ed range of AC97 regs only */ if (reg <= AC97_3D_CONTROL) { unsigned short reg_idx = reg / 2; reg_azf = azf_reg_mapper[reg_idx].azf_reg; /* a translation-only entry means it's real read/write: */ if (!(reg_azf & ~AZF_REG_MASK)) reg_azf |= AZF_AC97_REG_REAL_IO_RW; } else { switch (reg) { case AC97_POWERDOWN: reg_azf = AZF_AC97_REG_EMU_IO_RW; break; case AC97_EXTENDED_ID: reg_azf = AZF_AC97_REG_EMU_IO_READ; break; case AC97_EXTENDED_STATUS: /* I don't know what the h*ll AC97 layer * would consult this _extended_ register for * given a base-AC97-advertised card, * but let's just emulate it anyway :-P */ reg_azf = AZF_AC97_REG_EMU_IO_RW; break; case AC97_VENDOR_ID1: case AC97_VENDOR_ID2: reg_azf = AZF_AC97_REG_EMU_IO_READ; break; } } return reg_azf; } static const unsigned short azf_emulated_ac97_caps = AC97_BC_DEDICATED_MIC | AC97_BC_BASS_TREBLE | /* Headphone is an FM Synth control here */ AC97_BC_HEADPHONE | /* no AC97_BC_LOUDNESS! */ /* mask 0x7c00 is vendor-specific 3D enhancement vendor indicator. Since there actually _is_ an entry for Aztech Labs (13), make damn sure to indicate it. */ (13 << 10); static const unsigned short azf_emulated_ac97_powerdown = /* pretend everything to be active */ AC97_PD_ADC_STATUS | AC97_PD_DAC_STATUS | AC97_PD_MIXER_STATUS | AC97_PD_VREF_STATUS; /* * Emulated, _inofficial_ vendor ID * (there might be some devices such as the MR 2800-W * which could reveal the real Aztech AC97 ID). * We choose to use "AZT" prefix, and then use 1 to indicate PCI168 * (better don't use 0x68 since there's a PCI368 as well). */ static const unsigned int azf_emulated_ac97_vendor_id = 0x415a5401; static unsigned short snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97) { const struct snd_azf3328 *chip = ac97->private_data; unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); unsigned short reg_val = 0; bool unsupported = false; dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n", reg_ac97); if (reg_azf & AZF_AC97_REG_UNSUPPORTED) unsupported = true; else { if (reg_azf & AZF_AC97_REG_REAL_IO_READ) reg_val = snd_azf3328_mixer_inw(chip, reg_azf & AZF_REG_MASK); else { /* * Proceed with dummy I/O read, * to ensure compatible timing where this may matter. * (ALSA AC97 layer usually doesn't call I/O functions * due to intelligent I/O caching anyway) * Choose a mixer register that's thoroughly unrelated * to common audio (try to minimize distortion). */ snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H); } if (reg_azf & AZF_AC97_REG_EMU_IO_READ) { switch (reg_ac97) { case AC97_RESET: reg_val |= azf_emulated_ac97_caps; break; case AC97_POWERDOWN: reg_val |= azf_emulated_ac97_powerdown; break; case AC97_EXTENDED_ID: case AC97_EXTENDED_STATUS: /* AFAICS we simply can't support anything: */ reg_val |= 0; break; case AC97_VENDOR_ID1: reg_val = azf_emulated_ac97_vendor_id >> 16; break; case AC97_VENDOR_ID2: reg_val = azf_emulated_ac97_vendor_id & 0xffff; break; default: unsupported = true; break; } } } if (unsupported) snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read"); return reg_val; } static void snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97, unsigned short reg_ac97, unsigned short val) { const struct snd_azf3328 *chip = ac97->private_data; unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); bool unsupported = false; dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n", reg_ac97, val); if (reg_azf & AZF_AC97_REG_UNSUPPORTED) unsupported = true; else { if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE) snd_azf3328_mixer_outw( chip, reg_azf & AZF_REG_MASK, val ); else if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) { switch (reg_ac97) { case AC97_REC_GAIN_MIC: case AC97_POWERDOWN: case AC97_EXTENDED_STATUS: /* * Silently swallow these writes. * Since for most registers our card doesn't * actually support a comparable feature, * this is exactly what we should do here. * The AC97 layer's I/O caching probably * automatically takes care of all the rest... * (remembers written values etc.) */ break; default: unsupported = true; break; } } } if (unsupported) snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write"); } static int snd_azf3328_mixer_new(struct snd_azf3328 *chip) { struct snd_ac97_bus *bus; struct snd_ac97_template ac97; static const struct snd_ac97_bus_ops ops = { .write = snd_azf3328_mixer_ac97_write, .read = snd_azf3328_mixer_ac97_read, }; int rc; memset(&ac97, 0, sizeof(ac97)); ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_AUDIO /* we support audio! */ | AC97_SCAP_NO_SPDIF; ac97.private_data = chip; ac97.pci = chip->pci; /* * ALSA's AC97 layer has terrible init crackling issues, * unfortunately, and since it makes use of AC97_RESET, * there's no use trying to mute Master Playback proactively. */ rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus); if (!rc) rc = snd_ac97_mixer(bus, &ac97, &chip->ac97); /* * Make sure to complain loudly in case of AC97 init failure, * since failure may happen quite often, * due to this card being a very quirky AC97 "lookalike". */ if (rc) dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc); /* If we return an error here, then snd_card_free() should * free up any ac97 codecs that got created, as well as the bus. */ return rc; } #else /* AZF_USE_AC97_LAYER */ static void snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, unsigned reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay ) { unsigned long portbase = chip->mixer_io + reg; unsigned char curr_vol_left = 0, curr_vol_right = 0; int left_change = 0, right_change = 0; if (chan_sel & SET_CHAN_LEFT) { curr_vol_left = inb(portbase + 1); /* take care of muting flag contained in left channel */ if (curr_vol_left & AZF_MUTE_BIT) dst_vol_left |= AZF_MUTE_BIT; else dst_vol_left &= ~AZF_MUTE_BIT; left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; } if (chan_sel & SET_CHAN_RIGHT) { curr_vol_right = inb(portbase + 0); right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; } do { if (left_change) { if (curr_vol_left != dst_vol_left) { curr_vol_left += left_change; outb(curr_vol_left, portbase + 1); } else left_change = 0; } if (right_change) { if (curr_vol_right != dst_vol_right) { curr_vol_right += right_change; /* during volume change, the right channel is crackling * somewhat more than the left channel, unfortunately. * This seems to be a hardware issue. */ outb(curr_vol_right, portbase + 0); } else right_change = 0; } if (delay) mdelay(delay); } while ((left_change) || (right_change)); } /* * general mixer element */ struct azf3328_mixer_reg { unsigned reg; unsigned int lchan_shift, rchan_shift; unsigned int mask; unsigned int invert: 1; unsigned int stereo: 1; unsigned int enum_c: 4; }; #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ (mask << 16) | \ (invert << 24) | \ (stereo << 25) | \ (enum_c << 26)) static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) { r->reg = val & 0xff; r->lchan_shift = (val >> 8) & 0x0f; r->rchan_shift = (val >> 12) & 0x0f; r->mask = (val >> 16) & 0xff; r->invert = (val >> 24) & 1; r->stereo = (val >> 25) & 1; r->enum_c = (val >> 26) & 0x0f; } /* * mixer switches/volumes */ #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_azf3328_info_mixer, \ .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ } #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_azf3328_info_mixer, \ .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ } #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_azf3328_info_mixer, \ .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ } #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_azf3328_info_mixer, \ .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ } #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_azf3328_info_mixer_enum, \ .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ } static int snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct azf3328_mixer_reg reg; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = reg.stereo + 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = reg.mask; return 0; } static int snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); struct azf3328_mixer_reg reg; u16 oreg, val; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); oreg = snd_azf3328_mixer_inw(chip, reg.reg); val = (oreg >> reg.lchan_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[0] = val; if (reg.stereo) { val = (oreg >> reg.rchan_shift) & reg.mask; if (reg.invert) val = reg.mask - val; ucontrol->value.integer.value[1] = val; } dev_dbg(chip->card->dev, "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", reg.reg, oreg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); return 0; } static int snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); struct azf3328_mixer_reg reg; u16 oreg, nreg, val; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); oreg = snd_azf3328_mixer_inw(chip, reg.reg); val = ucontrol->value.integer.value[0] & reg.mask; if (reg.invert) val = reg.mask - val; nreg = oreg & ~(reg.mask << reg.lchan_shift); nreg |= (val << reg.lchan_shift); if (reg.stereo) { val = ucontrol->value.integer.value[1] & reg.mask; if (reg.invert) val = reg.mask - val; nreg &= ~(reg.mask << reg.rchan_shift); nreg |= (val << reg.rchan_shift); } if (reg.mask >= 0x07) /* it's a volume control, so better take care */ snd_azf3328_mixer_write_volume_gradually( chip, reg.reg, nreg >> 8, nreg & 0xff, /* just set both channels, doesn't matter */ SET_CHAN_LEFT|SET_CHAN_RIGHT, 0); else snd_azf3328_mixer_outw(chip, reg.reg, nreg); dev_dbg(chip->card->dev, "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], oreg, reg.lchan_shift, reg.rchan_shift, nreg, snd_azf3328_mixer_inw(chip, reg.reg)); return (nreg != oreg); } static int snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts1[] = { "Mic1", "Mic2" }; static const char * const texts2[] = { "Mix", "Mic" }; static const char * const texts3[] = { "Mic", "CD", "Video", "Aux", "Line", "Mix", "Mix Mono", "Phone" }; static const char * const texts4[] = { "pre 3D", "post 3D" }; struct azf3328_mixer_reg reg; const char * const *p = NULL; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); if (reg.reg == IDX_MIXER_ADVCTL2) { switch(reg.lchan_shift) { case 8: /* modem out sel */ p = texts1; break; case 9: /* mono sel source */ p = texts2; break; case 15: /* PCM Out Path */ p = texts4; break; } } else if (reg.reg == IDX_MIXER_REC_SELECT) p = texts3; return snd_ctl_enum_info(uinfo, (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, reg.enum_c, p); } static int snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); struct azf3328_mixer_reg reg; unsigned short val; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); val = snd_azf3328_mixer_inw(chip, reg.reg); if (reg.reg == IDX_MIXER_REC_SELECT) { ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); } else ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); dev_dbg(chip->card->dev, "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], reg.lchan_shift, reg.enum_c); return 0; } static int snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); struct azf3328_mixer_reg reg; u16 oreg, nreg, val; snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value); oreg = snd_azf3328_mixer_inw(chip, reg.reg); val = oreg; if (reg.reg == IDX_MIXER_REC_SELECT) { if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) return -EINVAL; val = (ucontrol->value.enumerated.item[0] << 8) | (ucontrol->value.enumerated.item[1] << 0); } else { if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) return -EINVAL; val &= ~((reg.enum_c - 1) << reg.lchan_shift); val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); } snd_azf3328_mixer_outw(chip, reg.reg, val); nreg = val; dev_dbg(chip->card->dev, "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); return (nreg != oreg); } static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = { AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1), AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1), AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ #if MIXER_TESTING AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), #endif }; static const u16 snd_azf3328_init_values[][2] = { { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_BASSTREBLE, 0x0000 }, { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, }; static int snd_azf3328_mixer_new(struct snd_azf3328 *chip) { struct snd_card *card; const struct snd_kcontrol_new *sw; unsigned int idx; int err; if (snd_BUG_ON(!chip || !chip->card)) return -EINVAL; card = chip->card; /* mixer reset */ snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); /* mute and zero volume channels */ for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { snd_azf3328_mixer_outw(chip, snd_azf3328_init_values[idx][0], snd_azf3328_init_values[idx][1]); } /* add mixer controls */ sw = snd_azf3328_mixer_controls; for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); ++idx, ++sw) { err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip)); if (err < 0) return err; } snd_component_add(card, "AZF3328 mixer"); strcpy(card->mixername, "AZF3328 mixer"); return 0; } #endif /* AZF_USE_AC97_LAYER */ static void snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, enum azf_freq_t bitrate, unsigned int format_width, unsigned int channels ) { unsigned long flags; u16 val = 0xff00; u8 freq = 0; switch (bitrate) { case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break; case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break; case AZF_FREQ_5512: /* the AZF3328 names it "5510" for some strange reason */ freq = SOUNDFORMAT_FREQ_5510; break; case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break; case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break; case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break; case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break; case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break; case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break; case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break; case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break; default: snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); fallthrough; case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break; case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break; case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break; } /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ val |= freq; if (channels == 2) val |= SOUNDFORMAT_FLAG_2CHANNELS; if (format_width == 16) val |= SOUNDFORMAT_FLAG_16BIT; spin_lock_irqsave(codec->lock, flags); /* set bitrate/format */ snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); /* changing the bitrate/format settings switches off the * audio output with an annoying click in case of 8/16bit format change * (maybe shutting down DAC/ADC?), thus immediately * do some tweaking to reenable it and get rid of the clicking * (FIXME: yes, it works, but what exactly am I doing here?? :) * FIXME: does this have some side effects for full-duplex * or other dramatic side effects? */ /* do it for non-capture codecs only */ if (codec->type != AZF_CODEC_CAPTURE) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2 | SOMETHING_ALMOST_ALWAYS_SET | DMA_EPILOGUE_SOMETHING | DMA_SOMETHING_ELSE ); spin_unlock_irqrestore(codec->lock, flags); } static inline void snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec ) { /* choose lowest frequency for low power consumption. * While this will cause louder noise due to rather coarse frequency, * it should never matter since output should always * get disabled properly when idle anyway. */ snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); } static void snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, unsigned bitmask, bool enable ) { bool do_mask = !enable; if (do_mask) chip->shadow_reg_ctrl_6AH |= bitmask; else chip->shadow_reg_ctrl_6AH &= ~bitmask; dev_dbg(chip->card->dev, "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", bitmask, do_mask, chip->shadow_reg_ctrl_6AH); snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); } static inline void snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) { dev_dbg(chip->card->dev, "codec_enable %d\n", enable); /* no idea what exactly is being done here, but I strongly assume it's * PM related */ snd_azf3328_ctrl_reg_6AH_update( chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable ); } static void snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, enum snd_azf3328_codec_type codec_type, bool enable ) { struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; bool need_change = (codec->running != enable); dev_dbg(chip->card->dev, "codec_activity: %s codec, enable %d, need_change %d\n", codec->name, enable, need_change ); if (need_change) { static const struct { enum snd_azf3328_codec_type other1; enum snd_azf3328_codec_type other2; } peer_codecs[3] = { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; bool call_function; if (enable) /* if enable codec, call enable_codecs func to enable codec supply... */ call_function = 1; else { /* ...otherwise call enable_codecs func (which globally shuts down operation of codecs) only in case the other codecs are currently not active either! */ call_function = ((!chip->codecs[peer_codecs[codec_type].other1] .running) && (!chip->codecs[peer_codecs[codec_type].other2] .running)); } if (call_function) snd_azf3328_ctrl_enable_codecs(chip, enable); /* ...and adjust clock, too * (reduce noise and power consumption) */ if (!enable) snd_azf3328_codec_setfmt_lowpower(codec); codec->running = enable; } } static void snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip, struct snd_azf3328_codec_data *codec, unsigned long addr, unsigned int period_bytes, unsigned int buffer_bytes ) { WARN_ONCE(period_bytes & 1, "odd period length!?\n"); WARN_ONCE(buffer_bytes != 2 * period_bytes, "missed our input expectations! %u vs. %u\n", buffer_bytes, period_bytes); if (!codec->running) { /* AZF3328 uses a two buffer pointer DMA transfer approach */ unsigned long flags; /* width 32bit (prevent overflow): */ u32 area_length; struct codec_setup_io { u32 dma_start_1; u32 dma_start_2; u32 dma_lengths; } __attribute__((packed)) setup_io; area_length = buffer_bytes/2; setup_io.dma_start_1 = addr; setup_io.dma_start_2 = addr+area_length; dev_dbg(chip->card->dev, "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n", setup_io.dma_start_1, area_length, setup_io.dma_start_2, area_length, period_bytes, buffer_bytes); /* Hmm, are we really supposed to decrement this by 1?? Most definitely certainly not: configuring full length does work properly (i.e. likely better), and BTW we violated possibly differing frame sizes with this... area_length--; |* max. index *| */ /* build combined I/O buffer length word */ setup_io.dma_lengths = (area_length << 16) | (area_length); spin_lock_irqsave(codec->lock, flags); snd_azf3328_codec_outl_multi( codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3 ); spin_unlock_irqrestore(codec->lock, flags); } } static int snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_azf3328_codec_data *codec = runtime->private_data; #if 0 unsigned int size = snd_pcm_lib_buffer_bytes(substream); unsigned int count = snd_pcm_lib_period_bytes(substream); #endif codec->dma_base = runtime->dma_addr; #if 0 snd_azf3328_codec_setfmt(codec, runtime->rate, snd_pcm_format_width(runtime->format), runtime->channels); snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, count, size); #endif return 0; } static int snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_azf3328_codec_data *codec = runtime->private_data; int result = 0; u16 flags1; bool previously_muted = false; bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); switch (cmd) { case SNDRV_PCM_TRIGGER_START: dev_dbg(chip->card->dev, "START PCM %s\n", codec->name); if (is_main_mixer_playback_codec) { /* mute WaveOut (avoid clicking during setup) */ previously_muted = snd_azf3328_mixer_mute_control_pcm( chip, 1 ); } snd_azf3328_codec_setfmt(codec, runtime->rate, snd_pcm_format_width(runtime->format), runtime->channels); spin_lock(codec->lock); /* first, remember current value: */ flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); /* stop transfer */ flags1 &= ~DMA_RESUME; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); /* FIXME: clear interrupts or what??? */ snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); spin_unlock(codec->lock); snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, snd_pcm_lib_period_bytes(substream), snd_pcm_lib_buffer_bytes(substream) ); spin_lock(codec->lock); #ifdef WIN9X /* FIXME: enable playback/recording??? */ flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); /* start transfer again */ /* FIXME: what is this value (0x0010)??? */ flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); #else /* NT4 */ snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 0x0000); snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, DMA_RUN_SOMETHING1); snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2); snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, DMA_RESUME | SOMETHING_ALMOST_ALWAYS_SET | DMA_EPILOGUE_SOMETHING | DMA_SOMETHING_ELSE); #endif spin_unlock(codec->lock); snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); if (is_main_mixer_playback_codec) { /* now unmute WaveOut */ if (!previously_muted) snd_azf3328_mixer_mute_control_pcm( chip, 0 ); } dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name); break; case SNDRV_PCM_TRIGGER_RESUME: dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name); /* resume codec if we were active */ spin_lock(codec->lock); if (codec->running) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, snd_azf3328_codec_inw( codec, IDX_IO_CODEC_DMA_FLAGS ) | DMA_RESUME ); spin_unlock(codec->lock); break; case SNDRV_PCM_TRIGGER_STOP: dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name); if (is_main_mixer_playback_codec) { /* mute WaveOut (avoid clicking during setup) */ previously_muted = snd_azf3328_mixer_mute_control_pcm( chip, 1 ); } spin_lock(codec->lock); /* first, remember current value: */ flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); /* stop transfer */ flags1 &= ~DMA_RESUME; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); /* hmm, is this really required? we're resetting the same bit * immediately thereafter... */ flags1 |= DMA_RUN_SOMETHING1; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); flags1 &= ~DMA_RUN_SOMETHING1; snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); spin_unlock(codec->lock); snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); if (is_main_mixer_playback_codec) { /* now unmute WaveOut */ if (!previously_muted) snd_azf3328_mixer_mute_control_pcm( chip, 0 ); } dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name); break; case SNDRV_PCM_TRIGGER_SUSPEND: dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name); /* make sure codec is stopped */ snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, snd_azf3328_codec_inw( codec, IDX_IO_CODEC_DMA_FLAGS ) & ~DMA_RESUME ); break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); break; default: WARN(1, "FIXME: unknown trigger mode!\n"); return -EINVAL; } return result; } static snd_pcm_uframes_t snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream ) { const struct snd_azf3328_codec_data *codec = substream->runtime->private_data; unsigned long result; snd_pcm_uframes_t frmres; result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); /* calculate offset */ #ifdef QUERY_HARDWARE result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); #else result -= codec->dma_base; #endif frmres = bytes_to_frames( substream->runtime, result); dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n", jiffies, codec->name, result, frmres); return frmres; } /******************************************************************/ #ifdef SUPPORT_GAMEPORT static inline void snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, bool enable ) { snd_azf3328_io_reg_setb( chip->game_io+IDX_GAME_HWCONFIG, GAME_HWCFG_IRQ_ENABLE, enable ); } static inline void snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, bool enable ) { snd_azf3328_io_reg_setb( chip->game_io+IDX_GAME_HWCONFIG, GAME_HWCFG_LEGACY_ADDRESS_ENABLE, enable ); } static void snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, unsigned int freq_cfg ) { snd_azf3328_io_reg_setb( chip->game_io+IDX_GAME_HWCONFIG, 0x02, (freq_cfg & 1) != 0 ); snd_azf3328_io_reg_setb( chip->game_io+IDX_GAME_HWCONFIG, 0x04, (freq_cfg & 2) != 0 ); } static inline void snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) { snd_azf3328_ctrl_reg_6AH_update( chip, IO_6A_SOMETHING2_GAMEPORT, enable ); } static inline void snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) { /* * skeleton handler only * (we do not want axis reading in interrupt handler - too much load!) */ dev_dbg(chip->card->dev, "gameport irq\n"); /* this should ACK the gameport IRQ properly, hopefully. */ snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); } static int snd_azf3328_gameport_open(struct gameport *gameport, int mode) { struct snd_azf3328 *chip = gameport_get_port_data(gameport); int res; dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode); switch (mode) { case GAMEPORT_MODE_COOKED: case GAMEPORT_MODE_RAW: res = 0; break; default: res = -1; break; } snd_azf3328_gameport_set_counter_frequency(chip, GAME_HWCFG_ADC_COUNTER_FREQ_STD); snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); return res; } static void snd_azf3328_gameport_close(struct gameport *gameport) { struct snd_azf3328 *chip = gameport_get_port_data(gameport); dev_dbg(chip->card->dev, "gameport_close\n"); snd_azf3328_gameport_set_counter_frequency(chip, GAME_HWCFG_ADC_COUNTER_FREQ_1_200); snd_azf3328_gameport_axis_circuit_enable(chip, 0); } static int snd_azf3328_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons ) { struct snd_azf3328 *chip = gameport_get_port_data(gameport); int i; u8 val; unsigned long flags; if (snd_BUG_ON(!chip)) return 0; spin_lock_irqsave(&chip->reg_lock, flags); val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); *buttons = (~(val) >> 4) & 0xf; /* ok, this one is a bit dirty: cooked_read is being polled by a timer, * thus we're atomic and cannot actively wait in here * (which would be useful for us since it probably would be better * to trigger a measurement in here, then wait a short amount of * time until it's finished, then read values of _this_ measurement). * * Thus we simply resort to reading values if they're available already * and trigger the next measurement. */ val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); if (val & GAME_AXES_SAMPLING_READY) { for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { /* configure the axis to read */ val = (i << 4) | 0x0f; snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); chip->axes[i] = snd_azf3328_game_inw( chip, IDX_GAME_AXIS_VALUE ); } } /* trigger next sampling of axes, to be evaluated the next time we * enter this function */ /* for some very, very strange reason we cannot enable * Measurement Ready monitoring for all axes here, * at least not when only one joystick connected */ val = 0x03; /* we're able to monitor axes 1 and 2 only */ snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); spin_unlock_irqrestore(&chip->reg_lock, flags); for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { axes[i] = chip->axes[i]; if (axes[i] == 0xffff) axes[i] = -1; } dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n", axes[0], axes[1], axes[2], axes[3], *buttons); return 0; } static int snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { struct gameport *gp; chip->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(chip->card->dev, "cannot alloc memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "AZF3328 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); gameport_set_dev_parent(gp, &chip->pci->dev); gp->io = chip->game_io; gameport_set_port_data(gp, chip); gp->open = snd_azf3328_gameport_open; gp->close = snd_azf3328_gameport_close; gp->fuzz = 16; /* seems ok */ gp->cooked_read = snd_azf3328_gameport_cooked_read; /* DISABLE legacy address: we don't need it! */ snd_azf3328_gameport_legacy_address_enable(chip, 0); snd_azf3328_gameport_set_counter_frequency(chip, GAME_HWCFG_ADC_COUNTER_FREQ_1_200); snd_azf3328_gameport_axis_circuit_enable(chip, 0); gameport_register_port(chip->gameport); return 0; } static void snd_azf3328_gameport_free(struct snd_azf3328 *chip) { if (chip->gameport) { gameport_unregister_port(chip->gameport); chip->gameport = NULL; } snd_azf3328_gameport_irq_enable(chip, 0); } #else static inline int snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } static inline void snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } static inline void snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) { dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n"); } #endif /* SUPPORT_GAMEPORT */ /******************************************************************/ static inline void snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which) { dev_dbg(chip->card->dev, "unknown IRQ type (%x) occurred, please report!\n", which); } static inline void snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip, const struct snd_azf3328_codec_data *first_codec, u8 status ) { u8 which; enum snd_azf3328_codec_type codec_type; const struct snd_azf3328_codec_data *codec = first_codec; for (codec_type = AZF_CODEC_PLAYBACK; codec_type <= AZF_CODEC_I2S_OUT; ++codec_type, ++codec) { /* skip codec if there's no interrupt for it */ if (!(status & (1 << codec_type))) continue; spin_lock(codec->lock); which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); /* ack all IRQ types immediately */ snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); spin_unlock(codec->lock); if (codec->substream) { snd_pcm_period_elapsed(codec->substream); dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n", codec->name, which, snd_azf3328_codec_inl( codec, IDX_IO_CODEC_DMA_CURRPOS)); } else dev_warn(chip->card->dev, "irq handler problem!\n"); if (which & IRQ_SOMETHING) snd_azf3328_irq_log_unknown_type(chip, which); } } static irqreturn_t snd_azf3328_interrupt(int irq, void *dev_id) { struct snd_azf3328 *chip = dev_id; u8 status; static unsigned long irq_count; status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); /* fast path out, to ease interrupt sharing */ if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) )) return IRQ_NONE; /* must be interrupt for another device */ dev_dbg(chip->card->dev, "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", irq_count++ /* debug-only */, status); if (status & IRQ_TIMER) { /* dev_dbg(chip->card->dev, "timer %ld\n", snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK ); */ if (chip->timer) snd_timer_interrupt(chip->timer, chip->timer->sticks); /* ACK timer */ spin_lock(&chip->reg_lock); snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); spin_unlock(&chip->reg_lock); dev_dbg(chip->card->dev, "timer IRQ\n"); } if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) snd_azf3328_pcm_interrupt(chip, chip->codecs, status); if (status & IRQ_GAMEPORT) snd_azf3328_gameport_interrupt(chip); /* MPU401 has less critical IRQ requirements * than timer and playback/recording, right? */ if (status & IRQ_MPU401) { snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); /* hmm, do we have to ack the IRQ here somehow? * If so, then I don't know how yet... */ dev_dbg(chip->card->dev, "MPU401 IRQ\n"); } return IRQ_HANDLED; } /*****************************************************************/ /* as long as we think we have identical snd_pcm_hardware parameters for playback, capture and i2s out, we can use the same physical struct since the struct is simply being copied into a member. */ static const struct snd_pcm_hardware snd_azf3328_hardware = { /* FIXME!! Correct? */ .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID, .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT, .rate_min = AZF_FREQ_4000, .rate_max = AZF_FREQ_66200, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (64*1024), .period_bytes_min = 1024, .period_bytes_max = (32*1024), /* We simply have two DMA areas (instead of a list of descriptors such as other cards); I believe that this is a fixed hardware attribute and there isn't much driver magic to be done to expand it. Thus indicate that we have at least and at most 2 periods. */ .periods_min = 2, .periods_max = 2, /* FIXME: maybe that card actually has a FIFO? * Hmm, it seems newer revisions do have one, but we still don't know * its size... */ .fifo_size = 0, }; static const unsigned int snd_azf3328_fixed_rates[] = { AZF_FREQ_4000, AZF_FREQ_4800, AZF_FREQ_5512, AZF_FREQ_6620, AZF_FREQ_8000, AZF_FREQ_9600, AZF_FREQ_11025, AZF_FREQ_13240, AZF_FREQ_16000, AZF_FREQ_22050, AZF_FREQ_32000, AZF_FREQ_44100, AZF_FREQ_48000, AZF_FREQ_66200 }; static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { .count = ARRAY_SIZE(snd_azf3328_fixed_rates), .list = snd_azf3328_fixed_rates, .mask = 0, }; /*****************************************************************/ static int snd_azf3328_pcm_open(struct snd_pcm_substream *substream, enum snd_azf3328_codec_type codec_type ) { struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; codec->substream = substream; /* same parameters for all our codecs - at least we think so... */ runtime->hw = snd_azf3328_hardware; snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &snd_azf3328_hw_constraints_rates); runtime->private_data = codec; return 0; } static int snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) { return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); } static int snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) { return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); } static int snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) { return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); } static int snd_azf3328_pcm_close(struct snd_pcm_substream *substream ) { struct snd_azf3328_codec_data *codec = substream->runtime->private_data; codec->substream = NULL; return 0; } /******************************************************************/ static const struct snd_pcm_ops snd_azf3328_playback_ops = { .open = snd_azf3328_pcm_playback_open, .close = snd_azf3328_pcm_close, .prepare = snd_azf3328_pcm_prepare, .trigger = snd_azf3328_pcm_trigger, .pointer = snd_azf3328_pcm_pointer }; static const struct snd_pcm_ops snd_azf3328_capture_ops = { .open = snd_azf3328_pcm_capture_open, .close = snd_azf3328_pcm_close, .prepare = snd_azf3328_pcm_prepare, .trigger = snd_azf3328_pcm_trigger, .pointer = snd_azf3328_pcm_pointer }; static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = { .open = snd_azf3328_pcm_i2s_out_open, .close = snd_azf3328_pcm_close, .prepare = snd_azf3328_pcm_prepare, .trigger = snd_azf3328_pcm_trigger, .pointer = snd_azf3328_pcm_pointer }; static int snd_azf3328_pcm(struct snd_azf3328 *chip) { /* pcm devices */ enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, 1, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, chip->card->shortname); /* same pcm object for playback/capture (see snd_pcm_new() above) */ chip->pcm[AZF_CODEC_PLAYBACK] = pcm; chip->pcm[AZF_CODEC_CAPTURE] = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 64*1024); err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, 1, 0, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_i2s_out_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, chip->card->shortname); chip->pcm[AZF_CODEC_I2S_OUT] = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 64*1024, 64*1024); return 0; } /******************************************************************/ /*** NOTE: the physical timer resolution actually is 1024000 ticks per second *** (probably derived from main crystal via a divider of 24), *** but announcing those attributes to user-space would make programs *** configure the timer to a 1 tick value, resulting in an absolutely fatal *** timer IRQ storm. *** Thus I chose to announce a down-scaled virtual timer to the outside and *** calculate real timer countdown values internally. *** (the scale factor can be set via module parameter "seqtimer_scaling"). ***/ static int snd_azf3328_timer_start(struct snd_timer *timer) { struct snd_azf3328 *chip; unsigned long flags; unsigned int delay; chip = snd_timer_chip(timer); delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; if (delay < 49) { /* uhoh, that's not good, since user-space won't know about * this timing tweak * (we need to do it to avoid a lockup, though) */ dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay); delay = 49; /* minimum time is 49 ticks */ } dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay); delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; spin_lock_irqsave(&chip->reg_lock, flags); snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); spin_unlock_irqrestore(&chip->reg_lock, flags); return 0; } static int snd_azf3328_timer_stop(struct snd_timer *timer) { struct snd_azf3328 *chip; unsigned long flags; chip = snd_timer_chip(timer); spin_lock_irqsave(&chip->reg_lock, flags); /* disable timer countdown and interrupt */ /* Hmm, should we write TIMER_IRQ_ACK here? YES indeed, otherwise a rogue timer operation - which prompts ALSA(?) to call repeated stop() in vain, but NOT start() - will never end (value 0x03 is kept shown in control byte). Simply manually poking 0x04 _once_ immediately successfully stops the hardware/ALSA interrupt activity. */ snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); spin_unlock_irqrestore(&chip->reg_lock, flags); return 0; } static int snd_azf3328_timer_precise_resolution(struct snd_timer *timer, unsigned long *num, unsigned long *den) { *num = 1; *den = 1024000 / seqtimer_scaling; return 0; } static struct snd_timer_hardware snd_azf3328_timer_hw = { .flags = SNDRV_TIMER_HW_AUTO, .resolution = 977, /* 1000000/1024000 = 0.9765625us */ .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ .start = snd_azf3328_timer_start, .stop = snd_azf3328_timer_stop, .precise_resolution = snd_azf3328_timer_precise_resolution, }; static int snd_azf3328_timer(struct snd_azf3328 *chip, int device) { struct snd_timer *timer = NULL; struct snd_timer_id tid; int err; tid.dev_class = SNDRV_TIMER_CLASS_CARD; tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; tid.card = chip->card->number; tid.device = device; tid.subdevice = 0; snd_azf3328_timer_hw.resolution *= seqtimer_scaling; snd_azf3328_timer_hw.ticks /= seqtimer_scaling; err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); if (err < 0) goto out; strcpy(timer->name, "AZF3328 timer"); timer->private_data = chip; timer->hw = snd_azf3328_timer_hw; chip->timer = timer; snd_azf3328_timer_stop(timer); err = 0; out: return err; } /******************************************************************/ static void snd_azf3328_free(struct snd_card *card) { struct snd_azf3328 *chip = card->private_data; snd_azf3328_mixer_reset(chip); snd_azf3328_timer_stop(chip->timer); snd_azf3328_gameport_free(chip); } #if 0 /* check whether a bit can be modified */ static void snd_azf3328_test_bit(unsigned unsigned reg, int bit) { unsigned char val, valoff, valon; val = inb(reg); outb(val & ~(1 << bit), reg); valoff = inb(reg); outb(val|(1 << bit), reg); valon = inb(reg); outb(val, reg); printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon ); } #endif static inline void snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) { u16 tmp; dev_dbg(chip->card->dev, "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", chip->ctrl_io, chip->game_io, chip->mpu_io, chip->opl3_io, chip->mixer_io, chip->irq); dev_dbg(chip->card->dev, "game %02x %02x %02x %02x %02x %02x\n", snd_azf3328_game_inb(chip, 0), snd_azf3328_game_inb(chip, 1), snd_azf3328_game_inb(chip, 2), snd_azf3328_game_inb(chip, 3), snd_azf3328_game_inb(chip, 4), snd_azf3328_game_inb(chip, 5)); for (tmp = 0; tmp < 0x07; tmp += 1) dev_dbg(chip->card->dev, "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); for (tmp = 0; tmp <= 0x07; tmp += 1) dev_dbg(chip->card->dev, "0x%02x: game200 0x%04x, game208 0x%04x\n", tmp, inb(0x200 + tmp), inb(0x208 + tmp)); for (tmp = 0; tmp <= 0x01; tmp += 1) dev_dbg(chip->card->dev, "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", tmp, inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp), inb(0x388 + tmp), inb(0x38c + tmp)); for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) dev_dbg(chip->card->dev, "ctrl 0x%02x: 0x%04x\n", tmp, snd_azf3328_ctrl_inw(chip, tmp)); for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) dev_dbg(chip->card->dev, "mixer 0x%02x: 0x%04x\n", tmp, snd_azf3328_mixer_inw(chip, tmp)); } static int snd_azf3328_create(struct snd_card *card, struct pci_dev *pci, unsigned long device_type) { struct snd_azf3328 *chip = card->private_data; int err; u8 dma_init; enum snd_azf3328_codec_type codec_type; struct snd_azf3328_codec_data *codec_setup; err = pcim_enable_device(pci); if (err < 0) return err; spin_lock_init(&chip->reg_lock); chip->card = card; chip->pci = pci; chip->irq = -1; /* check if we can restrict PCI DMA transfers to 24 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { dev_err(card->dev, "architecture does not support 24bit PCI busmaster DMA\n" ); return -ENXIO; } err = pci_request_regions(pci, "Aztech AZF3328"); if (err < 0) return err; chip->ctrl_io = pci_resource_start(pci, 0); chip->game_io = pci_resource_start(pci, 1); chip->mpu_io = pci_resource_start(pci, 2); chip->opl3_io = pci_resource_start(pci, 3); chip->mixer_io = pci_resource_start(pci, 4); codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; codec_setup->lock = &chip->reg_lock; codec_setup->type = AZF_CODEC_PLAYBACK; codec_setup->name = "PLAYBACK"; codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; codec_setup->lock = &chip->reg_lock; codec_setup->type = AZF_CODEC_CAPTURE; codec_setup->name = "CAPTURE"; codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; codec_setup->lock = &chip->reg_lock; codec_setup->type = AZF_CODEC_I2S_OUT; codec_setup->name = "I2S_OUT"; if (devm_request_irq(&pci->dev, pci->irq, snd_azf3328_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_azf3328_free; pci_set_master(pci); snd_azf3328_debug_show_ports(chip); /* create mixer interface & switches */ err = snd_azf3328_mixer_new(chip); if (err < 0) return err; /* standard codec init stuff */ /* default DMA init value */ dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; for (codec_type = AZF_CODEC_PLAYBACK; codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; /* shutdown codecs to reduce power / noise */ /* have ...ctrl_codec_activity() act properly */ codec->running = true; snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); spin_lock_irq(codec->lock); snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, dma_init); spin_unlock_irq(codec->lock); } return 0; } static int __snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct snd_azf3328 *chip; struct snd_opl3 *opl3; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; strcpy(card->driver, "AZF3328"); strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); err = snd_azf3328_create(card, pci, pci_id->driver_data); if (err < 0) return err; /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, since our hardware ought to be similar, thus use same ID. */ err = snd_mpu401_uart_new( card, 0, MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi ); if (err < 0) { dev_err(card->dev, "no MPU-401 device at 0x%lx?\n", chip->mpu_io ); return err; } err = snd_azf3328_timer(chip, 0); if (err < 0) return err; err = snd_azf3328_pcm(chip); if (err < 0) return err; if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, OPL3_HW_AUTO, 1, &opl3) < 0) { dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n", chip->opl3_io, chip->opl3_io+2 ); } else { /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ err = snd_opl3_timer_new(opl3, 1, 2); if (err < 0) return err; err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (err < 0) return err; opl3->private_data = chip; } sprintf(card->longname, "%s at 0x%lx, irq %i", card->shortname, chip->ctrl_io, chip->irq); err = snd_card_register(card); if (err < 0) return err; #ifdef MODULE dev_info(card->dev, "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"); dev_info(card->dev, "Hardware was completely undocumented, unfortunately.\n"); dev_info(card->dev, "Feel free to contact andi AT lisas.de for bug reports etc.!\n"); dev_info(card->dev, "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 1024000 / seqtimer_scaling, seqtimer_scaling); #endif snd_azf3328_gameport(chip, dev); pci_set_drvdata(pci, card); dev++; return 0; } static int snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_azf3328_probe(pci, pci_id)); } #ifdef CONFIG_PM_SLEEP static inline void snd_azf3328_suspend_regs(const struct snd_azf3328 *chip, unsigned long io_addr, unsigned count, u32 *saved_regs) { unsigned reg; for (reg = 0; reg < count; ++reg) { *saved_regs = inl(io_addr); dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n", io_addr, *saved_regs); ++saved_regs; io_addr += sizeof(*saved_regs); } } static inline void snd_azf3328_resume_regs(const struct snd_azf3328 *chip, const u32 *saved_regs, unsigned long io_addr, unsigned count ) { unsigned reg; for (reg = 0; reg < count; ++reg) { outl(*saved_regs, io_addr); dev_dbg(chip->card->dev, "resume: io 0x%04lx: 0x%08x --> 0x%08x\n", io_addr, *saved_regs, inl(io_addr)); ++saved_regs; io_addr += sizeof(*saved_regs); } } static inline void snd_azf3328_suspend_ac97(struct snd_azf3328 *chip) { #ifdef AZF_USE_AC97_LAYER snd_ac97_suspend(chip->ac97); #else snd_azf3328_suspend_regs(chip, chip->mixer_io, ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); /* make sure to disable master volume etc. to prevent looping sound */ snd_azf3328_mixer_mute_control_master(chip, 1); snd_azf3328_mixer_mute_control_pcm(chip, 1); #endif /* AZF_USE_AC97_LAYER */ } static inline void snd_azf3328_resume_ac97(const struct snd_azf3328 *chip) { #ifdef AZF_USE_AC97_LAYER snd_ac97_resume(chip->ac97); #else snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io, ARRAY_SIZE(chip->saved_regs_mixer)); /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) and IDX_MIXER_RESET (offset 0x00) get touched at the same time, resulting in a mixer reset condition persisting until _after_ master vol was restored. Thus master vol needs an extra restore. */ outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); #endif /* AZF_USE_AC97_LAYER */ } static int snd_azf3328_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_azf3328 *chip = card->private_data; u16 *saved_regs_ctrl_u16; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_azf3328_suspend_ac97(chip); snd_azf3328_suspend_regs(chip, chip->ctrl_io, ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); /* manually store the one currently relevant write-only reg, too */ saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; snd_azf3328_suspend_regs(chip, chip->game_io, ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); snd_azf3328_suspend_regs(chip, chip->mpu_io, ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); snd_azf3328_suspend_regs(chip, chip->opl3_io, ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); return 0; } static int snd_azf3328_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); const struct snd_azf3328 *chip = card->private_data; snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io, ARRAY_SIZE(chip->saved_regs_game)); snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io, ARRAY_SIZE(chip->saved_regs_mpu)); snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io, ARRAY_SIZE(chip->saved_regs_opl3)); snd_azf3328_resume_ac97(chip); snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io, ARRAY_SIZE(chip->saved_regs_ctrl)); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume); #define SND_AZF3328_PM_OPS &snd_azf3328_pm #else #define SND_AZF3328_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static struct pci_driver azf3328_driver = { .name = KBUILD_MODNAME, .id_table = snd_azf3328_ids, .probe = snd_azf3328_probe, .driver = { .pm = SND_AZF3328_PM_OPS, }, }; module_pci_driver(azf3328_driver);
linux-master
sound/pci/azt3328.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Universal interface for Audio Codec '97 * * For more details look to AC '97 component specification revision 2.2 * by Intel Corporation (http://developer.intel.com). */ #include <linux/delay.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/module.h> #include <linux/mutex.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/tlv.h> #include <sound/ac97_codec.h> #include <sound/asoundef.h> #include <sound/initval.h> #include "ac97_id.h" #include "ac97_patch.c" MODULE_AUTHOR("Jaroslav Kysela <[email protected]>"); MODULE_DESCRIPTION("Universal interface for Audio Codec '97"); MODULE_LICENSE("GPL"); static bool enable_loopback; module_param(enable_loopback, bool, 0444); MODULE_PARM_DESC(enable_loopback, "Enable AC97 ADC/DAC Loopback Control"); #ifdef CONFIG_SND_AC97_POWER_SAVE static int power_save = CONFIG_SND_AC97_POWER_SAVE_DEFAULT; module_param(power_save, int, 0644); MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " "(in second, 0 = disable)."); #endif /* */ struct ac97_codec_id { unsigned int id; unsigned int mask; const char *name; int (*patch)(struct snd_ac97 *ac97); int (*mpatch)(struct snd_ac97 *ac97); unsigned int flags; }; static const struct ac97_codec_id snd_ac97_codec_id_vendors[] = { { 0x41445300, 0xffffff00, "Analog Devices", NULL, NULL }, { 0x414b4d00, 0xffffff00, "Asahi Kasei", NULL, NULL }, { 0x414c4300, 0xffffff00, "Realtek", NULL, NULL }, { 0x414c4700, 0xffffff00, "Realtek", NULL, NULL }, /* * This is an _inofficial_ Aztech Labs entry * (value might differ from unknown official Aztech ID), * currently used by the AC97 emulation of the almost-AC97 PCI168 card. */ { 0x415a5400, 0xffffff00, "Aztech Labs (emulated)", NULL, NULL }, { 0x434d4900, 0xffffff00, "C-Media Electronics", NULL, NULL }, { 0x43525900, 0xffffff00, "Cirrus Logic", NULL, NULL }, { 0x43585400, 0xffffff00, "Conexant", NULL, NULL }, { 0x44543000, 0xffffff00, "Diamond Technology", NULL, NULL }, { 0x454d4300, 0xffffff00, "eMicro", NULL, NULL }, { 0x45838300, 0xffffff00, "ESS Technology", NULL, NULL }, { 0x48525300, 0xffffff00, "Intersil", NULL, NULL }, { 0x49434500, 0xffffff00, "ICEnsemble", NULL, NULL }, { 0x49544500, 0xffffff00, "ITE Tech.Inc", NULL, NULL }, { 0x4e534300, 0xffffff00, "National Semiconductor", NULL, NULL }, { 0x50534300, 0xffffff00, "Philips", NULL, NULL }, { 0x53494c00, 0xffffff00, "Silicon Laboratory", NULL, NULL }, { 0x53544d00, 0xffffff00, "STMicroelectronics", NULL, NULL }, { 0x54524100, 0xffffff00, "TriTech", NULL, NULL }, { 0x54584e00, 0xffffff00, "Texas Instruments", NULL, NULL }, { 0x56494100, 0xffffff00, "VIA Technologies", NULL, NULL }, { 0x57454300, 0xffffff00, "Winbond", NULL, NULL }, { 0x574d4c00, 0xffffff00, "Wolfson", NULL, NULL }, { 0x594d4800, 0xffffff00, "Yamaha", NULL, NULL }, { 0x83847600, 0xffffff00, "SigmaTel", NULL, NULL }, { 0, 0, NULL, NULL, NULL } }; static const struct ac97_codec_id snd_ac97_codec_ids[] = { { 0x41445303, 0xffffffff, "AD1819", patch_ad1819, NULL }, { 0x41445340, 0xffffffff, "AD1881", patch_ad1881, NULL }, { 0x41445348, 0xffffffff, "AD1881A", patch_ad1881, NULL }, { 0x41445360, 0xffffffff, "AD1885", patch_ad1885, NULL }, { 0x41445361, 0xffffffff, "AD1886", patch_ad1886, NULL }, { 0x41445362, 0xffffffff, "AD1887", patch_ad1881, NULL }, { 0x41445363, 0xffffffff, "AD1886A", patch_ad1881, NULL }, { 0x41445368, 0xffffffff, "AD1888", patch_ad1888, NULL }, { 0x41445370, 0xffffffff, "AD1980", patch_ad1980, NULL }, { 0x41445372, 0xffffffff, "AD1981A", patch_ad1981a, NULL }, { 0x41445374, 0xffffffff, "AD1981B", patch_ad1981b, NULL }, { 0x41445375, 0xffffffff, "AD1985", patch_ad1985, NULL }, { 0x41445378, 0xffffffff, "AD1986", patch_ad1986, NULL }, { 0x414b4d00, 0xffffffff, "AK4540", NULL, NULL }, { 0x414b4d01, 0xffffffff, "AK4542", NULL, NULL }, { 0x414b4d02, 0xffffffff, "AK4543", NULL, NULL }, { 0x414b4d06, 0xffffffff, "AK4544A", NULL, NULL }, { 0x414b4d07, 0xffffffff, "AK4545", NULL, NULL }, { 0x414c4300, 0xffffff00, "ALC100,100P", NULL, NULL }, { 0x414c4710, 0xfffffff0, "ALC200,200P", NULL, NULL }, { 0x414c4721, 0xffffffff, "ALC650D", NULL, NULL }, /* already patched */ { 0x414c4722, 0xffffffff, "ALC650E", NULL, NULL }, /* already patched */ { 0x414c4723, 0xffffffff, "ALC650F", NULL, NULL }, /* already patched */ { 0x414c4720, 0xfffffff0, "ALC650", patch_alc650, NULL }, { 0x414c4730, 0xffffffff, "ALC101", NULL, NULL }, { 0x414c4740, 0xfffffff0, "ALC202", NULL, NULL }, { 0x414c4750, 0xfffffff0, "ALC250", NULL, NULL }, { 0x414c4760, 0xfffffff0, "ALC655", patch_alc655, NULL }, { 0x414c4770, 0xfffffff0, "ALC203", patch_alc203, NULL }, { 0x414c4781, 0xffffffff, "ALC658D", NULL, NULL }, /* already patched */ { 0x414c4780, 0xfffffff0, "ALC658", patch_alc655, NULL }, { 0x414c4790, 0xfffffff0, "ALC850", patch_alc850, NULL }, { 0x415a5401, 0xffffffff, "AZF3328", patch_aztech_azf3328, NULL }, { 0x434d4941, 0xffffffff, "CMI9738", patch_cm9738, NULL }, { 0x434d4961, 0xffffffff, "CMI9739", patch_cm9739, NULL }, { 0x434d4969, 0xffffffff, "CMI9780", patch_cm9780, NULL }, { 0x434d4978, 0xffffffff, "CMI9761A", patch_cm9761, NULL }, { 0x434d4982, 0xffffffff, "CMI9761B", patch_cm9761, NULL }, { 0x434d4983, 0xffffffff, "CMI9761A+", patch_cm9761, NULL }, { 0x43525900, 0xfffffff8, "CS4297", NULL, NULL }, { 0x43525910, 0xfffffff8, "CS4297A", patch_cirrus_spdif, NULL }, { 0x43525920, 0xfffffff8, "CS4298", patch_cirrus_spdif, NULL }, { 0x43525928, 0xfffffff8, "CS4294", NULL, NULL }, { 0x43525930, 0xfffffff8, "CS4299", patch_cirrus_cs4299, NULL }, { 0x43525948, 0xfffffff8, "CS4201", NULL, NULL }, { 0x43525958, 0xfffffff8, "CS4205", patch_cirrus_spdif, NULL }, { 0x43525960, 0xfffffff8, "CS4291", NULL, NULL }, { 0x43525970, 0xfffffff8, "CS4202", NULL, NULL }, { 0x43585421, 0xffffffff, "HSD11246", NULL, NULL }, // SmartMC II { 0x43585428, 0xfffffff8, "Cx20468", patch_conexant, NULL }, // SmartAMC fixme: the mask might be different { 0x43585430, 0xffffffff, "Cx20468-31", patch_conexant, NULL }, { 0x43585431, 0xffffffff, "Cx20551", patch_cx20551, NULL }, { 0x44543031, 0xfffffff0, "DT0398", NULL, NULL }, { 0x454d4328, 0xffffffff, "EM28028", NULL, NULL }, // same as TR28028? { 0x45838308, 0xffffffff, "ESS1988", NULL, NULL }, { 0x48525300, 0xffffff00, "HMP9701", NULL, NULL }, { 0x49434501, 0xffffffff, "ICE1230", NULL, NULL }, { 0x49434511, 0xffffffff, "ICE1232", NULL, NULL }, // alias VIA VT1611A? { 0x49434514, 0xffffffff, "ICE1232A", NULL, NULL }, { 0x49434551, 0xffffffff, "VT1616", patch_vt1616, NULL }, { 0x49434552, 0xffffffff, "VT1616i", patch_vt1616, NULL }, // VT1616 compatible (chipset integrated) { 0x49544520, 0xffffffff, "IT2226E", NULL, NULL }, { 0x49544561, 0xffffffff, "IT2646E", patch_it2646, NULL }, { 0x4e534300, 0xffffffff, "LM4540,43,45,46,48", NULL, NULL }, // only guess --jk { 0x4e534331, 0xffffffff, "LM4549", NULL, NULL }, { 0x4e534350, 0xffffffff, "LM4550", patch_lm4550, NULL }, // volume wrap fix { 0x53494c20, 0xffffffe0, "Si3036,8", mpatch_si3036, mpatch_si3036, AC97_MODEM_PATCH }, { 0x53544d02, 0xffffffff, "ST7597", NULL, NULL }, { 0x54524102, 0xffffffff, "TR28022", NULL, NULL }, { 0x54524103, 0xffffffff, "TR28023", NULL, NULL }, { 0x54524106, 0xffffffff, "TR28026", NULL, NULL }, { 0x54524108, 0xffffffff, "TR28028", patch_tritech_tr28028, NULL }, // added by xin jin [07/09/99] { 0x54524123, 0xffffffff, "TR28602", NULL, NULL }, // only guess --jk [TR28023 = eMicro EM28023 (new CT1297)] { 0x54584e03, 0xffffffff, "TLV320AIC27", NULL, NULL }, { 0x54584e20, 0xffffffff, "TLC320AD9xC", NULL, NULL }, { 0x56494120, 0xfffffff0, "VIA1613", patch_vt1613, NULL }, { 0x56494161, 0xffffffff, "VIA1612A", NULL, NULL }, // modified ICE1232 with S/PDIF { 0x56494170, 0xffffffff, "VIA1617A", patch_vt1617a, NULL }, // modified VT1616 with S/PDIF { 0x56494182, 0xffffffff, "VIA1618", patch_vt1618, NULL }, { 0x57454301, 0xffffffff, "W83971D", NULL, NULL }, { 0x574d4c00, 0xffffffff, "WM9701,WM9701A", NULL, NULL }, { 0x574d4C03, 0xffffffff, "WM9703,WM9707,WM9708,WM9717", patch_wolfson03, NULL}, { 0x574d4C04, 0xffffffff, "WM9704M,WM9704Q", patch_wolfson04, NULL}, { 0x574d4C05, 0xffffffff, "WM9705,WM9710", patch_wolfson05, NULL}, { 0x574d4C09, 0xffffffff, "WM9709", NULL, NULL}, { 0x574d4C12, 0xffffffff, "WM9711,WM9712,WM9715", patch_wolfson11, NULL}, { 0x574d4c13, 0xffffffff, "WM9713,WM9714", patch_wolfson13, NULL, AC97_DEFAULT_POWER_OFF}, { 0x594d4800, 0xffffffff, "YMF743", patch_yamaha_ymf743, NULL }, { 0x594d4802, 0xffffffff, "YMF752", NULL, NULL }, { 0x594d4803, 0xffffffff, "YMF753", patch_yamaha_ymf753, NULL }, { 0x83847600, 0xffffffff, "STAC9700,83,84", patch_sigmatel_stac9700, NULL }, { 0x83847604, 0xffffffff, "STAC9701,3,4,5", NULL, NULL }, { 0x83847605, 0xffffffff, "STAC9704", NULL, NULL }, { 0x83847608, 0xffffffff, "STAC9708,11", patch_sigmatel_stac9708, NULL }, { 0x83847609, 0xffffffff, "STAC9721,23", patch_sigmatel_stac9721, NULL }, { 0x83847644, 0xffffffff, "STAC9744", patch_sigmatel_stac9744, NULL }, { 0x83847650, 0xffffffff, "STAC9750,51", NULL, NULL }, // patch? { 0x83847652, 0xffffffff, "STAC9752,53", NULL, NULL }, // patch? { 0x83847656, 0xffffffff, "STAC9756,57", patch_sigmatel_stac9756, NULL }, { 0x83847658, 0xffffffff, "STAC9758,59", patch_sigmatel_stac9758, NULL }, { 0x83847666, 0xffffffff, "STAC9766,67", NULL, NULL }, // patch? { 0, 0, NULL, NULL, NULL } }; static void update_power_regs(struct snd_ac97 *ac97); #ifdef CONFIG_SND_AC97_POWER_SAVE #define ac97_is_power_save_mode(ac97) \ ((ac97->scaps & AC97_SCAP_POWER_SAVE) && power_save) #else #define ac97_is_power_save_mode(ac97) 0 #endif #define ac97_err(ac97, fmt, args...) \ dev_err((ac97)->bus->card->dev, fmt, ##args) #define ac97_warn(ac97, fmt, args...) \ dev_warn((ac97)->bus->card->dev, fmt, ##args) #define ac97_dbg(ac97, fmt, args...) \ dev_dbg((ac97)->bus->card->dev, fmt, ##args) /* * I/O routines */ static int snd_ac97_valid_reg(struct snd_ac97 *ac97, unsigned short reg) { /* filter some registers for buggy codecs */ switch (ac97->id) { case AC97_ID_ST_AC97_ID4: if (reg == 0x08) return 0; fallthrough; case AC97_ID_ST7597: if (reg == 0x22 || reg == 0x7a) return 1; fallthrough; case AC97_ID_AK4540: case AC97_ID_AK4542: if (reg <= 0x1c || reg == 0x20 || reg == 0x26 || reg >= 0x7c) return 1; return 0; case AC97_ID_AD1819: /* AD1819 */ case AC97_ID_AD1881: /* AD1881 */ case AC97_ID_AD1881A: /* AD1881A */ if (reg >= 0x3a && reg <= 0x6e) /* 0x59 */ return 0; return 1; case AC97_ID_AD1885: /* AD1885 */ case AC97_ID_AD1886: /* AD1886 */ case AC97_ID_AD1886A: /* AD1886A - !!verify!! --jk */ case AC97_ID_AD1887: /* AD1887 - !!verify!! --jk */ if (reg == 0x5a) return 1; if (reg >= 0x3c && reg <= 0x6e) /* 0x59 */ return 0; return 1; case AC97_ID_STAC9700: case AC97_ID_STAC9704: case AC97_ID_STAC9705: case AC97_ID_STAC9708: case AC97_ID_STAC9721: case AC97_ID_STAC9744: case AC97_ID_STAC9756: if (reg <= 0x3a || reg >= 0x5a) return 1; return 0; } return 1; } /** * snd_ac97_write - write a value on the given register * @ac97: the ac97 instance * @reg: the register to change * @value: the value to set * * Writes a value on the given register. This will invoke the write * callback directly after the register check. * This function doesn't change the register cache unlike * #snd_ca97_write_cache(), so use this only when you don't want to * reflect the change to the suspend/resume state. */ void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) { if (!snd_ac97_valid_reg(ac97, reg)) return; if ((ac97->id & 0xffffff00) == AC97_ID_ALC100) { /* Fix H/W bug of ALC100/100P */ if (reg == AC97_MASTER || reg == AC97_HEADPHONE) ac97->bus->ops->write(ac97, AC97_RESET, 0); /* reset audio codec */ } ac97->bus->ops->write(ac97, reg, value); } EXPORT_SYMBOL(snd_ac97_write); /** * snd_ac97_read - read a value from the given register * * @ac97: the ac97 instance * @reg: the register to read * * Reads a value from the given register. This will invoke the read * callback directly after the register check. * * Return: The read value. */ unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { if (!snd_ac97_valid_reg(ac97, reg)) return 0; return ac97->bus->ops->read(ac97, reg); } /* read a register - return the cached value if already read */ static inline unsigned short snd_ac97_read_cache(struct snd_ac97 *ac97, unsigned short reg) { if (! test_bit(reg, ac97->reg_accessed)) { ac97->regs[reg] = ac97->bus->ops->read(ac97, reg); // set_bit(reg, ac97->reg_accessed); } return ac97->regs[reg]; } EXPORT_SYMBOL(snd_ac97_read); /** * snd_ac97_write_cache - write a value on the given register and update the cache * @ac97: the ac97 instance * @reg: the register to change * @value: the value to set * * Writes a value on the given register and updates the register * cache. The cached values are used for the cached-read and the * suspend/resume. */ void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) { if (!snd_ac97_valid_reg(ac97, reg)) return; mutex_lock(&ac97->reg_mutex); ac97->regs[reg] = value; ac97->bus->ops->write(ac97, reg, value); set_bit(reg, ac97->reg_accessed); mutex_unlock(&ac97->reg_mutex); } EXPORT_SYMBOL(snd_ac97_write_cache); /** * snd_ac97_update - update the value on the given register * @ac97: the ac97 instance * @reg: the register to change * @value: the value to set * * Compares the value with the register cache and updates the value * only when the value is changed. * * Return: 1 if the value is changed, 0 if no change, or a negative * code on failure. */ int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) { int change; if (!snd_ac97_valid_reg(ac97, reg)) return -EINVAL; mutex_lock(&ac97->reg_mutex); change = ac97->regs[reg] != value; if (change) { ac97->regs[reg] = value; ac97->bus->ops->write(ac97, reg, value); } set_bit(reg, ac97->reg_accessed); mutex_unlock(&ac97->reg_mutex); return change; } EXPORT_SYMBOL(snd_ac97_update); /** * snd_ac97_update_bits - update the bits on the given register * @ac97: the ac97 instance * @reg: the register to change * @mask: the bit-mask to change * @value: the value to set * * Updates the masked-bits on the given register only when the value * is changed. * * Return: 1 if the bits are changed, 0 if no change, or a negative * code on failure. */ int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value) { int change; if (!snd_ac97_valid_reg(ac97, reg)) return -EINVAL; mutex_lock(&ac97->reg_mutex); change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); mutex_unlock(&ac97->reg_mutex); return change; } EXPORT_SYMBOL(snd_ac97_update_bits); /* no lock version - see snd_ac97_update_bits() */ int snd_ac97_update_bits_nolock(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value) { int change; unsigned short old, new; old = snd_ac97_read_cache(ac97, reg); new = (old & ~mask) | (value & mask); change = old != new; if (change) { ac97->regs[reg] = new; ac97->bus->ops->write(ac97, reg, new); } set_bit(reg, ac97->reg_accessed); return change; } static int snd_ac97_ad18xx_update_pcm_bits(struct snd_ac97 *ac97, int codec, unsigned short mask, unsigned short value) { int change; unsigned short old, new, cfg; mutex_lock(&ac97->page_mutex); old = ac97->spec.ad18xx.pcmreg[codec]; new = (old & ~mask) | (value & mask); change = old != new; if (change) { mutex_lock(&ac97->reg_mutex); cfg = snd_ac97_read_cache(ac97, AC97_AD_SERIAL_CFG); ac97->spec.ad18xx.pcmreg[codec] = new; /* select single codec */ ac97->bus->ops->write(ac97, AC97_AD_SERIAL_CFG, (cfg & ~0x7000) | ac97->spec.ad18xx.unchained[codec] | ac97->spec.ad18xx.chained[codec]); /* update PCM bits */ ac97->bus->ops->write(ac97, AC97_PCM, new); /* select all codecs */ ac97->bus->ops->write(ac97, AC97_AD_SERIAL_CFG, cfg | 0x7000); mutex_unlock(&ac97->reg_mutex); } mutex_unlock(&ac97->page_mutex); return change; } /* * Controls */ static int snd_ac97_info_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct ac97_enum *e = (struct ac97_enum *)kcontrol->private_value; return snd_ctl_enum_info(uinfo, e->shift_l == e->shift_r ? 1 : 2, e->mask, e->texts); } static int snd_ac97_get_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); struct ac97_enum *e = (struct ac97_enum *)kcontrol->private_value; unsigned short val, bitmask; for (bitmask = 1; bitmask < e->mask; bitmask <<= 1) ; val = snd_ac97_read_cache(ac97, e->reg); ucontrol->value.enumerated.item[0] = (val >> e->shift_l) & (bitmask - 1); if (e->shift_l != e->shift_r) ucontrol->value.enumerated.item[1] = (val >> e->shift_r) & (bitmask - 1); return 0; } static int snd_ac97_put_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); struct ac97_enum *e = (struct ac97_enum *)kcontrol->private_value; unsigned short val; unsigned short mask, bitmask; for (bitmask = 1; bitmask < e->mask; bitmask <<= 1) ; if (ucontrol->value.enumerated.item[0] > e->mask - 1) return -EINVAL; val = ucontrol->value.enumerated.item[0] << e->shift_l; mask = (bitmask - 1) << e->shift_l; if (e->shift_l != e->shift_r) { if (ucontrol->value.enumerated.item[1] > e->mask - 1) return -EINVAL; val |= ucontrol->value.enumerated.item[1] << e->shift_r; mask |= (bitmask - 1) << e->shift_r; } return snd_ac97_update_bits(ac97, e->reg, mask, val); } /* save/restore ac97 v2.3 paging */ static int snd_ac97_page_save(struct snd_ac97 *ac97, int reg, struct snd_kcontrol *kcontrol) { int page_save = -1; if ((kcontrol->private_value & (1<<25)) && (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_23 && (reg >= 0x60 && reg < 0x70)) { unsigned short page = (kcontrol->private_value >> 26) & 0x0f; mutex_lock(&ac97->page_mutex); /* lock paging */ page_save = snd_ac97_read(ac97, AC97_INT_PAGING) & AC97_PAGE_MASK; snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, page); } return page_save; } static void snd_ac97_page_restore(struct snd_ac97 *ac97, int page_save) { if (page_save >= 0) { snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, page_save); mutex_unlock(&ac97->page_mutex); /* unlock paging */ } } /* volume and switch controls */ static int snd_ac97_info_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int mask = (kcontrol->private_value >> 16) & 0xff; int shift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = shift == rshift ? 1 : 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_ac97_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0x01; int page_save; page_save = snd_ac97_page_save(ac97, reg, kcontrol); ucontrol->value.integer.value[0] = (snd_ac97_read_cache(ac97, reg) >> shift) & mask; if (shift != rshift) ucontrol->value.integer.value[1] = (snd_ac97_read_cache(ac97, reg) >> rshift) & mask; if (invert) { ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; if (shift != rshift) ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; } snd_ac97_page_restore(ac97, page_save); return 0; } static int snd_ac97_put_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 0x01; int err, page_save; unsigned short val, val2, val_mask; page_save = snd_ac97_page_save(ac97, reg, kcontrol); val = (ucontrol->value.integer.value[0] & mask); if (invert) val = mask - val; val_mask = mask << shift; val = val << shift; if (shift != rshift) { val2 = (ucontrol->value.integer.value[1] & mask); if (invert) val2 = mask - val2; val_mask |= mask << rshift; val |= val2 << rshift; } err = snd_ac97_update_bits(ac97, reg, val_mask, val); snd_ac97_page_restore(ac97, page_save); #ifdef CONFIG_SND_AC97_POWER_SAVE /* check analog mixer power-down */ if ((val_mask & AC97_PD_EAPD) && (kcontrol->private_value & (1<<30))) { if (val & AC97_PD_EAPD) ac97->power_up &= ~(1 << (reg>>1)); else ac97->power_up |= 1 << (reg>>1); update_power_regs(ac97); } #endif return err; } static const struct snd_kcontrol_new snd_ac97_controls_tone[2] = { AC97_SINGLE("Tone Control - Bass", AC97_MASTER_TONE, 8, 15, 1), AC97_SINGLE("Tone Control - Treble", AC97_MASTER_TONE, 0, 15, 1) }; static const struct snd_kcontrol_new snd_ac97_controls_pc_beep[2] = { AC97_SINGLE("Beep Playback Switch", AC97_PC_BEEP, 15, 1, 1), AC97_SINGLE("Beep Playback Volume", AC97_PC_BEEP, 1, 15, 1) }; static const struct snd_kcontrol_new snd_ac97_controls_mic_boost = AC97_SINGLE("Mic Boost (+20dB)", AC97_MIC, 6, 1, 0); static const char* std_rec_sel[] = {"Mic", "CD", "Video", "Aux", "Line", "Mix", "Mix Mono", "Phone"}; static const char* std_3d_path[] = {"pre 3D", "post 3D"}; static const char* std_mix[] = {"Mix", "Mic"}; static const char* std_mic[] = {"Mic1", "Mic2"}; static const struct ac97_enum std_enum[] = { AC97_ENUM_DOUBLE(AC97_REC_SEL, 8, 0, 8, std_rec_sel), AC97_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, std_3d_path), AC97_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 9, 2, std_mix), AC97_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 8, 2, std_mic), }; static const struct snd_kcontrol_new snd_ac97_control_capture_src = AC97_ENUM("Capture Source", std_enum[0]); static const struct snd_kcontrol_new snd_ac97_control_capture_vol = AC97_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 15, 0); static const struct snd_kcontrol_new snd_ac97_controls_mic_capture[2] = { AC97_SINGLE("Mic Capture Switch", AC97_REC_GAIN_MIC, 15, 1, 1), AC97_SINGLE("Mic Capture Volume", AC97_REC_GAIN_MIC, 0, 15, 0) }; enum { AC97_GENERAL_PCM_OUT = 0, AC97_GENERAL_STEREO_ENHANCEMENT, AC97_GENERAL_3D, AC97_GENERAL_LOUDNESS, AC97_GENERAL_MONO, AC97_GENERAL_MIC, AC97_GENERAL_LOOPBACK }; static const struct snd_kcontrol_new snd_ac97_controls_general[7] = { AC97_ENUM("PCM Out Path & Mute", std_enum[1]), AC97_SINGLE("Simulated Stereo Enhancement", AC97_GENERAL_PURPOSE, 14, 1, 0), AC97_SINGLE("3D Control - Switch", AC97_GENERAL_PURPOSE, 13, 1, 0), AC97_SINGLE("Loudness (bass boost)", AC97_GENERAL_PURPOSE, 12, 1, 0), AC97_ENUM("Mono Output Select", std_enum[2]), AC97_ENUM("Mic Select", std_enum[3]), AC97_SINGLE("ADC/DAC Loopback", AC97_GENERAL_PURPOSE, 7, 1, 0) }; static const struct snd_kcontrol_new snd_ac97_controls_3d[2] = { AC97_SINGLE("3D Control - Center", AC97_3D_CONTROL, 8, 15, 0), AC97_SINGLE("3D Control - Depth", AC97_3D_CONTROL, 0, 15, 0) }; static const struct snd_kcontrol_new snd_ac97_controls_center[2] = { AC97_SINGLE("Center Playback Switch", AC97_CENTER_LFE_MASTER, 7, 1, 1), AC97_SINGLE("Center Playback Volume", AC97_CENTER_LFE_MASTER, 0, 31, 1) }; static const struct snd_kcontrol_new snd_ac97_controls_lfe[2] = { AC97_SINGLE("LFE Playback Switch", AC97_CENTER_LFE_MASTER, 15, 1, 1), AC97_SINGLE("LFE Playback Volume", AC97_CENTER_LFE_MASTER, 8, 31, 1) }; static const struct snd_kcontrol_new snd_ac97_control_eapd = AC97_SINGLE("External Amplifier", AC97_POWERDOWN, 15, 1, 1); static const struct snd_kcontrol_new snd_ac97_controls_modem_switches[2] = { AC97_SINGLE("Off-hook Switch", AC97_GPIO_STATUS, 0, 1, 0), AC97_SINGLE("Caller ID Switch", AC97_GPIO_STATUS, 2, 1, 0) }; /* change the existing EAPD control as inverted */ static void set_inv_eapd(struct snd_ac97 *ac97, struct snd_kcontrol *kctl) { kctl->private_value = AC97_SINGLE_VALUE(AC97_POWERDOWN, 15, 1, 0); snd_ac97_update_bits(ac97, AC97_POWERDOWN, (1<<15), (1<<15)); /* EAPD up */ ac97->scaps |= AC97_SCAP_INV_EAPD; } static int snd_ac97_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_ac97_spdif_cmask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_NONAUDIO | IEC958_AES0_CON_EMPHASIS_5015 | IEC958_AES0_CON_NOT_COPYRIGHT; ucontrol->value.iec958.status[1] = IEC958_AES1_CON_CATEGORY | IEC958_AES1_CON_ORIGINAL; ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS; return 0; } static int snd_ac97_spdif_pmask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* FIXME: AC'97 spec doesn't say which bits are used for what */ ucontrol->value.iec958.status[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_NONAUDIO | IEC958_AES0_PRO_FS | IEC958_AES0_PRO_EMPHASIS_5015; return 0; } static int snd_ac97_spdif_default_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); mutex_lock(&ac97->reg_mutex); ucontrol->value.iec958.status[0] = ac97->spdif_status & 0xff; ucontrol->value.iec958.status[1] = (ac97->spdif_status >> 8) & 0xff; ucontrol->value.iec958.status[2] = (ac97->spdif_status >> 16) & 0xff; ucontrol->value.iec958.status[3] = (ac97->spdif_status >> 24) & 0xff; mutex_unlock(&ac97->reg_mutex); return 0; } static int snd_ac97_spdif_default_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned int new = 0; unsigned short val = 0; int change; new = val = ucontrol->value.iec958.status[0] & (IEC958_AES0_PROFESSIONAL|IEC958_AES0_NONAUDIO); if (ucontrol->value.iec958.status[0] & IEC958_AES0_PROFESSIONAL) { new |= ucontrol->value.iec958.status[0] & (IEC958_AES0_PRO_FS|IEC958_AES0_PRO_EMPHASIS_5015); switch (new & IEC958_AES0_PRO_FS) { case IEC958_AES0_PRO_FS_44100: val |= 0<<12; break; case IEC958_AES0_PRO_FS_48000: val |= 2<<12; break; case IEC958_AES0_PRO_FS_32000: val |= 3<<12; break; default: val |= 1<<12; break; } if ((new & IEC958_AES0_PRO_EMPHASIS) == IEC958_AES0_PRO_EMPHASIS_5015) val |= 1<<3; } else { new |= ucontrol->value.iec958.status[0] & (IEC958_AES0_CON_EMPHASIS_5015|IEC958_AES0_CON_NOT_COPYRIGHT); new |= ((ucontrol->value.iec958.status[1] & (IEC958_AES1_CON_CATEGORY|IEC958_AES1_CON_ORIGINAL)) << 8); new |= ((ucontrol->value.iec958.status[3] & IEC958_AES3_CON_FS) << 24); if ((new & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_5015) val |= 1<<3; if (!(new & IEC958_AES0_CON_NOT_COPYRIGHT)) val |= 1<<2; val |= ((new >> 8) & 0xff) << 4; // category + original switch ((new >> 24) & 0xff) { case IEC958_AES3_CON_FS_44100: val |= 0<<12; break; case IEC958_AES3_CON_FS_48000: val |= 2<<12; break; case IEC958_AES3_CON_FS_32000: val |= 3<<12; break; default: val |= 1<<12; break; } } mutex_lock(&ac97->reg_mutex); change = ac97->spdif_status != new; ac97->spdif_status = new; if (ac97->flags & AC97_CS_SPDIF) { int x = (val >> 12) & 0x03; switch (x) { case 0: x = 1; break; // 44.1 case 2: x = 0; break; // 48.0 default: x = 0; break; // illegal. } change |= snd_ac97_update_bits_nolock(ac97, AC97_CSR_SPDIF, 0x3fff, ((val & 0xcfff) | (x << 12))); } else if (ac97->flags & AC97_CX_SPDIF) { int v; v = new & (IEC958_AES0_CON_EMPHASIS_5015|IEC958_AES0_CON_NOT_COPYRIGHT) ? 0 : AC97_CXR_COPYRGT; v |= new & IEC958_AES0_NONAUDIO ? AC97_CXR_SPDIF_AC3 : AC97_CXR_SPDIF_PCM; change |= snd_ac97_update_bits_nolock(ac97, AC97_CXR_AUDIO_MISC, AC97_CXR_SPDIF_MASK | AC97_CXR_COPYRGT, v); } else if (ac97->id == AC97_ID_YMF743) { change |= snd_ac97_update_bits_nolock(ac97, AC97_YMF7X3_DIT_CTRL, 0xff38, ((val << 4) & 0xff00) | ((val << 2) & 0x0038)); } else { unsigned short extst = snd_ac97_read_cache(ac97, AC97_EXTENDED_STATUS); snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); /* turn off */ change |= snd_ac97_update_bits_nolock(ac97, AC97_SPDIF, 0x3fff, val); if (extst & AC97_EA_SPDIF) { snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, AC97_EA_SPDIF); /* turn on again */ } } mutex_unlock(&ac97->reg_mutex); return change; } static int snd_ac97_put_spsa(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; // int invert = (kcontrol->private_value >> 24) & 0xff; unsigned short value, old, new; int change; value = (ucontrol->value.integer.value[0] & mask); mutex_lock(&ac97->reg_mutex); mask <<= shift; value <<= shift; old = snd_ac97_read_cache(ac97, reg); new = (old & ~mask) | value; change = old != new; if (change) { unsigned short extst = snd_ac97_read_cache(ac97, AC97_EXTENDED_STATUS); snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); /* turn off */ change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); if (extst & AC97_EA_SPDIF) snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, AC97_EA_SPDIF); /* turn on again */ } mutex_unlock(&ac97->reg_mutex); return change; } static const struct snd_kcontrol_new snd_ac97_controls_spdif[5] = { { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), .info = snd_ac97_spdif_mask_info, .get = snd_ac97_spdif_cmask_get, }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), .info = snd_ac97_spdif_mask_info, .get = snd_ac97_spdif_pmask_get, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = snd_ac97_spdif_mask_info, .get = snd_ac97_spdif_default_get, .put = snd_ac97_spdif_default_put, }, AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH),AC97_EXTENDED_STATUS, 2, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "AC97-SPSA", .info = snd_ac97_info_volsw, .get = snd_ac97_get_volsw, .put = snd_ac97_put_spsa, .private_value = AC97_SINGLE_VALUE(AC97_EXTENDED_STATUS, 4, 3, 0) }, }; #define AD18XX_PCM_BITS(xname, codec, lshift, rshift, mask) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_ac97_ad18xx_pcm_info_bits, \ .get = snd_ac97_ad18xx_pcm_get_bits, .put = snd_ac97_ad18xx_pcm_put_bits, \ .private_value = (codec) | ((lshift) << 8) | ((rshift) << 12) | ((mask) << 16) } static int snd_ac97_ad18xx_pcm_info_bits(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int mask = (kcontrol->private_value >> 16) & 0x0f; int lshift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; if (lshift != rshift && (ac97->flags & AC97_STEREO_MUTES)) uinfo->count = 2; else uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } static int snd_ac97_ad18xx_pcm_get_bits(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int codec = kcontrol->private_value & 3; int lshift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; ucontrol->value.integer.value[0] = mask - ((ac97->spec.ad18xx.pcmreg[codec] >> lshift) & mask); if (lshift != rshift && (ac97->flags & AC97_STEREO_MUTES)) ucontrol->value.integer.value[1] = mask - ((ac97->spec.ad18xx.pcmreg[codec] >> rshift) & mask); return 0; } static int snd_ac97_ad18xx_pcm_put_bits(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int codec = kcontrol->private_value & 3; int lshift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; unsigned short val, valmask; val = (mask - (ucontrol->value.integer.value[0] & mask)) << lshift; valmask = mask << lshift; if (lshift != rshift && (ac97->flags & AC97_STEREO_MUTES)) { val |= (mask - (ucontrol->value.integer.value[1] & mask)) << rshift; valmask |= mask << rshift; } return snd_ac97_ad18xx_update_pcm_bits(ac97, codec, valmask, val); } #define AD18XX_PCM_VOLUME(xname, codec) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_ac97_ad18xx_pcm_info_volume, \ .get = snd_ac97_ad18xx_pcm_get_volume, .put = snd_ac97_ad18xx_pcm_put_volume, \ .private_value = codec } static int snd_ac97_ad18xx_pcm_info_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = 31; return 0; } static int snd_ac97_ad18xx_pcm_get_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int codec = kcontrol->private_value & 3; mutex_lock(&ac97->page_mutex); ucontrol->value.integer.value[0] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 8) & 31); ucontrol->value.integer.value[1] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 0) & 31); mutex_unlock(&ac97->page_mutex); return 0; } static int snd_ac97_ad18xx_pcm_put_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int codec = kcontrol->private_value & 3; unsigned short val1, val2; val1 = 31 - (ucontrol->value.integer.value[0] & 31); val2 = 31 - (ucontrol->value.integer.value[1] & 31); return snd_ac97_ad18xx_update_pcm_bits(ac97, codec, 0x1f1f, (val1 << 8) | val2); } static const struct snd_kcontrol_new snd_ac97_controls_ad18xx_pcm[2] = { AD18XX_PCM_BITS("PCM Playback Switch", 0, 15, 7, 1), AD18XX_PCM_VOLUME("PCM Playback Volume", 0) }; static const struct snd_kcontrol_new snd_ac97_controls_ad18xx_surround[2] = { AD18XX_PCM_BITS("Surround Playback Switch", 1, 15, 7, 1), AD18XX_PCM_VOLUME("Surround Playback Volume", 1) }; static const struct snd_kcontrol_new snd_ac97_controls_ad18xx_center[2] = { AD18XX_PCM_BITS("Center Playback Switch", 2, 15, 15, 1), AD18XX_PCM_BITS("Center Playback Volume", 2, 8, 8, 31) }; static const struct snd_kcontrol_new snd_ac97_controls_ad18xx_lfe[2] = { AD18XX_PCM_BITS("LFE Playback Switch", 2, 7, 7, 1), AD18XX_PCM_BITS("LFE Playback Volume", 2, 0, 0, 31) }; /* * */ static void snd_ac97_powerdown(struct snd_ac97 *ac97); static int snd_ac97_bus_free(struct snd_ac97_bus *bus) { if (bus) { snd_ac97_bus_proc_done(bus); kfree(bus->pcms); if (bus->private_free) bus->private_free(bus); kfree(bus); } return 0; } static int snd_ac97_bus_dev_free(struct snd_device *device) { struct snd_ac97_bus *bus = device->device_data; return snd_ac97_bus_free(bus); } static int snd_ac97_free(struct snd_ac97 *ac97) { if (ac97) { #ifdef CONFIG_SND_AC97_POWER_SAVE cancel_delayed_work_sync(&ac97->power_work); #endif snd_ac97_proc_done(ac97); if (ac97->bus) ac97->bus->codec[ac97->num] = NULL; if (ac97->private_free) ac97->private_free(ac97); kfree(ac97); } return 0; } static int snd_ac97_dev_free(struct snd_device *device) { struct snd_ac97 *ac97 = device->device_data; snd_ac97_powerdown(ac97); /* for avoiding click noises during shut down */ return snd_ac97_free(ac97); } static int snd_ac97_try_volume_mix(struct snd_ac97 * ac97, int reg) { unsigned short val, mask = AC97_MUTE_MASK_MONO; if (! snd_ac97_valid_reg(ac97, reg)) return 0; switch (reg) { case AC97_MASTER_TONE: return ac97->caps & AC97_BC_BASS_TREBLE ? 1 : 0; case AC97_HEADPHONE: return ac97->caps & AC97_BC_HEADPHONE ? 1 : 0; case AC97_REC_GAIN_MIC: return ac97->caps & AC97_BC_DEDICATED_MIC ? 1 : 0; case AC97_3D_CONTROL: if (ac97->caps & AC97_BC_3D_TECH_ID_MASK) { val = snd_ac97_read(ac97, reg); /* if nonzero - fixed and we can't set it */ return val == 0; } return 0; case AC97_CENTER_LFE_MASTER: /* center */ if ((ac97->ext_id & AC97_EI_CDAC) == 0) return 0; break; case AC97_CENTER_LFE_MASTER+1: /* lfe */ if ((ac97->ext_id & AC97_EI_LDAC) == 0) return 0; reg = AC97_CENTER_LFE_MASTER; mask = 0x0080; break; case AC97_SURROUND_MASTER: if ((ac97->ext_id & AC97_EI_SDAC) == 0) return 0; break; } val = snd_ac97_read(ac97, reg); if (!(val & mask)) { /* nothing seems to be here - mute flag is not set */ /* try another test */ snd_ac97_write_cache(ac97, reg, val | mask); val = snd_ac97_read(ac97, reg); val = snd_ac97_read(ac97, reg); if (!(val & mask)) return 0; /* nothing here */ } return 1; /* success, useable */ } static void check_volume_resolution(struct snd_ac97 *ac97, int reg, unsigned char *lo_max, unsigned char *hi_max) { unsigned short cbit[3] = { 0x20, 0x10, 0x01 }; unsigned char max[3] = { 63, 31, 15 }; int i; /* first look up the static resolution table */ if (ac97->res_table) { const struct snd_ac97_res_table *tbl; for (tbl = ac97->res_table; tbl->reg; tbl++) { if (tbl->reg == reg) { *lo_max = tbl->bits & 0xff; *hi_max = (tbl->bits >> 8) & 0xff; return; } } } *lo_max = *hi_max = 0; for (i = 0 ; i < ARRAY_SIZE(cbit); i++) { unsigned short val; snd_ac97_write( ac97, reg, AC97_MUTE_MASK_STEREO | cbit[i] | (cbit[i] << 8) ); /* Do the read twice due to buffers on some ac97 codecs. * e.g. The STAC9704 returns exactly what you wrote to the register * if you read it immediately. This causes the detect routine to fail. */ val = snd_ac97_read(ac97, reg); val = snd_ac97_read(ac97, reg); if (! *lo_max && (val & 0x7f) == cbit[i]) *lo_max = max[i]; if (! *hi_max && ((val >> 8) & 0x7f) == cbit[i]) *hi_max = max[i]; if (*lo_max && *hi_max) break; } } static int snd_ac97_try_bit(struct snd_ac97 * ac97, int reg, int bit) { unsigned short mask, val, orig, res; mask = 1 << bit; orig = snd_ac97_read(ac97, reg); val = orig ^ mask; snd_ac97_write(ac97, reg, val); res = snd_ac97_read(ac97, reg); snd_ac97_write_cache(ac97, reg, orig); return res == val; } /* check the volume resolution of center/lfe */ static void snd_ac97_change_volume_params2(struct snd_ac97 * ac97, int reg, int shift, unsigned char *max) { unsigned short val, val1; *max = 63; val = AC97_MUTE_MASK_STEREO | (0x20 << shift); snd_ac97_write(ac97, reg, val); val1 = snd_ac97_read(ac97, reg); if (val != val1) { *max = 31; } /* reset volume to zero */ snd_ac97_write_cache(ac97, reg, AC97_MUTE_MASK_STEREO); } static inline int printable(unsigned int x) { x &= 0xff; if (x < ' ' || x >= 0x71) { if (x <= 0x89) return x - 0x71 + 'A'; return '?'; } return x; } static struct snd_kcontrol *snd_ac97_cnew(const struct snd_kcontrol_new *_template, struct snd_ac97 * ac97) { struct snd_kcontrol_new template; memcpy(&template, _template, sizeof(template)); template.index = ac97->num; return snd_ctl_new1(&template, ac97); } /* * create mute switch(es) for normal stereo controls */ static int snd_ac97_cmute_new_stereo(struct snd_card *card, char *name, int reg, int check_stereo, int check_amix, struct snd_ac97 *ac97) { struct snd_kcontrol *kctl; int err; unsigned short val, val1, mute_mask; if (! snd_ac97_valid_reg(ac97, reg)) return 0; mute_mask = AC97_MUTE_MASK_MONO; val = snd_ac97_read(ac97, reg); if (check_stereo || (ac97->flags & AC97_STEREO_MUTES)) { /* check whether both mute bits work */ val1 = val | AC97_MUTE_MASK_STEREO; snd_ac97_write(ac97, reg, val1); if (val1 == snd_ac97_read(ac97, reg)) mute_mask = AC97_MUTE_MASK_STEREO; } if (mute_mask == AC97_MUTE_MASK_STEREO) { struct snd_kcontrol_new tmp = AC97_DOUBLE(name, reg, 15, 7, 1, 1); if (check_amix) tmp.private_value |= (1 << 30); tmp.index = ac97->num; kctl = snd_ctl_new1(&tmp, ac97); } else { struct snd_kcontrol_new tmp = AC97_SINGLE(name, reg, 15, 1, 1); if (check_amix) tmp.private_value |= (1 << 30); tmp.index = ac97->num; kctl = snd_ctl_new1(&tmp, ac97); } err = snd_ctl_add(card, kctl); if (err < 0) return err; /* mute as default */ snd_ac97_write_cache(ac97, reg, val | mute_mask); return 0; } /* * set dB information */ static const DECLARE_TLV_DB_SCALE(db_scale_4bit, -4500, 300, 0); static const DECLARE_TLV_DB_SCALE(db_scale_5bit, -4650, 150, 0); static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0); static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0); static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0); static const unsigned int *find_db_scale(unsigned int maxval) { switch (maxval) { case 0x0f: return db_scale_4bit; case 0x1f: return db_scale_5bit; case 0x3f: return db_scale_6bit; } return NULL; } static void set_tlv_db_scale(struct snd_kcontrol *kctl, const unsigned int *tlv) { kctl->tlv.p = tlv; if (tlv) kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ; } /* * create a volume for normal stereo/mono controls */ static int snd_ac97_cvol_new(struct snd_card *card, char *name, int reg, unsigned int lo_max, unsigned int hi_max, struct snd_ac97 *ac97) { int err; struct snd_kcontrol *kctl; if (! snd_ac97_valid_reg(ac97, reg)) return 0; if (hi_max) { /* invert */ struct snd_kcontrol_new tmp = AC97_DOUBLE(name, reg, 8, 0, lo_max, 1); tmp.index = ac97->num; kctl = snd_ctl_new1(&tmp, ac97); } else { /* invert */ struct snd_kcontrol_new tmp = AC97_SINGLE(name, reg, 0, lo_max, 1); tmp.index = ac97->num; kctl = snd_ctl_new1(&tmp, ac97); } if (!kctl) return -ENOMEM; if (reg >= AC97_PHONE && reg <= AC97_PCM) set_tlv_db_scale(kctl, db_scale_5bit_12db_max); else set_tlv_db_scale(kctl, find_db_scale(lo_max)); err = snd_ctl_add(card, kctl); if (err < 0) return err; snd_ac97_write_cache( ac97, reg, (snd_ac97_read(ac97, reg) & AC97_MUTE_MASK_STEREO) | lo_max | (hi_max << 8) ); return 0; } /* * create a mute-switch and a volume for normal stereo/mono controls */ static int snd_ac97_cmix_new_stereo(struct snd_card *card, const char *pfx, int reg, int check_stereo, int check_amix, struct snd_ac97 *ac97) { int err; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; unsigned char lo_max, hi_max; if (! snd_ac97_valid_reg(ac97, reg)) return 0; if (snd_ac97_try_bit(ac97, reg, 15)) { sprintf(name, "%s Switch", pfx); err = snd_ac97_cmute_new_stereo(card, name, reg, check_stereo, check_amix, ac97); if (err < 0) return err; } check_volume_resolution(ac97, reg, &lo_max, &hi_max); if (lo_max) { sprintf(name, "%s Volume", pfx); err = snd_ac97_cvol_new(card, name, reg, lo_max, hi_max, ac97); if (err < 0) return err; } return 0; } #define snd_ac97_cmix_new(card, pfx, reg, acheck, ac97) \ snd_ac97_cmix_new_stereo(card, pfx, reg, 0, acheck, ac97) #define snd_ac97_cmute_new(card, name, reg, acheck, ac97) \ snd_ac97_cmute_new_stereo(card, name, reg, 0, acheck, ac97) static unsigned int snd_ac97_determine_spdif_rates(struct snd_ac97 *ac97); static int snd_ac97_mixer_build(struct snd_ac97 * ac97) { struct snd_card *card = ac97->bus->card; struct snd_kcontrol *kctl; int err; unsigned int idx; unsigned char max; /* build master controls */ /* AD claims to remove this control from AD1887, although spec v2.2 does not allow this */ if (snd_ac97_try_volume_mix(ac97, AC97_MASTER)) { if (ac97->flags & AC97_HAS_NO_MASTER_VOL) err = snd_ac97_cmute_new(card, "Master Playback Switch", AC97_MASTER, 0, ac97); else err = snd_ac97_cmix_new(card, "Master Playback", AC97_MASTER, 0, ac97); if (err < 0) return err; } ac97->regs[AC97_CENTER_LFE_MASTER] = AC97_MUTE_MASK_STEREO; /* build center controls */ if ((snd_ac97_try_volume_mix(ac97, AC97_CENTER_LFE_MASTER)) && !(ac97->flags & AC97_AD_MULTI)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_center[0], ac97)); if (err < 0) return err; err = snd_ctl_add(card, kctl = snd_ac97_cnew(&snd_ac97_controls_center[1], ac97)); if (err < 0) return err; snd_ac97_change_volume_params2(ac97, AC97_CENTER_LFE_MASTER, 0, &max); kctl->private_value &= ~(0xff << 16); kctl->private_value |= (int)max << 16; set_tlv_db_scale(kctl, find_db_scale(max)); snd_ac97_write_cache(ac97, AC97_CENTER_LFE_MASTER, ac97->regs[AC97_CENTER_LFE_MASTER] | max); } /* build LFE controls */ if ((snd_ac97_try_volume_mix(ac97, AC97_CENTER_LFE_MASTER+1)) && !(ac97->flags & AC97_AD_MULTI)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_lfe[0], ac97)); if (err < 0) return err; err = snd_ctl_add(card, kctl = snd_ac97_cnew(&snd_ac97_controls_lfe[1], ac97)); if (err < 0) return err; snd_ac97_change_volume_params2(ac97, AC97_CENTER_LFE_MASTER, 8, &max); kctl->private_value &= ~(0xff << 16); kctl->private_value |= (int)max << 16; set_tlv_db_scale(kctl, find_db_scale(max)); snd_ac97_write_cache(ac97, AC97_CENTER_LFE_MASTER, ac97->regs[AC97_CENTER_LFE_MASTER] | max << 8); } /* build surround controls */ if ((snd_ac97_try_volume_mix(ac97, AC97_SURROUND_MASTER)) && !(ac97->flags & AC97_AD_MULTI)) { /* Surround Master (0x38) is with stereo mutes */ err = snd_ac97_cmix_new_stereo(card, "Surround Playback", AC97_SURROUND_MASTER, 1, 0, ac97); if (err < 0) return err; } /* build headphone controls */ if (snd_ac97_try_volume_mix(ac97, AC97_HEADPHONE)) { err = snd_ac97_cmix_new(card, "Headphone Playback", AC97_HEADPHONE, 0, ac97); if (err < 0) return err; } /* build master mono controls */ if (snd_ac97_try_volume_mix(ac97, AC97_MASTER_MONO)) { err = snd_ac97_cmix_new(card, "Master Mono Playback", AC97_MASTER_MONO, 0, ac97); if (err < 0) return err; } /* build master tone controls */ if (!(ac97->flags & AC97_HAS_NO_TONE)) { if (snd_ac97_try_volume_mix(ac97, AC97_MASTER_TONE)) { for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_tone[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; if (ac97->id == AC97_ID_YMF743 || ac97->id == AC97_ID_YMF753) { kctl->private_value &= ~(0xff << 16); kctl->private_value |= 7 << 16; } } snd_ac97_write_cache(ac97, AC97_MASTER_TONE, 0x0f0f); } } /* build Beep controls */ if (!(ac97->flags & AC97_HAS_NO_PC_BEEP) && ((ac97->flags & AC97_HAS_PC_BEEP) || snd_ac97_try_volume_mix(ac97, AC97_PC_BEEP))) { for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_pc_beep[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_4bit); snd_ac97_write_cache( ac97, AC97_PC_BEEP, (snd_ac97_read(ac97, AC97_PC_BEEP) | AC97_MUTE_MASK_MONO | 0x001e) ); } /* build Phone controls */ if (!(ac97->flags & AC97_HAS_NO_PHONE)) { if (snd_ac97_try_volume_mix(ac97, AC97_PHONE)) { err = snd_ac97_cmix_new(card, "Phone Playback", AC97_PHONE, 1, ac97); if (err < 0) return err; } } /* build MIC controls */ if (!(ac97->flags & AC97_HAS_NO_MIC)) { if (snd_ac97_try_volume_mix(ac97, AC97_MIC)) { err = snd_ac97_cmix_new(card, "Mic Playback", AC97_MIC, 1, ac97); if (err < 0) return err; err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_mic_boost, ac97)); if (err < 0) return err; } } /* build Line controls */ if (snd_ac97_try_volume_mix(ac97, AC97_LINE)) { err = snd_ac97_cmix_new(card, "Line Playback", AC97_LINE, 1, ac97); if (err < 0) return err; } /* build CD controls */ if (!(ac97->flags & AC97_HAS_NO_CD)) { if (snd_ac97_try_volume_mix(ac97, AC97_CD)) { err = snd_ac97_cmix_new(card, "CD Playback", AC97_CD, 1, ac97); if (err < 0) return err; } } /* build Video controls */ if (!(ac97->flags & AC97_HAS_NO_VIDEO)) { if (snd_ac97_try_volume_mix(ac97, AC97_VIDEO)) { err = snd_ac97_cmix_new(card, "Video Playback", AC97_VIDEO, 1, ac97); if (err < 0) return err; } } /* build Aux controls */ if (!(ac97->flags & AC97_HAS_NO_AUX)) { if (snd_ac97_try_volume_mix(ac97, AC97_AUX)) { err = snd_ac97_cmix_new(card, "Aux Playback", AC97_AUX, 1, ac97); if (err < 0) return err; } } /* build PCM controls */ if (ac97->flags & AC97_AD_MULTI) { unsigned short init_val; if (ac97->flags & AC97_STEREO_MUTES) init_val = 0x9f9f; else init_val = 0x9f1f; for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_ad18xx_pcm[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_5bit); ac97->spec.ad18xx.pcmreg[0] = init_val; if (ac97->scaps & AC97_SCAP_SURROUND_DAC) { for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_ad18xx_surround[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_5bit); ac97->spec.ad18xx.pcmreg[1] = init_val; } if (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC) { for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_ad18xx_center[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_5bit); for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_ad18xx_lfe[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_5bit); ac97->spec.ad18xx.pcmreg[2] = init_val; } snd_ac97_write_cache(ac97, AC97_PCM, init_val); } else { if (!(ac97->flags & AC97_HAS_NO_STD_PCM)) { if (ac97->flags & AC97_HAS_NO_PCM_VOL) err = snd_ac97_cmute_new(card, "PCM Playback Switch", AC97_PCM, 0, ac97); else err = snd_ac97_cmix_new(card, "PCM Playback", AC97_PCM, 0, ac97); if (err < 0) return err; } } /* build Capture controls */ if (!(ac97->flags & AC97_HAS_NO_REC_GAIN)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_control_capture_src, ac97)); if (err < 0) return err; if (snd_ac97_try_bit(ac97, AC97_REC_GAIN, 15)) { err = snd_ac97_cmute_new(card, "Capture Switch", AC97_REC_GAIN, 0, ac97); if (err < 0) return err; } kctl = snd_ac97_cnew(&snd_ac97_control_capture_vol, ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; set_tlv_db_scale(kctl, db_scale_rec_gain); snd_ac97_write_cache(ac97, AC97_REC_SEL, 0x0000); snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x0000); } /* build MIC Capture controls */ if (snd_ac97_try_volume_mix(ac97, AC97_REC_GAIN_MIC)) { for (idx = 0; idx < 2; idx++) { kctl = snd_ac97_cnew(&snd_ac97_controls_mic_capture[idx], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; } set_tlv_db_scale(kctl, db_scale_rec_gain); snd_ac97_write_cache(ac97, AC97_REC_GAIN_MIC, 0x0000); } /* build PCM out path & mute control */ if (snd_ac97_try_bit(ac97, AC97_GENERAL_PURPOSE, 15)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_PCM_OUT], ac97)); if (err < 0) return err; } /* build Simulated Stereo Enhancement control */ if (ac97->caps & AC97_BC_SIM_STEREO) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_STEREO_ENHANCEMENT], ac97)); if (err < 0) return err; } /* build 3D Stereo Enhancement control */ if (snd_ac97_try_bit(ac97, AC97_GENERAL_PURPOSE, 13)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_3D], ac97)); if (err < 0) return err; } /* build Loudness control */ if (ac97->caps & AC97_BC_LOUDNESS) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_LOUDNESS], ac97)); if (err < 0) return err; } /* build Mono output select control */ if (snd_ac97_try_bit(ac97, AC97_GENERAL_PURPOSE, 9)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_MONO], ac97)); if (err < 0) return err; } /* build Mic select control */ if (snd_ac97_try_bit(ac97, AC97_GENERAL_PURPOSE, 8)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_MIC], ac97)); if (err < 0) return err; } /* build ADC/DAC loopback control */ if (enable_loopback && snd_ac97_try_bit(ac97, AC97_GENERAL_PURPOSE, 7)) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_general[AC97_GENERAL_LOOPBACK], ac97)); if (err < 0) return err; } snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, ~AC97_GP_DRSS_MASK, 0x0000); /* build 3D controls */ if (ac97->build_ops->build_3d) { ac97->build_ops->build_3d(ac97); } else { if (snd_ac97_try_volume_mix(ac97, AC97_3D_CONTROL)) { unsigned short val; val = 0x0707; snd_ac97_write(ac97, AC97_3D_CONTROL, val); val = snd_ac97_read(ac97, AC97_3D_CONTROL); val = val == 0x0606; kctl = snd_ac97_cnew(&snd_ac97_controls_3d[0], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; if (val) kctl->private_value = AC97_3D_CONTROL | (9 << 8) | (7 << 16); kctl = snd_ac97_cnew(&snd_ac97_controls_3d[1], ac97); err = snd_ctl_add(card, kctl); if (err < 0) return err; if (val) kctl->private_value = AC97_3D_CONTROL | (1 << 8) | (7 << 16); snd_ac97_write_cache(ac97, AC97_3D_CONTROL, 0x0000); } } /* build S/PDIF controls */ /* Hack for ASUS P5P800-VM, which does not indicate S/PDIF capability */ if (ac97->subsystem_vendor == 0x1043 && ac97->subsystem_device == 0x810f) ac97->ext_id |= AC97_EI_SPDIF; if ((ac97->ext_id & AC97_EI_SPDIF) && !(ac97->scaps & AC97_SCAP_NO_SPDIF)) { if (ac97->build_ops->build_spdif) { err = ac97->build_ops->build_spdif(ac97); if (err < 0) return err; } else { for (idx = 0; idx < 5; idx++) { err = snd_ctl_add(card, snd_ac97_cnew(&snd_ac97_controls_spdif[idx], ac97)); if (err < 0) return err; } if (ac97->build_ops->build_post_spdif) { err = ac97->build_ops->build_post_spdif(ac97); if (err < 0) return err; } /* set default PCM S/PDIF params */ /* consumer,PCM audio,no copyright,no preemphasis,PCM coder,original,48000Hz */ snd_ac97_write_cache(ac97, AC97_SPDIF, 0x2a20); ac97->rates[AC97_RATES_SPDIF] = snd_ac97_determine_spdif_rates(ac97); } ac97->spdif_status = SNDRV_PCM_DEFAULT_CON_SPDIF; } /* build chip specific controls */ if (ac97->build_ops->build_specific) { err = ac97->build_ops->build_specific(ac97); if (err < 0) return err; } if (snd_ac97_try_bit(ac97, AC97_POWERDOWN, 15)) { kctl = snd_ac97_cnew(&snd_ac97_control_eapd, ac97); if (! kctl) return -ENOMEM; if (ac97->scaps & AC97_SCAP_INV_EAPD) set_inv_eapd(ac97, kctl); err = snd_ctl_add(card, kctl); if (err < 0) return err; } return 0; } static int snd_ac97_modem_build(struct snd_card *card, struct snd_ac97 * ac97) { int err, idx; /* ac97_dbg(ac97, "AC97_GPIO_CFG = %x\n", snd_ac97_read(ac97,AC97_GPIO_CFG)); */ snd_ac97_write(ac97, AC97_GPIO_CFG, 0xffff & ~(AC97_GPIO_LINE1_OH)); snd_ac97_write(ac97, AC97_GPIO_POLARITY, 0xffff & ~(AC97_GPIO_LINE1_OH)); snd_ac97_write(ac97, AC97_GPIO_STICKY, 0xffff); snd_ac97_write(ac97, AC97_GPIO_WAKEUP, 0x0); snd_ac97_write(ac97, AC97_MISC_AFE, 0x0); /* build modem switches */ for (idx = 0; idx < ARRAY_SIZE(snd_ac97_controls_modem_switches); idx++) { err = snd_ctl_add(card, snd_ctl_new1(&snd_ac97_controls_modem_switches[idx], ac97)); if (err < 0) return err; } /* build chip specific controls */ if (ac97->build_ops->build_specific) { err = ac97->build_ops->build_specific(ac97); if (err < 0) return err; } return 0; } static int snd_ac97_test_rate(struct snd_ac97 *ac97, int reg, int shadow_reg, int rate) { unsigned short val; unsigned int tmp; tmp = ((unsigned int)rate * ac97->bus->clock) / 48000; snd_ac97_write_cache(ac97, reg, tmp & 0xffff); if (shadow_reg) snd_ac97_write_cache(ac97, shadow_reg, tmp & 0xffff); val = snd_ac97_read(ac97, reg); return val == (tmp & 0xffff); } static void snd_ac97_determine_rates(struct snd_ac97 *ac97, int reg, int shadow_reg, unsigned int *r_result) { unsigned int result = 0; unsigned short saved; if (ac97->bus->no_vra) { *r_result = SNDRV_PCM_RATE_48000; if ((ac97->flags & AC97_DOUBLE_RATE) && reg == AC97_PCM_FRONT_DAC_RATE) *r_result |= SNDRV_PCM_RATE_96000; return; } saved = snd_ac97_read(ac97, reg); if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_DRA, 0); /* test a non-standard rate */ if (snd_ac97_test_rate(ac97, reg, shadow_reg, 11000)) result |= SNDRV_PCM_RATE_CONTINUOUS; /* let's try to obtain standard rates */ if (snd_ac97_test_rate(ac97, reg, shadow_reg, 8000)) result |= SNDRV_PCM_RATE_8000; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 11025)) result |= SNDRV_PCM_RATE_11025; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 16000)) result |= SNDRV_PCM_RATE_16000; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 22050)) result |= SNDRV_PCM_RATE_22050; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 32000)) result |= SNDRV_PCM_RATE_32000; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 44100)) result |= SNDRV_PCM_RATE_44100; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 48000)) result |= SNDRV_PCM_RATE_48000; if ((ac97->flags & AC97_DOUBLE_RATE) && reg == AC97_PCM_FRONT_DAC_RATE) { /* test standard double rates */ snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_DRA, AC97_EA_DRA); if (snd_ac97_test_rate(ac97, reg, shadow_reg, 64000 / 2)) result |= SNDRV_PCM_RATE_64000; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 88200 / 2)) result |= SNDRV_PCM_RATE_88200; if (snd_ac97_test_rate(ac97, reg, shadow_reg, 96000 / 2)) result |= SNDRV_PCM_RATE_96000; /* some codecs don't support variable double rates */ if (!snd_ac97_test_rate(ac97, reg, shadow_reg, 76100 / 2)) result &= ~SNDRV_PCM_RATE_CONTINUOUS; snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_DRA, 0); } /* restore the default value */ snd_ac97_write_cache(ac97, reg, saved); if (shadow_reg) snd_ac97_write_cache(ac97, shadow_reg, saved); *r_result = result; } /* check AC97_SPDIF register to accept which sample rates */ static unsigned int snd_ac97_determine_spdif_rates(struct snd_ac97 *ac97) { unsigned int result = 0; int i; static const unsigned short ctl_bits[] = { AC97_SC_SPSR_44K, AC97_SC_SPSR_32K, AC97_SC_SPSR_48K }; static const unsigned int rate_bits[] = { SNDRV_PCM_RATE_44100, SNDRV_PCM_RATE_32000, SNDRV_PCM_RATE_48000 }; for (i = 0; i < (int)ARRAY_SIZE(ctl_bits); i++) { snd_ac97_update_bits(ac97, AC97_SPDIF, AC97_SC_SPSR_MASK, ctl_bits[i]); if ((snd_ac97_read(ac97, AC97_SPDIF) & AC97_SC_SPSR_MASK) == ctl_bits[i]) result |= rate_bits[i]; } return result; } /* look for the codec id table matching with the given id */ static const struct ac97_codec_id *look_for_codec_id(const struct ac97_codec_id *table, unsigned int id) { const struct ac97_codec_id *pid; for (pid = table; pid->id; pid++) if (pid->id == (id & pid->mask)) return pid; return NULL; } void snd_ac97_get_name(struct snd_ac97 *ac97, unsigned int id, char *name, int modem) { const struct ac97_codec_id *pid; sprintf(name, "0x%x %c%c%c", id, printable(id >> 24), printable(id >> 16), printable(id >> 8)); pid = look_for_codec_id(snd_ac97_codec_id_vendors, id); if (! pid) return; strcpy(name, pid->name); if (ac97 && pid->patch) { if ((modem && (pid->flags & AC97_MODEM_PATCH)) || (! modem && ! (pid->flags & AC97_MODEM_PATCH))) pid->patch(ac97); } pid = look_for_codec_id(snd_ac97_codec_ids, id); if (pid) { strcat(name, " "); strcat(name, pid->name); if (pid->mask != 0xffffffff) sprintf(name + strlen(name), " rev %d", id & ~pid->mask); if (ac97 && pid->patch) { if ((modem && (pid->flags & AC97_MODEM_PATCH)) || (! modem && ! (pid->flags & AC97_MODEM_PATCH))) pid->patch(ac97); } } else sprintf(name + strlen(name), " id %x", id & 0xff); } /** * snd_ac97_get_short_name - retrieve codec name * @ac97: the codec instance * * Return: The short identifying name of the codec. */ const char *snd_ac97_get_short_name(struct snd_ac97 *ac97) { const struct ac97_codec_id *pid; for (pid = snd_ac97_codec_ids; pid->id; pid++) if (pid->id == (ac97->id & pid->mask)) return pid->name; return "unknown codec"; } EXPORT_SYMBOL(snd_ac97_get_short_name); /* wait for a while until registers are accessible after RESET * return 0 if ok, negative not ready */ static int ac97_reset_wait(struct snd_ac97 *ac97, int timeout, int with_modem) { unsigned long end_time; unsigned short val; end_time = jiffies + timeout; do { /* use preliminary reads to settle the communication */ snd_ac97_read(ac97, AC97_RESET); snd_ac97_read(ac97, AC97_VENDOR_ID1); snd_ac97_read(ac97, AC97_VENDOR_ID2); /* modem? */ if (with_modem) { val = snd_ac97_read(ac97, AC97_EXTENDED_MID); if (val != 0xffff && (val & 1) != 0) return 0; } if (ac97->scaps & AC97_SCAP_DETECT_BY_VENDOR) { /* probably only Xbox issue - all registers are read as zero */ val = snd_ac97_read(ac97, AC97_VENDOR_ID1); if (val != 0 && val != 0xffff) return 0; } else { /* because the PCM or MASTER volume registers can be modified, * the REC_GAIN register is used for tests */ /* test if we can write to the record gain volume register */ snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05); if ((snd_ac97_read(ac97, AC97_REC_GAIN) & 0x7fff) == 0x0a05) return 0; } schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); return -ENODEV; } /** * snd_ac97_bus - create an AC97 bus component * @card: the card instance * @num: the bus number * @ops: the bus callbacks table * @private_data: private data pointer for the new instance * @rbus: the pointer to store the new AC97 bus instance. * * Creates an AC97 bus component. An struct snd_ac97_bus instance is newly * allocated and initialized. * * The ops table must include valid callbacks (at least read and * write). The other callbacks, wait and reset, are not mandatory. * * The clock is set to 48000. If another clock is needed, set * ``(*rbus)->clock`` manually. * * The AC97 bus instance is registered as a low-level device, so you don't * have to release it manually. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_bus(struct snd_card *card, int num, const struct snd_ac97_bus_ops *ops, void *private_data, struct snd_ac97_bus **rbus) { int err; struct snd_ac97_bus *bus; static const struct snd_device_ops dev_ops = { .dev_free = snd_ac97_bus_dev_free, }; if (snd_BUG_ON(!card)) return -EINVAL; bus = kzalloc(sizeof(*bus), GFP_KERNEL); if (bus == NULL) return -ENOMEM; bus->card = card; bus->num = num; bus->ops = ops; bus->private_data = private_data; bus->clock = 48000; spin_lock_init(&bus->bus_lock); snd_ac97_bus_proc_init(bus); err = snd_device_new(card, SNDRV_DEV_BUS, bus, &dev_ops); if (err < 0) { snd_ac97_bus_free(bus); return err; } if (rbus) *rbus = bus; return 0; } EXPORT_SYMBOL(snd_ac97_bus); /* stop no dev release warning */ static void ac97_device_release(struct device * dev) { } /* register ac97 codec to bus */ static int snd_ac97_dev_register(struct snd_device *device) { struct snd_ac97 *ac97 = device->device_data; int err; ac97->dev.bus = &ac97_bus_type; ac97->dev.parent = ac97->bus->card->dev; ac97->dev.release = ac97_device_release; dev_set_name(&ac97->dev, "%d-%d:%s", ac97->bus->card->number, ac97->num, snd_ac97_get_short_name(ac97)); err = device_register(&ac97->dev); if (err < 0) { ac97_err(ac97, "Can't register ac97 bus\n"); put_device(&ac97->dev); ac97->dev.bus = NULL; return err; } return 0; } /* disconnect ac97 codec */ static int snd_ac97_dev_disconnect(struct snd_device *device) { struct snd_ac97 *ac97 = device->device_data; if (ac97->dev.bus) device_unregister(&ac97->dev); return 0; } /* build_ops to do nothing */ static const struct snd_ac97_build_ops null_build_ops; #ifdef CONFIG_SND_AC97_POWER_SAVE static void do_update_power(struct work_struct *work) { update_power_regs( container_of(work, struct snd_ac97, power_work.work)); } #endif /** * snd_ac97_mixer - create an Codec97 component * @bus: the AC97 bus which codec is attached to * @template: the template of ac97, including index, callbacks and * the private data. * @rac97: the pointer to store the new ac97 instance. * * Creates an Codec97 component. An struct snd_ac97 instance is newly * allocated and initialized from the template. The codec * is then initialized by the standard procedure. * * The template must include the codec number (num) and address (addr), * and the private data (private_data). * * The ac97 instance is registered as a low-level device, so you don't * have to release it manually. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, struct snd_ac97 **rac97) { int err; struct snd_ac97 *ac97; struct snd_card *card; char name[64]; unsigned long end_time; unsigned int reg; const struct ac97_codec_id *pid; static const struct snd_device_ops ops = { .dev_free = snd_ac97_dev_free, .dev_register = snd_ac97_dev_register, .dev_disconnect = snd_ac97_dev_disconnect, }; if (snd_BUG_ON(!bus || !template || !rac97)) return -EINVAL; *rac97 = NULL; if (snd_BUG_ON(template->num >= 4)) return -EINVAL; if (bus->codec[template->num]) return -EBUSY; card = bus->card; ac97 = kzalloc(sizeof(*ac97), GFP_KERNEL); if (ac97 == NULL) return -ENOMEM; ac97->private_data = template->private_data; ac97->private_free = template->private_free; ac97->bus = bus; ac97->pci = template->pci; ac97->num = template->num; ac97->addr = template->addr; ac97->scaps = template->scaps; ac97->res_table = template->res_table; bus->codec[ac97->num] = ac97; mutex_init(&ac97->reg_mutex); mutex_init(&ac97->page_mutex); #ifdef CONFIG_SND_AC97_POWER_SAVE INIT_DELAYED_WORK(&ac97->power_work, do_update_power); #endif #ifdef CONFIG_PCI if (ac97->pci) { pci_read_config_word(ac97->pci, PCI_SUBSYSTEM_VENDOR_ID, &ac97->subsystem_vendor); pci_read_config_word(ac97->pci, PCI_SUBSYSTEM_ID, &ac97->subsystem_device); } #endif if (bus->ops->reset) { bus->ops->reset(ac97); goto __access_ok; } ac97->id = snd_ac97_read(ac97, AC97_VENDOR_ID1) << 16; ac97->id |= snd_ac97_read(ac97, AC97_VENDOR_ID2); if (ac97->id && ac97->id != (unsigned int)-1) { pid = look_for_codec_id(snd_ac97_codec_ids, ac97->id); if (pid && (pid->flags & AC97_DEFAULT_POWER_OFF)) goto __access_ok; } /* reset to defaults */ if (!(ac97->scaps & AC97_SCAP_SKIP_AUDIO)) snd_ac97_write(ac97, AC97_RESET, 0); if (!(ac97->scaps & AC97_SCAP_SKIP_MODEM)) snd_ac97_write(ac97, AC97_EXTENDED_MID, 0); if (bus->ops->wait) bus->ops->wait(ac97); else { udelay(50); if (ac97->scaps & AC97_SCAP_SKIP_AUDIO) err = ac97_reset_wait(ac97, msecs_to_jiffies(500), 1); else { err = ac97_reset_wait(ac97, msecs_to_jiffies(500), 0); if (err < 0) err = ac97_reset_wait(ac97, msecs_to_jiffies(500), 1); } if (err < 0) { ac97_warn(ac97, "AC'97 %d does not respond - RESET\n", ac97->num); /* proceed anyway - it's often non-critical */ } } __access_ok: ac97->id = snd_ac97_read(ac97, AC97_VENDOR_ID1) << 16; ac97->id |= snd_ac97_read(ac97, AC97_VENDOR_ID2); if (! (ac97->scaps & AC97_SCAP_DETECT_BY_VENDOR) && (ac97->id == 0x00000000 || ac97->id == 0xffffffff)) { ac97_err(ac97, "AC'97 %d access is not valid [0x%x], removing mixer.\n", ac97->num, ac97->id); snd_ac97_free(ac97); return -EIO; } pid = look_for_codec_id(snd_ac97_codec_ids, ac97->id); if (pid) ac97->flags |= pid->flags; /* test for AC'97 */ if (!(ac97->scaps & AC97_SCAP_SKIP_AUDIO) && !(ac97->scaps & AC97_SCAP_AUDIO)) { /* test if we can write to the record gain volume register */ snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a06); err = snd_ac97_read(ac97, AC97_REC_GAIN); if ((err & 0x7fff) == 0x0a06) ac97->scaps |= AC97_SCAP_AUDIO; } if (ac97->scaps & AC97_SCAP_AUDIO) { ac97->caps = snd_ac97_read(ac97, AC97_RESET); ac97->ext_id = snd_ac97_read(ac97, AC97_EXTENDED_ID); if (ac97->ext_id == 0xffff) /* invalid combination */ ac97->ext_id = 0; } /* test for MC'97 */ if (!(ac97->scaps & AC97_SCAP_SKIP_MODEM) && !(ac97->scaps & AC97_SCAP_MODEM)) { ac97->ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); if (ac97->ext_mid == 0xffff) /* invalid combination */ ac97->ext_mid = 0; if (ac97->ext_mid & 1) ac97->scaps |= AC97_SCAP_MODEM; } if (!ac97_is_audio(ac97) && !ac97_is_modem(ac97)) { if (!(ac97->scaps & (AC97_SCAP_SKIP_AUDIO|AC97_SCAP_SKIP_MODEM))) ac97_err(ac97, "AC'97 %d access error (not audio or modem codec)\n", ac97->num); snd_ac97_free(ac97); return -EACCES; } if (bus->ops->reset) // FIXME: always skipping? goto __ready_ok; /* FIXME: add powerdown control */ if (ac97_is_audio(ac97)) { /* nothing should be in powerdown mode */ snd_ac97_write_cache(ac97, AC97_POWERDOWN, 0); if (! (ac97->flags & AC97_DEFAULT_POWER_OFF)) { snd_ac97_write_cache(ac97, AC97_RESET, 0); /* reset to defaults */ udelay(100); snd_ac97_write_cache(ac97, AC97_POWERDOWN, 0); } /* nothing should be in powerdown mode */ snd_ac97_write_cache(ac97, AC97_GENERAL_PURPOSE, 0); end_time = jiffies + msecs_to_jiffies(5000); do { if ((snd_ac97_read(ac97, AC97_POWERDOWN) & 0x0f) == 0x0f) goto __ready_ok; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); ac97_warn(ac97, "AC'97 %d analog subsections not ready\n", ac97->num); } /* FIXME: add powerdown control */ if (ac97_is_modem(ac97)) { unsigned char tmp; /* nothing should be in powerdown mode */ /* note: it's important to set the rate at first */ tmp = AC97_MEA_GPIO; if (ac97->ext_mid & AC97_MEI_LINE1) { snd_ac97_write_cache(ac97, AC97_LINE1_RATE, 8000); tmp |= AC97_MEA_ADC1 | AC97_MEA_DAC1; } if (ac97->ext_mid & AC97_MEI_LINE2) { snd_ac97_write_cache(ac97, AC97_LINE2_RATE, 8000); tmp |= AC97_MEA_ADC2 | AC97_MEA_DAC2; } if (ac97->ext_mid & AC97_MEI_HANDSET) { snd_ac97_write_cache(ac97, AC97_HANDSET_RATE, 8000); tmp |= AC97_MEA_HADC | AC97_MEA_HDAC; } snd_ac97_write_cache(ac97, AC97_EXTENDED_MSTATUS, 0); udelay(100); /* nothing should be in powerdown mode */ snd_ac97_write_cache(ac97, AC97_EXTENDED_MSTATUS, 0); end_time = jiffies + msecs_to_jiffies(100); do { if ((snd_ac97_read(ac97, AC97_EXTENDED_MSTATUS) & tmp) == tmp) goto __ready_ok; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); ac97_warn(ac97, "MC'97 %d converters and GPIO not ready (0x%x)\n", ac97->num, snd_ac97_read(ac97, AC97_EXTENDED_MSTATUS)); } __ready_ok: if (ac97_is_audio(ac97)) ac97->addr = (ac97->ext_id & AC97_EI_ADDR_MASK) >> AC97_EI_ADDR_SHIFT; else ac97->addr = (ac97->ext_mid & AC97_MEI_ADDR_MASK) >> AC97_MEI_ADDR_SHIFT; if (ac97->ext_id & 0x01c9) { /* L/R, MIC, SDAC, LDAC VRA support */ reg = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); reg |= ac97->ext_id & 0x01c0; /* LDAC/SDAC/CDAC */ if (! bus->no_vra) reg |= ac97->ext_id & 0x0009; /* VRA/VRM */ snd_ac97_write_cache(ac97, AC97_EXTENDED_STATUS, reg); } if ((ac97->ext_id & AC97_EI_DRA) && bus->dra) { /* Intel controllers require double rate data to be put in * slots 7+8, so let's hope the codec supports it. */ snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, AC97_GP_DRSS_MASK, AC97_GP_DRSS_78); if ((snd_ac97_read(ac97, AC97_GENERAL_PURPOSE) & AC97_GP_DRSS_MASK) == AC97_GP_DRSS_78) ac97->flags |= AC97_DOUBLE_RATE; /* restore to slots 10/11 to avoid the confliction with surrounds */ snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, AC97_GP_DRSS_MASK, 0); } if (ac97->ext_id & AC97_EI_VRA) { /* VRA support */ snd_ac97_determine_rates(ac97, AC97_PCM_FRONT_DAC_RATE, 0, &ac97->rates[AC97_RATES_FRONT_DAC]); snd_ac97_determine_rates(ac97, AC97_PCM_LR_ADC_RATE, 0, &ac97->rates[AC97_RATES_ADC]); } else { ac97->rates[AC97_RATES_FRONT_DAC] = SNDRV_PCM_RATE_48000; if (ac97->flags & AC97_DOUBLE_RATE) ac97->rates[AC97_RATES_FRONT_DAC] |= SNDRV_PCM_RATE_96000; ac97->rates[AC97_RATES_ADC] = SNDRV_PCM_RATE_48000; } if (ac97->ext_id & AC97_EI_SPDIF) { /* codec specific code (patch) should override these values */ ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_32000; } if (ac97->ext_id & AC97_EI_VRM) { /* MIC VRA support */ snd_ac97_determine_rates(ac97, AC97_PCM_MIC_ADC_RATE, 0, &ac97->rates[AC97_RATES_MIC_ADC]); } else { ac97->rates[AC97_RATES_MIC_ADC] = SNDRV_PCM_RATE_48000; } if (ac97->ext_id & AC97_EI_SDAC) { /* SDAC support */ snd_ac97_determine_rates(ac97, AC97_PCM_SURR_DAC_RATE, AC97_PCM_FRONT_DAC_RATE, &ac97->rates[AC97_RATES_SURR_DAC]); ac97->scaps |= AC97_SCAP_SURROUND_DAC; } if (ac97->ext_id & AC97_EI_LDAC) { /* LDAC support */ snd_ac97_determine_rates(ac97, AC97_PCM_LFE_DAC_RATE, AC97_PCM_FRONT_DAC_RATE, &ac97->rates[AC97_RATES_LFE_DAC]); ac97->scaps |= AC97_SCAP_CENTER_LFE_DAC; } /* additional initializations */ if (bus->ops->init) bus->ops->init(ac97); snd_ac97_get_name(ac97, ac97->id, name, !ac97_is_audio(ac97)); snd_ac97_get_name(NULL, ac97->id, name, !ac97_is_audio(ac97)); // ac97->id might be changed in the special setup code if (! ac97->build_ops) ac97->build_ops = &null_build_ops; if (ac97_is_audio(ac97)) { char comp[16]; if (card->mixername[0] == '\0') { strcpy(card->mixername, name); } else { if (strlen(card->mixername) + 1 + strlen(name) + 1 <= sizeof(card->mixername)) { strcat(card->mixername, ","); strcat(card->mixername, name); } } sprintf(comp, "AC97a:%08x", ac97->id); err = snd_component_add(card, comp); if (err < 0) { snd_ac97_free(ac97); return err; } if (snd_ac97_mixer_build(ac97) < 0) { snd_ac97_free(ac97); return -ENOMEM; } } if (ac97_is_modem(ac97)) { char comp[16]; if (card->mixername[0] == '\0') { strcpy(card->mixername, name); } else { if (strlen(card->mixername) + 1 + strlen(name) + 1 <= sizeof(card->mixername)) { strcat(card->mixername, ","); strcat(card->mixername, name); } } sprintf(comp, "AC97m:%08x", ac97->id); err = snd_component_add(card, comp); if (err < 0) { snd_ac97_free(ac97); return err; } if (snd_ac97_modem_build(card, ac97) < 0) { snd_ac97_free(ac97); return -ENOMEM; } } if (ac97_is_audio(ac97)) update_power_regs(ac97); snd_ac97_proc_init(ac97); err = snd_device_new(card, SNDRV_DEV_CODEC, ac97, &ops); if (err < 0) { snd_ac97_free(ac97); return err; } *rac97 = ac97; return 0; } EXPORT_SYMBOL(snd_ac97_mixer); /* * Power down the chip. * * MASTER and HEADPHONE registers are muted but the register cache values * are not changed, so that the values can be restored in snd_ac97_resume(). */ static void snd_ac97_powerdown(struct snd_ac97 *ac97) { unsigned short power; if (ac97_is_audio(ac97)) { /* some codecs have stereo mute bits */ snd_ac97_write(ac97, AC97_MASTER, 0x9f9f); snd_ac97_write(ac97, AC97_HEADPHONE, 0x9f9f); } /* surround, CLFE, mic powerdown */ power = ac97->regs[AC97_EXTENDED_STATUS]; if (ac97->scaps & AC97_SCAP_SURROUND_DAC) power |= AC97_EA_PRJ; if (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC) power |= AC97_EA_PRI | AC97_EA_PRK; power |= AC97_EA_PRL; snd_ac97_write(ac97, AC97_EXTENDED_STATUS, power); /* powerdown external amplifier */ if (ac97->scaps & AC97_SCAP_INV_EAPD) power = ac97->regs[AC97_POWERDOWN] & ~AC97_PD_EAPD; else if (! (ac97->scaps & AC97_SCAP_EAPD_LED)) power = ac97->regs[AC97_POWERDOWN] | AC97_PD_EAPD; power |= AC97_PD_PR6; /* Headphone amplifier powerdown */ power |= AC97_PD_PR0 | AC97_PD_PR1; /* ADC & DAC powerdown */ snd_ac97_write(ac97, AC97_POWERDOWN, power); udelay(100); power |= AC97_PD_PR2; /* Analog Mixer powerdown (Vref on) */ snd_ac97_write(ac97, AC97_POWERDOWN, power); if (ac97_is_power_save_mode(ac97)) { power |= AC97_PD_PR3; /* Analog Mixer powerdown */ snd_ac97_write(ac97, AC97_POWERDOWN, power); udelay(100); /* AC-link powerdown, internal Clk disable */ /* FIXME: this may cause click noises on some boards */ power |= AC97_PD_PR4 | AC97_PD_PR5; snd_ac97_write(ac97, AC97_POWERDOWN, power); } } struct ac97_power_reg { unsigned short reg; unsigned short power_reg; unsigned short mask; }; enum { PWIDX_ADC, PWIDX_FRONT, PWIDX_CLFE, PWIDX_SURR, PWIDX_MIC, PWIDX_SIZE }; static const struct ac97_power_reg power_regs[PWIDX_SIZE] = { [PWIDX_ADC] = { AC97_PCM_LR_ADC_RATE, AC97_POWERDOWN, AC97_PD_PR0}, [PWIDX_FRONT] = { AC97_PCM_FRONT_DAC_RATE, AC97_POWERDOWN, AC97_PD_PR1}, [PWIDX_CLFE] = { AC97_PCM_LFE_DAC_RATE, AC97_EXTENDED_STATUS, AC97_EA_PRI | AC97_EA_PRK}, [PWIDX_SURR] = { AC97_PCM_SURR_DAC_RATE, AC97_EXTENDED_STATUS, AC97_EA_PRJ}, [PWIDX_MIC] = { AC97_PCM_MIC_ADC_RATE, AC97_EXTENDED_STATUS, AC97_EA_PRL}, }; #ifdef CONFIG_SND_AC97_POWER_SAVE /** * snd_ac97_update_power - update the powerdown register * @ac97: the codec instance * @reg: the rate register, e.g. AC97_PCM_FRONT_DAC_RATE * @powerup: non-zero when power up the part * * Update the AC97 powerdown register bits of the given part. * * Return: Zero. */ int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup) { int i; if (! ac97) return 0; if (reg) { /* SPDIF requires DAC power, too */ if (reg == AC97_SPDIF) reg = AC97_PCM_FRONT_DAC_RATE; for (i = 0; i < PWIDX_SIZE; i++) { if (power_regs[i].reg == reg) { if (powerup) ac97->power_up |= (1 << i); else ac97->power_up &= ~(1 << i); break; } } } if (ac97_is_power_save_mode(ac97) && !powerup) /* adjust power-down bits after two seconds delay * (for avoiding loud click noises for many (OSS) apps * that open/close frequently) */ schedule_delayed_work(&ac97->power_work, msecs_to_jiffies(power_save * 1000)); else { cancel_delayed_work(&ac97->power_work); update_power_regs(ac97); } return 0; } EXPORT_SYMBOL(snd_ac97_update_power); #endif /* CONFIG_SND_AC97_POWER_SAVE */ static void update_power_regs(struct snd_ac97 *ac97) { unsigned int power_up, bits; int i; power_up = (1 << PWIDX_FRONT) | (1 << PWIDX_ADC); power_up |= (1 << PWIDX_MIC); if (ac97->scaps & AC97_SCAP_SURROUND_DAC) power_up |= (1 << PWIDX_SURR); if (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC) power_up |= (1 << PWIDX_CLFE); #ifdef CONFIG_SND_AC97_POWER_SAVE if (ac97_is_power_save_mode(ac97)) power_up = ac97->power_up; #endif if (power_up) { if (ac97->regs[AC97_POWERDOWN] & AC97_PD_PR2) { /* needs power-up analog mix and vref */ snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_PR3, 0); msleep(1); snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_PR2, 0); } } for (i = 0; i < PWIDX_SIZE; i++) { if (power_up & (1 << i)) bits = 0; else bits = power_regs[i].mask; snd_ac97_update_bits(ac97, power_regs[i].power_reg, power_regs[i].mask, bits); } if (! power_up) { if (! (ac97->regs[AC97_POWERDOWN] & AC97_PD_PR2)) { /* power down analog mix and vref */ snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_PR2, AC97_PD_PR2); snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_PR3, AC97_PD_PR3); } } } #ifdef CONFIG_PM /** * snd_ac97_suspend - General suspend function for AC97 codec * @ac97: the ac97 instance * * Suspends the codec, power down the chip. */ void snd_ac97_suspend(struct snd_ac97 *ac97) { if (! ac97) return; if (ac97->build_ops->suspend) ac97->build_ops->suspend(ac97); #ifdef CONFIG_SND_AC97_POWER_SAVE cancel_delayed_work_sync(&ac97->power_work); #endif snd_ac97_powerdown(ac97); } EXPORT_SYMBOL(snd_ac97_suspend); /* * restore ac97 status */ static void snd_ac97_restore_status(struct snd_ac97 *ac97) { int i; for (i = 2; i < 0x7c ; i += 2) { if (i == AC97_POWERDOWN || i == AC97_EXTENDED_ID) continue; /* restore only accessible registers * some chip (e.g. nm256) may hang up when unsupported registers * are accessed..! */ if (test_bit(i, ac97->reg_accessed)) { snd_ac97_write(ac97, i, ac97->regs[i]); snd_ac97_read(ac97, i); } } } /* * restore IEC958 status */ static void snd_ac97_restore_iec958(struct snd_ac97 *ac97) { if (ac97->ext_id & AC97_EI_SPDIF) { if (ac97->regs[AC97_EXTENDED_STATUS] & AC97_EA_SPDIF) { /* reset spdif status */ snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); snd_ac97_write(ac97, AC97_EXTENDED_STATUS, ac97->regs[AC97_EXTENDED_STATUS]); if (ac97->flags & AC97_CS_SPDIF) snd_ac97_write(ac97, AC97_CSR_SPDIF, ac97->regs[AC97_CSR_SPDIF]); else snd_ac97_write(ac97, AC97_SPDIF, ac97->regs[AC97_SPDIF]); snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, AC97_EA_SPDIF); /* turn on again */ } } } /** * snd_ac97_resume - General resume function for AC97 codec * @ac97: the ac97 instance * * Do the standard resume procedure, power up and restoring the * old register values. */ void snd_ac97_resume(struct snd_ac97 *ac97) { unsigned long end_time; if (! ac97) return; if (ac97->bus->ops->reset) { ac97->bus->ops->reset(ac97); goto __reset_ready; } snd_ac97_write(ac97, AC97_POWERDOWN, 0); if (! (ac97->flags & AC97_DEFAULT_POWER_OFF)) { if (!(ac97->scaps & AC97_SCAP_SKIP_AUDIO)) snd_ac97_write(ac97, AC97_RESET, 0); else if (!(ac97->scaps & AC97_SCAP_SKIP_MODEM)) snd_ac97_write(ac97, AC97_EXTENDED_MID, 0); udelay(100); snd_ac97_write(ac97, AC97_POWERDOWN, 0); } snd_ac97_write(ac97, AC97_GENERAL_PURPOSE, 0); snd_ac97_write(ac97, AC97_POWERDOWN, ac97->regs[AC97_POWERDOWN]); if (ac97_is_audio(ac97)) { ac97->bus->ops->write(ac97, AC97_MASTER, 0x8101); end_time = jiffies + msecs_to_jiffies(100); do { if (snd_ac97_read(ac97, AC97_MASTER) == 0x8101) break; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); /* FIXME: extra delay */ ac97->bus->ops->write(ac97, AC97_MASTER, AC97_MUTE_MASK_MONO); if (snd_ac97_read(ac97, AC97_MASTER) != AC97_MUTE_MASK_MONO) msleep(250); } else { end_time = jiffies + msecs_to_jiffies(100); do { unsigned short val = snd_ac97_read(ac97, AC97_EXTENDED_MID); if (val != 0xffff && (val & 1) != 0) break; schedule_timeout_uninterruptible(1); } while (time_after_eq(end_time, jiffies)); } __reset_ready: if (ac97->bus->ops->init) ac97->bus->ops->init(ac97); if (ac97->build_ops->resume) ac97->build_ops->resume(ac97); else { snd_ac97_restore_status(ac97); snd_ac97_restore_iec958(ac97); } } EXPORT_SYMBOL(snd_ac97_resume); #endif /* * Hardware tuning */ static void set_ctl_name(char *dst, const char *src, const char *suffix) { const size_t msize = SNDRV_CTL_ELEM_ID_NAME_MAXLEN; if (suffix) { if (snprintf(dst, msize, "%s %s", src, suffix) >= msize) pr_warn("ALSA: AC97 control name '%s %s' truncated to '%s'\n", src, suffix, dst); } else { if (strscpy(dst, src, msize) < 0) pr_warn("ALSA: AC97 control name '%s' truncated to '%s'\n", src, dst); } } /* remove the control with the given name and optional suffix */ static int snd_ac97_remove_ctl(struct snd_ac97 *ac97, const char *name, const char *suffix) { struct snd_ctl_elem_id id; memset(&id, 0, sizeof(id)); set_ctl_name(id.name, name, suffix); id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; return snd_ctl_remove_id(ac97->bus->card, &id); } static struct snd_kcontrol *ctl_find(struct snd_ac97 *ac97, const char *name, const char *suffix) { struct snd_ctl_elem_id sid; memset(&sid, 0, sizeof(sid)); set_ctl_name(sid.name, name, suffix); sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER; return snd_ctl_find_id(ac97->bus->card, &sid); } /* rename the control with the given name and optional suffix */ static int snd_ac97_rename_ctl(struct snd_ac97 *ac97, const char *src, const char *dst, const char *suffix) { struct snd_kcontrol *kctl = ctl_find(ac97, src, suffix); char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; if (kctl) { set_ctl_name(name, dst, suffix); snd_ctl_rename(ac97->bus->card, kctl, name); return 0; } return -ENOENT; } /* rename both Volume and Switch controls - don't check the return value */ static void snd_ac97_rename_vol_ctl(struct snd_ac97 *ac97, const char *src, const char *dst) { snd_ac97_rename_ctl(ac97, src, dst, "Switch"); snd_ac97_rename_ctl(ac97, src, dst, "Volume"); } /* swap controls */ static int snd_ac97_swap_ctl(struct snd_ac97 *ac97, const char *s1, const char *s2, const char *suffix) { struct snd_kcontrol *kctl1, *kctl2; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; kctl1 = ctl_find(ac97, s1, suffix); kctl2 = ctl_find(ac97, s2, suffix); if (kctl1 && kctl2) { set_ctl_name(name, s2, suffix); snd_ctl_rename(ac97->bus->card, kctl1, name); set_ctl_name(name, s1, suffix); snd_ctl_rename(ac97->bus->card, kctl2, name); return 0; } return -ENOENT; } #if 1 /* bind hp and master controls instead of using only hp control */ static int bind_hp_volsw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int err = snd_ac97_put_volsw(kcontrol, ucontrol); if (err > 0) { unsigned long priv_saved = kcontrol->private_value; kcontrol->private_value = (kcontrol->private_value & ~0xff) | AC97_HEADPHONE; snd_ac97_put_volsw(kcontrol, ucontrol); kcontrol->private_value = priv_saved; } return err; } /* ac97 tune: bind Master and Headphone controls */ static int tune_hp_only(struct snd_ac97 *ac97) { struct snd_kcontrol *msw = ctl_find(ac97, "Master Playback Switch", NULL); struct snd_kcontrol *mvol = ctl_find(ac97, "Master Playback Volume", NULL); if (! msw || ! mvol) return -ENOENT; msw->put = bind_hp_volsw_put; mvol->put = bind_hp_volsw_put; snd_ac97_remove_ctl(ac97, "Headphone Playback", "Switch"); snd_ac97_remove_ctl(ac97, "Headphone Playback", "Volume"); return 0; } #else /* ac97 tune: use Headphone control as master */ static int tune_hp_only(struct snd_ac97 *ac97) { if (ctl_find(ac97, "Headphone Playback Switch", NULL) == NULL) return -ENOENT; snd_ac97_remove_ctl(ac97, "Master Playback", "Switch"); snd_ac97_remove_ctl(ac97, "Master Playback", "Volume"); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Master Playback"); return 0; } #endif /* ac97 tune: swap Headphone and Master controls */ static int tune_swap_hp(struct snd_ac97 *ac97) { if (ctl_find(ac97, "Headphone Playback Switch", NULL) == NULL) return -ENOENT; snd_ac97_rename_vol_ctl(ac97, "Master Playback", "Line-Out Playback"); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Master Playback"); return 0; } /* ac97 tune: swap Surround and Master controls */ static int tune_swap_surround(struct snd_ac97 *ac97) { if (snd_ac97_swap_ctl(ac97, "Master Playback", "Surround Playback", "Switch") || snd_ac97_swap_ctl(ac97, "Master Playback", "Surround Playback", "Volume")) return -ENOENT; return 0; } /* ac97 tune: set up mic sharing for AD codecs */ static int tune_ad_sharing(struct snd_ac97 *ac97) { unsigned short scfg; if ((ac97->id & 0xffffff00) != 0x41445300) { ac97_err(ac97, "ac97_quirk AD_SHARING is only for AD codecs\n"); return -EINVAL; } /* Turn on OMS bit to route microphone to back panel */ scfg = snd_ac97_read(ac97, AC97_AD_SERIAL_CFG); snd_ac97_write_cache(ac97, AC97_AD_SERIAL_CFG, scfg | 0x0200); return 0; } static const struct snd_kcontrol_new snd_ac97_alc_jack_detect = AC97_SINGLE("Jack Detect", AC97_ALC650_CLOCK, 5, 1, 0); /* ac97 tune: set up ALC jack-select */ static int tune_alc_jack(struct snd_ac97 *ac97) { if ((ac97->id & 0xffffff00) != 0x414c4700) { ac97_err(ac97, "ac97_quirk ALC_JACK is only for Realtek codecs\n"); return -EINVAL; } snd_ac97_update_bits(ac97, 0x7a, 0x20, 0x20); /* select jack detect function */ snd_ac97_update_bits(ac97, 0x7a, 0x01, 0x01); /* Line-out auto mute */ if (ac97->id == AC97_ID_ALC658D) snd_ac97_update_bits(ac97, 0x74, 0x0800, 0x0800); return snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&snd_ac97_alc_jack_detect, ac97)); } /* ac97 tune: inversed EAPD bit */ static int tune_inv_eapd(struct snd_ac97 *ac97) { struct snd_kcontrol *kctl = ctl_find(ac97, "External Amplifier", NULL); if (! kctl) return -ENOENT; set_inv_eapd(ac97, kctl); return 0; } static int master_mute_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int err = snd_ac97_put_volsw(kcontrol, ucontrol); if (err > 0) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; unsigned short mask; if (shift != rshift) mask = AC97_MUTE_MASK_STEREO; else mask = AC97_MUTE_MASK_MONO; snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_EAPD, (ac97->regs[AC97_MASTER] & mask) == mask ? AC97_PD_EAPD : 0); } return err; } /* ac97 tune: EAPD controls mute LED bound with the master mute */ static int tune_mute_led(struct snd_ac97 *ac97) { struct snd_kcontrol *msw = ctl_find(ac97, "Master Playback Switch", NULL); if (! msw) return -ENOENT; msw->put = master_mute_sw_put; snd_ac97_remove_ctl(ac97, "External Amplifier", NULL); snd_ac97_update_bits( ac97, AC97_POWERDOWN, AC97_PD_EAPD, AC97_PD_EAPD /* mute LED on */ ); ac97->scaps |= AC97_SCAP_EAPD_LED; return 0; } static int hp_master_mute_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int err = bind_hp_volsw_put(kcontrol, ucontrol); if (err > 0) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = (kcontrol->private_value >> 8) & 0x0f; int rshift = (kcontrol->private_value >> 12) & 0x0f; unsigned short mask; if (shift != rshift) mask = AC97_MUTE_MASK_STEREO; else mask = AC97_MUTE_MASK_MONO; snd_ac97_update_bits(ac97, AC97_POWERDOWN, AC97_PD_EAPD, (ac97->regs[AC97_MASTER] & mask) == mask ? AC97_PD_EAPD : 0); } return err; } static int tune_hp_mute_led(struct snd_ac97 *ac97) { struct snd_kcontrol *msw = ctl_find(ac97, "Master Playback Switch", NULL); struct snd_kcontrol *mvol = ctl_find(ac97, "Master Playback Volume", NULL); if (! msw || ! mvol) return -ENOENT; msw->put = hp_master_mute_sw_put; mvol->put = bind_hp_volsw_put; snd_ac97_remove_ctl(ac97, "External Amplifier", NULL); snd_ac97_remove_ctl(ac97, "Headphone Playback", "Switch"); snd_ac97_remove_ctl(ac97, "Headphone Playback", "Volume"); snd_ac97_update_bits( ac97, AC97_POWERDOWN, AC97_PD_EAPD, AC97_PD_EAPD /* mute LED on */ ); return 0; } struct quirk_table { const char *name; int (*func)(struct snd_ac97 *); }; static const struct quirk_table applicable_quirks[] = { { "none", NULL }, { "hp_only", tune_hp_only }, { "swap_hp", tune_swap_hp }, { "swap_surround", tune_swap_surround }, { "ad_sharing", tune_ad_sharing }, { "alc_jack", tune_alc_jack }, { "inv_eapd", tune_inv_eapd }, { "mute_led", tune_mute_led }, { "hp_mute_led", tune_hp_mute_led }, }; /* apply the quirk with the given type */ static int apply_quirk(struct snd_ac97 *ac97, int type) { if (type <= 0) return 0; else if (type >= ARRAY_SIZE(applicable_quirks)) return -EINVAL; if (applicable_quirks[type].func) return applicable_quirks[type].func(ac97); return 0; } /* apply the quirk with the given name */ static int apply_quirk_str(struct snd_ac97 *ac97, const char *typestr) { int i; const struct quirk_table *q; for (i = 0; i < ARRAY_SIZE(applicable_quirks); i++) { q = &applicable_quirks[i]; if (q->name && ! strcmp(typestr, q->name)) return apply_quirk(ac97, i); } /* for compatibility, accept the numbers, too */ if (*typestr >= '0' && *typestr <= '9') return apply_quirk(ac97, (int)simple_strtoul(typestr, NULL, 10)); return -EINVAL; } /** * snd_ac97_tune_hardware - tune up the hardware * @ac97: the ac97 instance * @quirk: quirk list * @override: explicit quirk value (overrides the list if non-NULL) * * Do some workaround for each pci device, such as renaming of the * headphone (true line-out) control as "Master". * The quirk-list must be terminated with a zero-filled entry. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_tune_hardware(struct snd_ac97 *ac97, const struct ac97_quirk *quirk, const char *override) { int result; /* quirk overriden? */ if (override && strcmp(override, "-1") && strcmp(override, "default")) { result = apply_quirk_str(ac97, override); if (result < 0) ac97_err(ac97, "applying quirk type %s failed (%d)\n", override, result); return result; } if (! quirk) return -EINVAL; for (; quirk->subvendor; quirk++) { if (quirk->subvendor != ac97->subsystem_vendor) continue; if ((! quirk->mask && quirk->subdevice == ac97->subsystem_device) || quirk->subdevice == (quirk->mask & ac97->subsystem_device)) { if (quirk->codec_id && quirk->codec_id != ac97->id) continue; ac97_dbg(ac97, "ac97 quirk for %s (%04x:%04x)\n", quirk->name, ac97->subsystem_vendor, ac97->subsystem_device); result = apply_quirk(ac97, quirk->type); if (result < 0) ac97_err(ac97, "applying quirk type %d for %s failed (%d)\n", quirk->type, quirk->name, result); return result; } } return 0; } EXPORT_SYMBOL(snd_ac97_tune_hardware);
linux-master
sound/pci/ac97/ac97_codec.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Universal interface for Audio Codec '97 * * For more details look to AC '97 component specification revision 2.2 * by Intel Corporation (http://developer.intel.com) and to datasheets * for specific codecs. */ #include "ac97_local.h" #include "ac97_patch.h" /* * Forward declarations */ static struct snd_kcontrol *snd_ac97_find_mixer_ctl(struct snd_ac97 *ac97, const char *name); static int snd_ac97_add_vmaster(struct snd_ac97 *ac97, char *name, const unsigned int *tlv, const char * const *followers); /* * Chip specific initialization */ static int patch_build_controls(struct snd_ac97 * ac97, const struct snd_kcontrol_new *controls, int count) { int idx, err; for (idx = 0; idx < count; idx++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&controls[idx], ac97)); if (err < 0) return err; } return 0; } /* replace with a new TLV */ static void reset_tlv(struct snd_ac97 *ac97, const char *name, const unsigned int *tlv) { struct snd_ctl_elem_id sid; struct snd_kcontrol *kctl; memset(&sid, 0, sizeof(sid)); strcpy(sid.name, name); sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER; kctl = snd_ctl_find_id(ac97->bus->card, &sid); if (kctl && kctl->tlv.p) kctl->tlv.p = tlv; } /* set to the page, update bits and restore the page */ static int ac97_update_bits_page(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value, unsigned short page) { unsigned short page_save; int ret; mutex_lock(&ac97->page_mutex); page_save = snd_ac97_read(ac97, AC97_INT_PAGING) & AC97_PAGE_MASK; snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, page); ret = snd_ac97_update_bits(ac97, reg, mask, value); snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, page_save); mutex_unlock(&ac97->page_mutex); /* unlock paging */ return ret; } /* * shared line-in/mic controls */ static int ac97_surround_jack_mode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[] = { "Shared", "Independent" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int ac97_surround_jack_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = ac97->indep_surround; return 0; } static int ac97_surround_jack_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned char indep = !!ucontrol->value.enumerated.item[0]; if (indep != ac97->indep_surround) { ac97->indep_surround = indep; if (ac97->build_ops->update_jacks) ac97->build_ops->update_jacks(ac97); return 1; } return 0; } static int ac97_channel_mode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[] = { "2ch", "4ch", "6ch", "8ch" }; return snd_ctl_enum_info(uinfo, 1, kcontrol->private_value, texts); } static int ac97_channel_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = ac97->channel_mode; return 0; } static int ac97_channel_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned char mode = ucontrol->value.enumerated.item[0]; if (mode >= kcontrol->private_value) return -EINVAL; if (mode != ac97->channel_mode) { ac97->channel_mode = mode; if (ac97->build_ops->update_jacks) ac97->build_ops->update_jacks(ac97); return 1; } return 0; } #define AC97_SURROUND_JACK_MODE_CTL \ { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = "Surround Jack Mode", \ .info = ac97_surround_jack_mode_info, \ .get = ac97_surround_jack_mode_get, \ .put = ac97_surround_jack_mode_put, \ } /* 6ch */ #define AC97_CHANNEL_MODE_CTL \ { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = "Channel Mode", \ .info = ac97_channel_mode_info, \ .get = ac97_channel_mode_get, \ .put = ac97_channel_mode_put, \ .private_value = 3, \ } /* 4ch */ #define AC97_CHANNEL_MODE_4CH_CTL \ { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = "Channel Mode", \ .info = ac97_channel_mode_info, \ .get = ac97_channel_mode_get, \ .put = ac97_channel_mode_put, \ .private_value = 2, \ } /* 8ch */ #define AC97_CHANNEL_MODE_8CH_CTL \ { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = "Channel Mode", \ .info = ac97_channel_mode_info, \ .get = ac97_channel_mode_get, \ .put = ac97_channel_mode_put, \ .private_value = 4, \ } static inline int is_surround_on(struct snd_ac97 *ac97) { return ac97->channel_mode >= 1; } static inline int is_clfe_on(struct snd_ac97 *ac97) { return ac97->channel_mode >= 2; } /* system has shared jacks with surround out enabled */ static inline int is_shared_surrout(struct snd_ac97 *ac97) { return !ac97->indep_surround && is_surround_on(ac97); } /* system has shared jacks with center/lfe out enabled */ static inline int is_shared_clfeout(struct snd_ac97 *ac97) { return !ac97->indep_surround && is_clfe_on(ac97); } /* system has shared jacks with line in enabled */ static inline int is_shared_linein(struct snd_ac97 *ac97) { return !ac97->indep_surround && !is_surround_on(ac97); } /* system has shared jacks with mic in enabled */ static inline int is_shared_micin(struct snd_ac97 *ac97) { return !ac97->indep_surround && !is_clfe_on(ac97); } static inline int alc850_is_aux_back_surround(struct snd_ac97 *ac97) { return is_surround_on(ac97); } /* The following snd_ac97_ymf753_... items added by David Shust ([email protected]) */ /* Modified for YMF743 by Keita Maehara <[email protected]> */ /* It is possible to indicate to the Yamaha YMF7x3 the type of speakers being used. */ static int snd_ac97_ymf7x3_info_speaker(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[3] = { "Standard", "Small", "Smaller" }; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int snd_ac97_ymf7x3_get_speaker(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_YMF7X3_3D_MODE_SEL]; val = (val >> 10) & 3; if (val > 0) /* 0 = invalid */ val--; ucontrol->value.enumerated.item[0] = val; return 0; } static int snd_ac97_ymf7x3_put_speaker(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 2) return -EINVAL; val = (ucontrol->value.enumerated.item[0] + 1) << 10; return snd_ac97_update(ac97, AC97_YMF7X3_3D_MODE_SEL, val); } static const struct snd_kcontrol_new snd_ac97_ymf7x3_controls_speaker = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "3D Control - Speaker", .info = snd_ac97_ymf7x3_info_speaker, .get = snd_ac97_ymf7x3_get_speaker, .put = snd_ac97_ymf7x3_put_speaker, }; /* It is possible to indicate to the Yamaha YMF7x3 the source to direct to the S/PDIF output. */ static int snd_ac97_ymf7x3_spdif_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[2] = { "AC-Link", "A/D Converter" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int snd_ac97_ymf7x3_spdif_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_YMF7X3_DIT_CTRL]; ucontrol->value.enumerated.item[0] = (val >> 1) & 1; return 0; } static int snd_ac97_ymf7x3_spdif_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 1) return -EINVAL; val = ucontrol->value.enumerated.item[0] << 1; return snd_ac97_update_bits(ac97, AC97_YMF7X3_DIT_CTRL, 0x0002, val); } static int patch_yamaha_ymf7x3_3d(struct snd_ac97 *ac97) { struct snd_kcontrol *kctl; int err; kctl = snd_ac97_cnew(&snd_ac97_controls_3d[0], ac97); err = snd_ctl_add(ac97->bus->card, kctl); if (err < 0) return err; strcpy(kctl->id.name, "3D Control - Wide"); kctl->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 9, 7, 0); snd_ac97_write_cache(ac97, AC97_3D_CONTROL, 0x0000); err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&snd_ac97_ymf7x3_controls_speaker, ac97)); if (err < 0) return err; snd_ac97_write_cache(ac97, AC97_YMF7X3_3D_MODE_SEL, 0x0c00); return 0; } static const struct snd_kcontrol_new snd_ac97_yamaha_ymf743_controls_spdif[3] = { AC97_SINGLE(SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), AC97_YMF7X3_DIT_CTRL, 0, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Source", .info = snd_ac97_ymf7x3_spdif_source_info, .get = snd_ac97_ymf7x3_spdif_source_get, .put = snd_ac97_ymf7x3_spdif_source_put, }, AC97_SINGLE(SNDRV_CTL_NAME_IEC958("", NONE, NONE) "Mute", AC97_YMF7X3_DIT_CTRL, 2, 1, 1) }; static int patch_yamaha_ymf743_build_spdif(struct snd_ac97 *ac97) { int err; err = patch_build_controls(ac97, &snd_ac97_controls_spdif[0], 3); if (err < 0) return err; err = patch_build_controls(ac97, snd_ac97_yamaha_ymf743_controls_spdif, 3); if (err < 0) return err; /* set default PCM S/PDIF params */ /* PCM audio,no copyright,no preemphasis,PCM coder,original */ snd_ac97_write_cache(ac97, AC97_YMF7X3_DIT_CTRL, 0xa201); return 0; } static const struct snd_ac97_build_ops patch_yamaha_ymf743_ops = { .build_spdif = patch_yamaha_ymf743_build_spdif, .build_3d = patch_yamaha_ymf7x3_3d, }; static int patch_yamaha_ymf743(struct snd_ac97 *ac97) { ac97->build_ops = &patch_yamaha_ymf743_ops; ac97->caps |= AC97_BC_BASS_TREBLE; ac97->caps |= 0x04 << 10; /* Yamaha 3D enhancement */ ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000; /* 48k only */ ac97->ext_id |= AC97_EI_SPDIF; /* force the detection of spdif */ return 0; } /* The AC'97 spec states that the S/PDIF signal is to be output at pin 48. The YMF753 will output the S/PDIF signal to pin 43, 47 (EAPD), or 48. By default, no output pin is selected, and the S/PDIF signal is not output. There is also a bit to mute S/PDIF output in a vendor-specific register. */ static int snd_ac97_ymf753_spdif_output_pin_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[3] = { "Disabled", "Pin 43", "Pin 48" }; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int snd_ac97_ymf753_spdif_output_pin_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_YMF7X3_DIT_CTRL]; ucontrol->value.enumerated.item[0] = (val & 0x0008) ? 2 : (val & 0x0020) ? 1 : 0; return 0; } static int snd_ac97_ymf753_spdif_output_pin_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 2) return -EINVAL; val = (ucontrol->value.enumerated.item[0] == 2) ? 0x0008 : (ucontrol->value.enumerated.item[0] == 1) ? 0x0020 : 0; return snd_ac97_update_bits(ac97, AC97_YMF7X3_DIT_CTRL, 0x0028, val); /* The following can be used to direct S/PDIF output to pin 47 (EAPD). snd_ac97_write_cache(ac97, 0x62, snd_ac97_read(ac97, 0x62) | 0x0008); */ } static const struct snd_kcontrol_new snd_ac97_ymf753_controls_spdif[3] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Source", .info = snd_ac97_ymf7x3_spdif_source_info, .get = snd_ac97_ymf7x3_spdif_source_get, .put = snd_ac97_ymf7x3_spdif_source_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Output Pin", .info = snd_ac97_ymf753_spdif_output_pin_info, .get = snd_ac97_ymf753_spdif_output_pin_get, .put = snd_ac97_ymf753_spdif_output_pin_put, }, AC97_SINGLE(SNDRV_CTL_NAME_IEC958("", NONE, NONE) "Mute", AC97_YMF7X3_DIT_CTRL, 2, 1, 1) }; static int patch_yamaha_ymf753_post_spdif(struct snd_ac97 * ac97) { int err; err = patch_build_controls(ac97, snd_ac97_ymf753_controls_spdif, ARRAY_SIZE(snd_ac97_ymf753_controls_spdif)); if (err < 0) return err; return 0; } static const struct snd_ac97_build_ops patch_yamaha_ymf753_ops = { .build_3d = patch_yamaha_ymf7x3_3d, .build_post_spdif = patch_yamaha_ymf753_post_spdif }; static int patch_yamaha_ymf753(struct snd_ac97 * ac97) { /* Patch for Yamaha YMF753, Copyright (c) by David Shust, [email protected]. This chip has nonstandard and extended behaviour with regard to its S/PDIF output. The AC'97 spec states that the S/PDIF signal is to be output at pin 48. The YMF753 will ouput the S/PDIF signal to pin 43, 47 (EAPD), or 48. By default, no output pin is selected, and the S/PDIF signal is not output. There is also a bit to mute S/PDIF output in a vendor-specific register. */ ac97->build_ops = &patch_yamaha_ymf753_ops; ac97->caps |= AC97_BC_BASS_TREBLE; ac97->caps |= 0x04 << 10; /* Yamaha 3D enhancement */ return 0; } /* * May 2, 2003 Liam Girdwood <[email protected]> * removed broken wolfson00 patch. * added support for WM9705,WM9708,WM9709,WM9710,WM9711,WM9712 and WM9717. */ static const struct snd_kcontrol_new wm97xx_snd_ac97_controls[] = { AC97_DOUBLE("Front Playback Volume", AC97_WM97XX_FMIXER_VOL, 8, 0, 31, 1), AC97_SINGLE("Front Playback Switch", AC97_WM97XX_FMIXER_VOL, 15, 1, 1), }; static int patch_wolfson_wm9703_specific(struct snd_ac97 * ac97) { /* This is known to work for the ViewSonic ViewPad 1000 * Randolph Bentson <[email protected]> * WM9703/9707/9708/9717 */ int err, i; for (i = 0; i < ARRAY_SIZE(wm97xx_snd_ac97_controls); i++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&wm97xx_snd_ac97_controls[i], ac97)); if (err < 0) return err; } snd_ac97_write_cache(ac97, AC97_WM97XX_FMIXER_VOL, 0x0808); return 0; } static const struct snd_ac97_build_ops patch_wolfson_wm9703_ops = { .build_specific = patch_wolfson_wm9703_specific, }; static int patch_wolfson03(struct snd_ac97 * ac97) { ac97->build_ops = &patch_wolfson_wm9703_ops; return 0; } static const struct snd_kcontrol_new wm9704_snd_ac97_controls[] = { AC97_DOUBLE("Front Playback Volume", AC97_WM97XX_FMIXER_VOL, 8, 0, 31, 1), AC97_SINGLE("Front Playback Switch", AC97_WM97XX_FMIXER_VOL, 15, 1, 1), AC97_DOUBLE("Rear Playback Volume", AC97_WM9704_RMIXER_VOL, 8, 0, 31, 1), AC97_SINGLE("Rear Playback Switch", AC97_WM9704_RMIXER_VOL, 15, 1, 1), AC97_DOUBLE("Rear DAC Volume", AC97_WM9704_RPCM_VOL, 8, 0, 31, 1), AC97_DOUBLE("Surround Volume", AC97_SURROUND_MASTER, 8, 0, 31, 1), }; static int patch_wolfson_wm9704_specific(struct snd_ac97 * ac97) { int err, i; for (i = 0; i < ARRAY_SIZE(wm9704_snd_ac97_controls); i++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&wm9704_snd_ac97_controls[i], ac97)); if (err < 0) return err; } /* patch for DVD noise */ snd_ac97_write_cache(ac97, AC97_WM9704_TEST, 0x0200); return 0; } static const struct snd_ac97_build_ops patch_wolfson_wm9704_ops = { .build_specific = patch_wolfson_wm9704_specific, }; static int patch_wolfson04(struct snd_ac97 * ac97) { /* WM9704M/9704Q */ ac97->build_ops = &patch_wolfson_wm9704_ops; return 0; } static int patch_wolfson05(struct snd_ac97 * ac97) { /* WM9705, WM9710 */ ac97->build_ops = &patch_wolfson_wm9703_ops; #ifdef CONFIG_TOUCHSCREEN_WM9705 /* WM9705 touchscreen uses AUX and VIDEO for touch */ ac97->flags |= AC97_HAS_NO_VIDEO | AC97_HAS_NO_AUX; #endif return 0; } static const char* wm9711_alc_select[] = {"None", "Left", "Right", "Stereo"}; static const char* wm9711_alc_mix[] = {"Stereo", "Right", "Left", "None"}; static const char* wm9711_out3_src[] = {"Left", "VREF", "Left + Right", "Mono"}; static const char* wm9711_out3_lrsrc[] = {"Master Mix", "Headphone Mix"}; static const char* wm9711_rec_adc[] = {"Stereo", "Left", "Right", "Mute"}; static const char* wm9711_base[] = {"Linear Control", "Adaptive Boost"}; static const char* wm9711_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"}; static const char* wm9711_mic[] = {"Mic 1", "Differential", "Mic 2", "Stereo"}; static const char* wm9711_rec_sel[] = {"Mic 1", "NC", "NC", "Master Mix", "Line", "Headphone Mix", "Phone Mix", "Phone"}; static const char* wm9711_ng_type[] = {"Constant Gain", "Mute"}; static const struct ac97_enum wm9711_enum[] = { AC97_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9711_alc_select), AC97_ENUM_SINGLE(AC97_VIDEO, 10, 4, wm9711_alc_mix), AC97_ENUM_SINGLE(AC97_AUX, 9, 4, wm9711_out3_src), AC97_ENUM_SINGLE(AC97_AUX, 8, 2, wm9711_out3_lrsrc), AC97_ENUM_SINGLE(AC97_REC_SEL, 12, 4, wm9711_rec_adc), AC97_ENUM_SINGLE(AC97_MASTER_TONE, 15, 2, wm9711_base), AC97_ENUM_DOUBLE(AC97_REC_GAIN, 14, 6, 2, wm9711_rec_gain), AC97_ENUM_SINGLE(AC97_MIC, 5, 4, wm9711_mic), AC97_ENUM_DOUBLE(AC97_REC_SEL, 8, 0, 8, wm9711_rec_sel), AC97_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9711_ng_type), }; static const struct snd_kcontrol_new wm9711_snd_ac97_controls[] = { AC97_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0), AC97_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0), AC97_SINGLE("ALC Decay Time", AC97_CODEC_CLASS_REV, 4, 15, 0), AC97_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0), AC97_ENUM("ALC Function", wm9711_enum[0]), AC97_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 1), AC97_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 1), AC97_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0), AC97_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0), AC97_ENUM("ALC NG Type", wm9711_enum[9]), AC97_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 1), AC97_SINGLE("Side Tone Switch", AC97_VIDEO, 15, 1, 1), AC97_SINGLE("Side Tone Volume", AC97_VIDEO, 12, 7, 1), AC97_ENUM("ALC Headphone Mux", wm9711_enum[1]), AC97_SINGLE("ALC Headphone Volume", AC97_VIDEO, 7, 7, 1), AC97_SINGLE("Out3 Switch", AC97_AUX, 15, 1, 1), AC97_SINGLE("Out3 ZC Switch", AC97_AUX, 7, 1, 0), AC97_ENUM("Out3 Mux", wm9711_enum[2]), AC97_ENUM("Out3 LR Mux", wm9711_enum[3]), AC97_SINGLE("Out3 Volume", AC97_AUX, 0, 31, 1), AC97_SINGLE("Beep to Headphone Switch", AC97_PC_BEEP, 15, 1, 1), AC97_SINGLE("Beep to Headphone Volume", AC97_PC_BEEP, 12, 7, 1), AC97_SINGLE("Beep to Side Tone Switch", AC97_PC_BEEP, 11, 1, 1), AC97_SINGLE("Beep to Side Tone Volume", AC97_PC_BEEP, 8, 7, 1), AC97_SINGLE("Beep to Phone Switch", AC97_PC_BEEP, 7, 1, 1), AC97_SINGLE("Beep to Phone Volume", AC97_PC_BEEP, 4, 7, 1), AC97_SINGLE("Aux to Headphone Switch", AC97_CD, 15, 1, 1), AC97_SINGLE("Aux to Headphone Volume", AC97_CD, 12, 7, 1), AC97_SINGLE("Aux to Side Tone Switch", AC97_CD, 11, 1, 1), AC97_SINGLE("Aux to Side Tone Volume", AC97_CD, 8, 7, 1), AC97_SINGLE("Aux to Phone Switch", AC97_CD, 7, 1, 1), AC97_SINGLE("Aux to Phone Volume", AC97_CD, 4, 7, 1), AC97_SINGLE("Phone to Headphone Switch", AC97_PHONE, 15, 1, 1), AC97_SINGLE("Phone to Master Switch", AC97_PHONE, 14, 1, 1), AC97_SINGLE("Line to Headphone Switch", AC97_LINE, 15, 1, 1), AC97_SINGLE("Line to Master Switch", AC97_LINE, 14, 1, 1), AC97_SINGLE("Line to Phone Switch", AC97_LINE, 13, 1, 1), AC97_SINGLE("PCM Playback to Headphone Switch", AC97_PCM, 15, 1, 1), AC97_SINGLE("PCM Playback to Master Switch", AC97_PCM, 14, 1, 1), AC97_SINGLE("PCM Playback to Phone Switch", AC97_PCM, 13, 1, 1), AC97_SINGLE("Capture 20dB Boost Switch", AC97_REC_SEL, 14, 1, 0), AC97_ENUM("Capture to Phone Mux", wm9711_enum[4]), AC97_SINGLE("Capture to Phone 20dB Boost Switch", AC97_REC_SEL, 11, 1, 1), AC97_ENUM("Capture Select", wm9711_enum[8]), AC97_SINGLE("3D Upper Cut-off Switch", AC97_3D_CONTROL, 5, 1, 1), AC97_SINGLE("3D Lower Cut-off Switch", AC97_3D_CONTROL, 4, 1, 1), AC97_ENUM("Bass Control", wm9711_enum[5]), AC97_SINGLE("Bass Cut-off Switch", AC97_MASTER_TONE, 12, 1, 1), AC97_SINGLE("Tone Cut-off Switch", AC97_MASTER_TONE, 4, 1, 1), AC97_SINGLE("Playback Attenuate (-6dB) Switch", AC97_MASTER_TONE, 6, 1, 0), AC97_SINGLE("ADC Switch", AC97_REC_GAIN, 15, 1, 1), AC97_ENUM("Capture Volume Steps", wm9711_enum[6]), AC97_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 63, 1), AC97_SINGLE("Capture ZC Switch", AC97_REC_GAIN, 7, 1, 0), AC97_SINGLE("Mic 1 to Phone Switch", AC97_MIC, 14, 1, 1), AC97_SINGLE("Mic 2 to Phone Switch", AC97_MIC, 13, 1, 1), AC97_ENUM("Mic Select Source", wm9711_enum[7]), AC97_SINGLE("Mic 1 Volume", AC97_MIC, 8, 31, 1), AC97_SINGLE("Mic 2 Volume", AC97_MIC, 0, 31, 1), AC97_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 7, 1, 0), AC97_SINGLE("Master Left Inv Switch", AC97_MASTER, 6, 1, 0), AC97_SINGLE("Master ZC Switch", AC97_MASTER, 7, 1, 0), AC97_SINGLE("Headphone ZC Switch", AC97_HEADPHONE, 7, 1, 0), AC97_SINGLE("Mono ZC Switch", AC97_MASTER_MONO, 7, 1, 0), }; static int patch_wolfson_wm9711_specific(struct snd_ac97 * ac97) { int err, i; for (i = 0; i < ARRAY_SIZE(wm9711_snd_ac97_controls); i++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&wm9711_snd_ac97_controls[i], ac97)); if (err < 0) return err; } snd_ac97_write_cache(ac97, AC97_CODEC_CLASS_REV, 0x0808); snd_ac97_write_cache(ac97, AC97_PCI_SVID, 0x0808); snd_ac97_write_cache(ac97, AC97_VIDEO, 0x0808); snd_ac97_write_cache(ac97, AC97_AUX, 0x0808); snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x0808); snd_ac97_write_cache(ac97, AC97_CD, 0x0000); return 0; } static const struct snd_ac97_build_ops patch_wolfson_wm9711_ops = { .build_specific = patch_wolfson_wm9711_specific, }; static int patch_wolfson11(struct snd_ac97 * ac97) { /* WM9711, WM9712 */ ac97->build_ops = &patch_wolfson_wm9711_ops; ac97->flags |= AC97_HAS_NO_REC_GAIN | AC97_STEREO_MUTES | AC97_HAS_NO_MIC | AC97_HAS_NO_PC_BEEP | AC97_HAS_NO_VIDEO | AC97_HAS_NO_CD; return 0; } static const char* wm9713_mic_mixer[] = {"Stereo", "Mic 1", "Mic 2", "Mute"}; static const char* wm9713_rec_mux[] = {"Stereo", "Left", "Right", "Mute"}; static const char* wm9713_rec_src[] = {"Mic 1", "Mic 2", "Line", "Mono In", "Headphone Mix", "Master Mix", "Mono Mix", "Zh"}; static const char* wm9713_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"}; static const char* wm9713_alc_select[] = {"None", "Left", "Right", "Stereo"}; static const char* wm9713_mono_pga[] = {"Vmid", "Zh", "Mono Mix", "Inv 1"}; static const char* wm9713_spk_pga[] = {"Vmid", "Zh", "Headphone Mix", "Master Mix", "Inv", "NC", "NC", "NC"}; static const char* wm9713_hp_pga[] = {"Vmid", "Zh", "Headphone Mix", "NC"}; static const char* wm9713_out3_pga[] = {"Vmid", "Zh", "Inv 1", "NC"}; static const char* wm9713_out4_pga[] = {"Vmid", "Zh", "Inv 2", "NC"}; static const char* wm9713_dac_inv[] = {"Off", "Mono Mix", "Master Mix", "Headphone Mix L", "Headphone Mix R", "Headphone Mix Mono", "NC", "Vmid"}; static const char* wm9713_base[] = {"Linear Control", "Adaptive Boost"}; static const char* wm9713_ng_type[] = {"Constant Gain", "Mute"}; static const struct ac97_enum wm9713_enum[] = { AC97_ENUM_SINGLE(AC97_LINE, 3, 4, wm9713_mic_mixer), AC97_ENUM_SINGLE(AC97_VIDEO, 14, 4, wm9713_rec_mux), AC97_ENUM_SINGLE(AC97_VIDEO, 9, 4, wm9713_rec_mux), AC97_ENUM_DOUBLE(AC97_VIDEO, 3, 0, 8, wm9713_rec_src), AC97_ENUM_DOUBLE(AC97_CD, 14, 6, 2, wm9713_rec_gain), AC97_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9713_alc_select), AC97_ENUM_SINGLE(AC97_REC_GAIN, 14, 4, wm9713_mono_pga), AC97_ENUM_DOUBLE(AC97_REC_GAIN, 11, 8, 8, wm9713_spk_pga), AC97_ENUM_DOUBLE(AC97_REC_GAIN, 6, 4, 4, wm9713_hp_pga), AC97_ENUM_SINGLE(AC97_REC_GAIN, 2, 4, wm9713_out3_pga), AC97_ENUM_SINGLE(AC97_REC_GAIN, 0, 4, wm9713_out4_pga), AC97_ENUM_DOUBLE(AC97_REC_GAIN_MIC, 13, 10, 8, wm9713_dac_inv), AC97_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, wm9713_base), AC97_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9713_ng_type), }; static const struct snd_kcontrol_new wm13_snd_ac97_controls[] = { AC97_DOUBLE("Line In Volume", AC97_PC_BEEP, 8, 0, 31, 1), AC97_SINGLE("Line In to Headphone Switch", AC97_PC_BEEP, 15, 1, 1), AC97_SINGLE("Line In to Master Switch", AC97_PC_BEEP, 14, 1, 1), AC97_SINGLE("Line In to Mono Switch", AC97_PC_BEEP, 13, 1, 1), AC97_DOUBLE("PCM Playback Volume", AC97_PHONE, 8, 0, 31, 1), AC97_SINGLE("PCM Playback to Headphone Switch", AC97_PHONE, 15, 1, 1), AC97_SINGLE("PCM Playback to Master Switch", AC97_PHONE, 14, 1, 1), AC97_SINGLE("PCM Playback to Mono Switch", AC97_PHONE, 13, 1, 1), AC97_SINGLE("Mic 1 Volume", AC97_MIC, 8, 31, 1), AC97_SINGLE("Mic 2 Volume", AC97_MIC, 0, 31, 1), AC97_SINGLE("Mic 1 to Mono Switch", AC97_LINE, 7, 1, 1), AC97_SINGLE("Mic 2 to Mono Switch", AC97_LINE, 6, 1, 1), AC97_SINGLE("Mic Boost (+20dB) Switch", AC97_LINE, 5, 1, 0), AC97_ENUM("Mic to Headphone Mux", wm9713_enum[0]), AC97_SINGLE("Mic Headphone Mixer Volume", AC97_LINE, 0, 7, 1), AC97_SINGLE("Capture Switch", AC97_CD, 15, 1, 1), AC97_ENUM("Capture Volume Steps", wm9713_enum[4]), AC97_DOUBLE("Capture Volume", AC97_CD, 8, 0, 15, 0), AC97_SINGLE("Capture ZC Switch", AC97_CD, 7, 1, 0), AC97_ENUM("Capture to Headphone Mux", wm9713_enum[1]), AC97_SINGLE("Capture to Headphone Volume", AC97_VIDEO, 11, 7, 1), AC97_ENUM("Capture to Mono Mux", wm9713_enum[2]), AC97_SINGLE("Capture to Mono Boost (+20dB) Switch", AC97_VIDEO, 8, 1, 0), AC97_SINGLE("Capture ADC Boost (+20dB) Switch", AC97_VIDEO, 6, 1, 0), AC97_ENUM("Capture Select", wm9713_enum[3]), AC97_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0), AC97_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0), AC97_SINGLE("ALC Decay Time ", AC97_CODEC_CLASS_REV, 4, 15, 0), AC97_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0), AC97_ENUM("ALC Function", wm9713_enum[5]), AC97_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0), AC97_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 0), AC97_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0), AC97_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0), AC97_ENUM("ALC NG Type", wm9713_enum[13]), AC97_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 0), AC97_DOUBLE("Master ZC Switch", AC97_MASTER, 14, 6, 1, 0), AC97_DOUBLE("Headphone ZC Switch", AC97_HEADPHONE, 14, 6, 1, 0), AC97_DOUBLE("Out3/4 ZC Switch", AC97_MASTER_MONO, 14, 6, 1, 0), AC97_SINGLE("Master Right Switch", AC97_MASTER, 7, 1, 1), AC97_SINGLE("Headphone Right Switch", AC97_HEADPHONE, 7, 1, 1), AC97_SINGLE("Out3/4 Right Switch", AC97_MASTER_MONO, 7, 1, 1), AC97_SINGLE("Mono In to Headphone Switch", AC97_MASTER_TONE, 15, 1, 1), AC97_SINGLE("Mono In to Master Switch", AC97_MASTER_TONE, 14, 1, 1), AC97_SINGLE("Mono In Volume", AC97_MASTER_TONE, 8, 31, 1), AC97_SINGLE("Mono Switch", AC97_MASTER_TONE, 7, 1, 1), AC97_SINGLE("Mono ZC Switch", AC97_MASTER_TONE, 6, 1, 0), AC97_SINGLE("Mono Volume", AC97_MASTER_TONE, 0, 31, 1), AC97_SINGLE("Beep to Headphone Switch", AC97_AUX, 15, 1, 1), AC97_SINGLE("Beep to Headphone Volume", AC97_AUX, 12, 7, 1), AC97_SINGLE("Beep to Master Switch", AC97_AUX, 11, 1, 1), AC97_SINGLE("Beep to Master Volume", AC97_AUX, 8, 7, 1), AC97_SINGLE("Beep to Mono Switch", AC97_AUX, 7, 1, 1), AC97_SINGLE("Beep to Mono Volume", AC97_AUX, 4, 7, 1), AC97_SINGLE("Voice to Headphone Switch", AC97_PCM, 15, 1, 1), AC97_SINGLE("Voice to Headphone Volume", AC97_PCM, 12, 7, 1), AC97_SINGLE("Voice to Master Switch", AC97_PCM, 11, 1, 1), AC97_SINGLE("Voice to Master Volume", AC97_PCM, 8, 7, 1), AC97_SINGLE("Voice to Mono Switch", AC97_PCM, 7, 1, 1), AC97_SINGLE("Voice to Mono Volume", AC97_PCM, 4, 7, 1), AC97_SINGLE("Aux to Headphone Switch", AC97_REC_SEL, 15, 1, 1), AC97_SINGLE("Aux to Headphone Volume", AC97_REC_SEL, 12, 7, 1), AC97_SINGLE("Aux to Master Switch", AC97_REC_SEL, 11, 1, 1), AC97_SINGLE("Aux to Master Volume", AC97_REC_SEL, 8, 7, 1), AC97_SINGLE("Aux to Mono Switch", AC97_REC_SEL, 7, 1, 1), AC97_SINGLE("Aux to Mono Volume", AC97_REC_SEL, 4, 7, 1), AC97_ENUM("Mono Input Mux", wm9713_enum[6]), AC97_ENUM("Master Input Mux", wm9713_enum[7]), AC97_ENUM("Headphone Input Mux", wm9713_enum[8]), AC97_ENUM("Out 3 Input Mux", wm9713_enum[9]), AC97_ENUM("Out 4 Input Mux", wm9713_enum[10]), AC97_ENUM("Bass Control", wm9713_enum[12]), AC97_SINGLE("Bass Cut-off Switch", AC97_GENERAL_PURPOSE, 12, 1, 1), AC97_SINGLE("Tone Cut-off Switch", AC97_GENERAL_PURPOSE, 4, 1, 1), AC97_SINGLE("Playback Attenuate (-6dB) Switch", AC97_GENERAL_PURPOSE, 6, 1, 0), AC97_SINGLE("Bass Volume", AC97_GENERAL_PURPOSE, 8, 15, 1), AC97_SINGLE("Tone Volume", AC97_GENERAL_PURPOSE, 0, 15, 1), }; static const struct snd_kcontrol_new wm13_snd_ac97_controls_3d[] = { AC97_ENUM("Inv Input Mux", wm9713_enum[11]), AC97_SINGLE("3D Upper Cut-off Switch", AC97_REC_GAIN_MIC, 5, 1, 0), AC97_SINGLE("3D Lower Cut-off Switch", AC97_REC_GAIN_MIC, 4, 1, 0), AC97_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1), }; static int patch_wolfson_wm9713_3d (struct snd_ac97 * ac97) { int err, i; for (i = 0; i < ARRAY_SIZE(wm13_snd_ac97_controls_3d); i++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&wm13_snd_ac97_controls_3d[i], ac97)); if (err < 0) return err; } return 0; } static int patch_wolfson_wm9713_specific(struct snd_ac97 * ac97) { int err, i; for (i = 0; i < ARRAY_SIZE(wm13_snd_ac97_controls); i++) { err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&wm13_snd_ac97_controls[i], ac97)); if (err < 0) return err; } snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x0808); snd_ac97_write_cache(ac97, AC97_PHONE, 0x0808); snd_ac97_write_cache(ac97, AC97_MIC, 0x0808); snd_ac97_write_cache(ac97, AC97_LINE, 0x00da); snd_ac97_write_cache(ac97, AC97_CD, 0x0808); snd_ac97_write_cache(ac97, AC97_VIDEO, 0xd612); snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x1ba0); return 0; } #ifdef CONFIG_PM static void patch_wolfson_wm9713_suspend (struct snd_ac97 * ac97) { snd_ac97_write_cache(ac97, AC97_EXTENDED_MID, 0xfeff); snd_ac97_write_cache(ac97, AC97_EXTENDED_MSTATUS, 0xffff); } static void patch_wolfson_wm9713_resume (struct snd_ac97 * ac97) { snd_ac97_write_cache(ac97, AC97_EXTENDED_MID, 0xda00); snd_ac97_write_cache(ac97, AC97_EXTENDED_MSTATUS, 0x3810); snd_ac97_write_cache(ac97, AC97_POWERDOWN, 0x0); } #endif static const struct snd_ac97_build_ops patch_wolfson_wm9713_ops = { .build_specific = patch_wolfson_wm9713_specific, .build_3d = patch_wolfson_wm9713_3d, #ifdef CONFIG_PM .suspend = patch_wolfson_wm9713_suspend, .resume = patch_wolfson_wm9713_resume #endif }; static int patch_wolfson13(struct snd_ac97 * ac97) { /* WM9713, WM9714 */ ac97->build_ops = &patch_wolfson_wm9713_ops; ac97->flags |= AC97_HAS_NO_REC_GAIN | AC97_STEREO_MUTES | AC97_HAS_NO_PHONE | AC97_HAS_NO_PC_BEEP | AC97_HAS_NO_VIDEO | AC97_HAS_NO_CD | AC97_HAS_NO_TONE | AC97_HAS_NO_STD_PCM; ac97->scaps &= ~AC97_SCAP_MODEM; snd_ac97_write_cache(ac97, AC97_EXTENDED_MID, 0xda00); snd_ac97_write_cache(ac97, AC97_EXTENDED_MSTATUS, 0x3810); snd_ac97_write_cache(ac97, AC97_POWERDOWN, 0x0); return 0; } /* * Tritech codec */ static int patch_tritech_tr28028(struct snd_ac97 * ac97) { snd_ac97_write_cache(ac97, 0x26, 0x0300); snd_ac97_write_cache(ac97, 0x26, 0x0000); snd_ac97_write_cache(ac97, AC97_SURROUND_MASTER, 0x0000); snd_ac97_write_cache(ac97, AC97_SPDIF, 0x0000); return 0; } /* * Sigmatel STAC97xx codecs */ static int patch_sigmatel_stac9700_3d(struct snd_ac97 * ac97) { struct snd_kcontrol *kctl; int err; err = snd_ctl_add(ac97->bus->card, kctl = snd_ac97_cnew(&snd_ac97_controls_3d[0], ac97)); if (err < 0) return err; strcpy(kctl->id.name, "3D Control Sigmatel - Depth"); kctl->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 2, 3, 0); snd_ac97_write_cache(ac97, AC97_3D_CONTROL, 0x0000); return 0; } static int patch_sigmatel_stac9708_3d(struct snd_ac97 * ac97) { struct snd_kcontrol *kctl; int err; kctl = snd_ac97_cnew(&snd_ac97_controls_3d[0], ac97); err = snd_ctl_add(ac97->bus->card, kctl); if (err < 0) return err; strcpy(kctl->id.name, "3D Control Sigmatel - Depth"); kctl->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 0, 3, 0); kctl = snd_ac97_cnew(&snd_ac97_controls_3d[0], ac97); err = snd_ctl_add(ac97->bus->card, kctl); if (err < 0) return err; strcpy(kctl->id.name, "3D Control Sigmatel - Rear Depth"); kctl->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 2, 3, 0); snd_ac97_write_cache(ac97, AC97_3D_CONTROL, 0x0000); return 0; } static const struct snd_kcontrol_new snd_ac97_sigmatel_4speaker = AC97_SINGLE("Sigmatel 4-Speaker Stereo Playback Switch", AC97_SIGMATEL_DAC2INVERT, 2, 1, 0); /* "Sigmatel " removed due to excessive name length: */ static const struct snd_kcontrol_new snd_ac97_sigmatel_phaseinvert = AC97_SINGLE("Surround Phase Inversion Playback Switch", AC97_SIGMATEL_DAC2INVERT, 3, 1, 0); static const struct snd_kcontrol_new snd_ac97_sigmatel_controls[] = { AC97_SINGLE("Sigmatel DAC 6dB Attenuate", AC97_SIGMATEL_ANALOG, 1, 1, 0), AC97_SINGLE("Sigmatel ADC 6dB Attenuate", AC97_SIGMATEL_ANALOG, 0, 1, 0) }; static int patch_sigmatel_stac97xx_specific(struct snd_ac97 * ac97) { int err; snd_ac97_write_cache(ac97, AC97_SIGMATEL_ANALOG, snd_ac97_read(ac97, AC97_SIGMATEL_ANALOG) & ~0x0003); if (snd_ac97_try_bit(ac97, AC97_SIGMATEL_ANALOG, 1)) { err = patch_build_controls(ac97, &snd_ac97_sigmatel_controls[0], 1); if (err < 0) return err; } if (snd_ac97_try_bit(ac97, AC97_SIGMATEL_ANALOG, 0)) { err = patch_build_controls(ac97, &snd_ac97_sigmatel_controls[1], 1); if (err < 0) return err; } if (snd_ac97_try_bit(ac97, AC97_SIGMATEL_DAC2INVERT, 2)) { err = patch_build_controls(ac97, &snd_ac97_sigmatel_4speaker, 1); if (err < 0) return err; } if (snd_ac97_try_bit(ac97, AC97_SIGMATEL_DAC2INVERT, 3)) { err = patch_build_controls(ac97, &snd_ac97_sigmatel_phaseinvert, 1); if (err < 0) return err; } return 0; } static const struct snd_ac97_build_ops patch_sigmatel_stac9700_ops = { .build_3d = patch_sigmatel_stac9700_3d, .build_specific = patch_sigmatel_stac97xx_specific }; static int patch_sigmatel_stac9700(struct snd_ac97 * ac97) { ac97->build_ops = &patch_sigmatel_stac9700_ops; return 0; } static int snd_ac97_stac9708_put_bias(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int err; mutex_lock(&ac97->page_mutex); snd_ac97_write(ac97, AC97_SIGMATEL_BIAS1, 0xabba); err = snd_ac97_update_bits(ac97, AC97_SIGMATEL_BIAS2, 0x0010, (ucontrol->value.integer.value[0] & 1) << 4); snd_ac97_write(ac97, AC97_SIGMATEL_BIAS1, 0); mutex_unlock(&ac97->page_mutex); return err; } static const struct snd_kcontrol_new snd_ac97_stac9708_bias_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Sigmatel Output Bias Switch", .info = snd_ac97_info_volsw, .get = snd_ac97_get_volsw, .put = snd_ac97_stac9708_put_bias, .private_value = AC97_SINGLE_VALUE(AC97_SIGMATEL_BIAS2, 4, 1, 0), }; static int patch_sigmatel_stac9708_specific(struct snd_ac97 *ac97) { int err; /* the register bit is writable, but the function is not implemented: */ snd_ac97_remove_ctl(ac97, "PCM Out Path & Mute", NULL); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Sigmatel Surround Playback"); err = patch_build_controls(ac97, &snd_ac97_stac9708_bias_control, 1); if (err < 0) return err; return patch_sigmatel_stac97xx_specific(ac97); } static const struct snd_ac97_build_ops patch_sigmatel_stac9708_ops = { .build_3d = patch_sigmatel_stac9708_3d, .build_specific = patch_sigmatel_stac9708_specific }; static int patch_sigmatel_stac9708(struct snd_ac97 * ac97) { unsigned int codec72, codec6c; ac97->build_ops = &patch_sigmatel_stac9708_ops; ac97->caps |= 0x10; /* HP (sigmatel surround) support */ codec72 = snd_ac97_read(ac97, AC97_SIGMATEL_BIAS2) & 0x8000; codec6c = snd_ac97_read(ac97, AC97_SIGMATEL_ANALOG); if ((codec72==0) && (codec6c==0)) { snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x1000); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS2, 0x0007); } else if ((codec72==0x8000) && (codec6c==0)) { snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x1001); snd_ac97_write_cache(ac97, AC97_SIGMATEL_DAC2INVERT, 0x0008); } else if ((codec72==0x8000) && (codec6c==0x0080)) { /* nothing */ } snd_ac97_write_cache(ac97, AC97_SIGMATEL_MULTICHN, 0x0000); return 0; } static int patch_sigmatel_stac9721(struct snd_ac97 * ac97) { ac97->build_ops = &patch_sigmatel_stac9700_ops; if (snd_ac97_read(ac97, AC97_SIGMATEL_ANALOG) == 0) { // patch for SigmaTel snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x4000); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS2, 0x0002); } snd_ac97_write_cache(ac97, AC97_SIGMATEL_MULTICHN, 0x0000); return 0; } static int patch_sigmatel_stac9744(struct snd_ac97 * ac97) { // patch for SigmaTel ac97->build_ops = &patch_sigmatel_stac9700_ops; snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x0000); /* is this correct? --jk */ snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS2, 0x0002); snd_ac97_write_cache(ac97, AC97_SIGMATEL_MULTICHN, 0x0000); return 0; } static int patch_sigmatel_stac9756(struct snd_ac97 * ac97) { // patch for SigmaTel ac97->build_ops = &patch_sigmatel_stac9700_ops; snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x0000); /* is this correct? --jk */ snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS1, 0xabba); snd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS2, 0x0002); snd_ac97_write_cache(ac97, AC97_SIGMATEL_MULTICHN, 0x0000); return 0; } static int snd_ac97_stac9758_output_jack_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[5] = { "Input/Disabled", "Front Output", "Rear Output", "Center/LFE Output", "Mixer Output" }; return snd_ctl_enum_info(uinfo, 1, 5, texts); } static int snd_ac97_stac9758_output_jack_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = kcontrol->private_value; unsigned short val; val = ac97->regs[AC97_SIGMATEL_OUTSEL] >> shift; if (!(val & 4)) ucontrol->value.enumerated.item[0] = 0; else ucontrol->value.enumerated.item[0] = 1 + (val & 3); return 0; } static int snd_ac97_stac9758_output_jack_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = kcontrol->private_value; unsigned short val; if (ucontrol->value.enumerated.item[0] > 4) return -EINVAL; if (ucontrol->value.enumerated.item[0] == 0) val = 0; else val = 4 | (ucontrol->value.enumerated.item[0] - 1); return ac97_update_bits_page(ac97, AC97_SIGMATEL_OUTSEL, 7 << shift, val << shift, 0); } static int snd_ac97_stac9758_input_jack_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[7] = { "Mic2 Jack", "Mic1 Jack", "Line In Jack", "Front Jack", "Rear Jack", "Center/LFE Jack", "Mute" }; return snd_ctl_enum_info(uinfo, 1, 7, texts); } static int snd_ac97_stac9758_input_jack_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = kcontrol->private_value; unsigned short val; val = ac97->regs[AC97_SIGMATEL_INSEL]; ucontrol->value.enumerated.item[0] = (val >> shift) & 7; return 0; } static int snd_ac97_stac9758_input_jack_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int shift = kcontrol->private_value; return ac97_update_bits_page(ac97, AC97_SIGMATEL_INSEL, 7 << shift, ucontrol->value.enumerated.item[0] << shift, 0); } static int snd_ac97_stac9758_phonesel_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[3] = { "None", "Front Jack", "Rear Jack" }; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int snd_ac97_stac9758_phonesel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = ac97->regs[AC97_SIGMATEL_IOMISC] & 3; return 0; } static int snd_ac97_stac9758_phonesel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); return ac97_update_bits_page(ac97, AC97_SIGMATEL_IOMISC, 3, ucontrol->value.enumerated.item[0], 0); } #define STAC9758_OUTPUT_JACK(xname, shift) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_ac97_stac9758_output_jack_info, \ .get = snd_ac97_stac9758_output_jack_get, \ .put = snd_ac97_stac9758_output_jack_put, \ .private_value = shift } #define STAC9758_INPUT_JACK(xname, shift) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_ac97_stac9758_input_jack_info, \ .get = snd_ac97_stac9758_input_jack_get, \ .put = snd_ac97_stac9758_input_jack_put, \ .private_value = shift } static const struct snd_kcontrol_new snd_ac97_sigmatel_stac9758_controls[] = { STAC9758_OUTPUT_JACK("Mic1 Jack", 1), STAC9758_OUTPUT_JACK("LineIn Jack", 4), STAC9758_OUTPUT_JACK("Front Jack", 7), STAC9758_OUTPUT_JACK("Rear Jack", 10), STAC9758_OUTPUT_JACK("Center/LFE Jack", 13), STAC9758_INPUT_JACK("Mic Input Source", 0), STAC9758_INPUT_JACK("Line Input Source", 8), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Amp", .info = snd_ac97_stac9758_phonesel_info, .get = snd_ac97_stac9758_phonesel_get, .put = snd_ac97_stac9758_phonesel_put }, AC97_SINGLE("Exchange Center/LFE", AC97_SIGMATEL_IOMISC, 4, 1, 0), AC97_SINGLE("Headphone +3dB Boost", AC97_SIGMATEL_IOMISC, 8, 1, 0) }; static int patch_sigmatel_stac9758_specific(struct snd_ac97 *ac97) { int err; err = patch_sigmatel_stac97xx_specific(ac97); if (err < 0) return err; err = patch_build_controls(ac97, snd_ac97_sigmatel_stac9758_controls, ARRAY_SIZE(snd_ac97_sigmatel_stac9758_controls)); if (err < 0) return err; /* DAC-A direct */ snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Front Playback"); /* DAC-A to Mix = PCM */ /* DAC-B direct = Surround */ /* DAC-B to Mix */ snd_ac97_rename_vol_ctl(ac97, "Video Playback", "Surround Mix Playback"); /* DAC-C direct = Center/LFE */ return 0; } static const struct snd_ac97_build_ops patch_sigmatel_stac9758_ops = { .build_3d = patch_sigmatel_stac9700_3d, .build_specific = patch_sigmatel_stac9758_specific }; static int patch_sigmatel_stac9758(struct snd_ac97 * ac97) { static const unsigned short regs[4] = { AC97_SIGMATEL_OUTSEL, AC97_SIGMATEL_IOMISC, AC97_SIGMATEL_INSEL, AC97_SIGMATEL_VARIOUS }; static const unsigned short def_regs[4] = { /* OUTSEL */ 0xd794, /* CL:CL, SR:SR, LO:MX, LI:DS, MI:DS */ /* IOMISC */ 0x2001, /* INSEL */ 0x0201, /* LI:LI, MI:M1 */ /* VARIOUS */ 0x0040 }; static const unsigned short m675_regs[4] = { /* OUTSEL */ 0xfc70, /* CL:MX, SR:MX, LO:DS, LI:MX, MI:DS */ /* IOMISC */ 0x2102, /* HP amp on */ /* INSEL */ 0x0203, /* LI:LI, MI:FR */ /* VARIOUS */ 0x0041 /* stereo mic */ }; const unsigned short *pregs = def_regs; int i; /* Gateway M675 notebook */ if (ac97->pci && ac97->subsystem_vendor == 0x107b && ac97->subsystem_device == 0x0601) pregs = m675_regs; // patch for SigmaTel ac97->build_ops = &patch_sigmatel_stac9758_ops; /* FIXME: assume only page 0 for writing cache */ snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_VENDOR); for (i = 0; i < 4; i++) snd_ac97_write_cache(ac97, regs[i], pregs[i]); ac97->flags |= AC97_STEREO_MUTES; return 0; } /* * Cirrus Logic CS42xx codecs */ static const struct snd_kcontrol_new snd_ac97_cirrus_controls_spdif[2] = { AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), AC97_CSR_SPDIF, 15, 1, 0), AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "AC97-SPSA", AC97_CSR_ACMODE, 0, 3, 0) }; static int patch_cirrus_build_spdif(struct snd_ac97 * ac97) { int err; /* con mask, pro mask, default */ err = patch_build_controls(ac97, &snd_ac97_controls_spdif[0], 3); if (err < 0) return err; /* switch, spsa */ err = patch_build_controls(ac97, &snd_ac97_cirrus_controls_spdif[0], 1); if (err < 0) return err; switch (ac97->id & AC97_ID_CS_MASK) { case AC97_ID_CS4205: err = patch_build_controls(ac97, &snd_ac97_cirrus_controls_spdif[1], 1); if (err < 0) return err; break; } /* set default PCM S/PDIF params */ /* consumer,PCM audio,no copyright,no preemphasis,PCM coder,original,48000Hz */ snd_ac97_write_cache(ac97, AC97_CSR_SPDIF, 0x0a20); return 0; } static const struct snd_ac97_build_ops patch_cirrus_ops = { .build_spdif = patch_cirrus_build_spdif }; static int patch_cirrus_spdif(struct snd_ac97 * ac97) { /* Basically, the cs4201/cs4205/cs4297a has non-standard sp/dif registers. WHY CAN'T ANYONE FOLLOW THE BLOODY SPEC? *sigh* - sp/dif EA ID is not set, but sp/dif is always present. - enable/disable is spdif register bit 15. - sp/dif control register is 0x68. differs from AC97: - valid is bit 14 (vs 15) - no DRS - only 44.1/48k [00 = 48, 01=44,1] (AC97 is 00=44.1, 10=48) - sp/dif ssource select is in 0x5e bits 0,1. */ ac97->build_ops = &patch_cirrus_ops; ac97->flags |= AC97_CS_SPDIF; ac97->rates[AC97_RATES_SPDIF] &= ~SNDRV_PCM_RATE_32000; ac97->ext_id |= AC97_EI_SPDIF; /* force the detection of spdif */ snd_ac97_write_cache(ac97, AC97_CSR_ACMODE, 0x0080); return 0; } static int patch_cirrus_cs4299(struct snd_ac97 * ac97) { /* force the detection of PC Beep */ ac97->flags |= AC97_HAS_PC_BEEP; return patch_cirrus_spdif(ac97); } /* * Conexant codecs */ static const struct snd_kcontrol_new snd_ac97_conexant_controls_spdif[1] = { AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), AC97_CXR_AUDIO_MISC, 3, 1, 0), }; static int patch_conexant_build_spdif(struct snd_ac97 * ac97) { int err; /* con mask, pro mask, default */ err = patch_build_controls(ac97, &snd_ac97_controls_spdif[0], 3); if (err < 0) return err; /* switch */ err = patch_build_controls(ac97, &snd_ac97_conexant_controls_spdif[0], 1); if (err < 0) return err; /* set default PCM S/PDIF params */ /* consumer,PCM audio,no copyright,no preemphasis,PCM coder,original,48000Hz */ snd_ac97_write_cache(ac97, AC97_CXR_AUDIO_MISC, snd_ac97_read(ac97, AC97_CXR_AUDIO_MISC) & ~(AC97_CXR_SPDIFEN|AC97_CXR_COPYRGT|AC97_CXR_SPDIF_MASK)); return 0; } static const struct snd_ac97_build_ops patch_conexant_ops = { .build_spdif = patch_conexant_build_spdif }; static int patch_conexant(struct snd_ac97 * ac97) { ac97->build_ops = &patch_conexant_ops; ac97->flags |= AC97_CX_SPDIF; ac97->ext_id |= AC97_EI_SPDIF; /* force the detection of spdif */ ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000; /* 48k only */ return 0; } static int patch_cx20551(struct snd_ac97 *ac97) { snd_ac97_update_bits(ac97, 0x5c, 0x01, 0x01); return 0; } /* * Analog Devices AD18xx, AD19xx codecs */ #ifdef CONFIG_PM static void ad18xx_resume(struct snd_ac97 *ac97) { static const unsigned short setup_regs[] = { AC97_AD_MISC, AC97_AD_SERIAL_CFG, AC97_AD_JACK_SPDIF, }; int i, codec; for (i = 0; i < (int)ARRAY_SIZE(setup_regs); i++) { unsigned short reg = setup_regs[i]; if (test_bit(reg, ac97->reg_accessed)) { snd_ac97_write(ac97, reg, ac97->regs[reg]); snd_ac97_read(ac97, reg); } } if (! (ac97->flags & AC97_AD_MULTI)) /* normal restore */ snd_ac97_restore_status(ac97); else { /* restore the AD18xx codec configurations */ for (codec = 0; codec < 3; codec++) { if (! ac97->spec.ad18xx.id[codec]) continue; /* select single codec */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, ac97->spec.ad18xx.unchained[codec] | ac97->spec.ad18xx.chained[codec]); ac97->bus->ops->write(ac97, AC97_AD_CODEC_CFG, ac97->spec.ad18xx.codec_cfg[codec]); } /* select all codecs */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, 0x7000); /* restore status */ for (i = 2; i < 0x7c ; i += 2) { if (i == AC97_POWERDOWN || i == AC97_EXTENDED_ID) continue; if (test_bit(i, ac97->reg_accessed)) { /* handle multi codecs for AD18xx */ if (i == AC97_PCM) { for (codec = 0; codec < 3; codec++) { if (! ac97->spec.ad18xx.id[codec]) continue; /* select single codec */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, ac97->spec.ad18xx.unchained[codec] | ac97->spec.ad18xx.chained[codec]); /* update PCM bits */ ac97->bus->ops->write(ac97, AC97_PCM, ac97->spec.ad18xx.pcmreg[codec]); } /* select all codecs */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, 0x7000); continue; } else if (i == AC97_AD_TEST || i == AC97_AD_CODEC_CFG || i == AC97_AD_SERIAL_CFG) continue; /* ignore */ } snd_ac97_write(ac97, i, ac97->regs[i]); snd_ac97_read(ac97, i); } } snd_ac97_restore_iec958(ac97); } static void ad1888_resume(struct snd_ac97 *ac97) { ad18xx_resume(ac97); snd_ac97_write_cache(ac97, AC97_CODEC_CLASS_REV, 0x8080); } #endif static const struct snd_ac97_res_table ad1819_restbl[] = { { AC97_PHONE, 0x9f1f }, { AC97_MIC, 0x9f1f }, { AC97_LINE, 0x9f1f }, { AC97_CD, 0x9f1f }, { AC97_VIDEO, 0x9f1f }, { AC97_AUX, 0x9f1f }, { AC97_PCM, 0x9f1f }, { } /* terminator */ }; static int patch_ad1819(struct snd_ac97 * ac97) { unsigned short scfg; // patch for Analog Devices scfg = snd_ac97_read(ac97, AC97_AD_SERIAL_CFG); snd_ac97_write_cache(ac97, AC97_AD_SERIAL_CFG, scfg | 0x7000); /* select all codecs */ ac97->res_table = ad1819_restbl; return 0; } static unsigned short patch_ad1881_unchained(struct snd_ac97 * ac97, int idx, unsigned short mask) { unsigned short val; // test for unchained codec snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, mask); snd_ac97_write_cache(ac97, AC97_AD_CODEC_CFG, 0x0000); /* ID0C, ID1C, SDIE = off */ val = snd_ac97_read(ac97, AC97_VENDOR_ID2); if ((val & 0xff40) != 0x5340) return 0; ac97->spec.ad18xx.unchained[idx] = mask; ac97->spec.ad18xx.id[idx] = val; ac97->spec.ad18xx.codec_cfg[idx] = 0x0000; return mask; } static int patch_ad1881_chained1(struct snd_ac97 * ac97, int idx, unsigned short codec_bits) { static const int cfg_bits[3] = { 1<<12, 1<<14, 1<<13 }; unsigned short val; snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, cfg_bits[idx]); snd_ac97_write_cache(ac97, AC97_AD_CODEC_CFG, 0x0004); // SDIE val = snd_ac97_read(ac97, AC97_VENDOR_ID2); if ((val & 0xff40) != 0x5340) return 0; if (codec_bits) snd_ac97_write_cache(ac97, AC97_AD_CODEC_CFG, codec_bits); ac97->spec.ad18xx.chained[idx] = cfg_bits[idx]; ac97->spec.ad18xx.id[idx] = val; ac97->spec.ad18xx.codec_cfg[idx] = codec_bits ? codec_bits : 0x0004; return 1; } static void patch_ad1881_chained(struct snd_ac97 * ac97, int unchained_idx, int cidx1, int cidx2) { // already detected? if (ac97->spec.ad18xx.unchained[cidx1] || ac97->spec.ad18xx.chained[cidx1]) cidx1 = -1; if (ac97->spec.ad18xx.unchained[cidx2] || ac97->spec.ad18xx.chained[cidx2]) cidx2 = -1; if (cidx1 < 0 && cidx2 < 0) return; // test for chained codecs snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, ac97->spec.ad18xx.unchained[unchained_idx]); snd_ac97_write_cache(ac97, AC97_AD_CODEC_CFG, 0x0002); // ID1C ac97->spec.ad18xx.codec_cfg[unchained_idx] = 0x0002; if (cidx1 >= 0) { if (cidx2 < 0) patch_ad1881_chained1(ac97, cidx1, 0); else if (patch_ad1881_chained1(ac97, cidx1, 0x0006)) // SDIE | ID1C patch_ad1881_chained1(ac97, cidx2, 0); else if (patch_ad1881_chained1(ac97, cidx2, 0x0006)) // SDIE | ID1C patch_ad1881_chained1(ac97, cidx1, 0); } else if (cidx2 >= 0) { patch_ad1881_chained1(ac97, cidx2, 0); } } static const struct snd_ac97_build_ops patch_ad1881_build_ops = { #ifdef CONFIG_PM .resume = ad18xx_resume #endif }; static int patch_ad1881(struct snd_ac97 * ac97) { static const char cfg_idxs[3][2] = { {2, 1}, {0, 2}, {0, 1} }; // patch for Analog Devices unsigned short codecs[3]; unsigned short val; int idx, num; val = snd_ac97_read(ac97, AC97_AD_SERIAL_CFG); snd_ac97_write_cache(ac97, AC97_AD_SERIAL_CFG, val); codecs[0] = patch_ad1881_unchained(ac97, 0, (1<<12)); codecs[1] = patch_ad1881_unchained(ac97, 1, (1<<14)); codecs[2] = patch_ad1881_unchained(ac97, 2, (1<<13)); if (! (codecs[0] || codecs[1] || codecs[2])) goto __end; for (idx = 0; idx < 3; idx++) if (ac97->spec.ad18xx.unchained[idx]) patch_ad1881_chained(ac97, idx, cfg_idxs[idx][0], cfg_idxs[idx][1]); if (ac97->spec.ad18xx.id[1]) { ac97->flags |= AC97_AD_MULTI; ac97->scaps |= AC97_SCAP_SURROUND_DAC; } if (ac97->spec.ad18xx.id[2]) { ac97->flags |= AC97_AD_MULTI; ac97->scaps |= AC97_SCAP_CENTER_LFE_DAC; } __end: /* select all codecs */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, 0x7000); /* check if only one codec is present */ for (idx = num = 0; idx < 3; idx++) if (ac97->spec.ad18xx.id[idx]) num++; if (num == 1) { /* ok, deselect all ID bits */ snd_ac97_write_cache(ac97, AC97_AD_CODEC_CFG, 0x0000); ac97->spec.ad18xx.codec_cfg[0] = ac97->spec.ad18xx.codec_cfg[1] = ac97->spec.ad18xx.codec_cfg[2] = 0x0000; } /* required for AD1886/AD1885 combination */ ac97->ext_id = snd_ac97_read(ac97, AC97_EXTENDED_ID); if (ac97->spec.ad18xx.id[0]) { ac97->id &= 0xffff0000; ac97->id |= ac97->spec.ad18xx.id[0]; } ac97->build_ops = &patch_ad1881_build_ops; return 0; } static const struct snd_kcontrol_new snd_ac97_controls_ad1885[] = { AC97_SINGLE("Digital Mono Direct", AC97_AD_MISC, 11, 1, 0), /* AC97_SINGLE("Digital Audio Mode", AC97_AD_MISC, 12, 1, 0), */ /* seems problematic */ AC97_SINGLE("Low Power Mixer", AC97_AD_MISC, 14, 1, 0), AC97_SINGLE("Zero Fill DAC", AC97_AD_MISC, 15, 1, 0), AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 9, 1, 1), /* inverted */ AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 8, 1, 1), /* inverted */ }; static const DECLARE_TLV_DB_SCALE(db_scale_6bit_6db_max, -8850, 150, 0); static int patch_ad1885_specific(struct snd_ac97 * ac97) { int err; err = patch_build_controls(ac97, snd_ac97_controls_ad1885, ARRAY_SIZE(snd_ac97_controls_ad1885)); if (err < 0) return err; reset_tlv(ac97, "Headphone Playback Volume", db_scale_6bit_6db_max); return 0; } static const struct snd_ac97_build_ops patch_ad1885_build_ops = { .build_specific = &patch_ad1885_specific, #ifdef CONFIG_PM .resume = ad18xx_resume #endif }; static int patch_ad1885(struct snd_ac97 * ac97) { patch_ad1881(ac97); /* This is required to deal with the Intel D815EEAL2 */ /* i.e. Line out is actually headphone out from codec */ /* set default */ snd_ac97_write_cache(ac97, AC97_AD_MISC, 0x0404); ac97->build_ops = &patch_ad1885_build_ops; return 0; } static int patch_ad1886_specific(struct snd_ac97 * ac97) { reset_tlv(ac97, "Headphone Playback Volume", db_scale_6bit_6db_max); return 0; } static const struct snd_ac97_build_ops patch_ad1886_build_ops = { .build_specific = &patch_ad1886_specific, #ifdef CONFIG_PM .resume = ad18xx_resume #endif }; static int patch_ad1886(struct snd_ac97 * ac97) { patch_ad1881(ac97); /* Presario700 workaround */ /* for Jack Sense/SPDIF Register misetting causing */ snd_ac97_write_cache(ac97, AC97_AD_JACK_SPDIF, 0x0010); ac97->build_ops = &patch_ad1886_build_ops; return 0; } /* MISC bits (AD1888/AD1980/AD1985 register 0x76) */ #define AC97_AD198X_MBC 0x0003 /* mic boost */ #define AC97_AD198X_MBC_20 0x0000 /* +20dB */ #define AC97_AD198X_MBC_10 0x0001 /* +10dB */ #define AC97_AD198X_MBC_30 0x0002 /* +30dB */ #define AC97_AD198X_VREFD 0x0004 /* VREF high-Z */ #define AC97_AD198X_VREFH 0x0008 /* 0=2.25V, 1=3.7V */ #define AC97_AD198X_VREF_0 0x000c /* 0V (AD1985 only) */ #define AC97_AD198X_VREF_MASK (AC97_AD198X_VREFH | AC97_AD198X_VREFD) #define AC97_AD198X_VREF_SHIFT 2 #define AC97_AD198X_SRU 0x0010 /* sample rate unlock */ #define AC97_AD198X_LOSEL 0x0020 /* LINE_OUT amplifiers input select */ #define AC97_AD198X_2MIC 0x0040 /* 2-channel mic select */ #define AC97_AD198X_SPRD 0x0080 /* SPREAD enable */ #define AC97_AD198X_DMIX0 0x0100 /* downmix mode: */ /* 0 = 6-to-4, 1 = 6-to-2 downmix */ #define AC97_AD198X_DMIX1 0x0200 /* downmix mode: 1 = enabled */ #define AC97_AD198X_HPSEL 0x0400 /* headphone amplifier input select */ #define AC97_AD198X_CLDIS 0x0800 /* center/lfe disable */ #define AC97_AD198X_LODIS 0x1000 /* LINE_OUT disable */ #define AC97_AD198X_MSPLT 0x2000 /* mute split */ #define AC97_AD198X_AC97NC 0x4000 /* AC97 no compatible mode */ #define AC97_AD198X_DACZ 0x8000 /* DAC zero-fill mode */ /* MISC 1 bits (AD1986 register 0x76) */ #define AC97_AD1986_MBC 0x0003 /* mic boost */ #define AC97_AD1986_MBC_20 0x0000 /* +20dB */ #define AC97_AD1986_MBC_10 0x0001 /* +10dB */ #define AC97_AD1986_MBC_30 0x0002 /* +30dB */ #define AC97_AD1986_LISEL0 0x0004 /* LINE_IN select bit 0 */ #define AC97_AD1986_LISEL1 0x0008 /* LINE_IN select bit 1 */ #define AC97_AD1986_LISEL_MASK (AC97_AD1986_LISEL1 | AC97_AD1986_LISEL0) #define AC97_AD1986_LISEL_LI 0x0000 /* LINE_IN pins as LINE_IN source */ #define AC97_AD1986_LISEL_SURR 0x0004 /* SURROUND pins as LINE_IN source */ #define AC97_AD1986_LISEL_MIC 0x0008 /* MIC_1/2 pins as LINE_IN source */ #define AC97_AD1986_SRU 0x0010 /* sample rate unlock */ #define AC97_AD1986_SOSEL 0x0020 /* SURROUND_OUT amplifiers input sel */ #define AC97_AD1986_2MIC 0x0040 /* 2-channel mic select */ #define AC97_AD1986_SPRD 0x0080 /* SPREAD enable */ #define AC97_AD1986_DMIX0 0x0100 /* downmix mode: */ /* 0 = 6-to-4, 1 = 6-to-2 downmix */ #define AC97_AD1986_DMIX1 0x0200 /* downmix mode: 1 = enabled */ #define AC97_AD1986_CLDIS 0x0800 /* center/lfe disable */ #define AC97_AD1986_SODIS 0x1000 /* SURROUND_OUT disable */ #define AC97_AD1986_MSPLT 0x2000 /* mute split (read only 1) */ #define AC97_AD1986_AC97NC 0x4000 /* AC97 no compatible mode (r/o 1) */ #define AC97_AD1986_DACZ 0x8000 /* DAC zero-fill mode */ /* MISC 2 bits (AD1986 register 0x70) */ #define AC97_AD_MISC2 0x70 /* Misc Control Bits 2 (AD1986) */ #define AC97_AD1986_CVREF0 0x0004 /* C/LFE VREF_OUT 2.25V */ #define AC97_AD1986_CVREF1 0x0008 /* C/LFE VREF_OUT 0V */ #define AC97_AD1986_CVREF2 0x0010 /* C/LFE VREF_OUT 3.7V */ #define AC97_AD1986_CVREF_MASK \ (AC97_AD1986_CVREF2 | AC97_AD1986_CVREF1 | AC97_AD1986_CVREF0) #define AC97_AD1986_JSMAP 0x0020 /* Jack Sense Mapping 1 = alternate */ #define AC97_AD1986_MMDIS 0x0080 /* Mono Mute Disable */ #define AC97_AD1986_MVREF0 0x0400 /* MIC VREF_OUT 2.25V */ #define AC97_AD1986_MVREF1 0x0800 /* MIC VREF_OUT 0V */ #define AC97_AD1986_MVREF2 0x1000 /* MIC VREF_OUT 3.7V */ #define AC97_AD1986_MVREF_MASK \ (AC97_AD1986_MVREF2 | AC97_AD1986_MVREF1 | AC97_AD1986_MVREF0) /* MISC 3 bits (AD1986 register 0x7a) */ #define AC97_AD_MISC3 0x7a /* Misc Control Bits 3 (AD1986) */ #define AC97_AD1986_MMIX 0x0004 /* Mic Mix, left/right */ #define AC97_AD1986_GPO 0x0008 /* General Purpose Out */ #define AC97_AD1986_LOHPEN 0x0010 /* LINE_OUT headphone drive */ #define AC97_AD1986_LVREF0 0x0100 /* LINE_OUT VREF_OUT 2.25V */ #define AC97_AD1986_LVREF1 0x0200 /* LINE_OUT VREF_OUT 0V */ #define AC97_AD1986_LVREF2 0x0400 /* LINE_OUT VREF_OUT 3.7V */ #define AC97_AD1986_LVREF_MASK \ (AC97_AD1986_LVREF2 | AC97_AD1986_LVREF1 | AC97_AD1986_LVREF0) #define AC97_AD1986_JSINVA 0x0800 /* Jack Sense Invert SENSE_A */ #define AC97_AD1986_LOSEL 0x1000 /* LINE_OUT amplifiers input select */ #define AC97_AD1986_HPSEL0 0x2000 /* Headphone amplifiers */ /* input select Surround DACs */ #define AC97_AD1986_HPSEL1 0x4000 /* Headphone amplifiers input */ /* select C/LFE DACs */ #define AC97_AD1986_JSINVB 0x8000 /* Jack Sense Invert SENSE_B */ /* Serial Config bits (AD1986 register 0x74) (incomplete) */ #define AC97_AD1986_OMS0 0x0100 /* Optional Mic Selector bit 0 */ #define AC97_AD1986_OMS1 0x0200 /* Optional Mic Selector bit 1 */ #define AC97_AD1986_OMS2 0x0400 /* Optional Mic Selector bit 2 */ #define AC97_AD1986_OMS_MASK \ (AC97_AD1986_OMS2 | AC97_AD1986_OMS1 | AC97_AD1986_OMS0) #define AC97_AD1986_OMS_M 0x0000 /* MIC_1/2 pins are MIC sources */ #define AC97_AD1986_OMS_L 0x0100 /* LINE_IN pins are MIC sources */ #define AC97_AD1986_OMS_C 0x0200 /* Center/LFE pins are MCI sources */ #define AC97_AD1986_OMS_MC 0x0400 /* Mix of MIC and C/LFE pins */ /* are MIC sources */ #define AC97_AD1986_OMS_ML 0x0500 /* MIX of MIC and LINE_IN pins */ /* are MIC sources */ #define AC97_AD1986_OMS_LC 0x0600 /* MIX of LINE_IN and C/LFE pins */ /* are MIC sources */ #define AC97_AD1986_OMS_MLC 0x0700 /* MIX of MIC, LINE_IN, C/LFE pins */ /* are MIC sources */ static int snd_ac97_ad198x_spdif_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[2] = { "AC-Link", "A/D Converter" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int snd_ac97_ad198x_spdif_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_AD_SERIAL_CFG]; ucontrol->value.enumerated.item[0] = (val >> 2) & 1; return 0; } static int snd_ac97_ad198x_spdif_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 1) return -EINVAL; val = ucontrol->value.enumerated.item[0] << 2; return snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x0004, val); } static const struct snd_kcontrol_new snd_ac97_ad198x_spdif_source = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Source", .info = snd_ac97_ad198x_spdif_source_info, .get = snd_ac97_ad198x_spdif_source_get, .put = snd_ac97_ad198x_spdif_source_put, }; static int patch_ad198x_post_spdif(struct snd_ac97 * ac97) { return patch_build_controls(ac97, &snd_ac97_ad198x_spdif_source, 1); } static const struct snd_kcontrol_new snd_ac97_ad1981x_jack_sense[] = { AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 11, 1, 0), AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0), }; /* deny list to avoid HP/Line jack-sense controls * (SS vendor << 16 | device) */ static const unsigned int ad1981_jacks_denylist[] = { 0x10140523, /* Thinkpad R40 */ 0x10140534, /* Thinkpad X31 */ 0x10140537, /* Thinkpad T41p */ 0x1014053e, /* Thinkpad R40e */ 0x10140554, /* Thinkpad T42p/R50p */ 0x10140567, /* Thinkpad T43p 2668-G7U */ 0x10140581, /* Thinkpad X41-2527 */ 0x10280160, /* Dell Dimension 2400 */ 0x104380b0, /* Asus A7V8X-MX */ 0x11790241, /* Toshiba Satellite A-15 S127 */ 0x1179ff10, /* Toshiba P500 */ 0x144dc01a, /* Samsung NP-X20C004/SEG */ 0 /* end */ }; static int check_list(struct snd_ac97 *ac97, const unsigned int *list) { u32 subid = ((u32)ac97->subsystem_vendor << 16) | ac97->subsystem_device; for (; *list; list++) if (*list == subid) return 1; return 0; } static int patch_ad1981a_specific(struct snd_ac97 * ac97) { if (check_list(ac97, ad1981_jacks_denylist)) return 0; return patch_build_controls(ac97, snd_ac97_ad1981x_jack_sense, ARRAY_SIZE(snd_ac97_ad1981x_jack_sense)); } static const struct snd_ac97_build_ops patch_ad1981a_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1981a_specific, #ifdef CONFIG_PM .resume = ad18xx_resume #endif }; /* allow list to enable HP jack-sense bits * (SS vendor << 16 | device) */ static const unsigned int ad1981_jacks_allowlist[] = { 0x0e11005a, /* HP nc4000/4010 */ 0x103c0890, /* HP nc6000 */ 0x103c0938, /* HP nc4220 */ 0x103c099c, /* HP nx6110 */ 0x103c0944, /* HP nc6220 */ 0x103c0934, /* HP nc8220 */ 0x103c006d, /* HP nx9105 */ 0x103c300d, /* HP Compaq dc5100 SFF(PT003AW) */ 0x17340088, /* FSC Scenic-W */ 0 /* end */ }; static void check_ad1981_hp_jack_sense(struct snd_ac97 *ac97) { if (check_list(ac97, ad1981_jacks_allowlist)) /* enable headphone jack sense */ snd_ac97_update_bits(ac97, AC97_AD_JACK_SPDIF, 1<<11, 1<<11); } static int patch_ad1981a(struct snd_ac97 *ac97) { patch_ad1881(ac97); ac97->build_ops = &patch_ad1981a_build_ops; snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD198X_MSPLT, AC97_AD198X_MSPLT); ac97->flags |= AC97_STEREO_MUTES; check_ad1981_hp_jack_sense(ac97); return 0; } static const struct snd_kcontrol_new snd_ac97_ad198x_2cmic = AC97_SINGLE("Stereo Mic", AC97_AD_MISC, 6, 1, 0); static int patch_ad1981b_specific(struct snd_ac97 *ac97) { int err; err = patch_build_controls(ac97, &snd_ac97_ad198x_2cmic, 1); if (err < 0) return err; if (check_list(ac97, ad1981_jacks_denylist)) return 0; return patch_build_controls(ac97, snd_ac97_ad1981x_jack_sense, ARRAY_SIZE(snd_ac97_ad1981x_jack_sense)); } static const struct snd_ac97_build_ops patch_ad1981b_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1981b_specific, #ifdef CONFIG_PM .resume = ad18xx_resume #endif }; static int patch_ad1981b(struct snd_ac97 *ac97) { patch_ad1881(ac97); ac97->build_ops = &patch_ad1981b_build_ops; snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD198X_MSPLT, AC97_AD198X_MSPLT); ac97->flags |= AC97_STEREO_MUTES; check_ad1981_hp_jack_sense(ac97); return 0; } #define snd_ac97_ad1888_lohpsel_info snd_ctl_boolean_mono_info static int snd_ac97_ad1888_lohpsel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_AD_MISC]; ucontrol->value.integer.value[0] = !(val & AC97_AD198X_LOSEL); if (ac97->spec.ad18xx.lo_as_master) ucontrol->value.integer.value[0] = !ucontrol->value.integer.value[0]; return 0; } static int snd_ac97_ad1888_lohpsel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = !ucontrol->value.integer.value[0]; if (ac97->spec.ad18xx.lo_as_master) val = !val; val = val ? (AC97_AD198X_LOSEL | AC97_AD198X_HPSEL) : 0; return snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD198X_LOSEL | AC97_AD198X_HPSEL, val); } static int snd_ac97_ad1888_downmix_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[3] = {"Off", "6 -> 4", "6 -> 2"}; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int snd_ac97_ad1888_downmix_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_AD_MISC]; if (!(val & AC97_AD198X_DMIX1)) ucontrol->value.enumerated.item[0] = 0; else ucontrol->value.enumerated.item[0] = 1 + ((val >> 8) & 1); return 0; } static int snd_ac97_ad1888_downmix_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 2) return -EINVAL; if (ucontrol->value.enumerated.item[0] == 0) val = 0; else val = AC97_AD198X_DMIX1 | ((ucontrol->value.enumerated.item[0] - 1) << 8); return snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD198X_DMIX0 | AC97_AD198X_DMIX1, val); } static void ad1888_update_jacks(struct snd_ac97 *ac97) { unsigned short val = 0; /* clear LODIS if shared jack is to be used for Surround out */ if (!ac97->spec.ad18xx.lo_as_master && is_shared_linein(ac97)) val |= (1 << 12); /* clear CLDIS if shared jack is to be used for C/LFE out */ if (is_shared_micin(ac97)) val |= (1 << 11); /* shared Line-In */ snd_ac97_update_bits(ac97, AC97_AD_MISC, (1 << 11) | (1 << 12), val); } static const struct snd_kcontrol_new snd_ac97_ad1888_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Exchange Front/Surround", .info = snd_ac97_ad1888_lohpsel_info, .get = snd_ac97_ad1888_lohpsel_get, .put = snd_ac97_ad1888_lohpsel_put }, AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, AC97_AD_VREFD_SHIFT, 1, 1), AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, AC97_AD_HPFD_SHIFT, 1, 1), AC97_SINGLE("Spread Front to Surround and Center/LFE", AC97_AD_MISC, 7, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Downmix", .info = snd_ac97_ad1888_downmix_info, .get = snd_ac97_ad1888_downmix_get, .put = snd_ac97_ad1888_downmix_put }, AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 10, 1, 0), AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0), }; static int patch_ad1888_specific(struct snd_ac97 *ac97) { if (!ac97->spec.ad18xx.lo_as_master) { /* rename 0x04 as "Master" and 0x02 as "Master Surround" */ snd_ac97_rename_vol_ctl(ac97, "Master Playback", "Master Surround Playback"); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Master Playback"); } return patch_build_controls(ac97, snd_ac97_ad1888_controls, ARRAY_SIZE(snd_ac97_ad1888_controls)); } static const struct snd_ac97_build_ops patch_ad1888_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1888_specific, #ifdef CONFIG_PM .resume = ad1888_resume, #endif .update_jacks = ad1888_update_jacks, }; static int patch_ad1888(struct snd_ac97 * ac97) { unsigned short misc; patch_ad1881(ac97); ac97->build_ops = &patch_ad1888_build_ops; /* * LO can be used as a real line-out on some devices, * and we need to revert the front/surround mixer switches */ if (ac97->subsystem_vendor == 0x1043 && ac97->subsystem_device == 0x1193) /* ASUS A9T laptop */ ac97->spec.ad18xx.lo_as_master = 1; misc = snd_ac97_read(ac97, AC97_AD_MISC); /* AD-compatible mode */ /* Stereo mutes enabled */ misc |= AC97_AD198X_MSPLT | AC97_AD198X_AC97NC; if (!ac97->spec.ad18xx.lo_as_master) /* Switch FRONT/SURROUND LINE-OUT/HP-OUT default connection */ /* it seems that most vendors connect line-out connector to * headphone out of AC'97 */ misc |= AC97_AD198X_LOSEL | AC97_AD198X_HPSEL; snd_ac97_write_cache(ac97, AC97_AD_MISC, misc); ac97->flags |= AC97_STEREO_MUTES; return 0; } static int patch_ad1980_specific(struct snd_ac97 *ac97) { int err; err = patch_ad1888_specific(ac97); if (err < 0) return err; return patch_build_controls(ac97, &snd_ac97_ad198x_2cmic, 1); } static const struct snd_ac97_build_ops patch_ad1980_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1980_specific, #ifdef CONFIG_PM .resume = ad18xx_resume, #endif .update_jacks = ad1888_update_jacks, }; static int patch_ad1980(struct snd_ac97 * ac97) { patch_ad1888(ac97); ac97->build_ops = &patch_ad1980_build_ops; return 0; } static int snd_ac97_ad1985_vrefout_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[4] = { "High-Z", "3.7 V", "2.25 V", "0 V" }; return snd_ctl_enum_info(uinfo, 1, 4, texts); } static int snd_ac97_ad1985_vrefout_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { static const int reg2ctrl[4] = {2, 0, 1, 3}; struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = (ac97->regs[AC97_AD_MISC] & AC97_AD198X_VREF_MASK) >> AC97_AD198X_VREF_SHIFT; ucontrol->value.enumerated.item[0] = reg2ctrl[val]; return 0; } static int snd_ac97_ad1985_vrefout_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { static const int ctrl2reg[4] = {1, 2, 0, 3}; struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; if (ucontrol->value.enumerated.item[0] > 3) return -EINVAL; val = ctrl2reg[ucontrol->value.enumerated.item[0]] << AC97_AD198X_VREF_SHIFT; return snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD198X_VREF_MASK, val); } static const struct snd_kcontrol_new snd_ac97_ad1985_controls[] = { AC97_SINGLE("Exchange Center/LFE", AC97_AD_SERIAL_CFG, 3, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Exchange Front/Surround", .info = snd_ac97_ad1888_lohpsel_info, .get = snd_ac97_ad1888_lohpsel_get, .put = snd_ac97_ad1888_lohpsel_put }, AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, 12, 1, 1), AC97_SINGLE("Spread Front to Surround and Center/LFE", AC97_AD_MISC, 7, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Downmix", .info = snd_ac97_ad1888_downmix_info, .get = snd_ac97_ad1888_downmix_get, .put = snd_ac97_ad1888_downmix_put }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "V_REFOUT", .info = snd_ac97_ad1985_vrefout_info, .get = snd_ac97_ad1985_vrefout_get, .put = snd_ac97_ad1985_vrefout_put }, AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 10, 1, 0), AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0), }; static void ad1985_update_jacks(struct snd_ac97 *ac97) { ad1888_update_jacks(ac97); /* clear OMS if shared jack is to be used for C/LFE out */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 1 << 9, is_shared_micin(ac97) ? 1 << 9 : 0); } static int patch_ad1985_specific(struct snd_ac97 *ac97) { int err; /* rename 0x04 as "Master" and 0x02 as "Master Surround" */ snd_ac97_rename_vol_ctl(ac97, "Master Playback", "Master Surround Playback"); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "Master Playback"); err = patch_build_controls(ac97, &snd_ac97_ad198x_2cmic, 1); if (err < 0) return err; return patch_build_controls(ac97, snd_ac97_ad1985_controls, ARRAY_SIZE(snd_ac97_ad1985_controls)); } static const struct snd_ac97_build_ops patch_ad1985_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1985_specific, #ifdef CONFIG_PM .resume = ad18xx_resume, #endif .update_jacks = ad1985_update_jacks, }; static int patch_ad1985(struct snd_ac97 * ac97) { unsigned short misc; patch_ad1881(ac97); ac97->build_ops = &patch_ad1985_build_ops; misc = snd_ac97_read(ac97, AC97_AD_MISC); /* switch front/surround line-out/hp-out */ /* AD-compatible mode */ /* Stereo mutes enabled */ snd_ac97_write_cache(ac97, AC97_AD_MISC, misc | AC97_AD198X_LOSEL | AC97_AD198X_HPSEL | AC97_AD198X_MSPLT | AC97_AD198X_AC97NC); ac97->flags |= AC97_STEREO_MUTES; /* update current jack configuration */ ad1985_update_jacks(ac97); /* on AD1985 rev. 3, AC'97 revision bits are zero */ ac97->ext_id = (ac97->ext_id & ~AC97_EI_REV_MASK) | AC97_EI_REV_23; return 0; } #define snd_ac97_ad1986_bool_info snd_ctl_boolean_mono_info static int snd_ac97_ad1986_lososel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_AD_MISC3]; ucontrol->value.integer.value[0] = (val & AC97_AD1986_LOSEL) != 0; return 0; } static int snd_ac97_ad1986_lososel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int ret0; int ret1; int sprd = (ac97->regs[AC97_AD_MISC] & AC97_AD1986_SPRD) != 0; ret0 = snd_ac97_update_bits(ac97, AC97_AD_MISC3, AC97_AD1986_LOSEL, ucontrol->value.integer.value[0] != 0 ? AC97_AD1986_LOSEL : 0); if (ret0 < 0) return ret0; /* SOSEL is set to values of "Spread" or "Exchange F/S" controls */ ret1 = snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD1986_SOSEL, (ucontrol->value.integer.value[0] != 0 || sprd) ? AC97_AD1986_SOSEL : 0); if (ret1 < 0) return ret1; return (ret0 > 0 || ret1 > 0) ? 1 : 0; } static int snd_ac97_ad1986_spread_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_AD_MISC]; ucontrol->value.integer.value[0] = (val & AC97_AD1986_SPRD) != 0; return 0; } static int snd_ac97_ad1986_spread_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int ret0; int ret1; int sprd = (ac97->regs[AC97_AD_MISC3] & AC97_AD1986_LOSEL) != 0; ret0 = snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD1986_SPRD, ucontrol->value.integer.value[0] != 0 ? AC97_AD1986_SPRD : 0); if (ret0 < 0) return ret0; /* SOSEL is set to values of "Spread" or "Exchange F/S" controls */ ret1 = snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD1986_SOSEL, (ucontrol->value.integer.value[0] != 0 || sprd) ? AC97_AD1986_SOSEL : 0); if (ret1 < 0) return ret1; return (ret0 > 0 || ret1 > 0) ? 1 : 0; } static int snd_ac97_ad1986_miclisel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = ac97->spec.ad18xx.swap_mic_linein; return 0; } static int snd_ac97_ad1986_miclisel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned char swap = ucontrol->value.integer.value[0] != 0; if (swap != ac97->spec.ad18xx.swap_mic_linein) { ac97->spec.ad18xx.swap_mic_linein = swap; if (ac97->build_ops->update_jacks) ac97->build_ops->update_jacks(ac97); return 1; } return 0; } static int snd_ac97_ad1986_vrefout_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* Use MIC_1/2 V_REFOUT as the "get" value */ struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; unsigned short reg = ac97->regs[AC97_AD_MISC2]; if ((reg & AC97_AD1986_MVREF0) != 0) val = 2; else if ((reg & AC97_AD1986_MVREF1) != 0) val = 3; else if ((reg & AC97_AD1986_MVREF2) != 0) val = 1; else val = 0; ucontrol->value.enumerated.item[0] = val; return 0; } static int snd_ac97_ad1986_vrefout_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short cval; unsigned short lval; unsigned short mval; int cret; int lret; int mret; switch (ucontrol->value.enumerated.item[0]) { case 0: /* High-Z */ cval = 0; lval = 0; mval = 0; break; case 1: /* 3.7 V */ cval = AC97_AD1986_CVREF2; lval = AC97_AD1986_LVREF2; mval = AC97_AD1986_MVREF2; break; case 2: /* 2.25 V */ cval = AC97_AD1986_CVREF0; lval = AC97_AD1986_LVREF0; mval = AC97_AD1986_MVREF0; break; case 3: /* 0 V */ cval = AC97_AD1986_CVREF1; lval = AC97_AD1986_LVREF1; mval = AC97_AD1986_MVREF1; break; default: return -EINVAL; } cret = snd_ac97_update_bits(ac97, AC97_AD_MISC2, AC97_AD1986_CVREF_MASK, cval); if (cret < 0) return cret; lret = snd_ac97_update_bits(ac97, AC97_AD_MISC3, AC97_AD1986_LVREF_MASK, lval); if (lret < 0) return lret; mret = snd_ac97_update_bits(ac97, AC97_AD_MISC2, AC97_AD1986_MVREF_MASK, mval); if (mret < 0) return mret; return (cret > 0 || lret > 0 || mret > 0) ? 1 : 0; } static const struct snd_kcontrol_new snd_ac97_ad1986_controls[] = { AC97_SINGLE("Exchange Center/LFE", AC97_AD_SERIAL_CFG, 3, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Exchange Front/Surround", .info = snd_ac97_ad1986_bool_info, .get = snd_ac97_ad1986_lososel_get, .put = snd_ac97_ad1986_lososel_put }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Exchange Mic/Line In", .info = snd_ac97_ad1986_bool_info, .get = snd_ac97_ad1986_miclisel_get, .put = snd_ac97_ad1986_miclisel_put }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Spread Front to Surround and Center/LFE", .info = snd_ac97_ad1986_bool_info, .get = snd_ac97_ad1986_spread_get, .put = snd_ac97_ad1986_spread_put }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Downmix", .info = snd_ac97_ad1888_downmix_info, .get = snd_ac97_ad1888_downmix_get, .put = snd_ac97_ad1888_downmix_put }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "V_REFOUT", .info = snd_ac97_ad1985_vrefout_info, .get = snd_ac97_ad1986_vrefout_get, .put = snd_ac97_ad1986_vrefout_put }, AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 10, 1, 0), AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0) }; static void ad1986_update_jacks(struct snd_ac97 *ac97) { unsigned short misc_val = 0; unsigned short ser_val; /* disable SURROUND and CENTER/LFE if not surround mode */ if (!is_surround_on(ac97)) misc_val |= AC97_AD1986_SODIS; if (!is_clfe_on(ac97)) misc_val |= AC97_AD1986_CLDIS; /* select line input (default=LINE_IN, SURROUND or MIC_1/2) */ if (is_shared_linein(ac97)) misc_val |= AC97_AD1986_LISEL_SURR; else if (ac97->spec.ad18xx.swap_mic_linein != 0) misc_val |= AC97_AD1986_LISEL_MIC; snd_ac97_update_bits(ac97, AC97_AD_MISC, AC97_AD1986_SODIS | AC97_AD1986_CLDIS | AC97_AD1986_LISEL_MASK, misc_val); /* select microphone input (MIC_1/2, Center/LFE or LINE_IN) */ if (is_shared_micin(ac97)) ser_val = AC97_AD1986_OMS_C; else if (ac97->spec.ad18xx.swap_mic_linein != 0) ser_val = AC97_AD1986_OMS_L; else ser_val = AC97_AD1986_OMS_M; snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, AC97_AD1986_OMS_MASK, ser_val); } static int patch_ad1986_specific(struct snd_ac97 *ac97) { int err; err = patch_build_controls(ac97, &snd_ac97_ad198x_2cmic, 1); if (err < 0) return err; return patch_build_controls(ac97, snd_ac97_ad1986_controls, ARRAY_SIZE(snd_ac97_ad1985_controls)); } static const struct snd_ac97_build_ops patch_ad1986_build_ops = { .build_post_spdif = patch_ad198x_post_spdif, .build_specific = patch_ad1986_specific, #ifdef CONFIG_PM .resume = ad18xx_resume, #endif .update_jacks = ad1986_update_jacks, }; static int patch_ad1986(struct snd_ac97 * ac97) { patch_ad1881(ac97); ac97->build_ops = &patch_ad1986_build_ops; ac97->flags |= AC97_STEREO_MUTES; /* update current jack configuration */ ad1986_update_jacks(ac97); return 0; } /* * realtek ALC203: use mono-out for pin 37 */ static int patch_alc203(struct snd_ac97 *ac97) { snd_ac97_update_bits(ac97, 0x7a, 0x400, 0x400); return 0; } /* * realtek ALC65x/850 codecs */ static void alc650_update_jacks(struct snd_ac97 *ac97) { int shared; /* shared Line-In / Surround Out */ shared = is_shared_surrout(ac97); snd_ac97_update_bits(ac97, AC97_ALC650_MULTICH, 1 << 9, shared ? (1 << 9) : 0); /* update shared Mic In / Center/LFE Out */ shared = is_shared_clfeout(ac97); /* disable/enable vref */ snd_ac97_update_bits(ac97, AC97_ALC650_CLOCK, 1 << 12, shared ? (1 << 12) : 0); /* turn on/off center-on-mic */ snd_ac97_update_bits(ac97, AC97_ALC650_MULTICH, 1 << 10, shared ? (1 << 10) : 0); /* GPIO0 high for mic */ snd_ac97_update_bits(ac97, AC97_ALC650_GPIO_STATUS, 0x100, shared ? 0 : 0x100); } static int alc650_swap_surround_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); struct snd_pcm_chmap *map = ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK]; if (map) { if (ucontrol->value.integer.value[0]) map->chmap = snd_pcm_std_chmaps; else map->chmap = snd_pcm_alt_chmaps; } return snd_ac97_put_volsw(kcontrol, ucontrol); } static const struct snd_kcontrol_new snd_ac97_controls_alc650[] = { AC97_SINGLE("Duplicate Front", AC97_ALC650_MULTICH, 0, 1, 0), AC97_SINGLE("Surround Down Mix", AC97_ALC650_MULTICH, 1, 1, 0), AC97_SINGLE("Center/LFE Down Mix", AC97_ALC650_MULTICH, 2, 1, 0), AC97_SINGLE("Exchange Center/LFE", AC97_ALC650_MULTICH, 3, 1, 0), /* 4: Analog Input To Surround */ /* 5: Analog Input To Center/LFE */ /* 6: Independent Master Volume Right */ /* 7: Independent Master Volume Left */ /* 8: reserved */ /* 9: Line-In/Surround share */ /* 10: Mic/CLFE share */ /* 11-13: in IEC958 controls */ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Swap Surround Slot", .info = snd_ac97_info_volsw, .get = snd_ac97_get_volsw, .put = alc650_swap_surround_put, .private_value = AC97_SINGLE_VALUE(AC97_ALC650_MULTICH, 14, 1, 0), }, #if 0 /* always set in patch_alc650 */ AC97_SINGLE("IEC958 Input Clock Enable", AC97_ALC650_CLOCK, 0, 1, 0), AC97_SINGLE("IEC958 Input Pin Enable", AC97_ALC650_CLOCK, 1, 1, 0), AC97_SINGLE("Surround DAC Switch", AC97_ALC650_SURR_DAC_VOL, 15, 1, 1), AC97_DOUBLE("Surround DAC Volume", AC97_ALC650_SURR_DAC_VOL, 8, 0, 31, 1), AC97_SINGLE("Center/LFE DAC Switch", AC97_ALC650_LFE_DAC_VOL, 15, 1, 1), AC97_DOUBLE("Center/LFE DAC Volume", AC97_ALC650_LFE_DAC_VOL, 8, 0, 31, 1), #endif AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, }; static const struct snd_kcontrol_new snd_ac97_spdif_controls_alc650[] = { AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), AC97_ALC650_MULTICH, 11, 1, 0), AC97_SINGLE("Analog to IEC958 Output", AC97_ALC650_MULTICH, 12, 1, 0), /* disable this controls since it doesn't work as expected */ /* AC97_SINGLE("IEC958 Input Monitor", AC97_ALC650_MULTICH, 13, 1, 0), */ }; static const DECLARE_TLV_DB_SCALE(db_scale_5bit_3db_max, -4350, 150, 0); static int patch_alc650_specific(struct snd_ac97 * ac97) { int err; err = patch_build_controls(ac97, snd_ac97_controls_alc650, ARRAY_SIZE(snd_ac97_controls_alc650)); if (err < 0) return err; if (ac97->ext_id & AC97_EI_SPDIF) { err = patch_build_controls(ac97, snd_ac97_spdif_controls_alc650, ARRAY_SIZE(snd_ac97_spdif_controls_alc650)); if (err < 0) return err; } if (ac97->id != AC97_ID_ALC650F) reset_tlv(ac97, "Master Playback Volume", db_scale_5bit_3db_max); return 0; } static const struct snd_ac97_build_ops patch_alc650_ops = { .build_specific = patch_alc650_specific, .update_jacks = alc650_update_jacks }; static int patch_alc650(struct snd_ac97 * ac97) { unsigned short val; ac97->build_ops = &patch_alc650_ops; /* determine the revision */ val = snd_ac97_read(ac97, AC97_ALC650_REVISION) & 0x3f; if (val < 3) ac97->id = 0x414c4720; /* Old version */ else if (val < 0x10) ac97->id = 0x414c4721; /* D version */ else if (val < 0x20) ac97->id = 0x414c4722; /* E version */ else if (val < 0x30) ac97->id = 0x414c4723; /* F version */ /* revision E or F */ /* FIXME: what about revision D ? */ ac97->spec.dev_flags = (ac97->id == 0x414c4722 || ac97->id == 0x414c4723); /* enable AC97_ALC650_GPIO_SETUP, AC97_ALC650_CLOCK for R/W */ snd_ac97_write_cache(ac97, AC97_ALC650_GPIO_STATUS, snd_ac97_read(ac97, AC97_ALC650_GPIO_STATUS) | 0x8000); /* Enable SPDIF-IN only on Rev.E and above */ val = snd_ac97_read(ac97, AC97_ALC650_CLOCK); /* SPDIF IN with pin 47 */ if (ac97->spec.dev_flags && /* ASUS A6KM requires EAPD */ ! (ac97->subsystem_vendor == 0x1043 && ac97->subsystem_device == 0x1103)) val |= 0x03; /* enable */ else val &= ~0x03; /* disable */ snd_ac97_write_cache(ac97, AC97_ALC650_CLOCK, val); /* set default: slot 3,4,7,8,6,9 spdif-in monitor off, analog-spdif off, spdif-in off center on mic off, surround on line-in off downmix off, duplicate front off */ snd_ac97_write_cache(ac97, AC97_ALC650_MULTICH, 0); /* set GPIO0 for mic bias */ /* GPIO0 pin output, no interrupt, high */ snd_ac97_write_cache(ac97, AC97_ALC650_GPIO_SETUP, snd_ac97_read(ac97, AC97_ALC650_GPIO_SETUP) | 0x01); snd_ac97_write_cache(ac97, AC97_ALC650_GPIO_STATUS, (snd_ac97_read(ac97, AC97_ALC650_GPIO_STATUS) | 0x100) & ~0x10); /* full DAC volume */ snd_ac97_write_cache(ac97, AC97_ALC650_SURR_DAC_VOL, 0x0808); snd_ac97_write_cache(ac97, AC97_ALC650_LFE_DAC_VOL, 0x0808); return 0; } static void alc655_update_jacks(struct snd_ac97 *ac97) { int shared; /* shared Line-In / Surround Out */ shared = is_shared_surrout(ac97); ac97_update_bits_page(ac97, AC97_ALC650_MULTICH, 1 << 9, shared ? (1 << 9) : 0, 0); /* update shared Mic In / Center/LFE Out */ shared = is_shared_clfeout(ac97); /* misc control; vrefout disable */ snd_ac97_update_bits(ac97, AC97_ALC650_CLOCK, 1 << 12, shared ? (1 << 12) : 0); ac97_update_bits_page(ac97, AC97_ALC650_MULTICH, 1 << 10, shared ? (1 << 10) : 0, 0); } static const struct snd_kcontrol_new snd_ac97_controls_alc655[] = { AC97_PAGE_SINGLE("Duplicate Front", AC97_ALC650_MULTICH, 0, 1, 0, 0), AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, }; static int alc655_iec958_route_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts_655[3] = { "PCM", "Analog In", "IEC958 In" }; static const char * const texts_658[4] = { "PCM", "Analog1 In", "Analog2 In", "IEC958 In" }; struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); if (ac97->spec.dev_flags) return snd_ctl_enum_info(uinfo, 1, 4, texts_658); else return snd_ctl_enum_info(uinfo, 1, 3, texts_655); } static int alc655_iec958_route_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_ALC650_MULTICH]; val = (val >> 12) & 3; if (ac97->spec.dev_flags && val == 3) val = 0; ucontrol->value.enumerated.item[0] = val; return 0; } static int alc655_iec958_route_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); return ac97_update_bits_page(ac97, AC97_ALC650_MULTICH, 3 << 12, (unsigned short)ucontrol->value.enumerated.item[0] << 12, 0); } static const struct snd_kcontrol_new snd_ac97_spdif_controls_alc655[] = { AC97_PAGE_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), AC97_ALC650_MULTICH, 11, 1, 0, 0), /* disable this controls since it doesn't work as expected */ /* AC97_PAGE_SINGLE("IEC958 Input Monitor", AC97_ALC650_MULTICH, 14, 1, 0, 0), */ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Source", .info = alc655_iec958_route_info, .get = alc655_iec958_route_get, .put = alc655_iec958_route_put, }, }; static int patch_alc655_specific(struct snd_ac97 * ac97) { int err; err = patch_build_controls(ac97, snd_ac97_controls_alc655, ARRAY_SIZE(snd_ac97_controls_alc655)); if (err < 0) return err; if (ac97->ext_id & AC97_EI_SPDIF) { err = patch_build_controls(ac97, snd_ac97_spdif_controls_alc655, ARRAY_SIZE(snd_ac97_spdif_controls_alc655)); if (err < 0) return err; } return 0; } static const struct snd_ac97_build_ops patch_alc655_ops = { .build_specific = patch_alc655_specific, .update_jacks = alc655_update_jacks }; static int patch_alc655(struct snd_ac97 * ac97) { unsigned int val; if (ac97->id == AC97_ID_ALC658) { ac97->spec.dev_flags = 1; /* ALC658 */ if ((snd_ac97_read(ac97, AC97_ALC650_REVISION) & 0x3f) == 2) { ac97->id = AC97_ID_ALC658D; ac97->spec.dev_flags = 2; } } ac97->build_ops = &patch_alc655_ops; /* assume only page 0 for writing cache */ snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_VENDOR); /* adjust default values */ val = snd_ac97_read(ac97, 0x7a); /* misc control */ if (ac97->spec.dev_flags) /* ALC658 */ val &= ~(1 << 1); /* Pin 47 is spdif input pin */ else { /* ALC655 */ if (ac97->subsystem_vendor == 0x1462 && (ac97->subsystem_device == 0x0131 || /* MSI S270 laptop */ ac97->subsystem_device == 0x0161 || /* LG K1 Express */ ac97->subsystem_device == 0x0351 || /* MSI L725 laptop */ ac97->subsystem_device == 0x0471 || /* MSI L720 laptop */ ac97->subsystem_device == 0x0061)) /* MSI S250 laptop */ val &= ~(1 << 1); /* Pin 47 is EAPD (for internal speaker) */ else val |= (1 << 1); /* Pin 47 is spdif input pin */ /* this seems missing on some hardwares */ ac97->ext_id |= AC97_EI_SPDIF; } val &= ~(1 << 12); /* vref enable */ snd_ac97_write_cache(ac97, 0x7a, val); /* set default: spdif-in enabled, spdif-in monitor off, spdif-in PCM off center on mic off, surround on line-in off duplicate front off */ snd_ac97_write_cache(ac97, AC97_ALC650_MULTICH, 1<<15); /* full DAC volume */ snd_ac97_write_cache(ac97, AC97_ALC650_SURR_DAC_VOL, 0x0808); snd_ac97_write_cache(ac97, AC97_ALC650_LFE_DAC_VOL, 0x0808); /* update undocumented bit... */ if (ac97->id == AC97_ID_ALC658D) snd_ac97_update_bits(ac97, 0x74, 0x0800, 0x0800); return 0; } #define AC97_ALC850_JACK_SELECT 0x76 #define AC97_ALC850_MISC1 0x7a #define AC97_ALC850_MULTICH 0x6a static void alc850_update_jacks(struct snd_ac97 *ac97) { int shared; int aux_is_back_surround; /* shared Line-In / Surround Out */ shared = is_shared_surrout(ac97); /* SURR 1kOhm (bit4), Amp (bit5) */ snd_ac97_update_bits(ac97, AC97_ALC850_MISC1, (1<<4)|(1<<5), shared ? (1<<5) : (1<<4)); /* LINE-IN = 0, SURROUND = 2 */ snd_ac97_update_bits(ac97, AC97_ALC850_JACK_SELECT, 7 << 12, shared ? (2<<12) : (0<<12)); /* update shared Mic In / Center/LFE Out */ shared = is_shared_clfeout(ac97); /* Vref disable (bit12), 1kOhm (bit13) */ snd_ac97_update_bits(ac97, AC97_ALC850_MISC1, (1<<12)|(1<<13), shared ? (1<<12) : (1<<13)); /* MIC-IN = 1, CENTER-LFE = 5 */ snd_ac97_update_bits(ac97, AC97_ALC850_JACK_SELECT, 7 << 4, shared ? (5<<4) : (1<<4)); aux_is_back_surround = alc850_is_aux_back_surround(ac97); /* Aux is Back Surround */ snd_ac97_update_bits(ac97, AC97_ALC850_MULTICH, 1 << 10, aux_is_back_surround ? (1<<10) : (0<<10)); } static const struct snd_kcontrol_new snd_ac97_controls_alc850[] = { AC97_PAGE_SINGLE("Duplicate Front", AC97_ALC650_MULTICH, 0, 1, 0, 0), AC97_SINGLE("Mic Front Input Switch", AC97_ALC850_JACK_SELECT, 15, 1, 1), AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_8CH_CTL, }; static int patch_alc850_specific(struct snd_ac97 *ac97) { int err; err = patch_build_controls(ac97, snd_ac97_controls_alc850, ARRAY_SIZE(snd_ac97_controls_alc850)); if (err < 0) return err; if (ac97->ext_id & AC97_EI_SPDIF) { err = patch_build_controls(ac97, snd_ac97_spdif_controls_alc655, ARRAY_SIZE(snd_ac97_spdif_controls_alc655)); if (err < 0) return err; } return 0; } static const struct snd_ac97_build_ops patch_alc850_ops = { .build_specific = patch_alc850_specific, .update_jacks = alc850_update_jacks }; static int patch_alc850(struct snd_ac97 *ac97) { ac97->build_ops = &patch_alc850_ops; ac97->spec.dev_flags = 0; /* for IEC958 playback route - ALC655 compatible */ ac97->flags |= AC97_HAS_8CH; /* assume only page 0 for writing cache */ snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_VENDOR); /* adjust default values */ /* set default: spdif-in enabled, spdif-in monitor off, spdif-in PCM off center on mic off, surround on line-in off duplicate front off NB default bit 10=0 = Aux is Capture, not Back Surround */ snd_ac97_write_cache(ac97, AC97_ALC650_MULTICH, 1<<15); /* SURR_OUT: on, Surr 1kOhm: on, Surr Amp: off, Front 1kOhm: off * Front Amp: on, Vref: enable, Center 1kOhm: on, Mix: on */ snd_ac97_write_cache(ac97, 0x7a, (1<<1)|(1<<4)|(0<<5)|(1<<6)| (1<<7)|(0<<12)|(1<<13)|(0<<14)); /* detection UIO2,3: all path floating, UIO3: MIC, Vref2: disable, * UIO1: FRONT, Vref3: disable, UIO3: LINE, Front-Mic: mute */ snd_ac97_write_cache(ac97, 0x76, (0<<0)|(0<<2)|(1<<4)|(1<<7)|(2<<8)| (1<<11)|(0<<12)|(1<<15)); /* full DAC volume */ snd_ac97_write_cache(ac97, AC97_ALC650_SURR_DAC_VOL, 0x0808); snd_ac97_write_cache(ac97, AC97_ALC650_LFE_DAC_VOL, 0x0808); return 0; } static int patch_aztech_azf3328_specific(struct snd_ac97 *ac97) { struct snd_kcontrol *kctl_3d_center = snd_ac97_find_mixer_ctl(ac97, "3D Control - Center"); struct snd_kcontrol *kctl_3d_depth = snd_ac97_find_mixer_ctl(ac97, "3D Control - Depth"); /* * 3D register is different from AC97 standard layout * (also do some renaming, to resemble Windows driver naming) */ if (kctl_3d_center) { kctl_3d_center->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 1, 0x07, 0); snd_ac97_rename_vol_ctl(ac97, "3D Control - Center", "3D Control - Width" ); } if (kctl_3d_depth) kctl_3d_depth->private_value = AC97_SINGLE_VALUE(AC97_3D_CONTROL, 8, 0x03, 0); /* Aztech Windows driver calls the equivalent control "Modem Playback", thus rename it: */ snd_ac97_rename_vol_ctl(ac97, "Master Mono Playback", "Modem Playback" ); snd_ac97_rename_vol_ctl(ac97, "Headphone Playback", "FM Synth Playback" ); return 0; } static const struct snd_ac97_build_ops patch_aztech_azf3328_ops = { .build_specific = patch_aztech_azf3328_specific }; static int patch_aztech_azf3328(struct snd_ac97 *ac97) { ac97->build_ops = &patch_aztech_azf3328_ops; return 0; } /* * C-Media CM97xx codecs */ static void cm9738_update_jacks(struct snd_ac97 *ac97) { /* shared Line-In / Surround Out */ snd_ac97_update_bits(ac97, AC97_CM9738_VENDOR_CTRL, 1 << 10, is_shared_surrout(ac97) ? (1 << 10) : 0); } static const struct snd_kcontrol_new snd_ac97_cm9738_controls[] = { AC97_SINGLE("Duplicate Front", AC97_CM9738_VENDOR_CTRL, 13, 1, 0), AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_4CH_CTL, }; static int patch_cm9738_specific(struct snd_ac97 * ac97) { return patch_build_controls(ac97, snd_ac97_cm9738_controls, ARRAY_SIZE(snd_ac97_cm9738_controls)); } static const struct snd_ac97_build_ops patch_cm9738_ops = { .build_specific = patch_cm9738_specific, .update_jacks = cm9738_update_jacks }; static int patch_cm9738(struct snd_ac97 * ac97) { ac97->build_ops = &patch_cm9738_ops; /* FIXME: can anyone confirm below? */ /* CM9738 has no PCM volume although the register reacts */ ac97->flags |= AC97_HAS_NO_PCM_VOL; snd_ac97_write_cache(ac97, AC97_PCM, 0x8000); return 0; } static int snd_ac97_cmedia_spdif_playback_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[] = { "Analog", "Digital" }; return snd_ctl_enum_info(uinfo, 1, 2, texts); } static int snd_ac97_cmedia_spdif_playback_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); unsigned short val; val = ac97->regs[AC97_CM9739_SPDIF_CTRL]; ucontrol->value.enumerated.item[0] = (val >> 1) & 0x01; return 0; } static int snd_ac97_cmedia_spdif_playback_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); return snd_ac97_update_bits(ac97, AC97_CM9739_SPDIF_CTRL, 0x01 << 1, (ucontrol->value.enumerated.item[0] & 0x01) << 1); } static const struct snd_kcontrol_new snd_ac97_cm9739_controls_spdif[] = { /* BIT 0: SPDI_EN - always true */ { /* BIT 1: SPDIFS */ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Source", .info = snd_ac97_cmedia_spdif_playback_source_info, .get = snd_ac97_cmedia_spdif_playback_source_get, .put = snd_ac97_cmedia_spdif_playback_source_put, }, /* BIT 2: IG_SPIV */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,NONE) "Valid Switch", AC97_CM9739_SPDIF_CTRL, 2, 1, 0), /* BIT 3: SPI2F */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,NONE) "Monitor", AC97_CM9739_SPDIF_CTRL, 3, 1, 0), /* BIT 4: SPI2SDI */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), AC97_CM9739_SPDIF_CTRL, 4, 1, 0), /* BIT 8: SPD32 - 32bit SPDIF - not supported yet */ }; static void cm9739_update_jacks(struct snd_ac97 *ac97) { /* shared Line-In / Surround Out */ snd_ac97_update_bits(ac97, AC97_CM9739_MULTI_CHAN, 1 << 10, is_shared_surrout(ac97) ? (1 << 10) : 0); /* shared Mic In / Center/LFE Out **/ snd_ac97_update_bits(ac97, AC97_CM9739_MULTI_CHAN, 0x3000, is_shared_clfeout(ac97) ? 0x1000 : 0x2000); } static const struct snd_kcontrol_new snd_ac97_cm9739_controls[] = { AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, }; static int patch_cm9739_specific(struct snd_ac97 * ac97) { return patch_build_controls(ac97, snd_ac97_cm9739_controls, ARRAY_SIZE(snd_ac97_cm9739_controls)); } static int patch_cm9739_post_spdif(struct snd_ac97 * ac97) { return patch_build_controls(ac97, snd_ac97_cm9739_controls_spdif, ARRAY_SIZE(snd_ac97_cm9739_controls_spdif)); } static const struct snd_ac97_build_ops patch_cm9739_ops = { .build_specific = patch_cm9739_specific, .build_post_spdif = patch_cm9739_post_spdif, .update_jacks = cm9739_update_jacks }; static int patch_cm9739(struct snd_ac97 * ac97) { unsigned short val; ac97->build_ops = &patch_cm9739_ops; /* CM9739/A has no Master and PCM volume although the register reacts */ ac97->flags |= AC97_HAS_NO_MASTER_VOL | AC97_HAS_NO_PCM_VOL; snd_ac97_write_cache(ac97, AC97_MASTER, 0x8000); snd_ac97_write_cache(ac97, AC97_PCM, 0x8000); /* check spdif */ val = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); if (val & AC97_EA_SPCV) { /* enable spdif in */ snd_ac97_write_cache(ac97, AC97_CM9739_SPDIF_CTRL, snd_ac97_read(ac97, AC97_CM9739_SPDIF_CTRL) | 0x01); ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000; /* 48k only */ } else { ac97->ext_id &= ~AC97_EI_SPDIF; /* disable extended-id */ ac97->rates[AC97_RATES_SPDIF] = 0; } /* set-up multi channel */ /* bit 14: 0 = SPDIF, 1 = EAPD */ /* bit 13: enable internal vref output for mic */ /* bit 12: disable center/lfe (switchable) */ /* bit 10: disable surround/line (switchable) */ /* bit 9: mix 2 surround off */ /* bit 4: undocumented; 0 mutes the CM9739A, which defaults to 1 */ /* bit 3: undocumented; surround? */ /* bit 0: dB */ val = snd_ac97_read(ac97, AC97_CM9739_MULTI_CHAN) & (1 << 4); val |= (1 << 3); val |= (1 << 13); if (! (ac97->ext_id & AC97_EI_SPDIF)) val |= (1 << 14); snd_ac97_write_cache(ac97, AC97_CM9739_MULTI_CHAN, val); /* FIXME: set up GPIO */ snd_ac97_write_cache(ac97, 0x70, 0x0100); snd_ac97_write_cache(ac97, 0x72, 0x0020); /* Special exception for ASUS W1000/CMI9739. It does not have an SPDIF in. */ if (ac97->pci && ac97->subsystem_vendor == 0x1043 && ac97->subsystem_device == 0x1843) { snd_ac97_write_cache(ac97, AC97_CM9739_SPDIF_CTRL, snd_ac97_read(ac97, AC97_CM9739_SPDIF_CTRL) & ~0x01); snd_ac97_write_cache(ac97, AC97_CM9739_MULTI_CHAN, snd_ac97_read(ac97, AC97_CM9739_MULTI_CHAN) | (1 << 14)); } return 0; } #define AC97_CM9761_MULTI_CHAN 0x64 #define AC97_CM9761_FUNC 0x66 #define AC97_CM9761_SPDIF_CTRL 0x6c static void cm9761_update_jacks(struct snd_ac97 *ac97) { /* FIXME: check the bits for each model * model 83 is confirmed to work */ static const unsigned short surr_on[3][2] = { { 0x0008, 0x0000 }, /* 9761-78 & 82 */ { 0x0000, 0x0008 }, /* 9761-82 rev.B */ { 0x0000, 0x0008 }, /* 9761-83 */ }; static const unsigned short clfe_on[3][2] = { { 0x0000, 0x1000 }, /* 9761-78 & 82 */ { 0x1000, 0x0000 }, /* 9761-82 rev.B */ { 0x0000, 0x1000 }, /* 9761-83 */ }; static const unsigned short surr_shared[3][2] = { { 0x0000, 0x0400 }, /* 9761-78 & 82 */ { 0x0000, 0x0400 }, /* 9761-82 rev.B */ { 0x0000, 0x0400 }, /* 9761-83 */ }; static const unsigned short clfe_shared[3][2] = { { 0x2000, 0x0880 }, /* 9761-78 & 82 */ { 0x0000, 0x2880 }, /* 9761-82 rev.B */ { 0x2000, 0x0800 }, /* 9761-83 */ }; unsigned short val = 0; val |= surr_on[ac97->spec.dev_flags][is_surround_on(ac97)]; val |= clfe_on[ac97->spec.dev_flags][is_clfe_on(ac97)]; val |= surr_shared[ac97->spec.dev_flags][is_shared_surrout(ac97)]; val |= clfe_shared[ac97->spec.dev_flags][is_shared_clfeout(ac97)]; snd_ac97_update_bits(ac97, AC97_CM9761_MULTI_CHAN, 0x3c88, val); } static const struct snd_kcontrol_new snd_ac97_cm9761_controls[] = { AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, }; static int cm9761_spdif_out_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const texts[] = { "AC-Link", "ADC", "SPDIF-In" }; return snd_ctl_enum_info(uinfo, 1, 3, texts); } static int cm9761_spdif_out_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); if (ac97->regs[AC97_CM9761_FUNC] & 0x1) ucontrol->value.enumerated.item[0] = 2; /* SPDIF-loopback */ else if (ac97->regs[AC97_CM9761_SPDIF_CTRL] & 0x2) ucontrol->value.enumerated.item[0] = 1; /* ADC loopback */ else ucontrol->value.enumerated.item[0] = 0; /* AC-link */ return 0; } static int cm9761_spdif_out_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); if (ucontrol->value.enumerated.item[0] == 2) return snd_ac97_update_bits(ac97, AC97_CM9761_FUNC, 0x1, 0x1); snd_ac97_update_bits(ac97, AC97_CM9761_FUNC, 0x1, 0); return snd_ac97_update_bits(ac97, AC97_CM9761_SPDIF_CTRL, 0x2, ucontrol->value.enumerated.item[0] == 1 ? 0x2 : 0); } static const char * const cm9761_dac_clock[] = { "AC-Link", "SPDIF-In", "Both" }; static const struct ac97_enum cm9761_dac_clock_enum = AC97_ENUM_SINGLE(AC97_CM9761_SPDIF_CTRL, 9, 3, cm9761_dac_clock); static const struct snd_kcontrol_new snd_ac97_cm9761_controls_spdif[] = { { /* BIT 1: SPDIFS */ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Source", .info = cm9761_spdif_out_source_info, .get = cm9761_spdif_out_source_get, .put = cm9761_spdif_out_source_put, }, /* BIT 2: IG_SPIV */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,NONE) "Valid Switch", AC97_CM9761_SPDIF_CTRL, 2, 1, 0), /* BIT 3: SPI2F */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,NONE) "Monitor", AC97_CM9761_SPDIF_CTRL, 3, 1, 0), /* BIT 4: SPI2SDI */ AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), AC97_CM9761_SPDIF_CTRL, 4, 1, 0), /* BIT 9-10: DAC_CTL */ AC97_ENUM("DAC Clock Source", cm9761_dac_clock_enum), }; static int patch_cm9761_post_spdif(struct snd_ac97 * ac97) { return patch_build_controls(ac97, snd_ac97_cm9761_controls_spdif, ARRAY_SIZE(snd_ac97_cm9761_controls_spdif)); } static int patch_cm9761_specific(struct snd_ac97 * ac97) { return patch_build_controls(ac97, snd_ac97_cm9761_controls, ARRAY_SIZE(snd_ac97_cm9761_controls)); } static const struct snd_ac97_build_ops patch_cm9761_ops = { .build_specific = patch_cm9761_specific, .build_post_spdif = patch_cm9761_post_spdif, .update_jacks = cm9761_update_jacks }; static int patch_cm9761(struct snd_ac97 *ac97) { unsigned short val; /* CM9761 has no PCM volume although the register reacts */ /* Master volume seems to have _some_ influence on the analog * input sounds */ ac97->flags |= /*AC97_HAS_NO_MASTER_VOL |*/ AC97_HAS_NO_PCM_VOL; snd_ac97_write_cache(ac97, AC97_MASTER, 0x8808); snd_ac97_write_cache(ac97, AC97_PCM, 0x8808); ac97->spec.dev_flags = 0; /* 1 = model 82 revision B, 2 = model 83 */ if (ac97->id == AC97_ID_CM9761_82) { unsigned short tmp; /* check page 1, reg 0x60 */ val = snd_ac97_read(ac97, AC97_INT_PAGING); snd_ac97_write_cache(ac97, AC97_INT_PAGING, (val & ~0x0f) | 0x01); tmp = snd_ac97_read(ac97, 0x60); ac97->spec.dev_flags = tmp & 1; /* revision B? */ snd_ac97_write_cache(ac97, AC97_INT_PAGING, val); } else if (ac97->id == AC97_ID_CM9761_83) ac97->spec.dev_flags = 2; ac97->build_ops = &patch_cm9761_ops; /* enable spdif */ /* force the SPDIF bit in ext_id - codec doesn't set this bit! */ ac97->ext_id |= AC97_EI_SPDIF; /* to be sure: we overwrite the ext status bits */ snd_ac97_write_cache(ac97, AC97_EXTENDED_STATUS, 0x05c0); /* Don't set 0x0200 here. This results in the silent analog output */ snd_ac97_write_cache(ac97, AC97_CM9761_SPDIF_CTRL, 0x0001); /* enable spdif-in */ ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000; /* 48k only */ /* set-up multi channel */ /* bit 15: pc master beep off * bit 14: pin47 = EAPD/SPDIF * bit 13: vref ctl [= cm9739] * bit 12: CLFE control (reverted on rev B) * bit 11: Mic/center share (reverted on rev B) * bit 10: suddound/line share * bit 9: Analog-in mix -> surround * bit 8: Analog-in mix -> CLFE * bit 7: Mic/LFE share (mic/center/lfe) * bit 5: vref select (9761A) * bit 4: front control * bit 3: surround control (revereted with rev B) * bit 2: front mic * bit 1: stereo mic * bit 0: mic boost level (0=20dB, 1=30dB) */ #if 0 if (ac97->spec.dev_flags) val = 0x0214; else val = 0x321c; #endif val = snd_ac97_read(ac97, AC97_CM9761_MULTI_CHAN); val |= (1 << 4); /* front on */ snd_ac97_write_cache(ac97, AC97_CM9761_MULTI_CHAN, val); /* FIXME: set up GPIO */ snd_ac97_write_cache(ac97, 0x70, 0x0100); snd_ac97_write_cache(ac97, 0x72, 0x0020); return 0; } #define AC97_CM9780_SIDE 0x60 #define AC97_CM9780_JACK 0x62 #define AC97_CM9780_MIXER 0x64 #define AC97_CM9780_MULTI_CHAN 0x66 #define AC97_CM9780_SPDIF 0x6c static const char * const cm9780_ch_select[] = { "Front", "Side", "Center/LFE", "Rear" }; static const struct ac97_enum cm9780_ch_select_enum = AC97_ENUM_SINGLE(AC97_CM9780_MULTI_CHAN, 6, 4, cm9780_ch_select); static const struct snd_kcontrol_new cm9780_controls[] = { AC97_DOUBLE("Side Playback Switch", AC97_CM9780_SIDE, 15, 7, 1, 1), AC97_DOUBLE("Side Playback Volume", AC97_CM9780_SIDE, 8, 0, 31, 0), AC97_ENUM("Side Playback Route", cm9780_ch_select_enum), }; static int patch_cm9780_specific(struct snd_ac97 *ac97) { return patch_build_controls(ac97, cm9780_controls, ARRAY_SIZE(cm9780_controls)); } static const struct snd_ac97_build_ops patch_cm9780_ops = { .build_specific = patch_cm9780_specific, .build_post_spdif = patch_cm9761_post_spdif /* identical with CM9761 */ }; static int patch_cm9780(struct snd_ac97 *ac97) { unsigned short val; ac97->build_ops = &patch_cm9780_ops; /* enable spdif */ if (ac97->ext_id & AC97_EI_SPDIF) { ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_48000; /* 48k only */ val = snd_ac97_read(ac97, AC97_CM9780_SPDIF); val |= 0x1; /* SPDI_EN */ snd_ac97_write_cache(ac97, AC97_CM9780_SPDIF, val); } return 0; } /* * VIA VT1613 codec */ static const struct snd_kcontrol_new snd_ac97_controls_vt1613[] = { AC97_SINGLE("DC Offset removal", 0x5a, 10, 1, 0), }; static int patch_vt1613_specific(struct snd_ac97 *ac97) { return patch_build_controls(ac97, &snd_ac97_controls_vt1613[0], ARRAY_SIZE(snd_ac97_controls_vt1613)); }; static const struct snd_ac97_build_ops patch_vt1613_ops = { .build_specific = patch_vt1613_specific }; static int patch_vt1613(struct snd_ac97 *ac97) { ac97->build_ops = &patch_vt1613_ops; ac97->flags |= AC97_HAS_NO_VIDEO; ac97->caps |= AC97_BC_HEADPHONE; return 0; } /* * VIA VT1616 codec */ static const struct snd_kcontrol_new snd_ac97_controls_vt1616[] = { AC97_SINGLE("DC Offset removal", 0x5a, 10, 1, 0), AC97_SINGLE("Alternate Level to Surround Out", 0x5a, 15, 1, 0), AC97_SINGLE("Downmix LFE and Center to Front", 0x5a, 12, 1, 0), AC97_SINGLE("Downmix Surround to Front", 0x5a, 11, 1, 0), }; static const char * const follower_vols_vt1616[] = { "Front Playback Volume", "Surround Playback Volume", "Center Playback Volume", "LFE Playback Volume", NULL }; static const char * const follower_sws_vt1616[] = { "Front Playback Switch", "Surround Playback Switch", "Center Playback Switch", "LFE Playback Switch", NULL }; /* find a mixer control element with the given name */ static struct snd_kcontrol *snd_ac97_find_mixer_ctl(struct snd_ac97 *ac97, const char *name) { return snd_ctl_find_id_mixer(ac97->bus->card, name); } /* create a virtual master control and add followers */ static int snd_ac97_add_vmaster(struct snd_ac97 *ac97, char *name, const unsigned int *tlv, const char * const *followers) { struct snd_kcontrol *kctl; int err; kctl = snd_ctl_make_virtual_master(name, tlv); if (!kctl) return -ENOMEM; err = snd_ctl_add(ac97->bus->card, kctl); if (err < 0) return err; return snd_ctl_add_followers(ac97->bus->card, kctl, followers); } static int patch_vt1616_specific(struct snd_ac97 * ac97) { struct snd_kcontrol *kctl; int err; if (snd_ac97_try_bit(ac97, 0x5a, 9)) { err = patch_build_controls(ac97, &snd_ac97_controls_vt1616[0], 1); if (err < 0) return err; } err = patch_build_controls(ac97, &snd_ac97_controls_vt1616[1], ARRAY_SIZE(snd_ac97_controls_vt1616) - 1); if (err < 0) return err; /* There is already a misnamed master switch. Rename it. */ kctl = snd_ac97_find_mixer_ctl(ac97, "Master Playback Volume"); if (!kctl) return -EINVAL; snd_ac97_rename_vol_ctl(ac97, "Master Playback", "Front Playback"); err = snd_ac97_add_vmaster(ac97, "Master Playback Volume", kctl->tlv.p, follower_vols_vt1616); if (err < 0) return err; err = snd_ac97_add_vmaster(ac97, "Master Playback Switch", NULL, follower_sws_vt1616); if (err < 0) return err; return 0; } static const struct snd_ac97_build_ops patch_vt1616_ops = { .build_specific = patch_vt1616_specific }; static int patch_vt1616(struct snd_ac97 * ac97) { ac97->build_ops = &patch_vt1616_ops; return 0; } /* * VT1617A codec */ /* * unfortunately, the vt1617a stashes the twiddlers required for * noodling the i/o jacks on 2 different regs. that means that we can't * use the easy way provided by AC97_ENUM_DOUBLE() we have to write * are own funcs. * * NB: this is absolutely and utterly different from the vt1618. dunno * about the 1616. */ /* copied from ac97_surround_jack_mode_info() */ static int snd_ac97_vt1617a_smart51_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { /* ordering in this list reflects vt1617a docs for Reg 20 and * 7a and Table 6 that lays out the matrix NB WRT Table6: SM51 * is SM51EN *AND* it's Bit14, not Bit15 so the table is very * counter-intuitive */ static const char * const texts[] = {"LineIn Mic1", "LineIn Mic1 Mic3", "Surr LFE/C Mic3", "LineIn LFE/C Mic3", "LineIn Mic2", "LineIn Mic2 Mic1", "Surr LFE Mic1", "Surr LFE Mic1 Mic2"}; return snd_ctl_enum_info(uinfo, 1, 8, texts); } static int snd_ac97_vt1617a_smart51_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ushort usSM51, usMS; struct snd_ac97 *pac97; pac97 = snd_kcontrol_chip(kcontrol); /* grab codec handle */ /* grab our desired bits, then mash them together in a manner * consistent with Table 6 on page 17 in the 1617a docs */ usSM51 = snd_ac97_read(pac97, 0x7a) >> 14; usMS = snd_ac97_read(pac97, 0x20) >> 8; ucontrol->value.enumerated.item[0] = (usSM51 << 1) + usMS; return 0; } static int snd_ac97_vt1617a_smart51_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ushort usSM51, usMS, usReg; struct snd_ac97 *pac97; pac97 = snd_kcontrol_chip(kcontrol); /* grab codec handle */ usSM51 = ucontrol->value.enumerated.item[0] >> 1; usMS = ucontrol->value.enumerated.item[0] & 1; /* push our values into the register - consider that things will be left * in a funky state if the write fails */ usReg = snd_ac97_read(pac97, 0x7a); snd_ac97_write_cache(pac97, 0x7a, (usReg & 0x3FFF) + (usSM51 << 14)); usReg = snd_ac97_read(pac97, 0x20); snd_ac97_write_cache(pac97, 0x20, (usReg & 0xFEFF) + (usMS << 8)); return 0; } static const struct snd_kcontrol_new snd_ac97_controls_vt1617a[] = { AC97_SINGLE("Center/LFE Exchange", 0x5a, 8, 1, 0), /* * These are used to enable/disable surround sound on motherboards * that have 3 bidirectional analog jacks */ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Smart 5.1 Select", .info = snd_ac97_vt1617a_smart51_info, .get = snd_ac97_vt1617a_smart51_get, .put = snd_ac97_vt1617a_smart51_put, }, }; static int patch_vt1617a(struct snd_ac97 * ac97) { int err = 0; int val; /* we choose to not fail out at this point, but we tell the caller when we return */ err = patch_build_controls(ac97, &snd_ac97_controls_vt1617a[0], ARRAY_SIZE(snd_ac97_controls_vt1617a)); /* bring analog power consumption to normal by turning off the * headphone amplifier, like WinXP driver for EPIA SP */ /* We need to check the bit before writing it. * On some (many?) hardwares, setting bit actually clears it! */ val = snd_ac97_read(ac97, 0x5c); if (!(val & 0x20)) snd_ac97_write_cache(ac97, 0x5c, 0x20); ac97->ext_id |= AC97_EI_SPDIF; /* force the detection of spdif */ ac97->rates[AC97_RATES_SPDIF] = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; ac97->build_ops = &patch_vt1616_ops; return err; } /* VIA VT1618 8 CHANNEL AC97 CODEC * * VIA implements 'Smart 5.1' completely differently on the 1618 than * it does on the 1617a. awesome! They seem to have sourced this * particular revision of the technology from somebody else, it's * called Universal Audio Jack and it shows up on some other folk's chips * as well. * * ordering in this list reflects vt1618 docs for Reg 60h and * the block diagram, DACs are as follows: * * OUT_O -> Front, * OUT_1 -> Surround, * OUT_2 -> C/LFE * * Unlike the 1617a, each OUT has a consistent set of mappings * for all bitpatterns other than 00: * * 01 Unmixed Output * 10 Line In * 11 Mic In * * Special Case of 00: * * OUT_0 Mixed Output * OUT_1 Reserved * OUT_2 Reserved * * I have no idea what the hell Reserved does, but on an MSI * CN700T, i have to set it to get 5.1 output - YMMV, bad * shit may happen. * * If other chips use Universal Audio Jack, then this code might be applicable * to them. */ struct vt1618_uaj_item { unsigned short mask; unsigned short shift; const char * const items[4]; }; /* This list reflects the vt1618 docs for Vendor Defined Register 0x60. */ static const struct vt1618_uaj_item vt1618_uaj[3] = { { /* speaker jack */ .mask = 0x03, .shift = 0, .items = { "Speaker Out", "DAC Unmixed Out", "Line In", "Mic In" } }, { /* line jack */ .mask = 0x0c, .shift = 2, .items = { "Surround Out", "DAC Unmixed Out", "Line In", "Mic In" } }, { /* mic jack */ .mask = 0x30, .shift = 4, .items = { "Center LFE Out", "DAC Unmixed Out", "Line In", "Mic In" }, }, }; static int snd_ac97_vt1618_UAJ_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { return snd_ctl_enum_info(uinfo, 1, 4, vt1618_uaj[kcontrol->private_value].items); } /* All of the vt1618 Universal Audio Jack twiddlers are on * Vendor Defined Register 0x60, page 0. The bits, and thus * the mask, are the only thing that changes */ static int snd_ac97_vt1618_UAJ_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { unsigned short datpag, uaj; struct snd_ac97 *pac97 = snd_kcontrol_chip(kcontrol); mutex_lock(&pac97->page_mutex); datpag = snd_ac97_read(pac97, AC97_INT_PAGING) & AC97_PAGE_MASK; snd_ac97_update_bits(pac97, AC97_INT_PAGING, AC97_PAGE_MASK, 0); uaj = snd_ac97_read(pac97, 0x60) & vt1618_uaj[kcontrol->private_value].mask; snd_ac97_update_bits(pac97, AC97_INT_PAGING, AC97_PAGE_MASK, datpag); mutex_unlock(&pac97->page_mutex); ucontrol->value.enumerated.item[0] = uaj >> vt1618_uaj[kcontrol->private_value].shift; return 0; } static int snd_ac97_vt1618_UAJ_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { return ac97_update_bits_page(snd_kcontrol_chip(kcontrol), 0x60, vt1618_uaj[kcontrol->private_value].mask, ucontrol->value.enumerated.item[0]<< vt1618_uaj[kcontrol->private_value].shift, 0); } /* config aux in jack - not found on 3 jack motherboards or soundcards */ static int snd_ac97_vt1618_aux_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const txt_aux[] = {"Aux In", "Back Surr Out"}; return snd_ctl_enum_info(uinfo, 1, 2, txt_aux); } static int snd_ac97_vt1618_aux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.enumerated.item[0] = (snd_ac97_read(snd_kcontrol_chip(kcontrol), 0x5c) & 0x0008)>>3; return 0; } static int snd_ac97_vt1618_aux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* toggle surround rear dac power */ snd_ac97_update_bits(snd_kcontrol_chip(kcontrol), 0x5c, 0x0008, ucontrol->value.enumerated.item[0] << 3); /* toggle aux in surround rear out jack */ return snd_ac97_update_bits(snd_kcontrol_chip(kcontrol), 0x76, 0x0008, ucontrol->value.enumerated.item[0] << 3); } static const struct snd_kcontrol_new snd_ac97_controls_vt1618[] = { AC97_SINGLE("Exchange Center/LFE", 0x5a, 8, 1, 0), AC97_SINGLE("DC Offset", 0x5a, 10, 1, 0), AC97_SINGLE("Soft Mute", 0x5c, 0, 1, 1), AC97_SINGLE("Headphone Amp", 0x5c, 5, 1, 1), AC97_DOUBLE("Back Surr Volume", 0x5e, 8, 0, 31, 1), AC97_SINGLE("Back Surr Switch", 0x5e, 15, 1, 1), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Speaker Jack Mode", .info = snd_ac97_vt1618_UAJ_info, .get = snd_ac97_vt1618_UAJ_get, .put = snd_ac97_vt1618_UAJ_put, .private_value = 0 }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Line Jack Mode", .info = snd_ac97_vt1618_UAJ_info, .get = snd_ac97_vt1618_UAJ_get, .put = snd_ac97_vt1618_UAJ_put, .private_value = 1 }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Mic Jack Mode", .info = snd_ac97_vt1618_UAJ_info, .get = snd_ac97_vt1618_UAJ_get, .put = snd_ac97_vt1618_UAJ_put, .private_value = 2 }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Aux Jack Mode", .info = snd_ac97_vt1618_aux_info, .get = snd_ac97_vt1618_aux_get, .put = snd_ac97_vt1618_aux_put, } }; static int patch_vt1618(struct snd_ac97 *ac97) { return patch_build_controls(ac97, snd_ac97_controls_vt1618, ARRAY_SIZE(snd_ac97_controls_vt1618)); } /* */ static void it2646_update_jacks(struct snd_ac97 *ac97) { /* shared Line-In / Surround Out */ snd_ac97_update_bits(ac97, 0x76, 1 << 9, is_shared_surrout(ac97) ? (1<<9) : 0); /* shared Mic / Center/LFE Out */ snd_ac97_update_bits(ac97, 0x76, 1 << 10, is_shared_clfeout(ac97) ? (1<<10) : 0); } static const struct snd_kcontrol_new snd_ac97_controls_it2646[] = { AC97_SURROUND_JACK_MODE_CTL, AC97_CHANNEL_MODE_CTL, }; static const struct snd_kcontrol_new snd_ac97_spdif_controls_it2646[] = { AC97_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0x76, 11, 1, 0), AC97_SINGLE("Analog to IEC958 Output", 0x76, 12, 1, 0), AC97_SINGLE("IEC958 Input Monitor", 0x76, 13, 1, 0), }; static int patch_it2646_specific(struct snd_ac97 * ac97) { int err; err = patch_build_controls(ac97, snd_ac97_controls_it2646, ARRAY_SIZE(snd_ac97_controls_it2646)); if (err < 0) return err; err = patch_build_controls(ac97, snd_ac97_spdif_controls_it2646, ARRAY_SIZE(snd_ac97_spdif_controls_it2646)); if (err < 0) return err; return 0; } static const struct snd_ac97_build_ops patch_it2646_ops = { .build_specific = patch_it2646_specific, .update_jacks = it2646_update_jacks }; static int patch_it2646(struct snd_ac97 * ac97) { ac97->build_ops = &patch_it2646_ops; /* full DAC volume */ snd_ac97_write_cache(ac97, 0x5E, 0x0808); snd_ac97_write_cache(ac97, 0x7A, 0x0808); return 0; } /* * Si3036 codec */ #define AC97_SI3036_CHIP_ID 0x5a #define AC97_SI3036_LINE_CFG 0x5c static const struct snd_kcontrol_new snd_ac97_controls_si3036[] = { AC97_DOUBLE("Modem Speaker Volume", 0x5c, 14, 12, 3, 1) }; static int patch_si3036_specific(struct snd_ac97 * ac97) { int idx, err; for (idx = 0; idx < ARRAY_SIZE(snd_ac97_controls_si3036); idx++) { err = snd_ctl_add(ac97->bus->card, snd_ctl_new1(&snd_ac97_controls_si3036[idx], ac97)); if (err < 0) return err; } return 0; } static const struct snd_ac97_build_ops patch_si3036_ops = { .build_specific = patch_si3036_specific, }; static int mpatch_si3036(struct snd_ac97 * ac97) { ac97->build_ops = &patch_si3036_ops; snd_ac97_write_cache(ac97, 0x5c, 0xf210 ); snd_ac97_write_cache(ac97, 0x68, 0); return 0; } /* * LM 4550 Codec * * We use a static resolution table since LM4550 codec cannot be * properly autoprobed to determine the resolution via * check_volume_resolution(). */ static const struct snd_ac97_res_table lm4550_restbl[] = { { AC97_MASTER, 0x1f1f }, { AC97_HEADPHONE, 0x1f1f }, { AC97_MASTER_MONO, 0x001f }, { AC97_PC_BEEP, 0x001f }, /* LSB is ignored */ { AC97_PHONE, 0x001f }, { AC97_MIC, 0x001f }, { AC97_LINE, 0x1f1f }, { AC97_CD, 0x1f1f }, { AC97_VIDEO, 0x1f1f }, { AC97_AUX, 0x1f1f }, { AC97_PCM, 0x1f1f }, { AC97_REC_GAIN, 0x0f0f }, { } /* terminator */ }; static int patch_lm4550(struct snd_ac97 *ac97) { ac97->res_table = lm4550_restbl; return 0; }
linux-master
sound/pci/ac97/ac97_patch.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Universal interface for Audio Codec '97 * * For more details look to AC '97 component specification revision 2.2 * by Intel Corporation (http://developer.intel.com) and to datasheets * for specific codecs. */ #include <linux/delay.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/mutex.h> #include <linux/export.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/control.h> #include <sound/ac97_codec.h> #include <sound/asoundef.h> #include "ac97_id.h" #include "ac97_local.h" /* * PCM support */ static const unsigned char rate_reg_tables[2][4][9] = { { /* standard rates */ { /* 3&4 front, 7&8 rear, 6&9 center/lfe */ AC97_PCM_FRONT_DAC_RATE, /* slot 3 */ AC97_PCM_FRONT_DAC_RATE, /* slot 4 */ 0xff, /* slot 5 */ AC97_PCM_LFE_DAC_RATE, /* slot 6 */ AC97_PCM_SURR_DAC_RATE, /* slot 7 */ AC97_PCM_SURR_DAC_RATE, /* slot 8 */ AC97_PCM_LFE_DAC_RATE, /* slot 9 */ 0xff, /* slot 10 */ 0xff, /* slot 11 */ }, { /* 7&8 front, 6&9 rear, 10&11 center/lfe */ 0xff, /* slot 3 */ 0xff, /* slot 4 */ 0xff, /* slot 5 */ AC97_PCM_SURR_DAC_RATE, /* slot 6 */ AC97_PCM_FRONT_DAC_RATE, /* slot 7 */ AC97_PCM_FRONT_DAC_RATE, /* slot 8 */ AC97_PCM_SURR_DAC_RATE, /* slot 9 */ AC97_PCM_LFE_DAC_RATE, /* slot 10 */ AC97_PCM_LFE_DAC_RATE, /* slot 11 */ }, { /* 6&9 front, 10&11 rear, 3&4 center/lfe */ AC97_PCM_LFE_DAC_RATE, /* slot 3 */ AC97_PCM_LFE_DAC_RATE, /* slot 4 */ 0xff, /* slot 5 */ AC97_PCM_FRONT_DAC_RATE, /* slot 6 */ 0xff, /* slot 7 */ 0xff, /* slot 8 */ AC97_PCM_FRONT_DAC_RATE, /* slot 9 */ AC97_PCM_SURR_DAC_RATE, /* slot 10 */ AC97_PCM_SURR_DAC_RATE, /* slot 11 */ }, { /* 10&11 front, 3&4 rear, 7&8 center/lfe */ AC97_PCM_SURR_DAC_RATE, /* slot 3 */ AC97_PCM_SURR_DAC_RATE, /* slot 4 */ 0xff, /* slot 5 */ 0xff, /* slot 6 */ AC97_PCM_LFE_DAC_RATE, /* slot 7 */ AC97_PCM_LFE_DAC_RATE, /* slot 8 */ 0xff, /* slot 9 */ AC97_PCM_FRONT_DAC_RATE, /* slot 10 */ AC97_PCM_FRONT_DAC_RATE, /* slot 11 */ }, }, { /* double rates */ { /* 3&4 front, 7&8 front (t+1) */ AC97_PCM_FRONT_DAC_RATE, /* slot 3 */ AC97_PCM_FRONT_DAC_RATE, /* slot 4 */ 0xff, /* slot 5 */ 0xff, /* slot 6 */ AC97_PCM_FRONT_DAC_RATE, /* slot 7 */ AC97_PCM_FRONT_DAC_RATE, /* slot 8 */ 0xff, /* slot 9 */ 0xff, /* slot 10 */ 0xff, /* slot 11 */ }, { /* not specified in the specification */ 0xff, /* slot 3 */ 0xff, /* slot 4 */ 0xff, /* slot 5 */ 0xff, /* slot 6 */ 0xff, /* slot 7 */ 0xff, /* slot 8 */ 0xff, /* slot 9 */ 0xff, /* slot 10 */ 0xff, /* slot 11 */ }, { 0xff, /* slot 3 */ 0xff, /* slot 4 */ 0xff, /* slot 5 */ 0xff, /* slot 6 */ 0xff, /* slot 7 */ 0xff, /* slot 8 */ 0xff, /* slot 9 */ 0xff, /* slot 10 */ 0xff, /* slot 11 */ }, { 0xff, /* slot 3 */ 0xff, /* slot 4 */ 0xff, /* slot 5 */ 0xff, /* slot 6 */ 0xff, /* slot 7 */ 0xff, /* slot 8 */ 0xff, /* slot 9 */ 0xff, /* slot 10 */ 0xff, /* slot 11 */ } }}; /* FIXME: more various mappings for ADC? */ static const unsigned char rate_cregs[9] = { AC97_PCM_LR_ADC_RATE, /* 3 */ AC97_PCM_LR_ADC_RATE, /* 4 */ 0xff, /* 5 */ AC97_PCM_MIC_ADC_RATE, /* 6 */ 0xff, /* 7 */ 0xff, /* 8 */ 0xff, /* 9 */ 0xff, /* 10 */ 0xff, /* 11 */ }; static unsigned char get_slot_reg(struct ac97_pcm *pcm, unsigned short cidx, unsigned short slot, int dbl) { if (slot < 3) return 0xff; if (slot > 11) return 0xff; if (pcm->spdif) return AC97_SPDIF; /* pseudo register */ if (pcm->stream == SNDRV_PCM_STREAM_PLAYBACK) return rate_reg_tables[dbl][pcm->r[dbl].rate_table[cidx]][slot - 3]; else return rate_cregs[slot - 3]; } static int set_spdif_rate(struct snd_ac97 *ac97, unsigned short rate) { unsigned short old, bits, reg, mask; unsigned int sbits; if (! (ac97->ext_id & AC97_EI_SPDIF)) return -ENODEV; /* TODO: double rate support */ if (ac97->flags & AC97_CS_SPDIF) { switch (rate) { case 48000: bits = 0; break; case 44100: bits = 1 << AC97_SC_SPSR_SHIFT; break; default: /* invalid - disable output */ snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); return -EINVAL; } reg = AC97_CSR_SPDIF; mask = 1 << AC97_SC_SPSR_SHIFT; } else { if (ac97->id == AC97_ID_CM9739 && rate != 48000) { snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); return -EINVAL; } switch (rate) { case 44100: bits = AC97_SC_SPSR_44K; break; case 48000: bits = AC97_SC_SPSR_48K; break; case 32000: bits = AC97_SC_SPSR_32K; break; default: /* invalid - disable output */ snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); return -EINVAL; } reg = AC97_SPDIF; mask = AC97_SC_SPSR_MASK; } mutex_lock(&ac97->reg_mutex); old = snd_ac97_read(ac97, reg) & mask; if (old != bits) { snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, 0); snd_ac97_update_bits_nolock(ac97, reg, mask, bits); /* update the internal spdif bits */ sbits = ac97->spdif_status; if (sbits & IEC958_AES0_PROFESSIONAL) { sbits &= ~IEC958_AES0_PRO_FS; switch (rate) { case 44100: sbits |= IEC958_AES0_PRO_FS_44100; break; case 48000: sbits |= IEC958_AES0_PRO_FS_48000; break; case 32000: sbits |= IEC958_AES0_PRO_FS_32000; break; } } else { sbits &= ~(IEC958_AES3_CON_FS << 24); switch (rate) { case 44100: sbits |= IEC958_AES3_CON_FS_44100<<24; break; case 48000: sbits |= IEC958_AES3_CON_FS_48000<<24; break; case 32000: sbits |= IEC958_AES3_CON_FS_32000<<24; break; } } ac97->spdif_status = sbits; } snd_ac97_update_bits_nolock(ac97, AC97_EXTENDED_STATUS, AC97_EA_SPDIF, AC97_EA_SPDIF); mutex_unlock(&ac97->reg_mutex); return 0; } /** * snd_ac97_set_rate - change the rate of the given input/output. * @ac97: the ac97 instance * @reg: the register to change * @rate: the sample rate to set * * Changes the rate of the given input/output on the codec. * If the codec doesn't support VAR, the rate must be 48000 (except * for SPDIF). * * The valid registers are AC97_PCM_MIC_ADC_RATE, * AC97_PCM_FRONT_DAC_RATE, AC97_PCM_LR_ADC_RATE. * AC97_PCM_SURR_DAC_RATE and AC97_PCM_LFE_DAC_RATE are accepted * if the codec supports them. * AC97_SPDIF is accepted as a pseudo register to modify the SPDIF * status bits. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate) { int dbl; unsigned int tmp; dbl = rate > 48000; if (dbl) { if (!(ac97->flags & AC97_DOUBLE_RATE)) return -EINVAL; if (reg != AC97_PCM_FRONT_DAC_RATE) return -EINVAL; } snd_ac97_update_power(ac97, reg, 1); switch (reg) { case AC97_PCM_MIC_ADC_RATE: if ((ac97->regs[AC97_EXTENDED_STATUS] & AC97_EA_VRM) == 0) /* MIC VRA */ if (rate != 48000) return -EINVAL; break; case AC97_PCM_FRONT_DAC_RATE: case AC97_PCM_LR_ADC_RATE: if ((ac97->regs[AC97_EXTENDED_STATUS] & AC97_EA_VRA) == 0) /* VRA */ if (rate != 48000 && rate != 96000) return -EINVAL; break; case AC97_PCM_SURR_DAC_RATE: if (! (ac97->scaps & AC97_SCAP_SURROUND_DAC)) return -EINVAL; break; case AC97_PCM_LFE_DAC_RATE: if (! (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC)) return -EINVAL; break; case AC97_SPDIF: /* special case */ return set_spdif_rate(ac97, rate); default: return -EINVAL; } if (dbl) rate /= 2; tmp = (rate * ac97->bus->clock) / 48000; if (tmp > 65535) return -EINVAL; if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, AC97_EA_DRA, dbl ? AC97_EA_DRA : 0); snd_ac97_update(ac97, reg, tmp & 0xffff); snd_ac97_read(ac97, reg); if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) { /* Intel controllers require double rate data to be put in * slots 7+8 */ snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, AC97_GP_DRSS_MASK, dbl ? AC97_GP_DRSS_78 : 0); snd_ac97_read(ac97, AC97_GENERAL_PURPOSE); } return 0; } EXPORT_SYMBOL(snd_ac97_set_rate); static unsigned short get_pslots(struct snd_ac97 *ac97, unsigned char *rate_table, unsigned short *spdif_slots) { if (!ac97_is_audio(ac97)) return 0; if (ac97_is_rev22(ac97) || ac97_can_amap(ac97)) { unsigned short slots = 0; if (ac97_is_rev22(ac97)) { /* Note: it's simply emulation of AMAP behaviour */ u16 es; es = ac97->regs[AC97_EXTENDED_ID] &= ~AC97_EI_DACS_SLOT_MASK; switch (ac97->addr) { case 1: case 2: es |= (1<<AC97_EI_DACS_SLOT_SHIFT); break; case 3: es |= (2<<AC97_EI_DACS_SLOT_SHIFT); break; } snd_ac97_write_cache(ac97, AC97_EXTENDED_ID, es); } switch (ac97->addr) { case 0: slots |= (1<<AC97_SLOT_PCM_LEFT)|(1<<AC97_SLOT_PCM_RIGHT); if (ac97->scaps & AC97_SCAP_SURROUND_DAC) slots |= (1<<AC97_SLOT_PCM_SLEFT)|(1<<AC97_SLOT_PCM_SRIGHT); if (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC) slots |= (1<<AC97_SLOT_PCM_CENTER)|(1<<AC97_SLOT_LFE); if (ac97->ext_id & AC97_EI_SPDIF) { if (!(ac97->scaps & AC97_SCAP_SURROUND_DAC)) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT)|(1<<AC97_SLOT_SPDIF_RIGHT); else if (!(ac97->scaps & AC97_SCAP_CENTER_LFE_DAC)) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT1)|(1<<AC97_SLOT_SPDIF_RIGHT1); else *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT2)|(1<<AC97_SLOT_SPDIF_RIGHT2); } *rate_table = 0; break; case 1: case 2: slots |= (1<<AC97_SLOT_PCM_SLEFT)|(1<<AC97_SLOT_PCM_SRIGHT); if (ac97->scaps & AC97_SCAP_SURROUND_DAC) slots |= (1<<AC97_SLOT_PCM_CENTER)|(1<<AC97_SLOT_LFE); if (ac97->ext_id & AC97_EI_SPDIF) { if (!(ac97->scaps & AC97_SCAP_SURROUND_DAC)) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT1)|(1<<AC97_SLOT_SPDIF_RIGHT1); else *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT2)|(1<<AC97_SLOT_SPDIF_RIGHT2); } *rate_table = 1; break; case 3: slots |= (1<<AC97_SLOT_PCM_CENTER)|(1<<AC97_SLOT_LFE); if (ac97->ext_id & AC97_EI_SPDIF) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT2)|(1<<AC97_SLOT_SPDIF_RIGHT2); *rate_table = 2; break; } return slots; } else { unsigned short slots; slots = (1<<AC97_SLOT_PCM_LEFT)|(1<<AC97_SLOT_PCM_RIGHT); if (ac97->scaps & AC97_SCAP_SURROUND_DAC) slots |= (1<<AC97_SLOT_PCM_SLEFT)|(1<<AC97_SLOT_PCM_SRIGHT); if (ac97->scaps & AC97_SCAP_CENTER_LFE_DAC) slots |= (1<<AC97_SLOT_PCM_CENTER)|(1<<AC97_SLOT_LFE); if (ac97->ext_id & AC97_EI_SPDIF) { if (!(ac97->scaps & AC97_SCAP_SURROUND_DAC)) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT)|(1<<AC97_SLOT_SPDIF_RIGHT); else if (!(ac97->scaps & AC97_SCAP_CENTER_LFE_DAC)) *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT1)|(1<<AC97_SLOT_SPDIF_RIGHT1); else *spdif_slots = (1<<AC97_SLOT_SPDIF_LEFT2)|(1<<AC97_SLOT_SPDIF_RIGHT2); } *rate_table = 0; return slots; } } static unsigned short get_cslots(struct snd_ac97 *ac97) { unsigned short slots; if (!ac97_is_audio(ac97)) return 0; slots = (1<<AC97_SLOT_PCM_LEFT)|(1<<AC97_SLOT_PCM_RIGHT); slots |= (1<<AC97_SLOT_MIC); return slots; } static unsigned int get_rates(struct ac97_pcm *pcm, unsigned int cidx, unsigned short slots, int dbl) { int i, idx; unsigned int rates = ~0; unsigned char reg; for (i = 3; i < 12; i++) { if (!(slots & (1 << i))) continue; reg = get_slot_reg(pcm, cidx, i, dbl); switch (reg) { case AC97_PCM_FRONT_DAC_RATE: idx = AC97_RATES_FRONT_DAC; break; case AC97_PCM_SURR_DAC_RATE: idx = AC97_RATES_SURR_DAC; break; case AC97_PCM_LFE_DAC_RATE: idx = AC97_RATES_LFE_DAC; break; case AC97_PCM_LR_ADC_RATE: idx = AC97_RATES_ADC; break; case AC97_PCM_MIC_ADC_RATE: idx = AC97_RATES_MIC_ADC; break; default: idx = AC97_RATES_SPDIF; break; } rates &= pcm->r[dbl].codec[cidx]->rates[idx]; } if (!dbl) rates &= ~(SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000); return rates; } /** * snd_ac97_pcm_assign - assign AC97 slots to given PCM streams * @bus: the ac97 bus instance * @pcms_count: count of PCMs to be assigned * @pcms: PCMs to be assigned * * It assigns available AC97 slots for given PCMs. If none or only * some slots are available, pcm->xxx.slots and pcm->xxx.rslots[] members * are reduced and might be zero. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_pcm_assign(struct snd_ac97_bus *bus, unsigned short pcms_count, const struct ac97_pcm *pcms) { int i, j, k; const struct ac97_pcm *pcm; struct ac97_pcm *rpcms, *rpcm; unsigned short avail_slots[2][4]; unsigned char rate_table[2][4]; unsigned short tmp, slots; unsigned short spdif_slots[4]; unsigned int rates; struct snd_ac97 *codec; rpcms = kcalloc(pcms_count, sizeof(struct ac97_pcm), GFP_KERNEL); if (rpcms == NULL) return -ENOMEM; memset(avail_slots, 0, sizeof(avail_slots)); memset(rate_table, 0, sizeof(rate_table)); memset(spdif_slots, 0, sizeof(spdif_slots)); for (i = 0; i < 4; i++) { codec = bus->codec[i]; if (!codec) continue; avail_slots[0][i] = get_pslots(codec, &rate_table[0][i], &spdif_slots[i]); avail_slots[1][i] = get_cslots(codec); if (!(codec->scaps & AC97_SCAP_INDEP_SDIN)) { for (j = 0; j < i; j++) { if (bus->codec[j]) avail_slots[1][i] &= ~avail_slots[1][j]; } } } /* first step - exclusive devices */ for (i = 0; i < pcms_count; i++) { pcm = &pcms[i]; rpcm = &rpcms[i]; /* low-level driver thinks that it's more clever */ if (pcm->copy_flag) { *rpcm = *pcm; continue; } rpcm->stream = pcm->stream; rpcm->exclusive = pcm->exclusive; rpcm->spdif = pcm->spdif; rpcm->private_value = pcm->private_value; rpcm->bus = bus; rpcm->rates = ~0; slots = pcm->r[0].slots; for (j = 0; j < 4 && slots; j++) { if (!bus->codec[j]) continue; rates = ~0; if (pcm->spdif && pcm->stream == 0) tmp = spdif_slots[j]; else tmp = avail_slots[pcm->stream][j]; if (pcm->exclusive) { /* exclusive access */ tmp &= slots; for (k = 0; k < i; k++) { if (rpcm->stream == rpcms[k].stream) tmp &= ~rpcms[k].r[0].rslots[j]; } } else { /* non-exclusive access */ tmp &= pcm->r[0].slots; } if (tmp) { rpcm->r[0].rslots[j] = tmp; rpcm->r[0].codec[j] = bus->codec[j]; rpcm->r[0].rate_table[j] = rate_table[pcm->stream][j]; if (bus->no_vra) rates = SNDRV_PCM_RATE_48000; else rates = get_rates(rpcm, j, tmp, 0); if (pcm->exclusive) avail_slots[pcm->stream][j] &= ~tmp; } slots &= ~tmp; rpcm->r[0].slots |= tmp; rpcm->rates &= rates; } /* for double rate, we check the first codec only */ if (pcm->stream == SNDRV_PCM_STREAM_PLAYBACK && bus->codec[0] && (bus->codec[0]->flags & AC97_DOUBLE_RATE) && rate_table[pcm->stream][0] == 0) { tmp = (1<<AC97_SLOT_PCM_LEFT) | (1<<AC97_SLOT_PCM_RIGHT) | (1<<AC97_SLOT_PCM_LEFT_0) | (1<<AC97_SLOT_PCM_RIGHT_0); if ((tmp & pcm->r[1].slots) == tmp) { rpcm->r[1].slots = tmp; rpcm->r[1].rslots[0] = tmp; rpcm->r[1].rate_table[0] = 0; rpcm->r[1].codec[0] = bus->codec[0]; if (pcm->exclusive) avail_slots[pcm->stream][0] &= ~tmp; if (bus->no_vra) rates = SNDRV_PCM_RATE_96000; else rates = get_rates(rpcm, 0, tmp, 1); rpcm->rates |= rates; } } if (rpcm->rates == ~0) rpcm->rates = 0; /* not used */ } bus->pcms_count = pcms_count; bus->pcms = rpcms; return 0; } EXPORT_SYMBOL(snd_ac97_pcm_assign); /** * snd_ac97_pcm_open - opens the given AC97 pcm * @pcm: the ac97 pcm instance * @rate: rate in Hz, if codec does not support VRA, this value must be 48000Hz * @cfg: output stream characteristics * @slots: a subset of allocated slots (snd_ac97_pcm_assign) for this pcm * * It locks the specified slots and sets the given rate to AC97 registers. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate, enum ac97_pcm_cfg cfg, unsigned short slots) { struct snd_ac97_bus *bus; int i, cidx, r, ok_flag; unsigned int reg_ok[4] = {0,0,0,0}; unsigned char reg; int err = 0; r = rate > 48000; bus = pcm->bus; if (cfg == AC97_PCM_CFG_SPDIF) { for (cidx = 0; cidx < 4; cidx++) if (bus->codec[cidx] && (bus->codec[cidx]->ext_id & AC97_EI_SPDIF)) { err = set_spdif_rate(bus->codec[cidx], rate); if (err < 0) return err; } } spin_lock_irq(&pcm->bus->bus_lock); for (i = 3; i < 12; i++) { if (!(slots & (1 << i))) continue; ok_flag = 0; for (cidx = 0; cidx < 4; cidx++) { if (bus->used_slots[pcm->stream][cidx] & (1 << i)) { spin_unlock_irq(&pcm->bus->bus_lock); err = -EBUSY; goto error; } if (pcm->r[r].rslots[cidx] & (1 << i)) { bus->used_slots[pcm->stream][cidx] |= (1 << i); ok_flag++; } } if (!ok_flag) { spin_unlock_irq(&pcm->bus->bus_lock); dev_err(bus->card->dev, "cannot find configuration for AC97 slot %i\n", i); err = -EAGAIN; goto error; } } pcm->cur_dbl = r; spin_unlock_irq(&pcm->bus->bus_lock); for (i = 3; i < 12; i++) { if (!(slots & (1 << i))) continue; for (cidx = 0; cidx < 4; cidx++) { if (pcm->r[r].rslots[cidx] & (1 << i)) { reg = get_slot_reg(pcm, cidx, i, r); if (reg == 0xff) { dev_err(bus->card->dev, "invalid AC97 slot %i?\n", i); continue; } if (reg_ok[cidx] & (1 << (reg - AC97_PCM_FRONT_DAC_RATE))) continue; dev_dbg(bus->card->dev, "setting ac97 reg 0x%x to rate %d\n", reg, rate); err = snd_ac97_set_rate(pcm->r[r].codec[cidx], reg, rate); if (err < 0) dev_err(bus->card->dev, "error in snd_ac97_set_rate: cidx=%d, reg=0x%x, rate=%d, err=%d\n", cidx, reg, rate, err); else reg_ok[cidx] |= (1 << (reg - AC97_PCM_FRONT_DAC_RATE)); } } } pcm->aslots = slots; return 0; error: pcm->aslots = slots; snd_ac97_pcm_close(pcm); return err; } EXPORT_SYMBOL(snd_ac97_pcm_open); /** * snd_ac97_pcm_close - closes the given AC97 pcm * @pcm: the ac97 pcm instance * * It frees the locked AC97 slots. * * Return: Zero. */ int snd_ac97_pcm_close(struct ac97_pcm *pcm) { struct snd_ac97_bus *bus; unsigned short slots = pcm->aslots; int i, cidx; #ifdef CONFIG_SND_AC97_POWER_SAVE int r = pcm->cur_dbl; for (i = 3; i < 12; i++) { if (!(slots & (1 << i))) continue; for (cidx = 0; cidx < 4; cidx++) { if (pcm->r[r].rslots[cidx] & (1 << i)) { int reg = get_slot_reg(pcm, cidx, i, r); snd_ac97_update_power(pcm->r[r].codec[cidx], reg, 0); } } } #endif bus = pcm->bus; spin_lock_irq(&pcm->bus->bus_lock); for (i = 3; i < 12; i++) { if (!(slots & (1 << i))) continue; for (cidx = 0; cidx < 4; cidx++) bus->used_slots[pcm->stream][cidx] &= ~(1 << i); } pcm->aslots = 0; pcm->cur_dbl = 0; spin_unlock_irq(&pcm->bus->bus_lock); return 0; } EXPORT_SYMBOL(snd_ac97_pcm_close); static int double_rate_hw_constraint_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); if (channels->min > 2) { static const struct snd_interval single_rates = { .min = 1, .max = 48000, }; struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); return snd_interval_refine(rate, &single_rates); } return 0; } static int double_rate_hw_constraint_channels(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); if (rate->min > 48000) { static const struct snd_interval double_rate_channels = { .min = 2, .max = 2, }; struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); return snd_interval_refine(channels, &double_rate_channels); } return 0; } /** * snd_ac97_pcm_double_rate_rules - set double rate constraints * @runtime: the runtime of the ac97 front playback pcm * * Installs the hardware constraint rules to prevent using double rates and * more than two channels at the same time. * * Return: Zero if successful, or a negative error code on failure. */ int snd_ac97_pcm_double_rate_rules(struct snd_pcm_runtime *runtime) { int err; err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, double_rate_hw_constraint_rate, NULL, SNDRV_PCM_HW_PARAM_CHANNELS, -1); if (err < 0) return err; err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, double_rate_hw_constraint_channels, NULL, SNDRV_PCM_HW_PARAM_RATE, -1); return err; } EXPORT_SYMBOL(snd_ac97_pcm_double_rate_rules);
linux-master
sound/pci/ac97/ac97_pcm.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Universal interface for Audio Codec '97 * * For more details look to AC '97 component specification revision 2.2 * by Intel Corporation (http://developer.intel.com). */ #include <linux/mutex.h> #include <sound/core.h> #include <sound/ac97_codec.h> #include <sound/asoundef.h> #include "ac97_local.h" #include "ac97_id.h" /* * proc interface */ static void snd_ac97_proc_read_functions(struct snd_ac97 *ac97, struct snd_info_buffer *buffer) { int header = 0, function; unsigned short info, sense_info; static const char *function_names[12] = { "Master Out", "AUX Out", "Center/LFE Out", "SPDIF Out", "Phone In", "Mic 1", "Mic 2", "Line In", "CD In", "Video In", "Aux In", "Mono Out" }; static const char *locations[8] = { "Rear I/O Panel", "Front Panel", "Motherboard", "Dock/External", "reserved", "reserved", "reserved", "NC/unused" }; for (function = 0; function < 12; ++function) { snd_ac97_write(ac97, AC97_FUNC_SELECT, function << 1); info = snd_ac97_read(ac97, AC97_FUNC_INFO); if (!(info & 0x0001)) continue; if (!header) { snd_iprintf(buffer, "\n Gain Inverted Buffer delay Location\n"); header = 1; } sense_info = snd_ac97_read(ac97, AC97_SENSE_INFO); snd_iprintf(buffer, "%-17s: %3d.%d dBV %c %2d/fs %s\n", function_names[function], (info & 0x8000 ? -1 : 1) * ((info & 0x7000) >> 12) * 3 / 2, ((info & 0x0800) >> 11) * 5, info & 0x0400 ? 'X' : '-', (info & 0x03e0) >> 5, locations[sense_info >> 13]); } } static const char *snd_ac97_stereo_enhancements[] = { /* 0 */ "No 3D Stereo Enhancement", /* 1 */ "Analog Devices Phat Stereo", /* 2 */ "Creative Stereo Enhancement", /* 3 */ "National Semi 3D Stereo Enhancement", /* 4 */ "YAMAHA Ymersion", /* 5 */ "BBE 3D Stereo Enhancement", /* 6 */ "Crystal Semi 3D Stereo Enhancement", /* 7 */ "Qsound QXpander", /* 8 */ "Spatializer 3D Stereo Enhancement", /* 9 */ "SRS 3D Stereo Enhancement", /* 10 */ "Platform Tech 3D Stereo Enhancement", /* 11 */ "AKM 3D Audio", /* 12 */ "Aureal Stereo Enhancement", /* 13 */ "Aztech 3D Enhancement", /* 14 */ "Binaura 3D Audio Enhancement", /* 15 */ "ESS Technology Stereo Enhancement", /* 16 */ "Harman International VMAx", /* 17 */ "Nvidea/IC Ensemble/KS Waves 3D Stereo Enhancement", /* 18 */ "Philips Incredible Sound", /* 19 */ "Texas Instruments 3D Stereo Enhancement", /* 20 */ "VLSI Technology 3D Stereo Enhancement", /* 21 */ "TriTech 3D Stereo Enhancement", /* 22 */ "Realtek 3D Stereo Enhancement", /* 23 */ "Samsung 3D Stereo Enhancement", /* 24 */ "Wolfson Microelectronics 3D Enhancement", /* 25 */ "Delta Integration 3D Enhancement", /* 26 */ "SigmaTel 3D Enhancement", /* 27 */ "IC Ensemble/KS Waves", /* 28 */ "Rockwell 3D Stereo Enhancement", /* 29 */ "Reserved 29", /* 30 */ "Reserved 30", /* 31 */ "Reserved 31" }; static void snd_ac97_proc_read_main(struct snd_ac97 *ac97, struct snd_info_buffer *buffer, int subidx) { char name[64]; unsigned short val, tmp, ext, mext; static const char *spdif_slots[4] = { " SPDIF=3/4", " SPDIF=7/8", " SPDIF=6/9", " SPDIF=10/11" }; static const char *spdif_rates[4] = { " Rate=44.1kHz", " Rate=res", " Rate=48kHz", " Rate=32kHz" }; static const char *spdif_rates_cs4205[4] = { " Rate=48kHz", " Rate=44.1kHz", " Rate=res", " Rate=res" }; static const char *double_rate_slots[4] = { "10/11", "7/8", "reserved", "reserved" }; snd_ac97_get_name(NULL, ac97->id, name, 0); snd_iprintf(buffer, "%d-%d/%d: %s\n\n", ac97->addr, ac97->num, subidx, name); if ((ac97->scaps & AC97_SCAP_AUDIO) == 0) goto __modem; snd_iprintf(buffer, "PCI Subsys Vendor: 0x%04x\n", ac97->subsystem_vendor); snd_iprintf(buffer, "PCI Subsys Device: 0x%04x\n\n", ac97->subsystem_device); snd_iprintf(buffer, "Flags: %x\n", ac97->flags); if ((ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_23) { val = snd_ac97_read(ac97, AC97_INT_PAGING); snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_1); tmp = snd_ac97_read(ac97, AC97_CODEC_CLASS_REV); snd_iprintf(buffer, "Revision : 0x%02x\n", tmp & 0xff); snd_iprintf(buffer, "Compat. Class : 0x%02x\n", (tmp >> 8) & 0x1f); snd_iprintf(buffer, "Subsys. Vendor ID: 0x%04x\n", snd_ac97_read(ac97, AC97_PCI_SVID)); snd_iprintf(buffer, "Subsys. ID : 0x%04x\n\n", snd_ac97_read(ac97, AC97_PCI_SID)); snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, val & AC97_PAGE_MASK); } // val = snd_ac97_read(ac97, AC97_RESET); val = ac97->caps; snd_iprintf(buffer, "Capabilities :%s%s%s%s%s%s\n", val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", val & AC97_BC_RESERVED1 ? " -reserved1-" : "", val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", val & AC97_BC_HEADPHONE ? " -headphone out-" : "", val & AC97_BC_LOUDNESS ? " -loudness-" : ""); tmp = ac97->caps & AC97_BC_DAC_MASK; snd_iprintf(buffer, "DAC resolution : %s%s%s%s\n", tmp == AC97_BC_16BIT_DAC ? "16-bit" : "", tmp == AC97_BC_18BIT_DAC ? "18-bit" : "", tmp == AC97_BC_20BIT_DAC ? "20-bit" : "", tmp == AC97_BC_DAC_MASK ? "???" : ""); tmp = ac97->caps & AC97_BC_ADC_MASK; snd_iprintf(buffer, "ADC resolution : %s%s%s%s\n", tmp == AC97_BC_16BIT_ADC ? "16-bit" : "", tmp == AC97_BC_18BIT_ADC ? "18-bit" : "", tmp == AC97_BC_20BIT_ADC ? "20-bit" : "", tmp == AC97_BC_ADC_MASK ? "???" : ""); snd_iprintf(buffer, "3D enhancement : %s\n", snd_ac97_stereo_enhancements[(val >> 10) & 0x1f]); snd_iprintf(buffer, "\nCurrent setup\n"); val = snd_ac97_read(ac97, AC97_MIC); snd_iprintf(buffer, "Mic gain : %s [%s]\n", val & 0x0040 ? "+20dB" : "+0dB", ac97->regs[AC97_MIC] & 0x0040 ? "+20dB" : "+0dB"); val = snd_ac97_read(ac97, AC97_GENERAL_PURPOSE); snd_iprintf(buffer, "POP path : %s 3D\n" "Sim. stereo : %s\n" "3D enhancement : %s\n" "Loudness : %s\n" "Mono output : %s\n" "Mic select : %s\n" "ADC/DAC loopback : %s\n", val & 0x8000 ? "post" : "pre", val & 0x4000 ? "on" : "off", val & 0x2000 ? "on" : "off", val & 0x1000 ? "on" : "off", val & 0x0200 ? "Mic" : "MIX", val & 0x0100 ? "Mic2" : "Mic1", val & 0x0080 ? "on" : "off"); if (ac97->ext_id & AC97_EI_DRA) snd_iprintf(buffer, "Double rate slots: %s\n", double_rate_slots[(val >> 10) & 3]); ext = snd_ac97_read(ac97, AC97_EXTENDED_ID); if (ext == 0) goto __modem; snd_iprintf(buffer, "Extended ID : codec=%i rev=%i%s%s%s%s DSA=%i%s%s%s%s\n", (ext & AC97_EI_ADDR_MASK) >> AC97_EI_ADDR_SHIFT, (ext & AC97_EI_REV_MASK) >> AC97_EI_REV_SHIFT, ext & AC97_EI_AMAP ? " AMAP" : "", ext & AC97_EI_LDAC ? " LDAC" : "", ext & AC97_EI_SDAC ? " SDAC" : "", ext & AC97_EI_CDAC ? " CDAC" : "", (ext & AC97_EI_DACS_SLOT_MASK) >> AC97_EI_DACS_SLOT_SHIFT, ext & AC97_EI_VRM ? " VRM" : "", ext & AC97_EI_SPDIF ? " SPDIF" : "", ext & AC97_EI_DRA ? " DRA" : "", ext & AC97_EI_VRA ? " VRA" : ""); val = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); snd_iprintf(buffer, "Extended status :%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", val & AC97_EA_PRL ? " PRL" : "", val & AC97_EA_PRK ? " PRK" : "", val & AC97_EA_PRJ ? " PRJ" : "", val & AC97_EA_PRI ? " PRI" : "", val & AC97_EA_SPCV ? " SPCV" : "", val & AC97_EA_MDAC ? " MADC" : "", val & AC97_EA_LDAC ? " LDAC" : "", val & AC97_EA_SDAC ? " SDAC" : "", val & AC97_EA_CDAC ? " CDAC" : "", ext & AC97_EI_SPDIF ? spdif_slots[(val & AC97_EA_SPSA_SLOT_MASK) >> AC97_EA_SPSA_SLOT_SHIFT] : "", val & AC97_EA_VRM ? " VRM" : "", val & AC97_EA_SPDIF ? " SPDIF" : "", val & AC97_EA_DRA ? " DRA" : "", val & AC97_EA_VRA ? " VRA" : ""); if (ext & AC97_EI_VRA) { /* VRA */ val = snd_ac97_read(ac97, AC97_PCM_FRONT_DAC_RATE); snd_iprintf(buffer, "PCM front DAC : %iHz\n", val); if (ext & AC97_EI_SDAC) { val = snd_ac97_read(ac97, AC97_PCM_SURR_DAC_RATE); snd_iprintf(buffer, "PCM Surr DAC : %iHz\n", val); } if (ext & AC97_EI_LDAC) { val = snd_ac97_read(ac97, AC97_PCM_LFE_DAC_RATE); snd_iprintf(buffer, "PCM LFE DAC : %iHz\n", val); } val = snd_ac97_read(ac97, AC97_PCM_LR_ADC_RATE); snd_iprintf(buffer, "PCM ADC : %iHz\n", val); } if (ext & AC97_EI_VRM) { val = snd_ac97_read(ac97, AC97_PCM_MIC_ADC_RATE); snd_iprintf(buffer, "PCM MIC ADC : %iHz\n", val); } if ((ext & AC97_EI_SPDIF) || (ac97->flags & AC97_CS_SPDIF) || (ac97->id == AC97_ID_YMF743)) { if (ac97->flags & AC97_CS_SPDIF) val = snd_ac97_read(ac97, AC97_CSR_SPDIF); else if (ac97->id == AC97_ID_YMF743) { val = snd_ac97_read(ac97, AC97_YMF7X3_DIT_CTRL); val = 0x2000 | (val & 0xff00) >> 4 | (val & 0x38) >> 2; } else val = snd_ac97_read(ac97, AC97_SPDIF); snd_iprintf(buffer, "SPDIF Control :%s%s%s%s Category=0x%x Generation=%i%s%s%s\n", val & AC97_SC_PRO ? " PRO" : " Consumer", val & AC97_SC_NAUDIO ? " Non-audio" : " PCM", val & AC97_SC_COPY ? "" : " Copyright", val & AC97_SC_PRE ? " Preemph50/15" : "", (val & AC97_SC_CC_MASK) >> AC97_SC_CC_SHIFT, (val & AC97_SC_L) >> 11, (ac97->flags & AC97_CS_SPDIF) ? spdif_rates_cs4205[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT] : spdif_rates[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT], (ac97->flags & AC97_CS_SPDIF) ? (val & AC97_SC_DRS ? " Validity" : "") : (val & AC97_SC_DRS ? " DRS" : ""), (ac97->flags & AC97_CS_SPDIF) ? (val & AC97_SC_V ? " Enabled" : "") : (val & AC97_SC_V ? " Validity" : "")); /* ALC650 specific*/ if ((ac97->id & 0xfffffff0) == 0x414c4720 && (snd_ac97_read(ac97, AC97_ALC650_CLOCK) & 0x01)) { val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); if (val & AC97_ALC650_CLOCK_LOCK) { val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS1); snd_iprintf(buffer, "SPDIF In Status :%s%s%s%s Category=0x%x Generation=%i", val & AC97_ALC650_PRO ? " PRO" : " Consumer", val & AC97_ALC650_NAUDIO ? " Non-audio" : " PCM", val & AC97_ALC650_COPY ? "" : " Copyright", val & AC97_ALC650_PRE ? " Preemph50/15" : "", (val & AC97_ALC650_CC_MASK) >> AC97_ALC650_CC_SHIFT, (val & AC97_ALC650_L) >> 15); val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); snd_iprintf(buffer, "%s Accuracy=%i%s%s\n", spdif_rates[(val & AC97_ALC650_SPSR_MASK) >> AC97_ALC650_SPSR_SHIFT], (val & AC97_ALC650_CLOCK_ACCURACY) >> AC97_ALC650_CLOCK_SHIFT, (val & AC97_ALC650_CLOCK_LOCK ? " Locked" : " Unlocked"), (val & AC97_ALC650_V ? " Validity?" : "")); } else { snd_iprintf(buffer, "SPDIF In Status : Not Locked\n"); } } } if ((ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_23) { val = snd_ac97_read(ac97, AC97_INT_PAGING); snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_1); snd_ac97_proc_read_functions(ac97, buffer); snd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, val & AC97_PAGE_MASK); } __modem: mext = snd_ac97_read(ac97, AC97_EXTENDED_MID); if (mext == 0) return; snd_iprintf(buffer, "Extended modem ID: codec=%i%s%s%s%s%s\n", (mext & AC97_MEI_ADDR_MASK) >> AC97_MEI_ADDR_SHIFT, mext & AC97_MEI_CID2 ? " CID2" : "", mext & AC97_MEI_CID1 ? " CID1" : "", mext & AC97_MEI_HANDSET ? " HSET" : "", mext & AC97_MEI_LINE2 ? " LIN2" : "", mext & AC97_MEI_LINE1 ? " LIN1" : ""); val = snd_ac97_read(ac97, AC97_EXTENDED_MSTATUS); snd_iprintf(buffer, "Modem status :%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", val & AC97_MEA_GPIO ? " GPIO" : "", val & AC97_MEA_MREF ? " MREF" : "", val & AC97_MEA_ADC1 ? " ADC1" : "", val & AC97_MEA_DAC1 ? " DAC1" : "", val & AC97_MEA_ADC2 ? " ADC2" : "", val & AC97_MEA_DAC2 ? " DAC2" : "", val & AC97_MEA_HADC ? " HADC" : "", val & AC97_MEA_HDAC ? " HDAC" : "", val & AC97_MEA_PRA ? " PRA(GPIO)" : "", val & AC97_MEA_PRB ? " PRB(res)" : "", val & AC97_MEA_PRC ? " PRC(ADC1)" : "", val & AC97_MEA_PRD ? " PRD(DAC1)" : "", val & AC97_MEA_PRE ? " PRE(ADC2)" : "", val & AC97_MEA_PRF ? " PRF(DAC2)" : "", val & AC97_MEA_PRG ? " PRG(HADC)" : "", val & AC97_MEA_PRH ? " PRH(HDAC)" : ""); if (mext & AC97_MEI_LINE1) { val = snd_ac97_read(ac97, AC97_LINE1_RATE); snd_iprintf(buffer, "Line1 rate : %iHz\n", val); } if (mext & AC97_MEI_LINE2) { val = snd_ac97_read(ac97, AC97_LINE2_RATE); snd_iprintf(buffer, "Line2 rate : %iHz\n", val); } if (mext & AC97_MEI_HANDSET) { val = snd_ac97_read(ac97, AC97_HANDSET_RATE); snd_iprintf(buffer, "Headset rate : %iHz\n", val); } } static void snd_ac97_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_ac97 *ac97 = entry->private_data; mutex_lock(&ac97->page_mutex); if ((ac97->id & 0xffffff40) == AC97_ID_AD1881) { // Analog Devices AD1881/85/86 int idx; for (idx = 0; idx < 3; idx++) if (ac97->spec.ad18xx.id[idx]) { /* select single codec */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, ac97->spec.ad18xx.unchained[idx] | ac97->spec.ad18xx.chained[idx]); snd_ac97_proc_read_main(ac97, buffer, idx); snd_iprintf(buffer, "\n\n"); } /* select all codecs */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, 0x7000); snd_iprintf(buffer, "\nAD18XX configuration\n"); snd_iprintf(buffer, "Unchained : 0x%04x,0x%04x,0x%04x\n", ac97->spec.ad18xx.unchained[0], ac97->spec.ad18xx.unchained[1], ac97->spec.ad18xx.unchained[2]); snd_iprintf(buffer, "Chained : 0x%04x,0x%04x,0x%04x\n", ac97->spec.ad18xx.chained[0], ac97->spec.ad18xx.chained[1], ac97->spec.ad18xx.chained[2]); } else { snd_ac97_proc_read_main(ac97, buffer, 0); } mutex_unlock(&ac97->page_mutex); } #ifdef CONFIG_SND_DEBUG /* direct register write for debugging */ static void snd_ac97_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_ac97 *ac97 = entry->private_data; char line[64]; unsigned int reg, val; mutex_lock(&ac97->page_mutex); while (!snd_info_get_line(buffer, line, sizeof(line))) { if (sscanf(line, "%x %x", &reg, &val) != 2) continue; /* register must be even */ if (reg < 0x80 && (reg & 1) == 0 && val <= 0xffff) snd_ac97_write_cache(ac97, reg, val); } mutex_unlock(&ac97->page_mutex); } #endif static void snd_ac97_proc_regs_read_main(struct snd_ac97 *ac97, struct snd_info_buffer *buffer, int subidx) { int reg, val; for (reg = 0; reg < 0x80; reg += 2) { val = snd_ac97_read(ac97, reg); snd_iprintf(buffer, "%i:%02x = %04x\n", subidx, reg, val); } } static void snd_ac97_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_ac97 *ac97 = entry->private_data; mutex_lock(&ac97->page_mutex); if ((ac97->id & 0xffffff40) == AC97_ID_AD1881) { // Analog Devices AD1881/85/86 int idx; for (idx = 0; idx < 3; idx++) if (ac97->spec.ad18xx.id[idx]) { /* select single codec */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, ac97->spec.ad18xx.unchained[idx] | ac97->spec.ad18xx.chained[idx]); snd_ac97_proc_regs_read_main(ac97, buffer, idx); } /* select all codecs */ snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, 0x7000); } else { snd_ac97_proc_regs_read_main(ac97, buffer, 0); } mutex_unlock(&ac97->page_mutex); } void snd_ac97_proc_init(struct snd_ac97 * ac97) { struct snd_info_entry *entry; char name[32]; const char *prefix; if (ac97->bus->proc == NULL) return; prefix = ac97_is_audio(ac97) ? "ac97" : "mc97"; sprintf(name, "%s#%d-%d", prefix, ac97->addr, ac97->num); entry = snd_info_create_card_entry(ac97->bus->card, name, ac97->bus->proc); if (entry) snd_info_set_text_ops(entry, ac97, snd_ac97_proc_read); ac97->proc = entry; sprintf(name, "%s#%d-%d+regs", prefix, ac97->addr, ac97->num); entry = snd_info_create_card_entry(ac97->bus->card, name, ac97->bus->proc); if (entry) { snd_info_set_text_ops(entry, ac97, snd_ac97_proc_regs_read); #ifdef CONFIG_SND_DEBUG entry->mode |= 0200; entry->c.text.write = snd_ac97_proc_regs_write; #endif } ac97->proc_regs = entry; } void snd_ac97_proc_done(struct snd_ac97 * ac97) { snd_info_free_entry(ac97->proc_regs); ac97->proc_regs = NULL; snd_info_free_entry(ac97->proc); ac97->proc = NULL; } void snd_ac97_bus_proc_init(struct snd_ac97_bus * bus) { struct snd_info_entry *entry; char name[32]; sprintf(name, "codec97#%d", bus->num); entry = snd_info_create_card_entry(bus->card, name, bus->card->proc_root); if (entry) entry->mode = S_IFDIR | 0555; bus->proc = entry; } void snd_ac97_bus_proc_done(struct snd_ac97_bus * bus) { snd_info_free_entry(bus->proc); bus->proc = NULL; }
linux-master
sound/pci/ac97/ac97_proc.c
// SPDX-License-Identifier: GPL-2.0-only /************************************************************************ AudioScience HPI driver Copyright (C) 1997-2011 AudioScience Inc. <[email protected]> Debug macro translation. ************************************************************************/ #include "hpi_internal.h" #include "hpidebug.h" /* Debug level; 0 quiet; 1 informative, 2 debug, 3 verbose debug. */ int hpi_debug_level = HPI_DEBUG_LEVEL_DEFAULT; void hpi_debug_init(void) { printk(KERN_INFO "debug start\n"); } int hpi_debug_level_set(int level) { int old_level; old_level = hpi_debug_level; hpi_debug_level = level; return old_level; } int hpi_debug_level_get(void) { return hpi_debug_level; } void hpi_debug_message(struct hpi_message *phm, char *sz_fileline) { if (phm) { printk(KERN_DEBUG "HPI_MSG%d,%d,%d,%d,%d\n", phm->version, phm->adapter_index, phm->obj_index, phm->function, phm->u.c.attribute); } } void hpi_debug_data(u16 *pdata, u32 len) { u32 i; int j; int k; int lines; int cols = 8; lines = DIV_ROUND_UP(len, cols); if (lines > 8) lines = 8; for (i = 0, j = 0; j < lines; j++) { printk(KERN_DEBUG "%p:", (pdata + i)); for (k = 0; k < cols && i < len; i++, k++) printk(KERN_CONT "%s%04x", k == 0 ? "" : " ", pdata[i]); printk(KERN_CONT "\n"); } }
linux-master
sound/pci/asihpi/hpidebug.c
// SPDX-License-Identifier: GPL-2.0-only /* * Asihpi soundcard * Copyright (c) by AudioScience Inc <[email protected]> * * The following is not a condition of use, merely a request: * If you modify this program, particularly if you fix errors, AudioScience Inc * would appreciate it if you grant us the right to use those modifications * for any purpose including commercial applications. */ #include "hpi_internal.h" #include "hpi_version.h" #include "hpimsginit.h" #include "hpioctl.h" #include "hpicmn.h" #include <linux/pci.h> #include <linux/init.h> #include <linux/jiffies.h> #include <linux/slab.h> #include <linux/time.h> #include <linux/wait.h> #include <linux/module.h> #include <sound/core.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/info.h> #include <sound/initval.h> #include <sound/tlv.h> #include <sound/hwdep.h> MODULE_LICENSE("GPL"); MODULE_AUTHOR("AudioScience inc. <[email protected]>"); MODULE_DESCRIPTION("AudioScience ALSA ASI5xxx ASI6xxx ASI87xx ASI89xx " HPI_VER_STRING); #if defined CONFIG_SND_DEBUG_VERBOSE /** * snd_printddd - very verbose debug printk * @format: format string * * Works like snd_printk() for debugging purposes. * Ignored when CONFIG_SND_DEBUG_VERBOSE is not set. * Must set snd module debug parameter to 3 to enable at runtime. */ #define snd_printddd(format, args...) \ __snd_printk(3, __FILE__, __LINE__, format, ##args) #else #define snd_printddd(format, args...) do { } while (0) #endif static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; static bool enable_hpi_hwdep = 1; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "ALSA index value for AudioScience soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ALSA ID string for AudioScience soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "ALSA enable AudioScience soundcard."); module_param(enable_hpi_hwdep, bool, 0644); MODULE_PARM_DESC(enable_hpi_hwdep, "ALSA enable HPI hwdep for AudioScience soundcard "); /* identify driver */ #ifdef KERNEL_ALSA_BUILD static char *build_info = "Built using headers from kernel source"; module_param(build_info, charp, 0444); MODULE_PARM_DESC(build_info, "Built using headers from kernel source"); #else static char *build_info = "Built within ALSA source"; module_param(build_info, charp, 0444); MODULE_PARM_DESC(build_info, "Built within ALSA source"); #endif /* set to 1 to dump every control from adapter to log */ static const int mixer_dump; #define DEFAULT_SAMPLERATE 44100 static int adapter_fs = DEFAULT_SAMPLERATE; /* defaults */ #define PERIODS_MIN 2 #define PERIOD_BYTES_MIN 2048 #define BUFFER_BYTES_MAX (512 * 1024) #define MAX_CLOCKSOURCES (HPI_SAMPLECLOCK_SOURCE_LAST + 1 + 7) struct clk_source { int source; int index; const char *name; }; struct clk_cache { int count; int has_local; struct clk_source s[MAX_CLOCKSOURCES]; }; /* Per card data */ struct snd_card_asihpi { struct snd_card *card; struct pci_dev *pci; struct hpi_adapter *hpi; /* In low latency mode there is only one stream, a pointer to its * private data is stored here on trigger and cleared on stop. * The interrupt handler uses it as a parameter when calling * snd_card_asihpi_timer_function(). */ struct snd_card_asihpi_pcm *llmode_streampriv; void (*pcm_start)(struct snd_pcm_substream *substream); void (*pcm_stop)(struct snd_pcm_substream *substream); u32 h_mixer; struct clk_cache cc; u16 can_dma; u16 support_grouping; u16 support_mrx; u16 update_interval_frames; u16 in_max_chans; u16 out_max_chans; u16 in_min_chans; u16 out_min_chans; }; /* Per stream data */ struct snd_card_asihpi_pcm { struct timer_list timer; unsigned int respawn_timer; unsigned int hpi_buffer_attached; unsigned int buffer_bytes; unsigned int period_bytes; unsigned int bytes_per_sec; unsigned int pcm_buf_host_rw_ofs; /* Host R/W pos */ unsigned int pcm_buf_dma_ofs; /* DMA R/W offset in buffer */ unsigned int pcm_buf_elapsed_dma_ofs; /* DMA R/W offset in buffer */ unsigned int drained_count; struct snd_pcm_substream *substream; u32 h_stream; struct hpi_format format; }; /* universal stream verbs work with out or in stream handles */ /* Functions to allow driver to give a buffer to HPI for busmastering */ static u16 hpi_stream_host_buffer_attach( u32 h_stream, /* handle to outstream. */ u32 size_in_bytes, /* size in bytes of bus mastering buffer */ u32 pci_address ) { struct hpi_message hm; struct hpi_response hr; unsigned int obj = hpi_handle_object(h_stream); if (!h_stream) return HPI_ERROR_INVALID_OBJ; hpi_init_message_response(&hm, &hr, obj, obj == HPI_OBJ_OSTREAM ? HPI_OSTREAM_HOSTBUFFER_ALLOC : HPI_ISTREAM_HOSTBUFFER_ALLOC); hpi_handle_to_indexes(h_stream, &hm.adapter_index, &hm.obj_index); hm.u.d.u.buffer.buffer_size = size_in_bytes; hm.u.d.u.buffer.pci_address = pci_address; hm.u.d.u.buffer.command = HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER; hpi_send_recv(&hm, &hr); return hr.error; } static u16 hpi_stream_host_buffer_detach(u32 h_stream) { struct hpi_message hm; struct hpi_response hr; unsigned int obj = hpi_handle_object(h_stream); if (!h_stream) return HPI_ERROR_INVALID_OBJ; hpi_init_message_response(&hm, &hr, obj, obj == HPI_OBJ_OSTREAM ? HPI_OSTREAM_HOSTBUFFER_FREE : HPI_ISTREAM_HOSTBUFFER_FREE); hpi_handle_to_indexes(h_stream, &hm.adapter_index, &hm.obj_index); hm.u.d.u.buffer.command = HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER; hpi_send_recv(&hm, &hr); return hr.error; } static inline u16 hpi_stream_start(u32 h_stream) { if (hpi_handle_object(h_stream) == HPI_OBJ_OSTREAM) return hpi_outstream_start(h_stream); else return hpi_instream_start(h_stream); } static inline u16 hpi_stream_stop(u32 h_stream) { if (hpi_handle_object(h_stream) == HPI_OBJ_OSTREAM) return hpi_outstream_stop(h_stream); else return hpi_instream_stop(h_stream); } static inline u16 hpi_stream_get_info_ex( u32 h_stream, u16 *pw_state, u32 *pbuffer_size, u32 *pdata_in_buffer, u32 *psample_count, u32 *pauxiliary_data ) { u16 e; if (hpi_handle_object(h_stream) == HPI_OBJ_OSTREAM) e = hpi_outstream_get_info_ex(h_stream, pw_state, pbuffer_size, pdata_in_buffer, psample_count, pauxiliary_data); else e = hpi_instream_get_info_ex(h_stream, pw_state, pbuffer_size, pdata_in_buffer, psample_count, pauxiliary_data); return e; } static inline u16 hpi_stream_group_add( u32 h_master, u32 h_stream) { if (hpi_handle_object(h_master) == HPI_OBJ_OSTREAM) return hpi_outstream_group_add(h_master, h_stream); else return hpi_instream_group_add(h_master, h_stream); } static inline u16 hpi_stream_group_reset(u32 h_stream) { if (hpi_handle_object(h_stream) == HPI_OBJ_OSTREAM) return hpi_outstream_group_reset(h_stream); else return hpi_instream_group_reset(h_stream); } static u16 handle_error(u16 err, int line, char *filename) { if (err) printk(KERN_WARNING "in file %s, line %d: HPI error %d\n", filename, line, err); return err; } #define hpi_handle_error(x) handle_error(x, __LINE__, __FILE__) /***************************** GENERAL PCM ****************/ static void print_hwparams(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *p) { char name[16]; snd_pcm_debug_name(substream, name, sizeof(name)); snd_printdd("%s HWPARAMS\n", name); snd_printdd(" samplerate=%dHz channels=%d format=%d subformat=%d\n", params_rate(p), params_channels(p), params_format(p), params_subformat(p)); snd_printdd(" buffer=%dB period=%dB period_size=%dB periods=%d\n", params_buffer_bytes(p), params_period_bytes(p), params_period_size(p), params_periods(p)); snd_printdd(" buffer_size=%d access=%d data_rate=%dB/s\n", params_buffer_size(p), params_access(p), params_rate(p) * params_channels(p) * snd_pcm_format_width(params_format(p)) / 8); } #define INVALID_FORMAT (__force snd_pcm_format_t)(-1) static const snd_pcm_format_t hpi_to_alsa_formats[] = { INVALID_FORMAT, /* INVALID */ SNDRV_PCM_FORMAT_U8, /* HPI_FORMAT_PCM8_UNSIGNED 1 */ SNDRV_PCM_FORMAT_S16, /* HPI_FORMAT_PCM16_SIGNED 2 */ INVALID_FORMAT, /* HPI_FORMAT_MPEG_L1 3 */ SNDRV_PCM_FORMAT_MPEG, /* HPI_FORMAT_MPEG_L2 4 */ SNDRV_PCM_FORMAT_MPEG, /* HPI_FORMAT_MPEG_L3 5 */ INVALID_FORMAT, /* HPI_FORMAT_DOLBY_AC2 6 */ INVALID_FORMAT, /* HPI_FORMAT_DOLBY_AC3 7 */ SNDRV_PCM_FORMAT_S16_BE,/* HPI_FORMAT_PCM16_BIGENDIAN 8 */ INVALID_FORMAT, /* HPI_FORMAT_AA_TAGIT1_HITS 9 */ INVALID_FORMAT, /* HPI_FORMAT_AA_TAGIT1_INSERTS 10 */ SNDRV_PCM_FORMAT_S32, /* HPI_FORMAT_PCM32_SIGNED 11 */ INVALID_FORMAT, /* HPI_FORMAT_RAW_BITSTREAM 12 */ INVALID_FORMAT, /* HPI_FORMAT_AA_TAGIT1_HITS_EX1 13 */ SNDRV_PCM_FORMAT_FLOAT, /* HPI_FORMAT_PCM32_FLOAT 14 */ #if 1 /* ALSA can't handle 3 byte sample size together with power-of-2 * constraint on buffer_bytes, so disable this format */ INVALID_FORMAT #else /* SNDRV_PCM_FORMAT_S24_3LE */ /* HPI_FORMAT_PCM24_SIGNED 15 */ #endif }; static int snd_card_asihpi_format_alsa2hpi(snd_pcm_format_t alsa_format, u16 *hpi_format) { u16 format; for (format = HPI_FORMAT_PCM8_UNSIGNED; format <= HPI_FORMAT_PCM24_SIGNED; format++) { if (hpi_to_alsa_formats[format] == alsa_format) { *hpi_format = format; return 0; } } snd_printd(KERN_WARNING "failed match for alsa format %d\n", alsa_format); *hpi_format = 0; return -EINVAL; } static void snd_card_asihpi_pcm_samplerates(struct snd_card_asihpi *asihpi, struct snd_pcm_hardware *pcmhw) { u16 err; u32 h_control; u32 sample_rate; int idx; unsigned int rate_min = 200000; unsigned int rate_max = 0; unsigned int rates = 0; if (asihpi->support_mrx) { rates |= SNDRV_PCM_RATE_CONTINUOUS; rates |= SNDRV_PCM_RATE_8000_96000; rate_min = 8000; rate_max = 100000; } else { /* on cards without SRC, valid rates are determined by sampleclock */ err = hpi_mixer_get_control(asihpi->h_mixer, HPI_SOURCENODE_CLOCK_SOURCE, 0, 0, 0, HPI_CONTROL_SAMPLECLOCK, &h_control); if (err) { dev_err(&asihpi->pci->dev, "No local sampleclock, err %d\n", err); } for (idx = -1; idx < 100; idx++) { if (idx == -1) { if (hpi_sample_clock_get_sample_rate(h_control, &sample_rate)) continue; } else if (hpi_sample_clock_query_local_rate(h_control, idx, &sample_rate)) { break; } rate_min = min(rate_min, sample_rate); rate_max = max(rate_max, sample_rate); switch (sample_rate) { case 5512: rates |= SNDRV_PCM_RATE_5512; break; case 8000: rates |= SNDRV_PCM_RATE_8000; break; case 11025: rates |= SNDRV_PCM_RATE_11025; break; case 16000: rates |= SNDRV_PCM_RATE_16000; break; case 22050: rates |= SNDRV_PCM_RATE_22050; break; case 32000: rates |= SNDRV_PCM_RATE_32000; break; case 44100: rates |= SNDRV_PCM_RATE_44100; break; case 48000: rates |= SNDRV_PCM_RATE_48000; break; case 64000: rates |= SNDRV_PCM_RATE_64000; break; case 88200: rates |= SNDRV_PCM_RATE_88200; break; case 96000: rates |= SNDRV_PCM_RATE_96000; break; case 176400: rates |= SNDRV_PCM_RATE_176400; break; case 192000: rates |= SNDRV_PCM_RATE_192000; break; default: /* some other rate */ rates |= SNDRV_PCM_RATE_KNOT; } } } pcmhw->rates = rates; pcmhw->rate_min = rate_min; pcmhw->rate_max = rate_max; } static int snd_card_asihpi_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; struct snd_card_asihpi *card = snd_pcm_substream_chip(substream); int err; u16 format; int width; unsigned int bytes_per_sec; print_hwparams(substream, params); err = snd_card_asihpi_format_alsa2hpi(params_format(params), &format); if (err) return err; hpi_handle_error(hpi_format_create(&dpcm->format, params_channels(params), format, params_rate(params), 0, 0)); if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { if (hpi_instream_reset(dpcm->h_stream) != 0) return -EINVAL; if (hpi_instream_set_format( dpcm->h_stream, &dpcm->format) != 0) return -EINVAL; } dpcm->hpi_buffer_attached = 0; if (card->can_dma) { err = hpi_stream_host_buffer_attach(dpcm->h_stream, params_buffer_bytes(params), runtime->dma_addr); if (err == 0) { snd_printdd( "stream_host_buffer_attach success %u %lu\n", params_buffer_bytes(params), (unsigned long)runtime->dma_addr); } else { snd_printd("stream_host_buffer_attach error %d\n", err); return -ENOMEM; } err = hpi_stream_get_info_ex(dpcm->h_stream, NULL, &dpcm->hpi_buffer_attached, NULL, NULL, NULL); } bytes_per_sec = params_rate(params) * params_channels(params); width = snd_pcm_format_width(params_format(params)); bytes_per_sec *= width; bytes_per_sec /= 8; if (width < 0 || bytes_per_sec == 0) return -EINVAL; dpcm->bytes_per_sec = bytes_per_sec; dpcm->buffer_bytes = params_buffer_bytes(params); dpcm->period_bytes = params_period_bytes(params); return 0; } static int snd_card_asihpi_hw_free(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; if (dpcm->hpi_buffer_attached) hpi_stream_host_buffer_detach(dpcm->h_stream); return 0; } static void snd_card_asihpi_runtime_free(struct snd_pcm_runtime *runtime) { struct snd_card_asihpi_pcm *dpcm = runtime->private_data; kfree(dpcm); } static void snd_card_asihpi_pcm_timer_start(struct snd_pcm_substream * substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; int expiry; expiry = HZ / 200; expiry = max(expiry, 1); /* don't let it be zero! */ mod_timer(&dpcm->timer, jiffies + expiry); dpcm->respawn_timer = 1; } static void snd_card_asihpi_pcm_timer_stop(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; dpcm->respawn_timer = 0; del_timer(&dpcm->timer); } static void snd_card_asihpi_pcm_int_start(struct snd_pcm_substream *substream) { struct snd_card_asihpi_pcm *dpcm; struct snd_card_asihpi *card; dpcm = (struct snd_card_asihpi_pcm *)substream->runtime->private_data; card = snd_pcm_substream_chip(substream); WARN_ON(in_interrupt()); card->llmode_streampriv = dpcm; hpi_handle_error(hpi_adapter_set_property(card->hpi->adapter->index, HPI_ADAPTER_PROPERTY_IRQ_RATE, card->update_interval_frames, 0)); } static void snd_card_asihpi_pcm_int_stop(struct snd_pcm_substream *substream) { struct snd_card_asihpi *card; card = snd_pcm_substream_chip(substream); hpi_handle_error(hpi_adapter_set_property(card->hpi->adapter->index, HPI_ADAPTER_PROPERTY_IRQ_RATE, 0, 0)); card->llmode_streampriv = NULL; } static int snd_card_asihpi_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_card_asihpi_pcm *dpcm = substream->runtime->private_data; struct snd_card_asihpi *card = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; u16 e; char name[16]; snd_pcm_debug_name(substream, name, sizeof(name)); switch (cmd) { case SNDRV_PCM_TRIGGER_START: snd_printdd("%s trigger start\n", name); snd_pcm_group_for_each_entry(s, substream) { struct snd_pcm_runtime *runtime = s->runtime; struct snd_card_asihpi_pcm *ds = runtime->private_data; if (snd_pcm_substream_chip(s) != card) continue; /* don't link Cap and Play */ if (substream->stream != s->stream) continue; ds->drained_count = 0; if (s->stream == SNDRV_PCM_STREAM_PLAYBACK) { /* How do I know how much valid data is present * in buffer? Must be at least one period! * Guessing 2 periods, but if * buffer is bigger it may contain even more * data?? */ unsigned int preload = ds->period_bytes * 1; snd_printddd("%d preload %d\n", s->number, preload); hpi_handle_error(hpi_outstream_write_buf( ds->h_stream, &runtime->dma_area[0], preload, &ds->format)); ds->pcm_buf_host_rw_ofs = preload; } if (card->support_grouping) { snd_printdd("%d group\n", s->number); e = hpi_stream_group_add( dpcm->h_stream, ds->h_stream); if (!e) { snd_pcm_trigger_done(s, substream); } else { hpi_handle_error(e); break; } } else break; } /* start the master stream */ card->pcm_start(substream); if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE) || !card->can_dma) hpi_handle_error(hpi_stream_start(dpcm->h_stream)); break; case SNDRV_PCM_TRIGGER_STOP: snd_printdd("%s trigger stop\n", name); card->pcm_stop(substream); snd_pcm_group_for_each_entry(s, substream) { if (snd_pcm_substream_chip(s) != card) continue; /* don't link Cap and Play */ if (substream->stream != s->stream) continue; /*? workaround linked streams don't transition to SETUP 20070706*/ __snd_pcm_set_state(s->runtime, SNDRV_PCM_STATE_SETUP); if (card->support_grouping) { snd_printdd("%d group\n", s->number); snd_pcm_trigger_done(s, substream); } else break; } /* _prepare and _hwparams reset the stream */ hpi_handle_error(hpi_stream_stop(dpcm->h_stream)); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) hpi_handle_error( hpi_outstream_reset(dpcm->h_stream)); if (card->support_grouping) hpi_handle_error(hpi_stream_group_reset(dpcm->h_stream)); break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: snd_printdd("%s trigger pause release\n", name); card->pcm_start(substream); hpi_handle_error(hpi_stream_start(dpcm->h_stream)); break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: snd_printdd("%s trigger pause push\n", name); card->pcm_stop(substream); hpi_handle_error(hpi_stream_stop(dpcm->h_stream)); break; default: snd_printd(KERN_ERR "\tINVALID\n"); return -EINVAL; } return 0; } /*algorithm outline Without linking degenerates to getting single stream pos etc Without mmap 2nd loop degenerates to snd_pcm_period_elapsed */ /* pcm_buf_dma_ofs=get_buf_pos(s); for_each_linked_stream(s) { pcm_buf_dma_ofs=get_buf_pos(s); min_buf_pos = modulo_min(min_buf_pos, pcm_buf_dma_ofs, buffer_bytes) new_data = min(new_data, calc_new_data(pcm_buf_dma_ofs,irq_pos) } timer.expires = jiffies + predict_next_period_ready(min_buf_pos); for_each_linked_stream(s) { s->pcm_buf_dma_ofs = min_buf_pos; if (new_data > period_bytes) { if (mmap) { irq_pos = (irq_pos + period_bytes) % buffer_bytes; if (playback) { write(period_bytes); } else { read(period_bytes); } } snd_pcm_period_elapsed(s); } } */ /** Minimum of 2 modulo values. Works correctly when the difference between * the values is less than half the modulus */ static inline unsigned int modulo_min(unsigned int a, unsigned int b, unsigned long int modulus) { unsigned int result; if (((a-b) % modulus) < (modulus/2)) result = b; else result = a; return result; } /** Timer function, equivalent to interrupt service routine for cards */ static void snd_card_asihpi_timer_function(struct timer_list *t) { struct snd_card_asihpi_pcm *dpcm = from_timer(dpcm, t, timer); struct snd_pcm_substream *substream = dpcm->substream; struct snd_card_asihpi *card = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime; struct snd_pcm_substream *s; unsigned int newdata = 0; unsigned int pcm_buf_dma_ofs, min_buf_pos = 0; unsigned int remdata, xfercount, next_jiffies; int first = 1; u16 state; u32 buffer_size, bytes_avail, samples_played, on_card_bytes; char name[16]; snd_pcm_debug_name(substream, name, sizeof(name)); /* find minimum newdata and buffer pos in group */ snd_pcm_group_for_each_entry(s, substream) { struct snd_card_asihpi_pcm *ds = s->runtime->private_data; runtime = s->runtime; if (snd_pcm_substream_chip(s) != card) continue; /* don't link Cap and Play */ if (substream->stream != s->stream) continue; hpi_handle_error(hpi_stream_get_info_ex( ds->h_stream, &state, &buffer_size, &bytes_avail, &samples_played, &on_card_bytes)); /* number of bytes in on-card buffer */ runtime->delay = on_card_bytes; if (!card->can_dma) on_card_bytes = bytes_avail; if (s->stream == SNDRV_PCM_STREAM_PLAYBACK) { pcm_buf_dma_ofs = ds->pcm_buf_host_rw_ofs - bytes_avail; if (state == HPI_STATE_STOPPED) { if (bytes_avail == 0) { hpi_handle_error(hpi_stream_start(ds->h_stream)); snd_printdd("P%d start\n", s->number); ds->drained_count = 0; } } else if (state == HPI_STATE_DRAINED) { snd_printd(KERN_WARNING "P%d drained\n", s->number); ds->drained_count++; if (ds->drained_count > 20) { snd_pcm_stop_xrun(s); continue; } } else { ds->drained_count = 0; } } else pcm_buf_dma_ofs = bytes_avail + ds->pcm_buf_host_rw_ofs; if (first) { /* can't statically init min when wrap is involved */ min_buf_pos = pcm_buf_dma_ofs; newdata = (pcm_buf_dma_ofs - ds->pcm_buf_elapsed_dma_ofs) % ds->buffer_bytes; first = 0; } else { min_buf_pos = modulo_min(min_buf_pos, pcm_buf_dma_ofs, UINT_MAX+1L); newdata = min( (pcm_buf_dma_ofs - ds->pcm_buf_elapsed_dma_ofs) % ds->buffer_bytes, newdata); } snd_printddd( "timer1, %s, %d, S=%d, elap=%d, rw=%d, dsp=%d, left=%d, aux=%d, space=%d, hw_ptr=%ld, appl_ptr=%ld\n", name, s->number, state, ds->pcm_buf_elapsed_dma_ofs, ds->pcm_buf_host_rw_ofs, pcm_buf_dma_ofs, (int)bytes_avail, (int)on_card_bytes, buffer_size-bytes_avail, (unsigned long)frames_to_bytes(runtime, runtime->status->hw_ptr), (unsigned long)frames_to_bytes(runtime, runtime->control->appl_ptr) ); } pcm_buf_dma_ofs = min_buf_pos; remdata = newdata % dpcm->period_bytes; xfercount = newdata - remdata; /* a multiple of period_bytes */ /* come back when on_card_bytes has decreased enough to allow write to happen, or when data has been consumed to make another period */ if (xfercount && (on_card_bytes > dpcm->period_bytes)) next_jiffies = ((on_card_bytes - dpcm->period_bytes) * HZ / dpcm->bytes_per_sec); else next_jiffies = ((dpcm->period_bytes - remdata) * HZ / dpcm->bytes_per_sec); next_jiffies = max(next_jiffies, 1U); dpcm->timer.expires = jiffies + next_jiffies; snd_printddd("timer2, jif=%d, buf_pos=%d, newdata=%d, xfer=%d\n", next_jiffies, pcm_buf_dma_ofs, newdata, xfercount); snd_pcm_group_for_each_entry(s, substream) { struct snd_card_asihpi_pcm *ds = s->runtime->private_data; /* don't link Cap and Play */ if (substream->stream != s->stream) continue; /* Store dma offset for use by pointer callback */ ds->pcm_buf_dma_ofs = pcm_buf_dma_ofs; if (xfercount && /* Limit use of on card fifo for playback */ ((on_card_bytes <= ds->period_bytes) || (s->stream == SNDRV_PCM_STREAM_CAPTURE))) { unsigned int buf_ofs = ds->pcm_buf_host_rw_ofs % ds->buffer_bytes; unsigned int xfer1, xfer2; char *pd = &s->runtime->dma_area[buf_ofs]; if (card->can_dma) { /* buffer wrap is handled at lower level */ xfer1 = xfercount; xfer2 = 0; } else { xfer1 = min(xfercount, ds->buffer_bytes - buf_ofs); xfer2 = xfercount - xfer1; } if (s->stream == SNDRV_PCM_STREAM_PLAYBACK) { snd_printddd("write1, P=%d, xfer=%d, buf_ofs=%d\n", s->number, xfer1, buf_ofs); hpi_handle_error( hpi_outstream_write_buf( ds->h_stream, pd, xfer1, &ds->format)); if (xfer2) { pd = s->runtime->dma_area; snd_printddd("write2, P=%d, xfer=%d, buf_ofs=%d\n", s->number, xfercount - xfer1, buf_ofs); hpi_handle_error( hpi_outstream_write_buf( ds->h_stream, pd, xfercount - xfer1, &ds->format)); } } else { snd_printddd("read1, C=%d, xfer=%d\n", s->number, xfer1); hpi_handle_error( hpi_instream_read_buf( ds->h_stream, pd, xfer1)); if (xfer2) { pd = s->runtime->dma_area; snd_printddd("read2, C=%d, xfer=%d\n", s->number, xfer2); hpi_handle_error( hpi_instream_read_buf( ds->h_stream, pd, xfer2)); } } /* ? host_rw_ofs always ahead of elapsed_dma_ofs by preload size? */ ds->pcm_buf_host_rw_ofs += xfercount; ds->pcm_buf_elapsed_dma_ofs += xfercount; snd_pcm_period_elapsed(s); } } if (!card->hpi->interrupt_mode && dpcm->respawn_timer) add_timer(&dpcm->timer); } static void snd_card_asihpi_isr(struct hpi_adapter *a) { struct snd_card_asihpi *asihpi; WARN_ON(!a || !a->snd_card || !a->snd_card->private_data); asihpi = (struct snd_card_asihpi *)a->snd_card->private_data; if (asihpi->llmode_streampriv) snd_card_asihpi_timer_function( &asihpi->llmode_streampriv->timer); } /***************************** PLAYBACK OPS ****************/ static int snd_card_asihpi_playback_prepare(struct snd_pcm_substream * substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; snd_printdd("P%d prepare\n", substream->number); hpi_handle_error(hpi_outstream_reset(dpcm->h_stream)); dpcm->pcm_buf_host_rw_ofs = 0; dpcm->pcm_buf_dma_ofs = 0; dpcm->pcm_buf_elapsed_dma_ofs = 0; return 0; } static snd_pcm_uframes_t snd_card_asihpi_playback_pointer(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; snd_pcm_uframes_t ptr; char name[16]; snd_pcm_debug_name(substream, name, sizeof(name)); ptr = bytes_to_frames(runtime, dpcm->pcm_buf_dma_ofs % dpcm->buffer_bytes); snd_printddd("%s, pointer=%ld\n", name, (unsigned long)ptr); return ptr; } static u64 snd_card_asihpi_playback_formats(struct snd_card_asihpi *asihpi, u32 h_stream) { struct hpi_format hpi_format; u16 format; u16 err; u32 h_control; u32 sample_rate = 48000; u64 formats = 0; /* on cards without SRC, must query at valid rate, * maybe set by external sync */ err = hpi_mixer_get_control(asihpi->h_mixer, HPI_SOURCENODE_CLOCK_SOURCE, 0, 0, 0, HPI_CONTROL_SAMPLECLOCK, &h_control); if (!err) err = hpi_sample_clock_get_sample_rate(h_control, &sample_rate); for (format = HPI_FORMAT_PCM8_UNSIGNED; format <= HPI_FORMAT_PCM24_SIGNED; format++) { err = hpi_format_create(&hpi_format, asihpi->out_max_chans, format, sample_rate, 128000, 0); if (!err) err = hpi_outstream_query_format(h_stream, &hpi_format); if (!err && (hpi_to_alsa_formats[format] != INVALID_FORMAT)) formats |= pcm_format_to_bits(hpi_to_alsa_formats[format]); } return formats; } static int snd_card_asihpi_playback_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm; struct snd_card_asihpi *card = snd_pcm_substream_chip(substream); struct snd_pcm_hardware snd_card_asihpi_playback; int err; dpcm = kzalloc(sizeof(*dpcm), GFP_KERNEL); if (dpcm == NULL) return -ENOMEM; err = hpi_outstream_open(card->hpi->adapter->index, substream->number, &dpcm->h_stream); hpi_handle_error(err); if (err) kfree(dpcm); if (err == HPI_ERROR_OBJ_ALREADY_OPEN) return -EBUSY; if (err) return -EIO; /*? also check ASI5000 samplerate source If external, only support external rate. If internal and other stream playing, can't switch */ timer_setup(&dpcm->timer, snd_card_asihpi_timer_function, 0); dpcm->substream = substream; runtime->private_data = dpcm; runtime->private_free = snd_card_asihpi_runtime_free; memset(&snd_card_asihpi_playback, 0, sizeof(snd_card_asihpi_playback)); if (!card->hpi->interrupt_mode) { snd_card_asihpi_playback.buffer_bytes_max = BUFFER_BYTES_MAX; snd_card_asihpi_playback.period_bytes_min = PERIOD_BYTES_MIN; snd_card_asihpi_playback.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN; snd_card_asihpi_playback.periods_min = PERIODS_MIN; snd_card_asihpi_playback.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN; } else { size_t pbmin = card->update_interval_frames * card->out_max_chans; snd_card_asihpi_playback.buffer_bytes_max = BUFFER_BYTES_MAX; snd_card_asihpi_playback.period_bytes_min = pbmin; snd_card_asihpi_playback.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN; snd_card_asihpi_playback.periods_min = PERIODS_MIN; snd_card_asihpi_playback.periods_max = BUFFER_BYTES_MAX / pbmin; } /* snd_card_asihpi_playback.fifo_size = 0; */ snd_card_asihpi_playback.channels_max = card->out_max_chans; snd_card_asihpi_playback.channels_min = card->out_min_chans; snd_card_asihpi_playback.formats = snd_card_asihpi_playback_formats(card, dpcm->h_stream); snd_card_asihpi_pcm_samplerates(card, &snd_card_asihpi_playback); snd_card_asihpi_playback.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_DOUBLE | SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID; if (card->support_grouping) { snd_card_asihpi_playback.info |= SNDRV_PCM_INFO_SYNC_START; snd_pcm_set_sync(substream); } /* struct is copied, so can create initializer dynamically */ runtime->hw = snd_card_asihpi_playback; if (card->can_dma) err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); if (err < 0) return err; snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, card->update_interval_frames); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, card->update_interval_frames, UINT_MAX); snd_printdd("playback open\n"); return 0; } static int snd_card_asihpi_playback_close(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; hpi_handle_error(hpi_outstream_close(dpcm->h_stream)); snd_printdd("playback close\n"); return 0; } static const struct snd_pcm_ops snd_card_asihpi_playback_mmap_ops = { .open = snd_card_asihpi_playback_open, .close = snd_card_asihpi_playback_close, .hw_params = snd_card_asihpi_pcm_hw_params, .hw_free = snd_card_asihpi_hw_free, .prepare = snd_card_asihpi_playback_prepare, .trigger = snd_card_asihpi_trigger, .pointer = snd_card_asihpi_playback_pointer, }; /***************************** CAPTURE OPS ****************/ static snd_pcm_uframes_t snd_card_asihpi_capture_pointer(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; char name[16]; snd_pcm_debug_name(substream, name, sizeof(name)); snd_printddd("%s, pointer=%d\n", name, dpcm->pcm_buf_dma_ofs); /* NOTE Unlike playback can't use actual samples_played for the capture position, because those samples aren't yet in the local buffer available for reading. */ return bytes_to_frames(runtime, dpcm->pcm_buf_dma_ofs % dpcm->buffer_bytes); } static int snd_card_asihpi_capture_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi_pcm *dpcm = runtime->private_data; hpi_handle_error(hpi_instream_reset(dpcm->h_stream)); dpcm->pcm_buf_host_rw_ofs = 0; dpcm->pcm_buf_dma_ofs = 0; dpcm->pcm_buf_elapsed_dma_ofs = 0; snd_printdd("Capture Prepare %d\n", substream->number); return 0; } static u64 snd_card_asihpi_capture_formats(struct snd_card_asihpi *asihpi, u32 h_stream) { struct hpi_format hpi_format; u16 format; u16 err; u32 h_control; u32 sample_rate = 48000; u64 formats = 0; /* on cards without SRC, must query at valid rate, maybe set by external sync */ err = hpi_mixer_get_control(asihpi->h_mixer, HPI_SOURCENODE_CLOCK_SOURCE, 0, 0, 0, HPI_CONTROL_SAMPLECLOCK, &h_control); if (!err) err = hpi_sample_clock_get_sample_rate(h_control, &sample_rate); for (format = HPI_FORMAT_PCM8_UNSIGNED; format <= HPI_FORMAT_PCM24_SIGNED; format++) { err = hpi_format_create(&hpi_format, asihpi->in_max_chans, format, sample_rate, 128000, 0); if (!err) err = hpi_instream_query_format(h_stream, &hpi_format); if (!err && (hpi_to_alsa_formats[format] != INVALID_FORMAT)) formats |= pcm_format_to_bits(hpi_to_alsa_formats[format]); } return formats; } static int snd_card_asihpi_capture_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_card_asihpi *card = snd_pcm_substream_chip(substream); struct snd_card_asihpi_pcm *dpcm; struct snd_pcm_hardware snd_card_asihpi_capture; int err; dpcm = kzalloc(sizeof(*dpcm), GFP_KERNEL); if (dpcm == NULL) return -ENOMEM; snd_printdd("capture open adapter %d stream %d\n", card->hpi->adapter->index, substream->number); err = hpi_handle_error( hpi_instream_open(card->hpi->adapter->index, substream->number, &dpcm->h_stream)); if (err) kfree(dpcm); if (err == HPI_ERROR_OBJ_ALREADY_OPEN) return -EBUSY; if (err) return -EIO; timer_setup(&dpcm->timer, snd_card_asihpi_timer_function, 0); dpcm->substream = substream; runtime->private_data = dpcm; runtime->private_free = snd_card_asihpi_runtime_free; memset(&snd_card_asihpi_capture, 0, sizeof(snd_card_asihpi_capture)); if (!card->hpi->interrupt_mode) { snd_card_asihpi_capture.buffer_bytes_max = BUFFER_BYTES_MAX; snd_card_asihpi_capture.period_bytes_min = PERIOD_BYTES_MIN; snd_card_asihpi_capture.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN; snd_card_asihpi_capture.periods_min = PERIODS_MIN; snd_card_asihpi_capture.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN; } else { size_t pbmin = card->update_interval_frames * card->out_max_chans; snd_card_asihpi_capture.buffer_bytes_max = BUFFER_BYTES_MAX; snd_card_asihpi_capture.period_bytes_min = pbmin; snd_card_asihpi_capture.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN; snd_card_asihpi_capture.periods_min = PERIODS_MIN; snd_card_asihpi_capture.periods_max = BUFFER_BYTES_MAX / pbmin; } /* snd_card_asihpi_capture.fifo_size = 0; */ snd_card_asihpi_capture.channels_max = card->in_max_chans; snd_card_asihpi_capture.channels_min = card->in_min_chans; snd_card_asihpi_capture.formats = snd_card_asihpi_capture_formats(card, dpcm->h_stream); snd_card_asihpi_pcm_samplerates(card, &snd_card_asihpi_capture); snd_card_asihpi_capture.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID; if (card->support_grouping) snd_card_asihpi_capture.info |= SNDRV_PCM_INFO_SYNC_START; runtime->hw = snd_card_asihpi_capture; if (card->can_dma) err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); if (err < 0) return err; snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, card->update_interval_frames); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, card->update_interval_frames, UINT_MAX); snd_pcm_set_sync(substream); return 0; } static int snd_card_asihpi_capture_close(struct snd_pcm_substream *substream) { struct snd_card_asihpi_pcm *dpcm = substream->runtime->private_data; hpi_handle_error(hpi_instream_close(dpcm->h_stream)); return 0; } static const struct snd_pcm_ops snd_card_asihpi_capture_mmap_ops = { .open = snd_card_asihpi_capture_open, .close = snd_card_asihpi_capture_close, .hw_params = snd_card_asihpi_pcm_hw_params, .hw_free = snd_card_asihpi_hw_free, .prepare = snd_card_asihpi_capture_prepare, .trigger = snd_card_asihpi_trigger, .pointer = snd_card_asihpi_capture_pointer, }; static int snd_card_asihpi_pcm_new(struct snd_card_asihpi *asihpi, int device) { struct snd_pcm *pcm; int err; u16 num_instreams, num_outstreams, x16; u32 x32; err = hpi_adapter_get_info(asihpi->hpi->adapter->index, &num_outstreams, &num_instreams, &x16, &x32, &x16); err = snd_pcm_new(asihpi->card, "Asihpi PCM", device, num_outstreams, num_instreams, &pcm); if (err < 0) return err; /* pointer to ops struct is stored, dont change ops afterwards! */ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_card_asihpi_playback_mmap_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_card_asihpi_capture_mmap_ops); pcm->private_data = asihpi; pcm->info_flags = 0; strcpy(pcm->name, "Asihpi PCM"); /*? do we want to emulate MMAP for non-BBM cards? Jack doesn't work with ALSAs MMAP emulation - WHY NOT? */ snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &asihpi->pci->dev, 64*1024, BUFFER_BYTES_MAX); return 0; } /***************************** MIXER CONTROLS ****************/ struct hpi_control { u32 h_control; u16 control_type; u16 src_node_type; u16 src_node_index; u16 dst_node_type; u16 dst_node_index; u16 band; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; /* copied to snd_ctl_elem_id.name[44]; */ }; static const char * const asihpi_tuner_band_names[] = { "invalid", "AM", "FM mono", "TV NTSC-M", "FM stereo", "AUX", "TV PAL BG", "TV PAL I", "TV PAL DK", "TV SECAM", "TV DAB", }; /* Number of strings must match the enumerations for HPI_TUNER_BAND in hpi.h */ compile_time_assert( (ARRAY_SIZE(asihpi_tuner_band_names) == (HPI_TUNER_BAND_LAST+1)), assert_tuner_band_names_size); static const char * const asihpi_src_names[] = { "no source", "PCM", "Line", "Digital", "Tuner", "RF", "Clock", "Bitstream", "Mic", "Net", "Analog", "Adapter", "RTP", "Internal", "AVB", "BLU-Link" }; /* Number of strings must match the enumerations for HPI_SOURCENODES in hpi.h */ compile_time_assert( (ARRAY_SIZE(asihpi_src_names) == (HPI_SOURCENODE_LAST_INDEX-HPI_SOURCENODE_NONE+1)), assert_src_names_size); static const char * const asihpi_dst_names[] = { "no destination", "PCM", "Line", "Digital", "RF", "Speaker", "Net", "Analog", "RTP", "AVB", "Internal", "BLU-Link" }; /* Number of strings must match the enumerations for HPI_DESTNODES in hpi.h */ compile_time_assert( (ARRAY_SIZE(asihpi_dst_names) == (HPI_DESTNODE_LAST_INDEX-HPI_DESTNODE_NONE+1)), assert_dst_names_size); static inline int ctl_add(struct snd_card *card, struct snd_kcontrol_new *ctl, struct snd_card_asihpi *asihpi) { int err; err = snd_ctl_add(card, snd_ctl_new1(ctl, asihpi)); if (err < 0) return err; else if (mixer_dump) dev_info(&asihpi->pci->dev, "added %s(%d)\n", ctl->name, ctl->index); return 0; } /* Convert HPI control name and location into ALSA control name */ static void asihpi_ctl_init(struct snd_kcontrol_new *snd_control, struct hpi_control *hpi_ctl, char *name) { char *dir; memset(snd_control, 0, sizeof(*snd_control)); snd_control->name = hpi_ctl->name; snd_control->private_value = hpi_ctl->h_control; snd_control->iface = SNDRV_CTL_ELEM_IFACE_MIXER; snd_control->index = 0; if (hpi_ctl->src_node_type + HPI_SOURCENODE_NONE == HPI_SOURCENODE_CLOCK_SOURCE) dir = ""; /* clock is neither capture nor playback */ else if (hpi_ctl->dst_node_type + HPI_DESTNODE_NONE == HPI_DESTNODE_ISTREAM) dir = "Capture "; /* On or towards a PCM capture destination*/ else if ((hpi_ctl->src_node_type + HPI_SOURCENODE_NONE != HPI_SOURCENODE_OSTREAM) && (!hpi_ctl->dst_node_type)) dir = "Capture "; /* On a source node that is not PCM playback */ else if (hpi_ctl->src_node_type && (hpi_ctl->src_node_type + HPI_SOURCENODE_NONE != HPI_SOURCENODE_OSTREAM) && (hpi_ctl->dst_node_type)) dir = "Monitor Playback "; /* Between an input and an output */ else dir = "Playback "; /* PCM Playback source, or output node */ if (hpi_ctl->src_node_type && hpi_ctl->dst_node_type) sprintf(hpi_ctl->name, "%s %d %s %d %s%s", asihpi_src_names[hpi_ctl->src_node_type], hpi_ctl->src_node_index, asihpi_dst_names[hpi_ctl->dst_node_type], hpi_ctl->dst_node_index, dir, name); else if (hpi_ctl->dst_node_type) { sprintf(hpi_ctl->name, "%s %d %s%s", asihpi_dst_names[hpi_ctl->dst_node_type], hpi_ctl->dst_node_index, dir, name); } else { sprintf(hpi_ctl->name, "%s %d %s%s", asihpi_src_names[hpi_ctl->src_node_type], hpi_ctl->src_node_index, dir, name); } /* printk(KERN_INFO "Adding %s %d to %d ", hpi_ctl->name, hpi_ctl->wSrcNodeType, hpi_ctl->wDstNodeType); */ } /*------------------------------------------------------------ Volume controls ------------------------------------------------------------*/ #define VOL_STEP_mB 1 static int snd_asihpi_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u32 h_control = kcontrol->private_value; u32 count; u16 err; /* native gains are in millibels */ short min_gain_mB; short max_gain_mB; short step_gain_mB; err = hpi_volume_query_range(h_control, &min_gain_mB, &max_gain_mB, &step_gain_mB); if (err) { max_gain_mB = 0; min_gain_mB = -10000; step_gain_mB = VOL_STEP_mB; } err = hpi_meter_query_channels(h_control, &count); if (err) count = HPI_MAX_CHANNELS; uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = count; uinfo->value.integer.min = min_gain_mB / VOL_STEP_mB; uinfo->value.integer.max = max_gain_mB / VOL_STEP_mB; uinfo->value.integer.step = step_gain_mB / VOL_STEP_mB; return 0; } static int snd_asihpi_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; short an_gain_mB[HPI_MAX_CHANNELS]; hpi_handle_error(hpi_volume_get_gain(h_control, an_gain_mB)); ucontrol->value.integer.value[0] = an_gain_mB[0] / VOL_STEP_mB; ucontrol->value.integer.value[1] = an_gain_mB[1] / VOL_STEP_mB; return 0; } static int snd_asihpi_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; short an_gain_mB[HPI_MAX_CHANNELS]; an_gain_mB[0] = (ucontrol->value.integer.value[0]) * VOL_STEP_mB; an_gain_mB[1] = (ucontrol->value.integer.value[1]) * VOL_STEP_mB; /* change = asihpi->mixer_volume[addr][0] != left || asihpi->mixer_volume[addr][1] != right; */ hpi_handle_error(hpi_volume_set_gain(h_control, an_gain_mB)); return 1; } static const DECLARE_TLV_DB_SCALE(db_scale_100, -10000, VOL_STEP_mB, 0); #define snd_asihpi_volume_mute_info snd_ctl_boolean_mono_info static int snd_asihpi_volume_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u32 mute; hpi_handle_error(hpi_volume_get_mute(h_control, &mute)); ucontrol->value.integer.value[0] = mute ? 0 : 1; return 0; } static int snd_asihpi_volume_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; /* HPI currently only supports all or none muting of multichannel volume ALSA Switch element has opposite sense to HPI mute: on==unmuted, off=muted */ int mute = ucontrol->value.integer.value[0] ? 0 : HPI_BITMASK_ALL_CHANNELS; hpi_handle_error(hpi_volume_set_mute(h_control, mute)); return 1; } static int snd_asihpi_volume_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; int err; u32 mute; asihpi_ctl_init(&snd_control, hpi_ctl, "Volume"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ; snd_control.info = snd_asihpi_volume_info; snd_control.get = snd_asihpi_volume_get; snd_control.put = snd_asihpi_volume_put; snd_control.tlv.p = db_scale_100; err = ctl_add(card, &snd_control, asihpi); if (err) return err; if (hpi_volume_get_mute(hpi_ctl->h_control, &mute) == 0) { asihpi_ctl_init(&snd_control, hpi_ctl, "Switch"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; snd_control.info = snd_asihpi_volume_mute_info; snd_control.get = snd_asihpi_volume_mute_get; snd_control.put = snd_asihpi_volume_mute_put; err = ctl_add(card, &snd_control, asihpi); } return err; } /*------------------------------------------------------------ Level controls ------------------------------------------------------------*/ static int snd_asihpi_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u32 h_control = kcontrol->private_value; u16 err; short min_gain_mB; short max_gain_mB; short step_gain_mB; err = hpi_level_query_range(h_control, &min_gain_mB, &max_gain_mB, &step_gain_mB); if (err) { max_gain_mB = 2400; min_gain_mB = -1000; step_gain_mB = 100; } uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = min_gain_mB / HPI_UNITS_PER_dB; uinfo->value.integer.max = max_gain_mB / HPI_UNITS_PER_dB; uinfo->value.integer.step = step_gain_mB / HPI_UNITS_PER_dB; return 0; } static int snd_asihpi_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; short an_gain_mB[HPI_MAX_CHANNELS]; hpi_handle_error(hpi_level_get_gain(h_control, an_gain_mB)); ucontrol->value.integer.value[0] = an_gain_mB[0] / HPI_UNITS_PER_dB; ucontrol->value.integer.value[1] = an_gain_mB[1] / HPI_UNITS_PER_dB; return 0; } static int snd_asihpi_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int change; u32 h_control = kcontrol->private_value; short an_gain_mB[HPI_MAX_CHANNELS]; an_gain_mB[0] = (ucontrol->value.integer.value[0]) * HPI_UNITS_PER_dB; an_gain_mB[1] = (ucontrol->value.integer.value[1]) * HPI_UNITS_PER_dB; /* change = asihpi->mixer_level[addr][0] != left || asihpi->mixer_level[addr][1] != right; */ change = 1; hpi_handle_error(hpi_level_set_gain(h_control, an_gain_mB)); return change; } static const DECLARE_TLV_DB_SCALE(db_scale_level, -1000, 100, 0); static int snd_asihpi_level_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; /* can't use 'volume' cos some nodes have volume as well */ asihpi_ctl_init(&snd_control, hpi_ctl, "Level"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ; snd_control.info = snd_asihpi_level_info; snd_control.get = snd_asihpi_level_get; snd_control.put = snd_asihpi_level_put; snd_control.tlv.p = db_scale_level; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ AESEBU controls ------------------------------------------------------------*/ /* AESEBU format */ static const char * const asihpi_aesebu_format_names[] = { "N/A", "S/PDIF", "AES/EBU" }; static int snd_asihpi_aesebu_format_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { return snd_ctl_enum_info(uinfo, 1, 3, asihpi_aesebu_format_names); } static int snd_asihpi_aesebu_format_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol, u16 (*func)(u32, u16 *)) { u32 h_control = kcontrol->private_value; u16 source, err; err = func(h_control, &source); /* default to N/A */ ucontrol->value.enumerated.item[0] = 0; /* return success but set the control to N/A */ if (err) return 0; if (source == HPI_AESEBU_FORMAT_SPDIF) ucontrol->value.enumerated.item[0] = 1; if (source == HPI_AESEBU_FORMAT_AESEBU) ucontrol->value.enumerated.item[0] = 2; return 0; } static int snd_asihpi_aesebu_format_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol, u16 (*func)(u32, u16)) { u32 h_control = kcontrol->private_value; /* default to S/PDIF */ u16 source = HPI_AESEBU_FORMAT_SPDIF; if (ucontrol->value.enumerated.item[0] == 1) source = HPI_AESEBU_FORMAT_SPDIF; if (ucontrol->value.enumerated.item[0] == 2) source = HPI_AESEBU_FORMAT_AESEBU; if (func(h_control, source) != 0) return -EINVAL; return 1; } static int snd_asihpi_aesebu_rx_format_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { return snd_asihpi_aesebu_format_get(kcontrol, ucontrol, hpi_aesebu_receiver_get_format); } static int snd_asihpi_aesebu_rx_format_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { return snd_asihpi_aesebu_format_put(kcontrol, ucontrol, hpi_aesebu_receiver_set_format); } static int snd_asihpi_aesebu_rxstatus_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 0X1F; uinfo->value.integer.step = 1; return 0; } static int snd_asihpi_aesebu_rxstatus_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u16 status; hpi_handle_error(hpi_aesebu_receiver_get_error_status( h_control, &status)); ucontrol->value.integer.value[0] = status; return 0; } static int snd_asihpi_aesebu_rx_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; asihpi_ctl_init(&snd_control, hpi_ctl, "Format"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; snd_control.info = snd_asihpi_aesebu_format_info; snd_control.get = snd_asihpi_aesebu_rx_format_get; snd_control.put = snd_asihpi_aesebu_rx_format_put; if (ctl_add(card, &snd_control, asihpi) < 0) return -EINVAL; asihpi_ctl_init(&snd_control, hpi_ctl, "Status"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_VOLATILE | SNDRV_CTL_ELEM_ACCESS_READ; snd_control.info = snd_asihpi_aesebu_rxstatus_info; snd_control.get = snd_asihpi_aesebu_rxstatus_get; return ctl_add(card, &snd_control, asihpi); } static int snd_asihpi_aesebu_tx_format_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { return snd_asihpi_aesebu_format_get(kcontrol, ucontrol, hpi_aesebu_transmitter_get_format); } static int snd_asihpi_aesebu_tx_format_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { return snd_asihpi_aesebu_format_put(kcontrol, ucontrol, hpi_aesebu_transmitter_set_format); } static int snd_asihpi_aesebu_tx_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; asihpi_ctl_init(&snd_control, hpi_ctl, "Format"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; snd_control.info = snd_asihpi_aesebu_format_info; snd_control.get = snd_asihpi_aesebu_tx_format_get; snd_control.put = snd_asihpi_aesebu_tx_format_put; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Tuner controls ------------------------------------------------------------*/ /* Gain */ static int snd_asihpi_tuner_gain_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u32 h_control = kcontrol->private_value; u16 err; short idx; u16 gain_range[3]; for (idx = 0; idx < 3; idx++) { err = hpi_tuner_query_gain(h_control, idx, &gain_range[idx]); if (err != 0) return err; } uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = ((int)gain_range[0]) / HPI_UNITS_PER_dB; uinfo->value.integer.max = ((int)gain_range[1]) / HPI_UNITS_PER_dB; uinfo->value.integer.step = ((int) gain_range[2]) / HPI_UNITS_PER_dB; return 0; } static int snd_asihpi_tuner_gain_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* struct snd_card_asihpi *asihpi = snd_kcontrol_chip(kcontrol); */ u32 h_control = kcontrol->private_value; short gain; hpi_handle_error(hpi_tuner_get_gain(h_control, &gain)); ucontrol->value.integer.value[0] = gain / HPI_UNITS_PER_dB; return 0; } static int snd_asihpi_tuner_gain_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* struct snd_card_asihpi *asihpi = snd_kcontrol_chip(kcontrol); */ u32 h_control = kcontrol->private_value; short gain; gain = (ucontrol->value.integer.value[0]) * HPI_UNITS_PER_dB; hpi_handle_error(hpi_tuner_set_gain(h_control, gain)); return 1; } /* Band */ static int asihpi_tuner_band_query(struct snd_kcontrol *kcontrol, u16 *band_list, u32 len) { u32 h_control = kcontrol->private_value; u16 err = 0; u32 i; for (i = 0; i < len; i++) { err = hpi_tuner_query_band( h_control, i, &band_list[i]); if (err != 0) break; } if (err && (err != HPI_ERROR_INVALID_OBJ_INDEX)) return -EIO; return i; } static int snd_asihpi_tuner_band_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u16 tuner_bands[HPI_TUNER_BAND_LAST]; int num_bands = 0; num_bands = asihpi_tuner_band_query(kcontrol, tuner_bands, HPI_TUNER_BAND_LAST); if (num_bands < 0) return num_bands; return snd_ctl_enum_info(uinfo, 1, num_bands, asihpi_tuner_band_names); } static int snd_asihpi_tuner_band_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; /* struct snd_card_asihpi *asihpi = snd_kcontrol_chip(kcontrol); */ u16 band, idx; u16 tuner_bands[HPI_TUNER_BAND_LAST]; __always_unused u32 num_bands; num_bands = asihpi_tuner_band_query(kcontrol, tuner_bands, HPI_TUNER_BAND_LAST); hpi_handle_error(hpi_tuner_get_band(h_control, &band)); ucontrol->value.enumerated.item[0] = -1; for (idx = 0; idx < HPI_TUNER_BAND_LAST; idx++) if (tuner_bands[idx] == band) { ucontrol->value.enumerated.item[0] = idx; break; } return 0; } static int snd_asihpi_tuner_band_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* struct snd_card_asihpi *asihpi = snd_kcontrol_chip(kcontrol); */ u32 h_control = kcontrol->private_value; unsigned int idx; u16 band; u16 tuner_bands[HPI_TUNER_BAND_LAST]; __always_unused u32 num_bands; num_bands = asihpi_tuner_band_query(kcontrol, tuner_bands, HPI_TUNER_BAND_LAST); idx = ucontrol->value.enumerated.item[0]; if (idx >= ARRAY_SIZE(tuner_bands)) idx = ARRAY_SIZE(tuner_bands) - 1; band = tuner_bands[idx]; hpi_handle_error(hpi_tuner_set_band(h_control, band)); return 1; } /* Freq */ static int snd_asihpi_tuner_freq_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u32 h_control = kcontrol->private_value; u16 err; u16 tuner_bands[HPI_TUNER_BAND_LAST]; u16 num_bands = 0, band_iter, idx; u32 freq_range[3], temp_freq_range[3]; num_bands = asihpi_tuner_band_query(kcontrol, tuner_bands, HPI_TUNER_BAND_LAST); freq_range[0] = INT_MAX; freq_range[1] = 0; freq_range[2] = INT_MAX; for (band_iter = 0; band_iter < num_bands; band_iter++) { for (idx = 0; idx < 3; idx++) { err = hpi_tuner_query_frequency(h_control, idx, tuner_bands[band_iter], &temp_freq_range[idx]); if (err != 0) return err; } /* skip band with bogus stepping */ if (temp_freq_range[2] <= 0) continue; if (temp_freq_range[0] < freq_range[0]) freq_range[0] = temp_freq_range[0]; if (temp_freq_range[1] > freq_range[1]) freq_range[1] = temp_freq_range[1]; if (temp_freq_range[2] < freq_range[2]) freq_range[2] = temp_freq_range[2]; } uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = ((int)freq_range[0]); uinfo->value.integer.max = ((int)freq_range[1]); uinfo->value.integer.step = ((int)freq_range[2]); return 0; } static int snd_asihpi_tuner_freq_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u32 freq; hpi_handle_error(hpi_tuner_get_frequency(h_control, &freq)); ucontrol->value.integer.value[0] = freq; return 0; } static int snd_asihpi_tuner_freq_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u32 freq; freq = ucontrol->value.integer.value[0]; hpi_handle_error(hpi_tuner_set_frequency(h_control, freq)); return 1; } /* Tuner control group initializer */ static int snd_asihpi_tuner_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; snd_control.private_value = hpi_ctl->h_control; snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; if (!hpi_tuner_get_gain(hpi_ctl->h_control, NULL)) { asihpi_ctl_init(&snd_control, hpi_ctl, "Gain"); snd_control.info = snd_asihpi_tuner_gain_info; snd_control.get = snd_asihpi_tuner_gain_get; snd_control.put = snd_asihpi_tuner_gain_put; if (ctl_add(card, &snd_control, asihpi) < 0) return -EINVAL; } asihpi_ctl_init(&snd_control, hpi_ctl, "Band"); snd_control.info = snd_asihpi_tuner_band_info; snd_control.get = snd_asihpi_tuner_band_get; snd_control.put = snd_asihpi_tuner_band_put; if (ctl_add(card, &snd_control, asihpi) < 0) return -EINVAL; asihpi_ctl_init(&snd_control, hpi_ctl, "Freq"); snd_control.info = snd_asihpi_tuner_freq_info; snd_control.get = snd_asihpi_tuner_freq_get; snd_control.put = snd_asihpi_tuner_freq_put; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Meter controls ------------------------------------------------------------*/ static int snd_asihpi_meter_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u32 h_control = kcontrol->private_value; u32 count; u16 err; err = hpi_meter_query_channels(h_control, &count); if (err) count = HPI_MAX_CHANNELS; uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = count; uinfo->value.integer.min = 0; uinfo->value.integer.max = 0x7FFFFFFF; return 0; } /* linear values for 10dB steps */ static const int log2lin[] = { 0x7FFFFFFF, /* 0dB */ 679093956, 214748365, 67909396, 21474837, 6790940, 2147484, /* -60dB */ 679094, 214748, /* -80 */ 67909, 21475, /* -100 */ 6791, 2147, 679, 214, 68, 21, 7, 2 }; static int snd_asihpi_meter_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; short an_gain_mB[HPI_MAX_CHANNELS], i; u16 err; err = hpi_meter_get_peak(h_control, an_gain_mB); for (i = 0; i < HPI_MAX_CHANNELS; i++) { if (err) { ucontrol->value.integer.value[i] = 0; } else if (an_gain_mB[i] >= 0) { ucontrol->value.integer.value[i] = an_gain_mB[i] << 16; } else { /* -ve is log value in millibels < -60dB, * convert to (roughly!) linear, */ ucontrol->value.integer.value[i] = log2lin[an_gain_mB[i] / -1000]; } } return 0; } static int snd_asihpi_meter_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl, int subidx) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; asihpi_ctl_init(&snd_control, hpi_ctl, "Meter"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_VOLATILE | SNDRV_CTL_ELEM_ACCESS_READ; snd_control.info = snd_asihpi_meter_info; snd_control.get = snd_asihpi_meter_get; snd_control.index = subidx; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Multiplexer controls ------------------------------------------------------------*/ static int snd_card_asihpi_mux_count_sources(struct snd_kcontrol *snd_control) { u32 h_control = snd_control->private_value; struct hpi_control hpi_ctl; int s, err; for (s = 0; s < 32; s++) { err = hpi_multiplexer_query_source(h_control, s, &hpi_ctl. src_node_type, &hpi_ctl. src_node_index); if (err) break; } return s; } static int snd_asihpi_mux_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { u16 src_node_type, src_node_index; u32 h_control = kcontrol->private_value; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = snd_card_asihpi_mux_count_sources(kcontrol); if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; hpi_multiplexer_query_source(h_control, uinfo->value.enumerated.item, &src_node_type, &src_node_index); sprintf(uinfo->value.enumerated.name, "%s %d", asihpi_src_names[src_node_type - HPI_SOURCENODE_NONE], src_node_index); return 0; } static int snd_asihpi_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u16 source_type, source_index; u16 src_node_type, src_node_index; int s; hpi_handle_error(hpi_multiplexer_get_source(h_control, &source_type, &source_index)); /* Should cache this search result! */ for (s = 0; s < 256; s++) { if (hpi_multiplexer_query_source(h_control, s, &src_node_type, &src_node_index)) break; if ((source_type == src_node_type) && (source_index == src_node_index)) { ucontrol->value.enumerated.item[0] = s; return 0; } } snd_printd(KERN_WARNING "Control %x failed to match mux source %hu %hu\n", h_control, source_type, source_index); ucontrol->value.enumerated.item[0] = 0; return 0; } static int snd_asihpi_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int change; u32 h_control = kcontrol->private_value; u16 source_type, source_index; u16 e; change = 1; e = hpi_multiplexer_query_source(h_control, ucontrol->value.enumerated.item[0], &source_type, &source_index); if (!e) hpi_handle_error( hpi_multiplexer_set_source(h_control, source_type, source_index)); return change; } static int snd_asihpi_mux_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; asihpi_ctl_init(&snd_control, hpi_ctl, "Route"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; snd_control.info = snd_asihpi_mux_info; snd_control.get = snd_asihpi_mux_get; snd_control.put = snd_asihpi_mux_put; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Channel mode controls ------------------------------------------------------------*/ static int snd_asihpi_cmode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char * const mode_names[HPI_CHANNEL_MODE_LAST + 1] = { "invalid", "Normal", "Swap", "From Left", "From Right", "To Left", "To Right" }; u32 h_control = kcontrol->private_value; u16 mode; int i; const char *mapped_names[6]; int valid_modes = 0; /* HPI channel mode values can be from 1 to 6 Some adapters only support a contiguous subset */ for (i = 0; i < HPI_CHANNEL_MODE_LAST; i++) if (!hpi_channel_mode_query_mode( h_control, i, &mode)) { mapped_names[valid_modes] = mode_names[mode]; valid_modes++; } if (!valid_modes) return -EINVAL; return snd_ctl_enum_info(uinfo, 1, valid_modes, mapped_names); } static int snd_asihpi_cmode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u16 mode; if (hpi_channel_mode_get(h_control, &mode)) mode = 1; ucontrol->value.enumerated.item[0] = mode - 1; return 0; } static int snd_asihpi_cmode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int change; u32 h_control = kcontrol->private_value; change = 1; hpi_handle_error(hpi_channel_mode_set(h_control, ucontrol->value.enumerated.item[0] + 1)); return change; } static int snd_asihpi_cmode_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card = asihpi->card; struct snd_kcontrol_new snd_control; asihpi_ctl_init(&snd_control, hpi_ctl, "Mode"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE; snd_control.info = snd_asihpi_cmode_info; snd_control.get = snd_asihpi_cmode_get; snd_control.put = snd_asihpi_cmode_put; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Sampleclock source controls ------------------------------------------------------------*/ static const char * const sampleclock_sources[] = { "N/A", "Local PLL", "Digital Sync", "Word External", "Word Header", "SMPTE", "Digital1", "Auto", "Network", "Invalid", "Prev Module", "BLU-Link", "Digital2", "Digital3", "Digital4", "Digital5", "Digital6", "Digital7", "Digital8"}; /* Number of strings must match expected enumerated values */ compile_time_assert( (ARRAY_SIZE(sampleclock_sources) == MAX_CLOCKSOURCES), assert_sampleclock_sources_size); static int snd_asihpi_clksrc_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct snd_card_asihpi *asihpi = (struct snd_card_asihpi *)(kcontrol->private_data); struct clk_cache *clkcache = &asihpi->cc; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = clkcache->count; if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; strcpy(uinfo->value.enumerated.name, clkcache->s[uinfo->value.enumerated.item].name); return 0; } static int snd_asihpi_clksrc_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_card_asihpi *asihpi = (struct snd_card_asihpi *)(kcontrol->private_data); struct clk_cache *clkcache = &asihpi->cc; u32 h_control = kcontrol->private_value; u16 source, srcindex = 0; int i; ucontrol->value.enumerated.item[0] = 0; if (hpi_sample_clock_get_source(h_control, &source)) source = 0; if (source == HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT) if (hpi_sample_clock_get_source_index(h_control, &srcindex)) srcindex = 0; for (i = 0; i < clkcache->count; i++) if ((clkcache->s[i].source == source) && (clkcache->s[i].index == srcindex)) break; ucontrol->value.enumerated.item[0] = i; return 0; } static int snd_asihpi_clksrc_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_card_asihpi *asihpi = (struct snd_card_asihpi *)(kcontrol->private_data); struct clk_cache *clkcache = &asihpi->cc; unsigned int item; int change; u32 h_control = kcontrol->private_value; change = 1; item = ucontrol->value.enumerated.item[0]; if (item >= clkcache->count) item = clkcache->count-1; hpi_handle_error(hpi_sample_clock_set_source( h_control, clkcache->s[item].source)); if (clkcache->s[item].source == HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT) hpi_handle_error(hpi_sample_clock_set_source_index( h_control, clkcache->s[item].index)); return change; } /*------------------------------------------------------------ Clkrate controls ------------------------------------------------------------*/ /* Need to change this to enumerated control with list of rates */ static int snd_asihpi_clklocal_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 8000; uinfo->value.integer.max = 192000; uinfo->value.integer.step = 100; return 0; } static int snd_asihpi_clklocal_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u32 rate; u16 e; e = hpi_sample_clock_get_local_rate(h_control, &rate); if (!e) ucontrol->value.integer.value[0] = rate; else ucontrol->value.integer.value[0] = 0; return 0; } static int snd_asihpi_clklocal_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int change; u32 h_control = kcontrol->private_value; /* change = asihpi->mixer_clkrate[addr][0] != left || asihpi->mixer_clkrate[addr][1] != right; */ change = 1; hpi_handle_error(hpi_sample_clock_set_local_rate(h_control, ucontrol->value.integer.value[0])); return change; } static int snd_asihpi_clkrate_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 8000; uinfo->value.integer.max = 192000; uinfo->value.integer.step = 100; return 0; } static int snd_asihpi_clkrate_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u32 h_control = kcontrol->private_value; u32 rate; u16 e; e = hpi_sample_clock_get_sample_rate(h_control, &rate); if (!e) ucontrol->value.integer.value[0] = rate; else ucontrol->value.integer.value[0] = 0; return 0; } static int snd_asihpi_sampleclock_add(struct snd_card_asihpi *asihpi, struct hpi_control *hpi_ctl) { struct snd_card *card; struct snd_kcontrol_new snd_control; struct clk_cache *clkcache; u32 hSC = hpi_ctl->h_control; int has_aes_in = 0; int i, j; u16 source; if (snd_BUG_ON(!asihpi)) return -EINVAL; card = asihpi->card; clkcache = &asihpi->cc; snd_control.private_value = hpi_ctl->h_control; clkcache->has_local = 0; for (i = 0; i <= HPI_SAMPLECLOCK_SOURCE_LAST; i++) { if (hpi_sample_clock_query_source(hSC, i, &source)) break; clkcache->s[i].source = source; clkcache->s[i].index = 0; clkcache->s[i].name = sampleclock_sources[source]; if (source == HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT) has_aes_in = 1; if (source == HPI_SAMPLECLOCK_SOURCE_LOCAL) clkcache->has_local = 1; } if (has_aes_in) /* already will have picked up index 0 above */ for (j = 1; j < 8; j++) { if (hpi_sample_clock_query_source_index(hSC, j, HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT, &source)) break; clkcache->s[i].source = HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT; clkcache->s[i].index = j; clkcache->s[i].name = sampleclock_sources[ j+HPI_SAMPLECLOCK_SOURCE_LAST]; i++; } clkcache->count = i; asihpi_ctl_init(&snd_control, hpi_ctl, "Source"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE ; snd_control.info = snd_asihpi_clksrc_info; snd_control.get = snd_asihpi_clksrc_get; snd_control.put = snd_asihpi_clksrc_put; if (ctl_add(card, &snd_control, asihpi) < 0) return -EINVAL; if (clkcache->has_local) { asihpi_ctl_init(&snd_control, hpi_ctl, "Localrate"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_READWRITE ; snd_control.info = snd_asihpi_clklocal_info; snd_control.get = snd_asihpi_clklocal_get; snd_control.put = snd_asihpi_clklocal_put; if (ctl_add(card, &snd_control, asihpi) < 0) return -EINVAL; } asihpi_ctl_init(&snd_control, hpi_ctl, "Rate"); snd_control.access = SNDRV_CTL_ELEM_ACCESS_VOLATILE | SNDRV_CTL_ELEM_ACCESS_READ; snd_control.info = snd_asihpi_clkrate_info; snd_control.get = snd_asihpi_clkrate_get; return ctl_add(card, &snd_control, asihpi); } /*------------------------------------------------------------ Mixer ------------------------------------------------------------*/ static int snd_card_asihpi_mixer_new(struct snd_card_asihpi *asihpi) { struct snd_card *card; unsigned int idx = 0; unsigned int subindex = 0; int err; struct hpi_control hpi_ctl, prev_ctl; if (snd_BUG_ON(!asihpi)) return -EINVAL; card = asihpi->card; strcpy(card->mixername, "Asihpi Mixer"); err = hpi_mixer_open(asihpi->hpi->adapter->index, &asihpi->h_mixer); hpi_handle_error(err); if (err) return -err; memset(&prev_ctl, 0, sizeof(prev_ctl)); prev_ctl.control_type = -1; for (idx = 0; idx < 2000; idx++) { err = hpi_mixer_get_control_by_index( asihpi->h_mixer, idx, &hpi_ctl.src_node_type, &hpi_ctl.src_node_index, &hpi_ctl.dst_node_type, &hpi_ctl.dst_node_index, &hpi_ctl.control_type, &hpi_ctl.h_control); if (err) { if (err == HPI_ERROR_CONTROL_DISABLED) { if (mixer_dump) dev_info(&asihpi->pci->dev, "Disabled HPI Control(%d)\n", idx); continue; } else break; } hpi_ctl.src_node_type -= HPI_SOURCENODE_NONE; hpi_ctl.dst_node_type -= HPI_DESTNODE_NONE; /* ASI50xx in SSX mode has multiple meters on the same node. Use subindex to create distinct ALSA controls for any duplicated controls. */ if ((hpi_ctl.control_type == prev_ctl.control_type) && (hpi_ctl.src_node_type == prev_ctl.src_node_type) && (hpi_ctl.src_node_index == prev_ctl.src_node_index) && (hpi_ctl.dst_node_type == prev_ctl.dst_node_type) && (hpi_ctl.dst_node_index == prev_ctl.dst_node_index)) subindex++; else subindex = 0; prev_ctl = hpi_ctl; switch (hpi_ctl.control_type) { case HPI_CONTROL_VOLUME: err = snd_asihpi_volume_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_LEVEL: err = snd_asihpi_level_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_MULTIPLEXER: err = snd_asihpi_mux_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_CHANNEL_MODE: err = snd_asihpi_cmode_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_METER: err = snd_asihpi_meter_add(asihpi, &hpi_ctl, subindex); break; case HPI_CONTROL_SAMPLECLOCK: err = snd_asihpi_sampleclock_add( asihpi, &hpi_ctl); break; case HPI_CONTROL_CONNECTION: /* ignore these */ continue; case HPI_CONTROL_TUNER: err = snd_asihpi_tuner_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_AESEBU_TRANSMITTER: err = snd_asihpi_aesebu_tx_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_AESEBU_RECEIVER: err = snd_asihpi_aesebu_rx_add(asihpi, &hpi_ctl); break; case HPI_CONTROL_VOX: case HPI_CONTROL_BITSTREAM: case HPI_CONTROL_MICROPHONE: case HPI_CONTROL_PARAMETRIC_EQ: case HPI_CONTROL_COMPANDER: default: if (mixer_dump) dev_info(&asihpi->pci->dev, "Untranslated HPI Control (%d) %d %d %d %d %d\n", idx, hpi_ctl.control_type, hpi_ctl.src_node_type, hpi_ctl.src_node_index, hpi_ctl.dst_node_type, hpi_ctl.dst_node_index); continue; } if (err < 0) return err; } if (HPI_ERROR_INVALID_OBJ_INDEX != err) hpi_handle_error(err); dev_info(&asihpi->pci->dev, "%d mixer controls found\n", idx); return 0; } /*------------------------------------------------------------ /proc interface ------------------------------------------------------------*/ static void snd_asihpi_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_card_asihpi *asihpi = entry->private_data; u32 h_control; u32 rate = 0; u16 source = 0; u16 num_outstreams; u16 num_instreams; u16 version; u32 serial_number; u16 type; int err; snd_iprintf(buffer, "ASIHPI driver proc file\n"); hpi_handle_error(hpi_adapter_get_info(asihpi->hpi->adapter->index, &num_outstreams, &num_instreams, &version, &serial_number, &type)); snd_iprintf(buffer, "Adapter type ASI%4X\nHardware Index %d\n" "%d outstreams\n%d instreams\n", type, asihpi->hpi->adapter->index, num_outstreams, num_instreams); snd_iprintf(buffer, "Serial#%d\nHardware version %c%d\nDSP code version %03d\n", serial_number, ((version >> 3) & 0xf) + 'A', version & 0x7, ((version >> 13) * 100) + ((version >> 7) & 0x3f)); err = hpi_mixer_get_control(asihpi->h_mixer, HPI_SOURCENODE_CLOCK_SOURCE, 0, 0, 0, HPI_CONTROL_SAMPLECLOCK, &h_control); if (!err) { err = hpi_sample_clock_get_sample_rate(h_control, &rate); err += hpi_sample_clock_get_source(h_control, &source); if (!err) snd_iprintf(buffer, "Sample Clock %dHz, source %s\n", rate, sampleclock_sources[source]); } } static void snd_asihpi_proc_init(struct snd_card_asihpi *asihpi) { snd_card_ro_proc_new(asihpi->card, "info", asihpi, snd_asihpi_proc_read); } /*------------------------------------------------------------ HWDEP ------------------------------------------------------------*/ static int snd_asihpi_hpi_open(struct snd_hwdep *hw, struct file *file) { if (enable_hpi_hwdep) return 0; else return -ENODEV; } static int snd_asihpi_hpi_release(struct snd_hwdep *hw, struct file *file) { if (enable_hpi_hwdep) return asihpi_hpi_release(file); else return -ENODEV; } static int snd_asihpi_hpi_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) { if (enable_hpi_hwdep) return asihpi_hpi_ioctl(file, cmd, arg); else return -ENODEV; } /* results in /dev/snd/hwC#D0 file for each card with index # also /proc/asound/hwdep will contain '#-00: asihpi (HPI) for each card' */ static int snd_asihpi_hpi_new(struct snd_card_asihpi *asihpi, int device) { struct snd_hwdep *hw; int err; err = snd_hwdep_new(asihpi->card, "HPI", device, &hw); if (err < 0) return err; strcpy(hw->name, "asihpi (HPI)"); hw->iface = SNDRV_HWDEP_IFACE_LAST; hw->ops.open = snd_asihpi_hpi_open; hw->ops.ioctl = snd_asihpi_hpi_ioctl; hw->ops.release = snd_asihpi_hpi_release; hw->private_data = asihpi; return 0; } /*------------------------------------------------------------ CARD ------------------------------------------------------------*/ static int snd_asihpi_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id) { int err; struct hpi_adapter *hpi; struct snd_card *card; struct snd_card_asihpi *asihpi; u32 h_control; u32 h_stream; u32 adapter_index; static int dev; if (dev >= SNDRV_CARDS) return -ENODEV; /* Should this be enable[hpi->index] ? */ if (!enable[dev]) { dev++; return -ENOENT; } /* Initialise low-level HPI driver */ err = asihpi_adapter_probe(pci_dev, pci_id); if (err < 0) return err; hpi = pci_get_drvdata(pci_dev); adapter_index = hpi->adapter->index; /* first try to give the card the same index as its hardware index */ err = snd_card_new(&pci_dev->dev, adapter_index, id[adapter_index], THIS_MODULE, sizeof(struct snd_card_asihpi), &card); if (err < 0) { /* if that fails, try the default index==next available */ err = snd_card_new(&pci_dev->dev, index[dev], id[dev], THIS_MODULE, sizeof(struct snd_card_asihpi), &card); if (err < 0) return err; dev_warn(&pci_dev->dev, "Adapter index %d->ALSA index %d\n", adapter_index, card->number); } asihpi = card->private_data; asihpi->card = card; asihpi->pci = pci_dev; asihpi->hpi = hpi; hpi->snd_card = card; err = hpi_adapter_get_property(adapter_index, HPI_ADAPTER_PROPERTY_CAPS1, NULL, &asihpi->support_grouping); if (err) asihpi->support_grouping = 0; err = hpi_adapter_get_property(adapter_index, HPI_ADAPTER_PROPERTY_CAPS2, &asihpi->support_mrx, NULL); if (err) asihpi->support_mrx = 0; err = hpi_adapter_get_property(adapter_index, HPI_ADAPTER_PROPERTY_INTERVAL, NULL, &asihpi->update_interval_frames); if (err) asihpi->update_interval_frames = 512; if (hpi->interrupt_mode) { asihpi->pcm_start = snd_card_asihpi_pcm_int_start; asihpi->pcm_stop = snd_card_asihpi_pcm_int_stop; hpi->interrupt_callback = snd_card_asihpi_isr; } else { asihpi->pcm_start = snd_card_asihpi_pcm_timer_start; asihpi->pcm_stop = snd_card_asihpi_pcm_timer_stop; } hpi_handle_error(hpi_instream_open(adapter_index, 0, &h_stream)); err = hpi_instream_host_buffer_free(h_stream); asihpi->can_dma = (!err); hpi_handle_error(hpi_instream_close(h_stream)); if (!asihpi->can_dma) asihpi->update_interval_frames *= 2; err = hpi_adapter_get_property(adapter_index, HPI_ADAPTER_PROPERTY_CURCHANNELS, &asihpi->in_max_chans, &asihpi->out_max_chans); if (err) { asihpi->in_max_chans = 2; asihpi->out_max_chans = 2; } if (asihpi->out_max_chans > 2) { /* assume LL mode */ asihpi->out_min_chans = asihpi->out_max_chans; asihpi->in_min_chans = asihpi->in_max_chans; asihpi->support_grouping = 0; } else { asihpi->out_min_chans = 1; asihpi->in_min_chans = 1; } dev_info(&pci_dev->dev, "Has dma:%d, grouping:%d, mrx:%d, uif:%d\n", asihpi->can_dma, asihpi->support_grouping, asihpi->support_mrx, asihpi->update_interval_frames ); err = snd_card_asihpi_pcm_new(asihpi, 0); if (err < 0) { dev_err(&pci_dev->dev, "pcm_new failed\n"); goto __nodev; } err = snd_card_asihpi_mixer_new(asihpi); if (err < 0) { dev_err(&pci_dev->dev, "mixer_new failed\n"); goto __nodev; } err = hpi_mixer_get_control(asihpi->h_mixer, HPI_SOURCENODE_CLOCK_SOURCE, 0, 0, 0, HPI_CONTROL_SAMPLECLOCK, &h_control); if (!err) err = hpi_sample_clock_set_local_rate( h_control, adapter_fs); snd_asihpi_proc_init(asihpi); /* always create, can be enabled or disabled dynamically by enable_hwdep module param*/ snd_asihpi_hpi_new(asihpi, 0); strcpy(card->driver, "ASIHPI"); sprintf(card->shortname, "AudioScience ASI%4X", asihpi->hpi->adapter->type); sprintf(card->longname, "%s %i", card->shortname, adapter_index); err = snd_card_register(card); if (!err) { dev++; return 0; } __nodev: snd_card_free(card); dev_err(&pci_dev->dev, "snd_asihpi_probe error %d\n", err); return err; } static void snd_asihpi_remove(struct pci_dev *pci_dev) { struct hpi_adapter *hpi = pci_get_drvdata(pci_dev); /* Stop interrupts */ if (hpi->interrupt_mode) { hpi->interrupt_callback = NULL; hpi_handle_error(hpi_adapter_set_property(hpi->adapter->index, HPI_ADAPTER_PROPERTY_IRQ_RATE, 0, 0)); } snd_card_free(hpi->snd_card); hpi->snd_card = NULL; asihpi_adapter_remove(pci_dev); } static const struct pci_device_id asihpi_pci_tbl[] = { {HPI_PCI_VENDOR_ID_TI, HPI_PCI_DEV_ID_DSP6205, HPI_PCI_VENDOR_ID_AUDIOSCIENCE, PCI_ANY_ID, 0, 0, (kernel_ulong_t)HPI_6205}, {HPI_PCI_VENDOR_ID_TI, HPI_PCI_DEV_ID_PCI2040, HPI_PCI_VENDOR_ID_AUDIOSCIENCE, PCI_ANY_ID, 0, 0, (kernel_ulong_t)HPI_6000}, {0,} }; MODULE_DEVICE_TABLE(pci, asihpi_pci_tbl); static struct pci_driver driver = { .name = KBUILD_MODNAME, .id_table = asihpi_pci_tbl, .probe = snd_asihpi_probe, .remove = snd_asihpi_remove, }; static int __init snd_asihpi_init(void) { asihpi_init(); return pci_register_driver(&driver); } static void __exit snd_asihpi_exit(void) { pci_unregister_driver(&driver); asihpi_exit(); } module_init(snd_asihpi_init) module_exit(snd_asihpi_exit)
linux-master
sound/pci/asihpi/asihpi.c
// SPDX-License-Identifier: GPL-2.0-only /******************************************************************************* AudioScience HPI driver Common Linux HPI ioctl and module probe/remove functions Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> *******************************************************************************/ #define SOURCEFILE_NAME "hpioctl.c" #include "hpi_internal.h" #include "hpi_version.h" #include "hpimsginit.h" #include "hpidebug.h" #include "hpimsgx.h" #include "hpioctl.h" #include "hpicmn.h" #include <linux/fs.h> #include <linux/interrupt.h> #include <linux/slab.h> #include <linux/moduleparam.h> #include <linux/uaccess.h> #include <linux/pci.h> #include <linux/stringify.h> #include <linux/module.h> #include <linux/vmalloc.h> #include <linux/nospec.h> #ifdef MODULE_FIRMWARE MODULE_FIRMWARE("asihpi/dsp5000.bin"); MODULE_FIRMWARE("asihpi/dsp6200.bin"); MODULE_FIRMWARE("asihpi/dsp6205.bin"); MODULE_FIRMWARE("asihpi/dsp6400.bin"); MODULE_FIRMWARE("asihpi/dsp6600.bin"); MODULE_FIRMWARE("asihpi/dsp8700.bin"); MODULE_FIRMWARE("asihpi/dsp8900.bin"); #endif static int prealloc_stream_buf; module_param(prealloc_stream_buf, int, 0444); MODULE_PARM_DESC(prealloc_stream_buf, "Preallocate size for per-adapter stream buffer"); /* Allow the debug level to be changed after module load. E.g. echo 2 > /sys/module/asihpi/parameters/hpiDebugLevel */ module_param(hpi_debug_level, int, 0644); MODULE_PARM_DESC(hpi_debug_level, "debug verbosity 0..5"); /* List of adapters found */ static struct hpi_adapter adapters[HPI_MAX_ADAPTERS]; /* Wrapper function to HPI_Message to enable dumping of the message and response types. */ static void hpi_send_recv_f(struct hpi_message *phm, struct hpi_response *phr, struct file *file) { if ((phm->adapter_index >= HPI_MAX_ADAPTERS) && (phm->object != HPI_OBJ_SUBSYSTEM)) phr->error = HPI_ERROR_INVALID_OBJ_INDEX; else hpi_send_recv_ex(phm, phr, file); } /* This is called from hpifunc.c functions, called by ALSA * (or other kernel process) In this case there is no file descriptor * available for the message cache code */ void hpi_send_recv(struct hpi_message *phm, struct hpi_response *phr) { hpi_send_recv_f(phm, phr, HOWNER_KERNEL); } EXPORT_SYMBOL(hpi_send_recv); /* for radio-asihpi */ int asihpi_hpi_release(struct file *file) { struct hpi_message hm; struct hpi_response hr; /* HPI_DEBUG_LOG(INFO,"hpi_release file %p, pid %d\n", file, current->pid); */ /* close the subsystem just in case the application forgot to. */ hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_CLOSE); hpi_send_recv_ex(&hm, &hr, file); return 0; } long asihpi_hpi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct hpi_ioctl_linux __user *phpi_ioctl_data; void __user *puhm; void __user *puhr; union hpi_message_buffer_v1 *hm; union hpi_response_buffer_v1 *hr; u16 msg_size; u16 res_max_size; u32 uncopied_bytes; int err = 0; if (cmd != HPI_IOCTL_LINUX) return -EINVAL; hm = kmalloc(sizeof(*hm), GFP_KERNEL); hr = kzalloc(sizeof(*hr), GFP_KERNEL); if (!hm || !hr) { err = -ENOMEM; goto out; } phpi_ioctl_data = (struct hpi_ioctl_linux __user *)arg; /* Read the message and response pointers from user space. */ if (get_user(puhm, &phpi_ioctl_data->phm) || get_user(puhr, &phpi_ioctl_data->phr)) { err = -EFAULT; goto out; } /* Now read the message size and data from user space. */ if (get_user(msg_size, (u16 __user *)puhm)) { err = -EFAULT; goto out; } if (msg_size > sizeof(*hm)) msg_size = sizeof(*hm); /* printk(KERN_INFO "message size %d\n", hm->h.wSize); */ uncopied_bytes = copy_from_user(hm, puhm, msg_size); if (uncopied_bytes) { HPI_DEBUG_LOG(ERROR, "uncopied bytes %d\n", uncopied_bytes); err = -EFAULT; goto out; } /* Override h.size in case it is changed between two userspace fetches */ hm->h.size = msg_size; if (get_user(res_max_size, (u16 __user *)puhr)) { err = -EFAULT; goto out; } /* printk(KERN_INFO "user response size %d\n", res_max_size); */ if (res_max_size < sizeof(struct hpi_response_header)) { HPI_DEBUG_LOG(WARNING, "small res size %d\n", res_max_size); err = -EFAULT; goto out; } res_max_size = min_t(size_t, res_max_size, sizeof(*hr)); switch (hm->h.function) { case HPI_SUBSYS_CREATE_ADAPTER: case HPI_ADAPTER_DELETE: /* Application must not use these functions! */ hr->h.size = sizeof(hr->h); hr->h.error = HPI_ERROR_INVALID_OPERATION; hr->h.function = hm->h.function; uncopied_bytes = copy_to_user(puhr, hr, hr->h.size); if (uncopied_bytes) err = -EFAULT; else err = 0; goto out; } hr->h.size = res_max_size; if (hm->h.object == HPI_OBJ_SUBSYSTEM) { hpi_send_recv_f(&hm->m0, &hr->r0, file); } else { u16 __user *ptr = NULL; u32 size = 0; /* -1=no data 0=read from user mem, 1=write to user mem */ int wrflag = -1; struct hpi_adapter *pa = NULL; if (hm->h.adapter_index < ARRAY_SIZE(adapters)) pa = &adapters[array_index_nospec(hm->h.adapter_index, ARRAY_SIZE(adapters))]; if (!pa || !pa->adapter || !pa->adapter->type) { hpi_init_response(&hr->r0, hm->h.object, hm->h.function, HPI_ERROR_BAD_ADAPTER_NUMBER); uncopied_bytes = copy_to_user(puhr, hr, sizeof(hr->h)); if (uncopied_bytes) err = -EFAULT; else err = 0; goto out; } if (mutex_lock_interruptible(&pa->mutex)) { err = -EINTR; goto out; } /* Dig out any pointers embedded in the message. */ switch (hm->h.function) { case HPI_OSTREAM_WRITE: case HPI_ISTREAM_READ:{ /* Yes, sparse, this is correct. */ ptr = (u16 __user *)hm->m0.u.d.u.data.pb_data; size = hm->m0.u.d.u.data.data_size; /* Allocate buffer according to application request. ?Is it better to alloc/free for the duration of the transaction? */ if (pa->buffer_size < size) { HPI_DEBUG_LOG(DEBUG, "Realloc adapter %d stream " "buffer from %zd to %d\n", hm->h.adapter_index, pa->buffer_size, size); if (pa->p_buffer) { pa->buffer_size = 0; vfree(pa->p_buffer); } pa->p_buffer = vmalloc(size); if (pa->p_buffer) pa->buffer_size = size; else { HPI_DEBUG_LOG(ERROR, "HPI could not allocate " "stream buffer size %d\n", size); mutex_unlock(&pa->mutex); err = -EINVAL; goto out; } } hm->m0.u.d.u.data.pb_data = pa->p_buffer; if (hm->h.function == HPI_ISTREAM_READ) /* from card, WRITE to user mem */ wrflag = 1; else wrflag = 0; break; } default: size = 0; break; } if (size && (wrflag == 0)) { uncopied_bytes = copy_from_user(pa->p_buffer, ptr, size); if (uncopied_bytes) HPI_DEBUG_LOG(WARNING, "Missed %d of %d " "bytes from user\n", uncopied_bytes, size); } hpi_send_recv_f(&hm->m0, &hr->r0, file); if (size && (wrflag == 1)) { uncopied_bytes = copy_to_user(ptr, pa->p_buffer, size); if (uncopied_bytes) HPI_DEBUG_LOG(WARNING, "Missed %d of %d " "bytes to user\n", uncopied_bytes, size); } mutex_unlock(&pa->mutex); } /* on return response size must be set */ /*printk(KERN_INFO "response size %d\n", hr->h.wSize); */ if (!hr->h.size) { HPI_DEBUG_LOG(ERROR, "response zero size\n"); err = -EFAULT; goto out; } if (hr->h.size > res_max_size) { HPI_DEBUG_LOG(ERROR, "response too big %d %d\n", hr->h.size, res_max_size); hr->h.error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; hr->h.specific_error = hr->h.size; hr->h.size = sizeof(hr->h); } uncopied_bytes = copy_to_user(puhr, hr, hr->h.size); if (uncopied_bytes) { HPI_DEBUG_LOG(ERROR, "uncopied bytes %d\n", uncopied_bytes); err = -EFAULT; goto out; } out: kfree(hm); kfree(hr); return err; } static int asihpi_irq_count; static irqreturn_t asihpi_isr(int irq, void *dev_id) { struct hpi_adapter *a = dev_id; int handled; if (!a->adapter->irq_query_and_clear) { pr_err("asihpi_isr ASI%04X:%d no handler\n", a->adapter->type, a->adapter->index); return IRQ_NONE; } handled = a->adapter->irq_query_and_clear(a->adapter, 0); if (!handled) return IRQ_NONE; asihpi_irq_count++; /* printk(KERN_INFO "asihpi_isr %d ASI%04X:%d irq handled\n", asihpi_irq_count, a->adapter->type, a->adapter->index); */ if (a->interrupt_callback) return IRQ_WAKE_THREAD; return IRQ_HANDLED; } static irqreturn_t asihpi_isr_thread(int irq, void *dev_id) { struct hpi_adapter *a = dev_id; if (a->interrupt_callback) a->interrupt_callback(a); return IRQ_HANDLED; } int asihpi_adapter_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id) { int idx, nm, low_latency_mode = 0, irq_supported = 0; int adapter_index; unsigned int memlen; struct hpi_message hm; struct hpi_response hr; struct hpi_adapter adapter; struct hpi_pci pci = { 0 }; memset(&adapter, 0, sizeof(adapter)); dev_printk(KERN_DEBUG, &pci_dev->dev, "probe %04x:%04x,%04x:%04x,%04x\n", pci_dev->vendor, pci_dev->device, pci_dev->subsystem_vendor, pci_dev->subsystem_device, pci_dev->devfn); if (pcim_enable_device(pci_dev) < 0) { dev_err(&pci_dev->dev, "pci_enable_device failed, disabling device\n"); return -EIO; } pci_set_master(pci_dev); /* also sets latency timer if < 16 */ hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_CREATE_ADAPTER); hpi_init_response(&hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_CREATE_ADAPTER, HPI_ERROR_PROCESSING_MESSAGE); hm.adapter_index = HPI_ADAPTER_INDEX_INVALID; nm = HPI_MAX_ADAPTER_MEM_SPACES; for (idx = 0; idx < nm; idx++) { HPI_DEBUG_LOG(INFO, "resource %d %pR\n", idx, &pci_dev->resource[idx]); if (pci_resource_flags(pci_dev, idx) & IORESOURCE_MEM) { memlen = pci_resource_len(pci_dev, idx); pci.ap_mem_base[idx] = ioremap(pci_resource_start(pci_dev, idx), memlen); if (!pci.ap_mem_base[idx]) { HPI_DEBUG_LOG(ERROR, "ioremap failed, aborting\n"); /* unmap previously mapped pci mem space */ goto err; } } } pci.pci_dev = pci_dev; hm.u.s.resource.bus_type = HPI_BUS_PCI; hm.u.s.resource.r.pci = &pci; /* call CreateAdapterObject on the relevant hpi module */ hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); if (hr.error) goto err; adapter_index = hr.u.s.adapter_index; adapter.adapter = hpi_find_adapter(adapter_index); if (prealloc_stream_buf) { adapter.p_buffer = vmalloc(prealloc_stream_buf); if (!adapter.p_buffer) { HPI_DEBUG_LOG(ERROR, "HPI could not allocate " "kernel buffer size %d\n", prealloc_stream_buf); goto err; } } hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_OPEN); hm.adapter_index = adapter.adapter->index; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); if (hr.error) { HPI_DEBUG_LOG(ERROR, "HPI_ADAPTER_OPEN failed, aborting\n"); goto err; } /* Check if current mode == Low Latency mode */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_MODE); hm.adapter_index = adapter.adapter->index; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); if (!hr.error && hr.u.ax.mode.adapter_mode == HPI_ADAPTER_MODE_LOW_LATENCY) low_latency_mode = 1; else dev_info(&pci_dev->dev, "Adapter at index %d is not in low latency mode\n", adapter.adapter->index); /* Check if IRQs are supported */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_PROPERTY); hm.adapter_index = adapter.adapter->index; hm.u.ax.property_set.property = HPI_ADAPTER_PROPERTY_SUPPORTS_IRQ; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); if (hr.error || !hr.u.ax.property_get.parameter1) { dev_info(&pci_dev->dev, "IRQs not supported by adapter at index %d\n", adapter.adapter->index); } else { irq_supported = 1; } /* WARNING can't init mutex in 'adapter' * and then copy it to adapters[] ?!?! */ adapters[adapter_index] = adapter; mutex_init(&adapters[adapter_index].mutex); pci_set_drvdata(pci_dev, &adapters[adapter_index]); if (low_latency_mode && irq_supported) { if (!adapter.adapter->irq_query_and_clear) { dev_err(&pci_dev->dev, "no IRQ handler for adapter %d, aborting\n", adapter.adapter->index); goto err; } /* Disable IRQ generation on DSP side by setting the rate to 0 */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_SET_PROPERTY); hm.adapter_index = adapter.adapter->index; hm.u.ax.property_set.property = HPI_ADAPTER_PROPERTY_IRQ_RATE; hm.u.ax.property_set.parameter1 = 0; hm.u.ax.property_set.parameter2 = 0; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); if (hr.error) { HPI_DEBUG_LOG(ERROR, "HPI_ADAPTER_GET_MODE failed, aborting\n"); goto err; } /* Note: request_irq calls asihpi_isr here */ if (request_threaded_irq(pci_dev->irq, asihpi_isr, asihpi_isr_thread, IRQF_SHARED, "asihpi", &adapters[adapter_index])) { dev_err(&pci_dev->dev, "request_irq(%d) failed\n", pci_dev->irq); goto err; } adapters[adapter_index].interrupt_mode = 1; dev_info(&pci_dev->dev, "using irq %d\n", pci_dev->irq); adapters[adapter_index].irq = pci_dev->irq; } else { dev_info(&pci_dev->dev, "using polled mode\n"); } dev_info(&pci_dev->dev, "probe succeeded for ASI%04X HPI index %d\n", adapter.adapter->type, adapter_index); return 0; err: while (--idx >= 0) { if (pci.ap_mem_base[idx]) { iounmap(pci.ap_mem_base[idx]); pci.ap_mem_base[idx] = NULL; } } if (adapter.p_buffer) { adapter.buffer_size = 0; vfree(adapter.p_buffer); } HPI_DEBUG_LOG(ERROR, "adapter_probe failed\n"); return -ENODEV; } void asihpi_adapter_remove(struct pci_dev *pci_dev) { int idx; struct hpi_message hm; struct hpi_response hr; struct hpi_adapter *pa; struct hpi_pci pci; pa = pci_get_drvdata(pci_dev); pci = pa->adapter->pci; /* Disable IRQ generation on DSP side */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_SET_PROPERTY); hm.adapter_index = pa->adapter->index; hm.u.ax.property_set.property = HPI_ADAPTER_PROPERTY_IRQ_RATE; hm.u.ax.property_set.parameter1 = 0; hm.u.ax.property_set.parameter2 = 0; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_DELETE); hm.adapter_index = pa->adapter->index; hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); /* unmap PCI memory space, mapped during device init. */ for (idx = 0; idx < HPI_MAX_ADAPTER_MEM_SPACES; ++idx) iounmap(pci.ap_mem_base[idx]); if (pa->irq) free_irq(pa->irq, pa); vfree(pa->p_buffer); if (1) dev_info(&pci_dev->dev, "remove %04x:%04x,%04x:%04x,%04x, HPI index %d\n", pci_dev->vendor, pci_dev->device, pci_dev->subsystem_vendor, pci_dev->subsystem_device, pci_dev->devfn, pa->adapter->index); memset(pa, 0, sizeof(*pa)); } void __init asihpi_init(void) { struct hpi_message hm; struct hpi_response hr; memset(adapters, 0, sizeof(adapters)); printk(KERN_INFO "ASIHPI driver " HPI_VER_STRING "\n"); hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_DRIVER_LOAD); hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); } void asihpi_exit(void) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_DRIVER_UNLOAD); hpi_send_recv_ex(&hm, &hr, HOWNER_KERNEL); }
linux-master
sound/pci/asihpi/hpioctl.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> \file hpicmn.c Common functions used by hpixxxx.c modules (C) Copyright AudioScience Inc. 1998-2003 *******************************************************************************/ #define SOURCEFILE_NAME "hpicmn.c" #include "hpi_internal.h" #include "hpidebug.h" #include "hpimsginit.h" #include "hpicmn.h" struct hpi_adapters_list { struct hpios_spinlock list_lock; struct hpi_adapter_obj adapter[HPI_MAX_ADAPTERS]; u16 gw_num_adapters; }; static struct hpi_adapters_list adapters; /** * hpi_validate_response - Given an HPI Message that was sent out and * a response that was received, validate that the response has the * correct fields filled in, i.e ObjectType, Function etc * @phm: message * @phr: response */ u16 hpi_validate_response(struct hpi_message *phm, struct hpi_response *phr) { if (phr->type != HPI_TYPE_RESPONSE) { HPI_DEBUG_LOG(ERROR, "header type %d invalid\n", phr->type); return HPI_ERROR_INVALID_RESPONSE; } if (phr->object != phm->object) { HPI_DEBUG_LOG(ERROR, "header object %d invalid\n", phr->object); return HPI_ERROR_INVALID_RESPONSE; } if (phr->function != phm->function) { HPI_DEBUG_LOG(ERROR, "header function %d invalid\n", phr->function); return HPI_ERROR_INVALID_RESPONSE; } return 0; } u16 hpi_add_adapter(struct hpi_adapter_obj *pao) { u16 retval = 0; /*HPI_ASSERT(pao->type); */ hpios_alistlock_lock(&adapters); if (pao->index >= HPI_MAX_ADAPTERS) { retval = HPI_ERROR_BAD_ADAPTER_NUMBER; goto unlock; } if (adapters.adapter[pao->index].type) { int a; for (a = HPI_MAX_ADAPTERS - 1; a >= 0; a--) { if (!adapters.adapter[a].type) { HPI_DEBUG_LOG(WARNING, "ASI%X duplicate index %d moved to %d\n", pao->type, pao->index, a); pao->index = a; break; } } if (a < 0) { retval = HPI_ERROR_DUPLICATE_ADAPTER_NUMBER; goto unlock; } } adapters.adapter[pao->index] = *pao; hpios_dsplock_init(&adapters.adapter[pao->index]); adapters.gw_num_adapters++; unlock: hpios_alistlock_unlock(&adapters); return retval; } void hpi_delete_adapter(struct hpi_adapter_obj *pao) { if (!pao->type) { HPI_DEBUG_LOG(ERROR, "removing null adapter?\n"); return; } hpios_alistlock_lock(&adapters); if (adapters.adapter[pao->index].type) adapters.gw_num_adapters--; memset(&adapters.adapter[pao->index], 0, sizeof(adapters.adapter[0])); hpios_alistlock_unlock(&adapters); } /** * hpi_find_adapter - FindAdapter returns a pointer to the struct * hpi_adapter_obj with index wAdapterIndex in an HPI_ADAPTERS_LIST * structure. * @adapter_index: value in [0, HPI_MAX_ADAPTERS[ */ struct hpi_adapter_obj *hpi_find_adapter(u16 adapter_index) { struct hpi_adapter_obj *pao = NULL; if (adapter_index >= HPI_MAX_ADAPTERS) { HPI_DEBUG_LOG(VERBOSE, "find_adapter invalid index %d\n", adapter_index); return NULL; } pao = &adapters.adapter[adapter_index]; if (pao->type != 0) { /* HPI_DEBUG_LOG(VERBOSE, "Found adapter index %d\n", wAdapterIndex); */ return pao; } else { /* HPI_DEBUG_LOG(VERBOSE, "No adapter index %d\n", wAdapterIndex); */ return NULL; } } /** * wipe_adapter_list - wipe an HPI_ADAPTERS_LIST structure. * */ static void wipe_adapter_list(void) { memset(&adapters, 0, sizeof(adapters)); } static void subsys_get_adapter(struct hpi_message *phm, struct hpi_response *phr) { int count = phm->obj_index; u16 index = 0; /* find the nCount'th nonzero adapter in array */ for (index = 0; index < HPI_MAX_ADAPTERS; index++) { if (adapters.adapter[index].type) { if (!count) break; count--; } } if (index < HPI_MAX_ADAPTERS) { phr->u.s.adapter_index = adapters.adapter[index].index; phr->u.s.adapter_type = adapters.adapter[index].type; } else { phr->u.s.adapter_index = 0; phr->u.s.adapter_type = 0; phr->error = HPI_ERROR_INVALID_OBJ_INDEX; } } static unsigned int control_cache_alloc_check(struct hpi_control_cache *pC) { unsigned int i; int cached = 0; if (!pC) return 0; if (pC->init) return pC->init; if (!pC->p_cache) return 0; if (pC->control_count && pC->cache_size_in_bytes) { char *p_master_cache; unsigned int byte_count = 0; p_master_cache = (char *)pC->p_cache; HPI_DEBUG_LOG(DEBUG, "check %d controls\n", pC->control_count); for (i = 0; i < pC->control_count; i++) { struct hpi_control_cache_info *info = (struct hpi_control_cache_info *) &p_master_cache[byte_count]; u16 control_index = info->control_index; if (control_index >= pC->control_count) { HPI_DEBUG_LOG(INFO, "adap %d control index %d out of range, cache not ready?\n", pC->adap_idx, control_index); return 0; } if (!info->size_in32bit_words) { if (!i) { HPI_DEBUG_LOG(INFO, "adap %d cache not ready?\n", pC->adap_idx); return 0; } /* The cache is invalid. * Minimum valid entry size is * sizeof(struct hpi_control_cache_info) */ HPI_DEBUG_LOG(ERROR, "adap %d zero size cache entry %d\n", pC->adap_idx, i); break; } if (info->control_type) { pC->p_info[control_index] = info; cached++; } else { /* dummy cache entry */ pC->p_info[control_index] = NULL; } byte_count += info->size_in32bit_words * 4; HPI_DEBUG_LOG(VERBOSE, "cached %d, pinfo %p index %d type %d size %d\n", cached, pC->p_info[info->control_index], info->control_index, info->control_type, info->size_in32bit_words); /* quit loop early if whole cache has been scanned. * dwControlCount is the maximum possible entries * but some may be absent from the cache */ if (byte_count >= pC->cache_size_in_bytes) break; /* have seen last control index */ if (info->control_index == pC->control_count - 1) break; } if (byte_count != pC->cache_size_in_bytes) HPI_DEBUG_LOG(WARNING, "adap %d bytecount %d != cache size %d\n", pC->adap_idx, byte_count, pC->cache_size_in_bytes); else HPI_DEBUG_LOG(DEBUG, "adap %d cache good, bytecount == cache size = %d\n", pC->adap_idx, byte_count); pC->init = (u16)cached; } return pC->init; } /** Find a control. */ static short find_control(u16 control_index, struct hpi_control_cache *p_cache, struct hpi_control_cache_info **pI) { if (!control_cache_alloc_check(p_cache)) { HPI_DEBUG_LOG(VERBOSE, "control_cache_alloc_check() failed %d\n", control_index); return 0; } *pI = p_cache->p_info[control_index]; if (!*pI) { HPI_DEBUG_LOG(VERBOSE, "Uncached Control %d\n", control_index); return 0; } else { HPI_DEBUG_LOG(VERBOSE, "find_control() type %d\n", (*pI)->control_type); } return 1; } /* allow unified treatment of several string fields within struct */ #define HPICMN_PAD_OFS_AND_SIZE(m) {\ offsetof(struct hpi_control_cache_pad, m), \ sizeof(((struct hpi_control_cache_pad *)(NULL))->m) } struct pad_ofs_size { unsigned int offset; unsigned int field_size; }; static const struct pad_ofs_size pad_desc[] = { HPICMN_PAD_OFS_AND_SIZE(c_channel), /* HPI_PAD_CHANNEL_NAME */ HPICMN_PAD_OFS_AND_SIZE(c_artist), /* HPI_PAD_ARTIST */ HPICMN_PAD_OFS_AND_SIZE(c_title), /* HPI_PAD_TITLE */ HPICMN_PAD_OFS_AND_SIZE(c_comment), /* HPI_PAD_COMMENT */ }; /** CheckControlCache checks the cache and fills the struct hpi_response * accordingly. It returns one if a cache hit occurred, zero otherwise. */ short hpi_check_control_cache_single(struct hpi_control_cache_single *pC, struct hpi_message *phm, struct hpi_response *phr) { size_t response_size; short found = 1; /* set the default response size */ response_size = sizeof(struct hpi_response_header) + sizeof(struct hpi_control_res); switch (pC->u.i.control_type) { case HPI_CONTROL_METER: if (phm->u.c.attribute == HPI_METER_PEAK) { phr->u.c.an_log_value[0] = pC->u.meter.an_log_peak[0]; phr->u.c.an_log_value[1] = pC->u.meter.an_log_peak[1]; } else if (phm->u.c.attribute == HPI_METER_RMS) { if (pC->u.meter.an_logRMS[0] == HPI_CACHE_INVALID_SHORT) { phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; phr->u.c.an_log_value[0] = HPI_METER_MINIMUM; phr->u.c.an_log_value[1] = HPI_METER_MINIMUM; } else { phr->u.c.an_log_value[0] = pC->u.meter.an_logRMS[0]; phr->u.c.an_log_value[1] = pC->u.meter.an_logRMS[1]; } } else found = 0; break; case HPI_CONTROL_VOLUME: if (phm->u.c.attribute == HPI_VOLUME_GAIN) { phr->u.c.an_log_value[0] = pC->u.vol.an_log[0]; phr->u.c.an_log_value[1] = pC->u.vol.an_log[1]; } else if (phm->u.c.attribute == HPI_VOLUME_MUTE) { if (pC->u.vol.flags & HPI_VOLUME_FLAG_HAS_MUTE) { if (pC->u.vol.flags & HPI_VOLUME_FLAG_MUTED) phr->u.c.param1 = HPI_BITMASK_ALL_CHANNELS; else phr->u.c.param1 = 0; } else { phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; phr->u.c.param1 = 0; } } else { found = 0; } break; case HPI_CONTROL_MULTIPLEXER: if (phm->u.c.attribute == HPI_MULTIPLEXER_SOURCE) { phr->u.c.param1 = pC->u.mux.source_node_type; phr->u.c.param2 = pC->u.mux.source_node_index; } else { found = 0; } break; case HPI_CONTROL_CHANNEL_MODE: if (phm->u.c.attribute == HPI_CHANNEL_MODE_MODE) phr->u.c.param1 = pC->u.mode.mode; else found = 0; break; case HPI_CONTROL_LEVEL: if (phm->u.c.attribute == HPI_LEVEL_GAIN) { phr->u.c.an_log_value[0] = pC->u.level.an_log[0]; phr->u.c.an_log_value[1] = pC->u.level.an_log[1]; } else found = 0; break; case HPI_CONTROL_TUNER: if (phm->u.c.attribute == HPI_TUNER_FREQ) phr->u.c.param1 = pC->u.tuner.freq_ink_hz; else if (phm->u.c.attribute == HPI_TUNER_BAND) phr->u.c.param1 = pC->u.tuner.band; else if (phm->u.c.attribute == HPI_TUNER_LEVEL_AVG) if (pC->u.tuner.s_level_avg == HPI_CACHE_INVALID_SHORT) { phr->u.cu.tuner.s_level = 0; phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; } else phr->u.cu.tuner.s_level = pC->u.tuner.s_level_avg; else found = 0; break; case HPI_CONTROL_AESEBU_RECEIVER: if (phm->u.c.attribute == HPI_AESEBURX_ERRORSTATUS) phr->u.c.param1 = pC->u.aes3rx.error_status; else if (phm->u.c.attribute == HPI_AESEBURX_FORMAT) phr->u.c.param1 = pC->u.aes3rx.format; else found = 0; break; case HPI_CONTROL_AESEBU_TRANSMITTER: if (phm->u.c.attribute == HPI_AESEBUTX_FORMAT) phr->u.c.param1 = pC->u.aes3tx.format; else found = 0; break; case HPI_CONTROL_TONEDETECTOR: if (phm->u.c.attribute == HPI_TONEDETECTOR_STATE) phr->u.c.param1 = pC->u.tone.state; else found = 0; break; case HPI_CONTROL_SILENCEDETECTOR: if (phm->u.c.attribute == HPI_SILENCEDETECTOR_STATE) { phr->u.c.param1 = pC->u.silence.state; } else found = 0; break; case HPI_CONTROL_MICROPHONE: if (phm->u.c.attribute == HPI_MICROPHONE_PHANTOM_POWER) phr->u.c.param1 = pC->u.microphone.phantom_state; else found = 0; break; case HPI_CONTROL_SAMPLECLOCK: if (phm->u.c.attribute == HPI_SAMPLECLOCK_SOURCE) phr->u.c.param1 = pC->u.clk.source; else if (phm->u.c.attribute == HPI_SAMPLECLOCK_SOURCE_INDEX) { if (pC->u.clk.source_index == HPI_CACHE_INVALID_UINT16) { phr->u.c.param1 = 0; phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; } else phr->u.c.param1 = pC->u.clk.source_index; } else if (phm->u.c.attribute == HPI_SAMPLECLOCK_SAMPLERATE) phr->u.c.param1 = pC->u.clk.sample_rate; else found = 0; break; case HPI_CONTROL_PAD:{ struct hpi_control_cache_pad *p_pad; p_pad = (struct hpi_control_cache_pad *)pC; if (!(p_pad->field_valid_flags & (1 << HPI_CTL_ATTR_INDEX(phm->u.c. attribute)))) { phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; break; } if (phm->u.c.attribute == HPI_PAD_PROGRAM_ID) phr->u.c.param1 = p_pad->pI; else if (phm->u.c.attribute == HPI_PAD_PROGRAM_TYPE) phr->u.c.param1 = p_pad->pTY; else { unsigned int index = HPI_CTL_ATTR_INDEX(phm->u.c. attribute) - 1; unsigned int offset = phm->u.c.param1; unsigned int pad_string_len, field_size; char *pad_string; unsigned int tocopy; if (index > ARRAY_SIZE(pad_desc) - 1) { phr->error = HPI_ERROR_INVALID_CONTROL_ATTRIBUTE; break; } pad_string = ((char *)p_pad) + pad_desc[index].offset; field_size = pad_desc[index].field_size; /* Ensure null terminator */ pad_string[field_size - 1] = 0; pad_string_len = strlen(pad_string) + 1; if (offset > pad_string_len) { phr->error = HPI_ERROR_INVALID_CONTROL_VALUE; break; } tocopy = pad_string_len - offset; if (tocopy > sizeof(phr->u.cu.chars8.sz_data)) tocopy = sizeof(phr->u.cu.chars8. sz_data); memcpy(phr->u.cu.chars8.sz_data, &pad_string[offset], tocopy); phr->u.cu.chars8.remaining_chars = pad_string_len - offset - tocopy; } } break; default: found = 0; break; } HPI_DEBUG_LOG(VERBOSE, "%s Adap %d, Ctl %d, Type %d, Attr %d\n", found ? "Cached" : "Uncached", phm->adapter_index, pC->u.i.control_index, pC->u.i.control_type, phm->u.c.attribute); if (found) { phr->size = (u16)response_size; phr->type = HPI_TYPE_RESPONSE; phr->object = phm->object; phr->function = phm->function; } return found; } short hpi_check_control_cache(struct hpi_control_cache *p_cache, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_control_cache_info *pI; if (!find_control(phm->obj_index, p_cache, &pI)) { HPI_DEBUG_LOG(VERBOSE, "HPICMN find_control() failed for adap %d\n", phm->adapter_index); return 0; } phr->error = 0; phr->specific_error = 0; phr->version = 0; return hpi_check_control_cache_single((struct hpi_control_cache_single *)pI, phm, phr); } /** Updates the cache with Set values. Only update if no error. Volume and Level return the limited values in the response, so use these Multiplexer does so use sent values */ void hpi_cmn_control_cache_sync_to_msg_single(struct hpi_control_cache_single *pC, struct hpi_message *phm, struct hpi_response *phr) { switch (pC->u.i.control_type) { case HPI_CONTROL_VOLUME: if (phm->u.c.attribute == HPI_VOLUME_GAIN) { pC->u.vol.an_log[0] = phr->u.c.an_log_value[0]; pC->u.vol.an_log[1] = phr->u.c.an_log_value[1]; } else if (phm->u.c.attribute == HPI_VOLUME_MUTE) { if (phm->u.c.param1) pC->u.vol.flags |= HPI_VOLUME_FLAG_MUTED; else pC->u.vol.flags &= ~HPI_VOLUME_FLAG_MUTED; } break; case HPI_CONTROL_MULTIPLEXER: /* mux does not return its setting on Set command. */ if (phm->u.c.attribute == HPI_MULTIPLEXER_SOURCE) { pC->u.mux.source_node_type = (u16)phm->u.c.param1; pC->u.mux.source_node_index = (u16)phm->u.c.param2; } break; case HPI_CONTROL_CHANNEL_MODE: /* mode does not return its setting on Set command. */ if (phm->u.c.attribute == HPI_CHANNEL_MODE_MODE) pC->u.mode.mode = (u16)phm->u.c.param1; break; case HPI_CONTROL_LEVEL: if (phm->u.c.attribute == HPI_LEVEL_GAIN) { pC->u.vol.an_log[0] = phr->u.c.an_log_value[0]; pC->u.vol.an_log[1] = phr->u.c.an_log_value[1]; } break; case HPI_CONTROL_MICROPHONE: if (phm->u.c.attribute == HPI_MICROPHONE_PHANTOM_POWER) pC->u.microphone.phantom_state = (u16)phm->u.c.param1; break; case HPI_CONTROL_AESEBU_TRANSMITTER: if (phm->u.c.attribute == HPI_AESEBUTX_FORMAT) pC->u.aes3tx.format = phm->u.c.param1; break; case HPI_CONTROL_AESEBU_RECEIVER: if (phm->u.c.attribute == HPI_AESEBURX_FORMAT) pC->u.aes3rx.format = phm->u.c.param1; break; case HPI_CONTROL_SAMPLECLOCK: if (phm->u.c.attribute == HPI_SAMPLECLOCK_SOURCE) pC->u.clk.source = (u16)phm->u.c.param1; else if (phm->u.c.attribute == HPI_SAMPLECLOCK_SOURCE_INDEX) pC->u.clk.source_index = (u16)phm->u.c.param1; else if (phm->u.c.attribute == HPI_SAMPLECLOCK_SAMPLERATE) pC->u.clk.sample_rate = phm->u.c.param1; break; default: break; } } void hpi_cmn_control_cache_sync_to_msg(struct hpi_control_cache *p_cache, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_control_cache_single *pC; struct hpi_control_cache_info *pI; if (phr->error) return; if (!find_control(phm->obj_index, p_cache, &pI)) { HPI_DEBUG_LOG(VERBOSE, "HPICMN find_control() failed for adap %d\n", phm->adapter_index); return; } /* pC is the default cached control strucure. May be cast to something else in the following switch statement. */ pC = (struct hpi_control_cache_single *)pI; hpi_cmn_control_cache_sync_to_msg_single(pC, phm, phr); } /** Allocate control cache. \return Cache pointer, or NULL if allocation fails. */ struct hpi_control_cache *hpi_alloc_control_cache(const u32 control_count, const u32 size_in_bytes, u8 *p_dsp_control_buffer) { struct hpi_control_cache *p_cache = kmalloc(sizeof(*p_cache), GFP_KERNEL); if (!p_cache) return NULL; p_cache->p_info = kcalloc(control_count, sizeof(*p_cache->p_info), GFP_KERNEL); if (!p_cache->p_info) { kfree(p_cache); return NULL; } p_cache->cache_size_in_bytes = size_in_bytes; p_cache->control_count = control_count; p_cache->p_cache = p_dsp_control_buffer; p_cache->init = 0; return p_cache; } void hpi_free_control_cache(struct hpi_control_cache *p_cache) { if (p_cache) { kfree(p_cache->p_info); kfree(p_cache); } } static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) { hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, phm->function, 0); switch (phm->function) { case HPI_SUBSYS_OPEN: case HPI_SUBSYS_CLOSE: case HPI_SUBSYS_DRIVER_UNLOAD: break; case HPI_SUBSYS_DRIVER_LOAD: wipe_adapter_list(); hpios_alistlock_init(&adapters); break; case HPI_SUBSYS_GET_ADAPTER: subsys_get_adapter(phm, phr); break; case HPI_SUBSYS_GET_NUM_ADAPTERS: phr->u.s.num_adapters = adapters.gw_num_adapters; break; case HPI_SUBSYS_CREATE_ADAPTER: break; default: phr->error = HPI_ERROR_INVALID_FUNC; break; } } void HPI_COMMON(struct hpi_message *phm, struct hpi_response *phr) { switch (phm->type) { case HPI_TYPE_REQUEST: switch (phm->object) { case HPI_OBJ_SUBSYSTEM: subsys_message(phm, phr); break; } break; default: phr->error = HPI_ERROR_INVALID_TYPE; break; } }
linux-master
sound/pci/asihpi/hpicmn.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2011 AudioScience Inc. <[email protected]> Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters. These PCI bus adapters are based on the TI C6711 DSP. Exported functions: void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) #defines HIDE_PCI_ASSERTS to show the PCI asserts PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1) (C) Copyright AudioScience Inc. 1998-2003 *******************************************************************************/ #define SOURCEFILE_NAME "hpi6000.c" #include "hpi_internal.h" #include "hpimsginit.h" #include "hpidebug.h" #include "hpi6000.h" #include "hpidspcd.h" #include "hpicmn.h" #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */ #define HPI_HIF_ADDR(member) \ (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member)) #define HPI_HIF_ERROR_MASK 0x4000 /* HPI6000 specific error codes */ #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */ /* operational/messaging errors */ #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901 #define HPI6000_ERROR_RESP_GET_LEN 902 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903 #define HPI6000_ERROR_MSG_GET_ADR 904 #define HPI6000_ERROR_RESP_GET_ADR 905 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911 #define HPI6000_ERROR_SEND_DATA_ACK 912 #define HPI6000_ERROR_SEND_DATA_ADR 913 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914 #define HPI6000_ERROR_SEND_DATA_CMD 915 #define HPI6000_ERROR_SEND_DATA_WRITE 916 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921 #define HPI6000_ERROR_GET_DATA_ACK 922 #define HPI6000_ERROR_GET_DATA_CMD 923 #define HPI6000_ERROR_GET_DATA_READ 924 #define HPI6000_ERROR_GET_DATA_IDLECMD 925 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951 #define HPI6000_ERROR_CONTROL_CACHE_READ 952 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962 /* Initialisation/bootload errors */ #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930 /* can't access PCI2040 */ #define HPI6000_ERROR_INIT_PCI2040 931 /* can't access DSP HPI i/f */ #define HPI6000_ERROR_INIT_DSPHPI 932 /* can't access internal DSP memory */ #define HPI6000_ERROR_INIT_DSPINTMEM 933 /* can't access SDRAM - test#1 */ #define HPI6000_ERROR_INIT_SDRAM1 934 /* can't access SDRAM - test#2 */ #define HPI6000_ERROR_INIT_SDRAM2 935 #define HPI6000_ERROR_INIT_VERIFY 938 #define HPI6000_ERROR_INIT_NOACK 939 #define HPI6000_ERROR_INIT_PLDTEST1 941 #define HPI6000_ERROR_INIT_PLDTEST2 942 /* local defines */ #define HIDE_PCI_ASSERTS #define PROFILE_DSP2 /* for PCI2040 i/f chip */ /* HPI CSR registers */ /* word offsets from CSR base */ /* use when io addresses defined as u32 * */ #define INTERRUPT_EVENT_SET 0 #define INTERRUPT_EVENT_CLEAR 1 #define INTERRUPT_MASK_SET 2 #define INTERRUPT_MASK_CLEAR 3 #define HPI_ERROR_REPORT 4 #define HPI_RESET 5 #define HPI_DATA_WIDTH 6 #define MAX_DSPS 2 /* HPI registers, spaced 8K bytes = 2K words apart */ #define DSP_SPACING 0x800 #define CONTROL 0x0000 #define ADDRESS 0x0200 #define DATA_AUTOINC 0x0400 #define DATA 0x0600 #define TIMEOUT 500000 struct dsp_obj { __iomem u32 *prHPI_control; __iomem u32 *prHPI_address; __iomem u32 *prHPI_data; __iomem u32 *prHPI_data_auto_inc; char c_dsp_rev; /*A, B */ u32 control_cache_address_on_dsp; u32 control_cache_length_on_dsp; struct hpi_adapter_obj *pa_parent_adapter; }; struct hpi_hw_obj { __iomem u32 *dw2040_HPICSR; __iomem u32 *dw2040_HPIDSP; u16 num_dsp; struct dsp_obj ado[MAX_DSPS]; u32 message_buffer_address_on_dsp; u32 response_buffer_address_on_dsp; u32 pCI2040HPI_error_count; struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS]; struct hpi_control_cache *p_cache; }; static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, u16 dsp_index, u32 hpi_address, u32 *source, u32 count); static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, u16 dsp_index, u32 hpi_address, u32 *dest, u32 count); static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code); static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, u16 read_or_write); #define H6READ 1 #define H6WRITE 0 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, struct hpi_message *phm); static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr); static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, u32 ack_value); static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, u16 dsp_index, u32 host_cmd); static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo); static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr); static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr); static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data); static u32 hpi_read_word(struct dsp_obj *pdo, u32 address); static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, u32 length); static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, u32 length); static void subsys_create_adapter(struct hpi_message *phm, struct hpi_response *phr); static void adapter_delete(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void adapter_get_asserts(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static short create_adapter_obj(struct hpi_adapter_obj *pao, u32 *pos_error_code); static void delete_adapter_obj(struct hpi_adapter_obj *pao); /* local globals */ static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */ static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */ static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_SUBSYS_CREATE_ADAPTER: subsys_create_adapter(phm, phr); break; default: phr->error = HPI_ERROR_INVALID_FUNC; break; } } static void control_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; switch (phm->function) { case HPI_CONTROL_GET_STATE: if (pao->has_control_cache) { u16 err; err = hpi6000_update_control_cache(pao, phm); if (err) { if (err >= HPI_ERROR_BACKEND_BASE) { phr->error = HPI_ERROR_CONTROL_CACHING; phr->specific_error = err; } else { phr->error = err; } break; } if (hpi_check_control_cache(phw->p_cache, phm, phr)) break; } hw_message(pao, phm, phr); break; case HPI_CONTROL_SET_STATE: hw_message(pao, phm, phr); hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr); break; case HPI_CONTROL_GET_INFO: default: hw_message(pao, phm, phr); break; } } static void adapter_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_ADAPTER_GET_ASSERT: adapter_get_asserts(pao, phm, phr); break; case HPI_ADAPTER_DELETE: adapter_delete(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } } static void outstream_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_OSTREAM_HOSTBUFFER_ALLOC: case HPI_OSTREAM_HOSTBUFFER_FREE: /* Don't let these messages go to the HW function because * they're called without locking the spinlock. * For the HPI6000 adapters the HW would return * HPI_ERROR_INVALID_FUNC anyway. */ phr->error = HPI_ERROR_INVALID_FUNC; break; default: hw_message(pao, phm, phr); return; } } static void instream_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_ISTREAM_HOSTBUFFER_ALLOC: case HPI_ISTREAM_HOSTBUFFER_FREE: /* Don't let these messages go to the HW function because * they're called without locking the spinlock. * For the HPI6000 adapters the HW would return * HPI_ERROR_INVALID_FUNC anyway. */ phr->error = HPI_ERROR_INVALID_FUNC; break; default: hw_message(pao, phm, phr); return; } } /************************************************************************/ /** HPI_6000() * Entry point from HPIMAN * All calls to the HPI start here */ void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) { struct hpi_adapter_obj *pao = NULL; if (phm->object != HPI_OBJ_SUBSYSTEM) { pao = hpi_find_adapter(phm->adapter_index); if (!pao) { hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_BAD_ADAPTER_NUMBER); HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n", phm->adapter_index); return; } /* Don't even try to communicate with crashed DSP */ if (pao->dsp_crashed >= 10) { hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_DSP_HARDWARE); HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n", phm->adapter_index); return; } } /* Init default response including the size field */ if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_PROCESSING_MESSAGE); switch (phm->type) { case HPI_TYPE_REQUEST: switch (phm->object) { case HPI_OBJ_SUBSYSTEM: subsys_message(phm, phr); break; case HPI_OBJ_ADAPTER: phr->size = sizeof(struct hpi_response_header) + sizeof(struct hpi_adapter_res); adapter_message(pao, phm, phr); break; case HPI_OBJ_CONTROL: control_message(pao, phm, phr); break; case HPI_OBJ_OSTREAM: outstream_message(pao, phm, phr); break; case HPI_OBJ_ISTREAM: instream_message(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } break; default: phr->error = HPI_ERROR_INVALID_TYPE; break; } } /************************************************************************/ /* SUBSYSTEM */ /* create an adapter object and initialise it based on resource information * passed in the message * NOTE - you cannot use this function AND the FindAdapters function at the * same time, the application must use only one of them to get the adapters */ static void subsys_create_adapter(struct hpi_message *phm, struct hpi_response *phr) { /* create temp adapter obj, because we don't know what index yet */ struct hpi_adapter_obj ao; struct hpi_adapter_obj *pao; u32 os_error_code; u16 err = 0; u32 dsp_index = 0; HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n"); memset(&ao, 0, sizeof(ao)); ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); if (!ao.priv) { HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); phr->error = HPI_ERROR_MEMORY_ALLOC; return; } /* create the adapter object based on the resource information */ ao.pci = *phm->u.s.resource.r.pci; err = create_adapter_obj(&ao, &os_error_code); if (err) { delete_adapter_obj(&ao); if (err >= HPI_ERROR_BACKEND_BASE) { phr->error = HPI_ERROR_DSP_BOOTLOAD; phr->specific_error = err; } else { phr->error = err; } phr->u.s.data = os_error_code; return; } /* need to update paParentAdapter */ pao = hpi_find_adapter(ao.index); if (!pao) { /* We just added this adapter, why can't we find it!? */ HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n"); phr->error = HPI_ERROR_BAD_ADAPTER; return; } for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { struct hpi_hw_obj *phw = pao->priv; phw->ado[dsp_index].pa_parent_adapter = pao; } phr->u.s.adapter_type = ao.type; phr->u.s.adapter_index = ao.index; phr->error = 0; } static void adapter_delete(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { delete_adapter_obj(pao); hpi_delete_adapter(pao); phr->error = 0; } /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */ static short create_adapter_obj(struct hpi_adapter_obj *pao, u32 *pos_error_code) { short boot_error = 0; u32 dsp_index = 0; u32 control_cache_size = 0; u32 control_cache_count = 0; struct hpi_hw_obj *phw = pao->priv; /* The PCI2040 has the following address map */ /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ /* BAR1 - 32K = HPI registers on DSP */ phw->dw2040_HPICSR = pao->pci.ap_mem_base[0]; phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1]; HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR, phw->dw2040_HPIDSP); /* set addresses for the possible DSP HPI interfaces */ for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { phw->ado[dsp_index].prHPI_control = phw->dw2040_HPIDSP + (CONTROL + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_address = phw->dw2040_HPIDSP + (ADDRESS + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_data = phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_data_auto_inc = phw->dw2040_HPIDSP + (DATA_AUTOINC + DSP_SPACING * dsp_index); HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n", phw->ado[dsp_index].prHPI_control, phw->ado[dsp_index].prHPI_address, phw->ado[dsp_index].prHPI_data, phw->ado[dsp_index].prHPI_data_auto_inc); phw->ado[dsp_index].pa_parent_adapter = pao; } phw->pCI2040HPI_error_count = 0; pao->has_control_cache = 0; /* Set the default number of DSPs on this card */ /* This is (conditionally) adjusted after bootloading */ /* of the first DSP in the bootload section. */ phw->num_dsp = 1; boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code); if (boot_error) return boot_error; HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); phw->message_buffer_address_on_dsp = 0L; phw->response_buffer_address_on_dsp = 0L; /* get info about the adapter by asking the adapter */ /* send a HPI_ADAPTER_GET_INFO message */ { struct hpi_message hm; struct hpi_response hr0; /* response from DSP 0 */ struct hpi_response hr1; /* response from DSP 1 */ u16 error = 0; HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n"); memset(&hm, 0, sizeof(hm)); hm.type = HPI_TYPE_REQUEST; hm.size = sizeof(struct hpi_message); hm.object = HPI_OBJ_ADAPTER; hm.function = HPI_ADAPTER_GET_INFO; hm.adapter_index = 0; memset(&hr0, 0, sizeof(hr0)); memset(&hr1, 0, sizeof(hr1)); hr0.size = sizeof(hr0); hr1.size = sizeof(hr1); error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0); if (hr0.error) { HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error); return hr0.error; } if (phw->num_dsp == 2) { error = hpi6000_message_response_sequence(pao, 1, &hm, &hr1); if (error) return error; } pao->type = hr0.u.ax.info.adapter_type; pao->index = hr0.u.ax.info.adapter_index; } memset(&phw->control_cache[0], 0, sizeof(struct hpi_control_cache_single) * HPI_NMIXER_CONTROLS); /* Read the control cache length to figure out if it is turned on */ control_cache_size = hpi_read_word(&phw->ado[0], HPI_HIF_ADDR(control_cache_size_in_bytes)); if (control_cache_size) { control_cache_count = hpi_read_word(&phw->ado[0], HPI_HIF_ADDR(control_cache_count)); phw->p_cache = hpi_alloc_control_cache(control_cache_count, control_cache_size, (unsigned char *) &phw->control_cache[0] ); if (phw->p_cache) pao->has_control_cache = 1; } HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", pao->type, pao->index); if (phw->p_cache) phw->p_cache->adap_idx = pao->index; return hpi_add_adapter(pao); } static void delete_adapter_obj(struct hpi_adapter_obj *pao) { struct hpi_hw_obj *phw = pao->priv; if (pao->has_control_cache) hpi_free_control_cache(phw->p_cache); /* reset DSPs on adapter */ iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET); kfree(phw); } /************************************************************************/ /* ADAPTER */ static void adapter_get_asserts(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { #ifndef HIDE_PCI_ASSERTS /* if we have PCI2040 asserts then collect them */ if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) { phr->u.ax.assert.p1 = gw_pci_read_asserts * 100 + gw_pci_write_asserts; phr->u.ax.assert.p2 = 0; phr->u.ax.assert.count = 1; /* assert count */ phr->u.ax.assert.dsp_index = -1; /* "dsp index" */ strcpy(phr->u.ax.assert.sz_message, "PCI2040 error"); phr->u.ax.assert.dsp_msg_addr = 0; gw_pci_read_asserts = 0; gw_pci_write_asserts = 0; phr->error = 0; } else #endif hw_message(pao, phm, phr); /*get DSP asserts */ return; } /************************************************************************/ /* LOW-LEVEL */ static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code) { struct hpi_hw_obj *phw = pao->priv; short error; u32 timeout; u32 read = 0; u32 i = 0; u32 data = 0; u32 j = 0; u32 test_addr = 0x80000000; u32 test_data = 0x00000001; u32 dw2040_reset = 0; u32 dsp_index = 0; u32 endian = 0; u32 adapter_info = 0; u32 delay = 0; struct dsp_code dsp_code; u16 boot_load_family = 0; /* NOTE don't use wAdapterType in this routine. It is not setup yet */ switch (pao->pci.pci_dev->subsystem_device) { case 0x5100: case 0x5110: /* ASI5100 revB or higher with C6711D */ case 0x5200: /* ASI5200 PCIe version of ASI5100 */ case 0x6100: case 0x6200: boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200); break; default: return HPI6000_ERROR_UNHANDLED_SUBSYS_ID; } /* reset all DSPs, indicate two DSPs are present * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode */ endian = 0; dw2040_reset = 0x0003000F; iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* read back register to make sure PCI2040 chip is functioning * note that bits 4..15 are read-only and so should always return zero, * even though we wrote 1 to them */ hpios_delay_micro_seconds(1000); delay = ioread32(phw->dw2040_HPICSR + HPI_RESET); if (delay != dw2040_reset) { HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset, delay); return HPI6000_ERROR_INIT_PCI2040; } /* Indicate that DSP#0,1 is a C6X */ iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH); /* set Bit30 and 29 - which will prevent Target aborts from being * issued upon HPI or GP error */ iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET); /* isolate DSP HAD8 line from PCI2040 so that * Little endian can be set by pullup */ dw2040_reset = dw2040_reset & (~(endian << 3)); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); phw->ado[0].c_dsp_rev = 'B'; /* revB */ phw->ado[1].c_dsp_rev = 'B'; /* revB */ /*Take both DSPs out of reset, setting HAD8 to the correct Endian */ dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* set HAD8 back to PCI2040, now that DSP set to little endian mode */ dw2040_reset = dw2040_reset & (~0x00000008); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /*delay to allow DSP to get going */ hpios_delay_micro_seconds(100); /* loop through all DSPs, downloading DSP code */ for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) { struct dsp_obj *pdo = &phw->ado[dsp_index]; /* configure DSP so that we download code into the SRAM */ /* set control reg for little endian, HWOB=1 */ iowrite32(0x00010001, pdo->prHPI_control); /* test access to the HPI address register (HPIA) */ test_data = 0x00000001; for (j = 0; j < 32; j++) { iowrite32(test_data, pdo->prHPI_address); data = ioread32(pdo->prHPI_address); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n", test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPHPI; } test_data = test_data << 1; } /* if C6713 the setup PLL to generate 225MHz from 25MHz. * Since the PLLDIV1 read is sometimes wrong, even on a C6713, * we're going to do this unconditionally */ /* PLLDIV1 should have a value of 8000 after reset */ /* if (HpiReadWord(pdo,0x01B7C118) == 0x8000) */ { /* C6713 datasheet says we cannot program PLL from HPI, * and indeed if we try to set the PLL multiply from the * HPI, the PLL does not seem to lock, * so we enable the PLL and use the default of x 7 */ /* bypass PLL */ hpi_write_word(pdo, 0x01B7C100, 0x0000); hpios_delay_micro_seconds(100); /* ** use default of PLL x7 ** */ /* EMIF = 225/3=75MHz */ hpi_write_word(pdo, 0x01B7C120, 0x8002); hpios_delay_micro_seconds(100); /* peri = 225/2 */ hpi_write_word(pdo, 0x01B7C11C, 0x8001); hpios_delay_micro_seconds(100); /* cpu = 225/1 */ hpi_write_word(pdo, 0x01B7C118, 0x8000); /* ~2ms delay */ hpios_delay_micro_seconds(2000); /* PLL not bypassed */ hpi_write_word(pdo, 0x01B7C100, 0x0001); /* ~2ms delay */ hpios_delay_micro_seconds(2000); } /* test r/w to internal DSP memory * C6711 has L2 cache mapped to 0x0 when reset * * revB - because of bug 3.0.1 last HPI read * (before HPI address issued) must be non-autoinc */ /* test each bit in the 32bit word */ for (i = 0; i < 100; i++) { test_addr = 0x00000000; test_data = 0x00000001; for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr + i, test_data); data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP mem %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPINTMEM; } test_data = test_data << 1; } } /* memory map of ASI6200 00000000-0000FFFF 16Kx32 internal program 01800000-019FFFFF Internal peripheral 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz 90000000-9000FFFF CE1 Async peripherals: EMIF config ------------ Global EMIF control 0 - 1 - 2 - 3 CLK2EN = 1 CLKOUT2 enabled 4 CLK1EN = 0 CLKOUT1 disabled 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT 6 - 7 NOHOLD = 1 external HOLD disabled 8 HOLDA = 0 HOLDA output is low 9 HOLD = 0 HOLD input is low 10 ARDY = 1 ARDY input is high 11 BUSREQ = 0 BUSREQ output is low 12,13 Reserved = 1 */ hpi_write_word(pdo, 0x01800000, 0x34A8); /* EMIF CE0 setup - 2Mx32 Sync DRAM 31..28 Wr setup 27..22 Wr strobe 21..20 Wr hold 19..16 Rd setup 15..14 - 13..8 Rd strobe 7..4 MTYPE 0011 Sync DRAM 32bits 3 Wr hold MSB 2..0 Rd hold */ hpi_write_word(pdo, 0x01800008, 0x00000030); /* EMIF SDRAM Extension 31-21 0 20 WR2RD = 0 19-18 WR2DEAC = 1 17 WR2WR = 0 16-15 R2WDQM = 2 14-12 RD2WR = 4 11-10 RD2DEAC = 1 9 RD2RD = 1 8-7 THZP = 10b 6-5 TWR = 2-1 = 01b (tWR = 10ns) 4 TRRD = 0b = 2 ECLK (tRRD = 14ns) 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK) 1 CAS latency = 3 ECLK (for Micron 2M32-7 operating at 100Mhz) */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800020, 0x001BDF29); /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 31 - - 30 SDBSZ 1 4 bank 29..28 SDRSZ 00 11 row address pins 27..26 SDCSZ 01 8 column address pins 25 RFEN 1 refersh enabled 24 INIT 1 init SDRAM 23..20 TRCD 0001 19..16 TRP 0001 15..12 TRC 0110 11..0 - - */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800018, 0x47117000); /* EMIF SDRAM Refresh Timing */ hpi_write_word(pdo, 0x0180001C, 0x00000410); /*MIF CE1 setup - Async peripherals @100MHz bus speed, each cycle is 10ns, 31..28 Wr setup = 1 27..22 Wr strobe = 3 30ns 21..20 Wr hold = 1 19..16 Rd setup =1 15..14 Ta = 2 13..8 Rd strobe = 3 30ns 7..4 MTYPE 0010 Async 32bits 3 Wr hold MSB =0 2..0 Rd hold = 1 */ { u32 cE1 = (1L << 28) | (3L << 22) | (1L << 20) | (1L << 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L; hpi_write_word(pdo, 0x01800004, cE1); } /* delay a little to allow SDRAM and DSP to "get going" */ hpios_delay_micro_seconds(1000); /* test access to SDRAM */ { test_addr = 0x80000000; test_data = 0x00000001; /* test each bit in the 32bit word */ for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr, test_data); data = hpi_read_word(pdo, test_addr); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM1; } test_data = test_data << 1; } /* test every Nth address in the DRAM */ #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */ #define DRAM_INC 1024 test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { hpi_write_word(pdo, test_addr + i, test_data); test_data++; } test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM2; } test_data++; } } /* write the DSP code down into the DSPs memory */ error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev, &dsp_code, pos_error_code); if (error) return error; while (1) { u32 length; u32 address; u32 type; u32 *pcode; error = hpi_dsp_code_read_word(&dsp_code, &length); if (error) break; if (length == 0xFFFFFFFF) break; /* end of code */ error = hpi_dsp_code_read_word(&dsp_code, &address); if (error) break; error = hpi_dsp_code_read_word(&dsp_code, &type); if (error) break; error = hpi_dsp_code_read_block(length, &dsp_code, &pcode); if (error) break; error = hpi6000_dsp_block_write32(pao, (u16)dsp_index, address, pcode, length); if (error) break; } if (error) { hpi_dsp_code_close(&dsp_code); return error; } /* verify that code was written correctly */ /* this time through, assume no errors in DSP code file/array */ hpi_dsp_code_rewind(&dsp_code); while (1) { u32 length; u32 address; u32 type; u32 *pcode; hpi_dsp_code_read_word(&dsp_code, &length); if (length == 0xFFFFFFFF) break; /* end of code */ hpi_dsp_code_read_word(&dsp_code, &address); hpi_dsp_code_read_word(&dsp_code, &type); hpi_dsp_code_read_block(length, &dsp_code, &pcode); for (i = 0; i < length; i++) { data = hpi_read_word(pdo, address); if (data != *pcode) { error = HPI6000_ERROR_INIT_VERIFY; HPI_DEBUG_LOG(ERROR, "DSP verify %x %x %x %x\n", address, *pcode, data, dsp_index); break; } pcode++; address += 4; } if (error) break; } hpi_dsp_code_close(&dsp_code); if (error) return error; /* zero out the hostmailbox */ { u32 address = HPI_HIF_ADDR(host_cmd); for (i = 0; i < 4; i++) { hpi_write_word(pdo, address, 0); address += 4; } } /* write the DSP number into the hostmailbox */ /* structure before starting the DSP */ hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index); /* write the DSP adapter Info into the */ /* hostmailbox before starting the DSP */ if (dsp_index > 0) hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info), adapter_info); /* step 3. Start code by sending interrupt */ iowrite32(0x00030003, pdo->prHPI_control); hpios_delay_micro_seconds(10000); /* wait for a non-zero value in hostcmd - * indicating initialization is complete * * Init could take a while if DSP checks SDRAM memory * Was 200000. Increased to 2000000 for ASI8801 so we * don't get 938 errors. */ timeout = 2000000; while (timeout) { do { read = hpi_read_word(pdo, HPI_HIF_ADDR(host_cmd)); } while (--timeout && hpi6000_check_PCI2040_error_flag(pao, H6READ)); if (read) break; /* The following is a workaround for bug #94: * Bluescreen on install and subsequent boots on a * DELL PowerEdge 600SC PC with 1.8GHz P4 and * ServerWorks chipset. Without this delay the system * locks up with a bluescreen (NOT GPF or pagefault). */ else hpios_delay_micro_seconds(10000); } if (timeout == 0) return HPI6000_ERROR_INIT_NOACK; /* read the DSP adapter Info from the */ /* hostmailbox structure after starting the DSP */ if (dsp_index == 0) { /*u32 dwTestData=0; */ u32 mask = 0; adapter_info = hpi_read_word(pdo, HPI_HIF_ADDR(adapter_info)); if (HPI_ADAPTER_FAMILY_ASI (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER (adapter_info)) == HPI_ADAPTER_FAMILY_ASI(0x6200)) /* all 6200 cards have this many DSPs */ phw->num_dsp = 2; /* test that the PLD is programmed */ /* and we can read/write 24bits */ #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */ switch (boot_load_family) { case HPI_ADAPTER_FAMILY_ASI(0x6200): /* ASI6100/6200 has 24bit path to FPGA */ mask = 0xFFFFFF00L; /* ASI5100 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5100)) mask = 0x00000000L; /* ASI5200 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5200)) mask = 0x00000000L; break; case HPI_ADAPTER_FAMILY_ASI(0x8800): /* ASI8800 has 16bit path to FPGA */ mask = 0xFFFF0000L; break; } test_data = 0xAAAAAA00L & mask; /* write to 24 bit Debug register (D31-D8) */ hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST1; } test_data = 0x55555500L & mask; hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST2; } } } /* for numDSP */ return 0; } #define PCI_TIMEOUT 100 static int hpi_set_address(struct dsp_obj *pdo, u32 address) { u32 timeout = PCI_TIMEOUT; do { iowrite32(address, pdo->prHPI_address); } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter, H6WRITE) && --timeout); if (timeout) return 0; return 1; } /* write one word to the HPI port */ static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data) { if (hpi_set_address(pdo, address)) return; iowrite32(data, pdo->prHPI_data); } /* read one word from the HPI port */ static u32 hpi_read_word(struct dsp_obj *pdo, u32 address) { u32 data = 0; if (hpi_set_address(pdo, address)) return 0; /*? No way to return error */ /* take care of errata in revB DSP (2.0.1) */ data = ioread32(pdo->prHPI_data); return data; } /* write a block of 32bit words to the DSP HPI port using auto-inc mode */ static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, u32 length) { u16 length16 = length - 1; if (length == 0) return; if (hpi_set_address(pdo, address)) return; iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16); /* take care of errata in revB DSP (2.0.1) */ /* must end with non auto-inc */ iowrite32(*(pdata + length - 1), pdo->prHPI_data); } /** read a block of 32bit words from the DSP HPI port using auto-inc mode */ static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, u32 length) { u16 length16 = length - 1; if (length == 0) return; if (hpi_set_address(pdo, address)) return; ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16); /* take care of errata in revB DSP (2.0.1) */ /* must end with non auto-inc */ *(pdata + length - 1) = ioread32(pdo->prHPI_data); } static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, u16 dsp_index, u32 hpi_address, u32 *source, u32 count) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 time_out = PCI_TIMEOUT; int c6711_burst_size = 128; u32 local_hpi_address = hpi_address; int local_count = count; int xfer_size; u32 *pdata = source; while (local_count) { if (local_count > c6711_burst_size) xfer_size = c6711_burst_size; else xfer_size = local_count; time_out = PCI_TIMEOUT; do { hpi_write_block(pdo, local_hpi_address, pdata, xfer_size); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --time_out); if (!time_out) break; pdata += xfer_size; local_hpi_address += sizeof(u32) * xfer_size; local_count -= xfer_size; } if (time_out) return 0; else return 1; } static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, u16 dsp_index, u32 hpi_address, u32 *dest, u32 count) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 time_out = PCI_TIMEOUT; int c6711_burst_size = 16; u32 local_hpi_address = hpi_address; int local_count = count; int xfer_size; u32 *pdata = dest; while (local_count) { if (local_count > c6711_burst_size) xfer_size = c6711_burst_size; else xfer_size = local_count; time_out = PCI_TIMEOUT; do { hpi_read_block(pdo, local_hpi_address, pdata, xfer_size); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --time_out); if (!time_out) break; pdata += xfer_size; local_hpi_address += sizeof(u32) * xfer_size; local_count -= xfer_size; } if (time_out) return 0; else return 1; } static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout; u16 ack; u32 address; u32 length; u32 *p_data; u16 error = 0; ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) { pao->dsp_crashed++; return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT; } pao->dsp_crashed = 0; /* get the message address and size */ if (phw->message_buffer_address_on_dsp == 0) { timeout = TIMEOUT; do { address = hpi_read_word(pdo, HPI_HIF_ADDR(message_buffer_address)); phw->message_buffer_address_on_dsp = address; } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) return HPI6000_ERROR_MSG_GET_ADR; } else address = phw->message_buffer_address_on_dsp; length = phm->size; /* send the message */ p_data = (u32 *)phm; if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, (u16)length / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP)) return HPI6000_ERROR_MSG_RESP_GETRESPCMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK; /* get the response address */ if (phw->response_buffer_address_on_dsp == 0) { timeout = TIMEOUT; do { address = hpi_read_word(pdo, HPI_HIF_ADDR(response_buffer_address)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); phw->response_buffer_address_on_dsp = address; if (!timeout) return HPI6000_ERROR_RESP_GET_ADR; } else address = phw->response_buffer_address_on_dsp; /* read the length of the response back from the DSP */ timeout = TIMEOUT; do { length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) return HPI6000_ERROR_RESP_GET_LEN; if (length > phr->size) return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; /* get the response */ p_data = (u32 *)phr; if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, (u16)length / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKREAD32; /* set i/f back to idle */ if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_MSG_RESP_IDLECMD; hpi6000_send_dsp_interrupt(pdo); error = hpi_validate_response(phm, phr); return error; } /* have to set up the below defines to match stuff in the MAP file */ #define MSG_ADDRESS (HPI_HIF_BASE+0x18) #define MSG_LENGTH 11 #define RESP_ADDRESS (HPI_HIF_BASE+0x44) #define RESP_LENGTH 16 #define QUEUE_START (HPI_HIF_BASE+0x88) #define QUEUE_SIZE 0x8000 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords) { /*#define CHECKING // comment this line in to enable checking */ #ifdef CHECKING if (address < (u32)MSG_ADDRESS) return 0; if (address > (u32)(QUEUE_START + QUEUE_SIZE)) return 0; if ((address + (length_in_dwords << 2)) > (u32)(QUEUE_START + QUEUE_SIZE)) return 0; #else (void)address; (void)length_in_dwords; return 1; #endif } static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 data_sent = 0; u16 ack; u32 length, address; u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; u16 time_out = 8; (void)phr; /* round dwDataSize down to nearest 4 bytes */ while ((data_sent < (phm->u.d.u.data.data_size & ~3L)) && --time_out) { ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_SEND_DATA)) return HPI6000_ERROR_SEND_DATA_CMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_ACK; do { /* get the address and size */ address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); /* DSP returns number of DWORDS */ length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); if (!hpi6000_send_data_check_adr(address, length)) return HPI6000_ERROR_SEND_DATA_ADR; /* send the data. break data into 512 DWORD blocks (2K bytes) * and send using block write. 2Kbytes is the max as this is the * memory window given to the HPI data register by the PCI2040 */ { u32 len = length; u32 blk_len = 512; while (len) { if (len < blk_len) blk_len = len; if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, blk_len)) return HPI6000_ERROR_SEND_DATA_WRITE; address += blk_len * 4; p_data += blk_len; len -= blk_len; } } if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_SEND_DATA_IDLECMD; hpi6000_send_dsp_interrupt(pdo); data_sent += length * 4; } if (!time_out) return HPI6000_ERROR_SEND_DATA_TIMEOUT; return 0; } static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 data_got = 0; u16 ack; u32 length, address; u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; (void)phr; /* this parameter not used! */ /* round dwDataSize down to nearest 4 bytes */ while (data_got < (phm->u.d.u.data.data_size & ~3L)) { ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_DATA)) return HPI6000_ERROR_GET_DATA_CMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_ACK; /* get the address and size */ do { address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); /* read the data */ { u32 len = length; u32 blk_len = 512; while (len) { if (len < blk_len) blk_len = len; if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, blk_len)) return HPI6000_ERROR_GET_DATA_READ; address += blk_len * 4; p_data += blk_len; len -= blk_len; } } if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_GET_DATA_IDLECMD; hpi6000_send_dsp_interrupt(pdo); data_got += length * 4; } return 0; } static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo) { iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */ } static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, u16 dsp_index, u32 host_cmd) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout = TIMEOUT; /* set command */ do { hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); /* reset the interrupt bit */ iowrite32(0x00040004, pdo->prHPI_control); if (timeout) return 0; else return 1; } /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */ static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, u16 read_or_write) { u32 hPI_error; struct hpi_hw_obj *phw = pao->priv; /* read the error bits from the PCI2040 */ hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT); if (hPI_error) { /* reset the error flag */ iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT); phw->pCI2040HPI_error_count++; if (read_or_write == 1) gw_pci_read_asserts++; /************* inc global */ else gw_pci_write_asserts++; return 1; } else return 0; } static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, u32 ack_value) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 ack = 0L; u32 timeout; u32 hPIC = 0L; /* wait for host interrupt to signal ack is ready */ timeout = TIMEOUT; while (--timeout) { hPIC = ioread32(pdo->prHPI_control); if (hPIC & 0x04) /* 0x04 = HINT from DSP */ break; } if (timeout == 0) return HPI_HIF_ERROR_MASK; /* wait for dwAckValue */ timeout = TIMEOUT; while (--timeout) { /* read the ack mailbox */ ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack)); if (ack == ack_value) break; if ((ack & HPI_HIF_ERROR_MASK) && !hpi6000_check_PCI2040_error_flag(pao, H6READ)) break; /*for (i=0;i<1000;i++) */ /* dwPause=i+1; */ } if (ack & HPI_HIF_ERROR_MASK) /* indicates bad read from DSP - typically 0xffffff is read for some reason */ ack = HPI_HIF_ERROR_MASK; if (timeout == 0) ack = HPI_HIF_ERROR_MASK; return (short)ack; } static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, struct hpi_message *phm) { const u16 dsp_index = 0; struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout; u32 cache_dirty_flag; u16 err; hpios_dsplock_lock(pao); timeout = TIMEOUT; do { cache_dirty_flag = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; goto unlock; } if (cache_dirty_flag) { /* read the cached controls */ u32 address; u32 length; timeout = TIMEOUT; if (pdo->control_cache_address_on_dsp == 0) { do { address = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_address)); length = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR (control_cache_size_in_bytes)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; goto unlock; } pdo->control_cache_address_on_dsp = address; pdo->control_cache_length_on_dsp = length; } else { address = pdo->control_cache_address_on_dsp; length = pdo->control_cache_length_on_dsp; } if (hpi6000_dsp_block_read32(pao, dsp_index, address, (u32 *)&phw->control_cache[0], length / sizeof(u32))) { err = HPI6000_ERROR_CONTROL_CACHE_READ; goto unlock; } do { hpi_write_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty), 0); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; goto unlock; } } err = 0; unlock: hpios_dsplock_unlock(pao); return err; } /** Get dsp index for multi DSP adapters only */ static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm) { u16 ret = 0; switch (phm->object) { case HPI_OBJ_ISTREAM: if (phm->obj_index < 2) ret = 1; break; case HPI_OBJ_PROFILE: ret = phm->obj_index; break; default: break; } return ret; } /** Complete transaction with DSP Send message, get response, send or get stream data if any. */ static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { u16 error = 0; u16 dsp_index = 0; struct hpi_hw_obj *phw = pao->priv; u16 num_dsp = phw->num_dsp; if (num_dsp < 2) dsp_index = 0; else { dsp_index = get_dsp_index(pao, phm); /* is this checked on the DSP anyway? */ if ((phm->function == HPI_ISTREAM_GROUP_ADD) || (phm->function == HPI_OSTREAM_GROUP_ADD)) { struct hpi_message hm; u16 add_index; hm.obj_index = phm->u.d.u.stream.stream_index; hm.object = phm->u.d.u.stream.object_type; add_index = get_dsp_index(pao, &hm); if (add_index != dsp_index) { phr->error = HPI_ERROR_NO_INTERDSP_GROUPS; return; } } } hpios_dsplock_lock(pao); error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr); if (error) /* something failed in the HPI/DSP interface */ goto err; if (phr->error) /* something failed in the DSP */ goto out; switch (phm->function) { case HPI_OSTREAM_WRITE: case HPI_ISTREAM_ANC_WRITE: error = hpi6000_send_data(pao, dsp_index, phm, phr); break; case HPI_ISTREAM_READ: case HPI_OSTREAM_ANC_READ: error = hpi6000_get_data(pao, dsp_index, phm, phr); break; case HPI_ADAPTER_GET_ASSERT: phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */ if (num_dsp == 2) { if (!phr->u.ax.assert.count) { /* no assert from dsp 0, check dsp 1 */ error = hpi6000_message_response_sequence(pao, 1, phm, phr); phr->u.ax.assert.dsp_index = 1; } } } err: if (error) { if (error >= HPI_ERROR_BACKEND_BASE) { phr->error = HPI_ERROR_DSP_COMMUNICATION; phr->specific_error = error; } else { phr->error = error; } /* just the header of the response is valid */ phr->size = sizeof(struct hpi_response_header); } out: hpios_dsplock_unlock(pao); return; }
linux-master
sound/pci/asihpi/hpi6000.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> Extended Message Function With Response Caching (C) Copyright AudioScience Inc. 2002 *****************************************************************************/ #define SOURCEFILE_NAME "hpimsgx.c" #include "hpi_internal.h" #include "hpi_version.h" #include "hpimsginit.h" #include "hpicmn.h" #include "hpimsgx.h" #include "hpidebug.h" static const struct pci_device_id asihpi_pci_tbl[] = { #include "hpipcida.h" }; static struct hpios_spinlock msgx_lock; static hpi_handler_func *hpi_entry_points[HPI_MAX_ADAPTERS]; static int logging_enabled = 1; static hpi_handler_func *hpi_lookup_entry_point_function(const struct hpi_pci *pci_info) { int i; for (i = 0; asihpi_pci_tbl[i].vendor != 0; i++) { if (asihpi_pci_tbl[i].vendor != PCI_ANY_ID && asihpi_pci_tbl[i].vendor != pci_info->pci_dev->vendor) continue; if (asihpi_pci_tbl[i].device != PCI_ANY_ID && asihpi_pci_tbl[i].device != pci_info->pci_dev->device) continue; if (asihpi_pci_tbl[i].subvendor != PCI_ANY_ID && asihpi_pci_tbl[i].subvendor != pci_info->pci_dev->subsystem_vendor) continue; if (asihpi_pci_tbl[i].subdevice != PCI_ANY_ID && asihpi_pci_tbl[i].subdevice != pci_info->pci_dev->subsystem_device) continue; /* HPI_DEBUG_LOG(DEBUG, " %x,%lx\n", i, asihpi_pci_tbl[i].driver_data); */ return (hpi_handler_func *) asihpi_pci_tbl[i].driver_data; } return NULL; } static inline void hw_entry_point(struct hpi_message *phm, struct hpi_response *phr) { if ((phm->adapter_index < HPI_MAX_ADAPTERS) && hpi_entry_points[phm->adapter_index]) hpi_entry_points[phm->adapter_index] (phm, phr); else hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_PROCESSING_MESSAGE); } static void adapter_open(struct hpi_message *phm, struct hpi_response *phr); static void adapter_close(struct hpi_message *phm, struct hpi_response *phr); static void mixer_open(struct hpi_message *phm, struct hpi_response *phr); static void mixer_close(struct hpi_message *phm, struct hpi_response *phr); static void outstream_open(struct hpi_message *phm, struct hpi_response *phr, void *h_owner); static void outstream_close(struct hpi_message *phm, struct hpi_response *phr, void *h_owner); static void instream_open(struct hpi_message *phm, struct hpi_response *phr, void *h_owner); static void instream_close(struct hpi_message *phm, struct hpi_response *phr, void *h_owner); static void HPIMSGX__reset(u16 adapter_index); static u16 HPIMSGX__init(struct hpi_message *phm, struct hpi_response *phr); static void HPIMSGX__cleanup(u16 adapter_index, void *h_owner); #ifndef DISABLE_PRAGMA_PACK1 #pragma pack(push, 1) #endif struct hpi_adapter_response { struct hpi_response_header h; struct hpi_adapter_res a; }; struct hpi_mixer_response { struct hpi_response_header h; struct hpi_mixer_res m; }; struct hpi_stream_response { struct hpi_response_header h; struct hpi_stream_res d; }; struct adapter_info { u16 type; u16 num_instreams; u16 num_outstreams; }; struct asi_open_state { int open_flag; void *h_owner; }; #ifndef DISABLE_PRAGMA_PACK1 #pragma pack(pop) #endif /* Globals */ static struct hpi_adapter_response rESP_HPI_ADAPTER_OPEN[HPI_MAX_ADAPTERS]; static struct hpi_stream_response rESP_HPI_OSTREAM_OPEN[HPI_MAX_ADAPTERS][HPI_MAX_STREAMS]; static struct hpi_stream_response rESP_HPI_ISTREAM_OPEN[HPI_MAX_ADAPTERS][HPI_MAX_STREAMS]; static struct hpi_mixer_response rESP_HPI_MIXER_OPEN[HPI_MAX_ADAPTERS]; static struct adapter_info aDAPTER_INFO[HPI_MAX_ADAPTERS]; /* use these to keep track of opens from user mode apps/DLLs */ static struct asi_open_state outstream_user_open[HPI_MAX_ADAPTERS][HPI_MAX_STREAMS]; static struct asi_open_state instream_user_open[HPI_MAX_ADAPTERS][HPI_MAX_STREAMS]; static void subsys_message(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { if (phm->adapter_index != HPI_ADAPTER_INDEX_INVALID) HPI_DEBUG_LOG(WARNING, "suspicious adapter index %d in subsys message 0x%x.\n", phm->adapter_index, phm->function); switch (phm->function) { case HPI_SUBSYS_GET_VERSION: hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_GET_VERSION, 0); phr->u.s.version = HPI_VER >> 8; /* return major.minor */ phr->u.s.data = HPI_VER; /* return major.minor.release */ break; case HPI_SUBSYS_OPEN: /*do not propagate the message down the chain */ hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_OPEN, 0); break; case HPI_SUBSYS_CLOSE: /*do not propagate the message down the chain */ hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_CLOSE, 0); HPIMSGX__cleanup(HPIMSGX_ALLADAPTERS, h_owner); break; case HPI_SUBSYS_DRIVER_LOAD: /* Initialize this module's internal state */ hpios_msgxlock_init(&msgx_lock); memset(&hpi_entry_points, 0, sizeof(hpi_entry_points)); /* Init subsys_findadapters response to no-adapters */ HPIMSGX__reset(HPIMSGX_ALLADAPTERS); hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_DRIVER_LOAD, 0); /* individual HPIs dont implement driver load */ HPI_COMMON(phm, phr); break; case HPI_SUBSYS_DRIVER_UNLOAD: HPI_COMMON(phm, phr); HPIMSGX__cleanup(HPIMSGX_ALLADAPTERS, h_owner); hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_DRIVER_UNLOAD, 0); return; case HPI_SUBSYS_GET_NUM_ADAPTERS: case HPI_SUBSYS_GET_ADAPTER: HPI_COMMON(phm, phr); break; case HPI_SUBSYS_CREATE_ADAPTER: HPIMSGX__init(phm, phr); break; default: /* Must explicitly handle every subsys message in this switch */ hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, phm->function, HPI_ERROR_INVALID_FUNC); break; } } static void adapter_message(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { switch (phm->function) { case HPI_ADAPTER_OPEN: adapter_open(phm, phr); break; case HPI_ADAPTER_CLOSE: adapter_close(phm, phr); break; case HPI_ADAPTER_DELETE: HPIMSGX__cleanup(phm->adapter_index, h_owner); { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_CLOSE); hm.adapter_index = phm->adapter_index; hw_entry_point(&hm, &hr); } hw_entry_point(phm, phr); break; default: hw_entry_point(phm, phr); break; } } static void mixer_message(struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_MIXER_OPEN: mixer_open(phm, phr); break; case HPI_MIXER_CLOSE: mixer_close(phm, phr); break; default: hw_entry_point(phm, phr); break; } } static void outstream_message(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { if (phm->obj_index >= aDAPTER_INFO[phm->adapter_index].num_outstreams) { hpi_init_response(phr, HPI_OBJ_OSTREAM, phm->function, HPI_ERROR_INVALID_OBJ_INDEX); return; } switch (phm->function) { case HPI_OSTREAM_OPEN: outstream_open(phm, phr, h_owner); break; case HPI_OSTREAM_CLOSE: outstream_close(phm, phr, h_owner); break; default: hw_entry_point(phm, phr); break; } } static void instream_message(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { if (phm->obj_index >= aDAPTER_INFO[phm->adapter_index].num_instreams) { hpi_init_response(phr, HPI_OBJ_ISTREAM, phm->function, HPI_ERROR_INVALID_OBJ_INDEX); return; } switch (phm->function) { case HPI_ISTREAM_OPEN: instream_open(phm, phr, h_owner); break; case HPI_ISTREAM_CLOSE: instream_close(phm, phr, h_owner); break; default: hw_entry_point(phm, phr); break; } } /* NOTE: HPI_Message() must be defined in the driver as a wrapper for * HPI_MessageEx so that functions in hpifunc.c compile. */ void hpi_send_recv_ex(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { if (logging_enabled) HPI_DEBUG_MESSAGE(DEBUG, phm); if (phm->type != HPI_TYPE_REQUEST) { hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_INVALID_TYPE); return; } if (phm->adapter_index >= HPI_MAX_ADAPTERS && phm->adapter_index != HPIMSGX_ALLADAPTERS) { hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_BAD_ADAPTER_NUMBER); return; } switch (phm->object) { case HPI_OBJ_SUBSYSTEM: subsys_message(phm, phr, h_owner); break; case HPI_OBJ_ADAPTER: adapter_message(phm, phr, h_owner); break; case HPI_OBJ_MIXER: mixer_message(phm, phr); break; case HPI_OBJ_OSTREAM: outstream_message(phm, phr, h_owner); break; case HPI_OBJ_ISTREAM: instream_message(phm, phr, h_owner); break; default: hw_entry_point(phm, phr); break; } if (logging_enabled) HPI_DEBUG_RESPONSE(phr); if (phr->error >= HPI_ERROR_DSP_COMMUNICATION) { hpi_debug_level_set(HPI_DEBUG_LEVEL_ERROR); logging_enabled = 0; } } static void adapter_open(struct hpi_message *phm, struct hpi_response *phr) { HPI_DEBUG_LOG(VERBOSE, "adapter_open\n"); memcpy(phr, &rESP_HPI_ADAPTER_OPEN[phm->adapter_index], sizeof(rESP_HPI_ADAPTER_OPEN[0])); } static void adapter_close(struct hpi_message *phm, struct hpi_response *phr) { HPI_DEBUG_LOG(VERBOSE, "adapter_close\n"); hpi_init_response(phr, HPI_OBJ_ADAPTER, HPI_ADAPTER_CLOSE, 0); } static void mixer_open(struct hpi_message *phm, struct hpi_response *phr) { memcpy(phr, &rESP_HPI_MIXER_OPEN[phm->adapter_index], sizeof(rESP_HPI_MIXER_OPEN[0])); } static void mixer_close(struct hpi_message *phm, struct hpi_response *phr) { hpi_init_response(phr, HPI_OBJ_MIXER, HPI_MIXER_CLOSE, 0); } static void instream_open(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { struct hpi_message hm; struct hpi_response hr; hpi_init_response(phr, HPI_OBJ_ISTREAM, HPI_ISTREAM_OPEN, 0); hpios_msgxlock_lock(&msgx_lock); if (instream_user_open[phm->adapter_index][phm->obj_index].open_flag) phr->error = HPI_ERROR_OBJ_ALREADY_OPEN; else if (rESP_HPI_ISTREAM_OPEN[phm->adapter_index] [phm->obj_index].h.error) memcpy(phr, &rESP_HPI_ISTREAM_OPEN[phm->adapter_index][phm-> obj_index], sizeof(rESP_HPI_ISTREAM_OPEN[0][0])); else { instream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 1; hpios_msgxlock_unlock(&msgx_lock); /* issue a reset */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_RESET); hm.adapter_index = phm->adapter_index; hm.obj_index = phm->obj_index; hw_entry_point(&hm, &hr); hpios_msgxlock_lock(&msgx_lock); if (hr.error) { instream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 0; phr->error = hr.error; } else { instream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 1; instream_user_open[phm->adapter_index][phm-> obj_index].h_owner = h_owner; memcpy(phr, &rESP_HPI_ISTREAM_OPEN[phm->adapter_index] [phm->obj_index], sizeof(rESP_HPI_ISTREAM_OPEN[0][0])); } } hpios_msgxlock_unlock(&msgx_lock); } static void instream_close(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { struct hpi_message hm; struct hpi_response hr; hpi_init_response(phr, HPI_OBJ_ISTREAM, HPI_ISTREAM_CLOSE, 0); hpios_msgxlock_lock(&msgx_lock); if (h_owner == instream_user_open[phm->adapter_index][phm-> obj_index].h_owner) { /* HPI_DEBUG_LOG(INFO,"closing adapter %d " "instream %d owned by %p\n", phm->wAdapterIndex, phm->wObjIndex, hOwner); */ instream_user_open[phm->adapter_index][phm-> obj_index].h_owner = NULL; hpios_msgxlock_unlock(&msgx_lock); /* issue a reset */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_RESET); hm.adapter_index = phm->adapter_index; hm.obj_index = phm->obj_index; hw_entry_point(&hm, &hr); hpios_msgxlock_lock(&msgx_lock); if (hr.error) { instream_user_open[phm->adapter_index][phm-> obj_index].h_owner = h_owner; phr->error = hr.error; } else { instream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 0; instream_user_open[phm->adapter_index][phm-> obj_index].h_owner = NULL; } } else { HPI_DEBUG_LOG(WARNING, "%p trying to close %d instream %d owned by %p\n", h_owner, phm->adapter_index, phm->obj_index, instream_user_open[phm->adapter_index][phm-> obj_index].h_owner); phr->error = HPI_ERROR_OBJ_NOT_OPEN; } hpios_msgxlock_unlock(&msgx_lock); } static void outstream_open(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { struct hpi_message hm; struct hpi_response hr; hpi_init_response(phr, HPI_OBJ_OSTREAM, HPI_OSTREAM_OPEN, 0); hpios_msgxlock_lock(&msgx_lock); if (outstream_user_open[phm->adapter_index][phm->obj_index].open_flag) phr->error = HPI_ERROR_OBJ_ALREADY_OPEN; else if (rESP_HPI_OSTREAM_OPEN[phm->adapter_index] [phm->obj_index].h.error) memcpy(phr, &rESP_HPI_OSTREAM_OPEN[phm->adapter_index][phm-> obj_index], sizeof(rESP_HPI_OSTREAM_OPEN[0][0])); else { outstream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 1; hpios_msgxlock_unlock(&msgx_lock); /* issue a reset */ hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_RESET); hm.adapter_index = phm->adapter_index; hm.obj_index = phm->obj_index; hw_entry_point(&hm, &hr); hpios_msgxlock_lock(&msgx_lock); if (hr.error) { outstream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 0; phr->error = hr.error; } else { outstream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 1; outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner = h_owner; memcpy(phr, &rESP_HPI_OSTREAM_OPEN[phm->adapter_index] [phm->obj_index], sizeof(rESP_HPI_OSTREAM_OPEN[0][0])); } } hpios_msgxlock_unlock(&msgx_lock); } static void outstream_close(struct hpi_message *phm, struct hpi_response *phr, void *h_owner) { struct hpi_message hm; struct hpi_response hr; hpi_init_response(phr, HPI_OBJ_OSTREAM, HPI_OSTREAM_CLOSE, 0); hpios_msgxlock_lock(&msgx_lock); if (h_owner == outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner) { /* HPI_DEBUG_LOG(INFO,"closing adapter %d " "outstream %d owned by %p\n", phm->wAdapterIndex, phm->wObjIndex, hOwner); */ outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner = NULL; hpios_msgxlock_unlock(&msgx_lock); /* issue a reset */ hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_RESET); hm.adapter_index = phm->adapter_index; hm.obj_index = phm->obj_index; hw_entry_point(&hm, &hr); hpios_msgxlock_lock(&msgx_lock); if (hr.error) { outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner = h_owner; phr->error = hr.error; } else { outstream_user_open[phm->adapter_index][phm-> obj_index].open_flag = 0; outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner = NULL; } } else { HPI_DEBUG_LOG(WARNING, "%p trying to close %d outstream %d owned by %p\n", h_owner, phm->adapter_index, phm->obj_index, outstream_user_open[phm->adapter_index][phm-> obj_index].h_owner); phr->error = HPI_ERROR_OBJ_NOT_OPEN; } hpios_msgxlock_unlock(&msgx_lock); } static u16 adapter_prepare(u16 adapter) { struct hpi_message hm; struct hpi_response hr; /* Open the adapter and streams */ u16 i; /* call to HPI_ADAPTER_OPEN */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_OPEN); hm.adapter_index = adapter; hw_entry_point(&hm, &hr); memcpy(&rESP_HPI_ADAPTER_OPEN[adapter], &hr, sizeof(rESP_HPI_ADAPTER_OPEN[0])); if (hr.error) return hr.error; /* call to HPI_ADAPTER_GET_INFO */ hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_INFO); hm.adapter_index = adapter; hw_entry_point(&hm, &hr); if (hr.error) return hr.error; aDAPTER_INFO[adapter].num_outstreams = hr.u.ax.info.num_outstreams; aDAPTER_INFO[adapter].num_instreams = hr.u.ax.info.num_instreams; aDAPTER_INFO[adapter].type = hr.u.ax.info.adapter_type; /* call to HPI_OSTREAM_OPEN */ for (i = 0; i < aDAPTER_INFO[adapter].num_outstreams; i++) { hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_OPEN); hm.adapter_index = adapter; hm.obj_index = i; hw_entry_point(&hm, &hr); memcpy(&rESP_HPI_OSTREAM_OPEN[adapter][i], &hr, sizeof(rESP_HPI_OSTREAM_OPEN[0][0])); outstream_user_open[adapter][i].open_flag = 0; outstream_user_open[adapter][i].h_owner = NULL; } /* call to HPI_ISTREAM_OPEN */ for (i = 0; i < aDAPTER_INFO[adapter].num_instreams; i++) { hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_OPEN); hm.adapter_index = adapter; hm.obj_index = i; hw_entry_point(&hm, &hr); memcpy(&rESP_HPI_ISTREAM_OPEN[adapter][i], &hr, sizeof(rESP_HPI_ISTREAM_OPEN[0][0])); instream_user_open[adapter][i].open_flag = 0; instream_user_open[adapter][i].h_owner = NULL; } /* call to HPI_MIXER_OPEN */ hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_OPEN); hm.adapter_index = adapter; hw_entry_point(&hm, &hr); memcpy(&rESP_HPI_MIXER_OPEN[adapter], &hr, sizeof(rESP_HPI_MIXER_OPEN[0])); return 0; } static void HPIMSGX__reset(u16 adapter_index) { int i; u16 adapter; struct hpi_response hr; if (adapter_index == HPIMSGX_ALLADAPTERS) { for (adapter = 0; adapter < HPI_MAX_ADAPTERS; adapter++) { hpi_init_response(&hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_OPEN, HPI_ERROR_BAD_ADAPTER); memcpy(&rESP_HPI_ADAPTER_OPEN[adapter], &hr, sizeof(rESP_HPI_ADAPTER_OPEN[adapter])); hpi_init_response(&hr, HPI_OBJ_MIXER, HPI_MIXER_OPEN, HPI_ERROR_INVALID_OBJ); memcpy(&rESP_HPI_MIXER_OPEN[adapter], &hr, sizeof(rESP_HPI_MIXER_OPEN[adapter])); for (i = 0; i < HPI_MAX_STREAMS; i++) { hpi_init_response(&hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_OPEN, HPI_ERROR_INVALID_OBJ); memcpy(&rESP_HPI_OSTREAM_OPEN[adapter][i], &hr, sizeof(rESP_HPI_OSTREAM_OPEN[adapter] [i])); hpi_init_response(&hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_OPEN, HPI_ERROR_INVALID_OBJ); memcpy(&rESP_HPI_ISTREAM_OPEN[adapter][i], &hr, sizeof(rESP_HPI_ISTREAM_OPEN[adapter] [i])); } } } else if (adapter_index < HPI_MAX_ADAPTERS) { rESP_HPI_ADAPTER_OPEN[adapter_index].h.error = HPI_ERROR_BAD_ADAPTER; rESP_HPI_MIXER_OPEN[adapter_index].h.error = HPI_ERROR_INVALID_OBJ; for (i = 0; i < HPI_MAX_STREAMS; i++) { rESP_HPI_OSTREAM_OPEN[adapter_index][i].h.error = HPI_ERROR_INVALID_OBJ; rESP_HPI_ISTREAM_OPEN[adapter_index][i].h.error = HPI_ERROR_INVALID_OBJ; } } } static u16 HPIMSGX__init(struct hpi_message *phm, /* HPI_SUBSYS_CREATE_ADAPTER structure with */ /* resource list or NULL=find all */ struct hpi_response *phr /* response from HPI_ADAPTER_GET_INFO */ ) { hpi_handler_func *entry_point_func; struct hpi_response hr; /* Init response here so we can pass in previous adapter list */ hpi_init_response(&hr, phm->object, phm->function, HPI_ERROR_INVALID_OBJ); entry_point_func = hpi_lookup_entry_point_function(phm->u.s.resource.r.pci); if (entry_point_func) { HPI_DEBUG_MESSAGE(DEBUG, phm); entry_point_func(phm, &hr); } else { phr->error = HPI_ERROR_PROCESSING_MESSAGE; return phr->error; } if (hr.error == 0) { /* the adapter was created successfully save the mapping for future use */ hpi_entry_points[hr.u.s.adapter_index] = entry_point_func; /* prepare adapter (pre-open streams etc.) */ HPI_DEBUG_LOG(DEBUG, "HPI_SUBSYS_CREATE_ADAPTER successful," " preparing adapter\n"); adapter_prepare(hr.u.s.adapter_index); } memcpy(phr, &hr, hr.size); return phr->error; } static void HPIMSGX__cleanup(u16 adapter_index, void *h_owner) { int i, adapter, adapter_limit; if (!h_owner) return; if (adapter_index == HPIMSGX_ALLADAPTERS) { adapter = 0; adapter_limit = HPI_MAX_ADAPTERS; } else { adapter = adapter_index; adapter_limit = adapter + 1; } for (; adapter < adapter_limit; adapter++) { /* printk(KERN_INFO "Cleanup adapter #%d\n",wAdapter); */ for (i = 0; i < HPI_MAX_STREAMS; i++) { if (h_owner == outstream_user_open[adapter][i].h_owner) { struct hpi_message hm; struct hpi_response hr; HPI_DEBUG_LOG(DEBUG, "Close adapter %d ostream %d\n", adapter, i); hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_RESET); hm.adapter_index = (u16)adapter; hm.obj_index = (u16)i; hw_entry_point(&hm, &hr); hm.function = HPI_OSTREAM_HOSTBUFFER_FREE; hw_entry_point(&hm, &hr); hm.function = HPI_OSTREAM_GROUP_RESET; hw_entry_point(&hm, &hr); outstream_user_open[adapter][i].open_flag = 0; outstream_user_open[adapter][i].h_owner = NULL; } if (h_owner == instream_user_open[adapter][i].h_owner) { struct hpi_message hm; struct hpi_response hr; HPI_DEBUG_LOG(DEBUG, "Close adapter %d istream %d\n", adapter, i); hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_RESET); hm.adapter_index = (u16)adapter; hm.obj_index = (u16)i; hw_entry_point(&hm, &hr); hm.function = HPI_ISTREAM_HOSTBUFFER_FREE; hw_entry_point(&hm, &hr); hm.function = HPI_ISTREAM_GROUP_RESET; hw_entry_point(&hm, &hr); instream_user_open[adapter][i].open_flag = 0; instream_user_open[adapter][i].h_owner = NULL; } } } }
linux-master
sound/pci/asihpi/hpimsgx.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> Hardware Programming Interface (HPI) for AudioScience ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. These PCI and PCIe bus adapters are based on a TMS320C6205 PCI bus mastering DSP, and (except ASI50xx) TI TMS320C6xxx floating point DSP Exported function: void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) (C) Copyright AudioScience Inc. 1998-2010 *******************************************************************************/ #define SOURCEFILE_NAME "hpi6205.c" #include "hpi_internal.h" #include "hpimsginit.h" #include "hpidebug.h" #include "hpi6205.h" #include "hpidspcd.h" #include "hpicmn.h" /*****************************************************************************/ /* HPI6205 specific error codes */ #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ /* operational/messaging errors */ #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 /* initialization/bootload errors */ #define HPI6205_ERROR_6205_NO_IRQ 1002 #define HPI6205_ERROR_6205_INIT_FAILED 1003 #define HPI6205_ERROR_6205_REG 1006 #define HPI6205_ERROR_6205_DSPPAGE 1007 #define HPI6205_ERROR_C6713_HPIC 1009 #define HPI6205_ERROR_C6713_HPIA 1010 #define HPI6205_ERROR_C6713_PLL 1011 #define HPI6205_ERROR_DSP_INTMEM 1012 #define HPI6205_ERROR_DSP_EXTMEM 1013 #define HPI6205_ERROR_DSP_PLD 1014 #define HPI6205_ERROR_6205_EEPROM 1017 #define HPI6205_ERROR_DSP_EMIF1 1018 #define HPI6205_ERROR_DSP_EMIF2 1019 #define HPI6205_ERROR_DSP_EMIF3 1020 #define HPI6205_ERROR_DSP_EMIF4 1021 /*****************************************************************************/ /* for C6205 PCI i/f */ /* Host Status Register (HSR) bitfields */ #define C6205_HSR_INTSRC 0x01 #define C6205_HSR_INTAVAL 0x02 #define C6205_HSR_INTAM 0x04 #define C6205_HSR_CFGERR 0x08 #define C6205_HSR_EEREAD 0x10 /* Host-to-DSP Control Register (HDCR) bitfields */ #define C6205_HDCR_WARMRESET 0x01 #define C6205_HDCR_DSPINT 0x02 #define C6205_HDCR_PCIBOOT 0x04 /* DSP Page Register (DSPP) bitfields, */ /* defines 4 Mbyte page that BAR0 points to */ #define C6205_DSPP_MAP1 0x400 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. * BAR1 maps to non-prefetchable 8 Mbyte memory block * of DSP memory mapped registers (starting at 0x01800000). * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this * needs to be added to the BAR1 base address set in the PCI config reg */ #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) /* used to control LED (revA) and reset C6713 (revB) */ #define C6205_BAR0_TIMER1_CTL (0x01980000L) /* For first 6713 in CE1 space, using DA17,16,2 */ #define HPICL_ADDR 0x01400000L #define HPICH_ADDR 0x01400004L #define HPIAL_ADDR 0x01410000L #define HPIAH_ADDR 0x01410004L #define HPIDIL_ADDR 0x01420000L #define HPIDIH_ADDR 0x01420004L #define HPIDL_ADDR 0x01430000L #define HPIDH_ADDR 0x01430004L #define C6713_EMIF_GCTL 0x01800000 #define C6713_EMIF_CE1 0x01800004 #define C6713_EMIF_CE0 0x01800008 #define C6713_EMIF_CE2 0x01800010 #define C6713_EMIF_CE3 0x01800014 #define C6713_EMIF_SDRAMCTL 0x01800018 #define C6713_EMIF_SDRAMTIMING 0x0180001C #define C6713_EMIF_SDRAMEXT 0x01800020 struct hpi_hw_obj { /* PCI registers */ __iomem u32 *prHSR; __iomem u32 *prHDCR; __iomem u32 *prDSPP; u32 dsp_page; struct consistent_dma_area h_locked_mem; struct bus_master_interface *p_interface_buffer; u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; /* a non-NULL handle means there is an HPI allocated buffer */ struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; /* non-zero size means a buffer exists, may be external */ u32 instream_host_buffer_size[HPI_MAX_STREAMS]; u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; struct consistent_dma_area h_control_cache; struct hpi_control_cache *p_cache; }; /*****************************************************************************/ /* local prototypes */ #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code); static u16 message_response_sequence(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); #define HPI6205_TIMEOUT 1000000 static void subsys_create_adapter(struct hpi_message *phm, struct hpi_response *phr); static void adapter_delete(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static u16 create_adapter_obj(struct hpi_adapter_obj *pao, u32 *pos_error_code); static void delete_adapter_obj(struct hpi_adapter_obj *pao); static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao, u32 message); static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_write(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_start(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_open(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void outstream_reset(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_host_buffer_free(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_read(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static void instream_start(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr); static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, u32 address); static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index, u32 address, u32 data); static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index); static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, u32 address, u32 length); static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, int dsp_index); static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, int dsp_index); static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); /*****************************************************************************/ static void subsys_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_SUBSYS_CREATE_ADAPTER: subsys_create_adapter(phm, phr); break; default: phr->error = HPI_ERROR_INVALID_FUNC; break; } } static void control_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; u16 pending_cache_error = 0; switch (phm->function) { case HPI_CONTROL_GET_STATE: if (pao->has_control_cache) { rmb(); /* make sure we see updates DMAed from DSP */ if (hpi_check_control_cache(phw->p_cache, phm, phr)) { break; } else if (phm->u.c.attribute == HPI_METER_PEAK) { pending_cache_error = HPI_ERROR_CONTROL_CACHING; } } hw_message(pao, phm, phr); if (pending_cache_error && !phr->error) phr->error = pending_cache_error; break; case HPI_CONTROL_GET_INFO: hw_message(pao, phm, phr); break; case HPI_CONTROL_SET_STATE: hw_message(pao, phm, phr); if (pao->has_control_cache) hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr); break; default: phr->error = HPI_ERROR_INVALID_FUNC; break; } } static void adapter_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { switch (phm->function) { case HPI_ADAPTER_DELETE: adapter_delete(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } } static void outstream_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { if (phm->obj_index >= HPI_MAX_STREAMS) { phr->error = HPI_ERROR_INVALID_OBJ_INDEX; HPI_DEBUG_LOG(WARNING, "Message referencing invalid stream %d " "on adapter index %d\n", phm->obj_index, phm->adapter_index); return; } switch (phm->function) { case HPI_OSTREAM_WRITE: outstream_write(pao, phm, phr); break; case HPI_OSTREAM_GET_INFO: outstream_get_info(pao, phm, phr); break; case HPI_OSTREAM_HOSTBUFFER_ALLOC: outstream_host_buffer_allocate(pao, phm, phr); break; case HPI_OSTREAM_HOSTBUFFER_GET_INFO: outstream_host_buffer_get_info(pao, phm, phr); break; case HPI_OSTREAM_HOSTBUFFER_FREE: outstream_host_buffer_free(pao, phm, phr); break; case HPI_OSTREAM_START: outstream_start(pao, phm, phr); break; case HPI_OSTREAM_OPEN: outstream_open(pao, phm, phr); break; case HPI_OSTREAM_RESET: outstream_reset(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } } static void instream_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { if (phm->obj_index >= HPI_MAX_STREAMS) { phr->error = HPI_ERROR_INVALID_OBJ_INDEX; HPI_DEBUG_LOG(WARNING, "Message referencing invalid stream %d " "on adapter index %d\n", phm->obj_index, phm->adapter_index); return; } switch (phm->function) { case HPI_ISTREAM_READ: instream_read(pao, phm, phr); break; case HPI_ISTREAM_GET_INFO: instream_get_info(pao, phm, phr); break; case HPI_ISTREAM_HOSTBUFFER_ALLOC: instream_host_buffer_allocate(pao, phm, phr); break; case HPI_ISTREAM_HOSTBUFFER_GET_INFO: instream_host_buffer_get_info(pao, phm, phr); break; case HPI_ISTREAM_HOSTBUFFER_FREE: instream_host_buffer_free(pao, phm, phr); break; case HPI_ISTREAM_START: instream_start(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } } /*****************************************************************************/ /** Entry point to this HPI backend * All calls to the HPI start here */ static void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { if (pao && (pao->dsp_crashed >= 10) && (phm->function != HPI_ADAPTER_DEBUG_READ)) { /* allow last resort debug read even after crash */ hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_DSP_HARDWARE); HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object, phm->function); return; } /* Init default response */ if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) phr->error = HPI_ERROR_PROCESSING_MESSAGE; HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); switch (phm->type) { case HPI_TYPE_REQUEST: switch (phm->object) { case HPI_OBJ_SUBSYSTEM: subsys_message(pao, phm, phr); break; case HPI_OBJ_ADAPTER: adapter_message(pao, phm, phr); break; case HPI_OBJ_CONTROL: control_message(pao, phm, phr); break; case HPI_OBJ_OSTREAM: outstream_message(pao, phm, phr); break; case HPI_OBJ_ISTREAM: instream_message(pao, phm, phr); break; default: hw_message(pao, phm, phr); break; } break; default: phr->error = HPI_ERROR_INVALID_TYPE; break; } } void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) { struct hpi_adapter_obj *pao = NULL; if (phm->object != HPI_OBJ_SUBSYSTEM) { /* normal messages must have valid adapter index */ pao = hpi_find_adapter(phm->adapter_index); } else { /* subsys messages don't address an adapter */ phr->error = HPI_ERROR_INVALID_OBJ_INDEX; return; } if (pao) _HPI_6205(pao, phm, phr); else hpi_init_response(phr, phm->object, phm->function, HPI_ERROR_BAD_ADAPTER_NUMBER); } /*****************************************************************************/ /* SUBSYSTEM */ /** Create an adapter object and initialise it based on resource information * passed in the message * *** NOTE - you cannot use this function AND the FindAdapters function at the * same time, the application must use only one of them to get the adapters *** */ static void subsys_create_adapter(struct hpi_message *phm, struct hpi_response *phr) { /* create temp adapter obj, because we don't know what index yet */ struct hpi_adapter_obj ao; u32 os_error_code; u16 err; HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); memset(&ao, 0, sizeof(ao)); ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); if (!ao.priv) { HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); phr->error = HPI_ERROR_MEMORY_ALLOC; return; } ao.pci = *phm->u.s.resource.r.pci; err = create_adapter_obj(&ao, &os_error_code); if (err) { delete_adapter_obj(&ao); if (err >= HPI_ERROR_BACKEND_BASE) { phr->error = HPI_ERROR_DSP_BOOTLOAD; phr->specific_error = err; } else { phr->error = err; } phr->u.s.data = os_error_code; return; } phr->u.s.adapter_type = ao.type; phr->u.s.adapter_index = ao.index; phr->error = 0; } /** delete an adapter - required by WDM driver */ static void adapter_delete(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw; if (!pao) { phr->error = HPI_ERROR_INVALID_OBJ_INDEX; return; } phw = pao->priv; /* reset adapter h/w */ /* Reset C6713 #1 */ boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); /* reset C6205 */ iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); delete_adapter_obj(pao); hpi_delete_adapter(pao); phr->error = 0; } /** Create adapter object allocate buffers, bootload DSPs, initialise control cache */ static u16 create_adapter_obj(struct hpi_adapter_obj *pao, u32 *pos_error_code) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface; u32 phys_addr; int i; u16 err; /* init error reporting */ pao->dsp_crashed = 0; for (i = 0; i < HPI_MAX_STREAMS; i++) phw->flag_outstream_just_reset[i] = 1; /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ phw->prHSR = pao->pci.ap_mem_base[1] + C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); phw->prHDCR = pao->pci.ap_mem_base[1] + C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); phw->prDSPP = pao->pci.ap_mem_base[1] + C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); pao->has_control_cache = 0; if (hpios_locked_mem_alloc(&phw->h_locked_mem, sizeof(struct bus_master_interface), pao->pci.pci_dev)) phw->p_interface_buffer = NULL; else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, (void *)&phw->p_interface_buffer)) phw->p_interface_buffer = NULL; HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", phw->p_interface_buffer); if (phw->p_interface_buffer) { memset((void *)phw->p_interface_buffer, 0, sizeof(struct bus_master_interface)); phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; } err = adapter_boot_load_dsp(pao, pos_error_code); if (err) { HPI_DEBUG_LOG(ERROR, "DSP code load failed\n"); /* no need to clean up as SubSysCreateAdapter */ /* calls DeleteAdapter on error. */ return err; } HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); /* allow boot load even if mem alloc wont work */ if (!phw->p_interface_buffer) return HPI_ERROR_MEMORY_ALLOC; interface = phw->p_interface_buffer; /* make sure the DSP has started ok */ if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); return HPI6205_ERROR_6205_INIT_FAILED; } /* Note that *pao, *phw are zeroed after allocation, * so pointers and flags are NULL by default. * Allocate bus mastering control cache buffer and tell the DSP about it */ if (interface->control_cache.number_of_controls) { u8 *p_control_cache_virtual; err = hpios_locked_mem_alloc(&phw->h_control_cache, interface->control_cache.size_in_bytes, pao->pci.pci_dev); if (!err) err = hpios_locked_mem_get_virt_addr(&phw-> h_control_cache, (void *)&p_control_cache_virtual); if (!err) { memset(p_control_cache_virtual, 0, interface->control_cache.size_in_bytes); phw->p_cache = hpi_alloc_control_cache(interface-> control_cache.number_of_controls, interface->control_cache.size_in_bytes, p_control_cache_virtual); if (!phw->p_cache) err = HPI_ERROR_MEMORY_ALLOC; } if (!err) { err = hpios_locked_mem_get_phys_addr(&phw-> h_control_cache, &phys_addr); interface->control_cache.physical_address32 = phys_addr; } if (!err) pao->has_control_cache = 1; else { if (hpios_locked_mem_valid(&phw->h_control_cache)) hpios_locked_mem_free(&phw->h_control_cache); pao->has_control_cache = 0; } } send_dsp_command(phw, H620_HIF_IDLE); { struct hpi_message hm; struct hpi_response hr; HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); memset(&hm, 0, sizeof(hm)); /* wAdapterIndex == version == 0 */ hm.type = HPI_TYPE_REQUEST; hm.size = sizeof(hm); hm.object = HPI_OBJ_ADAPTER; hm.function = HPI_ADAPTER_GET_INFO; memset(&hr, 0, sizeof(hr)); hr.size = sizeof(hr); err = message_response_sequence(pao, &hm, &hr); if (err) { HPI_DEBUG_LOG(ERROR, "message transport error %d\n", err); return err; } if (hr.error) return hr.error; pao->type = hr.u.ax.info.adapter_type; pao->index = hr.u.ax.info.adapter_index; HPI_DEBUG_LOG(VERBOSE, "got adapter info type %x index %d serial %d\n", hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, hr.u.ax.info.serial_number); } if (phw->p_cache) phw->p_cache->adap_idx = pao->index; HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); pao->irq_query_and_clear = adapter_irq_query_and_clear; pao->instream_host_buffer_status = phw->p_interface_buffer->instream_host_buffer_status; pao->outstream_host_buffer_status = phw->p_interface_buffer->outstream_host_buffer_status; return hpi_add_adapter(pao); } /** Free memory areas allocated by adapter * this routine is called from AdapterDelete, * and SubSysCreateAdapter if duplicate index */ static void delete_adapter_obj(struct hpi_adapter_obj *pao) { struct hpi_hw_obj *phw = pao->priv; int i; if (hpios_locked_mem_valid(&phw->h_control_cache)) { hpios_locked_mem_free(&phw->h_control_cache); hpi_free_control_cache(phw->p_cache); } if (hpios_locked_mem_valid(&phw->h_locked_mem)) { hpios_locked_mem_free(&phw->h_locked_mem); phw->p_interface_buffer = NULL; } for (i = 0; i < HPI_MAX_STREAMS; i++) if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { hpios_locked_mem_free(&phw->instream_host_buffers[i]); /*?phw->InStreamHostBuffers[i] = NULL; */ phw->instream_host_buffer_size[i] = 0; } for (i = 0; i < HPI_MAX_STREAMS; i++) if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { hpios_locked_mem_free(&phw->outstream_host_buffers [i]); phw->outstream_host_buffer_size[i] = 0; } kfree(phw); } /*****************************************************************************/ /* Adapter functions */ static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao, u32 message) { struct hpi_hw_obj *phw = pao->priv; u32 hsr = 0; hsr = ioread32(phw->prHSR); if (hsr & C6205_HSR_INTSRC) { /* reset the interrupt from the DSP */ iowrite32(C6205_HSR_INTSRC, phw->prHSR); return HPI_IRQ_MIXER; } return HPI_IRQ_NONE; } /*****************************************************************************/ /* OutStream Host buffer functions */ /** Allocate or attach buffer for busmastering */ static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { u16 err = 0; u32 command = phm->u.d.u.buffer.command; struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; hpi_init_response(phr, phm->object, phm->function, 0); if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { /* ALLOC phase, allocate a buffer with power of 2 size, get its bus address for PCI bus mastering */ phm->u.d.u.buffer.buffer_size = roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); /* return old size and allocated size, so caller can detect change */ phr->u.d.u.stream_info.data_available = phw->outstream_host_buffer_size[phm->obj_index]; phr->u.d.u.stream_info.buffer_size = phm->u.d.u.buffer.buffer_size; if (phw->outstream_host_buffer_size[phm->obj_index] == phm->u.d.u.buffer.buffer_size) { /* Same size, no action required */ return; } if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> obj_index])) hpios_locked_mem_free(&phw->outstream_host_buffers [phm->obj_index]); err = hpios_locked_mem_alloc(&phw->outstream_host_buffers [phm->obj_index], phm->u.d.u.buffer.buffer_size, pao->pci.pci_dev); if (err) { phr->error = HPI_ERROR_INVALID_DATASIZE; phw->outstream_host_buffer_size[phm->obj_index] = 0; return; } err = hpios_locked_mem_get_phys_addr (&phw->outstream_host_buffers[phm->obj_index], &phm->u.d.u.buffer.pci_address); /* get the phys addr into msg for single call alloc caller * needs to do this for split alloc (or use the same message) * return the phy address for split alloc in the respose too */ phr->u.d.u.stream_info.auxiliary_data_available = phm->u.d.u.buffer.pci_address; if (err) { hpios_locked_mem_free(&phw->outstream_host_buffers [phm->obj_index]); phw->outstream_host_buffer_size[phm->obj_index] = 0; phr->error = HPI_ERROR_MEMORY_ALLOC; return; } } if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { /* GRANT phase. Set up the BBM status, tell the DSP about the buffer so it can start using BBM. */ struct hpi_hostbuffer_status *status; if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. buffer_size - 1)) { HPI_DEBUG_LOG(ERROR, "Buffer size must be 2^N not %d\n", phm->u.d.u.buffer.buffer_size); phr->error = HPI_ERROR_INVALID_DATASIZE; return; } phw->outstream_host_buffer_size[phm->obj_index] = phm->u.d.u.buffer.buffer_size; status = &interface->outstream_host_buffer_status[phm-> obj_index]; status->samples_processed = 0; status->stream_state = HPI_STATE_STOPPED; status->dsp_index = 0; status->host_index = status->dsp_index; status->size_in_bytes = phm->u.d.u.buffer.buffer_size; status->auxiliary_data_available = 0; hw_message(pao, phm, phr); if (phr->error && hpios_locked_mem_valid(&phw-> outstream_host_buffers[phm->obj_index])) { hpios_locked_mem_free(&phw->outstream_host_buffers [phm->obj_index]); phw->outstream_host_buffer_size[phm->obj_index] = 0; } } } static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; u8 *p_bbm_data; if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> obj_index])) { if (hpios_locked_mem_get_virt_addr(&phw-> outstream_host_buffers[phm->obj_index], (void *)&p_bbm_data)) { phr->error = HPI_ERROR_INVALID_OPERATION; return; } status = &interface->outstream_host_buffer_status[phm-> obj_index]; hpi_init_response(phr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; phr->u.d.u.hostbuffer_info.p_status = status; } else { hpi_init_response(phr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_GET_INFO, HPI_ERROR_INVALID_OPERATION); } } static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; u32 command = phm->u.d.u.buffer.command; if (phw->outstream_host_buffer_size[phm->obj_index]) { if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { phw->outstream_host_buffer_size[phm->obj_index] = 0; hw_message(pao, phm, phr); /* Tell adapter to stop using the host buffer. */ } if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_FREE) hpios_locked_mem_free(&phw->outstream_host_buffers [phm->obj_index]); } /* Should HPI_ERROR_INVALID_OPERATION be returned if no host buffer is allocated? */ else hpi_init_response(phr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_FREE, 0); } static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) { return status->size_in_bytes - (status->host_index - status->dsp_index); } static void outstream_write(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; u32 space_available; if (!phw->outstream_host_buffer_size[phm->obj_index]) { /* there is no BBM buffer, write via message */ hw_message(pao, phm, phr); return; } hpi_init_response(phr, phm->object, phm->function, 0); status = &interface->outstream_host_buffer_status[phm->obj_index]; space_available = outstream_get_space_available(status); if (space_available < phm->u.d.u.data.data_size) { phr->error = HPI_ERROR_INVALID_DATASIZE; return; } /* HostBuffers is used to indicate host buffer is internally allocated. otherwise, assumed external, data written externally */ if (phm->u.d.u.data.pb_data && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> obj_index])) { u8 *p_bbm_data; u32 l_first_write; u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; if (hpios_locked_mem_get_virt_addr(&phw-> outstream_host_buffers[phm->obj_index], (void *)&p_bbm_data)) { phr->error = HPI_ERROR_INVALID_OPERATION; return; } /* either all data, or enough to fit from current to end of BBM buffer */ l_first_write = min(phm->u.d.u.data.data_size, status->size_in_bytes - (status->host_index & (status->size_in_bytes - 1))); memcpy(p_bbm_data + (status->host_index & (status->size_in_bytes - 1)), p_app_data, l_first_write); /* remaining data if any */ memcpy(p_bbm_data, p_app_data + l_first_write, phm->u.d.u.data.data_size - l_first_write); } /* * This version relies on the DSP code triggering an OStream buffer * update immediately following a SET_FORMAT call. The host has * already written data into the BBM buffer, but the DSP won't know * about it until dwHostIndex is adjusted. */ if (phw->flag_outstream_just_reset[phm->obj_index]) { /* Format can only change after reset. Must tell DSP. */ u16 function = phm->function; phw->flag_outstream_just_reset[phm->obj_index] = 0; phm->function = HPI_OSTREAM_SET_FORMAT; hw_message(pao, phm, phr); /* send the format to the DSP */ phm->function = function; if (phr->error) return; } status->host_index += phm->u.d.u.data.data_size; } static void outstream_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; if (!phw->outstream_host_buffer_size[phm->obj_index]) { hw_message(pao, phm, phr); return; } hpi_init_response(phr, phm->object, phm->function, 0); status = &interface->outstream_host_buffer_status[phm->obj_index]; phr->u.d.u.stream_info.state = (u16)status->stream_state; phr->u.d.u.stream_info.samples_transferred = status->samples_processed; phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; phr->u.d.u.stream_info.data_available = status->size_in_bytes - outstream_get_space_available(status); phr->u.d.u.stream_info.auxiliary_data_available = status->auxiliary_data_available; } static void outstream_start(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { hw_message(pao, phm, phr); } static void outstream_reset(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; phw->flag_outstream_just_reset[phm->obj_index] = 1; hw_message(pao, phm, phr); } static void outstream_open(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { outstream_reset(pao, phm, phr); } /*****************************************************************************/ /* InStream Host buffer functions */ static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { u16 err = 0; u32 command = phm->u.d.u.buffer.command; struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; hpi_init_response(phr, phm->object, phm->function, 0); if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { phm->u.d.u.buffer.buffer_size = roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); phr->u.d.u.stream_info.data_available = phw->instream_host_buffer_size[phm->obj_index]; phr->u.d.u.stream_info.buffer_size = phm->u.d.u.buffer.buffer_size; if (phw->instream_host_buffer_size[phm->obj_index] == phm->u.d.u.buffer.buffer_size) { /* Same size, no action required */ return; } if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> obj_index])) hpios_locked_mem_free(&phw->instream_host_buffers [phm->obj_index]); err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> obj_index], phm->u.d.u.buffer.buffer_size, pao->pci.pci_dev); if (err) { phr->error = HPI_ERROR_INVALID_DATASIZE; phw->instream_host_buffer_size[phm->obj_index] = 0; return; } err = hpios_locked_mem_get_phys_addr (&phw->instream_host_buffers[phm->obj_index], &phm->u.d.u.buffer.pci_address); /* get the phys addr into msg for single call alloc. Caller needs to do this for split alloc so return the phy address */ phr->u.d.u.stream_info.auxiliary_data_available = phm->u.d.u.buffer.pci_address; if (err) { hpios_locked_mem_free(&phw->instream_host_buffers [phm->obj_index]); phw->instream_host_buffer_size[phm->obj_index] = 0; phr->error = HPI_ERROR_MEMORY_ALLOC; return; } } if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { struct hpi_hostbuffer_status *status; if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. buffer_size - 1)) { HPI_DEBUG_LOG(ERROR, "Buffer size must be 2^N not %d\n", phm->u.d.u.buffer.buffer_size); phr->error = HPI_ERROR_INVALID_DATASIZE; return; } phw->instream_host_buffer_size[phm->obj_index] = phm->u.d.u.buffer.buffer_size; status = &interface->instream_host_buffer_status[phm-> obj_index]; status->samples_processed = 0; status->stream_state = HPI_STATE_STOPPED; status->dsp_index = 0; status->host_index = status->dsp_index; status->size_in_bytes = phm->u.d.u.buffer.buffer_size; status->auxiliary_data_available = 0; hw_message(pao, phm, phr); if (phr->error && hpios_locked_mem_valid(&phw-> instream_host_buffers[phm->obj_index])) { hpios_locked_mem_free(&phw->instream_host_buffers [phm->obj_index]); phw->instream_host_buffer_size[phm->obj_index] = 0; } } } static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; u8 *p_bbm_data; if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> obj_index])) { if (hpios_locked_mem_get_virt_addr(&phw-> instream_host_buffers[phm->obj_index], (void *)&p_bbm_data)) { phr->error = HPI_ERROR_INVALID_OPERATION; return; } status = &interface->instream_host_buffer_status[phm-> obj_index]; hpi_init_response(phr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; phr->u.d.u.hostbuffer_info.p_status = status; } else { hpi_init_response(phr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_GET_INFO, HPI_ERROR_INVALID_OPERATION); } } static void instream_host_buffer_free(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; u32 command = phm->u.d.u.buffer.command; if (phw->instream_host_buffer_size[phm->obj_index]) { if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { phw->instream_host_buffer_size[phm->obj_index] = 0; hw_message(pao, phm, phr); } if (command == HPI_BUFFER_CMD_EXTERNAL || command == HPI_BUFFER_CMD_INTERNAL_FREE) hpios_locked_mem_free(&phw->instream_host_buffers [phm->obj_index]); } else { /* Should HPI_ERROR_INVALID_OPERATION be returned if no host buffer is allocated? */ hpi_init_response(phr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_FREE, 0); } } static void instream_start(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { hw_message(pao, phm, phr); } static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) { return status->dsp_index - status->host_index; } static void instream_read(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; u32 data_available; u8 *p_bbm_data; u32 l_first_read; u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; if (!phw->instream_host_buffer_size[phm->obj_index]) { hw_message(pao, phm, phr); return; } hpi_init_response(phr, phm->object, phm->function, 0); status = &interface->instream_host_buffer_status[phm->obj_index]; data_available = instream_get_bytes_available(status); if (data_available < phm->u.d.u.data.data_size) { phr->error = HPI_ERROR_INVALID_DATASIZE; return; } if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> obj_index])) { if (hpios_locked_mem_get_virt_addr(&phw-> instream_host_buffers[phm->obj_index], (void *)&p_bbm_data)) { phr->error = HPI_ERROR_INVALID_OPERATION; return; } /* either all data, or enough to fit from current to end of BBM buffer */ l_first_read = min(phm->u.d.u.data.data_size, status->size_in_bytes - (status->host_index & (status->size_in_bytes - 1))); memcpy(p_app_data, p_bbm_data + (status->host_index & (status->size_in_bytes - 1)), l_first_read); /* remaining data if any */ memcpy(p_app_data + l_first_read, p_bbm_data, phm->u.d.u.data.data_size - l_first_read); } status->host_index += phm->u.d.u.data.data_size; } static void instream_get_info(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; struct hpi_hostbuffer_status *status; if (!phw->instream_host_buffer_size[phm->obj_index]) { hw_message(pao, phm, phr); return; } status = &interface->instream_host_buffer_status[phm->obj_index]; hpi_init_response(phr, phm->object, phm->function, 0); phr->u.d.u.stream_info.state = (u16)status->stream_state; phr->u.d.u.stream_info.samples_transferred = status->samples_processed; phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; phr->u.d.u.stream_info.data_available = instream_get_bytes_available(status); phr->u.d.u.stream_info.auxiliary_data_available = status->auxiliary_data_available; } /*****************************************************************************/ /* LOW-LEVEL */ #define HPI6205_MAX_FILES_TO_LOAD 2 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code) { struct hpi_hw_obj *phw = pao->priv; struct dsp_code dsp_code; u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; u32 temp; int dsp = 0, i = 0; u16 err = 0; boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); boot_code_id[1] = pao->pci.pci_dev->subsystem_device; boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]); /* fix up cases where bootcode id[1] != subsys id */ switch (boot_code_id[1]) { case HPI_ADAPTER_FAMILY_ASI(0x5000): boot_code_id[0] = boot_code_id[1]; boot_code_id[1] = 0; break; case HPI_ADAPTER_FAMILY_ASI(0x5300): case HPI_ADAPTER_FAMILY_ASI(0x5400): case HPI_ADAPTER_FAMILY_ASI(0x6300): boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); break; case HPI_ADAPTER_FAMILY_ASI(0x5500): case HPI_ADAPTER_FAMILY_ASI(0x5600): case HPI_ADAPTER_FAMILY_ASI(0x6500): boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); break; case HPI_ADAPTER_FAMILY_ASI(0x8800): boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); break; default: break; } /* reset DSP by writing a 1 to the WARMRESET bit */ temp = C6205_HDCR_WARMRESET; iowrite32(temp, phw->prHDCR); hpios_delay_micro_seconds(1000); /* check that PCI i/f was configured by EEPROM */ temp = ioread32(phw->prHSR); if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != C6205_HSR_EEREAD) return HPI6205_ERROR_6205_EEPROM; temp |= 0x04; /* disable PINTA interrupt */ iowrite32(temp, phw->prHSR); /* check control register reports PCI boot mode */ temp = ioread32(phw->prHDCR); if (!(temp & C6205_HDCR_PCIBOOT)) return HPI6205_ERROR_6205_REG; /* try writing a few numbers to the DSP page register */ /* and reading them back. */ temp = 3; iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE; temp = 2; iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE; temp = 1; iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE; /* reset DSP page to the correct number */ temp = 0; iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE; phw->dsp_page = 0; /* release 6713 from reset before 6205 is bootloaded. This ensures that the EMIF is inactive, and the 6713 HPI gets the correct bootmode etc */ if (boot_code_id[1] != 0) { /* DSP 1 is a C6713 */ /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202); hpios_delay_micro_seconds(100); /* Reset the 6713 #1 - revB */ boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); /* value of bit 3 is unknown after DSP reset, other bits shoudl be 0 */ if (0 != (boot_loader_read_mem32(pao, 0, (C6205_BAR0_TIMER1_CTL)) & ~8)) return HPI6205_ERROR_6205_REG; hpios_delay_micro_seconds(100); /* Release C6713 from reset - revB */ boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); if (4 != (boot_loader_read_mem32(pao, 0, (C6205_BAR0_TIMER1_CTL)) & ~8)) return HPI6205_ERROR_6205_REG; hpios_delay_micro_seconds(100); } for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { /* is there a DSP to load? */ if (boot_code_id[dsp] == 0) continue; err = boot_loader_config_emif(pao, dsp); if (err) return err; err = boot_loader_test_internal_memory(pao, dsp); if (err) return err; err = boot_loader_test_external_memory(pao, dsp); if (err) return err; err = boot_loader_test_pld(pao, dsp); if (err) return err; /* write the DSP code down into the DSPs memory */ err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev, &dsp_code, pos_error_code); if (err) return err; while (1) { u32 length; u32 address; u32 type; u32 *pcode; err = hpi_dsp_code_read_word(&dsp_code, &length); if (err) break; if (length == 0xFFFFFFFF) break; /* end of code */ err = hpi_dsp_code_read_word(&dsp_code, &address); if (err) break; err = hpi_dsp_code_read_word(&dsp_code, &type); if (err) break; err = hpi_dsp_code_read_block(length, &dsp_code, &pcode); if (err) break; for (i = 0; i < (int)length; i++) { boot_loader_write_mem32(pao, dsp, address, *pcode); /* dummy read every 4 words */ /* for 6205 advisory 1.4.4 */ if (i % 4 == 0) boot_loader_read_mem32(pao, dsp, address); pcode++; address += 4; } } if (err) { hpi_dsp_code_close(&dsp_code); return err; } /* verify code */ hpi_dsp_code_rewind(&dsp_code); while (1) { u32 length = 0; u32 address = 0; u32 type = 0; u32 *pcode = NULL; u32 data = 0; hpi_dsp_code_read_word(&dsp_code, &length); if (length == 0xFFFFFFFF) break; /* end of code */ hpi_dsp_code_read_word(&dsp_code, &address); hpi_dsp_code_read_word(&dsp_code, &type); hpi_dsp_code_read_block(length, &dsp_code, &pcode); for (i = 0; i < (int)length; i++) { data = boot_loader_read_mem32(pao, dsp, address); if (data != *pcode) { err = 0; break; } pcode++; address += 4; } if (err) break; } hpi_dsp_code_close(&dsp_code); if (err) return err; } /* After bootloading all DSPs, start DSP0 running * The DSP0 code will handle starting and synchronizing with its slaves */ if (phw->p_interface_buffer) { /* we need to tell the card the physical PCI address */ u32 physicalPC_iaddress; struct bus_master_interface *interface = phw->p_interface_buffer; u32 host_mailbox_address_on_dsp; u32 physicalPC_iaddress_verify = 0; int time_out = 10; /* set ack so we know when DSP is ready to go */ /* (dwDspAck will be changed to HIF_RESET) */ interface->dsp_ack = H620_HIF_UNKNOWN; wmb(); /* ensure ack is written before dsp writes back */ err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, &physicalPC_iaddress); /* locate the host mailbox on the DSP. */ host_mailbox_address_on_dsp = 0x80000000; while ((physicalPC_iaddress != physicalPC_iaddress_verify) && time_out--) { boot_loader_write_mem32(pao, 0, host_mailbox_address_on_dsp, physicalPC_iaddress); physicalPC_iaddress_verify = boot_loader_read_mem32(pao, 0, host_mailbox_address_on_dsp); } } HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); /* enable interrupts */ temp = ioread32(phw->prHSR); temp &= ~(u32)C6205_HSR_INTAM; iowrite32(temp, phw->prHSR); /* start code running... */ temp = ioread32(phw->prHDCR); temp |= (u32)C6205_HDCR_DSPINT; iowrite32(temp, phw->prHDCR); /* give the DSP 10ms to start up */ hpios_delay_micro_seconds(10000); return err; } /*****************************************************************************/ /* Bootloader utility functions */ static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, u32 address) { struct hpi_hw_obj *phw = pao->priv; u32 data = 0; __iomem u32 *p_data; if (dsp_index == 0) { /* DSP 0 is always C6205 */ if ((address >= 0x01800000) & (address < 0x02000000)) { /* BAR1 register access */ p_data = pao->pci.ap_mem_base[1] + (address & 0x007fffff) / sizeof(*pao->pci.ap_mem_base[1]); /* HPI_DEBUG_LOG(WARNING, "BAR1 access %08x\n", dwAddress); */ } else { u32 dw4M_page = address >> 22L; if (dw4M_page != phw->dsp_page) { phw->dsp_page = dw4M_page; /* *INDENT OFF* */ iowrite32(phw->dsp_page, phw->prDSPP); /* *INDENT-ON* */ } address &= 0x3fffff; /* address within 4M page */ /* BAR0 memory access */ p_data = pao->pci.ap_mem_base[0] + address / sizeof(u32); } data = ioread32(p_data); } else if (dsp_index == 1) { /* DSP 1 is a C6713 */ u32 lsb; boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); data = (data << 16) | (lsb & 0xFFFF); } return data; } static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index, u32 address, u32 data) { struct hpi_hw_obj *phw = pao->priv; __iomem u32 *p_data; /* u32 dwVerifyData=0; */ if (dsp_index == 0) { /* DSP 0 is always C6205 */ if ((address >= 0x01800000) & (address < 0x02000000)) { /* BAR1 - DSP register access using */ /* Non-prefetchable PCI access */ p_data = pao->pci.ap_mem_base[1] + (address & 0x007fffff) / sizeof(*pao->pci.ap_mem_base[1]); } else { /* BAR0 access - all of DSP memory using */ /* pre-fetchable PCI access */ u32 dw4M_page = address >> 22L; if (dw4M_page != phw->dsp_page) { phw->dsp_page = dw4M_page; /* *INDENT-OFF* */ iowrite32(phw->dsp_page, phw->prDSPP); /* *INDENT-ON* */ } address &= 0x3fffff; /* address within 4M page */ p_data = pao->pci.ap_mem_base[0] + address / sizeof(u32); } iowrite32(data, p_data); } else if (dsp_index == 1) { /* DSP 1 is a C6713 */ boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); /* dummy read every 4 words for 6205 advisory 1.4.4 */ boot_loader_read_mem32(pao, 0, 0); boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); /* dummy read every 4 words for 6205 advisory 1.4.4 */ boot_loader_read_mem32(pao, 0, 0); } } static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) { if (dsp_index == 0) { u32 setting; /* DSP 0 is always C6205 */ /* Set the EMIF */ /* memory map of C6205 */ /* 00000000-0000FFFF 16Kx32 internal program */ /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ /* EMIF config */ /*------------ */ /* Global EMIF control */ boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); #define WS_OFS 28 #define WST_OFS 22 #define WH_OFS 20 #define RS_OFS 16 #define RST_OFS 8 #define MTYPE_OFS 4 #define RH_OFS 0 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ setting = 0x00000030; boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); if (setting != boot_loader_read_mem32(pao, dsp_index, 0x01800008)) return HPI6205_ERROR_DSP_EMIF1; /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ /* which occupies D15..0. 6713 starts at 27MHz, so need */ /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ /* WST should be 71, but 63 is max possible */ setting = (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | (2L << MTYPE_OFS); boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); if (setting != boot_loader_read_mem32(pao, dsp_index, 0x01800004)) return HPI6205_ERROR_DSP_EMIF2; /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ /* which occupies D15..0. 6713 starts at 27MHz, so need */ /* plenty of wait states */ setting = (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | (2L << MTYPE_OFS); boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); if (setting != boot_loader_read_mem32(pao, dsp_index, 0x01800010)) return HPI6205_ERROR_DSP_EMIF3; /* EMIF CE3 setup - 32 bit async. */ /* This is the PLD on the ASI5000 cards only */ setting = (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | (2L << MTYPE_OFS); boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); if (setting != boot_loader_read_mem32(pao, dsp_index, 0x01800014)) return HPI6205_ERROR_DSP_EMIF4; /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ /* need to use this else DSP code crashes? */ boot_loader_write_mem32(pao, dsp_index, 0x01800018, 0x07117000); /* EMIF SDRAM Refresh Timing */ /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ boot_loader_write_mem32(pao, dsp_index, 0x0180001C, 0x00000410); } else if (dsp_index == 1) { /* test access to the C6713s HPI registers */ u32 write_data = 0, read_data = 0, i = 0; /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ write_data = 1; boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); /* C67 HPI is on lower 16bits of 32bit EMIF */ read_data = 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); if (write_data != read_data) { HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, read_data); return HPI6205_ERROR_C6713_HPIC; } /* HPIA - walking ones test */ write_data = 1; for (i = 0; i < 32; i++) { boot_loader_write_mem32(pao, 0, HPIAL_ADDR, write_data); boot_loader_write_mem32(pao, 0, HPIAH_ADDR, (write_data >> 16)); read_data = 0xFFFF & boot_loader_read_mem32(pao, 0, HPIAL_ADDR); read_data = read_data | ((0xFFFF & boot_loader_read_mem32(pao, 0, HPIAH_ADDR)) << 16); if (read_data != write_data) { HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", write_data, read_data); return HPI6205_ERROR_C6713_HPIA; } write_data = write_data << 1; } /* setup C67x PLL * ** C6713 datasheet says we cannot program PLL from HPI, * and indeed if we try to set the PLL multiply from the HPI, * the PLL does not seem to lock, so we enable the PLL and * use the default multiply of x 7, which for a 27MHz clock * gives a DSP speed of 189MHz */ /* bypass PLL */ boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); hpios_delay_micro_seconds(1000); /* EMIF = 189/3=63MHz */ boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); /* peri = 189/2 */ boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); /* cpu = 189/1 */ boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); hpios_delay_micro_seconds(1000); /* ** SGT test to take GPO3 high when we start the PLL */ /* and low when the delay is completed */ /* FSX0 <- '1' (GPO3) */ boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); /* PLL not bypassed */ boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); hpios_delay_micro_seconds(1000); /* FSX0 <- '0' (GPO3) */ boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); /* 6205 EMIF CE1 resetup - 32 bit async. */ /* Now 6713 #1 is running at 189MHz can reduce waitstates */ boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | (2L << MTYPE_OFS)); hpios_delay_micro_seconds(1000); /* check that we can read one of the PLL registers */ /* PLL should not be bypassed! */ if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) != 0x0001) { return HPI6205_ERROR_C6713_PLL; } /* setup C67x EMIF (note this is the only use of BAR1 via BootLoader_WriteMem32) */ boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, 0x000034A8); /* EMIF CE0 setup - 2Mx32 Sync DRAM 31..28 Wr setup 27..22 Wr strobe 21..20 Wr hold 19..16 Rd setup 15..14 - 13..8 Rd strobe 7..4 MTYPE 0011 Sync DRAM 32bits 3 Wr hold MSB 2..0 Rd hold */ boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, 0x00000030); /* EMIF SDRAM Extension 0x00 31-21 0000b 0000b 000b 20 WR2RD = 2cycles-1 = 1b 19-18 WR2DEAC = 3cycle-1 = 10b 17 WR2WR = 2cycle-1 = 1b 16-15 R2WDQM = 4cycle-1 = 11b 14-12 RD2WR = 6cycles-1 = 101b 11-10 RD2DEAC = 4cycle-1 = 11b 9 RD2RD = 2cycle-1 = 1b 8-7 THZP = 3cycle-1 = 10b 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns) 4 TRRD = 2cycle = 0b (tRRD = 14ns) 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns) 1 CAS latency = 3cyc = 1b (for Micron 2M32-7 operating at 100MHz) */ boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, 0x001BDF29); /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 31 - 0b - 30 SDBSZ 1b 4 bank 29..28 SDRSZ 00b 11 row address pins 27..26 SDCSZ 01b 8 column address pins 25 RFEN 1b refersh enabled 24 INIT 1b init SDRAM! 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6 11..0 - 0000b 0000b 0000b */ boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, 0x47116000); /* SDRAM refresh timing Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A */ boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMTIMING, 0x00000410); hpios_delay_micro_seconds(1000); } else if (dsp_index == 2) { /* DSP 2 is a C6713 */ } return 0; } static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, u32 start_address, u32 length) { u32 i = 0, j = 0; u32 test_addr = 0; u32 test_data = 0, data = 0; length = 1000; /* for 1st word, test each bit in the 32bit word, */ /* dwLength specifies number of 32bit words to test */ /*for(i=0; i<dwLength; i++) */ i = 0; { test_addr = start_address + i * 4; test_data = 0x00000001; for (j = 0; j < 32; j++) { boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); data = boot_loader_read_mem32(pao, dsp_index, test_addr); if (data != test_data) { HPI_DEBUG_LOG(VERBOSE, "Memtest error details " "%08x %08x %08x %i\n", test_addr, test_data, data, dsp_index); return 1; /* error */ } test_data = test_data << 1; } /* for(j) */ } /* for(i) */ /* for the next 100 locations test each location, leaving it as zero */ /* write a zero to the next word in memory before we read */ /* the previous write to make sure every memory location is unique */ for (i = 0; i < 100; i++) { test_addr = start_address + i * 4; test_data = 0xA5A55A5A; boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); data = boot_loader_read_mem32(pao, dsp_index, test_addr); if (data != test_data) { HPI_DEBUG_LOG(VERBOSE, "Memtest error details " "%08x %08x %08x %i\n", test_addr, test_data, data, dsp_index); return 1; /* error */ } /* leave location as zero */ boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); } /* zero out entire memory block */ for (i = 0; i < length; i++) { test_addr = start_address + i * 4; boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); } return 0; } static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, int dsp_index) { int err = 0; if (dsp_index == 0) { /* DSP 0 is a C6205 */ /* 64K prog mem */ err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 0x10000); if (!err) /* 64K data mem */ err = boot_loader_test_memory(pao, dsp_index, 0x80000000, 0x10000); } else if (dsp_index == 1) { /* DSP 1 is a C6713 */ /* 192K internal mem */ err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 0x30000); if (!err) /* 64K internal mem / L2 cache */ err = boot_loader_test_memory(pao, dsp_index, 0x00030000, 0x10000); } if (err) return HPI6205_ERROR_DSP_INTMEM; else return 0; } static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, int dsp_index) { u32 dRAM_start_address = 0; u32 dRAM_size = 0; if (dsp_index == 0) { /* only test for SDRAM if an ASI5000 card */ if (pao->pci.pci_dev->subsystem_device == 0x5000) { /* DSP 0 is always C6205 */ dRAM_start_address = 0x00400000; dRAM_size = 0x200000; /*dwDRAMinc=1024; */ } else return 0; } else if (dsp_index == 1) { /* DSP 1 is a C6713 */ dRAM_start_address = 0x80000000; dRAM_size = 0x200000; /*dwDRAMinc=1024; */ } if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, dRAM_size)) return HPI6205_ERROR_DSP_EXTMEM; return 0; } static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) { u32 data = 0; if (dsp_index == 0) { /* only test for DSP0 PLD on ASI5000 card */ if (pao->pci.pci_dev->subsystem_device == 0x5000) { /* PLD is located at CE3=0x03000000 */ data = boot_loader_read_mem32(pao, dsp_index, 0x03000008); if ((data & 0xF) != 0x5) return HPI6205_ERROR_DSP_PLD; data = boot_loader_read_mem32(pao, dsp_index, 0x0300000C); if ((data & 0xF) != 0xA) return HPI6205_ERROR_DSP_PLD; } } else if (dsp_index == 1) { /* DSP 1 is a C6713 */ if (pao->pci.pci_dev->subsystem_device == 0x8700) { /* PLD is located at CE1=0x90000000 */ data = boot_loader_read_mem32(pao, dsp_index, 0x90000010); if ((data & 0xFF) != 0xAA) return HPI6205_ERROR_DSP_PLD; /* 8713 - LED on */ boot_loader_write_mem32(pao, dsp_index, 0x90000000, 0x02); } } return 0; } /** Transfer data to or from DSP nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA */ static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, u32 data_size, int operation) { struct hpi_hw_obj *phw = pao->priv; u32 data_transferred = 0; u16 err = 0; u32 temp2; struct bus_master_interface *interface = phw->p_interface_buffer; if (!p_data) return HPI_ERROR_INVALID_DATA_POINTER; data_size &= ~3L; /* round data_size down to nearest 4 bytes */ /* make sure state is IDLE */ if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) return HPI_ERROR_DSP_HARDWARE; while (data_transferred < data_size) { u32 this_copy = data_size - data_transferred; if (this_copy > HPI6205_SIZEOF_DATA) this_copy = HPI6205_SIZEOF_DATA; if (operation == H620_HIF_SEND_DATA) memcpy((void *)&interface->u.b_data[0], &p_data[data_transferred], this_copy); interface->transfer_size_in_bytes = this_copy; /* DSP must change this back to nOperation */ interface->dsp_ack = H620_HIF_IDLE; send_dsp_command(phw, operation); temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", HPI6205_TIMEOUT - temp2, this_copy); if (!temp2) { /* timed out */ HPI_DEBUG_LOG(ERROR, "Timed out waiting for " "state %d got %d\n", operation, interface->dsp_ack); break; } if (operation == H620_HIF_GET_DATA) memcpy(&p_data[data_transferred], (void *)&interface->u.b_data[0], this_copy); data_transferred += this_copy; } if (interface->dsp_ack != operation) HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", interface->dsp_ack, operation); /* err=HPI_ERROR_DSP_HARDWARE; */ send_dsp_command(phw, H620_HIF_IDLE); return err; } /* wait for up to timeout_us microseconds for the DSP to signal state by DMA into dwDspAck */ static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) { struct bus_master_interface *interface = phw->p_interface_buffer; int t = timeout_us / 4; rmb(); /* ensure interface->dsp_ack is up to date */ while ((interface->dsp_ack != state) && --t) { hpios_delay_micro_seconds(4); rmb(); /* DSP changes dsp_ack by DMA */ } /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ return t * 4; } /* set the busmaster interface to cmd, then interrupt the DSP */ static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) { struct bus_master_interface *interface = phw->p_interface_buffer; u32 r; interface->host_cmd = cmd; wmb(); /* DSP gets state by DMA, make sure it is written to memory */ /* before we interrupt the DSP */ r = ioread32(phw->prHDCR); r |= (u32)C6205_HDCR_DSPINT; iowrite32(r, phw->prHDCR); r &= ~(u32)C6205_HDCR_DSPINT; iowrite32(r, phw->prHDCR); } static unsigned int message_count; static u16 message_response_sequence(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { u32 time_out, time_out2; struct hpi_hw_obj *phw = pao->priv; struct bus_master_interface *interface = phw->p_interface_buffer; u16 err = 0; message_count++; if (phm->size > sizeof(interface->u.message_buffer)) { phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; phr->specific_error = sizeof(interface->u.message_buffer); phr->size = sizeof(struct hpi_response_header); HPI_DEBUG_LOG(ERROR, "message len %d too big for buffer %zd \n", phm->size, sizeof(interface->u.message_buffer)); return 0; } /* Assume buffer of type struct bus_master_interface_62 is allocated "noncacheable" */ if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; } memcpy(&interface->u.message_buffer, phm, phm->size); /* signal we want a response */ send_dsp_command(phw, H620_HIF_GET_RESP); time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); if (!time_out2) { HPI_DEBUG_LOG(ERROR, "(%u) Timed out waiting for " "GET_RESP state [%x]\n", message_count, interface->dsp_ack); } else { HPI_DEBUG_LOG(VERBOSE, "(%u) transition to GET_RESP after %u\n", message_count, HPI6205_TIMEOUT - time_out2); } /* spin waiting on HIF interrupt flag (end of msg process) */ time_out = HPI6205_TIMEOUT; /* read the result */ if (time_out) { if (interface->u.response_buffer.response.size <= phr->size) memcpy(phr, &interface->u.response_buffer, interface->u.response_buffer.response.size); else { HPI_DEBUG_LOG(ERROR, "response len %d too big for buffer %d\n", interface->u.response_buffer.response.size, phr->size); memcpy(phr, &interface->u.response_buffer, sizeof(struct hpi_response_header)); phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; phr->specific_error = interface->u.response_buffer.response.size; phr->size = sizeof(struct hpi_response_header); } } /* set interface back to idle */ send_dsp_command(phw, H620_HIF_IDLE); if (!time_out || !time_out2) { HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); return HPI6205_ERROR_MSG_RESP_TIMEOUT; } /* special case for adapter close - */ /* wait for the DSP to indicate it is idle */ if (phm->function == HPI_ADAPTER_CLOSE) { if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { HPI_DEBUG_LOG(DEBUG, "Timeout waiting for idle " "(on adapter_close)\n"); return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; } } err = hpi_validate_response(phm, phr); return err; } static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr) { u16 err = 0; hpios_dsplock_lock(pao); err = message_response_sequence(pao, phm, phr); /* maybe an error response */ if (err) { /* something failed in the HPI/DSP interface */ if (err >= HPI_ERROR_BACKEND_BASE) { phr->error = HPI_ERROR_DSP_COMMUNICATION; phr->specific_error = err; } else { phr->error = err; } pao->dsp_crashed++; /* just the header of the response is valid */ phr->size = sizeof(struct hpi_response_header); goto err; } else pao->dsp_crashed = 0; if (phr->error != 0) /* something failed in the DSP */ goto err; switch (phm->function) { case HPI_OSTREAM_WRITE: case HPI_ISTREAM_ANC_WRITE: err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); break; case HPI_ISTREAM_READ: case HPI_OSTREAM_ANC_READ: err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, phm->u.d.u.data.data_size, H620_HIF_GET_DATA); break; } phr->error = err; err: hpios_dsplock_unlock(pao); return; }
linux-master
sound/pci/asihpi/hpi6205.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2012 AudioScience Inc. <[email protected]> HPI Operating System function implementation for Linux (C) Copyright AudioScience Inc. 1997-2003 ******************************************************************************/ #define SOURCEFILE_NAME "hpios.c" #include "hpi_internal.h" #include "hpidebug.h" #include <linux/delay.h> #include <linux/sched.h> void hpios_delay_micro_seconds(u32 num_micro_sec) { if ((usecs_to_jiffies(num_micro_sec) > 1) && !in_interrupt()) { /* MUST NOT SCHEDULE IN INTERRUPT CONTEXT! */ schedule_timeout_uninterruptible(usecs_to_jiffies (num_micro_sec)); } else if (num_micro_sec <= 2000) udelay(num_micro_sec); else mdelay(num_micro_sec / 1000); } /** Allocate an area of locked memory for bus master DMA operations. If allocation fails, return 1, and *pMemArea.size = 0 */ u16 hpios_locked_mem_alloc(struct consistent_dma_area *p_mem_area, u32 size, struct pci_dev *pdev) { /*?? any benefit in using managed dmam_alloc_coherent? */ p_mem_area->vaddr = dma_alloc_coherent(&pdev->dev, size, &p_mem_area->dma_handle, GFP_KERNEL); if (p_mem_area->vaddr) { HPI_DEBUG_LOG(DEBUG, "allocated %d bytes, dma 0x%x vma %p\n", size, (unsigned int)p_mem_area->dma_handle, p_mem_area->vaddr); p_mem_area->pdev = &pdev->dev; p_mem_area->size = size; return 0; } else { HPI_DEBUG_LOG(WARNING, "failed to allocate %d bytes locked memory\n", size); p_mem_area->size = 0; return 1; } } u16 hpios_locked_mem_free(struct consistent_dma_area *p_mem_area) { if (p_mem_area->size) { dma_free_coherent(p_mem_area->pdev, p_mem_area->size, p_mem_area->vaddr, p_mem_area->dma_handle); HPI_DEBUG_LOG(DEBUG, "freed %lu bytes, dma 0x%x vma %p\n", (unsigned long)p_mem_area->size, (unsigned int)p_mem_area->dma_handle, p_mem_area->vaddr); p_mem_area->size = 0; return 0; } else { return 1; } }
linux-master
sound/pci/asihpi/hpios.c
// SPDX-License-Identifier: GPL-2.0-only /****************************************************************************** AudioScience HPI driver Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> Hardware Programming Interface (HPI) Utility functions. (C) Copyright AudioScience Inc. 2007 *******************************************************************************/ #include "hpi_internal.h" #include "hpimsginit.h" #include <linux/nospec.h> /* The actual message size for each object type */ static u16 msg_size[HPI_OBJ_MAXINDEX + 1] = HPI_MESSAGE_SIZE_BY_OBJECT; /* The actual response size for each object type */ static u16 res_size[HPI_OBJ_MAXINDEX + 1] = HPI_RESPONSE_SIZE_BY_OBJECT; /* Flag to enable alternate message type for SSX2 bypass. */ static u16 gwSSX2_bypass; /** \internal * initialize the HPI message structure */ static void hpi_init_message(struct hpi_message *phm, u16 object, u16 function) { u16 size; if ((object > 0) && (object <= HPI_OBJ_MAXINDEX)) { object = array_index_nospec(object, HPI_OBJ_MAXINDEX + 1); size = msg_size[object]; } else { size = sizeof(*phm); } memset(phm, 0, size); phm->size = size; if (gwSSX2_bypass) phm->type = HPI_TYPE_SSX2BYPASS_MESSAGE; else phm->type = HPI_TYPE_REQUEST; phm->object = object; phm->function = function; phm->version = 0; phm->adapter_index = HPI_ADAPTER_INDEX_INVALID; /* Expect actual adapter index to be set by caller */ } /** \internal * initialize the HPI response structure */ void hpi_init_response(struct hpi_response *phr, u16 object, u16 function, u16 error) { u16 size; if ((object > 0) && (object <= HPI_OBJ_MAXINDEX)) { object = array_index_nospec(object, HPI_OBJ_MAXINDEX + 1); size = res_size[object]; } else { size = sizeof(*phr); } memset(phr, 0, sizeof(*phr)); phr->size = size; phr->type = HPI_TYPE_RESPONSE; phr->object = object; phr->function = function; phr->error = error; phr->specific_error = 0; phr->version = 0; } void hpi_init_message_response(struct hpi_message *phm, struct hpi_response *phr, u16 object, u16 function) { hpi_init_message(phm, object, function); /* default error return if the response is not filled in by the callee */ hpi_init_response(phr, object, function, HPI_ERROR_PROCESSING_MESSAGE); } static void hpi_init_messageV1(struct hpi_message_header *phm, u16 size, u16 object, u16 function) { memset(phm, 0, size); if ((object > 0) && (object <= HPI_OBJ_MAXINDEX)) { phm->size = size; phm->type = HPI_TYPE_REQUEST; phm->object = object; phm->function = function; phm->version = 1; /* Expect adapter index to be set by caller */ } } void hpi_init_responseV1(struct hpi_response_header *phr, u16 size, u16 object, u16 function) { (void)object; (void)function; memset(phr, 0, size); phr->size = size; phr->version = 1; phr->type = HPI_TYPE_RESPONSE; phr->error = HPI_ERROR_PROCESSING_MESSAGE; } void hpi_init_message_responseV1(struct hpi_message_header *phm, u16 msg_size, struct hpi_response_header *phr, u16 res_size, u16 object, u16 function) { hpi_init_messageV1(phm, msg_size, object, function); hpi_init_responseV1(phr, res_size, object, function); }
linux-master
sound/pci/asihpi/hpimsginit.c
// SPDX-License-Identifier: GPL-2.0 #include "hpi_internal.h" #include "hpimsginit.h" #include "hpidebug.h" struct hpi_handle { unsigned int obj_index:12; unsigned int obj_type:4; unsigned int adapter_index:14; unsigned int spare:1; unsigned int read_only:1; }; union handle_word { struct hpi_handle h; u32 w; }; u32 hpi_indexes_to_handle(const char c_object, const u16 adapter_index, const u16 object_index) { union handle_word handle; handle.h.adapter_index = adapter_index; handle.h.spare = 0; handle.h.read_only = 0; handle.h.obj_type = c_object; handle.h.obj_index = object_index; return handle.w; } static u16 hpi_handle_indexes(const u32 h, u16 *p1, u16 *p2) { union handle_word uhandle; if (!h) return HPI_ERROR_INVALID_HANDLE; uhandle.w = h; *p1 = (u16)uhandle.h.adapter_index; if (p2) *p2 = (u16)uhandle.h.obj_index; return 0; } void hpi_handle_to_indexes(const u32 handle, u16 *pw_adapter_index, u16 *pw_object_index) { hpi_handle_indexes(handle, pw_adapter_index, pw_object_index); } char hpi_handle_object(const u32 handle) { union handle_word uhandle; uhandle.w = handle; return (char)uhandle.h.obj_type; } void hpi_format_to_msg(struct hpi_msg_format *pMF, const struct hpi_format *pF) { pMF->sample_rate = pF->sample_rate; pMF->bit_rate = pF->bit_rate; pMF->attributes = pF->attributes; pMF->channels = pF->channels; pMF->format = pF->format; } static void hpi_msg_to_format(struct hpi_format *pF, struct hpi_msg_format *pMF) { pF->sample_rate = pMF->sample_rate; pF->bit_rate = pMF->bit_rate; pF->attributes = pMF->attributes; pF->channels = pMF->channels; pF->format = pMF->format; pF->mode_legacy = 0; pF->unused = 0; } void hpi_stream_response_to_legacy(struct hpi_stream_res *pSR) { pSR->u.legacy_stream_info.auxiliary_data_available = pSR->u.stream_info.auxiliary_data_available; pSR->u.legacy_stream_info.state = pSR->u.stream_info.state; } static inline void hpi_send_recvV1(struct hpi_message_header *m, struct hpi_response_header *r) { hpi_send_recv((struct hpi_message *)m, (struct hpi_response *)r); } u16 hpi_subsys_get_version_ex(u32 *pversion_ex) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_GET_VERSION); hpi_send_recv(&hm, &hr); *pversion_ex = hr.u.s.data; return hr.error; } u16 hpi_subsys_get_num_adapters(int *pn_num_adapters) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_GET_NUM_ADAPTERS); hpi_send_recv(&hm, &hr); *pn_num_adapters = (int)hr.u.s.num_adapters; return hr.error; } u16 hpi_subsys_get_adapter(int iterator, u32 *padapter_index, u16 *pw_adapter_type) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_SUBSYSTEM, HPI_SUBSYS_GET_ADAPTER); hm.obj_index = (u16)iterator; hpi_send_recv(&hm, &hr); *padapter_index = (int)hr.u.s.adapter_index; *pw_adapter_type = hr.u.s.adapter_type; return hr.error; } u16 hpi_adapter_open(u16 adapter_index) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_OPEN); hm.adapter_index = adapter_index; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_adapter_close(u16 adapter_index) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_CLOSE); hm.adapter_index = adapter_index; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_adapter_set_mode(u16 adapter_index, u32 adapter_mode) { return hpi_adapter_set_mode_ex(adapter_index, adapter_mode, HPI_ADAPTER_MODE_SET); } u16 hpi_adapter_set_mode_ex(u16 adapter_index, u32 adapter_mode, u16 query_or_set) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_SET_MODE); hm.adapter_index = adapter_index; hm.u.ax.mode.adapter_mode = adapter_mode; hm.u.ax.mode.query_or_set = query_or_set; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_adapter_get_mode(u16 adapter_index, u32 *padapter_mode) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_MODE); hm.adapter_index = adapter_index; hpi_send_recv(&hm, &hr); if (padapter_mode) *padapter_mode = hr.u.ax.mode.adapter_mode; return hr.error; } u16 hpi_adapter_get_info(u16 adapter_index, u16 *pw_num_outstreams, u16 *pw_num_instreams, u16 *pw_version, u32 *pserial_number, u16 *pw_adapter_type) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_INFO); hm.adapter_index = adapter_index; hpi_send_recv(&hm, &hr); *pw_adapter_type = hr.u.ax.info.adapter_type; *pw_num_outstreams = hr.u.ax.info.num_outstreams; *pw_num_instreams = hr.u.ax.info.num_instreams; *pw_version = hr.u.ax.info.version; *pserial_number = hr.u.ax.info.serial_number; return hr.error; } u16 hpi_adapter_get_module_by_index(u16 adapter_index, u16 module_index, u16 *pw_num_outputs, u16 *pw_num_inputs, u16 *pw_version, u32 *pserial_number, u16 *pw_module_type, u32 *ph_module) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_MODULE_INFO); hm.adapter_index = adapter_index; hm.u.ax.module_info.index = module_index; hpi_send_recv(&hm, &hr); *pw_module_type = hr.u.ax.info.adapter_type; *pw_num_outputs = hr.u.ax.info.num_outstreams; *pw_num_inputs = hr.u.ax.info.num_instreams; *pw_version = hr.u.ax.info.version; *pserial_number = hr.u.ax.info.serial_number; *ph_module = 0; return hr.error; } u16 hpi_adapter_set_property(u16 adapter_index, u16 property, u16 parameter1, u16 parameter2) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_SET_PROPERTY); hm.adapter_index = adapter_index; hm.u.ax.property_set.property = property; hm.u.ax.property_set.parameter1 = parameter1; hm.u.ax.property_set.parameter2 = parameter2; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_adapter_get_property(u16 adapter_index, u16 property, u16 *pw_parameter1, u16 *pw_parameter2) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ADAPTER, HPI_ADAPTER_GET_PROPERTY); hm.adapter_index = adapter_index; hm.u.ax.property_set.property = property; hpi_send_recv(&hm, &hr); if (!hr.error) { if (pw_parameter1) *pw_parameter1 = hr.u.ax.property_get.parameter1; if (pw_parameter2) *pw_parameter2 = hr.u.ax.property_get.parameter2; } return hr.error; } u16 hpi_adapter_enumerate_property(u16 adapter_index, u16 index, u16 what_to_enumerate, u16 property_index, u32 *psetting) { return 0; } u16 hpi_format_create(struct hpi_format *p_format, u16 channels, u16 format, u32 sample_rate, u32 bit_rate, u32 attributes) { u16 err = 0; struct hpi_msg_format fmt; switch (channels) { case 1: case 2: case 4: case 6: case 8: case 16: break; default: err = HPI_ERROR_INVALID_CHANNELS; return err; } fmt.channels = channels; switch (format) { case HPI_FORMAT_PCM16_SIGNED: case HPI_FORMAT_PCM24_SIGNED: case HPI_FORMAT_PCM32_SIGNED: case HPI_FORMAT_PCM32_FLOAT: case HPI_FORMAT_PCM16_BIGENDIAN: case HPI_FORMAT_PCM8_UNSIGNED: case HPI_FORMAT_MPEG_L1: case HPI_FORMAT_MPEG_L2: case HPI_FORMAT_MPEG_L3: case HPI_FORMAT_DOLBY_AC2: case HPI_FORMAT_AA_TAGIT1_HITS: case HPI_FORMAT_AA_TAGIT1_INSERTS: case HPI_FORMAT_RAW_BITSTREAM: case HPI_FORMAT_AA_TAGIT1_HITS_EX1: case HPI_FORMAT_OEM1: case HPI_FORMAT_OEM2: break; default: err = HPI_ERROR_INVALID_FORMAT; return err; } fmt.format = format; if (sample_rate < 8000L) { err = HPI_ERROR_INCOMPATIBLE_SAMPLERATE; sample_rate = 8000L; } if (sample_rate > 200000L) { err = HPI_ERROR_INCOMPATIBLE_SAMPLERATE; sample_rate = 200000L; } fmt.sample_rate = sample_rate; switch (format) { case HPI_FORMAT_MPEG_L1: case HPI_FORMAT_MPEG_L2: case HPI_FORMAT_MPEG_L3: fmt.bit_rate = bit_rate; break; case HPI_FORMAT_PCM16_SIGNED: case HPI_FORMAT_PCM16_BIGENDIAN: fmt.bit_rate = channels * sample_rate * 2; break; case HPI_FORMAT_PCM32_SIGNED: case HPI_FORMAT_PCM32_FLOAT: fmt.bit_rate = channels * sample_rate * 4; break; case HPI_FORMAT_PCM8_UNSIGNED: fmt.bit_rate = channels * sample_rate; break; default: fmt.bit_rate = 0; } switch (format) { case HPI_FORMAT_MPEG_L2: if ((channels == 1) && (attributes != HPI_MPEG_MODE_DEFAULT)) { attributes = HPI_MPEG_MODE_DEFAULT; err = HPI_ERROR_INVALID_FORMAT; } else if (attributes > HPI_MPEG_MODE_DUALCHANNEL) { attributes = HPI_MPEG_MODE_DEFAULT; err = HPI_ERROR_INVALID_FORMAT; } fmt.attributes = attributes; break; default: fmt.attributes = attributes; } hpi_msg_to_format(p_format, &fmt); return err; } u16 hpi_stream_estimate_buffer_size(struct hpi_format *p_format, u32 host_polling_rate_in_milli_seconds, u32 *recommended_buffer_size) { u32 bytes_per_second; u32 size; u16 channels; struct hpi_format *pF = p_format; channels = pF->channels; switch (pF->format) { case HPI_FORMAT_PCM16_BIGENDIAN: case HPI_FORMAT_PCM16_SIGNED: bytes_per_second = pF->sample_rate * 2L * channels; break; case HPI_FORMAT_PCM24_SIGNED: bytes_per_second = pF->sample_rate * 3L * channels; break; case HPI_FORMAT_PCM32_SIGNED: case HPI_FORMAT_PCM32_FLOAT: bytes_per_second = pF->sample_rate * 4L * channels; break; case HPI_FORMAT_PCM8_UNSIGNED: bytes_per_second = pF->sample_rate * 1L * channels; break; case HPI_FORMAT_MPEG_L1: case HPI_FORMAT_MPEG_L2: case HPI_FORMAT_MPEG_L3: bytes_per_second = pF->bit_rate / 8L; break; case HPI_FORMAT_DOLBY_AC2: bytes_per_second = 256000L / 8L; break; default: return HPI_ERROR_INVALID_FORMAT; } size = (bytes_per_second * host_polling_rate_in_milli_seconds * 2) / 1000L; *recommended_buffer_size = roundup_pow_of_two(((size + 4095L) & ~4095L)); return 0; } u16 hpi_outstream_open(u16 adapter_index, u16 outstream_index, u32 *ph_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_OPEN); hm.adapter_index = adapter_index; hm.obj_index = outstream_index; hpi_send_recv(&hm, &hr); if (hr.error == 0) *ph_outstream = hpi_indexes_to_handle(HPI_OBJ_OSTREAM, adapter_index, outstream_index); else *ph_outstream = 0; return hr.error; } u16 hpi_outstream_close(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_FREE); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_GROUP_RESET); hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index); hpi_send_recv(&hm, &hr); hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_CLOSE); hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_get_info_ex(u32 h_outstream, u16 *pw_state, u32 *pbuffer_size, u32 *pdata_to_play, u32 *psamples_played, u32 *pauxiliary_data_to_play) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_GET_INFO); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (pw_state) *pw_state = hr.u.d.u.stream_info.state; if (pbuffer_size) *pbuffer_size = hr.u.d.u.stream_info.buffer_size; if (pdata_to_play) *pdata_to_play = hr.u.d.u.stream_info.data_available; if (psamples_played) *psamples_played = hr.u.d.u.stream_info.samples_transferred; if (pauxiliary_data_to_play) *pauxiliary_data_to_play = hr.u.d.u.stream_info.auxiliary_data_available; return hr.error; } u16 hpi_outstream_write_buf(u32 h_outstream, const u8 *pb_data, u32 bytes_to_write, const struct hpi_format *p_format) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_WRITE); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.pb_data = (u8 *)pb_data; hm.u.d.u.data.data_size = bytes_to_write; hpi_format_to_msg(&hm.u.d.u.data.format, p_format); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_start(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_START); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_wait_start(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_WAIT_START); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_stop(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_STOP); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_sinegen(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_SINEGEN); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_reset(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_RESET); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_query_format(u32 h_outstream, struct hpi_format *p_format) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_QUERY_FORMAT); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_format_to_msg(&hm.u.d.u.data.format, p_format); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_set_format(u32 h_outstream, struct hpi_format *p_format) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_SET_FORMAT); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_format_to_msg(&hm.u.d.u.data.format, p_format); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_set_velocity(u32 h_outstream, short velocity) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_SET_VELOCITY); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.velocity = velocity; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_set_punch_in_out(u32 h_outstream, u32 punch_in_sample, u32 punch_out_sample) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_SET_PUNCHINOUT); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.pio.punch_in_sample = punch_in_sample; hm.u.d.u.pio.punch_out_sample = punch_out_sample; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_ancillary_reset(u32 h_outstream, u16 mode) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_ANC_RESET); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.format.channels = mode; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_ancillary_get_info(u32 h_outstream, u32 *pframes_available) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_ANC_GET_INFO); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (hr.error == 0) { if (pframes_available) *pframes_available = hr.u.d.u.stream_info.data_available / sizeof(struct hpi_anc_frame); } return hr.error; } u16 hpi_outstream_ancillary_read(u32 h_outstream, struct hpi_anc_frame *p_anc_frame_buffer, u32 anc_frame_buffer_size_in_bytes, u32 number_of_ancillary_frames_to_read) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_ANC_READ); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.pb_data = (u8 *)p_anc_frame_buffer; hm.u.d.u.data.data_size = number_of_ancillary_frames_to_read * sizeof(struct hpi_anc_frame); if (hm.u.d.u.data.data_size <= anc_frame_buffer_size_in_bytes) hpi_send_recv(&hm, &hr); else hr.error = HPI_ERROR_INVALID_DATASIZE; return hr.error; } u16 hpi_outstream_set_time_scale(u32 h_outstream, u32 time_scale) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_SET_TIMESCALE); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.time_scale = time_scale; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_host_buffer_allocate(u32 h_outstream, u32 size_in_bytes) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_ALLOC); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.data_size = size_in_bytes; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_host_buffer_get_info(u32 h_outstream, u8 **pp_buffer, struct hpi_hostbuffer_status **pp_status) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_GET_INFO); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (hr.error == 0) { if (pp_buffer) *pp_buffer = hr.u.d.u.hostbuffer_info.p_buffer; if (pp_status) *pp_status = hr.u.d.u.hostbuffer_info.p_status; } return hr.error; } u16 hpi_outstream_host_buffer_free(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_HOSTBUFFER_FREE); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_group_add(u32 h_outstream, u32 h_stream) { struct hpi_message hm; struct hpi_response hr; u16 adapter; char c_obj_type; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_GROUP_ADD); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; if (hpi_handle_indexes(h_stream, &adapter, &hm.u.d.u.stream.stream_index)) return HPI_ERROR_INVALID_HANDLE; c_obj_type = hpi_handle_object(h_stream); switch (c_obj_type) { case HPI_OBJ_OSTREAM: case HPI_OBJ_ISTREAM: hm.u.d.u.stream.object_type = c_obj_type; break; default: return HPI_ERROR_INVALID_OBJ; } if (adapter != hm.adapter_index) return HPI_ERROR_NO_INTERADAPTER_GROUPS; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_outstream_group_get_map(u32 h_outstream, u32 *poutstream_map, u32 *pinstream_map) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_GROUP_GETMAP); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (poutstream_map) *poutstream_map = hr.u.d.u.group_info.outstream_group_map; if (pinstream_map) *pinstream_map = hr.u.d.u.group_info.instream_group_map; return hr.error; } u16 hpi_outstream_group_reset(u32 h_outstream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_OSTREAM, HPI_OSTREAM_GROUP_RESET); if (hpi_handle_indexes(h_outstream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_open(u16 adapter_index, u16 instream_index, u32 *ph_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_OPEN); hm.adapter_index = adapter_index; hm.obj_index = instream_index; hpi_send_recv(&hm, &hr); if (hr.error == 0) *ph_instream = hpi_indexes_to_handle(HPI_OBJ_ISTREAM, adapter_index, instream_index); else *ph_instream = 0; return hr.error; } u16 hpi_instream_close(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_FREE); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_GROUP_RESET); hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index); hpi_send_recv(&hm, &hr); hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_CLOSE); hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_query_format(u32 h_instream, const struct hpi_format *p_format) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_QUERY_FORMAT); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_format_to_msg(&hm.u.d.u.data.format, p_format); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_set_format(u32 h_instream, const struct hpi_format *p_format) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_SET_FORMAT); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_format_to_msg(&hm.u.d.u.data.format, p_format); hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_read_buf(u32 h_instream, u8 *pb_data, u32 bytes_to_read) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_READ); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.data_size = bytes_to_read; hm.u.d.u.data.pb_data = pb_data; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_start(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_START); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_wait_start(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_WAIT_START); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_stop(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_STOP); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_reset(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_RESET); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_get_info_ex(u32 h_instream, u16 *pw_state, u32 *pbuffer_size, u32 *pdata_recorded, u32 *psamples_recorded, u32 *pauxiliary_data_recorded) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_GET_INFO); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (pw_state) *pw_state = hr.u.d.u.stream_info.state; if (pbuffer_size) *pbuffer_size = hr.u.d.u.stream_info.buffer_size; if (pdata_recorded) *pdata_recorded = hr.u.d.u.stream_info.data_available; if (psamples_recorded) *psamples_recorded = hr.u.d.u.stream_info.samples_transferred; if (pauxiliary_data_recorded) *pauxiliary_data_recorded = hr.u.d.u.stream_info.auxiliary_data_available; return hr.error; } u16 hpi_instream_ancillary_reset(u32 h_instream, u16 bytes_per_frame, u16 mode, u16 alignment, u16 idle_bit) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_ANC_RESET); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.format.attributes = bytes_per_frame; hm.u.d.u.data.format.format = (mode << 8) | (alignment & 0xff); hm.u.d.u.data.format.channels = idle_bit; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_ancillary_get_info(u32 h_instream, u32 *pframe_space) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_ANC_GET_INFO); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (pframe_space) *pframe_space = (hr.u.d.u.stream_info.buffer_size - hr.u.d.u.stream_info.data_available) / sizeof(struct hpi_anc_frame); return hr.error; } u16 hpi_instream_ancillary_write(u32 h_instream, const struct hpi_anc_frame *p_anc_frame_buffer, u32 anc_frame_buffer_size_in_bytes, u32 number_of_ancillary_frames_to_write) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_ANC_WRITE); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.pb_data = (u8 *)p_anc_frame_buffer; hm.u.d.u.data.data_size = number_of_ancillary_frames_to_write * sizeof(struct hpi_anc_frame); if (hm.u.d.u.data.data_size <= anc_frame_buffer_size_in_bytes) hpi_send_recv(&hm, &hr); else hr.error = HPI_ERROR_INVALID_DATASIZE; return hr.error; } u16 hpi_instream_host_buffer_allocate(u32 h_instream, u32 size_in_bytes) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_ALLOC); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.d.u.data.data_size = size_in_bytes; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_host_buffer_get_info(u32 h_instream, u8 **pp_buffer, struct hpi_hostbuffer_status **pp_status) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_GET_INFO); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (hr.error == 0) { if (pp_buffer) *pp_buffer = hr.u.d.u.hostbuffer_info.p_buffer; if (pp_status) *pp_status = hr.u.d.u.hostbuffer_info.p_status; } return hr.error; } u16 hpi_instream_host_buffer_free(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_FREE); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_group_add(u32 h_instream, u32 h_stream) { struct hpi_message hm; struct hpi_response hr; u16 adapter; char c_obj_type; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_GROUP_ADD); hr.error = 0; if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; if (hpi_handle_indexes(h_stream, &adapter, &hm.u.d.u.stream.stream_index)) return HPI_ERROR_INVALID_HANDLE; c_obj_type = hpi_handle_object(h_stream); switch (c_obj_type) { case HPI_OBJ_OSTREAM: case HPI_OBJ_ISTREAM: hm.u.d.u.stream.object_type = c_obj_type; break; default: return HPI_ERROR_INVALID_OBJ; } if (adapter != hm.adapter_index) return HPI_ERROR_NO_INTERADAPTER_GROUPS; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_instream_group_get_map(u32 h_instream, u32 *poutstream_map, u32 *pinstream_map) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_HOSTBUFFER_FREE); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); if (poutstream_map) *poutstream_map = hr.u.d.u.group_info.outstream_group_map; if (pinstream_map) *pinstream_map = hr.u.d.u.group_info.instream_group_map; return hr.error; } u16 hpi_instream_group_reset(u32 h_instream) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_ISTREAM, HPI_ISTREAM_GROUP_RESET); if (hpi_handle_indexes(h_instream, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_mixer_open(u16 adapter_index, u32 *ph_mixer) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_OPEN); hm.adapter_index = adapter_index; hpi_send_recv(&hm, &hr); if (hr.error == 0) *ph_mixer = hpi_indexes_to_handle(HPI_OBJ_MIXER, adapter_index, 0); else *ph_mixer = 0; return hr.error; } u16 hpi_mixer_close(u32 h_mixer) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_CLOSE); if (hpi_handle_indexes(h_mixer, &hm.adapter_index, NULL)) return HPI_ERROR_INVALID_HANDLE; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_mixer_get_control(u32 h_mixer, u16 src_node_type, u16 src_node_type_index, u16 dst_node_type, u16 dst_node_type_index, u16 control_type, u32 *ph_control) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_GET_CONTROL); if (hpi_handle_indexes(h_mixer, &hm.adapter_index, NULL)) return HPI_ERROR_INVALID_HANDLE; hm.u.m.node_type1 = src_node_type; hm.u.m.node_index1 = src_node_type_index; hm.u.m.node_type2 = dst_node_type; hm.u.m.node_index2 = dst_node_type_index; hm.u.m.control_type = control_type; hpi_send_recv(&hm, &hr); if (hr.error == 0) *ph_control = hpi_indexes_to_handle(HPI_OBJ_CONTROL, hm.adapter_index, hr.u.m.control_index); else *ph_control = 0; return hr.error; } u16 hpi_mixer_get_control_by_index(u32 h_mixer, u16 control_index, u16 *pw_src_node_type, u16 *pw_src_node_index, u16 *pw_dst_node_type, u16 *pw_dst_node_index, u16 *pw_control_type, u32 *ph_control) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_GET_CONTROL_BY_INDEX); if (hpi_handle_indexes(h_mixer, &hm.adapter_index, NULL)) return HPI_ERROR_INVALID_HANDLE; hm.u.m.control_index = control_index; hpi_send_recv(&hm, &hr); if (pw_src_node_type) { *pw_src_node_type = hr.u.m.src_node_type + HPI_SOURCENODE_NONE; *pw_src_node_index = hr.u.m.src_node_index; *pw_dst_node_type = hr.u.m.dst_node_type + HPI_DESTNODE_NONE; *pw_dst_node_index = hr.u.m.dst_node_index; } if (pw_control_type) *pw_control_type = hr.u.m.control_index; if (ph_control) { if (hr.error == 0) *ph_control = hpi_indexes_to_handle(HPI_OBJ_CONTROL, hm.adapter_index, control_index); else *ph_control = 0; } return hr.error; } u16 hpi_mixer_store(u32 h_mixer, enum HPI_MIXER_STORE_COMMAND command, u16 index) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_MIXER, HPI_MIXER_STORE); if (hpi_handle_indexes(h_mixer, &hm.adapter_index, NULL)) return HPI_ERROR_INVALID_HANDLE; hm.u.mx.store.command = command; hm.u.mx.store.index = index; hpi_send_recv(&hm, &hr); return hr.error; } static u16 hpi_control_param_set(const u32 h_control, const u16 attrib, const u32 param1, const u32 param2) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attrib; hm.u.c.param1 = param1; hm.u.c.param2 = param2; hpi_send_recv(&hm, &hr); return hr.error; } static u16 hpi_control_log_set2(u32 h_control, u16 attrib, short sv0, short sv1) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attrib; hm.u.c.an_log_value[0] = sv0; hm.u.c.an_log_value[1] = sv1; hpi_send_recv(&hm, &hr); return hr.error; } static u16 hpi_control_param_get(const u32 h_control, const u16 attrib, u32 param1, u32 param2, u32 *pparam1, u32 *pparam2) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attrib; hm.u.c.param1 = param1; hm.u.c.param2 = param2; hpi_send_recv(&hm, &hr); *pparam1 = hr.u.c.param1; if (pparam2) *pparam2 = hr.u.c.param2; return hr.error; } #define hpi_control_param1_get(h, a, p1) \ hpi_control_param_get(h, a, 0, 0, p1, NULL) #define hpi_control_param2_get(h, a, p1, p2) \ hpi_control_param_get(h, a, 0, 0, p1, p2) static u16 hpi_control_log_get2(u32 h_control, u16 attrib, short *sv0, short *sv1) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attrib; hpi_send_recv(&hm, &hr); *sv0 = hr.u.c.an_log_value[0]; if (sv1) *sv1 = hr.u.c.an_log_value[1]; return hr.error; } static u16 hpi_control_query(const u32 h_control, const u16 attrib, const u32 index, const u32 param, u32 *psetting) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_INFO); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attrib; hm.u.c.param1 = index; hm.u.c.param2 = param; hpi_send_recv(&hm, &hr); *psetting = hr.u.c.param1; return hr.error; } static u16 hpi_control_get_string(const u32 h_control, const u16 attribute, char *psz_string, const u32 string_length) { unsigned int sub_string_index = 0, j = 0; char c = 0; unsigned int n = 0; u16 err = 0; if ((string_length < 1) || (string_length > 256)) return HPI_ERROR_INVALID_CONTROL_VALUE; for (sub_string_index = 0; sub_string_index < string_length; sub_string_index += 8) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = attribute; hm.u.c.param1 = sub_string_index; hm.u.c.param2 = 0; hpi_send_recv(&hm, &hr); if (sub_string_index == 0 && (hr.u.cu.chars8.remaining_chars + 8) > string_length) return HPI_ERROR_INVALID_CONTROL_VALUE; if (hr.error) { err = hr.error; break; } for (j = 0; j < 8; j++) { c = hr.u.cu.chars8.sz_data[j]; psz_string[sub_string_index + j] = c; n++; if (n >= string_length) { psz_string[string_length - 1] = 0; err = HPI_ERROR_INVALID_CONTROL_VALUE; break; } if (c == 0) break; } if ((hr.u.cu.chars8.remaining_chars == 0) && ((sub_string_index + j) < string_length) && (c != 0)) { c = 0; psz_string[sub_string_index + j] = c; } if (c == 0) break; } return err; } u16 hpi_aesebu_receiver_query_format(const u32 h_aes_rx, const u32 index, u16 *pw_format) { u32 qr; u16 err; err = hpi_control_query(h_aes_rx, HPI_AESEBURX_FORMAT, index, 0, &qr); *pw_format = (u16)qr; return err; } u16 hpi_aesebu_receiver_set_format(u32 h_control, u16 format) { return hpi_control_param_set(h_control, HPI_AESEBURX_FORMAT, format, 0); } u16 hpi_aesebu_receiver_get_format(u32 h_control, u16 *pw_format) { u16 err; u32 param; err = hpi_control_param1_get(h_control, HPI_AESEBURX_FORMAT, &param); if (!err && pw_format) *pw_format = (u16)param; return err; } u16 hpi_aesebu_receiver_get_sample_rate(u32 h_control, u32 *psample_rate) { return hpi_control_param1_get(h_control, HPI_AESEBURX_SAMPLERATE, psample_rate); } u16 hpi_aesebu_receiver_get_user_data(u32 h_control, u16 index, u16 *pw_data) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_AESEBURX_USERDATA; hm.u.c.param1 = index; hpi_send_recv(&hm, &hr); if (pw_data) *pw_data = (u16)hr.u.c.param2; return hr.error; } u16 hpi_aesebu_receiver_get_channel_status(u32 h_control, u16 index, u16 *pw_data) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_AESEBURX_CHANNELSTATUS; hm.u.c.param1 = index; hpi_send_recv(&hm, &hr); if (pw_data) *pw_data = (u16)hr.u.c.param2; return hr.error; } u16 hpi_aesebu_receiver_get_error_status(u32 h_control, u16 *pw_error_data) { u32 error_data = 0; u16 err = 0; err = hpi_control_param1_get(h_control, HPI_AESEBURX_ERRORSTATUS, &error_data); if (pw_error_data) *pw_error_data = (u16)error_data; return err; } u16 hpi_aesebu_transmitter_set_sample_rate(u32 h_control, u32 sample_rate) { return hpi_control_param_set(h_control, HPI_AESEBUTX_SAMPLERATE, sample_rate, 0); } u16 hpi_aesebu_transmitter_set_user_data(u32 h_control, u16 index, u16 data) { return hpi_control_param_set(h_control, HPI_AESEBUTX_USERDATA, index, data); } u16 hpi_aesebu_transmitter_set_channel_status(u32 h_control, u16 index, u16 data) { return hpi_control_param_set(h_control, HPI_AESEBUTX_CHANNELSTATUS, index, data); } u16 hpi_aesebu_transmitter_get_channel_status(u32 h_control, u16 index, u16 *pw_data) { return HPI_ERROR_INVALID_OPERATION; } u16 hpi_aesebu_transmitter_query_format(const u32 h_aes_tx, const u32 index, u16 *pw_format) { u32 qr; u16 err; err = hpi_control_query(h_aes_tx, HPI_AESEBUTX_FORMAT, index, 0, &qr); *pw_format = (u16)qr; return err; } u16 hpi_aesebu_transmitter_set_format(u32 h_control, u16 output_format) { return hpi_control_param_set(h_control, HPI_AESEBUTX_FORMAT, output_format, 0); } u16 hpi_aesebu_transmitter_get_format(u32 h_control, u16 *pw_output_format) { u16 err; u32 param; err = hpi_control_param1_get(h_control, HPI_AESEBUTX_FORMAT, &param); if (!err && pw_output_format) *pw_output_format = (u16)param; return err; } u16 hpi_bitstream_set_clock_edge(u32 h_control, u16 edge_type) { return hpi_control_param_set(h_control, HPI_BITSTREAM_CLOCK_EDGE, edge_type, 0); } u16 hpi_bitstream_set_data_polarity(u32 h_control, u16 polarity) { return hpi_control_param_set(h_control, HPI_BITSTREAM_DATA_POLARITY, polarity, 0); } u16 hpi_bitstream_get_activity(u32 h_control, u16 *pw_clk_activity, u16 *pw_data_activity) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_BITSTREAM_ACTIVITY; hpi_send_recv(&hm, &hr); if (pw_clk_activity) *pw_clk_activity = (u16)hr.u.c.param1; if (pw_data_activity) *pw_data_activity = (u16)hr.u.c.param2; return hr.error; } u16 hpi_channel_mode_query_mode(const u32 h_mode, const u32 index, u16 *pw_mode) { u32 qr; u16 err; err = hpi_control_query(h_mode, HPI_CHANNEL_MODE_MODE, index, 0, &qr); *pw_mode = (u16)qr; return err; } u16 hpi_channel_mode_set(u32 h_control, u16 mode) { return hpi_control_param_set(h_control, HPI_CHANNEL_MODE_MODE, mode, 0); } u16 hpi_channel_mode_get(u32 h_control, u16 *mode) { u32 mode32 = 0; u16 err = hpi_control_param1_get(h_control, HPI_CHANNEL_MODE_MODE, &mode32); if (mode) *mode = (u16)mode32; return err; } u16 hpi_cobranet_hmi_write(u32 h_control, u32 hmi_address, u32 byte_count, u8 *pb_data) { struct hpi_msg_cobranet_hmiwrite hm; struct hpi_response_header hr; hpi_init_message_responseV1(&hm.h, sizeof(hm), &hr, sizeof(hr), HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.h.adapter_index, &hm.h.obj_index)) return HPI_ERROR_INVALID_HANDLE; if (byte_count > sizeof(hm.bytes)) return HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; hm.p.attribute = HPI_COBRANET_SET; hm.p.byte_count = byte_count; hm.p.hmi_address = hmi_address; memcpy(hm.bytes, pb_data, byte_count); hm.h.size = (u16)(sizeof(hm.h) + sizeof(hm.p) + byte_count); hpi_send_recvV1(&hm.h, &hr); return hr.error; } u16 hpi_cobranet_hmi_read(u32 h_control, u32 hmi_address, u32 max_byte_count, u32 *pbyte_count, u8 *pb_data) { struct hpi_msg_cobranet_hmiread hm; struct hpi_res_cobranet_hmiread hr; hpi_init_message_responseV1(&hm.h, sizeof(hm), &hr.h, sizeof(hr), HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.h.adapter_index, &hm.h.obj_index)) return HPI_ERROR_INVALID_HANDLE; if (max_byte_count > sizeof(hr.bytes)) return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; hm.p.attribute = HPI_COBRANET_GET; hm.p.byte_count = max_byte_count; hm.p.hmi_address = hmi_address; hpi_send_recvV1(&hm.h, &hr.h); if (!hr.h.error && pb_data) { if (hr.byte_count > sizeof(hr.bytes)) return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; *pbyte_count = hr.byte_count; if (hr.byte_count < max_byte_count) max_byte_count = *pbyte_count; memcpy(pb_data, hr.bytes, max_byte_count); } return hr.h.error; } u16 hpi_cobranet_hmi_get_status(u32 h_control, u32 *pstatus, u32 *preadable_size, u32 *pwriteable_size) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_COBRANET_GET_STATUS; hpi_send_recv(&hm, &hr); if (!hr.error) { if (pstatus) *pstatus = hr.u.cu.cobranet.status.status; if (preadable_size) *preadable_size = hr.u.cu.cobranet.status.readable_size; if (pwriteable_size) *pwriteable_size = hr.u.cu.cobranet.status.writeable_size; } return hr.error; } u16 hpi_cobranet_get_ip_address(u32 h_control, u32 *pdw_ip_address) { u32 byte_count; u32 iP; u16 err; err = hpi_cobranet_hmi_read(h_control, HPI_COBRANET_HMI_cobra_ip_mon_currentIP, 4, &byte_count, (u8 *)&iP); *pdw_ip_address = ((iP & 0xff000000) >> 8) | ((iP & 0x00ff0000) << 8) | ((iP & 0x0000ff00) >> 8) | ((iP & 0x000000ff) << 8); if (err) *pdw_ip_address = 0; return err; } u16 hpi_cobranet_set_ip_address(u32 h_control, u32 dw_ip_address) { u32 iP; u16 err; iP = ((dw_ip_address & 0xff000000) >> 8) | ((dw_ip_address & 0x00ff0000) << 8) | ((dw_ip_address & 0x0000ff00) >> 8) | ((dw_ip_address & 0x000000ff) << 8); err = hpi_cobranet_hmi_write(h_control, HPI_COBRANET_HMI_cobra_ip_mon_currentIP, 4, (u8 *)&iP); return err; } u16 hpi_cobranet_get_static_ip_address(u32 h_control, u32 *pdw_ip_address) { u32 byte_count; u32 iP; u16 err; err = hpi_cobranet_hmi_read(h_control, HPI_COBRANET_HMI_cobra_ip_mon_staticIP, 4, &byte_count, (u8 *)&iP); *pdw_ip_address = ((iP & 0xff000000) >> 8) | ((iP & 0x00ff0000) << 8) | ((iP & 0x0000ff00) >> 8) | ((iP & 0x000000ff) << 8); if (err) *pdw_ip_address = 0; return err; } u16 hpi_cobranet_set_static_ip_address(u32 h_control, u32 dw_ip_address) { u32 iP; u16 err; iP = ((dw_ip_address & 0xff000000) >> 8) | ((dw_ip_address & 0x00ff0000) << 8) | ((dw_ip_address & 0x0000ff00) >> 8) | ((dw_ip_address & 0x000000ff) << 8); err = hpi_cobranet_hmi_write(h_control, HPI_COBRANET_HMI_cobra_ip_mon_staticIP, 4, (u8 *)&iP); return err; } u16 hpi_cobranet_get_macaddress(u32 h_control, u32 *p_mac_msbs, u32 *p_mac_lsbs) { u32 byte_count; u16 err; u32 mac; err = hpi_cobranet_hmi_read(h_control, HPI_COBRANET_HMI_cobra_if_phy_address, 4, &byte_count, (u8 *)&mac); if (!err) { *p_mac_msbs = ((mac & 0xff000000) >> 8) | ((mac & 0x00ff0000) << 8) | ((mac & 0x0000ff00) >> 8) | ((mac & 0x000000ff) << 8); err = hpi_cobranet_hmi_read(h_control, HPI_COBRANET_HMI_cobra_if_phy_address + 1, 4, &byte_count, (u8 *)&mac); } if (!err) { *p_mac_lsbs = ((mac & 0xff000000) >> 8) | ((mac & 0x00ff0000) << 8) | ((mac & 0x0000ff00) >> 8) | ((mac & 0x000000ff) << 8); } else { *p_mac_msbs = 0; *p_mac_lsbs = 0; } return err; } u16 hpi_compander_set_enable(u32 h_control, u32 enable) { return hpi_control_param_set(h_control, HPI_GENERIC_ENABLE, enable, 0); } u16 hpi_compander_get_enable(u32 h_control, u32 *enable) { return hpi_control_param1_get(h_control, HPI_GENERIC_ENABLE, enable); } u16 hpi_compander_set_makeup_gain(u32 h_control, short makeup_gain0_01dB) { return hpi_control_log_set2(h_control, HPI_COMPANDER_MAKEUPGAIN, makeup_gain0_01dB, 0); } u16 hpi_compander_get_makeup_gain(u32 h_control, short *makeup_gain0_01dB) { return hpi_control_log_get2(h_control, HPI_COMPANDER_MAKEUPGAIN, makeup_gain0_01dB, NULL); } u16 hpi_compander_set_attack_time_constant(u32 h_control, unsigned int index, u32 attack) { return hpi_control_param_set(h_control, HPI_COMPANDER_ATTACK, attack, index); } u16 hpi_compander_get_attack_time_constant(u32 h_control, unsigned int index, u32 *attack) { return hpi_control_param_get(h_control, HPI_COMPANDER_ATTACK, 0, index, attack, NULL); } u16 hpi_compander_set_decay_time_constant(u32 h_control, unsigned int index, u32 decay) { return hpi_control_param_set(h_control, HPI_COMPANDER_DECAY, decay, index); } u16 hpi_compander_get_decay_time_constant(u32 h_control, unsigned int index, u32 *decay) { return hpi_control_param_get(h_control, HPI_COMPANDER_DECAY, 0, index, decay, NULL); } u16 hpi_compander_set_threshold(u32 h_control, unsigned int index, short threshold0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_COMPANDER_THRESHOLD; hm.u.c.param2 = index; hm.u.c.an_log_value[0] = threshold0_01dB; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_compander_get_threshold(u32 h_control, unsigned int index, short *threshold0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_COMPANDER_THRESHOLD; hm.u.c.param2 = index; hpi_send_recv(&hm, &hr); *threshold0_01dB = hr.u.c.an_log_value[0]; return hr.error; } u16 hpi_compander_set_ratio(u32 h_control, u32 index, u32 ratio100) { return hpi_control_param_set(h_control, HPI_COMPANDER_RATIO, ratio100, index); } u16 hpi_compander_get_ratio(u32 h_control, u32 index, u32 *ratio100) { return hpi_control_param_get(h_control, HPI_COMPANDER_RATIO, 0, index, ratio100, NULL); } u16 hpi_level_query_range(u32 h_control, short *min_gain_01dB, short *max_gain_01dB, short *step_gain_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_LEVEL_RANGE; hpi_send_recv(&hm, &hr); if (hr.error) { hr.u.c.an_log_value[0] = 0; hr.u.c.an_log_value[1] = 0; hr.u.c.param1 = 0; } if (min_gain_01dB) *min_gain_01dB = hr.u.c.an_log_value[0]; if (max_gain_01dB) *max_gain_01dB = hr.u.c.an_log_value[1]; if (step_gain_01dB) *step_gain_01dB = (short)hr.u.c.param1; return hr.error; } u16 hpi_level_set_gain(u32 h_control, short an_gain0_01dB[HPI_MAX_CHANNELS] ) { return hpi_control_log_set2(h_control, HPI_LEVEL_GAIN, an_gain0_01dB[0], an_gain0_01dB[1]); } u16 hpi_level_get_gain(u32 h_control, short an_gain0_01dB[HPI_MAX_CHANNELS] ) { return hpi_control_log_get2(h_control, HPI_LEVEL_GAIN, &an_gain0_01dB[0], &an_gain0_01dB[1]); } u16 hpi_meter_query_channels(const u32 h_meter, u32 *p_channels) { return hpi_control_query(h_meter, HPI_METER_NUM_CHANNELS, 0, 0, p_channels); } u16 hpi_meter_get_peak(u32 h_control, short an_peakdB[HPI_MAX_CHANNELS] ) { short i = 0; struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_METER_PEAK; hpi_send_recv(&hm, &hr); if (!hr.error) memcpy(an_peakdB, hr.u.c.an_log_value, sizeof(short) * HPI_MAX_CHANNELS); else for (i = 0; i < HPI_MAX_CHANNELS; i++) an_peakdB[i] = HPI_METER_MINIMUM; return hr.error; } u16 hpi_meter_get_rms(u32 h_control, short an_rmsdB[HPI_MAX_CHANNELS] ) { short i = 0; struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_METER_RMS; hpi_send_recv(&hm, &hr); if (!hr.error) memcpy(an_rmsdB, hr.u.c.an_log_value, sizeof(short) * HPI_MAX_CHANNELS); else for (i = 0; i < HPI_MAX_CHANNELS; i++) an_rmsdB[i] = HPI_METER_MINIMUM; return hr.error; } u16 hpi_meter_set_rms_ballistics(u32 h_control, u16 attack, u16 decay) { return hpi_control_param_set(h_control, HPI_METER_RMS_BALLISTICS, attack, decay); } u16 hpi_meter_get_rms_ballistics(u32 h_control, u16 *pn_attack, u16 *pn_decay) { u32 attack; u32 decay; u16 error; error = hpi_control_param2_get(h_control, HPI_METER_RMS_BALLISTICS, &attack, &decay); if (pn_attack) *pn_attack = (unsigned short)attack; if (pn_decay) *pn_decay = (unsigned short)decay; return error; } u16 hpi_meter_set_peak_ballistics(u32 h_control, u16 attack, u16 decay) { return hpi_control_param_set(h_control, HPI_METER_PEAK_BALLISTICS, attack, decay); } u16 hpi_meter_get_peak_ballistics(u32 h_control, u16 *pn_attack, u16 *pn_decay) { u32 attack; u32 decay; u16 error; error = hpi_control_param2_get(h_control, HPI_METER_PEAK_BALLISTICS, &attack, &decay); if (pn_attack) *pn_attack = (short)attack; if (pn_decay) *pn_decay = (short)decay; return error; } u16 hpi_microphone_set_phantom_power(u32 h_control, u16 on_off) { return hpi_control_param_set(h_control, HPI_MICROPHONE_PHANTOM_POWER, (u32)on_off, 0); } u16 hpi_microphone_get_phantom_power(u32 h_control, u16 *pw_on_off) { u16 error = 0; u32 on_off = 0; error = hpi_control_param1_get(h_control, HPI_MICROPHONE_PHANTOM_POWER, &on_off); if (pw_on_off) *pw_on_off = (u16)on_off; return error; } u16 hpi_multiplexer_set_source(u32 h_control, u16 source_node_type, u16 source_node_index) { return hpi_control_param_set(h_control, HPI_MULTIPLEXER_SOURCE, source_node_type, source_node_index); } u16 hpi_multiplexer_get_source(u32 h_control, u16 *source_node_type, u16 *source_node_index) { u32 node, index; u16 err = hpi_control_param2_get(h_control, HPI_MULTIPLEXER_SOURCE, &node, &index); if (source_node_type) *source_node_type = (u16)node; if (source_node_index) *source_node_index = (u16)index; return err; } u16 hpi_multiplexer_query_source(u32 h_control, u16 index, u16 *source_node_type, u16 *source_node_index) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_MULTIPLEXER_QUERYSOURCE; hm.u.c.param1 = index; hpi_send_recv(&hm, &hr); if (source_node_type) *source_node_type = (u16)hr.u.c.param1; if (source_node_index) *source_node_index = (u16)hr.u.c.param2; return hr.error; } u16 hpi_parametric_eq_get_info(u32 h_control, u16 *pw_number_of_bands, u16 *pw_on_off) { u32 oB = 0; u32 oO = 0; u16 error = 0; error = hpi_control_param2_get(h_control, HPI_EQUALIZER_NUM_FILTERS, &oO, &oB); if (pw_number_of_bands) *pw_number_of_bands = (u16)oB; if (pw_on_off) *pw_on_off = (u16)oO; return error; } u16 hpi_parametric_eq_set_state(u32 h_control, u16 on_off) { return hpi_control_param_set(h_control, HPI_EQUALIZER_NUM_FILTERS, on_off, 0); } u16 hpi_parametric_eq_get_band(u32 h_control, u16 index, u16 *pn_type, u32 *pfrequency_hz, short *pnQ100, short *pn_gain0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_EQUALIZER_FILTER; hm.u.c.param2 = index; hpi_send_recv(&hm, &hr); if (pfrequency_hz) *pfrequency_hz = hr.u.c.param1; if (pn_type) *pn_type = (u16)(hr.u.c.param2 >> 16); if (pnQ100) *pnQ100 = hr.u.c.an_log_value[1]; if (pn_gain0_01dB) *pn_gain0_01dB = hr.u.c.an_log_value[0]; return hr.error; } u16 hpi_parametric_eq_set_band(u32 h_control, u16 index, u16 type, u32 frequency_hz, short q100, short gain0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.param1 = frequency_hz; hm.u.c.param2 = (index & 0xFFFFL) + ((u32)type << 16); hm.u.c.an_log_value[0] = gain0_01dB; hm.u.c.an_log_value[1] = q100; hm.u.c.attribute = HPI_EQUALIZER_FILTER; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_parametric_eq_get_coeffs(u32 h_control, u16 index, short coeffs[5] ) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_EQUALIZER_COEFFICIENTS; hm.u.c.param2 = index; hpi_send_recv(&hm, &hr); coeffs[0] = (short)hr.u.c.an_log_value[0]; coeffs[1] = (short)hr.u.c.an_log_value[1]; coeffs[2] = (short)hr.u.c.param1; coeffs[3] = (short)(hr.u.c.param1 >> 16); coeffs[4] = (short)hr.u.c.param2; return hr.error; } u16 hpi_sample_clock_query_source(const u32 h_clock, const u32 index, u16 *pw_source) { u32 qr; u16 err; err = hpi_control_query(h_clock, HPI_SAMPLECLOCK_SOURCE, index, 0, &qr); *pw_source = (u16)qr; return err; } u16 hpi_sample_clock_set_source(u32 h_control, u16 source) { return hpi_control_param_set(h_control, HPI_SAMPLECLOCK_SOURCE, source, 0); } u16 hpi_sample_clock_get_source(u32 h_control, u16 *pw_source) { u16 err = 0; u32 source = 0; err = hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_SOURCE, &source); if (!err) if (pw_source) *pw_source = (u16)source; return err; } u16 hpi_sample_clock_query_source_index(const u32 h_clock, const u32 index, const u32 source, u16 *pw_source_index) { u32 qr; u16 err; err = hpi_control_query(h_clock, HPI_SAMPLECLOCK_SOURCE_INDEX, index, source, &qr); *pw_source_index = (u16)qr; return err; } u16 hpi_sample_clock_set_source_index(u32 h_control, u16 source_index) { return hpi_control_param_set(h_control, HPI_SAMPLECLOCK_SOURCE_INDEX, source_index, 0); } u16 hpi_sample_clock_get_source_index(u32 h_control, u16 *pw_source_index) { u16 err = 0; u32 source_index = 0; err = hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_SOURCE_INDEX, &source_index); if (!err) if (pw_source_index) *pw_source_index = (u16)source_index; return err; } u16 hpi_sample_clock_query_local_rate(const u32 h_clock, const u32 index, u32 *prate) { return hpi_control_query(h_clock, HPI_SAMPLECLOCK_LOCAL_SAMPLERATE, index, 0, prate); } u16 hpi_sample_clock_set_local_rate(u32 h_control, u32 sample_rate) { return hpi_control_param_set(h_control, HPI_SAMPLECLOCK_LOCAL_SAMPLERATE, sample_rate, 0); } u16 hpi_sample_clock_get_local_rate(u32 h_control, u32 *psample_rate) { u16 err = 0; u32 sample_rate = 0; err = hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_LOCAL_SAMPLERATE, &sample_rate); if (!err) if (psample_rate) *psample_rate = sample_rate; return err; } u16 hpi_sample_clock_get_sample_rate(u32 h_control, u32 *psample_rate) { u16 err = 0; u32 sample_rate = 0; err = hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_SAMPLERATE, &sample_rate); if (!err) if (psample_rate) *psample_rate = sample_rate; return err; } u16 hpi_sample_clock_set_auto(u32 h_control, u32 enable) { return hpi_control_param_set(h_control, HPI_SAMPLECLOCK_AUTO, enable, 0); } u16 hpi_sample_clock_get_auto(u32 h_control, u32 *penable) { return hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_AUTO, penable); } u16 hpi_sample_clock_set_local_rate_lock(u32 h_control, u32 lock) { return hpi_control_param_set(h_control, HPI_SAMPLECLOCK_LOCAL_LOCK, lock, 0); } u16 hpi_sample_clock_get_local_rate_lock(u32 h_control, u32 *plock) { return hpi_control_param1_get(h_control, HPI_SAMPLECLOCK_LOCAL_LOCK, plock); } u16 hpi_tone_detector_get_frequency(u32 h_control, u32 index, u32 *frequency) { return hpi_control_param_get(h_control, HPI_TONEDETECTOR_FREQUENCY, index, 0, frequency, NULL); } u16 hpi_tone_detector_get_state(u32 h_control, u32 *state) { return hpi_control_param1_get(h_control, HPI_TONEDETECTOR_STATE, state); } u16 hpi_tone_detector_set_enable(u32 h_control, u32 enable) { return hpi_control_param_set(h_control, HPI_GENERIC_ENABLE, enable, 0); } u16 hpi_tone_detector_get_enable(u32 h_control, u32 *enable) { return hpi_control_param1_get(h_control, HPI_GENERIC_ENABLE, enable); } u16 hpi_tone_detector_set_event_enable(u32 h_control, u32 event_enable) { return hpi_control_param_set(h_control, HPI_GENERIC_EVENT_ENABLE, (u32)event_enable, 0); } u16 hpi_tone_detector_get_event_enable(u32 h_control, u32 *event_enable) { return hpi_control_param1_get(h_control, HPI_GENERIC_EVENT_ENABLE, event_enable); } u16 hpi_tone_detector_set_threshold(u32 h_control, int threshold) { return hpi_control_param_set(h_control, HPI_TONEDETECTOR_THRESHOLD, (u32)threshold, 0); } u16 hpi_tone_detector_get_threshold(u32 h_control, int *threshold) { return hpi_control_param1_get(h_control, HPI_TONEDETECTOR_THRESHOLD, (u32 *)threshold); } u16 hpi_silence_detector_get_state(u32 h_control, u32 *state) { return hpi_control_param1_get(h_control, HPI_SILENCEDETECTOR_STATE, state); } u16 hpi_silence_detector_set_enable(u32 h_control, u32 enable) { return hpi_control_param_set(h_control, HPI_GENERIC_ENABLE, enable, 0); } u16 hpi_silence_detector_get_enable(u32 h_control, u32 *enable) { return hpi_control_param1_get(h_control, HPI_GENERIC_ENABLE, enable); } u16 hpi_silence_detector_set_event_enable(u32 h_control, u32 event_enable) { return hpi_control_param_set(h_control, HPI_GENERIC_EVENT_ENABLE, event_enable, 0); } u16 hpi_silence_detector_get_event_enable(u32 h_control, u32 *event_enable) { return hpi_control_param1_get(h_control, HPI_GENERIC_EVENT_ENABLE, event_enable); } u16 hpi_silence_detector_set_delay(u32 h_control, u32 delay) { return hpi_control_param_set(h_control, HPI_SILENCEDETECTOR_DELAY, delay, 0); } u16 hpi_silence_detector_get_delay(u32 h_control, u32 *delay) { return hpi_control_param1_get(h_control, HPI_SILENCEDETECTOR_DELAY, delay); } u16 hpi_silence_detector_set_threshold(u32 h_control, int threshold) { return hpi_control_param_set(h_control, HPI_SILENCEDETECTOR_THRESHOLD, threshold, 0); } u16 hpi_silence_detector_get_threshold(u32 h_control, int *threshold) { return hpi_control_param1_get(h_control, HPI_SILENCEDETECTOR_THRESHOLD, (u32 *)threshold); } u16 hpi_tuner_query_band(const u32 h_tuner, const u32 index, u16 *pw_band) { u32 qr; u16 err; err = hpi_control_query(h_tuner, HPI_TUNER_BAND, index, 0, &qr); *pw_band = (u16)qr; return err; } u16 hpi_tuner_set_band(u32 h_control, u16 band) { return hpi_control_param_set(h_control, HPI_TUNER_BAND, band, 0); } u16 hpi_tuner_get_band(u32 h_control, u16 *pw_band) { u32 band = 0; u16 error = 0; error = hpi_control_param1_get(h_control, HPI_TUNER_BAND, &band); if (pw_band) *pw_band = (u16)band; return error; } u16 hpi_tuner_query_frequency(const u32 h_tuner, const u32 index, const u16 band, u32 *pfreq) { return hpi_control_query(h_tuner, HPI_TUNER_FREQ, index, band, pfreq); } u16 hpi_tuner_set_frequency(u32 h_control, u32 freq_ink_hz) { return hpi_control_param_set(h_control, HPI_TUNER_FREQ, freq_ink_hz, 0); } u16 hpi_tuner_get_frequency(u32 h_control, u32 *pw_freq_ink_hz) { return hpi_control_param1_get(h_control, HPI_TUNER_FREQ, pw_freq_ink_hz); } u16 hpi_tuner_query_gain(const u32 h_tuner, const u32 index, u16 *pw_gain) { u32 qr; u16 err; err = hpi_control_query(h_tuner, HPI_TUNER_BAND, index, 0, &qr); *pw_gain = (u16)qr; return err; } u16 hpi_tuner_set_gain(u32 h_control, short gain) { return hpi_control_param_set(h_control, HPI_TUNER_GAIN, gain, 0); } u16 hpi_tuner_get_gain(u32 h_control, short *pn_gain) { u32 gain = 0; u16 error = 0; error = hpi_control_param1_get(h_control, HPI_TUNER_GAIN, &gain); if (pn_gain) *pn_gain = (u16)gain; return error; } u16 hpi_tuner_get_rf_level(u32 h_control, short *pw_level) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.cu.attribute = HPI_TUNER_LEVEL_AVG; hpi_send_recv(&hm, &hr); if (pw_level) *pw_level = hr.u.cu.tuner.s_level; return hr.error; } u16 hpi_tuner_get_raw_rf_level(u32 h_control, short *pw_level) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.cu.attribute = HPI_TUNER_LEVEL_RAW; hpi_send_recv(&hm, &hr); if (pw_level) *pw_level = hr.u.cu.tuner.s_level; return hr.error; } u16 hpi_tuner_query_deemphasis(const u32 h_tuner, const u32 index, const u16 band, u32 *pdeemphasis) { return hpi_control_query(h_tuner, HPI_TUNER_DEEMPHASIS, index, band, pdeemphasis); } u16 hpi_tuner_set_deemphasis(u32 h_control, u32 deemphasis) { return hpi_control_param_set(h_control, HPI_TUNER_DEEMPHASIS, deemphasis, 0); } u16 hpi_tuner_get_deemphasis(u32 h_control, u32 *pdeemphasis) { return hpi_control_param1_get(h_control, HPI_TUNER_DEEMPHASIS, pdeemphasis); } u16 hpi_tuner_query_program(const u32 h_tuner, u32 *pbitmap_program) { return hpi_control_query(h_tuner, HPI_TUNER_PROGRAM, 0, 0, pbitmap_program); } u16 hpi_tuner_set_program(u32 h_control, u32 program) { return hpi_control_param_set(h_control, HPI_TUNER_PROGRAM, program, 0); } u16 hpi_tuner_get_program(u32 h_control, u32 *pprogram) { return hpi_control_param1_get(h_control, HPI_TUNER_PROGRAM, pprogram); } u16 hpi_tuner_get_hd_radio_dsp_version(u32 h_control, char *psz_dsp_version, const u32 string_size) { return hpi_control_get_string(h_control, HPI_TUNER_HDRADIO_DSP_VERSION, psz_dsp_version, string_size); } u16 hpi_tuner_get_hd_radio_sdk_version(u32 h_control, char *psz_sdk_version, const u32 string_size) { return hpi_control_get_string(h_control, HPI_TUNER_HDRADIO_SDK_VERSION, psz_sdk_version, string_size); } u16 hpi_tuner_get_status(u32 h_control, u16 *pw_status_mask, u16 *pw_status) { u32 status = 0; u16 error = 0; error = hpi_control_param1_get(h_control, HPI_TUNER_STATUS, &status); if (pw_status) { if (!error) { *pw_status_mask = (u16)(status >> 16); *pw_status = (u16)(status & 0xFFFF); } else { *pw_status_mask = 0; *pw_status = 0; } } return error; } u16 hpi_tuner_set_mode(u32 h_control, u32 mode, u32 value) { return hpi_control_param_set(h_control, HPI_TUNER_MODE, mode, value); } u16 hpi_tuner_get_mode(u32 h_control, u32 mode, u32 *pn_value) { return hpi_control_param_get(h_control, HPI_TUNER_MODE, mode, 0, pn_value, NULL); } u16 hpi_tuner_get_hd_radio_signal_quality(u32 h_control, u32 *pquality) { return hpi_control_param1_get(h_control, HPI_TUNER_HDRADIO_SIGNAL_QUALITY, pquality); } u16 hpi_tuner_get_hd_radio_signal_blend(u32 h_control, u32 *pblend) { return hpi_control_param1_get(h_control, HPI_TUNER_HDRADIO_BLEND, pblend); } u16 hpi_tuner_set_hd_radio_signal_blend(u32 h_control, const u32 blend) { return hpi_control_param_set(h_control, HPI_TUNER_HDRADIO_BLEND, blend, 0); } u16 hpi_tuner_get_rds(u32 h_control, char *p_data) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_TUNER_RDS; hpi_send_recv(&hm, &hr); if (p_data) { *(u32 *)&p_data[0] = hr.u.cu.tuner.rds.data[0]; *(u32 *)&p_data[4] = hr.u.cu.tuner.rds.data[1]; *(u32 *)&p_data[8] = hr.u.cu.tuner.rds.bLER; } return hr.error; } u16 hpi_pad_get_channel_name(u32 h_control, char *psz_string, const u32 data_length) { return hpi_control_get_string(h_control, HPI_PAD_CHANNEL_NAME, psz_string, data_length); } u16 hpi_pad_get_artist(u32 h_control, char *psz_string, const u32 data_length) { return hpi_control_get_string(h_control, HPI_PAD_ARTIST, psz_string, data_length); } u16 hpi_pad_get_title(u32 h_control, char *psz_string, const u32 data_length) { return hpi_control_get_string(h_control, HPI_PAD_TITLE, psz_string, data_length); } u16 hpi_pad_get_comment(u32 h_control, char *psz_string, const u32 data_length) { return hpi_control_get_string(h_control, HPI_PAD_COMMENT, psz_string, data_length); } u16 hpi_pad_get_program_type(u32 h_control, u32 *ppTY) { return hpi_control_param1_get(h_control, HPI_PAD_PROGRAM_TYPE, ppTY); } u16 hpi_pad_get_rdsPI(u32 h_control, u32 *ppI) { return hpi_control_param1_get(h_control, HPI_PAD_PROGRAM_ID, ppI); } u16 hpi_volume_query_channels(const u32 h_volume, u32 *p_channels) { return hpi_control_query(h_volume, HPI_VOLUME_NUM_CHANNELS, 0, 0, p_channels); } u16 hpi_volume_set_gain(u32 h_control, short an_log_gain[HPI_MAX_CHANNELS] ) { return hpi_control_log_set2(h_control, HPI_VOLUME_GAIN, an_log_gain[0], an_log_gain[1]); } u16 hpi_volume_get_gain(u32 h_control, short an_log_gain[HPI_MAX_CHANNELS] ) { return hpi_control_log_get2(h_control, HPI_VOLUME_GAIN, &an_log_gain[0], &an_log_gain[1]); } u16 hpi_volume_set_mute(u32 h_control, u32 mute) { return hpi_control_param_set(h_control, HPI_VOLUME_MUTE, mute, 0); } u16 hpi_volume_get_mute(u32 h_control, u32 *mute) { return hpi_control_param1_get(h_control, HPI_VOLUME_MUTE, mute); } u16 hpi_volume_query_range(u32 h_control, short *min_gain_01dB, short *max_gain_01dB, short *step_gain_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_VOLUME_RANGE; hpi_send_recv(&hm, &hr); if (hr.error) { hr.u.c.an_log_value[0] = 0; hr.u.c.an_log_value[1] = 0; hr.u.c.param1 = 0; } if (min_gain_01dB) *min_gain_01dB = hr.u.c.an_log_value[0]; if (max_gain_01dB) *max_gain_01dB = hr.u.c.an_log_value[1]; if (step_gain_01dB) *step_gain_01dB = (short)hr.u.c.param1; return hr.error; } u16 hpi_volume_auto_fade_profile(u32 h_control, short an_stop_gain0_01dB[HPI_MAX_CHANNELS], u32 duration_ms, u16 profile) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; memcpy(hm.u.c.an_log_value, an_stop_gain0_01dB, sizeof(short) * HPI_MAX_CHANNELS); hm.u.c.attribute = HPI_VOLUME_AUTOFADE; hm.u.c.param1 = duration_ms; hm.u.c.param2 = profile; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_volume_auto_fade(u32 h_control, short an_stop_gain0_01dB[HPI_MAX_CHANNELS], u32 duration_ms) { return hpi_volume_auto_fade_profile(h_control, an_stop_gain0_01dB, duration_ms, HPI_VOLUME_AUTOFADE_LOG); } u16 hpi_volume_query_auto_fade_profile(const u32 h_volume, const u32 i, u16 *profile) { u16 e; u32 u; e = hpi_control_query(h_volume, HPI_VOLUME_AUTOFADE, i, 0, &u); *profile = (u16)u; return e; } u16 hpi_vox_set_threshold(u32 h_control, short an_gain0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_SET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_VOX_THRESHOLD; hm.u.c.an_log_value[0] = an_gain0_01dB; hpi_send_recv(&hm, &hr); return hr.error; } u16 hpi_vox_get_threshold(u32 h_control, short *an_gain0_01dB) { struct hpi_message hm; struct hpi_response hr; hpi_init_message_response(&hm, &hr, HPI_OBJ_CONTROL, HPI_CONTROL_GET_STATE); if (hpi_handle_indexes(h_control, &hm.adapter_index, &hm.obj_index)) return HPI_ERROR_INVALID_HANDLE; hm.u.c.attribute = HPI_VOX_THRESHOLD; hpi_send_recv(&hm, &hr); *an_gain0_01dB = hr.u.c.an_log_value[0]; return hr.error; }
linux-master
sound/pci/asihpi/hpifunc.c
// SPDX-License-Identifier: GPL-2.0-only /*********************************************************************** AudioScience HPI driver Functions for reading DSP code using hotplug firmware loader Copyright (C) 1997-2014 AudioScience Inc. <[email protected]> ***********************************************************************/ #define SOURCEFILE_NAME "hpidspcd.c" #include "hpidspcd.h" #include "hpidebug.h" #include "hpi_version.h" struct dsp_code_private { /** Firmware descriptor */ const struct firmware *firmware; struct pci_dev *dev; }; /*-------------------------------------------------------------------*/ short hpi_dsp_code_open(u32 adapter, void *os_data, struct dsp_code *dsp_code, u32 *os_error_code) { const struct firmware *firmware; struct pci_dev *dev = os_data; struct code_header header; char fw_name[20]; short err_ret = HPI_ERROR_DSP_FILE_NOT_FOUND; int err; sprintf(fw_name, "asihpi/dsp%04x.bin", adapter); err = request_firmware(&firmware, fw_name, &dev->dev); if (err || !firmware) { dev_err(&dev->dev, "%d, request_firmware failed for %s\n", err, fw_name); goto error1; } if (firmware->size < sizeof(header)) { dev_err(&dev->dev, "Header size too small %s\n", fw_name); goto error2; } memcpy(&header, firmware->data, sizeof(header)); if ((header.type != 0x45444F43) || /* "CODE" */ (header.adapter != adapter) || (header.size != firmware->size)) { dev_err(&dev->dev, "Invalid firmware header size %d != file %zd\n", header.size, firmware->size); goto error2; } if (HPI_VER_MAJOR(header.version) != HPI_VER_MAJOR(HPI_VER)) { /* Major version change probably means Host-DSP protocol change */ dev_err(&dev->dev, "Incompatible firmware version DSP image %X != Driver %X\n", header.version, HPI_VER); goto error2; } if (header.version != HPI_VER) { dev_warn(&dev->dev, "Firmware version mismatch: DSP image %X != Driver %X\n", header.version, HPI_VER); } HPI_DEBUG_LOG(DEBUG, "dsp code %s opened\n", fw_name); dsp_code->pvt = kmalloc(sizeof(*dsp_code->pvt), GFP_KERNEL); if (!dsp_code->pvt) { err_ret = HPI_ERROR_MEMORY_ALLOC; goto error2; } dsp_code->pvt->dev = dev; dsp_code->pvt->firmware = firmware; dsp_code->header = header; dsp_code->block_length = header.size / sizeof(u32); dsp_code->word_count = sizeof(header) / sizeof(u32); return 0; error2: release_firmware(firmware); error1: dsp_code->block_length = 0; return err_ret; } /*-------------------------------------------------------------------*/ void hpi_dsp_code_close(struct dsp_code *dsp_code) { HPI_DEBUG_LOG(DEBUG, "dsp code closed\n"); release_firmware(dsp_code->pvt->firmware); kfree(dsp_code->pvt); } /*-------------------------------------------------------------------*/ void hpi_dsp_code_rewind(struct dsp_code *dsp_code) { /* Go back to start of data, after header */ dsp_code->word_count = sizeof(struct code_header) / sizeof(u32); } /*-------------------------------------------------------------------*/ short hpi_dsp_code_read_word(struct dsp_code *dsp_code, u32 *pword) { if (dsp_code->word_count + 1 > dsp_code->block_length) return HPI_ERROR_DSP_FILE_FORMAT; *pword = ((u32 *)(dsp_code->pvt->firmware->data))[dsp_code-> word_count]; dsp_code->word_count++; return 0; } /*-------------------------------------------------------------------*/ short hpi_dsp_code_read_block(size_t words_requested, struct dsp_code *dsp_code, u32 **ppblock) { if (dsp_code->word_count + words_requested > dsp_code->block_length) return HPI_ERROR_DSP_FILE_FORMAT; *ppblock = ((u32 *)(dsp_code->pvt->firmware->data)) + dsp_code->word_count; dsp_code->word_count += words_requested; return 0; }
linux-master
sound/pci/asihpi/hpidspcd.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctamixer.c * * @Brief * This file contains the implementation of the Audio Mixer * resource management object. * * @Author Liu Chun * @Date May 21 2008 */ #include "ctamixer.h" #include "cthardware.h" #include <linux/slab.h> #define AMIXER_RESOURCE_NUM 256 #define SUM_RESOURCE_NUM 256 #define AMIXER_Y_IMMEDIATE 1 #define BLANK_SLOT 4094 static void amixer_master(struct rsc *rsc) { rsc->conj = 0; rsc->idx = container_of(rsc, struct amixer, rsc)->idx[0]; } static void amixer_next_conj(struct rsc *rsc) { rsc->conj++; } static int amixer_index(const struct rsc *rsc) { return container_of(rsc, struct amixer, rsc)->idx[rsc->conj]; } static int amixer_output_slot(const struct rsc *rsc) { return (amixer_index(rsc) << 4) + 0x4; } static const struct rsc_ops amixer_basic_rsc_ops = { .master = amixer_master, .next_conj = amixer_next_conj, .index = amixer_index, .output_slot = amixer_output_slot, }; static int amixer_set_input(struct amixer *amixer, struct rsc *rsc) { struct hw *hw; hw = amixer->rsc.hw; hw->amixer_set_mode(amixer->rsc.ctrl_blk, AMIXER_Y_IMMEDIATE); amixer->input = rsc; if (!rsc) hw->amixer_set_x(amixer->rsc.ctrl_blk, BLANK_SLOT); else hw->amixer_set_x(amixer->rsc.ctrl_blk, rsc->ops->output_slot(rsc)); return 0; } /* y is a 14-bit immediate constant */ static int amixer_set_y(struct amixer *amixer, unsigned int y) { struct hw *hw; hw = amixer->rsc.hw; hw->amixer_set_y(amixer->rsc.ctrl_blk, y); return 0; } static int amixer_set_invalid_squash(struct amixer *amixer, unsigned int iv) { struct hw *hw; hw = amixer->rsc.hw; hw->amixer_set_iv(amixer->rsc.ctrl_blk, iv); return 0; } static int amixer_set_sum(struct amixer *amixer, struct sum *sum) { struct hw *hw; hw = amixer->rsc.hw; amixer->sum = sum; if (!sum) { hw->amixer_set_se(amixer->rsc.ctrl_blk, 0); } else { hw->amixer_set_se(amixer->rsc.ctrl_blk, 1); hw->amixer_set_sadr(amixer->rsc.ctrl_blk, sum->rsc.ops->index(&sum->rsc)); } return 0; } static int amixer_commit_write(struct amixer *amixer) { struct hw *hw; unsigned int index; int i; struct rsc *input; struct sum *sum; hw = amixer->rsc.hw; input = amixer->input; sum = amixer->sum; /* Program master and conjugate resources */ amixer->rsc.ops->master(&amixer->rsc); if (input) input->ops->master(input); if (sum) sum->rsc.ops->master(&sum->rsc); for (i = 0; i < amixer->rsc.msr; i++) { hw->amixer_set_dirty_all(amixer->rsc.ctrl_blk); if (input) { hw->amixer_set_x(amixer->rsc.ctrl_blk, input->ops->output_slot(input)); input->ops->next_conj(input); } if (sum) { hw->amixer_set_sadr(amixer->rsc.ctrl_blk, sum->rsc.ops->index(&sum->rsc)); sum->rsc.ops->next_conj(&sum->rsc); } index = amixer->rsc.ops->output_slot(&amixer->rsc); hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk); amixer->rsc.ops->next_conj(&amixer->rsc); } amixer->rsc.ops->master(&amixer->rsc); if (input) input->ops->master(input); if (sum) sum->rsc.ops->master(&sum->rsc); return 0; } static int amixer_commit_raw_write(struct amixer *amixer) { struct hw *hw; unsigned int index; hw = amixer->rsc.hw; index = amixer->rsc.ops->output_slot(&amixer->rsc); hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk); return 0; } static int amixer_get_y(struct amixer *amixer) { struct hw *hw; hw = amixer->rsc.hw; return hw->amixer_get_y(amixer->rsc.ctrl_blk); } static int amixer_setup(struct amixer *amixer, struct rsc *input, unsigned int scale, struct sum *sum) { amixer_set_input(amixer, input); amixer_set_y(amixer, scale); amixer_set_sum(amixer, sum); amixer_commit_write(amixer); return 0; } static const struct amixer_rsc_ops amixer_ops = { .set_input = amixer_set_input, .set_invalid_squash = amixer_set_invalid_squash, .set_scale = amixer_set_y, .set_sum = amixer_set_sum, .commit_write = amixer_commit_write, .commit_raw_write = amixer_commit_raw_write, .setup = amixer_setup, .get_scale = amixer_get_y, }; static int amixer_rsc_init(struct amixer *amixer, const struct amixer_desc *desc, struct amixer_mgr *mgr) { int err; err = rsc_init(&amixer->rsc, amixer->idx[0], AMIXER, desc->msr, mgr->mgr.hw); if (err) return err; /* Set amixer specific operations */ amixer->rsc.ops = &amixer_basic_rsc_ops; amixer->ops = &amixer_ops; amixer->input = NULL; amixer->sum = NULL; amixer_setup(amixer, NULL, 0, NULL); return 0; } static int amixer_rsc_uninit(struct amixer *amixer) { amixer_setup(amixer, NULL, 0, NULL); rsc_uninit(&amixer->rsc); amixer->ops = NULL; amixer->input = NULL; amixer->sum = NULL; return 0; } static int get_amixer_rsc(struct amixer_mgr *mgr, const struct amixer_desc *desc, struct amixer **ramixer) { int err, i; unsigned int idx; struct amixer *amixer; unsigned long flags; *ramixer = NULL; /* Allocate mem for amixer resource */ amixer = kzalloc(sizeof(*amixer), GFP_KERNEL); if (!amixer) return -ENOMEM; /* Check whether there are sufficient * amixer resources to meet request. */ err = 0; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < desc->msr; i++) { err = mgr_get_resource(&mgr->mgr, 1, &idx); if (err) break; amixer->idx[i] = idx; } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { dev_err(mgr->card->dev, "Can't meet AMIXER resource request!\n"); goto error; } err = amixer_rsc_init(amixer, desc, mgr); if (err) goto error; *ramixer = amixer; return 0; error: spin_lock_irqsave(&mgr->mgr_lock, flags); for (i--; i >= 0; i--) mgr_put_resource(&mgr->mgr, 1, amixer->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); kfree(amixer); return err; } static int put_amixer_rsc(struct amixer_mgr *mgr, struct amixer *amixer) { unsigned long flags; int i; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < amixer->rsc.msr; i++) mgr_put_resource(&mgr->mgr, 1, amixer->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); amixer_rsc_uninit(amixer); kfree(amixer); return 0; } int amixer_mgr_create(struct hw *hw, struct amixer_mgr **ramixer_mgr) { int err; struct amixer_mgr *amixer_mgr; *ramixer_mgr = NULL; amixer_mgr = kzalloc(sizeof(*amixer_mgr), GFP_KERNEL); if (!amixer_mgr) return -ENOMEM; err = rsc_mgr_init(&amixer_mgr->mgr, AMIXER, AMIXER_RESOURCE_NUM, hw); if (err) goto error; spin_lock_init(&amixer_mgr->mgr_lock); amixer_mgr->get_amixer = get_amixer_rsc; amixer_mgr->put_amixer = put_amixer_rsc; amixer_mgr->card = hw->card; *ramixer_mgr = amixer_mgr; return 0; error: kfree(amixer_mgr); return err; } int amixer_mgr_destroy(struct amixer_mgr *amixer_mgr) { rsc_mgr_uninit(&amixer_mgr->mgr); kfree(amixer_mgr); return 0; } /* SUM resource management */ static void sum_master(struct rsc *rsc) { rsc->conj = 0; rsc->idx = container_of(rsc, struct sum, rsc)->idx[0]; } static void sum_next_conj(struct rsc *rsc) { rsc->conj++; } static int sum_index(const struct rsc *rsc) { return container_of(rsc, struct sum, rsc)->idx[rsc->conj]; } static int sum_output_slot(const struct rsc *rsc) { return (sum_index(rsc) << 4) + 0xc; } static const struct rsc_ops sum_basic_rsc_ops = { .master = sum_master, .next_conj = sum_next_conj, .index = sum_index, .output_slot = sum_output_slot, }; static int sum_rsc_init(struct sum *sum, const struct sum_desc *desc, struct sum_mgr *mgr) { int err; err = rsc_init(&sum->rsc, sum->idx[0], SUM, desc->msr, mgr->mgr.hw); if (err) return err; sum->rsc.ops = &sum_basic_rsc_ops; return 0; } static int sum_rsc_uninit(struct sum *sum) { rsc_uninit(&sum->rsc); return 0; } static int get_sum_rsc(struct sum_mgr *mgr, const struct sum_desc *desc, struct sum **rsum) { int err, i; unsigned int idx; struct sum *sum; unsigned long flags; *rsum = NULL; /* Allocate mem for sum resource */ sum = kzalloc(sizeof(*sum), GFP_KERNEL); if (!sum) return -ENOMEM; /* Check whether there are sufficient sum resources to meet request. */ err = 0; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < desc->msr; i++) { err = mgr_get_resource(&mgr->mgr, 1, &idx); if (err) break; sum->idx[i] = idx; } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { dev_err(mgr->card->dev, "Can't meet SUM resource request!\n"); goto error; } err = sum_rsc_init(sum, desc, mgr); if (err) goto error; *rsum = sum; return 0; error: spin_lock_irqsave(&mgr->mgr_lock, flags); for (i--; i >= 0; i--) mgr_put_resource(&mgr->mgr, 1, sum->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); kfree(sum); return err; } static int put_sum_rsc(struct sum_mgr *mgr, struct sum *sum) { unsigned long flags; int i; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < sum->rsc.msr; i++) mgr_put_resource(&mgr->mgr, 1, sum->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); sum_rsc_uninit(sum); kfree(sum); return 0; } int sum_mgr_create(struct hw *hw, struct sum_mgr **rsum_mgr) { int err; struct sum_mgr *sum_mgr; *rsum_mgr = NULL; sum_mgr = kzalloc(sizeof(*sum_mgr), GFP_KERNEL); if (!sum_mgr) return -ENOMEM; err = rsc_mgr_init(&sum_mgr->mgr, SUM, SUM_RESOURCE_NUM, hw); if (err) goto error; spin_lock_init(&sum_mgr->mgr_lock); sum_mgr->get_sum = get_sum_rsc; sum_mgr->put_sum = put_sum_rsc; sum_mgr->card = hw->card; *rsum_mgr = sum_mgr; return 0; error: kfree(sum_mgr); return err; } int sum_mgr_destroy(struct sum_mgr *sum_mgr) { rsc_mgr_uninit(&sum_mgr->mgr); kfree(sum_mgr); return 0; }
linux-master
sound/pci/ctxfi/ctamixer.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctpcm.c * * @Brief * This file contains the definition of the pcm device functions. * * @Author Liu Chun * @Date Apr 2 2008 */ #include "ctpcm.h" #include "cttimer.h" #include <linux/slab.h> #include <sound/pcm.h> /* Hardware descriptions for playback */ static const struct snd_pcm_hardware ct_pcm_playback_hw = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT_LE), .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000), .rate_min = 8000, .rate_max = 192000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = (64), .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; static const struct snd_pcm_hardware ct_spdif_passthru_playback_hw = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_32000), .rate_min = 32000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = (64), .period_bytes_max = (128*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; /* Hardware descriptions for capture */ static const struct snd_pcm_hardware ct_pcm_capture_hw = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_MMAP_VALID), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT_LE), .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_96000), .rate_min = 8000, .rate_max = 96000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = (384), .period_bytes_max = (64*1024), .periods_min = 2, .periods_max = 1024, .fifo_size = 0, }; static void ct_atc_pcm_interrupt(struct ct_atc_pcm *atc_pcm) { struct ct_atc_pcm *apcm = atc_pcm; if (!apcm->substream) return; snd_pcm_period_elapsed(apcm->substream); } static void ct_atc_pcm_free_substream(struct snd_pcm_runtime *runtime) { struct ct_atc_pcm *apcm = runtime->private_data; struct ct_atc *atc = snd_pcm_substream_chip(apcm->substream); atc->pcm_release_resources(atc, apcm); ct_timer_instance_free(apcm->timer); kfree(apcm); runtime->private_data = NULL; } /* pcm playback operations */ static int ct_pcm_playback_open(struct snd_pcm_substream *substream) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm; int err; apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); if (!apcm) return -ENOMEM; apcm->substream = substream; apcm->interrupt = ct_atc_pcm_interrupt; if (IEC958 == substream->pcm->device) { runtime->hw = ct_spdif_passthru_playback_hw; atc->spdif_out_passthru(atc, 1); } else { runtime->hw = ct_pcm_playback_hw; if (FRONT == substream->pcm->device) runtime->hw.channels_max = 8; } err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (err < 0) goto free_pcm; err = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1024, UINT_MAX); if (err < 0) goto free_pcm; apcm->timer = ct_timer_instance_new(atc->timer, apcm); if (!apcm->timer) { err = -ENOMEM; goto free_pcm; } runtime->private_data = apcm; runtime->private_free = ct_atc_pcm_free_substream; return 0; free_pcm: kfree(apcm); return err; } static int ct_pcm_playback_close(struct snd_pcm_substream *substream) { struct ct_atc *atc = snd_pcm_substream_chip(substream); /* TODO: Notify mixer inactive. */ if (IEC958 == substream->pcm->device) atc->spdif_out_passthru(atc, 0); /* The ct_atc_pcm object will be freed by runtime->private_free */ return 0; } static int ct_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct ct_atc_pcm *apcm = substream->runtime->private_data; /* clear previous resources */ atc->pcm_release_resources(atc, apcm); return 0; } static int ct_pcm_hw_free(struct snd_pcm_substream *substream) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct ct_atc_pcm *apcm = substream->runtime->private_data; /* clear previous resources */ atc->pcm_release_resources(atc, apcm); return 0; } static int ct_pcm_playback_prepare(struct snd_pcm_substream *substream) { int err; struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; if (IEC958 == substream->pcm->device) err = atc->spdif_passthru_playback_prepare(atc, apcm); else err = atc->pcm_playback_prepare(atc, apcm); if (err < 0) { dev_err(atc->card->dev, "Preparing pcm playback failed!!!\n"); return err; } return 0; } static int ct_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: atc->pcm_playback_start(atc, apcm); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: atc->pcm_playback_stop(atc, apcm); break; default: break; } return 0; } static snd_pcm_uframes_t ct_pcm_playback_pointer(struct snd_pcm_substream *substream) { unsigned long position; struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; /* Read out playback position */ position = atc->pcm_playback_position(atc, apcm); position = bytes_to_frames(runtime, position); if (position >= runtime->buffer_size) position = 0; return position; } /* pcm capture operations */ static int ct_pcm_capture_open(struct snd_pcm_substream *substream) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm; int err; apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); if (!apcm) return -ENOMEM; apcm->started = 0; apcm->substream = substream; apcm->interrupt = ct_atc_pcm_interrupt; runtime->hw = ct_pcm_capture_hw; runtime->hw.rate_max = atc->rsr * atc->msr; err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (err < 0) goto free_pcm; err = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1024, UINT_MAX); if (err < 0) goto free_pcm; apcm->timer = ct_timer_instance_new(atc->timer, apcm); if (!apcm->timer) { err = -ENOMEM; goto free_pcm; } runtime->private_data = apcm; runtime->private_free = ct_atc_pcm_free_substream; return 0; free_pcm: kfree(apcm); return err; } static int ct_pcm_capture_close(struct snd_pcm_substream *substream) { /* The ct_atc_pcm object will be freed by runtime->private_free */ /* TODO: Notify mixer inactive. */ return 0; } static int ct_pcm_capture_prepare(struct snd_pcm_substream *substream) { int err; struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; err = atc->pcm_capture_prepare(atc, apcm); if (err < 0) { dev_err(atc->card->dev, "Preparing pcm capture failed!!!\n"); return err; } return 0; } static int ct_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; switch (cmd) { case SNDRV_PCM_TRIGGER_START: atc->pcm_capture_start(atc, apcm); break; case SNDRV_PCM_TRIGGER_STOP: atc->pcm_capture_stop(atc, apcm); break; default: atc->pcm_capture_stop(atc, apcm); break; } return 0; } static snd_pcm_uframes_t ct_pcm_capture_pointer(struct snd_pcm_substream *substream) { unsigned long position; struct ct_atc *atc = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = runtime->private_data; /* Read out playback position */ position = atc->pcm_capture_position(atc, apcm); position = bytes_to_frames(runtime, position); if (position >= runtime->buffer_size) position = 0; return position; } /* PCM operators for playback */ static const struct snd_pcm_ops ct_pcm_playback_ops = { .open = ct_pcm_playback_open, .close = ct_pcm_playback_close, .hw_params = ct_pcm_hw_params, .hw_free = ct_pcm_hw_free, .prepare = ct_pcm_playback_prepare, .trigger = ct_pcm_playback_trigger, .pointer = ct_pcm_playback_pointer, }; /* PCM operators for capture */ static const struct snd_pcm_ops ct_pcm_capture_ops = { .open = ct_pcm_capture_open, .close = ct_pcm_capture_close, .hw_params = ct_pcm_hw_params, .hw_free = ct_pcm_hw_free, .prepare = ct_pcm_capture_prepare, .trigger = ct_pcm_capture_trigger, .pointer = ct_pcm_capture_pointer, }; static const struct snd_pcm_chmap_elem surround_map[] = { { .channels = 1, .map = { SNDRV_CHMAP_MONO } }, { .channels = 2, .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, { } }; static const struct snd_pcm_chmap_elem clfe_map[] = { { .channels = 1, .map = { SNDRV_CHMAP_MONO } }, { .channels = 2, .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } }, { } }; static const struct snd_pcm_chmap_elem side_map[] = { { .channels = 1, .map = { SNDRV_CHMAP_MONO } }, { .channels = 2, .map = { SNDRV_CHMAP_SL, SNDRV_CHMAP_SR } }, { } }; /* Create ALSA pcm device */ int ct_alsa_pcm_create(struct ct_atc *atc, enum CTALSADEVS device, const char *device_name) { struct snd_pcm *pcm; const struct snd_pcm_chmap_elem *map; int chs; int err; int playback_count, capture_count; playback_count = (IEC958 == device) ? 1 : 256; capture_count = (FRONT == device) ? 1 : 0; err = snd_pcm_new(atc->card, "ctxfi", device, playback_count, capture_count, &pcm); if (err < 0) { dev_err(atc->card->dev, "snd_pcm_new failed!! Err=%d\n", err); return err; } pcm->private_data = atc; pcm->info_flags = 0; pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX; strscpy(pcm->name, device_name, sizeof(pcm->name)); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &ct_pcm_playback_ops); if (FRONT == device) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &ct_pcm_capture_ops); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &atc->pci->dev, 128*1024, 128*1024); chs = 2; switch (device) { case FRONT: chs = 8; map = snd_pcm_std_chmaps; break; case SURROUND: map = surround_map; break; case CLFE: map = clfe_map; break; case SIDE: map = side_map; break; default: map = snd_pcm_std_chmaps; break; } err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, chs, 0, NULL); if (err < 0) return err; #ifdef CONFIG_PM_SLEEP atc->pcms[device] = pcm; #endif return 0; }
linux-master
sound/pci/ctxfi/ctpcm.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctdaio.c * * @Brief * This file contains the implementation of Digital Audio Input Output * resource management object. * * @Author Liu Chun * @Date May 23 2008 */ #include "ctdaio.h" #include "cthardware.h" #include "ctimap.h" #include <linux/slab.h> #include <linux/kernel.h> #define DAIO_OUT_MAX SPDIFOO struct daio_usage { unsigned short data; }; struct daio_rsc_idx { unsigned short left; unsigned short right; }; static const struct daio_rsc_idx idx_20k1[NUM_DAIOTYP] = { [LINEO1] = {.left = 0x00, .right = 0x01}, [LINEO2] = {.left = 0x18, .right = 0x19}, [LINEO3] = {.left = 0x08, .right = 0x09}, [LINEO4] = {.left = 0x10, .right = 0x11}, [LINEIM] = {.left = 0x1b5, .right = 0x1bd}, [SPDIFOO] = {.left = 0x20, .right = 0x21}, [SPDIFIO] = {.left = 0x15, .right = 0x1d}, [SPDIFI1] = {.left = 0x95, .right = 0x9d}, }; static const struct daio_rsc_idx idx_20k2[NUM_DAIOTYP] = { [LINEO1] = {.left = 0x40, .right = 0x41}, [LINEO2] = {.left = 0x60, .right = 0x61}, [LINEO3] = {.left = 0x50, .right = 0x51}, [LINEO4] = {.left = 0x70, .right = 0x71}, [LINEIM] = {.left = 0x45, .right = 0xc5}, [MIC] = {.left = 0x55, .right = 0xd5}, [SPDIFOO] = {.left = 0x00, .right = 0x01}, [SPDIFIO] = {.left = 0x05, .right = 0x85}, }; static void daio_master(struct rsc *rsc) { /* Actually, this is not the resource index of DAIO. * For DAO, it is the input mapper index. And, for DAI, * it is the output time-slot index. */ rsc->conj = rsc->idx; } static int daio_index(const struct rsc *rsc) { return rsc->conj; } static void daio_out_next_conj(struct rsc *rsc) { rsc->conj += 2; } static void daio_in_next_conj_20k1(struct rsc *rsc) { rsc->conj += 0x200; } static void daio_in_next_conj_20k2(struct rsc *rsc) { rsc->conj += 0x100; } static const struct rsc_ops daio_out_rsc_ops = { .master = daio_master, .next_conj = daio_out_next_conj, .index = daio_index, .output_slot = NULL, }; static const struct rsc_ops daio_in_rsc_ops_20k1 = { .master = daio_master, .next_conj = daio_in_next_conj_20k1, .index = NULL, .output_slot = daio_index, }; static const struct rsc_ops daio_in_rsc_ops_20k2 = { .master = daio_master, .next_conj = daio_in_next_conj_20k2, .index = NULL, .output_slot = daio_index, }; static unsigned int daio_device_index(enum DAIOTYP type, struct hw *hw) { switch (hw->chip_type) { case ATC20K1: switch (type) { case SPDIFOO: return 0; case SPDIFIO: return 0; case SPDIFI1: return 1; case LINEO1: return 4; case LINEO2: return 7; case LINEO3: return 5; case LINEO4: return 6; case LINEIM: return 7; default: return -EINVAL; } case ATC20K2: switch (type) { case SPDIFOO: return 0; case SPDIFIO: return 0; case LINEO1: return 4; case LINEO2: return 7; case LINEO3: return 5; case LINEO4: return 6; case LINEIM: return 4; case MIC: return 5; default: return -EINVAL; } default: return -EINVAL; } } static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc); static int dao_spdif_get_spos(struct dao *dao, unsigned int *spos) { dao->hw->dao_get_spos(dao->ctrl_blk, spos); return 0; } static int dao_spdif_set_spos(struct dao *dao, unsigned int spos) { dao->hw->dao_set_spos(dao->ctrl_blk, spos); return 0; } static int dao_commit_write(struct dao *dao) { dao->hw->dao_commit_write(dao->hw, daio_device_index(dao->daio.type, dao->hw), dao->ctrl_blk); return 0; } static int dao_set_left_input(struct dao *dao, struct rsc *input) { struct imapper *entry; struct daio *daio = &dao->daio; int i; entry = kzalloc((sizeof(*entry) * daio->rscl.msr), GFP_KERNEL); if (!entry) return -ENOMEM; dao->ops->clear_left_input(dao); /* Program master and conjugate resources */ input->ops->master(input); daio->rscl.ops->master(&daio->rscl); for (i = 0; i < daio->rscl.msr; i++, entry++) { entry->slot = input->ops->output_slot(input); entry->user = entry->addr = daio->rscl.ops->index(&daio->rscl); dao->mgr->imap_add(dao->mgr, entry); dao->imappers[i] = entry; input->ops->next_conj(input); daio->rscl.ops->next_conj(&daio->rscl); } input->ops->master(input); daio->rscl.ops->master(&daio->rscl); return 0; } static int dao_set_right_input(struct dao *dao, struct rsc *input) { struct imapper *entry; struct daio *daio = &dao->daio; int i; entry = kzalloc((sizeof(*entry) * daio->rscr.msr), GFP_KERNEL); if (!entry) return -ENOMEM; dao->ops->clear_right_input(dao); /* Program master and conjugate resources */ input->ops->master(input); daio->rscr.ops->master(&daio->rscr); for (i = 0; i < daio->rscr.msr; i++, entry++) { entry->slot = input->ops->output_slot(input); entry->user = entry->addr = daio->rscr.ops->index(&daio->rscr); dao->mgr->imap_add(dao->mgr, entry); dao->imappers[daio->rscl.msr + i] = entry; input->ops->next_conj(input); daio->rscr.ops->next_conj(&daio->rscr); } input->ops->master(input); daio->rscr.ops->master(&daio->rscr); return 0; } static int dao_clear_left_input(struct dao *dao) { struct imapper *entry; struct daio *daio = &dao->daio; int i; if (!dao->imappers[0]) return 0; entry = dao->imappers[0]; dao->mgr->imap_delete(dao->mgr, entry); /* Program conjugate resources */ for (i = 1; i < daio->rscl.msr; i++) { entry = dao->imappers[i]; dao->mgr->imap_delete(dao->mgr, entry); dao->imappers[i] = NULL; } kfree(dao->imappers[0]); dao->imappers[0] = NULL; return 0; } static int dao_clear_right_input(struct dao *dao) { struct imapper *entry; struct daio *daio = &dao->daio; int i; if (!dao->imappers[daio->rscl.msr]) return 0; entry = dao->imappers[daio->rscl.msr]; dao->mgr->imap_delete(dao->mgr, entry); /* Program conjugate resources */ for (i = 1; i < daio->rscr.msr; i++) { entry = dao->imappers[daio->rscl.msr + i]; dao->mgr->imap_delete(dao->mgr, entry); dao->imappers[daio->rscl.msr + i] = NULL; } kfree(dao->imappers[daio->rscl.msr]); dao->imappers[daio->rscl.msr] = NULL; return 0; } static const struct dao_rsc_ops dao_ops = { .set_spos = dao_spdif_set_spos, .commit_write = dao_commit_write, .get_spos = dao_spdif_get_spos, .reinit = dao_rsc_reinit, .set_left_input = dao_set_left_input, .set_right_input = dao_set_right_input, .clear_left_input = dao_clear_left_input, .clear_right_input = dao_clear_right_input, }; static int dai_set_srt_srcl(struct dai *dai, struct rsc *src) { src->ops->master(src); dai->hw->dai_srt_set_srcm(dai->ctrl_blk, src->ops->index(src)); return 0; } static int dai_set_srt_srcr(struct dai *dai, struct rsc *src) { src->ops->master(src); dai->hw->dai_srt_set_srco(dai->ctrl_blk, src->ops->index(src)); return 0; } static int dai_set_srt_msr(struct dai *dai, unsigned int msr) { unsigned int rsr; for (rsr = 0; msr > 1; msr >>= 1) rsr++; dai->hw->dai_srt_set_rsr(dai->ctrl_blk, rsr); return 0; } static int dai_set_enb_src(struct dai *dai, unsigned int enb) { dai->hw->dai_srt_set_ec(dai->ctrl_blk, enb); return 0; } static int dai_set_enb_srt(struct dai *dai, unsigned int enb) { dai->hw->dai_srt_set_et(dai->ctrl_blk, enb); return 0; } static int dai_commit_write(struct dai *dai) { dai->hw->dai_commit_write(dai->hw, daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk); return 0; } static const struct dai_rsc_ops dai_ops = { .set_srt_srcl = dai_set_srt_srcl, .set_srt_srcr = dai_set_srt_srcr, .set_srt_msr = dai_set_srt_msr, .set_enb_src = dai_set_enb_src, .set_enb_srt = dai_set_enb_srt, .commit_write = dai_commit_write, }; static int daio_rsc_init(struct daio *daio, const struct daio_desc *desc, struct hw *hw) { int err; unsigned int idx_l, idx_r; switch (hw->chip_type) { case ATC20K1: idx_l = idx_20k1[desc->type].left; idx_r = idx_20k1[desc->type].right; break; case ATC20K2: idx_l = idx_20k2[desc->type].left; idx_r = idx_20k2[desc->type].right; break; default: return -EINVAL; } err = rsc_init(&daio->rscl, idx_l, DAIO, desc->msr, hw); if (err) return err; err = rsc_init(&daio->rscr, idx_r, DAIO, desc->msr, hw); if (err) goto error1; /* Set daio->rscl/r->ops to daio specific ones */ if (desc->type <= DAIO_OUT_MAX) { daio->rscl.ops = daio->rscr.ops = &daio_out_rsc_ops; } else { switch (hw->chip_type) { case ATC20K1: daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k1; break; case ATC20K2: daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k2; break; default: break; } } daio->type = desc->type; return 0; error1: rsc_uninit(&daio->rscl); return err; } static int daio_rsc_uninit(struct daio *daio) { rsc_uninit(&daio->rscl); rsc_uninit(&daio->rscr); return 0; } static int dao_rsc_init(struct dao *dao, const struct daio_desc *desc, struct daio_mgr *mgr) { struct hw *hw = mgr->mgr.hw; unsigned int conf; int err; err = daio_rsc_init(&dao->daio, desc, mgr->mgr.hw); if (err) return err; dao->imappers = kzalloc(array3_size(sizeof(void *), desc->msr, 2), GFP_KERNEL); if (!dao->imappers) { err = -ENOMEM; goto error1; } dao->ops = &dao_ops; dao->mgr = mgr; dao->hw = hw; err = hw->dao_get_ctrl_blk(&dao->ctrl_blk); if (err) goto error2; hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk, daio_device_index(dao->daio.type, hw)); hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk); conf = (desc->msr & 0x7) | (desc->passthru << 3); hw->daio_mgr_dao_init(mgr->mgr.ctrl_blk, daio_device_index(dao->daio.type, hw), conf); hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk, daio_device_index(dao->daio.type, hw)); hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk); return 0; error2: kfree(dao->imappers); dao->imappers = NULL; error1: daio_rsc_uninit(&dao->daio); return err; } static int dao_rsc_uninit(struct dao *dao) { if (dao->imappers) { if (dao->imappers[0]) dao_clear_left_input(dao); if (dao->imappers[dao->daio.rscl.msr]) dao_clear_right_input(dao); kfree(dao->imappers); dao->imappers = NULL; } dao->hw->dao_put_ctrl_blk(dao->ctrl_blk); dao->hw = dao->ctrl_blk = NULL; daio_rsc_uninit(&dao->daio); return 0; } static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc) { struct daio_mgr *mgr = dao->mgr; struct daio_desc dsc = {0}; dsc.type = dao->daio.type; dsc.msr = desc->msr; dsc.passthru = desc->passthru; dao_rsc_uninit(dao); return dao_rsc_init(dao, &dsc, mgr); } static int dai_rsc_init(struct dai *dai, const struct daio_desc *desc, struct daio_mgr *mgr) { int err; struct hw *hw = mgr->mgr.hw; unsigned int rsr, msr; err = daio_rsc_init(&dai->daio, desc, mgr->mgr.hw); if (err) return err; dai->ops = &dai_ops; dai->hw = mgr->mgr.hw; err = hw->dai_get_ctrl_blk(&dai->ctrl_blk); if (err) goto error1; for (rsr = 0, msr = desc->msr; msr > 1; msr >>= 1) rsr++; hw->dai_srt_set_rsr(dai->ctrl_blk, rsr); hw->dai_srt_set_drat(dai->ctrl_blk, 0); /* default to disabling control of a SRC */ hw->dai_srt_set_ec(dai->ctrl_blk, 0); hw->dai_srt_set_et(dai->ctrl_blk, 0); /* default to disabling SRT */ hw->dai_commit_write(hw, daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk); return 0; error1: daio_rsc_uninit(&dai->daio); return err; } static int dai_rsc_uninit(struct dai *dai) { dai->hw->dai_put_ctrl_blk(dai->ctrl_blk); dai->hw = dai->ctrl_blk = NULL; daio_rsc_uninit(&dai->daio); return 0; } static int daio_mgr_get_rsc(struct rsc_mgr *mgr, enum DAIOTYP type) { if (((struct daio_usage *)mgr->rscs)->data & (0x1 << type)) return -ENOENT; ((struct daio_usage *)mgr->rscs)->data |= (0x1 << type); return 0; } static int daio_mgr_put_rsc(struct rsc_mgr *mgr, enum DAIOTYP type) { ((struct daio_usage *)mgr->rscs)->data &= ~(0x1 << type); return 0; } static int get_daio_rsc(struct daio_mgr *mgr, const struct daio_desc *desc, struct daio **rdaio) { int err; unsigned long flags; *rdaio = NULL; /* Check whether there are sufficient daio resources to meet request. */ spin_lock_irqsave(&mgr->mgr_lock, flags); err = daio_mgr_get_rsc(&mgr->mgr, desc->type); spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { dev_err(mgr->card->dev, "Can't meet DAIO resource request!\n"); return err; } err = -ENOMEM; /* Allocate mem for daio resource */ if (desc->type <= DAIO_OUT_MAX) { struct dao *dao = kzalloc(sizeof(*dao), GFP_KERNEL); if (!dao) goto error; err = dao_rsc_init(dao, desc, mgr); if (err) { kfree(dao); goto error; } *rdaio = &dao->daio; } else { struct dai *dai = kzalloc(sizeof(*dai), GFP_KERNEL); if (!dai) goto error; err = dai_rsc_init(dai, desc, mgr); if (err) { kfree(dai); goto error; } *rdaio = &dai->daio; } mgr->daio_enable(mgr, *rdaio); mgr->commit_write(mgr); return 0; error: spin_lock_irqsave(&mgr->mgr_lock, flags); daio_mgr_put_rsc(&mgr->mgr, desc->type); spin_unlock_irqrestore(&mgr->mgr_lock, flags); return err; } static int put_daio_rsc(struct daio_mgr *mgr, struct daio *daio) { unsigned long flags; mgr->daio_disable(mgr, daio); mgr->commit_write(mgr); spin_lock_irqsave(&mgr->mgr_lock, flags); daio_mgr_put_rsc(&mgr->mgr, daio->type); spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (daio->type <= DAIO_OUT_MAX) { dao_rsc_uninit(container_of(daio, struct dao, daio)); kfree(container_of(daio, struct dao, daio)); } else { dai_rsc_uninit(container_of(daio, struct dai, daio)); kfree(container_of(daio, struct dai, daio)); } return 0; } static int daio_mgr_enb_daio(struct daio_mgr *mgr, struct daio *daio) { struct hw *hw = mgr->mgr.hw; if (DAIO_OUT_MAX >= daio->type) { hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk, daio_device_index(daio->type, hw)); } else { hw->daio_mgr_enb_dai(mgr->mgr.ctrl_blk, daio_device_index(daio->type, hw)); } return 0; } static int daio_mgr_dsb_daio(struct daio_mgr *mgr, struct daio *daio) { struct hw *hw = mgr->mgr.hw; if (DAIO_OUT_MAX >= daio->type) { hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk, daio_device_index(daio->type, hw)); } else { hw->daio_mgr_dsb_dai(mgr->mgr.ctrl_blk, daio_device_index(daio->type, hw)); } return 0; } static int daio_map_op(void *data, struct imapper *entry) { struct rsc_mgr *mgr = &((struct daio_mgr *)data)->mgr; struct hw *hw = mgr->hw; hw->daio_mgr_set_imaparc(mgr->ctrl_blk, entry->slot); hw->daio_mgr_set_imapnxt(mgr->ctrl_blk, entry->next); hw->daio_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr); hw->daio_mgr_commit_write(mgr->hw, mgr->ctrl_blk); return 0; } static int daio_imap_add(struct daio_mgr *mgr, struct imapper *entry) { unsigned long flags; int err; spin_lock_irqsave(&mgr->imap_lock, flags); if (!entry->addr && mgr->init_imap_added) { input_mapper_delete(&mgr->imappers, mgr->init_imap, daio_map_op, mgr); mgr->init_imap_added = 0; } err = input_mapper_add(&mgr->imappers, entry, daio_map_op, mgr); spin_unlock_irqrestore(&mgr->imap_lock, flags); return err; } static int daio_imap_delete(struct daio_mgr *mgr, struct imapper *entry) { unsigned long flags; int err; spin_lock_irqsave(&mgr->imap_lock, flags); err = input_mapper_delete(&mgr->imappers, entry, daio_map_op, mgr); if (list_empty(&mgr->imappers)) { input_mapper_add(&mgr->imappers, mgr->init_imap, daio_map_op, mgr); mgr->init_imap_added = 1; } spin_unlock_irqrestore(&mgr->imap_lock, flags); return err; } static int daio_mgr_commit_write(struct daio_mgr *mgr) { struct hw *hw = mgr->mgr.hw; hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk); return 0; } int daio_mgr_create(struct hw *hw, struct daio_mgr **rdaio_mgr) { int err, i; struct daio_mgr *daio_mgr; struct imapper *entry; *rdaio_mgr = NULL; daio_mgr = kzalloc(sizeof(*daio_mgr), GFP_KERNEL); if (!daio_mgr) return -ENOMEM; err = rsc_mgr_init(&daio_mgr->mgr, DAIO, NUM_DAIOTYP, hw); if (err) goto error1; spin_lock_init(&daio_mgr->mgr_lock); spin_lock_init(&daio_mgr->imap_lock); INIT_LIST_HEAD(&daio_mgr->imappers); entry = kzalloc(sizeof(*entry), GFP_KERNEL); if (!entry) { err = -ENOMEM; goto error2; } entry->slot = entry->addr = entry->next = entry->user = 0; list_add(&entry->list, &daio_mgr->imappers); daio_mgr->init_imap = entry; daio_mgr->init_imap_added = 1; daio_mgr->get_daio = get_daio_rsc; daio_mgr->put_daio = put_daio_rsc; daio_mgr->daio_enable = daio_mgr_enb_daio; daio_mgr->daio_disable = daio_mgr_dsb_daio; daio_mgr->imap_add = daio_imap_add; daio_mgr->imap_delete = daio_imap_delete; daio_mgr->commit_write = daio_mgr_commit_write; daio_mgr->card = hw->card; for (i = 0; i < 8; i++) { hw->daio_mgr_dsb_dao(daio_mgr->mgr.ctrl_blk, i); hw->daio_mgr_dsb_dai(daio_mgr->mgr.ctrl_blk, i); } hw->daio_mgr_commit_write(hw, daio_mgr->mgr.ctrl_blk); *rdaio_mgr = daio_mgr; return 0; error2: rsc_mgr_uninit(&daio_mgr->mgr); error1: kfree(daio_mgr); return err; } int daio_mgr_destroy(struct daio_mgr *daio_mgr) { unsigned long flags; /* free daio input mapper list */ spin_lock_irqsave(&daio_mgr->imap_lock, flags); free_input_mapper_list(&daio_mgr->imappers); spin_unlock_irqrestore(&daio_mgr->imap_lock, flags); rsc_mgr_uninit(&daio_mgr->mgr); kfree(daio_mgr); return 0; }
linux-master
sound/pci/ctxfi/ctdaio.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctatc.c * * @Brief * This file contains the implementation of the device resource management * object. * * @Author Liu Chun * @Date Mar 28 2008 */ #include "ctatc.h" #include "ctpcm.h" #include "ctmixer.h" #include "ctsrc.h" #include "ctamixer.h" #include "ctdaio.h" #include "cttimer.h" #include <linux/delay.h> #include <linux/slab.h> #include <sound/pcm.h> #include <sound/control.h> #include <sound/asoundef.h> #define MONO_SUM_SCALE 0x19a8 /* 2^(-0.5) in 14-bit floating format */ #define MAX_MULTI_CHN 8 #define IEC958_DEFAULT_CON ((IEC958_AES0_NONAUDIO \ | IEC958_AES0_CON_NOT_COPYRIGHT) \ | ((IEC958_AES1_CON_MIXER \ | IEC958_AES1_CON_ORIGINAL) << 8) \ | (0x10 << 16) \ | ((IEC958_AES3_CON_FS_48000) << 24)) static const struct snd_pci_quirk subsys_20k1_list[] = { SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0021, "SB046x", CTSB046X), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0022, "SB055x", CTSB055X), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x002f, "SB055x", CTSB055X), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0029, "SB073x", CTSB073X), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0031, "SB073x", CTSB073X), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_CREATIVE, 0xf000, 0x6000, "UAA", CTUAA), { } /* terminator */ }; static const struct snd_pci_quirk subsys_20k2_list[] = { SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB0760, "SB0760", CTSB0760), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB1270, "SB1270", CTSB1270), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08801, "SB0880", CTSB0880), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08802, "SB0880", CTSB0880), SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08803, "SB0880", CTSB0880), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_CREATIVE, 0xf000, PCI_SUBDEVICE_ID_CREATIVE_HENDRIX, "HENDRIX", CTHENDRIX), { } /* terminator */ }; static const char *ct_subsys_name[NUM_CTCARDS] = { /* 20k1 models */ [CTSB046X] = "SB046x", [CTSB055X] = "SB055x", [CTSB073X] = "SB073x", [CTUAA] = "UAA", [CT20K1_UNKNOWN] = "Unknown", /* 20k2 models */ [CTSB0760] = "SB076x", [CTHENDRIX] = "Hendrix", [CTSB0880] = "SB0880", [CTSB1270] = "SB1270", [CT20K2_UNKNOWN] = "Unknown", }; static struct { int (*create)(struct ct_atc *atc, enum CTALSADEVS device, const char *device_name); int (*destroy)(void *alsa_dev); const char *public_name; } alsa_dev_funcs[NUM_CTALSADEVS] = { [FRONT] = { .create = ct_alsa_pcm_create, .destroy = NULL, .public_name = "Front/WaveIn"}, [SURROUND] = { .create = ct_alsa_pcm_create, .destroy = NULL, .public_name = "Surround"}, [CLFE] = { .create = ct_alsa_pcm_create, .destroy = NULL, .public_name = "Center/LFE"}, [SIDE] = { .create = ct_alsa_pcm_create, .destroy = NULL, .public_name = "Side"}, [IEC958] = { .create = ct_alsa_pcm_create, .destroy = NULL, .public_name = "IEC958 Non-audio"}, [MIXER] = { .create = ct_alsa_mix_create, .destroy = NULL, .public_name = "Mixer"} }; typedef int (*create_t)(struct hw *, void **); typedef int (*destroy_t)(void *); static struct { int (*create)(struct hw *hw, void **rmgr); int (*destroy)(void *mgr); } rsc_mgr_funcs[NUM_RSCTYP] = { [SRC] = { .create = (create_t)src_mgr_create, .destroy = (destroy_t)src_mgr_destroy }, [SRCIMP] = { .create = (create_t)srcimp_mgr_create, .destroy = (destroy_t)srcimp_mgr_destroy }, [AMIXER] = { .create = (create_t)amixer_mgr_create, .destroy = (destroy_t)amixer_mgr_destroy }, [SUM] = { .create = (create_t)sum_mgr_create, .destroy = (destroy_t)sum_mgr_destroy }, [DAIO] = { .create = (create_t)daio_mgr_create, .destroy = (destroy_t)daio_mgr_destroy } }; static int atc_pcm_release_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm); /* * * Only mono and interleaved modes are supported now. * Always allocates a contiguous channel block. * */ static int ct_map_audio_buffer(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct snd_pcm_runtime *runtime; struct ct_vm *vm; if (!apcm->substream) return 0; runtime = apcm->substream->runtime; vm = atc->vm; apcm->vm_block = vm->map(vm, apcm->substream, runtime->dma_bytes); if (!apcm->vm_block) return -ENOENT; return 0; } static void ct_unmap_audio_buffer(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct ct_vm *vm; if (!apcm->vm_block) return; vm = atc->vm; vm->unmap(vm, apcm->vm_block); apcm->vm_block = NULL; } static unsigned long atc_get_ptp_phys(struct ct_atc *atc, int index) { return atc->vm->get_ptp_phys(atc->vm, index); } static unsigned int convert_format(snd_pcm_format_t snd_format, struct snd_card *card) { switch (snd_format) { case SNDRV_PCM_FORMAT_U8: return SRC_SF_U8; case SNDRV_PCM_FORMAT_S16_LE: return SRC_SF_S16; case SNDRV_PCM_FORMAT_S24_3LE: return SRC_SF_S24; case SNDRV_PCM_FORMAT_S32_LE: return SRC_SF_S32; case SNDRV_PCM_FORMAT_FLOAT_LE: return SRC_SF_F32; default: dev_err(card->dev, "not recognized snd format is %d\n", snd_format); return SRC_SF_S16; } } static unsigned int atc_get_pitch(unsigned int input_rate, unsigned int output_rate) { unsigned int pitch; int b; /* get pitch and convert to fixed-point 8.24 format. */ pitch = (input_rate / output_rate) << 24; input_rate %= output_rate; input_rate /= 100; output_rate /= 100; for (b = 31; ((b >= 0) && !(input_rate >> b)); ) b--; if (b >= 0) { input_rate <<= (31 - b); input_rate /= output_rate; b = 24 - (31 - b); if (b >= 0) input_rate <<= b; else input_rate >>= -b; pitch |= input_rate; } return pitch; } static int select_rom(unsigned int pitch) { if (pitch > 0x00428f5c && pitch < 0x01b851ec) { /* 0.26 <= pitch <= 1.72 */ return 1; } else if (pitch == 0x01d66666 || pitch == 0x01d66667) { /* pitch == 1.8375 */ return 2; } else if (pitch == 0x02000000) { /* pitch == 2 */ return 3; } else if (pitch <= 0x08000000) { /* 0 <= pitch <= 8 */ return 0; } else { return -ENOENT; } } static int atc_pcm_playback_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src_mgr *src_mgr = atc->rsc_mgrs[SRC]; struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER]; struct src_desc desc = {0}; struct amixer_desc mix_dsc = {0}; struct src *src; struct amixer *amixer; int err; int n_amixer = apcm->substream->runtime->channels, i = 0; int device = apcm->substream->pcm->device; unsigned int pitch; /* first release old resources */ atc_pcm_release_resources(atc, apcm); /* Get SRC resource */ desc.multi = apcm->substream->runtime->channels; desc.msr = atc->msr; desc.mode = MEMRD; err = src_mgr->get_src(src_mgr, &desc, (struct src **)&apcm->src); if (err) goto error1; pitch = atc_get_pitch(apcm->substream->runtime->rate, (atc->rsr * atc->msr)); src = apcm->src; src->ops->set_pitch(src, pitch); src->ops->set_rom(src, select_rom(pitch)); src->ops->set_sf(src, convert_format(apcm->substream->runtime->format, atc->card)); src->ops->set_pm(src, (src->ops->next_interleave(src) != NULL)); /* Get AMIXER resource */ n_amixer = (n_amixer < 2) ? 2 : n_amixer; apcm->amixers = kcalloc(n_amixer, sizeof(void *), GFP_KERNEL); if (!apcm->amixers) { err = -ENOMEM; goto error1; } mix_dsc.msr = atc->msr; for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) { err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc, (struct amixer **)&apcm->amixers[i]); if (err) goto error1; apcm->n_amixer++; } /* Set up device virtual mem map */ err = ct_map_audio_buffer(atc, apcm); if (err < 0) goto error1; /* Connect resources */ src = apcm->src; for (i = 0; i < n_amixer; i++) { amixer = apcm->amixers[i]; mutex_lock(&atc->atc_mutex); amixer->ops->setup(amixer, &src->rsc, INIT_VOL, atc->pcm[i+device*2]); mutex_unlock(&atc->atc_mutex); src = src->ops->next_interleave(src); if (!src) src = apcm->src; } ct_timer_prepare(apcm->timer); return 0; error1: atc_pcm_release_resources(atc, apcm); return err; } static int atc_pcm_release_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src_mgr *src_mgr = atc->rsc_mgrs[SRC]; struct srcimp_mgr *srcimp_mgr = atc->rsc_mgrs[SRCIMP]; struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER]; struct sum_mgr *sum_mgr = atc->rsc_mgrs[SUM]; struct srcimp *srcimp; int i; if (apcm->srcimps) { for (i = 0; i < apcm->n_srcimp; i++) { srcimp = apcm->srcimps[i]; srcimp->ops->unmap(srcimp); srcimp_mgr->put_srcimp(srcimp_mgr, srcimp); apcm->srcimps[i] = NULL; } kfree(apcm->srcimps); apcm->srcimps = NULL; } if (apcm->srccs) { for (i = 0; i < apcm->n_srcc; i++) { src_mgr->put_src(src_mgr, apcm->srccs[i]); apcm->srccs[i] = NULL; } kfree(apcm->srccs); apcm->srccs = NULL; } if (apcm->amixers) { for (i = 0; i < apcm->n_amixer; i++) { amixer_mgr->put_amixer(amixer_mgr, apcm->amixers[i]); apcm->amixers[i] = NULL; } kfree(apcm->amixers); apcm->amixers = NULL; } if (apcm->mono) { sum_mgr->put_sum(sum_mgr, apcm->mono); apcm->mono = NULL; } if (apcm->src) { src_mgr->put_src(src_mgr, apcm->src); apcm->src = NULL; } if (apcm->vm_block) { /* Undo device virtual mem map */ ct_unmap_audio_buffer(atc, apcm); apcm->vm_block = NULL; } return 0; } static int atc_pcm_playback_start(struct ct_atc *atc, struct ct_atc_pcm *apcm) { unsigned int max_cisz; struct src *src = apcm->src; if (apcm->started) return 0; apcm->started = 1; max_cisz = src->multi * src->rsc.msr; max_cisz = 0x80 * (max_cisz < 8 ? max_cisz : 8); src->ops->set_sa(src, apcm->vm_block->addr); src->ops->set_la(src, apcm->vm_block->addr + apcm->vm_block->size); src->ops->set_ca(src, apcm->vm_block->addr + max_cisz); src->ops->set_cisz(src, max_cisz); src->ops->set_bm(src, 1); src->ops->set_state(src, SRC_STATE_INIT); src->ops->commit_write(src); ct_timer_start(apcm->timer); return 0; } static int atc_pcm_stop(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src; int i; ct_timer_stop(apcm->timer); src = apcm->src; src->ops->set_bm(src, 0); src->ops->set_state(src, SRC_STATE_OFF); src->ops->commit_write(src); if (apcm->srccs) { for (i = 0; i < apcm->n_srcc; i++) { src = apcm->srccs[i]; src->ops->set_bm(src, 0); src->ops->set_state(src, SRC_STATE_OFF); src->ops->commit_write(src); } } apcm->started = 0; return 0; } static int atc_pcm_playback_position(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src = apcm->src; u32 size, max_cisz; int position; if (!src) return 0; position = src->ops->get_ca(src); if (position < apcm->vm_block->addr) { dev_dbg(atc->card->dev, "bad ca - ca=0x%08x, vba=0x%08x, vbs=0x%08x\n", position, apcm->vm_block->addr, apcm->vm_block->size); position = apcm->vm_block->addr; } size = apcm->vm_block->size; max_cisz = src->multi * src->rsc.msr; max_cisz = 128 * (max_cisz < 8 ? max_cisz : 8); return (position + size - max_cisz - apcm->vm_block->addr) % size; } struct src_node_conf_t { unsigned int pitch; unsigned int msr:8; unsigned int mix_msr:8; unsigned int imp_msr:8; unsigned int vo:1; }; static void setup_src_node_conf(struct ct_atc *atc, struct ct_atc_pcm *apcm, struct src_node_conf_t *conf, int *n_srcc) { unsigned int pitch; /* get pitch and convert to fixed-point 8.24 format. */ pitch = atc_get_pitch((atc->rsr * atc->msr), apcm->substream->runtime->rate); *n_srcc = 0; if (1 == atc->msr) { /* FIXME: do we really need SRC here if pitch==1 */ *n_srcc = apcm->substream->runtime->channels; conf[0].pitch = pitch; conf[0].mix_msr = conf[0].imp_msr = conf[0].msr = 1; conf[0].vo = 1; } else if (2 <= atc->msr) { if (0x8000000 < pitch) { /* Need two-stage SRCs, SRCIMPs and * AMIXERs for converting format */ conf[0].pitch = (atc->msr << 24); conf[0].msr = conf[0].mix_msr = 1; conf[0].imp_msr = atc->msr; conf[0].vo = 0; conf[1].pitch = atc_get_pitch(atc->rsr, apcm->substream->runtime->rate); conf[1].msr = conf[1].mix_msr = conf[1].imp_msr = 1; conf[1].vo = 1; *n_srcc = apcm->substream->runtime->channels * 2; } else if (0x1000000 < pitch) { /* Need one-stage SRCs, SRCIMPs and * AMIXERs for converting format */ conf[0].pitch = pitch; conf[0].msr = conf[0].mix_msr = conf[0].imp_msr = atc->msr; conf[0].vo = 1; *n_srcc = apcm->substream->runtime->channels; } } } static int atc_pcm_capture_get_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src_mgr *src_mgr = atc->rsc_mgrs[SRC]; struct srcimp_mgr *srcimp_mgr = atc->rsc_mgrs[SRCIMP]; struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER]; struct sum_mgr *sum_mgr = atc->rsc_mgrs[SUM]; struct src_desc src_dsc = {0}; struct src *src; struct srcimp_desc srcimp_dsc = {0}; struct srcimp *srcimp; struct amixer_desc mix_dsc = {0}; struct sum_desc sum_dsc = {0}; unsigned int pitch; int multi, err, i; int n_srcimp, n_amixer, n_srcc, n_sum; struct src_node_conf_t src_node_conf[2] = {{0} }; /* first release old resources */ atc_pcm_release_resources(atc, apcm); /* The numbers of converting SRCs and SRCIMPs should be determined * by pitch value. */ multi = apcm->substream->runtime->channels; /* get pitch and convert to fixed-point 8.24 format. */ pitch = atc_get_pitch((atc->rsr * atc->msr), apcm->substream->runtime->rate); setup_src_node_conf(atc, apcm, src_node_conf, &n_srcc); n_sum = (1 == multi) ? 1 : 0; n_amixer = n_sum * 2 + n_srcc; n_srcimp = n_srcc; if ((multi > 1) && (0x8000000 >= pitch)) { /* Need extra AMIXERs and SRCIMPs for special treatment * of interleaved recording of conjugate channels */ n_amixer += multi * atc->msr; n_srcimp += multi * atc->msr; } else { n_srcimp += multi; } if (n_srcc) { apcm->srccs = kcalloc(n_srcc, sizeof(void *), GFP_KERNEL); if (!apcm->srccs) return -ENOMEM; } if (n_amixer) { apcm->amixers = kcalloc(n_amixer, sizeof(void *), GFP_KERNEL); if (!apcm->amixers) { err = -ENOMEM; goto error1; } } apcm->srcimps = kcalloc(n_srcimp, sizeof(void *), GFP_KERNEL); if (!apcm->srcimps) { err = -ENOMEM; goto error1; } /* Allocate SRCs for sample rate conversion if needed */ src_dsc.multi = 1; src_dsc.mode = ARCRW; for (i = 0, apcm->n_srcc = 0; i < n_srcc; i++) { src_dsc.msr = src_node_conf[i/multi].msr; err = src_mgr->get_src(src_mgr, &src_dsc, (struct src **)&apcm->srccs[i]); if (err) goto error1; src = apcm->srccs[i]; pitch = src_node_conf[i/multi].pitch; src->ops->set_pitch(src, pitch); src->ops->set_rom(src, select_rom(pitch)); src->ops->set_vo(src, src_node_conf[i/multi].vo); apcm->n_srcc++; } /* Allocate AMIXERs for routing SRCs of conversion if needed */ for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) { if (i < (n_sum*2)) mix_dsc.msr = atc->msr; else if (i < (n_sum*2+n_srcc)) mix_dsc.msr = src_node_conf[(i-n_sum*2)/multi].mix_msr; else mix_dsc.msr = 1; err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc, (struct amixer **)&apcm->amixers[i]); if (err) goto error1; apcm->n_amixer++; } /* Allocate a SUM resource to mix all input channels together */ sum_dsc.msr = atc->msr; err = sum_mgr->get_sum(sum_mgr, &sum_dsc, (struct sum **)&apcm->mono); if (err) goto error1; pitch = atc_get_pitch((atc->rsr * atc->msr), apcm->substream->runtime->rate); /* Allocate SRCIMP resources */ for (i = 0, apcm->n_srcimp = 0; i < n_srcimp; i++) { if (i < (n_srcc)) srcimp_dsc.msr = src_node_conf[i/multi].imp_msr; else if (1 == multi) srcimp_dsc.msr = (pitch <= 0x8000000) ? atc->msr : 1; else srcimp_dsc.msr = 1; err = srcimp_mgr->get_srcimp(srcimp_mgr, &srcimp_dsc, &srcimp); if (err) goto error1; apcm->srcimps[i] = srcimp; apcm->n_srcimp++; } /* Allocate a SRC for writing data to host memory */ src_dsc.multi = apcm->substream->runtime->channels; src_dsc.msr = 1; src_dsc.mode = MEMWR; err = src_mgr->get_src(src_mgr, &src_dsc, (struct src **)&apcm->src); if (err) goto error1; src = apcm->src; src->ops->set_pitch(src, pitch); /* Set up device virtual mem map */ err = ct_map_audio_buffer(atc, apcm); if (err < 0) goto error1; return 0; error1: atc_pcm_release_resources(atc, apcm); return err; } static int atc_pcm_capture_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src; struct amixer *amixer; struct srcimp *srcimp; struct ct_mixer *mixer = atc->mixer; struct sum *mono; struct rsc *out_ports[8] = {NULL}; int err, i, j, n_sum, multi; unsigned int pitch; int mix_base = 0, imp_base = 0; atc_pcm_release_resources(atc, apcm); /* Get needed resources. */ err = atc_pcm_capture_get_resources(atc, apcm); if (err) return err; /* Connect resources */ mixer->get_output_ports(mixer, MIX_PCMO_FRONT, &out_ports[0], &out_ports[1]); multi = apcm->substream->runtime->channels; if (1 == multi) { mono = apcm->mono; for (i = 0; i < 2; i++) { amixer = apcm->amixers[i]; amixer->ops->setup(amixer, out_ports[i], MONO_SUM_SCALE, mono); } out_ports[0] = &mono->rsc; n_sum = 1; mix_base = n_sum * 2; } for (i = 0; i < apcm->n_srcc; i++) { src = apcm->srccs[i]; srcimp = apcm->srcimps[imp_base+i]; amixer = apcm->amixers[mix_base+i]; srcimp->ops->map(srcimp, src, out_ports[i%multi]); amixer->ops->setup(amixer, &src->rsc, INIT_VOL, NULL); out_ports[i%multi] = &amixer->rsc; } pitch = atc_get_pitch((atc->rsr * atc->msr), apcm->substream->runtime->rate); if ((multi > 1) && (pitch <= 0x8000000)) { /* Special connection for interleaved * recording with conjugate channels */ for (i = 0; i < multi; i++) { out_ports[i]->ops->master(out_ports[i]); for (j = 0; j < atc->msr; j++) { amixer = apcm->amixers[apcm->n_srcc+j*multi+i]; amixer->ops->set_input(amixer, out_ports[i]); amixer->ops->set_scale(amixer, INIT_VOL); amixer->ops->set_sum(amixer, NULL); amixer->ops->commit_raw_write(amixer); out_ports[i]->ops->next_conj(out_ports[i]); srcimp = apcm->srcimps[apcm->n_srcc+j*multi+i]; srcimp->ops->map(srcimp, apcm->src, &amixer->rsc); } } } else { for (i = 0; i < multi; i++) { srcimp = apcm->srcimps[apcm->n_srcc+i]; srcimp->ops->map(srcimp, apcm->src, out_ports[i]); } } ct_timer_prepare(apcm->timer); return 0; } static int atc_pcm_capture_start(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src; struct src_mgr *src_mgr = atc->rsc_mgrs[SRC]; int i, multi; if (apcm->started) return 0; apcm->started = 1; multi = apcm->substream->runtime->channels; /* Set up converting SRCs */ for (i = 0; i < apcm->n_srcc; i++) { src = apcm->srccs[i]; src->ops->set_pm(src, ((i%multi) != (multi-1))); src_mgr->src_disable(src_mgr, src); } /* Set up recording SRC */ src = apcm->src; src->ops->set_sf(src, convert_format(apcm->substream->runtime->format, atc->card)); src->ops->set_sa(src, apcm->vm_block->addr); src->ops->set_la(src, apcm->vm_block->addr + apcm->vm_block->size); src->ops->set_ca(src, apcm->vm_block->addr); src_mgr->src_disable(src_mgr, src); /* Disable relevant SRCs firstly */ src_mgr->commit_write(src_mgr); /* Enable SRCs respectively */ for (i = 0; i < apcm->n_srcc; i++) { src = apcm->srccs[i]; src->ops->set_state(src, SRC_STATE_RUN); src->ops->commit_write(src); src_mgr->src_enable_s(src_mgr, src); } src = apcm->src; src->ops->set_bm(src, 1); src->ops->set_state(src, SRC_STATE_RUN); src->ops->commit_write(src); src_mgr->src_enable_s(src_mgr, src); /* Enable relevant SRCs synchronously */ src_mgr->commit_write(src_mgr); ct_timer_start(apcm->timer); return 0; } static int atc_pcm_capture_position(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src = apcm->src; if (!src) return 0; return src->ops->get_ca(src) - apcm->vm_block->addr; } static int spdif_passthru_playback_get_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src_mgr *src_mgr = atc->rsc_mgrs[SRC]; struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER]; struct src_desc desc = {0}; struct amixer_desc mix_dsc = {0}; struct src *src; int err; int n_amixer = apcm->substream->runtime->channels, i; unsigned int pitch, rsr = atc->pll_rate; /* first release old resources */ atc_pcm_release_resources(atc, apcm); /* Get SRC resource */ desc.multi = apcm->substream->runtime->channels; desc.msr = 1; while (apcm->substream->runtime->rate > (rsr * desc.msr)) desc.msr <<= 1; desc.mode = MEMRD; err = src_mgr->get_src(src_mgr, &desc, (struct src **)&apcm->src); if (err) goto error1; pitch = atc_get_pitch(apcm->substream->runtime->rate, (rsr * desc.msr)); src = apcm->src; src->ops->set_pitch(src, pitch); src->ops->set_rom(src, select_rom(pitch)); src->ops->set_sf(src, convert_format(apcm->substream->runtime->format, atc->card)); src->ops->set_pm(src, (src->ops->next_interleave(src) != NULL)); src->ops->set_bp(src, 1); /* Get AMIXER resource */ n_amixer = (n_amixer < 2) ? 2 : n_amixer; apcm->amixers = kcalloc(n_amixer, sizeof(void *), GFP_KERNEL); if (!apcm->amixers) { err = -ENOMEM; goto error1; } mix_dsc.msr = desc.msr; for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) { err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc, (struct amixer **)&apcm->amixers[i]); if (err) goto error1; apcm->n_amixer++; } /* Set up device virtual mem map */ err = ct_map_audio_buffer(atc, apcm); if (err < 0) goto error1; return 0; error1: atc_pcm_release_resources(atc, apcm); return err; } static int atc_pll_init(struct ct_atc *atc, int rate) { struct hw *hw = atc->hw; int err; err = hw->pll_init(hw, rate); atc->pll_rate = err ? 0 : rate; return err; } static int spdif_passthru_playback_setup(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct dao *dao = container_of(atc->daios[SPDIFOO], struct dao, daio); unsigned int rate = apcm->substream->runtime->rate; unsigned int status; int err = 0; unsigned char iec958_con_fs; switch (rate) { case 48000: iec958_con_fs = IEC958_AES3_CON_FS_48000; break; case 44100: iec958_con_fs = IEC958_AES3_CON_FS_44100; break; case 32000: iec958_con_fs = IEC958_AES3_CON_FS_32000; break; default: return -ENOENT; } mutex_lock(&atc->atc_mutex); dao->ops->get_spos(dao, &status); if (((status >> 24) & IEC958_AES3_CON_FS) != iec958_con_fs) { status &= ~(IEC958_AES3_CON_FS << 24); status |= (iec958_con_fs << 24); dao->ops->set_spos(dao, status); dao->ops->commit_write(dao); } if ((rate != atc->pll_rate) && (32000 != rate)) err = atc_pll_init(atc, rate); mutex_unlock(&atc->atc_mutex); return err; } static int spdif_passthru_playback_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm) { struct src *src; struct amixer *amixer; struct dao *dao; int err; int i; atc_pcm_release_resources(atc, apcm); /* Configure SPDIFOO and PLL to passthrough mode; * determine pll_rate. */ err = spdif_passthru_playback_setup(atc, apcm); if (err) return err; /* Get needed resources. */ err = spdif_passthru_playback_get_resources(atc, apcm); if (err) return err; /* Connect resources */ src = apcm->src; for (i = 0; i < apcm->n_amixer; i++) { amixer = apcm->amixers[i]; amixer->ops->setup(amixer, &src->rsc, INIT_VOL, NULL); src = src->ops->next_interleave(src); if (!src) src = apcm->src; } /* Connect to SPDIFOO */ mutex_lock(&atc->atc_mutex); dao = container_of(atc->daios[SPDIFOO], struct dao, daio); amixer = apcm->amixers[0]; dao->ops->set_left_input(dao, &amixer->rsc); amixer = apcm->amixers[1]; dao->ops->set_right_input(dao, &amixer->rsc); mutex_unlock(&atc->atc_mutex); ct_timer_prepare(apcm->timer); return 0; } static int atc_select_line_in(struct ct_atc *atc) { struct hw *hw = atc->hw; struct ct_mixer *mixer = atc->mixer; struct src *src; if (hw->is_adc_source_selected(hw, ADC_LINEIN)) return 0; mixer->set_input_left(mixer, MIX_MIC_IN, NULL); mixer->set_input_right(mixer, MIX_MIC_IN, NULL); hw->select_adc_source(hw, ADC_LINEIN); src = atc->srcs[2]; mixer->set_input_left(mixer, MIX_LINE_IN, &src->rsc); src = atc->srcs[3]; mixer->set_input_right(mixer, MIX_LINE_IN, &src->rsc); return 0; } static int atc_select_mic_in(struct ct_atc *atc) { struct hw *hw = atc->hw; struct ct_mixer *mixer = atc->mixer; struct src *src; if (hw->is_adc_source_selected(hw, ADC_MICIN)) return 0; mixer->set_input_left(mixer, MIX_LINE_IN, NULL); mixer->set_input_right(mixer, MIX_LINE_IN, NULL); hw->select_adc_source(hw, ADC_MICIN); src = atc->srcs[2]; mixer->set_input_left(mixer, MIX_MIC_IN, &src->rsc); src = atc->srcs[3]; mixer->set_input_right(mixer, MIX_MIC_IN, &src->rsc); return 0; } static struct capabilities atc_capabilities(struct ct_atc *atc) { struct hw *hw = atc->hw; return hw->capabilities(hw); } static int atc_output_switch_get(struct ct_atc *atc) { struct hw *hw = atc->hw; return hw->output_switch_get(hw); } static int atc_output_switch_put(struct ct_atc *atc, int position) { struct hw *hw = atc->hw; return hw->output_switch_put(hw, position); } static int atc_mic_source_switch_get(struct ct_atc *atc) { struct hw *hw = atc->hw; return hw->mic_source_switch_get(hw); } static int atc_mic_source_switch_put(struct ct_atc *atc, int position) { struct hw *hw = atc->hw; return hw->mic_source_switch_put(hw, position); } static int atc_select_digit_io(struct ct_atc *atc) { struct hw *hw = atc->hw; if (hw->is_adc_source_selected(hw, ADC_NONE)) return 0; hw->select_adc_source(hw, ADC_NONE); return 0; } static int atc_daio_unmute(struct ct_atc *atc, unsigned char state, int type) { struct daio_mgr *daio_mgr = atc->rsc_mgrs[DAIO]; if (state) daio_mgr->daio_enable(daio_mgr, atc->daios[type]); else daio_mgr->daio_disable(daio_mgr, atc->daios[type]); daio_mgr->commit_write(daio_mgr); return 0; } static int atc_dao_get_status(struct ct_atc *atc, unsigned int *status, int type) { struct dao *dao = container_of(atc->daios[type], struct dao, daio); return dao->ops->get_spos(dao, status); } static int atc_dao_set_status(struct ct_atc *atc, unsigned int status, int type) { struct dao *dao = container_of(atc->daios[type], struct dao, daio); dao->ops->set_spos(dao, status); dao->ops->commit_write(dao); return 0; } static int atc_line_front_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, LINEO1); } static int atc_line_surround_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, LINEO2); } static int atc_line_clfe_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, LINEO3); } static int atc_line_rear_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, LINEO4); } static int atc_line_in_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, LINEIM); } static int atc_mic_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, MIC); } static int atc_spdif_out_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, SPDIFOO); } static int atc_spdif_in_unmute(struct ct_atc *atc, unsigned char state) { return atc_daio_unmute(atc, state, SPDIFIO); } static int atc_spdif_out_get_status(struct ct_atc *atc, unsigned int *status) { return atc_dao_get_status(atc, status, SPDIFOO); } static int atc_spdif_out_set_status(struct ct_atc *atc, unsigned int status) { return atc_dao_set_status(atc, status, SPDIFOO); } static int atc_spdif_out_passthru(struct ct_atc *atc, unsigned char state) { struct dao_desc da_dsc = {0}; struct dao *dao; int err; struct ct_mixer *mixer = atc->mixer; struct rsc *rscs[2] = {NULL}; unsigned int spos = 0; mutex_lock(&atc->atc_mutex); dao = container_of(atc->daios[SPDIFOO], struct dao, daio); da_dsc.msr = state ? 1 : atc->msr; da_dsc.passthru = state ? 1 : 0; err = dao->ops->reinit(dao, &da_dsc); if (state) { spos = IEC958_DEFAULT_CON; } else { mixer->get_output_ports(mixer, MIX_SPDIF_OUT, &rscs[0], &rscs[1]); dao->ops->set_left_input(dao, rscs[0]); dao->ops->set_right_input(dao, rscs[1]); /* Restore PLL to atc->rsr if needed. */ if (atc->pll_rate != atc->rsr) err = atc_pll_init(atc, atc->rsr); } dao->ops->set_spos(dao, spos); dao->ops->commit_write(dao); mutex_unlock(&atc->atc_mutex); return err; } static int atc_release_resources(struct ct_atc *atc) { int i; struct daio_mgr *daio_mgr = NULL; struct dao *dao = NULL; struct daio *daio = NULL; struct sum_mgr *sum_mgr = NULL; struct src_mgr *src_mgr = NULL; struct srcimp_mgr *srcimp_mgr = NULL; struct srcimp *srcimp = NULL; struct ct_mixer *mixer = NULL; /* disconnect internal mixer objects */ if (atc->mixer) { mixer = atc->mixer; mixer->set_input_left(mixer, MIX_LINE_IN, NULL); mixer->set_input_right(mixer, MIX_LINE_IN, NULL); mixer->set_input_left(mixer, MIX_MIC_IN, NULL); mixer->set_input_right(mixer, MIX_MIC_IN, NULL); mixer->set_input_left(mixer, MIX_SPDIF_IN, NULL); mixer->set_input_right(mixer, MIX_SPDIF_IN, NULL); } if (atc->daios) { daio_mgr = (struct daio_mgr *)atc->rsc_mgrs[DAIO]; for (i = 0; i < atc->n_daio; i++) { daio = atc->daios[i]; if (daio->type < LINEIM) { dao = container_of(daio, struct dao, daio); dao->ops->clear_left_input(dao); dao->ops->clear_right_input(dao); } daio_mgr->put_daio(daio_mgr, daio); } kfree(atc->daios); atc->daios = NULL; } if (atc->pcm) { sum_mgr = atc->rsc_mgrs[SUM]; for (i = 0; i < atc->n_pcm; i++) sum_mgr->put_sum(sum_mgr, atc->pcm[i]); kfree(atc->pcm); atc->pcm = NULL; } if (atc->srcs) { src_mgr = atc->rsc_mgrs[SRC]; for (i = 0; i < atc->n_src; i++) src_mgr->put_src(src_mgr, atc->srcs[i]); kfree(atc->srcs); atc->srcs = NULL; } if (atc->srcimps) { srcimp_mgr = atc->rsc_mgrs[SRCIMP]; for (i = 0; i < atc->n_srcimp; i++) { srcimp = atc->srcimps[i]; srcimp->ops->unmap(srcimp); srcimp_mgr->put_srcimp(srcimp_mgr, atc->srcimps[i]); } kfree(atc->srcimps); atc->srcimps = NULL; } return 0; } static int ct_atc_destroy(struct ct_atc *atc) { int i = 0; if (!atc) return 0; if (atc->timer) { ct_timer_free(atc->timer); atc->timer = NULL; } atc_release_resources(atc); /* Destroy internal mixer objects */ if (atc->mixer) ct_mixer_destroy(atc->mixer); for (i = 0; i < NUM_RSCTYP; i++) { if (rsc_mgr_funcs[i].destroy && atc->rsc_mgrs[i]) rsc_mgr_funcs[i].destroy(atc->rsc_mgrs[i]); } if (atc->hw) destroy_hw_obj(atc->hw); /* Destroy device virtual memory manager object */ if (atc->vm) { ct_vm_destroy(atc->vm); atc->vm = NULL; } kfree(atc); return 0; } static int atc_dev_free(struct snd_device *dev) { struct ct_atc *atc = dev->device_data; return ct_atc_destroy(atc); } static int atc_identify_card(struct ct_atc *atc, unsigned int ssid) { const struct snd_pci_quirk *p; const struct snd_pci_quirk *list; u16 vendor_id, device_id; switch (atc->chip_type) { case ATC20K1: atc->chip_name = "20K1"; list = subsys_20k1_list; break; case ATC20K2: atc->chip_name = "20K2"; list = subsys_20k2_list; break; default: return -ENOENT; } if (ssid) { vendor_id = ssid >> 16; device_id = ssid & 0xffff; } else { vendor_id = atc->pci->subsystem_vendor; device_id = atc->pci->subsystem_device; } p = snd_pci_quirk_lookup_id(vendor_id, device_id, list); if (p) { if (p->value < 0) { dev_err(atc->card->dev, "Device %04x:%04x is on the denylist\n", vendor_id, device_id); return -ENOENT; } atc->model = p->value; } else { if (atc->chip_type == ATC20K1) atc->model = CT20K1_UNKNOWN; else atc->model = CT20K2_UNKNOWN; } atc->model_name = ct_subsys_name[atc->model]; dev_info(atc->card->dev, "chip %s model %s (%04x:%04x) is found\n", atc->chip_name, atc->model_name, vendor_id, device_id); return 0; } int ct_atc_create_alsa_devs(struct ct_atc *atc) { enum CTALSADEVS i; int err; alsa_dev_funcs[MIXER].public_name = atc->chip_name; for (i = 0; i < NUM_CTALSADEVS; i++) { if (!alsa_dev_funcs[i].create) continue; err = alsa_dev_funcs[i].create(atc, i, alsa_dev_funcs[i].public_name); if (err) { dev_err(atc->card->dev, "Creating alsa device %d failed!\n", i); return err; } } return 0; } static int atc_create_hw_devs(struct ct_atc *atc) { struct hw *hw; struct card_conf info = {0}; int i, err; err = create_hw_obj(atc->pci, atc->chip_type, atc->model, &hw); if (err) { dev_err(atc->card->dev, "Failed to create hw obj!!!\n"); return err; } hw->card = atc->card; atc->hw = hw; /* Initialize card hardware. */ info.rsr = atc->rsr; info.msr = atc->msr; info.vm_pgt_phys = atc_get_ptp_phys(atc, 0); err = hw->card_init(hw, &info); if (err < 0) return err; for (i = 0; i < NUM_RSCTYP; i++) { if (!rsc_mgr_funcs[i].create) continue; err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]); if (err) { dev_err(atc->card->dev, "Failed to create rsc_mgr %d!!!\n", i); return err; } } return 0; } static int atc_get_resources(struct ct_atc *atc) { struct daio_desc da_desc = {0}; struct daio_mgr *daio_mgr; struct src_desc src_dsc = {0}; struct src_mgr *src_mgr; struct srcimp_desc srcimp_dsc = {0}; struct srcimp_mgr *srcimp_mgr; struct sum_desc sum_dsc = {0}; struct sum_mgr *sum_mgr; int err, i, num_srcs, num_daios; num_daios = ((atc->model == CTSB1270) ? 8 : 7); num_srcs = ((atc->model == CTSB1270) ? 6 : 4); atc->daios = kcalloc(num_daios, sizeof(void *), GFP_KERNEL); if (!atc->daios) return -ENOMEM; atc->srcs = kcalloc(num_srcs, sizeof(void *), GFP_KERNEL); if (!atc->srcs) return -ENOMEM; atc->srcimps = kcalloc(num_srcs, sizeof(void *), GFP_KERNEL); if (!atc->srcimps) return -ENOMEM; atc->pcm = kcalloc(2 * 4, sizeof(void *), GFP_KERNEL); if (!atc->pcm) return -ENOMEM; daio_mgr = (struct daio_mgr *)atc->rsc_mgrs[DAIO]; da_desc.msr = atc->msr; for (i = 0, atc->n_daio = 0; i < num_daios; i++) { da_desc.type = (atc->model != CTSB073X) ? i : ((i == SPDIFIO) ? SPDIFI1 : i); err = daio_mgr->get_daio(daio_mgr, &da_desc, (struct daio **)&atc->daios[i]); if (err) { dev_err(atc->card->dev, "Failed to get DAIO resource %d!!!\n", i); return err; } atc->n_daio++; } src_mgr = atc->rsc_mgrs[SRC]; src_dsc.multi = 1; src_dsc.msr = atc->msr; src_dsc.mode = ARCRW; for (i = 0, atc->n_src = 0; i < num_srcs; i++) { err = src_mgr->get_src(src_mgr, &src_dsc, (struct src **)&atc->srcs[i]); if (err) return err; atc->n_src++; } srcimp_mgr = atc->rsc_mgrs[SRCIMP]; srcimp_dsc.msr = 8; for (i = 0, atc->n_srcimp = 0; i < num_srcs; i++) { err = srcimp_mgr->get_srcimp(srcimp_mgr, &srcimp_dsc, (struct srcimp **)&atc->srcimps[i]); if (err) return err; atc->n_srcimp++; } sum_mgr = atc->rsc_mgrs[SUM]; sum_dsc.msr = atc->msr; for (i = 0, atc->n_pcm = 0; i < (2*4); i++) { err = sum_mgr->get_sum(sum_mgr, &sum_dsc, (struct sum **)&atc->pcm[i]); if (err) return err; atc->n_pcm++; } return 0; } static void atc_connect_dai(struct src_mgr *src_mgr, struct dai *dai, struct src **srcs, struct srcimp **srcimps) { struct rsc *rscs[2] = {NULL}; struct src *src; struct srcimp *srcimp; int i = 0; rscs[0] = &dai->daio.rscl; rscs[1] = &dai->daio.rscr; for (i = 0; i < 2; i++) { src = srcs[i]; srcimp = srcimps[i]; srcimp->ops->map(srcimp, src, rscs[i]); src_mgr->src_disable(src_mgr, src); } src_mgr->commit_write(src_mgr); /* Actually disable SRCs */ src = srcs[0]; src->ops->set_pm(src, 1); for (i = 0; i < 2; i++) { src = srcs[i]; src->ops->set_state(src, SRC_STATE_RUN); src->ops->commit_write(src); src_mgr->src_enable_s(src_mgr, src); } dai->ops->set_srt_srcl(dai, &(srcs[0]->rsc)); dai->ops->set_srt_srcr(dai, &(srcs[1]->rsc)); dai->ops->set_enb_src(dai, 1); dai->ops->set_enb_srt(dai, 1); dai->ops->commit_write(dai); src_mgr->commit_write(src_mgr); /* Synchronously enable SRCs */ } static void atc_connect_resources(struct ct_atc *atc) { struct dai *dai; struct dao *dao; struct src *src; struct sum *sum; struct ct_mixer *mixer; struct rsc *rscs[2] = {NULL}; int i, j; mixer = atc->mixer; for (i = MIX_WAVE_FRONT, j = LINEO1; i <= MIX_SPDIF_OUT; i++, j++) { mixer->get_output_ports(mixer, i, &rscs[0], &rscs[1]); dao = container_of(atc->daios[j], struct dao, daio); dao->ops->set_left_input(dao, rscs[0]); dao->ops->set_right_input(dao, rscs[1]); } dai = container_of(atc->daios[LINEIM], struct dai, daio); atc_connect_dai(atc->rsc_mgrs[SRC], dai, (struct src **)&atc->srcs[2], (struct srcimp **)&atc->srcimps[2]); src = atc->srcs[2]; mixer->set_input_left(mixer, MIX_LINE_IN, &src->rsc); src = atc->srcs[3]; mixer->set_input_right(mixer, MIX_LINE_IN, &src->rsc); if (atc->model == CTSB1270) { /* Titanium HD has a dedicated ADC for the Mic. */ dai = container_of(atc->daios[MIC], struct dai, daio); atc_connect_dai(atc->rsc_mgrs[SRC], dai, (struct src **)&atc->srcs[4], (struct srcimp **)&atc->srcimps[4]); src = atc->srcs[4]; mixer->set_input_left(mixer, MIX_MIC_IN, &src->rsc); src = atc->srcs[5]; mixer->set_input_right(mixer, MIX_MIC_IN, &src->rsc); } dai = container_of(atc->daios[SPDIFIO], struct dai, daio); atc_connect_dai(atc->rsc_mgrs[SRC], dai, (struct src **)&atc->srcs[0], (struct srcimp **)&atc->srcimps[0]); src = atc->srcs[0]; mixer->set_input_left(mixer, MIX_SPDIF_IN, &src->rsc); src = atc->srcs[1]; mixer->set_input_right(mixer, MIX_SPDIF_IN, &src->rsc); for (i = MIX_PCMI_FRONT, j = 0; i <= MIX_PCMI_SURROUND; i++, j += 2) { sum = atc->pcm[j]; mixer->set_input_left(mixer, i, &sum->rsc); sum = atc->pcm[j+1]; mixer->set_input_right(mixer, i, &sum->rsc); } } #ifdef CONFIG_PM_SLEEP static int atc_suspend(struct ct_atc *atc) { struct hw *hw = atc->hw; snd_power_change_state(atc->card, SNDRV_CTL_POWER_D3hot); atc_release_resources(atc); hw->suspend(hw); return 0; } static int atc_hw_resume(struct ct_atc *atc) { struct hw *hw = atc->hw; struct card_conf info = {0}; /* Re-initialize card hardware. */ info.rsr = atc->rsr; info.msr = atc->msr; info.vm_pgt_phys = atc_get_ptp_phys(atc, 0); return hw->resume(hw, &info); } static int atc_resources_resume(struct ct_atc *atc) { struct ct_mixer *mixer; int err = 0; /* Get resources */ err = atc_get_resources(atc); if (err < 0) { atc_release_resources(atc); return err; } /* Build topology */ atc_connect_resources(atc); mixer = atc->mixer; mixer->resume(mixer); return 0; } static int atc_resume(struct ct_atc *atc) { int err = 0; /* Do hardware resume. */ err = atc_hw_resume(atc); if (err < 0) { dev_err(atc->card->dev, "pci_enable_device failed, disabling device\n"); snd_card_disconnect(atc->card); return err; } err = atc_resources_resume(atc); if (err < 0) return err; snd_power_change_state(atc->card, SNDRV_CTL_POWER_D0); return 0; } #endif static const struct ct_atc atc_preset = { .map_audio_buffer = ct_map_audio_buffer, .unmap_audio_buffer = ct_unmap_audio_buffer, .pcm_playback_prepare = atc_pcm_playback_prepare, .pcm_release_resources = atc_pcm_release_resources, .pcm_playback_start = atc_pcm_playback_start, .pcm_playback_stop = atc_pcm_stop, .pcm_playback_position = atc_pcm_playback_position, .pcm_capture_prepare = atc_pcm_capture_prepare, .pcm_capture_start = atc_pcm_capture_start, .pcm_capture_stop = atc_pcm_stop, .pcm_capture_position = atc_pcm_capture_position, .spdif_passthru_playback_prepare = spdif_passthru_playback_prepare, .get_ptp_phys = atc_get_ptp_phys, .select_line_in = atc_select_line_in, .select_mic_in = atc_select_mic_in, .select_digit_io = atc_select_digit_io, .line_front_unmute = atc_line_front_unmute, .line_surround_unmute = atc_line_surround_unmute, .line_clfe_unmute = atc_line_clfe_unmute, .line_rear_unmute = atc_line_rear_unmute, .line_in_unmute = atc_line_in_unmute, .mic_unmute = atc_mic_unmute, .spdif_out_unmute = atc_spdif_out_unmute, .spdif_in_unmute = atc_spdif_in_unmute, .spdif_out_get_status = atc_spdif_out_get_status, .spdif_out_set_status = atc_spdif_out_set_status, .spdif_out_passthru = atc_spdif_out_passthru, .capabilities = atc_capabilities, .output_switch_get = atc_output_switch_get, .output_switch_put = atc_output_switch_put, .mic_source_switch_get = atc_mic_source_switch_get, .mic_source_switch_put = atc_mic_source_switch_put, #ifdef CONFIG_PM_SLEEP .suspend = atc_suspend, .resume = atc_resume, #endif }; /** * ct_atc_create - create and initialize a hardware manager * @card: corresponding alsa card object * @pci: corresponding kernel pci device object * @rsr: reference sampling rate * @msr: master sampling rate * @chip_type: CHIPTYP enum values * @ssid: vendor ID (upper 16 bits) and device ID (lower 16 bits) * @ratc: return created object address in it * * Creates and initializes a hardware manager. * * Creates kmallocated ct_atc structure. Initializes hardware. * Returns 0 if succeeds, or negative error code if fails. */ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, unsigned int rsr, unsigned int msr, int chip_type, unsigned int ssid, struct ct_atc **ratc) { struct ct_atc *atc; static const struct snd_device_ops ops = { .dev_free = atc_dev_free, }; int err; *ratc = NULL; atc = kzalloc(sizeof(*atc), GFP_KERNEL); if (!atc) return -ENOMEM; /* Set operations */ *atc = atc_preset; atc->card = card; atc->pci = pci; atc->rsr = rsr; atc->msr = msr; atc->chip_type = chip_type; mutex_init(&atc->atc_mutex); /* Find card model */ err = atc_identify_card(atc, ssid); if (err < 0) { dev_err(card->dev, "ctatc: Card not recognised\n"); goto error1; } /* Set up device virtual memory management object */ err = ct_vm_create(&atc->vm, pci); if (err < 0) goto error1; /* Create all atc hw devices */ err = atc_create_hw_devs(atc); if (err < 0) goto error1; err = ct_mixer_create(atc, (struct ct_mixer **)&atc->mixer); if (err) { dev_err(card->dev, "Failed to create mixer obj!!!\n"); goto error1; } /* Get resources */ err = atc_get_resources(atc); if (err < 0) goto error1; /* Build topology */ atc_connect_resources(atc); atc->timer = ct_timer_new(atc); if (!atc->timer) { err = -ENOMEM; goto error1; } err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, atc, &ops); if (err < 0) goto error1; *ratc = atc; return 0; error1: ct_atc_destroy(atc); dev_err(card->dev, "Something wrong!!!\n"); return err; }
linux-master
sound/pci/ctxfi/ctatc.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctimap.c * * @Brief * This file contains the implementation of generic input mapper operations * for input mapper management. * * @Author Liu Chun * @Date May 23 2008 */ #include "ctimap.h" #include <linux/slab.h> int input_mapper_add(struct list_head *mappers, struct imapper *entry, int (*map_op)(void *, struct imapper *), void *data) { struct list_head *pos, *pre, *head; struct imapper *pre_ent, *pos_ent; head = mappers; if (list_empty(head)) { entry->next = entry->addr; map_op(data, entry); list_add(&entry->list, head); return 0; } list_for_each(pos, head) { pos_ent = list_entry(pos, struct imapper, list); if (pos_ent->slot > entry->slot) { /* found a position in list */ break; } } if (pos != head) { pre = pos->prev; if (pre == head) pre = head->prev; __list_add(&entry->list, pos->prev, pos); } else { pre = head->prev; pos = head->next; list_add_tail(&entry->list, head); } pre_ent = list_entry(pre, struct imapper, list); pos_ent = list_entry(pos, struct imapper, list); entry->next = pos_ent->addr; map_op(data, entry); pre_ent->next = entry->addr; map_op(data, pre_ent); return 0; } int input_mapper_delete(struct list_head *mappers, struct imapper *entry, int (*map_op)(void *, struct imapper *), void *data) { struct list_head *next, *pre, *head; struct imapper *pre_ent, *next_ent; head = mappers; if (list_empty(head)) return 0; pre = (entry->list.prev == head) ? head->prev : entry->list.prev; next = (entry->list.next == head) ? head->next : entry->list.next; if (pre == &entry->list) { /* entry is the only one node in mappers list */ entry->next = entry->addr = entry->user = entry->slot = 0; map_op(data, entry); list_del(&entry->list); return 0; } pre_ent = list_entry(pre, struct imapper, list); next_ent = list_entry(next, struct imapper, list); pre_ent->next = next_ent->addr; map_op(data, pre_ent); list_del(&entry->list); return 0; } void free_input_mapper_list(struct list_head *head) { struct imapper *entry; struct list_head *pos; while (!list_empty(head)) { pos = head->next; list_del(pos); entry = list_entry(pos, struct imapper, list); kfree(entry); } }
linux-master
sound/pci/ctxfi/ctimap.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File cthardware.c * * @Brief * This file contains the implementation of hardware access methord. * * @Author Liu Chun * @Date Jun 26 2008 */ #include "cthardware.h" #include "cthw20k1.h" #include "cthw20k2.h" #include <linux/bug.h> int create_hw_obj(struct pci_dev *pci, enum CHIPTYP chip_type, enum CTCARDS model, struct hw **rhw) { int err; switch (chip_type) { case ATC20K1: err = create_20k1_hw_obj(rhw); break; case ATC20K2: err = create_20k2_hw_obj(rhw); break; default: err = -ENODEV; break; } if (err) return err; (*rhw)->pci = pci; (*rhw)->chip_type = chip_type; (*rhw)->model = model; return 0; } int destroy_hw_obj(struct hw *hw) { int err; switch (hw->pci->device) { case 0x0005: /* 20k1 device */ err = destroy_20k1_hw_obj(hw); break; case 0x000B: /* 20k2 device */ err = destroy_20k2_hw_obj(hw); break; default: err = -ENODEV; break; } return err; } unsigned int get_field(unsigned int data, unsigned int field) { int i; if (WARN_ON(!field)) return 0; /* @field should always be greater than 0 */ for (i = 0; !(field & (1 << i)); ) i++; return (data & field) >> i; } void set_field(unsigned int *data, unsigned int field, unsigned int value) { int i; if (WARN_ON(!field)) return; /* @field should always be greater than 0 */ for (i = 0; !(field & (1 << i)); ) i++; *data = (*data & (~field)) | ((value << i) & field); }
linux-master
sound/pci/ctxfi/cthardware.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File cthw20k2.c * * @Brief * This file contains the implementation of hardware access method for 20k2. * * @Author Liu Chun * @Date May 14 2008 */ #include <linux/types.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/io.h> #include <linux/string.h> #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/delay.h> #include "cthw20k2.h" #include "ct20k2reg.h" struct hw20k2 { struct hw hw; /* for i2c */ unsigned char dev_id; unsigned char addr_size; unsigned char data_size; int mic_source; }; static u32 hw_read_20kx(struct hw *hw, u32 reg); static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); /* * Type definition block. * The layout of control structures can be directly applied on 20k2 chip. */ /* * SRC control block definitions. */ /* SRC resource control block */ #define SRCCTL_STATE 0x00000007 #define SRCCTL_BM 0x00000008 #define SRCCTL_RSR 0x00000030 #define SRCCTL_SF 0x000001C0 #define SRCCTL_WR 0x00000200 #define SRCCTL_PM 0x00000400 #define SRCCTL_ROM 0x00001800 #define SRCCTL_VO 0x00002000 #define SRCCTL_ST 0x00004000 #define SRCCTL_IE 0x00008000 #define SRCCTL_ILSZ 0x000F0000 #define SRCCTL_BP 0x00100000 #define SRCCCR_CISZ 0x000007FF #define SRCCCR_CWA 0x001FF800 #define SRCCCR_D 0x00200000 #define SRCCCR_RS 0x01C00000 #define SRCCCR_NAL 0x3E000000 #define SRCCCR_RA 0xC0000000 #define SRCCA_CA 0x0FFFFFFF #define SRCCA_RS 0xE0000000 #define SRCSA_SA 0x0FFFFFFF #define SRCLA_LA 0x0FFFFFFF /* Mixer Parameter Ring ram Low and Hight register. * Fixed-point value in 8.24 format for parameter channel */ #define MPRLH_PITCH 0xFFFFFFFF /* SRC resource register dirty flags */ union src_dirty { struct { u16 ctl:1; u16 ccr:1; u16 sa:1; u16 la:1; u16 ca:1; u16 mpr:1; u16 czbfs:1; /* Clear Z-Buffers */ u16 rsv:9; } bf; u16 data; }; struct src_rsc_ctrl_blk { unsigned int ctl; unsigned int ccr; unsigned int ca; unsigned int sa; unsigned int la; unsigned int mpr; union src_dirty dirty; }; /* SRC manager control block */ union src_mgr_dirty { struct { u16 enb0:1; u16 enb1:1; u16 enb2:1; u16 enb3:1; u16 enb4:1; u16 enb5:1; u16 enb6:1; u16 enb7:1; u16 enbsa:1; u16 rsv:7; } bf; u16 data; }; struct src_mgr_ctrl_blk { unsigned int enbsa; unsigned int enb[8]; union src_mgr_dirty dirty; }; /* SRCIMP manager control block */ #define SRCAIM_ARC 0x00000FFF #define SRCAIM_NXT 0x00FF0000 #define SRCAIM_SRC 0xFF000000 struct srcimap { unsigned int srcaim; unsigned int idx; }; /* SRCIMP manager register dirty flags */ union srcimp_mgr_dirty { struct { u16 srcimap:1; u16 rsv:15; } bf; u16 data; }; struct srcimp_mgr_ctrl_blk { struct srcimap srcimap; union srcimp_mgr_dirty dirty; }; /* * Function implementation block. */ static int src_get_rsc_ctrl_blk(void **rblk) { struct src_rsc_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int src_put_rsc_ctrl_blk(void *blk) { kfree(blk); return 0; } static int src_set_state(void *blk, unsigned int state) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_STATE, state); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_bm(void *blk, unsigned int bm) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_BM, bm); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_rsr(void *blk, unsigned int rsr) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_RSR, rsr); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_sf(void *blk, unsigned int sf) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_SF, sf); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_wr(void *blk, unsigned int wr) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_WR, wr); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_pm(void *blk, unsigned int pm) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_PM, pm); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_rom(void *blk, unsigned int rom) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ROM, rom); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_vo(void *blk, unsigned int vo) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_VO, vo); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_st(void *blk, unsigned int st) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ST, st); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_ie(void *blk, unsigned int ie) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_IE, ie); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_ilsz(void *blk, unsigned int ilsz) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_bp(void *blk, unsigned int bp) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_BP, bp); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_cisz(void *blk, unsigned int cisz) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ccr, SRCCCR_CISZ, cisz); ctl->dirty.bf.ccr = 1; return 0; } static int src_set_ca(void *blk, unsigned int ca) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ca, SRCCA_CA, ca); ctl->dirty.bf.ca = 1; return 0; } static int src_set_sa(void *blk, unsigned int sa) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->sa, SRCSA_SA, sa); ctl->dirty.bf.sa = 1; return 0; } static int src_set_la(void *blk, unsigned int la) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->la, SRCLA_LA, la); ctl->dirty.bf.la = 1; return 0; } static int src_set_pitch(void *blk, unsigned int pitch) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->mpr, MPRLH_PITCH, pitch); ctl->dirty.bf.mpr = 1; return 0; } static int src_set_clear_zbufs(void *blk, unsigned int clear) { ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); return 0; } static int src_set_dirty(void *blk, unsigned int flags) { ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); return 0; } static int src_set_dirty_all(void *blk) { ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); return 0; } #define AR_SLOT_SIZE 4096 #define AR_SLOT_BLOCK_SIZE 16 #define AR_PTS_PITCH 6 #define AR_PARAM_SRC_OFFSET 0x60 static unsigned int src_param_pitch_mixer(unsigned int src_idx) { return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; } static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct src_rsc_ctrl_blk *ctl = blk; int i; if (ctl->dirty.bf.czbfs) { /* Clear Z-Buffer registers */ for (i = 0; i < 8; i++) hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0); for (i = 0; i < 4; i++) hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0); for (i = 0; i < 8; i++) hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0); ctl->dirty.bf.czbfs = 0; } if (ctl->dirty.bf.mpr) { /* Take the parameter mixer resource in the same group as that * the idx src is in for simplicity. Unlike src, all conjugate * parameter mixer resources must be programmed for * corresponding conjugate src resources. */ unsigned int pm_idx = src_param_pitch_mixer(idx); hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr); hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3); hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0); ctl->dirty.bf.mpr = 0; } if (ctl->dirty.bf.sa) { hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa); ctl->dirty.bf.sa = 0; } if (ctl->dirty.bf.la) { hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la); ctl->dirty.bf.la = 0; } if (ctl->dirty.bf.ca) { hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca); ctl->dirty.bf.ca = 0; } /* Write srccf register */ hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0); if (ctl->dirty.bf.ccr) { hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr); ctl->dirty.bf.ccr = 0; } if (ctl->dirty.bf.ctl) { hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl); ctl->dirty.bf.ctl = 0; } return 0; } static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) { struct src_rsc_ctrl_blk *ctl = blk; ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100); ctl->dirty.bf.ca = 0; return get_field(ctl->ca, SRCCA_CA); } static unsigned int src_get_dirty(void *blk) { return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; } static unsigned int src_dirty_conj_mask(void) { return 0x20; } static int src_mgr_enbs_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4)); ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); return 0; } static int src_mgr_enb_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); return 0; } static int src_mgr_dsb_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); return 0; } static int src_mgr_commit_write(struct hw *hw, void *blk) { struct src_mgr_ctrl_blk *ctl = blk; int i; unsigned int ret; if (ctl->dirty.bf.enbsa) { do { ret = hw_read_20kx(hw, SRC_ENBSTAT); } while (ret & 0x1); hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa); ctl->dirty.bf.enbsa = 0; } for (i = 0; i < 8; i++) { if ((ctl->dirty.data & (0x1 << i))) { hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]); ctl->dirty.data &= ~(0x1 << i); } } return 0; } static int src_mgr_get_ctrl_blk(void **rblk) { struct src_mgr_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int src_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int srcimp_mgr_get_ctrl_blk(void **rblk) { struct srcimp_mgr_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int srcimp_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapuser(void *blk, unsigned int user) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr) { ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr; ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_commit_write(struct hw *hw, void *blk) { struct srcimp_mgr_ctrl_blk *ctl = blk; if (ctl->dirty.bf.srcimap) { hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100, ctl->srcimap.srcaim); ctl->dirty.bf.srcimap = 0; } return 0; } /* * AMIXER control block definitions. */ #define AMOPLO_M 0x00000003 #define AMOPLO_IV 0x00000004 #define AMOPLO_X 0x0003FFF0 #define AMOPLO_Y 0xFFFC0000 #define AMOPHI_SADR 0x000000FF #define AMOPHI_SE 0x80000000 /* AMIXER resource register dirty flags */ union amixer_dirty { struct { u16 amoplo:1; u16 amophi:1; u16 rsv:14; } bf; u16 data; }; /* AMIXER resource control block */ struct amixer_rsc_ctrl_blk { unsigned int amoplo; unsigned int amophi; union amixer_dirty dirty; }; static int amixer_set_mode(void *blk, unsigned int mode) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_M, mode); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_iv(void *blk, unsigned int iv) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_IV, iv); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_x(void *blk, unsigned int x) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_X, x); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_y(void *blk, unsigned int y) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_Y, y); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_sadr(void *blk, unsigned int sadr) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amophi, AMOPHI_SADR, sadr); ctl->dirty.bf.amophi = 1; return 0; } static int amixer_set_se(void *blk, unsigned int se) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amophi, AMOPHI_SE, se); ctl->dirty.bf.amophi = 1; return 0; } static int amixer_set_dirty(void *blk, unsigned int flags) { ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); return 0; } static int amixer_set_dirty_all(void *blk) { ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); return 0; } static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct amixer_rsc_ctrl_blk *ctl = blk; if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo); ctl->dirty.bf.amoplo = 0; hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi); ctl->dirty.bf.amophi = 0; } return 0; } static int amixer_get_y(void *blk) { struct amixer_rsc_ctrl_blk *ctl = blk; return get_field(ctl->amoplo, AMOPLO_Y); } static unsigned int amixer_get_dirty(void *blk) { return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; } static int amixer_rsc_get_ctrl_blk(void **rblk) { struct amixer_rsc_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int amixer_rsc_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int amixer_mgr_get_ctrl_blk(void **rblk) { *rblk = NULL; return 0; } static int amixer_mgr_put_ctrl_blk(void *blk) { return 0; } /* * DAIO control block definitions. */ /* Receiver Sample Rate Tracker Control register */ #define SRTCTL_SRCO 0x000000FF #define SRTCTL_SRCM 0x0000FF00 #define SRTCTL_RSR 0x00030000 #define SRTCTL_DRAT 0x00300000 #define SRTCTL_EC 0x01000000 #define SRTCTL_ET 0x10000000 /* DAIO Receiver register dirty flags */ union dai_dirty { struct { u16 srt:1; u16 rsv:15; } bf; u16 data; }; /* DAIO Receiver control block */ struct dai_ctrl_blk { unsigned int srt; union dai_dirty dirty; }; /* Audio Input Mapper RAM */ #define AIM_ARC 0x00000FFF #define AIM_NXT 0x007F0000 struct daoimap { unsigned int aim; unsigned int idx; }; /* Audio Transmitter Control and Status register */ #define ATXCTL_EN 0x00000001 #define ATXCTL_MODE 0x00000010 #define ATXCTL_CD 0x00000020 #define ATXCTL_RAW 0x00000100 #define ATXCTL_MT 0x00000200 #define ATXCTL_NUC 0x00003000 #define ATXCTL_BEN 0x00010000 #define ATXCTL_BMUX 0x00700000 #define ATXCTL_B24 0x01000000 #define ATXCTL_CPF 0x02000000 #define ATXCTL_RIV 0x10000000 #define ATXCTL_LIV 0x20000000 #define ATXCTL_RSAT 0x40000000 #define ATXCTL_LSAT 0x80000000 /* XDIF Transmitter register dirty flags */ union dao_dirty { struct { u16 atxcsl:1; u16 rsv:15; } bf; u16 data; }; /* XDIF Transmitter control block */ struct dao_ctrl_blk { /* XDIF Transmitter Channel Status Low Register */ unsigned int atxcsl; union dao_dirty dirty; }; /* Audio Receiver Control register */ #define ARXCTL_EN 0x00000001 /* DAIO manager register dirty flags */ union daio_mgr_dirty { struct { u32 atxctl:8; u32 arxctl:8; u32 daoimap:1; u32 rsv:15; } bf; u32 data; }; /* DAIO manager control block */ struct daio_mgr_ctrl_blk { struct daoimap daoimap; unsigned int txctl[8]; unsigned int rxctl[8]; union daio_mgr_dirty dirty; }; static int dai_srt_set_srco(void *blk, unsigned int src) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_SRCO, src); ctl->dirty.bf.srt = 1; return 0; } static int dai_srt_set_srcm(void *blk, unsigned int src) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_SRCM, src); ctl->dirty.bf.srt = 1; return 0; } static int dai_srt_set_rsr(void *blk, unsigned int rsr) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_RSR, rsr); ctl->dirty.bf.srt = 1; return 0; } static int dai_srt_set_drat(void *blk, unsigned int drat) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_DRAT, drat); ctl->dirty.bf.srt = 1; return 0; } static int dai_srt_set_ec(void *blk, unsigned int ec) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0); ctl->dirty.bf.srt = 1; return 0; } static int dai_srt_set_et(void *blk, unsigned int et) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0); ctl->dirty.bf.srt = 1; return 0; } static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct dai_ctrl_blk *ctl = blk; if (ctl->dirty.bf.srt) { hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt); ctl->dirty.bf.srt = 0; } return 0; } static int dai_get_ctrl_blk(void **rblk) { struct dai_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int dai_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int dao_set_spos(void *blk, unsigned int spos) { ((struct dao_ctrl_blk *)blk)->atxcsl = spos; ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1; return 0; } static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct dao_ctrl_blk *ctl = blk; if (ctl->dirty.bf.atxcsl) { if (idx < 4) { /* S/PDIF SPOSx */ hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx, ctl->atxcsl); } ctl->dirty.bf.atxcsl = 0; } return 0; } static int dao_get_spos(void *blk, unsigned int *spos) { *spos = ((struct dao_ctrl_blk *)blk)->atxcsl; return 0; } static int dao_get_ctrl_blk(void **rblk) { struct dao_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int dao_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int daio_mgr_enb_dai(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->rxctl[idx], ARXCTL_EN, 1); ctl->dirty.bf.arxctl |= (0x1 << idx); return 0; } static int daio_mgr_dsb_dai(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->rxctl[idx], ARXCTL_EN, 0); ctl->dirty.bf.arxctl |= (0x1 << idx); return 0; } static int daio_mgr_enb_dao(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->txctl[idx], ATXCTL_EN, 1); ctl->dirty.bf.atxctl |= (0x1 << idx); return 0; } static int daio_mgr_dsb_dao(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->txctl[idx], ATXCTL_EN, 0); ctl->dirty.bf.atxctl |= (0x1 << idx); return 0; } static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF output */ switch ((conf & 0xf)) { case 1: set_field(&ctl->txctl[idx], ATXCTL_NUC, 0); break; case 2: set_field(&ctl->txctl[idx], ATXCTL_NUC, 1); break; case 4: set_field(&ctl->txctl[idx], ATXCTL_NUC, 2); break; case 8: set_field(&ctl->txctl[idx], ATXCTL_NUC, 3); break; default: break; } /* CDIF */ set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7))); /* Non-audio */ set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1); /* Non-audio */ set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1); set_field(&ctl->txctl[idx], ATXCTL_RAW, ((conf >> 3) & 0x1) ? 0 : 0); ctl->dirty.bf.atxctl |= (0x1 << idx); } else { /* I2S output */ /*idx %= 4; */ } return 0; } static int daio_mgr_set_imaparc(void *blk, unsigned int slot) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->daoimap.aim, AIM_ARC, slot); ctl->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_set_imapnxt(void *blk, unsigned int next) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->daoimap.aim, AIM_NXT, next); ctl->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_set_imapaddr(void *blk, unsigned int addr) { ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr; ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_commit_write(struct hw *hw, void *blk) { struct daio_mgr_ctrl_blk *ctl = blk; unsigned int data; int i; for (i = 0; i < 8; i++) { if ((ctl->dirty.bf.atxctl & (0x1 << i))) { data = ctl->txctl[i]; hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); ctl->dirty.bf.atxctl &= ~(0x1 << i); mdelay(1); } if ((ctl->dirty.bf.arxctl & (0x1 << i))) { data = ctl->rxctl[i]; hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); ctl->dirty.bf.arxctl &= ~(0x1 << i); mdelay(1); } } if (ctl->dirty.bf.daoimap) { hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4, ctl->daoimap.aim); ctl->dirty.bf.daoimap = 0; } return 0; } static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) { struct daio_mgr_ctrl_blk *blk; int i; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; for (i = 0; i < 8; i++) { blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i)); blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i)); } *rblk = blk; return 0; } static int daio_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } /* Timer interrupt */ static int set_timer_irq(struct hw *hw, int enable) { hw_write_20kx(hw, GIE, enable ? IT_INT : 0); return 0; } static int set_timer_tick(struct hw *hw, unsigned int ticks) { if (ticks) ticks |= TIMR_IE | TIMR_IP; hw_write_20kx(hw, TIMR, ticks); return 0; } static unsigned int get_wc(struct hw *hw) { return hw_read_20kx(hw, WC); } /* Card hardware initialization block */ struct dac_conf { unsigned int msr; /* master sample rate in rsrs */ }; struct adc_conf { unsigned int msr; /* master sample rate in rsrs */ unsigned char input; /* the input source of ADC */ unsigned char mic20db; /* boost mic by 20db if input is microphone */ }; struct daio_conf { unsigned int msr; /* master sample rate in rsrs */ }; struct trn_conf { unsigned long vm_pgt_phys; }; static int hw_daio_init(struct hw *hw, const struct daio_conf *info) { u32 data; int i; /* Program I2S with proper sample rate and enable the correct I2S * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */ if (1 == info->msr) { hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101); hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101); hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); } else if (2 == info->msr) { if (hw->model != CTSB1270) { hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111); } else { /* PCM4220 on Titanium HD is different. */ hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111); } /* Specify all playing 96khz * EA [0] - Enabled * RTA [4:5] - 96kHz * EB [8] - Enabled * RTB [12:13] - 96kHz * EC [16] - Enabled * RTC [20:21] - 96kHz * ED [24] - Enabled * RTD [28:29] - 96kHz */ hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111); hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); } else if ((4 == info->msr) && (hw->model == CTSB1270)) { hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111); hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); } else { dev_alert(hw->card->dev, "ERROR!!! Invalid sampling rate!!!\n"); return -EINVAL; } for (i = 0; i < 8; i++) { if (i <= 3) { /* This comment looks wrong since loop is over 4 */ /* channels and emu20k2 supports 4 spdif IOs. */ /* 1st 3 channels are SPDIFs (SB0960) */ if (i == 3) data = 0x1001001; else data = 0x1000001; hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); /* Initialize the SPDIF Out Channel status registers. * The value specified here is based on the typical * values provided in the specification, namely: Clock * Accuracy of 1000ppm, Sample Rate of 48KHz, * unspecified source number, Generation status = 1, * Category code = 0x12 (Digital Signal Mixer), * Mode = 0, Emph = 0, Copy Permitted, AN = 0 * (indicating that we're transmitting digital audio, * and the Professional Use bit is 0. */ hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i), 0x02109204); /* Default to 48kHz */ hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B); } else { /* Again, loop is over 4 channels not 5. */ /* Next 5 channels are I2S (SB0960) */ data = 0x11; hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data); if (2 == info->msr) { /* Four channels per sample period */ data |= 0x1000; } else if (4 == info->msr) { /* FIXME: check this against the chip spec */ data |= 0x2000; } hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data); } } return 0; } /* TRANSPORT operations */ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) { u32 vmctl, data; u32 ptp_phys_low, ptp_phys_high; int i; /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { dev_alert(hw->card->dev, "Wrong device page table page address!!!\n"); return -1; } vmctl = 0x80000C0F; /* 32-bit, 4k-size page */ ptp_phys_low = (u32)info->vm_pgt_phys; ptp_phys_high = upper_32_bits(info->vm_pgt_phys); if (sizeof(void *) == 8) /* 64bit address */ vmctl |= (3 << 8); /* Write page table physical address to all PTPAL registers */ for (i = 0; i < 64; i++) { hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low); hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high); } /* Enable virtual memory transfer */ hw_write_20kx(hw, VMEM_CTL, vmctl); /* Enable transport bus master and queueing of request */ hw_write_20kx(hw, TRANSPORT_CTL, 0x03); hw_write_20kx(hw, TRANSPORT_INT, 0x200c01); /* Enable transport ring */ data = hw_read_20kx(hw, TRANSPORT_ENB); hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03)); return 0; } /* Card initialization */ #define GCTL_AIE 0x00000001 #define GCTL_UAA 0x00000002 #define GCTL_DPC 0x00000004 #define GCTL_DBP 0x00000008 #define GCTL_ABP 0x00000010 #define GCTL_TBP 0x00000020 #define GCTL_SBP 0x00000040 #define GCTL_FBP 0x00000080 #define GCTL_ME 0x00000100 #define GCTL_AID 0x00001000 #define PLLCTL_SRC 0x00000007 #define PLLCTL_SPE 0x00000008 #define PLLCTL_RD 0x000000F0 #define PLLCTL_FD 0x0001FF00 #define PLLCTL_OD 0x00060000 #define PLLCTL_B 0x00080000 #define PLLCTL_AS 0x00100000 #define PLLCTL_LF 0x03E00000 #define PLLCTL_SPS 0x1C000000 #define PLLCTL_AD 0x60000000 #define PLLSTAT_CCS 0x00000007 #define PLLSTAT_SPL 0x00000008 #define PLLSTAT_CRD 0x000000F0 #define PLLSTAT_CFD 0x0001FF00 #define PLLSTAT_SL 0x00020000 #define PLLSTAT_FAS 0x00040000 #define PLLSTAT_B 0x00080000 #define PLLSTAT_PD 0x00100000 #define PLLSTAT_OCA 0x00200000 #define PLLSTAT_NCA 0x00400000 static int hw_pll_init(struct hw *hw, unsigned int rsr) { unsigned int pllenb; unsigned int pllctl; unsigned int pllstat; int i; pllenb = 0xB; hw_write_20kx(hw, PLL_ENB, pllenb); pllctl = 0x20C00000; set_field(&pllctl, PLLCTL_B, 0); set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4); set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1); hw_write_20kx(hw, PLL_CTL, pllctl); msleep(40); pllctl = hw_read_20kx(hw, PLL_CTL); set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2); hw_write_20kx(hw, PLL_CTL, pllctl); msleep(40); for (i = 0; i < 1000; i++) { pllstat = hw_read_20kx(hw, PLL_STAT); if (get_field(pllstat, PLLSTAT_PD)) continue; if (get_field(pllstat, PLLSTAT_B) != get_field(pllctl, PLLCTL_B)) continue; if (get_field(pllstat, PLLSTAT_CCS) != get_field(pllctl, PLLCTL_SRC)) continue; if (get_field(pllstat, PLLSTAT_CRD) != get_field(pllctl, PLLCTL_RD)) continue; if (get_field(pllstat, PLLSTAT_CFD) != get_field(pllctl, PLLCTL_FD)) continue; break; } if (i >= 1000) { dev_alert(hw->card->dev, "PLL initialization failed!!!\n"); return -EBUSY; } return 0; } static int hw_auto_init(struct hw *hw) { unsigned int gctl; int i; gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); set_field(&gctl, GCTL_AIE, 0); hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); set_field(&gctl, GCTL_AIE, 1); hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); mdelay(10); for (i = 0; i < 400000; i++) { gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); if (get_field(gctl, GCTL_AID)) break; } if (!get_field(gctl, GCTL_AID)) { dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); return -EBUSY; } return 0; } /* DAC operations */ #define CS4382_MC1 0x1 #define CS4382_MC2 0x2 #define CS4382_MC3 0x3 #define CS4382_FC 0x4 #define CS4382_IC 0x5 #define CS4382_XC1 0x6 #define CS4382_VCA1 0x7 #define CS4382_VCB1 0x8 #define CS4382_XC2 0x9 #define CS4382_VCA2 0xA #define CS4382_VCB2 0xB #define CS4382_XC3 0xC #define CS4382_VCA3 0xD #define CS4382_VCB3 0xE #define CS4382_XC4 0xF #define CS4382_VCA4 0x10 #define CS4382_VCB4 0x11 #define CS4382_CREV 0x12 /* I2C status */ #define STATE_LOCKED 0x00 #define STATE_UNLOCKED 0xAA #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */ #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */ #define I2C_STATUS_DCM 0x00000001 #define I2C_STATUS_BC 0x00000006 #define I2C_STATUS_APD 0x00000008 #define I2C_STATUS_AB 0x00010000 #define I2C_STATUS_DR 0x00800000 #define I2C_ADDRESS_PTAD 0x0000FFFF #define I2C_ADDRESS_SLAD 0x007F0000 struct regs_cs4382 { u32 mode_control_1; u32 mode_control_2; u32 mode_control_3; u32 filter_control; u32 invert_control; u32 mix_control_P1; u32 vol_control_A1; u32 vol_control_B1; u32 mix_control_P2; u32 vol_control_A2; u32 vol_control_B2; u32 mix_control_P3; u32 vol_control_A3; u32 vol_control_B3; u32 mix_control_P4; u32 vol_control_A4; u32 vol_control_B4; }; static int hw20k2_i2c_unlock_full_access(struct hw *hw) { u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4}; /* Send keys for forced BIOS mode */ hw_write_20kx(hw, I2C_IF_WLOCK, UnlockKeySequence_FLASH_FULLACCESS_MODE[0]); hw_write_20kx(hw, I2C_IF_WLOCK, UnlockKeySequence_FLASH_FULLACCESS_MODE[1]); /* Check whether the chip is unlocked */ if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED) return 0; return -1; } static int hw20k2_i2c_lock_chip(struct hw *hw) { /* Write twice */ hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED) return 0; return -1; } static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size) { struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; int err; unsigned int i2c_status; unsigned int i2c_addr; err = hw20k2_i2c_unlock_full_access(hw); if (err < 0) return err; hw20k2->addr_size = addr_size; hw20k2->data_size = data_size; hw20k2->dev_id = dev_id; i2c_addr = 0; set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id); hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */ hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); return 0; } static int hw20k2_i2c_uninit(struct hw *hw) { unsigned int i2c_status; unsigned int i2c_addr; i2c_addr = 0; set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */ hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */ hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); return hw20k2_i2c_lock_chip(hw); } static int hw20k2_i2c_wait_data_ready(struct hw *hw) { int i = 0x400000; unsigned int ret; do { ret = hw_read_20kx(hw, I2C_IF_STATUS); } while ((!(ret & DATA_READY)) && --i); return i; } static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap) { struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; unsigned int i2c_status; i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); set_field(&i2c_status, I2C_STATUS_BC, (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size); hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); if (!hw20k2_i2c_wait_data_ready(hw)) return -1; hw_write_20kx(hw, I2C_IF_WDATA, addr); if (!hw20k2_i2c_wait_data_ready(hw)) return -1; /* Force a read operation */ hw_write_20kx(hw, I2C_IF_RDATA, 0); if (!hw20k2_i2c_wait_data_ready(hw)) return -1; *datap = hw_read_20kx(hw, I2C_IF_RDATA); return 0; } static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data) { struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr; unsigned int i2c_status; i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); set_field(&i2c_status, I2C_STATUS_BC, (4 == (hw20k2->addr_size + hw20k2->data_size)) ? 0 : (hw20k2->addr_size + hw20k2->data_size)); hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); hw20k2_i2c_wait_data_ready(hw); /* Dummy write to trigger the write operation */ hw_write_20kx(hw, I2C_IF_WDATA, 0); hw20k2_i2c_wait_data_ready(hw); /* This is the real data */ hw_write_20kx(hw, I2C_IF_WDATA, i2c_data); hw20k2_i2c_wait_data_ready(hw); return 0; } static void hw_dac_stop(struct hw *hw) { u32 data; data = hw_read_20kx(hw, GPIO_DATA); data &= 0xFFFFFFFD; hw_write_20kx(hw, GPIO_DATA, data); usleep_range(10000, 11000); } static void hw_dac_start(struct hw *hw) { u32 data; data = hw_read_20kx(hw, GPIO_DATA); data |= 0x2; hw_write_20kx(hw, GPIO_DATA, data); msleep(50); } static void hw_dac_reset(struct hw *hw) { hw_dac_stop(hw); hw_dac_start(hw); } static int hw_dac_init(struct hw *hw, const struct dac_conf *info) { int err; u32 data; int i; struct regs_cs4382 cs_read = {0}; struct regs_cs4382 cs_def = { .mode_control_1 = 0x00000001, /* Mode Control 1 */ .mode_control_2 = 0x00000000, /* Mode Control 2 */ .mode_control_3 = 0x00000084, /* Mode Control 3 */ .filter_control = 0x00000000, /* Filter Control */ .invert_control = 0x00000000, /* Invert Control */ .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */ .vol_control_A1 = 0x00000000, /* Vol Control A1 */ .vol_control_B1 = 0x00000000, /* Vol Control B1 */ .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */ .vol_control_A2 = 0x00000000, /* Vol Control A2 */ .vol_control_B2 = 0x00000000, /* Vol Control B2 */ .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */ .vol_control_A3 = 0x00000000, /* Vol Control A3 */ .vol_control_B3 = 0x00000000, /* Vol Control B3 */ .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */ .vol_control_A4 = 0x00000000, /* Vol Control A4 */ .vol_control_B4 = 0x00000000 /* Vol Control B4 */ }; if (hw->model == CTSB1270) { hw_dac_stop(hw); data = hw_read_20kx(hw, GPIO_DATA); data &= ~0x0600; if (1 == info->msr) data |= 0x0000; /* Single Speed Mode 0-50kHz */ else if (2 == info->msr) data |= 0x0200; /* Double Speed Mode 50-100kHz */ else data |= 0x0600; /* Quad Speed Mode 100-200kHz */ hw_write_20kx(hw, GPIO_DATA, data); hw_dac_start(hw); return 0; } /* Set DAC reset bit as output */ data = hw_read_20kx(hw, GPIO_CTRL); data |= 0x02; hw_write_20kx(hw, GPIO_CTRL, data); err = hw20k2_i2c_init(hw, 0x18, 1, 1); if (err < 0) goto End; for (i = 0; i < 2; i++) { /* Reset DAC twice just in-case the chip * didn't initialized properly */ hw_dac_reset(hw); hw_dac_reset(hw); if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1)) continue; if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2)) continue; if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3)) continue; if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control)) continue; if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control)) continue; if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1)) continue; if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1)) continue; if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1)) continue; if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2)) continue; if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2)) continue; if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2)) continue; if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3)) continue; if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3)) continue; if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3)) continue; if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4)) continue; if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4)) continue; if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4)) continue; if (memcmp(&cs_read, &cs_def, sizeof(cs_read))) continue; else break; } if (i >= 2) goto End; /* Note: Every I2C write must have some delay. * This is not a requirement but the delay works here... */ hw20k2_i2c_write(hw, CS4382_MC1, 0x80); hw20k2_i2c_write(hw, CS4382_MC2, 0x10); if (1 == info->msr) { hw20k2_i2c_write(hw, CS4382_XC1, 0x24); hw20k2_i2c_write(hw, CS4382_XC2, 0x24); hw20k2_i2c_write(hw, CS4382_XC3, 0x24); hw20k2_i2c_write(hw, CS4382_XC4, 0x24); } else if (2 == info->msr) { hw20k2_i2c_write(hw, CS4382_XC1, 0x25); hw20k2_i2c_write(hw, CS4382_XC2, 0x25); hw20k2_i2c_write(hw, CS4382_XC3, 0x25); hw20k2_i2c_write(hw, CS4382_XC4, 0x25); } else { hw20k2_i2c_write(hw, CS4382_XC1, 0x26); hw20k2_i2c_write(hw, CS4382_XC2, 0x26); hw20k2_i2c_write(hw, CS4382_XC3, 0x26); hw20k2_i2c_write(hw, CS4382_XC4, 0x26); } return 0; End: hw20k2_i2c_uninit(hw); return -1; } /* ADC operations */ #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1)) #define MAKE_WM8775_DATA(data) (u32)(data&0xFF) #define WM8775_IC 0x0B #define WM8775_MMC 0x0C #define WM8775_AADCL 0x0E #define WM8775_AADCR 0x0F #define WM8775_ADCMC 0x15 #define WM8775_RESET 0x17 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) { u32 data; if (hw->model == CTSB1270) { /* Titanium HD has two ADC chips, one for line in and one */ /* for MIC. We don't need to switch the ADC input. */ return 1; } data = hw_read_20kx(hw, GPIO_DATA); switch (type) { case ADC_MICIN: data = (data & (0x1 << 14)) ? 1 : 0; break; case ADC_LINEIN: data = (data & (0x1 << 14)) ? 0 : 1; break; default: data = 0; } return data; } #define MIC_BOOST_0DB 0xCF #define MIC_BOOST_STEPS_PER_DB 2 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db) { u32 adcmc, gain; if (input > 3) input = 3; adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */ hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc), MAKE_WM8775_DATA(adcmc)); if (gain_in_db < -103) gain_in_db = -103; if (gain_in_db > 24) gain_in_db = 24; gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB; hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain), MAKE_WM8775_DATA(gain)); /* ...so there should be no need for the following. */ hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain), MAKE_WM8775_DATA(gain)); } static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) { u32 data; data = hw_read_20kx(hw, GPIO_DATA); switch (type) { case ADC_MICIN: data |= (0x1 << 14); hw_write_20kx(hw, GPIO_DATA, data); hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */ break; case ADC_LINEIN: data &= ~(0x1 << 14); hw_write_20kx(hw, GPIO_DATA, data); hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */ break; default: break; } return 0; } static int hw_adc_init(struct hw *hw, const struct adc_conf *info) { int err; u32 data, ctl; /* Set ADC reset bit as output */ data = hw_read_20kx(hw, GPIO_CTRL); data |= (0x1 << 15); hw_write_20kx(hw, GPIO_CTRL, data); /* Initialize I2C */ err = hw20k2_i2c_init(hw, 0x1A, 1, 1); if (err < 0) { dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n"); goto error; } /* Reset the ADC (reset is active low). */ data = hw_read_20kx(hw, GPIO_DATA); data &= ~(0x1 << 15); hw_write_20kx(hw, GPIO_DATA, data); if (hw->model == CTSB1270) { /* Set up the PCM4220 ADC on Titanium HD */ data &= ~0x0C; if (1 == info->msr) data |= 0x00; /* Single Speed Mode 32-50kHz */ else if (2 == info->msr) data |= 0x08; /* Double Speed Mode 50-108kHz */ else data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */ hw_write_20kx(hw, GPIO_DATA, data); } usleep_range(10000, 11000); /* Return the ADC to normal operation. */ data |= (0x1 << 15); hw_write_20kx(hw, GPIO_DATA, data); msleep(50); /* I2C write to register offset 0x0B to set ADC LRCLK polarity */ /* invert bit, interface format to I2S, word length to 24-bit, */ /* enable ADC high pass filter. Fixes bug 5323? */ hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26), MAKE_WM8775_DATA(0x26)); /* Set the master mode (256fs) */ if (1 == info->msr) { /* slave mode, 128x oversampling 256fs */ hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02), MAKE_WM8775_DATA(0x02)); } else if ((2 == info->msr) || (4 == info->msr)) { /* slave mode, 64x oversampling, 256fs */ hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), MAKE_WM8775_DATA(0x0A)); } else { dev_alert(hw->card->dev, "Invalid master sampling rate (msr %d)!!!\n", info->msr); err = -EINVAL; goto error; } if (hw->model != CTSB1270) { /* Configure GPIO bit 14 change to line-in/mic-in */ ctl = hw_read_20kx(hw, GPIO_CTRL); ctl |= 0x1 << 14; hw_write_20kx(hw, GPIO_CTRL, ctl); hw_adc_input_select(hw, ADC_LINEIN); } else { hw_wm8775_input_select(hw, 0, 0); } return 0; error: hw20k2_i2c_uninit(hw); return err; } static struct capabilities hw_capabilities(struct hw *hw) { struct capabilities cap; cap.digit_io_switch = 0; cap.dedicated_mic = hw->model == CTSB1270; cap.output_switch = hw->model == CTSB1270; cap.mic_source_switch = hw->model == CTSB1270; return cap; } static int hw_output_switch_get(struct hw *hw) { u32 data = hw_read_20kx(hw, GPIO_EXT_DATA); switch (data & 0x30) { case 0x00: return 0; case 0x10: return 1; case 0x20: return 2; default: return 3; } } static int hw_output_switch_put(struct hw *hw, int position) { u32 data; if (position == hw_output_switch_get(hw)) return 0; /* Mute line and headphones (intended for anti-pop). */ data = hw_read_20kx(hw, GPIO_DATA); data |= (0x03 << 11); hw_write_20kx(hw, GPIO_DATA, data); data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30; switch (position) { case 0: break; case 1: data |= 0x10; break; default: data |= 0x20; } hw_write_20kx(hw, GPIO_EXT_DATA, data); /* Unmute line and headphones. */ data = hw_read_20kx(hw, GPIO_DATA); data &= ~(0x03 << 11); hw_write_20kx(hw, GPIO_DATA, data); return 1; } static int hw_mic_source_switch_get(struct hw *hw) { struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; return hw20k2->mic_source; } static int hw_mic_source_switch_put(struct hw *hw, int position) { struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; if (position == hw20k2->mic_source) return 0; switch (position) { case 0: hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */ break; case 1: hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */ break; case 2: hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */ break; default: return 0; } hw20k2->mic_source = position; return 1; } static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id) { struct hw *hw = dev_id; unsigned int status; status = hw_read_20kx(hw, GIP); if (!status) return IRQ_NONE; if (hw->irq_callback) hw->irq_callback(hw->irq_callback_data, status); hw_write_20kx(hw, GIP, status); return IRQ_HANDLED; } static int hw_card_start(struct hw *hw) { int err = 0; struct pci_dev *pci = hw->pci; unsigned int gctl; const unsigned int dma_bits = BITS_PER_LONG; err = pci_enable_device(pci); if (err < 0) return err; /* Set DMA transfer mask */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); if (!hw->io_base) { err = pci_request_regions(pci, "XFi"); if (err < 0) goto error1; hw->io_base = pci_resource_start(hw->pci, 2); hw->mem_base = ioremap(hw->io_base, pci_resource_len(hw->pci, 2)); if (!hw->mem_base) { err = -ENOENT; goto error2; } } /* Switch to 20k2 mode from UAA mode. */ gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); set_field(&gctl, GCTL_UAA, 0); hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); if (hw->irq < 0) { err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { dev_err(hw->card->dev, "XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; hw->card->sync_irq = hw->irq; } pci_set_master(pci); return 0; /*error3: iounmap((void *)hw->mem_base); hw->mem_base = (unsigned long)NULL;*/ error2: pci_release_regions(pci); hw->io_base = 0; error1: pci_disable_device(pci); return err; } static int hw_card_stop(struct hw *hw) { unsigned int data; /* disable transport bus master and queueing of request */ hw_write_20kx(hw, TRANSPORT_CTL, 0x00); /* disable pll */ data = hw_read_20kx(hw, PLL_ENB); hw_write_20kx(hw, PLL_ENB, (data & (~0x07))); /* TODO: Disable interrupt and so on... */ return 0; } static int hw_card_shutdown(struct hw *hw) { if (hw->irq >= 0) free_irq(hw->irq, hw); hw->irq = -1; iounmap(hw->mem_base); hw->mem_base = NULL; if (hw->io_base) pci_release_regions(hw->pci); hw->io_base = 0; pci_disable_device(hw->pci); return 0; } static int hw_card_init(struct hw *hw, struct card_conf *info) { int err; unsigned int gctl; u32 data = 0; struct dac_conf dac_info = {0}; struct adc_conf adc_info = {0}; struct daio_conf daio_info = {0}; struct trn_conf trn_info = {0}; /* Get PCI io port/memory base address and * do 20kx core switch if needed. */ err = hw_card_start(hw); if (err) return err; /* PLL init */ err = hw_pll_init(hw, info->rsr); if (err < 0) return err; /* kick off auto-init */ err = hw_auto_init(hw); if (err < 0) return err; gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); set_field(&gctl, GCTL_DBP, 1); set_field(&gctl, GCTL_TBP, 1); set_field(&gctl, GCTL_FBP, 1); set_field(&gctl, GCTL_DPC, 0); hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); /* Reset all global pending interrupts */ hw_write_20kx(hw, GIE, 0); /* Reset all SRC pending interrupts */ hw_write_20kx(hw, SRC_IP, 0); if (hw->model != CTSB1270) { /* TODO: detect the card ID and configure GPIO accordingly. */ /* Configures GPIO (0xD802 0x98028) */ /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/ /* Configures GPIO (SB0880) */ /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/ hw_write_20kx(hw, GPIO_CTRL, 0xD802); } else { hw_write_20kx(hw, GPIO_CTRL, 0x9E5F); } /* Enable audio ring */ hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01); trn_info.vm_pgt_phys = info->vm_pgt_phys; err = hw_trn_init(hw, &trn_info); if (err < 0) return err; daio_info.msr = info->msr; err = hw_daio_init(hw, &daio_info); if (err < 0) return err; dac_info.msr = info->msr; err = hw_dac_init(hw, &dac_info); if (err < 0) return err; adc_info.msr = info->msr; adc_info.input = ADC_LINEIN; adc_info.mic20db = 0; err = hw_adc_init(hw, &adc_info); if (err < 0) return err; data = hw_read_20kx(hw, SRC_MCTL); data |= 0x1; /* Enables input from the audio ring */ hw_write_20kx(hw, SRC_MCTL, data); return 0; } #ifdef CONFIG_PM_SLEEP static int hw_suspend(struct hw *hw) { hw_card_stop(hw); return 0; } static int hw_resume(struct hw *hw, struct card_conf *info) { /* Re-initialize card hardware. */ return hw_card_init(hw, info); } #endif static u32 hw_read_20kx(struct hw *hw, u32 reg) { return readl(hw->mem_base + reg); } static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) { writel(data, hw->mem_base + reg); } static const struct hw ct20k2_preset = { .irq = -1, .card_init = hw_card_init, .card_stop = hw_card_stop, .pll_init = hw_pll_init, .is_adc_source_selected = hw_is_adc_input_selected, .select_adc_source = hw_adc_input_select, .capabilities = hw_capabilities, .output_switch_get = hw_output_switch_get, .output_switch_put = hw_output_switch_put, .mic_source_switch_get = hw_mic_source_switch_get, .mic_source_switch_put = hw_mic_source_switch_put, #ifdef CONFIG_PM_SLEEP .suspend = hw_suspend, .resume = hw_resume, #endif .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk, .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk, .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk, .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk, .src_set_state = src_set_state, .src_set_bm = src_set_bm, .src_set_rsr = src_set_rsr, .src_set_sf = src_set_sf, .src_set_wr = src_set_wr, .src_set_pm = src_set_pm, .src_set_rom = src_set_rom, .src_set_vo = src_set_vo, .src_set_st = src_set_st, .src_set_ie = src_set_ie, .src_set_ilsz = src_set_ilsz, .src_set_bp = src_set_bp, .src_set_cisz = src_set_cisz, .src_set_ca = src_set_ca, .src_set_sa = src_set_sa, .src_set_la = src_set_la, .src_set_pitch = src_set_pitch, .src_set_dirty = src_set_dirty, .src_set_clear_zbufs = src_set_clear_zbufs, .src_set_dirty_all = src_set_dirty_all, .src_commit_write = src_commit_write, .src_get_ca = src_get_ca, .src_get_dirty = src_get_dirty, .src_dirty_conj_mask = src_dirty_conj_mask, .src_mgr_enbs_src = src_mgr_enbs_src, .src_mgr_enb_src = src_mgr_enb_src, .src_mgr_dsb_src = src_mgr_dsb_src, .src_mgr_commit_write = src_mgr_commit_write, .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk, .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk, .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc, .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser, .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt, .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr, .srcimp_mgr_commit_write = srcimp_mgr_commit_write, .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk, .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk, .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk, .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk, .amixer_set_mode = amixer_set_mode, .amixer_set_iv = amixer_set_iv, .amixer_set_x = amixer_set_x, .amixer_set_y = amixer_set_y, .amixer_set_sadr = amixer_set_sadr, .amixer_set_se = amixer_set_se, .amixer_set_dirty = amixer_set_dirty, .amixer_set_dirty_all = amixer_set_dirty_all, .amixer_commit_write = amixer_commit_write, .amixer_get_y = amixer_get_y, .amixer_get_dirty = amixer_get_dirty, .dai_get_ctrl_blk = dai_get_ctrl_blk, .dai_put_ctrl_blk = dai_put_ctrl_blk, .dai_srt_set_srco = dai_srt_set_srco, .dai_srt_set_srcm = dai_srt_set_srcm, .dai_srt_set_rsr = dai_srt_set_rsr, .dai_srt_set_drat = dai_srt_set_drat, .dai_srt_set_ec = dai_srt_set_ec, .dai_srt_set_et = dai_srt_set_et, .dai_commit_write = dai_commit_write, .dao_get_ctrl_blk = dao_get_ctrl_blk, .dao_put_ctrl_blk = dao_put_ctrl_blk, .dao_set_spos = dao_set_spos, .dao_commit_write = dao_commit_write, .dao_get_spos = dao_get_spos, .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk, .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk, .daio_mgr_enb_dai = daio_mgr_enb_dai, .daio_mgr_dsb_dai = daio_mgr_dsb_dai, .daio_mgr_enb_dao = daio_mgr_enb_dao, .daio_mgr_dsb_dao = daio_mgr_dsb_dao, .daio_mgr_dao_init = daio_mgr_dao_init, .daio_mgr_set_imaparc = daio_mgr_set_imaparc, .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt, .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr, .daio_mgr_commit_write = daio_mgr_commit_write, .set_timer_irq = set_timer_irq, .set_timer_tick = set_timer_tick, .get_wc = get_wc, }; int create_20k2_hw_obj(struct hw **rhw) { struct hw20k2 *hw20k2; *rhw = NULL; hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL); if (!hw20k2) return -ENOMEM; hw20k2->hw = ct20k2_preset; *rhw = &hw20k2->hw; return 0; } int destroy_20k2_hw_obj(struct hw *hw) { if (hw->io_base) hw_card_shutdown(hw); kfree(hw); return 0; }
linux-master
sound/pci/ctxfi/cthw20k2.c
// SPDX-License-Identifier: GPL-2.0-only /* * xfi linux driver. * * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. */ #include <linux/init.h> #include <linux/pci.h> #include <linux/moduleparam.h> #include <linux/pci_ids.h> #include <linux/module.h> #include <sound/core.h> #include <sound/initval.h> #include "ctatc.h" #include "cthardware.h" MODULE_AUTHOR("Creative Technology Ltd"); MODULE_DESCRIPTION("X-Fi driver version 1.03"); MODULE_LICENSE("GPL v2"); static unsigned int reference_rate = 48000; static unsigned int multiple = 2; MODULE_PARM_DESC(reference_rate, "Reference rate (default=48000)"); module_param(reference_rate, uint, 0444); MODULE_PARM_DESC(multiple, "Rate multiplier (default=2)"); module_param(multiple, uint, 0444); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; static unsigned int subsystem[SNDRV_CARDS]; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Creative X-Fi driver"); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Creative X-Fi driver"); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Creative X-Fi driver"); module_param_array(subsystem, int, NULL, 0444); MODULE_PARM_DESC(subsystem, "Override subsystem ID for Creative X-Fi driver"); static const struct pci_device_id ct_pci_dev_ids[] = { /* only X-Fi is supported, so... */ { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K1), .driver_data = ATC20K1, }, { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2), .driver_data = ATC20K2, }, { 0, } }; MODULE_DEVICE_TABLE(pci, ct_pci_dev_ids); static int ct_card_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct ct_atc *atc; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 0, &card); if (err) return err; if ((reference_rate != 48000) && (reference_rate != 44100)) { dev_err(card->dev, "Invalid reference_rate value %u!!!\n", reference_rate); dev_err(card->dev, "The valid values for reference_rate are 48000 and 44100, Value 48000 is assumed.\n"); reference_rate = 48000; } if ((multiple != 1) && (multiple != 2) && (multiple != 4)) { dev_err(card->dev, "Invalid multiple value %u!!!\n", multiple); dev_err(card->dev, "The valid values for multiple are 1, 2 and 4, Value 2 is assumed.\n"); multiple = 2; } err = ct_atc_create(card, pci, reference_rate, multiple, pci_id->driver_data, subsystem[dev], &atc); if (err < 0) goto error; card->private_data = atc; /* Create alsa devices supported by this card */ err = ct_atc_create_alsa_devs(atc); if (err < 0) goto error; strcpy(card->driver, "SB-XFi"); strcpy(card->shortname, "Creative X-Fi"); snprintf(card->longname, sizeof(card->longname), "%s %s %s", card->shortname, atc->chip_name, atc->model_name); err = snd_card_register(card); if (err < 0) goto error; pci_set_drvdata(pci, card); dev++; return 0; error: snd_card_free(card); return err; } static void ct_card_remove(struct pci_dev *pci) { snd_card_free(pci_get_drvdata(pci)); } #ifdef CONFIG_PM_SLEEP static int ct_card_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct ct_atc *atc = card->private_data; return atc->suspend(atc); } static int ct_card_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct ct_atc *atc = card->private_data; return atc->resume(atc); } static SIMPLE_DEV_PM_OPS(ct_card_pm, ct_card_suspend, ct_card_resume); #define CT_CARD_PM_OPS &ct_card_pm #else #define CT_CARD_PM_OPS NULL #endif static struct pci_driver ct_driver = { .name = KBUILD_MODNAME, .id_table = ct_pci_dev_ids, .probe = ct_card_probe, .remove = ct_card_remove, .driver = { .pm = CT_CARD_PM_OPS, }, }; module_pci_driver(ct_driver);
linux-master
sound/pci/ctxfi/xfi.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctsrc.c * * @Brief * This file contains the implementation of the Sample Rate Convertor * resource management object. * * @Author Liu Chun * @Date May 13 2008 */ #include "ctsrc.h" #include "cthardware.h" #include <linux/slab.h> #define SRC_RESOURCE_NUM 256 #define SRCIMP_RESOURCE_NUM 256 static unsigned int conj_mask; static int src_default_config_memrd(struct src *src); static int src_default_config_memwr(struct src *src); static int src_default_config_arcrw(struct src *src); static int (*src_default_config[3])(struct src *) = { [MEMRD] = src_default_config_memrd, [MEMWR] = src_default_config_memwr, [ARCRW] = src_default_config_arcrw }; static int src_set_state(struct src *src, unsigned int state) { struct hw *hw; hw = src->rsc.hw; hw->src_set_state(src->rsc.ctrl_blk, state); return 0; } static int src_set_bm(struct src *src, unsigned int bm) { struct hw *hw; hw = src->rsc.hw; hw->src_set_bm(src->rsc.ctrl_blk, bm); return 0; } static int src_set_sf(struct src *src, unsigned int sf) { struct hw *hw; hw = src->rsc.hw; hw->src_set_sf(src->rsc.ctrl_blk, sf); return 0; } static int src_set_pm(struct src *src, unsigned int pm) { struct hw *hw; hw = src->rsc.hw; hw->src_set_pm(src->rsc.ctrl_blk, pm); return 0; } static int src_set_rom(struct src *src, unsigned int rom) { struct hw *hw; hw = src->rsc.hw; hw->src_set_rom(src->rsc.ctrl_blk, rom); return 0; } static int src_set_vo(struct src *src, unsigned int vo) { struct hw *hw; hw = src->rsc.hw; hw->src_set_vo(src->rsc.ctrl_blk, vo); return 0; } static int src_set_st(struct src *src, unsigned int st) { struct hw *hw; hw = src->rsc.hw; hw->src_set_st(src->rsc.ctrl_blk, st); return 0; } static int src_set_bp(struct src *src, unsigned int bp) { struct hw *hw; hw = src->rsc.hw; hw->src_set_bp(src->rsc.ctrl_blk, bp); return 0; } static int src_set_cisz(struct src *src, unsigned int cisz) { struct hw *hw; hw = src->rsc.hw; hw->src_set_cisz(src->rsc.ctrl_blk, cisz); return 0; } static int src_set_ca(struct src *src, unsigned int ca) { struct hw *hw; hw = src->rsc.hw; hw->src_set_ca(src->rsc.ctrl_blk, ca); return 0; } static int src_set_sa(struct src *src, unsigned int sa) { struct hw *hw; hw = src->rsc.hw; hw->src_set_sa(src->rsc.ctrl_blk, sa); return 0; } static int src_set_la(struct src *src, unsigned int la) { struct hw *hw; hw = src->rsc.hw; hw->src_set_la(src->rsc.ctrl_blk, la); return 0; } static int src_set_pitch(struct src *src, unsigned int pitch) { struct hw *hw; hw = src->rsc.hw; hw->src_set_pitch(src->rsc.ctrl_blk, pitch); return 0; } static int src_set_clear_zbufs(struct src *src) { struct hw *hw; hw = src->rsc.hw; hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); return 0; } static int src_commit_write(struct src *src) { struct hw *hw; int i; unsigned int dirty = 0; hw = src->rsc.hw; src->rsc.ops->master(&src->rsc); if (src->rsc.msr > 1) { /* Save dirty flags for conjugate resource programming */ dirty = hw->src_get_dirty(src->rsc.ctrl_blk) & conj_mask; } hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); /* Program conjugate parameter mixer resources */ if (MEMWR == src->mode) return 0; for (i = 1; i < src->rsc.msr; i++) { src->rsc.ops->next_conj(&src->rsc); hw->src_set_dirty(src->rsc.ctrl_blk, dirty); hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); } src->rsc.ops->master(&src->rsc); return 0; } static int src_get_ca(struct src *src) { struct hw *hw; hw = src->rsc.hw; return hw->src_get_ca(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); } static int src_init(struct src *src) { src_default_config[src->mode](src); return 0; } static struct src *src_next_interleave(struct src *src) { return src->intlv; } static int src_default_config_memrd(struct src *src) { struct hw *hw = src->rsc.hw; unsigned int rsr, msr; hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); hw->src_set_bm(src->rsc.ctrl_blk, 1); for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1) rsr++; hw->src_set_rsr(src->rsc.ctrl_blk, rsr); hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16); hw->src_set_wr(src->rsc.ctrl_blk, 0); hw->src_set_pm(src->rsc.ctrl_blk, 0); hw->src_set_rom(src->rsc.ctrl_blk, 0); hw->src_set_vo(src->rsc.ctrl_blk, 0); hw->src_set_st(src->rsc.ctrl_blk, 0); hw->src_set_ilsz(src->rsc.ctrl_blk, src->multi - 1); hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); hw->src_set_sa(src->rsc.ctrl_blk, 0x0); hw->src_set_la(src->rsc.ctrl_blk, 0x1000); hw->src_set_ca(src->rsc.ctrl_blk, 0x80); hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src->rsc.ops->master(&src->rsc); hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); for (msr = 1; msr < src->rsc.msr; msr++) { src->rsc.ops->next_conj(&src->rsc); hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); } src->rsc.ops->master(&src->rsc); return 0; } static int src_default_config_memwr(struct src *src) { struct hw *hw = src->rsc.hw; hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); hw->src_set_bm(src->rsc.ctrl_blk, 1); hw->src_set_rsr(src->rsc.ctrl_blk, 0); hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16); hw->src_set_wr(src->rsc.ctrl_blk, 1); hw->src_set_pm(src->rsc.ctrl_blk, 0); hw->src_set_rom(src->rsc.ctrl_blk, 0); hw->src_set_vo(src->rsc.ctrl_blk, 0); hw->src_set_st(src->rsc.ctrl_blk, 0); hw->src_set_ilsz(src->rsc.ctrl_blk, 0); hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); hw->src_set_sa(src->rsc.ctrl_blk, 0x0); hw->src_set_la(src->rsc.ctrl_blk, 0x1000); hw->src_set_ca(src->rsc.ctrl_blk, 0x80); hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src->rsc.ops->master(&src->rsc); hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); return 0; } static int src_default_config_arcrw(struct src *src) { struct hw *hw = src->rsc.hw; unsigned int rsr, msr; unsigned int dirty; hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); hw->src_set_bm(src->rsc.ctrl_blk, 0); for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1) rsr++; hw->src_set_rsr(src->rsc.ctrl_blk, rsr); hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_F32); hw->src_set_wr(src->rsc.ctrl_blk, 0); hw->src_set_pm(src->rsc.ctrl_blk, 0); hw->src_set_rom(src->rsc.ctrl_blk, 0); hw->src_set_vo(src->rsc.ctrl_blk, 0); hw->src_set_st(src->rsc.ctrl_blk, 0); hw->src_set_ilsz(src->rsc.ctrl_blk, 0); hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); hw->src_set_sa(src->rsc.ctrl_blk, 0x0); /*hw->src_set_sa(src->rsc.ctrl_blk, 0x100);*/ hw->src_set_la(src->rsc.ctrl_blk, 0x1000); /*hw->src_set_la(src->rsc.ctrl_blk, 0x03ffffe0);*/ hw->src_set_ca(src->rsc.ctrl_blk, 0x80); hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); dirty = hw->src_get_dirty(src->rsc.ctrl_blk); src->rsc.ops->master(&src->rsc); for (msr = 0; msr < src->rsc.msr; msr++) { hw->src_set_dirty(src->rsc.ctrl_blk, dirty); hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src->rsc.ctrl_blk); src->rsc.ops->next_conj(&src->rsc); } src->rsc.ops->master(&src->rsc); return 0; } static const struct src_rsc_ops src_rsc_ops = { .set_state = src_set_state, .set_bm = src_set_bm, .set_sf = src_set_sf, .set_pm = src_set_pm, .set_rom = src_set_rom, .set_vo = src_set_vo, .set_st = src_set_st, .set_bp = src_set_bp, .set_cisz = src_set_cisz, .set_ca = src_set_ca, .set_sa = src_set_sa, .set_la = src_set_la, .set_pitch = src_set_pitch, .set_clr_zbufs = src_set_clear_zbufs, .commit_write = src_commit_write, .get_ca = src_get_ca, .init = src_init, .next_interleave = src_next_interleave, }; static int src_rsc_init(struct src *src, u32 idx, const struct src_desc *desc, struct src_mgr *mgr) { int err; int i, n; struct src *p; n = (MEMRD == desc->mode) ? desc->multi : 1; for (i = 0, p = src; i < n; i++, p++) { err = rsc_init(&p->rsc, idx + i, SRC, desc->msr, mgr->mgr.hw); if (err) goto error1; /* Initialize src specific rsc operations */ p->ops = &src_rsc_ops; p->multi = (0 == i) ? desc->multi : 1; p->mode = desc->mode; src_default_config[desc->mode](p); mgr->src_enable(mgr, p); p->intlv = p + 1; } (--p)->intlv = NULL; /* Set @intlv of the last SRC to NULL */ mgr->commit_write(mgr); return 0; error1: for (i--, p--; i >= 0; i--, p--) { mgr->src_disable(mgr, p); rsc_uninit(&p->rsc); } mgr->commit_write(mgr); return err; } static int src_rsc_uninit(struct src *src, struct src_mgr *mgr) { int i, n; struct src *p; n = (MEMRD == src->mode) ? src->multi : 1; for (i = 0, p = src; i < n; i++, p++) { mgr->src_disable(mgr, p); rsc_uninit(&p->rsc); p->multi = 0; p->ops = NULL; p->mode = NUM_SRCMODES; p->intlv = NULL; } mgr->commit_write(mgr); return 0; } static int get_src_rsc(struct src_mgr *mgr, const struct src_desc *desc, struct src **rsrc) { unsigned int idx = SRC_RESOURCE_NUM; int err; struct src *src; unsigned long flags; *rsrc = NULL; /* Check whether there are sufficient src resources to meet request. */ spin_lock_irqsave(&mgr->mgr_lock, flags); if (MEMRD == desc->mode) err = mgr_get_resource(&mgr->mgr, desc->multi, &idx); else err = mgr_get_resource(&mgr->mgr, 1, &idx); spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { dev_err(mgr->card->dev, "Can't meet SRC resource request!\n"); return err; } /* Allocate mem for master src resource */ if (MEMRD == desc->mode) src = kcalloc(desc->multi, sizeof(*src), GFP_KERNEL); else src = kzalloc(sizeof(*src), GFP_KERNEL); if (!src) { err = -ENOMEM; goto error1; } err = src_rsc_init(src, idx, desc, mgr); if (err) goto error2; *rsrc = src; return 0; error2: kfree(src); error1: spin_lock_irqsave(&mgr->mgr_lock, flags); if (MEMRD == desc->mode) mgr_put_resource(&mgr->mgr, desc->multi, idx); else mgr_put_resource(&mgr->mgr, 1, idx); spin_unlock_irqrestore(&mgr->mgr_lock, flags); return err; } static int put_src_rsc(struct src_mgr *mgr, struct src *src) { unsigned long flags; spin_lock_irqsave(&mgr->mgr_lock, flags); src->rsc.ops->master(&src->rsc); if (MEMRD == src->mode) mgr_put_resource(&mgr->mgr, src->multi, src->rsc.ops->index(&src->rsc)); else mgr_put_resource(&mgr->mgr, 1, src->rsc.ops->index(&src->rsc)); spin_unlock_irqrestore(&mgr->mgr_lock, flags); src_rsc_uninit(src, mgr); kfree(src); return 0; } static int src_enable_s(struct src_mgr *mgr, struct src *src) { struct hw *hw = mgr->mgr.hw; int i; src->rsc.ops->master(&src->rsc); for (i = 0; i < src->rsc.msr; i++) { hw->src_mgr_enbs_src(mgr->mgr.ctrl_blk, src->rsc.ops->index(&src->rsc)); src->rsc.ops->next_conj(&src->rsc); } src->rsc.ops->master(&src->rsc); return 0; } static int src_enable(struct src_mgr *mgr, struct src *src) { struct hw *hw = mgr->mgr.hw; int i; src->rsc.ops->master(&src->rsc); for (i = 0; i < src->rsc.msr; i++) { hw->src_mgr_enb_src(mgr->mgr.ctrl_blk, src->rsc.ops->index(&src->rsc)); src->rsc.ops->next_conj(&src->rsc); } src->rsc.ops->master(&src->rsc); return 0; } static int src_disable(struct src_mgr *mgr, struct src *src) { struct hw *hw = mgr->mgr.hw; int i; src->rsc.ops->master(&src->rsc); for (i = 0; i < src->rsc.msr; i++) { hw->src_mgr_dsb_src(mgr->mgr.ctrl_blk, src->rsc.ops->index(&src->rsc)); src->rsc.ops->next_conj(&src->rsc); } src->rsc.ops->master(&src->rsc); return 0; } static int src_mgr_commit_write(struct src_mgr *mgr) { struct hw *hw = mgr->mgr.hw; hw->src_mgr_commit_write(hw, mgr->mgr.ctrl_blk); return 0; } int src_mgr_create(struct hw *hw, struct src_mgr **rsrc_mgr) { int err, i; struct src_mgr *src_mgr; *rsrc_mgr = NULL; src_mgr = kzalloc(sizeof(*src_mgr), GFP_KERNEL); if (!src_mgr) return -ENOMEM; err = rsc_mgr_init(&src_mgr->mgr, SRC, SRC_RESOURCE_NUM, hw); if (err) goto error1; spin_lock_init(&src_mgr->mgr_lock); conj_mask = hw->src_dirty_conj_mask(); src_mgr->get_src = get_src_rsc; src_mgr->put_src = put_src_rsc; src_mgr->src_enable_s = src_enable_s; src_mgr->src_enable = src_enable; src_mgr->src_disable = src_disable; src_mgr->commit_write = src_mgr_commit_write; src_mgr->card = hw->card; /* Disable all SRC resources. */ for (i = 0; i < 256; i++) hw->src_mgr_dsb_src(src_mgr->mgr.ctrl_blk, i); hw->src_mgr_commit_write(hw, src_mgr->mgr.ctrl_blk); *rsrc_mgr = src_mgr; return 0; error1: kfree(src_mgr); return err; } int src_mgr_destroy(struct src_mgr *src_mgr) { rsc_mgr_uninit(&src_mgr->mgr); kfree(src_mgr); return 0; } /* SRCIMP resource manager operations */ static void srcimp_master(struct rsc *rsc) { rsc->conj = 0; rsc->idx = container_of(rsc, struct srcimp, rsc)->idx[0]; } static void srcimp_next_conj(struct rsc *rsc) { rsc->conj++; } static int srcimp_index(const struct rsc *rsc) { return container_of(rsc, struct srcimp, rsc)->idx[rsc->conj]; } static const struct rsc_ops srcimp_basic_rsc_ops = { .master = srcimp_master, .next_conj = srcimp_next_conj, .index = srcimp_index, .output_slot = NULL, }; static int srcimp_map(struct srcimp *srcimp, struct src *src, struct rsc *input) { struct imapper *entry; int i; srcimp->rsc.ops->master(&srcimp->rsc); src->rsc.ops->master(&src->rsc); input->ops->master(input); /* Program master and conjugate resources */ for (i = 0; i < srcimp->rsc.msr; i++) { entry = &srcimp->imappers[i]; entry->slot = input->ops->output_slot(input); entry->user = src->rsc.ops->index(&src->rsc); entry->addr = srcimp->rsc.ops->index(&srcimp->rsc); srcimp->mgr->imap_add(srcimp->mgr, entry); srcimp->mapped |= (0x1 << i); srcimp->rsc.ops->next_conj(&srcimp->rsc); input->ops->next_conj(input); } srcimp->rsc.ops->master(&srcimp->rsc); input->ops->master(input); return 0; } static int srcimp_unmap(struct srcimp *srcimp) { int i; /* Program master and conjugate resources */ for (i = 0; i < srcimp->rsc.msr; i++) { if (srcimp->mapped & (0x1 << i)) { srcimp->mgr->imap_delete(srcimp->mgr, &srcimp->imappers[i]); srcimp->mapped &= ~(0x1 << i); } } return 0; } static const struct srcimp_rsc_ops srcimp_ops = { .map = srcimp_map, .unmap = srcimp_unmap }; static int srcimp_rsc_init(struct srcimp *srcimp, const struct srcimp_desc *desc, struct srcimp_mgr *mgr) { int err; err = rsc_init(&srcimp->rsc, srcimp->idx[0], SRCIMP, desc->msr, mgr->mgr.hw); if (err) return err; /* Reserve memory for imapper nodes */ srcimp->imappers = kcalloc(desc->msr, sizeof(struct imapper), GFP_KERNEL); if (!srcimp->imappers) { err = -ENOMEM; goto error1; } /* Set srcimp specific operations */ srcimp->rsc.ops = &srcimp_basic_rsc_ops; srcimp->ops = &srcimp_ops; srcimp->mgr = mgr; srcimp->rsc.ops->master(&srcimp->rsc); return 0; error1: rsc_uninit(&srcimp->rsc); return err; } static int srcimp_rsc_uninit(struct srcimp *srcimp) { kfree(srcimp->imappers); srcimp->imappers = NULL; srcimp->ops = NULL; srcimp->mgr = NULL; rsc_uninit(&srcimp->rsc); return 0; } static int get_srcimp_rsc(struct srcimp_mgr *mgr, const struct srcimp_desc *desc, struct srcimp **rsrcimp) { int err, i; unsigned int idx; struct srcimp *srcimp; unsigned long flags; *rsrcimp = NULL; /* Allocate mem for SRCIMP resource */ srcimp = kzalloc(sizeof(*srcimp), GFP_KERNEL); if (!srcimp) return -ENOMEM; /* Check whether there are sufficient SRCIMP resources. */ err = 0; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < desc->msr; i++) { err = mgr_get_resource(&mgr->mgr, 1, &idx); if (err) break; srcimp->idx[i] = idx; } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { dev_err(mgr->card->dev, "Can't meet SRCIMP resource request!\n"); goto error1; } err = srcimp_rsc_init(srcimp, desc, mgr); if (err) goto error1; *rsrcimp = srcimp; return 0; error1: spin_lock_irqsave(&mgr->mgr_lock, flags); for (i--; i >= 0; i--) mgr_put_resource(&mgr->mgr, 1, srcimp->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); kfree(srcimp); return err; } static int put_srcimp_rsc(struct srcimp_mgr *mgr, struct srcimp *srcimp) { unsigned long flags; int i; spin_lock_irqsave(&mgr->mgr_lock, flags); for (i = 0; i < srcimp->rsc.msr; i++) mgr_put_resource(&mgr->mgr, 1, srcimp->idx[i]); spin_unlock_irqrestore(&mgr->mgr_lock, flags); srcimp_rsc_uninit(srcimp); kfree(srcimp); return 0; } static int srcimp_map_op(void *data, struct imapper *entry) { struct rsc_mgr *mgr = &((struct srcimp_mgr *)data)->mgr; struct hw *hw = mgr->hw; hw->srcimp_mgr_set_imaparc(mgr->ctrl_blk, entry->slot); hw->srcimp_mgr_set_imapuser(mgr->ctrl_blk, entry->user); hw->srcimp_mgr_set_imapnxt(mgr->ctrl_blk, entry->next); hw->srcimp_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr); hw->srcimp_mgr_commit_write(mgr->hw, mgr->ctrl_blk); return 0; } static int srcimp_imap_add(struct srcimp_mgr *mgr, struct imapper *entry) { unsigned long flags; int err; spin_lock_irqsave(&mgr->imap_lock, flags); if ((0 == entry->addr) && (mgr->init_imap_added)) { input_mapper_delete(&mgr->imappers, mgr->init_imap, srcimp_map_op, mgr); mgr->init_imap_added = 0; } err = input_mapper_add(&mgr->imappers, entry, srcimp_map_op, mgr); spin_unlock_irqrestore(&mgr->imap_lock, flags); return err; } static int srcimp_imap_delete(struct srcimp_mgr *mgr, struct imapper *entry) { unsigned long flags; int err; spin_lock_irqsave(&mgr->imap_lock, flags); err = input_mapper_delete(&mgr->imappers, entry, srcimp_map_op, mgr); if (list_empty(&mgr->imappers)) { input_mapper_add(&mgr->imappers, mgr->init_imap, srcimp_map_op, mgr); mgr->init_imap_added = 1; } spin_unlock_irqrestore(&mgr->imap_lock, flags); return err; } int srcimp_mgr_create(struct hw *hw, struct srcimp_mgr **rsrcimp_mgr) { int err; struct srcimp_mgr *srcimp_mgr; struct imapper *entry; *rsrcimp_mgr = NULL; srcimp_mgr = kzalloc(sizeof(*srcimp_mgr), GFP_KERNEL); if (!srcimp_mgr) return -ENOMEM; err = rsc_mgr_init(&srcimp_mgr->mgr, SRCIMP, SRCIMP_RESOURCE_NUM, hw); if (err) goto error1; spin_lock_init(&srcimp_mgr->mgr_lock); spin_lock_init(&srcimp_mgr->imap_lock); INIT_LIST_HEAD(&srcimp_mgr->imappers); entry = kzalloc(sizeof(*entry), GFP_KERNEL); if (!entry) { err = -ENOMEM; goto error2; } entry->slot = entry->addr = entry->next = entry->user = 0; list_add(&entry->list, &srcimp_mgr->imappers); srcimp_mgr->init_imap = entry; srcimp_mgr->init_imap_added = 1; srcimp_mgr->get_srcimp = get_srcimp_rsc; srcimp_mgr->put_srcimp = put_srcimp_rsc; srcimp_mgr->imap_add = srcimp_imap_add; srcimp_mgr->imap_delete = srcimp_imap_delete; srcimp_mgr->card = hw->card; *rsrcimp_mgr = srcimp_mgr; return 0; error2: rsc_mgr_uninit(&srcimp_mgr->mgr); error1: kfree(srcimp_mgr); return err; } int srcimp_mgr_destroy(struct srcimp_mgr *srcimp_mgr) { unsigned long flags; /* free src input mapper list */ spin_lock_irqsave(&srcimp_mgr->imap_lock, flags); free_input_mapper_list(&srcimp_mgr->imappers); spin_unlock_irqrestore(&srcimp_mgr->imap_lock, flags); rsc_mgr_uninit(&srcimp_mgr->mgr); kfree(srcimp_mgr); return 0; }
linux-master
sound/pci/ctxfi/ctsrc.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctmixer.c * * @Brief * This file contains the implementation of alsa mixer device functions. * * @Author Liu Chun * @Date May 28 2008 */ #include "ctmixer.h" #include "ctamixer.h" #include <linux/slab.h> #include <sound/core.h> #include <sound/control.h> #include <sound/asoundef.h> #include <sound/pcm.h> #include <sound/tlv.h> enum CT_SUM_CTL { SUM_IN_F, SUM_IN_R, SUM_IN_C, SUM_IN_S, SUM_IN_F_C, NUM_CT_SUMS }; enum CT_AMIXER_CTL { /* volume control mixers */ AMIXER_MASTER_F, AMIXER_MASTER_R, AMIXER_MASTER_C, AMIXER_MASTER_S, AMIXER_PCM_F, AMIXER_PCM_R, AMIXER_PCM_C, AMIXER_PCM_S, AMIXER_SPDIFI, AMIXER_LINEIN, AMIXER_MIC, AMIXER_SPDIFO, AMIXER_WAVE_F, AMIXER_WAVE_R, AMIXER_WAVE_C, AMIXER_WAVE_S, AMIXER_MASTER_F_C, AMIXER_PCM_F_C, AMIXER_SPDIFI_C, AMIXER_LINEIN_C, AMIXER_MIC_C, /* this should always be the last one */ NUM_CT_AMIXERS }; enum CTALSA_MIXER_CTL { /* volume control mixers */ MIXER_MASTER_P, MIXER_PCM_P, MIXER_LINEIN_P, MIXER_MIC_P, MIXER_SPDIFI_P, MIXER_SPDIFO_P, MIXER_WAVEF_P, MIXER_WAVER_P, MIXER_WAVEC_P, MIXER_WAVES_P, MIXER_MASTER_C, MIXER_PCM_C, MIXER_LINEIN_C, MIXER_MIC_C, MIXER_SPDIFI_C, /* switch control mixers */ MIXER_PCM_C_S, MIXER_LINEIN_C_S, MIXER_MIC_C_S, MIXER_SPDIFI_C_S, MIXER_SPDIFO_P_S, MIXER_WAVEF_P_S, MIXER_WAVER_P_S, MIXER_WAVEC_P_S, MIXER_WAVES_P_S, MIXER_DIGITAL_IO_S, MIXER_IEC958_MASK, MIXER_IEC958_DEFAULT, MIXER_IEC958_STREAM, /* this should always be the last one */ NUM_CTALSA_MIXERS }; #define VOL_MIXER_START MIXER_MASTER_P #define VOL_MIXER_END MIXER_SPDIFI_C #define VOL_MIXER_NUM (VOL_MIXER_END - VOL_MIXER_START + 1) #define SWH_MIXER_START MIXER_PCM_C_S #define SWH_MIXER_END MIXER_DIGITAL_IO_S #define SWH_CAPTURE_START MIXER_PCM_C_S #define SWH_CAPTURE_END MIXER_SPDIFI_C_S #define CHN_NUM 2 struct ct_kcontrol_init { unsigned char ctl; char *name; }; static struct ct_kcontrol_init ct_kcontrol_init_table[NUM_CTALSA_MIXERS] = { [MIXER_MASTER_P] = { .ctl = 1, .name = "Master Playback Volume", }, [MIXER_MASTER_C] = { .ctl = 1, .name = "Master Capture Volume", }, [MIXER_PCM_P] = { .ctl = 1, .name = "PCM Playback Volume", }, [MIXER_PCM_C] = { .ctl = 1, .name = "PCM Capture Volume", }, [MIXER_LINEIN_P] = { .ctl = 1, .name = "Line Playback Volume", }, [MIXER_LINEIN_C] = { .ctl = 1, .name = "Line Capture Volume", }, [MIXER_MIC_P] = { .ctl = 1, .name = "Mic Playback Volume", }, [MIXER_MIC_C] = { .ctl = 1, .name = "Mic Capture Volume", }, [MIXER_SPDIFI_P] = { .ctl = 1, .name = "IEC958 Playback Volume", }, [MIXER_SPDIFI_C] = { .ctl = 1, .name = "IEC958 Capture Volume", }, [MIXER_SPDIFO_P] = { .ctl = 1, .name = "Digital Playback Volume", }, [MIXER_WAVEF_P] = { .ctl = 1, .name = "Front Playback Volume", }, [MIXER_WAVES_P] = { .ctl = 1, .name = "Side Playback Volume", }, [MIXER_WAVEC_P] = { .ctl = 1, .name = "Center/LFE Playback Volume", }, [MIXER_WAVER_P] = { .ctl = 1, .name = "Surround Playback Volume", }, [MIXER_PCM_C_S] = { .ctl = 1, .name = "PCM Capture Switch", }, [MIXER_LINEIN_C_S] = { .ctl = 1, .name = "Line Capture Switch", }, [MIXER_MIC_C_S] = { .ctl = 1, .name = "Mic Capture Switch", }, [MIXER_SPDIFI_C_S] = { .ctl = 1, .name = "IEC958 Capture Switch", }, [MIXER_SPDIFO_P_S] = { .ctl = 1, .name = "Digital Playback Switch", }, [MIXER_WAVEF_P_S] = { .ctl = 1, .name = "Front Playback Switch", }, [MIXER_WAVES_P_S] = { .ctl = 1, .name = "Side Playback Switch", }, [MIXER_WAVEC_P_S] = { .ctl = 1, .name = "Center/LFE Playback Switch", }, [MIXER_WAVER_P_S] = { .ctl = 1, .name = "Surround Playback Switch", }, [MIXER_DIGITAL_IO_S] = { .ctl = 0, .name = "Digit-IO Playback Switch", }, }; static void ct_mixer_recording_select(struct ct_mixer *mixer, enum CT_AMIXER_CTL type); static void ct_mixer_recording_unselect(struct ct_mixer *mixer, enum CT_AMIXER_CTL type); /* FIXME: this static looks like it would fail if more than one card was */ /* installed. */ static struct snd_kcontrol *kctls[2] = {NULL}; static enum CT_AMIXER_CTL get_amixer_index(enum CTALSA_MIXER_CTL alsa_index) { switch (alsa_index) { case MIXER_MASTER_P: return AMIXER_MASTER_F; case MIXER_MASTER_C: return AMIXER_MASTER_F_C; case MIXER_PCM_P: return AMIXER_PCM_F; case MIXER_PCM_C: case MIXER_PCM_C_S: return AMIXER_PCM_F_C; case MIXER_LINEIN_P: return AMIXER_LINEIN; case MIXER_LINEIN_C: case MIXER_LINEIN_C_S: return AMIXER_LINEIN_C; case MIXER_MIC_P: return AMIXER_MIC; case MIXER_MIC_C: case MIXER_MIC_C_S: return AMIXER_MIC_C; case MIXER_SPDIFI_P: return AMIXER_SPDIFI; case MIXER_SPDIFI_C: case MIXER_SPDIFI_C_S: return AMIXER_SPDIFI_C; case MIXER_SPDIFO_P: return AMIXER_SPDIFO; case MIXER_WAVEF_P: return AMIXER_WAVE_F; case MIXER_WAVES_P: return AMIXER_WAVE_S; case MIXER_WAVEC_P: return AMIXER_WAVE_C; case MIXER_WAVER_P: return AMIXER_WAVE_R; default: return NUM_CT_AMIXERS; } } static enum CT_AMIXER_CTL get_recording_amixer(enum CT_AMIXER_CTL index) { switch (index) { case AMIXER_MASTER_F: return AMIXER_MASTER_F_C; case AMIXER_PCM_F: return AMIXER_PCM_F_C; case AMIXER_SPDIFI: return AMIXER_SPDIFI_C; case AMIXER_LINEIN: return AMIXER_LINEIN_C; case AMIXER_MIC: return AMIXER_MIC_C; default: return NUM_CT_AMIXERS; } } static unsigned char get_switch_state(struct ct_mixer *mixer, enum CTALSA_MIXER_CTL type) { return (mixer->switch_state & (0x1 << (type - SWH_MIXER_START))) ? 1 : 0; } static void set_switch_state(struct ct_mixer *mixer, enum CTALSA_MIXER_CTL type, unsigned char state) { if (state) mixer->switch_state |= (0x1 << (type - SWH_MIXER_START)); else mixer->switch_state &= ~(0x1 << (type - SWH_MIXER_START)); } #if 0 /* not used */ /* Map integer value ranging from 0 to 65535 to 14-bit float value ranging * from 2^-6 to (1+1023/1024) */ static unsigned int uint16_to_float14(unsigned int x) { unsigned int i; if (x < 17) return 0; x *= 2031; x /= 65535; x += 16; /* i <= 6 */ for (i = 0; !(x & 0x400); i++) x <<= 1; x = (((7 - i) & 0x7) << 10) | (x & 0x3ff); return x; } static unsigned int float14_to_uint16(unsigned int x) { unsigned int e; if (!x) return x; e = (x >> 10) & 0x7; x &= 0x3ff; x += 1024; x >>= (7 - e); x -= 16; x *= 65535; x /= 2031; return x; } #endif /* not used */ #define VOL_SCALE 0x1c #define VOL_MAX 0x100 static const DECLARE_TLV_DB_SCALE(ct_vol_db_scale, -6400, 25, 1); static int ct_alsa_mix_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = VOL_MAX; return 0; } static int ct_alsa_mix_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); enum CT_AMIXER_CTL type = get_amixer_index(kcontrol->private_value); struct amixer *amixer; int i, val; for (i = 0; i < 2; i++) { amixer = ((struct ct_mixer *)atc->mixer)-> amixers[type*CHN_NUM+i]; val = amixer->ops->get_scale(amixer) / VOL_SCALE; if (val < 0) val = 0; else if (val > VOL_MAX) val = VOL_MAX; ucontrol->value.integer.value[i] = val; } return 0; } static int ct_alsa_mix_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); struct ct_mixer *mixer = atc->mixer; enum CT_AMIXER_CTL type = get_amixer_index(kcontrol->private_value); struct amixer *amixer; int i, j, val, oval, change = 0; for (i = 0; i < 2; i++) { val = ucontrol->value.integer.value[i]; if (val < 0) val = 0; else if (val > VOL_MAX) val = VOL_MAX; val *= VOL_SCALE; amixer = mixer->amixers[type*CHN_NUM+i]; oval = amixer->ops->get_scale(amixer); if (val != oval) { amixer->ops->set_scale(amixer, val); amixer->ops->commit_write(amixer); change = 1; /* Synchronize Master/PCM playback AMIXERs. */ if (AMIXER_MASTER_F == type || AMIXER_PCM_F == type) { for (j = 1; j < 4; j++) { amixer = mixer-> amixers[(type+j)*CHN_NUM+i]; amixer->ops->set_scale(amixer, val); amixer->ops->commit_write(amixer); } } } } return change; } static struct snd_kcontrol_new vol_ctl = { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = ct_alsa_mix_volume_info, .get = ct_alsa_mix_volume_get, .put = ct_alsa_mix_volume_put, .tlv = { .p = ct_vol_db_scale }, }; static int output_switch_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info) { static const char *const names[3] = { "FP Headphones", "Headphones", "Speakers" }; return snd_ctl_enum_info(info, 1, 3, names); } static int output_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = atc->output_switch_get(atc); return 0; } static int output_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); if (ucontrol->value.enumerated.item[0] > 2) return -EINVAL; return atc->output_switch_put(atc, ucontrol->value.enumerated.item[0]); } static struct snd_kcontrol_new output_ctl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Output Playback Enum", .info = output_switch_info, .get = output_switch_get, .put = output_switch_put, }; static int mic_source_switch_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info) { static const char *const names[3] = { "Mic", "FP Mic", "Aux" }; return snd_ctl_enum_info(info, 1, 3, names); } static int mic_source_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = atc->mic_source_switch_get(atc); return 0; } static int mic_source_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); if (ucontrol->value.enumerated.item[0] > 2) return -EINVAL; return atc->mic_source_switch_put(atc, ucontrol->value.enumerated.item[0]); } static struct snd_kcontrol_new mic_source_ctl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Mic Source Capture Enum", .info = mic_source_switch_info, .get = mic_source_switch_get, .put = mic_source_switch_put, }; static void do_line_mic_switch(struct ct_atc *atc, enum CTALSA_MIXER_CTL type) { if (MIXER_LINEIN_C_S == type) { atc->select_line_in(atc); set_switch_state(atc->mixer, MIXER_MIC_C_S, 0); snd_ctl_notify(atc->card, SNDRV_CTL_EVENT_MASK_VALUE, &kctls[1]->id); } else if (MIXER_MIC_C_S == type) { atc->select_mic_in(atc); set_switch_state(atc->mixer, MIXER_LINEIN_C_S, 0); snd_ctl_notify(atc->card, SNDRV_CTL_EVENT_MASK_VALUE, &kctls[0]->id); } } static void do_digit_io_switch(struct ct_atc *atc, int state) { struct ct_mixer *mixer = atc->mixer; if (state) { atc->select_digit_io(atc); atc->spdif_out_unmute(atc, get_switch_state(mixer, MIXER_SPDIFO_P_S)); atc->spdif_in_unmute(atc, 1); atc->line_in_unmute(atc, 0); return; } if (get_switch_state(mixer, MIXER_LINEIN_C_S)) atc->select_line_in(atc); else if (get_switch_state(mixer, MIXER_MIC_C_S)) atc->select_mic_in(atc); atc->spdif_out_unmute(atc, 0); atc->spdif_in_unmute(atc, 0); atc->line_in_unmute(atc, 1); return; } static void do_switch(struct ct_atc *atc, enum CTALSA_MIXER_CTL type, int state) { struct ct_mixer *mixer = atc->mixer; struct capabilities cap = atc->capabilities(atc); /* Do changes in mixer. */ if ((SWH_CAPTURE_START <= type) && (SWH_CAPTURE_END >= type)) { if (state) { ct_mixer_recording_select(mixer, get_amixer_index(type)); } else { ct_mixer_recording_unselect(mixer, get_amixer_index(type)); } } /* Do changes out of mixer. */ if (!cap.dedicated_mic && (MIXER_LINEIN_C_S == type || MIXER_MIC_C_S == type)) { if (state) do_line_mic_switch(atc, type); atc->line_in_unmute(atc, state); } else if (cap.dedicated_mic && (MIXER_LINEIN_C_S == type)) atc->line_in_unmute(atc, state); else if (cap.dedicated_mic && (MIXER_MIC_C_S == type)) atc->mic_unmute(atc, state); else if (MIXER_SPDIFI_C_S == type) atc->spdif_in_unmute(atc, state); else if (MIXER_WAVEF_P_S == type) atc->line_front_unmute(atc, state); else if (MIXER_WAVES_P_S == type) atc->line_surround_unmute(atc, state); else if (MIXER_WAVEC_P_S == type) atc->line_clfe_unmute(atc, state); else if (MIXER_WAVER_P_S == type) atc->line_rear_unmute(atc, state); else if (MIXER_SPDIFO_P_S == type) atc->spdif_out_unmute(atc, state); else if (MIXER_DIGITAL_IO_S == type) do_digit_io_switch(atc, state); return; } static int ct_alsa_mix_switch_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 1; uinfo->value.integer.step = 1; return 0; } static int ct_alsa_mix_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_mixer *mixer = ((struct ct_atc *)snd_kcontrol_chip(kcontrol))->mixer; enum CTALSA_MIXER_CTL type = kcontrol->private_value; ucontrol->value.integer.value[0] = get_switch_state(mixer, type); return 0; } static int ct_alsa_mix_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); struct ct_mixer *mixer = atc->mixer; enum CTALSA_MIXER_CTL type = kcontrol->private_value; int state; state = ucontrol->value.integer.value[0]; if (get_switch_state(mixer, type) == state) return 0; set_switch_state(mixer, type, state); do_switch(atc, type, state); return 1; } static struct snd_kcontrol_new swh_ctl = { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = ct_alsa_mix_switch_info, .get = ct_alsa_mix_switch_get, .put = ct_alsa_mix_switch_put }; static int ct_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int ct_spdif_get_mask(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = 0xff; ucontrol->value.iec958.status[1] = 0xff; ucontrol->value.iec958.status[2] = 0xff; ucontrol->value.iec958.status[3] = 0xff; return 0; } static int ct_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); unsigned int status; atc->spdif_out_get_status(atc, &status); if (status == 0) status = SNDRV_PCM_DEFAULT_CON_SPDIF; ucontrol->value.iec958.status[0] = (status >> 0) & 0xff; ucontrol->value.iec958.status[1] = (status >> 8) & 0xff; ucontrol->value.iec958.status[2] = (status >> 16) & 0xff; ucontrol->value.iec958.status[3] = (status >> 24) & 0xff; return 0; } static int ct_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct ct_atc *atc = snd_kcontrol_chip(kcontrol); int change; unsigned int status, old_status; status = (ucontrol->value.iec958.status[0] << 0) | (ucontrol->value.iec958.status[1] << 8) | (ucontrol->value.iec958.status[2] << 16) | (ucontrol->value.iec958.status[3] << 24); atc->spdif_out_get_status(atc, &old_status); change = (old_status != status); if (change) atc->spdif_out_set_status(atc, status); return change; } static struct snd_kcontrol_new iec958_mask_ctl = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), .count = 1, .info = ct_spdif_info, .get = ct_spdif_get_mask, .private_value = MIXER_IEC958_MASK }; static struct snd_kcontrol_new iec958_default_ctl = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), .count = 1, .info = ct_spdif_info, .get = ct_spdif_get, .put = ct_spdif_put, .private_value = MIXER_IEC958_DEFAULT }; static struct snd_kcontrol_new iec958_ctl = { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), .count = 1, .info = ct_spdif_info, .get = ct_spdif_get, .put = ct_spdif_put, .private_value = MIXER_IEC958_STREAM }; #define NUM_IEC958_CTL 3 static int ct_mixer_kcontrol_new(struct ct_mixer *mixer, struct snd_kcontrol_new *new) { struct snd_kcontrol *kctl; int err; kctl = snd_ctl_new1(new, mixer->atc); if (!kctl) return -ENOMEM; if (SNDRV_CTL_ELEM_IFACE_PCM == kctl->id.iface) kctl->id.device = IEC958; err = snd_ctl_add(mixer->atc->card, kctl); if (err) return err; switch (new->private_value) { case MIXER_LINEIN_C_S: kctls[0] = kctl; break; case MIXER_MIC_C_S: kctls[1] = kctl; break; default: break; } return 0; } static int ct_mixer_kcontrols_create(struct ct_mixer *mixer) { enum CTALSA_MIXER_CTL type; struct ct_atc *atc = mixer->atc; struct capabilities cap = atc->capabilities(atc); int err; /* Create snd kcontrol instances on demand */ for (type = VOL_MIXER_START; type <= VOL_MIXER_END; type++) { if (ct_kcontrol_init_table[type].ctl) { vol_ctl.name = ct_kcontrol_init_table[type].name; vol_ctl.private_value = (unsigned long)type; err = ct_mixer_kcontrol_new(mixer, &vol_ctl); if (err) return err; } } ct_kcontrol_init_table[MIXER_DIGITAL_IO_S].ctl = cap.digit_io_switch; for (type = SWH_MIXER_START; type <= SWH_MIXER_END; type++) { if (ct_kcontrol_init_table[type].ctl) { swh_ctl.name = ct_kcontrol_init_table[type].name; swh_ctl.private_value = (unsigned long)type; err = ct_mixer_kcontrol_new(mixer, &swh_ctl); if (err) return err; } } err = ct_mixer_kcontrol_new(mixer, &iec958_mask_ctl); if (err) return err; err = ct_mixer_kcontrol_new(mixer, &iec958_default_ctl); if (err) return err; err = ct_mixer_kcontrol_new(mixer, &iec958_ctl); if (err) return err; if (cap.output_switch) { err = ct_mixer_kcontrol_new(mixer, &output_ctl); if (err) return err; } if (cap.mic_source_switch) { err = ct_mixer_kcontrol_new(mixer, &mic_source_ctl); if (err) return err; } atc->line_front_unmute(atc, 1); set_switch_state(mixer, MIXER_WAVEF_P_S, 1); atc->line_surround_unmute(atc, 0); set_switch_state(mixer, MIXER_WAVES_P_S, 0); atc->line_clfe_unmute(atc, 0); set_switch_state(mixer, MIXER_WAVEC_P_S, 0); atc->line_rear_unmute(atc, 0); set_switch_state(mixer, MIXER_WAVER_P_S, 0); atc->spdif_out_unmute(atc, 0); set_switch_state(mixer, MIXER_SPDIFO_P_S, 0); atc->line_in_unmute(atc, 0); if (cap.dedicated_mic) atc->mic_unmute(atc, 0); atc->spdif_in_unmute(atc, 0); set_switch_state(mixer, MIXER_PCM_C_S, 0); set_switch_state(mixer, MIXER_LINEIN_C_S, 0); set_switch_state(mixer, MIXER_SPDIFI_C_S, 0); return 0; } static void ct_mixer_recording_select(struct ct_mixer *mixer, enum CT_AMIXER_CTL type) { struct amixer *amix_d; struct sum *sum_c; int i; for (i = 0; i < 2; i++) { amix_d = mixer->amixers[type*CHN_NUM+i]; sum_c = mixer->sums[SUM_IN_F_C*CHN_NUM+i]; amix_d->ops->set_sum(amix_d, sum_c); amix_d->ops->commit_write(amix_d); } } static void ct_mixer_recording_unselect(struct ct_mixer *mixer, enum CT_AMIXER_CTL type) { struct amixer *amix_d; int i; for (i = 0; i < 2; i++) { amix_d = mixer->amixers[type*CHN_NUM+i]; amix_d->ops->set_sum(amix_d, NULL); amix_d->ops->commit_write(amix_d); } } static int ct_mixer_get_resources(struct ct_mixer *mixer) { struct sum_mgr *sum_mgr; struct sum *sum; struct sum_desc sum_desc = {0}; struct amixer_mgr *amixer_mgr; struct amixer *amixer; struct amixer_desc am_desc = {0}; int err; int i; /* Allocate sum resources for mixer obj */ sum_mgr = (struct sum_mgr *)mixer->atc->rsc_mgrs[SUM]; sum_desc.msr = mixer->atc->msr; for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { err = sum_mgr->get_sum(sum_mgr, &sum_desc, &sum); if (err) { dev_err(mixer->atc->card->dev, "Failed to get sum resources for front output!\n"); break; } mixer->sums[i] = sum; } if (err) goto error1; /* Allocate amixer resources for mixer obj */ amixer_mgr = (struct amixer_mgr *)mixer->atc->rsc_mgrs[AMIXER]; am_desc.msr = mixer->atc->msr; for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { err = amixer_mgr->get_amixer(amixer_mgr, &am_desc, &amixer); if (err) { dev_err(mixer->atc->card->dev, "Failed to get amixer resources for mixer obj!\n"); break; } mixer->amixers[i] = amixer; } if (err) goto error2; return 0; error2: for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { if (NULL != mixer->amixers[i]) { amixer = mixer->amixers[i]; amixer_mgr->put_amixer(amixer_mgr, amixer); mixer->amixers[i] = NULL; } } error1: for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { if (NULL != mixer->sums[i]) { sum_mgr->put_sum(sum_mgr, (struct sum *)mixer->sums[i]); mixer->sums[i] = NULL; } } return err; } static int ct_mixer_get_mem(struct ct_mixer **rmixer) { struct ct_mixer *mixer; int err; *rmixer = NULL; /* Allocate mem for mixer obj */ mixer = kzalloc(sizeof(*mixer), GFP_KERNEL); if (!mixer) return -ENOMEM; mixer->amixers = kcalloc(NUM_CT_AMIXERS * CHN_NUM, sizeof(void *), GFP_KERNEL); if (!mixer->amixers) { err = -ENOMEM; goto error1; } mixer->sums = kcalloc(NUM_CT_SUMS * CHN_NUM, sizeof(void *), GFP_KERNEL); if (!mixer->sums) { err = -ENOMEM; goto error2; } *rmixer = mixer; return 0; error2: kfree(mixer->amixers); error1: kfree(mixer); return err; } static int ct_mixer_topology_build(struct ct_mixer *mixer) { struct sum *sum; struct amixer *amix_d, *amix_s; enum CT_AMIXER_CTL i, j; enum CT_SUM_CTL k; /* Build topology from destination to source */ /* Set up Master mixer */ for (i = AMIXER_MASTER_F, k = SUM_IN_F; i <= AMIXER_MASTER_S; i++, k++) { amix_d = mixer->amixers[i*CHN_NUM]; sum = mixer->sums[k*CHN_NUM]; amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL); amix_d = mixer->amixers[i*CHN_NUM+1]; sum = mixer->sums[k*CHN_NUM+1]; amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL); } /* Set up Wave-out mixer */ for (i = AMIXER_WAVE_F, j = AMIXER_MASTER_F; i <= AMIXER_WAVE_S; i++, j++) { amix_d = mixer->amixers[i*CHN_NUM]; amix_s = mixer->amixers[j*CHN_NUM]; amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL); amix_d = mixer->amixers[i*CHN_NUM+1]; amix_s = mixer->amixers[j*CHN_NUM+1]; amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL); } /* Set up S/PDIF-out mixer */ amix_d = mixer->amixers[AMIXER_SPDIFO*CHN_NUM]; amix_s = mixer->amixers[AMIXER_MASTER_F*CHN_NUM]; amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL); amix_d = mixer->amixers[AMIXER_SPDIFO*CHN_NUM+1]; amix_s = mixer->amixers[AMIXER_MASTER_F*CHN_NUM+1]; amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL); /* Set up PCM-in mixer */ for (i = AMIXER_PCM_F, k = SUM_IN_F; i <= AMIXER_PCM_S; i++, k++) { amix_d = mixer->amixers[i*CHN_NUM]; sum = mixer->sums[k*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[i*CHN_NUM+1]; sum = mixer->sums[k*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); } /* Set up Line-in mixer */ amix_d = mixer->amixers[AMIXER_LINEIN*CHN_NUM]; sum = mixer->sums[SUM_IN_F*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_LINEIN*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up Mic-in mixer */ amix_d = mixer->amixers[AMIXER_MIC*CHN_NUM]; sum = mixer->sums[SUM_IN_F*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_MIC*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up S/PDIF-in mixer */ amix_d = mixer->amixers[AMIXER_SPDIFI*CHN_NUM]; sum = mixer->sums[SUM_IN_F*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_SPDIFI*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up Master recording mixer */ amix_d = mixer->amixers[AMIXER_MASTER_F_C*CHN_NUM]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM]; amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL); amix_d = mixer->amixers[AMIXER_MASTER_F_C*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1]; amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL); /* Set up PCM-in recording mixer */ amix_d = mixer->amixers[AMIXER_PCM_F_C*CHN_NUM]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_PCM_F_C*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up Line-in recording mixer */ amix_d = mixer->amixers[AMIXER_LINEIN_C*CHN_NUM]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_LINEIN_C*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up Mic-in recording mixer */ amix_d = mixer->amixers[AMIXER_MIC_C*CHN_NUM]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_MIC_C*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); /* Set up S/PDIF-in recording mixer */ amix_d = mixer->amixers[AMIXER_SPDIFI_C*CHN_NUM]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); amix_d = mixer->amixers[AMIXER_SPDIFI_C*CHN_NUM+1]; sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1]; amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum); return 0; } static int mixer_set_input_port(struct amixer *amixer, struct rsc *rsc) { amixer->ops->set_input(amixer, rsc); amixer->ops->commit_write(amixer); return 0; } static enum CT_AMIXER_CTL port_to_amixer(enum MIXER_PORT_T type) { switch (type) { case MIX_WAVE_FRONT: return AMIXER_WAVE_F; case MIX_WAVE_SURROUND: return AMIXER_WAVE_S; case MIX_WAVE_CENTLFE: return AMIXER_WAVE_C; case MIX_WAVE_REAR: return AMIXER_WAVE_R; case MIX_PCMO_FRONT: return AMIXER_MASTER_F_C; case MIX_SPDIF_OUT: return AMIXER_SPDIFO; case MIX_LINE_IN: return AMIXER_LINEIN; case MIX_MIC_IN: return AMIXER_MIC; case MIX_SPDIF_IN: return AMIXER_SPDIFI; case MIX_PCMI_FRONT: return AMIXER_PCM_F; case MIX_PCMI_SURROUND: return AMIXER_PCM_S; case MIX_PCMI_CENTLFE: return AMIXER_PCM_C; case MIX_PCMI_REAR: return AMIXER_PCM_R; default: return 0; } } static int mixer_get_output_ports(struct ct_mixer *mixer, enum MIXER_PORT_T type, struct rsc **rleft, struct rsc **rright) { enum CT_AMIXER_CTL amix = port_to_amixer(type); if (NULL != rleft) *rleft = &((struct amixer *)mixer->amixers[amix*CHN_NUM])->rsc; if (NULL != rright) *rright = &((struct amixer *)mixer->amixers[amix*CHN_NUM+1])->rsc; return 0; } static int mixer_set_input_left(struct ct_mixer *mixer, enum MIXER_PORT_T type, struct rsc *rsc) { enum CT_AMIXER_CTL amix = port_to_amixer(type); mixer_set_input_port(mixer->amixers[amix*CHN_NUM], rsc); amix = get_recording_amixer(amix); if (amix < NUM_CT_AMIXERS) mixer_set_input_port(mixer->amixers[amix*CHN_NUM], rsc); return 0; } static int mixer_set_input_right(struct ct_mixer *mixer, enum MIXER_PORT_T type, struct rsc *rsc) { enum CT_AMIXER_CTL amix = port_to_amixer(type); mixer_set_input_port(mixer->amixers[amix*CHN_NUM+1], rsc); amix = get_recording_amixer(amix); if (amix < NUM_CT_AMIXERS) mixer_set_input_port(mixer->amixers[amix*CHN_NUM+1], rsc); return 0; } #ifdef CONFIG_PM_SLEEP static int mixer_resume(struct ct_mixer *mixer) { int i, state; struct amixer *amixer; /* resume topology and volume gain. */ for (i = 0; i < NUM_CT_AMIXERS*CHN_NUM; i++) { amixer = mixer->amixers[i]; amixer->ops->commit_write(amixer); } /* resume switch state. */ for (i = SWH_MIXER_START; i <= SWH_MIXER_END; i++) { state = get_switch_state(mixer, i); do_switch(mixer->atc, i, state); } return 0; } #endif int ct_mixer_destroy(struct ct_mixer *mixer) { struct sum_mgr *sum_mgr = (struct sum_mgr *)mixer->atc->rsc_mgrs[SUM]; struct amixer_mgr *amixer_mgr = (struct amixer_mgr *)mixer->atc->rsc_mgrs[AMIXER]; struct amixer *amixer; int i = 0; /* Release amixer resources */ for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { if (NULL != mixer->amixers[i]) { amixer = mixer->amixers[i]; amixer_mgr->put_amixer(amixer_mgr, amixer); } } /* Release sum resources */ for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { if (NULL != mixer->sums[i]) sum_mgr->put_sum(sum_mgr, (struct sum *)mixer->sums[i]); } /* Release mem assigned to mixer object */ kfree(mixer->sums); kfree(mixer->amixers); kfree(mixer); return 0; } int ct_mixer_create(struct ct_atc *atc, struct ct_mixer **rmixer) { struct ct_mixer *mixer; int err; *rmixer = NULL; /* Allocate mem for mixer obj */ err = ct_mixer_get_mem(&mixer); if (err) return err; mixer->switch_state = 0; mixer->atc = atc; /* Set operations */ mixer->get_output_ports = mixer_get_output_ports; mixer->set_input_left = mixer_set_input_left; mixer->set_input_right = mixer_set_input_right; #ifdef CONFIG_PM_SLEEP mixer->resume = mixer_resume; #endif /* Allocate chip resources for mixer obj */ err = ct_mixer_get_resources(mixer); if (err) goto error; /* Build internal mixer topology */ ct_mixer_topology_build(mixer); *rmixer = mixer; return 0; error: ct_mixer_destroy(mixer); return err; } int ct_alsa_mix_create(struct ct_atc *atc, enum CTALSADEVS device, const char *device_name) { int err; /* Create snd kcontrol instances on demand */ /* vol_ctl.device = swh_ctl.device = device; */ /* better w/ device 0 */ err = ct_mixer_kcontrols_create((struct ct_mixer *)atc->mixer); if (err) return err; strcpy(atc->card->mixername, device_name); return 0; }
linux-master
sound/pci/ctxfi/ctmixer.c
// SPDX-License-Identifier: GPL-2.0-only /* * PCM timer handling on ctxfi */ #include <linux/slab.h> #include <linux/math64.h> #include <linux/moduleparam.h> #include <sound/core.h> #include <sound/pcm.h> #include "ctatc.h" #include "cthardware.h" #include "cttimer.h" static bool use_system_timer; MODULE_PARM_DESC(use_system_timer, "Force to use system-timer"); module_param(use_system_timer, bool, 0444); struct ct_timer_ops { void (*init)(struct ct_timer_instance *); void (*prepare)(struct ct_timer_instance *); void (*start)(struct ct_timer_instance *); void (*stop)(struct ct_timer_instance *); void (*free_instance)(struct ct_timer_instance *); void (*interrupt)(struct ct_timer *); void (*free_global)(struct ct_timer *); }; /* timer instance -- assigned to each PCM stream */ struct ct_timer_instance { spinlock_t lock; struct ct_timer *timer_base; struct ct_atc_pcm *apcm; struct snd_pcm_substream *substream; struct timer_list timer; struct list_head instance_list; struct list_head running_list; unsigned int position; unsigned int frag_count; unsigned int running:1; unsigned int need_update:1; }; /* timer instance manager */ struct ct_timer { spinlock_t lock; /* global timer lock (for xfitimer) */ spinlock_t list_lock; /* lock for instance list */ struct ct_atc *atc; const struct ct_timer_ops *ops; struct list_head instance_head; struct list_head running_head; unsigned int wc; /* current wallclock */ unsigned int irq_handling:1; /* in IRQ handling */ unsigned int reprogram:1; /* need to reprogram the internval */ unsigned int running:1; /* global timer running */ }; /* * system-timer-based updates */ static void ct_systimer_callback(struct timer_list *t) { struct ct_timer_instance *ti = from_timer(ti, t, timer); struct snd_pcm_substream *substream = ti->substream; struct snd_pcm_runtime *runtime = substream->runtime; struct ct_atc_pcm *apcm = ti->apcm; unsigned int period_size = runtime->period_size; unsigned int buffer_size = runtime->buffer_size; unsigned long flags; unsigned int position, dist, interval; position = substream->ops->pointer(substream); dist = (position + buffer_size - ti->position) % buffer_size; if (dist >= period_size || position / period_size != ti->position / period_size) { apcm->interrupt(apcm); ti->position = position; } /* Add extra HZ*5/1000 to avoid overrun issue when recording * at 8kHz in 8-bit format or at 88kHz in 24-bit format. */ interval = ((period_size - (position % period_size)) * HZ + (runtime->rate - 1)) / runtime->rate + HZ * 5 / 1000; spin_lock_irqsave(&ti->lock, flags); if (ti->running) mod_timer(&ti->timer, jiffies + interval); spin_unlock_irqrestore(&ti->lock, flags); } static void ct_systimer_init(struct ct_timer_instance *ti) { timer_setup(&ti->timer, ct_systimer_callback, 0); } static void ct_systimer_start(struct ct_timer_instance *ti) { struct snd_pcm_runtime *runtime = ti->substream->runtime; unsigned long flags; spin_lock_irqsave(&ti->lock, flags); ti->running = 1; mod_timer(&ti->timer, jiffies + (runtime->period_size * HZ + (runtime->rate - 1)) / runtime->rate); spin_unlock_irqrestore(&ti->lock, flags); } static void ct_systimer_stop(struct ct_timer_instance *ti) { unsigned long flags; spin_lock_irqsave(&ti->lock, flags); ti->running = 0; del_timer(&ti->timer); spin_unlock_irqrestore(&ti->lock, flags); } static void ct_systimer_prepare(struct ct_timer_instance *ti) { ct_systimer_stop(ti); try_to_del_timer_sync(&ti->timer); } #define ct_systimer_free ct_systimer_prepare static const struct ct_timer_ops ct_systimer_ops = { .init = ct_systimer_init, .free_instance = ct_systimer_free, .prepare = ct_systimer_prepare, .start = ct_systimer_start, .stop = ct_systimer_stop, }; /* * Handling multiple streams using a global emu20k1 timer irq */ #define CT_TIMER_FREQ 48000 #define MIN_TICKS 1 #define MAX_TICKS ((1 << 13) - 1) static void ct_xfitimer_irq_rearm(struct ct_timer *atimer, int ticks) { struct hw *hw = atimer->atc->hw; if (ticks > MAX_TICKS) ticks = MAX_TICKS; hw->set_timer_tick(hw, ticks); if (!atimer->running) hw->set_timer_irq(hw, 1); atimer->running = 1; } static void ct_xfitimer_irq_stop(struct ct_timer *atimer) { if (atimer->running) { struct hw *hw = atimer->atc->hw; hw->set_timer_irq(hw, 0); hw->set_timer_tick(hw, 0); atimer->running = 0; } } static inline unsigned int ct_xfitimer_get_wc(struct ct_timer *atimer) { struct hw *hw = atimer->atc->hw; return hw->get_wc(hw); } /* * reprogram the timer interval; * checks the running instance list and determines the next timer interval. * also updates the each stream position, returns the number of streams * to call snd_pcm_period_elapsed() appropriately * * call this inside the lock and irq disabled */ static int ct_xfitimer_reprogram(struct ct_timer *atimer, int can_update) { struct ct_timer_instance *ti; unsigned int min_intr = (unsigned int)-1; int updates = 0; unsigned int wc, diff; if (list_empty(&atimer->running_head)) { ct_xfitimer_irq_stop(atimer); atimer->reprogram = 0; /* clear flag */ return 0; } wc = ct_xfitimer_get_wc(atimer); diff = wc - atimer->wc; atimer->wc = wc; list_for_each_entry(ti, &atimer->running_head, running_list) { if (ti->frag_count > diff) ti->frag_count -= diff; else { unsigned int pos; unsigned int period_size, rate; period_size = ti->substream->runtime->period_size; rate = ti->substream->runtime->rate; pos = ti->substream->ops->pointer(ti->substream); if (pos / period_size != ti->position / period_size) { ti->need_update = 1; ti->position = pos; updates++; } pos %= period_size; pos = period_size - pos; ti->frag_count = div_u64((u64)pos * CT_TIMER_FREQ + rate - 1, rate); } if (ti->need_update && !can_update) min_intr = 0; /* pending to the next irq */ if (ti->frag_count < min_intr) min_intr = ti->frag_count; } if (min_intr < MIN_TICKS) min_intr = MIN_TICKS; ct_xfitimer_irq_rearm(atimer, min_intr); atimer->reprogram = 0; /* clear flag */ return updates; } /* look through the instance list and call period_elapsed if needed */ static void ct_xfitimer_check_period(struct ct_timer *atimer) { struct ct_timer_instance *ti; unsigned long flags; spin_lock_irqsave(&atimer->list_lock, flags); list_for_each_entry(ti, &atimer->instance_head, instance_list) { if (ti->running && ti->need_update) { ti->need_update = 0; ti->apcm->interrupt(ti->apcm); } } spin_unlock_irqrestore(&atimer->list_lock, flags); } /* Handle timer-interrupt */ static void ct_xfitimer_callback(struct ct_timer *atimer) { int update; unsigned long flags; spin_lock_irqsave(&atimer->lock, flags); atimer->irq_handling = 1; do { update = ct_xfitimer_reprogram(atimer, 1); spin_unlock(&atimer->lock); if (update) ct_xfitimer_check_period(atimer); spin_lock(&atimer->lock); } while (atimer->reprogram); atimer->irq_handling = 0; spin_unlock_irqrestore(&atimer->lock, flags); } static void ct_xfitimer_prepare(struct ct_timer_instance *ti) { ti->frag_count = ti->substream->runtime->period_size; ti->running = 0; ti->need_update = 0; } /* start/stop the timer */ static void ct_xfitimer_update(struct ct_timer *atimer) { unsigned long flags; spin_lock_irqsave(&atimer->lock, flags); if (atimer->irq_handling) { /* reached from IRQ handler; let it handle later */ atimer->reprogram = 1; spin_unlock_irqrestore(&atimer->lock, flags); return; } ct_xfitimer_irq_stop(atimer); ct_xfitimer_reprogram(atimer, 0); spin_unlock_irqrestore(&atimer->lock, flags); } static void ct_xfitimer_start(struct ct_timer_instance *ti) { struct ct_timer *atimer = ti->timer_base; unsigned long flags; spin_lock_irqsave(&atimer->lock, flags); if (list_empty(&ti->running_list)) atimer->wc = ct_xfitimer_get_wc(atimer); ti->running = 1; ti->need_update = 0; list_add(&ti->running_list, &atimer->running_head); spin_unlock_irqrestore(&atimer->lock, flags); ct_xfitimer_update(atimer); } static void ct_xfitimer_stop(struct ct_timer_instance *ti) { struct ct_timer *atimer = ti->timer_base; unsigned long flags; spin_lock_irqsave(&atimer->lock, flags); list_del_init(&ti->running_list); ti->running = 0; spin_unlock_irqrestore(&atimer->lock, flags); ct_xfitimer_update(atimer); } static void ct_xfitimer_free_global(struct ct_timer *atimer) { ct_xfitimer_irq_stop(atimer); } static const struct ct_timer_ops ct_xfitimer_ops = { .prepare = ct_xfitimer_prepare, .start = ct_xfitimer_start, .stop = ct_xfitimer_stop, .interrupt = ct_xfitimer_callback, .free_global = ct_xfitimer_free_global, }; /* * timer instance */ struct ct_timer_instance * ct_timer_instance_new(struct ct_timer *atimer, struct ct_atc_pcm *apcm) { struct ct_timer_instance *ti; ti = kzalloc(sizeof(*ti), GFP_KERNEL); if (!ti) return NULL; spin_lock_init(&ti->lock); INIT_LIST_HEAD(&ti->instance_list); INIT_LIST_HEAD(&ti->running_list); ti->timer_base = atimer; ti->apcm = apcm; ti->substream = apcm->substream; if (atimer->ops->init) atimer->ops->init(ti); spin_lock_irq(&atimer->list_lock); list_add(&ti->instance_list, &atimer->instance_head); spin_unlock_irq(&atimer->list_lock); return ti; } void ct_timer_prepare(struct ct_timer_instance *ti) { if (ti->timer_base->ops->prepare) ti->timer_base->ops->prepare(ti); ti->position = 0; ti->running = 0; } void ct_timer_start(struct ct_timer_instance *ti) { struct ct_timer *atimer = ti->timer_base; atimer->ops->start(ti); } void ct_timer_stop(struct ct_timer_instance *ti) { struct ct_timer *atimer = ti->timer_base; atimer->ops->stop(ti); } void ct_timer_instance_free(struct ct_timer_instance *ti) { struct ct_timer *atimer = ti->timer_base; atimer->ops->stop(ti); /* to be sure */ if (atimer->ops->free_instance) atimer->ops->free_instance(ti); spin_lock_irq(&atimer->list_lock); list_del(&ti->instance_list); spin_unlock_irq(&atimer->list_lock); kfree(ti); } /* * timer manager */ static void ct_timer_interrupt(void *data, unsigned int status) { struct ct_timer *timer = data; /* Interval timer interrupt */ if ((status & IT_INT) && timer->ops->interrupt) timer->ops->interrupt(timer); } struct ct_timer *ct_timer_new(struct ct_atc *atc) { struct ct_timer *atimer; struct hw *hw; atimer = kzalloc(sizeof(*atimer), GFP_KERNEL); if (!atimer) return NULL; spin_lock_init(&atimer->lock); spin_lock_init(&atimer->list_lock); INIT_LIST_HEAD(&atimer->instance_head); INIT_LIST_HEAD(&atimer->running_head); atimer->atc = atc; hw = atc->hw; if (!use_system_timer && hw->set_timer_irq) { dev_info(atc->card->dev, "Use xfi-native timer\n"); atimer->ops = &ct_xfitimer_ops; hw->irq_callback_data = atimer; hw->irq_callback = ct_timer_interrupt; } else { dev_info(atc->card->dev, "Use system timer\n"); atimer->ops = &ct_systimer_ops; } return atimer; } void ct_timer_free(struct ct_timer *atimer) { struct hw *hw = atimer->atc->hw; hw->irq_callback = NULL; if (atimer->ops->free_global) atimer->ops->free_global(atimer); kfree(atimer); }
linux-master
sound/pci/ctxfi/cttimer.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctvmem.c * * @Brief * This file contains the implementation of virtual memory management object * for card device. * * @Author Liu Chun * @Date Apr 1 2008 */ #include "ctvmem.h" #include "ctatc.h" #include <linux/slab.h> #include <linux/mm.h> #include <linux/io.h> #include <sound/pcm.h> #define CT_PTES_PER_PAGE (CT_PAGE_SIZE / sizeof(void *)) #define CT_ADDRS_PER_PAGE (CT_PTES_PER_PAGE * CT_PAGE_SIZE) /* * * Find or create vm block based on requested @size. * @size must be page aligned. * */ static struct ct_vm_block * get_vm_block(struct ct_vm *vm, unsigned int size, struct ct_atc *atc) { struct ct_vm_block *block = NULL, *entry; struct list_head *pos; size = CT_PAGE_ALIGN(size); if (size > vm->size) { dev_err(atc->card->dev, "Fail! No sufficient device virtual memory space available!\n"); return NULL; } mutex_lock(&vm->lock); list_for_each(pos, &vm->unused) { entry = list_entry(pos, struct ct_vm_block, list); if (entry->size >= size) break; /* found a block that is big enough */ } if (pos == &vm->unused) goto out; if (entry->size == size) { /* Move the vm node from unused list to used list directly */ list_move(&entry->list, &vm->used); vm->size -= size; block = entry; goto out; } block = kzalloc(sizeof(*block), GFP_KERNEL); if (!block) goto out; block->addr = entry->addr; block->size = size; list_add(&block->list, &vm->used); entry->addr += size; entry->size -= size; vm->size -= size; out: mutex_unlock(&vm->lock); return block; } static void put_vm_block(struct ct_vm *vm, struct ct_vm_block *block) { struct ct_vm_block *entry, *pre_ent; struct list_head *pos, *pre; block->size = CT_PAGE_ALIGN(block->size); mutex_lock(&vm->lock); list_del(&block->list); vm->size += block->size; list_for_each(pos, &vm->unused) { entry = list_entry(pos, struct ct_vm_block, list); if (entry->addr >= (block->addr + block->size)) break; /* found a position */ } if (pos == &vm->unused) { list_add_tail(&block->list, &vm->unused); entry = block; } else { if ((block->addr + block->size) == entry->addr) { entry->addr = block->addr; entry->size += block->size; kfree(block); } else { __list_add(&block->list, pos->prev, pos); entry = block; } } pos = &entry->list; pre = pos->prev; while (pre != &vm->unused) { entry = list_entry(pos, struct ct_vm_block, list); pre_ent = list_entry(pre, struct ct_vm_block, list); if ((pre_ent->addr + pre_ent->size) > entry->addr) break; pre_ent->size += entry->size; list_del(pos); kfree(entry); pos = pre; pre = pos->prev; } mutex_unlock(&vm->lock); } /* Map host addr (kmalloced/vmalloced) to device logical addr. */ static struct ct_vm_block * ct_vm_map(struct ct_vm *vm, struct snd_pcm_substream *substream, int size) { struct ct_vm_block *block; unsigned int pte_start; unsigned i, pages; unsigned long *ptp; struct ct_atc *atc = snd_pcm_substream_chip(substream); block = get_vm_block(vm, size, atc); if (block == NULL) { dev_err(atc->card->dev, "No virtual memory block that is big enough to allocate!\n"); return NULL; } ptp = (unsigned long *)vm->ptp[0].area; pte_start = (block->addr >> CT_PAGE_SHIFT); pages = block->size >> CT_PAGE_SHIFT; for (i = 0; i < pages; i++) { unsigned long addr; addr = snd_pcm_sgbuf_get_addr(substream, i << CT_PAGE_SHIFT); ptp[pte_start + i] = addr; } block->size = size; return block; } static void ct_vm_unmap(struct ct_vm *vm, struct ct_vm_block *block) { /* do unmapping */ put_vm_block(vm, block); } /* * * return the host physical addr of the @index-th device * page table page on success, or ~0UL on failure. * The first returned ~0UL indicates the termination. * */ static dma_addr_t ct_get_ptp_phys(struct ct_vm *vm, int index) { return (index >= CT_PTP_NUM) ? ~0UL : vm->ptp[index].addr; } int ct_vm_create(struct ct_vm **rvm, struct pci_dev *pci) { struct ct_vm *vm; struct ct_vm_block *block; int i, err = 0; *rvm = NULL; vm = kzalloc(sizeof(*vm), GFP_KERNEL); if (!vm) return -ENOMEM; mutex_init(&vm->lock); /* Allocate page table pages */ for (i = 0; i < CT_PTP_NUM; i++) { err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, PAGE_SIZE, &vm->ptp[i]); if (err < 0) break; } if (err < 0) { /* no page table pages are allocated */ ct_vm_destroy(vm); return -ENOMEM; } vm->size = CT_ADDRS_PER_PAGE * i; vm->map = ct_vm_map; vm->unmap = ct_vm_unmap; vm->get_ptp_phys = ct_get_ptp_phys; INIT_LIST_HEAD(&vm->unused); INIT_LIST_HEAD(&vm->used); block = kzalloc(sizeof(*block), GFP_KERNEL); if (NULL != block) { block->addr = 0; block->size = vm->size; list_add(&block->list, &vm->unused); } *rvm = vm; return 0; } /* The caller must ensure no mapping pages are being used * by hardware before calling this function */ void ct_vm_destroy(struct ct_vm *vm) { int i; struct list_head *pos; struct ct_vm_block *entry; /* free used and unused list nodes */ while (!list_empty(&vm->used)) { pos = vm->used.next; list_del(pos); entry = list_entry(pos, struct ct_vm_block, list); kfree(entry); } while (!list_empty(&vm->unused)) { pos = vm->unused.next; list_del(pos); entry = list_entry(pos, struct ct_vm_block, list); kfree(entry); } /* free allocated page table pages */ for (i = 0; i < CT_PTP_NUM; i++) snd_dma_free_pages(&vm->ptp[i]); vm->size = 0; kfree(vm); }
linux-master
sound/pci/ctxfi/ctvmem.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File cthw20k1.c * * @Brief * This file contains the implementation of hardware access methord for 20k1. * * @Author Liu Chun * @Date Jun 24 2008 */ #include <linux/types.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/io.h> #include <linux/string.h> #include <linux/spinlock.h> #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/delay.h> #include "cthw20k1.h" #include "ct20k1reg.h" struct hw20k1 { struct hw hw; spinlock_t reg_20k1_lock; spinlock_t reg_pci_lock; }; static u32 hw_read_20kx(struct hw *hw, u32 reg); static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); static u32 hw_read_pci(struct hw *hw, u32 reg); static void hw_write_pci(struct hw *hw, u32 reg, u32 data); /* * Type definition block. * The layout of control structures can be directly applied on 20k2 chip. */ /* * SRC control block definitions. */ /* SRC resource control block */ #define SRCCTL_STATE 0x00000007 #define SRCCTL_BM 0x00000008 #define SRCCTL_RSR 0x00000030 #define SRCCTL_SF 0x000001C0 #define SRCCTL_WR 0x00000200 #define SRCCTL_PM 0x00000400 #define SRCCTL_ROM 0x00001800 #define SRCCTL_VO 0x00002000 #define SRCCTL_ST 0x00004000 #define SRCCTL_IE 0x00008000 #define SRCCTL_ILSZ 0x000F0000 #define SRCCTL_BP 0x00100000 #define SRCCCR_CISZ 0x000007FF #define SRCCCR_CWA 0x001FF800 #define SRCCCR_D 0x00200000 #define SRCCCR_RS 0x01C00000 #define SRCCCR_NAL 0x3E000000 #define SRCCCR_RA 0xC0000000 #define SRCCA_CA 0x03FFFFFF #define SRCCA_RS 0x1C000000 #define SRCCA_NAL 0xE0000000 #define SRCSA_SA 0x03FFFFFF #define SRCLA_LA 0x03FFFFFF /* Mixer Parameter Ring ram Low and Hight register. * Fixed-point value in 8.24 format for parameter channel */ #define MPRLH_PITCH 0xFFFFFFFF /* SRC resource register dirty flags */ union src_dirty { struct { u16 ctl:1; u16 ccr:1; u16 sa:1; u16 la:1; u16 ca:1; u16 mpr:1; u16 czbfs:1; /* Clear Z-Buffers */ u16 rsv:9; } bf; u16 data; }; struct src_rsc_ctrl_blk { unsigned int ctl; unsigned int ccr; unsigned int ca; unsigned int sa; unsigned int la; unsigned int mpr; union src_dirty dirty; }; /* SRC manager control block */ union src_mgr_dirty { struct { u16 enb0:1; u16 enb1:1; u16 enb2:1; u16 enb3:1; u16 enb4:1; u16 enb5:1; u16 enb6:1; u16 enb7:1; u16 enbsa:1; u16 rsv:7; } bf; u16 data; }; struct src_mgr_ctrl_blk { unsigned int enbsa; unsigned int enb[8]; union src_mgr_dirty dirty; }; /* SRCIMP manager control block */ #define SRCAIM_ARC 0x00000FFF #define SRCAIM_NXT 0x00FF0000 #define SRCAIM_SRC 0xFF000000 struct srcimap { unsigned int srcaim; unsigned int idx; }; /* SRCIMP manager register dirty flags */ union srcimp_mgr_dirty { struct { u16 srcimap:1; u16 rsv:15; } bf; u16 data; }; struct srcimp_mgr_ctrl_blk { struct srcimap srcimap; union srcimp_mgr_dirty dirty; }; /* * Function implementation block. */ static int src_get_rsc_ctrl_blk(void **rblk) { struct src_rsc_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int src_put_rsc_ctrl_blk(void *blk) { kfree(blk); return 0; } static int src_set_state(void *blk, unsigned int state) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_STATE, state); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_bm(void *blk, unsigned int bm) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_BM, bm); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_rsr(void *blk, unsigned int rsr) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_RSR, rsr); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_sf(void *blk, unsigned int sf) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_SF, sf); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_wr(void *blk, unsigned int wr) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_WR, wr); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_pm(void *blk, unsigned int pm) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_PM, pm); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_rom(void *blk, unsigned int rom) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ROM, rom); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_vo(void *blk, unsigned int vo) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_VO, vo); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_st(void *blk, unsigned int st) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ST, st); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_ie(void *blk, unsigned int ie) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_IE, ie); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_ilsz(void *blk, unsigned int ilsz) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_bp(void *blk, unsigned int bp) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ctl, SRCCTL_BP, bp); ctl->dirty.bf.ctl = 1; return 0; } static int src_set_cisz(void *blk, unsigned int cisz) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ccr, SRCCCR_CISZ, cisz); ctl->dirty.bf.ccr = 1; return 0; } static int src_set_ca(void *blk, unsigned int ca) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->ca, SRCCA_CA, ca); ctl->dirty.bf.ca = 1; return 0; } static int src_set_sa(void *blk, unsigned int sa) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->sa, SRCSA_SA, sa); ctl->dirty.bf.sa = 1; return 0; } static int src_set_la(void *blk, unsigned int la) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->la, SRCLA_LA, la); ctl->dirty.bf.la = 1; return 0; } static int src_set_pitch(void *blk, unsigned int pitch) { struct src_rsc_ctrl_blk *ctl = blk; set_field(&ctl->mpr, MPRLH_PITCH, pitch); ctl->dirty.bf.mpr = 1; return 0; } static int src_set_clear_zbufs(void *blk, unsigned int clear) { ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); return 0; } static int src_set_dirty(void *blk, unsigned int flags) { ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); return 0; } static int src_set_dirty_all(void *blk) { ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); return 0; } #define AR_SLOT_SIZE 4096 #define AR_SLOT_BLOCK_SIZE 16 #define AR_PTS_PITCH 6 #define AR_PARAM_SRC_OFFSET 0x60 static unsigned int src_param_pitch_mixer(unsigned int src_idx) { return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; } static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct src_rsc_ctrl_blk *ctl = blk; int i; if (ctl->dirty.bf.czbfs) { /* Clear Z-Buffer registers */ for (i = 0; i < 8; i++) hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0); for (i = 0; i < 4; i++) hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0); for (i = 0; i < 8; i++) hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0); ctl->dirty.bf.czbfs = 0; } if (ctl->dirty.bf.mpr) { /* Take the parameter mixer resource in the same group as that * the idx src is in for simplicity. Unlike src, all conjugate * parameter mixer resources must be programmed for * corresponding conjugate src resources. */ unsigned int pm_idx = src_param_pitch_mixer(idx); hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr); hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3); hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0); ctl->dirty.bf.mpr = 0; } if (ctl->dirty.bf.sa) { hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa); ctl->dirty.bf.sa = 0; } if (ctl->dirty.bf.la) { hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la); ctl->dirty.bf.la = 0; } if (ctl->dirty.bf.ca) { hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca); ctl->dirty.bf.ca = 0; } /* Write srccf register */ hw_write_20kx(hw, SRCCF+idx*0x100, 0x0); if (ctl->dirty.bf.ccr) { hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr); ctl->dirty.bf.ccr = 0; } if (ctl->dirty.bf.ctl) { hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl); ctl->dirty.bf.ctl = 0; } return 0; } static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) { struct src_rsc_ctrl_blk *ctl = blk; ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100); ctl->dirty.bf.ca = 0; return get_field(ctl->ca, SRCCA_CA); } static unsigned int src_get_dirty(void *blk) { return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; } static unsigned int src_dirty_conj_mask(void) { return 0x20; } static int src_mgr_enbs_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0); ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); return 0; } static int src_mgr_enb_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); return 0; } static int src_mgr_dsb_src(void *blk, unsigned int idx) { ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); return 0; } static int src_mgr_commit_write(struct hw *hw, void *blk) { struct src_mgr_ctrl_blk *ctl = blk; int i; unsigned int ret; if (ctl->dirty.bf.enbsa) { do { ret = hw_read_20kx(hw, SRCENBSTAT); } while (ret & 0x1); hw_write_20kx(hw, SRCENBS, ctl->enbsa); ctl->dirty.bf.enbsa = 0; } for (i = 0; i < 8; i++) { if ((ctl->dirty.data & (0x1 << i))) { hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]); ctl->dirty.data &= ~(0x1 << i); } } return 0; } static int src_mgr_get_ctrl_blk(void **rblk) { struct src_mgr_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int src_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int srcimp_mgr_get_ctrl_blk(void **rblk) { struct srcimp_mgr_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int srcimp_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapuser(void *blk, unsigned int user) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next) { struct srcimp_mgr_ctrl_blk *ctl = blk; set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next); ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr) { struct srcimp_mgr_ctrl_blk *ctl = blk; ctl->srcimap.idx = addr; ctl->dirty.bf.srcimap = 1; return 0; } static int srcimp_mgr_commit_write(struct hw *hw, void *blk) { struct srcimp_mgr_ctrl_blk *ctl = blk; if (ctl->dirty.bf.srcimap) { hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100, ctl->srcimap.srcaim); ctl->dirty.bf.srcimap = 0; } return 0; } /* * AMIXER control block definitions. */ #define AMOPLO_M 0x00000003 #define AMOPLO_X 0x0003FFF0 #define AMOPLO_Y 0xFFFC0000 #define AMOPHI_SADR 0x000000FF #define AMOPHI_SE 0x80000000 /* AMIXER resource register dirty flags */ union amixer_dirty { struct { u16 amoplo:1; u16 amophi:1; u16 rsv:14; } bf; u16 data; }; /* AMIXER resource control block */ struct amixer_rsc_ctrl_blk { unsigned int amoplo; unsigned int amophi; union amixer_dirty dirty; }; static int amixer_set_mode(void *blk, unsigned int mode) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_M, mode); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_iv(void *blk, unsigned int iv) { /* 20k1 amixer does not have this field */ return 0; } static int amixer_set_x(void *blk, unsigned int x) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_X, x); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_y(void *blk, unsigned int y) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amoplo, AMOPLO_Y, y); ctl->dirty.bf.amoplo = 1; return 0; } static int amixer_set_sadr(void *blk, unsigned int sadr) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amophi, AMOPHI_SADR, sadr); ctl->dirty.bf.amophi = 1; return 0; } static int amixer_set_se(void *blk, unsigned int se) { struct amixer_rsc_ctrl_blk *ctl = blk; set_field(&ctl->amophi, AMOPHI_SE, se); ctl->dirty.bf.amophi = 1; return 0; } static int amixer_set_dirty(void *blk, unsigned int flags) { ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); return 0; } static int amixer_set_dirty_all(void *blk) { ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); return 0; } static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct amixer_rsc_ctrl_blk *ctl = blk; if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo); ctl->dirty.bf.amoplo = 0; hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi); ctl->dirty.bf.amophi = 0; } return 0; } static int amixer_get_y(void *blk) { struct amixer_rsc_ctrl_blk *ctl = blk; return get_field(ctl->amoplo, AMOPLO_Y); } static unsigned int amixer_get_dirty(void *blk) { return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; } static int amixer_rsc_get_ctrl_blk(void **rblk) { struct amixer_rsc_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int amixer_rsc_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int amixer_mgr_get_ctrl_blk(void **rblk) { /*amixer_mgr_ctrl_blk_t *blk;*/ *rblk = NULL; /*blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk;*/ return 0; } static int amixer_mgr_put_ctrl_blk(void *blk) { /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/ return 0; } /* * DAIO control block definitions. */ /* Receiver Sample Rate Tracker Control register */ #define SRTCTL_SRCR 0x000000FF #define SRTCTL_SRCL 0x0000FF00 #define SRTCTL_RSR 0x00030000 #define SRTCTL_DRAT 0x000C0000 #define SRTCTL_RLE 0x10000000 #define SRTCTL_RLP 0x20000000 #define SRTCTL_EC 0x40000000 #define SRTCTL_ET 0x80000000 /* DAIO Receiver register dirty flags */ union dai_dirty { struct { u16 srtctl:1; u16 rsv:15; } bf; u16 data; }; /* DAIO Receiver control block */ struct dai_ctrl_blk { unsigned int srtctl; union dai_dirty dirty; }; /* S/PDIF Transmitter register dirty flags */ union dao_dirty { struct { u16 spos:1; u16 rsv:15; } bf; u16 data; }; /* S/PDIF Transmitter control block */ struct dao_ctrl_blk { unsigned int spos; /* S/PDIF Output Channel Status Register */ union dao_dirty dirty; }; /* Audio Input Mapper RAM */ #define AIM_ARC 0x00000FFF #define AIM_NXT 0x007F0000 struct daoimap { unsigned int aim; unsigned int idx; }; /* I2S Transmitter/Receiver Control register */ #define I2SCTL_EA 0x00000004 #define I2SCTL_EI 0x00000010 /* S/PDIF Transmitter Control register */ #define SPOCTL_OE 0x00000001 #define SPOCTL_OS 0x0000000E #define SPOCTL_RIV 0x00000010 #define SPOCTL_LIV 0x00000020 #define SPOCTL_SR 0x000000C0 /* S/PDIF Receiver Control register */ #define SPICTL_EN 0x00000001 #define SPICTL_I24 0x00000002 #define SPICTL_IB 0x00000004 #define SPICTL_SM 0x00000008 #define SPICTL_VM 0x00000010 /* DAIO manager register dirty flags */ union daio_mgr_dirty { struct { u32 i2soctl:4; u32 i2sictl:4; u32 spoctl:4; u32 spictl:4; u32 daoimap:1; u32 rsv:15; } bf; u32 data; }; /* DAIO manager control block */ struct daio_mgr_ctrl_blk { unsigned int i2sctl; unsigned int spoctl; unsigned int spictl; struct daoimap daoimap; union daio_mgr_dirty dirty; }; static int dai_srt_set_srcr(void *blk, unsigned int src) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_SRCR, src); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_srt_set_srcl(void *blk, unsigned int src) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_SRCL, src); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_srt_set_rsr(void *blk, unsigned int rsr) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_RSR, rsr); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_srt_set_drat(void *blk, unsigned int drat) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_DRAT, drat); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_srt_set_ec(void *blk, unsigned int ec) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_srt_set_et(void *blk, unsigned int et) { struct dai_ctrl_blk *ctl = blk; set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0); ctl->dirty.bf.srtctl = 1; return 0; } static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct dai_ctrl_blk *ctl = blk; if (ctl->dirty.bf.srtctl) { if (idx < 4) { /* S/PDIF SRTs */ hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl); } else { /* I2S SRT */ hw_write_20kx(hw, SRTICTL, ctl->srtctl); } ctl->dirty.bf.srtctl = 0; } return 0; } static int dai_get_ctrl_blk(void **rblk) { struct dai_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int dai_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int dao_set_spos(void *blk, unsigned int spos) { ((struct dao_ctrl_blk *)blk)->spos = spos; ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1; return 0; } static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) { struct dao_ctrl_blk *ctl = blk; if (ctl->dirty.bf.spos) { if (idx < 4) { /* S/PDIF SPOSx */ hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos); } ctl->dirty.bf.spos = 0; } return 0; } static int dao_get_spos(void *blk, unsigned int *spos) { *spos = ((struct dao_ctrl_blk *)blk)->spos; return 0; } static int dao_get_ctrl_blk(void **rblk) { struct dao_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; *rblk = blk; return 0; } static int dao_put_ctrl_blk(void *blk) { kfree(blk); return 0; } static int daio_mgr_enb_dai(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF input */ set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1); ctl->dirty.bf.spictl |= (0x1 << idx); } else { /* I2S input */ idx %= 4; set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1); ctl->dirty.bf.i2sictl |= (0x1 << idx); } return 0; } static int daio_mgr_dsb_dai(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF input */ set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0); ctl->dirty.bf.spictl |= (0x1 << idx); } else { /* I2S input */ idx %= 4; set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0); ctl->dirty.bf.i2sictl |= (0x1 << idx); } return 0; } static int daio_mgr_enb_dao(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF output */ set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1); ctl->dirty.bf.spoctl |= (0x1 << idx); } else { /* I2S output */ idx %= 4; set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1); ctl->dirty.bf.i2soctl |= (0x1 << idx); } return 0; } static int daio_mgr_dsb_dao(void *blk, unsigned int idx) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF output */ set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0); ctl->dirty.bf.spoctl |= (0x1 << idx); } else { /* I2S output */ idx %= 4; set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0); ctl->dirty.bf.i2soctl |= (0x1 << idx); } return 0; } static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf) { struct daio_mgr_ctrl_blk *ctl = blk; if (idx < 4) { /* S/PDIF output */ switch ((conf & 0x7)) { case 0: set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3); break; /* CDIF */ case 1: set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0); break; case 2: set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1); break; case 4: set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2); break; default: break; } set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8), (conf >> 4) & 0x1); /* Non-audio */ set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8), (conf >> 4) & 0x1); /* Non-audio */ set_field(&ctl->spoctl, SPOCTL_OS << (idx*8), ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */ ctl->dirty.bf.spoctl |= (0x1 << idx); } else { /* I2S output */ /*idx %= 4; */ } return 0; } static int daio_mgr_set_imaparc(void *blk, unsigned int slot) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->daoimap.aim, AIM_ARC, slot); ctl->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_set_imapnxt(void *blk, unsigned int next) { struct daio_mgr_ctrl_blk *ctl = blk; set_field(&ctl->daoimap.aim, AIM_NXT, next); ctl->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_set_imapaddr(void *blk, unsigned int addr) { struct daio_mgr_ctrl_blk *ctl = blk; ctl->daoimap.idx = addr; ctl->dirty.bf.daoimap = 1; return 0; } static int daio_mgr_commit_write(struct hw *hw, void *blk) { struct daio_mgr_ctrl_blk *ctl = blk; int i; if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) { for (i = 0; i < 4; i++) { if ((ctl->dirty.bf.i2sictl & (0x1 << i))) ctl->dirty.bf.i2sictl &= ~(0x1 << i); if ((ctl->dirty.bf.i2soctl & (0x1 << i))) ctl->dirty.bf.i2soctl &= ~(0x1 << i); } hw_write_20kx(hw, I2SCTL, ctl->i2sctl); mdelay(1); } if (ctl->dirty.bf.spoctl) { for (i = 0; i < 4; i++) { if ((ctl->dirty.bf.spoctl & (0x1 << i))) ctl->dirty.bf.spoctl &= ~(0x1 << i); } hw_write_20kx(hw, SPOCTL, ctl->spoctl); mdelay(1); } if (ctl->dirty.bf.spictl) { for (i = 0; i < 4; i++) { if ((ctl->dirty.bf.spictl & (0x1 << i))) ctl->dirty.bf.spictl &= ~(0x1 << i); } hw_write_20kx(hw, SPICTL, ctl->spictl); mdelay(1); } if (ctl->dirty.bf.daoimap) { hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4, ctl->daoimap.aim); ctl->dirty.bf.daoimap = 0; } return 0; } static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) { struct daio_mgr_ctrl_blk *blk; *rblk = NULL; blk = kzalloc(sizeof(*blk), GFP_KERNEL); if (!blk) return -ENOMEM; blk->i2sctl = hw_read_20kx(hw, I2SCTL); blk->spoctl = hw_read_20kx(hw, SPOCTL); blk->spictl = hw_read_20kx(hw, SPICTL); *rblk = blk; return 0; } static int daio_mgr_put_ctrl_blk(void *blk) { kfree(blk); return 0; } /* Timer interrupt */ static int set_timer_irq(struct hw *hw, int enable) { hw_write_20kx(hw, GIE, enable ? IT_INT : 0); return 0; } static int set_timer_tick(struct hw *hw, unsigned int ticks) { if (ticks) ticks |= TIMR_IE | TIMR_IP; hw_write_20kx(hw, TIMR, ticks); return 0; } static unsigned int get_wc(struct hw *hw) { return hw_read_20kx(hw, WC); } /* Card hardware initialization block */ struct dac_conf { unsigned int msr; /* master sample rate in rsrs */ }; struct adc_conf { unsigned int msr; /* master sample rate in rsrs */ unsigned char input; /* the input source of ADC */ unsigned char mic20db; /* boost mic by 20db if input is microphone */ }; struct daio_conf { unsigned int msr; /* master sample rate in rsrs */ }; struct trn_conf { unsigned long vm_pgt_phys; }; static int hw_daio_init(struct hw *hw, const struct daio_conf *info) { u32 i2sorg; u32 spdorg; /* Read I2S CTL. Keep original value. */ /*i2sorg = hw_read_20kx(hw, I2SCTL);*/ i2sorg = 0x94040404; /* enable all audio out and I2S-D input */ /* Program I2S with proper master sample rate and enable * the correct I2S channel. */ i2sorg &= 0xfffffffc; /* Enable S/PDIF-out-A in fixed 24-bit data * format and default to 48kHz. */ /* Disable all before doing any changes. */ hw_write_20kx(hw, SPOCTL, 0x0); spdorg = 0x05; switch (info->msr) { case 1: i2sorg |= 1; spdorg |= (0x0 << 6); break; case 2: i2sorg |= 2; spdorg |= (0x1 << 6); break; case 4: i2sorg |= 3; spdorg |= (0x2 << 6); break; default: i2sorg |= 1; break; } hw_write_20kx(hw, I2SCTL, i2sorg); hw_write_20kx(hw, SPOCTL, spdorg); /* Enable S/PDIF-in-A in fixed 24-bit data format. */ /* Disable all before doing any changes. */ hw_write_20kx(hw, SPICTL, 0x0); mdelay(1); spdorg = 0x0a0a0a0a; hw_write_20kx(hw, SPICTL, spdorg); mdelay(1); return 0; } /* TRANSPORT operations */ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) { u32 trnctl; u32 ptp_phys_low, ptp_phys_high; /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { dev_err(hw->card->dev, "Wrong device page table page address!\n"); return -1; } trnctl = 0x13; /* 32-bit, 4k-size page */ ptp_phys_low = (u32)info->vm_pgt_phys; ptp_phys_high = upper_32_bits(info->vm_pgt_phys); if (sizeof(void *) == 8) /* 64bit address */ trnctl |= (1 << 2); #if 0 /* Only 4k h/w pages for simplicitiy */ #if PAGE_SIZE == 8192 trnctl |= (1<<5); #endif #endif hw_write_20kx(hw, PTPALX, ptp_phys_low); hw_write_20kx(hw, PTPAHX, ptp_phys_high); hw_write_20kx(hw, TRNCTL, trnctl); hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */ return 0; } /* Card initialization */ #define GCTL_EAC 0x00000001 #define GCTL_EAI 0x00000002 #define GCTL_BEP 0x00000004 #define GCTL_BES 0x00000008 #define GCTL_DSP 0x00000010 #define GCTL_DBP 0x00000020 #define GCTL_ABP 0x00000040 #define GCTL_TBP 0x00000080 #define GCTL_SBP 0x00000100 #define GCTL_FBP 0x00000200 #define GCTL_XA 0x00000400 #define GCTL_ET 0x00000800 #define GCTL_PR 0x00001000 #define GCTL_MRL 0x00002000 #define GCTL_SDE 0x00004000 #define GCTL_SDI 0x00008000 #define GCTL_SM 0x00010000 #define GCTL_SR 0x00020000 #define GCTL_SD 0x00040000 #define GCTL_SE 0x00080000 #define GCTL_AID 0x00100000 static int hw_pll_init(struct hw *hw, unsigned int rsr) { unsigned int pllctl; int i; pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731; for (i = 0; i < 3; i++) { if (hw_read_20kx(hw, PLLCTL) == pllctl) break; hw_write_20kx(hw, PLLCTL, pllctl); msleep(40); } if (i >= 3) { dev_alert(hw->card->dev, "PLL initialization failed!!!\n"); return -EBUSY; } return 0; } static int hw_auto_init(struct hw *hw) { unsigned int gctl; int i; gctl = hw_read_20kx(hw, GCTL); set_field(&gctl, GCTL_EAI, 0); hw_write_20kx(hw, GCTL, gctl); set_field(&gctl, GCTL_EAI, 1); hw_write_20kx(hw, GCTL, gctl); mdelay(10); for (i = 0; i < 400000; i++) { gctl = hw_read_20kx(hw, GCTL); if (get_field(gctl, GCTL_AID)) break; } if (!get_field(gctl, GCTL_AID)) { dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); return -EBUSY; } return 0; } static int i2c_unlock(struct hw *hw) { if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) return 0; hw_write_pci(hw, 0xcc, 0x8c); hw_write_pci(hw, 0xcc, 0x0e); if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) return 0; hw_write_pci(hw, 0xcc, 0xee); hw_write_pci(hw, 0xcc, 0xaa); if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) return 0; return -1; } static void i2c_lock(struct hw *hw) { if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) hw_write_pci(hw, 0xcc, 0x00); } static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data) { unsigned int ret; do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); hw_write_pci(hw, 0xE0, device); hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff)); } /* DAC operations */ static int hw_reset_dac(struct hw *hw) { u32 i; u16 gpioorg; unsigned int ret; if (i2c_unlock(hw)) return -1; do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ /* To be effective, need to reset the DAC twice. */ for (i = 0; i < 2; i++) { /* set gpio */ msleep(100); gpioorg = (u16)hw_read_20kx(hw, GPIO); gpioorg &= 0xfffd; hw_write_20kx(hw, GPIO, gpioorg); mdelay(1); hw_write_20kx(hw, GPIO, gpioorg | 0x2); } i2c_write(hw, 0x00180080, 0x01, 0x80); i2c_write(hw, 0x00180080, 0x02, 0x10); i2c_lock(hw); return 0; } static int hw_dac_init(struct hw *hw, const struct dac_conf *info) { u32 data; u16 gpioorg; unsigned int ret; if (hw->model == CTSB055X) { /* SB055x, unmute outputs */ gpioorg = (u16)hw_read_20kx(hw, GPIO); gpioorg &= 0xffbf; /* set GPIO6 to low */ gpioorg |= 2; /* set GPIO1 to high */ hw_write_20kx(hw, GPIO, gpioorg); return 0; } /* mute outputs */ gpioorg = (u16)hw_read_20kx(hw, GPIO); gpioorg &= 0xffbf; hw_write_20kx(hw, GPIO, gpioorg); hw_reset_dac(hw); if (i2c_unlock(hw)) return -1; hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); switch (info->msr) { case 1: data = 0x24; break; case 2: data = 0x25; break; case 4: data = 0x26; break; default: data = 0x24; break; } i2c_write(hw, 0x00180080, 0x06, data); i2c_write(hw, 0x00180080, 0x09, data); i2c_write(hw, 0x00180080, 0x0c, data); i2c_write(hw, 0x00180080, 0x0f, data); i2c_lock(hw); /* unmute outputs */ gpioorg = (u16)hw_read_20kx(hw, GPIO); gpioorg = gpioorg | 0x40; hw_write_20kx(hw, GPIO, gpioorg); return 0; } /* ADC operations */ static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type) { return 0; } static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type) { u32 data; data = hw_read_20kx(hw, GPIO); switch (type) { case ADC_MICIN: data = ((data & (0x1<<7)) && (data & (0x1<<8))); break; case ADC_LINEIN: data = (!(data & (0x1<<7)) && (data & (0x1<<8))); break; case ADC_NONE: /* Digital I/O */ data = (!(data & (0x1<<8))); break; default: data = 0; } return data; } static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type) { u32 data; data = hw_read_20kx(hw, GPIO); switch (type) { case ADC_MICIN: data = (data & (0x1 << 7)) ? 1 : 0; break; case ADC_LINEIN: data = (data & (0x1 << 7)) ? 0 : 1; break; default: data = 0; } return data; } static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) { switch (hw->model) { case CTSB055X: return is_adc_input_selected_SB055x(hw, type); case CTSB073X: return is_adc_input_selected_hendrix(hw, type); case CTUAA: return is_adc_input_selected_hendrix(hw, type); default: return is_adc_input_selected_SBx(hw, type); } } static int adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost) { u32 data; /* * check and set the following GPIO bits accordingly * ADC_Gain = GPIO2 * DRM_off = GPIO3 * Mic_Pwr_on = GPIO7 * Digital_IO_Sel = GPIO8 * Mic_Sw = GPIO9 * Aux/MicLine_Sw = GPIO12 */ data = hw_read_20kx(hw, GPIO); data &= 0xec73; switch (type) { case ADC_MICIN: data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ; data |= boost ? (0x1<<2) : 0; break; case ADC_LINEIN: data |= (0x1<<8); break; case ADC_AUX: data |= (0x1<<8) | (0x1<<12); break; case ADC_NONE: data |= (0x1<<12); /* set to digital */ break; default: return -1; } hw_write_20kx(hw, GPIO, data); return 0; } static int adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost) { u32 data; u32 i2c_data; unsigned int ret; if (i2c_unlock(hw)) return -1; do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); /* i2c ready poll */ /* set i2c access mode as Direct Control */ hw_write_pci(hw, 0xEC, 0x05); data = hw_read_20kx(hw, GPIO); switch (type) { case ADC_MICIN: data |= ((0x1 << 7) | (0x1 << 8)); i2c_data = 0x1; /* Mic-in */ break; case ADC_LINEIN: data &= ~(0x1 << 7); data |= (0x1 << 8); i2c_data = 0x2; /* Line-in */ break; case ADC_NONE: data &= ~(0x1 << 8); i2c_data = 0x0; /* set to Digital */ break; default: i2c_lock(hw); return -1; } hw_write_20kx(hw, GPIO, data); i2c_write(hw, 0x001a0080, 0x2a, i2c_data); if (boost) { i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ } else { i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ } i2c_lock(hw); return 0; } static int adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost) { u32 data; u32 i2c_data; unsigned int ret; if (i2c_unlock(hw)) return -1; do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); /* i2c ready poll */ /* set i2c access mode as Direct Control */ hw_write_pci(hw, 0xEC, 0x05); data = hw_read_20kx(hw, GPIO); switch (type) { case ADC_MICIN: data |= (0x1 << 7); i2c_data = 0x1; /* Mic-in */ break; case ADC_LINEIN: data &= ~(0x1 << 7); i2c_data = 0x2; /* Line-in */ break; default: i2c_lock(hw); return -1; } hw_write_20kx(hw, GPIO, data); i2c_write(hw, 0x001a0080, 0x2a, i2c_data); if (boost) { i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ } else { i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ } i2c_lock(hw); return 0; } static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) { int state = type == ADC_MICIN; switch (hw->model) { case CTSB055X: return adc_input_select_SB055x(hw, type, state); case CTSB073X: return adc_input_select_hendrix(hw, type, state); case CTUAA: return adc_input_select_hendrix(hw, type, state); default: return adc_input_select_SBx(hw, type, state); } } static int adc_init_SB055x(struct hw *hw, int input, int mic20db) { return adc_input_select_SB055x(hw, input, mic20db); } static int adc_init_SBx(struct hw *hw, int input, int mic20db) { u16 gpioorg; u16 input_source; u32 adcdata; unsigned int ret; input_source = 0x100; /* default to analog */ switch (input) { case ADC_MICIN: adcdata = 0x1; input_source = 0x180; /* set GPIO7 to select Mic */ break; case ADC_LINEIN: adcdata = 0x2; break; case ADC_VIDEO: adcdata = 0x4; break; case ADC_AUX: adcdata = 0x8; break; case ADC_NONE: adcdata = 0x0; input_source = 0x0; /* set to Digital */ break; default: adcdata = 0x0; break; } if (i2c_unlock(hw)) return -1; do { ret = hw_read_pci(hw, 0xEC); } while (!(ret & 0x800000)); /* i2c ready poll */ hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ i2c_write(hw, 0x001a0080, 0x0e, 0x08); i2c_write(hw, 0x001a0080, 0x18, 0x0a); i2c_write(hw, 0x001a0080, 0x28, 0x86); i2c_write(hw, 0x001a0080, 0x2a, adcdata); if (mic20db) { i2c_write(hw, 0x001a0080, 0x1c, 0xf7); i2c_write(hw, 0x001a0080, 0x1e, 0xf7); } else { i2c_write(hw, 0x001a0080, 0x1c, 0xcf); i2c_write(hw, 0x001a0080, 0x1e, 0xcf); } if (!(hw_read_20kx(hw, ID0) & 0x100)) i2c_write(hw, 0x001a0080, 0x16, 0x26); i2c_lock(hw); gpioorg = (u16)hw_read_20kx(hw, GPIO); gpioorg &= 0xfe7f; gpioorg |= input_source; hw_write_20kx(hw, GPIO, gpioorg); return 0; } static int hw_adc_init(struct hw *hw, const struct adc_conf *info) { if (hw->model == CTSB055X) return adc_init_SB055x(hw, info->input, info->mic20db); else return adc_init_SBx(hw, info->input, info->mic20db); } static struct capabilities hw_capabilities(struct hw *hw) { struct capabilities cap; /* SB073x and Vista compatible cards have no digit IO switch */ cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA); cap.dedicated_mic = 0; cap.output_switch = 0; cap.mic_source_switch = 0; return cap; } #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) #define UAA_CFG_PWRSTATUS 0x44 #define UAA_CFG_SPACE_FLAG 0xA0 #define UAA_CORE_CHANGE 0x3FFC static int uaa_to_xfi(struct pci_dev *pci) { unsigned int bar0, bar1, bar2, bar3, bar4, bar5; unsigned int cmd, irq, cl_size, l_timer, pwr; unsigned int is_uaa; unsigned int data[4] = {0}; unsigned int io_base; void __iomem *mem_base; int i; const u32 CTLX = CTLBITS('C', 'T', 'L', 'X'); const u32 CTL_ = CTLBITS('C', 'T', 'L', '-'); const u32 CTLF = CTLBITS('C', 'T', 'L', 'F'); const u32 CTLi = CTLBITS('C', 'T', 'L', 'i'); const u32 CTLA = CTLBITS('C', 'T', 'L', 'A'); const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z'); const u32 CTLL = CTLBITS('C', 'T', 'L', 'L'); /* By default, Hendrix card UAA Bar0 should be using memory... */ io_base = pci_resource_start(pci, 0); mem_base = ioremap(io_base, pci_resource_len(pci, 0)); if (!mem_base) return -ENOENT; /* Read current mode from Mode Change Register */ for (i = 0; i < 4; i++) data[i] = readl(mem_base + UAA_CORE_CHANGE); /* Determine current mode... */ if (data[0] == CTLA) { is_uaa = ((data[1] == CTLZ && data[2] == CTLL && data[3] == CTLA) || (data[1] == CTLA && data[2] == CTLZ && data[3] == CTLL)); } else if (data[0] == CTLZ) { is_uaa = (data[1] == CTLL && data[2] == CTLA && data[3] == CTLA); } else if (data[0] == CTLL) { is_uaa = (data[1] == CTLA && data[2] == CTLA && data[3] == CTLZ); } else { is_uaa = 0; } if (!is_uaa) { /* Not in UAA mode currently. Return directly. */ iounmap(mem_base); return 0; } pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0); pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1); pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2); pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3); pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4); pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5); pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq); pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size); pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer); pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr); pci_read_config_dword(pci, PCI_COMMAND, &cmd); /* Set up X-Fi core PCI configuration space. */ /* Switch to X-Fi config space with BAR0 exposed. */ pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321); /* Copy UAA's BAR5 into X-Fi BAR0 */ pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5); /* Switch to X-Fi config space without BAR0 exposed. */ pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678); pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1); pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2); pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3); pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4); pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq); pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size); pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer); pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr); pci_write_config_dword(pci, PCI_COMMAND, cmd); /* Switch to X-Fi mode */ writel(CTLX, (mem_base + UAA_CORE_CHANGE)); writel(CTL_, (mem_base + UAA_CORE_CHANGE)); writel(CTLF, (mem_base + UAA_CORE_CHANGE)); writel(CTLi, (mem_base + UAA_CORE_CHANGE)); iounmap(mem_base); return 0; } static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id) { struct hw *hw = dev_id; unsigned int status; status = hw_read_20kx(hw, GIP); if (!status) return IRQ_NONE; if (hw->irq_callback) hw->irq_callback(hw->irq_callback_data, status); hw_write_20kx(hw, GIP, status); return IRQ_HANDLED; } static int hw_card_start(struct hw *hw) { int err; struct pci_dev *pci = hw->pci; const unsigned int dma_bits = BITS_PER_LONG; err = pci_enable_device(pci); if (err < 0) return err; /* Set DMA transfer mask */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); if (!hw->io_base) { err = pci_request_regions(pci, "XFi"); if (err < 0) goto error1; if (hw->model == CTUAA) hw->io_base = pci_resource_start(pci, 5); else hw->io_base = pci_resource_start(pci, 0); } /* Switch to X-Fi mode from UAA mode if needed */ if (hw->model == CTUAA) { err = uaa_to_xfi(pci); if (err) goto error2; } if (hw->irq < 0) { err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { dev_err(hw->card->dev, "XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; hw->card->sync_irq = hw->irq; } pci_set_master(pci); return 0; error2: pci_release_regions(pci); hw->io_base = 0; error1: pci_disable_device(pci); return err; } static int hw_card_stop(struct hw *hw) { unsigned int data; /* disable transport bus master and queueing of request */ hw_write_20kx(hw, TRNCTL, 0x00); /* disable pll */ data = hw_read_20kx(hw, PLLCTL); hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); return 0; } static int hw_card_shutdown(struct hw *hw) { if (hw->irq >= 0) free_irq(hw->irq, hw); hw->irq = -1; iounmap(hw->mem_base); hw->mem_base = NULL; if (hw->io_base) pci_release_regions(hw->pci); hw->io_base = 0; pci_disable_device(hw->pci); return 0; } static int hw_card_init(struct hw *hw, struct card_conf *info) { int err; unsigned int gctl; u32 data; struct dac_conf dac_info = {0}; struct adc_conf adc_info = {0}; struct daio_conf daio_info = {0}; struct trn_conf trn_info = {0}; /* Get PCI io port base address and do Hendrix switch if needed. */ err = hw_card_start(hw); if (err) return err; /* PLL init */ err = hw_pll_init(hw, info->rsr); if (err < 0) return err; /* kick off auto-init */ err = hw_auto_init(hw); if (err < 0) return err; /* Enable audio ring */ gctl = hw_read_20kx(hw, GCTL); set_field(&gctl, GCTL_EAC, 1); set_field(&gctl, GCTL_DBP, 1); set_field(&gctl, GCTL_TBP, 1); set_field(&gctl, GCTL_FBP, 1); set_field(&gctl, GCTL_ET, 1); hw_write_20kx(hw, GCTL, gctl); mdelay(10); /* Reset all global pending interrupts */ hw_write_20kx(hw, GIE, 0); /* Reset all SRC pending interrupts */ hw_write_20kx(hw, SRCIP, 0); msleep(30); /* Detect the card ID and configure GPIO accordingly. */ switch (hw->model) { case CTSB055X: hw_write_20kx(hw, GPIOCTL, 0x13fe); break; case CTSB073X: hw_write_20kx(hw, GPIOCTL, 0x00e6); break; case CTUAA: hw_write_20kx(hw, GPIOCTL, 0x00c2); break; default: hw_write_20kx(hw, GPIOCTL, 0x01e6); break; } trn_info.vm_pgt_phys = info->vm_pgt_phys; err = hw_trn_init(hw, &trn_info); if (err < 0) return err; daio_info.msr = info->msr; err = hw_daio_init(hw, &daio_info); if (err < 0) return err; dac_info.msr = info->msr; err = hw_dac_init(hw, &dac_info); if (err < 0) return err; adc_info.msr = info->msr; adc_info.input = ADC_LINEIN; adc_info.mic20db = 0; err = hw_adc_init(hw, &adc_info); if (err < 0) return err; data = hw_read_20kx(hw, SRCMCTL); data |= 0x1; /* Enables input from the audio ring */ hw_write_20kx(hw, SRCMCTL, data); return 0; } #ifdef CONFIG_PM_SLEEP static int hw_suspend(struct hw *hw) { struct pci_dev *pci = hw->pci; hw_card_stop(hw); if (hw->model == CTUAA) { /* Switch to UAA config space. */ pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0); } return 0; } static int hw_resume(struct hw *hw, struct card_conf *info) { /* Re-initialize card hardware. */ return hw_card_init(hw, info); } #endif static u32 hw_read_20kx(struct hw *hw, u32 reg) { u32 value; unsigned long flags; spin_lock_irqsave( &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); outl(reg, hw->io_base + 0x0); value = inl(hw->io_base + 0x4); spin_unlock_irqrestore( &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); return value; } static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) { unsigned long flags; spin_lock_irqsave( &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); outl(reg, hw->io_base + 0x0); outl(data, hw->io_base + 0x4); spin_unlock_irqrestore( &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); } static u32 hw_read_pci(struct hw *hw, u32 reg) { u32 value; unsigned long flags; spin_lock_irqsave( &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); outl(reg, hw->io_base + 0x10); value = inl(hw->io_base + 0x14); spin_unlock_irqrestore( &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); return value; } static void hw_write_pci(struct hw *hw, u32 reg, u32 data) { unsigned long flags; spin_lock_irqsave( &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); outl(reg, hw->io_base + 0x10); outl(data, hw->io_base + 0x14); spin_unlock_irqrestore( &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); } static const struct hw ct20k1_preset = { .irq = -1, .card_init = hw_card_init, .card_stop = hw_card_stop, .pll_init = hw_pll_init, .is_adc_source_selected = hw_is_adc_input_selected, .select_adc_source = hw_adc_input_select, .capabilities = hw_capabilities, #ifdef CONFIG_PM_SLEEP .suspend = hw_suspend, .resume = hw_resume, #endif .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk, .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk, .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk, .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk, .src_set_state = src_set_state, .src_set_bm = src_set_bm, .src_set_rsr = src_set_rsr, .src_set_sf = src_set_sf, .src_set_wr = src_set_wr, .src_set_pm = src_set_pm, .src_set_rom = src_set_rom, .src_set_vo = src_set_vo, .src_set_st = src_set_st, .src_set_ie = src_set_ie, .src_set_ilsz = src_set_ilsz, .src_set_bp = src_set_bp, .src_set_cisz = src_set_cisz, .src_set_ca = src_set_ca, .src_set_sa = src_set_sa, .src_set_la = src_set_la, .src_set_pitch = src_set_pitch, .src_set_dirty = src_set_dirty, .src_set_clear_zbufs = src_set_clear_zbufs, .src_set_dirty_all = src_set_dirty_all, .src_commit_write = src_commit_write, .src_get_ca = src_get_ca, .src_get_dirty = src_get_dirty, .src_dirty_conj_mask = src_dirty_conj_mask, .src_mgr_enbs_src = src_mgr_enbs_src, .src_mgr_enb_src = src_mgr_enb_src, .src_mgr_dsb_src = src_mgr_dsb_src, .src_mgr_commit_write = src_mgr_commit_write, .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk, .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk, .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc, .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser, .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt, .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr, .srcimp_mgr_commit_write = srcimp_mgr_commit_write, .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk, .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk, .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk, .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk, .amixer_set_mode = amixer_set_mode, .amixer_set_iv = amixer_set_iv, .amixer_set_x = amixer_set_x, .amixer_set_y = amixer_set_y, .amixer_set_sadr = amixer_set_sadr, .amixer_set_se = amixer_set_se, .amixer_set_dirty = amixer_set_dirty, .amixer_set_dirty_all = amixer_set_dirty_all, .amixer_commit_write = amixer_commit_write, .amixer_get_y = amixer_get_y, .amixer_get_dirty = amixer_get_dirty, .dai_get_ctrl_blk = dai_get_ctrl_blk, .dai_put_ctrl_blk = dai_put_ctrl_blk, .dai_srt_set_srco = dai_srt_set_srcr, .dai_srt_set_srcm = dai_srt_set_srcl, .dai_srt_set_rsr = dai_srt_set_rsr, .dai_srt_set_drat = dai_srt_set_drat, .dai_srt_set_ec = dai_srt_set_ec, .dai_srt_set_et = dai_srt_set_et, .dai_commit_write = dai_commit_write, .dao_get_ctrl_blk = dao_get_ctrl_blk, .dao_put_ctrl_blk = dao_put_ctrl_blk, .dao_set_spos = dao_set_spos, .dao_commit_write = dao_commit_write, .dao_get_spos = dao_get_spos, .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk, .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk, .daio_mgr_enb_dai = daio_mgr_enb_dai, .daio_mgr_dsb_dai = daio_mgr_dsb_dai, .daio_mgr_enb_dao = daio_mgr_enb_dao, .daio_mgr_dsb_dao = daio_mgr_dsb_dao, .daio_mgr_dao_init = daio_mgr_dao_init, .daio_mgr_set_imaparc = daio_mgr_set_imaparc, .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt, .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr, .daio_mgr_commit_write = daio_mgr_commit_write, .set_timer_irq = set_timer_irq, .set_timer_tick = set_timer_tick, .get_wc = get_wc, }; int create_20k1_hw_obj(struct hw **rhw) { struct hw20k1 *hw20k1; *rhw = NULL; hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL); if (!hw20k1) return -ENOMEM; spin_lock_init(&hw20k1->reg_20k1_lock); spin_lock_init(&hw20k1->reg_pci_lock); hw20k1->hw = ct20k1_preset; *rhw = &hw20k1->hw; return 0; } int destroy_20k1_hw_obj(struct hw *hw) { if (hw->io_base) hw_card_shutdown(hw); kfree(container_of(hw, struct hw20k1, hw)); return 0; }
linux-master
sound/pci/ctxfi/cthw20k1.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. * * @File ctresource.c * * @Brief * This file contains the implementation of some generic helper functions. * * @Author Liu Chun * @Date May 15 2008 */ #include "ctresource.h" #include "cthardware.h" #include <linux/err.h> #include <linux/slab.h> #define AUDIO_SLOT_BLOCK_NUM 256 /* Resource allocation based on bit-map management mechanism */ static int get_resource(u8 *rscs, unsigned int amount, unsigned int multi, unsigned int *ridx) { int i, j, k, n; /* Check whether there are sufficient resources to meet request. */ for (i = 0, n = multi; i < amount; i++) { j = i / 8; k = i % 8; if (rscs[j] & ((u8)1 << k)) { n = multi; continue; } if (!(--n)) break; /* found sufficient contiguous resources */ } if (i >= amount) { /* Can not find sufficient contiguous resources */ return -ENOENT; } /* Mark the contiguous bits in resource bit-map as used */ for (n = multi; n > 0; n--) { j = i / 8; k = i % 8; rscs[j] |= ((u8)1 << k); i--; } *ridx = i + 1; return 0; } static int put_resource(u8 *rscs, unsigned int multi, unsigned int idx) { unsigned int i, j, k, n; /* Mark the contiguous bits in resource bit-map as used */ for (n = multi, i = idx; n > 0; n--) { j = i / 8; k = i % 8; rscs[j] &= ~((u8)1 << k); i++; } return 0; } int mgr_get_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int *ridx) { int err; if (n > mgr->avail) return -ENOENT; err = get_resource(mgr->rscs, mgr->amount, n, ridx); if (!err) mgr->avail -= n; return err; } int mgr_put_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int idx) { put_resource(mgr->rscs, n, idx); mgr->avail += n; return 0; } static const unsigned char offset_in_audio_slot_block[NUM_RSCTYP] = { /* SRC channel is at Audio Ring slot 1 every 16 slots. */ [SRC] = 0x1, [AMIXER] = 0x4, [SUM] = 0xc, }; static int rsc_index(const struct rsc *rsc) { return rsc->conj; } static int audio_ring_slot(const struct rsc *rsc) { return (rsc->conj << 4) + offset_in_audio_slot_block[rsc->type]; } static void rsc_next_conj(struct rsc *rsc) { unsigned int i; for (i = 0; (i < 8) && (!(rsc->msr & (0x1 << i))); ) i++; rsc->conj += (AUDIO_SLOT_BLOCK_NUM >> i); } static void rsc_master(struct rsc *rsc) { rsc->conj = rsc->idx; } static const struct rsc_ops rsc_generic_ops = { .index = rsc_index, .output_slot = audio_ring_slot, .master = rsc_master, .next_conj = rsc_next_conj, }; int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, struct hw *hw) { int err = 0; rsc->idx = idx; rsc->conj = idx; rsc->type = type; rsc->msr = msr; rsc->hw = hw; rsc->ops = &rsc_generic_ops; if (!hw) { rsc->ctrl_blk = NULL; return 0; } switch (type) { case SRC: err = hw->src_rsc_get_ctrl_blk(&rsc->ctrl_blk); break; case AMIXER: err = hw->amixer_rsc_get_ctrl_blk(&rsc->ctrl_blk); break; case SRCIMP: case SUM: case DAIO: break; default: dev_err(((struct hw *)hw)->card->dev, "Invalid resource type value %d!\n", type); return -EINVAL; } if (err) { dev_err(((struct hw *)hw)->card->dev, "Failed to get resource control block!\n"); return err; } return 0; } int rsc_uninit(struct rsc *rsc) { if ((NULL != rsc->hw) && (NULL != rsc->ctrl_blk)) { switch (rsc->type) { case SRC: rsc->hw->src_rsc_put_ctrl_blk(rsc->ctrl_blk); break; case AMIXER: rsc->hw->amixer_rsc_put_ctrl_blk(rsc->ctrl_blk); break; case SUM: case DAIO: break; default: dev_err(((struct hw *)rsc->hw)->card->dev, "Invalid resource type value %d!\n", rsc->type); break; } rsc->hw = rsc->ctrl_blk = NULL; } rsc->idx = rsc->conj = 0; rsc->type = NUM_RSCTYP; rsc->msr = 0; return 0; } int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type, unsigned int amount, struct hw *hw) { int err = 0; mgr->type = NUM_RSCTYP; mgr->rscs = kzalloc(DIV_ROUND_UP(amount, 8), GFP_KERNEL); if (!mgr->rscs) return -ENOMEM; switch (type) { case SRC: err = hw->src_mgr_get_ctrl_blk(&mgr->ctrl_blk); break; case SRCIMP: err = hw->srcimp_mgr_get_ctrl_blk(&mgr->ctrl_blk); break; case AMIXER: err = hw->amixer_mgr_get_ctrl_blk(&mgr->ctrl_blk); break; case DAIO: err = hw->daio_mgr_get_ctrl_blk(hw, &mgr->ctrl_blk); break; case SUM: break; default: dev_err(hw->card->dev, "Invalid resource type value %d!\n", type); err = -EINVAL; goto error; } if (err) { dev_err(hw->card->dev, "Failed to get manager control block!\n"); goto error; } mgr->type = type; mgr->avail = mgr->amount = amount; mgr->hw = hw; return 0; error: kfree(mgr->rscs); return err; } int rsc_mgr_uninit(struct rsc_mgr *mgr) { kfree(mgr->rscs); mgr->rscs = NULL; if ((NULL != mgr->hw) && (NULL != mgr->ctrl_blk)) { switch (mgr->type) { case SRC: mgr->hw->src_mgr_put_ctrl_blk(mgr->ctrl_blk); break; case SRCIMP: mgr->hw->srcimp_mgr_put_ctrl_blk(mgr->ctrl_blk); break; case AMIXER: mgr->hw->amixer_mgr_put_ctrl_blk(mgr->ctrl_blk); break; case DAIO: mgr->hw->daio_mgr_put_ctrl_blk(mgr->ctrl_blk); break; case SUM: break; default: dev_err(((struct hw *)mgr->hw)->card->dev, "Invalid resource type value %d!\n", mgr->type); break; } mgr->hw = mgr->ctrl_blk = NULL; } mgr->type = NUM_RSCTYP; mgr->avail = mgr->amount = 0; return 0; }
linux-master
sound/pci/ctxfi/ctresource.c
// SPDX-License-Identifier: GPL-2.0-only /* * helper functions for HDMI models (Xonar HDAV1.3/HDAV1.3 Slim) * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/pci.h> #include <linux/delay.h> #include <sound/asoundef.h> #include <sound/control.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #include "xonar.h" static void hdmi_write_command(struct oxygen *chip, u8 command, unsigned int count, const u8 *params) { unsigned int i; u8 checksum; oxygen_write_uart(chip, 0xfb); oxygen_write_uart(chip, 0xef); oxygen_write_uart(chip, command); oxygen_write_uart(chip, count); for (i = 0; i < count; ++i) oxygen_write_uart(chip, params[i]); checksum = 0xfb + 0xef + command + count; for (i = 0; i < count; ++i) checksum += params[i]; oxygen_write_uart(chip, checksum); } static void xonar_hdmi_init_commands(struct oxygen *chip, struct xonar_hdmi *hdmi) { u8 param; oxygen_reset_uart(chip); param = 0; hdmi_write_command(chip, 0x61, 1, &param); param = 1; hdmi_write_command(chip, 0x74, 1, &param); hdmi_write_command(chip, 0x54, 5, hdmi->params); } void xonar_hdmi_init(struct oxygen *chip, struct xonar_hdmi *hdmi) { hdmi->params[1] = IEC958_AES3_CON_FS_48000; hdmi->params[4] = 1; xonar_hdmi_init_commands(chip, hdmi); } void xonar_hdmi_cleanup(struct oxygen *chip) { u8 param = 0; hdmi_write_command(chip, 0x74, 1, &param); } void xonar_hdmi_resume(struct oxygen *chip, struct xonar_hdmi *hdmi) { xonar_hdmi_init_commands(chip, hdmi); } void xonar_hdmi_pcm_hardware_filter(unsigned int channel, struct snd_pcm_hardware *hardware) { if (channel == PCM_MULTICH) { hardware->rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000; hardware->rate_min = 44100; } } void xonar_set_hdmi_params(struct oxygen *chip, struct xonar_hdmi *hdmi, struct snd_pcm_hw_params *params) { hdmi->params[0] = 0; /* 1 = non-audio */ switch (params_rate(params)) { case 44100: hdmi->params[1] = IEC958_AES3_CON_FS_44100; break; case 48000: hdmi->params[1] = IEC958_AES3_CON_FS_48000; break; default: /* 96000 */ hdmi->params[1] = IEC958_AES3_CON_FS_96000; break; case 192000: hdmi->params[1] = IEC958_AES3_CON_FS_192000; break; } hdmi->params[2] = params_channels(params) / 2 - 1; if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE) hdmi->params[3] = 0; else hdmi->params[3] = 0xc0; hdmi->params[4] = 1; /* ? */ hdmi_write_command(chip, 0x54, 5, hdmi->params); } void xonar_hdmi_uart_input(struct oxygen *chip) { if (chip->uart_input_count >= 2 && chip->uart_input[chip->uart_input_count - 2] == 'O' && chip->uart_input[chip->uart_input_count - 1] == 'K') { dev_dbg(chip->card->dev, "message from HDMI chip received:\n"); print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, chip->uart_input, chip->uart_input_count); chip->uart_input_count = 0; } }
linux-master
sound/pci/oxygen/xonar_hdmi.c
// SPDX-License-Identifier: GPL-2.0-only /* * card driver for models with CS4398/CS4362A DACs (Xonar D1/DX) * * Copyright (c) Clemens Ladisch <[email protected]> */ /* * Xonar D1/DX * ----------- * * CMI8788: * * I²C <-> CS4398 (addr 1001111) (front) * <-> CS4362A (addr 0011000) (surround, center/LFE, back) * * GPI 0 <- external power present (DX only) * * GPIO 0 -> enable output to speakers * GPIO 1 -> route output to front panel * GPIO 2 -> M0 of CS5361 * GPIO 3 -> M1 of CS5361 * GPIO 6 -> ? * GPIO 7 -> ? * GPIO 8 -> route input jack to line-in (0) or mic-in (1) * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * MIC_IN <- mic * FMIC_IN <- front mic * * GPO 0 -> route line-in (0) or AC97 output (1) to CS5361 input */ #include <linux/pci.h> #include <linux/delay.h> #include <sound/ac97_codec.h> #include <sound/control.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #include "xonar.h" #include "cm9780.h" #include "cs4398.h" #include "cs4362a.h" #define GPI_EXT_POWER 0x01 #define GPIO_D1_OUTPUT_ENABLE 0x0001 #define GPIO_D1_FRONT_PANEL 0x0002 #define GPIO_D1_MAGIC 0x00c0 #define GPIO_D1_INPUT_ROUTE 0x0100 #define I2C_DEVICE_CS4398 0x9e /* 10011, AD1=1, AD0=1, /W=0 */ #define I2C_DEVICE_CS4362A 0x30 /* 001100, AD0=0, /W=0 */ struct xonar_cs43xx { struct xonar_generic generic; u8 cs4398_regs[8]; u8 cs4362a_regs[15]; }; static void cs4398_write(struct oxygen *chip, u8 reg, u8 value) { struct xonar_cs43xx *data = chip->model_data; oxygen_write_i2c(chip, I2C_DEVICE_CS4398, reg, value); if (reg < ARRAY_SIZE(data->cs4398_regs)) data->cs4398_regs[reg] = value; } static void cs4398_write_cached(struct oxygen *chip, u8 reg, u8 value) { struct xonar_cs43xx *data = chip->model_data; if (value != data->cs4398_regs[reg]) cs4398_write(chip, reg, value); } static void cs4362a_write(struct oxygen *chip, u8 reg, u8 value) { struct xonar_cs43xx *data = chip->model_data; oxygen_write_i2c(chip, I2C_DEVICE_CS4362A, reg, value); if (reg < ARRAY_SIZE(data->cs4362a_regs)) data->cs4362a_regs[reg] = value; } static void cs4362a_write_cached(struct oxygen *chip, u8 reg, u8 value) { struct xonar_cs43xx *data = chip->model_data; if (value != data->cs4362a_regs[reg]) cs4362a_write(chip, reg, value); } static void cs43xx_registers_init(struct oxygen *chip) { struct xonar_cs43xx *data = chip->model_data; unsigned int i; /* set CPEN (control port mode) and power down */ cs4398_write(chip, 8, CS4398_CPEN | CS4398_PDN); cs4362a_write(chip, 0x01, CS4362A_PDN | CS4362A_CPEN); /* configure */ cs4398_write(chip, 2, data->cs4398_regs[2]); cs4398_write(chip, 3, CS4398_ATAPI_B_R | CS4398_ATAPI_A_L); cs4398_write(chip, 4, data->cs4398_regs[4]); cs4398_write(chip, 5, data->cs4398_regs[5]); cs4398_write(chip, 6, data->cs4398_regs[6]); cs4398_write(chip, 7, data->cs4398_regs[7]); cs4362a_write(chip, 0x02, CS4362A_DIF_LJUST); cs4362a_write(chip, 0x03, CS4362A_MUTEC_6 | CS4362A_AMUTE | CS4362A_RMP_UP | CS4362A_ZERO_CROSS | CS4362A_SOFT_RAMP); cs4362a_write(chip, 0x04, data->cs4362a_regs[0x04]); cs4362a_write(chip, 0x05, 0); for (i = 6; i <= 14; ++i) cs4362a_write(chip, i, data->cs4362a_regs[i]); /* clear power down */ cs4398_write(chip, 8, CS4398_CPEN); cs4362a_write(chip, 0x01, CS4362A_CPEN); } static void xonar_d1_init(struct oxygen *chip) { struct xonar_cs43xx *data = chip->model_data; data->generic.anti_pop_delay = 800; data->generic.output_enable_bit = GPIO_D1_OUTPUT_ENABLE; data->cs4398_regs[2] = CS4398_FM_SINGLE | CS4398_DEM_NONE | CS4398_DIF_LJUST; data->cs4398_regs[4] = CS4398_MUTEP_LOW | CS4398_MUTE_B | CS4398_MUTE_A | CS4398_PAMUTE; data->cs4398_regs[5] = 60 * 2; data->cs4398_regs[6] = 60 * 2; data->cs4398_regs[7] = CS4398_RMP_DN | CS4398_RMP_UP | CS4398_ZERO_CROSS | CS4398_SOFT_RAMP; data->cs4362a_regs[4] = CS4362A_RMP_DN | CS4362A_DEM_NONE; data->cs4362a_regs[6] = CS4362A_FM_SINGLE | CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L; data->cs4362a_regs[7] = 60 | CS4362A_MUTE; data->cs4362a_regs[8] = 60 | CS4362A_MUTE; data->cs4362a_regs[9] = data->cs4362a_regs[6]; data->cs4362a_regs[10] = 60 | CS4362A_MUTE; data->cs4362a_regs[11] = 60 | CS4362A_MUTE; data->cs4362a_regs[12] = data->cs4362a_regs[6]; data->cs4362a_regs[13] = 60 | CS4362A_MUTE; data->cs4362a_regs[14] = 60 | CS4362A_MUTE; oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_FAST); cs43xx_registers_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D1_FRONT_PANEL | GPIO_D1_MAGIC | GPIO_D1_INPUT_ROUTE); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_D1_FRONT_PANEL | GPIO_D1_INPUT_ROUTE); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "CS4398"); snd_component_add(chip->card, "CS4362A"); snd_component_add(chip->card, "CS5361"); } static void xonar_dx_init(struct oxygen *chip) { struct xonar_cs43xx *data = chip->model_data; data->generic.ext_power_reg = OXYGEN_GPI_DATA; data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK; data->generic.ext_power_bit = GPI_EXT_POWER; xonar_init_ext_power(chip); xonar_d1_init(chip); } static void xonar_d1_cleanup(struct oxygen *chip) { xonar_disable_output(chip); cs4362a_write(chip, 0x01, CS4362A_PDN | CS4362A_CPEN); oxygen_clear_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC); } static void xonar_d1_suspend(struct oxygen *chip) { xonar_d1_cleanup(chip); } static void xonar_d1_resume(struct oxygen *chip) { oxygen_set_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC); msleep(1); cs43xx_registers_init(chip); xonar_enable_output(chip); } static void set_cs43xx_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct xonar_cs43xx *data = chip->model_data; u8 cs4398_fm, cs4362a_fm; if (params_rate(params) <= 50000) { cs4398_fm = CS4398_FM_SINGLE; cs4362a_fm = CS4362A_FM_SINGLE; } else if (params_rate(params) <= 100000) { cs4398_fm = CS4398_FM_DOUBLE; cs4362a_fm = CS4362A_FM_DOUBLE; } else { cs4398_fm = CS4398_FM_QUAD; cs4362a_fm = CS4362A_FM_QUAD; } cs4398_fm |= CS4398_DEM_NONE | CS4398_DIF_LJUST; cs4398_write_cached(chip, 2, cs4398_fm); cs4362a_fm |= data->cs4362a_regs[6] & ~CS4362A_FM_MASK; cs4362a_write_cached(chip, 6, cs4362a_fm); cs4362a_write_cached(chip, 12, cs4362a_fm); cs4362a_fm &= CS4362A_FM_MASK; cs4362a_fm |= data->cs4362a_regs[9] & ~CS4362A_FM_MASK; cs4362a_write_cached(chip, 9, cs4362a_fm); } static void update_cs4362a_volumes(struct oxygen *chip) { unsigned int i; u8 mute; mute = chip->dac_mute ? CS4362A_MUTE : 0; for (i = 0; i < 6; ++i) cs4362a_write_cached(chip, 7 + i + i / 2, (127 - chip->dac_volume[2 + i]) | mute); } static void update_cs43xx_volume(struct oxygen *chip) { cs4398_write_cached(chip, 5, (127 - chip->dac_volume[0]) * 2); cs4398_write_cached(chip, 6, (127 - chip->dac_volume[1]) * 2); update_cs4362a_volumes(chip); } static void update_cs43xx_mute(struct oxygen *chip) { u8 reg; reg = CS4398_MUTEP_LOW | CS4398_PAMUTE; if (chip->dac_mute) reg |= CS4398_MUTE_B | CS4398_MUTE_A; cs4398_write_cached(chip, 4, reg); update_cs4362a_volumes(chip); } static void update_cs43xx_center_lfe_mix(struct oxygen *chip, bool mixed) { struct xonar_cs43xx *data = chip->model_data; u8 reg; reg = data->cs4362a_regs[9] & ~CS4362A_ATAPI_MASK; if (mixed) reg |= CS4362A_ATAPI_B_LR | CS4362A_ATAPI_A_LR; else reg |= CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L; cs4362a_write_cached(chip, 9, reg); } static const struct snd_kcontrol_new front_panel_switch = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Front Panel Playback Switch", .info = snd_ctl_boolean_mono_info, .get = xonar_gpio_bit_switch_get, .put = xonar_gpio_bit_switch_put, .private_value = GPIO_D1_FRONT_PANEL, }; static int rolloff_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "Fast Roll-off", "Slow Roll-off" }; return snd_ctl_enum_info(info, 1, 2, names); } static int rolloff_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_cs43xx *data = chip->model_data; value->value.enumerated.item[0] = (data->cs4398_regs[7] & CS4398_FILT_SEL) != 0; return 0; } static int rolloff_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_cs43xx *data = chip->model_data; int changed; u8 reg; mutex_lock(&chip->mutex); reg = data->cs4398_regs[7]; if (value->value.enumerated.item[0]) reg |= CS4398_FILT_SEL; else reg &= ~CS4398_FILT_SEL; changed = reg != data->cs4398_regs[7]; if (changed) { cs4398_write(chip, 7, reg); if (reg & CS4398_FILT_SEL) reg = data->cs4362a_regs[0x04] | CS4362A_FILT_SEL; else reg = data->cs4362a_regs[0x04] & ~CS4362A_FILT_SEL; cs4362a_write(chip, 0x04, reg); } mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new rolloff_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DAC Filter Playback Enum", .info = rolloff_info, .get = rolloff_get, .put = rolloff_put, }; static void xonar_d1_line_mic_ac97_switch(struct oxygen *chip, unsigned int reg, unsigned int mute) { if (reg == AC97_LINE) { spin_lock_irq(&chip->reg_lock); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, mute ? GPIO_D1_INPUT_ROUTE : 0, GPIO_D1_INPUT_ROUTE); spin_unlock_irq(&chip->reg_lock); } } static const DECLARE_TLV_DB_SCALE(cs4362a_db_scale, -6000, 100, 0); static int xonar_d1_mixer_init(struct oxygen *chip) { int err; err = snd_ctl_add(chip->card, snd_ctl_new1(&front_panel_switch, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip)); if (err < 0) return err; return 0; } static void dump_cs4362a_registers(struct xonar_cs43xx *data, struct snd_info_buffer *buffer) { unsigned int i; snd_iprintf(buffer, "\nCS4362A:"); for (i = 1; i <= 14; ++i) snd_iprintf(buffer, " %02x", data->cs4362a_regs[i]); snd_iprintf(buffer, "\n"); } static void dump_d1_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct xonar_cs43xx *data = chip->model_data; unsigned int i; snd_iprintf(buffer, "\nCS4398: 7?"); for (i = 2; i < 8; ++i) snd_iprintf(buffer, " %02x", data->cs4398_regs[i]); snd_iprintf(buffer, "\n"); dump_cs4362a_registers(data, buffer); } static const struct oxygen_model model_xonar_d1 = { .longname = "Asus Virtuoso 100", .chip = "AV200", .init = xonar_d1_init, .mixer_init = xonar_d1_mixer_init, .cleanup = xonar_d1_cleanup, .suspend = xonar_d1_suspend, .resume = xonar_d1_resume, .set_dac_params = set_cs43xx_params, .set_adc_params = xonar_set_cs53x1_params, .update_dac_volume = update_cs43xx_volume, .update_dac_mute = update_cs43xx_mute, .update_center_lfe_mix = update_cs43xx_center_lfe_mix, .ac97_switch = xonar_d1_line_mic_ac97_switch, .dump_registers = dump_d1_registers, .dac_tlv = cs4362a_db_scale, .model_data_size = sizeof(struct xonar_cs43xx), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF | AC97_FMIC_SWITCH, .dac_channels_pcm = 8, .dac_channels_mixer = 8, .dac_volume_min = 127 - 60, .dac_volume_max = 127, .function_flags = OXYGEN_FUNCTION_2WIRE, .dac_mclks = OXYGEN_MCLKS(256, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 128, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; int get_xonar_cs43xx_model(struct oxygen *chip, const struct pci_device_id *id) { switch (id->subdevice) { case 0x834f: chip->model = model_xonar_d1; chip->model.shortname = "Xonar D1"; break; case 0x8275: case 0x8327: chip->model = model_xonar_d1; chip->model.shortname = "Xonar DX"; chip->model.init = xonar_dx_init; break; default: return -EINVAL; } return 0; }
linux-master
sound/pci/oxygen/xonar_cs43xx.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver - PCM code * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/pci.h> #include <sound/control.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include "oxygen.h" /* most DMA channels have a 16-bit counter for 32-bit words */ #define BUFFER_BYTES_MAX ((1 << 16) * 4) /* the multichannel DMA channel has a 24-bit counter */ #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4) #define FIFO_BYTES 256 #define FIFO_BYTES_MULTICH 1024 #define PERIOD_BYTES_MIN 64 #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2) #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024) static const struct snd_pcm_hardware oxygen_stereo_hardware = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000, .rate_min = 32000, .rate_max = 192000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = BUFFER_BYTES_MAX, .period_bytes_min = PERIOD_BYTES_MIN, .period_bytes_max = BUFFER_BYTES_MAX, .periods_min = 1, .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN, .fifo_size = FIFO_BYTES, }; static const struct snd_pcm_hardware oxygen_multichannel_hardware = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000, .rate_min = 32000, .rate_max = 192000, .channels_min = 2, .channels_max = 8, .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH, .period_bytes_min = PERIOD_BYTES_MIN, .period_bytes_max = BUFFER_BYTES_MAX_MULTICH, .periods_min = 1, .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN, .fifo_size = FIFO_BYTES_MULTICH, }; static const struct snd_pcm_hardware oxygen_ac97_hardware = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_48000, .rate_min = 48000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = BUFFER_BYTES_MAX, .period_bytes_min = PERIOD_BYTES_MIN, .period_bytes_max = BUFFER_BYTES_MAX, .periods_min = 1, .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN, .fifo_size = FIFO_BYTES, }; static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = { [PCM_A] = &oxygen_stereo_hardware, [PCM_B] = &oxygen_stereo_hardware, [PCM_C] = &oxygen_stereo_hardware, [PCM_SPDIF] = &oxygen_stereo_hardware, [PCM_MULTICH] = &oxygen_multichannel_hardware, [PCM_AC97] = &oxygen_ac97_hardware, }; static inline unsigned int oxygen_substream_channel(struct snd_pcm_substream *substream) { return (unsigned int)(uintptr_t)substream->runtime->private_data; } static int oxygen_open(struct snd_pcm_substream *substream, unsigned int channel) { struct oxygen *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; runtime->private_data = (void *)(uintptr_t)channel; if (channel == PCM_B && chip->has_ac97_1 && (chip->model.device_config & CAPTURE_2_FROM_AC97_1)) runtime->hw = oxygen_ac97_hardware; else runtime->hw = *oxygen_hardware[channel]; switch (channel) { case PCM_C: if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) { runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_64000); runtime->hw.rate_min = 44100; } fallthrough; case PCM_A: case PCM_B: runtime->hw.fifo_size = 0; break; case PCM_MULTICH: runtime->hw.channels_max = chip->model.dac_channels_pcm; break; } if (chip->model.pcm_hardware_filter) chip->model.pcm_hardware_filter(channel, &runtime->hw); err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32); if (err < 0) return err; err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32); if (err < 0) return err; if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) { err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); if (err < 0) return err; } if (runtime->hw.channels_max > 2) { err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); if (err < 0) return err; } snd_pcm_set_sync(substream); chip->streams[channel] = substream; mutex_lock(&chip->mutex); chip->pcm_active |= 1 << channel; if (channel == PCM_SPDIF) { chip->spdif_pcm_bits = chip->spdif_bits; chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &chip->controls[CONTROL_SPDIF_PCM]->id); } mutex_unlock(&chip->mutex); return 0; } static int oxygen_rec_a_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_A); } static int oxygen_rec_b_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_B); } static int oxygen_rec_c_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_C); } static int oxygen_spdif_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_SPDIF); } static int oxygen_multich_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_MULTICH); } static int oxygen_ac97_open(struct snd_pcm_substream *substream) { return oxygen_open(substream, PCM_AC97); } static int oxygen_close(struct snd_pcm_substream *substream) { struct oxygen *chip = snd_pcm_substream_chip(substream); unsigned int channel = oxygen_substream_channel(substream); mutex_lock(&chip->mutex); chip->pcm_active &= ~(1 << channel); if (channel == PCM_SPDIF) { chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &chip->controls[CONTROL_SPDIF_PCM]->id); } if (channel == PCM_SPDIF || channel == PCM_MULTICH) oxygen_update_spdif_source(chip); mutex_unlock(&chip->mutex); chip->streams[channel] = NULL; return 0; } static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params) { if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE) return OXYGEN_FORMAT_24; else return OXYGEN_FORMAT_16; } static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params) { switch (params_rate(hw_params)) { case 32000: return OXYGEN_RATE_32000; case 44100: return OXYGEN_RATE_44100; default: /* 48000 */ return OXYGEN_RATE_48000; case 64000: return OXYGEN_RATE_64000; case 88200: return OXYGEN_RATE_88200; case 96000: return OXYGEN_RATE_96000; case 176400: return OXYGEN_RATE_176400; case 192000: return OXYGEN_RATE_192000; } } static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params) { if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE) return OXYGEN_I2S_BITS_24; else return OXYGEN_I2S_BITS_16; } static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params) { switch (params_channels(hw_params)) { default: /* 2 */ return OXYGEN_PLAY_CHANNELS_2; case 4: return OXYGEN_PLAY_CHANNELS_4; case 6: return OXYGEN_PLAY_CHANNELS_6; case 8: return OXYGEN_PLAY_CHANNELS_8; } } static const unsigned int channel_base_registers[PCM_COUNT] = { [PCM_A] = OXYGEN_DMA_A_ADDRESS, [PCM_B] = OXYGEN_DMA_B_ADDRESS, [PCM_C] = OXYGEN_DMA_C_ADDRESS, [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS, [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS, [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS, }; static int oxygen_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); unsigned int channel = oxygen_substream_channel(substream); oxygen_write32(chip, channel_base_registers[channel], (u32)substream->runtime->dma_addr); if (channel == PCM_MULTICH) { oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT, params_buffer_bytes(hw_params) / 4 - 1); oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT, params_period_bytes(hw_params) / 4 - 1); } else { oxygen_write16(chip, channel_base_registers[channel] + 4, params_buffer_bytes(hw_params) / 4 - 1); oxygen_write16(chip, channel_base_registers[channel] + 6, params_period_bytes(hw_params) / 4 - 1); } return 0; } static u16 get_mclk(struct oxygen *chip, unsigned int channel, struct snd_pcm_hw_params *params) { unsigned int mclks, shift; if (channel == PCM_MULTICH) mclks = chip->model.dac_mclks; else mclks = chip->model.adc_mclks; if (params_rate(params) <= 48000) shift = 0; else if (params_rate(params) <= 96000) shift = 2; else shift = 4; return OXYGEN_I2S_MCLK(mclks >> shift); } static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT, OXYGEN_REC_FORMAT_A_MASK); oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, oxygen_rate(hw_params) | chip->model.adc_i2s_format | get_mclk(chip, PCM_A, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); spin_unlock_irq(&chip->reg_lock); mutex_lock(&chip->mutex); chip->model.set_adc_params(chip, hw_params); mutex_unlock(&chip->mutex); return 0; } static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int is_ac97; int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; is_ac97 = chip->has_ac97_1 && (chip->model.device_config & CAPTURE_2_FROM_AC97_1); spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT, OXYGEN_REC_FORMAT_B_MASK); if (!is_ac97) oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT, oxygen_rate(hw_params) | chip->model.adc_i2s_format | get_mclk(chip, PCM_B, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); spin_unlock_irq(&chip->reg_lock); if (!is_ac97) { mutex_lock(&chip->mutex); chip->model.set_adc_params(chip, hw_params); mutex_unlock(&chip->mutex); } return 0; } static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); bool is_spdif; int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; is_spdif = chip->model.device_config & CAPTURE_1_FROM_SPDIF; spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT, OXYGEN_REC_FORMAT_C_MASK); if (!is_spdif) oxygen_write16_masked(chip, OXYGEN_I2S_C_FORMAT, oxygen_rate(hw_params) | chip->model.adc_i2s_format | get_mclk(chip, PCM_B, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); spin_unlock_irq(&chip->reg_lock); if (!is_spdif) { mutex_lock(&chip->mutex); chip->model.set_adc_params(chip, hw_params); mutex_unlock(&chip->mutex); } return 0; } static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; mutex_lock(&chip->mutex); spin_lock_irq(&chip->reg_lock); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE); oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT, oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT, OXYGEN_SPDIF_FORMAT_MASK); oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT, OXYGEN_SPDIF_OUT_RATE_MASK); oxygen_update_spdif_source(chip); spin_unlock_irq(&chip->reg_lock); mutex_unlock(&chip->mutex); return 0; } static int oxygen_multich_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; mutex_lock(&chip->mutex); spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS, oxygen_play_channels(hw_params), OXYGEN_PLAY_CHANNELS_MASK); oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT, oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT, OXYGEN_MULTICH_FORMAT_MASK); oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT, oxygen_rate(hw_params) | chip->model.dac_i2s_format | get_mclk(chip, PCM_MULTICH, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); oxygen_update_spdif_source(chip); spin_unlock_irq(&chip->reg_lock); chip->model.set_dac_params(chip, hw_params); oxygen_update_dac_routing(chip); mutex_unlock(&chip->mutex); return 0; } static int oxygen_hw_free(struct snd_pcm_substream *substream) { struct oxygen *chip = snd_pcm_substream_chip(substream); unsigned int channel = oxygen_substream_channel(substream); unsigned int channel_mask = 1 << channel; spin_lock_irq(&chip->reg_lock); chip->interrupt_mask &= ~channel_mask; oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask); oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask); spin_unlock_irq(&chip->reg_lock); return 0; } static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream) { struct oxygen *chip = snd_pcm_substream_chip(substream); spin_lock_irq(&chip->reg_lock); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE); spin_unlock_irq(&chip->reg_lock); return oxygen_hw_free(substream); } static int oxygen_prepare(struct snd_pcm_substream *substream) { struct oxygen *chip = snd_pcm_substream_chip(substream); unsigned int channel = oxygen_substream_channel(substream); unsigned int channel_mask = 1 << channel; spin_lock_irq(&chip->reg_lock); oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask); oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask); if (substream->runtime->no_period_wakeup) chip->interrupt_mask &= ~channel_mask; else chip->interrupt_mask |= channel_mask; oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); spin_unlock_irq(&chip->reg_lock); return 0; } static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd) { struct oxygen *chip = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; unsigned int mask = 0; int pausing; switch (cmd) { case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_SUSPEND: pausing = 0; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: pausing = 1; break; default: return -EINVAL; } snd_pcm_group_for_each_entry(s, substream) { if (snd_pcm_substream_chip(s) == chip) { mask |= 1 << oxygen_substream_channel(s); snd_pcm_trigger_done(s, substream); } } spin_lock(&chip->reg_lock); if (!pausing) { if (cmd == SNDRV_PCM_TRIGGER_START) chip->pcm_running |= mask; else chip->pcm_running &= ~mask; oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running); } else { if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask); else oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask); } spin_unlock(&chip->reg_lock); return 0; } static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream) { struct oxygen *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; unsigned int channel = oxygen_substream_channel(substream); u32 curr_addr; /* no spinlock, this read should be atomic */ curr_addr = oxygen_read32(chip, channel_base_registers[channel]); return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr); } static const struct snd_pcm_ops oxygen_rec_a_ops = { .open = oxygen_rec_a_open, .close = oxygen_close, .hw_params = oxygen_rec_a_hw_params, .hw_free = oxygen_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; static const struct snd_pcm_ops oxygen_rec_b_ops = { .open = oxygen_rec_b_open, .close = oxygen_close, .hw_params = oxygen_rec_b_hw_params, .hw_free = oxygen_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; static const struct snd_pcm_ops oxygen_rec_c_ops = { .open = oxygen_rec_c_open, .close = oxygen_close, .hw_params = oxygen_rec_c_hw_params, .hw_free = oxygen_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; static const struct snd_pcm_ops oxygen_spdif_ops = { .open = oxygen_spdif_open, .close = oxygen_close, .hw_params = oxygen_spdif_hw_params, .hw_free = oxygen_spdif_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; static const struct snd_pcm_ops oxygen_multich_ops = { .open = oxygen_multich_open, .close = oxygen_close, .hw_params = oxygen_multich_hw_params, .hw_free = oxygen_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; static const struct snd_pcm_ops oxygen_ac97_ops = { .open = oxygen_ac97_open, .close = oxygen_close, .hw_params = oxygen_hw_params, .hw_free = oxygen_hw_free, .prepare = oxygen_prepare, .trigger = oxygen_trigger, .pointer = oxygen_pointer, }; int oxygen_pcm_init(struct oxygen *chip) { struct snd_pcm *pcm; int outs, ins; int err; outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S); ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 | CAPTURE_0_FROM_I2S_2)); if (outs | ins) { err = snd_pcm_new(chip->card, "Multichannel", 0, outs, ins, &pcm); if (err < 0) return err; if (outs) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops); if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_a_ops); else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_b_ops); pcm->private_data = chip; strcpy(pcm->name, "Multichannel"); if (outs) snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, DEFAULT_BUFFER_BYTES_MULTICH, BUFFER_BYTES_MAX_MULTICH); if (ins) snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF); ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF); if (outs | ins) { err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm); if (err < 0) return err; if (outs) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_spdif_ops); if (ins) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops); pcm->private_data = chip; strcpy(pcm->name, "Digital"); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } if (chip->has_ac97_1) { outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1); ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1); } else { outs = 0; ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2); } if (outs | ins) { err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2", 2, outs, ins, &pcm); if (err < 0) return err; if (outs) { snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_ac97_ops); oxygen_write8_masked(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_B_ROUTE_AC97_1, OXYGEN_REC_B_ROUTE_MASK); } if (ins) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_b_ops); pcm->private_data = chip; strcpy(pcm->name, outs ? "Front Panel" : "Analog 2"); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } ins = !!(chip->model.device_config & CAPTURE_3_FROM_I2S_3); if (ins) { err = snd_pcm_new(chip->card, "Analog3", 3, 0, ins, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops); oxygen_write8_masked(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_C_ROUTE_I2S_ADC_3, OXYGEN_REC_C_ROUTE_MASK); pcm->private_data = chip; strcpy(pcm->name, "Analog 3"); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } return 0; }
linux-master
sound/pci/oxygen/oxygen_pcm.c
// SPDX-License-Identifier: GPL-2.0-only /* * Mixer controls for the Xonar DG/DGX * * Copyright (c) Clemens Ladisch <[email protected]> * Copyright (c) Roman Volkov <[email protected]> */ #include <linux/pci.h> #include <linux/delay.h> #include <sound/control.h> #include <sound/core.h> #include <sound/info.h> #include <sound/pcm.h> #include <sound/tlv.h> #include "oxygen.h" #include "xonar_dg.h" #include "cs4245.h" /* analog output select */ static int output_select_apply(struct oxygen *chip) { struct dg *data = chip->model_data; data->cs4245_shadow[CS4245_SIGNAL_SEL] &= ~CS4245_A_OUT_SEL_MASK; if (data->output_sel == PLAYBACK_DST_HP) { /* mute FP (aux output) amplifier, switch rear jack to CS4245 */ oxygen_set_bits8(chip, OXYGEN_GPIO_DATA, GPIO_HP_REAR); } else if (data->output_sel == PLAYBACK_DST_HP_FP) { /* * Unmute FP amplifier, switch rear jack to CS4361; * I2S channels 2,3,4 should be inactive. */ oxygen_clear_bits8(chip, OXYGEN_GPIO_DATA, GPIO_HP_REAR); data->cs4245_shadow[CS4245_SIGNAL_SEL] |= CS4245_A_OUT_SEL_DAC; } else { /* * 2.0, 4.0, 5.1: switch to CS4361, mute FP amp., * and change playback routing. */ oxygen_clear_bits8(chip, OXYGEN_GPIO_DATA, GPIO_HP_REAR); } return cs4245_write_spi(chip, CS4245_SIGNAL_SEL); } static int output_select_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[3] = { "Stereo Headphones", "Stereo Headphones FP", "Multichannel", }; return snd_ctl_enum_info(info, 1, 3, names); } static int output_select_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; mutex_lock(&chip->mutex); value->value.enumerated.item[0] = data->output_sel; mutex_unlock(&chip->mutex); return 0; } static int output_select_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; unsigned int new = value->value.enumerated.item[0]; int changed = 0; int ret; mutex_lock(&chip->mutex); if (data->output_sel != new) { data->output_sel = new; ret = output_select_apply(chip); changed = ret >= 0 ? 1 : ret; oxygen_update_dac_routing(chip); } mutex_unlock(&chip->mutex); return changed; } /* CS4245 Headphone Channels A&B Volume Control */ static int hp_stereo_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 2; info->value.integer.min = 0; info->value.integer.max = 255; return 0; } static int hp_stereo_volume_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *val) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; unsigned int tmp; mutex_lock(&chip->mutex); tmp = (~data->cs4245_shadow[CS4245_DAC_A_CTRL]) & 255; val->value.integer.value[0] = tmp; tmp = (~data->cs4245_shadow[CS4245_DAC_B_CTRL]) & 255; val->value.integer.value[1] = tmp; mutex_unlock(&chip->mutex); return 0; } static int hp_stereo_volume_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *val) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; int ret; int changed = 0; long new1 = val->value.integer.value[0]; long new2 = val->value.integer.value[1]; if ((new1 > 255) || (new1 < 0) || (new2 > 255) || (new2 < 0)) return -EINVAL; mutex_lock(&chip->mutex); if ((data->cs4245_shadow[CS4245_DAC_A_CTRL] != ~new1) || (data->cs4245_shadow[CS4245_DAC_B_CTRL] != ~new2)) { data->cs4245_shadow[CS4245_DAC_A_CTRL] = ~new1; data->cs4245_shadow[CS4245_DAC_B_CTRL] = ~new2; ret = cs4245_write_spi(chip, CS4245_DAC_A_CTRL); if (ret >= 0) ret = cs4245_write_spi(chip, CS4245_DAC_B_CTRL); changed = ret >= 0 ? 1 : ret; } mutex_unlock(&chip->mutex); return changed; } /* Headphone Mute */ static int hp_mute_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *val) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; mutex_lock(&chip->mutex); val->value.integer.value[0] = !(data->cs4245_shadow[CS4245_DAC_CTRL_1] & CS4245_MUTE_DAC); mutex_unlock(&chip->mutex); return 0; } static int hp_mute_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *val) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; int ret; int changed; if (val->value.integer.value[0] > 1) return -EINVAL; mutex_lock(&chip->mutex); data->cs4245_shadow[CS4245_DAC_CTRL_1] &= ~CS4245_MUTE_DAC; data->cs4245_shadow[CS4245_DAC_CTRL_1] |= (~val->value.integer.value[0] << 2) & CS4245_MUTE_DAC; ret = cs4245_write_spi(chip, CS4245_DAC_CTRL_1); changed = ret >= 0 ? 1 : ret; mutex_unlock(&chip->mutex); return changed; } /* capture volume for all sources */ static int input_volume_apply(struct oxygen *chip, char left, char right) { struct dg *data = chip->model_data; int ret; data->cs4245_shadow[CS4245_PGA_A_CTRL] = left; data->cs4245_shadow[CS4245_PGA_B_CTRL] = right; ret = cs4245_write_spi(chip, CS4245_PGA_A_CTRL); if (ret < 0) return ret; return cs4245_write_spi(chip, CS4245_PGA_B_CTRL); } static int input_vol_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 2; info->value.integer.min = 2 * -12; info->value.integer.max = 2 * 12; return 0; } static int input_vol_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; unsigned int idx = ctl->private_value; mutex_lock(&chip->mutex); value->value.integer.value[0] = data->input_vol[idx][0]; value->value.integer.value[1] = data->input_vol[idx][1]; mutex_unlock(&chip->mutex); return 0; } static int input_vol_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; unsigned int idx = ctl->private_value; int changed = 0; int ret = 0; if (value->value.integer.value[0] < 2 * -12 || value->value.integer.value[0] > 2 * 12 || value->value.integer.value[1] < 2 * -12 || value->value.integer.value[1] > 2 * 12) return -EINVAL; mutex_lock(&chip->mutex); changed = data->input_vol[idx][0] != value->value.integer.value[0] || data->input_vol[idx][1] != value->value.integer.value[1]; if (changed) { data->input_vol[idx][0] = value->value.integer.value[0]; data->input_vol[idx][1] = value->value.integer.value[1]; if (idx == data->input_sel) { ret = input_volume_apply(chip, data->input_vol[idx][0], data->input_vol[idx][1]); } changed = ret >= 0 ? 1 : ret; } mutex_unlock(&chip->mutex); return changed; } /* Capture Source */ static int input_source_apply(struct oxygen *chip) { struct dg *data = chip->model_data; data->cs4245_shadow[CS4245_ANALOG_IN] &= ~CS4245_SEL_MASK; if (data->input_sel == CAPTURE_SRC_FP_MIC) data->cs4245_shadow[CS4245_ANALOG_IN] |= CS4245_SEL_INPUT_2; else if (data->input_sel == CAPTURE_SRC_LINE) data->cs4245_shadow[CS4245_ANALOG_IN] |= CS4245_SEL_INPUT_4; else if (data->input_sel != CAPTURE_SRC_MIC) data->cs4245_shadow[CS4245_ANALOG_IN] |= CS4245_SEL_INPUT_1; return cs4245_write_spi(chip, CS4245_ANALOG_IN); } static int input_sel_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[4] = { "Mic", "Front Mic", "Line", "Aux" }; return snd_ctl_enum_info(info, 1, 4, names); } static int input_sel_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; mutex_lock(&chip->mutex); value->value.enumerated.item[0] = data->input_sel; mutex_unlock(&chip->mutex); return 0; } static int input_sel_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; int changed; int ret; if (value->value.enumerated.item[0] > 3) return -EINVAL; mutex_lock(&chip->mutex); changed = value->value.enumerated.item[0] != data->input_sel; if (changed) { data->input_sel = value->value.enumerated.item[0]; ret = input_source_apply(chip); if (ret >= 0) ret = input_volume_apply(chip, data->input_vol[data->input_sel][0], data->input_vol[data->input_sel][1]); changed = ret >= 0 ? 1 : ret; } mutex_unlock(&chip->mutex); return changed; } /* ADC high-pass filter */ static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "Active", "Frozen" }; return snd_ctl_enum_info(info, 1, 2, names); } static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; value->value.enumerated.item[0] = !!(data->cs4245_shadow[CS4245_ADC_CTRL] & CS4245_HPF_FREEZE); return 0; } static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; u8 reg; int changed; mutex_lock(&chip->mutex); reg = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_HPF_FREEZE; if (value->value.enumerated.item[0]) reg |= CS4245_HPF_FREEZE; changed = reg != data->cs4245_shadow[CS4245_ADC_CTRL]; if (changed) { data->cs4245_shadow[CS4245_ADC_CTRL] = reg; cs4245_write_spi(chip, CS4245_ADC_CTRL); } mutex_unlock(&chip->mutex); return changed; } #define INPUT_VOLUME(xname, index) { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ .info = input_vol_info, \ .get = input_vol_get, \ .put = input_vol_put, \ .tlv = { .p = pga_db_scale }, \ .private_value = index, \ } static const DECLARE_TLV_DB_MINMAX(hp_db_scale, -12550, 0); static const DECLARE_TLV_DB_MINMAX(pga_db_scale, -1200, 1200); static const struct snd_kcontrol_new dg_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Output Playback Enum", .info = output_select_info, .get = output_select_get, .put = output_select_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = hp_stereo_volume_info, .get = hp_stereo_volume_get, .put = hp_stereo_volume_put, .tlv = { .p = hp_db_scale, }, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Playback Switch", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .info = snd_ctl_boolean_mono_info, .get = hp_mute_get, .put = hp_mute_put, }, INPUT_VOLUME("Mic Capture Volume", CAPTURE_SRC_MIC), INPUT_VOLUME("Front Mic Capture Volume", CAPTURE_SRC_FP_MIC), INPUT_VOLUME("Line Capture Volume", CAPTURE_SRC_LINE), INPUT_VOLUME("Aux Capture Volume", CAPTURE_SRC_AUX), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Capture Source", .info = input_sel_info, .get = input_sel_get, .put = input_sel_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "ADC High-pass Filter Capture Enum", .info = hpf_info, .get = hpf_get, .put = hpf_put, }, }; static int dg_control_filter(struct snd_kcontrol_new *template) { if (!strncmp(template->name, "Master Playback ", 16)) return 1; return 0; } static int dg_mixer_init(struct oxygen *chip) { unsigned int i; int err; output_select_apply(chip); input_source_apply(chip); oxygen_update_dac_routing(chip); for (i = 0; i < ARRAY_SIZE(dg_controls); ++i) { err = snd_ctl_add(chip->card, snd_ctl_new1(&dg_controls[i], chip)); if (err < 0) return err; } return 0; } const struct oxygen_model model_xonar_dg = { .longname = "C-Media Oxygen HD Audio", .chip = "CMI8786", .init = dg_init, .control_filter = dg_control_filter, .mixer_init = dg_mixer_init, .cleanup = dg_cleanup, .suspend = dg_suspend, .resume = dg_resume, .set_dac_params = set_cs4245_dac_params, .set_adc_params = set_cs4245_adc_params, .adjust_dac_routing = adjust_dg_dac_routing, .dump_registers = dump_cs4245_registers, .model_data_size = sizeof(struct dg), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_1 | CAPTURE_1_FROM_SPDIF, .dac_channels_pcm = 6, .dac_channels_mixer = 0, .function_flags = OXYGEN_FUNCTION_SPI, .dac_mclks = OXYGEN_MCLKS(256, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 128, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, };
linux-master
sound/pci/oxygen/xonar_dg_mixer.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver for C-Media's reference design and similar models * * Copyright (c) Clemens Ladisch <[email protected]> */ /* * CMI8788: * * SPI 0 -> 1st AK4396 (front) * SPI 1 -> 2nd AK4396 (surround) * SPI 2 -> 3rd AK4396 (center/LFE) * SPI 3 -> WM8785 * SPI 4 -> 4th AK4396 (back) * * GPIO 0 -> DFS0 of AK5385 * GPIO 1 -> DFS1 of AK5385 * * X-Meridian models: * GPIO 4 -> enable extension S/PDIF input * GPIO 6 -> enable on-board S/PDIF input * * Claro models: * GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input * GPIO 8 -> enable headphone amplifier * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * CD_IN <- CD * MIC_IN <- mic * * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input */ #include <linux/delay.h> #include <linux/mutex.h> #include <linux/pci.h> #include <linux/module.h> #include <sound/ac97_codec.h> #include <sound/control.h> #include <sound/core.h> #include <sound/info.h> #include <sound/initval.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #include "oxygen.h" #include "xonar_dg.h" #include "ak4396.h" #include "wm8785.h" MODULE_AUTHOR("Clemens Ladisch <[email protected]>"); MODULE_DESCRIPTION("C-Media CMI8788 driver"); MODULE_LICENSE("GPL v2"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "card index"); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string"); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "enable card"); enum { MODEL_CMEDIA_REF, MODEL_MERIDIAN, MODEL_MERIDIAN_2G, MODEL_CLARO, MODEL_CLARO_HALO, MODEL_FANTASIA, MODEL_SERENADE, MODEL_2CH_OUTPUT, MODEL_HG2PCI, MODEL_XONAR_DG, MODEL_XONAR_DGX, }; static const struct pci_device_id oxygen_ids[] = { /* C-Media's reference design */ { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF }, { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF }, /* Asus Xonar DG */ { OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG }, /* Asus Xonar DGX */ { OXYGEN_PCI_SUBID(0x1043, 0x8521), .driver_data = MODEL_XONAR_DGX }, /* PCI 2.0 HD Audio */ { OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT }, /* Kuroutoshikou CMI8787-HG2PCI */ { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_HG2PCI }, /* TempoTec HiFier Fantasia */ { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA }, /* TempoTec HiFier Serenade */ { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_SERENADE }, /* AuzenTech X-Meridian */ { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN }, /* AuzenTech X-Meridian 2G */ { OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN_2G }, /* HT-Omega Claro */ { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO }, /* HT-Omega Claro halo */ { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO }, { } }; MODULE_DEVICE_TABLE(pci, oxygen_ids); #define GPIO_AK5385_DFS_MASK 0x0003 #define GPIO_AK5385_DFS_NORMAL 0x0000 #define GPIO_AK5385_DFS_DOUBLE 0x0001 #define GPIO_AK5385_DFS_QUAD 0x0002 #define GPIO_MERIDIAN_DIG_MASK 0x0050 #define GPIO_MERIDIAN_DIG_EXT 0x0010 #define GPIO_MERIDIAN_DIG_BOARD 0x0040 #define GPIO_CLARO_DIG_COAX 0x0040 #define GPIO_CLARO_HP 0x0100 struct generic_data { unsigned int dacs; u8 ak4396_regs[4][5]; u16 wm8785_regs[3]; }; static void ak4396_write(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { /* maps ALSA channel pair number to SPI output */ static const u8 codec_spi_map[4] = { 0, 1, 2, 4 }; struct generic_data *data = chip->model_data; oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CLOCK_160 | (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, AK4396_WRITE | (reg << 8) | value); data->ak4396_regs[codec][reg] = value; } static void ak4396_write_cached(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { struct generic_data *data = chip->model_data; if (value != data->ak4396_regs[codec][reg]) ak4396_write(chip, codec, reg, value); } static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) { struct generic_data *data = chip->model_data; oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CLOCK_160 | (3 << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, (reg << 9) | value); if (reg < ARRAY_SIZE(data->wm8785_regs)) data->wm8785_regs[reg] = value; } static void ak4396_registers_init(struct oxygen *chip) { struct generic_data *data = chip->model_data; unsigned int i; for (i = 0; i < data->dacs; ++i) { ak4396_write(chip, i, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_RSTN); ak4396_write(chip, i, AK4396_CONTROL_2, data->ak4396_regs[0][AK4396_CONTROL_2]); ak4396_write(chip, i, AK4396_CONTROL_3, AK4396_PCM); ak4396_write(chip, i, AK4396_LCH_ATT, chip->dac_volume[i * 2]); ak4396_write(chip, i, AK4396_RCH_ATT, chip->dac_volume[i * 2 + 1]); } } static void ak4396_init(struct oxygen *chip) { struct generic_data *data = chip->model_data; data->dacs = chip->model.dac_channels_pcm / 2; data->ak4396_regs[0][AK4396_CONTROL_2] = AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL; ak4396_registers_init(chip); snd_component_add(chip->card, "AK4396"); } static void ak5385_init(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK); snd_component_add(chip->card, "AK5385"); } static void wm8785_registers_init(struct oxygen *chip) { struct generic_data *data = chip->model_data; wm8785_write(chip, WM8785_R7, 0); wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]); wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); } static void wm8785_init(struct oxygen *chip) { struct generic_data *data = chip->model_data; data->wm8785_regs[0] = WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST; data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL; wm8785_registers_init(chip); snd_component_add(chip->card, "WM8785"); } static void generic_init(struct oxygen *chip) { ak4396_init(chip); wm8785_init(chip); } static void meridian_init(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_MERIDIAN_DIG_MASK); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, GPIO_MERIDIAN_DIG_BOARD, GPIO_MERIDIAN_DIG_MASK); ak4396_init(chip); ak5385_init(chip); } static void claro_enable_hp(struct oxygen *chip) { msleep(300); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP); oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); } static void claro_init(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX); ak4396_init(chip); wm8785_init(chip); claro_enable_hp(chip); } static void claro_halo_init(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX); ak4396_init(chip); ak5385_init(chip); claro_enable_hp(chip); } static void fantasia_init(struct oxygen *chip) { ak4396_init(chip); snd_component_add(chip->card, "CS5340"); } static void stereo_output_init(struct oxygen *chip) { ak4396_init(chip); } static void generic_cleanup(struct oxygen *chip) { } static void claro_disable_hp(struct oxygen *chip) { oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); } static void claro_cleanup(struct oxygen *chip) { claro_disable_hp(chip); } static void claro_suspend(struct oxygen *chip) { claro_disable_hp(chip); } static void generic_resume(struct oxygen *chip) { ak4396_registers_init(chip); wm8785_registers_init(chip); } static void meridian_resume(struct oxygen *chip) { ak4396_registers_init(chip); } static void claro_resume(struct oxygen *chip) { ak4396_registers_init(chip); claro_enable_hp(chip); } static void stereo_resume(struct oxygen *chip) { ak4396_registers_init(chip); } static void set_ak4396_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct generic_data *data = chip->model_data; unsigned int i; u8 value; value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK; if (params_rate(params) <= 54000) value |= AK4396_DFS_NORMAL; else if (params_rate(params) <= 108000) value |= AK4396_DFS_DOUBLE; else value |= AK4396_DFS_QUAD; msleep(1); /* wait for the new MCLK to become stable */ if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) { for (i = 0; i < data->dacs; ++i) { ak4396_write(chip, i, AK4396_CONTROL_1, AK4396_DIF_24_MSB); ak4396_write(chip, i, AK4396_CONTROL_2, value); ak4396_write(chip, i, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_RSTN); } } } static void update_ak4396_volume(struct oxygen *chip) { struct generic_data *data = chip->model_data; unsigned int i; for (i = 0; i < data->dacs; ++i) { ak4396_write_cached(chip, i, AK4396_LCH_ATT, chip->dac_volume[i * 2]); ak4396_write_cached(chip, i, AK4396_RCH_ATT, chip->dac_volume[i * 2 + 1]); } } static void update_ak4396_mute(struct oxygen *chip) { struct generic_data *data = chip->model_data; unsigned int i; u8 value; value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE; if (chip->dac_mute) value |= AK4396_SMUTE; for (i = 0; i < data->dacs; ++i) ak4396_write_cached(chip, i, AK4396_CONTROL_2, value); } static void set_wm8785_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct generic_data *data = chip->model_data; unsigned int value; value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST; if (params_rate(params) <= 48000) value |= WM8785_OSR_SINGLE; else if (params_rate(params) <= 96000) value |= WM8785_OSR_DOUBLE; else value |= WM8785_OSR_QUAD; if (value != data->wm8785_regs[0]) { wm8785_write(chip, WM8785_R7, 0); wm8785_write(chip, WM8785_R0, value); wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); } } static void set_ak5385_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { unsigned int value; if (params_rate(params) <= 54000) value = GPIO_AK5385_DFS_NORMAL; else if (params_rate(params) <= 108000) value = GPIO_AK5385_DFS_DOUBLE; else value = GPIO_AK5385_DFS_QUAD; oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, value, GPIO_AK5385_DFS_MASK); } static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { } static int rolloff_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "Sharp Roll-off", "Slow Roll-off" }; return snd_ctl_enum_info(info, 1, 2, names); } static int rolloff_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct generic_data *data = chip->model_data; value->value.enumerated.item[0] = (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0; return 0; } static int rolloff_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct generic_data *data = chip->model_data; unsigned int i; int changed; u8 reg; mutex_lock(&chip->mutex); reg = data->ak4396_regs[0][AK4396_CONTROL_2]; if (value->value.enumerated.item[0]) reg |= AK4396_SLOW; else reg &= ~AK4396_SLOW; changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2]; if (changed) { for (i = 0; i < data->dacs; ++i) ak4396_write(chip, i, AK4396_CONTROL_2, reg); } mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new rolloff_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DAC Filter Playback Enum", .info = rolloff_info, .get = rolloff_get, .put = rolloff_put, }; static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "None", "High-pass Filter" }; return snd_ctl_enum_info(info, 1, 2, names); } static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct generic_data *data = chip->model_data; value->value.enumerated.item[0] = (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0; return 0; } static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct generic_data *data = chip->model_data; unsigned int reg; int changed; mutex_lock(&chip->mutex); reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL); if (value->value.enumerated.item[0]) reg |= WM8785_HPFR | WM8785_HPFL; changed = reg != data->wm8785_regs[WM8785_R2]; if (changed) wm8785_write(chip, WM8785_R2, reg); mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new hpf_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "ADC Filter Capture Enum", .info = hpf_info, .get = hpf_get, .put = hpf_put, }; static int meridian_dig_source_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "On-board", "Extension" }; return snd_ctl_enum_info(info, 1, 2, names); } static int claro_dig_source_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "Optical", "Coaxial" }; return snd_ctl_enum_info(info, 1, 2, names); } static int meridian_dig_source_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; value->value.enumerated.item[0] = !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_MERIDIAN_DIG_EXT); return 0; } static int claro_dig_source_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; value->value.enumerated.item[0] = !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_CLARO_DIG_COAX); return 0; } static int meridian_dig_source_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 old_reg, new_reg; int changed; mutex_lock(&chip->mutex); old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA); new_reg = old_reg & ~GPIO_MERIDIAN_DIG_MASK; if (value->value.enumerated.item[0] == 0) new_reg |= GPIO_MERIDIAN_DIG_BOARD; else new_reg |= GPIO_MERIDIAN_DIG_EXT; changed = new_reg != old_reg; if (changed) oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg); mutex_unlock(&chip->mutex); return changed; } static int claro_dig_source_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 old_reg, new_reg; int changed; mutex_lock(&chip->mutex); old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA); new_reg = old_reg & ~GPIO_CLARO_DIG_COAX; if (value->value.enumerated.item[0]) new_reg |= GPIO_CLARO_DIG_COAX; changed = new_reg != old_reg; if (changed) oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg); mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new meridian_dig_source_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "IEC958 Source Capture Enum", .info = meridian_dig_source_info, .get = meridian_dig_source_get, .put = meridian_dig_source_put, }; static const struct snd_kcontrol_new claro_dig_source_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "IEC958 Source Capture Enum", .info = claro_dig_source_info, .get = claro_dig_source_get, .put = claro_dig_source_put, }; static int generic_mixer_init(struct oxygen *chip) { return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip)); } static int generic_wm8785_mixer_init(struct oxygen *chip) { int err; err = generic_mixer_init(chip); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip)); if (err < 0) return err; return 0; } static int meridian_mixer_init(struct oxygen *chip) { int err; err = generic_mixer_init(chip); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&meridian_dig_source_control, chip)); if (err < 0) return err; return 0; } static int claro_mixer_init(struct oxygen *chip) { int err; err = generic_wm8785_mixer_init(chip); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&claro_dig_source_control, chip)); if (err < 0) return err; return 0; } static int claro_halo_mixer_init(struct oxygen *chip) { int err; err = generic_mixer_init(chip); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&claro_dig_source_control, chip)); if (err < 0) return err; return 0; } static void dump_ak4396_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct generic_data *data = chip->model_data; unsigned int dac, i; for (dac = 0; dac < data->dacs; ++dac) { snd_iprintf(buffer, "\nAK4396 %u:", dac + 1); for (i = 0; i < 5; ++i) snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]); } snd_iprintf(buffer, "\n"); } static void dump_wm8785_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct generic_data *data = chip->model_data; unsigned int i; snd_iprintf(buffer, "\nWM8785:"); for (i = 0; i < 3; ++i) snd_iprintf(buffer, " %03x", data->wm8785_regs[i]); snd_iprintf(buffer, "\n"); } static void dump_oxygen_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { dump_ak4396_registers(chip, buffer); dump_wm8785_registers(chip, buffer); } static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0); static const struct oxygen_model model_generic = { .shortname = "C-Media CMI8788", .longname = "C-Media Oxygen HD Audio", .chip = "CMI8788", .init = generic_init, .mixer_init = generic_wm8785_mixer_init, .cleanup = generic_cleanup, .resume = generic_resume, .set_dac_params = set_ak4396_params, .set_adc_params = set_wm8785_params, .update_dac_volume = update_ak4396_volume, .update_dac_mute = update_ak4396_mute, .dump_registers = dump_oxygen_registers, .dac_tlv = ak4396_db_scale, .model_data_size = sizeof(struct generic_data), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | PLAYBACK_2_TO_AC97_1 | CAPTURE_0_FROM_I2S_1 | CAPTURE_1_FROM_SPDIF | CAPTURE_2_FROM_AC97_1 | AC97_CD_INPUT, .dac_channels_pcm = 8, .dac_channels_mixer = 8, .dac_volume_min = 0, .dac_volume_max = 255, .function_flags = OXYGEN_FUNCTION_SPI | OXYGEN_FUNCTION_ENABLE_SPI_4_5, .dac_mclks = OXYGEN_MCLKS(256, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 256, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; static int get_oxygen_model(struct oxygen *chip, const struct pci_device_id *id) { static const char *const names[] = { [MODEL_MERIDIAN] = "AuzenTech X-Meridian", [MODEL_MERIDIAN_2G] = "AuzenTech X-Meridian 2G", [MODEL_CLARO] = "HT-Omega Claro", [MODEL_CLARO_HALO] = "HT-Omega Claro halo", [MODEL_FANTASIA] = "TempoTec HiFier Fantasia", [MODEL_SERENADE] = "TempoTec HiFier Serenade", [MODEL_HG2PCI] = "CMI8787-HG2PCI", [MODEL_XONAR_DG] = "Xonar DG", [MODEL_XONAR_DGX] = "Xonar DGX", }; chip->model = model_generic; switch (id->driver_data) { case MODEL_MERIDIAN: case MODEL_MERIDIAN_2G: chip->model.init = meridian_init; chip->model.mixer_init = meridian_mixer_init; chip->model.resume = meridian_resume; chip->model.set_adc_params = set_ak5385_params; chip->model.dump_registers = dump_ak4396_registers; chip->model.device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF; if (id->driver_data == MODEL_MERIDIAN) chip->model.device_config |= AC97_CD_INPUT; break; case MODEL_CLARO: chip->model.init = claro_init; chip->model.mixer_init = claro_mixer_init; chip->model.cleanup = claro_cleanup; chip->model.suspend = claro_suspend; chip->model.resume = claro_resume; break; case MODEL_CLARO_HALO: chip->model.init = claro_halo_init; chip->model.mixer_init = claro_halo_mixer_init; chip->model.cleanup = claro_cleanup; chip->model.suspend = claro_suspend; chip->model.resume = claro_resume; chip->model.set_adc_params = set_ak5385_params; chip->model.dump_registers = dump_ak4396_registers; chip->model.device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF; break; case MODEL_FANTASIA: case MODEL_SERENADE: case MODEL_2CH_OUTPUT: case MODEL_HG2PCI: chip->model.shortname = "C-Media CMI8787"; chip->model.chip = "CMI8787"; if (id->driver_data == MODEL_FANTASIA) chip->model.init = fantasia_init; else chip->model.init = stereo_output_init; chip->model.resume = stereo_resume; chip->model.mixer_init = generic_mixer_init; chip->model.set_adc_params = set_no_params; chip->model.dump_registers = dump_ak4396_registers; chip->model.device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF; if (id->driver_data == MODEL_FANTASIA) { chip->model.device_config |= CAPTURE_0_FROM_I2S_1; chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128); } chip->model.dac_channels_pcm = 2; chip->model.dac_channels_mixer = 2; break; case MODEL_XONAR_DG: case MODEL_XONAR_DGX: chip->model = model_xonar_dg; break; } if (id->driver_data == MODEL_MERIDIAN || id->driver_data == MODEL_MERIDIAN_2G || id->driver_data == MODEL_CLARO_HALO) { chip->model.misc_flags = OXYGEN_MISC_MIDI; chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT; } if (id->driver_data < ARRAY_SIZE(names) && names[id->driver_data]) chip->model.shortname = names[id->driver_data]; return 0; } static int generic_oxygen_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { ++dev; return -ENOENT; } err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE, oxygen_ids, get_oxygen_model); if (err >= 0) ++dev; return err; } static struct pci_driver oxygen_driver = { .name = KBUILD_MODNAME, .id_table = oxygen_ids, .probe = generic_oxygen_probe, #ifdef CONFIG_PM_SLEEP .driver = { .pm = &oxygen_pci_pm, }, #endif }; module_pci_driver(oxygen_driver);
linux-master
sound/pci/oxygen/oxygen.c
// SPDX-License-Identifier: GPL-2.0-only /* * card driver for models with PCM1796 DACs (Xonar D2/D2X/HDAV1.3/ST/STX) * * Copyright (c) Clemens Ladisch <[email protected]> */ /* * Xonar D2/D2X * ------------ * * CMI8788: * * SPI 0 -> 1st PCM1796 (front) * SPI 1 -> 2nd PCM1796 (surround) * SPI 2 -> 3rd PCM1796 (center/LFE) * SPI 4 -> 4th PCM1796 (back) * * GPIO 2 -> M0 of CS5381 * GPIO 3 -> M1 of CS5381 * GPIO 5 <- external power present (D2X only) * GPIO 7 -> ALT * GPIO 8 -> enable output to speakers * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * VIDEO_IN <- CD * FMIC_IN <- mic * * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input */ /* * Xonar HDAV1.3 (Deluxe) * ---------------------- * * CMI8788: * * I²C <-> PCM1796 (addr 1001100) (front) * * GPI 0 <- external power present * * GPIO 0 -> enable HDMI (0) or speaker (1) output * GPIO 2 -> M0 of CS5381 * GPIO 3 -> M1 of CS5381 * GPIO 4 <- daughterboard detection * GPIO 5 <- daughterboard detection * GPIO 6 -> ? * GPIO 7 -> ? * GPIO 8 -> route input jack to line-in (0) or mic-in (1) * * UART <-> HDMI controller * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * CD_IN <- CD * MIC_IN <- mic * * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input * * no daughterboard * ---------------- * * GPIO 4 <- 1 * * H6 daughterboard * ---------------- * * GPIO 4 <- 0 * GPIO 5 <- 0 * * I²C <-> PCM1796 (addr 1001101) (surround) * <-> PCM1796 (addr 1001110) (center/LFE) * <-> PCM1796 (addr 1001111) (back) * * unknown daughterboard * --------------------- * * GPIO 4 <- 0 * GPIO 5 <- 1 * * I²C <-> CS4362A (addr 0011000) (surround, center/LFE, back) */ /* * Xonar Essence ST (Deluxe)/STX (II) * ---------------------------------- * * CMI8788: * * I²C <-> PCM1792A (addr 1001100) * <-> CS2000 (addr 1001110) (ST only) * * ADC1 MCLK -> REF_CLK of CS2000 (ST only) * * GPI 0 <- external power present (STX only) * * GPIO 0 -> enable output to speakers * GPIO 1 -> route HP to front panel (0) or rear jack (1) * GPIO 2 -> M0 of CS5381 * GPIO 3 -> M1 of CS5381 * GPIO 4 <- daughterboard detection * GPIO 5 <- daughterboard detection * GPIO 6 -> ? * GPIO 7 -> route output to speaker jacks (0) or HP (1) * GPIO 8 -> route input jack to line-in (0) or mic-in (1) * * PCM1792A: * * SCK <- CLK_OUT of CS2000 (ST only) * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * MIC_IN <- mic * * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input * * H6 daughterboard * ---------------- * * GPIO 4 <- 0 * GPIO 5 <- 0 */ /* * Xonar Xense * ----------- * * CMI8788: * * I²C <-> PCM1796 (addr 1001100) (front) * <-> CS4362A (addr 0011000) (surround, center/LFE, back) * <-> CS2000 (addr 1001110) * * ADC1 MCLK -> REF_CLK of CS2000 * * GPI 0 <- external power present * * GPIO 0 -> enable output * GPIO 1 -> route HP to front panel (0) or rear jack (1) * GPIO 2 -> M0 of CS5381 * GPIO 3 -> M1 of CS5381 * GPIO 4 -> enable output * GPIO 5 -> enable output * GPIO 6 -> ? * GPIO 7 -> route output to HP (0) or speaker (1) * GPIO 8 -> route input jack to mic-in (0) or line-in (1) * * CM9780: * * LINE_OUT -> input of ADC * * AUX_IN <- aux * VIDEO_IN <- ? * FMIC_IN <- mic * * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input * GPO 1 -> route mic-in from input jack (0) or front panel header (1) */ #include <linux/pci.h> #include <linux/delay.h> #include <linux/mutex.h> #include <sound/ac97_codec.h> #include <sound/control.h> #include <sound/core.h> #include <sound/info.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #include "xonar.h" #include "cm9780.h" #include "pcm1796.h" #include "cs2000.h" #define GPIO_D2X_EXT_POWER 0x0020 #define GPIO_D2_ALT 0x0080 #define GPIO_D2_OUTPUT_ENABLE 0x0100 #define GPI_EXT_POWER 0x01 #define GPIO_INPUT_ROUTE 0x0100 #define GPIO_HDAV_OUTPUT_ENABLE 0x0001 #define GPIO_HDAV_MAGIC 0x00c0 #define GPIO_DB_MASK 0x0030 #define GPIO_DB_H6 0x0000 #define GPIO_ST_OUTPUT_ENABLE 0x0001 #define GPIO_ST_HP_REAR 0x0002 #define GPIO_ST_MAGIC 0x0040 #define GPIO_ST_HP 0x0080 #define GPIO_XENSE_OUTPUT_ENABLE (0x0001 | 0x0010 | 0x0020) #define GPIO_XENSE_SPEAKERS 0x0080 #define I2C_DEVICE_PCM1796(i) (0x98 + ((i) << 1)) /* 10011, ii, /W=0 */ #define I2C_DEVICE_CS2000 0x9c /* 100111, 0, /W=0 */ #define PCM1796_REG_BASE 16 struct xonar_pcm179x { struct xonar_generic generic; unsigned int dacs; u8 pcm1796_regs[4][5]; unsigned int current_rate; bool h6; bool hp_active; s8 hp_gain_offset; bool has_cs2000; u8 cs2000_regs[0x1f]; bool broken_i2c; }; struct xonar_hdav { struct xonar_pcm179x pcm179x; struct xonar_hdmi hdmi; }; static inline void pcm1796_write_spi(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { /* maps ALSA channel pair number to SPI output */ static const u8 codec_map[4] = { 0, 1, 2, 4 }; oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CLOCK_160 | (codec_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, (reg << 8) | value); } static inline void pcm1796_write_i2c(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { oxygen_write_i2c(chip, I2C_DEVICE_PCM1796(codec), reg, value); } static void pcm1796_write(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { struct xonar_pcm179x *data = chip->model_data; if ((chip->model.function_flags & OXYGEN_FUNCTION_2WIRE_SPI_MASK) == OXYGEN_FUNCTION_SPI) pcm1796_write_spi(chip, codec, reg, value); else pcm1796_write_i2c(chip, codec, reg, value); if ((unsigned int)(reg - PCM1796_REG_BASE) < ARRAY_SIZE(data->pcm1796_regs[codec])) data->pcm1796_regs[codec][reg - PCM1796_REG_BASE] = value; } static void pcm1796_write_cached(struct oxygen *chip, unsigned int codec, u8 reg, u8 value) { struct xonar_pcm179x *data = chip->model_data; if (value != data->pcm1796_regs[codec][reg - PCM1796_REG_BASE]) pcm1796_write(chip, codec, reg, value); } static void cs2000_write(struct oxygen *chip, u8 reg, u8 value) { struct xonar_pcm179x *data = chip->model_data; oxygen_write_i2c(chip, I2C_DEVICE_CS2000, reg, value); data->cs2000_regs[reg] = value; } static void cs2000_write_cached(struct oxygen *chip, u8 reg, u8 value) { struct xonar_pcm179x *data = chip->model_data; if (value != data->cs2000_regs[reg]) cs2000_write(chip, reg, value); } static void pcm1796_registers_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; s8 gain_offset; msleep(1); gain_offset = data->hp_active ? data->hp_gain_offset : 0; for (i = 0; i < data->dacs; ++i) { /* set ATLD before ATL/ATR */ pcm1796_write(chip, i, 18, data->pcm1796_regs[0][18 - PCM1796_REG_BASE]); pcm1796_write(chip, i, 16, chip->dac_volume[i * 2] + gain_offset); pcm1796_write(chip, i, 17, chip->dac_volume[i * 2 + 1] + gain_offset); pcm1796_write(chip, i, 19, data->pcm1796_regs[0][19 - PCM1796_REG_BASE]); pcm1796_write(chip, i, 20, data->pcm1796_regs[0][20 - PCM1796_REG_BASE]); pcm1796_write(chip, i, 21, 0); gain_offset = 0; } } static void pcm1796_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->pcm1796_regs[0][18 - PCM1796_REG_BASE] = PCM1796_FMT_24_I2S | PCM1796_ATLD; if (!data->broken_i2c) data->pcm1796_regs[0][18 - PCM1796_REG_BASE] |= PCM1796_MUTE; data->pcm1796_regs[0][19 - PCM1796_REG_BASE] = PCM1796_FLT_SHARP | PCM1796_ATS_1; data->pcm1796_regs[0][20 - PCM1796_REG_BASE] = data->h6 ? PCM1796_OS_64 : PCM1796_OS_128; pcm1796_registers_init(chip); data->current_rate = 48000; } static void xonar_d2_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.anti_pop_delay = 300; data->generic.output_enable_bit = GPIO_D2_OUTPUT_ENABLE; data->dacs = 4; pcm1796_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D2_ALT); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_D2_ALT); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_FMIC2MIC); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "PCM1796"); snd_component_add(chip->card, "CS5381"); } static void xonar_d2x_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.ext_power_reg = OXYGEN_GPIO_DATA; data->generic.ext_power_int_reg = OXYGEN_GPIO_INTERRUPT_MASK; data->generic.ext_power_bit = GPIO_D2X_EXT_POWER; oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D2X_EXT_POWER); xonar_init_ext_power(chip); xonar_d2_init(chip); } static void xonar_hdav_init(struct oxygen *chip) { struct xonar_hdav *data = chip->model_data; oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_STANDARD); data->pcm179x.generic.anti_pop_delay = 100; data->pcm179x.generic.output_enable_bit = GPIO_HDAV_OUTPUT_ENABLE; data->pcm179x.generic.ext_power_reg = OXYGEN_GPI_DATA; data->pcm179x.generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK; data->pcm179x.generic.ext_power_bit = GPI_EXT_POWER; data->pcm179x.dacs = chip->model.dac_channels_mixer / 2; data->pcm179x.h6 = chip->model.dac_channels_mixer > 2; pcm1796_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_HDAV_MAGIC | GPIO_INPUT_ROUTE); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_INPUT_ROUTE); xonar_init_cs53x1(chip); xonar_init_ext_power(chip); xonar_hdmi_init(chip, &data->hdmi); xonar_enable_output(chip); snd_component_add(chip->card, "PCM1796"); snd_component_add(chip->card, "CS5381"); } static void xonar_st_init_i2c(struct oxygen *chip) { oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_STANDARD); } static void xonar_st_init_common(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.output_enable_bit = GPIO_ST_OUTPUT_ENABLE; data->dacs = chip->model.dac_channels_mixer / 2; data->h6 = chip->model.dac_channels_mixer > 2; data->hp_gain_offset = 2*-18; pcm1796_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR | GPIO_ST_MAGIC | GPIO_ST_HP); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR | GPIO_ST_HP); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "PCM1792A"); snd_component_add(chip->card, "CS5381"); } static void cs2000_registers_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; cs2000_write(chip, CS2000_GLOBAL_CFG, CS2000_FREEZE); cs2000_write(chip, CS2000_DEV_CTRL, 0); cs2000_write(chip, CS2000_DEV_CFG_1, CS2000_R_MOD_SEL_1 | (0 << CS2000_R_SEL_SHIFT) | CS2000_AUX_OUT_SRC_REF_CLK | CS2000_EN_DEV_CFG_1); cs2000_write(chip, CS2000_DEV_CFG_2, (0 << CS2000_LOCK_CLK_SHIFT) | CS2000_FRAC_N_SRC_STATIC); cs2000_write(chip, CS2000_RATIO_0 + 0, 0x00); /* 1.0 */ cs2000_write(chip, CS2000_RATIO_0 + 1, 0x10); cs2000_write(chip, CS2000_RATIO_0 + 2, 0x00); cs2000_write(chip, CS2000_RATIO_0 + 3, 0x00); cs2000_write(chip, CS2000_FUN_CFG_1, data->cs2000_regs[CS2000_FUN_CFG_1]); cs2000_write(chip, CS2000_FUN_CFG_2, 0); cs2000_write(chip, CS2000_GLOBAL_CFG, CS2000_EN_DEV_CFG_2); msleep(3); /* PLL lock delay */ } static void xonar_st_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.anti_pop_delay = 100; data->h6 = chip->model.dac_channels_mixer > 2; data->has_cs2000 = true; data->cs2000_regs[CS2000_FUN_CFG_1] = CS2000_REF_CLK_DIV_1; data->broken_i2c = true; oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_I2S | OXYGEN_I2S_MCLK(data->h6 ? MCLK_256 : MCLK_512) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); xonar_st_init_i2c(chip); cs2000_registers_init(chip); xonar_st_init_common(chip); snd_component_add(chip->card, "CS2000"); } static void xonar_stx_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; xonar_st_init_i2c(chip); data->generic.anti_pop_delay = 800; data->generic.ext_power_reg = OXYGEN_GPI_DATA; data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK; data->generic.ext_power_bit = GPI_EXT_POWER; xonar_init_ext_power(chip); xonar_st_init_common(chip); } static void xonar_xense_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.ext_power_reg = OXYGEN_GPI_DATA; data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK; data->generic.ext_power_bit = GPI_EXT_POWER; xonar_init_ext_power(chip); data->generic.anti_pop_delay = 100; data->has_cs2000 = true; data->cs2000_regs[CS2000_FUN_CFG_1] = CS2000_REF_CLK_DIV_1; oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_I2S | OXYGEN_I2S_MCLK(MCLK_512) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); xonar_st_init_i2c(chip); cs2000_registers_init(chip); data->generic.output_enable_bit = GPIO_XENSE_OUTPUT_ENABLE; data->dacs = 1; data->hp_gain_offset = 2*-18; pcm1796_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR | GPIO_ST_MAGIC | GPIO_XENSE_SPEAKERS); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR | GPIO_XENSE_SPEAKERS); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "PCM1796"); snd_component_add(chip->card, "CS5381"); snd_component_add(chip->card, "CS2000"); } static void xonar_d2_cleanup(struct oxygen *chip) { xonar_disable_output(chip); } static void xonar_hdav_cleanup(struct oxygen *chip) { xonar_hdmi_cleanup(chip); xonar_disable_output(chip); msleep(2); } static void xonar_st_cleanup(struct oxygen *chip) { xonar_disable_output(chip); } static void xonar_d2_suspend(struct oxygen *chip) { xonar_d2_cleanup(chip); } static void xonar_hdav_suspend(struct oxygen *chip) { xonar_hdav_cleanup(chip); } static void xonar_st_suspend(struct oxygen *chip) { xonar_st_cleanup(chip); } static void xonar_d2_resume(struct oxygen *chip) { pcm1796_registers_init(chip); xonar_enable_output(chip); } static void xonar_hdav_resume(struct oxygen *chip) { struct xonar_hdav *data = chip->model_data; pcm1796_registers_init(chip); xonar_hdmi_resume(chip, &data->hdmi); xonar_enable_output(chip); } static void xonar_stx_resume(struct oxygen *chip) { pcm1796_registers_init(chip); xonar_enable_output(chip); } static void xonar_st_resume(struct oxygen *chip) { cs2000_registers_init(chip); xonar_stx_resume(chip); } static void update_pcm1796_oversampling(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; u8 reg; if (data->current_rate <= 48000 && !data->h6) reg = PCM1796_OS_128; else reg = PCM1796_OS_64; for (i = 0; i < data->dacs; ++i) pcm1796_write_cached(chip, i, 20, reg); } static void update_pcm1796_deemph(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; u8 reg; reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE] & ~PCM1796_DMF_MASK; if (data->current_rate == 48000) reg |= PCM1796_DMF_48; else if (data->current_rate == 44100) reg |= PCM1796_DMF_441; else if (data->current_rate == 32000) reg |= PCM1796_DMF_32; for (i = 0; i < data->dacs; ++i) pcm1796_write_cached(chip, i, 18, reg); } static void set_pcm1796_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct xonar_pcm179x *data = chip->model_data; msleep(1); data->current_rate = params_rate(params); update_pcm1796_oversampling(chip); update_pcm1796_deemph(chip); } static void update_pcm1796_volume(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; s8 gain_offset; gain_offset = data->hp_active ? data->hp_gain_offset : 0; for (i = 0; i < data->dacs; ++i) { pcm1796_write_cached(chip, i, 16, chip->dac_volume[i * 2] + gain_offset); pcm1796_write_cached(chip, i, 17, chip->dac_volume[i * 2 + 1] + gain_offset); gain_offset = 0; } } static void update_pcm1796_mute(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; u8 value; value = data->pcm1796_regs[0][18 - PCM1796_REG_BASE]; if (chip->dac_mute) value |= PCM1796_MUTE; else value &= ~PCM1796_MUTE; for (i = 0; i < data->dacs; ++i) pcm1796_write_cached(chip, i, 18, value); } static void update_cs2000_rate(struct oxygen *chip, unsigned int rate) { struct xonar_pcm179x *data = chip->model_data; u8 rate_mclk, reg; switch (rate) { case 32000: case 64000: rate_mclk = OXYGEN_RATE_32000; break; case 44100: case 88200: case 176400: rate_mclk = OXYGEN_RATE_44100; break; default: case 48000: case 96000: case 192000: rate_mclk = OXYGEN_RATE_48000; break; } if (rate <= 96000 && (rate > 48000 || data->h6)) { rate_mclk |= OXYGEN_I2S_MCLK(MCLK_256); reg = CS2000_REF_CLK_DIV_1; } else { rate_mclk |= OXYGEN_I2S_MCLK(MCLK_512); reg = CS2000_REF_CLK_DIV_2; } oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, rate_mclk, OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_MCLK_MASK); cs2000_write_cached(chip, CS2000_FUN_CFG_1, reg); msleep(3); /* PLL lock delay */ } static void set_st_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { update_cs2000_rate(chip, params_rate(params)); set_pcm1796_params(chip, params); } static void set_hdav_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct xonar_hdav *data = chip->model_data; set_pcm1796_params(chip, params); xonar_set_hdmi_params(chip, &data->hdmi, params); } static const struct snd_kcontrol_new alt_switch = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Loopback Switch", .info = snd_ctl_boolean_mono_info, .get = xonar_gpio_bit_switch_get, .put = xonar_gpio_bit_switch_put, .private_value = GPIO_D2_ALT, }; static int rolloff_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "Sharp Roll-off", "Slow Roll-off" }; return snd_ctl_enum_info(info, 1, 2, names); } static int rolloff_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; value->value.enumerated.item[0] = (data->pcm1796_regs[0][19 - PCM1796_REG_BASE] & PCM1796_FLT_MASK) != PCM1796_FLT_SHARP; return 0; } static int rolloff_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; unsigned int i; int changed; u8 reg; mutex_lock(&chip->mutex); reg = data->pcm1796_regs[0][19 - PCM1796_REG_BASE]; reg &= ~PCM1796_FLT_MASK; if (!value->value.enumerated.item[0]) reg |= PCM1796_FLT_SHARP; else reg |= PCM1796_FLT_SLOW; changed = reg != data->pcm1796_regs[0][19 - PCM1796_REG_BASE]; if (changed) { for (i = 0; i < data->dacs; ++i) pcm1796_write(chip, i, 19, reg); } mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new rolloff_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DAC Filter Playback Enum", .info = rolloff_info, .get = rolloff_get, .put = rolloff_put, }; static int deemph_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; value->value.integer.value[0] = !!(data->pcm1796_regs[0][18 - PCM1796_REG_BASE] & PCM1796_DME); return 0; } static int deemph_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; unsigned int i; int changed; u8 reg; mutex_lock(&chip->mutex); reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE]; if (!value->value.integer.value[0]) reg &= ~PCM1796_DME; else reg |= PCM1796_DME; changed = reg != data->pcm1796_regs[0][18 - PCM1796_REG_BASE]; if (changed) { for (i = 0; i < data->dacs; ++i) pcm1796_write(chip, i, 18, reg); } mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new deemph_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "De-emphasis Playback Switch", .info = snd_ctl_boolean_mono_info, .get = deemph_get, .put = deemph_put, }; static const struct snd_kcontrol_new hdav_hdmi_control = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "HDMI Playback Switch", .info = snd_ctl_boolean_mono_info, .get = xonar_gpio_bit_switch_get, .put = xonar_gpio_bit_switch_put, .private_value = GPIO_HDAV_OUTPUT_ENABLE | XONAR_GPIO_BIT_INVERT, }; static int st_output_switch_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[3] = { "Speakers", "Headphones", "FP Headphones" }; return snd_ctl_enum_info(info, 1, 3, names); } static int st_output_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 gpio; gpio = oxygen_read16(chip, OXYGEN_GPIO_DATA); if (!(gpio & GPIO_ST_HP)) value->value.enumerated.item[0] = 0; else if (gpio & GPIO_ST_HP_REAR) value->value.enumerated.item[0] = 1; else value->value.enumerated.item[0] = 2; return 0; } static int st_output_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; u16 gpio_old, gpio; mutex_lock(&chip->mutex); gpio_old = oxygen_read16(chip, OXYGEN_GPIO_DATA); gpio = gpio_old; switch (value->value.enumerated.item[0]) { case 0: gpio &= ~(GPIO_ST_HP | GPIO_ST_HP_REAR); break; case 1: gpio |= GPIO_ST_HP | GPIO_ST_HP_REAR; break; case 2: gpio = (gpio | GPIO_ST_HP) & ~GPIO_ST_HP_REAR; break; } oxygen_write16(chip, OXYGEN_GPIO_DATA, gpio); data->hp_active = gpio & GPIO_ST_HP; update_pcm1796_volume(chip); mutex_unlock(&chip->mutex); return gpio != gpio_old; } static int st_hp_volume_offset_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[4] = { "< 32 ohms", "32-64 ohms", "64-300 ohms", "300-600 ohms" }; return snd_ctl_enum_info(info, 1, 4, names); } static int st_hp_volume_offset_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; mutex_lock(&chip->mutex); if (data->hp_gain_offset < 2*-12) value->value.enumerated.item[0] = 0; else if (data->hp_gain_offset < 2*-6) value->value.enumerated.item[0] = 1; else if (data->hp_gain_offset < 0) value->value.enumerated.item[0] = 2; else value->value.enumerated.item[0] = 3; mutex_unlock(&chip->mutex); return 0; } static int st_hp_volume_offset_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { static const s8 offsets[] = { 2*-18, 2*-12, 2*-6, 0 }; struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; s8 offset; int changed; if (value->value.enumerated.item[0] > 3) return -EINVAL; offset = offsets[value->value.enumerated.item[0]]; mutex_lock(&chip->mutex); changed = offset != data->hp_gain_offset; if (changed) { data->hp_gain_offset = offset; update_pcm1796_volume(chip); } mutex_unlock(&chip->mutex); return changed; } static const struct snd_kcontrol_new st_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Output", .info = st_output_switch_info, .get = st_output_switch_get, .put = st_output_switch_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphones Impedance Playback Enum", .info = st_hp_volume_offset_info, .get = st_hp_volume_offset_get, .put = st_hp_volume_offset_put, }, }; static int xense_output_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 gpio; gpio = oxygen_read16(chip, OXYGEN_GPIO_DATA); if (gpio & GPIO_XENSE_SPEAKERS) value->value.enumerated.item[0] = 0; else if (!(gpio & GPIO_XENSE_SPEAKERS) && (gpio & GPIO_ST_HP_REAR)) value->value.enumerated.item[0] = 1; else value->value.enumerated.item[0] = 2; return 0; } static int xense_output_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_pcm179x *data = chip->model_data; u16 gpio_old, gpio; mutex_lock(&chip->mutex); gpio_old = oxygen_read16(chip, OXYGEN_GPIO_DATA); gpio = gpio_old; switch (value->value.enumerated.item[0]) { case 0: gpio |= GPIO_XENSE_SPEAKERS | GPIO_ST_HP_REAR; break; case 1: gpio = (gpio | GPIO_ST_HP_REAR) & ~GPIO_XENSE_SPEAKERS; break; case 2: gpio &= ~(GPIO_XENSE_SPEAKERS | GPIO_ST_HP_REAR); break; } oxygen_write16(chip, OXYGEN_GPIO_DATA, gpio); data->hp_active = !(gpio & GPIO_XENSE_SPEAKERS); update_pcm1796_volume(chip); mutex_unlock(&chip->mutex); return gpio != gpio_old; } static const struct snd_kcontrol_new xense_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Output", .info = st_output_switch_info, .get = xense_output_switch_get, .put = xense_output_switch_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphones Impedance Playback Enum", .info = st_hp_volume_offset_info, .get = st_hp_volume_offset_get, .put = st_hp_volume_offset_put, }, }; static void xonar_line_mic_ac97_switch(struct oxygen *chip, unsigned int reg, unsigned int mute) { if (reg == AC97_LINE) { spin_lock_irq(&chip->reg_lock); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, mute ? GPIO_INPUT_ROUTE : 0, GPIO_INPUT_ROUTE); spin_unlock_irq(&chip->reg_lock); } } static const DECLARE_TLV_DB_SCALE(pcm1796_db_scale, -6000, 50, 0); static int xonar_d2_control_filter(struct snd_kcontrol_new *template) { if (!strncmp(template->name, "CD Capture ", 11)) /* CD in is actually connected to the video in pin */ template->private_value ^= AC97_CD ^ AC97_VIDEO; return 0; } static int xonar_st_h6_control_filter(struct snd_kcontrol_new *template) { if (!strncmp(template->name, "Master Playback ", 16)) /* no volume/mute, as I²C to the third DAC does not work */ return 1; return 0; } static int add_pcm1796_controls(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; int err; if (!data->broken_i2c) { err = snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&deemph_control, chip)); if (err < 0) return err; } return 0; } static int xonar_d2_mixer_init(struct oxygen *chip) { int err; err = snd_ctl_add(chip->card, snd_ctl_new1(&alt_switch, chip)); if (err < 0) return err; err = add_pcm1796_controls(chip); if (err < 0) return err; return 0; } static int xonar_hdav_mixer_init(struct oxygen *chip) { int err; err = snd_ctl_add(chip->card, snd_ctl_new1(&hdav_hdmi_control, chip)); if (err < 0) return err; err = add_pcm1796_controls(chip); if (err < 0) return err; return 0; } static int xonar_st_mixer_init(struct oxygen *chip) { unsigned int i; int err; for (i = 0; i < ARRAY_SIZE(st_controls); ++i) { err = snd_ctl_add(chip->card, snd_ctl_new1(&st_controls[i], chip)); if (err < 0) return err; } err = add_pcm1796_controls(chip); if (err < 0) return err; return 0; } static int xonar_xense_mixer_init(struct oxygen *chip) { unsigned int i; int err; for (i = 0; i < ARRAY_SIZE(xense_controls); ++i) { err = snd_ctl_add(chip->card, snd_ctl_new1(&xense_controls[i], chip)); if (err < 0) return err; } err = add_pcm1796_controls(chip); if (err < 0) return err; return 0; } static void dump_pcm1796_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct xonar_pcm179x *data = chip->model_data; unsigned int dac, i; for (dac = 0; dac < data->dacs; ++dac) { snd_iprintf(buffer, "\nPCM1796 %u:", dac + 1); for (i = 0; i < 5; ++i) snd_iprintf(buffer, " %02x", data->pcm1796_regs[dac][i]); } snd_iprintf(buffer, "\n"); } static void dump_cs2000_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct xonar_pcm179x *data = chip->model_data; unsigned int i; if (data->has_cs2000) { snd_iprintf(buffer, "\nCS2000:\n00: "); for (i = 1; i < 0x10; ++i) snd_iprintf(buffer, " %02x", data->cs2000_regs[i]); snd_iprintf(buffer, "\n10:"); for (i = 0x10; i < 0x1f; ++i) snd_iprintf(buffer, " %02x", data->cs2000_regs[i]); snd_iprintf(buffer, "\n"); } } static void dump_st_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { dump_pcm1796_registers(chip, buffer); dump_cs2000_registers(chip, buffer); } static const struct oxygen_model model_xonar_d2 = { .longname = "Asus Virtuoso 200", .chip = "AV200", .init = xonar_d2_init, .control_filter = xonar_d2_control_filter, .mixer_init = xonar_d2_mixer_init, .cleanup = xonar_d2_cleanup, .suspend = xonar_d2_suspend, .resume = xonar_d2_resume, .set_dac_params = set_pcm1796_params, .set_adc_params = xonar_set_cs53x1_params, .update_dac_volume = update_pcm1796_volume, .update_dac_mute = update_pcm1796_mute, .dump_registers = dump_pcm1796_registers, .dac_tlv = pcm1796_db_scale, .model_data_size = sizeof(struct xonar_pcm179x), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF | MIDI_OUTPUT | MIDI_INPUT | AC97_CD_INPUT, .dac_channels_pcm = 8, .dac_channels_mixer = 8, .dac_volume_min = 255 - 2*60, .dac_volume_max = 255, .misc_flags = OXYGEN_MISC_MIDI, .function_flags = OXYGEN_FUNCTION_SPI | OXYGEN_FUNCTION_ENABLE_SPI_4_5, .dac_mclks = OXYGEN_MCLKS(512, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 128, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; static const struct oxygen_model model_xonar_hdav = { .longname = "Asus Virtuoso 200", .chip = "AV200", .init = xonar_hdav_init, .mixer_init = xonar_hdav_mixer_init, .cleanup = xonar_hdav_cleanup, .suspend = xonar_hdav_suspend, .resume = xonar_hdav_resume, .pcm_hardware_filter = xonar_hdmi_pcm_hardware_filter, .set_dac_params = set_hdav_params, .set_adc_params = xonar_set_cs53x1_params, .update_dac_volume = update_pcm1796_volume, .update_dac_mute = update_pcm1796_mute, .uart_input = xonar_hdmi_uart_input, .ac97_switch = xonar_line_mic_ac97_switch, .dump_registers = dump_pcm1796_registers, .dac_tlv = pcm1796_db_scale, .model_data_size = sizeof(struct xonar_hdav), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF, .dac_channels_pcm = 8, .dac_channels_mixer = 2, .dac_volume_min = 255 - 2*60, .dac_volume_max = 255, .misc_flags = OXYGEN_MISC_MIDI, .function_flags = OXYGEN_FUNCTION_2WIRE, .dac_mclks = OXYGEN_MCLKS(512, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 128, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; static const struct oxygen_model model_xonar_st = { .longname = "Asus Virtuoso 100", .chip = "AV200", .init = xonar_st_init, .mixer_init = xonar_st_mixer_init, .cleanup = xonar_st_cleanup, .suspend = xonar_st_suspend, .resume = xonar_st_resume, .set_dac_params = set_st_params, .set_adc_params = xonar_set_cs53x1_params, .update_dac_volume = update_pcm1796_volume, .update_dac_mute = update_pcm1796_mute, .ac97_switch = xonar_line_mic_ac97_switch, .dump_registers = dump_st_registers, .dac_tlv = pcm1796_db_scale, .model_data_size = sizeof(struct xonar_pcm179x), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_2 | CAPTURE_1_FROM_SPDIF | AC97_FMIC_SWITCH, .dac_channels_pcm = 2, .dac_channels_mixer = 2, .dac_volume_min = 255 - 2*60, .dac_volume_max = 255, .function_flags = OXYGEN_FUNCTION_2WIRE, .dac_mclks = OXYGEN_MCLKS(512, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 128, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; int get_xonar_pcm179x_model(struct oxygen *chip, const struct pci_device_id *id) { switch (id->subdevice) { case 0x8269: chip->model = model_xonar_d2; chip->model.shortname = "Xonar D2"; break; case 0x82b7: chip->model = model_xonar_d2; chip->model.shortname = "Xonar D2X"; chip->model.init = xonar_d2x_init; break; case 0x8314: chip->model = model_xonar_hdav; oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK); switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) { default: chip->model.shortname = "Xonar HDAV1.3"; break; case GPIO_DB_H6: chip->model.shortname = "Xonar HDAV1.3+H6"; chip->model.dac_channels_mixer = 8; chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128); break; } break; case 0x835d: chip->model = model_xonar_st; oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK); switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) { default: chip->model.shortname = "Xonar ST"; break; case GPIO_DB_H6: chip->model.shortname = "Xonar ST+H6"; chip->model.control_filter = xonar_st_h6_control_filter; chip->model.dac_channels_pcm = 8; chip->model.dac_channels_mixer = 8; chip->model.dac_volume_min = 255; chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128); break; } break; case 0x835c: chip->model = model_xonar_st; chip->model.shortname = "Xonar STX"; chip->model.init = xonar_stx_init; chip->model.resume = xonar_stx_resume; chip->model.set_dac_params = set_pcm1796_params; break; case 0x85f4: chip->model = model_xonar_st; oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK); switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) { default: chip->model.shortname = "Xonar STX II"; break; case GPIO_DB_H6: chip->model.shortname = "Xonar STX II+H6"; chip->model.dac_channels_pcm = 8; chip->model.dac_channels_mixer = 8; chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128); break; } chip->model.init = xonar_stx_init; chip->model.resume = xonar_stx_resume; chip->model.set_dac_params = set_pcm1796_params; break; case 0x8428: chip->model = model_xonar_st; chip->model.shortname = "Xonar Xense"; chip->model.chip = "AV100"; chip->model.init = xonar_xense_init; chip->model.mixer_init = xonar_xense_mixer_init; break; default: return -EINVAL; } return 0; }
linux-master
sound/pci/oxygen/xonar_pcm179x.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver - main driver module * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/mutex.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/ac97_codec.h> #include <sound/asoundef.h> #include <sound/core.h> #include <sound/info.h> #include <sound/mpu401.h> #include <sound/pcm.h> #include "oxygen.h" #include "cm9780.h" MODULE_AUTHOR("Clemens Ladisch <[email protected]>"); MODULE_DESCRIPTION("C-Media CMI8788 helper library"); MODULE_LICENSE("GPL v2"); #define DRIVER "oxygen" static inline int oxygen_uart_input_ready(struct oxygen *chip) { return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY); } static void oxygen_read_uart(struct oxygen *chip) { if (unlikely(!oxygen_uart_input_ready(chip))) { /* no data, but read it anyway to clear the interrupt */ oxygen_read8(chip, OXYGEN_MPU401); return; } do { u8 data = oxygen_read8(chip, OXYGEN_MPU401); if (data == MPU401_ACK) continue; if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input)) chip->uart_input_count = 0; chip->uart_input[chip->uart_input_count++] = data; } while (oxygen_uart_input_ready(chip)); if (chip->model.uart_input) chip->model.uart_input(chip); } static irqreturn_t oxygen_interrupt(int dummy, void *dev_id) { struct oxygen *chip = dev_id; unsigned int status, clear, elapsed_streams, i; status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS); if (!status) return IRQ_NONE; spin_lock(&chip->reg_lock); clear = status & (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B | OXYGEN_CHANNEL_C | OXYGEN_CHANNEL_SPDIF | OXYGEN_CHANNEL_MULTICH | OXYGEN_CHANNEL_AC97 | OXYGEN_INT_SPDIF_IN_DETECT | OXYGEN_INT_GPIO | OXYGEN_INT_AC97); if (clear) { if (clear & OXYGEN_INT_SPDIF_IN_DETECT) chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT; oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask & ~clear); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); } elapsed_streams = status & chip->pcm_running; spin_unlock(&chip->reg_lock); for (i = 0; i < PCM_COUNT; ++i) if ((elapsed_streams & (1 << i)) && chip->streams[i]) snd_pcm_period_elapsed(chip->streams[i]); if (status & OXYGEN_INT_SPDIF_IN_DETECT) { spin_lock(&chip->reg_lock); i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT | OXYGEN_SPDIF_RATE_INT)) { /* write the interrupt bit(s) to clear */ oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); schedule_work(&chip->spdif_input_bits_work); } spin_unlock(&chip->reg_lock); } if (status & OXYGEN_INT_GPIO) schedule_work(&chip->gpio_work); if (status & OXYGEN_INT_MIDI) { if (chip->midi) snd_mpu401_uart_interrupt(0, chip->midi->private_data); else oxygen_read_uart(chip); } if (status & OXYGEN_INT_AC97) wake_up(&chip->ac97_waitqueue); return IRQ_HANDLED; } static void oxygen_spdif_input_bits_changed(struct work_struct *work) { struct oxygen *chip = container_of(work, struct oxygen, spdif_input_bits_work); u32 reg; /* * This function gets called when there is new activity on the SPDIF * input, or when we lose lock on the input signal, or when the rate * changes. */ msleep(1); spin_lock_irq(&chip->reg_lock); reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | OXYGEN_SPDIF_LOCK_STATUS)) == OXYGEN_SPDIF_SENSE_STATUS) { /* * If we detect activity on the SPDIF input but cannot lock to * a signal, the clock bit is likely to be wrong. */ reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); spin_unlock_irq(&chip->reg_lock); msleep(1); spin_lock_irq(&chip->reg_lock); reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | OXYGEN_SPDIF_LOCK_STATUS)) == OXYGEN_SPDIF_SENSE_STATUS) { /* nothing detected with either clock; give up */ if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) == OXYGEN_SPDIF_IN_CLOCK_192) { /* * Reset clock to <= 96 kHz because this is * more likely to be received next time. */ reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; reg |= OXYGEN_SPDIF_IN_CLOCK_96; oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); } } } spin_unlock_irq(&chip->reg_lock); if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { spin_lock_irq(&chip->reg_lock); chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); spin_unlock_irq(&chip->reg_lock); /* * We don't actually know that any channel status bits have * changed, but let's send a notification just to be sure. */ snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id); } } static void oxygen_gpio_changed(struct work_struct *work) { struct oxygen *chip = container_of(work, struct oxygen, gpio_work); if (chip->model.gpio_changed) chip->model.gpio_changed(chip); } static void oxygen_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct oxygen *chip = entry->private_data; int i, j; switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) { case OXYGEN_PACKAGE_ID_8786: i = '6'; break; case OXYGEN_PACKAGE_ID_8787: i = '7'; break; case OXYGEN_PACKAGE_ID_8788: i = '8'; break; default: i = '?'; break; } snd_iprintf(buffer, "CMI878%c:\n", i); for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) { snd_iprintf(buffer, "%02x:", i); for (j = 0; j < 0x10; ++j) snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j)); snd_iprintf(buffer, "\n"); } if (mutex_lock_interruptible(&chip->mutex) < 0) return; if (chip->has_ac97_0) { snd_iprintf(buffer, "\nAC97:\n"); for (i = 0; i < 0x80; i += 0x10) { snd_iprintf(buffer, "%02x:", i); for (j = 0; j < 0x10; j += 2) snd_iprintf(buffer, " %04x", oxygen_read_ac97(chip, 0, i + j)); snd_iprintf(buffer, "\n"); } } if (chip->has_ac97_1) { snd_iprintf(buffer, "\nAC97 2:\n"); for (i = 0; i < 0x80; i += 0x10) { snd_iprintf(buffer, "%02x:", i); for (j = 0; j < 0x10; j += 2) snd_iprintf(buffer, " %04x", oxygen_read_ac97(chip, 1, i + j)); snd_iprintf(buffer, "\n"); } } mutex_unlock(&chip->mutex); if (chip->model.dump_registers) chip->model.dump_registers(chip, buffer); } static void oxygen_proc_init(struct oxygen *chip) { snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read); } static const struct pci_device_id * oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[]) { u16 subdevice; /* * Make sure the EEPROM pins are available, i.e., not used for SPI. * (This function is called before we initialize or use SPI.) */ oxygen_clear_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_ENABLE_SPI_4_5); /* * Read the subsystem device ID directly from the EEPROM, because the * chip didn't if the first EEPROM word was overwritten. */ subdevice = oxygen_read_eeprom(chip, 2); /* use default ID if EEPROM is missing */ if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff) subdevice = 0x8788; /* * We use only the subsystem device ID for searching because it is * unique even without the subsystem vendor ID, which may have been * overwritten in the EEPROM. */ for (; ids->vendor; ++ids) if (ids->subdevice == subdevice && ids->driver_data != BROKEN_EEPROM_DRIVER_DATA) return ids; return NULL; } static void oxygen_restore_eeprom(struct oxygen *chip, const struct pci_device_id *id) { u16 eeprom_id; eeprom_id = oxygen_read_eeprom(chip, 0); if (eeprom_id != OXYGEN_EEPROM_ID && (eeprom_id != 0xffff || id->subdevice != 0x8788)) { /* * This function gets called only when a known card model has * been detected, i.e., we know there is a valid subsystem * product ID at index 2 in the EEPROM. Therefore, we have * been able to deduce the correct subsystem vendor ID, and * this is enough information to restore the original EEPROM * contents. */ oxygen_write_eeprom(chip, 1, id->subvendor); oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID); oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_WRITE_PCI_SUBID); pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, id->subvendor); pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID, id->subdevice); oxygen_clear_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_WRITE_PCI_SUBID); dev_info(chip->card->dev, "EEPROM ID restored\n"); } } static void configure_pcie_bridge(struct pci_dev *pci) { enum { PEX811X, PI7C9X110, XIO2001 }; static const struct pci_device_id bridge_ids[] = { { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X }, { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X }, { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 }, { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 }, { } }; struct pci_dev *bridge; const struct pci_device_id *id; u32 tmp; if (!pci->bus || !pci->bus->self) return; bridge = pci->bus->self; id = pci_match_id(bridge_ids, bridge); if (!id) return; switch (id->driver_data) { case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */ pci_read_config_dword(bridge, 0x48, &tmp); tmp |= 1; /* enable blind prefetching */ tmp |= 1 << 11; /* enable beacon generation */ pci_write_config_dword(bridge, 0x48, tmp); pci_write_config_dword(bridge, 0x84, 0x0c); pci_read_config_dword(bridge, 0x88, &tmp); tmp &= ~(7 << 27); tmp |= 2 << 27; /* set prefetch size to 128 bytes */ pci_write_config_dword(bridge, 0x88, tmp); break; case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */ pci_read_config_dword(bridge, 0x40, &tmp); tmp |= 1; /* park the PCI arbiter to the sound chip */ pci_write_config_dword(bridge, 0x40, tmp); break; case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */ pci_read_config_dword(bridge, 0xe8, &tmp); tmp &= ~0xf; /* request length limit: 64 bytes */ tmp &= ~(0xf << 8); tmp |= 1 << 8; /* request count limit: one buffer */ pci_write_config_dword(bridge, 0xe8, tmp); break; } } static void oxygen_init(struct oxygen *chip) { unsigned int i; chip->dac_routing = 1; for (i = 0; i < 8; ++i) chip->dac_volume[i] = chip->model.dac_volume_min; chip->dac_mute = 1; chip->spdif_playback_enable = 0; chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); chip->spdif_pcm_bits = chip->spdif_bits; if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)) oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_PCI_MEM_W_1_CLOCK); i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; oxygen_write8_masked(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC | chip->model.function_flags, OXYGEN_FUNCTION_RESET_CODEC | OXYGEN_FUNCTION_2WIRE_SPI_MASK | OXYGEN_FUNCTION_ENABLE_SPI_4_5); oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, OXYGEN_PLAY_CHANNELS_2 | OXYGEN_DMA_A_BURST_8 | OXYGEN_DMA_MULTICH_BURST_8); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); oxygen_write8_masked(chip, OXYGEN_MISC, chip->model.misc_flags, OXYGEN_MISC_WRITE_PCI_SUBID | OXYGEN_MISC_REC_C_FROM_SPDIF | OXYGEN_MISC_REC_B_FROM_AC97 | OXYGEN_MISC_REC_A_FROM_MULTICH | OXYGEN_MISC_MIDI); oxygen_write8(chip, OXYGEN_REC_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); oxygen_write8(chip, OXYGEN_PLAY_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, OXYGEN_RATE_48000 | chip->model.dac_i2s_format | OXYGEN_I2S_MCLK(chip->model.dac_mclks) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK(chip->model.adc_mclks) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | CAPTURE_2_FROM_I2S_2)) oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK(chip->model.adc_mclks) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); if (chip->model.device_config & CAPTURE_3_FROM_I2S_3) oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK(chip->model.adc_mclks) | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE | OXYGEN_SPDIF_LOOPBACK); if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_96, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_SENSE_PAR | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_MASK); else oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK); oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_STANDARD); oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF | (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); oxygen_write8(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_A_ROUTE_I2S_ADC_1 | OXYGEN_REC_B_ROUTE_I2S_ADC_2 | OXYGEN_REC_C_ROUTE_SPDIF); oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); if (chip->has_ac97_0 | chip->has_ac97_1) oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, OXYGEN_AC97_INT_READ_DONE | OXYGEN_AC97_INT_WRITE_DONE); else oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); if (!(chip->has_ac97_0 | chip->has_ac97_1)) oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_CLOCK_DISABLE); if (!chip->has_ac97_0) { oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_NO_CODEC_0); } else { oxygen_write_ac97(chip, 0, AC97_RESET, 0); msleep(1); oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, CM9780_GPIO0IO | CM9780_GPIO1IO); oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, CM9780_BSTSEL | CM9780_STRO_MIC | CM9780_MIX2FR | CM9780_PCBSW); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_RSOE | CM9780_CBOE | CM9780_SSOE | CM9780_FROE | CM9780_MIC2MIC | CM9780_LI2LI); oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, CM9780_GPO0); /* power down unused ADCs and DACs */ oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, AC97_PD_PR0 | AC97_PD_PR1); oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); } if (chip->has_ac97_1) { oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, OXYGEN_AC97_CODEC1_SLOT3 | OXYGEN_AC97_CODEC1_SLOT4); oxygen_write_ac97(chip, 1, AC97_RESET, 0); msleep(1); oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); } } static void oxygen_shutdown(struct oxygen *chip) { spin_lock_irq(&chip->reg_lock); chip->interrupt_mask = 0; chip->pcm_running = 0; oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); spin_unlock_irq(&chip->reg_lock); } static void oxygen_card_free(struct snd_card *card) { struct oxygen *chip = card->private_data; oxygen_shutdown(chip); flush_work(&chip->spdif_input_bits_work); flush_work(&chip->gpio_work); chip->model.cleanup(chip); mutex_destroy(&chip->mutex); } static int __oxygen_pci_probe(struct pci_dev *pci, int index, char *id, struct module *owner, const struct pci_device_id *ids, int (*get_model)(struct oxygen *chip, const struct pci_device_id *id ) ) { struct snd_card *card; struct oxygen *chip; const struct pci_device_id *pci_id; int err; err = snd_devm_card_new(&pci->dev, index, id, owner, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; chip->card = card; chip->pci = pci; chip->irq = -1; spin_lock_init(&chip->reg_lock); mutex_init(&chip->mutex); INIT_WORK(&chip->spdif_input_bits_work, oxygen_spdif_input_bits_changed); INIT_WORK(&chip->gpio_work, oxygen_gpio_changed); init_waitqueue_head(&chip->ac97_waitqueue); err = pcim_enable_device(pci); if (err < 0) return err; err = pci_request_regions(pci, DRIVER); if (err < 0) { dev_err(card->dev, "cannot reserve PCI resources\n"); return err; } if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) || pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) { dev_err(card->dev, "invalid PCI I/O range\n"); return -ENXIO; } chip->addr = pci_resource_start(pci, 0); pci_id = oxygen_search_pci_id(chip, ids); if (!pci_id) return -ENODEV; oxygen_restore_eeprom(chip, pci_id); err = get_model(chip, pci_id); if (err < 0) return err; if (chip->model.model_data_size) { chip->model_data = devm_kzalloc(&pci->dev, chip->model.model_data_size, GFP_KERNEL); if (!chip->model_data) return -ENOMEM; } pci_set_master(pci); card->private_free = oxygen_card_free; configure_pcie_bridge(pci); oxygen_init(chip); chip->model.init(chip); err = devm_request_irq(&pci->dev, pci->irq, oxygen_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip); if (err < 0) { dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq); return err; } chip->irq = pci->irq; card->sync_irq = chip->irq; strcpy(card->driver, chip->model.chip); strcpy(card->shortname, chip->model.shortname); sprintf(card->longname, "%s at %#lx, irq %i", chip->model.longname, chip->addr, chip->irq); strcpy(card->mixername, chip->model.chip); snd_component_add(card, chip->model.chip); err = oxygen_pcm_init(chip); if (err < 0) return err; err = oxygen_mixer_init(chip); if (err < 0) return err; if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) { unsigned int info_flags = MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK; if (chip->model.device_config & MIDI_OUTPUT) info_flags |= MPU401_INFO_OUTPUT; if (chip->model.device_config & MIDI_INPUT) info_flags |= MPU401_INFO_INPUT; err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, chip->addr + OXYGEN_MPU401, info_flags, -1, &chip->midi); if (err < 0) return err; } oxygen_proc_init(chip); spin_lock_irq(&chip->reg_lock); if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; if (chip->has_ac97_0 | chip->has_ac97_1) chip->interrupt_mask |= OXYGEN_INT_AC97; oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); spin_unlock_irq(&chip->reg_lock); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); return 0; } int oxygen_pci_probe(struct pci_dev *pci, int index, char *id, struct module *owner, const struct pci_device_id *ids, int (*get_model)(struct oxygen *chip, const struct pci_device_id *id)) { return snd_card_free_on_error(&pci->dev, __oxygen_pci_probe(pci, index, id, owner, ids, get_model)); } EXPORT_SYMBOL(oxygen_pci_probe); #ifdef CONFIG_PM_SLEEP static int oxygen_pci_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct oxygen *chip = card->private_data; unsigned int saved_interrupt_mask; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); if (chip->model.suspend) chip->model.suspend(chip); spin_lock_irq(&chip->reg_lock); saved_interrupt_mask = chip->interrupt_mask; chip->interrupt_mask = 0; oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); spin_unlock_irq(&chip->reg_lock); flush_work(&chip->spdif_input_bits_work); flush_work(&chip->gpio_work); chip->interrupt_mask = saved_interrupt_mask; return 0; } static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = { 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff, 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000 }; static const u32 ac97_registers_to_restore[2][0x40 / 32] = { { 0x18284fa2, 0x03060000 }, { 0x00007fa6, 0x00200000 } }; static inline int is_bit_set(const u32 *bitmap, unsigned int bit) { return bitmap[bit / 32] & (1 << (bit & 31)); } static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec) { unsigned int i; oxygen_write_ac97(chip, codec, AC97_RESET, 0); msleep(1); for (i = 1; i < 0x40; ++i) if (is_bit_set(ac97_registers_to_restore[codec], i)) oxygen_write_ac97(chip, codec, i * 2, chip->saved_ac97_registers[codec][i]); } static int oxygen_pci_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct oxygen *chip = card->private_data; unsigned int i; oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); for (i = 0; i < OXYGEN_IO_SIZE; ++i) if (is_bit_set(registers_to_restore, i)) oxygen_write8(chip, i, chip->saved_registers._8[i]); if (chip->has_ac97_0) oxygen_restore_ac97(chip, 0); if (chip->has_ac97_1) oxygen_restore_ac97(chip, 1); if (chip->model.resume) chip->model.resume(chip); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume); EXPORT_SYMBOL(oxygen_pci_pm); #endif /* CONFIG_PM_SLEEP */ void oxygen_pci_shutdown(struct pci_dev *pci) { struct snd_card *card = pci_get_drvdata(pci); struct oxygen *chip = card->private_data; oxygen_shutdown(chip); chip->model.cleanup(chip); } EXPORT_SYMBOL(oxygen_pci_shutdown);
linux-master
sound/pci/oxygen/oxygen_lib.c
// SPDX-License-Identifier: GPL-2.0-only /* * helper functions for Asus Xonar cards * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/delay.h> #include <sound/core.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include "xonar.h" #define GPIO_CS53x1_M_MASK 0x000c #define GPIO_CS53x1_M_SINGLE 0x0000 #define GPIO_CS53x1_M_DOUBLE 0x0004 #define GPIO_CS53x1_M_QUAD 0x0008 void xonar_enable_output(struct oxygen *chip) { struct xonar_generic *data = chip->model_data; oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, data->output_enable_bit); msleep(data->anti_pop_delay); oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, data->output_enable_bit); } void xonar_disable_output(struct oxygen *chip) { struct xonar_generic *data = chip->model_data; oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, data->output_enable_bit); } static void xonar_ext_power_gpio_changed(struct oxygen *chip) { struct xonar_generic *data = chip->model_data; u8 has_power; has_power = !!(oxygen_read8(chip, data->ext_power_reg) & data->ext_power_bit); if (has_power != data->has_power) { data->has_power = has_power; if (has_power) { dev_notice(chip->card->dev, "power restored\n"); } else { dev_crit(chip->card->dev, "Hey! Don't unplug the power cable!\n"); /* TODO: stop PCMs */ } } } void xonar_init_ext_power(struct oxygen *chip) { struct xonar_generic *data = chip->model_data; oxygen_set_bits8(chip, data->ext_power_int_reg, data->ext_power_bit); chip->interrupt_mask |= OXYGEN_INT_GPIO; chip->model.gpio_changed = xonar_ext_power_gpio_changed; data->has_power = !!(oxygen_read8(chip, data->ext_power_reg) & data->ext_power_bit); } void xonar_init_cs53x1(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CS53x1_M_MASK); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, GPIO_CS53x1_M_SINGLE, GPIO_CS53x1_M_MASK); } void xonar_set_cs53x1_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { unsigned int value; if (params_rate(params) <= 54000) value = GPIO_CS53x1_M_SINGLE; else if (params_rate(params) <= 108000) value = GPIO_CS53x1_M_DOUBLE; else value = GPIO_CS53x1_M_QUAD; oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, value, GPIO_CS53x1_M_MASK); } int xonar_gpio_bit_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 bit = ctl->private_value; bool invert = ctl->private_value & XONAR_GPIO_BIT_INVERT; value->value.integer.value[0] = !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) & bit) ^ invert; return 0; } int xonar_gpio_bit_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 bit = ctl->private_value; bool invert = ctl->private_value & XONAR_GPIO_BIT_INVERT; u16 old_bits, new_bits; int changed; spin_lock_irq(&chip->reg_lock); old_bits = oxygen_read16(chip, OXYGEN_GPIO_DATA); if (!!value->value.integer.value[0] ^ invert) new_bits = old_bits | bit; else new_bits = old_bits & ~bit; changed = new_bits != old_bits; if (changed) oxygen_write16(chip, OXYGEN_GPIO_DATA, new_bits); spin_unlock_irq(&chip->reg_lock); return changed; }
linux-master
sound/pci/oxygen/xonar_lib.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8787 driver for the Studio Evolution SE6X * * Copyright (c) Clemens Ladisch <[email protected]> */ /* * CMI8787: * * SPI -> microcontroller (not actually used) * GPIO 0 -> do. * GPIO 2 -> do. * * DAC0 -> both PCM1792A (L+R, each in mono mode) * ADC1 <- 1st PCM1804 * ADC2 <- 2nd PCM1804 * ADC3 <- 3rd PCM1804 */ #include <linux/pci.h> #include <linux/module.h> #include <sound/core.h> #include <sound/control.h> #include <sound/initval.h> #include <sound/pcm.h> #include "oxygen.h" MODULE_AUTHOR("Clemens Ladisch <[email protected]>"); MODULE_DESCRIPTION("Studio Evolution SE6X driver"); MODULE_LICENSE("GPL v2"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "card index"); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string"); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "enable card"); static const struct pci_device_id se6x_ids[] = { { OXYGEN_PCI_SUBID(0x13f6, 0x8788) }, { } }; MODULE_DEVICE_TABLE(pci, se6x_ids); static void se6x_init(struct oxygen *chip) { oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, 0x005); snd_component_add(chip->card, "PCM1792A"); snd_component_add(chip->card, "PCM1804"); } static int se6x_control_filter(struct snd_kcontrol_new *template) { /* no DAC volume/mute */ if (!strncmp(template->name, "Master Playback ", 16)) return 1; return 0; } static void se6x_cleanup(struct oxygen *chip) { } static void set_pcm1792a_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { /* nothing to do (the microcontroller monitors DAC_LRCK) */ } static void set_pcm1804_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { } static unsigned int se6x_adjust_dac_routing(struct oxygen *chip, unsigned int play_routing) { /* route the same stereo pair to DAC0 and DAC1 */ return ( play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) | ((play_routing << 2) & OXYGEN_PLAY_DAC1_SOURCE_MASK); } static const struct oxygen_model model_se6x = { .shortname = "Studio Evolution SE6X", .longname = "C-Media Oxygen HD Audio", .chip = "CMI8787", .init = se6x_init, .control_filter = se6x_control_filter, .cleanup = se6x_cleanup, .set_dac_params = set_pcm1792a_params, .set_adc_params = set_pcm1804_params, .adjust_dac_routing = se6x_adjust_dac_routing, .device_config = PLAYBACK_0_TO_I2S | CAPTURE_0_FROM_I2S_1 | CAPTURE_2_FROM_I2S_2 | CAPTURE_3_FROM_I2S_3, .dac_channels_pcm = 2, .function_flags = OXYGEN_FUNCTION_SPI, .dac_mclks = OXYGEN_MCLKS(256, 128, 128), .adc_mclks = OXYGEN_MCLKS(256, 256, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_I2S, }; static int se6x_get_model(struct oxygen *chip, const struct pci_device_id *pci_id) { chip->model = model_se6x; return 0; } static int se6x_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { ++dev; return -ENOENT; } err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE, se6x_ids, se6x_get_model); if (err >= 0) ++dev; return err; } static struct pci_driver se6x_driver = { .name = KBUILD_MODNAME, .id_table = se6x_ids, .probe = se6x_probe, #ifdef CONFIG_PM_SLEEP .driver = { .pm = &oxygen_pci_pm, }, #endif .shutdown = oxygen_pci_shutdown, }; module_pci_driver(se6x_driver);
linux-master
sound/pci/oxygen/se6x.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver for Asus Xonar cards * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/pci.h> #include <linux/delay.h> #include <linux/module.h> #include <sound/core.h> #include <sound/initval.h> #include <sound/pcm.h> #include "xonar.h" MODULE_AUTHOR("Clemens Ladisch <[email protected]>"); MODULE_DESCRIPTION("Asus Virtuoso driver"); MODULE_LICENSE("GPL v2"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "card index"); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string"); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "enable card"); static const struct pci_device_id xonar_ids[] = { { OXYGEN_PCI_SUBID(0x1043, 0x8269) }, { OXYGEN_PCI_SUBID(0x1043, 0x8275) }, { OXYGEN_PCI_SUBID(0x1043, 0x82b7) }, { OXYGEN_PCI_SUBID(0x1043, 0x8314) }, { OXYGEN_PCI_SUBID(0x1043, 0x8327) }, { OXYGEN_PCI_SUBID(0x1043, 0x834f) }, { OXYGEN_PCI_SUBID(0x1043, 0x835c) }, { OXYGEN_PCI_SUBID(0x1043, 0x835d) }, { OXYGEN_PCI_SUBID(0x1043, 0x835e) }, { OXYGEN_PCI_SUBID(0x1043, 0x838e) }, { OXYGEN_PCI_SUBID(0x1043, 0x8428) }, { OXYGEN_PCI_SUBID(0x1043, 0x8522) }, { OXYGEN_PCI_SUBID(0x1043, 0x85f4) }, { OXYGEN_PCI_SUBID_BROKEN_EEPROM }, { } }; MODULE_DEVICE_TABLE(pci, xonar_ids); static int get_xonar_model(struct oxygen *chip, const struct pci_device_id *id) { if (get_xonar_pcm179x_model(chip, id) >= 0) return 0; if (get_xonar_cs43xx_model(chip, id) >= 0) return 0; if (get_xonar_wm87x6_model(chip, id) >= 0) return 0; return -EINVAL; } static int xonar_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { ++dev; return -ENOENT; } err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE, xonar_ids, get_xonar_model); if (err >= 0) ++dev; return err; } static struct pci_driver xonar_driver = { .name = KBUILD_MODNAME, .id_table = xonar_ids, .probe = xonar_probe, #ifdef CONFIG_PM_SLEEP .driver = { .pm = &oxygen_pci_pm, }, #endif .shutdown = oxygen_pci_shutdown, }; module_pci_driver(xonar_driver);
linux-master
sound/pci/oxygen/virtuoso.c
// SPDX-License-Identifier: GPL-2.0-only /* * card driver for the Xonar DG/DGX * * Copyright (c) Clemens Ladisch <[email protected]> * Copyright (c) Roman Volkov <[email protected]> */ /* * Xonar DG/DGX * ------------ * * CS4245 and CS4361 both will mute all outputs if any clock ratio * is invalid. * * CMI8788: * * SPI 0 -> CS4245 * * Playback: * I²S 1 -> CS4245 * I²S 2 -> CS4361 (center/LFE) * I²S 3 -> CS4361 (surround) * I²S 4 -> CS4361 (front) * Capture: * I²S ADC 1 <- CS4245 * * GPIO 3 <- ? * GPIO 4 <- headphone detect * GPIO 5 -> enable ADC analog circuit for the left channel * GPIO 6 -> enable ADC analog circuit for the right channel * GPIO 7 -> switch green rear output jack between CS4245 and the first * channel of CS4361 (mechanical relay) * GPIO 8 -> enable output to speakers * * CS4245: * * input 0 <- mic * input 1 <- aux * input 2 <- front mic * input 4 <- line * DAC out -> headphones * aux out -> front panel headphones */ #include <linux/pci.h> #include <linux/delay.h> #include <sound/control.h> #include <sound/core.h> #include <sound/info.h> #include <sound/pcm.h> #include <sound/tlv.h> #include "oxygen.h" #include "xonar_dg.h" #include "cs4245.h" int cs4245_write_spi(struct oxygen *chip, u8 reg) { struct dg *data = chip->model_data; unsigned int packet; packet = reg << 8; packet |= (CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 16; packet |= data->cs4245_shadow[reg]; return oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_3 | OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, packet); } int cs4245_read_spi(struct oxygen *chip, u8 addr) { struct dg *data = chip->model_data; int ret; ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CEN_LATCH_CLOCK_HI | OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT), ((CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 8) | addr); if (ret < 0) return ret; ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CEN_LATCH_CLOCK_HI | OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT), (CS4245_SPI_ADDRESS | CS4245_SPI_READ) << 8); if (ret < 0) return ret; data->cs4245_shadow[addr] = oxygen_read8(chip, OXYGEN_SPI_DATA1); return 0; } int cs4245_shadow_control(struct oxygen *chip, enum cs4245_shadow_operation op) { struct dg *data = chip->model_data; unsigned char addr; int ret; for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) { ret = (op == CS4245_SAVE_TO_SHADOW ? cs4245_read_spi(chip, addr) : cs4245_write_spi(chip, addr)); if (ret < 0) return ret; } return 0; } static void cs4245_init(struct oxygen *chip) { struct dg *data = chip->model_data; /* save the initial state: codec version, registers */ cs4245_shadow_control(chip, CS4245_SAVE_TO_SHADOW); /* * Power up the CODEC internals, enable soft ramp & zero cross, work in * async. mode, enable aux output from DAC. Invert DAC output as in the * Windows driver. */ data->cs4245_shadow[CS4245_POWER_CTRL] = 0; data->cs4245_shadow[CS4245_SIGNAL_SEL] = CS4245_A_OUT_SEL_DAC | CS4245_ASYNCH; data->cs4245_shadow[CS4245_DAC_CTRL_1] = CS4245_DAC_FM_SINGLE | CS4245_DAC_DIF_LJUST; data->cs4245_shadow[CS4245_DAC_CTRL_2] = CS4245_DAC_SOFT | CS4245_DAC_ZERO | CS4245_INVERT_DAC; data->cs4245_shadow[CS4245_ADC_CTRL] = CS4245_ADC_FM_SINGLE | CS4245_ADC_DIF_LJUST; data->cs4245_shadow[CS4245_ANALOG_IN] = CS4245_PGA_SOFT | CS4245_PGA_ZERO; data->cs4245_shadow[CS4245_PGA_B_CTRL] = 0; data->cs4245_shadow[CS4245_PGA_A_CTRL] = 0; data->cs4245_shadow[CS4245_DAC_A_CTRL] = 8; data->cs4245_shadow[CS4245_DAC_B_CTRL] = 8; cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW); snd_component_add(chip->card, "CS4245"); } void dg_init(struct oxygen *chip) { struct dg *data = chip->model_data; data->output_sel = PLAYBACK_DST_HP_FP; data->input_sel = CAPTURE_SRC_MIC; cs4245_init(chip); oxygen_write16(chip, OXYGEN_GPIO_CONTROL, GPIO_OUTPUT_ENABLE | GPIO_HP_REAR | GPIO_INPUT_ROUTE); /* anti-pop delay, wait some time before enabling the output */ msleep(2500); oxygen_write16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE | GPIO_INPUT_ROUTE); } void dg_cleanup(struct oxygen *chip) { oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE); } void dg_suspend(struct oxygen *chip) { dg_cleanup(chip); } void dg_resume(struct oxygen *chip) { cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW); msleep(2500); oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE); } void set_cs4245_dac_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct dg *data = chip->model_data; unsigned char dac_ctrl; unsigned char mclk_freq; dac_ctrl = data->cs4245_shadow[CS4245_DAC_CTRL_1] & ~CS4245_DAC_FM_MASK; mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK1_MASK; if (params_rate(params) <= 50000) { dac_ctrl |= CS4245_DAC_FM_SINGLE; mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT; } else if (params_rate(params) <= 100000) { dac_ctrl |= CS4245_DAC_FM_DOUBLE; mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT; } else { dac_ctrl |= CS4245_DAC_FM_QUAD; mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK1_SHIFT; } data->cs4245_shadow[CS4245_DAC_CTRL_1] = dac_ctrl; data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq; cs4245_write_spi(chip, CS4245_DAC_CTRL_1); cs4245_write_spi(chip, CS4245_MCLK_FREQ); } void set_cs4245_adc_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct dg *data = chip->model_data; unsigned char adc_ctrl; unsigned char mclk_freq; adc_ctrl = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_ADC_FM_MASK; mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK2_MASK; if (params_rate(params) <= 50000) { adc_ctrl |= CS4245_ADC_FM_SINGLE; mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT; } else if (params_rate(params) <= 100000) { adc_ctrl |= CS4245_ADC_FM_DOUBLE; mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT; } else { adc_ctrl |= CS4245_ADC_FM_QUAD; mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK2_SHIFT; } data->cs4245_shadow[CS4245_ADC_CTRL] = adc_ctrl; data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq; cs4245_write_spi(chip, CS4245_ADC_CTRL); cs4245_write_spi(chip, CS4245_MCLK_FREQ); } static inline unsigned int shift_bits(unsigned int value, unsigned int shift_from, unsigned int shift_to, unsigned int mask) { if (shift_from < shift_to) return (value << (shift_to - shift_from)) & mask; else return (value >> (shift_from - shift_to)) & mask; } unsigned int adjust_dg_dac_routing(struct oxygen *chip, unsigned int play_routing) { struct dg *data = chip->model_data; switch (data->output_sel) { case PLAYBACK_DST_HP: case PLAYBACK_DST_HP_FP: oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK); break; case PLAYBACK_DST_MULTICH: oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK); break; } return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC2_SOURCE_SHIFT, OXYGEN_PLAY_DAC1_SOURCE_SHIFT, OXYGEN_PLAY_DAC1_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC1_SOURCE_SHIFT, OXYGEN_PLAY_DAC2_SOURCE_SHIFT, OXYGEN_PLAY_DAC2_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC0_SOURCE_SHIFT, OXYGEN_PLAY_DAC3_SOURCE_SHIFT, OXYGEN_PLAY_DAC3_SOURCE_MASK); } void dump_cs4245_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct dg *data = chip->model_data; unsigned int addr; snd_iprintf(buffer, "\nCS4245:"); cs4245_read_spi(chip, CS4245_INT_STATUS); for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) snd_iprintf(buffer, " %02x", data->cs4245_shadow[addr]); snd_iprintf(buffer, "\n"); }
linux-master
sound/pci/oxygen/xonar_dg.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver - mixer code * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/mutex.h> #include <sound/ac97_codec.h> #include <sound/asoundef.h> #include <sound/control.h> #include <sound/tlv.h> #include "oxygen.h" #include "cm9780.h" static int dac_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { struct oxygen *chip = ctl->private_data; info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = chip->model.dac_channels_mixer; info->value.integer.min = chip->model.dac_volume_min; info->value.integer.max = chip->model.dac_volume_max; return 0; } static int dac_volume_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int i; mutex_lock(&chip->mutex); for (i = 0; i < chip->model.dac_channels_mixer; ++i) value->value.integer.value[i] = chip->dac_volume[i]; mutex_unlock(&chip->mutex); return 0; } static int dac_volume_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int i; int changed; changed = 0; mutex_lock(&chip->mutex); for (i = 0; i < chip->model.dac_channels_mixer; ++i) if (value->value.integer.value[i] != chip->dac_volume[i]) { chip->dac_volume[i] = value->value.integer.value[i]; changed = 1; } if (changed) chip->model.update_dac_volume(chip); mutex_unlock(&chip->mutex); return changed; } static int dac_mute_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); value->value.integer.value[0] = !chip->dac_mute; mutex_unlock(&chip->mutex); return 0; } static int dac_mute_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; int changed; mutex_lock(&chip->mutex); changed = (!value->value.integer.value[0]) != chip->dac_mute; if (changed) { chip->dac_mute = !value->value.integer.value[0]; chip->model.update_dac_mute(chip); } mutex_unlock(&chip->mutex); return changed; } static unsigned int upmix_item_count(struct oxygen *chip) { if (chip->model.dac_channels_pcm < 8) return 2; else if (chip->model.update_center_lfe_mix) return 5; else return 3; } static int upmix_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[5] = { "Front", "Front+Surround", "Front+Surround+Back", "Front+Surround+Center/LFE", "Front+Surround+Center/LFE+Back", }; struct oxygen *chip = ctl->private_data; unsigned int count = upmix_item_count(chip); return snd_ctl_enum_info(info, 1, count, names); } static int upmix_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); value->value.enumerated.item[0] = chip->dac_routing; mutex_unlock(&chip->mutex); return 0; } void oxygen_update_dac_routing(struct oxygen *chip) { /* DAC 0: front, DAC 1: surround, DAC 2: center/LFE, DAC 3: back */ static const unsigned int reg_values[5] = { /* stereo -> front */ (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT), /* stereo -> front+surround */ (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT), /* stereo -> front+surround+back */ (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT), /* stereo -> front+surround+center/LFE */ (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT), /* stereo -> front+surround+center/LFE+back */ (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (0 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT), }; u8 channels; unsigned int reg_value; channels = oxygen_read8(chip, OXYGEN_PLAY_CHANNELS) & OXYGEN_PLAY_CHANNELS_MASK; if (channels == OXYGEN_PLAY_CHANNELS_2) reg_value = reg_values[chip->dac_routing]; else if (channels == OXYGEN_PLAY_CHANNELS_8) /* in 7.1 mode, "rear" channels go to the "back" jack */ reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT); else reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT); if (chip->model.adjust_dac_routing) reg_value = chip->model.adjust_dac_routing(chip, reg_value); oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING, reg_value, OXYGEN_PLAY_DAC0_SOURCE_MASK | OXYGEN_PLAY_DAC1_SOURCE_MASK | OXYGEN_PLAY_DAC2_SOURCE_MASK | OXYGEN_PLAY_DAC3_SOURCE_MASK); if (chip->model.update_center_lfe_mix) chip->model.update_center_lfe_mix(chip, chip->dac_routing > 2); } EXPORT_SYMBOL(oxygen_update_dac_routing); static int upmix_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int count = upmix_item_count(chip); int changed; if (value->value.enumerated.item[0] >= count) return -EINVAL; mutex_lock(&chip->mutex); changed = value->value.enumerated.item[0] != chip->dac_routing; if (changed) { chip->dac_routing = value->value.enumerated.item[0]; oxygen_update_dac_routing(chip); } mutex_unlock(&chip->mutex); return changed; } static int spdif_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); value->value.integer.value[0] = chip->spdif_playback_enable; mutex_unlock(&chip->mutex); return 0; } static unsigned int oxygen_spdif_rate(unsigned int oxygen_rate) { switch (oxygen_rate) { case OXYGEN_RATE_32000: return IEC958_AES3_CON_FS_32000 << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_44100: return IEC958_AES3_CON_FS_44100 << OXYGEN_SPDIF_CS_RATE_SHIFT; default: /* OXYGEN_RATE_48000 */ return IEC958_AES3_CON_FS_48000 << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_64000: return 0xb << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_88200: return IEC958_AES3_CON_FS_88200 << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_96000: return IEC958_AES3_CON_FS_96000 << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_176400: return IEC958_AES3_CON_FS_176400 << OXYGEN_SPDIF_CS_RATE_SHIFT; case OXYGEN_RATE_192000: return IEC958_AES3_CON_FS_192000 << OXYGEN_SPDIF_CS_RATE_SHIFT; } } void oxygen_update_spdif_source(struct oxygen *chip) { u32 old_control, new_control; u16 old_routing, new_routing; unsigned int oxygen_rate; old_control = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); old_routing = oxygen_read16(chip, OXYGEN_PLAY_ROUTING); if (chip->pcm_active & (1 << PCM_SPDIF)) { new_control = old_control | OXYGEN_SPDIF_OUT_ENABLE; new_routing = (old_routing & ~OXYGEN_PLAY_SPDIF_MASK) | OXYGEN_PLAY_SPDIF_SPDIF; oxygen_rate = (old_control >> OXYGEN_SPDIF_OUT_RATE_SHIFT) & OXYGEN_I2S_RATE_MASK; /* S/PDIF rate was already set by the caller */ } else if ((chip->pcm_active & (1 << PCM_MULTICH)) && chip->spdif_playback_enable) { new_routing = (old_routing & ~OXYGEN_PLAY_SPDIF_MASK) | OXYGEN_PLAY_SPDIF_MULTICH_01; oxygen_rate = oxygen_read16(chip, OXYGEN_I2S_MULTICH_FORMAT) & OXYGEN_I2S_RATE_MASK; new_control = (old_control & ~OXYGEN_SPDIF_OUT_RATE_MASK) | (oxygen_rate << OXYGEN_SPDIF_OUT_RATE_SHIFT) | OXYGEN_SPDIF_OUT_ENABLE; } else { new_control = old_control & ~OXYGEN_SPDIF_OUT_ENABLE; new_routing = old_routing; oxygen_rate = OXYGEN_RATE_44100; } if (old_routing != new_routing) { oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, new_control & ~OXYGEN_SPDIF_OUT_ENABLE); oxygen_write16(chip, OXYGEN_PLAY_ROUTING, new_routing); } if (new_control & OXYGEN_SPDIF_OUT_ENABLE) oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, oxygen_spdif_rate(oxygen_rate) | ((chip->pcm_active & (1 << PCM_SPDIF)) ? chip->spdif_pcm_bits : chip->spdif_bits)); oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, new_control); } static int spdif_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; int changed; mutex_lock(&chip->mutex); changed = value->value.integer.value[0] != chip->spdif_playback_enable; if (changed) { chip->spdif_playback_enable = !!value->value.integer.value[0]; spin_lock_irq(&chip->reg_lock); oxygen_update_spdif_source(chip); spin_unlock_irq(&chip->reg_lock); } mutex_unlock(&chip->mutex); return changed; } static int spdif_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_IEC958; info->count = 1; return 0; } static void oxygen_to_iec958(u32 bits, struct snd_ctl_elem_value *value) { value->value.iec958.status[0] = bits & (OXYGEN_SPDIF_NONAUDIO | OXYGEN_SPDIF_C | OXYGEN_SPDIF_PREEMPHASIS); value->value.iec958.status[1] = /* category and original */ bits >> OXYGEN_SPDIF_CATEGORY_SHIFT; } static u32 iec958_to_oxygen(struct snd_ctl_elem_value *value) { u32 bits; bits = value->value.iec958.status[0] & (OXYGEN_SPDIF_NONAUDIO | OXYGEN_SPDIF_C | OXYGEN_SPDIF_PREEMPHASIS); bits |= value->value.iec958.status[1] << OXYGEN_SPDIF_CATEGORY_SHIFT; if (bits & OXYGEN_SPDIF_NONAUDIO) bits |= OXYGEN_SPDIF_V; return bits; } static inline void write_spdif_bits(struct oxygen *chip, u32 bits) { oxygen_write32_masked(chip, OXYGEN_SPDIF_OUTPUT_BITS, bits, OXYGEN_SPDIF_NONAUDIO | OXYGEN_SPDIF_C | OXYGEN_SPDIF_PREEMPHASIS | OXYGEN_SPDIF_CATEGORY_MASK | OXYGEN_SPDIF_ORIGINAL | OXYGEN_SPDIF_V); } static int spdif_default_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); oxygen_to_iec958(chip->spdif_bits, value); mutex_unlock(&chip->mutex); return 0; } static int spdif_default_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u32 new_bits; int changed; new_bits = iec958_to_oxygen(value); mutex_lock(&chip->mutex); changed = new_bits != chip->spdif_bits; if (changed) { chip->spdif_bits = new_bits; if (!(chip->pcm_active & (1 << PCM_SPDIF))) write_spdif_bits(chip, new_bits); } mutex_unlock(&chip->mutex); return changed; } static int spdif_mask_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { value->value.iec958.status[0] = IEC958_AES0_NONAUDIO | IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS; value->value.iec958.status[1] = IEC958_AES1_CON_CATEGORY | IEC958_AES1_CON_ORIGINAL; return 0; } static int spdif_pcm_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); oxygen_to_iec958(chip->spdif_pcm_bits, value); mutex_unlock(&chip->mutex); return 0; } static int spdif_pcm_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u32 new_bits; int changed; new_bits = iec958_to_oxygen(value); mutex_lock(&chip->mutex); changed = new_bits != chip->spdif_pcm_bits; if (changed) { chip->spdif_pcm_bits = new_bits; if (chip->pcm_active & (1 << PCM_SPDIF)) write_spdif_bits(chip, new_bits); } mutex_unlock(&chip->mutex); return changed; } static int spdif_input_mask_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { value->value.iec958.status[0] = 0xff; value->value.iec958.status[1] = 0xff; value->value.iec958.status[2] = 0xff; value->value.iec958.status[3] = 0xff; return 0; } static int spdif_input_default_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u32 bits; bits = oxygen_read32(chip, OXYGEN_SPDIF_INPUT_BITS); value->value.iec958.status[0] = bits; value->value.iec958.status[1] = bits >> 8; value->value.iec958.status[2] = bits >> 16; value->value.iec958.status[3] = bits >> 24; return 0; } static int spdif_bit_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u32 bit = ctl->private_value; value->value.integer.value[0] = !!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL) & bit); return 0; } static int spdif_bit_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u32 bit = ctl->private_value; u32 oldreg, newreg; int changed; spin_lock_irq(&chip->reg_lock); oldreg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); if (value->value.integer.value[0]) newreg = oldreg | bit; else newreg = oldreg & ~bit; changed = newreg != oldreg; if (changed) oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, newreg); spin_unlock_irq(&chip->reg_lock); return changed; } static int monitor_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 1; info->value.integer.min = 0; info->value.integer.max = 1; return 0; } static int monitor_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u8 bit = ctl->private_value; int invert = ctl->private_value & (1 << 8); value->value.integer.value[0] = !!invert ^ !!(oxygen_read8(chip, OXYGEN_ADC_MONITOR) & bit); return 0; } static int monitor_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u8 bit = ctl->private_value; int invert = ctl->private_value & (1 << 8); u8 oldreg, newreg; int changed; spin_lock_irq(&chip->reg_lock); oldreg = oxygen_read8(chip, OXYGEN_ADC_MONITOR); if ((!!value->value.integer.value[0] ^ !!invert) != 0) newreg = oldreg | bit; else newreg = oldreg & ~bit; changed = newreg != oldreg; if (changed) oxygen_write8(chip, OXYGEN_ADC_MONITOR, newreg); spin_unlock_irq(&chip->reg_lock); return changed; } static int ac97_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int codec = (ctl->private_value >> 24) & 1; unsigned int index = ctl->private_value & 0xff; unsigned int bitnr = (ctl->private_value >> 8) & 0xff; int invert = ctl->private_value & (1 << 16); u16 reg; mutex_lock(&chip->mutex); reg = oxygen_read_ac97(chip, codec, index); mutex_unlock(&chip->mutex); if (!(reg & (1 << bitnr)) ^ !invert) value->value.integer.value[0] = 1; else value->value.integer.value[0] = 0; return 0; } static void mute_ac97_ctl(struct oxygen *chip, unsigned int control) { unsigned int priv_idx; u16 value; if (!chip->controls[control]) return; priv_idx = chip->controls[control]->private_value & 0xff; value = oxygen_read_ac97(chip, 0, priv_idx); if (!(value & 0x8000)) { oxygen_write_ac97(chip, 0, priv_idx, value | 0x8000); if (chip->model.ac97_switch) chip->model.ac97_switch(chip, priv_idx, 0x8000); snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->controls[control]->id); } } static int ac97_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int codec = (ctl->private_value >> 24) & 1; unsigned int index = ctl->private_value & 0xff; unsigned int bitnr = (ctl->private_value >> 8) & 0xff; int invert = ctl->private_value & (1 << 16); u16 oldreg, newreg; int change; mutex_lock(&chip->mutex); oldreg = oxygen_read_ac97(chip, codec, index); newreg = oldreg; if (!value->value.integer.value[0] ^ !invert) newreg |= 1 << bitnr; else newreg &= ~(1 << bitnr); change = newreg != oldreg; if (change) { oxygen_write_ac97(chip, codec, index, newreg); if (codec == 0 && chip->model.ac97_switch) chip->model.ac97_switch(chip, index, newreg & 0x8000); if (index == AC97_LINE) { oxygen_write_ac97_masked(chip, 0, CM9780_GPIO_STATUS, newreg & 0x8000 ? CM9780_GPO0 : 0, CM9780_GPO0); if (!(newreg & 0x8000)) { mute_ac97_ctl(chip, CONTROL_MIC_CAPTURE_SWITCH); mute_ac97_ctl(chip, CONTROL_CD_CAPTURE_SWITCH); mute_ac97_ctl(chip, CONTROL_AUX_CAPTURE_SWITCH); } } else if ((index == AC97_MIC || index == AC97_CD || index == AC97_VIDEO || index == AC97_AUX) && bitnr == 15 && !(newreg & 0x8000)) { mute_ac97_ctl(chip, CONTROL_LINE_CAPTURE_SWITCH); oxygen_write_ac97_masked(chip, 0, CM9780_GPIO_STATUS, CM9780_GPO0, CM9780_GPO0); } } mutex_unlock(&chip->mutex); return change; } static int ac97_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { int stereo = (ctl->private_value >> 16) & 1; info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = stereo ? 2 : 1; info->value.integer.min = 0; info->value.integer.max = 0x1f; return 0; } static int ac97_volume_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int codec = (ctl->private_value >> 24) & 1; int stereo = (ctl->private_value >> 16) & 1; unsigned int index = ctl->private_value & 0xff; u16 reg; mutex_lock(&chip->mutex); reg = oxygen_read_ac97(chip, codec, index); mutex_unlock(&chip->mutex); if (!stereo) { value->value.integer.value[0] = 31 - (reg & 0x1f); } else { value->value.integer.value[0] = 31 - ((reg >> 8) & 0x1f); value->value.integer.value[1] = 31 - (reg & 0x1f); } return 0; } static int ac97_volume_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; unsigned int codec = (ctl->private_value >> 24) & 1; int stereo = (ctl->private_value >> 16) & 1; unsigned int index = ctl->private_value & 0xff; u16 oldreg, newreg; int change; mutex_lock(&chip->mutex); oldreg = oxygen_read_ac97(chip, codec, index); if (!stereo) { newreg = oldreg & ~0x1f; newreg |= 31 - (value->value.integer.value[0] & 0x1f); } else { newreg = oldreg & ~0x1f1f; newreg |= (31 - (value->value.integer.value[0] & 0x1f)) << 8; newreg |= 31 - (value->value.integer.value[1] & 0x1f); } change = newreg != oldreg; if (change) oxygen_write_ac97(chip, codec, index, newreg); mutex_unlock(&chip->mutex); return change; } static int mic_fmic_source_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[] = { "Mic Jack", "Front Panel" }; return snd_ctl_enum_info(info, 1, 2, names); } static int mic_fmic_source_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; mutex_lock(&chip->mutex); value->value.enumerated.item[0] = !!(oxygen_read_ac97(chip, 0, CM9780_JACK) & CM9780_FMIC2MIC); mutex_unlock(&chip->mutex); return 0; } static int mic_fmic_source_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 oldreg, newreg; int change; mutex_lock(&chip->mutex); oldreg = oxygen_read_ac97(chip, 0, CM9780_JACK); if (value->value.enumerated.item[0]) newreg = oldreg | CM9780_FMIC2MIC; else newreg = oldreg & ~CM9780_FMIC2MIC; change = newreg != oldreg; if (change) oxygen_write_ac97(chip, 0, CM9780_JACK, newreg); mutex_unlock(&chip->mutex); return change; } static int ac97_fp_rec_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 2; info->value.integer.min = 0; info->value.integer.max = 7; return 0; } static int ac97_fp_rec_volume_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 reg; mutex_lock(&chip->mutex); reg = oxygen_read_ac97(chip, 1, AC97_REC_GAIN); mutex_unlock(&chip->mutex); value->value.integer.value[0] = reg & 7; value->value.integer.value[1] = (reg >> 8) & 7; return 0; } static int ac97_fp_rec_volume_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; u16 oldreg, newreg; int change; mutex_lock(&chip->mutex); oldreg = oxygen_read_ac97(chip, 1, AC97_REC_GAIN); newreg = oldreg & ~0x0707; newreg = newreg | (value->value.integer.value[0] & 7); newreg = newreg | ((value->value.integer.value[0] & 7) << 8); change = newreg != oldreg; if (change) oxygen_write_ac97(chip, 1, AC97_REC_GAIN, newreg); mutex_unlock(&chip->mutex); return change; } #define AC97_SWITCH(xname, codec, index, bitnr, invert) { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .info = snd_ctl_boolean_mono_info, \ .get = ac97_switch_get, \ .put = ac97_switch_put, \ .private_value = ((codec) << 24) | ((invert) << 16) | \ ((bitnr) << 8) | (index), \ } #define AC97_VOLUME(xname, codec, index, stereo) { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ .info = ac97_volume_info, \ .get = ac97_volume_get, \ .put = ac97_volume_put, \ .tlv = { .p = ac97_db_scale, }, \ .private_value = ((codec) << 24) | ((stereo) << 16) | (index), \ } static DECLARE_TLV_DB_SCALE(monitor_db_scale, -600, 600, 0); static DECLARE_TLV_DB_SCALE(ac97_db_scale, -3450, 150, 0); static DECLARE_TLV_DB_SCALE(ac97_rec_db_scale, 0, 150, 0); static const struct snd_kcontrol_new controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Master Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .info = dac_volume_info, .get = dac_volume_get, .put = dac_volume_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Master Playback Switch", .info = snd_ctl_boolean_mono_info, .get = dac_mute_get, .put = dac_mute_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Stereo Upmixing", .info = upmix_info, .get = upmix_get, .put = upmix_put, }, }; static const struct snd_kcontrol_new spdif_output_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), .info = snd_ctl_boolean_mono_info, .get = spdif_switch_get, .put = spdif_switch_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 1, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), .info = spdif_info, .get = spdif_default_get, .put = spdif_default_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 1, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), .access = SNDRV_CTL_ELEM_ACCESS_READ, .info = spdif_info, .get = spdif_mask_get, }, { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 1, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .info = spdif_info, .get = spdif_pcm_get, .put = spdif_pcm_put, }, }; static const struct snd_kcontrol_new spdif_input_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 1, .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), .access = SNDRV_CTL_ELEM_ACCESS_READ, .info = spdif_info, .get = spdif_input_mask_get, }, { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .device = 1, .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), .access = SNDRV_CTL_ELEM_ACCESS_READ, .info = spdif_info, .get = spdif_input_default_get, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("Loopback ", NONE, SWITCH), .info = snd_ctl_boolean_mono_info, .get = spdif_bit_switch_get, .put = spdif_bit_switch_put, .private_value = OXYGEN_SPDIF_LOOPBACK, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("Validity Check ",CAPTURE,SWITCH), .info = snd_ctl_boolean_mono_info, .get = spdif_bit_switch_get, .put = spdif_bit_switch_put, .private_value = OXYGEN_SPDIF_SPDVALID, }, }; static const struct { unsigned int pcm_dev; struct snd_kcontrol_new controls[2]; } monitor_controls[] = { { .pcm_dev = CAPTURE_0_FROM_I2S_1, .controls = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Switch", .info = snd_ctl_boolean_mono_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_A, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = monitor_volume_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_A_HALF_VOL | (1 << 8), .tlv = { .p = monitor_db_scale, }, }, }, }, { .pcm_dev = CAPTURE_0_FROM_I2S_2, .controls = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Switch", .info = snd_ctl_boolean_mono_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_B, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = monitor_volume_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_B_HALF_VOL | (1 << 8), .tlv = { .p = monitor_db_scale, }, }, }, }, { .pcm_dev = CAPTURE_2_FROM_I2S_2, .controls = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Switch", .index = 1, .info = snd_ctl_boolean_mono_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_B, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Volume", .index = 1, .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = monitor_volume_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_B_HALF_VOL | (1 << 8), .tlv = { .p = monitor_db_scale, }, }, }, }, { .pcm_dev = CAPTURE_3_FROM_I2S_3, .controls = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Switch", .index = 2, .info = snd_ctl_boolean_mono_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_C, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Analog Input Monitor Playback Volume", .index = 2, .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = monitor_volume_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_C_HALF_VOL | (1 << 8), .tlv = { .p = monitor_db_scale, }, }, }, }, { .pcm_dev = CAPTURE_1_FROM_SPDIF, .controls = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Digital Input Monitor Playback Switch", .info = snd_ctl_boolean_mono_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_C, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Digital Input Monitor Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = monitor_volume_info, .get = monitor_get, .put = monitor_put, .private_value = OXYGEN_ADC_MONITOR_C_HALF_VOL | (1 << 8), .tlv = { .p = monitor_db_scale, }, }, }, }, }; static const struct snd_kcontrol_new ac97_controls[] = { AC97_VOLUME("Mic Capture Volume", 0, AC97_MIC, 0), AC97_SWITCH("Mic Capture Switch", 0, AC97_MIC, 15, 1), AC97_SWITCH("Mic Boost (+20dB)", 0, AC97_MIC, 6, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Mic Source Capture Enum", .info = mic_fmic_source_info, .get = mic_fmic_source_get, .put = mic_fmic_source_put, }, AC97_SWITCH("Line Capture Switch", 0, AC97_LINE, 15, 1), AC97_VOLUME("CD Capture Volume", 0, AC97_CD, 1), AC97_SWITCH("CD Capture Switch", 0, AC97_CD, 15, 1), AC97_VOLUME("Aux Capture Volume", 0, AC97_AUX, 1), AC97_SWITCH("Aux Capture Switch", 0, AC97_AUX, 15, 1), }; static const struct snd_kcontrol_new ac97_fp_controls[] = { AC97_VOLUME("Front Panel Playback Volume", 1, AC97_HEADPHONE, 1), AC97_SWITCH("Front Panel Playback Switch", 1, AC97_HEADPHONE, 15, 1), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Front Panel Capture Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .info = ac97_fp_rec_volume_info, .get = ac97_fp_rec_volume_get, .put = ac97_fp_rec_volume_put, .tlv = { .p = ac97_rec_db_scale, }, }, AC97_SWITCH("Front Panel Capture Switch", 1, AC97_REC_GAIN, 15, 1), }; static void oxygen_any_ctl_free(struct snd_kcontrol *ctl) { struct oxygen *chip = ctl->private_data; unsigned int i; /* I'm too lazy to write a function for each control :-) */ for (i = 0; i < ARRAY_SIZE(chip->controls); ++i) chip->controls[i] = NULL; } static int add_controls(struct oxygen *chip, const struct snd_kcontrol_new controls[], unsigned int count) { static const char *const known_ctl_names[CONTROL_COUNT] = { [CONTROL_SPDIF_PCM] = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), [CONTROL_SPDIF_INPUT_BITS] = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), [CONTROL_MIC_CAPTURE_SWITCH] = "Mic Capture Switch", [CONTROL_LINE_CAPTURE_SWITCH] = "Line Capture Switch", [CONTROL_CD_CAPTURE_SWITCH] = "CD Capture Switch", [CONTROL_AUX_CAPTURE_SWITCH] = "Aux Capture Switch", }; unsigned int i; struct snd_kcontrol_new template; struct snd_kcontrol *ctl; int j, err; for (i = 0; i < count; ++i) { template = controls[i]; if (chip->model.control_filter) { err = chip->model.control_filter(&template); if (err < 0) return err; if (err == 1) continue; } if (!strcmp(template.name, "Stereo Upmixing") && chip->model.dac_channels_pcm == 2) continue; if (!strcmp(template.name, "Mic Source Capture Enum") && !(chip->model.device_config & AC97_FMIC_SWITCH)) continue; if (!strncmp(template.name, "CD Capture ", 11) && !(chip->model.device_config & AC97_CD_INPUT)) continue; if (!strcmp(template.name, "Master Playback Volume") && chip->model.dac_tlv) { template.tlv.p = chip->model.dac_tlv; template.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ; } ctl = snd_ctl_new1(&template, chip); if (!ctl) return -ENOMEM; err = snd_ctl_add(chip->card, ctl); if (err < 0) return err; j = match_string(known_ctl_names, CONTROL_COUNT, ctl->id.name); if (j >= 0) { chip->controls[j] = ctl; ctl->private_free = oxygen_any_ctl_free; } } return 0; } int oxygen_mixer_init(struct oxygen *chip) { unsigned int i; int err; err = add_controls(chip, controls, ARRAY_SIZE(controls)); if (err < 0) return err; if (chip->model.device_config & PLAYBACK_1_TO_SPDIF) { err = add_controls(chip, spdif_output_controls, ARRAY_SIZE(spdif_output_controls)); if (err < 0) return err; } if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) { err = add_controls(chip, spdif_input_controls, ARRAY_SIZE(spdif_input_controls)); if (err < 0) return err; } for (i = 0; i < ARRAY_SIZE(monitor_controls); ++i) { if (!(chip->model.device_config & monitor_controls[i].pcm_dev)) continue; err = add_controls(chip, monitor_controls[i].controls, ARRAY_SIZE(monitor_controls[i].controls)); if (err < 0) return err; } if (chip->has_ac97_0) { err = add_controls(chip, ac97_controls, ARRAY_SIZE(ac97_controls)); if (err < 0) return err; } if (chip->has_ac97_1) { err = add_controls(chip, ac97_fp_controls, ARRAY_SIZE(ac97_fp_controls)); if (err < 0) return err; } return chip->model.mixer_init ? chip->model.mixer_init(chip) : 0; }
linux-master
sound/pci/oxygen/oxygen_mixer.c
// SPDX-License-Identifier: GPL-2.0-only /* * C-Media CMI8788 driver - helper functions * * Copyright (c) Clemens Ladisch <[email protected]> */ #include <linux/delay.h> #include <linux/sched.h> #include <linux/export.h> #include <linux/io.h> #include <sound/core.h> #include <sound/mpu401.h> #include "oxygen.h" u8 oxygen_read8(struct oxygen *chip, unsigned int reg) { return inb(chip->addr + reg); } EXPORT_SYMBOL(oxygen_read8); u16 oxygen_read16(struct oxygen *chip, unsigned int reg) { return inw(chip->addr + reg); } EXPORT_SYMBOL(oxygen_read16); u32 oxygen_read32(struct oxygen *chip, unsigned int reg) { return inl(chip->addr + reg); } EXPORT_SYMBOL(oxygen_read32); void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value) { outb(value, chip->addr + reg); chip->saved_registers._8[reg] = value; } EXPORT_SYMBOL(oxygen_write8); void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value) { outw(value, chip->addr + reg); chip->saved_registers._16[reg / 2] = cpu_to_le16(value); } EXPORT_SYMBOL(oxygen_write16); void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value) { outl(value, chip->addr + reg); chip->saved_registers._32[reg / 4] = cpu_to_le32(value); } EXPORT_SYMBOL(oxygen_write32); void oxygen_write8_masked(struct oxygen *chip, unsigned int reg, u8 value, u8 mask) { u8 tmp = inb(chip->addr + reg); tmp &= ~mask; tmp |= value & mask; outb(tmp, chip->addr + reg); chip->saved_registers._8[reg] = tmp; } EXPORT_SYMBOL(oxygen_write8_masked); void oxygen_write16_masked(struct oxygen *chip, unsigned int reg, u16 value, u16 mask) { u16 tmp = inw(chip->addr + reg); tmp &= ~mask; tmp |= value & mask; outw(tmp, chip->addr + reg); chip->saved_registers._16[reg / 2] = cpu_to_le16(tmp); } EXPORT_SYMBOL(oxygen_write16_masked); void oxygen_write32_masked(struct oxygen *chip, unsigned int reg, u32 value, u32 mask) { u32 tmp = inl(chip->addr + reg); tmp &= ~mask; tmp |= value & mask; outl(tmp, chip->addr + reg); chip->saved_registers._32[reg / 4] = cpu_to_le32(tmp); } EXPORT_SYMBOL(oxygen_write32_masked); static int oxygen_ac97_wait(struct oxygen *chip, unsigned int mask) { u8 status = 0; /* * Reading the status register also clears the bits, so we have to save * the read bits in status. */ wait_event_timeout(chip->ac97_waitqueue, ({ status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS); status & mask; }), msecs_to_jiffies(1) + 1); /* * Check even after a timeout because this function should not require * the AC'97 interrupt to be enabled. */ status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS); return status & mask ? 0 : -EIO; } /* * About 10% of AC'97 register reads or writes fail to complete, but even those * where the controller indicates completion aren't guaranteed to have actually * happened. * * It's hard to assign blame to either the controller or the codec because both * were made by C-Media ... */ void oxygen_write_ac97(struct oxygen *chip, unsigned int codec, unsigned int index, u16 data) { unsigned int count, succeeded; u32 reg; reg = data; reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT; reg |= OXYGEN_AC97_REG_DIR_WRITE; reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; succeeded = 0; for (count = 5; count > 0; --count) { udelay(5); oxygen_write32(chip, OXYGEN_AC97_REGS, reg); /* require two "completed" writes, just to be sure */ if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_WRITE_DONE) >= 0 && ++succeeded >= 2) { chip->saved_ac97_registers[codec][index / 2] = data; return; } } dev_err(chip->card->dev, "AC'97 write timeout\n"); } EXPORT_SYMBOL(oxygen_write_ac97); u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec, unsigned int index) { unsigned int count; unsigned int last_read = UINT_MAX; u32 reg; reg = index << OXYGEN_AC97_REG_ADDR_SHIFT; reg |= OXYGEN_AC97_REG_DIR_READ; reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; for (count = 5; count > 0; --count) { udelay(5); oxygen_write32(chip, OXYGEN_AC97_REGS, reg); udelay(10); if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_READ_DONE) >= 0) { u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS); /* we require two consecutive reads of the same value */ if (value == last_read) return value; last_read = value; /* * Invert the register value bits to make sure that two * consecutive unsuccessful reads do not return the same * value. */ reg ^= 0xffff; } } dev_err(chip->card->dev, "AC'97 read timeout on codec %u\n", codec); return 0; } EXPORT_SYMBOL(oxygen_read_ac97); void oxygen_write_ac97_masked(struct oxygen *chip, unsigned int codec, unsigned int index, u16 data, u16 mask) { u16 value = oxygen_read_ac97(chip, codec, index); value &= ~mask; value |= data & mask; oxygen_write_ac97(chip, codec, index, value); } EXPORT_SYMBOL(oxygen_write_ac97_masked); static int oxygen_wait_spi(struct oxygen *chip) { unsigned int count; /* * Higher timeout to be sure: 200 us; * actual transaction should not need more than 40 us. */ for (count = 50; count > 0; count--) { udelay(4); if ((oxygen_read8(chip, OXYGEN_SPI_CONTROL) & OXYGEN_SPI_BUSY) == 0) return 0; } dev_err(chip->card->dev, "oxygen: SPI wait timeout\n"); return -EIO; } int oxygen_write_spi(struct oxygen *chip, u8 control, unsigned int data) { /* * We need to wait AFTER initiating the SPI transaction, * otherwise read operations will not work. */ oxygen_write8(chip, OXYGEN_SPI_DATA1, data); oxygen_write8(chip, OXYGEN_SPI_DATA2, data >> 8); if (control & OXYGEN_SPI_DATA_LENGTH_3) oxygen_write8(chip, OXYGEN_SPI_DATA3, data >> 16); oxygen_write8(chip, OXYGEN_SPI_CONTROL, control); return oxygen_wait_spi(chip); } EXPORT_SYMBOL(oxygen_write_spi); void oxygen_write_i2c(struct oxygen *chip, u8 device, u8 map, u8 data) { /* should not need more than about 300 us */ msleep(1); oxygen_write8(chip, OXYGEN_2WIRE_MAP, map); oxygen_write8(chip, OXYGEN_2WIRE_DATA, data); oxygen_write8(chip, OXYGEN_2WIRE_CONTROL, device | OXYGEN_2WIRE_DIR_WRITE); } EXPORT_SYMBOL(oxygen_write_i2c); static void _write_uart(struct oxygen *chip, unsigned int port, u8 data) { if (oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_TX_FULL) msleep(1); oxygen_write8(chip, OXYGEN_MPU401 + port, data); } void oxygen_reset_uart(struct oxygen *chip) { _write_uart(chip, 1, MPU401_RESET); msleep(1); /* wait for ACK */ _write_uart(chip, 1, MPU401_ENTER_UART); } EXPORT_SYMBOL(oxygen_reset_uart); void oxygen_write_uart(struct oxygen *chip, u8 data) { _write_uart(chip, 0, data); } EXPORT_SYMBOL(oxygen_write_uart); u16 oxygen_read_eeprom(struct oxygen *chip, unsigned int index) { unsigned int timeout; oxygen_write8(chip, OXYGEN_EEPROM_CONTROL, index | OXYGEN_EEPROM_DIR_READ); for (timeout = 0; timeout < 100; ++timeout) { udelay(1); if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS) & OXYGEN_EEPROM_BUSY)) break; } return oxygen_read16(chip, OXYGEN_EEPROM_DATA); } void oxygen_write_eeprom(struct oxygen *chip, unsigned int index, u16 value) { unsigned int timeout; oxygen_write16(chip, OXYGEN_EEPROM_DATA, value); oxygen_write8(chip, OXYGEN_EEPROM_CONTROL, index | OXYGEN_EEPROM_DIR_WRITE); for (timeout = 0; timeout < 10; ++timeout) { msleep(1); if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS) & OXYGEN_EEPROM_BUSY)) return; } dev_err(chip->card->dev, "EEPROM write timeout\n"); }
linux-master
sound/pci/oxygen/oxygen_io.c
// SPDX-License-Identifier: GPL-2.0-only /* * card driver for models with WM8776/WM8766 DACs (Xonar DS/HDAV1.3 Slim) * * Copyright (c) Clemens Ladisch <[email protected]> */ /* * Xonar DS * -------- * * CMI8788: * * SPI 0 -> WM8766 (surround, center/LFE, back) * SPI 1 -> WM8776 (front, input) * * GPIO 4 <- headphone detect, 0 = plugged * GPIO 6 -> route input jack to mic-in (0) or line-in (1) * GPIO 7 -> enable output to front L/R speaker channels * GPIO 8 -> enable output to other speaker channels and front panel headphone * * WM8776: * * input 1 <- line * input 2 <- mic * input 3 <- front mic * input 4 <- aux */ /* * Xonar HDAV1.3 Slim * ------------------ * * CMI8788: * * I²C <-> WM8776 (addr 0011010) * * GPIO 0 -> disable HDMI output * GPIO 1 -> enable HP output * GPIO 6 -> firmware EEPROM I²C clock * GPIO 7 <-> firmware EEPROM I²C data * * UART <-> HDMI controller * * WM8776: * * input 1 <- mic * input 2 <- aux */ #include <linux/pci.h> #include <linux/delay.h> #include <sound/control.h> #include <sound/core.h> #include <sound/info.h> #include <sound/jack.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #include "xonar.h" #include "wm8776.h" #include "wm8766.h" #define GPIO_DS_HP_DETECT 0x0010 #define GPIO_DS_INPUT_ROUTE 0x0040 #define GPIO_DS_OUTPUT_FRONTLR 0x0080 #define GPIO_DS_OUTPUT_ENABLE 0x0100 #define GPIO_SLIM_HDMI_DISABLE 0x0001 #define GPIO_SLIM_OUTPUT_ENABLE 0x0002 #define GPIO_SLIM_FIRMWARE_CLK 0x0040 #define GPIO_SLIM_FIRMWARE_DATA 0x0080 #define I2C_DEVICE_WM8776 0x34 /* 001101, 0, /W=0 */ #define LC_CONTROL_LIMITER 0x40000000 #define LC_CONTROL_ALC 0x20000000 struct xonar_wm87x6 { struct xonar_generic generic; u16 wm8776_regs[0x17]; u16 wm8766_regs[0x10]; struct snd_kcontrol *line_adcmux_control; struct snd_kcontrol *mic_adcmux_control; struct snd_kcontrol *lc_controls[13]; struct snd_jack *hp_jack; struct xonar_hdmi hdmi; }; static void wm8776_write_spi(struct oxygen *chip, unsigned int reg, unsigned int value) { oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CLOCK_160 | (1 << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, (reg << 9) | value); } static void wm8776_write_i2c(struct oxygen *chip, unsigned int reg, unsigned int value) { oxygen_write_i2c(chip, I2C_DEVICE_WM8776, (reg << 1) | (value >> 8), value); } static void wm8776_write(struct oxygen *chip, unsigned int reg, unsigned int value) { struct xonar_wm87x6 *data = chip->model_data; if ((chip->model.function_flags & OXYGEN_FUNCTION_2WIRE_SPI_MASK) == OXYGEN_FUNCTION_SPI) wm8776_write_spi(chip, reg, value); else wm8776_write_i2c(chip, reg, value); if (reg < ARRAY_SIZE(data->wm8776_regs)) { /* reg >= WM8776_HPLVOL is always true */ if (reg <= WM8776_DACMASTER) value &= ~WM8776_UPDATE; data->wm8776_regs[reg] = value; } } static void wm8776_write_cached(struct oxygen *chip, unsigned int reg, unsigned int value) { struct xonar_wm87x6 *data = chip->model_data; if (reg >= ARRAY_SIZE(data->wm8776_regs) || value != data->wm8776_regs[reg]) wm8776_write(chip, reg, value); } static void wm8766_write(struct oxygen *chip, unsigned int reg, unsigned int value) { struct xonar_wm87x6 *data = chip->model_data; oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_2 | OXYGEN_SPI_CLOCK_160 | (0 << OXYGEN_SPI_CODEC_SHIFT) | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, (reg << 9) | value); if (reg < ARRAY_SIZE(data->wm8766_regs)) { /* reg >= WM8766_LDA1 is always true */ if (reg <= WM8766_RDA1 || (reg >= WM8766_LDA2 && reg <= WM8766_MASTDA)) value &= ~WM8766_UPDATE; data->wm8766_regs[reg] = value; } } static void wm8766_write_cached(struct oxygen *chip, unsigned int reg, unsigned int value) { struct xonar_wm87x6 *data = chip->model_data; if (reg >= ARRAY_SIZE(data->wm8766_regs) || value != data->wm8766_regs[reg]) wm8766_write(chip, reg, value); } static void wm8776_registers_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; wm8776_write(chip, WM8776_RESET, 0); wm8776_write(chip, WM8776_PHASESWAP, WM8776_PH_MASK); wm8776_write(chip, WM8776_DACCTRL1, WM8776_DZCEN | WM8776_PL_LEFT_LEFT | WM8776_PL_RIGHT_RIGHT); wm8776_write(chip, WM8776_DACMUTE, chip->dac_mute ? WM8776_DMUTE : 0); wm8776_write(chip, WM8776_DACIFCTRL, WM8776_DACFMT_LJUST | WM8776_DACWL_24); wm8776_write(chip, WM8776_ADCIFCTRL, data->wm8776_regs[WM8776_ADCIFCTRL]); wm8776_write(chip, WM8776_MSTRCTRL, data->wm8776_regs[WM8776_MSTRCTRL]); wm8776_write(chip, WM8776_PWRDOWN, data->wm8776_regs[WM8776_PWRDOWN]); wm8776_write(chip, WM8776_HPLVOL, data->wm8776_regs[WM8776_HPLVOL]); wm8776_write(chip, WM8776_HPRVOL, data->wm8776_regs[WM8776_HPRVOL] | WM8776_UPDATE); wm8776_write(chip, WM8776_ADCLVOL, data->wm8776_regs[WM8776_ADCLVOL]); wm8776_write(chip, WM8776_ADCRVOL, data->wm8776_regs[WM8776_ADCRVOL]); wm8776_write(chip, WM8776_ADCMUX, data->wm8776_regs[WM8776_ADCMUX]); wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0]); wm8776_write(chip, WM8776_DACRVOL, chip->dac_volume[1] | WM8776_UPDATE); } static void wm8766_registers_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; wm8766_write(chip, WM8766_RESET, 0); wm8766_write(chip, WM8766_DAC_CTRL, data->wm8766_regs[WM8766_DAC_CTRL]); wm8766_write(chip, WM8766_INT_CTRL, WM8766_FMT_LJUST | WM8766_IWL_24); wm8766_write(chip, WM8766_DAC_CTRL2, WM8766_ZCD | (chip->dac_mute ? WM8766_DMUTE_MASK : 0)); wm8766_write(chip, WM8766_LDA1, chip->dac_volume[2]); wm8766_write(chip, WM8766_RDA1, chip->dac_volume[3]); wm8766_write(chip, WM8766_LDA2, chip->dac_volume[4]); wm8766_write(chip, WM8766_RDA2, chip->dac_volume[5]); wm8766_write(chip, WM8766_LDA3, chip->dac_volume[6]); wm8766_write(chip, WM8766_RDA3, chip->dac_volume[7] | WM8766_UPDATE); } static void wm8776_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; data->wm8776_regs[WM8776_HPLVOL] = (0x79 - 60) | WM8776_HPZCEN; data->wm8776_regs[WM8776_HPRVOL] = (0x79 - 60) | WM8776_HPZCEN; data->wm8776_regs[WM8776_ADCIFCTRL] = WM8776_ADCFMT_LJUST | WM8776_ADCWL_24 | WM8776_ADCMCLK; data->wm8776_regs[WM8776_MSTRCTRL] = WM8776_ADCRATE_256 | WM8776_DACRATE_256; data->wm8776_regs[WM8776_PWRDOWN] = WM8776_HPPD; data->wm8776_regs[WM8776_ADCLVOL] = 0xa5 | WM8776_ZCA; data->wm8776_regs[WM8776_ADCRVOL] = 0xa5 | WM8776_ZCA; data->wm8776_regs[WM8776_ADCMUX] = 0x001; wm8776_registers_init(chip); } static void wm8766_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; data->wm8766_regs[WM8766_DAC_CTRL] = WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT; wm8766_registers_init(chip); } static void xonar_ds_handle_hp_jack(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; bool hp_plugged; unsigned int reg; mutex_lock(&chip->mutex); hp_plugged = !(oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DS_HP_DETECT); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, hp_plugged ? 0 : GPIO_DS_OUTPUT_FRONTLR, GPIO_DS_OUTPUT_FRONTLR); reg = data->wm8766_regs[WM8766_DAC_CTRL] & ~WM8766_MUTEALL; if (hp_plugged) reg |= WM8766_MUTEALL; wm8766_write_cached(chip, WM8766_DAC_CTRL, reg); snd_jack_report(data->hp_jack, hp_plugged ? SND_JACK_HEADPHONE : 0); mutex_unlock(&chip->mutex); } static void xonar_ds_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; data->generic.anti_pop_delay = 300; data->generic.output_enable_bit = GPIO_DS_OUTPUT_ENABLE; wm8776_init(chip); wm8766_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DS_INPUT_ROUTE | GPIO_DS_OUTPUT_FRONTLR); oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DS_HP_DETECT); oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_DS_INPUT_ROUTE); oxygen_set_bits16(chip, OXYGEN_GPIO_INTERRUPT_MASK, GPIO_DS_HP_DETECT); chip->interrupt_mask |= OXYGEN_INT_GPIO; xonar_enable_output(chip); snd_jack_new(chip->card, "Headphone", SND_JACK_HEADPHONE, &data->hp_jack, false, false); xonar_ds_handle_hp_jack(chip); snd_component_add(chip->card, "WM8776"); snd_component_add(chip->card, "WM8766"); } static void xonar_hdav_slim_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; data->generic.anti_pop_delay = 300; data->generic.output_enable_bit = GPIO_SLIM_OUTPUT_ENABLE; wm8776_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_SLIM_HDMI_DISABLE | GPIO_SLIM_FIRMWARE_CLK | GPIO_SLIM_FIRMWARE_DATA); xonar_hdmi_init(chip, &data->hdmi); xonar_enable_output(chip); snd_component_add(chip->card, "WM8776"); } static void xonar_ds_cleanup(struct oxygen *chip) { xonar_disable_output(chip); wm8776_write(chip, WM8776_RESET, 0); } static void xonar_hdav_slim_cleanup(struct oxygen *chip) { xonar_hdmi_cleanup(chip); xonar_disable_output(chip); wm8776_write(chip, WM8776_RESET, 0); msleep(2); } static void xonar_ds_suspend(struct oxygen *chip) { xonar_ds_cleanup(chip); } static void xonar_hdav_slim_suspend(struct oxygen *chip) { xonar_hdav_slim_cleanup(chip); } static void xonar_ds_resume(struct oxygen *chip) { wm8776_registers_init(chip); wm8766_registers_init(chip); xonar_enable_output(chip); xonar_ds_handle_hp_jack(chip); } static void xonar_hdav_slim_resume(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; wm8776_registers_init(chip); xonar_hdmi_resume(chip, &data->hdmi); xonar_enable_output(chip); } static void wm8776_adc_hardware_filter(unsigned int channel, struct snd_pcm_hardware *hardware) { if (channel == PCM_A) { hardware->rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; hardware->rate_max = 96000; } } static void xonar_hdav_slim_hardware_filter(unsigned int channel, struct snd_pcm_hardware *hardware) { wm8776_adc_hardware_filter(channel, hardware); xonar_hdmi_pcm_hardware_filter(channel, hardware); } static void set_wm87x6_dac_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { } static void set_wm8776_adc_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { u16 reg; reg = WM8776_ADCRATE_256 | WM8776_DACRATE_256; if (params_rate(params) > 48000) reg |= WM8776_ADCOSR; wm8776_write_cached(chip, WM8776_MSTRCTRL, reg); } static void set_hdav_slim_dac_params(struct oxygen *chip, struct snd_pcm_hw_params *params) { struct xonar_wm87x6 *data = chip->model_data; xonar_set_hdmi_params(chip, &data->hdmi, params); } static void update_wm8776_volume(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; u8 to_change; if (chip->dac_volume[0] == chip->dac_volume[1]) { if (chip->dac_volume[0] != data->wm8776_regs[WM8776_DACLVOL] || chip->dac_volume[1] != data->wm8776_regs[WM8776_DACRVOL]) { wm8776_write(chip, WM8776_DACMASTER, chip->dac_volume[0] | WM8776_UPDATE); data->wm8776_regs[WM8776_DACLVOL] = chip->dac_volume[0]; data->wm8776_regs[WM8776_DACRVOL] = chip->dac_volume[0]; } } else { to_change = (chip->dac_volume[0] != data->wm8776_regs[WM8776_DACLVOL]) << 0; to_change |= (chip->dac_volume[1] != data->wm8776_regs[WM8776_DACLVOL]) << 1; if (to_change & 1) wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0] | ((to_change & 2) ? 0 : WM8776_UPDATE)); if (to_change & 2) wm8776_write(chip, WM8776_DACRVOL, chip->dac_volume[1] | WM8776_UPDATE); } } static void update_wm87x6_volume(struct oxygen *chip) { static const u8 wm8766_regs[6] = { WM8766_LDA1, WM8766_RDA1, WM8766_LDA2, WM8766_RDA2, WM8766_LDA3, WM8766_RDA3, }; struct xonar_wm87x6 *data = chip->model_data; unsigned int i; u8 to_change; update_wm8776_volume(chip); if (chip->dac_volume[2] == chip->dac_volume[3] && chip->dac_volume[2] == chip->dac_volume[4] && chip->dac_volume[2] == chip->dac_volume[5] && chip->dac_volume[2] == chip->dac_volume[6] && chip->dac_volume[2] == chip->dac_volume[7]) { to_change = 0; for (i = 0; i < 6; ++i) if (chip->dac_volume[2] != data->wm8766_regs[wm8766_regs[i]]) to_change = 1; if (to_change) { wm8766_write(chip, WM8766_MASTDA, chip->dac_volume[2] | WM8766_UPDATE); for (i = 0; i < 6; ++i) data->wm8766_regs[wm8766_regs[i]] = chip->dac_volume[2]; } } else { to_change = 0; for (i = 0; i < 6; ++i) to_change |= (chip->dac_volume[2 + i] != data->wm8766_regs[wm8766_regs[i]]) << i; for (i = 0; i < 6; ++i) if (to_change & (1 << i)) wm8766_write(chip, wm8766_regs[i], chip->dac_volume[2 + i] | ((to_change & (0x3e << i)) ? 0 : WM8766_UPDATE)); } } static void update_wm8776_mute(struct oxygen *chip) { wm8776_write_cached(chip, WM8776_DACMUTE, chip->dac_mute ? WM8776_DMUTE : 0); } static void update_wm87x6_mute(struct oxygen *chip) { update_wm8776_mute(chip); wm8766_write_cached(chip, WM8766_DAC_CTRL2, WM8766_ZCD | (chip->dac_mute ? WM8766_DMUTE_MASK : 0)); } static void update_wm8766_center_lfe_mix(struct oxygen *chip, bool mixed) { struct xonar_wm87x6 *data = chip->model_data; unsigned int reg; /* * The WM8766 can mix left and right channels, but this setting * applies to all three stereo pairs. */ reg = data->wm8766_regs[WM8766_DAC_CTRL] & ~(WM8766_PL_LEFT_MASK | WM8766_PL_RIGHT_MASK); if (mixed) reg |= WM8766_PL_LEFT_LRMIX | WM8766_PL_RIGHT_LRMIX; else reg |= WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT; wm8766_write_cached(chip, WM8766_DAC_CTRL, reg); } static void xonar_ds_gpio_changed(struct oxygen *chip) { xonar_ds_handle_hp_jack(chip); } static int wm8776_bit_switch_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; u16 bit = ctl->private_value & 0xffff; unsigned int reg_index = (ctl->private_value >> 16) & 0xff; bool invert = (ctl->private_value >> 24) & 1; value->value.integer.value[0] = ((data->wm8776_regs[reg_index] & bit) != 0) ^ invert; return 0; } static int wm8776_bit_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; u16 bit = ctl->private_value & 0xffff; u16 reg_value; unsigned int reg_index = (ctl->private_value >> 16) & 0xff; bool invert = (ctl->private_value >> 24) & 1; int changed; mutex_lock(&chip->mutex); reg_value = data->wm8776_regs[reg_index] & ~bit; if (value->value.integer.value[0] ^ invert) reg_value |= bit; changed = reg_value != data->wm8776_regs[reg_index]; if (changed) wm8776_write(chip, reg_index, reg_value); mutex_unlock(&chip->mutex); return changed; } static int wm8776_field_enum_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const hld[16] = { "0 ms", "2.67 ms", "5.33 ms", "10.6 ms", "21.3 ms", "42.7 ms", "85.3 ms", "171 ms", "341 ms", "683 ms", "1.37 s", "2.73 s", "5.46 s", "10.9 s", "21.8 s", "43.7 s", }; static const char *const atk_lim[11] = { "0.25 ms", "0.5 ms", "1 ms", "2 ms", "4 ms", "8 ms", "16 ms", "32 ms", "64 ms", "128 ms", "256 ms", }; static const char *const atk_alc[11] = { "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms", "134 ms", "269 ms", "538 ms", "1.08 s", "2.15 s", "4.3 s", "8.6 s", }; static const char *const dcy_lim[11] = { "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms", "19.2 ms", "38.4 ms", "76.8 ms", "154 ms", "307 ms", "614 ms", "1.23 s", }; static const char *const dcy_alc[11] = { "33.5 ms", "67.0 ms", "134 ms", "268 ms", "536 ms", "1.07 s", "2.14 s", "4.29 s", "8.58 s", "17.2 s", "34.3 s", }; static const char *const tranwin[8] = { "0 us", "62.5 us", "125 us", "250 us", "500 us", "1 ms", "2 ms", "4 ms", }; u8 max; const char *const *names; max = (ctl->private_value >> 12) & 0xf; switch ((ctl->private_value >> 24) & 0x1f) { case WM8776_ALCCTRL2: names = hld; break; case WM8776_ALCCTRL3: if (((ctl->private_value >> 20) & 0xf) == 0) { if (ctl->private_value & LC_CONTROL_LIMITER) names = atk_lim; else names = atk_alc; } else { if (ctl->private_value & LC_CONTROL_LIMITER) names = dcy_lim; else names = dcy_alc; } break; case WM8776_LIMITER: names = tranwin; break; default: return -ENXIO; } return snd_ctl_enum_info(info, 1, max + 1, names); } static int wm8776_field_volume_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 1; info->value.integer.min = (ctl->private_value >> 8) & 0xf; info->value.integer.max = (ctl->private_value >> 12) & 0xf; return 0; } static void wm8776_field_set_from_ctl(struct snd_kcontrol *ctl) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; unsigned int value, reg_index, mode; u8 min, max, shift; u16 mask, reg_value; bool invert; if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) == WM8776_LCSEL_LIMITER) mode = LC_CONTROL_LIMITER; else mode = LC_CONTROL_ALC; if (!(ctl->private_value & mode)) return; value = ctl->private_value & 0xf; min = (ctl->private_value >> 8) & 0xf; max = (ctl->private_value >> 12) & 0xf; mask = (ctl->private_value >> 16) & 0xf; shift = (ctl->private_value >> 20) & 0xf; reg_index = (ctl->private_value >> 24) & 0x1f; invert = (ctl->private_value >> 29) & 0x1; if (invert) value = max - (value - min); reg_value = data->wm8776_regs[reg_index]; reg_value &= ~(mask << shift); reg_value |= value << shift; wm8776_write_cached(chip, reg_index, reg_value); } static int wm8776_field_set(struct snd_kcontrol *ctl, unsigned int value) { struct oxygen *chip = ctl->private_data; u8 min, max; int changed; min = (ctl->private_value >> 8) & 0xf; max = (ctl->private_value >> 12) & 0xf; if (value < min || value > max) return -EINVAL; mutex_lock(&chip->mutex); changed = value != (ctl->private_value & 0xf); if (changed) { ctl->private_value = (ctl->private_value & ~0xf) | value; wm8776_field_set_from_ctl(ctl); } mutex_unlock(&chip->mutex); return changed; } static int wm8776_field_enum_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { value->value.enumerated.item[0] = ctl->private_value & 0xf; return 0; } static int wm8776_field_volume_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { value->value.integer.value[0] = ctl->private_value & 0xf; return 0; } static int wm8776_field_enum_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { return wm8776_field_set(ctl, value->value.enumerated.item[0]); } static int wm8776_field_volume_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { return wm8776_field_set(ctl, value->value.integer.value[0]); } static int wm8776_hp_vol_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 2; info->value.integer.min = 0x79 - 60; info->value.integer.max = 0x7f; return 0; } static int wm8776_hp_vol_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; mutex_lock(&chip->mutex); value->value.integer.value[0] = data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK; value->value.integer.value[1] = data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK; mutex_unlock(&chip->mutex); return 0; } static int wm8776_hp_vol_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; u8 to_update; mutex_lock(&chip->mutex); to_update = (value->value.integer.value[0] != (data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK)) << 0; to_update |= (value->value.integer.value[1] != (data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK)) << 1; if (value->value.integer.value[0] == value->value.integer.value[1]) { if (to_update) { wm8776_write(chip, WM8776_HPMASTER, value->value.integer.value[0] | WM8776_HPZCEN | WM8776_UPDATE); data->wm8776_regs[WM8776_HPLVOL] = value->value.integer.value[0] | WM8776_HPZCEN; data->wm8776_regs[WM8776_HPRVOL] = value->value.integer.value[0] | WM8776_HPZCEN; } } else { if (to_update & 1) wm8776_write(chip, WM8776_HPLVOL, value->value.integer.value[0] | WM8776_HPZCEN | ((to_update & 2) ? 0 : WM8776_UPDATE)); if (to_update & 2) wm8776_write(chip, WM8776_HPRVOL, value->value.integer.value[1] | WM8776_HPZCEN | WM8776_UPDATE); } mutex_unlock(&chip->mutex); return to_update != 0; } static int wm8776_input_mux_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; unsigned int mux_bit = ctl->private_value; value->value.integer.value[0] = !!(data->wm8776_regs[WM8776_ADCMUX] & mux_bit); return 0; } static int wm8776_input_mux_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; struct snd_kcontrol *other_ctl; unsigned int mux_bit = ctl->private_value; u16 reg; int changed; mutex_lock(&chip->mutex); reg = data->wm8776_regs[WM8776_ADCMUX]; if (value->value.integer.value[0]) { reg |= mux_bit; /* line-in and mic-in are exclusive */ mux_bit ^= 3; if (reg & mux_bit) { reg &= ~mux_bit; if (mux_bit == 1) other_ctl = data->line_adcmux_control; else other_ctl = data->mic_adcmux_control; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &other_ctl->id); } } else reg &= ~mux_bit; changed = reg != data->wm8776_regs[WM8776_ADCMUX]; if (changed) { oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, reg & 1 ? GPIO_DS_INPUT_ROUTE : 0, GPIO_DS_INPUT_ROUTE); wm8776_write(chip, WM8776_ADCMUX, reg); } mutex_unlock(&chip->mutex); return changed; } static int wm8776_input_vol_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; info->count = 2; info->value.integer.min = 0xa5; info->value.integer.max = 0xff; return 0; } static int wm8776_input_vol_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; mutex_lock(&chip->mutex); value->value.integer.value[0] = data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK; value->value.integer.value[1] = data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK; mutex_unlock(&chip->mutex); return 0; } static int wm8776_input_vol_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; int changed = 0; mutex_lock(&chip->mutex); changed = (value->value.integer.value[0] != (data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK)) || (value->value.integer.value[1] != (data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK)); wm8776_write_cached(chip, WM8776_ADCLVOL, value->value.integer.value[0] | WM8776_ZCA); wm8776_write_cached(chip, WM8776_ADCRVOL, value->value.integer.value[1] | WM8776_ZCA); mutex_unlock(&chip->mutex); return changed; } static int wm8776_level_control_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[3] = { "None", "Peak Limiter", "Automatic Level Control" }; return snd_ctl_enum_info(info, 1, 3, names); } static int wm8776_level_control_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; if (!(data->wm8776_regs[WM8776_ALCCTRL2] & WM8776_LCEN)) value->value.enumerated.item[0] = 0; else if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) == WM8776_LCSEL_LIMITER) value->value.enumerated.item[0] = 1; else value->value.enumerated.item[0] = 2; return 0; } static void activate_control(struct oxygen *chip, struct snd_kcontrol *ctl, unsigned int mode) { unsigned int access; if (ctl->private_value & mode) access = 0; else access = SNDRV_CTL_ELEM_ACCESS_INACTIVE; if ((ctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_INACTIVE) != access) { ctl->vd[0].access ^= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &ctl->id); } } static int wm8776_level_control_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; unsigned int mode = 0, i; u16 ctrl1, ctrl2; int changed; if (value->value.enumerated.item[0] >= 3) return -EINVAL; mutex_lock(&chip->mutex); changed = value->value.enumerated.item[0] != ctl->private_value; if (changed) { ctl->private_value = value->value.enumerated.item[0]; ctrl1 = data->wm8776_regs[WM8776_ALCCTRL1]; ctrl2 = data->wm8776_regs[WM8776_ALCCTRL2]; switch (value->value.enumerated.item[0]) { default: wm8776_write_cached(chip, WM8776_ALCCTRL2, ctrl2 & ~WM8776_LCEN); break; case 1: wm8776_write_cached(chip, WM8776_ALCCTRL1, (ctrl1 & ~WM8776_LCSEL_MASK) | WM8776_LCSEL_LIMITER); wm8776_write_cached(chip, WM8776_ALCCTRL2, ctrl2 | WM8776_LCEN); mode = LC_CONTROL_LIMITER; break; case 2: wm8776_write_cached(chip, WM8776_ALCCTRL1, (ctrl1 & ~WM8776_LCSEL_MASK) | WM8776_LCSEL_ALC_STEREO); wm8776_write_cached(chip, WM8776_ALCCTRL2, ctrl2 | WM8776_LCEN); mode = LC_CONTROL_ALC; break; } for (i = 0; i < ARRAY_SIZE(data->lc_controls); ++i) activate_control(chip, data->lc_controls[i], mode); } mutex_unlock(&chip->mutex); return changed; } static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) { static const char *const names[2] = { "None", "High-pass Filter" }; return snd_ctl_enum_info(info, 1, 2, names); } static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; value->value.enumerated.item[0] = !(data->wm8776_regs[WM8776_ADCIFCTRL] & WM8776_ADCHPD); return 0; } static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct xonar_wm87x6 *data = chip->model_data; unsigned int reg; int changed; mutex_lock(&chip->mutex); reg = data->wm8776_regs[WM8776_ADCIFCTRL] & ~WM8776_ADCHPD; if (!value->value.enumerated.item[0]) reg |= WM8776_ADCHPD; changed = reg != data->wm8776_regs[WM8776_ADCIFCTRL]; if (changed) wm8776_write(chip, WM8776_ADCIFCTRL, reg); mutex_unlock(&chip->mutex); return changed; } #define WM8776_BIT_SWITCH(xname, reg, bit, invert, flags) { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .info = snd_ctl_boolean_mono_info, \ .get = wm8776_bit_switch_get, \ .put = wm8776_bit_switch_put, \ .private_value = ((reg) << 16) | (bit) | ((invert) << 24) | (flags), \ } #define _WM8776_FIELD_CTL(xname, reg, shift, initval, min, max, mask, flags) \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .private_value = (initval) | ((min) << 8) | ((max) << 12) | \ ((mask) << 16) | ((shift) << 20) | ((reg) << 24) | (flags) #define WM8776_FIELD_CTL_ENUM(xname, reg, shift, init, min, max, mask, flags) {\ _WM8776_FIELD_CTL(xname " Capture Enum", \ reg, shift, init, min, max, mask, flags), \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_INACTIVE, \ .info = wm8776_field_enum_info, \ .get = wm8776_field_enum_get, \ .put = wm8776_field_enum_put, \ } #define WM8776_FIELD_CTL_VOLUME(a, b, c, d, e, f, g, h, tlv_p) { \ _WM8776_FIELD_CTL(a " Capture Volume", b, c, d, e, f, g, h), \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_INACTIVE | \ SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ .info = wm8776_field_volume_info, \ .get = wm8776_field_volume_get, \ .put = wm8776_field_volume_put, \ .tlv = { .p = tlv_p }, \ } static const DECLARE_TLV_DB_SCALE(wm87x6_dac_db_scale, -6000, 50, 0); static const DECLARE_TLV_DB_SCALE(wm8776_adc_db_scale, -2100, 50, 0); static const DECLARE_TLV_DB_SCALE(wm8776_hp_db_scale, -6000, 100, 0); static const DECLARE_TLV_DB_SCALE(wm8776_lct_db_scale, -1600, 100, 0); static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_db_scale, 0, 400, 0); static const DECLARE_TLV_DB_SCALE(wm8776_ngth_db_scale, -7800, 600, 0); static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_db_scale, -1200, 100, 0); static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_db_scale, -2100, 400, 0); static const struct snd_kcontrol_new ds_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Playback Volume", .info = wm8776_hp_vol_info, .get = wm8776_hp_vol_get, .put = wm8776_hp_vol_put, .tlv = { .p = wm8776_hp_db_scale }, }, WM8776_BIT_SWITCH("Headphone Playback Switch", WM8776_PWRDOWN, WM8776_HPPD, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Input Capture Volume", .info = wm8776_input_vol_info, .get = wm8776_input_vol_get, .put = wm8776_input_vol_put, .tlv = { .p = wm8776_adc_db_scale }, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Line Capture Switch", .info = snd_ctl_boolean_mono_info, .get = wm8776_input_mux_get, .put = wm8776_input_mux_put, .private_value = 1 << 0, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Mic Capture Switch", .info = snd_ctl_boolean_mono_info, .get = wm8776_input_mux_get, .put = wm8776_input_mux_put, .private_value = 1 << 1, }, WM8776_BIT_SWITCH("Front Mic Capture Switch", WM8776_ADCMUX, 1 << 2, 0, 0), WM8776_BIT_SWITCH("Aux Capture Switch", WM8776_ADCMUX, 1 << 3, 0, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "ADC Filter Capture Enum", .info = hpf_info, .get = hpf_get, .put = hpf_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Level Control Capture Enum", .info = wm8776_level_control_info, .get = wm8776_level_control_get, .put = wm8776_level_control_put, .private_value = 0, }, }; static const struct snd_kcontrol_new hdav_slim_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "HDMI Playback Switch", .info = snd_ctl_boolean_mono_info, .get = xonar_gpio_bit_switch_get, .put = xonar_gpio_bit_switch_put, .private_value = GPIO_SLIM_HDMI_DISABLE | XONAR_GPIO_BIT_INVERT, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Playback Volume", .info = wm8776_hp_vol_info, .get = wm8776_hp_vol_get, .put = wm8776_hp_vol_put, .tlv = { .p = wm8776_hp_db_scale }, }, WM8776_BIT_SWITCH("Headphone Playback Switch", WM8776_PWRDOWN, WM8776_HPPD, 1, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Input Capture Volume", .info = wm8776_input_vol_info, .get = wm8776_input_vol_get, .put = wm8776_input_vol_put, .tlv = { .p = wm8776_adc_db_scale }, }, WM8776_BIT_SWITCH("Mic Capture Switch", WM8776_ADCMUX, 1 << 0, 0, 0), WM8776_BIT_SWITCH("Aux Capture Switch", WM8776_ADCMUX, 1 << 1, 0, 0), { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "ADC Filter Capture Enum", .info = hpf_info, .get = hpf_get, .put = hpf_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Level Control Capture Enum", .info = wm8776_level_control_info, .get = wm8776_level_control_get, .put = wm8776_level_control_put, .private_value = 0, }, }; static const struct snd_kcontrol_new lc_controls[] = { WM8776_FIELD_CTL_VOLUME("Limiter Threshold", WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf, LC_CONTROL_LIMITER, wm8776_lct_db_scale), WM8776_FIELD_CTL_ENUM("Limiter Attack Time", WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf, LC_CONTROL_LIMITER), WM8776_FIELD_CTL_ENUM("Limiter Decay Time", WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf, LC_CONTROL_LIMITER), WM8776_FIELD_CTL_ENUM("Limiter Transient Window", WM8776_LIMITER, 4, 2, 0, 7, 0x7, LC_CONTROL_LIMITER), WM8776_FIELD_CTL_VOLUME("Limiter Maximum Attenuation", WM8776_LIMITER, 0, 6, 3, 12, 0xf, LC_CONTROL_LIMITER, wm8776_maxatten_lim_db_scale), WM8776_FIELD_CTL_VOLUME("ALC Target Level", WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf, LC_CONTROL_ALC, wm8776_lct_db_scale), WM8776_FIELD_CTL_ENUM("ALC Attack Time", WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf, LC_CONTROL_ALC), WM8776_FIELD_CTL_ENUM("ALC Decay Time", WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf, LC_CONTROL_ALC), WM8776_FIELD_CTL_VOLUME("ALC Maximum Gain", WM8776_ALCCTRL1, 4, 7, 1, 7, 0x7, LC_CONTROL_ALC, wm8776_maxgain_db_scale), WM8776_FIELD_CTL_VOLUME("ALC Maximum Attenuation", WM8776_LIMITER, 0, 10, 10, 15, 0xf, LC_CONTROL_ALC, wm8776_maxatten_alc_db_scale), WM8776_FIELD_CTL_ENUM("ALC Hold Time", WM8776_ALCCTRL2, 0, 0, 0, 15, 0xf, LC_CONTROL_ALC), WM8776_BIT_SWITCH("Noise Gate Capture Switch", WM8776_NOISEGATE, WM8776_NGAT, 0, LC_CONTROL_ALC), WM8776_FIELD_CTL_VOLUME("Noise Gate Threshold", WM8776_NOISEGATE, 2, 0, 0, 7, 0x7, LC_CONTROL_ALC, wm8776_ngth_db_scale), }; static int add_lc_controls(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; unsigned int i; struct snd_kcontrol *ctl; int err; BUILD_BUG_ON(ARRAY_SIZE(lc_controls) != ARRAY_SIZE(data->lc_controls)); for (i = 0; i < ARRAY_SIZE(lc_controls); ++i) { ctl = snd_ctl_new1(&lc_controls[i], chip); if (!ctl) return -ENOMEM; err = snd_ctl_add(chip->card, ctl); if (err < 0) return err; data->lc_controls[i] = ctl; } return 0; } static int xonar_ds_mixer_init(struct oxygen *chip) { struct xonar_wm87x6 *data = chip->model_data; unsigned int i; struct snd_kcontrol *ctl; int err; for (i = 0; i < ARRAY_SIZE(ds_controls); ++i) { ctl = snd_ctl_new1(&ds_controls[i], chip); if (!ctl) return -ENOMEM; err = snd_ctl_add(chip->card, ctl); if (err < 0) return err; if (!strcmp(ctl->id.name, "Line Capture Switch")) data->line_adcmux_control = ctl; else if (!strcmp(ctl->id.name, "Mic Capture Switch")) data->mic_adcmux_control = ctl; } if (!data->line_adcmux_control || !data->mic_adcmux_control) return -ENXIO; return add_lc_controls(chip); } static int xonar_hdav_slim_mixer_init(struct oxygen *chip) { unsigned int i; struct snd_kcontrol *ctl; int err; for (i = 0; i < ARRAY_SIZE(hdav_slim_controls); ++i) { ctl = snd_ctl_new1(&hdav_slim_controls[i], chip); if (!ctl) return -ENOMEM; err = snd_ctl_add(chip->card, ctl); if (err < 0) return err; } return add_lc_controls(chip); } static void dump_wm8776_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct xonar_wm87x6 *data = chip->model_data; unsigned int i; snd_iprintf(buffer, "\nWM8776:\n00:"); for (i = 0; i < 0x10; ++i) snd_iprintf(buffer, " %03x", data->wm8776_regs[i]); snd_iprintf(buffer, "\n10:"); for (i = 0x10; i < 0x17; ++i) snd_iprintf(buffer, " %03x", data->wm8776_regs[i]); snd_iprintf(buffer, "\n"); } static void dump_wm87x6_registers(struct oxygen *chip, struct snd_info_buffer *buffer) { struct xonar_wm87x6 *data = chip->model_data; unsigned int i; dump_wm8776_registers(chip, buffer); snd_iprintf(buffer, "\nWM8766:\n00:"); for (i = 0; i < 0x10; ++i) snd_iprintf(buffer, " %03x", data->wm8766_regs[i]); snd_iprintf(buffer, "\n"); } static const struct oxygen_model model_xonar_ds = { .longname = "Asus Virtuoso 66", .chip = "AV200", .init = xonar_ds_init, .mixer_init = xonar_ds_mixer_init, .cleanup = xonar_ds_cleanup, .suspend = xonar_ds_suspend, .resume = xonar_ds_resume, .pcm_hardware_filter = wm8776_adc_hardware_filter, .set_dac_params = set_wm87x6_dac_params, .set_adc_params = set_wm8776_adc_params, .update_dac_volume = update_wm87x6_volume, .update_dac_mute = update_wm87x6_mute, .update_center_lfe_mix = update_wm8766_center_lfe_mix, .gpio_changed = xonar_ds_gpio_changed, .dump_registers = dump_wm87x6_registers, .dac_tlv = wm87x6_dac_db_scale, .model_data_size = sizeof(struct xonar_wm87x6), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_1 | CAPTURE_1_FROM_SPDIF, .dac_channels_pcm = 8, .dac_channels_mixer = 8, .dac_volume_min = 255 - 2*60, .dac_volume_max = 255, .function_flags = OXYGEN_FUNCTION_SPI, .dac_mclks = OXYGEN_MCLKS(256, 256, 128), .adc_mclks = OXYGEN_MCLKS(256, 256, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; static const struct oxygen_model model_xonar_hdav_slim = { .shortname = "Xonar HDAV1.3 Slim", .longname = "Asus Virtuoso 200", .chip = "AV200", .init = xonar_hdav_slim_init, .mixer_init = xonar_hdav_slim_mixer_init, .cleanup = xonar_hdav_slim_cleanup, .suspend = xonar_hdav_slim_suspend, .resume = xonar_hdav_slim_resume, .pcm_hardware_filter = xonar_hdav_slim_hardware_filter, .set_dac_params = set_hdav_slim_dac_params, .set_adc_params = set_wm8776_adc_params, .update_dac_volume = update_wm8776_volume, .update_dac_mute = update_wm8776_mute, .uart_input = xonar_hdmi_uart_input, .dump_registers = dump_wm8776_registers, .dac_tlv = wm87x6_dac_db_scale, .model_data_size = sizeof(struct xonar_wm87x6), .device_config = PLAYBACK_0_TO_I2S | PLAYBACK_1_TO_SPDIF | CAPTURE_0_FROM_I2S_1 | CAPTURE_1_FROM_SPDIF, .dac_channels_pcm = 8, .dac_channels_mixer = 2, .dac_volume_min = 255 - 2*60, .dac_volume_max = 255, .function_flags = OXYGEN_FUNCTION_2WIRE, .dac_mclks = OXYGEN_MCLKS(256, 256, 128), .adc_mclks = OXYGEN_MCLKS(256, 256, 128), .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, }; int get_xonar_wm87x6_model(struct oxygen *chip, const struct pci_device_id *id) { switch (id->subdevice) { case 0x838e: chip->model = model_xonar_ds; chip->model.shortname = "Xonar DS"; break; case 0x8522: chip->model = model_xonar_ds; chip->model.shortname = "Xonar DSX"; break; case 0x835e: chip->model = model_xonar_hdav_slim; break; default: return -EINVAL; } return 0; }
linux-master
sound/pci/oxygen/xonar_wm87x6.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Matt Wu <[email protected]> * Apr 26, 2001 * Routines for control of ALi pci audio M5451 * * BUGS: * -- * * TODO: * -- */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/info.h> #include <sound/ac97_codec.h> #include <sound/mpu401.h> #include <sound/initval.h> MODULE_AUTHOR("Matt Wu <[email protected]>"); MODULE_DESCRIPTION("ALI M5451"); MODULE_LICENSE("GPL"); static int index = SNDRV_DEFAULT_IDX1; /* Index */ static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ static int pcm_channels = 32; static bool spdif; module_param(index, int, 0444); MODULE_PARM_DESC(index, "Index value for ALI M5451 PCI Audio."); module_param(id, charp, 0444); MODULE_PARM_DESC(id, "ID string for ALI M5451 PCI Audio."); module_param(pcm_channels, int, 0444); MODULE_PARM_DESC(pcm_channels, "PCM Channels"); module_param(spdif, bool, 0444); MODULE_PARM_DESC(spdif, "Support SPDIF I/O"); /* just for backward compatibility */ static bool enable; module_param(enable, bool, 0444); /* * Constants definition */ #define DEVICE_ID_ALI5451 ((PCI_VENDOR_ID_AL<<16)|PCI_DEVICE_ID_AL_M5451) #define ALI_CHANNELS 32 #define ALI_PCM_IN_CHANNEL 31 #define ALI_SPDIF_IN_CHANNEL 19 #define ALI_SPDIF_OUT_CHANNEL 15 #define ALI_CENTER_CHANNEL 24 #define ALI_LEF_CHANNEL 23 #define ALI_SURR_LEFT_CHANNEL 26 #define ALI_SURR_RIGHT_CHANNEL 25 #define ALI_MODEM_IN_CHANNEL 21 #define ALI_MODEM_OUT_CHANNEL 20 #define SNDRV_ALI_VOICE_TYPE_PCM 01 #define SNDRV_ALI_VOICE_TYPE_OTH 02 #define ALI_5451_V02 0x02 /* * Direct Registers */ #define ALI_LEGACY_DMAR0 0x00 /* ADR0 */ #define ALI_LEGACY_DMAR4 0x04 /* CNT0 */ #define ALI_LEGACY_DMAR11 0x0b /* MOD */ #define ALI_LEGACY_DMAR15 0x0f /* MMR */ #define ALI_MPUR0 0x20 #define ALI_MPUR1 0x21 #define ALI_MPUR2 0x22 #define ALI_MPUR3 0x23 #define ALI_AC97_WRITE 0x40 #define ALI_AC97_READ 0x44 #define ALI_SCTRL 0x48 #define ALI_SPDIF_OUT_ENABLE 0x20 #define ALI_SCTRL_LINE_IN2 (1 << 9) #define ALI_SCTRL_GPIO_IN2 (1 << 13) #define ALI_SCTRL_LINE_OUT_EN (1 << 20) #define ALI_SCTRL_GPIO_OUT_EN (1 << 23) #define ALI_SCTRL_CODEC1_READY (1 << 24) #define ALI_SCTRL_CODEC2_READY (1 << 25) #define ALI_AC97_GPIO 0x4c #define ALI_AC97_GPIO_ENABLE 0x8000 #define ALI_AC97_GPIO_DATA_SHIFT 16 #define ALI_SPDIF_CS 0x70 #define ALI_SPDIF_CTRL 0x74 #define ALI_SPDIF_IN_FUNC_ENABLE 0x02 #define ALI_SPDIF_IN_CH_STATUS 0x40 #define ALI_SPDIF_OUT_CH_STATUS 0xbf #define ALI_START 0x80 #define ALI_STOP 0x84 #define ALI_CSPF 0x90 #define ALI_AINT 0x98 #define ALI_GC_CIR 0xa0 #define ENDLP_IE 0x00001000 #define MIDLP_IE 0x00002000 #define ALI_AINTEN 0xa4 #define ALI_VOLUME 0xa8 #define ALI_SBDELTA_DELTA_R 0xac #define ALI_MISCINT 0xb0 #define ADDRESS_IRQ 0x00000020 #define TARGET_REACHED 0x00008000 #define MIXER_OVERFLOW 0x00000800 #define MIXER_UNDERFLOW 0x00000400 #define GPIO_IRQ 0x01000000 #define ALI_SBBL_SBCL 0xc0 #define ALI_SBCTRL_SBE2R_SBDD 0xc4 #define ALI_STIMER 0xc8 #define ALI_GLOBAL_CONTROL 0xd4 #define ALI_SPDIF_OUT_SEL_PCM 0x00000400 /* bit 10 */ #define ALI_SPDIF_IN_SUPPORT 0x00000800 /* bit 11 */ #define ALI_SPDIF_OUT_CH_ENABLE 0x00008000 /* bit 15 */ #define ALI_SPDIF_IN_CH_ENABLE 0x00080000 /* bit 19 */ #define ALI_PCM_IN_ENABLE 0x80000000 /* bit 31 */ #define ALI_CSO_ALPHA_FMS 0xe0 #define ALI_LBA 0xe4 #define ALI_ESO_DELTA 0xe8 #define ALI_GVSEL_PAN_VOC_CTRL_EC 0xf0 #define ALI_EBUF1 0xf4 #define ALI_EBUF2 0xf8 #define ALI_REG(codec, x) ((codec)->port + x) #define MAX_CODECS 2 struct snd_ali; struct snd_ali_voice; struct snd_ali_channel_control { /* register data */ struct REGDATA { unsigned int start; unsigned int stop; unsigned int aint; unsigned int ainten; } data; /* register addresses */ struct REGS { unsigned int start; unsigned int stop; unsigned int aint; unsigned int ainten; unsigned int ac97read; unsigned int ac97write; } regs; }; struct snd_ali_voice { unsigned int number; unsigned int use :1, pcm :1, midi :1, mode :1, synth :1, running :1; /* PCM data */ struct snd_ali *codec; struct snd_pcm_substream *substream; struct snd_ali_voice *extra; int eso; /* final ESO value for channel */ int count; /* runtime->period_size */ /* --- */ void *private_data; void (*private_free)(void *private_data); }; struct snd_alidev { struct snd_ali_voice voices[ALI_CHANNELS]; unsigned int chcnt; /* num of opened channels */ unsigned int chmap; /* bitmap for opened channels */ unsigned int synthcount; }; #define ALI_GLOBAL_REGS 56 #define ALI_CHANNEL_REGS 8 struct snd_ali_image { u32 regs[ALI_GLOBAL_REGS]; u32 channel_regs[ALI_CHANNELS][ALI_CHANNEL_REGS]; }; struct snd_ali { int irq; unsigned long port; unsigned char revision; unsigned int hw_initialized :1; unsigned int spdif_support :1; struct pci_dev *pci; struct pci_dev *pci_m1533; struct pci_dev *pci_m7101; struct snd_card *card; struct snd_pcm *pcm[MAX_CODECS]; struct snd_alidev synth; struct snd_ali_channel_control chregs; /* S/PDIF Mask */ unsigned int spdif_mask; unsigned int spurious_irq_count; unsigned int spurious_irq_max_delta; unsigned int num_of_codecs; struct snd_ac97_bus *ac97_bus; struct snd_ac97 *ac97[MAX_CODECS]; unsigned short ac97_ext_id; unsigned short ac97_ext_status; spinlock_t reg_lock; spinlock_t voice_alloc; #ifdef CONFIG_PM_SLEEP struct snd_ali_image *image; #endif }; static const struct pci_device_id snd_ali_ids[] = { {PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5451), 0, 0, 0}, {0, } }; MODULE_DEVICE_TABLE(pci, snd_ali_ids); static void snd_ali_clear_voices(struct snd_ali *, unsigned int, unsigned int); static unsigned short snd_ali_codec_peek(struct snd_ali *, int, unsigned short); static void snd_ali_codec_poke(struct snd_ali *, int, unsigned short, unsigned short); /* * AC97 ACCESS */ static inline unsigned int snd_ali_5451_peek(struct snd_ali *codec, unsigned int port) { return (unsigned int)inl(ALI_REG(codec, port)); } static inline void snd_ali_5451_poke(struct snd_ali *codec, unsigned int port, unsigned int val) { outl((unsigned int)val, ALI_REG(codec, port)); } static int snd_ali_codec_ready(struct snd_ali *codec, unsigned int port) { unsigned long end_time; unsigned int res; end_time = jiffies + msecs_to_jiffies(250); for (;;) { res = snd_ali_5451_peek(codec,port); if (!(res & 0x8000)) return 0; if (!time_after_eq(end_time, jiffies)) break; schedule_timeout_uninterruptible(1); } snd_ali_5451_poke(codec, port, res & ~0x8000); dev_dbg(codec->card->dev, "ali_codec_ready: codec is not ready.\n "); return -EIO; } static int snd_ali_stimer_ready(struct snd_ali *codec) { unsigned long end_time; unsigned long dwChk1,dwChk2; dwChk1 = snd_ali_5451_peek(codec, ALI_STIMER); end_time = jiffies + msecs_to_jiffies(250); for (;;) { dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER); if (dwChk2 != dwChk1) return 0; if (!time_after_eq(end_time, jiffies)) break; schedule_timeout_uninterruptible(1); } dev_err(codec->card->dev, "ali_stimer_read: stimer is not ready.\n"); return -EIO; } static void snd_ali_codec_poke(struct snd_ali *codec,int secondary, unsigned short reg, unsigned short val) { unsigned int dwVal; unsigned int port; if (reg >= 0x80) { dev_err(codec->card->dev, "ali_codec_poke: reg(%xh) invalid.\n", reg); return; } port = codec->chregs.regs.ac97write; if (snd_ali_codec_ready(codec, port) < 0) return; if (snd_ali_stimer_ready(codec) < 0) return; dwVal = (unsigned int) (reg & 0xff); dwVal |= 0x8000 | (val << 16); if (secondary) dwVal |= 0x0080; if (codec->revision == ALI_5451_V02) dwVal |= 0x0100; snd_ali_5451_poke(codec, port, dwVal); return ; } static unsigned short snd_ali_codec_peek(struct snd_ali *codec, int secondary, unsigned short reg) { unsigned int dwVal; unsigned int port; if (reg >= 0x80) { dev_err(codec->card->dev, "ali_codec_peek: reg(%xh) invalid.\n", reg); return ~0; } port = codec->chregs.regs.ac97read; if (snd_ali_codec_ready(codec, port) < 0) return ~0; if (snd_ali_stimer_ready(codec) < 0) return ~0; dwVal = (unsigned int) (reg & 0xff); dwVal |= 0x8000; /* bit 15*/ if (secondary) dwVal |= 0x0080; snd_ali_5451_poke(codec, port, dwVal); if (snd_ali_stimer_ready(codec) < 0) return ~0; if (snd_ali_codec_ready(codec, port) < 0) return ~0; return (snd_ali_5451_peek(codec, port) & 0xffff0000) >> 16; } static void snd_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val ) { struct snd_ali *codec = ac97->private_data; dev_dbg(codec->card->dev, "codec_write: reg=%xh data=%xh.\n", reg, val); if (reg == AC97_GPIO_STATUS) { outl((val << ALI_AC97_GPIO_DATA_SHIFT) | ALI_AC97_GPIO_ENABLE, ALI_REG(codec, ALI_AC97_GPIO)); return; } snd_ali_codec_poke(codec, ac97->num, reg, val); return ; } static unsigned short snd_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) { struct snd_ali *codec = ac97->private_data; dev_dbg(codec->card->dev, "codec_read reg=%xh.\n", reg); return snd_ali_codec_peek(codec, ac97->num, reg); } /* * AC97 Reset */ static int snd_ali_reset_5451(struct snd_ali *codec) { struct pci_dev *pci_dev; unsigned short wCount, wReg; unsigned int dwVal; pci_dev = codec->pci_m1533; if (pci_dev) { pci_read_config_dword(pci_dev, 0x7c, &dwVal); pci_write_config_dword(pci_dev, 0x7c, dwVal | 0x08000000); mdelay(5); pci_read_config_dword(pci_dev, 0x7c, &dwVal); pci_write_config_dword(pci_dev, 0x7c, dwVal & 0xf7ffffff); mdelay(5); } pci_dev = codec->pci; pci_read_config_dword(pci_dev, 0x44, &dwVal); pci_write_config_dword(pci_dev, 0x44, dwVal | 0x000c0000); udelay(500); pci_read_config_dword(pci_dev, 0x44, &dwVal); pci_write_config_dword(pci_dev, 0x44, dwVal & 0xfffbffff); mdelay(5); wCount = 200; while(wCount--) { wReg = snd_ali_codec_peek(codec, 0, AC97_POWERDOWN); if ((wReg & 0x000f) == 0x000f) return 0; mdelay(5); } /* non-fatal if you have a non PM capable codec */ /* dev_warn(codec->card->dev, "ali5451: reset time out\n"); */ return 0; } /* * ALI 5451 Controller */ static void snd_ali_enable_special_channel(struct snd_ali *codec, unsigned int channel) { unsigned long dwVal; dwVal = inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)); dwVal |= 1 << (channel & 0x0000001f); outl(dwVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); } static void snd_ali_disable_special_channel(struct snd_ali *codec, unsigned int channel) { unsigned long dwVal; dwVal = inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)); dwVal &= ~(1 << (channel & 0x0000001f)); outl(dwVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); } static void snd_ali_enable_address_interrupt(struct snd_ali *codec) { unsigned int gc; gc = inl(ALI_REG(codec, ALI_GC_CIR)); gc |= ENDLP_IE; gc |= MIDLP_IE; outl( gc, ALI_REG(codec, ALI_GC_CIR)); } static void snd_ali_disable_address_interrupt(struct snd_ali *codec) { unsigned int gc; gc = inl(ALI_REG(codec, ALI_GC_CIR)); gc &= ~ENDLP_IE; gc &= ~MIDLP_IE; outl(gc, ALI_REG(codec, ALI_GC_CIR)); } static void snd_ali_disable_voice_irq(struct snd_ali *codec, unsigned int channel) { unsigned int mask; struct snd_ali_channel_control *pchregs = &(codec->chregs); dev_dbg(codec->card->dev, "disable_voice_irq channel=%d\n", channel); mask = 1 << (channel & 0x1f); pchregs->data.ainten = inl(ALI_REG(codec, pchregs->regs.ainten)); pchregs->data.ainten &= ~mask; outl(pchregs->data.ainten, ALI_REG(codec, pchregs->regs.ainten)); } static int snd_ali_alloc_pcm_channel(struct snd_ali *codec, int channel) { unsigned int idx = channel & 0x1f; if (codec->synth.chcnt >= ALI_CHANNELS){ dev_err(codec->card->dev, "ali_alloc_pcm_channel: no free channels.\n"); return -1; } if (!(codec->synth.chmap & (1 << idx))) { codec->synth.chmap |= 1 << idx; codec->synth.chcnt++; dev_dbg(codec->card->dev, "alloc_pcm_channel no. %d.\n", idx); return idx; } return -1; } static int snd_ali_find_free_channel(struct snd_ali * codec, int rec) { int idx; int result = -1; dev_dbg(codec->card->dev, "find_free_channel: for %s\n", rec ? "rec" : "pcm"); /* recording */ if (rec) { if (codec->spdif_support && (inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)) & ALI_SPDIF_IN_SUPPORT)) idx = ALI_SPDIF_IN_CHANNEL; else idx = ALI_PCM_IN_CHANNEL; result = snd_ali_alloc_pcm_channel(codec, idx); if (result >= 0) return result; else { dev_err(codec->card->dev, "ali_find_free_channel: record channel is busy now.\n"); return -1; } } /* playback... */ if (codec->spdif_support && (inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)) & ALI_SPDIF_OUT_CH_ENABLE)) { idx = ALI_SPDIF_OUT_CHANNEL; result = snd_ali_alloc_pcm_channel(codec, idx); if (result >= 0) return result; else dev_err(codec->card->dev, "ali_find_free_channel: S/PDIF out channel is in busy now.\n"); } for (idx = 0; idx < ALI_CHANNELS; idx++) { result = snd_ali_alloc_pcm_channel(codec, idx); if (result >= 0) return result; } dev_err(codec->card->dev, "ali_find_free_channel: no free channels.\n"); return -1; } static void snd_ali_free_channel_pcm(struct snd_ali *codec, int channel) { unsigned int idx = channel & 0x0000001f; dev_dbg(codec->card->dev, "free_channel_pcm channel=%d\n", channel); if (channel < 0 || channel >= ALI_CHANNELS) return; if (!(codec->synth.chmap & (1 << idx))) { dev_err(codec->card->dev, "ali_free_channel_pcm: channel %d is not in use.\n", channel); return; } else { codec->synth.chmap &= ~(1 << idx); codec->synth.chcnt--; } } static void snd_ali_stop_voice(struct snd_ali *codec, unsigned int channel) { unsigned int mask = 1 << (channel & 0x1f); dev_dbg(codec->card->dev, "stop_voice: channel=%d\n", channel); outl(mask, ALI_REG(codec, codec->chregs.regs.stop)); } /* * S/PDIF Part */ static void snd_ali_delay(struct snd_ali *codec,int interval) { unsigned long begintimer,currenttimer; begintimer = inl(ALI_REG(codec, ALI_STIMER)); currenttimer = inl(ALI_REG(codec, ALI_STIMER)); while (currenttimer < begintimer + interval) { if (snd_ali_stimer_ready(codec) < 0) break; currenttimer = inl(ALI_REG(codec, ALI_STIMER)); cpu_relax(); } } static void snd_ali_detect_spdif_rate(struct snd_ali *codec) { u16 wval; u16 count = 0; u8 bval, R1 = 0, R2; bval = inb(ALI_REG(codec, ALI_SPDIF_CTRL + 1)); bval |= 0x1F; outb(bval, ALI_REG(codec, ALI_SPDIF_CTRL + 1)); while ((R1 < 0x0b || R1 > 0x0e) && R1 != 0x12 && count <= 50000) { count ++; snd_ali_delay(codec, 6); bval = inb(ALI_REG(codec, ALI_SPDIF_CTRL + 1)); R1 = bval & 0x1F; } if (count > 50000) { dev_err(codec->card->dev, "ali_detect_spdif_rate: timeout!\n"); return; } for (count = 0; count <= 50000; count++) { snd_ali_delay(codec, 6); bval = inb(ALI_REG(codec,ALI_SPDIF_CTRL + 1)); R2 = bval & 0x1F; if (R2 != R1) R1 = R2; else break; } if (count > 50000) { dev_err(codec->card->dev, "ali_detect_spdif_rate: timeout!\n"); return; } if (R2 >= 0x0b && R2 <= 0x0e) { wval = inw(ALI_REG(codec, ALI_SPDIF_CTRL + 2)); wval &= 0xe0f0; wval |= (0x09 << 8) | 0x05; outw(wval, ALI_REG(codec, ALI_SPDIF_CTRL + 2)); bval = inb(ALI_REG(codec, ALI_SPDIF_CS + 3)) & 0xf0; outb(bval | 0x02, ALI_REG(codec, ALI_SPDIF_CS + 3)); } else if (R2 == 0x12) { wval = inw(ALI_REG(codec, ALI_SPDIF_CTRL + 2)); wval &= 0xe0f0; wval |= (0x0e << 8) | 0x08; outw(wval, ALI_REG(codec, ALI_SPDIF_CTRL + 2)); bval = inb(ALI_REG(codec,ALI_SPDIF_CS + 3)) & 0xf0; outb(bval | 0x03, ALI_REG(codec, ALI_SPDIF_CS + 3)); } } static unsigned int snd_ali_get_spdif_in_rate(struct snd_ali *codec) { u32 dwRate; u8 bval; bval = inb(ALI_REG(codec, ALI_SPDIF_CTRL)); bval &= 0x7f; bval |= 0x40; outb(bval, ALI_REG(codec, ALI_SPDIF_CTRL)); snd_ali_detect_spdif_rate(codec); bval = inb(ALI_REG(codec, ALI_SPDIF_CS + 3)); bval &= 0x0f; switch (bval) { case 0: dwRate = 44100; break; case 1: dwRate = 48000; break; case 2: dwRate = 32000; break; default: dwRate = 0; break; } return dwRate; } static void snd_ali_enable_spdif_in(struct snd_ali *codec) { unsigned int dwVal; dwVal = inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)); dwVal |= ALI_SPDIF_IN_SUPPORT; outl(dwVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); dwVal = inb(ALI_REG(codec, ALI_SPDIF_CTRL)); dwVal |= 0x02; outb(dwVal, ALI_REG(codec, ALI_SPDIF_CTRL)); snd_ali_enable_special_channel(codec, ALI_SPDIF_IN_CHANNEL); } static void snd_ali_disable_spdif_in(struct snd_ali *codec) { unsigned int dwVal; dwVal = inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)); dwVal &= ~ALI_SPDIF_IN_SUPPORT; outl(dwVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); snd_ali_disable_special_channel(codec, ALI_SPDIF_IN_CHANNEL); } static void snd_ali_set_spdif_out_rate(struct snd_ali *codec, unsigned int rate) { unsigned char bVal; unsigned int dwRate; switch (rate) { case 32000: dwRate = 0x300; break; case 48000: dwRate = 0x200; break; default: dwRate = 0; break; } bVal = inb(ALI_REG(codec, ALI_SPDIF_CTRL)); bVal &= (unsigned char)(~(1<<6)); bVal |= 0x80; /* select right */ outb(bVal, ALI_REG(codec, ALI_SPDIF_CTRL)); outb(dwRate | 0x20, ALI_REG(codec, ALI_SPDIF_CS + 2)); bVal &= ~0x80; /* select left */ outb(bVal, ALI_REG(codec, ALI_SPDIF_CTRL)); outw(rate | 0x10, ALI_REG(codec, ALI_SPDIF_CS + 2)); } static void snd_ali_enable_spdif_out(struct snd_ali *codec) { unsigned short wVal; unsigned char bVal; struct pci_dev *pci_dev; pci_dev = codec->pci_m1533; if (pci_dev == NULL) return; pci_read_config_byte(pci_dev, 0x61, &bVal); bVal |= 0x40; pci_write_config_byte(pci_dev, 0x61, bVal); pci_read_config_byte(pci_dev, 0x7d, &bVal); bVal |= 0x01; pci_write_config_byte(pci_dev, 0x7d, bVal); pci_read_config_byte(pci_dev, 0x7e, &bVal); bVal &= (~0x20); bVal |= 0x10; pci_write_config_byte(pci_dev, 0x7e, bVal); bVal = inb(ALI_REG(codec, ALI_SCTRL)); outb(bVal | ALI_SPDIF_OUT_ENABLE, ALI_REG(codec, ALI_SCTRL)); bVal = inb(ALI_REG(codec, ALI_SPDIF_CTRL)); outb(bVal & ALI_SPDIF_OUT_CH_STATUS, ALI_REG(codec, ALI_SPDIF_CTRL)); wVal = inw(ALI_REG(codec, ALI_GLOBAL_CONTROL)); wVal |= ALI_SPDIF_OUT_SEL_PCM; outw(wVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); snd_ali_disable_special_channel(codec, ALI_SPDIF_OUT_CHANNEL); } static void snd_ali_enable_spdif_chnout(struct snd_ali *codec) { unsigned short wVal; wVal = inw(ALI_REG(codec, ALI_GLOBAL_CONTROL)); wVal &= ~ALI_SPDIF_OUT_SEL_PCM; outw(wVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); /* wVal = inw(ALI_REG(codec, ALI_SPDIF_CS)); if (flag & ALI_SPDIF_OUT_NON_PCM) wVal |= 0x0002; else wVal &= (~0x0002); outw(wVal, ALI_REG(codec, ALI_SPDIF_CS)); */ snd_ali_enable_special_channel(codec, ALI_SPDIF_OUT_CHANNEL); } static void snd_ali_disable_spdif_chnout(struct snd_ali *codec) { unsigned short wVal; wVal = inw(ALI_REG(codec, ALI_GLOBAL_CONTROL)); wVal |= ALI_SPDIF_OUT_SEL_PCM; outw(wVal, ALI_REG(codec, ALI_GLOBAL_CONTROL)); snd_ali_enable_special_channel(codec, ALI_SPDIF_OUT_CHANNEL); } static void snd_ali_disable_spdif_out(struct snd_ali *codec) { unsigned char bVal; bVal = inb(ALI_REG(codec, ALI_SCTRL)); outb(bVal & ~ALI_SPDIF_OUT_ENABLE, ALI_REG(codec, ALI_SCTRL)); snd_ali_disable_spdif_chnout(codec); } static void snd_ali_update_ptr(struct snd_ali *codec, int channel) { struct snd_ali_voice *pvoice; struct snd_ali_channel_control *pchregs; unsigned int old, mask; pchregs = &(codec->chregs); /* check if interrupt occurred for channel */ old = pchregs->data.aint; mask = 1U << (channel & 0x1f); if (!(old & mask)) return; pvoice = &codec->synth.voices[channel]; udelay(100); spin_lock(&codec->reg_lock); if (pvoice->pcm && pvoice->substream) { /* pcm interrupt */ if (pvoice->running) { dev_dbg(codec->card->dev, "update_ptr: cso=%4.4x cspf=%d.\n", inw(ALI_REG(codec, ALI_CSO_ALPHA_FMS + 2)), (inl(ALI_REG(codec, ALI_CSPF)) & mask) == mask); spin_unlock(&codec->reg_lock); snd_pcm_period_elapsed(pvoice->substream); spin_lock(&codec->reg_lock); } else { snd_ali_stop_voice(codec, channel); snd_ali_disable_voice_irq(codec, channel); } } else if (codec->synth.voices[channel].synth) { /* synth interrupt */ } else if (codec->synth.voices[channel].midi) { /* midi interrupt */ } else { /* unknown interrupt */ snd_ali_stop_voice(codec, channel); snd_ali_disable_voice_irq(codec, channel); } spin_unlock(&codec->reg_lock); outl(mask,ALI_REG(codec,pchregs->regs.aint)); pchregs->data.aint = old & (~mask); } static irqreturn_t snd_ali_card_interrupt(int irq, void *dev_id) { struct snd_ali *codec = dev_id; int channel; unsigned int audio_int; struct snd_ali_channel_control *pchregs; if (codec == NULL || !codec->hw_initialized) return IRQ_NONE; audio_int = inl(ALI_REG(codec, ALI_MISCINT)); if (!audio_int) return IRQ_NONE; pchregs = &(codec->chregs); if (audio_int & ADDRESS_IRQ) { /* get interrupt status for all channels */ pchregs->data.aint = inl(ALI_REG(codec, pchregs->regs.aint)); for (channel = 0; channel < ALI_CHANNELS; channel++) snd_ali_update_ptr(codec, channel); } outl((TARGET_REACHED | MIXER_OVERFLOW | MIXER_UNDERFLOW), ALI_REG(codec, ALI_MISCINT)); return IRQ_HANDLED; } static struct snd_ali_voice *snd_ali_alloc_voice(struct snd_ali * codec, int type, int rec, int channel) { struct snd_ali_voice *pvoice; int idx; dev_dbg(codec->card->dev, "alloc_voice: type=%d rec=%d\n", type, rec); spin_lock_irq(&codec->voice_alloc); if (type == SNDRV_ALI_VOICE_TYPE_PCM) { idx = channel > 0 ? snd_ali_alloc_pcm_channel(codec, channel) : snd_ali_find_free_channel(codec,rec); if (idx < 0) { dev_err(codec->card->dev, "ali_alloc_voice: err.\n"); spin_unlock_irq(&codec->voice_alloc); return NULL; } pvoice = &(codec->synth.voices[idx]); pvoice->codec = codec; pvoice->use = 1; pvoice->pcm = 1; pvoice->mode = rec; spin_unlock_irq(&codec->voice_alloc); return pvoice; } spin_unlock_irq(&codec->voice_alloc); return NULL; } static void snd_ali_free_voice(struct snd_ali * codec, struct snd_ali_voice *pvoice) { void (*private_free)(void *); void *private_data; dev_dbg(codec->card->dev, "free_voice: channel=%d\n", pvoice->number); if (!pvoice->use) return; snd_ali_clear_voices(codec, pvoice->number, pvoice->number); spin_lock_irq(&codec->voice_alloc); private_free = pvoice->private_free; private_data = pvoice->private_data; pvoice->private_free = NULL; pvoice->private_data = NULL; if (pvoice->pcm) snd_ali_free_channel_pcm(codec, pvoice->number); pvoice->use = pvoice->pcm = pvoice->synth = 0; pvoice->substream = NULL; spin_unlock_irq(&codec->voice_alloc); if (private_free) private_free(private_data); } static void snd_ali_clear_voices(struct snd_ali *codec, unsigned int v_min, unsigned int v_max) { unsigned int i; for (i = v_min; i <= v_max; i++) { snd_ali_stop_voice(codec, i); snd_ali_disable_voice_irq(codec, i); } } static void snd_ali_write_voice_regs(struct snd_ali *codec, unsigned int Channel, unsigned int LBA, unsigned int CSO, unsigned int ESO, unsigned int DELTA, unsigned int ALPHA_FMS, unsigned int GVSEL, unsigned int PAN, unsigned int VOL, unsigned int CTRL, unsigned int EC) { unsigned int ctlcmds[4]; outb((unsigned char)(Channel & 0x001f), ALI_REG(codec, ALI_GC_CIR)); ctlcmds[0] = (CSO << 16) | (ALPHA_FMS & 0x0000ffff); ctlcmds[1] = LBA; ctlcmds[2] = (ESO << 16) | (DELTA & 0x0ffff); ctlcmds[3] = (GVSEL << 31) | ((PAN & 0x0000007f) << 24) | ((VOL & 0x000000ff) << 16) | ((CTRL & 0x0000000f) << 12) | (EC & 0x00000fff); outb(Channel, ALI_REG(codec, ALI_GC_CIR)); outl(ctlcmds[0], ALI_REG(codec, ALI_CSO_ALPHA_FMS)); outl(ctlcmds[1], ALI_REG(codec, ALI_LBA)); outl(ctlcmds[2], ALI_REG(codec, ALI_ESO_DELTA)); outl(ctlcmds[3], ALI_REG(codec, ALI_GVSEL_PAN_VOC_CTRL_EC)); outl(0x30000000, ALI_REG(codec, ALI_EBUF1)); /* Still Mode */ outl(0x30000000, ALI_REG(codec, ALI_EBUF2)); /* Still Mode */ } static unsigned int snd_ali_convert_rate(unsigned int rate, int rec) { unsigned int delta; if (rate < 4000) rate = 4000; if (rate > 48000) rate = 48000; if (rec) { if (rate == 44100) delta = 0x116a; else if (rate == 8000) delta = 0x6000; else if (rate == 48000) delta = 0x1000; else delta = ((48000 << 12) / rate) & 0x0000ffff; } else { if (rate == 44100) delta = 0xeb3; else if (rate == 8000) delta = 0x2ab; else if (rate == 48000) delta = 0x1000; else delta = (((rate << 12) + rate) / 48000) & 0x0000ffff; } return delta; } static unsigned int snd_ali_control_mode(struct snd_pcm_substream *substream) { unsigned int CTRL; struct snd_pcm_runtime *runtime = substream->runtime; /* set ctrl mode CTRL default: 8-bit (unsigned) mono, loop mode enabled */ CTRL = 0x00000001; if (snd_pcm_format_width(runtime->format) == 16) CTRL |= 0x00000008; /* 16-bit data */ if (!snd_pcm_format_unsigned(runtime->format)) CTRL |= 0x00000002; /* signed data */ if (runtime->channels > 1) CTRL |= 0x00000004; /* stereo data */ return CTRL; } /* * PCM part */ static int snd_ali_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_substream *s; unsigned int what, whati; struct snd_ali_voice *pvoice, *evoice; unsigned int val; int do_start; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: do_start = 1; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: do_start = 0; break; default: return -EINVAL; } what = whati = 0; snd_pcm_group_for_each_entry(s, substream) { if ((struct snd_ali *) snd_pcm_substream_chip(s) == codec) { pvoice = s->runtime->private_data; evoice = pvoice->extra; what |= 1 << (pvoice->number & 0x1f); if (evoice == NULL) whati |= 1 << (pvoice->number & 0x1f); else { whati |= 1 << (evoice->number & 0x1f); what |= 1 << (evoice->number & 0x1f); } if (do_start) { pvoice->running = 1; if (evoice != NULL) evoice->running = 1; } else { pvoice->running = 0; if (evoice != NULL) evoice->running = 0; } snd_pcm_trigger_done(s, substream); } } spin_lock(&codec->reg_lock); if (!do_start) outl(what, ALI_REG(codec, ALI_STOP)); val = inl(ALI_REG(codec, ALI_AINTEN)); if (do_start) val |= whati; else val &= ~whati; outl(val, ALI_REG(codec, ALI_AINTEN)); if (do_start) outl(what, ALI_REG(codec, ALI_START)); dev_dbg(codec->card->dev, "trigger: what=%xh whati=%xh\n", what, whati); spin_unlock(&codec->reg_lock); return 0; } static int snd_ali_playback_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; struct snd_ali_voice *evoice = pvoice->extra; /* voice management */ if (params_buffer_size(hw_params) / 2 != params_period_size(hw_params)) { if (!evoice) { evoice = snd_ali_alloc_voice(codec, SNDRV_ALI_VOICE_TYPE_PCM, 0, -1); if (!evoice) return -ENOMEM; pvoice->extra = evoice; evoice->substream = substream; } } else { if (evoice) { snd_ali_free_voice(codec, evoice); pvoice->extra = evoice = NULL; } } return 0; } static int snd_ali_playback_hw_free(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; struct snd_ali_voice *evoice = pvoice ? pvoice->extra : NULL; if (evoice) { snd_ali_free_voice(codec, evoice); pvoice->extra = NULL; } return 0; } static int snd_ali_playback_prepare(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; struct snd_ali_voice *evoice = pvoice->extra; unsigned int LBA; unsigned int Delta; unsigned int ESO; unsigned int CTRL; unsigned int GVSEL; unsigned int PAN; unsigned int VOL; unsigned int EC; dev_dbg(codec->card->dev, "playback_prepare ...\n"); spin_lock_irq(&codec->reg_lock); /* set Delta (rate) value */ Delta = snd_ali_convert_rate(runtime->rate, 0); if (pvoice->number == ALI_SPDIF_IN_CHANNEL || pvoice->number == ALI_PCM_IN_CHANNEL) snd_ali_disable_special_channel(codec, pvoice->number); else if (codec->spdif_support && (inl(ALI_REG(codec, ALI_GLOBAL_CONTROL)) & ALI_SPDIF_OUT_CH_ENABLE) && pvoice->number == ALI_SPDIF_OUT_CHANNEL) { snd_ali_set_spdif_out_rate(codec, runtime->rate); Delta = 0x1000; } /* set Loop Back Address */ LBA = runtime->dma_addr; /* set interrupt count size */ pvoice->count = runtime->period_size; /* set target ESO for channel */ pvoice->eso = runtime->buffer_size; dev_dbg(codec->card->dev, "playback_prepare: eso=%xh count=%xh\n", pvoice->eso, pvoice->count); /* set ESO to capture first MIDLP interrupt */ ESO = pvoice->eso -1; /* set ctrl mode */ CTRL = snd_ali_control_mode(substream); GVSEL = 1; PAN = 0; VOL = 0; EC = 0; dev_dbg(codec->card->dev, "playback_prepare:\n"); dev_dbg(codec->card->dev, "ch=%d, Rate=%d Delta=%xh,GVSEL=%xh,PAN=%xh,CTRL=%xh\n", pvoice->number,runtime->rate,Delta,GVSEL,PAN,CTRL); snd_ali_write_voice_regs(codec, pvoice->number, LBA, 0, /* cso */ ESO, Delta, 0, /* alpha */ GVSEL, PAN, VOL, CTRL, EC); if (evoice) { evoice->count = pvoice->count; evoice->eso = pvoice->count << 1; ESO = evoice->eso - 1; snd_ali_write_voice_regs(codec, evoice->number, LBA, 0, /* cso */ ESO, Delta, 0, /* alpha */ GVSEL, 0x7f, 0x3ff, CTRL, EC); } spin_unlock_irq(&codec->reg_lock); return 0; } static int snd_ali_prepare(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; unsigned int LBA; unsigned int Delta; unsigned int ESO; unsigned int CTRL; unsigned int GVSEL; unsigned int PAN; unsigned int VOL; unsigned int EC; u8 bValue; spin_lock_irq(&codec->reg_lock); dev_dbg(codec->card->dev, "ali_prepare...\n"); snd_ali_enable_special_channel(codec,pvoice->number); Delta = (pvoice->number == ALI_MODEM_IN_CHANNEL || pvoice->number == ALI_MODEM_OUT_CHANNEL) ? 0x1000 : snd_ali_convert_rate(runtime->rate, pvoice->mode); /* Prepare capture intr channel */ if (pvoice->number == ALI_SPDIF_IN_CHANNEL) { unsigned int rate; spin_unlock_irq(&codec->reg_lock); if (codec->revision != ALI_5451_V02) return -1; rate = snd_ali_get_spdif_in_rate(codec); if (rate == 0) { dev_warn(codec->card->dev, "ali_capture_prepare: spdif rate detect err!\n"); rate = 48000; } spin_lock_irq(&codec->reg_lock); bValue = inb(ALI_REG(codec,ALI_SPDIF_CTRL)); if (bValue & 0x10) { outb(bValue,ALI_REG(codec,ALI_SPDIF_CTRL)); dev_warn(codec->card->dev, "clear SPDIF parity error flag.\n"); } if (rate != 48000) Delta = ((rate << 12) / runtime->rate) & 0x00ffff; } /* set target ESO for channel */ pvoice->eso = runtime->buffer_size; /* set interrupt count size */ pvoice->count = runtime->period_size; /* set Loop Back Address */ LBA = runtime->dma_addr; /* set ESO to capture first MIDLP interrupt */ ESO = pvoice->eso - 1; CTRL = snd_ali_control_mode(substream); GVSEL = 0; PAN = 0x00; VOL = 0x00; EC = 0; snd_ali_write_voice_regs( codec, pvoice->number, LBA, 0, /* cso */ ESO, Delta, 0, /* alpha */ GVSEL, PAN, VOL, CTRL, EC); spin_unlock_irq(&codec->reg_lock); return 0; } static snd_pcm_uframes_t snd_ali_playback_pointer(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; unsigned int cso; spin_lock(&codec->reg_lock); if (!pvoice->running) { spin_unlock(&codec->reg_lock); return 0; } outb(pvoice->number, ALI_REG(codec, ALI_GC_CIR)); cso = inw(ALI_REG(codec, ALI_CSO_ALPHA_FMS + 2)); spin_unlock(&codec->reg_lock); dev_dbg(codec->card->dev, "playback pointer returned cso=%xh.\n", cso); cso %= runtime->buffer_size; return cso; } static snd_pcm_uframes_t snd_ali_pointer(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice = runtime->private_data; unsigned int cso; spin_lock(&codec->reg_lock); if (!pvoice->running) { spin_unlock(&codec->reg_lock); return 0; } outb(pvoice->number, ALI_REG(codec, ALI_GC_CIR)); cso = inw(ALI_REG(codec, ALI_CSO_ALPHA_FMS + 2)); spin_unlock(&codec->reg_lock); cso %= runtime->buffer_size; return cso; } static const struct snd_pcm_hardware snd_ali_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_SYNC_START), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (256*1024), .period_bytes_min = 64, .period_bytes_max = (256*1024), .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; /* * Capture support device description */ static const struct snd_pcm_hardware snd_ali_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_SYNC_START), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE), .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, .rate_min = 4000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = 64, .period_bytes_max = (128*1024), .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static void snd_ali_pcm_free_substream(struct snd_pcm_runtime *runtime) { struct snd_ali_voice *pvoice = runtime->private_data; if (pvoice) snd_ali_free_voice(pvoice->codec, pvoice); } static int snd_ali_open(struct snd_pcm_substream *substream, int rec, int channel, const struct snd_pcm_hardware *phw) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_ali_voice *pvoice; pvoice = snd_ali_alloc_voice(codec, SNDRV_ALI_VOICE_TYPE_PCM, rec, channel); if (!pvoice) return -EAGAIN; pvoice->substream = substream; runtime->private_data = pvoice; runtime->private_free = snd_ali_pcm_free_substream; runtime->hw = *phw; snd_pcm_set_sync(substream); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 64*1024); return 0; } static int snd_ali_playback_open(struct snd_pcm_substream *substream) { return snd_ali_open(substream, 0, -1, &snd_ali_playback); } static int snd_ali_capture_open(struct snd_pcm_substream *substream) { return snd_ali_open(substream, 1, -1, &snd_ali_capture); } static int snd_ali_playback_close(struct snd_pcm_substream *substream) { return 0; } static int snd_ali_close(struct snd_pcm_substream *substream) { struct snd_ali *codec = snd_pcm_substream_chip(substream); struct snd_ali_voice *pvoice = substream->runtime->private_data; snd_ali_disable_special_channel(codec,pvoice->number); return 0; } static const struct snd_pcm_ops snd_ali_playback_ops = { .open = snd_ali_playback_open, .close = snd_ali_playback_close, .hw_params = snd_ali_playback_hw_params, .hw_free = snd_ali_playback_hw_free, .prepare = snd_ali_playback_prepare, .trigger = snd_ali_trigger, .pointer = snd_ali_playback_pointer, }; static const struct snd_pcm_ops snd_ali_capture_ops = { .open = snd_ali_capture_open, .close = snd_ali_close, .prepare = snd_ali_prepare, .trigger = snd_ali_trigger, .pointer = snd_ali_pointer, }; /* * Modem PCM */ static int snd_ali_modem_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct snd_ali *chip = snd_pcm_substream_chip(substream); unsigned int modem_num = chip->num_of_codecs - 1; snd_ac97_write(chip->ac97[modem_num], AC97_LINE1_RATE, params_rate(hw_params)); snd_ac97_write(chip->ac97[modem_num], AC97_LINE1_LEVEL, 0); return 0; } static const struct snd_pcm_hardware snd_ali_modem = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_SYNC_START), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = (SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000), .rate_min = 8000, .rate_max = 16000, .channels_min = 1, .channels_max = 1, .buffer_bytes_max = (256*1024), .period_bytes_min = 64, .period_bytes_max = (256*1024), .periods_min = 1, .periods_max = 1024, .fifo_size = 0, }; static int snd_ali_modem_open(struct snd_pcm_substream *substream, int rec, int channel) { static const unsigned int rates[] = {8000, 9600, 12000, 16000}; static const struct snd_pcm_hw_constraint_list hw_constraint_rates = { .count = ARRAY_SIZE(rates), .list = rates, .mask = 0, }; int err = snd_ali_open(substream, rec, channel, &snd_ali_modem); if (err) return err; return snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraint_rates); } static int snd_ali_modem_playback_open(struct snd_pcm_substream *substream) { return snd_ali_modem_open(substream, 0, ALI_MODEM_OUT_CHANNEL); } static int snd_ali_modem_capture_open(struct snd_pcm_substream *substream) { return snd_ali_modem_open(substream, 1, ALI_MODEM_IN_CHANNEL); } static const struct snd_pcm_ops snd_ali_modem_playback_ops = { .open = snd_ali_modem_playback_open, .close = snd_ali_close, .hw_params = snd_ali_modem_hw_params, .prepare = snd_ali_prepare, .trigger = snd_ali_trigger, .pointer = snd_ali_pointer, }; static const struct snd_pcm_ops snd_ali_modem_capture_ops = { .open = snd_ali_modem_capture_open, .close = snd_ali_close, .hw_params = snd_ali_modem_hw_params, .prepare = snd_ali_prepare, .trigger = snd_ali_trigger, .pointer = snd_ali_pointer, }; struct ali_pcm_description { char *name; unsigned int playback_num; unsigned int capture_num; const struct snd_pcm_ops *playback_ops; const struct snd_pcm_ops *capture_ops; unsigned short class; }; static void snd_ali_pcm_free(struct snd_pcm *pcm) { struct snd_ali *codec = pcm->private_data; codec->pcm[pcm->device] = NULL; } static int snd_ali_pcm(struct snd_ali *codec, int device, struct ali_pcm_description *desc) { struct snd_pcm *pcm; int err; err = snd_pcm_new(codec->card, desc->name, device, desc->playback_num, desc->capture_num, &pcm); if (err < 0) { dev_err(codec->card->dev, "snd_ali_pcm: err called snd_pcm_new.\n"); return err; } pcm->private_data = codec; pcm->private_free = snd_ali_pcm_free; if (desc->playback_ops) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, desc->playback_ops); if (desc->capture_ops) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, desc->capture_ops); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &codec->pci->dev, 64*1024, 128*1024); pcm->info_flags = 0; pcm->dev_class = desc->class; pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX; strcpy(pcm->name, desc->name); codec->pcm[0] = pcm; return 0; } static struct ali_pcm_description ali_pcms[] = { { .name = "ALI 5451", .playback_num = ALI_CHANNELS, .capture_num = 1, .playback_ops = &snd_ali_playback_ops, .capture_ops = &snd_ali_capture_ops }, { .name = "ALI 5451 modem", .playback_num = 1, .capture_num = 1, .playback_ops = &snd_ali_modem_playback_ops, .capture_ops = &snd_ali_modem_capture_ops, .class = SNDRV_PCM_CLASS_MODEM } }; static int snd_ali_build_pcms(struct snd_ali *codec) { int i, err; for (i = 0; i < codec->num_of_codecs && i < ARRAY_SIZE(ali_pcms); i++) { err = snd_ali_pcm(codec, i, &ali_pcms[i]); if (err < 0) return err; } return 0; } #define ALI5451_SPDIF(xname, xindex, value) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex,\ .info = snd_ali5451_spdif_info, .get = snd_ali5451_spdif_get, \ .put = snd_ali5451_spdif_put, .private_value = value} #define snd_ali5451_spdif_info snd_ctl_boolean_mono_info static int snd_ali5451_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ali *codec = kcontrol->private_data; unsigned int spdif_enable; spdif_enable = ucontrol->value.integer.value[0] ? 1 : 0; spin_lock_irq(&codec->reg_lock); switch (kcontrol->private_value) { case 0: spdif_enable = (codec->spdif_mask & 0x02) ? 1 : 0; break; case 1: spdif_enable = ((codec->spdif_mask & 0x02) && (codec->spdif_mask & 0x04)) ? 1 : 0; break; case 2: spdif_enable = (codec->spdif_mask & 0x01) ? 1 : 0; break; default: break; } ucontrol->value.integer.value[0] = spdif_enable; spin_unlock_irq(&codec->reg_lock); return 0; } static int snd_ali5451_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_ali *codec = kcontrol->private_data; unsigned int change = 0, spdif_enable = 0; spdif_enable = ucontrol->value.integer.value[0] ? 1 : 0; spin_lock_irq(&codec->reg_lock); switch (kcontrol->private_value) { case 0: change = (codec->spdif_mask & 0x02) ? 1 : 0; change = change ^ spdif_enable; if (change) { if (spdif_enable) { codec->spdif_mask |= 0x02; snd_ali_enable_spdif_out(codec); } else { codec->spdif_mask &= ~(0x02); codec->spdif_mask &= ~(0x04); snd_ali_disable_spdif_out(codec); } } break; case 1: change = (codec->spdif_mask & 0x04) ? 1 : 0; change = change ^ spdif_enable; if (change && (codec->spdif_mask & 0x02)) { if (spdif_enable) { codec->spdif_mask |= 0x04; snd_ali_enable_spdif_chnout(codec); } else { codec->spdif_mask &= ~(0x04); snd_ali_disable_spdif_chnout(codec); } } break; case 2: change = (codec->spdif_mask & 0x01) ? 1 : 0; change = change ^ spdif_enable; if (change) { if (spdif_enable) { codec->spdif_mask |= 0x01; snd_ali_enable_spdif_in(codec); } else { codec->spdif_mask &= ~(0x01); snd_ali_disable_spdif_in(codec); } } break; default: break; } spin_unlock_irq(&codec->reg_lock); return change; } static const struct snd_kcontrol_new snd_ali5451_mixer_spdif[] = { /* spdif aplayback switch */ /* FIXME: "IEC958 Playback Switch" may conflict with one on ac97_codec */ ALI5451_SPDIF(SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 0, 0), /* spdif out to spdif channel */ ALI5451_SPDIF(SNDRV_CTL_NAME_IEC958("Channel Output ",NONE,SWITCH), 0, 1), /* spdif in from spdif channel */ ALI5451_SPDIF(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, 2) }; static int snd_ali_mixer(struct snd_ali *codec) { struct snd_ac97_template ac97; unsigned int idx; int i, err; static const struct snd_ac97_bus_ops ops = { .write = snd_ali_codec_write, .read = snd_ali_codec_read, }; err = snd_ac97_bus(codec->card, 0, &ops, codec, &codec->ac97_bus); if (err < 0) return err; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = codec; for (i = 0; i < codec->num_of_codecs; i++) { ac97.num = i; err = snd_ac97_mixer(codec->ac97_bus, &ac97, &codec->ac97[i]); if (err < 0) { dev_err(codec->card->dev, "ali mixer %d creating error.\n", i); if (i == 0) return err; codec->num_of_codecs = 1; break; } } if (codec->spdif_support) { for (idx = 0; idx < ARRAY_SIZE(snd_ali5451_mixer_spdif); idx++) { err = snd_ctl_add(codec->card, snd_ctl_new1(&snd_ali5451_mixer_spdif[idx], codec)); if (err < 0) return err; } } return 0; } #ifdef CONFIG_PM_SLEEP static int ali_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_ali *chip = card->private_data; struct snd_ali_image *im; int i, j; im = chip->image; if (!im) return 0; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); for (i = 0; i < chip->num_of_codecs; i++) snd_ac97_suspend(chip->ac97[i]); spin_lock_irq(&chip->reg_lock); im->regs[ALI_MISCINT >> 2] = inl(ALI_REG(chip, ALI_MISCINT)); /* im->regs[ALI_START >> 2] = inl(ALI_REG(chip, ALI_START)); */ im->regs[ALI_STOP >> 2] = inl(ALI_REG(chip, ALI_STOP)); /* disable all IRQ bits */ outl(0, ALI_REG(chip, ALI_MISCINT)); for (i = 0; i < ALI_GLOBAL_REGS; i++) { if ((i*4 == ALI_MISCINT) || (i*4 == ALI_STOP)) continue; im->regs[i] = inl(ALI_REG(chip, i*4)); } for (i = 0; i < ALI_CHANNELS; i++) { outb(i, ALI_REG(chip, ALI_GC_CIR)); for (j = 0; j < ALI_CHANNEL_REGS; j++) im->channel_regs[i][j] = inl(ALI_REG(chip, j*4 + 0xe0)); } /* stop all HW channel */ outl(0xffffffff, ALI_REG(chip, ALI_STOP)); spin_unlock_irq(&chip->reg_lock); return 0; } static int ali_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_ali *chip = card->private_data; struct snd_ali_image *im; int i, j; im = chip->image; if (!im) return 0; spin_lock_irq(&chip->reg_lock); for (i = 0; i < ALI_CHANNELS; i++) { outb(i, ALI_REG(chip, ALI_GC_CIR)); for (j = 0; j < ALI_CHANNEL_REGS; j++) outl(im->channel_regs[i][j], ALI_REG(chip, j*4 + 0xe0)); } for (i = 0; i < ALI_GLOBAL_REGS; i++) { if ((i*4 == ALI_MISCINT) || (i*4 == ALI_STOP) || (i*4 == ALI_START)) continue; outl(im->regs[i], ALI_REG(chip, i*4)); } /* start HW channel */ outl(im->regs[ALI_START >> 2], ALI_REG(chip, ALI_START)); /* restore IRQ enable bits */ outl(im->regs[ALI_MISCINT >> 2], ALI_REG(chip, ALI_MISCINT)); spin_unlock_irq(&chip->reg_lock); for (i = 0 ; i < chip->num_of_codecs; i++) snd_ac97_resume(chip->ac97[i]); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static SIMPLE_DEV_PM_OPS(ali_pm, ali_suspend, ali_resume); #define ALI_PM_OPS &ali_pm #else #define ALI_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static void snd_ali_free(struct snd_card *card) { struct snd_ali *codec = card->private_data; if (codec->hw_initialized) snd_ali_disable_address_interrupt(codec); pci_dev_put(codec->pci_m1533); pci_dev_put(codec->pci_m7101); } static int snd_ali_chip_init(struct snd_ali *codec) { unsigned int legacy; unsigned char temp; struct pci_dev *pci_dev; dev_dbg(codec->card->dev, "chip initializing ...\n"); if (snd_ali_reset_5451(codec)) { dev_err(codec->card->dev, "ali_chip_init: reset 5451 error.\n"); return -1; } if (codec->revision == ALI_5451_V02) { pci_dev = codec->pci_m1533; pci_read_config_byte(pci_dev, 0x59, &temp); temp |= 0x80; pci_write_config_byte(pci_dev, 0x59, temp); pci_dev = codec->pci_m7101; pci_read_config_byte(pci_dev, 0xb8, &temp); temp |= 0x20; pci_write_config_byte(pci_dev, 0xB8, temp); } pci_read_config_dword(codec->pci, 0x44, &legacy); legacy &= 0xff00ff00; legacy |= 0x000800aa; pci_write_config_dword(codec->pci, 0x44, legacy); outl(0x80000001, ALI_REG(codec, ALI_GLOBAL_CONTROL)); outl(0x00000000, ALI_REG(codec, ALI_AINTEN)); outl(0xffffffff, ALI_REG(codec, ALI_AINT)); outl(0x00000000, ALI_REG(codec, ALI_VOLUME)); outb(0x10, ALI_REG(codec, ALI_MPUR2)); codec->ac97_ext_id = snd_ali_codec_peek(codec, 0, AC97_EXTENDED_ID); codec->ac97_ext_status = snd_ali_codec_peek(codec, 0, AC97_EXTENDED_STATUS); if (codec->spdif_support) { snd_ali_enable_spdif_out(codec); codec->spdif_mask = 0x00000002; } codec->num_of_codecs = 1; /* secondary codec - modem */ if (inl(ALI_REG(codec, ALI_SCTRL)) & ALI_SCTRL_CODEC2_READY) { codec->num_of_codecs++; outl(inl(ALI_REG(codec, ALI_SCTRL)) | (ALI_SCTRL_LINE_IN2 | ALI_SCTRL_GPIO_IN2 | ALI_SCTRL_LINE_OUT_EN), ALI_REG(codec, ALI_SCTRL)); } dev_dbg(codec->card->dev, "chip initialize succeed.\n"); return 0; } /* proc for register dump */ static void snd_ali_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buf) { struct snd_ali *codec = entry->private_data; int i; for (i = 0; i < 256 ; i+= 4) snd_iprintf(buf, "%02x: %08x\n", i, inl(ALI_REG(codec, i))); } static void snd_ali_proc_init(struct snd_ali *codec) { snd_card_ro_proc_new(codec->card, "ali5451", codec, snd_ali_proc_read); } static int snd_ali_resources(struct snd_ali *codec) { int err; dev_dbg(codec->card->dev, "resources allocation ...\n"); err = pci_request_regions(codec->pci, "ALI 5451"); if (err < 0) return err; codec->port = pci_resource_start(codec->pci, 0); if (devm_request_irq(&codec->pci->dev, codec->pci->irq, snd_ali_card_interrupt, IRQF_SHARED, KBUILD_MODNAME, codec)) { dev_err(codec->card->dev, "Unable to request irq.\n"); return -EBUSY; } codec->irq = codec->pci->irq; codec->card->sync_irq = codec->irq; dev_dbg(codec->card->dev, "resources allocated.\n"); return 0; } static int snd_ali_create(struct snd_card *card, struct pci_dev *pci, int pcm_streams, int spdif_support) { struct snd_ali *codec = card->private_data; int i, err; unsigned short cmdw; dev_dbg(card->dev, "creating ...\n"); /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; /* check, if we can restrict PCI DMA transfers to 31 bits */ if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31))) { dev_err(card->dev, "architecture does not support 31bit PCI busmaster DMA\n"); return -ENXIO; } spin_lock_init(&codec->reg_lock); spin_lock_init(&codec->voice_alloc); codec->card = card; codec->pci = pci; codec->irq = -1; codec->revision = pci->revision; codec->spdif_support = spdif_support; if (pcm_streams < 1) pcm_streams = 1; if (pcm_streams > 32) pcm_streams = 32; pci_set_master(pci); pci_read_config_word(pci, PCI_COMMAND, &cmdw); if ((cmdw & PCI_COMMAND_IO) != PCI_COMMAND_IO) { cmdw |= PCI_COMMAND_IO; pci_write_config_word(pci, PCI_COMMAND, cmdw); } if (snd_ali_resources(codec)) return -EBUSY; card->private_free = snd_ali_free; codec->synth.chmap = 0; codec->synth.chcnt = 0; codec->spdif_mask = 0; codec->synth.synthcount = 0; if (codec->revision == ALI_5451_V02) codec->chregs.regs.ac97read = ALI_AC97_WRITE; else codec->chregs.regs.ac97read = ALI_AC97_READ; codec->chregs.regs.ac97write = ALI_AC97_WRITE; codec->chregs.regs.start = ALI_START; codec->chregs.regs.stop = ALI_STOP; codec->chregs.regs.aint = ALI_AINT; codec->chregs.regs.ainten = ALI_AINTEN; codec->chregs.data.start = 0x00; codec->chregs.data.stop = 0x00; codec->chregs.data.aint = 0x00; codec->chregs.data.ainten = 0x00; /* M1533: southbridge */ codec->pci_m1533 = pci_get_device(0x10b9, 0x1533, NULL); if (!codec->pci_m1533) { dev_err(card->dev, "cannot find ALi 1533 chip.\n"); return -ENODEV; } /* M7101: power management */ codec->pci_m7101 = pci_get_device(0x10b9, 0x7101, NULL); if (!codec->pci_m7101 && codec->revision == ALI_5451_V02) { dev_err(card->dev, "cannot find ALi 7101 chip.\n"); return -ENODEV; } /* initialise synth voices*/ for (i = 0; i < ALI_CHANNELS; i++) codec->synth.voices[i].number = i; err = snd_ali_chip_init(codec); if (err < 0) { dev_err(card->dev, "ali create: chip init error.\n"); return err; } #ifdef CONFIG_PM_SLEEP codec->image = devm_kmalloc(&pci->dev, sizeof(*codec->image), GFP_KERNEL); if (!codec->image) dev_warn(card->dev, "can't allocate apm buffer\n"); #endif snd_ali_enable_address_interrupt(codec); codec->hw_initialized = 1; return 0; } static int __snd_ali_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { struct snd_card *card; struct snd_ali *codec; int err; dev_dbg(&pci->dev, "probe ...\n"); err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, sizeof(*codec), &card); if (err < 0) return err; codec = card->private_data; err = snd_ali_create(card, pci, pcm_channels, spdif); if (err < 0) return err; dev_dbg(&pci->dev, "mixer building ...\n"); err = snd_ali_mixer(codec); if (err < 0) return err; dev_dbg(&pci->dev, "pcm building ...\n"); err = snd_ali_build_pcms(codec); if (err < 0) return err; snd_ali_proc_init(codec); strcpy(card->driver, "ALI5451"); strcpy(card->shortname, "ALI 5451"); sprintf(card->longname, "%s at 0x%lx, irq %i", card->shortname, codec->port, codec->irq); dev_dbg(&pci->dev, "register card.\n"); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); return 0; } static int snd_ali_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_ali_probe(pci, pci_id)); } static struct pci_driver ali5451_driver = { .name = KBUILD_MODNAME, .id_table = snd_ali_ids, .probe = snd_ali_probe, .driver = { .pm = ALI_PM_OPS, }, }; module_pci_driver(ali5451_driver);
linux-master
sound/pci/ali5451/ali5451.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram VX222 V2/Mic soundcards * * VX222-specific low-level routines * * Copyright (c) 2002 by Takashi Iwai <[email protected]> */ #include <linux/delay.h> #include <linux/device.h> #include <linux/firmware.h> #include <linux/mutex.h> #include <linux/io.h> #include <sound/core.h> #include <sound/control.h> #include <sound/tlv.h> #include "vx222.h" static const int vx2_reg_offset[VX_REG_MAX] = { [VX_ICR] = 0x00, [VX_CVR] = 0x04, [VX_ISR] = 0x08, [VX_IVR] = 0x0c, [VX_RXH] = 0x14, [VX_RXM] = 0x18, [VX_RXL] = 0x1c, [VX_DMA] = 0x10, [VX_CDSP] = 0x20, [VX_CFG] = 0x24, [VX_RUER] = 0x28, [VX_DATA] = 0x2c, [VX_STATUS] = 0x30, [VX_LOFREQ] = 0x34, [VX_HIFREQ] = 0x38, [VX_CSUER] = 0x3c, [VX_SELMIC] = 0x40, [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030) }; static const int vx2_reg_index[VX_REG_MAX] = { [VX_ICR] = 1, [VX_CVR] = 1, [VX_ISR] = 1, [VX_IVR] = 1, [VX_RXH] = 1, [VX_RXM] = 1, [VX_RXL] = 1, [VX_DMA] = 1, [VX_CDSP] = 1, [VX_CFG] = 1, [VX_RUER] = 1, [VX_DATA] = 1, [VX_STATUS] = 1, [VX_LOFREQ] = 1, [VX_HIFREQ] = 1, [VX_CSUER] = 1, [VX_SELMIC] = 1, [VX_COMPOT] = 1, [VX_SCOMPR] = 1, [VX_GLIMIT] = 1, [VX_INTCSR] = 0, /* on the PLX */ [VX_CNTRL] = 0, /* on the PLX */ [VX_GPIOC] = 0, /* on the PLX */ }; static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) { struct snd_vx222 *chip = to_vx222(_chip); return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; } /** * vx2_inb - read a byte from the register * @chip: VX core instance * @offset: register enum */ static unsigned char vx2_inb(struct vx_core *chip, int offset) { return inb(vx2_reg_addr(chip, offset)); } /** * vx2_outb - write a byte on the register * @chip: VX core instance * @offset: the register offset * @val: the value to write */ static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) { outb(val, vx2_reg_addr(chip, offset)); /* dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset)); */ } /** * vx2_inl - read a 32bit word from the register * @chip: VX core instance * @offset: register enum */ static unsigned int vx2_inl(struct vx_core *chip, int offset) { return inl(vx2_reg_addr(chip, offset)); } /** * vx2_outl - write a 32bit word on the register * @chip: VX core instance * @offset: the register enum * @val: the value to write */ static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) { /* dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset)); */ outl(val, vx2_reg_addr(chip, offset)); } /* * redefine macros to call directly */ #undef vx_inb #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) #undef vx_outb #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) #undef vx_inl #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) #undef vx_outl #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) /* * vx_reset_dsp - reset the DSP */ #define XX_DSP_RESET_WAIT_TIME 2 /* ms */ static void vx2_reset_dsp(struct vx_core *_chip) { struct snd_vx222 *chip = to_vx222(_chip); /* set the reset dsp bit to 0 */ vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); mdelay(XX_DSP_RESET_WAIT_TIME); chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; /* set the reset dsp bit to 1 */ vx_outl(chip, CDSP, chip->regCDSP); } static int vx2_test_xilinx(struct vx_core *_chip) { struct snd_vx222 *chip = to_vx222(_chip); unsigned int data; dev_dbg(_chip->card->dev, "testing xilinx...\n"); /* This test uses several write/read sequences on TEST0 and TEST1 bits * to figure out whever or not the xilinx was correctly loaded */ /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); vx_inl(chip, ISR); data = vx_inl(chip, STATUS); if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) { dev_dbg(_chip->card->dev, "bad!\n"); return -ENODEV; } /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); vx_inl(chip, ISR); data = vx_inl(chip, STATUS); if (! (data & VX_STATUS_VAL_TEST0_MASK)) { dev_dbg(_chip->card->dev, "bad! #2\n"); return -ENODEV; } if (_chip->type == VX_TYPE_BOARD) { /* not implemented on VX_2_BOARDS */ /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); vx_inl(chip, ISR); data = vx_inl(chip, STATUS); if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) { dev_dbg(_chip->card->dev, "bad! #3\n"); return -ENODEV; } /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); vx_inl(chip, ISR); data = vx_inl(chip, STATUS); if (! (data & VX_STATUS_VAL_TEST1_MASK)) { dev_dbg(_chip->card->dev, "bad! #4\n"); return -ENODEV; } } dev_dbg(_chip->card->dev, "ok, xilinx fine.\n"); return 0; } /** * vx2_setup_pseudo_dma - set up the pseudo dma read/write mode. * @chip: VX core instance * @do_write: 0 = read, 1 = set up for DMA write */ static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write) { /* Interrupt mode and HREQ pin enabled for host transmit data transfers * (in case of the use of the pseudo-dma facility). */ vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); /* Reset the pseudo-dma register (in case of the use of the * pseudo-dma facility). */ vx_outl(chip, RESET_DMA, 0); } /* * vx_release_pseudo_dma - disable the pseudo-DMA mode */ static inline void vx2_release_pseudo_dma(struct vx_core *chip) { /* HREQ pin disabled. */ vx_outl(chip, ICR, 0); } /* pseudo-dma write */ static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, struct vx_pipe *pipe, int count) { unsigned long port = vx2_reg_addr(chip, VX_DMA); int offset = pipe->hw_ptr; u32 *addr = (u32 *)(runtime->dma_area + offset); if (snd_BUG_ON(count % 4)) return; vx2_setup_pseudo_dma(chip, 1); /* Transfer using pseudo-dma. */ if (offset + count >= pipe->buffer_bytes) { int length = pipe->buffer_bytes - offset; count -= length; length >>= 2; /* in 32bit words */ /* Transfer using pseudo-dma. */ for (; length > 0; length--) { outl(*addr, port); addr++; } addr = (u32 *)runtime->dma_area; pipe->hw_ptr = 0; } pipe->hw_ptr += count; count >>= 2; /* in 32bit words */ /* Transfer using pseudo-dma. */ for (; count > 0; count--) { outl(*addr, port); addr++; } vx2_release_pseudo_dma(chip); } /* pseudo dma read */ static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, struct vx_pipe *pipe, int count) { int offset = pipe->hw_ptr; u32 *addr = (u32 *)(runtime->dma_area + offset); unsigned long port = vx2_reg_addr(chip, VX_DMA); if (snd_BUG_ON(count % 4)) return; vx2_setup_pseudo_dma(chip, 0); /* Transfer using pseudo-dma. */ if (offset + count >= pipe->buffer_bytes) { int length = pipe->buffer_bytes - offset; count -= length; length >>= 2; /* in 32bit words */ /* Transfer using pseudo-dma. */ for (; length > 0; length--) *addr++ = inl(port); addr = (u32 *)runtime->dma_area; pipe->hw_ptr = 0; } pipe->hw_ptr += count; count >>= 2; /* in 32bit words */ /* Transfer using pseudo-dma. */ for (; count > 0; count--) *addr++ = inl(port); vx2_release_pseudo_dma(chip); } #define VX_XILINX_RESET_MASK 0x40000000 #define VX_USERBIT0_MASK 0x00000004 #define VX_USERBIT1_MASK 0x00000020 #define VX_CNTRL_REGISTER_VALUE 0x00172012 /* * transfer counts bits to PLX */ static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data) { unsigned int i; for (i = 0; i < counts; i++) { unsigned int val; /* set the clock bit to 0. */ val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; vx2_outl(chip, port, val); vx2_inl(chip, port); udelay(1); if (data & (1 << i)) val |= VX_USERBIT1_MASK; else val &= ~VX_USERBIT1_MASK; vx2_outl(chip, port, val); vx2_inl(chip, port); /* set the clock bit to 1. */ val |= VX_USERBIT0_MASK; vx2_outl(chip, port, val); vx2_inl(chip, port); udelay(1); } return 0; } /* * load the xilinx image */ static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx) { unsigned int i; unsigned int port; const unsigned char *image; /* XILINX reset (wait at least 1 millisecond between reset on and off). */ vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); vx_inl(chip, CNTRL); msleep(10); vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); vx_inl(chip, CNTRL); msleep(10); if (chip->type == VX_TYPE_BOARD) port = VX_CNTRL; else port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */ image = xilinx->data; for (i = 0; i < xilinx->size; i++, image++) { if (put_xilinx_data(chip, port, 8, *image) < 0) return -EINVAL; /* don't take too much time in this loop... */ cond_resched(); } put_xilinx_data(chip, port, 4, 0xff); /* end signature */ msleep(200); /* test after loading (is buggy with VX222) */ if (chip->type != VX_TYPE_BOARD) { /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */ i = vx_inl(chip, GPIOC); if (i & 0x0100) return 0; dev_err(chip->card->dev, "xilinx test failed after load, GPIOC=0x%x\n", i); return -EINVAL; } return 0; } /* * load the boot/dsp images */ static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp) { int err; switch (index) { case 1: /* xilinx image */ err = vx2_load_xilinx_binary(vx, dsp); if (err < 0) return err; err = vx2_test_xilinx(vx); if (err < 0) return err; return 0; case 2: /* DSP boot */ return snd_vx_dsp_boot(vx, dsp); case 3: /* DSP image */ return snd_vx_dsp_load(vx, dsp); default: snd_BUG(); return -EINVAL; } } /* * vx_test_and_ack - test and acknowledge interrupt * * called from irq hander, too * * spinlock held! */ static int vx2_test_and_ack(struct vx_core *chip) { /* not booted yet? */ if (! (chip->chip_status & VX_STAT_XILINX_LOADED)) return -ENXIO; if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK)) return -EIO; /* ok, interrupts generated, now ack it */ /* set ACQUIT bit up and down */ vx_outl(chip, STATUS, 0); /* useless read just to spend some time and maintain * the ACQUIT signal up for a while ( a bus cycle ) */ vx_inl(chip, STATUS); /* ack */ vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK); /* useless read just to spend some time and maintain * the ACQUIT signal up for a while ( a bus cycle ) */ vx_inl(chip, STATUS); /* clear */ vx_outl(chip, STATUS, 0); return 0; } /* * vx_validate_irq - enable/disable IRQ */ static void vx2_validate_irq(struct vx_core *_chip, int enable) { struct snd_vx222 *chip = to_vx222(_chip); /* Set the interrupt enable bit to 1 in CDSP register */ if (enable) { /* Set the PCI interrupt enable bit to 1.*/ vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK); chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK; } else { /* Set the PCI interrupt enable bit to 0. */ vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK); chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK; } vx_outl(chip, CDSP, chip->regCDSP); } /* * write an AKM codec data (24bit) */ static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data) { unsigned int i; vx_inl(chip, HIFREQ); /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ for (i = 0; i < 24; i++, data <<= 1) vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); /* Terminate access to codec registers */ vx_inl(chip, RUER); } #define AKM_CODEC_POWER_CONTROL_CMD 0xA007 #define AKM_CODEC_RESET_ON_CMD 0xA100 #define AKM_CODEC_RESET_OFF_CMD 0xA103 #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240 #define AKM_CODEC_MUTE_CMD 0xA38D #define AKM_CODEC_UNMUTE_CMD 0xA30D #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400 #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500 static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = { 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB) 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB) 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB) 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB) 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB) 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB) 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB) 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB) 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB) 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB) 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB) 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB) 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB) 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB) 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB) 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB) 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB) 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB) 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB) 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB) 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB) 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB) 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB) 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB) 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB) 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB) 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB) 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB) 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB) 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB) 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB) 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB) 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB) 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB) 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB) 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB) 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB) 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB) 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB) 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB) 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB) 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB) 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB) 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB) 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB) 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB) 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB) 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB) 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB) 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB) 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB) 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB) 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB) 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB) 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB) 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB) 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB) 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB) 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB) 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB) 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB) 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB) 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB) 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB) 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB) 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB) 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB) 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB) 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB) 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB) 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB) 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB) 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB) 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB) 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB) 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB) 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB) 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB) 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB) 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB) 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB) 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB) 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB) 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB) 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB) 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB) 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB) 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB) 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB) 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB) 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB) 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB) 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB) 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB) 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB) 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB) 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB) 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB) 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB) 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB) 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB) 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB) 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB) 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB) 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB) 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB) 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB) 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB) 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB) 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB) 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB) 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB) 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB) 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB) 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB) 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB) 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB) 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB) 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB) 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB) 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB) 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB) 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB) 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB) 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB) 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB) 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB) 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB) 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB) 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB) 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB) 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB) 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB) 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB) 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB) 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB) 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB) 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB) 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB) 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB) 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB) 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB) 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB) 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB) 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB) 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB) 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB) 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini) /* * pseudo-codec write entry */ static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) { unsigned int val; if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD); return; } /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need a look up table, as there is no linear matching between the driver codec values and the real dBu value */ if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut))) return; switch (reg) { case XX_CODEC_LEVEL_LEFT_REGISTER: val = AKM_CODEC_LEFT_LEVEL_CMD; break; case XX_CODEC_LEVEL_RIGHT_REGISTER: val = AKM_CODEC_RIGHT_LEVEL_CMD; break; default: snd_BUG(); return; } val |= vx2_akm_gains_lut[data]; vx2_write_codec_reg(chip, val); } /* * write codec bit for old VX222 board */ static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data) { int i; /* activate access to codec registers */ vx_inl(chip, HIFREQ); for (i = 0; i < 24; i++, data <<= 1) vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); /* Terminate access to codec registers */ vx_inl(chip, RUER); } /* * reset codec bit */ static void vx2_reset_codec(struct vx_core *_chip) { struct snd_vx222 *chip = to_vx222(_chip); /* Set the reset CODEC bit to 0. */ vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); vx_inl(chip, CDSP); msleep(10); /* Set the reset CODEC bit to 1. */ chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; vx_outl(chip, CDSP, chip->regCDSP); vx_inl(chip, CDSP); if (_chip->type == VX_TYPE_BOARD) { msleep(1); return; } msleep(5); /* additionnel wait time for AKM's */ vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */ vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */ vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */ if (_chip->type == VX_TYPE_MIC) { /* set up the micro input selector */ chip->regSELMIC = MICRO_SELECT_INPUT_NORM | MICRO_SELECT_PREAMPLI_G_0 | MICRO_SELECT_NOISE_T_52DB; /* reset phantom power supply */ chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM; vx_outl(_chip, SELMIC, chip->regSELMIC); } } /* * change the audio source */ static void vx2_change_audio_source(struct vx_core *_chip, int src) { struct snd_vx222 *chip = to_vx222(_chip); switch (src) { case VX_AUDIO_SRC_DIGITAL: chip->regCFG |= VX_CFG_DATAIN_SEL_MASK; break; default: chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK; break; } vx_outl(chip, CFG, chip->regCFG); } /* * set the clock source */ static void vx2_set_clock_source(struct vx_core *_chip, int source) { struct snd_vx222 *chip = to_vx222(_chip); if (source == INTERNAL_QUARTZ) chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK; else chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK; vx_outl(chip, CFG, chip->regCFG); } /* * reset the board */ static void vx2_reset_board(struct vx_core *_chip, int cold_reset) { struct snd_vx222 *chip = to_vx222(_chip); /* initialize the register values */ chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ; chip->regCFG = 0; } /* * input level controls for VX222 Mic */ /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318), * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli) * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset ! */ #define V2_MICRO_LEVEL_RANGE (318 - 255) static void vx2_set_input_level(struct snd_vx222 *chip) { int i, miclevel, preamp; unsigned int data; miclevel = chip->mic_level; miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */ preamp = 0; while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */ preamp++; /* raise pre ampli + 18dB */ miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */ } if (snd_BUG_ON(preamp >= 4)) return; /* set pre-amp level */ chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK; chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK; vx_outl(chip, SELMIC, chip->regSELMIC); data = (unsigned int)miclevel << 16 | (unsigned int)chip->input_level[1] << 8 | (unsigned int)chip->input_level[0]; vx_inl(chip, DATA); /* Activate input level programming */ /* We have to send 32 bits (4 x 8 bits) */ for (i = 0; i < 32; i++, data <<= 1) vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0)); vx_inl(chip, RUER); /* Terminate input level programming */ } #define MIC_LEVEL_MAX 0xff static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0); /* * controls API for input levels */ /* input levels */ static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = MIC_LEVEL_MAX; return 0; } static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct vx_core *_chip = snd_kcontrol_chip(kcontrol); struct snd_vx222 *chip = to_vx222(_chip); mutex_lock(&_chip->mixer_mutex); ucontrol->value.integer.value[0] = chip->input_level[0]; ucontrol->value.integer.value[1] = chip->input_level[1]; mutex_unlock(&_chip->mixer_mutex); return 0; } static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct vx_core *_chip = snd_kcontrol_chip(kcontrol); struct snd_vx222 *chip = to_vx222(_chip); if (ucontrol->value.integer.value[0] < 0 || ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) return -EINVAL; if (ucontrol->value.integer.value[1] < 0 || ucontrol->value.integer.value[1] > MIC_LEVEL_MAX) return -EINVAL; mutex_lock(&_chip->mixer_mutex); if (chip->input_level[0] != ucontrol->value.integer.value[0] || chip->input_level[1] != ucontrol->value.integer.value[1]) { chip->input_level[0] = ucontrol->value.integer.value[0]; chip->input_level[1] = ucontrol->value.integer.value[1]; vx2_set_input_level(chip); mutex_unlock(&_chip->mixer_mutex); return 1; } mutex_unlock(&_chip->mixer_mutex); return 0; } /* mic level */ static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = MIC_LEVEL_MAX; return 0; } static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct vx_core *_chip = snd_kcontrol_chip(kcontrol); struct snd_vx222 *chip = to_vx222(_chip); ucontrol->value.integer.value[0] = chip->mic_level; return 0; } static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct vx_core *_chip = snd_kcontrol_chip(kcontrol); struct snd_vx222 *chip = to_vx222(_chip); if (ucontrol->value.integer.value[0] < 0 || ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) return -EINVAL; mutex_lock(&_chip->mixer_mutex); if (chip->mic_level != ucontrol->value.integer.value[0]) { chip->mic_level = ucontrol->value.integer.value[0]; vx2_set_input_level(chip); mutex_unlock(&_chip->mixer_mutex); return 1; } mutex_unlock(&_chip->mixer_mutex); return 0; } static const struct snd_kcontrol_new vx_control_input_level = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Capture Volume", .info = vx_input_level_info, .get = vx_input_level_get, .put = vx_input_level_put, .tlv = { .p = db_scale_mic }, }; static const struct snd_kcontrol_new vx_control_mic_level = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Mic Capture Volume", .info = vx_mic_level_info, .get = vx_mic_level_get, .put = vx_mic_level_put, .tlv = { .p = db_scale_mic }, }; /* * FIXME: compressor/limiter implementation is missing yet... */ static int vx2_add_mic_controls(struct vx_core *_chip) { struct snd_vx222 *chip = to_vx222(_chip); int err; if (_chip->type != VX_TYPE_MIC) return 0; /* mute input levels */ chip->input_level[0] = chip->input_level[1] = 0; chip->mic_level = 0; vx2_set_input_level(chip); /* controls */ err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip)); if (err < 0) return err; err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip)); if (err < 0) return err; return 0; } /* * callbacks */ const struct snd_vx_ops vx222_ops = { .in8 = vx2_inb, .in32 = vx2_inl, .out8 = vx2_outb, .out32 = vx2_outl, .test_and_ack = vx2_test_and_ack, .validate_irq = vx2_validate_irq, .akm_write = vx2_write_akm, .reset_codec = vx2_reset_codec, .change_audio_source = vx2_change_audio_source, .set_clock_source = vx2_set_clock_source, .load_dsp = vx2_load_dsp, .reset_dsp = vx2_reset_dsp, .reset_board = vx2_reset_board, .dma_write = vx2_dma_write, .dma_read = vx2_dma_read, .add_controls = vx2_add_mic_controls, }; /* for old VX222 board */ const struct snd_vx_ops vx222_old_ops = { .in8 = vx2_inb, .in32 = vx2_inl, .out8 = vx2_outb, .out32 = vx2_outl, .test_and_ack = vx2_test_and_ack, .validate_irq = vx2_validate_irq, .write_codec = vx2_old_write_codec_bit, .reset_codec = vx2_reset_codec, .change_audio_source = vx2_change_audio_source, .set_clock_source = vx2_set_clock_source, .load_dsp = vx2_load_dsp, .reset_dsp = vx2_reset_dsp, .reset_board = vx2_reset_board, .dma_write = vx2_dma_write, .dma_read = vx2_dma_read, };
linux-master
sound/pci/vx222/vx222_ops.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram VX222 V2/Mic PCI soundcards * * Copyright (c) 2002 by Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/initval.h> #include <sound/tlv.h> #include "vx222.h" #define CARD_NAME "VX222" MODULE_AUTHOR("Takashi Iwai <[email protected]>"); MODULE_DESCRIPTION("Digigram VX222 V2/Mic"); MODULE_LICENSE("GPL"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ static bool mic[SNDRV_CARDS]; /* microphone */ static int ibl[SNDRV_CARDS]; /* microphone */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Digigram " CARD_NAME " soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Digigram " CARD_NAME " soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Digigram " CARD_NAME " soundcard."); module_param_array(mic, bool, NULL, 0444); MODULE_PARM_DESC(mic, "Enable Microphone."); module_param_array(ibl, int, NULL, 0444); MODULE_PARM_DESC(ibl, "Capture IBL size."); /* */ enum { VX_PCI_VX222_OLD, VX_PCI_VX222_NEW }; static const struct pci_device_id snd_vx222_ids[] = { { 0x10b5, 0x9050, 0x1369, PCI_ANY_ID, 0, 0, VX_PCI_VX222_OLD, }, /* PLX */ { 0x10b5, 0x9030, 0x1369, PCI_ANY_ID, 0, 0, VX_PCI_VX222_NEW, }, /* PLX */ { 0, } }; MODULE_DEVICE_TABLE(pci, snd_vx222_ids); /* */ static const DECLARE_TLV_DB_SCALE(db_scale_old_vol, -11350, 50, 0); static const DECLARE_TLV_DB_SCALE(db_scale_akm, -7350, 50, 0); static const struct snd_vx_hardware vx222_old_hw = { .name = "VX222/Old", .type = VX_TYPE_BOARD, /* hw specs */ .num_codecs = 1, .num_ins = 1, .num_outs = 1, .output_level_max = VX_ANALOG_OUT_LEVEL_MAX, .output_level_db_scale = db_scale_old_vol, }; static const struct snd_vx_hardware vx222_v2_hw = { .name = "VX222/v2", .type = VX_TYPE_V2, /* hw specs */ .num_codecs = 1, .num_ins = 1, .num_outs = 1, .output_level_max = VX2_AKM_LEVEL_MAX, .output_level_db_scale = db_scale_akm, }; static const struct snd_vx_hardware vx222_mic_hw = { .name = "VX222/Mic", .type = VX_TYPE_MIC, /* hw specs */ .num_codecs = 1, .num_ins = 1, .num_outs = 1, .output_level_max = VX2_AKM_LEVEL_MAX, .output_level_db_scale = db_scale_akm, }; /* */ static int snd_vx222_create(struct snd_card *card, struct pci_dev *pci, const struct snd_vx_hardware *hw, struct snd_vx222 **rchip) { struct vx_core *chip; struct snd_vx222 *vx; int i, err; const struct snd_vx_ops *vx_ops; /* enable PCI device */ err = pcim_enable_device(pci); if (err < 0) return err; pci_set_master(pci); vx_ops = hw->type == VX_TYPE_BOARD ? &vx222_old_ops : &vx222_ops; chip = snd_vx_create(card, hw, vx_ops, sizeof(struct snd_vx222) - sizeof(struct vx_core)); if (!chip) return -ENOMEM; vx = to_vx222(chip); vx->pci = pci; err = pci_request_regions(pci, CARD_NAME); if (err < 0) return err; for (i = 0; i < 2; i++) vx->port[i] = pci_resource_start(pci, i + 1); if (devm_request_threaded_irq(&pci->dev, pci->irq, snd_vx_irq_handler, snd_vx_threaded_irq_handler, IRQF_SHARED, KBUILD_MODNAME, chip)) { dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; *rchip = vx; return 0; } static int snd_vx222_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; const struct snd_vx_hardware *hw; struct snd_vx222 *vx; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 0, &card); if (err < 0) return err; switch ((int)pci_id->driver_data) { case VX_PCI_VX222_OLD: hw = &vx222_old_hw; break; case VX_PCI_VX222_NEW: default: if (mic[dev]) hw = &vx222_mic_hw; else hw = &vx222_v2_hw; break; } err = snd_vx222_create(card, pci, hw, &vx); if (err < 0) return err; card->private_data = vx; vx->core.ibl.size = ibl[dev]; sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %i", card->shortname, vx->port[0], vx->port[1], vx->core.irq); dev_dbg(card->dev, "%s at 0x%lx & 0x%lx, irq %i\n", card->shortname, vx->port[0], vx->port[1], vx->core.irq); #ifdef SND_VX_FW_LOADER vx->core.dev = &pci->dev; #endif err = snd_vx_setup_firmware(&vx->core); if (err < 0) return err; err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } #ifdef CONFIG_PM_SLEEP static int snd_vx222_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_vx222 *vx = card->private_data; return snd_vx_suspend(&vx->core); } static int snd_vx222_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_vx222 *vx = card->private_data; return snd_vx_resume(&vx->core); } static SIMPLE_DEV_PM_OPS(snd_vx222_pm, snd_vx222_suspend, snd_vx222_resume); #define SND_VX222_PM_OPS &snd_vx222_pm #else #define SND_VX222_PM_OPS NULL #endif static struct pci_driver vx222_driver = { .name = KBUILD_MODNAME, .id_table = snd_vx222_ids, .probe = snd_vx222_probe, .driver = { .pm = SND_VX222_PM_OPS, }, }; module_pci_driver(vx222_driver);
linux-master
sound/pci/vx222/vx222.c
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * au88x0_a3ddata.c * * Wed Nov 19 21:11:32 2003 * Copyright 2003 mjander * [email protected] ****************************************************************************/ /* */ /* Constant initializer values. */ static const a3d_Hrtf_t A3dHrirZeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static __maybe_unused const a3d_Hrtf_t A3dHrirImpulse = { 0x7fff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static __maybe_unused const a3d_Hrtf_t A3dHrirOnes = { 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff }; static __maybe_unused const a3d_Hrtf_t A3dHrirSatTest = { 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x7fff, 0x0000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static __maybe_unused const a3d_Hrtf_t A3dHrirDImpulse = { 0, 0x7fff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static const a3d_ItdDline_t A3dItdDlineZeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static short const GainTCDefault = 0x300; static short const ItdTCDefault = 0x0C8; static short const HrtfTCDefault = 0x147; static short const CoefTCDefault = 0x300;
linux-master
sound/pci/au88x0/au88x0_a3ddata.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <[email protected]> * Routines for control of MPU-401 in UART mode * * Modified for the Aureal Vortex based Soundcards * by Manuel Jander ([email protected]). */ #include <linux/time.h> #include <linux/init.h> #include <sound/core.h> #include <sound/mpu401.h> #include "au88x0.h" /* Check for mpu401 mmio support. */ /* MPU401 legacy support is only provided as a emergency fallback * * for older versions of ALSA. Its usage is strongly discouraged. */ #ifndef MPU401_HW_AUREAL #define VORTEX_MPU401_LEGACY #endif /* Vortex MPU401 defines. */ #define MIDI_CLOCK_DIV 0x61 /* Standart MPU401 defines. */ #define MPU401_RESET 0xff #define MPU401_ENTER_UART 0x3f #define MPU401_ACK 0xfe static int snd_vortex_midi(vortex_t *vortex) { struct snd_rawmidi *rmidi; int temp, mode; struct snd_mpu401 *mpu; unsigned long port; #ifdef VORTEX_MPU401_LEGACY /* EnableHardCodedMPU401Port() */ /* Enable Legacy MIDI Interface port. */ port = (0x03 << 5); /* FIXME: static address. 0x330 */ temp = (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | CTRL_MIDI_EN | port; hwwrite(vortex->mmio, VORTEX_CTRL, temp); #else /* Disable Legacy MIDI Interface port. */ temp = (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & ~CTRL_MIDI_EN; hwwrite(vortex->mmio, VORTEX_CTRL, temp); #endif /* Mpu401UartInit() */ mode = 1; temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; temp |= (MIDI_CLOCK_DIV << 8) | ((mode >> 24) & 0xff) << 4; hwwrite(vortex->mmio, VORTEX_CTRL2, temp); hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); /* Check if anything is OK. */ temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); if (temp != MPU401_ACK /*0xfe */ ) { dev_err(vortex->card->dev, "midi port doesn't acknowledge!\n"); return -ENODEV; } /* Enable MPU401 interrupts. */ hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) | IRQ_MIDI); /* Create MPU401 instance. */ #ifdef VORTEX_MPU401_LEGACY temp = snd_mpu401_uart_new(vortex->card, 0, MPU401_HW_MPU401, 0x330, MPU401_INFO_IRQ_HOOK, -1, &rmidi); if (temp) { hwwrite(vortex->mmio, VORTEX_CTRL, (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & ~CTRL_MIDI_EN); return temp; } #else port = (unsigned long)(vortex->mmio + VORTEX_MIDI_DATA); temp = snd_mpu401_uart_new(vortex->card, 0, MPU401_HW_AUREAL, port, MPU401_INFO_INTEGRATED | MPU401_INFO_MMIO | MPU401_INFO_IRQ_HOOK, -1, &rmidi); if (temp) { hwwrite(vortex->mmio, VORTEX_CTRL, (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & ~CTRL_MIDI_EN); return temp; } mpu = rmidi->private_data; mpu->cport = (unsigned long)(vortex->mmio + VORTEX_MIDI_CMD); #endif /* Overwrite MIDI name */ snprintf(rmidi->name, sizeof(rmidi->name), "%s MIDI %d", CARD_NAME_SHORT , vortex->card->number); vortex->rmidi = rmidi; return 0; }
linux-master
sound/pci/au88x0/au88x0_mpu401.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Manuel Jander. * * Based on the work of: * Vojtech Pavlik * Raymond Ingles * * Should you need to contact me, the author, you can do so either by * e-mail - mail your message to <[email protected]>, or by paper mail: * Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic * * Based 90% on Vojtech Pavlik pcigame driver. * Merged and modified by Manuel Jander, for the OpenVortex * driver. (email: [email protected]). */ #include <linux/time.h> #include <linux/delay.h> #include <linux/init.h> #include <sound/core.h> #include "au88x0.h" #include <linux/gameport.h> #include <linux/export.h> #if IS_REACHABLE(CONFIG_GAMEPORT) #define VORTEX_GAME_DWAIT 20 /* 20 ms */ static unsigned char vortex_game_read(struct gameport *gameport) { vortex_t *vortex = gameport_get_port_data(gameport); return hwread(vortex->mmio, VORTEX_GAME_LEGACY); } static void vortex_game_trigger(struct gameport *gameport) { vortex_t *vortex = gameport_get_port_data(gameport); hwwrite(vortex->mmio, VORTEX_GAME_LEGACY, 0xff); } static int vortex_game_cooked_read(struct gameport *gameport, int *axes, int *buttons) { vortex_t *vortex = gameport_get_port_data(gameport); int i; *buttons = (~hwread(vortex->mmio, VORTEX_GAME_LEGACY) >> 4) & 0xf; for (i = 0; i < 4; i++) { axes[i] = hwread(vortex->mmio, VORTEX_GAME_AXIS + (i * AXIS_SIZE)); if (axes[i] == AXIS_RANGE) axes[i] = -1; } return 0; } static int vortex_game_open(struct gameport *gameport, int mode) { vortex_t *vortex = gameport_get_port_data(gameport); switch (mode) { case GAMEPORT_MODE_COOKED: hwwrite(vortex->mmio, VORTEX_CTRL2, hwread(vortex->mmio, VORTEX_CTRL2) | CTRL2_GAME_ADCMODE); msleep(VORTEX_GAME_DWAIT); return 0; case GAMEPORT_MODE_RAW: hwwrite(vortex->mmio, VORTEX_CTRL2, hwread(vortex->mmio, VORTEX_CTRL2) & ~CTRL2_GAME_ADCMODE); return 0; default: return -1; } return 0; } static int vortex_gameport_register(vortex_t *vortex) { struct gameport *gp; vortex->gameport = gp = gameport_allocate_port(); if (!gp) { dev_err(vortex->card->dev, "cannot allocate memory for gameport\n"); return -ENOMEM; } gameport_set_name(gp, "AU88x0 Gameport"); gameport_set_phys(gp, "pci%s/gameport0", pci_name(vortex->pci_dev)); gameport_set_dev_parent(gp, &vortex->pci_dev->dev); gp->read = vortex_game_read; gp->trigger = vortex_game_trigger; gp->cooked_read = vortex_game_cooked_read; gp->open = vortex_game_open; gameport_set_port_data(gp, vortex); gp->fuzz = 64; gameport_register_port(gp); return 0; } static void vortex_gameport_unregister(vortex_t * vortex) { if (vortex->gameport) { gameport_unregister_port(vortex->gameport); vortex->gameport = NULL; } } #else static inline int vortex_gameport_register(vortex_t * vortex) { return -ENOSYS; } static inline void vortex_gameport_unregister(vortex_t * vortex) { } #endif
linux-master
sound/pci/au88x0/au88x0_game.c
// SPDX-License-Identifier: GPL-2.0 #include "au8810.h" #include "au88x0.h" static const struct pci_device_id snd_vortex_ids[] = { {PCI_VDEVICE(AUREAL, PCI_DEVICE_ID_AUREAL_ADVANTAGE), 1,}, {0,} }; #include "au88x0_core.c" #include "au88x0_pcm.c" #include "au88x0_mixer.c" #include "au88x0_mpu401.c" #include "au88x0_game.c" #include "au88x0_eq.c" #include "au88x0_a3d.c" #include "au88x0_xtalk.c" #include "au88x0.c"
linux-master
sound/pci/au88x0/au8810.c
// SPDX-License-Identifier: GPL-2.0-or-later /* */ /* * Someday its supposed to make use of the WT DMA engine * for a Wavetable synthesizer. */ #include "au88x0.h" #include "au88x0_wt.h" static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en); static void vortex_connection_adb_mixin(vortex_t * vortex, int en, unsigned char channel, unsigned char source, unsigned char mixin); static void vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin, unsigned char mix, int a); static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j); static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt, u32 val); /* WT */ /* Put 2 WT channels together for one stereo interlaced channel. */ static void vortex_wt_setstereo(vortex_t * vortex, u32 wt, u32 stereo) { int temp; //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); temp = hwread(vortex->mmio, WT_STEREO(wt)); temp = (temp & 0xfe) | (stereo & 1); //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); hwwrite(vortex->mmio, WT_STEREO(wt), temp); } /* Join to mixdown route. */ static void vortex_wt_setdsout(vortex_t * vortex, u32 wt, int en) { int temp; /* There is one DSREG register for each bank (32 voices each). */ temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); if (en) temp |= (1 << (wt & 0x1f)); else temp &= ~(1 << (wt & 0x1f)); hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); } /* Setup WT route. */ static int vortex_wt_allocroute(vortex_t * vortex, int wt, int nr_ch) { wt_voice_t *voice = &(vortex->wt_voice[wt]); int temp; //FIXME: WT audio routing. if (nr_ch) { vortex_fifo_wtinitialize(vortex, wt, 1); vortex_fifo_setwtvalid(vortex, wt, 1); vortex_wt_setstereo(vortex, wt, nr_ch - 1); } else vortex_fifo_setwtvalid(vortex, wt, 0); /* Set mixdown mode. */ vortex_wt_setdsout(vortex, wt, 1); /* Set other parameter registers. */ hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff); #ifdef CHIP_AU8830 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff); #endif hwwrite(vortex->mmio, WT_PARM(wt, 0), 0); hwwrite(vortex->mmio, WT_PARM(wt, 1), 0); hwwrite(vortex->mmio, WT_PARM(wt, 2), 0); temp = hwread(vortex->mmio, WT_PARM(wt, 3)); dev_dbg(vortex->card->dev, "WT PARM3: %x\n", temp); //hwwrite(vortex->mmio, WT_PARM(wt, 3), temp); hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0); hwwrite(vortex->mmio, WT_DELAY(wt, 1), 0); hwwrite(vortex->mmio, WT_DELAY(wt, 2), 0); hwwrite(vortex->mmio, WT_DELAY(wt, 3), 0); dev_dbg(vortex->card->dev, "WT GMODE: %x\n", hwread(vortex->mmio, WT_GMODE(wt))); hwwrite(vortex->mmio, WT_PARM(wt, 2), 0xffffffff); hwwrite(vortex->mmio, WT_PARM(wt, 3), 0xcff1c810); voice->parm0 = voice->parm1 = 0xcfb23e2f; hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0); hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1); dev_dbg(vortex->card->dev, "WT GMODE 2 : %x\n", hwread(vortex->mmio, WT_GMODE(wt))); return 0; } static void vortex_wt_connect(vortex_t * vortex, int en) { int i, ii, mix; #define NR_WTROUTES 6 #ifdef CHIP_AU8830 #define NR_WTBLOCKS 2 #else #define NR_WTBLOCKS 1 #endif for (i = 0; i < NR_WTBLOCKS; i++) { for (ii = 0; ii < NR_WTROUTES; ii++) { mix = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); vortex->mixwt[(i * NR_WTROUTES) + ii] = mix; vortex_route(vortex, en, 0x11, ADB_WTOUT(i, ii + 0x20), ADB_MIXIN(mix)); vortex_connection_mixin_mix(vortex, en, mix, vortex->mixplayb[ii % 2], 0); if (VORTEX_IS_QUAD(vortex)) vortex_connection_mixin_mix(vortex, en, mix, vortex->mixplayb[2 + (ii % 2)], 0); } } for (i = 0; i < NR_WT; i++) { hwwrite(vortex->mmio, WT_RUN(i), 1); } } /* Read WT Register */ #if 0 static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt) { //int eax, esi; if (reg == 4) { return hwread(vortex->mmio, WT_PARM(wt, 3)); } if (reg == 7) { return hwread(vortex->mmio, WT_GMODE(wt)); } return 0; } /* WT hardware abstraction layer generic register interface. */ static int vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt, u16 val) { /* int eax, edx; if (wt >= NR_WT) // 0x40 -> NR_WT return 0; if ((reg - 0x20) > 0) { if ((reg - 0x21) != 0) return 0; eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2 } else { eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3 } hwwrite(vortex->mmio, eax, c); */ return 1; } /*public: static void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */ #endif static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt, u32 val) { int ecx; if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) { if (wt >= (NR_WT / NR_WT_PB)) { dev_warn(vortex->card->dev, "WT SetReg: bank out of range. reg=0x%x, wt=%d\n", reg, wt); return 0; } } else { if (wt >= NR_WT) { dev_err(vortex->card->dev, "WT SetReg: voice out of range\n"); return 0; } } if (reg > 0xc) return 0; switch (reg) { /* Voice specific parameters */ case 0: /* running */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_RUN(wt), (int)val); */ hwwrite(vortex->mmio, WT_RUN(wt), val); return 0xc; case 1: /* param 0 */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,0), (int)val); */ hwwrite(vortex->mmio, WT_PARM(wt, 0), val); return 0xc; case 2: /* param 1 */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,1), (int)val); */ hwwrite(vortex->mmio, WT_PARM(wt, 1), val); return 0xc; case 3: /* param 2 */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,2), (int)val); */ hwwrite(vortex->mmio, WT_PARM(wt, 2), val); return 0xc; case 4: /* param 3 */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,3), (int)val); */ hwwrite(vortex->mmio, WT_PARM(wt, 3), val); return 0xc; case 6: /* mute */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_MUTE(wt), (int)val); */ hwwrite(vortex->mmio, WT_MUTE(wt), val); return 0xc; case 0xb: /* delay */ /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", WT_DELAY(wt,0), (int)val); */ hwwrite(vortex->mmio, WT_DELAY(wt, 3), val); hwwrite(vortex->mmio, WT_DELAY(wt, 2), val); hwwrite(vortex->mmio, WT_DELAY(wt, 1), val); hwwrite(vortex->mmio, WT_DELAY(wt, 0), val); return 0xc; /* Global WT block parameters */ case 5: /* sramp */ ecx = WT_SRAMP(wt); break; case 8: /* aramp */ ecx = WT_ARAMP(wt); break; case 9: /* mramp */ ecx = WT_MRAMP(wt); break; case 0xa: /* ctrl */ ecx = WT_CTRL(wt); break; case 0xc: /* ds_reg */ ecx = WT_DSREG(wt); break; default: return 0; } /* pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val); */ hwwrite(vortex->mmio, ecx, val); return 1; } static void vortex_wt_init(vortex_t * vortex) { u32 var4, var8, varc, var10 = 0, edi; var10 &= 0xFFFFFFE3; var10 |= 0x22; var10 &= 0xFFFFFEBF; var10 |= 0x80; var10 |= 0x200; var10 &= 0xfffffffe; var10 &= 0xfffffbff; var10 |= 0x1800; // var10 = 0x1AA2 var4 = 0x10000000; varc = 0x00830000; var8 = 0x00830000; /* Init Bank registers. */ for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) { vortex_wt_SetReg(vortex, 0xc, edi, 0); /* ds_reg */ vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ vortex_wt_SetReg(vortex, 0x9, edi, var4); /* mramp */ vortex_wt_SetReg(vortex, 0x8, edi, varc); /* aramp */ vortex_wt_SetReg(vortex, 0x5, edi, var8); /* sramp */ } /* Init Voice registers. */ for (edi = 0; edi < NR_WT; edi++) { vortex_wt_SetReg(vortex, 0x4, edi, 0); /* param 3 0x20c */ vortex_wt_SetReg(vortex, 0x3, edi, 0); /* param 2 0x208 */ vortex_wt_SetReg(vortex, 0x2, edi, 0); /* param 1 0x204 */ vortex_wt_SetReg(vortex, 0x1, edi, 0); /* param 0 0x200 */ vortex_wt_SetReg(vortex, 0xb, edi, 0); /* delay 0x400 - 0x40c */ } var10 |= 1; for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ } /* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */ #if 0 static void vortex_wt_SetVolume(vortex_t * vortex, int wt, int vol[]) { wt_voice_t *voice = &(vortex->wt_voice[wt]); int ecx = vol[1], eax = vol[0]; /* This is pure guess */ voice->parm0 &= 0xff00ffff; voice->parm0 |= (vol[0] & 0xff) << 0x10; voice->parm1 &= 0xff00ffff; voice->parm1 |= (vol[1] & 0xff) << 0x10; /* This is real */ hwwrite(vortex, WT_PARM(wt, 0), voice->parm0); hwwrite(vortex, WT_PARM(wt, 1), voice->parm0); if (voice->this_1D0 & 4) { eax >>= 8; ecx = eax; if (ecx < 0x80) ecx = 0x7f; voice->parm3 &= 0xFFFFC07F; voice->parm3 |= (ecx & 0x7f) << 7; voice->parm3 &= 0xFFFFFF80; voice->parm3 |= (eax & 0x7f); } else { voice->parm3 &= 0xFFE03FFF; voice->parm3 |= (eax & 0xFE00) << 5; } hwwrite(vortex, WT_PARM(wt, 3), voice->parm3); } /* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */ static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr) { wt_voice_t *voice = &(vortex->wt_voice[wt]); u32 eax, edx; //FIXME: 64 bit operation. eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff; edx = (((sr << 0xf) * 0x57619F1)) >> 0x20; edx >>= 0xa; edx <<= 1; if (edx) { if (edx & 0x0FFF80000) eax = 0x7fff; else { edx <<= 0xd; eax = 7; while ((edx & 0x80000000) == 0) { edx <<= 1; eax--; if (eax == 0) break; } if (eax) edx <<= 1; eax <<= 0xc; edx >>= 0x14; eax |= edx; } } else eax = 0; voice->parm0 &= 0xffff0001; voice->parm0 |= (eax & 0x7fff) << 1; voice->parm1 = voice->parm0 | 1; // Wt: this_1D4 //AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4); //AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8); hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0); hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1); } #endif /* End of File */
linux-master
sound/pci/au88x0/au88x0_synth.c
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * au88x0_cxtalk.c * * Wed Nov 19 16:29:47 2003 * Copyright 2003 mjander * [email protected] ****************************************************************************/ /* */ #include "au88x0_xtalk.h" /* Data (a whole lot of data.... ) */ static short const sXtalkWideKLeftEq = 0x269C; static short const sXtalkWideKRightEq = 0x269C; static short const sXtalkWideKLeftXt = 0xF25E; static __maybe_unused short const sXtalkWideKRightXt = 0xF25E; static short const sXtalkWideShiftLeftEq = 1; static short const sXtalkWideShiftRightEq = 1; static short const sXtalkWideShiftLeftXt = 0; static __maybe_unused short const sXtalkWideShiftRightXt = 0; static unsigned short const wXtalkWideLeftDelay = 0xd; static unsigned short const wXtalkWideRightDelay = 0xd; static short const sXtalkNarrowKLeftEq = 0x468D; static short const sXtalkNarrowKRightEq = 0x468D; static short const sXtalkNarrowKLeftXt = 0xF82E; static __maybe_unused short const sXtalkNarrowKRightXt = 0xF82E; static short const sXtalkNarrowShiftLeftEq = 0x3; static short const sXtalkNarrowShiftRightEq = 0x3; static short const sXtalkNarrowShiftLeftXt = 0; static __maybe_unused short const sXtalkNarrowShiftRightXt = 0; static unsigned short const wXtalkNarrowLeftDelay = 0x7; static unsigned short const wXtalkNarrowRightDelay = 0x7; static __maybe_unused xtalk_gains_t const asXtalkGainsDefault = { 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000 }; static __maybe_unused xtalk_gains_t const asXtalkGainsTest = { 0x7fff, 0x8000, 0x0000, 0x0000, 0x0001, 0xffff, 0x4000, 0xc000, 0x0002, 0xfffe }; static __maybe_unused xtalk_gains_t const asXtalkGains1Chan = { 0x7FFF, 0, 0, 0, 0, 0x7FFF, 0, 0, 0, 0, }; // Input gain for 4 A3D slices. One possible input pair is left zero. static xtalk_gains_t const asXtalkGainsAllChan = { 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0 }; static xtalk_gains_t const asXtalkGainsZeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static xtalk_dline_t const alXtalkDlineZeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static __maybe_unused xtalk_dline_t const alXtalkDlineTest = { 0x0000fc18, 0xfff03e8, 0x000186a0, 0xfffe7960, 1, 0xffffffff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static xtalk_instate_t const asXtalkInStateZeros = { 0, 0, 0, 0 }; static __maybe_unused xtalk_instate_t const asXtalkInStateTest = { 0x0080, 0xff80, 0x0001, 0xffff }; static xtalk_state_t const asXtalkOutStateZeros = { {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} }; static short const sDiamondKLeftEq = 0x401d; static short const sDiamondKRightEq = 0x401d; static short const sDiamondKLeftXt = 0xF90E; static __maybe_unused short const sDiamondKRightXt = 0xF90E; static short const sDiamondShiftLeftEq = 1; static short const sDiamondShiftRightEq = 1; static short const sDiamondShiftLeftXt = 0; static __maybe_unused short const sDiamondShiftRightXt = 0; static unsigned short const wDiamondLeftDelay = 0xb; static unsigned short const wDiamondRightDelay = 0xb; static xtalk_coefs_t const asXtalkWideCoefsLeftEq = { {0xEC4C, 0xDCE9, 0xFDC2, 0xFEEC, 0}, {0x5F60, 0xCBCB, 0xFC26, 0x0305, 0}, {0x340B, 0xe8f5, 0x236c, 0xe40d, 0}, {0x76d5, 0xc78d, 0x05ac, 0xfa5b, 0}, {0x7F04, 0xC0FA, 0x0263, 0xFDA2, 0} }; static xtalk_coefs_t const asXtalkWideCoefsRightEq = { {0xEC4C, 0xDCE9, 0xFDC2, 0xFEEC, 0}, {0x5F60, 0xCBCB, 0xFC26, 0x0305, 0}, {0x340B, 0xe8f5, 0x236c, 0xe40d, 0}, {0x76d5, 0xc78d, 0x05ac, 0xfa5b, 0}, {0x7F04, 0xC0FA, 0x0263, 0xFDA2, 0} }; static xtalk_coefs_t const asXtalkWideCoefsLeftXt = { {0x55c6, 0xc97b, 0x005b, 0x0047, 0}, {0x6a60, 0xca20, 0xffc6, 0x0040, 0}, {0x6411, 0xd711, 0xfca1, 0x0190, 0}, {0x77dc, 0xc79e, 0xffb8, 0x000a, 0}, {0, 0, 0, 0, 0} }; static __maybe_unused xtalk_coefs_t const asXtalkWideCoefsRightXt = { {0x55c6, 0xc97b, 0x005b, 0x0047, 0}, {0x6a60, 0xca20, 0xffc6, 0x0040, 0}, {0x6411, 0xd711, 0xfca1, 0x0190, 0}, {0x77dc, 0xc79e, 0xffb8, 0x000a, 0}, {0, 0, 0, 0, 0} }; static xtalk_coefs_t const asXtalkNarrowCoefsLeftEq = { {0x50B5, 0xD07C, 0x026D, 0xFD21, 0}, {0x460F, 0xE44F, 0xF75E, 0xEFA6, 0}, {0x556D, 0xDCAB, 0x2098, 0xF0F2, 0}, {0x7E03, 0xC1F0, 0x007D, 0xFF89, 0}, {0x383E, 0xFD9D, 0xB278, 0x4547, 0} }; static xtalk_coefs_t const asXtalkNarrowCoefsRightEq = { {0x50B5, 0xD07C, 0x026D, 0xFD21, 0}, {0x460F, 0xE44F, 0xF75E, 0xEFA6, 0}, {0x556D, 0xDCAB, 0x2098, 0xF0F2, 0}, {0x7E03, 0xC1F0, 0x007D, 0xFF89, 0}, {0x383E, 0xFD9D, 0xB278, 0x4547, 0} }; static xtalk_coefs_t const asXtalkNarrowCoefsLeftXt = { {0x3CB2, 0xDF49, 0xF6EA, 0x095B, 0}, {0x6777, 0xC915, 0xFEAF, 0x00B1, 0}, {0x7762, 0xC7D9, 0x025B, 0xFDA6, 0}, {0x6B7A, 0xD2AA, 0xF2FB, 0x0B64, 0}, {0, 0, 0, 0, 0} }; static __maybe_unused xtalk_coefs_t const asXtalkNarrowCoefsRightXt = { {0x3CB2, 0xDF49, 0xF6EA, 0x095B, 0}, {0x6777, 0xC915, 0xFEAF, 0x00B1, 0}, {0x7762, 0xC7D9, 0x025B, 0xFDA6, 0}, {0x6B7A, 0xD2AA, 0xF2FB, 0x0B64, 0}, {0, 0, 0, 0, 0} }; static xtalk_coefs_t const asXtalkCoefsZeros = { {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static xtalk_coefs_t const asXtalkCoefsPipe = { {0, 0, 0x0FA0, 0, 0}, {0, 0, 0x0FA0, 0, 0}, {0, 0, 0x0FA0, 0, 0}, {0, 0, 0x0FA0, 0, 0}, {0, 0, 0x1180, 0, 0}, }; static __maybe_unused xtalk_coefs_t const asXtalkCoefsNegPipe = { {0, 0, 0xF380, 0, 0}, {0, 0, 0xF380, 0, 0}, {0, 0, 0xF380, 0, 0}, {0, 0, 0xF380, 0, 0}, {0, 0, 0xF200, 0, 0} }; static __maybe_unused xtalk_coefs_t const asXtalkCoefsNumTest = { {0, 0, 0xF380, 0x8000, 0x6D60}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static __maybe_unused xtalk_coefs_t const asXtalkCoefsDenTest = { {0xC000, 0x2000, 0x4000, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static __maybe_unused xtalk_state_t const asXtalkOutStateTest = { {0x7FFF, 0x0004, 0xFFFC, 0}, {0xFE00, 0x0008, 0xFFF8, 0x4000}, {0x0200, 0x0010, 0xFFF0, 0xC000}, {0x8000, 0x0020, 0xFFE0, 0}, {0, 0, 0, 0} }; static xtalk_coefs_t const asDiamondCoefsLeftEq = { {0x0F1E, 0x2D05, 0xF8E3, 0x07C8, 0}, {0x45E2, 0xCA51, 0x0448, 0xFCE7, 0}, {0xA93E, 0xDBD5, 0x022C, 0x028A, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static xtalk_coefs_t const asDiamondCoefsRightEq = { {0x0F1E, 0x2D05, 0xF8E3, 0x07C8, 0}, {0x45E2, 0xCA51, 0x0448, 0xFCE7, 0}, {0xA93E, 0xDBD5, 0x022C, 0x028A, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static xtalk_coefs_t const asDiamondCoefsLeftXt = { {0x3B50, 0xFE08, 0xF959, 0x0060, 0}, {0x9FCB, 0xD8F1, 0x00A2, 0x003A, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; static __maybe_unused xtalk_coefs_t const asDiamondCoefsRightXt = { {0x3B50, 0xFE08, 0xF959, 0x0060, 0}, {0x9FCB, 0xD8F1, 0x00A2, 0x003A, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0} }; /**/ /* XTalk EQ and XT */ static void vortex_XtalkHw_SetLeftEQ(vortex_t * vortex, short arg_0, short arg_4, xtalk_coefs_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); } hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); } static void vortex_XtalkHw_SetRightEQ(vortex_t * vortex, short arg_0, short arg_4, xtalk_coefs_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x242c0 + i * 0x24, coefs[i][3]); hwwrite(vortex->mmio, 0x242c4 + i * 0x24, coefs[i][4]); } hwwrite(vortex->mmio, 0x24540, arg_0 & 0xffff); hwwrite(vortex->mmio, 0x24544, arg_4 & 0xffff); } static void vortex_XtalkHw_SetLeftXT(vortex_t * vortex, short arg_0, short arg_4, xtalk_coefs_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x24368 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x2436c + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x24370 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x24374 + i * 0x24, coefs[i][3]); hwwrite(vortex->mmio, 0x24378 + i * 0x24, coefs[i][4]); } hwwrite(vortex->mmio, 0x24548, arg_0 & 0xffff); hwwrite(vortex->mmio, 0x2454C, arg_4 & 0xffff); } static void vortex_XtalkHw_SetRightXT(vortex_t * vortex, short arg_0, short arg_4, xtalk_coefs_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x2441C + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x24420 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x24424 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x24428 + i * 0x24, coefs[i][3]); hwwrite(vortex->mmio, 0x2442C + i * 0x24, coefs[i][4]); } hwwrite(vortex->mmio, 0x24550, arg_0 & 0xffff); hwwrite(vortex->mmio, 0x24554, arg_4 & 0xffff); } static void vortex_XtalkHw_SetLeftEQStates(vortex_t * vortex, xtalk_instate_t const arg_0, xtalk_state_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x24214 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x24218 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x2421C + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x24220 + i * 0x24, coefs[i][3]); } hwwrite(vortex->mmio, 0x244F8, arg_0[0]); hwwrite(vortex->mmio, 0x244FC, arg_0[1]); hwwrite(vortex->mmio, 0x24500, arg_0[2]); hwwrite(vortex->mmio, 0x24504, arg_0[3]); } static void vortex_XtalkHw_SetRightEQStates(vortex_t * vortex, xtalk_instate_t const arg_0, xtalk_state_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x242C8 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x242CC + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x242D0 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x244D4 + i * 0x24, coefs[i][3]); } hwwrite(vortex->mmio, 0x24508, arg_0[0]); hwwrite(vortex->mmio, 0x2450C, arg_0[1]); hwwrite(vortex->mmio, 0x24510, arg_0[2]); hwwrite(vortex->mmio, 0x24514, arg_0[3]); } static void vortex_XtalkHw_SetLeftXTStates(vortex_t * vortex, xtalk_instate_t const arg_0, xtalk_state_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x2437C + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x24380 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x24384 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x24388 + i * 0x24, coefs[i][3]); } hwwrite(vortex->mmio, 0x24518, arg_0[0]); hwwrite(vortex->mmio, 0x2451C, arg_0[1]); hwwrite(vortex->mmio, 0x24520, arg_0[2]); hwwrite(vortex->mmio, 0x24524, arg_0[3]); } static void vortex_XtalkHw_SetRightXTStates(vortex_t * vortex, xtalk_instate_t const arg_0, xtalk_state_t const coefs) { int i; for (i = 0; i < 5; i++) { hwwrite(vortex->mmio, 0x24430 + i * 0x24, coefs[i][0]); hwwrite(vortex->mmio, 0x24434 + i * 0x24, coefs[i][1]); hwwrite(vortex->mmio, 0x24438 + i * 0x24, coefs[i][2]); hwwrite(vortex->mmio, 0x2443C + i * 0x24, coefs[i][3]); } hwwrite(vortex->mmio, 0x24528, arg_0[0]); hwwrite(vortex->mmio, 0x2452C, arg_0[1]); hwwrite(vortex->mmio, 0x24530, arg_0[2]); hwwrite(vortex->mmio, 0x24534, arg_0[3]); } #if 0 static void vortex_XtalkHw_GetLeftEQ(vortex_t * vortex, short *arg_0, short *arg_4, xtalk_coefs_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x24200 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x24204 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x24208 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x2420c + i * 0x24); coefs[i][4] = hwread(vortex->mmio, 0x24210 + i * 0x24); } *arg_0 = hwread(vortex->mmio, 0x24538) & 0xffff; *arg_4 = hwread(vortex->mmio, 0x2453c) & 0xffff; } static void vortex_XtalkHw_GetRightEQ(vortex_t * vortex, short *arg_0, short *arg_4, xtalk_coefs_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x242b4 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x242b8 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x242bc + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x242c0 + i * 0x24); coefs[i][4] = hwread(vortex->mmio, 0x242c4 + i * 0x24); } *arg_0 = hwread(vortex->mmio, 0x24540) & 0xffff; *arg_4 = hwread(vortex->mmio, 0x24544) & 0xffff; } static void vortex_XtalkHw_GetLeftXT(vortex_t * vortex, short *arg_0, short *arg_4, xtalk_coefs_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x24368 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x2436C + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x24370 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x24374 + i * 0x24); coefs[i][4] = hwread(vortex->mmio, 0x24378 + i * 0x24); } *arg_0 = hwread(vortex->mmio, 0x24548) & 0xffff; *arg_4 = hwread(vortex->mmio, 0x2454C) & 0xffff; } static void vortex_XtalkHw_GetRightXT(vortex_t * vortex, short *arg_0, short *arg_4, xtalk_coefs_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x2441C + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x24420 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x24424 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x24428 + i * 0x24); coefs[i][4] = hwread(vortex->mmio, 0x2442C + i * 0x24); } *arg_0 = hwread(vortex->mmio, 0x24550) & 0xffff; *arg_4 = hwread(vortex->mmio, 0x24554) & 0xffff; } static void vortex_XtalkHw_GetLeftEQStates(vortex_t * vortex, xtalk_instate_t arg_0, xtalk_state_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x24214 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x24218 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x2421C + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x24220 + i * 0x24); } arg_0[0] = hwread(vortex->mmio, 0x244F8); arg_0[1] = hwread(vortex->mmio, 0x244FC); arg_0[2] = hwread(vortex->mmio, 0x24500); arg_0[3] = hwread(vortex->mmio, 0x24504); } static void vortex_XtalkHw_GetRightEQStates(vortex_t * vortex, xtalk_instate_t arg_0, xtalk_state_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x242C8 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x242CC + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x242D0 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x242D4 + i * 0x24); } arg_0[0] = hwread(vortex->mmio, 0x24508); arg_0[1] = hwread(vortex->mmio, 0x2450C); arg_0[2] = hwread(vortex->mmio, 0x24510); arg_0[3] = hwread(vortex->mmio, 0x24514); } static void vortex_XtalkHw_GetLeftXTStates(vortex_t * vortex, xtalk_instate_t arg_0, xtalk_state_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x2437C + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x24380 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x24384 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x24388 + i * 0x24); } arg_0[0] = hwread(vortex->mmio, 0x24518); arg_0[1] = hwread(vortex->mmio, 0x2451C); arg_0[2] = hwread(vortex->mmio, 0x24520); arg_0[3] = hwread(vortex->mmio, 0x24524); } static void vortex_XtalkHw_GetRightXTStates(vortex_t * vortex, xtalk_instate_t arg_0, xtalk_state_t coefs) { int i; for (i = 0; i < 5; i++) { coefs[i][0] = hwread(vortex->mmio, 0x24430 + i * 0x24); coefs[i][1] = hwread(vortex->mmio, 0x24434 + i * 0x24); coefs[i][2] = hwread(vortex->mmio, 0x24438 + i * 0x24); coefs[i][3] = hwread(vortex->mmio, 0x2443C + i * 0x24); } arg_0[0] = hwread(vortex->mmio, 0x24528); arg_0[1] = hwread(vortex->mmio, 0x2452C); arg_0[2] = hwread(vortex->mmio, 0x24530); arg_0[3] = hwread(vortex->mmio, 0x24534); } #endif /* Gains */ static void vortex_XtalkHw_SetGains(vortex_t * vortex, xtalk_gains_t const gains) { int i; for (i = 0; i < XTGAINS_SZ; i++) { hwwrite(vortex->mmio, 0x244D0 + (i * 4), gains[i]); } } static void vortex_XtalkHw_SetGainsAllChan(vortex_t * vortex) { vortex_XtalkHw_SetGains(vortex, asXtalkGainsAllChan); } #if 0 static void vortex_XtalkHw_GetGains(vortex_t * vortex, xtalk_gains_t gains) { int i; for (i = 0; i < XTGAINS_SZ; i++) gains[i] = hwread(vortex->mmio, 0x244D0 + i * 4); } #endif /* Delay parameters */ static void vortex_XtalkHw_SetDelay(vortex_t * vortex, unsigned short right, unsigned short left) { u32 esp0 = 0; esp0 &= 0x1FFFFFFF; esp0 |= 0xA0000000; esp0 = (esp0 & 0xffffE0ff) | ((right & 0x1F) << 8); esp0 = (esp0 & 0xfffc1fff) | ((left & 0x1F) << 0xd); hwwrite(vortex->mmio, 0x24660, esp0); } static void vortex_XtalkHw_SetLeftDline(vortex_t * vortex, xtalk_dline_t const dline) { int i; for (i = 0; i < 0x20; i++) { hwwrite(vortex->mmio, 0x24000 + (i << 2), dline[i] & 0xffff); hwwrite(vortex->mmio, 0x24080 + (i << 2), dline[i] >> 0x10); } } static void vortex_XtalkHw_SetRightDline(vortex_t * vortex, xtalk_dline_t const dline) { int i; for (i = 0; i < 0x20; i++) { hwwrite(vortex->mmio, 0x24100 + (i << 2), dline[i] & 0xffff); hwwrite(vortex->mmio, 0x24180 + (i << 2), dline[i] >> 0x10); } } #if 0 static void vortex_XtalkHw_GetDelay(vortex_t * vortex, unsigned short *right, unsigned short *left) { int esp0; esp0 = hwread(vortex->mmio, 0x24660); *right = (esp0 >> 8) & 0x1f; *left = (esp0 >> 0xd) & 0x1f; } static void vortex_XtalkHw_GetLeftDline(vortex_t * vortex, xtalk_dline_t dline) { int i; for (i = 0; i < 0x20; i++) { dline[i] = (hwread(vortex->mmio, 0x24000 + (i << 2)) & 0xffff) | (hwread(vortex->mmio, 0x24080 + (i << 2)) << 0x10); } } static void vortex_XtalkHw_GetRightDline(vortex_t * vortex, xtalk_dline_t dline) { int i; for (i = 0; i < 0x20; i++) { dline[i] = (hwread(vortex->mmio, 0x24100 + (i << 2)) & 0xffff) | (hwread(vortex->mmio, 0x24180 + (i << 2)) << 0x10); } } #endif /* Control/Global stuff */ #if 0 static void vortex_XtalkHw_SetControlReg(vortex_t * vortex, u32 ctrl) { hwwrite(vortex->mmio, 0x24660, ctrl); } static void vortex_XtalkHw_GetControlReg(vortex_t * vortex, u32 *ctrl) { *ctrl = hwread(vortex->mmio, 0x24660); } #endif static void vortex_XtalkHw_SetSampleRate(vortex_t * vortex, u32 sr) { u32 temp; temp = (hwread(vortex->mmio, 0x24660) & 0x1FFFFFFF) | 0xC0000000; temp = (temp & 0xffffff07) | ((sr & 0x1f) << 3); hwwrite(vortex->mmio, 0x24660, temp); } #if 0 static void vortex_XtalkHw_GetSampleRate(vortex_t * vortex, u32 *sr) { *sr = (hwread(vortex->mmio, 0x24660) >> 3) & 0x1f; } #endif static void vortex_XtalkHw_Enable(vortex_t * vortex) { u32 temp; temp = (hwread(vortex->mmio, 0x24660) & 0x1FFFFFFF) | 0xC0000000; temp |= 1; hwwrite(vortex->mmio, 0x24660, temp); } static void vortex_XtalkHw_Disable(vortex_t * vortex) { u32 temp; temp = (hwread(vortex->mmio, 0x24660) & 0x1FFFFFFF) | 0xC0000000; temp &= 0xfffffffe; hwwrite(vortex->mmio, 0x24660, temp); } static void vortex_XtalkHw_ZeroIO(vortex_t * vortex) { int i; for (i = 0; i < 20; i++) hwwrite(vortex->mmio, 0x24600 + (i << 2), 0); for (i = 0; i < 4; i++) hwwrite(vortex->mmio, 0x24650 + (i << 2), 0); } static void vortex_XtalkHw_ZeroState(vortex_t * vortex) { vortex_XtalkHw_ZeroIO(vortex); // inlined vortex_XtalkHw_SetLeftEQ(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetRightEQ(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetLeftXT(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetRightXT(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetGains(vortex, asXtalkGainsZeros); // inlined vortex_XtalkHw_SetDelay(vortex, 0, 0); // inlined vortex_XtalkHw_SetLeftDline(vortex, alXtalkDlineZeros); // inlined vortex_XtalkHw_SetRightDline(vortex, alXtalkDlineZeros); // inlined vortex_XtalkHw_SetLeftDline(vortex, alXtalkDlineZeros); // inlined vortex_XtalkHw_SetRightDline(vortex, alXtalkDlineZeros); // inlined vortex_XtalkHw_SetLeftEQStates(vortex, asXtalkInStateZeros, asXtalkOutStateZeros); vortex_XtalkHw_SetRightEQStates(vortex, asXtalkInStateZeros, asXtalkOutStateZeros); vortex_XtalkHw_SetLeftXTStates(vortex, asXtalkInStateZeros, asXtalkOutStateZeros); vortex_XtalkHw_SetRightXTStates(vortex, asXtalkInStateZeros, asXtalkOutStateZeros); } static void vortex_XtalkHw_ProgramPipe(vortex_t * vortex) { vortex_XtalkHw_SetLeftEQ(vortex, 0, 1, asXtalkCoefsPipe); vortex_XtalkHw_SetRightEQ(vortex, 0, 1, asXtalkCoefsPipe); vortex_XtalkHw_SetLeftXT(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetRightXT(vortex, 0, 0, asXtalkCoefsZeros); vortex_XtalkHw_SetDelay(vortex, 0, 0); // inlined } static void vortex_XtalkHw_ProgramXtalkWide(vortex_t * vortex) { vortex_XtalkHw_SetLeftEQ(vortex, sXtalkWideKLeftEq, sXtalkWideShiftLeftEq, asXtalkWideCoefsLeftEq); vortex_XtalkHw_SetRightEQ(vortex, sXtalkWideKRightEq, sXtalkWideShiftRightEq, asXtalkWideCoefsRightEq); vortex_XtalkHw_SetLeftXT(vortex, sXtalkWideKLeftXt, sXtalkWideShiftLeftXt, asXtalkWideCoefsLeftXt); vortex_XtalkHw_SetRightXT(vortex, sXtalkWideKLeftXt, sXtalkWideShiftLeftXt, asXtalkWideCoefsLeftXt); vortex_XtalkHw_SetDelay(vortex, wXtalkWideRightDelay, wXtalkWideLeftDelay); // inlined } static void vortex_XtalkHw_ProgramXtalkNarrow(vortex_t * vortex) { vortex_XtalkHw_SetLeftEQ(vortex, sXtalkNarrowKLeftEq, sXtalkNarrowShiftLeftEq, asXtalkNarrowCoefsLeftEq); vortex_XtalkHw_SetRightEQ(vortex, sXtalkNarrowKRightEq, sXtalkNarrowShiftRightEq, asXtalkNarrowCoefsRightEq); vortex_XtalkHw_SetLeftXT(vortex, sXtalkNarrowKLeftXt, sXtalkNarrowShiftLeftXt, asXtalkNarrowCoefsLeftXt); vortex_XtalkHw_SetRightXT(vortex, sXtalkNarrowKLeftXt, sXtalkNarrowShiftLeftXt, asXtalkNarrowCoefsLeftXt); vortex_XtalkHw_SetDelay(vortex, wXtalkNarrowRightDelay, wXtalkNarrowLeftDelay); // inlined } static void vortex_XtalkHw_ProgramDiamondXtalk(vortex_t * vortex) { //sDiamondKLeftEq,sDiamondKRightXt,asDiamondCoefsLeftEq vortex_XtalkHw_SetLeftEQ(vortex, sDiamondKLeftEq, sDiamondShiftLeftEq, asDiamondCoefsLeftEq); vortex_XtalkHw_SetRightEQ(vortex, sDiamondKRightEq, sDiamondShiftRightEq, asDiamondCoefsRightEq); vortex_XtalkHw_SetLeftXT(vortex, sDiamondKLeftXt, sDiamondShiftLeftXt, asDiamondCoefsLeftXt); vortex_XtalkHw_SetRightXT(vortex, sDiamondKLeftXt, sDiamondShiftLeftXt, asDiamondCoefsLeftXt); vortex_XtalkHw_SetDelay(vortex, wDiamondRightDelay, wDiamondLeftDelay); // inlined } static void vortex_XtalkHw_init(vortex_t * vortex) { vortex_XtalkHw_ZeroState(vortex); } /* End of file */
linux-master
sound/pci/au88x0/au88x0_xtalk.c
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * au88x0_a3d.c * * Fri Jul 18 14:16:22 2003 * Copyright 2003 mjander * [email protected] * * A3D. You may think i'm crazy, but this may work someday. Who knows... ****************************************************************************/ /* */ #include "au88x0_a3d.h" #include "au88x0_a3ddata.c" #include "au88x0_xtalk.h" #include "au88x0.h" static void a3dsrc_SetTimeConsts(a3dsrc_t * a, short HrtfTrack, short ItdTrack, short GTrack, short CTrack) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfTrackTC), HrtfTrack); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_ITDTrackTC), ItdTrack); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_GainTrackTC), GTrack); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_CoeffTrackTC), CTrack); } #if 0 static void a3dsrc_GetTimeConsts(a3dsrc_t * a, short *HrtfTrack, short *ItdTrack, short *GTrack, short *CTrack) { // stub! } #endif /* Atmospheric absorption. */ static void a3dsrc_SetAtmosTarget(a3dsrc_t * a, short aa, short b, short c, short d, short e) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_A21Target), (e << 0x10) | d); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_B10Target), (b << 0x10) | aa); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_B2Target), c); } static void a3dsrc_SetAtmosCurrent(a3dsrc_t * a, short aa, short b, short c, short d, short e) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_A12Current), (e << 0x10) | d); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_B01Current), (b << 0x10) | aa); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_B2Current), c); } static void a3dsrc_SetAtmosState(a3dsrc_t * a, short x1, short x2, short y1, short y2) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_x1), x1); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_x2), x2); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_y1), y1); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_y2), y2); } #if 0 static void a3dsrc_GetAtmosTarget(a3dsrc_t * a, short *aa, short *b, short *c, short *d, short *e) { } static void a3dsrc_GetAtmosCurrent(a3dsrc_t * a, short *bb01, short *ab01, short *b2, short *aa12, short *ba12) { vortex_t *vortex = (vortex_t *) (a->vortex); *aa12 = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_A12Current)); *ba12 = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_A12Current)); *ab01 = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_B01Current)); *bb01 = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_B01Current)); *b2 = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_B2Current)); } static void a3dsrc_GetAtmosState(a3dsrc_t * a, short *x1, short *x2, short *y1, short *y2) { } #endif /* HRTF */ static void a3dsrc_SetHrtfTarget(a3dsrc_t * a, a3d_Hrtf_t const aa, a3d_Hrtf_t const b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < HRTF_SZ; i++) hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfTarget) + (i << 2), (b[i] << 0x10) | aa[i]); } static void a3dsrc_SetHrtfCurrent(a3dsrc_t * a, a3d_Hrtf_t const aa, a3d_Hrtf_t const b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < HRTF_SZ; i++) hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfCurrent) + (i << 2), (b[i] << 0x10) | aa[i]); } static void a3dsrc_SetHrtfState(a3dsrc_t * a, a3d_Hrtf_t const aa, a3d_Hrtf_t const b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < HRTF_SZ; i++) hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfDelayLine) + (i << 2), (b[i] << 0x10) | aa[i]); } static void a3dsrc_SetHrtfOutput(a3dsrc_t * a, short left, short right) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfOutL), left); hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfOutR), right); } #if 0 static void a3dsrc_GetHrtfTarget(a3dsrc_t * a, a3d_Hrtf_t aa, a3d_Hrtf_t b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < HRTF_SZ; i++) aa[i] = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfTarget + (i << 2))); for (i = 0; i < HRTF_SZ; i++) b[i] = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfTarget + (i << 2))); } static void a3dsrc_GetHrtfCurrent(a3dsrc_t * a, a3d_Hrtf_t aa, a3d_Hrtf_t b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < HRTF_SZ; i++) aa[i] = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfCurrent + (i << 2))); for (i = 0; i < HRTF_SZ; i++) b[i] = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfCurrent + (i << 2))); } static void a3dsrc_GetHrtfState(a3dsrc_t * a, a3d_Hrtf_t aa, a3d_Hrtf_t b) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; // FIXME: verify this! for (i = 0; i < HRTF_SZ; i++) aa[i] = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfDelayLine + (i << 2))); for (i = 0; i < HRTF_SZ; i++) b[i] = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_HrtfDelayLine + (i << 2))); } static void a3dsrc_GetHrtfOutput(a3dsrc_t * a, short *left, short *right) { vortex_t *vortex = (vortex_t *) (a->vortex); *left = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfOutL)); *right = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_HrtfOutR)); } #endif /* Interaural Time Difference. * "The other main clue that humans use to locate sounds, is called * Interaural Time Difference (ITD). The differences in distance from * the sound source to a listeners ears means that the sound will * reach one ear slightly before the other....", found somewhere with google.*/ static void a3dsrc_SetItdTarget(a3dsrc_t * a, short litd, short ritd) { vortex_t *vortex = (vortex_t *) (a->vortex); if (litd < 0) litd = 0; if (litd > 0x57FF) litd = 0x57FF; if (ritd < 0) ritd = 0; if (ritd > 0x57FF) ritd = 0x57FF; hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_ITDTarget), (ritd << 0x10) | litd); //hwwrite(vortex->mmio, addr(0x191DF+5, this04, this08), (ritd<<0x10)|litd); } static void a3dsrc_SetItdCurrent(a3dsrc_t * a, short litd, short ritd) { vortex_t *vortex = (vortex_t *) (a->vortex); if (litd < 0) litd = 0; if (litd > 0x57FF) litd = 0x57FF; if (ritd < 0) ritd = 0; if (ritd > 0x57FF) ritd = 0x57FF; hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_ITDCurrent), (ritd << 0x10) | litd); //hwwrite(vortex->mmio, addr(0x191DF+1, this04, this08), (ritd<<0x10)|litd); } static void a3dsrc_SetItdDline(a3dsrc_t * a, a3d_ItdDline_t const dline) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; /* 45 != 40 -> Check this ! */ for (i = 0; i < DLINE_SZ; i++) hwwrite(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_ITDDelayLine) + (i << 2), dline[i]); } #if 0 static void a3dsrc_GetItdTarget(a3dsrc_t * a, short *litd, short *ritd) { vortex_t *vortex = (vortex_t *) (a->vortex); *ritd = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_ITDTarget)); *litd = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_ITDTarget)); } static void a3dsrc_GetItdCurrent(a3dsrc_t * a, short *litd, short *ritd) { vortex_t *vortex = (vortex_t *) (a->vortex); *ritd = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_ITDCurrent)); *litd = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_ITDCurrent)); } static void a3dsrc_GetItdDline(a3dsrc_t * a, a3d_ItdDline_t dline) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < DLINE_SZ; i++) dline[i] = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_ITDDelayLine + (i << 2))); } #endif /* This is may be used for ILD Interaural Level Difference. */ static void a3dsrc_SetGainTarget(a3dsrc_t * a, short left, short right) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_GainTarget), (right << 0x10) | left); } static void a3dsrc_SetGainCurrent(a3dsrc_t * a, short left, short right) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_GainCurrent), (right << 0x10) | left); } #if 0 static void a3dsrc_GetGainTarget(a3dsrc_t * a, short *left, short *right) { vortex_t *vortex = (vortex_t *) (a->vortex); *right = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_GainTarget)); *left = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_GainTarget)); } static void a3dsrc_GetGainCurrent(a3dsrc_t * a, short *left, short *right) { vortex_t *vortex = (vortex_t *) (a->vortex); *right = hwread(vortex->mmio, a3d_addrA(a->slice, a->source, A3D_A_GainCurrent)); *left = hwread(vortex->mmio, a3d_addrB(a->slice, a->source, A3D_B_GainCurrent)); } /* CA3dIO this func seems to be inlined all over this place. */ static void CA3dIO_WriteReg(a3dsrc_t * a, unsigned long addr, short aa, short b) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, addr, (aa << 0x10) | b); } #endif /* Generic A3D stuff */ static void a3dsrc_SetA3DSampleRate(a3dsrc_t * a, int sr) { vortex_t *vortex = (vortex_t *) (a->vortex); int esp0 = 0; esp0 = (((esp0 & 0x7fffffff) | 0xB8000000) & 0x7) | ((sr & 0x1f) << 3); hwwrite(vortex->mmio, A3D_SLICE_Control + ((a->slice) << 0xd), esp0); //hwwrite(vortex->mmio, 0x19C38 + (this08<<0xd), esp0); } static void a3dsrc_EnableA3D(a3dsrc_t * a) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, A3D_SLICE_Control + ((a->slice) << 0xd), 0xF0000001); //hwwrite(vortex->mmio, 0x19C38 + (this08<<0xd), 0xF0000001); } static void a3dsrc_DisableA3D(a3dsrc_t * a) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, A3D_SLICE_Control + ((a->slice) << 0xd), 0xF0000000); } static void a3dsrc_SetA3DControlReg(a3dsrc_t * a, unsigned long ctrl) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, A3D_SLICE_Control + ((a->slice) << 0xd), ctrl); } static void a3dsrc_SetA3DPointerReg(a3dsrc_t * a, unsigned long ptr) { vortex_t *vortex = (vortex_t *) (a->vortex); hwwrite(vortex->mmio, A3D_SLICE_Pointers + ((a->slice) << 0xd), ptr); } #if 0 static void a3dsrc_GetA3DSampleRate(a3dsrc_t * a, int *sr) { vortex_t *vortex = (vortex_t *) (a->vortex); *sr = ((hwread(vortex->mmio, A3D_SLICE_Control + (a->slice << 0xd)) >> 3) & 0x1f); //*sr = ((hwread(vortex->mmio, 0x19C38 + (this08<<0xd))>>3)&0x1f); } static void a3dsrc_GetA3DControlReg(a3dsrc_t * a, unsigned long *ctrl) { vortex_t *vortex = (vortex_t *) (a->vortex); *ctrl = hwread(vortex->mmio, A3D_SLICE_Control + ((a->slice) << 0xd)); } static void a3dsrc_GetA3DPointerReg(a3dsrc_t * a, unsigned long *ptr) { vortex_t *vortex = (vortex_t *) (a->vortex); *ptr = hwread(vortex->mmio, A3D_SLICE_Pointers + ((a->slice) << 0xd)); } #endif static void a3dsrc_ZeroSliceIO(a3dsrc_t * a) { vortex_t *vortex = (vortex_t *) (a->vortex); int i; for (i = 0; i < 8; i++) hwwrite(vortex->mmio, A3D_SLICE_VDBDest + ((((a->slice) << 0xb) + i) << 2), 0); for (i = 0; i < 4; i++) hwwrite(vortex->mmio, A3D_SLICE_VDBSource + ((((a->slice) << 0xb) + i) << 2), 0); } /* Reset Single A3D source. */ static void a3dsrc_ZeroState(a3dsrc_t * a) { /* pr_debug( "vortex: ZeroState slice: %d, source %d\n", a->slice, a->source); */ a3dsrc_SetAtmosState(a, 0, 0, 0, 0); a3dsrc_SetHrtfState(a, A3dHrirZeros, A3dHrirZeros); a3dsrc_SetItdDline(a, A3dItdDlineZeros); a3dsrc_SetHrtfOutput(a, 0, 0); a3dsrc_SetTimeConsts(a, 0, 0, 0, 0); a3dsrc_SetAtmosCurrent(a, 0, 0, 0, 0, 0); a3dsrc_SetAtmosTarget(a, 0, 0, 0, 0, 0); a3dsrc_SetItdCurrent(a, 0, 0); a3dsrc_SetItdTarget(a, 0, 0); a3dsrc_SetGainCurrent(a, 0, 0); a3dsrc_SetGainTarget(a, 0, 0); a3dsrc_SetHrtfCurrent(a, A3dHrirZeros, A3dHrirZeros); a3dsrc_SetHrtfTarget(a, A3dHrirZeros, A3dHrirZeros); } /* Reset entire A3D engine */ static void a3dsrc_ZeroStateA3D(a3dsrc_t *a, vortex_t *v) { int i, var, var2; if ((a->vortex) == NULL) { dev_err(v->card->dev, "ZeroStateA3D: ERROR: a->vortex is NULL\n"); return; } a3dsrc_SetA3DControlReg(a, 0); a3dsrc_SetA3DPointerReg(a, 0); var = a->slice; var2 = a->source; for (i = 0; i < 4; i++) { a->slice = i; a3dsrc_ZeroSliceIO(a); //a3dsrc_ZeroState(a); } a->source = var2; a->slice = var; } /* Program A3D block as pass through */ static void a3dsrc_ProgramPipe(a3dsrc_t * a) { a3dsrc_SetTimeConsts(a, 0, 0, 0, 0); a3dsrc_SetAtmosCurrent(a, 0, 0x4000, 0, 0, 0); a3dsrc_SetAtmosTarget(a, 0x4000, 0, 0, 0, 0); a3dsrc_SetItdCurrent(a, 0, 0); a3dsrc_SetItdTarget(a, 0, 0); a3dsrc_SetGainCurrent(a, 0x7fff, 0x7fff); a3dsrc_SetGainTarget(a, 0x7fff, 0x7fff); /* SET HRTF HERE */ /* Single spike leads to identity transfer function. */ a3dsrc_SetHrtfCurrent(a, A3dHrirImpulse, A3dHrirImpulse); a3dsrc_SetHrtfTarget(a, A3dHrirImpulse, A3dHrirImpulse); /* Test: Sounds saturated. */ //a3dsrc_SetHrtfCurrent(a, A3dHrirSatTest, A3dHrirSatTest); //a3dsrc_SetHrtfTarget(a, A3dHrirSatTest, A3dHrirSatTest); } /* VDB = Vortex audio Dataflow Bus */ #if 0 static void a3dsrc_ClearVDBData(a3dsrc_t * a, unsigned long aa) { vortex_t *vortex = (vortex_t *) (a->vortex); // ((aa >> 2) << 8) - (aa >> 2) hwwrite(vortex->mmio, a3d_addrS(a->slice, A3D_SLICE_VDBDest) + (a->source << 2), 0); hwwrite(vortex->mmio, a3d_addrS(a->slice, A3D_SLICE_VDBDest + 4) + (a->source << 2), 0); /* hwwrite(vortex->mmio, 0x19c00 + (((aa>>2)*255*4)+aa)*8, 0); hwwrite(vortex->mmio, 0x19c04 + (((aa>>2)*255*4)+aa)*8, 0); */ } #endif /* A3D HwSource stuff. */ static void vortex_A3dSourceHw_Initialize(vortex_t * v, int source, int slice) { a3dsrc_t *a3dsrc = &(v->a3d[source + (slice * 4)]); //a3dsrc_t *a3dsrc = &(v->a3d[source + (slice*4)]); a3dsrc->vortex = (void *)v; a3dsrc->source = source; /* source */ a3dsrc->slice = slice; /* slice */ a3dsrc_ZeroState(a3dsrc); /* Added by me. */ a3dsrc_SetA3DSampleRate(a3dsrc, 0x11); } static int Vort3DRend_Initialize(vortex_t * v, unsigned short mode) { v->xt_mode = mode; /* this_14 */ vortex_XtalkHw_init(v); vortex_XtalkHw_SetGainsAllChan(v); switch (v->xt_mode) { case XT_SPEAKER0: vortex_XtalkHw_ProgramXtalkNarrow(v); break; case XT_SPEAKER1: vortex_XtalkHw_ProgramXtalkWide(v); break; default: case XT_HEADPHONE: vortex_XtalkHw_ProgramPipe(v); break; case XT_DIAMOND: vortex_XtalkHw_ProgramDiamondXtalk(v); break; } vortex_XtalkHw_SetSampleRate(v, 0x11); vortex_XtalkHw_Enable(v); return 0; } /* 3D Sound entry points. */ static int vortex_a3d_register_controls(vortex_t * vortex); static void vortex_a3d_unregister_controls(vortex_t * vortex); /* A3D base support init/shudown */ static void vortex_Vort3D_enable(vortex_t *v) { int i; Vort3DRend_Initialize(v, XT_HEADPHONE); for (i = 0; i < NR_A3D; i++) { vortex_A3dSourceHw_Initialize(v, i % 4, i >> 2); a3dsrc_ZeroStateA3D(&v->a3d[0], v); } /* Register ALSA controls */ vortex_a3d_register_controls(v); } static void vortex_Vort3D_disable(vortex_t * v) { vortex_XtalkHw_Disable(v); vortex_a3d_unregister_controls(v); } /* Make A3D subsystem connections. */ static void vortex_Vort3D_connect(vortex_t * v, int en) { int i; // Disable AU8810 routes, since they seem to be wrong (in au8810.h). #ifdef CHIP_AU8810 return; #endif #if 1 /* Alloc Xtalk mixin resources */ v->mixxtlk[0] = vortex_adb_checkinout(v, v->fixed_res, en, VORTEX_RESOURCE_MIXIN); if (v->mixxtlk[0] < 0) { dev_warn(v->card->dev, "vortex_Vort3D: ERROR: not enough free mixer resources.\n"); return; } v->mixxtlk[1] = vortex_adb_checkinout(v, v->fixed_res, en, VORTEX_RESOURCE_MIXIN); if (v->mixxtlk[1] < 0) { dev_warn(v->card->dev, "vortex_Vort3D: ERROR: not enough free mixer resources.\n"); return; } #endif /* Connect A3D -> XTALK */ for (i = 0; i < 4; i++) { // 2 outputs per each A3D slice. vortex_route(v, en, 0x11, ADB_A3DOUT(i * 2), ADB_XTALKIN(i)); vortex_route(v, en, 0x11, ADB_A3DOUT(i * 2) + 1, ADB_XTALKIN(5 + i)); } #if 0 vortex_route(v, en, 0x11, ADB_XTALKOUT(0), ADB_EQIN(2)); vortex_route(v, en, 0x11, ADB_XTALKOUT(1), ADB_EQIN(3)); #else /* Connect XTalk -> mixer */ vortex_route(v, en, 0x11, ADB_XTALKOUT(0), ADB_MIXIN(v->mixxtlk[0])); vortex_route(v, en, 0x11, ADB_XTALKOUT(1), ADB_MIXIN(v->mixxtlk[1])); vortex_connection_mixin_mix(v, en, v->mixxtlk[0], v->mixplayb[0], 0); vortex_connection_mixin_mix(v, en, v->mixxtlk[1], v->mixplayb[1], 0); vortex_mix_setinputvolumebyte(v, v->mixplayb[0], v->mixxtlk[0], en ? MIX_DEFIGAIN : VOL_MIN); vortex_mix_setinputvolumebyte(v, v->mixplayb[1], v->mixxtlk[1], en ? MIX_DEFIGAIN : VOL_MIN); if (VORTEX_IS_QUAD(v)) { vortex_connection_mixin_mix(v, en, v->mixxtlk[0], v->mixplayb[2], 0); vortex_connection_mixin_mix(v, en, v->mixxtlk[1], v->mixplayb[3], 0); vortex_mix_setinputvolumebyte(v, v->mixplayb[2], v->mixxtlk[0], en ? MIX_DEFIGAIN : VOL_MIN); vortex_mix_setinputvolumebyte(v, v->mixplayb[3], v->mixxtlk[1], en ? MIX_DEFIGAIN : VOL_MIN); } #endif } /* Initialize one single A3D source. */ static void vortex_Vort3D_InitializeSource(a3dsrc_t *a, int en, vortex_t *v) { if (a->vortex == NULL) { dev_warn(v->card->dev, "Vort3D_InitializeSource: A3D source not initialized\n"); return; } if (en) { a3dsrc_ProgramPipe(a); a3dsrc_SetA3DSampleRate(a, 0x11); a3dsrc_SetTimeConsts(a, HrtfTCDefault, ItdTCDefault, GainTCDefault, CoefTCDefault); /* Remark: zero gain is muted. */ //a3dsrc_SetGainTarget(a,0,0); //a3dsrc_SetGainCurrent(a,0,0); a3dsrc_EnableA3D(a); } else { a3dsrc_DisableA3D(a); a3dsrc_ZeroState(a); } } /* Conversion of coordinates into 3D parameters. */ static void vortex_a3d_coord2hrtf(a3d_Hrtf_t hrtf, int *coord) { /* FIXME: implement this. */ } static void vortex_a3d_coord2itd(a3d_Itd_t itd, int *coord) { /* FIXME: implement this. */ } static void vortex_a3d_coord2ild(a3d_LRGains_t ild, int left, int right) { /* FIXME: implement this. */ } static void vortex_a3d_translate_filter(a3d_atmos_t filter, int *params) { /* FIXME: implement this. */ } /* ALSA control interface. */ static int snd_vortex_a3d_hrtf_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 6; uinfo->value.integer.min = 0x00000000; uinfo->value.integer.max = 0xffffffff; return 0; } static int snd_vortex_a3d_itd_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0x00000000; uinfo->value.integer.max = 0xffffffff; return 0; } static int snd_vortex_a3d_ild_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0x00000000; uinfo->value.integer.max = 0xffffffff; return 0; } static int snd_vortex_a3d_filter_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 4; uinfo->value.integer.min = 0x00000000; uinfo->value.integer.max = 0xffffffff; return 0; } static int snd_vortex_a3d_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { //a3dsrc_t *a = kcontrol->private_data; /* No read yet. Would this be really useable/needed ? */ return 0; } static int snd_vortex_a3d_hrtf_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { a3dsrc_t *a = kcontrol->private_data; int i; int coord[6]; for (i = 0; i < 6; i++) coord[i] = ucontrol->value.integer.value[i]; /* Translate orientation coordinates to a3d params. */ vortex_a3d_coord2hrtf(a->hrtf[0], coord); vortex_a3d_coord2hrtf(a->hrtf[1], coord); a3dsrc_SetHrtfTarget(a, a->hrtf[0], a->hrtf[1]); a3dsrc_SetHrtfCurrent(a, a->hrtf[0], a->hrtf[1]); return 1; } static int snd_vortex_a3d_itd_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { a3dsrc_t *a = kcontrol->private_data; int coord[6]; int i; for (i = 0; i < 6; i++) coord[i] = ucontrol->value.integer.value[i]; /* Translate orientation coordinates to a3d params. */ vortex_a3d_coord2itd(a->hrtf[0], coord); vortex_a3d_coord2itd(a->hrtf[1], coord); /* Inter aural time difference. */ a3dsrc_SetItdTarget(a, a->itd[0], a->itd[1]); a3dsrc_SetItdCurrent(a, a->itd[0], a->itd[1]); a3dsrc_SetItdDline(a, a->dline); return 1; } static int snd_vortex_a3d_ild_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { a3dsrc_t *a = kcontrol->private_data; int l, r; /* There may be some scale tranlation needed here. */ l = ucontrol->value.integer.value[0]; r = ucontrol->value.integer.value[1]; vortex_a3d_coord2ild(a->ild, l, r); /* Left Right panning. */ a3dsrc_SetGainTarget(a, l, r); a3dsrc_SetGainCurrent(a, l, r); return 1; } static int snd_vortex_a3d_filter_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { a3dsrc_t *a = kcontrol->private_data; int i; int params[6]; for (i = 0; i < 6; i++) params[i] = ucontrol->value.integer.value[i]; /* Translate generic filter params to a3d filter params. */ vortex_a3d_translate_filter(a->filter, params); /* Atmospheric absorption and filtering. */ a3dsrc_SetAtmosTarget(a, a->filter[0], a->filter[1], a->filter[2], a->filter[3], a->filter[4]); a3dsrc_SetAtmosCurrent(a, a->filter[0], a->filter[1], a->filter[2], a->filter[3], a->filter[4]); return 1; } static const struct snd_kcontrol_new vortex_a3d_kcontrol = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = "Playback PCM advanced processing", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .info = snd_vortex_a3d_hrtf_info, .get = snd_vortex_a3d_get, .put = snd_vortex_a3d_hrtf_put, }; /* Control (un)registration. */ static int vortex_a3d_register_controls(vortex_t *vortex) { struct snd_kcontrol *kcontrol; int err, i; /* HRTF controls. */ for (i = 0; i < NR_A3D; i++) { kcontrol = snd_ctl_new1(&vortex_a3d_kcontrol, &vortex->a3d[i]); if (!kcontrol) return -ENOMEM; kcontrol->id.numid = CTRLID_HRTF; kcontrol->info = snd_vortex_a3d_hrtf_info; kcontrol->put = snd_vortex_a3d_hrtf_put; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; } /* ITD controls. */ for (i = 0; i < NR_A3D; i++) { kcontrol = snd_ctl_new1(&vortex_a3d_kcontrol, &vortex->a3d[i]); if (!kcontrol) return -ENOMEM; kcontrol->id.numid = CTRLID_ITD; kcontrol->info = snd_vortex_a3d_itd_info; kcontrol->put = snd_vortex_a3d_itd_put; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; } /* ILD (gains) controls. */ for (i = 0; i < NR_A3D; i++) { kcontrol = snd_ctl_new1(&vortex_a3d_kcontrol, &vortex->a3d[i]); if (!kcontrol) return -ENOMEM; kcontrol->id.numid = CTRLID_GAINS; kcontrol->info = snd_vortex_a3d_ild_info; kcontrol->put = snd_vortex_a3d_ild_put; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; } /* Filter controls. */ for (i = 0; i < NR_A3D; i++) { kcontrol = snd_ctl_new1(&vortex_a3d_kcontrol, &vortex->a3d[i]); if (!kcontrol) return -ENOMEM; kcontrol->id.numid = CTRLID_FILTER; kcontrol->info = snd_vortex_a3d_filter_info; kcontrol->put = snd_vortex_a3d_filter_put; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; } return 0; } static void vortex_a3d_unregister_controls(vortex_t * vortex) { } /* End of File*/
linux-master
sound/pci/au88x0/au88x0_a3d.c
// SPDX-License-Identifier: GPL-2.0-or-later /* */ /* Vortex core low level functions. Author: Manuel Jander ([email protected]) These functions are mainly the result of translations made from the original disassembly of the au88x0 binary drivers, written by Aureal before they went down. Many thanks to the Jeff Muizelaar, Kester Maddock, and whoever contributed to the OpenVortex project. The author of this file, put the few available pieces together and translated the rest of the riddle (Mix, Src and connection stuff). Some things are still to be discovered, and their meanings are unclear. Some of these functions aren't intended to be really used, rather to help to understand how does the AU88X0 chips work. Keep them in, because they could be used somewhere in the future. This code hasn't been tested or proof read thoroughly. If you wanna help, take a look at the AU88X0 assembly and check if this matches. Functions tested ok so far are (they show the desired effect at least): vortex_routes(); (1 bug fixed). vortex_adb_addroute(); vortex_adb_addroutes(); vortex_connect_codecplay(); vortex_src_flushbuffers(); vortex_adbdma_setmode(); note: still some unknown arguments! vortex_adbdma_startfifo(); vortex_adbdma_stopfifo(); vortex_fifo_setadbctrl(); note: still some unknown arguments! vortex_mix_setinputvolumebyte(); vortex_mix_enableinput(); vortex_mixer_addWTD(); (fixed) vortex_connection_adbdma_src_src(); vortex_connection_adbdma_src(); vortex_src_change_convratio(); vortex_src_addWTD(); (fixed) History: 01-03-2003 First revision. 01-21-2003 Some bug fixes. 17-02-2003 many bugfixes after a big versioning mess. 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy ! (2 hours later...) I cant believe it! Im really lucky today. Now the SRC is working too! Yeah! XMMS works ! 20-02-2003 First steps into the ALSA world. 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really work :-). It was all wrong. 12-03-2003 ALSA driver starts working (2 channels). 16-03-2003 More srcblock_setupchannel discoveries. 12-04-2003 AU8830 playback support. Recording in the works. 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording works now, but chipn' dale effect is still there. 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely into au88x0_pcm.c . 06-06-2003 Buffer shifter bugfix. Mixer volume fix. 07-12-2003 A3D routing finally fixed. Believed to be OK. 25-03-2004 Many thanks to Claudia, for such valuable bug reports. */ #include "au88x0.h" #include "au88x0_a3d.h" #include <linux/delay.h> /* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */ // FIXME: get rid of this. static int mchannels[NR_MIXIN]; static int rampchs[NR_MIXIN]; static void vortex_mixer_en_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_MIXER_SR, hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); } static void vortex_mixer_dis_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_MIXER_SR, hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); } #if 0 static void vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix, unsigned char channel) { hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel), 0x80); hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel), 0x80); } static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix) { int a; a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff; //FP2LinearFrac(a); return (a); } static int vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix, int channel, int *vol) { int a; if (!(mchannels[mix] & (1 << channel))) return 0; a = hwread(vortex->mmio, VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2)); /* if (rampchs[mix] == 0) a = FP2LinearFrac(a); else a = FP2LinearFracWT(a); */ *vol = a; return (0); } static unsigned int vortex_mix_boost6db(unsigned char vol) { return (vol + 8); /* WOW! what a complex function! */ } static void vortex_mix_rampvolume(vortex_t * vortex, int mix) { int ch; char a; // This function is intended for ramping down only (see vortex_disableinput()). for (ch = 0; ch < 0x20; ch++) { if (((1 << ch) & rampchs[mix]) == 0) continue; a = hwread(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2)); if (a > -126) { a -= 2; hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + (((mix << 5) + ch) << 2), a); hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2), a); } else vortex_mix_killinput(vortex, mix, ch); } } static int vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin) { int addr, temp; if (mixin >= 0) addr = mixin; else addr = mixin + 3; addr = ((mix << 3) + (addr >> 2)) << 2; temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); return ((temp >> (mixin & 3)) & 1); } #endif static void vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix, unsigned char vol) { int temp; hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol); if (1) { /*if (this_10) */ temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2)); if ((temp != 0x80) || (vol == 0x80)) return; } hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol); } static void vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix, int mixin, unsigned char vol) { int temp; hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol); if (1) { /* this_10, initialized to 1. */ temp = hwread(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2)); if ((temp != 0x80) || (vol == 0x80)) return; } hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol); } static void vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en) { int temp, addr; if (mixin < 0) addr = (mixin + 3); else addr = mixin; addr = ((mix << 3) + (addr >> 2)) << 2; temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); if (en) temp |= (1 << (mixin & 3)); else temp &= ~(1 << (mixin & 3)); /* Mute input. Astatic void crackling? */ hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80); /* Looks like clear buffer. */ hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0); hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0); /* Write enable bit. */ hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp); } static void vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin) { rampchs[mix] &= ~(1 << mixin); vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); mchannels[mix] &= ~(1 << mixin); vortex_mix_setenablebit(vortex, mix, mixin, 0); } static void vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin) { vortex_mix_killinput(vortex, mix, mixin); if ((mchannels[mix] & (1 << mixin)) == 0) { vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */ mchannels[mix] |= (1 << mixin); } vortex_mix_setenablebit(vortex, mix, mixin, 1); } static void vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel, int ramp) { if (ramp) { rampchs[mix] |= (1 << channel); // Register callback. //vortex_mix_startrampvolume(vortex); vortex_mix_killinput(vortex, mix, channel); } else vortex_mix_killinput(vortex, mix, channel); } static int vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch) { int temp, lifeboat = 0, prev; temp = hwread(vortex->mmio, VORTEX_MIXER_SR); if ((temp & (1 << ch)) == 0) { hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix); vortex_mixer_en_sr(vortex, ch); return 1; } prev = VORTEX_MIXER_CHNBASE + (ch << 2); temp = hwread(vortex->mmio, prev); while (temp & 0x10) { prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2); temp = hwread(vortex->mmio, prev); //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp); if ((++lifeboat) > 0xf) { dev_err(vortex->card->dev, "vortex_mixer_addWTD: lifeboat overflow\n"); return 0; } } hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix); hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); return 1; } static int vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch) { int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0; //int esp1f=edi(while)=src, esp10=ch; eax = hwread(vortex->mmio, VORTEX_MIXER_SR); if (((1 << ch) & eax) == 0) { dev_err(vortex->card->dev, "mix ALARM %x\n", eax); return 0; } ebp = VORTEX_MIXER_CHNBASE + (ch << 2); esp18 = hwread(vortex->mmio, ebp); if (esp18 & 0x10) { ebx = (esp18 & 0xf); if (mix == ebx) { ebx = VORTEX_MIXER_RTBASE + (mix << 2); edx = hwread(vortex->mmio, ebx); //7b60 hwwrite(vortex->mmio, ebp, edx); hwwrite(vortex->mmio, ebx, 0); } else { //7ad3 edx = hwread(vortex->mmio, VORTEX_MIXER_RTBASE + (ebx << 2)); //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); while ((edx & 0xf) != mix) { if ((esi) > 0xf) { dev_err(vortex->card->dev, "mixdelWTD: error lifeboat overflow\n"); return 0; } esp14 = ebx; ebx = edx & 0xf; ebp = ebx << 2; edx = hwread(vortex->mmio, VORTEX_MIXER_RTBASE + ebp); //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx); esi++; } //7b30 ebp = ebx << 2; if (edx & 0x10) { /* Delete entry in between others */ ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2); edx = hwread(vortex->mmio, ebx); //7b60 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ebp, edx); hwwrite(vortex->mmio, ebx, 0); //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); } else { /* Delete last entry */ //7b83 if (esp14 == -1) hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), esp18 & 0xef); else { ebx = (0xffffffe0 & edx) | (0xf & ebx); hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + (esp14 << 2), ebx); //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); } hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ebp, 0); return 1; } } } else { //printk(KERN_INFO "removed last mix\n"); //7be0 vortex_mixer_dis_sr(vortex, ch); hwwrite(vortex->mmio, ebp, 0); } return 1; } static void vortex_mixer_init(vortex_t * vortex) { u32 addr; int x; // FIXME: get rid of this crap. memset(mchannels, 0, NR_MIXOUT * sizeof(int)); memset(rampchs, 0, NR_MIXOUT * sizeof(int)); addr = VORTEX_MIX_SMP + 0x17c; for (x = 0x5f; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0); addr -= 4; } addr = VORTEX_MIX_ENIN + 0x1fc; for (x = 0x7f; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0); addr -= 4; } addr = VORTEX_MIX_SMP + 0x17c; for (x = 0x5f; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0); addr -= 4; } addr = VORTEX_MIX_INVOL_A + 0x7fc; for (x = 0x1ff; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0x80); addr -= 4; } addr = VORTEX_MIX_VOL_A + 0x3c; for (x = 0xf; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0x80); addr -= 4; } addr = VORTEX_MIX_INVOL_B + 0x7fc; for (x = 0x1ff; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0x80); addr -= 4; } addr = VORTEX_MIX_VOL_B + 0x3c; for (x = 0xf; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0x80); addr -= 4; } addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4; for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) { hwwrite(vortex->mmio, addr, 0x0); addr -= 4; } hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0); /* Set clipping ceiling (this may be all wrong). */ /* for (x = 0; x < 0x80; x++) { hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff); } */ /* call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____ Register ISR callback for volume smooth fade out. Maybe this avoids clicks when press "stop" ? */ } /* SRC (CAsp4Src.s and CAsp4SrcBlock) */ static void vortex_src_en_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel)); } static void vortex_src_dis_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel)); } static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src) { int i; for (i = 0x1f; i >= 0; i--) hwwrite(vortex->mmio, VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0); hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0); hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0); } static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src) { hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0); hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); } static void vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en) { int temp; temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE); if (en) temp |= 1 << src; else temp &= ~(1 << src); hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp); } static int vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio) { int temp, lifeboat = 0; do { hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio); temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); if ((++lifeboat) > 0x9) { dev_err(vortex->card->dev, "Src cvr fail\n"); break; } } while (temp != ratio); return temp; } #if 0 static void vortex_src_slowlock(vortex_t * vortex, unsigned char src) { int temp; hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); if (temp & 0x200) hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), temp & ~0x200L); } static void vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio) { int temp, a; if ((ratio & 0x10000) && (ratio != 0x10000)) { if (ratio & 0x3fff) a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1; else a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2; } else a = 0xc; temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); if (((temp >> 4) & 0xf) != a) hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), (temp & 0xf) | ((a & 0xf) << 4)); vortex_src_persist_convratio(vortex, src, ratio); } static int vortex_src_checkratio(vortex_t * vortex, unsigned char src, unsigned int desired_ratio) { int hw_ratio, lifeboat = 0; hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); while (hw_ratio != desired_ratio) { hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio); if ((lifeboat++) > 15) { pr_err( "Vortex: could not set src-%d from %d to %d\n", src, hw_ratio, desired_ratio); break; } } return hw_ratio; } #endif /* Objective: Set samplerate for given SRC module. Arguments: card: pointer to vortex_t strcut. src: Integer index of the SRC module. cr: Current sample rate conversion factor. b: unknown 16 bit value. sweep: Enable Samplerate fade from cr toward tr flag. dirplay: 1: playback, 0: recording. sl: Slow Lock flag. tr: Target samplerate conversion. thsource: Throttle source flag (no idea what that means). */ static void vortex_src_setupchannel(vortex_t * card, unsigned char src, unsigned int cr, unsigned int b, int sweep, int d, int dirplay, int sl, unsigned int tr, int thsource) { // noplayback: d=2,4,7,0xa,0xb when using first 2 src's. // c: enables pitch sweep. // looks like g is c related. Maybe g is a sweep parameter ? // g = cvr // dirplay: 0 = recording, 1 = playback // d = src hw index. int esi, ebp = 0, esp10; vortex_src_flushbuffers(card, src); if (sweep) { if ((tr & 0x10000) && (tr != 0x10000)) { tr = 0; esi = 0x7; } else { if ((((short)tr) < 0) && (tr != 0x8000)) { tr = 0; esi = 0x8; } else { tr = 1; esi = 0xc; } } } else { if ((cr & 0x10000) && (cr != 0x10000)) { tr = 0; /*ebx = 0 */ esi = 0x11 - ((cr >> 0xe) & 7); if (cr & 0x3fff) esi -= 1; else esi -= 2; } else { tr = 1; esi = 0xc; } } vortex_src_cleardrift(card, src); vortex_src_set_throttlesource(card, src, thsource); if ((dirplay == 0) && (sweep == 0)) { if (tr) esp10 = 0xf; else esp10 = 0xc; ebp = 0; } else { if (tr) ebp = 0xf; else ebp = 0xc; esp10 = 0; } hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2), (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d); /* 0xc0 esi=0xc c=f=0 d=0 */ vortex_src_persist_convratio(card, src, cr); hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff); /* 0 b=0 */ hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2), (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10); /* 0x30f00 e=g=1 esp10=0 ebp=f */ //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp); } static void vortex_srcblock_init(vortex_t * vortex) { u32 addr; int x; hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff); /* for (x=0; x<0x10; x++) { vortex_src_init(&vortex_src[x], x); } */ //addr = 0xcc3c; //addr = 0x26c3c; addr = VORTEX_SRC_RTBASE + 0x3c; for (x = 0xf; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0); addr -= 4; } //addr = 0xcc94; //addr = 0x26c94; addr = VORTEX_SRC_CHNBASE + 0x54; for (x = 0x15; x >= 0; x--) { hwwrite(vortex->mmio, addr, 0); addr -= 4; } } static int vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch) { int temp, lifeboat = 0, prev; // esp13 = src temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); if ((temp & (1 << ch)) == 0) { hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src); vortex_src_en_sr(vortex, ch); return 1; } prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */ temp = hwread(vortex->mmio, prev); //while (temp & NR_SRC) { while (temp & 0x10) { prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */ //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/ temp = hwread(vortex->mmio, prev); //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp); if ((++lifeboat) > 0xf) { dev_err(vortex->card->dev, "vortex_src_addWTD: lifeboat overflow\n"); return 0; } } hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src); //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC); hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); return 1; } static int vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch) { int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0; //int esp1f=edi(while)=src, esp10=ch; eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); if (((1 << ch) & eax) == 0) { dev_err(vortex->card->dev, "src alarm\n"); return 0; } ebp = VORTEX_SRC_CHNBASE + (ch << 2); esp18 = hwread(vortex->mmio, ebp); if (esp18 & 0x10) { ebx = (esp18 & 0xf); if (src == ebx) { ebx = VORTEX_SRC_RTBASE + (src << 2); edx = hwread(vortex->mmio, ebx); //7b60 hwwrite(vortex->mmio, ebp, edx); hwwrite(vortex->mmio, ebx, 0); } else { //7ad3 edx = hwread(vortex->mmio, VORTEX_SRC_RTBASE + (ebx << 2)); //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); while ((edx & 0xf) != src) { if ((esi) > 0xf) { dev_warn(vortex->card->dev, "srcdelWTD: error, lifeboat overflow\n"); return 0; } esp14 = ebx; ebx = edx & 0xf; ebp = ebx << 2; edx = hwread(vortex->mmio, VORTEX_SRC_RTBASE + ebp); //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx); esi++; } //7b30 ebp = ebx << 2; if (edx & 0x10) { /* Delete entry in between others */ ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2); edx = hwread(vortex->mmio, ebx); //7b60 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ebp, edx); hwwrite(vortex->mmio, ebx, 0); //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); } else { /* Delete last entry */ //7b83 if (esp14 == -1) hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), esp18 & 0xef); else { ebx = (0xffffffe0 & edx) | (0xf & ebx); hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + (esp14 << 2), ebx); //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); } hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ebp, 0); return 1; } } } else { //7be0 vortex_src_dis_sr(vortex, ch); hwwrite(vortex->mmio, ebp, 0); } return 1; } /*FIFO*/ static void vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x) { for (x--; x >= 0; x--) hwwrite(vortex->mmio, VORTEX_FIFO_ADBDATA + (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); } #if 0 static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j) { vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); #ifdef CHIP_AU8820 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); #else hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); #endif } #endif static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en) { hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) & 0xffffffef) | ((1 & en) << 4) | FIFO_U1); } static void vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int stereo, int priority, int empty, int valid, int f) { int temp, lifeboat = 0; //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */ int this_4 = 0x2; /* f seems priority related. * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1 * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority * is never called, thus the f related bits remain a mystery for now. */ do { temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); if (lifeboat++ > 0xbb8) { dev_err(vortex->card->dev, "vortex_fifo_setadbctrl fail\n"); break; } } while (temp & FIFO_RDONLY); // AU8830 semes to take some special care about fifo content (data). // But i'm just to lazy to translate that :) if (valid) { if ((temp & FIFO_VALID) == 0) { //this_8[fifo] = 0; vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4 #ifdef CHIP_AU8820 temp = (this_4 & 0x1f) << 0xb; #else temp = (this_4 & 0x3f) << 0xc; #endif temp = (temp & 0xfffffffd) | ((stereo & 1) << 1); temp = (temp & 0xfffffff3) | ((priority & 3) << 2); temp = (temp & 0xffffffef) | ((valid & 1) << 4); temp |= FIFO_U1; temp = (temp & 0xffffffdf) | ((empty & 1) << 5); #ifdef CHIP_AU8820 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12); #endif #ifdef CHIP_AU8830 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b); temp = (temp & 0xefffffff) | ((f & 1) << 0x1c); #endif #ifdef CHIP_AU8810 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18); temp = (temp & 0xfdffffff) | ((f & 1) << 0x19); #endif } } else { if (temp & FIFO_VALID) { #ifdef CHIP_AU8820 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); #endif #ifdef CHIP_AU8830 temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; #endif #ifdef CHIP_AU8810 temp = ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS; #endif } else /*if (this_8[fifo]) */ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); } hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp); hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); } #ifndef CHIP_AU8810 static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x) { if (x < 1) return; for (x--; x >= 0; x--) hwwrite(vortex->mmio, VORTEX_FIFO_WTDATA + (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); } static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j) { vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); #ifdef CHIP_AU8820 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); #else hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); #endif } static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en) { hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) & 0xffffffef) | ((en & 1) << 4) | FIFO_U1); } static void vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority, int empty, int valid, int f) { int temp = 0, lifeboat = 0; int this_4 = 2; do { temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); if (lifeboat++ > 0xbb8) { dev_err(vortex->card->dev, "vortex_fifo_setwtctrl fail\n"); break; } } while (temp & FIFO_RDONLY); if (valid) { if ((temp & FIFO_VALID) == 0) { vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4 #ifdef CHIP_AU8820 temp = (this_4 & 0x1f) << 0xb; #else temp = (this_4 & 0x3f) << 0xc; #endif temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); temp = (temp & 0xfffffff3) | ((priority & 3) << 2); temp = (temp & 0xffffffef) | ((valid & 1) << 4); temp |= FIFO_U1; temp = (temp & 0xffffffdf) | ((empty & 1) << 5); #ifdef CHIP_AU8820 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12); #endif #ifdef CHIP_AU8830 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b); temp = (temp & 0xefffffff) | ((f & 1) << 0x1c); #endif #ifdef CHIP_AU8810 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18); temp = (temp & 0xfdffffff) | ((f & 1) << 0x19); #endif } } else { if (temp & FIFO_VALID) { #ifdef CHIP_AU8820 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); #endif #ifdef CHIP_AU8830 temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; #endif #ifdef CHIP_AU8810 temp = ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS; #endif } else /*if (this_8[fifo]) */ vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); } hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); /* do { temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); if (lifeboat++ > 0xbb8) { pr_err( "Vortex: vortex_fifo_setwtctrl fail (hanging)\n"); break; } } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF)); if (valid) { if (temp & FIFO_VALID) { temp = 0x40000; //temp |= 0x08000000; //temp |= 0x10000000; //temp |= 0x04000000; //temp |= 0x00400000; temp |= 0x1c400000; temp &= 0xFFFFFFF3; temp &= 0xFFFFFFEF; temp |= (valid & 1) << 4; hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); return; } else { vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); return; } } else { temp &= 0xffffffef; temp |= 0x08000000; temp |= 0x10000000; temp |= 0x04000000; temp |= 0x00400000; hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); //((temp >> 6) & 0x3f) priority = 0; if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0) vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); valid = 0xfb; temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); temp = (temp & 0xfffdffff) | ((f & 1) << 0x11); temp = (temp & 0xfffffff3) | ((priority & 3) << 2); temp = (temp & 0xffffffef) | ((valid & 1) << 4); temp = (temp & 0xffffffdf) | ((empty & 1) << 5); hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); } */ /* temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); temp = (temp & 0xfffdffff) | ((f & 1) << 0x11); temp = (temp & 0xfffffff3) | ((priority & 3) << 2); temp = (temp & 0xffffffef) | ((valid & 1) << 4); temp = (temp & 0xffffffdf) | ((empty & 1) << 5); #ifdef FIFO_BITS temp = temp | FIFO_BITS | 40000; #endif // 0x1c440010, 0x1c400000 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); */ } #endif static void vortex_fifo_init(vortex_t * vortex) { int x; u32 addr; /* ADB DMA channels fifos. */ addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4); for (x = NR_ADB - 1; x >= 0; x--) { hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1)); if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1)) dev_err(vortex->card->dev, "bad adb fifo reset!\n"); vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); addr -= 4; } #ifndef CHIP_AU8810 /* WT DMA channels fifos. */ addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4); for (x = NR_WT - 1; x >= 0; x--) { hwwrite(vortex->mmio, addr, FIFO_U0); if (hwread(vortex->mmio, addr) != FIFO_U0) dev_err(vortex->card->dev, "bad wt fifo reset (0x%08x, 0x%08x)!\n", addr, hwread(vortex->mmio, addr)); vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE); addr -= 4; } #endif /* trigger... */ #ifdef CHIP_AU8820 hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b #else #ifdef CHIP_AU8830 hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */ hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */ #endif hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */ #endif } /* ADBDMA */ static void vortex_adbdma_init(vortex_t * vortex) { } static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); } static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb) { stream_t *dma = &vortex->dma_adb[adbdma]; //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2)))); hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << ((0xf - (adbdma & 0xf)) * 2)); dma->period_real = dma->period_virt = sb; } static void vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma, int psize, int count) { stream_t *dma = &vortex->dma_adb[adbdma]; dma->period_bytes = psize; dma->nr_periods = count; dma->cfg0 = 0; dma->cfg1 = 0; switch (count) { /* Four or more pages */ default: case 4: dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc, snd_pcm_sgbuf_get_addr(dma->substream, psize * 3)); fallthrough; /* 3 pages */ case 3: dma->cfg0 |= 0x12000000; dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8, snd_pcm_sgbuf_get_addr(dma->substream, psize * 2)); fallthrough; /* 2 pages */ case 2: dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4, snd_pcm_sgbuf_get_addr(dma->substream, psize)); fallthrough; /* 1 page */ case 1: dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (adbdma << 4), snd_pcm_sgbuf_get_addr(dma->substream, 0)); break; } /* pr_debug( "vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", dma->cfg0, dma->cfg1); */ hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1); vortex_adbdma_setfirstbuffer(vortex, adbdma); vortex_adbdma_setstartbuffer(vortex, adbdma, 0); } static void vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir, int fmt, int stereo, u32 offset) { stream_t *dma = &vortex->dma_adb[adbdma]; dma->dma_unknown = stereo; dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); /* Enable PCMOUT interrupts. */ dma->dma_ctrl = (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); dma->dma_ctrl = (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK); dma->dma_ctrl = (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2)); } static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int page, p, pp, delta, i; page = (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; if (dma->nr_periods >= 4) delta = (page - dma->period_real) & 3; else { delta = (page - dma->period_real); if (delta < 0) delta += dma->nr_periods; } if (delta == 0) return 0; /* refresh hw page table */ if (dma->nr_periods > 4) { for (i = 0; i < delta; i++) { /* p: audio buffer page index */ p = dma->period_virt + i + 4; if (p >= dma->nr_periods) p -= dma->nr_periods; /* pp: hardware DMA page index. */ pp = dma->period_real + i; if (pp >= 4) pp -= 4; //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr); hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2), snd_pcm_sgbuf_get_addr(dma->substream, dma->period_bytes * p)); /* Force write thru cache. */ hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2)); } } dma->period_virt += delta; dma->period_real = page; if (dma->period_virt >= dma->nr_periods) dma->period_virt -= dma->nr_periods; if (delta != 1) dev_info(vortex->card->dev, "%d virt=%d, real=%d, delta=%d\n", adbdma, dma->period_virt, dma->period_real, delta); return delta; } static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int p, pp, i; /* refresh hw page table */ for (i=0 ; i < 4 && i < dma->nr_periods; i++) { /* p: audio buffer page index */ p = dma->period_virt + i; if (p >= dma->nr_periods) p -= dma->nr_periods; /* pp: hardware DMA page index. */ pp = dma->period_real + i; if (dma->nr_periods < 4) { if (pp >= dma->nr_periods) pp -= dma->nr_periods; } else { if (pp >= 4) pp -= 4; } hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2), snd_pcm_sgbuf_get_addr(dma->substream, dma->period_bytes * p)); /* Force write thru cache. */ hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2)); } } static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int temp, page, delta; temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; if (dma->nr_periods >= 4) delta = (page - dma->period_real) & 3; else { delta = (page - dma->period_real); if (delta < 0) delta += dma->nr_periods; } return (dma->period_virt + delta) * dma->period_bytes + (temp & (dma->period_bytes - 1)); } static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma) { int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ; stream_t *dma = &vortex->dma_adb[adbdma]; switch (dma->fifo_status) { case FIFO_START: vortex_fifo_setadbvalid(vortex, adbdma, dma->fifo_enabled ? 1 : 0); break; case FIFO_STOP: this_8 = 1; hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; case FIFO_PAUSE: vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; } dma->fifo_status = FIFO_START; } static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int this_8 = 1, this_4 = 0; switch (dma->fifo_status) { case FIFO_STOP: hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; case FIFO_PAUSE: vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; } dma->fifo_status = FIFO_START; } static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int this_8 = 0, this_4 = 0; switch (dma->fifo_status) { case FIFO_START: vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); break; case FIFO_STOP: hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); break; } dma->fifo_status = FIFO_PAUSE; } static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma) { stream_t *dma = &vortex->dma_adb[adbdma]; int this_4 = 0, this_8 = 0; if (dma->fifo_status == FIFO_START) vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); else if (dma->fifo_status == FIFO_STOP) return; dma->fifo_status = FIFO_STOP; dma->fifo_enabled = 0; } /* WTDMA */ #ifndef CHIP_AU8810 static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma) { //int this_7c=dma_ctrl; stream_t *dma = &vortex->dma_wt[wtdma]; hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); } static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb) { stream_t *dma = &vortex->dma_wt[wtdma]; //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2))); hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0xf - (wtdma & 0xf)) * 2)); dma->period_real = dma->period_virt = sb; } static void vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma, int psize, int count) { stream_t *dma = &vortex->dma_wt[wtdma]; dma->period_bytes = psize; dma->nr_periods = count; dma->cfg0 = 0; dma->cfg1 = 0; switch (count) { /* Four or more pages */ default: case 4: dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1); hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc, snd_pcm_sgbuf_get_addr(dma->substream, psize * 3)); fallthrough; /* 3 pages */ case 3: dma->cfg0 |= 0x12000000; dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8, snd_pcm_sgbuf_get_addr(dma->substream, psize * 2)); fallthrough; /* 2 pages */ case 2: dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1); hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4, snd_pcm_sgbuf_get_addr(dma->substream, psize)); fallthrough; /* 1 page */ case 1: dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4), snd_pcm_sgbuf_get_addr(dma->substream, 0)); break; } hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); vortex_wtdma_setfirstbuffer(vortex, wtdma); vortex_wtdma_setstartbuffer(vortex, wtdma, 0); } static void vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d, /*int e, */ u32 offset) { stream_t *dma = &vortex->dma_wt[wtdma]; //dma->this_08 = e; dma->dma_unknown = d; dma->dma_ctrl = 0; dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); /* PCMOUT interrupt */ dma->dma_ctrl = (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); /* Always playback. */ dma->dma_ctrl |= (1 << DIR_SHIFT); /* Audio Format */ dma->dma_ctrl = (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); /* Write into hardware */ hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); } static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int page, p, pp, delta, i; page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK; if (dma->nr_periods >= 4) delta = (page - dma->period_real) & 3; else { delta = (page - dma->period_real); if (delta < 0) delta += dma->nr_periods; } if (delta == 0) return 0; /* refresh hw page table */ if (dma->nr_periods > 4) { for (i = 0; i < delta; i++) { /* p: audio buffer page index */ p = dma->period_virt + i + 4; if (p >= dma->nr_periods) p -= dma->nr_periods; /* pp: hardware DMA page index. */ pp = dma->period_real + i; if (pp >= 4) pp -= 4; hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (((wtdma << 2) + pp) << 2), snd_pcm_sgbuf_get_addr(dma->substream, dma->period_bytes * p)); /* Force write thru cache. */ hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE + (((wtdma << 2) + pp) << 2)); } } dma->period_virt += delta; if (dma->period_virt >= dma->nr_periods) dma->period_virt -= dma->nr_periods; dma->period_real = page; if (delta != 1) dev_warn(vortex->card->dev, "wt virt = %d, delta = %d\n", dma->period_virt, delta); return delta; } #if 0 static void vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos) { int temp; temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK; *pos = temp & POS_MASK; } static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma) { return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> POS_SHIFT) & POS_MASK); } #endif static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int temp; temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1)); return temp; } static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int this_8 = 0, this_4 = 0; switch (dma->fifo_status) { case FIFO_START: vortex_fifo_setwtvalid(vortex, wtdma, dma->fifo_enabled ? 1 : 0); break; case FIFO_STOP: this_8 = 1; hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; case FIFO_PAUSE: vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; } dma->fifo_status = FIFO_START; } static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int this_8 = 0, this_4 = 0; switch (dma->fifo_status) { case FIFO_STOP: hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; case FIFO_PAUSE: vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, dma->fifo_enabled ? 1 : 0, 0); break; } dma->fifo_status = FIFO_START; } static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int this_8 = 0, this_4 = 0; switch (dma->fifo_status) { case FIFO_START: vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); break; case FIFO_STOP: hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); break; } dma->fifo_status = FIFO_PAUSE; } static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma) { stream_t *dma = &vortex->dma_wt[wtdma]; int this_4 = 0, this_8 = 0; if (dma->fifo_status == FIFO_START) vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); else if (dma->fifo_status == FIFO_STOP) return; dma->fifo_status = FIFO_STOP; dma->fifo_enabled = 0; } #endif /* ADB Routes */ typedef int ADBRamLink; static void vortex_adb_init(vortex_t * vortex) { int i; /* it looks like we are writing more than we need to... * if we write what we are supposed to it breaks things... */ hwwrite(vortex->mmio, VORTEX_ADB_SR, 0); for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++) hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2), hwread(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK); for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) { hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2), hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK); } } static void vortex_adb_en_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_ADB_SR, hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel)); } static void vortex_adb_dis_sr(vortex_t * vortex, int channel) { hwwrite(vortex->mmio, VORTEX_ADB_SR, hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel)); } static void vortex_adb_addroutes(vortex_t * vortex, unsigned char channel, ADBRamLink * route, int rnum) { int temp, prev, lifeboat = 0; if ((rnum <= 0) || (route == NULL)) return; /* Write last routes. */ rnum--; hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2), ROUTE_MASK); while (rnum > 0) { hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]); rnum--; } /* Write first route. */ temp = hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; if (temp == ADB_MASK) { /* First entry on this channel. */ hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), route[0]); vortex_adb_en_sr(vortex, channel); return; } /* Not first entry on this channel. Need to link. */ do { prev = temp; temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK; if ((lifeboat++) > ADB_MASK) { dev_err(vortex->card->dev, "vortex_adb_addroutes: unending route! 0x%x\n", *route); return; } } while (temp != ADB_MASK); hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]); } static void vortex_adb_delroutes(vortex_t * vortex, unsigned char channel, ADBRamLink route0, ADBRamLink route1) { int temp, lifeboat = 0, prev; /* Find route. */ temp = hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; if (temp == (route0 & ADB_MASK)) { temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2)); if ((temp & ADB_MASK) == ADB_MASK) vortex_adb_dis_sr(vortex, channel); hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), temp); return; } do { prev = temp; temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK; if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) { dev_err(vortex->card->dev, "vortex_adb_delroutes: route not found! 0x%x\n", route0); return; } } while (temp != (route0 & ADB_MASK)); temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); if ((temp & ADB_MASK) == route1) temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); /* Make bridge over deleted route. */ hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp); } static void vortex_route(vortex_t * vortex, int en, unsigned char channel, unsigned char source, unsigned char dest) { ADBRamLink route; route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); if (en) { vortex_adb_addroutes(vortex, channel, &route, 1); if ((source < (OFFSET_SRCOUT + NR_SRC)) && (source >= OFFSET_SRCOUT)) vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), channel); else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) && (source >= OFFSET_MIXOUT)) vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); } else { vortex_adb_delroutes(vortex, channel, route, route); if ((source < (OFFSET_SRCOUT + NR_SRC)) && (source >= OFFSET_SRCOUT)) vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) && (source >= OFFSET_MIXOUT)) vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); } } #if 0 static void vortex_routes(vortex_t * vortex, int en, unsigned char channel, unsigned char source, unsigned char dest0, unsigned char dest1) { ADBRamLink route[2]; route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK); route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK); if (en) { vortex_adb_addroutes(vortex, channel, route, 2); if ((source < (OFFSET_SRCOUT + NR_SRC)) && (source >= (OFFSET_SRCOUT))) vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), channel); else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) && (source >= (OFFSET_MIXOUT))) vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); } else { vortex_adb_delroutes(vortex, channel, route[0], route[1]); if ((source < (OFFSET_SRCOUT + NR_SRC)) && (source >= (OFFSET_SRCOUT))) vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) && (source >= (OFFSET_MIXOUT))) vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); } } #endif /* Route two sources to same target. Sources must be of same class !!! */ static void vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch, unsigned char source0, unsigned char source1, unsigned char dest) { ADBRamLink route[2]; route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); if (dest < 0x10) route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */ if (en) { vortex_adb_addroutes(vortex, ch, route, 2); if ((source0 < (OFFSET_SRCOUT + NR_SRC)) && (source0 >= OFFSET_SRCOUT)) { vortex_src_addWTD(vortex, (source0 - OFFSET_SRCOUT), ch); vortex_src_addWTD(vortex, (source1 - OFFSET_SRCOUT), ch); } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT)) && (source0 >= OFFSET_MIXOUT)) { vortex_mixer_addWTD(vortex, (source0 - OFFSET_MIXOUT), ch); vortex_mixer_addWTD(vortex, (source1 - OFFSET_MIXOUT), ch); } } else { vortex_adb_delroutes(vortex, ch, route[0], route[1]); if ((source0 < (OFFSET_SRCOUT + NR_SRC)) && (source0 >= OFFSET_SRCOUT)) { vortex_src_delWTD(vortex, (source0 - OFFSET_SRCOUT), ch); vortex_src_delWTD(vortex, (source1 - OFFSET_SRCOUT), ch); } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT)) && (source0 >= OFFSET_MIXOUT)) { vortex_mixer_delWTD(vortex, (source0 - OFFSET_MIXOUT), ch); vortex_mixer_delWTD(vortex, (source1 - OFFSET_MIXOUT), ch); } } } /* Connection stuff */ // Connect adbdma to src('s). static void vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch, unsigned char adbdma, unsigned char src) { vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src)); } // Connect SRC to mixin. static void vortex_connection_src_mixin(vortex_t * vortex, int en, unsigned char channel, unsigned char src, unsigned char mixin) { vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin)); } // Connect mixin with mix output. static void vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin, unsigned char mix, int a) { if (en) { vortex_mix_enableinput(vortex, mix, mixin); vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code. } else vortex_mix_disableinput(vortex, mix, mixin, a); } // Connect absolut address to mixin. static void vortex_connection_adb_mixin(vortex_t * vortex, int en, unsigned char channel, unsigned char source, unsigned char mixin) { vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin)); } static void vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch, unsigned char src, unsigned char adbdma) { vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma)); } static void vortex_connection_src_src_adbdma(vortex_t * vortex, int en, unsigned char ch, unsigned char src0, unsigned char src1, unsigned char adbdma) { vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1), ADB_DMA(adbdma)); } // mix to absolut address. static void vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch, unsigned char mix, unsigned char dest) { vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest); vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. } // mixer to src. static void vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch, unsigned char mix, unsigned char src) { vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src)); vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. } #if 0 static void vortex_connection_adbdma_src_src(vortex_t * vortex, int en, unsigned char channel, unsigned char adbdma, unsigned char src0, unsigned char src1) { vortex_routes(vortex, en, channel, ADB_DMA(adbdma), ADB_SRCIN(src0), ADB_SRCIN(src1)); } // Connect two mix to AdbDma. static void vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en, unsigned char ch, unsigned char mix0, unsigned char mix1, unsigned char adbdma) { ADBRamLink routes[2]; routes[0] = (((mix0 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK); routes[1] = (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma + 0x20) & ADB_MASK); if (en) { vortex_adb_addroutes(vortex, ch, routes, 0x2); vortex_mixer_addWTD(vortex, mix0, ch); vortex_mixer_addWTD(vortex, mix1, ch); } else { vortex_adb_delroutes(vortex, ch, routes[0], routes[1]); vortex_mixer_delWTD(vortex, mix0, ch); vortex_mixer_delWTD(vortex, mix1, ch); } } #endif /* CODEC connect. */ static void vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[]) { #ifdef CHIP_AU8820 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); #else #if 1 // Connect front channels through EQ. vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0)); vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1)); /* Lower volume, since EQ has some gain. */ vortex_mix_setvolumebyte(vortex, mixers[0], 0); vortex_mix_setvolumebyte(vortex, mixers[1], 0); vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0)); vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1)); /* Check if reg 0x28 has SDAC bit set. */ if (VORTEX_IS_QUAD(vortex)) { /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */ vortex_connection_mix_adb(vortex, en, 0x11, mixers[2], ADB_CODECOUT(0 + 4)); vortex_connection_mix_adb(vortex, en, 0x11, mixers[3], ADB_CODECOUT(1 + 4)); /* pr_debug( "SDAC detected "); */ } #else // Use plain direct output to codec. vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); #endif #endif } static void vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0, unsigned char mixin1) { /* Enable: 0x1, 0x1 Channel: 0x11, 0x11 ADB Source address: 0x48, 0x49 Destination Asp4Topology_0x9c,0x98 */ vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0); vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1); } // Higher level ADB audio path (de)allocator. /* Resource manager */ static const int resnum[VORTEX_RESOURCE_LAST] = { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D }; /* Checkout/Checkin resource of given type. resmap: resource map to be used. If NULL means that we want to allocate a DMA resource (root of all other resources of a dma channel). out: Mean checkout if != 0. Else mean Checkin resource. restype: Indicates type of resource to be checked in or out. */ static int vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype) { int i, qty = resnum[restype], resinuse = 0; if (out) { /* Gather used resources by all streams. */ for (i = 0; i < NR_ADB; i++) { resinuse |= vortex->dma_adb[i].resources[restype]; } resinuse |= vortex->fixed_res[restype]; /* Find and take free resource. */ for (i = 0; i < qty; i++) { if ((resinuse & (1 << i)) == 0) { if (resmap != NULL) resmap[restype] |= (1 << i); else vortex->dma_adb[i].resources[restype] |= (1 << i); /* pr_debug( "vortex: ResManager: type %d out %d\n", restype, i); */ return i; } } } else { if (resmap == NULL) return -EINVAL; /* Checkin first resource of type restype. */ for (i = 0; i < qty; i++) { if (resmap[restype] & (1 << i)) { resmap[restype] &= ~(1 << i); /* pr_debug( "vortex: ResManager: type %d in %d\n", restype, i); */ return i; } } } dev_err(vortex->card->dev, "FATAL: ResManager: resource type %d exhausted.\n", restype); return -ENOMEM; } /* Default Connections */ static void vortex_connect_default(vortex_t * vortex, int en) { // Connect AC97 codec. vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); if (VORTEX_IS_QUAD(vortex)) { vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); } vortex_connect_codecplay(vortex, en, vortex->mixplayb); vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1)); // Connect SPDIF #ifndef CHIP_AU8820 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0], ADB_SPDIFOUT(0)); vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1], ADB_SPDIFOUT(1)); #endif // Connect WT #ifndef CHIP_AU8810 vortex_wt_connect(vortex, en); #endif // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now. #ifndef CHIP_AU8820 vortex_Vort3D_connect(vortex, en); #endif // Connect I2S // Connect DSP interface for SQ3500 turbo (not here i think...) // Connect AC98 modem codec } /* Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes are deallocated. dma: DMA engine routes to be deallocated when dma >= 0. nr_ch: Number of channels to be de/allocated. dir: direction of stream. Uses same values as substream->stream. type: Type of audio output/source (codec, spdif, i2s, dsp, etc) Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0. */ static int vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir, int type, int subdev) { stream_t *stream; int i, en; struct pcm_vol *p; if (dma >= 0) { en = 0; vortex_adb_checkinout(vortex, vortex->dma_adb[dma].resources, en, VORTEX_RESOURCE_DMA); } else { en = 1; dma = vortex_adb_checkinout(vortex, NULL, en, VORTEX_RESOURCE_DMA); if (dma < 0) return -EBUSY; } stream = &vortex->dma_adb[dma]; stream->dma = dma; stream->dir = dir; stream->type = type; /* PLAYBACK ROUTES. */ if (dir == SNDRV_PCM_STREAM_PLAYBACK) { int src[4], mix[4], ch_top; #ifndef CHIP_AU8820 int a3d = 0; #endif /* Get SRC and MIXER hardware resources. */ if (stream->type != VORTEX_PCM_SPDIF) { for (i = 0; i < nr_ch; i++) { src[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_SRC); if (src[i] < 0) { memset(stream->resources, 0, sizeof(stream->resources)); return -EBUSY; } if (stream->type != VORTEX_PCM_A3D) { mix[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_MIXIN); if (mix[i] < 0) { memset(stream->resources, 0, sizeof(stream->resources)); return -EBUSY; } } } } #ifndef CHIP_AU8820 if (stream->type == VORTEX_PCM_A3D) { a3d = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_A3D); if (a3d < 0) { memset(stream->resources, 0, sizeof(stream->resources)); dev_err(vortex->card->dev, "out of A3D sources. Sorry\n"); return -EBUSY; } /* (De)Initialize A3D hardware source. */ vortex_Vort3D_InitializeSource(&vortex->a3d[a3d], en, vortex); } /* Make SPDIF out exclusive to "spdif" device when in use. */ if ((stream->type == VORTEX_PCM_SPDIF) && (en)) { vortex_route(vortex, 0, 0x14, ADB_MIXOUT(vortex->mixspdif[0]), ADB_SPDIFOUT(0)); vortex_route(vortex, 0, 0x14, ADB_MIXOUT(vortex->mixspdif[1]), ADB_SPDIFOUT(1)); } #endif /* Make playback routes. */ for (i = 0; i < nr_ch; i++) { if (stream->type == VORTEX_PCM_ADB) { vortex_connection_adbdma_src(vortex, en, src[nr_ch - 1], dma, src[i]); vortex_connection_src_mixin(vortex, en, 0x11, src[i], mix[i]); vortex_connection_mixin_mix(vortex, en, mix[i], MIX_PLAYB(i), 0); #ifndef CHIP_AU8820 vortex_connection_mixin_mix(vortex, en, mix[i], MIX_SPDIF(i % 2), 0); vortex_mix_setinputvolumebyte(vortex, MIX_SPDIF(i % 2), mix[i], MIX_DEFIGAIN); #endif } #ifndef CHIP_AU8820 if (stream->type == VORTEX_PCM_A3D) { vortex_connection_adbdma_src(vortex, en, src[nr_ch - 1], dma, src[i]); vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d)); /* XTalk test. */ //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4)); //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9)); } if (stream->type == VORTEX_PCM_SPDIF) vortex_route(vortex, en, 0x14, ADB_DMA(stream->dma), ADB_SPDIFOUT(i)); #endif } if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) { ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2); for (i = nr_ch; i < ch_top; i++) { vortex_connection_mixin_mix(vortex, en, mix[i % nr_ch], MIX_PLAYB(i), 0); #ifndef CHIP_AU8820 vortex_connection_mixin_mix(vortex, en, mix[i % nr_ch], MIX_SPDIF(i % 2), 0); vortex_mix_setinputvolumebyte(vortex, MIX_SPDIF(i % 2), mix[i % nr_ch], MIX_DEFIGAIN); #endif } if (stream->type == VORTEX_PCM_ADB && en) { p = &vortex->pcm_vol[subdev]; p->dma = dma; for (i = 0; i < nr_ch; i++) p->mixin[i] = mix[i]; for (i = 0; i < ch_top; i++) p->vol[i] = 0; } } #ifndef CHIP_AU8820 else { if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF) vortex_route(vortex, en, 0x14, ADB_DMA(stream->dma), ADB_SPDIFOUT(1)); } /* Reconnect SPDIF out when "spdif" device is down. */ if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) { vortex_route(vortex, 1, 0x14, ADB_MIXOUT(vortex->mixspdif[0]), ADB_SPDIFOUT(0)); vortex_route(vortex, 1, 0x14, ADB_MIXOUT(vortex->mixspdif[1]), ADB_SPDIFOUT(1)); } #endif /* CAPTURE ROUTES. */ } else { int src[2], mix[2]; if (nr_ch < 1) return -EINVAL; /* Get SRC and MIXER hardware resources. */ for (i = 0; i < nr_ch; i++) { mix[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_MIXOUT); if (mix[i] < 0) { memset(stream->resources, 0, sizeof(stream->resources)); return -EBUSY; } src[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_SRC); if (src[i] < 0) { memset(stream->resources, 0, sizeof(stream->resources)); return -EBUSY; } } /* Make capture routes. */ vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0); vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]); if (nr_ch == 1) { vortex_connection_mixin_mix(vortex, en, MIX_CAPT(1), mix[0], 0); vortex_connection_src_adbdma(vortex, en, src[0], src[0], dma); } else { vortex_connection_mixin_mix(vortex, en, MIX_CAPT(1), mix[1], 0); vortex_connection_mix_src(vortex, en, 0x11, mix[1], src[1]); vortex_connection_src_src_adbdma(vortex, en, src[1], src[0], src[1], dma); } } vortex->dma_adb[dma].nr_ch = nr_ch; #if 0 /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */ if (nr_ch < 4) { /* Copy stereo to rear channel (surround) */ snd_ac97_write_cache(vortex->codec, AC97_SIGMATEL_DAC2INVERT, snd_ac97_read(vortex->codec, AC97_SIGMATEL_DAC2INVERT) | 4); } else { /* Allow separate front and rear channels. */ snd_ac97_write_cache(vortex->codec, AC97_SIGMATEL_DAC2INVERT, snd_ac97_read(vortex->codec, AC97_SIGMATEL_DAC2INVERT) & ~((u32) 4)); } #endif return dma; } /* Set the SampleRate of the SRC's attached to the given DMA engine. */ static void vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir) { stream_t *stream = &(vortex->dma_adb[adbdma]); int i, cvrt; /* dir=1:play ; dir=0:rec */ if (dir) cvrt = SRC_RATIO(rate, 48000); else cvrt = SRC_RATIO(48000, rate); /* Setup SRC's */ for (i = 0; i < NR_SRC; i++) { if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i)) vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir); } } // Timer and ISR functions. static void vortex_settimer(vortex_t * vortex, int period) { //set the timer period to <period> 48000ths of a second. hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period); } #if 0 static void vortex_enable_timer_int(vortex_t * card) { hwwrite(card->mmio, VORTEX_IRQ_CTRL, hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60); } static void vortex_disable_timer_int(vortex_t * card) { hwwrite(card->mmio, VORTEX_IRQ_CTRL, hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER); } #endif static void vortex_enable_int(vortex_t * card) { // CAsp4ISR__EnableVortexInt_void_ hwwrite(card->mmio, VORTEX_CTRL, hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE); hwwrite(card->mmio, VORTEX_IRQ_CTRL, (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24); } static void vortex_disable_int(vortex_t * card) { hwwrite(card->mmio, VORTEX_CTRL, hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE); } static irqreturn_t vortex_interrupt(int irq, void *dev_id) { vortex_t *vortex = dev_id; int i, handled; u32 source; //check if the interrupt is ours. if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1)) return IRQ_NONE; // This is the Interrupt Enable flag we set before (consistency check). if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE)) return IRQ_NONE; source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); // Reset IRQ flags. hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source); hwread(vortex->mmio, VORTEX_IRQ_SOURCE); // Is at least one IRQ flag set? if (source == 0) { dev_err(vortex->card->dev, "missing irq source\n"); return IRQ_NONE; } handled = 0; // Attend every interrupt source. if (unlikely(source & IRQ_ERR_MASK)) { if (source & IRQ_FATAL) { dev_err(vortex->card->dev, "IRQ fatal error\n"); } if (source & IRQ_PARITY) { dev_err(vortex->card->dev, "IRQ parity error\n"); } if (source & IRQ_REG) { dev_err(vortex->card->dev, "IRQ reg error\n"); } if (source & IRQ_FIFO) { dev_err(vortex->card->dev, "IRQ fifo error\n"); } if (source & IRQ_DMA) { dev_err(vortex->card->dev, "IRQ dma error\n"); } handled = 1; } if (source & IRQ_PCMOUT) { /* ALSA period acknowledge. */ spin_lock(&vortex->lock); for (i = 0; i < NR_ADB; i++) { if (vortex->dma_adb[i].fifo_status == FIFO_START) { if (!vortex_adbdma_bufshift(vortex, i)) continue; spin_unlock(&vortex->lock); snd_pcm_period_elapsed(vortex->dma_adb[i]. substream); spin_lock(&vortex->lock); } } #ifndef CHIP_AU8810 for (i = 0; i < NR_WT; i++) { if (vortex->dma_wt[i].fifo_status == FIFO_START) { /* FIXME: we ignore the return value from * vortex_wtdma_bufshift() below as the delta * calculation seems not working for wavetable * by some reason */ vortex_wtdma_bufshift(vortex, i); spin_unlock(&vortex->lock); snd_pcm_period_elapsed(vortex->dma_wt[i]. substream); spin_lock(&vortex->lock); } } #endif spin_unlock(&vortex->lock); handled = 1; } //Acknowledge the Timer interrupt if (source & IRQ_TIMER) { hwread(vortex->mmio, VORTEX_IRQ_STAT); handled = 1; } if ((source & IRQ_MIDI) && vortex->rmidi) { snd_mpu401_uart_interrupt(vortex->irq, vortex->rmidi->private_data); handled = 1; } if (!handled) { dev_err(vortex->card->dev, "unknown irq source %x\n", source); } return IRQ_RETVAL(handled); } /* Codec */ #define POLL_COUNT 1000 static void vortex_codec_init(vortex_t * vortex) { int i; for (i = 0; i < 32; i++) { /* the windows driver writes -i, so we write -i */ hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i); msleep(2); } if (0) { hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068); msleep(1); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8); msleep(1); } else { hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8); msleep(2); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8); msleep(2); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8); msleep(2); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8); msleep(2); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8); msleep(2); hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8); } for (i = 0; i < 32; i++) { hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i); msleep(5); } hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8); msleep(1); /* Enable codec channels 0 and 1. */ hwwrite(vortex->mmio, VORTEX_CODEC_EN, hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC); } static void vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data) { vortex_t *card = (vortex_t *) codec->private_data; unsigned int lifeboat = 0; /* wait for transactions to clear */ while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { udelay(100); if (lifeboat++ > POLL_COUNT) { dev_err(card->card->dev, "ac97 codec stuck busy\n"); return; } } /* write register */ hwwrite(card->mmio, VORTEX_CODEC_IO, ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) | VORTEX_CODEC_WRITE | (codec->num << VORTEX_CODEC_ID_SHIFT) ); /* Flush Caches. */ hwread(card->mmio, VORTEX_CODEC_IO); } static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr) { vortex_t *card = (vortex_t *) codec->private_data; u32 read_addr, data; unsigned lifeboat = 0; /* wait for transactions to clear */ while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { udelay(100); if (lifeboat++ > POLL_COUNT) { dev_err(card->card->dev, "ac97 codec stuck busy\n"); return 0xffff; } } /* set up read address */ read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | (codec->num << VORTEX_CODEC_ID_SHIFT) ; hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); /* wait for address */ do { udelay(100); data = hwread(card->mmio, VORTEX_CODEC_IO); if (lifeboat++ > POLL_COUNT) { dev_err(card->card->dev, "ac97 address never arrived\n"); return 0xffff; } } while ((data & VORTEX_CODEC_ADDMASK) != (addr << VORTEX_CODEC_ADDSHIFT)); /* return data. */ return (u16) (data & VORTEX_CODEC_DATMASK); } /* SPDIF support */ static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode) { int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0; /* CAsp4Spdif::InitializeSpdifHardware(void) */ hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS, hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd); //for (i=0x291D4; i<0x29200; i+=4) for (i = 0; i < 11; i++) hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0); //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000); hwwrite(vortex->mmio, VORTEX_CODEC_EN, hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF); /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */ if (this_04 && this_08) { int edi; i = (((0x5DC00000 / spdif_sr) + 1) >> 1); if (i > 0x800) { if (i < 0x1ffff) edi = (i >> 1); else edi = 0x1ffff; } else { edi = 0x800; } /* this_04 and this_08 are the CASp4Src's (samplerate converters) */ vortex_src_setupchannel(vortex, this_04, edi, 0, 1, this_0c, 1, 0, edi, 1); vortex_src_setupchannel(vortex, this_08, edi, 0, 1, this_0c, 1, 0, edi, 1); } i = spdif_sr; spdif_sr |= 0x8c; switch (i) { case 32000: this_38 &= 0xFFFFFFFE; this_38 &= 0xFFFFFFFD; this_38 &= 0xF3FFFFFF; this_38 |= 0x03000000; /* set 32khz samplerate */ this_38 &= 0xFFFFFF3F; spdif_sr &= 0xFFFFFFFD; spdif_sr |= 1; break; case 44100: this_38 &= 0xFFFFFFFE; this_38 &= 0xFFFFFFFD; this_38 &= 0xF0FFFFFF; this_38 |= 0x03000000; this_38 &= 0xFFFFFF3F; spdif_sr &= 0xFFFFFFFC; break; case 48000: if (spdif_mode == 1) { this_38 &= 0xFFFFFFFE; this_38 &= 0xFFFFFFFD; this_38 &= 0xF2FFFFFF; this_38 |= 0x02000000; /* set 48khz samplerate */ this_38 &= 0xFFFFFF3F; } else { /* J. Gordon Wolfe: I think this stuff is for AC3 */ this_38 |= 0x00000003; this_38 &= 0xFFFFFFBF; this_38 |= 0x80; } spdif_sr |= 2; spdif_sr &= 0xFFFFFFFE; break; } /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit registers. seems to be for the standard IEC/SPDIF initialization stuff */ hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff); hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10); hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr); } /* Initialization */ static int vortex_core_init(vortex_t *vortex) { dev_info(vortex->card->dev, "init started\n"); /* Hardware Init. */ hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff); msleep(5); hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff); msleep(5); /* Reset IRQ flags */ hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff); hwread(vortex->mmio, VORTEX_IRQ_STAT); vortex_codec_init(vortex); #ifdef CHIP_AU8830 hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000); #endif /* Init audio engine. */ vortex_adbdma_init(vortex); hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58 vortex_adb_init(vortex); /* Init processing blocks. */ vortex_fifo_init(vortex); vortex_mixer_init(vortex); vortex_srcblock_init(vortex); #ifndef CHIP_AU8820 vortex_eq_init(vortex); vortex_spdif_init(vortex, 48000, 1); vortex_Vort3D_enable(vortex); #endif #ifndef CHIP_AU8810 vortex_wt_init(vortex); #endif // Moved to au88x0.c //vortex_connect_default(vortex, 1); vortex_settimer(vortex, 0x90); // Enable Interrupts. // vortex_enable_int() must be first !! // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); // vortex_enable_int(vortex); //vortex_enable_timer_int(vortex); //vortex_disable_timer_int(vortex); dev_info(vortex->card->dev, "init.... done.\n"); spin_lock_init(&vortex->lock); return 0; } static int vortex_core_shutdown(vortex_t * vortex) { dev_info(vortex->card->dev, "shutdown started\n"); #ifndef CHIP_AU8820 vortex_eq_free(vortex); vortex_Vort3D_disable(vortex); #endif //vortex_disable_timer_int(vortex); vortex_disable_int(vortex); vortex_connect_default(vortex, 0); /* Reset all DMA fifos. */ vortex_fifo_init(vortex); /* Erase all audio routes. */ vortex_adb_init(vortex); /* Disable MPU401 */ //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI); //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN); hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); hwwrite(vortex->mmio, VORTEX_CTRL, 0); msleep(5); hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff); dev_info(vortex->card->dev, "shutdown.... done.\n"); return 0; } /* Alsa support. */ static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v) { int fmt; switch (alsafmt) { case SNDRV_PCM_FORMAT_U8: fmt = 0x1; break; case SNDRV_PCM_FORMAT_MU_LAW: fmt = 0x2; break; case SNDRV_PCM_FORMAT_A_LAW: fmt = 0x3; break; case SNDRV_PCM_FORMAT_SPECIAL: fmt = 0x4; /* guess. */ break; case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: fmt = 0x5; /* guess. */ break; case SNDRV_PCM_FORMAT_S16_LE: fmt = 0x8; break; case SNDRV_PCM_FORMAT_S16_BE: fmt = 0x9; /* check this... */ break; default: fmt = 0x8; dev_err(v->card->dev, "format unsupported %d\n", alsafmt); break; } return fmt; } /* Some not yet useful translations. */ #if 0 typedef enum { ASPFMTLINEAR16 = 0, /* 0x8 */ ASPFMTLINEAR8, /* 0x1 */ ASPFMTULAW, /* 0x2 */ ASPFMTALAW, /* 0x3 */ ASPFMTSPORT, /* ? */ ASPFMTSPDIF, /* ? */ } ASPENCODING; static int vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod) { int a, this_194; if ((bits != 8) && (bits != 16)) return -1; switch (encod) { case 0: if (bits == 0x10) a = 8; // 16 bit break; case 1: if (bits == 8) a = 1; // 8 bit break; case 2: a = 2; // U_LAW break; case 3: a = 3; // A_LAW break; } switch (nch) { case 1: this_194 = 0; break; case 2: this_194 = 1; break; case 4: this_194 = 1; break; case 6: this_194 = 1; break; } return (a); } static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch) { short int d, this_148; d = ((bits >> 3) * nch); this_148 = 0xbb80 / d; } #endif
linux-master
sound/pci/au88x0/au88x0_core.c
// SPDX-License-Identifier: GPL-2.0 /* * Vortex Mixer support. * * There is much more than just the AC97 mixer... * */ #include <linux/time.h> #include <linux/init.h> #include <sound/core.h> #include "au88x0.h" static int remove_ctl(struct snd_card *card, const char *name) { struct snd_ctl_elem_id id; memset(&id, 0, sizeof(id)); strcpy(id.name, name); id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; return snd_ctl_remove_id(card, &id); } static int snd_vortex_mixer(vortex_t *vortex) { struct snd_ac97_bus *pbus; struct snd_ac97_template ac97; int err; static const struct snd_ac97_bus_ops ops = { .write = vortex_codec_write, .read = vortex_codec_read, }; err = snd_ac97_bus(vortex->card, 0, &ops, NULL, &pbus); if (err < 0) return err; memset(&ac97, 0, sizeof(ac97)); // Initialize AC97 codec stuff. ac97.private_data = vortex; ac97.scaps = AC97_SCAP_NO_SPDIF; err = snd_ac97_mixer(pbus, &ac97, &vortex->codec); vortex->isquad = ((vortex->codec == NULL) ? 0 : (vortex->codec->ext_id&0x80)); remove_ctl(vortex->card, "Master Mono Playback Volume"); remove_ctl(vortex->card, "Master Mono Playback Switch"); return err; }
linux-master
sound/pci/au88x0/au88x0_mixer.c
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * au88x0_eq.c * Aureal Vortex Hardware EQ control/access. * * Sun Jun 8 18:19:19 2003 * 2003 Manuel Jander ([email protected]) * * 02 July 2003: First time something works :) * November 2003: A3D Bypass code completed but untested. * * TODO: * - Debug (testing) * - Test peak visualization support. * ****************************************************************************/ /* */ /* The Aureal Hardware EQ is found on AU8810 and AU8830 chips only. it has 4 inputs (2 for general mix, 2 for A3D) and 2 outputs (supposed to be routed to the codec). */ #include "au88x0.h" #include "au88x0_eq.h" #include "au88x0_eqdata.c" #define VORTEX_EQ_BASE 0x2b000 #define VORTEX_EQ_DEST (VORTEX_EQ_BASE + 0x410) #define VORTEX_EQ_SOURCE (VORTEX_EQ_BASE + 0x430) #define VORTEX_EQ_CTRL (VORTEX_EQ_BASE + 0x440) #define VORTEX_BAND_COEFF_SIZE 0x30 /* CEqHw.s */ static void vortex_EqHw_SetTimeConsts(vortex_t * vortex, u16 gain, u16 level) { hwwrite(vortex->mmio, 0x2b3c4, gain); hwwrite(vortex->mmio, 0x2b3c8, level); } static inline u16 sign_invert(u16 a) { /* -(-32768) -> -32768 so we do -(-32768) -> 32767 to make the result positive */ if (a == (u16)-32768) return 32767; else return -a; } static void vortex_EqHw_SetLeftCoefs(vortex_t *vortex, const u16 coefs[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i = 0, n /*esp2c */; for (n = 0; n < eqhw->this04; n++) { hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); if (eqhw->this08 == 0) { hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); } else { hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); hwwrite(vortex->mmio, 0x2b010 + n * 0x30, sign_invert(coefs[4 + i])); } i += 5; } } static void vortex_EqHw_SetRightCoefs(vortex_t *vortex, const u16 coefs[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i = 0, n /*esp2c */; for (n = 0; n < eqhw->this04; n++) { hwwrite(vortex->mmio, 0x2b1e0 + n * 0x30, coefs[0 + i]); hwwrite(vortex->mmio, 0x2b1e4 + n * 0x30, coefs[1 + i]); if (eqhw->this08 == 0) { hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, coefs[2 + i]); hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, coefs[3 + i]); hwwrite(vortex->mmio, 0x2b1f0 + n * 0x30, coefs[4 + i]); } else { hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, sign_invert(coefs[2 + i])); hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, sign_invert(coefs[3 + i])); hwwrite(vortex->mmio, 0x2b1f0 + n * 0x30, sign_invert(coefs[4 + i])); } i += 5; } } static void vortex_EqHw_SetLeftStates(vortex_t *vortex, const u16 a[], const u16 b[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i = 0, ebx; hwwrite(vortex->mmio, 0x2b3fc, a[0]); hwwrite(vortex->mmio, 0x2b400, a[1]); for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b014 + (i * 0xc), b[i]); hwwrite(vortex->mmio, 0x2b018 + (i * 0xc), b[1 + i]); hwwrite(vortex->mmio, 0x2b01c + (i * 0xc), b[2 + i]); hwwrite(vortex->mmio, 0x2b020 + (i * 0xc), b[3 + i]); i += 4; } } static void vortex_EqHw_SetRightStates(vortex_t *vortex, const u16 a[], const u16 b[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i = 0, ebx; hwwrite(vortex->mmio, 0x2b404, a[0]); hwwrite(vortex->mmio, 0x2b408, a[1]); for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b1f4 + (i * 0xc), b[i]); hwwrite(vortex->mmio, 0x2b1f8 + (i * 0xc), b[1 + i]); hwwrite(vortex->mmio, 0x2b1fc + (i * 0xc), b[2 + i]); hwwrite(vortex->mmio, 0x2b200 + (i * 0xc), b[3 + i]); i += 4; } } #if 0 static void vortex_EqHw_GetTimeConsts(vortex_t * vortex, u16 * a, u16 * b) { *a = hwread(vortex->mmio, 0x2b3c4); *b = hwread(vortex->mmio, 0x2b3c8); } static void vortex_EqHw_GetLeftCoefs(vortex_t * vortex, u16 a[]) { } static void vortex_EqHw_GetRightCoefs(vortex_t * vortex, u16 a[]) { } static void vortex_EqHw_GetLeftStates(vortex_t * vortex, u16 * a, u16 b[]) { } static void vortex_EqHw_GetRightStates(vortex_t * vortex, u16 * a, u16 b[]) { } #endif /* Mix Gains */ static void vortex_EqHw_SetBypassGain(vortex_t * vortex, u16 a, u16 b) { eqhw_t *eqhw = &(vortex->eq.this04); if (eqhw->this08 == 0) { hwwrite(vortex->mmio, 0x2b3d4, a); hwwrite(vortex->mmio, 0x2b3ec, b); } else { hwwrite(vortex->mmio, 0x2b3d4, sign_invert(a)); hwwrite(vortex->mmio, 0x2b3ec, sign_invert(b)); } } static void vortex_EqHw_SetA3DBypassGain(vortex_t * vortex, u16 a, u16 b) { hwwrite(vortex->mmio, 0x2b3e0, a); hwwrite(vortex->mmio, 0x2b3f8, b); } #if 0 static void vortex_EqHw_SetCurrBypassGain(vortex_t * vortex, u16 a, u16 b) { hwwrite(vortex->mmio, 0x2b3d0, a); hwwrite(vortex->mmio, 0x2b3e8, b); } static void vortex_EqHw_SetCurrA3DBypassGain(vortex_t * vortex, u16 a, u16 b) { hwwrite(vortex->mmio, 0x2b3dc, a); hwwrite(vortex->mmio, 0x2b3f4, b); } #endif static void vortex_EqHw_SetLeftGainsSingleTarget(vortex_t * vortex, u16 index, u16 b) { hwwrite(vortex->mmio, 0x2b02c + (index * 0x30), b); } static void vortex_EqHw_SetRightGainsSingleTarget(vortex_t * vortex, u16 index, u16 b) { hwwrite(vortex->mmio, 0x2b20c + (index * 0x30), b); } static void vortex_EqHw_SetLeftGainsTarget(vortex_t *vortex, const u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx; for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b02c + ebx * 0x30, a[ebx]); } } static void vortex_EqHw_SetRightGainsTarget(vortex_t *vortex, const u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx; for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b20c + ebx * 0x30, a[ebx]); } } static void vortex_EqHw_SetLeftGainsCurrent(vortex_t *vortex, const u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx; for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b028 + ebx * 0x30, a[ebx]); } } static void vortex_EqHw_SetRightGainsCurrent(vortex_t *vortex, const u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx; for (ebx = 0; ebx < eqhw->this04; ebx++) { hwwrite(vortex->mmio, 0x2b208 + ebx * 0x30, a[ebx]); } } #if 0 static void vortex_EqHw_GetLeftGainsTarget(vortex_t * vortex, u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx = 0; if (eqhw->this04 < 0) return; do { a[ebx] = hwread(vortex->mmio, 0x2b02c + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); } static void vortex_EqHw_GetRightGainsTarget(vortex_t * vortex, u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx = 0; if (eqhw->this04 < 0) return; do { a[ebx] = hwread(vortex->mmio, 0x2b20c + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); } static void vortex_EqHw_GetLeftGainsCurrent(vortex_t * vortex, u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx = 0; if (eqhw->this04 < 0) return; do { a[ebx] = hwread(vortex->mmio, 0x2b028 + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); } static void vortex_EqHw_GetRightGainsCurrent(vortex_t * vortex, u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx = 0; if (eqhw->this04 < 0) return; do { a[ebx] = hwread(vortex->mmio, 0x2b208 + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); } #endif /* EQ band levels settings */ static void vortex_EqHw_SetLevels(vortex_t *vortex, const u16 peaks[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i; /* set left peaks */ for (i = 0; i < eqhw->this04; i++) { hwwrite(vortex->mmio, 0x2b024 + i * VORTEX_BAND_COEFF_SIZE, peaks[i]); } hwwrite(vortex->mmio, 0x2b3cc, peaks[eqhw->this04]); hwwrite(vortex->mmio, 0x2b3d8, peaks[eqhw->this04 + 1]); /* set right peaks */ for (i = 0; i < eqhw->this04; i++) { hwwrite(vortex->mmio, 0x2b204 + i * VORTEX_BAND_COEFF_SIZE, peaks[i + (eqhw->this04 + 2)]); } hwwrite(vortex->mmio, 0x2b3e4, peaks[2 + (eqhw->this04 * 2)]); hwwrite(vortex->mmio, 0x2b3f0, peaks[3 + (eqhw->this04 * 2)]); } #if 0 static void vortex_EqHw_GetLevels(vortex_t * vortex, u16 a[]) { eqhw_t *eqhw = &(vortex->eq.this04); int ebx; if (eqhw->this04 < 0) return; ebx = 0; do { a[ebx] = hwread(vortex->mmio, 0x2b024 + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); a[eqhw->this04] = hwread(vortex->mmio, 0x2b3cc); a[eqhw->this04 + 1] = hwread(vortex->mmio, 0x2b3d8); ebx = 0; do { a[ebx + (eqhw->this04 + 2)] = hwread(vortex->mmio, 0x2b204 + ebx * 0x30); ebx++; } while (ebx < eqhw->this04); a[2 + (eqhw->this04 * 2)] = hwread(vortex->mmio, 0x2b3e4); a[3 + (eqhw->this04 * 2)] = hwread(vortex->mmio, 0x2b3f0); } #endif /* Global Control */ static void vortex_EqHw_SetControlReg(vortex_t * vortex, u32 reg) { hwwrite(vortex->mmio, 0x2b440, reg); } static void vortex_EqHw_SetSampleRate(vortex_t * vortex, u32 sr) { hwwrite(vortex->mmio, 0x2b440, ((sr & 0x1f) << 3) | 0xb800); } #if 0 static void vortex_EqHw_GetControlReg(vortex_t * vortex, u32 *reg) { *reg = hwread(vortex->mmio, 0x2b440); } static void vortex_EqHw_GetSampleRate(vortex_t * vortex, u32 *sr) { *sr = (hwread(vortex->mmio, 0x2b440) >> 3) & 0x1f; } #endif static void vortex_EqHw_Enable(vortex_t * vortex) { hwwrite(vortex->mmio, VORTEX_EQ_CTRL, 0xf001); } static void vortex_EqHw_Disable(vortex_t * vortex) { hwwrite(vortex->mmio, VORTEX_EQ_CTRL, 0xf000); } /* Reset (zero) buffers */ static void vortex_EqHw_ZeroIO(vortex_t * vortex) { int i; for (i = 0; i < 0x8; i++) hwwrite(vortex->mmio, VORTEX_EQ_DEST + (i << 2), 0x0); for (i = 0; i < 0x4; i++) hwwrite(vortex->mmio, VORTEX_EQ_SOURCE + (i << 2), 0x0); } static void vortex_EqHw_ZeroA3DIO(vortex_t * vortex) { int i; for (i = 0; i < 0x4; i++) hwwrite(vortex->mmio, VORTEX_EQ_DEST + (i << 2), 0x0); } static void vortex_EqHw_ZeroState(vortex_t * vortex) { vortex_EqHw_SetControlReg(vortex, 0); vortex_EqHw_ZeroIO(vortex); hwwrite(vortex->mmio, 0x2b3c0, 0); vortex_EqHw_SetTimeConsts(vortex, 0, 0); vortex_EqHw_SetLeftCoefs(vortex, asEqCoefsZeros); vortex_EqHw_SetRightCoefs(vortex, asEqCoefsZeros); vortex_EqHw_SetLeftGainsCurrent(vortex, eq_gains_zero); vortex_EqHw_SetRightGainsCurrent(vortex, eq_gains_zero); vortex_EqHw_SetLeftGainsTarget(vortex, eq_gains_zero); vortex_EqHw_SetRightGainsTarget(vortex, eq_gains_zero); vortex_EqHw_SetBypassGain(vortex, 0, 0); //vortex_EqHw_SetCurrBypassGain(vortex, 0, 0); vortex_EqHw_SetA3DBypassGain(vortex, 0, 0); //vortex_EqHw_SetCurrA3DBypassGain(vortex, 0, 0); vortex_EqHw_SetLeftStates(vortex, eq_states_zero, asEqOutStateZeros); vortex_EqHw_SetRightStates(vortex, eq_states_zero, asEqOutStateZeros); vortex_EqHw_SetLevels(vortex, (u16 *) eq_levels); } /* Program coeficients as pass through */ static void vortex_EqHw_ProgramPipe(vortex_t * vortex) { vortex_EqHw_SetTimeConsts(vortex, 0, 0); vortex_EqHw_SetLeftCoefs(vortex, asEqCoefsPipes); vortex_EqHw_SetRightCoefs(vortex, asEqCoefsPipes); vortex_EqHw_SetLeftGainsCurrent(vortex, eq_gains_current); vortex_EqHw_SetRightGainsCurrent(vortex, eq_gains_current); vortex_EqHw_SetLeftGainsTarget(vortex, eq_gains_current); vortex_EqHw_SetRightGainsTarget(vortex, eq_gains_current); } /* Program EQ block as 10 band Equalizer */ static void vortex_EqHw_Program10Band(vortex_t * vortex, auxxEqCoeffSet_t * coefset) { vortex_EqHw_SetTimeConsts(vortex, 0xc, 0x7fe0); vortex_EqHw_SetLeftCoefs(vortex, coefset->LeftCoefs); vortex_EqHw_SetRightCoefs(vortex, coefset->RightCoefs); vortex_EqHw_SetLeftGainsCurrent(vortex, coefset->LeftGains); vortex_EqHw_SetRightGainsTarget(vortex, coefset->RightGains); vortex_EqHw_SetLeftGainsTarget(vortex, coefset->LeftGains); vortex_EqHw_SetRightGainsCurrent(vortex, coefset->RightGains); } /* Read all EQ peaks. (think VU meter) */ static void vortex_EqHw_GetTenBandLevels(vortex_t * vortex, u16 peaks[]) { eqhw_t *eqhw = &(vortex->eq.this04); int i; if (eqhw->this04 <= 0) return; for (i = 0; i < eqhw->this04; i++) peaks[i] = hwread(vortex->mmio, 0x2B024 + i * 0x30); for (i = 0; i < eqhw->this04; i++) peaks[i + eqhw->this04] = hwread(vortex->mmio, 0x2B204 + i * 0x30); } /* CEqlzr.s */ static int vortex_Eqlzr_GetLeftGain(vortex_t * vortex, u16 index, u16 * gain) { eqlzr_t *eq = &(vortex->eq); if (eq->this28) { *gain = eq->this130[index]; return 0; } return 1; } static void vortex_Eqlzr_SetLeftGain(vortex_t * vortex, u16 index, u16 gain) { eqlzr_t *eq = &(vortex->eq); if (eq->this28 == 0) return; eq->this130[index] = gain; if (eq->this54) return; vortex_EqHw_SetLeftGainsSingleTarget(vortex, index, gain); } static int vortex_Eqlzr_GetRightGain(vortex_t * vortex, u16 index, u16 * gain) { eqlzr_t *eq = &(vortex->eq); if (eq->this28) { *gain = eq->this130[index + eq->this10]; return 0; } return 1; } static void vortex_Eqlzr_SetRightGain(vortex_t * vortex, u16 index, u16 gain) { eqlzr_t *eq = &(vortex->eq); if (eq->this28 == 0) return; eq->this130[index + eq->this10] = gain; if (eq->this54) return; vortex_EqHw_SetRightGainsSingleTarget(vortex, index, gain); } #if 0 static int vortex_Eqlzr_GetAllBands(vortex_t * vortex, u16 * gains, s32 *cnt) { eqlzr_t *eq = &(vortex->eq); int si = 0; if (eq->this10 == 0) return 1; { if (vortex_Eqlzr_GetLeftGain(vortex, si, &gains[si])) return 1; if (vortex_Eqlzr_GetRightGain (vortex, si, &gains[si + eq->this10])) return 1; si++; } while (eq->this10 > si) ; *cnt = si * 2; return 0; } #endif static int vortex_Eqlzr_SetAllBandsFromActiveCoeffSet(vortex_t * vortex) { eqlzr_t *eq = &(vortex->eq); vortex_EqHw_SetLeftGainsTarget(vortex, eq->this130); vortex_EqHw_SetRightGainsTarget(vortex, &(eq->this130[eq->this10])); return 0; } static int vortex_Eqlzr_SetAllBands(vortex_t *vortex, const u16 gains[], s32 count) { eqlzr_t *eq = &(vortex->eq); int i; if (((eq->this10) * 2 != count) || (eq->this28 == 0)) return 1; for (i = 0; i < count; i++) { eq->this130[i] = gains[i]; } if (eq->this54) return 0; return vortex_Eqlzr_SetAllBandsFromActiveCoeffSet(vortex); } static void vortex_Eqlzr_SetA3dBypassGain(vortex_t * vortex, u32 a, u32 b) { eqlzr_t *eq = &(vortex->eq); u32 eax, ebx; eq->this58 = a; eq->this5c = b; if (eq->this54) eax = eq->this0e; else eax = eq->this0a; ebx = (eax * eq->this58) >> 0x10; eax = (eax * eq->this5c) >> 0x10; vortex_EqHw_SetA3DBypassGain(vortex, ebx, eax); } static void vortex_Eqlzr_ProgramA3dBypassGain(vortex_t * vortex) { eqlzr_t *eq = &(vortex->eq); u32 eax, ebx; if (eq->this54) eax = eq->this0e; else eax = eq->this0a; ebx = (eax * eq->this58) >> 0x10; eax = (eax * eq->this5c) >> 0x10; vortex_EqHw_SetA3DBypassGain(vortex, ebx, eax); } static void vortex_Eqlzr_ShutDownA3d(vortex_t * vortex) { if (vortex != NULL) vortex_EqHw_ZeroA3DIO(vortex); } static void vortex_Eqlzr_SetBypass(vortex_t * vortex, u32 bp) { eqlzr_t *eq = &(vortex->eq); if ((eq->this28) && (bp == 0)) { /* EQ enabled */ vortex_Eqlzr_SetAllBandsFromActiveCoeffSet(vortex); vortex_EqHw_SetBypassGain(vortex, eq->this08, eq->this08); } else { /* EQ disabled. */ vortex_EqHw_SetLeftGainsTarget(vortex, eq->this14_array); vortex_EqHw_SetRightGainsTarget(vortex, eq->this14_array); vortex_EqHw_SetBypassGain(vortex, eq->this0c, eq->this0c); } vortex_Eqlzr_ProgramA3dBypassGain(vortex); } static void vortex_Eqlzr_ReadAndSetActiveCoefSet(vortex_t * vortex) { eqlzr_t *eq = &(vortex->eq); /* Set EQ BiQuad filter coeficients */ memcpy(&(eq->coefset), &asEqCoefsNormal, sizeof(auxxEqCoeffSet_t)); /* Set EQ Band gain levels and dump into hardware registers. */ vortex_Eqlzr_SetAllBands(vortex, eq_gains_normal, eq->this10 * 2); } static int vortex_Eqlzr_GetAllPeaks(vortex_t * vortex, u16 * peaks, int *count) { eqlzr_t *eq = &(vortex->eq); if (eq->this10 == 0) return 1; *count = eq->this10 * 2; vortex_EqHw_GetTenBandLevels(vortex, peaks); return 0; } #if 0 static auxxEqCoeffSet_t *vortex_Eqlzr_GetActiveCoefSet(vortex_t * vortex) { eqlzr_t *eq = &(vortex->eq); return (&(eq->coefset)); } #endif static void vortex_Eqlzr_init(vortex_t * vortex) { eqlzr_t *eq = &(vortex->eq); /* Object constructor */ //eq->this04 = 0; eq->this08 = 0; /* Bypass gain with EQ in use. */ eq->this0a = 0x5999; eq->this0c = 0x5999; /* Bypass gain with EQ disabled. */ eq->this0e = 0x5999; eq->this10 = 0xa; /* 10 eq frequency bands. */ eq->this04.this04 = eq->this10; eq->this28 = 0x1; /* if 1 => Allow read access to this130 (gains) */ eq->this54 = 0x0; /* if 1 => Dont Allow access to hardware (gains) */ eq->this58 = 0xffff; eq->this5c = 0xffff; /* Set gains. */ memset(eq->this14_array, 0, sizeof(eq->this14_array)); /* Actual init. */ vortex_EqHw_ZeroState(vortex); vortex_EqHw_SetSampleRate(vortex, 0x11); vortex_Eqlzr_ReadAndSetActiveCoefSet(vortex); vortex_EqHw_Program10Band(vortex, &(eq->coefset)); vortex_Eqlzr_SetBypass(vortex, eq->this54); vortex_Eqlzr_SetA3dBypassGain(vortex, 0, 0); vortex_EqHw_Enable(vortex); } static void vortex_Eqlzr_shutdown(vortex_t * vortex) { vortex_Eqlzr_ShutDownA3d(vortex); vortex_EqHw_ProgramPipe(vortex); vortex_EqHw_Disable(vortex); } /* ALSA interface */ /* Control interface */ #define snd_vortex_eqtoggle_info snd_ctl_boolean_mono_info static int snd_vortex_eqtoggle_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); eqlzr_t *eq = &(vortex->eq); //int i = kcontrol->private_value; ucontrol->value.integer.value[0] = eq->this54 ? 0 : 1; return 0; } static int snd_vortex_eqtoggle_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); eqlzr_t *eq = &(vortex->eq); //int i = kcontrol->private_value; eq->this54 = ucontrol->value.integer.value[0] ? 0 : 1; vortex_Eqlzr_SetBypass(vortex, eq->this54); return 1; /* Allways changes */ } static const struct snd_kcontrol_new vortex_eqtoggle_kcontrol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "EQ Enable", .index = 0, .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .private_value = 0, .info = snd_vortex_eqtoggle_info, .get = snd_vortex_eqtoggle_get, .put = snd_vortex_eqtoggle_put }; static int snd_vortex_eq_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0x0000; uinfo->value.integer.max = 0x7fff; return 0; } static int snd_vortex_eq_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); int i = kcontrol->private_value; u16 gainL = 0, gainR = 0; vortex_Eqlzr_GetLeftGain(vortex, i, &gainL); vortex_Eqlzr_GetRightGain(vortex, i, &gainR); ucontrol->value.integer.value[0] = gainL; ucontrol->value.integer.value[1] = gainR; return 0; } static int snd_vortex_eq_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); int changed = 0, i = kcontrol->private_value; u16 gainL = 0, gainR = 0; vortex_Eqlzr_GetLeftGain(vortex, i, &gainL); vortex_Eqlzr_GetRightGain(vortex, i, &gainR); if (gainL != ucontrol->value.integer.value[0]) { vortex_Eqlzr_SetLeftGain(vortex, i, ucontrol->value.integer.value[0]); changed = 1; } if (gainR != ucontrol->value.integer.value[1]) { vortex_Eqlzr_SetRightGain(vortex, i, ucontrol->value.integer.value[1]); changed = 1; } return changed; } static const struct snd_kcontrol_new vortex_eq_kcontrol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = " .", .index = 0, .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .private_value = 0, .info = snd_vortex_eq_info, .get = snd_vortex_eq_get, .put = snd_vortex_eq_put }; static int snd_vortex_peaks_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 20; uinfo->value.integer.min = 0x0000; uinfo->value.integer.max = 0x7fff; return 0; } static int snd_vortex_peaks_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); int i, count = 0; u16 peaks[20]; vortex_Eqlzr_GetAllPeaks(vortex, peaks, &count); if (count != 20) { dev_err(vortex->card->dev, "peak count error 20 != %d\n", count); return -1; } for (i = 0; i < 20; i++) ucontrol->value.integer.value[i] = peaks[i]; return 0; } static const struct snd_kcontrol_new vortex_levels_kcontrol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "EQ Peaks", .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, .info = snd_vortex_peaks_info, .get = snd_vortex_peaks_get, }; /* EQ band gain labels. */ static const char * const EqBandLabels[10] = { "EQ0 31Hz\0", "EQ1 63Hz\0", "EQ2 125Hz\0", "EQ3 250Hz\0", "EQ4 500Hz\0", "EQ5 1KHz\0", "EQ6 2KHz\0", "EQ7 4KHz\0", "EQ8 8KHz\0", "EQ9 16KHz\0", }; /* ALSA driver entry points. Init and exit. */ static int vortex_eq_init(vortex_t *vortex) { struct snd_kcontrol *kcontrol; int err, i; vortex_Eqlzr_init(vortex); kcontrol = snd_ctl_new1(&vortex_eqtoggle_kcontrol, vortex); if (!kcontrol) return -ENOMEM; kcontrol->private_value = 0; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; /* EQ gain controls */ for (i = 0; i < 10; i++) { kcontrol = snd_ctl_new1(&vortex_eq_kcontrol, vortex); if (!kcontrol) return -ENOMEM; snprintf(kcontrol->id.name, sizeof(kcontrol->id.name), "%s Playback Volume", EqBandLabels[i]); kcontrol->private_value = i; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; //vortex->eqctrl[i] = kcontrol; } /* EQ band levels */ kcontrol = snd_ctl_new1(&vortex_levels_kcontrol, vortex); if (!kcontrol) return -ENOMEM; err = snd_ctl_add(vortex->card, kcontrol); if (err < 0) return err; return 0; } static int vortex_eq_free(vortex_t * vortex) { /* //FIXME: segfault because vortex->eqctrl[i] == 4 int i; for (i=0; i<10; i++) { if (vortex->eqctrl[i]) snd_ctl_remove(vortex->card, vortex->eqctrl[i]); } */ vortex_Eqlzr_shutdown(vortex); return 0; } /* End */
linux-master
sound/pci/au88x0/au88x0_eq.c
// SPDX-License-Identifier: GPL-2.0 #include "au8820.h" #include "au88x0.h" static const struct pci_device_id snd_vortex_ids[] = { {PCI_VDEVICE(AUREAL, PCI_DEVICE_ID_AUREAL_VORTEX_1), 0,}, {0,} }; #include "au88x0_synth.c" #include "au88x0_core.c" #include "au88x0_pcm.c" #include "au88x0_mpu401.c" #include "au88x0_game.c" #include "au88x0_mixer.c" #include "au88x0.c"
linux-master
sound/pci/au88x0/au8820.c
// SPDX-License-Identifier: GPL-2.0-only /* * ALSA driver for the Aureal Vortex family of soundprocessors. * Author: Manuel Jander ([email protected]) * * This driver is the result of the OpenVortex Project from Savannah * (savannah.nongnu.org/projects/openvortex). I would like to thank * the developers of OpenVortex, Jeff Muizelaar and Kester Maddock, from * whom i got plenty of help, and their codebase was invaluable. * Thanks to the ALSA developers, they helped a lot working out * the ALSA part. * Thanks also to Sourceforge for maintaining the old binary drivers, * and the forum, where developers could comunicate. * * Now at least i can play Legacy DOOM with MIDI music :-) */ #include "au88x0.h" #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <sound/initval.h> // module parameters (see "Module Parameters") static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; static int pcifix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 255 }; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); module_param_array(pcifix, int, NULL, 0444); MODULE_PARM_DESC(pcifix, "Enable VIA-workaround for " CARD_NAME " soundcard."); MODULE_DESCRIPTION("Aureal vortex"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, snd_vortex_ids); static void vortex_fix_latency(struct pci_dev *vortex) { int rc; rc = pci_write_config_byte(vortex, 0x40, 0xff); if (!rc) { dev_info(&vortex->dev, "vortex latency is 0xff\n"); } else { dev_warn(&vortex->dev, "could not set vortex latency: pci error 0x%x\n", rc); } } static void vortex_fix_agp_bridge(struct pci_dev *via) { int rc; u8 value; /* * only set the bit (Extend PCI#2 Internal Master for * Efficient Handling of Dummy Requests) if the can * read the config and it is not already set */ rc = pci_read_config_byte(via, 0x42, &value); if (!rc) { if (!(value & 0x10)) rc = pci_write_config_byte(via, 0x42, value | 0x10); } if (!rc) { dev_info(&via->dev, "bridge config is 0x%x\n", value | 0x10); } else { dev_warn(&via->dev, "could not set vortex latency: pci error 0x%x\n", rc); } } static void snd_vortex_workaround(struct pci_dev *vortex, int fix) { struct pci_dev *via = NULL; /* autodetect if workarounds are required */ if (fix == 255) { /* VIA KT133 */ via = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8365_1, NULL); /* VIA Apollo */ if (via == NULL) { via = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C598_1, NULL); /* AMD Irongate */ if (via == NULL) via = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_7007, NULL); } if (via) { dev_info(&vortex->dev, "Activating latency workaround...\n"); vortex_fix_latency(vortex); vortex_fix_agp_bridge(via); } } else { if (fix & 0x1) vortex_fix_latency(vortex); if (fix & 0x2) via = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8365_1, NULL); else if (fix & 0x4) via = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C598_1, NULL); else if (fix & 0x8) via = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_7007, NULL); if (via) vortex_fix_agp_bridge(via); } pci_dev_put(via); } // component-destructor // (see "Management of Cards and Components") static void snd_vortex_free(struct snd_card *card) { vortex_t *vortex = card->private_data; vortex_gameport_unregister(vortex); vortex_core_shutdown(vortex); } // chip-specific constructor // (see "Management of Cards and Components") static int snd_vortex_create(struct snd_card *card, struct pci_dev *pci) { vortex_t *chip = card->private_data; int err; // check PCI availability (DMA). err = pcim_enable_device(pci); if (err < 0) return err; if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32))) { dev_err(card->dev, "error to set DMA mask\n"); return -ENXIO; } chip->card = card; // initialize the stuff chip->pci_dev = pci; chip->vendor = pci->vendor; chip->device = pci->device; chip->card = card; chip->irq = -1; // (1) PCI resource allocation // Get MMIO area // err = pcim_iomap_regions(pci, 1 << 0, CARD_NAME_SHORT); if (err) return err; chip->io = pci_resource_start(pci, 0); chip->mmio = pcim_iomap_table(pci)[0]; /* Init audio core. * This must be done before we do request_irq otherwise we can get spurious * interrupts that we do not handle properly and make a mess of things */ err = vortex_core_init(chip); if (err) { dev_err(card->dev, "hw core init failed\n"); return err; } err = devm_request_irq(&pci->dev, pci->irq, vortex_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip); if (err) { dev_err(card->dev, "cannot grab irq\n"); return err; } chip->irq = pci->irq; card->sync_irq = chip->irq; card->private_free = snd_vortex_free; pci_set_master(pci); // End of PCI setup. return 0; } // constructor -- see "Constructor" sub-section static int __snd_vortex_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; vortex_t *chip; int err; // (1) if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } // (2) err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; // (3) err = snd_vortex_create(card, pci); if (err < 0) return err; snd_vortex_workaround(pci, pcifix[dev]); // Card details needed in snd_vortex_midi strcpy(card->driver, CARD_NAME_SHORT); sprintf(card->shortname, "Aureal Vortex %s", CARD_NAME_SHORT); sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->io, chip->irq); // (4) Alloc components. err = snd_vortex_mixer(chip); if (err < 0) return err; // ADB pcm. err = snd_vortex_new_pcm(chip, VORTEX_PCM_ADB, NR_PCM); if (err < 0) return err; #ifndef CHIP_AU8820 // ADB SPDIF err = snd_vortex_new_pcm(chip, VORTEX_PCM_SPDIF, 1); if (err < 0) return err; // A3D err = snd_vortex_new_pcm(chip, VORTEX_PCM_A3D, NR_A3D); if (err < 0) return err; #endif /* // ADB I2S if ((err = snd_vortex_new_pcm(chip, VORTEX_PCM_I2S, 1)) < 0) { return err; } */ #ifndef CHIP_AU8810 // WT pcm. err = snd_vortex_new_pcm(chip, VORTEX_PCM_WT, NR_WT); if (err < 0) return err; #endif err = snd_vortex_midi(chip); if (err < 0) return err; vortex_gameport_register(chip); #if 0 if (snd_seq_device_new(card, 1, SNDRV_SEQ_DEV_ID_VORTEX_SYNTH, sizeof(snd_vortex_synth_arg_t), &wave) < 0 || wave == NULL) { dev_err(card->dev, "Can't initialize Aureal wavetable synth\n"); } else { snd_vortex_synth_arg_t *arg; arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); strcpy(wave->name, "Aureal Synth"); arg->hwptr = vortex; arg->index = 1; arg->seq_ports = seq_ports[dev]; arg->max_voices = max_synth_voices[dev]; } #endif // (5) err = pci_read_config_word(pci, PCI_DEVICE_ID, &chip->device); if (err < 0) return err; err = pci_read_config_word(pci, PCI_VENDOR_ID, &chip->vendor); if (err < 0) return err; chip->rev = pci->revision; #ifdef CHIP_AU8830 if ((chip->rev) != 0xfe && (chip->rev) != 0xfa) { dev_alert(card->dev, "The revision (%x) of your card has not been seen before.\n", chip->rev); dev_alert(card->dev, "Please email the results of 'lspci -vv' to [email protected].\n"); return -ENODEV; } #endif // (6) err = snd_card_register(card); if (err < 0) return err; // (7) pci_set_drvdata(pci, card); dev++; vortex_connect_default(chip, 1); vortex_enable_int(chip); return 0; } static int snd_vortex_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_vortex_probe(pci, pci_id)); } // pci_driver definition static struct pci_driver vortex_driver = { .name = KBUILD_MODNAME, .id_table = snd_vortex_ids, .probe = snd_vortex_probe, }; module_pci_driver(vortex_driver);
linux-master
sound/pci/au88x0/au88x0.c
// SPDX-License-Identifier: GPL-2.0-or-later /* */ /* * Vortex PCM ALSA driver. * * Supports ADB and WT DMA. Unfortunately, WT channels do not run yet. * It remains stuck,and DMA transfers do not happen. */ #include <sound/asoundef.h> #include <linux/time.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include "au88x0.h" #define VORTEX_PCM_TYPE(x) (x->name[40]) /* hardware definition */ static const struct snd_pcm_hardware snd_vortex_playback_hw_adb = { .info = (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 5000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 0x10000, .period_bytes_min = 0x20, .period_bytes_max = 0x1000, .periods_min = 2, .periods_max = 1024, }; #ifndef CHIP_AU8820 static const struct snd_pcm_hardware snd_vortex_playback_hw_a3d = { .info = (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 5000, .rate_max = 48000, .channels_min = 1, .channels_max = 1, .buffer_bytes_max = 0x10000, .period_bytes_min = 0x100, .period_bytes_max = 0x1000, .periods_min = 2, .periods_max = 64, }; #endif static const struct snd_pcm_hardware snd_vortex_playback_hw_spdif = { .info = (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE | SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, .rate_min = 32000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 0x10000, .period_bytes_min = 0x100, .period_bytes_max = 0x1000, .periods_min = 2, .periods_max = 64, }; #ifndef CHIP_AU8810 static const struct snd_pcm_hardware snd_vortex_playback_hw_wt = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_LE, .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS, // SNDRV_PCM_RATE_48000, .rate_min = 8000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 0x10000, .period_bytes_min = 0x0400, .period_bytes_max = 0x1000, .periods_min = 2, .periods_max = 64, }; #endif #ifdef CHIP_AU8830 static const unsigned int au8830_channels[3] = { 1, 2, 4, }; static const struct snd_pcm_hw_constraint_list hw_constraints_au8830_channels = { .count = ARRAY_SIZE(au8830_channels), .list = au8830_channels, .mask = 0, }; #endif static void vortex_notify_pcm_vol_change(struct snd_card *card, struct snd_kcontrol *kctl, int activate) { if (activate) kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; else kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &(kctl->id)); } /* open callback */ static int snd_vortex_pcm_open(struct snd_pcm_substream *substream) { vortex_t *vortex = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err; /* Force equal size periods */ err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (err < 0) return err; /* Avoid PAGE_SIZE boundary to fall inside of a period. */ err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES); if (err < 0) return err; snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 64); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) { #ifndef CHIP_AU8820 if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_A3D) { runtime->hw = snd_vortex_playback_hw_a3d; } #endif if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_SPDIF) { runtime->hw = snd_vortex_playback_hw_spdif; switch (vortex->spdif_sr) { case 32000: runtime->hw.rates = SNDRV_PCM_RATE_32000; break; case 44100: runtime->hw.rates = SNDRV_PCM_RATE_44100; break; case 48000: runtime->hw.rates = SNDRV_PCM_RATE_48000; break; } } if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB || VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_I2S) runtime->hw = snd_vortex_playback_hw_adb; #ifdef CHIP_AU8830 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && VORTEX_IS_QUAD(vortex) && VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) { runtime->hw.channels_max = 4; snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_au8830_channels); } #endif substream->runtime->private_data = NULL; } #ifndef CHIP_AU8810 else { runtime->hw = snd_vortex_playback_hw_wt; substream->runtime->private_data = NULL; } #endif return 0; } /* close callback */ static int snd_vortex_pcm_close(struct snd_pcm_substream *substream) { //vortex_t *chip = snd_pcm_substream_chip(substream); stream_t *stream = (stream_t *) substream->runtime->private_data; // the hardware-specific codes will be here if (stream != NULL) { stream->substream = NULL; stream->nr_ch = 0; } substream->runtime->private_data = NULL; return 0; } /* hw_params callback */ static int snd_vortex_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { vortex_t *chip = snd_pcm_substream_chip(substream); stream_t *stream = (stream_t *) (substream->runtime->private_data); /* pr_info( "Vortex: periods %d, period_bytes %d, channels = %d\n", params_periods(hw_params), params_period_bytes(hw_params), params_channels(hw_params)); */ spin_lock_irq(&chip->lock); // Make audio routes and config buffer DMA. if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) { int dma, type = VORTEX_PCM_TYPE(substream->pcm); /* Dealloc any routes. */ if (stream != NULL) vortex_adb_allocroute(chip, stream->dma, stream->nr_ch, stream->dir, stream->type, substream->number); /* Alloc routes. */ dma = vortex_adb_allocroute(chip, -1, params_channels(hw_params), substream->stream, type, substream->number); if (dma < 0) { spin_unlock_irq(&chip->lock); return dma; } stream = substream->runtime->private_data = &chip->dma_adb[dma]; stream->substream = substream; /* Setup Buffers. */ vortex_adbdma_setbuffers(chip, dma, params_period_bytes(hw_params), params_periods(hw_params)); if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) { chip->pcm_vol[substream->number].active = 1; vortex_notify_pcm_vol_change(chip->card, chip->pcm_vol[substream->number].kctl, 1); } } #ifndef CHIP_AU8810 else { /* if (stream != NULL) vortex_wt_allocroute(chip, substream->number, 0); */ vortex_wt_allocroute(chip, substream->number, params_channels(hw_params)); stream = substream->runtime->private_data = &chip->dma_wt[substream->number]; stream->dma = substream->number; stream->substream = substream; vortex_wtdma_setbuffers(chip, substream->number, params_period_bytes(hw_params), params_periods(hw_params)); } #endif spin_unlock_irq(&chip->lock); return 0; } /* hw_free callback */ static int snd_vortex_pcm_hw_free(struct snd_pcm_substream *substream) { vortex_t *chip = snd_pcm_substream_chip(substream); stream_t *stream = (stream_t *) (substream->runtime->private_data); spin_lock_irq(&chip->lock); // Delete audio routes. if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) { if (stream != NULL) { if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) { chip->pcm_vol[substream->number].active = 0; vortex_notify_pcm_vol_change(chip->card, chip->pcm_vol[substream->number].kctl, 0); } vortex_adb_allocroute(chip, stream->dma, stream->nr_ch, stream->dir, stream->type, substream->number); } } #ifndef CHIP_AU8810 else { if (stream != NULL) vortex_wt_allocroute(chip, stream->dma, 0); } #endif substream->runtime->private_data = NULL; spin_unlock_irq(&chip->lock); return 0; } /* prepare callback */ static int snd_vortex_pcm_prepare(struct snd_pcm_substream *substream) { vortex_t *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; stream_t *stream = (stream_t *) substream->runtime->private_data; int dma = stream->dma, fmt, dir; // set up the hardware with the current configuration. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 1; else dir = 0; fmt = vortex_alsafmt_aspfmt(runtime->format, chip); spin_lock_irq(&chip->lock); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) { vortex_adbdma_setmode(chip, dma, 1, dir, fmt, runtime->channels == 1 ? 0 : 1, 0); vortex_adbdma_setstartbuffer(chip, dma, 0); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_SPDIF) vortex_adb_setsrc(chip, dma, runtime->rate, dir); } #ifndef CHIP_AU8810 else { vortex_wtdma_setmode(chip, dma, 1, fmt, 0, 0); // FIXME: Set rate (i guess using vortex_wt_writereg() somehow). vortex_wtdma_setstartbuffer(chip, dma, 0); } #endif spin_unlock_irq(&chip->lock); return 0; } /* trigger callback */ static int snd_vortex_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { vortex_t *chip = snd_pcm_substream_chip(substream); stream_t *stream = (stream_t *) substream->runtime->private_data; int dma = stream->dma; spin_lock(&chip->lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: // do something to start the PCM engine //printk(KERN_INFO "vortex: start %d\n", dma); stream->fifo_enabled = 1; if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) { vortex_adbdma_resetup(chip, dma); vortex_adbdma_startfifo(chip, dma); } #ifndef CHIP_AU8810 else { dev_info(chip->card->dev, "wt start %d\n", dma); vortex_wtdma_startfifo(chip, dma); } #endif break; case SNDRV_PCM_TRIGGER_STOP: // do something to stop the PCM engine //printk(KERN_INFO "vortex: stop %d\n", dma); stream->fifo_enabled = 0; if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) vortex_adbdma_stopfifo(chip, dma); #ifndef CHIP_AU8810 else { dev_info(chip->card->dev, "wt stop %d\n", dma); vortex_wtdma_stopfifo(chip, dma); } #endif break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: //printk(KERN_INFO "vortex: pause %d\n", dma); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) vortex_adbdma_pausefifo(chip, dma); #ifndef CHIP_AU8810 else vortex_wtdma_pausefifo(chip, dma); #endif break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: //printk(KERN_INFO "vortex: resume %d\n", dma); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) vortex_adbdma_resumefifo(chip, dma); #ifndef CHIP_AU8810 else vortex_wtdma_resumefifo(chip, dma); #endif break; default: spin_unlock(&chip->lock); return -EINVAL; } spin_unlock(&chip->lock); return 0; } /* pointer callback */ static snd_pcm_uframes_t snd_vortex_pcm_pointer(struct snd_pcm_substream *substream) { vortex_t *chip = snd_pcm_substream_chip(substream); stream_t *stream = (stream_t *) substream->runtime->private_data; int dma = stream->dma; snd_pcm_uframes_t current_ptr = 0; spin_lock(&chip->lock); if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) current_ptr = vortex_adbdma_getlinearpos(chip, dma); #ifndef CHIP_AU8810 else current_ptr = vortex_wtdma_getlinearpos(chip, dma); #endif //printk(KERN_INFO "vortex: pointer = 0x%x\n", current_ptr); spin_unlock(&chip->lock); current_ptr = bytes_to_frames(substream->runtime, current_ptr); if (current_ptr >= substream->runtime->buffer_size) current_ptr = 0; return current_ptr; } /* operators */ static const struct snd_pcm_ops snd_vortex_playback_ops = { .open = snd_vortex_pcm_open, .close = snd_vortex_pcm_close, .hw_params = snd_vortex_pcm_hw_params, .hw_free = snd_vortex_pcm_hw_free, .prepare = snd_vortex_pcm_prepare, .trigger = snd_vortex_pcm_trigger, .pointer = snd_vortex_pcm_pointer, }; /* * definitions of capture are omitted here... */ static const char * const vortex_pcm_prettyname[VORTEX_PCM_LAST] = { CARD_NAME " ADB", CARD_NAME " SPDIF", CARD_NAME " A3D", CARD_NAME " WT", CARD_NAME " I2S", }; static const char * const vortex_pcm_name[VORTEX_PCM_LAST] = { "adb", "spdif", "a3d", "wt", "i2s", }; /* SPDIF kcontrol */ static int snd_vortex_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_vortex_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = 0xff; ucontrol->value.iec958.status[1] = 0xff; ucontrol->value.iec958.status[2] = 0xff; ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS; return 0; } static int snd_vortex_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); ucontrol->value.iec958.status[0] = 0x00; ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL|IEC958_AES1_CON_DIGDIGCONV_ID; ucontrol->value.iec958.status[2] = 0x00; switch (vortex->spdif_sr) { case 32000: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_32000; break; case 44100: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_44100; break; case 48000: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000; break; } return 0; } static int snd_vortex_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); int spdif_sr = 48000; switch (ucontrol->value.iec958.status[3] & IEC958_AES3_CON_FS) { case IEC958_AES3_CON_FS_32000: spdif_sr = 32000; break; case IEC958_AES3_CON_FS_44100: spdif_sr = 44100; break; case IEC958_AES3_CON_FS_48000: spdif_sr = 48000; break; } if (spdif_sr == vortex->spdif_sr) return 0; vortex->spdif_sr = spdif_sr; vortex_spdif_init(vortex, vortex->spdif_sr, 1); return 1; } /* spdif controls */ static const struct snd_kcontrol_new snd_vortex_mixer_spdif[] = { { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = snd_vortex_spdif_info, .get = snd_vortex_spdif_get, .put = snd_vortex_spdif_put, }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), .info = snd_vortex_spdif_info, .get = snd_vortex_spdif_mask_get }, }; /* subdevice PCM Volume control */ static int snd_vortex_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { vortex_t *vortex = snd_kcontrol_chip(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = (VORTEX_IS_QUAD(vortex) ? 4 : 2); uinfo->value.integer.min = -128; uinfo->value.integer.max = 32; return 0; } static int snd_vortex_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int i; vortex_t *vortex = snd_kcontrol_chip(kcontrol); int subdev = kcontrol->id.subdevice; struct pcm_vol *p = &vortex->pcm_vol[subdev]; int max_chn = (VORTEX_IS_QUAD(vortex) ? 4 : 2); for (i = 0; i < max_chn; i++) ucontrol->value.integer.value[i] = p->vol[i]; return 0; } static int snd_vortex_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int i; int changed = 0; int mixin; unsigned char vol; vortex_t *vortex = snd_kcontrol_chip(kcontrol); int subdev = kcontrol->id.subdevice; struct pcm_vol *p = &vortex->pcm_vol[subdev]; int max_chn = (VORTEX_IS_QUAD(vortex) ? 4 : 2); for (i = 0; i < max_chn; i++) { if (p->vol[i] != ucontrol->value.integer.value[i]) { p->vol[i] = ucontrol->value.integer.value[i]; if (p->active) { switch (vortex->dma_adb[p->dma].nr_ch) { case 1: mixin = p->mixin[0]; break; case 2: default: mixin = p->mixin[(i < 2) ? i : (i - 2)]; break; case 4: mixin = p->mixin[i]; break; } vol = p->vol[i]; vortex_mix_setinputvolumebyte(vortex, vortex->mixplayb[i], mixin, vol); } changed = 1; } } return changed; } static const DECLARE_TLV_DB_MINMAX(vortex_pcm_vol_db_scale, -9600, 2400); static const struct snd_kcontrol_new snd_vortex_pcm_vol = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = "PCM Playback Volume", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .info = snd_vortex_pcm_vol_info, .get = snd_vortex_pcm_vol_get, .put = snd_vortex_pcm_vol_put, .tlv = { .p = vortex_pcm_vol_db_scale }, }; /* create a pcm device */ static int snd_vortex_new_pcm(vortex_t *chip, int idx, int nr) { struct snd_pcm *pcm; struct snd_kcontrol *kctl; int i; int err, nr_capt; if (!chip || idx < 0 || idx >= VORTEX_PCM_LAST) return -ENODEV; /* idx indicates which kind of PCM device. ADB, SPDIF, I2S and A3D share the * same dma engine. WT uses it own separate dma engine which can't capture. */ if (idx == VORTEX_PCM_ADB) nr_capt = nr; else nr_capt = 0; err = snd_pcm_new(chip->card, vortex_pcm_prettyname[idx], idx, nr, nr_capt, &pcm); if (err < 0) return err; snprintf(pcm->name, sizeof(pcm->name), "%s %s", CARD_NAME_SHORT, vortex_pcm_name[idx]); chip->pcm[idx] = pcm; // This is an evil hack, but it saves a lot of duplicated code. VORTEX_PCM_TYPE(pcm) = idx; pcm->private_data = chip; /* set operators */ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vortex_playback_ops); if (idx == VORTEX_PCM_ADB) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_vortex_playback_ops); /* pre-allocation of Scatter-Gather buffers */ snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci_dev->dev, 0x10000, 0x10000); switch (VORTEX_PCM_TYPE(pcm)) { case VORTEX_PCM_ADB: err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_std_chmaps, VORTEX_IS_QUAD(chip) ? 4 : 2, 0, NULL); if (err < 0) return err; err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_CAPTURE, snd_pcm_std_chmaps, 2, 0, NULL); if (err < 0) return err; break; #ifdef CHIP_AU8830 case VORTEX_PCM_A3D: err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_std_chmaps, 1, 0, NULL); if (err < 0) return err; break; #endif } if (VORTEX_PCM_TYPE(pcm) == VORTEX_PCM_SPDIF) { for (i = 0; i < ARRAY_SIZE(snd_vortex_mixer_spdif); i++) { kctl = snd_ctl_new1(&snd_vortex_mixer_spdif[i], chip); if (!kctl) return -ENOMEM; err = snd_ctl_add(chip->card, kctl); if (err < 0) return err; } } if (VORTEX_PCM_TYPE(pcm) == VORTEX_PCM_ADB) { for (i = 0; i < NR_PCM; i++) { chip->pcm_vol[i].active = 0; chip->pcm_vol[i].dma = -1; kctl = snd_ctl_new1(&snd_vortex_pcm_vol, chip); if (!kctl) return -ENOMEM; chip->pcm_vol[i].kctl = kctl; kctl->id.device = 0; kctl->id.subdevice = i; err = snd_ctl_add(chip->card, kctl); if (err < 0) return err; } } return 0; }
linux-master
sound/pci/au88x0/au88x0_pcm.c
// SPDX-License-Identifier: GPL-2.0 /* Data structs */ static const u16 asEqCoefsZeros[50] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; static const u16 asEqCoefsPipes[64] = { 0x0000, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0666, 0x0000, 0x0000, 0x066a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; /* More coef sets can be found in the win2k "inf" file. */ static const auxxEqCoeffSet_t asEqCoefsNormal = { .LeftCoefs = { 0x7e60, 0xc19e, 0x0001, 0x0002, 0x0001, 0x7fa0, 0xc05f, 0x004f, 0x0000, 0xffb1, 0x7f3f, 0xc0bc, 0x00c2, 0x0000, 0xff3e, 0x7e78, 0xc177, 0x011f, 0x0000, 0xfee1, 0x7cd6, 0xc2e5, 0x025c, 0x0000, 0xfda4, 0x7949, 0xc5aa, 0x0467, 0x0000, 0xfb99, 0x7120, 0xcadf, 0x0864, 0x0000, 0xf79c, 0x5d33, 0xd430, 0x0f7e, 0x0000, 0xf082, 0x2beb, 0xe3ca, 0x1bd3, 0x0000, 0xe42d, 0xd740, 0xf01d, 0x2ac5, 0x0000, 0xd53b}, .RightCoefs = { 0x7e60, 0xc19e, 0x0001, 0x0002, 0x0001, 0x7fa0, 0xc05f, 0x004f, 0x0000, 0xffb1, 0x7f3f, 0xc0bc, 0x00c2, 0x0000, 0xff3e, 0x7e78, 0xc177, 0x011f, 0x0000, 0xfee1, 0x7cd6, 0xc2e5, 0x025c, 0x0000, 0xfda4, 0x7949, 0xc5aa, 0x0467, 0x0000, 0xfb99, 0x7120, 0xcadf, 0x0864, 0x0000, 0xf79c, 0x5d33, 0xd430, 0x0f7e, 0x0000, 0xf082, 0x2beb, 0xe3ca, 0x1bd3, 0x0000, 0xe42d, 0xd740, 0xf01d, 0x2ac5, 0x0000, 0xd53b}, .LeftGains = { 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96}, .RightGains = { 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96} }; static const u16 eq_gains_normal[20] = { 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96 }; /* _rodatab60 */ static const u16 eq_gains_zero[10] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; /* _rodatab7c: ProgramPipe */ static const u16 eq_gains_current[12] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff }; /* _rodatab78 */ static const u16 eq_states_zero[2] = { 0x0000, 0x0000 }; static const u16 asEqOutStateZeros[48] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; /*_rodataba0:*/ static const u16 eq_levels[64] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 };
linux-master
sound/pci/au88x0/au88x0_eqdata.c
// SPDX-License-Identifier: GPL-2.0 #include "au8830.h" #include "au88x0.h" static const struct pci_device_id snd_vortex_ids[] = { {PCI_VDEVICE(AUREAL, PCI_DEVICE_ID_AUREAL_VORTEX_2), 0,}, {0,} }; #include "au88x0_synth.c" #include "au88x0_core.c" #include "au88x0_pcm.c" #include "au88x0_mixer.c" #include "au88x0_mpu401.c" #include "au88x0_game.c" #include "au88x0_eq.c" #include "au88x0_a3d.c" #include "au88x0_xtalk.c" #include "au88x0.c"
linux-master
sound/pci/au88x0/au8830.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram pcxhr compatible soundcards * * low level interface with interrupt and message handling implementation * * Copyright (c) 2004 by Digigram <[email protected]> */ #include <linux/delay.h> #include <linux/firmware.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/io.h> #include <sound/core.h> #include "pcxhr.h" #include "pcxhr_mixer.h" #include "pcxhr_hwdep.h" #include "pcxhr_core.h" /* registers used on the PLX (port 1) */ #define PCXHR_PLX_OFFSET_MIN 0x40 #define PCXHR_PLX_MBOX0 0x40 #define PCXHR_PLX_MBOX1 0x44 #define PCXHR_PLX_MBOX2 0x48 #define PCXHR_PLX_MBOX3 0x4C #define PCXHR_PLX_MBOX4 0x50 #define PCXHR_PLX_MBOX5 0x54 #define PCXHR_PLX_MBOX6 0x58 #define PCXHR_PLX_MBOX7 0x5C #define PCXHR_PLX_L2PCIDB 0x64 #define PCXHR_PLX_IRQCS 0x68 #define PCXHR_PLX_CHIPSC 0x6C /* registers used on the DSP (port 2) */ #define PCXHR_DSP_ICR 0x00 #define PCXHR_DSP_CVR 0x04 #define PCXHR_DSP_ISR 0x08 #define PCXHR_DSP_IVR 0x0C #define PCXHR_DSP_RXH 0x14 #define PCXHR_DSP_TXH 0x14 #define PCXHR_DSP_RXM 0x18 #define PCXHR_DSP_TXM 0x18 #define PCXHR_DSP_RXL 0x1C #define PCXHR_DSP_TXL 0x1C #define PCXHR_DSP_RESET 0x20 #define PCXHR_DSP_OFFSET_MAX 0x20 /* access to the card */ #define PCXHR_PLX 1 #define PCXHR_DSP 2 #if (PCXHR_DSP_OFFSET_MAX > PCXHR_PLX_OFFSET_MIN) #error PCXHR_REG_TO_PORT(x) #else #define PCXHR_REG_TO_PORT(x) ((x)>PCXHR_DSP_OFFSET_MAX ? PCXHR_PLX : PCXHR_DSP) #endif #define PCXHR_INPB(mgr,x) inb((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x)) #define PCXHR_INPL(mgr,x) inl((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x)) #define PCXHR_OUTPB(mgr,x,data) outb((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x)) #define PCXHR_OUTPL(mgr,x,data) outl((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x)) /* attention : access the PCXHR_DSP_* registers with inb and outb only ! */ /* params used with PCXHR_PLX_MBOX0 */ #define PCXHR_MBOX0_HF5 (1 << 0) #define PCXHR_MBOX0_HF4 (1 << 1) #define PCXHR_MBOX0_BOOT_HERE (1 << 23) /* params used with PCXHR_PLX_IRQCS */ #define PCXHR_IRQCS_ENABLE_PCIIRQ (1 << 8) #define PCXHR_IRQCS_ENABLE_PCIDB (1 << 9) #define PCXHR_IRQCS_ACTIVE_PCIDB (1 << 13) /* params used with PCXHR_PLX_CHIPSC */ #define PCXHR_CHIPSC_INIT_VALUE 0x100D767E #define PCXHR_CHIPSC_RESET_XILINX (1 << 16) #define PCXHR_CHIPSC_GPI_USERI (1 << 17) #define PCXHR_CHIPSC_DATA_CLK (1 << 24) #define PCXHR_CHIPSC_DATA_IN (1 << 26) /* params used with PCXHR_DSP_ICR */ #define PCXHR_ICR_HI08_RREQ 0x01 #define PCXHR_ICR_HI08_TREQ 0x02 #define PCXHR_ICR_HI08_HDRQ 0x04 #define PCXHR_ICR_HI08_HF0 0x08 #define PCXHR_ICR_HI08_HF1 0x10 #define PCXHR_ICR_HI08_HLEND 0x20 #define PCXHR_ICR_HI08_INIT 0x80 /* params used with PCXHR_DSP_CVR */ #define PCXHR_CVR_HI08_HC 0x80 /* params used with PCXHR_DSP_ISR */ #define PCXHR_ISR_HI08_RXDF 0x01 #define PCXHR_ISR_HI08_TXDE 0x02 #define PCXHR_ISR_HI08_TRDY 0x04 #define PCXHR_ISR_HI08_ERR 0x08 #define PCXHR_ISR_HI08_CHK 0x10 #define PCXHR_ISR_HI08_HREQ 0x80 /* constants used for delay in msec */ #define PCXHR_WAIT_DEFAULT 2 #define PCXHR_WAIT_IT 25 #define PCXHR_WAIT_IT_EXTRA 65 /* * pcxhr_check_reg_bit - wait for the specified bit is set/reset on a register * @reg: register to check * @mask: bit mask * @bit: resultant bit to be checked * @time: time-out of loop in msec * * returns zero if a bit matches, or a negative error code. */ static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg, unsigned char mask, unsigned char bit, int time, unsigned char* read) { int i = 0; unsigned long end_time = jiffies + (time * HZ + 999) / 1000; do { *read = PCXHR_INPB(mgr, reg); if ((*read & mask) == bit) { if (i > 100) dev_dbg(&mgr->pci->dev, "ATTENTION! check_reg(%x) loopcount=%d\n", reg, i); return 0; } i++; } while (time_after_eq(end_time, jiffies)); dev_err(&mgr->pci->dev, "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=%x\n", reg, mask, *read); return -EIO; } /* constants used with pcxhr_check_reg_bit() */ #define PCXHR_TIMEOUT_DSP 200 #define PCXHR_MASK_EXTRA_INFO 0x0000FE #define PCXHR_MASK_IT_HF0 0x000100 #define PCXHR_MASK_IT_HF1 0x000200 #define PCXHR_MASK_IT_NO_HF0_HF1 0x000400 #define PCXHR_MASK_IT_MANAGE_HF5 0x000800 #define PCXHR_MASK_IT_WAIT 0x010000 #define PCXHR_MASK_IT_WAIT_EXTRA 0x020000 #define PCXHR_IT_SEND_BYTE_XILINX (0x0000003C | PCXHR_MASK_IT_HF0) #define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \ PCXHR_MASK_IT_MANAGE_HF5) #define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \ PCXHR_MASK_IT_MANAGE_HF5 | \ PCXHR_MASK_IT_WAIT) #define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \ PCXHR_MASK_IT_MANAGE_HF5 | \ PCXHR_MASK_IT_WAIT_EXTRA) #define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \ PCXHR_MASK_IT_MANAGE_HF5 | \ PCXHR_MASK_IT_WAIT) #define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1) #define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1) #define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1) #define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1) #define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1) static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atomic) { int err; unsigned char reg; if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { /* clear hf5 bit */ PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5); } if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) { reg = (PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ); if (itdsp & PCXHR_MASK_IT_HF0) reg |= PCXHR_ICR_HI08_HF0; if (itdsp & PCXHR_MASK_IT_HF1) reg |= PCXHR_ICR_HI08_HF1; PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); } reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | PCXHR_CVR_HI08_HC); PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg); if (itdsp & PCXHR_MASK_IT_WAIT) { if (atomic) mdelay(PCXHR_WAIT_IT); else msleep(PCXHR_WAIT_IT); } if (itdsp & PCXHR_MASK_IT_WAIT_EXTRA) { if (atomic) mdelay(PCXHR_WAIT_IT_EXTRA); else msleep(PCXHR_WAIT_IT); } /* wait for CVR_HI08_HC == 0 */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_CVR, PCXHR_CVR_HI08_HC, 0, PCXHR_TIMEOUT_DSP, &reg); if (err) { dev_err(&mgr->pci->dev, "pcxhr_send_it_dsp : TIMEOUT CVR\n"); return err; } if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { /* wait for hf5 bit */ err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5, PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &reg); if (err) { dev_err(&mgr->pci->dev, "pcxhr_send_it_dsp : TIMEOUT HF5\n"); return err; } } return 0; /* retry not handled here */ } void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr) { /* reset second xilinx */ PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, PCXHR_CHIPSC_INIT_VALUE & ~PCXHR_CHIPSC_RESET_XILINX); } static void pcxhr_enable_irq(struct pcxhr_mgr *mgr, int enable) { unsigned int reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); /* enable/disable interrupts */ if (enable) reg |= (PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB); else reg &= ~(PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB); PCXHR_OUTPL(mgr, PCXHR_PLX_IRQCS, reg); } void pcxhr_reset_dsp(struct pcxhr_mgr *mgr) { /* disable interrupts */ pcxhr_enable_irq(mgr, 0); /* let's reset the DSP */ PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 0); msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */ PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 3); msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */ /* reset mailbox */ PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, 0); } void pcxhr_enable_dsp(struct pcxhr_mgr *mgr) { /* enable interrupts */ pcxhr_enable_irq(mgr, 1); } /* * load the xilinx image */ int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second) { unsigned int i; unsigned int chipsc; unsigned char data; unsigned char mask; const unsigned char *image; /* test first xilinx */ chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC); /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */ /* this bit will always be 1; * no possibility to test presence of first xilinx */ if(second) { if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) { dev_err(&mgr->pci->dev, "error loading first xilinx\n"); return -EINVAL; } /* activate second xilinx */ chipsc |= PCXHR_CHIPSC_RESET_XILINX; PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */ } image = xilinx->data; for (i = 0; i < xilinx->size; i++, image++) { data = *image; mask = 0x80; while (mask) { chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN); if (data & mask) chipsc |= PCXHR_CHIPSC_DATA_IN; PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); chipsc |= PCXHR_CHIPSC_DATA_CLK; PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); mask >>= 1; } /* don't take too much time in this loop... */ cond_resched(); } chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN); PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); /* wait 2 msec (time to boot the xilinx before any access) */ msleep( PCXHR_WAIT_DEFAULT ); return 0; } /* * send an executable file to the DSP */ static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp) { int err; unsigned int i; unsigned int len; const unsigned char *data; unsigned char dummy; /* check the length of boot image */ if (dsp->size <= 0) return -EINVAL; if (dsp->size % 3) return -EINVAL; if (snd_BUG_ON(!dsp->data)) return -EINVAL; /* transfert data buffer from PC to DSP */ for (i = 0; i < dsp->size; i += 3) { data = dsp->data + i; if (i == 0) { /* test data header consistency */ len = (unsigned int)((data[0]<<16) + (data[1]<<8) + data[2]); if (len && (dsp->size != (len + 2) * 3)) return -EINVAL; } /* wait DSP ready for new transfer */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &dummy); if (err) { dev_err(&mgr->pci->dev, "dsp loading error at position %d\n", i); return err; } /* send host data */ PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, data[0]); PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, data[1]); PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, data[2]); /* don't take too much time in this loop... */ cond_resched(); } /* give some time to boot the DSP */ msleep(PCXHR_WAIT_DEFAULT); return 0; } /* * load the eeprom image */ int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom) { int err; unsigned char reg; /* init value of the ICR register */ reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) { /* no need to load the eeprom binary, * but init the HI08 interface */ PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT); msleep(PCXHR_WAIT_DEFAULT); PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); msleep(PCXHR_WAIT_DEFAULT); dev_dbg(&mgr->pci->dev, "no need to load eeprom boot\n"); return 0; } PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); err = pcxhr_download_dsp(mgr, eeprom); if (err) return err; /* wait for chk bit */ return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg); } /* * load the boot image */ int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot) { int err; unsigned int physaddr = mgr->hostport.addr; unsigned char dummy; /* send the hostport address to the DSP (only the upper 24 bit !) */ if (snd_BUG_ON(physaddr & 0xff)) return -EINVAL; PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX1, (physaddr >> 8)); err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_BOOT, 0); if (err) return err; /* clear hf5 bit */ PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5); err = pcxhr_download_dsp(mgr, boot); if (err) return err; /* wait for hf5 bit */ return pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5, PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &dummy); } /* * load the final dsp image */ int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp) { int err; unsigned char dummy; err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_BOARD_FUNC, 0); if (err) return err; err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_DSP, 0); if (err) return err; err = pcxhr_download_dsp(mgr, dsp); if (err) return err; /* wait for chk bit */ return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &dummy); } struct pcxhr_cmd_info { u32 opcode; /* command word */ u16 st_length; /* status length */ u16 st_type; /* status type (RMH_SSIZE_XXX) */ }; /* RMH status type */ enum { RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */ RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ RMH_SSIZE_MASK = 2, /* status size given in bitmask */ }; /* * Array of DSP commands */ static const struct pcxhr_cmd_info pcxhr_dsp_cmds[] = { [CMD_VERSION] = { 0x010000, 1, RMH_SSIZE_FIXED }, [CMD_SUPPORTED] = { 0x020000, 4, RMH_SSIZE_FIXED }, [CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED }, [CMD_SEND_IRQA] = { 0x070001, 0, RMH_SSIZE_FIXED }, [CMD_ACCESS_IO_WRITE] = { 0x090000, 1, RMH_SSIZE_ARG }, [CMD_ACCESS_IO_READ] = { 0x094000, 1, RMH_SSIZE_ARG }, [CMD_ASYNC] = { 0x0a0000, 1, RMH_SSIZE_ARG }, [CMD_MODIFY_CLOCK] = { 0x0d0000, 0, RMH_SSIZE_FIXED }, [CMD_RESYNC_AUDIO_INPUTS] = { 0x0e0000, 0, RMH_SSIZE_FIXED }, [CMD_GET_DSP_RESOURCES] = { 0x100000, 4, RMH_SSIZE_FIXED }, [CMD_SET_TIMER_INTERRUPT] = { 0x110000, 0, RMH_SSIZE_FIXED }, [CMD_RES_PIPE] = { 0x400000, 0, RMH_SSIZE_FIXED }, [CMD_FREE_PIPE] = { 0x410000, 0, RMH_SSIZE_FIXED }, [CMD_CONF_PIPE] = { 0x422101, 0, RMH_SSIZE_FIXED }, [CMD_STOP_PIPE] = { 0x470004, 0, RMH_SSIZE_FIXED }, [CMD_PIPE_SAMPLE_COUNT] = { 0x49a000, 2, RMH_SSIZE_FIXED }, [CMD_CAN_START_PIPE] = { 0x4b0000, 1, RMH_SSIZE_FIXED }, [CMD_START_STREAM] = { 0x802000, 0, RMH_SSIZE_FIXED }, [CMD_STREAM_OUT_LEVEL_ADJUST] = { 0x822000, 0, RMH_SSIZE_FIXED }, [CMD_STOP_STREAM] = { 0x832000, 0, RMH_SSIZE_FIXED }, [CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED }, [CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED }, [CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED }, [CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, [CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED }, [CMD_GET_TIME_CODE] = { 0x060000, 5, RMH_SSIZE_FIXED }, [CMD_MANAGE_SIGNAL] = { 0x0f0000, 0, RMH_SSIZE_FIXED }, }; #ifdef CONFIG_SND_DEBUG_VERBOSE static const char * const cmd_names[] = { [CMD_VERSION] = "CMD_VERSION", [CMD_SUPPORTED] = "CMD_SUPPORTED", [CMD_TEST_IT] = "CMD_TEST_IT", [CMD_SEND_IRQA] = "CMD_SEND_IRQA", [CMD_ACCESS_IO_WRITE] = "CMD_ACCESS_IO_WRITE", [CMD_ACCESS_IO_READ] = "CMD_ACCESS_IO_READ", [CMD_ASYNC] = "CMD_ASYNC", [CMD_MODIFY_CLOCK] = "CMD_MODIFY_CLOCK", [CMD_RESYNC_AUDIO_INPUTS] = "CMD_RESYNC_AUDIO_INPUTS", [CMD_GET_DSP_RESOURCES] = "CMD_GET_DSP_RESOURCES", [CMD_SET_TIMER_INTERRUPT] = "CMD_SET_TIMER_INTERRUPT", [CMD_RES_PIPE] = "CMD_RES_PIPE", [CMD_FREE_PIPE] = "CMD_FREE_PIPE", [CMD_CONF_PIPE] = "CMD_CONF_PIPE", [CMD_STOP_PIPE] = "CMD_STOP_PIPE", [CMD_PIPE_SAMPLE_COUNT] = "CMD_PIPE_SAMPLE_COUNT", [CMD_CAN_START_PIPE] = "CMD_CAN_START_PIPE", [CMD_START_STREAM] = "CMD_START_STREAM", [CMD_STREAM_OUT_LEVEL_ADJUST] = "CMD_STREAM_OUT_LEVEL_ADJUST", [CMD_STOP_STREAM] = "CMD_STOP_STREAM", [CMD_UPDATE_R_BUFFERS] = "CMD_UPDATE_R_BUFFERS", [CMD_FORMAT_STREAM_OUT] = "CMD_FORMAT_STREAM_OUT", [CMD_FORMAT_STREAM_IN] = "CMD_FORMAT_STREAM_IN", [CMD_STREAM_SAMPLE_COUNT] = "CMD_STREAM_SAMPLE_COUNT", [CMD_AUDIO_LEVEL_ADJUST] = "CMD_AUDIO_LEVEL_ADJUST", [CMD_GET_TIME_CODE] = "CMD_GET_TIME_CODE", [CMD_MANAGE_SIGNAL] = "CMD_MANAGE_SIGNAL", }; #endif static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) { int err; int i; u32 data; u32 size_mask; unsigned char reg; int max_stat_len; if (rmh->stat_len < PCXHR_SIZE_MAX_STATUS) max_stat_len = PCXHR_SIZE_MAX_STATUS; else max_stat_len = rmh->stat_len; for (i = 0; i < rmh->stat_len; i++) { /* wait for receiver full */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg); if (err) { dev_err(&mgr->pci->dev, "ERROR RMH stat: ISR:RXDF=1 (ISR = %x; i=%d )\n", reg, i); return err; } /* read data */ data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16; data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8; data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); /* need to update rmh->stat_len on the fly ?? */ if (!i) { if (rmh->dsp_stat != RMH_SSIZE_FIXED) { if (rmh->dsp_stat == RMH_SSIZE_ARG) { rmh->stat_len = (data & 0x0000ff) + 1; data &= 0xffff00; } else { /* rmh->dsp_stat == RMH_SSIZE_MASK */ rmh->stat_len = 1; size_mask = data; while (size_mask) { if (size_mask & 1) rmh->stat_len++; size_mask >>= 1; } } } } #ifdef CONFIG_SND_DEBUG_VERBOSE if (rmh->cmd_idx < CMD_LAST_INDEX) dev_dbg(&mgr->pci->dev, " stat[%d]=%x\n", i, data); #endif if (i < max_stat_len) rmh->stat[i] = data; } if (rmh->stat_len > max_stat_len) { dev_dbg(&mgr->pci->dev, "PCXHR : rmh->stat_len=%x too big\n", rmh->stat_len); rmh->stat_len = max_stat_len; } return 0; } static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) { int err; int i; u32 data; unsigned char reg; if (snd_BUG_ON(rmh->cmd_len >= PCXHR_SIZE_MAX_CMD)) return -EINVAL; err = pcxhr_send_it_dsp(mgr, PCXHR_IT_MESSAGE, 1); if (err) { dev_err(&mgr->pci->dev, "pcxhr_send_message : ED_DSP_CRASHED\n"); return err; } /* wait for chk bit */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; /* reset irq chk */ err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_CHK, 1); if (err) return err; /* wait for chk bit == 0*/ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, 0, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; data = rmh->cmd[0]; if (rmh->cmd_len > 1) data |= 0x008000; /* MASK_MORE_THAN_1_WORD_COMMAND */ else data &= 0xff7fff; /* MASK_1_WORD_COMMAND */ #ifdef CONFIG_SND_DEBUG_VERBOSE if (rmh->cmd_idx < CMD_LAST_INDEX) dev_dbg(&mgr->pci->dev, "MSG cmd[0]=%x (%s)\n", data, cmd_names[rmh->cmd_idx]); #endif err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF)); if (rmh->cmd_len > 1) { /* send length */ data = rmh->cmd_len - 1; err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF)); for (i=1; i < rmh->cmd_len; i++) { /* send other words */ data = rmh->cmd[i]; #ifdef CONFIG_SND_DEBUG_VERBOSE if (rmh->cmd_idx < CMD_LAST_INDEX) dev_dbg(&mgr->pci->dev, " cmd[%d]=%x\n", i, data); #endif err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF); PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF)); } } /* wait for chk bit */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg); if (err) return err; /* test status ISR */ if (reg & PCXHR_ISR_HI08_ERR) { /* ERROR, wait for receiver full */ err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg); if (err) { dev_err(&mgr->pci->dev, "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg); return err; } /* read error code */ data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16; data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8; data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); dev_err(&mgr->pci->dev, "ERROR RMH(%d): 0x%x\n", rmh->cmd_idx, data); err = -EINVAL; } else { /* read the response data */ err = pcxhr_read_rmh_status(mgr, rmh); } /* reset semaphore */ if (pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_SEMAPHORE, 1) < 0) return -EIO; return err; } /** * pcxhr_init_rmh - initialize the RMH instance * @rmh: the rmh pointer to be initialized * @cmd: the rmh command to be set */ void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd) { if (snd_BUG_ON(cmd >= CMD_LAST_INDEX)) return; rmh->cmd[0] = pcxhr_dsp_cmds[cmd].opcode; rmh->cmd_len = 1; rmh->stat_len = pcxhr_dsp_cmds[cmd].st_length; rmh->dsp_stat = pcxhr_dsp_cmds[cmd].st_type; rmh->cmd_idx = cmd; } void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh *rmh, int capture, unsigned int param1, unsigned int param2, unsigned int param3) { snd_BUG_ON(param1 > MASK_FIRST_FIELD); if (capture) rmh->cmd[0] |= 0x800; /* COMMAND_RECORD_MASK */ if (param1) rmh->cmd[0] |= (param1 << FIELD_SIZE); if (param2) { snd_BUG_ON(param2 > MASK_FIRST_FIELD); rmh->cmd[0] |= param2; } if(param3) { snd_BUG_ON(param3 > MASK_DSP_WORD); rmh->cmd[1] = param3; rmh->cmd_len = 2; } } /* * pcxhr_send_msg - send a DSP message with spinlock * @rmh: the rmh record to send and receive * * returns 0 if successful, or a negative error code. */ int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) { int err; mutex_lock(&mgr->msg_lock); err = pcxhr_send_msg_nolock(mgr, rmh); mutex_unlock(&mgr->msg_lock); return err; } static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr) { int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2); /* least segnificant 12 bits are the pipe states * for the playback audios * next 12 bits are the pipe states for the capture audios * (PCXHR_PIPE_STATE_CAPTURE_OFFSET) */ start_mask &= 0xffffff; dev_dbg(&mgr->pci->dev, "CMD_PIPE_STATE MBOX2=0x%06x\n", start_mask); return start_mask; } #define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12 #define MAX_WAIT_FOR_DSP 20 static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *retry) { struct pcxhr_rmh rmh; int err; int audio = 0; *retry = 0; while (audio_mask) { if (audio_mask & 1) { pcxhr_init_rmh(&rmh, CMD_CAN_START_PIPE); if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) { /* can start playback pipe */ pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0); } else { /* can start capture pipe */ pcxhr_set_pipe_cmd_params(&rmh, 1, audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET, 0, 0); } err = pcxhr_send_msg(mgr, &rmh); if (err) { dev_err(&mgr->pci->dev, "error pipe start " "(CMD_CAN_START_PIPE) err=%x!\n", err); return err; } /* if the pipe couldn't be prepaired for start, * retry it later */ if (rmh.stat[0] == 0) *retry |= (1<<audio); } audio_mask>>=1; audio++; } return 0; } static int pcxhr_stop_pipes(struct pcxhr_mgr *mgr, int audio_mask) { struct pcxhr_rmh rmh; int err; int audio = 0; while (audio_mask) { if (audio_mask & 1) { pcxhr_init_rmh(&rmh, CMD_STOP_PIPE); if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) { /* stop playback pipe */ pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0); } else { /* stop capture pipe */ pcxhr_set_pipe_cmd_params(&rmh, 1, audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET, 0, 0); } err = pcxhr_send_msg(mgr, &rmh); if (err) { dev_err(&mgr->pci->dev, "error pipe stop " "(CMD_STOP_PIPE) err=%x!\n", err); return err; } } audio_mask>>=1; audio++; } return 0; } static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask) { struct pcxhr_rmh rmh; int err; int audio = 0; while (audio_mask) { if (audio_mask & 1) { pcxhr_init_rmh(&rmh, CMD_CONF_PIPE); if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, 1 << audio); else pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0, 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET)); err = pcxhr_send_msg(mgr, &rmh); if (err) { dev_err(&mgr->pci->dev, "error pipe start " "(CMD_CONF_PIPE) err=%x!\n", err); return err; } } audio_mask>>=1; audio++; } /* now fire the interrupt on the card */ pcxhr_init_rmh(&rmh, CMD_SEND_IRQA); err = pcxhr_send_msg(mgr, &rmh); if (err) { dev_err(&mgr->pci->dev, "error pipe start (CMD_SEND_IRQA) err=%x!\n", err); return err; } return 0; } int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start) { int state, i, err; int audio_mask; #ifdef CONFIG_SND_DEBUG_VERBOSE ktime_t start_time, stop_time, diff_time; start_time = ktime_get(); #endif audio_mask = (playback_mask | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET)); /* current pipe state (playback + record) */ state = pcxhr_pipes_running(mgr); dev_dbg(&mgr->pci->dev, "pcxhr_set_pipe_state %s (mask %x current %x)\n", start ? "START" : "STOP", audio_mask, state); if (start) { /* start only pipes that are not yet started */ audio_mask &= ~state; state = audio_mask; for (i = 0; i < MAX_WAIT_FOR_DSP; i++) { err = pcxhr_prepair_pipe_start(mgr, state, &state); if (err) return err; if (state == 0) break; /* success, all pipes prepaired */ mdelay(1); /* wait 1 millisecond and retry */ } } else { audio_mask &= state; /* stop only pipes that are started */ } if (audio_mask == 0) return 0; err = pcxhr_toggle_pipes(mgr, audio_mask); if (err) return err; i = 0; while (1) { state = pcxhr_pipes_running(mgr); /* have all pipes the new state ? */ if ((state & audio_mask) == (start ? audio_mask : 0)) break; if (++i >= MAX_WAIT_FOR_DSP * 100) { dev_err(&mgr->pci->dev, "error pipe start/stop\n"); return -EBUSY; } udelay(10); /* wait 10 microseconds */ } if (!start) { err = pcxhr_stop_pipes(mgr, audio_mask); if (err) return err; } #ifdef CONFIG_SND_DEBUG_VERBOSE stop_time = ktime_get(); diff_time = ktime_sub(stop_time, start_time); dev_dbg(&mgr->pci->dev, "***SET PIPE STATE*** TIME = %ld (err = %x)\n", (long)(ktime_to_ns(diff_time)), err); #endif return 0; } int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask, unsigned int value, int *changed) { struct pcxhr_rmh rmh; int err; mutex_lock(&mgr->msg_lock); if ((mgr->io_num_reg_cont & mask) == value) { dev_dbg(&mgr->pci->dev, "IO_NUM_REG_CONT mask %x already is set to %x\n", mask, value); if (changed) *changed = 0; mutex_unlock(&mgr->msg_lock); return 0; /* already programmed */ } pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd[0] |= IO_NUM_REG_CONT; rmh.cmd[1] = mask; rmh.cmd[2] = value; rmh.cmd_len = 3; err = pcxhr_send_msg_nolock(mgr, &rmh); if (err == 0) { mgr->io_num_reg_cont &= ~mask; mgr->io_num_reg_cont |= value; if (changed) *changed = 1; } mutex_unlock(&mgr->msg_lock); return err; } #define PCXHR_IRQ_TIMER 0x000300 #define PCXHR_IRQ_FREQ_CHANGE 0x000800 #define PCXHR_IRQ_TIME_CODE 0x001000 #define PCXHR_IRQ_NOTIFY 0x002000 #define PCXHR_IRQ_ASYNC 0x008000 #define PCXHR_IRQ_MASK 0x00bb00 #define PCXHR_FATAL_DSP_ERR 0xff0000 enum pcxhr_async_err_src { PCXHR_ERR_PIPE, PCXHR_ERR_STREAM, PCXHR_ERR_AUDIO }; static int pcxhr_handle_async_err(struct pcxhr_mgr *mgr, u32 err, enum pcxhr_async_err_src err_src, int pipe, int is_capture) { static const char * const err_src_name[] = { [PCXHR_ERR_PIPE] = "Pipe", [PCXHR_ERR_STREAM] = "Stream", [PCXHR_ERR_AUDIO] = "Audio" }; if (err & 0xfff) err &= 0xfff; else err = ((err >> 12) & 0xfff); if (!err) return 0; dev_dbg(&mgr->pci->dev, "CMD_ASYNC : Error %s %s Pipe %d err=%x\n", err_src_name[err_src], is_capture ? "Record" : "Play", pipe, err); if (err == 0xe01) mgr->async_err_stream_xrun++; else if (err == 0xe10) mgr->async_err_pipe_xrun++; else mgr->async_err_other_last = (int)err; return 1; } static void pcxhr_msg_thread(struct pcxhr_mgr *mgr) { struct pcxhr_rmh *prmh = mgr->prmh; int err; int i, j; if (mgr->src_it_dsp & PCXHR_IRQ_FREQ_CHANGE) dev_dbg(&mgr->pci->dev, "PCXHR_IRQ_FREQ_CHANGE event occurred\n"); if (mgr->src_it_dsp & PCXHR_IRQ_TIME_CODE) dev_dbg(&mgr->pci->dev, "PCXHR_IRQ_TIME_CODE event occurred\n"); if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY) dev_dbg(&mgr->pci->dev, "PCXHR_IRQ_NOTIFY event occurred\n"); if (mgr->src_it_dsp & (PCXHR_IRQ_FREQ_CHANGE | PCXHR_IRQ_TIME_CODE)) { /* clear events FREQ_CHANGE and TIME_CODE */ pcxhr_init_rmh(prmh, CMD_TEST_IT); err = pcxhr_send_msg(mgr, prmh); dev_dbg(&mgr->pci->dev, "CMD_TEST_IT : err=%x, stat=%x\n", err, prmh->stat[0]); } if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) { dev_dbg(&mgr->pci->dev, "PCXHR_IRQ_ASYNC event occurred\n"); pcxhr_init_rmh(prmh, CMD_ASYNC); prmh->cmd[0] |= 1; /* add SEL_ASYNC_EVENTS */ /* this is the only one extra long response command */ prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS; err = pcxhr_send_msg(mgr, prmh); if (err) dev_err(&mgr->pci->dev, "ERROR pcxhr_msg_thread=%x;\n", err); i = 1; while (i < prmh->stat_len) { int nb_audio = ((prmh->stat[i] >> FIELD_SIZE) & MASK_FIRST_FIELD); int nb_stream = ((prmh->stat[i] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD); int pipe = prmh->stat[i] & MASK_FIRST_FIELD; int is_capture = prmh->stat[i] & 0x400000; u32 err2; if (prmh->stat[i] & 0x800000) { /* if BIT_END */ dev_dbg(&mgr->pci->dev, "TASKLET : End%sPipe %d\n", is_capture ? "Record" : "Play", pipe); } i++; err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; if (err2) pcxhr_handle_async_err(mgr, err2, PCXHR_ERR_PIPE, pipe, is_capture); i += 2; for (j = 0; j < nb_stream; j++) { err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; if (err2) pcxhr_handle_async_err(mgr, err2, PCXHR_ERR_STREAM, pipe, is_capture); i += 2; } for (j = 0; j < nb_audio; j++) { err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; if (err2) pcxhr_handle_async_err(mgr, err2, PCXHR_ERR_AUDIO, pipe, is_capture); i += 2; } } } } static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr, struct pcxhr_stream *stream) { u_int64_t hw_sample_count; struct pcxhr_rmh rmh; int err, stream_mask; stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number; /* get sample count for one stream */ pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT); pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, stream->pipe->first_audio, 0, stream_mask); /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */ err = pcxhr_send_msg(mgr, &rmh); if (err) return 0; hw_sample_count = ((u_int64_t)rmh.stat[0]) << 24; hw_sample_count += (u_int64_t)rmh.stat[1]; dev_dbg(&mgr->pci->dev, "stream %c%d : abs samples real(%llu) timer(%llu)\n", stream->pipe->is_capture ? 'C' : 'P', stream->substream->number, hw_sample_count, stream->timer_abs_periods + stream->timer_period_frag + mgr->granularity); return hw_sample_count; } static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, struct pcxhr_stream *stream, int samples_to_add) { if (stream->substream && (stream->status == PCXHR_STREAM_STATUS_RUNNING)) { u_int64_t new_sample_count; int elapsed = 0; int hardware_read = 0; struct snd_pcm_runtime *runtime = stream->substream->runtime; if (samples_to_add < 0) { stream->timer_is_synced = 0; /* add default if no hardware_read possible */ samples_to_add = mgr->granularity; } if (!stream->timer_is_synced) { if ((stream->timer_abs_periods != 0) || ((stream->timer_period_frag + samples_to_add) >= runtime->period_size)) { new_sample_count = pcxhr_stream_read_position(mgr, stream); hardware_read = 1; if (new_sample_count >= mgr->granularity) { /* sub security offset because of * jitter and finer granularity of * dsp time (MBOX4) */ new_sample_count -= mgr->granularity; stream->timer_is_synced = 1; } } } if (!hardware_read) { /* if we didn't try to sync the position, increment it * by PCXHR_GRANULARITY every timer interrupt */ new_sample_count = stream->timer_abs_periods + stream->timer_period_frag + samples_to_add; } while (1) { u_int64_t new_elapse_pos = stream->timer_abs_periods + runtime->period_size; if (new_elapse_pos > new_sample_count) break; elapsed = 1; stream->timer_buf_periods++; if (stream->timer_buf_periods >= runtime->periods) stream->timer_buf_periods = 0; stream->timer_abs_periods = new_elapse_pos; } if (new_sample_count >= stream->timer_abs_periods) { stream->timer_period_frag = (u_int32_t)(new_sample_count - stream->timer_abs_periods); } else { dev_err(&mgr->pci->dev, "ERROR new_sample_count too small ??? %ld\n", (long unsigned int)new_sample_count); } if (elapsed) { mutex_unlock(&mgr->lock); snd_pcm_period_elapsed(stream->substream); mutex_lock(&mgr->lock); } } } irqreturn_t pcxhr_interrupt(int irq, void *dev_id) { struct pcxhr_mgr *mgr = dev_id; unsigned int reg; bool wake_thread = false; reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) { /* this device did not cause the interrupt */ return IRQ_NONE; } /* clear interrupt */ reg = PCXHR_INPL(mgr, PCXHR_PLX_L2PCIDB); PCXHR_OUTPL(mgr, PCXHR_PLX_L2PCIDB, reg); /* timer irq occurred */ if (reg & PCXHR_IRQ_TIMER) { int timer_toggle = reg & PCXHR_IRQ_TIMER; if (timer_toggle == mgr->timer_toggle) { dev_dbg(&mgr->pci->dev, "ERROR TIMER TOGGLE\n"); mgr->dsp_time_err++; } mgr->timer_toggle = timer_toggle; mgr->src_it_dsp = reg; wake_thread = true; } /* other irq's handled in the thread */ if (reg & PCXHR_IRQ_MASK) { if (reg & PCXHR_IRQ_ASYNC) { /* as we didn't request any async notifications, * some kind of xrun error will probably occurred */ /* better resynchronize all streams next interrupt : */ mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; } mgr->src_it_dsp = reg; wake_thread = true; } #ifdef CONFIG_SND_DEBUG_VERBOSE if (reg & PCXHR_FATAL_DSP_ERR) dev_dbg(&mgr->pci->dev, "FATAL DSP ERROR : %x\n", reg); #endif return wake_thread ? IRQ_WAKE_THREAD : IRQ_HANDLED; } irqreturn_t pcxhr_threaded_irq(int irq, void *dev_id) { struct pcxhr_mgr *mgr = dev_id; int i, j; struct snd_pcxhr *chip; mutex_lock(&mgr->lock); if (mgr->src_it_dsp & PCXHR_IRQ_TIMER) { /* is a 24 bit counter */ int dsp_time_new = PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK; int dsp_time_diff = dsp_time_new - mgr->dsp_time_last; if ((dsp_time_diff < 0) && (mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID)) { /* handle dsp counter wraparound without resync */ int tmp_diff = dsp_time_diff + PCXHR_DSP_TIME_MASK + 1; dev_dbg(&mgr->pci->dev, "WARNING DSP timestamp old(%d) new(%d)", mgr->dsp_time_last, dsp_time_new); if (tmp_diff > 0 && tmp_diff <= (2*mgr->granularity)) { dev_dbg(&mgr->pci->dev, "-> timestamp wraparound OK: " "diff=%d\n", tmp_diff); dsp_time_diff = tmp_diff; } else { dev_dbg(&mgr->pci->dev, "-> resynchronize all streams\n"); mgr->dsp_time_err++; } } #ifdef CONFIG_SND_DEBUG_VERBOSE if (dsp_time_diff == 0) dev_dbg(&mgr->pci->dev, "ERROR DSP TIME NO DIFF time(%d)\n", dsp_time_new); else if (dsp_time_diff >= (2*mgr->granularity)) dev_dbg(&mgr->pci->dev, "ERROR DSP TIME TOO BIG old(%d) add(%d)\n", mgr->dsp_time_last, dsp_time_new - mgr->dsp_time_last); else if (dsp_time_diff % mgr->granularity) dev_dbg(&mgr->pci->dev, "ERROR DSP TIME increased by %d\n", dsp_time_diff); #endif mgr->dsp_time_last = dsp_time_new; for (i = 0; i < mgr->num_cards; i++) { chip = mgr->chip[i]; for (j = 0; j < chip->nb_streams_capt; j++) pcxhr_update_timer_pos(mgr, &chip->capture_stream[j], dsp_time_diff); } for (i = 0; i < mgr->num_cards; i++) { chip = mgr->chip[i]; for (j = 0; j < chip->nb_streams_play; j++) pcxhr_update_timer_pos(mgr, &chip->playback_stream[j], dsp_time_diff); } } pcxhr_msg_thread(mgr); mutex_unlock(&mgr->lock); return IRQ_HANDLED; }
linux-master
sound/pci/pcxhr/pcxhr_core.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram pcxhr compatible soundcards * * mixer interface for stereo cards * * Copyright (c) 2004 by Digigram <[email protected]> */ #include <linux/delay.h> #include <linux/io.h> #include <linux/pci.h> #include <sound/core.h> #include <sound/control.h> #include <sound/tlv.h> #include <sound/asoundef.h> #include "pcxhr.h" #include "pcxhr_core.h" #include "pcxhr_mix22.h" /* registers used on the DSP and Xilinx (port 2) : HR stereo cards only */ #define PCXHR_DSP_RESET 0x20 #define PCXHR_XLX_CFG 0x24 #define PCXHR_XLX_RUER 0x28 #define PCXHR_XLX_DATA 0x2C #define PCXHR_XLX_STATUS 0x30 #define PCXHR_XLX_LOFREQ 0x34 #define PCXHR_XLX_HIFREQ 0x38 #define PCXHR_XLX_CSUER 0x3C #define PCXHR_XLX_SELMIC 0x40 #define PCXHR_DSP 2 /* byte access only ! */ #define PCXHR_INPB(mgr, x) inb((mgr)->port[PCXHR_DSP] + (x)) #define PCXHR_OUTPB(mgr, x, data) outb((data), (mgr)->port[PCXHR_DSP] + (x)) /* values for PCHR_DSP_RESET register */ #define PCXHR_DSP_RESET_DSP 0x01 #define PCXHR_DSP_RESET_MUTE 0x02 #define PCXHR_DSP_RESET_CODEC 0x08 #define PCXHR_DSP_RESET_SMPTE 0x10 #define PCXHR_DSP_RESET_GPO_OFFSET 5 #define PCXHR_DSP_RESET_GPO_MASK 0x60 /* values for PCHR_XLX_CFG register */ #define PCXHR_CFG_SYNCDSP_MASK 0x80 #define PCXHR_CFG_DEPENDENCY_MASK 0x60 #define PCXHR_CFG_INDEPENDANT_SEL 0x00 #define PCXHR_CFG_MASTER_SEL 0x40 #define PCXHR_CFG_SLAVE_SEL 0x20 #define PCXHR_CFG_DATA_UER1_SEL_MASK 0x10 /* 0 (UER0), 1(UER1) */ #define PCXHR_CFG_DATAIN_SEL_MASK 0x08 /* 0 (ana), 1 (UER) */ #define PCXHR_CFG_SRC_MASK 0x04 /* 0 (Bypass), 1 (SRC Actif) */ #define PCXHR_CFG_CLOCK_UER1_SEL_MASK 0x02 /* 0 (UER0), 1(UER1) */ #define PCXHR_CFG_CLOCKIN_SEL_MASK 0x01 /* 0 (internal), 1 (AES/EBU) */ /* values for PCHR_XLX_DATA register */ #define PCXHR_DATA_CODEC 0x80 #define AKM_POWER_CONTROL_CMD 0xA007 #define AKM_RESET_ON_CMD 0xA100 #define AKM_RESET_OFF_CMD 0xA103 #define AKM_CLOCK_INF_55K_CMD 0xA240 #define AKM_CLOCK_SUP_55K_CMD 0xA24D #define AKM_MUTE_CMD 0xA38D #define AKM_UNMUTE_CMD 0xA30D #define AKM_LEFT_LEVEL_CMD 0xA600 #define AKM_RIGHT_LEVEL_CMD 0xA700 /* values for PCHR_XLX_STATUS register - READ */ #define PCXHR_STAT_SRC_LOCK 0x01 #define PCXHR_STAT_LEVEL_IN 0x02 #define PCXHR_STAT_GPI_OFFSET 2 #define PCXHR_STAT_GPI_MASK 0x0C #define PCXHR_STAT_MIC_CAPS 0x10 /* values for PCHR_XLX_STATUS register - WRITE */ #define PCXHR_STAT_FREQ_SYNC_MASK 0x01 #define PCXHR_STAT_FREQ_UER1_MASK 0x02 #define PCXHR_STAT_FREQ_SAVE_MASK 0x80 /* values for PCHR_XLX_CSUER register */ #define PCXHR_SUER1_BIT_U_READ_MASK 0x80 #define PCXHR_SUER1_BIT_C_READ_MASK 0x40 #define PCXHR_SUER1_DATA_PRESENT_MASK 0x20 #define PCXHR_SUER1_CLOCK_PRESENT_MASK 0x10 #define PCXHR_SUER_BIT_U_READ_MASK 0x08 #define PCXHR_SUER_BIT_C_READ_MASK 0x04 #define PCXHR_SUER_DATA_PRESENT_MASK 0x02 #define PCXHR_SUER_CLOCK_PRESENT_MASK 0x01 #define PCXHR_SUER_BIT_U_WRITE_MASK 0x02 #define PCXHR_SUER_BIT_C_WRITE_MASK 0x01 /* values for PCXHR_XLX_SELMIC register - WRITE */ #define PCXHR_SELMIC_PREAMPLI_OFFSET 2 #define PCXHR_SELMIC_PREAMPLI_MASK 0x0C #define PCXHR_SELMIC_PHANTOM_ALIM 0x80 static const unsigned char g_hr222_p_level[] = { 0x00, /* [000] -49.5 dB: AKM[000] = -1.#INF dB (mute) */ 0x01, /* [001] -49.0 dB: AKM[001] = -48.131 dB (diff=0.86920 dB) */ 0x01, /* [002] -48.5 dB: AKM[001] = -48.131 dB (diff=0.36920 dB) */ 0x01, /* [003] -48.0 dB: AKM[001] = -48.131 dB (diff=0.13080 dB) */ 0x01, /* [004] -47.5 dB: AKM[001] = -48.131 dB (diff=0.63080 dB) */ 0x01, /* [005] -46.5 dB: AKM[001] = -48.131 dB (diff=1.63080 dB) */ 0x01, /* [006] -47.0 dB: AKM[001] = -48.131 dB (diff=1.13080 dB) */ 0x01, /* [007] -46.0 dB: AKM[001] = -48.131 dB (diff=2.13080 dB) */ 0x01, /* [008] -45.5 dB: AKM[001] = -48.131 dB (diff=2.63080 dB) */ 0x02, /* [009] -45.0 dB: AKM[002] = -42.110 dB (diff=2.88980 dB) */ 0x02, /* [010] -44.5 dB: AKM[002] = -42.110 dB (diff=2.38980 dB) */ 0x02, /* [011] -44.0 dB: AKM[002] = -42.110 dB (diff=1.88980 dB) */ 0x02, /* [012] -43.5 dB: AKM[002] = -42.110 dB (diff=1.38980 dB) */ 0x02, /* [013] -43.0 dB: AKM[002] = -42.110 dB (diff=0.88980 dB) */ 0x02, /* [014] -42.5 dB: AKM[002] = -42.110 dB (diff=0.38980 dB) */ 0x02, /* [015] -42.0 dB: AKM[002] = -42.110 dB (diff=0.11020 dB) */ 0x02, /* [016] -41.5 dB: AKM[002] = -42.110 dB (diff=0.61020 dB) */ 0x02, /* [017] -41.0 dB: AKM[002] = -42.110 dB (diff=1.11020 dB) */ 0x02, /* [018] -40.5 dB: AKM[002] = -42.110 dB (diff=1.61020 dB) */ 0x03, /* [019] -40.0 dB: AKM[003] = -38.588 dB (diff=1.41162 dB) */ 0x03, /* [020] -39.5 dB: AKM[003] = -38.588 dB (diff=0.91162 dB) */ 0x03, /* [021] -39.0 dB: AKM[003] = -38.588 dB (diff=0.41162 dB) */ 0x03, /* [022] -38.5 dB: AKM[003] = -38.588 dB (diff=0.08838 dB) */ 0x03, /* [023] -38.0 dB: AKM[003] = -38.588 dB (diff=0.58838 dB) */ 0x03, /* [024] -37.5 dB: AKM[003] = -38.588 dB (diff=1.08838 dB) */ 0x04, /* [025] -37.0 dB: AKM[004] = -36.090 dB (diff=0.91040 dB) */ 0x04, /* [026] -36.5 dB: AKM[004] = -36.090 dB (diff=0.41040 dB) */ 0x04, /* [027] -36.0 dB: AKM[004] = -36.090 dB (diff=0.08960 dB) */ 0x04, /* [028] -35.5 dB: AKM[004] = -36.090 dB (diff=0.58960 dB) */ 0x05, /* [029] -35.0 dB: AKM[005] = -34.151 dB (diff=0.84860 dB) */ 0x05, /* [030] -34.5 dB: AKM[005] = -34.151 dB (diff=0.34860 dB) */ 0x05, /* [031] -34.0 dB: AKM[005] = -34.151 dB (diff=0.15140 dB) */ 0x05, /* [032] -33.5 dB: AKM[005] = -34.151 dB (diff=0.65140 dB) */ 0x06, /* [033] -33.0 dB: AKM[006] = -32.568 dB (diff=0.43222 dB) */ 0x06, /* [034] -32.5 dB: AKM[006] = -32.568 dB (diff=0.06778 dB) */ 0x06, /* [035] -32.0 dB: AKM[006] = -32.568 dB (diff=0.56778 dB) */ 0x07, /* [036] -31.5 dB: AKM[007] = -31.229 dB (diff=0.27116 dB) */ 0x07, /* [037] -31.0 dB: AKM[007] = -31.229 dB (diff=0.22884 dB) */ 0x08, /* [038] -30.5 dB: AKM[008] = -30.069 dB (diff=0.43100 dB) */ 0x08, /* [039] -30.0 dB: AKM[008] = -30.069 dB (diff=0.06900 dB) */ 0x09, /* [040] -29.5 dB: AKM[009] = -29.046 dB (diff=0.45405 dB) */ 0x09, /* [041] -29.0 dB: AKM[009] = -29.046 dB (diff=0.04595 dB) */ 0x0a, /* [042] -28.5 dB: AKM[010] = -28.131 dB (diff=0.36920 dB) */ 0x0a, /* [043] -28.0 dB: AKM[010] = -28.131 dB (diff=0.13080 dB) */ 0x0b, /* [044] -27.5 dB: AKM[011] = -27.303 dB (diff=0.19705 dB) */ 0x0b, /* [045] -27.0 dB: AKM[011] = -27.303 dB (diff=0.30295 dB) */ 0x0c, /* [046] -26.5 dB: AKM[012] = -26.547 dB (diff=0.04718 dB) */ 0x0d, /* [047] -26.0 dB: AKM[013] = -25.852 dB (diff=0.14806 dB) */ 0x0e, /* [048] -25.5 dB: AKM[014] = -25.208 dB (diff=0.29176 dB) */ 0x0e, /* [049] -25.0 dB: AKM[014] = -25.208 dB (diff=0.20824 dB) */ 0x0f, /* [050] -24.5 dB: AKM[015] = -24.609 dB (diff=0.10898 dB) */ 0x10, /* [051] -24.0 dB: AKM[016] = -24.048 dB (diff=0.04840 dB) */ 0x11, /* [052] -23.5 dB: AKM[017] = -23.522 dB (diff=0.02183 dB) */ 0x12, /* [053] -23.0 dB: AKM[018] = -23.025 dB (diff=0.02535 dB) */ 0x13, /* [054] -22.5 dB: AKM[019] = -22.556 dB (diff=0.05573 dB) */ 0x14, /* [055] -22.0 dB: AKM[020] = -22.110 dB (diff=0.11020 dB) */ 0x15, /* [056] -21.5 dB: AKM[021] = -21.686 dB (diff=0.18642 dB) */ 0x17, /* [057] -21.0 dB: AKM[023] = -20.896 dB (diff=0.10375 dB) */ 0x18, /* [058] -20.5 dB: AKM[024] = -20.527 dB (diff=0.02658 dB) */ 0x1a, /* [059] -20.0 dB: AKM[026] = -19.831 dB (diff=0.16866 dB) */ 0x1b, /* [060] -19.5 dB: AKM[027] = -19.504 dB (diff=0.00353 dB) */ 0x1d, /* [061] -19.0 dB: AKM[029] = -18.883 dB (diff=0.11716 dB) */ 0x1e, /* [062] -18.5 dB: AKM[030] = -18.588 dB (diff=0.08838 dB) */ 0x20, /* [063] -18.0 dB: AKM[032] = -18.028 dB (diff=0.02780 dB) */ 0x22, /* [064] -17.5 dB: AKM[034] = -17.501 dB (diff=0.00123 dB) */ 0x24, /* [065] -17.0 dB: AKM[036] = -17.005 dB (diff=0.00475 dB) */ 0x26, /* [066] -16.5 dB: AKM[038] = -16.535 dB (diff=0.03513 dB) */ 0x28, /* [067] -16.0 dB: AKM[040] = -16.090 dB (diff=0.08960 dB) */ 0x2b, /* [068] -15.5 dB: AKM[043] = -15.461 dB (diff=0.03857 dB) */ 0x2d, /* [069] -15.0 dB: AKM[045] = -15.067 dB (diff=0.06655 dB) */ 0x30, /* [070] -14.5 dB: AKM[048] = -14.506 dB (diff=0.00598 dB) */ 0x33, /* [071] -14.0 dB: AKM[051] = -13.979 dB (diff=0.02060 dB) */ 0x36, /* [072] -13.5 dB: AKM[054] = -13.483 dB (diff=0.01707 dB) */ 0x39, /* [073] -13.0 dB: AKM[057] = -13.013 dB (diff=0.01331 dB) */ 0x3c, /* [074] -12.5 dB: AKM[060] = -12.568 dB (diff=0.06778 dB) */ 0x40, /* [075] -12.0 dB: AKM[064] = -12.007 dB (diff=0.00720 dB) */ 0x44, /* [076] -11.5 dB: AKM[068] = -11.481 dB (diff=0.01937 dB) */ 0x48, /* [077] -11.0 dB: AKM[072] = -10.984 dB (diff=0.01585 dB) */ 0x4c, /* [078] -10.5 dB: AKM[076] = -10.515 dB (diff=0.01453 dB) */ 0x51, /* [079] -10.0 dB: AKM[081] = -9.961 dB (diff=0.03890 dB) */ 0x55, /* [080] -9.5 dB: AKM[085] = -9.542 dB (diff=0.04243 dB) */ 0x5a, /* [081] -9.0 dB: AKM[090] = -9.046 dB (diff=0.04595 dB) */ 0x60, /* [082] -8.5 dB: AKM[096] = -8.485 dB (diff=0.01462 dB) */ 0x66, /* [083] -8.0 dB: AKM[102] = -7.959 dB (diff=0.04120 dB) */ 0x6c, /* [084] -7.5 dB: AKM[108] = -7.462 dB (diff=0.03767 dB) */ 0x72, /* [085] -7.0 dB: AKM[114] = -6.993 dB (diff=0.00729 dB) */ 0x79, /* [086] -6.5 dB: AKM[121] = -6.475 dB (diff=0.02490 dB) */ 0x80, /* [087] -6.0 dB: AKM[128] = -5.987 dB (diff=0.01340 dB) */ 0x87, /* [088] -5.5 dB: AKM[135] = -5.524 dB (diff=0.02413 dB) */ 0x8f, /* [089] -5.0 dB: AKM[143] = -5.024 dB (diff=0.02408 dB) */ 0x98, /* [090] -4.5 dB: AKM[152] = -4.494 dB (diff=0.00607 dB) */ 0xa1, /* [091] -4.0 dB: AKM[161] = -3.994 dB (diff=0.00571 dB) */ 0xaa, /* [092] -3.5 dB: AKM[170] = -3.522 dB (diff=0.02183 dB) */ 0xb5, /* [093] -3.0 dB: AKM[181] = -2.977 dB (diff=0.02277 dB) */ 0xbf, /* [094] -2.5 dB: AKM[191] = -2.510 dB (diff=0.01014 dB) */ 0xcb, /* [095] -2.0 dB: AKM[203] = -1.981 dB (diff=0.01912 dB) */ 0xd7, /* [096] -1.5 dB: AKM[215] = -1.482 dB (diff=0.01797 dB) */ 0xe3, /* [097] -1.0 dB: AKM[227] = -1.010 dB (diff=0.01029 dB) */ 0xf1, /* [098] -0.5 dB: AKM[241] = -0.490 dB (diff=0.00954 dB) */ 0xff, /* [099] +0.0 dB: AKM[255] = +0.000 dB (diff=0.00000 dB) */ }; static void hr222_config_akm(struct pcxhr_mgr *mgr, unsigned short data) { unsigned short mask = 0x8000; /* activate access to codec registers */ PCXHR_INPB(mgr, PCXHR_XLX_HIFREQ); while (mask) { PCXHR_OUTPB(mgr, PCXHR_XLX_DATA, data & mask ? PCXHR_DATA_CODEC : 0); mask >>= 1; } /* termiate access to codec registers */ PCXHR_INPB(mgr, PCXHR_XLX_RUER); } static int hr222_set_hw_playback_level(struct pcxhr_mgr *mgr, int idx, int level) { unsigned short cmd; if (idx > 1 || level < 0 || level >= ARRAY_SIZE(g_hr222_p_level)) return -EINVAL; if (idx == 0) cmd = AKM_LEFT_LEVEL_CMD; else cmd = AKM_RIGHT_LEVEL_CMD; /* conversion from PmBoardCodedLevel to AKM nonlinear programming */ cmd += g_hr222_p_level[level]; hr222_config_akm(mgr, cmd); return 0; } static int hr222_set_hw_capture_level(struct pcxhr_mgr *mgr, int level_l, int level_r, int level_mic) { /* program all input levels at the same time */ unsigned int data; int i; if (!mgr->capture_chips) return -EINVAL; /* no PCX22 */ data = ((level_mic & 0xff) << 24); /* micro is mono, but apply */ data |= ((level_mic & 0xff) << 16); /* level on both channels */ data |= ((level_r & 0xff) << 8); /* line input right channel */ data |= (level_l & 0xff); /* line input left channel */ PCXHR_INPB(mgr, PCXHR_XLX_DATA); /* activate input codec */ /* send 32 bits (4 x 8 bits) */ for (i = 0; i < 32; i++, data <<= 1) { PCXHR_OUTPB(mgr, PCXHR_XLX_DATA, (data & 0x80000000) ? PCXHR_DATA_CODEC : 0); } PCXHR_INPB(mgr, PCXHR_XLX_RUER); /* close input level codec */ return 0; } static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level); int hr222_sub_init(struct pcxhr_mgr *mgr) { unsigned char reg; mgr->board_has_analog = 1; /* analog always available */ mgr->xlx_cfg = PCXHR_CFG_SYNCDSP_MASK; reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS); if (reg & PCXHR_STAT_MIC_CAPS) mgr->board_has_mic = 1; /* microphone available */ dev_dbg(&mgr->pci->dev, "MIC input available = %d\n", mgr->board_has_mic); /* reset codec */ PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, PCXHR_DSP_RESET_DSP); msleep(5); mgr->dsp_reset = PCXHR_DSP_RESET_DSP | PCXHR_DSP_RESET_MUTE | PCXHR_DSP_RESET_CODEC; PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset); /* hr222_write_gpo(mgr, 0); does the same */ msleep(5); /* config AKM */ hr222_config_akm(mgr, AKM_POWER_CONTROL_CMD); hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD); hr222_config_akm(mgr, AKM_UNMUTE_CMD); hr222_config_akm(mgr, AKM_RESET_OFF_CMD); /* init micro boost */ hr222_micro_boost(mgr, 0); return 0; } /* calc PLL register */ /* TODO : there is a very similar fct in pcxhr.c */ static int hr222_pll_freq_register(unsigned int freq, unsigned int *pllreg, unsigned int *realfreq) { unsigned int reg; if (freq < 6900 || freq > 219000) return -EINVAL; reg = (28224000 * 2) / freq; reg = (reg - 1) / 2; if (reg < 0x100) *pllreg = reg + 0xC00; else if (reg < 0x200) *pllreg = reg + 0x800; else if (reg < 0x400) *pllreg = reg & 0x1ff; else if (reg < 0x800) { *pllreg = ((reg >> 1) & 0x1ff) + 0x200; reg &= ~1; } else { *pllreg = ((reg >> 2) & 0x1ff) + 0x400; reg &= ~3; } if (realfreq) *realfreq = (28224000 / (reg + 1)); return 0; } int hr222_sub_set_clock(struct pcxhr_mgr *mgr, unsigned int rate, int *changed) { unsigned int speed, pllreg = 0; int err; unsigned realfreq = rate; switch (mgr->use_clock_type) { case HR22_CLOCK_TYPE_INTERNAL: err = hr222_pll_freq_register(rate, &pllreg, &realfreq); if (err) return err; mgr->xlx_cfg &= ~(PCXHR_CFG_CLOCKIN_SEL_MASK | PCXHR_CFG_CLOCK_UER1_SEL_MASK); break; case HR22_CLOCK_TYPE_AES_SYNC: mgr->xlx_cfg |= PCXHR_CFG_CLOCKIN_SEL_MASK; mgr->xlx_cfg &= ~PCXHR_CFG_CLOCK_UER1_SEL_MASK; break; case HR22_CLOCK_TYPE_AES_1: if (!mgr->board_has_aes1) return -EINVAL; mgr->xlx_cfg |= (PCXHR_CFG_CLOCKIN_SEL_MASK | PCXHR_CFG_CLOCK_UER1_SEL_MASK); break; default: return -EINVAL; } hr222_config_akm(mgr, AKM_MUTE_CMD); if (mgr->use_clock_type == HR22_CLOCK_TYPE_INTERNAL) { PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8); PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff); } /* set clock source */ PCXHR_OUTPB(mgr, PCXHR_XLX_CFG, mgr->xlx_cfg); /* codec speed modes */ speed = rate < 55000 ? 0 : 1; if (mgr->codec_speed != speed) { mgr->codec_speed = speed; if (speed == 0) hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD); else hr222_config_akm(mgr, AKM_CLOCK_SUP_55K_CMD); } mgr->sample_rate_real = realfreq; mgr->cur_clock_type = mgr->use_clock_type; if (changed) *changed = 1; hr222_config_akm(mgr, AKM_UNMUTE_CMD); dev_dbg(&mgr->pci->dev, "set_clock to %dHz (realfreq=%d pllreg=%x)\n", rate, realfreq, pllreg); return 0; } int hr222_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) { int rate, calc_rate = 0; unsigned int ticks; unsigned char mask, reg; if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) { mask = (PCXHR_SUER_CLOCK_PRESENT_MASK | PCXHR_SUER_DATA_PRESENT_MASK); reg = PCXHR_STAT_FREQ_SYNC_MASK; } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) { mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK | PCXHR_SUER1_DATA_PRESENT_MASK); reg = PCXHR_STAT_FREQ_UER1_MASK; } else { dev_dbg(&mgr->pci->dev, "get_external_clock : type %d not supported\n", clock_type); return -EINVAL; /* other clocks not supported */ } if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) { dev_dbg(&mgr->pci->dev, "get_external_clock(%d) = 0 Hz\n", clock_type); *sample_rate = 0; return 0; /* no external clock locked */ } PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */ /* save the measured clock frequency */ reg |= PCXHR_STAT_FREQ_SAVE_MASK; if (mgr->last_reg_stat != reg) { udelay(500); /* wait min 2 cycles of lowest freq (8000) */ mgr->last_reg_stat = reg; } PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */ /* get the frequency */ ticks = (unsigned int)PCXHR_INPB(mgr, PCXHR_XLX_CFG); ticks = (ticks & 0x03) << 8; ticks |= (unsigned int)PCXHR_INPB(mgr, PCXHR_DSP_RESET); if (ticks != 0) calc_rate = 28224000 / ticks; /* rounding */ if (calc_rate > 184200) rate = 192000; else if (calc_rate > 152200) rate = 176400; else if (calc_rate > 112000) rate = 128000; else if (calc_rate > 92100) rate = 96000; else if (calc_rate > 76100) rate = 88200; else if (calc_rate > 56000) rate = 64000; else if (calc_rate > 46050) rate = 48000; else if (calc_rate > 38050) rate = 44100; else if (calc_rate > 28000) rate = 32000; else if (calc_rate > 23025) rate = 24000; else if (calc_rate > 19025) rate = 22050; else if (calc_rate > 14000) rate = 16000; else if (calc_rate > 11512) rate = 12000; else if (calc_rate > 9512) rate = 11025; else if (calc_rate > 7000) rate = 8000; else rate = 0; dev_dbg(&mgr->pci->dev, "External clock is at %d Hz (measured %d Hz)\n", rate, calc_rate); *sample_rate = rate; return 0; } int hr222_read_gpio(struct pcxhr_mgr *mgr, int is_gpi, int *value) { if (is_gpi) { unsigned char reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS); *value = (int)(reg & PCXHR_STAT_GPI_MASK) >> PCXHR_STAT_GPI_OFFSET; } else { *value = (int)(mgr->dsp_reset & PCXHR_DSP_RESET_GPO_MASK) >> PCXHR_DSP_RESET_GPO_OFFSET; } return 0; } int hr222_write_gpo(struct pcxhr_mgr *mgr, int value) { unsigned char reg = mgr->dsp_reset & ~PCXHR_DSP_RESET_GPO_MASK; reg |= (unsigned char)(value << PCXHR_DSP_RESET_GPO_OFFSET) & PCXHR_DSP_RESET_GPO_MASK; PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, reg); mgr->dsp_reset = reg; return 0; } int hr222_manage_timecode(struct pcxhr_mgr *mgr, int enable) { if (enable) mgr->dsp_reset |= PCXHR_DSP_RESET_SMPTE; else mgr->dsp_reset &= ~PCXHR_DSP_RESET_SMPTE; PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset); return 0; } int hr222_update_analog_audio_level(struct snd_pcxhr *chip, int is_capture, int channel) { dev_dbg(chip->card->dev, "hr222_update_analog_audio_level(%s chan=%d)\n", is_capture ? "capture" : "playback", channel); if (is_capture) { int level_l, level_r, level_mic; /* we have to update all levels */ if (chip->analog_capture_active) { level_l = chip->analog_capture_volume[0]; level_r = chip->analog_capture_volume[1]; } else { level_l = HR222_LINE_CAPTURE_LEVEL_MIN; level_r = HR222_LINE_CAPTURE_LEVEL_MIN; } if (chip->mic_active) level_mic = chip->mic_volume; else level_mic = HR222_MICRO_CAPTURE_LEVEL_MIN; return hr222_set_hw_capture_level(chip->mgr, level_l, level_r, level_mic); } else { int vol; if (chip->analog_playback_active[channel]) vol = chip->analog_playback_volume[channel]; else vol = HR222_LINE_PLAYBACK_LEVEL_MIN; return hr222_set_hw_playback_level(chip->mgr, channel, vol); } } /*texts[5] = {"Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"}*/ #define SOURCE_LINE 0 #define SOURCE_DIGITAL 1 #define SOURCE_DIGISRC 2 #define SOURCE_MIC 3 #define SOURCE_LINEMIC 4 int hr222_set_audio_source(struct snd_pcxhr *chip) { int digital = 0; /* default analog source */ chip->mgr->xlx_cfg &= ~(PCXHR_CFG_SRC_MASK | PCXHR_CFG_DATAIN_SEL_MASK | PCXHR_CFG_DATA_UER1_SEL_MASK); if (chip->audio_capture_source == SOURCE_DIGISRC) { chip->mgr->xlx_cfg |= PCXHR_CFG_SRC_MASK; digital = 1; } else { if (chip->audio_capture_source == SOURCE_DIGITAL) digital = 1; } if (digital) { chip->mgr->xlx_cfg |= PCXHR_CFG_DATAIN_SEL_MASK; if (chip->mgr->board_has_aes1) { /* get data from the AES1 plug */ chip->mgr->xlx_cfg |= PCXHR_CFG_DATA_UER1_SEL_MASK; } /* chip->mic_active = 0; */ /* chip->analog_capture_active = 0; */ } else { int update_lvl = 0; chip->analog_capture_active = 0; chip->mic_active = 0; if (chip->audio_capture_source == SOURCE_LINE || chip->audio_capture_source == SOURCE_LINEMIC) { if (chip->analog_capture_active == 0) update_lvl = 1; chip->analog_capture_active = 1; } if (chip->audio_capture_source == SOURCE_MIC || chip->audio_capture_source == SOURCE_LINEMIC) { if (chip->mic_active == 0) update_lvl = 1; chip->mic_active = 1; } if (update_lvl) { /* capture: update all 3 mutes/unmutes with one call */ hr222_update_analog_audio_level(chip, 1, 0); } } /* set the source infos (max 3 bits modified) */ PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CFG, chip->mgr->xlx_cfg); return 0; } int hr222_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char *aes_bits) { unsigned char idx = (unsigned char)(aes_idx * 8); unsigned char temp = 0; unsigned char mask = chip->mgr->board_has_aes1 ? PCXHR_SUER1_BIT_C_READ_MASK : PCXHR_SUER_BIT_C_READ_MASK; int i; for (i = 0; i < 8; i++) { PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx++); /* idx < 192 */ temp <<= 1; if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask) temp |= 1; } dev_dbg(chip->card->dev, "read iec958 AES %d byte %d = 0x%x\n", chip->chip_idx, aes_idx, temp); *aes_bits = temp; return 0; } int hr222_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char aes_bits) { int i; unsigned char new_bits = aes_bits; unsigned char old_bits = chip->aes_bits[aes_idx]; unsigned char idx = (unsigned char)(aes_idx * 8); for (i = 0; i < 8; i++) { if ((old_bits & 0x01) != (new_bits & 0x01)) { /* idx < 192 */ PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx); /* write C and U bit */ PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CSUER, new_bits&0x01 ? PCXHR_SUER_BIT_C_WRITE_MASK : 0); } idx++; old_bits >>= 1; new_bits >>= 1; } chip->aes_bits[aes_idx] = aes_bits; return 0; } static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level) { unsigned char boost_mask; boost_mask = (unsigned char) (level << PCXHR_SELMIC_PREAMPLI_OFFSET); if (boost_mask & (~PCXHR_SELMIC_PREAMPLI_MASK)) return; /* only values form 0 to 3 accepted */ mgr->xlx_selmic &= ~PCXHR_SELMIC_PREAMPLI_MASK; mgr->xlx_selmic |= boost_mask; PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic); dev_dbg(&mgr->pci->dev, "hr222_micro_boost : set %x\n", boost_mask); } static void hr222_phantom_power(struct pcxhr_mgr *mgr, int power) { if (power) mgr->xlx_selmic |= PCXHR_SELMIC_PHANTOM_ALIM; else mgr->xlx_selmic &= ~PCXHR_SELMIC_PHANTOM_ALIM; PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic); dev_dbg(&mgr->pci->dev, "hr222_phantom_power : set %d\n", power); } /* mic level */ static const DECLARE_TLV_DB_SCALE(db_scale_mic_hr222, -9850, 50, 650); static int hr222_mic_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = HR222_MICRO_CAPTURE_LEVEL_MIN; /* -98 dB */ /* gains from 9 dB to 31.5 dB not recommended; use micboost instead */ uinfo->value.integer.max = HR222_MICRO_CAPTURE_LEVEL_MAX; /* +7 dB */ return 0; } static int hr222_mic_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->mic_volume; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int hr222_mic_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; mutex_lock(&chip->mgr->mixer_mutex); if (chip->mic_volume != ucontrol->value.integer.value[0]) { changed = 1; chip->mic_volume = ucontrol->value.integer.value[0]; hr222_update_analog_audio_level(chip, 1, 0); } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new hr222_control_mic_level = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Mic Capture Volume", .info = hr222_mic_vol_info, .get = hr222_mic_vol_get, .put = hr222_mic_vol_put, .tlv = { .p = db_scale_mic_hr222 }, }; /* mic boost level */ static const DECLARE_TLV_DB_SCALE(db_scale_micboost_hr222, 0, 1800, 5400); static int hr222_mic_boost_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; /* 0 dB */ uinfo->value.integer.max = 3; /* 54 dB */ return 0; } static int hr222_mic_boost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->mic_boost; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int hr222_mic_boost_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; mutex_lock(&chip->mgr->mixer_mutex); if (chip->mic_boost != ucontrol->value.integer.value[0]) { changed = 1; chip->mic_boost = ucontrol->value.integer.value[0]; hr222_micro_boost(chip->mgr, chip->mic_boost); } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new hr222_control_mic_boost = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "MicBoost Capture Volume", .info = hr222_mic_boost_info, .get = hr222_mic_boost_get, .put = hr222_mic_boost_put, .tlv = { .p = db_scale_micboost_hr222 }, }; /******************* Phantom power switch *******************/ #define hr222_phantom_power_info snd_ctl_boolean_mono_info static int hr222_phantom_power_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->phantom_power; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int hr222_phantom_power_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int power, changed = 0; mutex_lock(&chip->mgr->mixer_mutex); power = !!ucontrol->value.integer.value[0]; if (chip->phantom_power != power) { hr222_phantom_power(chip->mgr, power); chip->phantom_power = power; changed = 1; } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new hr222_phantom_power_switch = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Phantom Power Switch", .info = hr222_phantom_power_info, .get = hr222_phantom_power_get, .put = hr222_phantom_power_put, }; int hr222_add_mic_controls(struct snd_pcxhr *chip) { int err; if (!chip->mgr->board_has_mic) return 0; /* controls */ err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_level, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_boost, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_phantom_power_switch, chip)); return err; }
linux-master
sound/pci/pcxhr/pcxhr_mix22.c
// SPDX-License-Identifier: GPL-2.0-or-later #define __NO_VERSION__ /* * Driver for Digigram pcxhr compatible soundcards * * mixer callbacks * * Copyright (c) 2004 by Digigram <[email protected]> */ #include <linux/time.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/mutex.h> #include <sound/core.h> #include "pcxhr.h" #include "pcxhr_hwdep.h" #include "pcxhr_core.h" #include <sound/control.h> #include <sound/tlv.h> #include <sound/asoundef.h> #include "pcxhr_mixer.h" #include "pcxhr_mix22.h" #define PCXHR_LINE_CAPTURE_LEVEL_MIN 0 /* -112.0 dB */ #define PCXHR_LINE_CAPTURE_LEVEL_MAX 255 /* +15.5 dB */ #define PCXHR_LINE_CAPTURE_ZERO_LEVEL 224 /* 0.0 dB ( 0 dBu -> 0 dBFS ) */ #define PCXHR_LINE_PLAYBACK_LEVEL_MIN 0 /* -104.0 dB */ #define PCXHR_LINE_PLAYBACK_LEVEL_MAX 128 /* +24.0 dB */ #define PCXHR_LINE_PLAYBACK_ZERO_LEVEL 104 /* 0.0 dB ( 0 dBFS -> 0 dBu ) */ static const DECLARE_TLV_DB_SCALE(db_scale_analog_capture, -11200, 50, 1550); static const DECLARE_TLV_DB_SCALE(db_scale_analog_playback, -10400, 100, 2400); static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_capture, -11150, 50, 1600); static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_playback, -2550, 50, 2400); static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip, int is_capture, int channel) { int err, vol; struct pcxhr_rmh rmh; pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); if (is_capture) { rmh.cmd[0] |= IO_NUM_REG_IN_ANA_LEVEL; rmh.cmd[2] = chip->analog_capture_volume[channel]; } else { rmh.cmd[0] |= IO_NUM_REG_OUT_ANA_LEVEL; if (chip->analog_playback_active[channel]) vol = chip->analog_playback_volume[channel]; else vol = PCXHR_LINE_PLAYBACK_LEVEL_MIN; /* playback analog levels are inversed */ rmh.cmd[2] = PCXHR_LINE_PLAYBACK_LEVEL_MAX - vol; } rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */ rmh.cmd_len = 3; err = pcxhr_send_msg(chip->mgr, &rmh); if (err < 0) { dev_dbg(chip->card->dev, "error update_analog_audio_level card(%d)" " is_capture(%d) err(%x)\n", chip->chip_idx, is_capture, err); return -EINVAL; } return 0; } /* * analog level control */ static int pcxhr_analog_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; if (kcontrol->private_value == 0) { /* playback */ if (chip->mgr->is_hr_stereo) { uinfo->value.integer.min = HR222_LINE_PLAYBACK_LEVEL_MIN; /* -25 dB */ uinfo->value.integer.max = HR222_LINE_PLAYBACK_LEVEL_MAX; /* +24 dB */ } else { uinfo->value.integer.min = PCXHR_LINE_PLAYBACK_LEVEL_MIN; /*-104 dB */ uinfo->value.integer.max = PCXHR_LINE_PLAYBACK_LEVEL_MAX; /* +24 dB */ } } else { /* capture */ if (chip->mgr->is_hr_stereo) { uinfo->value.integer.min = HR222_LINE_CAPTURE_LEVEL_MIN; /*-112 dB */ uinfo->value.integer.max = HR222_LINE_CAPTURE_LEVEL_MAX; /* +15.5 dB */ } else { uinfo->value.integer.min = PCXHR_LINE_CAPTURE_LEVEL_MIN; /*-112 dB */ uinfo->value.integer.max = PCXHR_LINE_CAPTURE_LEVEL_MAX; /* +15.5 dB */ } } return 0; } static int pcxhr_analog_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); if (kcontrol->private_value == 0) { /* playback */ ucontrol->value.integer.value[0] = chip->analog_playback_volume[0]; ucontrol->value.integer.value[1] = chip->analog_playback_volume[1]; } else { /* capture */ ucontrol->value.integer.value[0] = chip->analog_capture_volume[0]; ucontrol->value.integer.value[1] = chip->analog_capture_volume[1]; } mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_analog_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; int is_capture, i; mutex_lock(&chip->mgr->mixer_mutex); is_capture = (kcontrol->private_value != 0); for (i = 0; i < 2; i++) { int new_volume = ucontrol->value.integer.value[i]; int *stored_volume = is_capture ? &chip->analog_capture_volume[i] : &chip->analog_playback_volume[i]; if (is_capture) { if (chip->mgr->is_hr_stereo) { if (new_volume < HR222_LINE_CAPTURE_LEVEL_MIN || new_volume > HR222_LINE_CAPTURE_LEVEL_MAX) continue; } else { if (new_volume < PCXHR_LINE_CAPTURE_LEVEL_MIN || new_volume > PCXHR_LINE_CAPTURE_LEVEL_MAX) continue; } } else { if (chip->mgr->is_hr_stereo) { if (new_volume < HR222_LINE_PLAYBACK_LEVEL_MIN || new_volume > HR222_LINE_PLAYBACK_LEVEL_MAX) continue; } else { if (new_volume < PCXHR_LINE_PLAYBACK_LEVEL_MIN || new_volume > PCXHR_LINE_PLAYBACK_LEVEL_MAX) continue; } } if (*stored_volume != new_volume) { *stored_volume = new_volume; changed = 1; if (chip->mgr->is_hr_stereo) hr222_update_analog_audio_level(chip, is_capture, i); else pcxhr_update_analog_audio_level(chip, is_capture, i); } } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new pcxhr_control_analog_level = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), /* name will be filled later */ .info = pcxhr_analog_vol_info, .get = pcxhr_analog_vol_get, .put = pcxhr_analog_vol_put, /* tlv will be filled later */ }; /* shared */ #define pcxhr_sw_info snd_ctl_boolean_stereo_info static int pcxhr_audio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->analog_playback_active[0]; ucontrol->value.integer.value[1] = chip->analog_playback_active[1]; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_audio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int i, changed = 0; mutex_lock(&chip->mgr->mixer_mutex); for(i = 0; i < 2; i++) { if (chip->analog_playback_active[i] != ucontrol->value.integer.value[i]) { chip->analog_playback_active[i] = !!ucontrol->value.integer.value[i]; changed = 1; /* update playback levels */ if (chip->mgr->is_hr_stereo) hr222_update_analog_audio_level(chip, 0, i); else pcxhr_update_analog_audio_level(chip, 0, i); } } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new pcxhr_control_output_switch = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Master Playback Switch", .info = pcxhr_sw_info, /* shared */ .get = pcxhr_audio_sw_get, .put = pcxhr_audio_sw_put }; #define PCXHR_DIGITAL_LEVEL_MIN 0x000 /* -110 dB */ #define PCXHR_DIGITAL_LEVEL_MAX 0x1ff /* +18 dB */ #define PCXHR_DIGITAL_ZERO_LEVEL 0x1b7 /* 0 dB */ static const DECLARE_TLV_DB_SCALE(db_scale_digital, -10975, 25, 1800); #define MORE_THAN_ONE_STREAM_LEVEL 0x000001 #define VALID_STREAM_PAN_LEVEL_MASK 0x800000 #define VALID_STREAM_LEVEL_MASK 0x400000 #define VALID_STREAM_LEVEL_1_MASK 0x200000 #define VALID_STREAM_LEVEL_2_MASK 0x100000 static int pcxhr_update_playback_stream_level(struct snd_pcxhr* chip, int idx) { int err; struct pcxhr_rmh rmh; struct pcxhr_pipe *pipe = &chip->playback_pipe; int left, right; if (chip->digital_playback_active[idx][0]) left = chip->digital_playback_volume[idx][0]; else left = PCXHR_DIGITAL_LEVEL_MIN; if (chip->digital_playback_active[idx][1]) right = chip->digital_playback_volume[idx][1]; else right = PCXHR_DIGITAL_LEVEL_MIN; pcxhr_init_rmh(&rmh, CMD_STREAM_OUT_LEVEL_ADJUST); /* add pipe and stream mask */ pcxhr_set_pipe_cmd_params(&rmh, 0, pipe->first_audio, 0, 1<<idx); /* volume left->left / right->right panoramic level */ rmh.cmd[0] |= MORE_THAN_ONE_STREAM_LEVEL; rmh.cmd[2] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_1_MASK; rmh.cmd[2] |= (left << 10); rmh.cmd[3] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_2_MASK; rmh.cmd[3] |= right; rmh.cmd_len = 4; err = pcxhr_send_msg(chip->mgr, &rmh); if (err < 0) { dev_dbg(chip->card->dev, "error update_playback_stream_level " "card(%d) err(%x)\n", chip->chip_idx, err); return -EINVAL; } return 0; } #define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 #define AUDIO_IO_HAS_MUTE_MONITOR_1 0x200000 #define VALID_AUDIO_IO_DIGITAL_LEVEL 0x000001 #define VALID_AUDIO_IO_MONITOR_LEVEL 0x000002 #define VALID_AUDIO_IO_MUTE_LEVEL 0x000004 #define VALID_AUDIO_IO_MUTE_MONITOR_1 0x000008 static int pcxhr_update_audio_pipe_level(struct snd_pcxhr *chip, int capture, int channel) { int err; struct pcxhr_rmh rmh; struct pcxhr_pipe *pipe; if (capture) pipe = &chip->capture_pipe[0]; else pipe = &chip->playback_pipe; pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST); /* add channel mask */ pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0, 1 << (channel + pipe->first_audio)); /* TODO : if mask (3 << pipe->first_audio) is used, left and right * channel will be programmed to the same params */ if (capture) { rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL; /* VALID_AUDIO_IO_MUTE_LEVEL not yet handled * (capture pipe level) */ rmh.cmd[2] = chip->digital_capture_volume[channel]; } else { rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL | VALID_AUDIO_IO_MUTE_MONITOR_1; /* VALID_AUDIO_IO_DIGITAL_LEVEL and VALID_AUDIO_IO_MUTE_LEVEL * not yet handled (playback pipe level) */ rmh.cmd[2] = chip->monitoring_volume[channel] << 10; if (chip->monitoring_active[channel] == 0) rmh.cmd[2] |= AUDIO_IO_HAS_MUTE_MONITOR_1; } rmh.cmd_len = 3; err = pcxhr_send_msg(chip->mgr, &rmh); if (err < 0) { dev_dbg(chip->card->dev, "error update_audio_level(%d) err=%x\n", chip->chip_idx, err); return -EINVAL; } return 0; } /* shared */ static int pcxhr_digital_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = PCXHR_DIGITAL_LEVEL_MIN; /* -109.5 dB */ uinfo->value.integer.max = PCXHR_DIGITAL_LEVEL_MAX; /* 18.0 dB */ return 0; } static int pcxhr_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ int *stored_volume; int is_capture = kcontrol->private_value; mutex_lock(&chip->mgr->mixer_mutex); if (is_capture) /* digital capture */ stored_volume = chip->digital_capture_volume; else /* digital playback */ stored_volume = chip->digital_playback_volume[idx]; ucontrol->value.integer.value[0] = stored_volume[0]; ucontrol->value.integer.value[1] = stored_volume[1]; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ int changed = 0; int is_capture = kcontrol->private_value; int *stored_volume; int i; mutex_lock(&chip->mgr->mixer_mutex); if (is_capture) /* digital capture */ stored_volume = chip->digital_capture_volume; else /* digital playback */ stored_volume = chip->digital_playback_volume[idx]; for (i = 0; i < 2; i++) { int vol = ucontrol->value.integer.value[i]; if (vol < PCXHR_DIGITAL_LEVEL_MIN || vol > PCXHR_DIGITAL_LEVEL_MAX) continue; if (stored_volume[i] != vol) { stored_volume[i] = vol; changed = 1; if (is_capture) /* update capture volume */ pcxhr_update_audio_pipe_level(chip, 1, i); } } if (!is_capture && changed) /* update playback volume */ pcxhr_update_playback_stream_level(chip, idx); mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new snd_pcxhr_pcm_vol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), /* name will be filled later */ /* count will be filled later */ .info = pcxhr_digital_vol_info, /* shared */ .get = pcxhr_pcm_vol_get, .put = pcxhr_pcm_vol_put, .tlv = { .p = db_scale_digital }, }; static int pcxhr_pcm_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->digital_playback_active[idx][0]; ucontrol->value.integer.value[1] = chip->digital_playback_active[idx][1]; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_pcm_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ int i, j; mutex_lock(&chip->mgr->mixer_mutex); j = idx; for (i = 0; i < 2; i++) { if (chip->digital_playback_active[j][i] != ucontrol->value.integer.value[i]) { chip->digital_playback_active[j][i] = !!ucontrol->value.integer.value[i]; changed = 1; } } if (changed) pcxhr_update_playback_stream_level(chip, idx); mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new pcxhr_control_pcm_switch = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "PCM Playback Switch", .count = PCXHR_PLAYBACK_STREAMS, .info = pcxhr_sw_info, /* shared */ .get = pcxhr_pcm_sw_get, .put = pcxhr_pcm_sw_put }; /* * monitoring level control */ static int pcxhr_monitor_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->monitoring_volume[0]; ucontrol->value.integer.value[1] = chip->monitoring_volume[1]; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_monitor_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; int i; mutex_lock(&chip->mgr->mixer_mutex); for (i = 0; i < 2; i++) { if (chip->monitoring_volume[i] != ucontrol->value.integer.value[i]) { chip->monitoring_volume[i] = ucontrol->value.integer.value[i]; if (chip->monitoring_active[i]) /* update monitoring volume and mute */ /* do only when monitoring is unmuted */ pcxhr_update_audio_pipe_level(chip, 0, i); changed = 1; } } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new pcxhr_control_monitor_vol = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Monitoring Playback Volume", .info = pcxhr_digital_vol_info, /* shared */ .get = pcxhr_monitor_vol_get, .put = pcxhr_monitor_vol_put, .tlv = { .p = db_scale_digital }, }; /* * monitoring switch control */ static int pcxhr_monitor_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); mutex_lock(&chip->mgr->mixer_mutex); ucontrol->value.integer.value[0] = chip->monitoring_active[0]; ucontrol->value.integer.value[1] = chip->monitoring_active[1]; mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_monitor_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int changed = 0; int i; mutex_lock(&chip->mgr->mixer_mutex); for (i = 0; i < 2; i++) { if (chip->monitoring_active[i] != ucontrol->value.integer.value[i]) { chip->monitoring_active[i] = !!ucontrol->value.integer.value[i]; changed |= (1<<i); /* mask 0x01 and 0x02 */ } } if (changed & 0x01) /* update left monitoring volume and mute */ pcxhr_update_audio_pipe_level(chip, 0, 0); if (changed & 0x02) /* update right monitoring volume and mute */ pcxhr_update_audio_pipe_level(chip, 0, 1); mutex_unlock(&chip->mgr->mixer_mutex); return (changed != 0); } static const struct snd_kcontrol_new pcxhr_control_monitor_sw = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Monitoring Playback Switch", .info = pcxhr_sw_info, /* shared */ .get = pcxhr_monitor_sw_get, .put = pcxhr_monitor_sw_put }; /* * audio source select */ #define PCXHR_SOURCE_AUDIO01_UER 0x000100 #define PCXHR_SOURCE_AUDIO01_SYNC 0x000200 #define PCXHR_SOURCE_AUDIO23_UER 0x000400 #define PCXHR_SOURCE_AUDIO45_UER 0x001000 #define PCXHR_SOURCE_AUDIO67_UER 0x040000 static int pcxhr_set_audio_source(struct snd_pcxhr* chip) { struct pcxhr_rmh rmh; unsigned int mask, reg; unsigned int codec; int err, changed; switch (chip->chip_idx) { case 0 : mask = PCXHR_SOURCE_AUDIO01_UER; codec = CS8420_01_CS; break; case 1 : mask = PCXHR_SOURCE_AUDIO23_UER; codec = CS8420_23_CS; break; case 2 : mask = PCXHR_SOURCE_AUDIO45_UER; codec = CS8420_45_CS; break; case 3 : mask = PCXHR_SOURCE_AUDIO67_UER; codec = CS8420_67_CS; break; default: return -EINVAL; } if (chip->audio_capture_source != 0) { reg = mask; /* audio source from digital plug */ } else { reg = 0; /* audio source from analog plug */ } /* set the input source */ pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed); /* resync them (otherwise channel inversion possible) */ if (changed) { pcxhr_init_rmh(&rmh, CMD_RESYNC_AUDIO_INPUTS); rmh.cmd[0] |= (1 << chip->chip_idx); err = pcxhr_send_msg(chip->mgr, &rmh); if (err) return err; } if (chip->mgr->board_aes_in_192k) { int i; unsigned int src_config = 0xC0; /* update all src configs with one call */ for (i = 0; (i < 4) && (i < chip->mgr->capture_chips); i++) { if (chip->mgr->chip[i]->audio_capture_source == 2) src_config |= (1 << (3 - i)); } /* set codec SRC on off */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd_len = 2; rmh.cmd[0] |= IO_NUM_REG_CONFIG_SRC; rmh.cmd[1] = src_config; err = pcxhr_send_msg(chip->mgr, &rmh); } else { int use_src = 0; if (chip->audio_capture_source == 2) use_src = 1; /* set codec SRC on off */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd_len = 3; rmh.cmd[0] |= IO_NUM_UER_CHIP_REG; rmh.cmd[1] = codec; rmh.cmd[2] = ((CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x54)); err = pcxhr_send_msg(chip->mgr, &rmh); if (err) return err; rmh.cmd[2] = ((CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x49)); err = pcxhr_send_msg(chip->mgr, &rmh); } return err; } static int pcxhr_audio_src_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char *texts[5] = { "Line", "Digital", "Digi+SRC", "Mic", "Line+Mic" }; int i; struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); i = 2; /* no SRC, no Mic available */ if (chip->mgr->board_has_aes1) { i = 3; /* SRC available */ if (chip->mgr->board_has_mic) i = 5; /* Mic and MicroMix available */ } return snd_ctl_enum_info(uinfo, 1, i, texts); } static int pcxhr_audio_src_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = chip->audio_capture_source; return 0; } static int pcxhr_audio_src_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int ret = 0; int i = 2; /* no SRC, no Mic available */ if (chip->mgr->board_has_aes1) { i = 3; /* SRC available */ if (chip->mgr->board_has_mic) i = 5; /* Mic and MicroMix available */ } if (ucontrol->value.enumerated.item[0] >= i) return -EINVAL; mutex_lock(&chip->mgr->mixer_mutex); if (chip->audio_capture_source != ucontrol->value.enumerated.item[0]) { chip->audio_capture_source = ucontrol->value.enumerated.item[0]; if (chip->mgr->is_hr_stereo) hr222_set_audio_source(chip); else pcxhr_set_audio_source(chip); ret = 1; } mutex_unlock(&chip->mgr->mixer_mutex); return ret; } static const struct snd_kcontrol_new pcxhr_control_audio_src = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Capture Source", .info = pcxhr_audio_src_info, .get = pcxhr_audio_src_get, .put = pcxhr_audio_src_put, }; /* * clock type selection * enum pcxhr_clock_type { * PCXHR_CLOCK_TYPE_INTERNAL = 0, * PCXHR_CLOCK_TYPE_WORD_CLOCK, * PCXHR_CLOCK_TYPE_AES_SYNC, * PCXHR_CLOCK_TYPE_AES_1, * PCXHR_CLOCK_TYPE_AES_2, * PCXHR_CLOCK_TYPE_AES_3, * PCXHR_CLOCK_TYPE_AES_4, * PCXHR_CLOCK_TYPE_MAX = PCXHR_CLOCK_TYPE_AES_4, * HR22_CLOCK_TYPE_INTERNAL = PCXHR_CLOCK_TYPE_INTERNAL, * HR22_CLOCK_TYPE_AES_SYNC, * HR22_CLOCK_TYPE_AES_1, * HR22_CLOCK_TYPE_MAX = HR22_CLOCK_TYPE_AES_1, * }; */ static int pcxhr_clock_type_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static const char *textsPCXHR[7] = { "Internal", "WordClock", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" }; static const char *textsHR22[3] = { "Internal", "AES Sync", "AES 1" }; const char **texts; struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); int clock_items = 2; /* at least Internal and AES Sync clock */ if (mgr->board_has_aes1) { clock_items += mgr->capture_chips; /* add AES x */ if (!mgr->is_hr_stereo) clock_items += 1; /* add word clock */ } if (mgr->is_hr_stereo) { texts = textsHR22; snd_BUG_ON(clock_items > (HR22_CLOCK_TYPE_MAX+1)); } else { texts = textsPCXHR; snd_BUG_ON(clock_items > (PCXHR_CLOCK_TYPE_MAX+1)); } return snd_ctl_enum_info(uinfo, 1, clock_items, texts); } static int pcxhr_clock_type_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); ucontrol->value.enumerated.item[0] = mgr->use_clock_type; return 0; } static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); int rate, ret = 0; unsigned int clock_items = 2; /* at least Internal and AES Sync clock */ if (mgr->board_has_aes1) { clock_items += mgr->capture_chips; /* add AES x */ if (!mgr->is_hr_stereo) clock_items += 1; /* add word clock */ } if (ucontrol->value.enumerated.item[0] >= clock_items) return -EINVAL; mutex_lock(&mgr->mixer_mutex); if (mgr->use_clock_type != ucontrol->value.enumerated.item[0]) { mutex_lock(&mgr->setup_mutex); mgr->use_clock_type = ucontrol->value.enumerated.item[0]; rate = 0; if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { pcxhr_get_external_clock(mgr, mgr->use_clock_type, &rate); } else { rate = mgr->sample_rate; if (!rate) rate = 48000; } if (rate) { pcxhr_set_clock(mgr, rate); if (mgr->sample_rate) mgr->sample_rate = rate; } mutex_unlock(&mgr->setup_mutex); ret = 1; /* return 1 even if the set was not done. ok ? */ } mutex_unlock(&mgr->mixer_mutex); return ret; } static const struct snd_kcontrol_new pcxhr_control_clock_type = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Clock Mode", .info = pcxhr_clock_type_info, .get = pcxhr_clock_type_get, .put = pcxhr_clock_type_put, }; /* * clock rate control * specific control that scans the sample rates on the external plugs */ static int pcxhr_clock_rate_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 3 + mgr->capture_chips; uinfo->value.integer.min = 0; /* clock not present */ uinfo->value.integer.max = 192000; /* max sample rate 192 kHz */ return 0; } static int pcxhr_clock_rate_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); int i, err, rate; mutex_lock(&mgr->mixer_mutex); for(i = 0; i < 3 + mgr->capture_chips; i++) { if (i == PCXHR_CLOCK_TYPE_INTERNAL) rate = mgr->sample_rate_real; else { err = pcxhr_get_external_clock(mgr, i, &rate); if (err) break; } ucontrol->value.integer.value[i] = rate; } mutex_unlock(&mgr->mixer_mutex); return 0; } static const struct snd_kcontrol_new pcxhr_control_clock_rate = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = "Clock Rates", .info = pcxhr_clock_rate_info, .get = pcxhr_clock_rate_get, }; /* * IEC958 status bits */ static int pcxhr_iec958_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int pcxhr_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char *aes_bits) { int i, err; unsigned char temp; struct pcxhr_rmh rmh; pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); rmh.cmd[0] |= IO_NUM_UER_CHIP_REG; switch (chip->chip_idx) { /* instead of CS8420_01_CS use CS8416_01_CS for AES SYNC plug */ case 0: rmh.cmd[1] = CS8420_01_CS; break; case 1: rmh.cmd[1] = CS8420_23_CS; break; case 2: rmh.cmd[1] = CS8420_45_CS; break; case 3: rmh.cmd[1] = CS8420_67_CS; break; default: return -EINVAL; } if (chip->mgr->board_aes_in_192k) { switch (aes_idx) { case 0: rmh.cmd[2] = CS8416_CSB0; break; case 1: rmh.cmd[2] = CS8416_CSB1; break; case 2: rmh.cmd[2] = CS8416_CSB2; break; case 3: rmh.cmd[2] = CS8416_CSB3; break; case 4: rmh.cmd[2] = CS8416_CSB4; break; default: return -EINVAL; } } else { switch (aes_idx) { /* instead of CS8420_CSB0 use CS8416_CSBx for AES SYNC plug */ case 0: rmh.cmd[2] = CS8420_CSB0; break; case 1: rmh.cmd[2] = CS8420_CSB1; break; case 2: rmh.cmd[2] = CS8420_CSB2; break; case 3: rmh.cmd[2] = CS8420_CSB3; break; case 4: rmh.cmd[2] = CS8420_CSB4; break; default: return -EINVAL; } } /* size and code the chip id for the fpga */ rmh.cmd[1] &= 0x0fffff; /* chip signature + map for spi read */ rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI; rmh.cmd_len = 3; err = pcxhr_send_msg(chip->mgr, &rmh); if (err) return err; if (chip->mgr->board_aes_in_192k) { temp = (unsigned char)rmh.stat[1]; } else { temp = 0; /* reversed bit order (not with CS8416_01_CS) */ for (i = 0; i < 8; i++) { temp <<= 1; if (rmh.stat[1] & (1 << i)) temp |= 1; } } dev_dbg(chip->card->dev, "read iec958 AES %d byte %d = 0x%x\n", chip->chip_idx, aes_idx, temp); *aes_bits = temp; return 0; } static int pcxhr_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); unsigned char aes_bits; int i, err; mutex_lock(&chip->mgr->mixer_mutex); for(i = 0; i < 5; i++) { if (kcontrol->private_value == 0) /* playback */ aes_bits = chip->aes_bits[i]; else { /* capture */ if (chip->mgr->is_hr_stereo) err = hr222_iec958_capture_byte(chip, i, &aes_bits); else err = pcxhr_iec958_capture_byte(chip, i, &aes_bits); if (err) break; } ucontrol->value.iec958.status[i] = aes_bits; } mutex_unlock(&chip->mgr->mixer_mutex); return 0; } static int pcxhr_iec958_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { int i; for (i = 0; i < 5; i++) ucontrol->value.iec958.status[i] = 0xff; return 0; } static int pcxhr_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char aes_bits) { int i, err, cmd; unsigned char new_bits = aes_bits; unsigned char old_bits = chip->aes_bits[aes_idx]; struct pcxhr_rmh rmh; for (i = 0; i < 8; i++) { if ((old_bits & 0x01) != (new_bits & 0x01)) { cmd = chip->chip_idx & 0x03; /* chip index 0..3 */ if (chip->chip_idx > 3) /* new bit used if chip_idx>3 (PCX1222HR) */ cmd |= 1 << 22; cmd |= ((aes_idx << 3) + i) << 2; /* add bit offset */ cmd |= (new_bits & 0x01) << 23; /* add bit value */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd[0] |= IO_NUM_REG_CUER; rmh.cmd[1] = cmd; rmh.cmd_len = 2; dev_dbg(chip->card->dev, "write iec958 AES %d byte %d bit %d (cmd %x)\n", chip->chip_idx, aes_idx, i, cmd); err = pcxhr_send_msg(chip->mgr, &rmh); if (err) return err; } old_bits >>= 1; new_bits >>= 1; } chip->aes_bits[aes_idx] = aes_bits; return 0; } static int pcxhr_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); int i, changed = 0; /* playback */ mutex_lock(&chip->mgr->mixer_mutex); for (i = 0; i < 5; i++) { if (ucontrol->value.iec958.status[i] != chip->aes_bits[i]) { if (chip->mgr->is_hr_stereo) hr222_iec958_update_byte(chip, i, ucontrol->value.iec958.status[i]); else pcxhr_iec958_update_byte(chip, i, ucontrol->value.iec958.status[i]); changed = 1; } } mutex_unlock(&chip->mgr->mixer_mutex); return changed; } static const struct snd_kcontrol_new pcxhr_control_playback_iec958_mask = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), .info = pcxhr_iec958_info, .get = pcxhr_iec958_mask_get }; static const struct snd_kcontrol_new pcxhr_control_playback_iec958 = { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = pcxhr_iec958_info, .get = pcxhr_iec958_get, .put = pcxhr_iec958_put, .private_value = 0 /* playback */ }; static const struct snd_kcontrol_new pcxhr_control_capture_iec958_mask = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK), .info = pcxhr_iec958_info, .get = pcxhr_iec958_mask_get }; static const struct snd_kcontrol_new pcxhr_control_capture_iec958 = { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT), .info = pcxhr_iec958_info, .get = pcxhr_iec958_get, .private_value = 1 /* capture */ }; static void pcxhr_init_audio_levels(struct snd_pcxhr *chip) { int i; for (i = 0; i < 2; i++) { if (chip->nb_streams_play) { int j; /* at boot time the digital volumes are unmuted 0dB */ for (j = 0; j < PCXHR_PLAYBACK_STREAMS; j++) { chip->digital_playback_active[j][i] = 1; chip->digital_playback_volume[j][i] = PCXHR_DIGITAL_ZERO_LEVEL; } /* after boot, only two bits are set on the uer * interface */ chip->aes_bits[0] = (IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_FS_48000); #ifdef CONFIG_SND_DEBUG /* analog volumes for playback * (is LEVEL_MIN after boot) */ chip->analog_playback_active[i] = 1; if (chip->mgr->is_hr_stereo) chip->analog_playback_volume[i] = HR222_LINE_PLAYBACK_ZERO_LEVEL; else { chip->analog_playback_volume[i] = PCXHR_LINE_PLAYBACK_ZERO_LEVEL; pcxhr_update_analog_audio_level(chip, 0, i); } #endif /* stereo cards need to be initialised after boot */ if (chip->mgr->is_hr_stereo) hr222_update_analog_audio_level(chip, 0, i); } if (chip->nb_streams_capt) { /* at boot time the digital volumes are unmuted 0dB */ chip->digital_capture_volume[i] = PCXHR_DIGITAL_ZERO_LEVEL; chip->analog_capture_active = 1; #ifdef CONFIG_SND_DEBUG /* analog volumes for playback * (is LEVEL_MIN after boot) */ if (chip->mgr->is_hr_stereo) chip->analog_capture_volume[i] = HR222_LINE_CAPTURE_ZERO_LEVEL; else { chip->analog_capture_volume[i] = PCXHR_LINE_CAPTURE_ZERO_LEVEL; pcxhr_update_analog_audio_level(chip, 1, i); } #endif /* stereo cards need to be initialised after boot */ if (chip->mgr->is_hr_stereo) hr222_update_analog_audio_level(chip, 1, i); } } return; } int pcxhr_create_mixer(struct pcxhr_mgr *mgr) { struct snd_pcxhr *chip; int err, i; mutex_init(&mgr->mixer_mutex); /* can be in another place */ for (i = 0; i < mgr->num_cards; i++) { struct snd_kcontrol_new temp; chip = mgr->chip[i]; if (chip->nb_streams_play) { /* analog output level control */ temp = pcxhr_control_analog_level; temp.name = "Master Playback Volume"; temp.private_value = 0; /* playback */ if (mgr->is_hr_stereo) temp.tlv.p = db_scale_a_hr222_playback; else temp.tlv.p = db_scale_analog_playback; err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip)); if (err < 0) return err; /* output mute controls */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_output_switch, chip)); if (err < 0) return err; temp = snd_pcxhr_pcm_vol; temp.name = "PCM Playback Volume"; temp.count = PCXHR_PLAYBACK_STREAMS; temp.private_value = 0; /* playback */ err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_pcm_switch, chip)); if (err < 0) return err; /* IEC958 controls */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_playback_iec958_mask, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_playback_iec958, chip)); if (err < 0) return err; } if (chip->nb_streams_capt) { /* analog input level control */ temp = pcxhr_control_analog_level; temp.name = "Line Capture Volume"; temp.private_value = 1; /* capture */ if (mgr->is_hr_stereo) temp.tlv.p = db_scale_a_hr222_capture; else temp.tlv.p = db_scale_analog_capture; err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip)); if (err < 0) return err; temp = snd_pcxhr_pcm_vol; temp.name = "PCM Capture Volume"; temp.count = 1; temp.private_value = 1; /* capture */ err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip)); if (err < 0) return err; /* Audio source */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_audio_src, chip)); if (err < 0) return err; /* IEC958 controls */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_capture_iec958_mask, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_capture_iec958, chip)); if (err < 0) return err; if (mgr->is_hr_stereo) { err = hr222_add_mic_controls(chip); if (err < 0) return err; } } /* monitoring only if playback and capture device available */ if (chip->nb_streams_capt > 0 && chip->nb_streams_play > 0) { /* monitoring */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_monitor_vol, chip)); if (err < 0) return err; err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_monitor_sw, chip)); if (err < 0) return err; } if (i == 0) { /* clock mode only one control per pcxhr */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_clock_type, mgr)); if (err < 0) return err; /* non standard control used to scan * the external clock presence/frequencies */ err = snd_ctl_add(chip->card, snd_ctl_new1(&pcxhr_control_clock_rate, mgr)); if (err < 0) return err; } /* init values for the mixer data */ pcxhr_init_audio_levels(chip); } return 0; }
linux-master
sound/pci/pcxhr/pcxhr_mixer.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram pcxhr compatible soundcards * * main file with alsa callbacks * * Copyright (c) 2004 by Digigram <[email protected]> */ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/mutex.h> #include <sound/core.h> #include <sound/initval.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include "pcxhr.h" #include "pcxhr_mixer.h" #include "pcxhr_hwdep.h" #include "pcxhr_core.h" #include "pcxhr_mix22.h" #define DRIVER_NAME "pcxhr" MODULE_AUTHOR("Markus Bollinger <[email protected]>, " "Marc Titinger <[email protected]>"); MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); MODULE_LICENSE("GPL"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ static bool mono[SNDRV_CARDS]; /* capture mono only */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard"); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard"); module_param_array(mono, bool, NULL, 0444); MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)"); enum { PCI_ID_VX882HR, PCI_ID_PCX882HR, PCI_ID_VX881HR, PCI_ID_PCX881HR, PCI_ID_VX882E, PCI_ID_PCX882E, PCI_ID_VX881E, PCI_ID_PCX881E, PCI_ID_VX1222HR, PCI_ID_PCX1222HR, PCI_ID_VX1221HR, PCI_ID_PCX1221HR, PCI_ID_VX1222E, PCI_ID_PCX1222E, PCI_ID_VX1221E, PCI_ID_PCX1221E, PCI_ID_VX222HR, PCI_ID_VX222E, PCI_ID_PCX22HR, PCI_ID_PCX22E, PCI_ID_VX222HRMIC, PCI_ID_VX222E_MIC, PCI_ID_PCX924HR, PCI_ID_PCX924E, PCI_ID_PCX924HRMIC, PCI_ID_PCX924E_MIC, PCI_ID_VX442HR, PCI_ID_PCX442HR, PCI_ID_VX442E, PCI_ID_PCX442E, PCI_ID_VX822HR, PCI_ID_PCX822HR, PCI_ID_VX822E, PCI_ID_PCX822E, PCI_ID_LAST }; static const struct pci_device_id pcxhr_ids[] = { { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, }, { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, }, { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, }, { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, }, { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, }, { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, }, { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, }, { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, }, { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, }, { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, }, { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, }, { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, }, { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, }, { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, }, { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, }, { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, }, { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, }, { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, }, { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, }, { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, }, { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, }, { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, }, { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, }, { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, }, { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, }, { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, }, { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, }, { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, }, { 0, } }; MODULE_DEVICE_TABLE(pci, pcxhr_ids); struct board_parameters { char* board_name; short playback_chips; short capture_chips; short fw_file_set; short firmware_num; }; static const struct board_parameters pcxhr_board_params[] = { [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 }, [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 }, [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 }, [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 }, [PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 }, [PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 }, [PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 }, [PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 }, [PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 }, [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 }, [PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 }, [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 }, [PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 }, [PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 }, [PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 }, [PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 }, [PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 }, [PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 }, [PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 }, [PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 }, [PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 }, [PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 }, [PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 }, [PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 }, [PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 }, [PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 }, [PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 }, [PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 }, [PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 }, [PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 }, [PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 }, [PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 }, [PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 }, [PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 }, }; /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */ /* VX222HR, VX222e, PCX22HR and PCX22e */ #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4) /* some boards do not support 192kHz on digital AES input plugs */ #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \ (x->fw_file_set == 0) || \ (x->fw_file_set == 2)) static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, unsigned int* realfreq) { unsigned int reg; if (freq < 6900 || freq > 110000) return -EINVAL; reg = (28224000 * 2) / freq; reg = (reg - 1) / 2; if (reg < 0x200) *pllreg = reg + 0x800; else if (reg < 0x400) *pllreg = reg & 0x1ff; else if (reg < 0x800) { *pllreg = ((reg >> 1) & 0x1ff) + 0x200; reg &= ~1; } else { *pllreg = ((reg >> 2) & 0x1ff) + 0x400; reg &= ~3; } if (realfreq) *realfreq = (28224000 / (reg + 1)); return 0; } #define PCXHR_FREQ_REG_MASK 0x1f #define PCXHR_FREQ_QUARTZ_48000 0x00 #define PCXHR_FREQ_QUARTZ_24000 0x01 #define PCXHR_FREQ_QUARTZ_12000 0x09 #define PCXHR_FREQ_QUARTZ_32000 0x08 #define PCXHR_FREQ_QUARTZ_16000 0x04 #define PCXHR_FREQ_QUARTZ_8000 0x0c #define PCXHR_FREQ_QUARTZ_44100 0x02 #define PCXHR_FREQ_QUARTZ_22050 0x0a #define PCXHR_FREQ_QUARTZ_11025 0x06 #define PCXHR_FREQ_PLL 0x05 #define PCXHR_FREQ_QUARTZ_192000 0x10 #define PCXHR_FREQ_QUARTZ_96000 0x18 #define PCXHR_FREQ_QUARTZ_176400 0x14 #define PCXHR_FREQ_QUARTZ_88200 0x1c #define PCXHR_FREQ_QUARTZ_128000 0x12 #define PCXHR_FREQ_QUARTZ_64000 0x1a #define PCXHR_FREQ_WORD_CLOCK 0x0f #define PCXHR_FREQ_SYNC_AES 0x0e #define PCXHR_FREQ_AES_1 0x07 #define PCXHR_FREQ_AES_2 0x0b #define PCXHR_FREQ_AES_3 0x03 #define PCXHR_FREQ_AES_4 0x0d static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, unsigned int *reg, unsigned int *freq) { unsigned int val, realfreq, pllreg; struct pcxhr_rmh rmh; int err; realfreq = rate; switch (mgr->use_clock_type) { case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */ switch (rate) { case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; default : val = PCXHR_FREQ_PLL; /* get the value for the pll register */ err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); if (err) return err; pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd[0] |= IO_NUM_REG_GENCLK; rmh.cmd[1] = pllreg & MASK_DSP_WORD; rmh.cmd[2] = pllreg >> 24; rmh.cmd_len = 3; err = pcxhr_send_msg(mgr, &rmh); if (err < 0) { dev_err(&mgr->pci->dev, "error CMD_ACCESS_IO_WRITE " "for PLL register : %x!\n", err); return err; } } break; case PCXHR_CLOCK_TYPE_WORD_CLOCK: val = PCXHR_FREQ_WORD_CLOCK; break; case PCXHR_CLOCK_TYPE_AES_SYNC: val = PCXHR_FREQ_SYNC_AES; break; case PCXHR_CLOCK_TYPE_AES_1: val = PCXHR_FREQ_AES_1; break; case PCXHR_CLOCK_TYPE_AES_2: val = PCXHR_FREQ_AES_2; break; case PCXHR_CLOCK_TYPE_AES_3: val = PCXHR_FREQ_AES_3; break; case PCXHR_CLOCK_TYPE_AES_4: val = PCXHR_FREQ_AES_4; break; default: return -EINVAL; } *reg = val; *freq = realfreq; return 0; } static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr, unsigned int rate, int *changed) { unsigned int val, realfreq, speed; struct pcxhr_rmh rmh; int err; err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); if (err) return err; /* codec speed modes */ if (rate < 55000) speed = 0; /* single speed */ else if (rate < 100000) speed = 1; /* dual speed */ else speed = 2; /* quad speed */ if (mgr->codec_speed != speed) { pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; if (DSP_EXT_CMD_SET(mgr)) { rmh.cmd[1] = 1; rmh.cmd_len = 2; } err = pcxhr_send_msg(mgr, &rmh); if (err) return err; pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ rmh.cmd[0] |= IO_NUM_SPEED_RATIO; rmh.cmd[1] = speed; rmh.cmd_len = 2; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; } /* set the new frequency */ dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val); err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, changed); if (err) return err; mgr->sample_rate_real = realfreq; mgr->cur_clock_type = mgr->use_clock_type; /* unmute after codec speed modes */ if (mgr->codec_speed != speed) { pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; if (DSP_EXT_CMD_SET(mgr)) { rmh.cmd[1] = 1; rmh.cmd_len = 2; } err = pcxhr_send_msg(mgr, &rmh); if (err) return err; mgr->codec_speed = speed; /* save new codec speed */ } dev_dbg(&mgr->pci->dev, "%s to %dHz (realfreq=%d)\n", __func__, rate, realfreq); return 0; } #define PCXHR_MODIFY_CLOCK_S_BIT 0x04 #define PCXHR_IRQ_TIMER_FREQ 92000 #define PCXHR_IRQ_TIMER_PERIOD 48 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) { struct pcxhr_rmh rmh; int err, changed; if (rate == 0) return 0; /* nothing to do */ if (mgr->is_hr_stereo) err = hr222_sub_set_clock(mgr, rate, &changed); else err = pcxhr_sub_set_clock(mgr, rate, &changed); if (err) return err; if (changed) { pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ if (rate < PCXHR_IRQ_TIMER_FREQ) rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; else rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2; rmh.cmd[2] = rate; rmh.cmd_len = 3; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; } return 0; } static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) { struct pcxhr_rmh rmh; unsigned char reg; int err, rate; switch (clock_type) { case PCXHR_CLOCK_TYPE_WORD_CLOCK: reg = REG_STATUS_WORD_CLOCK; break; case PCXHR_CLOCK_TYPE_AES_SYNC: reg = REG_STATUS_AES_SYNC; break; case PCXHR_CLOCK_TYPE_AES_1: reg = REG_STATUS_AES_1; break; case PCXHR_CLOCK_TYPE_AES_2: reg = REG_STATUS_AES_2; break; case PCXHR_CLOCK_TYPE_AES_3: reg = REG_STATUS_AES_3; break; case PCXHR_CLOCK_TYPE_AES_4: reg = REG_STATUS_AES_4; break; default: return -EINVAL; } pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); rmh.cmd_len = 2; rmh.cmd[0] |= IO_NUM_REG_STATUS; if (mgr->last_reg_stat != reg) { rmh.cmd[1] = reg; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ mgr->last_reg_stat = reg; } rmh.cmd[1] = REG_STATUS_CURRENT; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; switch (rmh.stat[1] & 0x0f) { case REG_STATUS_SYNC_32000 : rate = 32000; break; case REG_STATUS_SYNC_44100 : rate = 44100; break; case REG_STATUS_SYNC_48000 : rate = 48000; break; case REG_STATUS_SYNC_64000 : rate = 64000; break; case REG_STATUS_SYNC_88200 : rate = 88200; break; case REG_STATUS_SYNC_96000 : rate = 96000; break; case REG_STATUS_SYNC_128000 : rate = 128000; break; case REG_STATUS_SYNC_176400 : rate = 176400; break; case REG_STATUS_SYNC_192000 : rate = 192000; break; default: rate = 0; } dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate); *sample_rate = rate; return 0; } int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) { if (mgr->is_hr_stereo) return hr222_get_external_clock(mgr, clock_type, sample_rate); else return pcxhr_sub_get_external_clock(mgr, clock_type, sample_rate); } /* * start or stop playback/capture substream */ static int pcxhr_set_stream_state(struct snd_pcxhr *chip, struct pcxhr_stream *stream) { int err; struct pcxhr_rmh rmh; int stream_mask, start; if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) start = 1; else { if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { dev_err(chip->card->dev, "%s CANNOT be stopped\n", __func__); return -EINVAL; } start = 0; } if (!stream->substream) return -EINVAL; stream->timer_abs_periods = 0; stream->timer_period_frag = 0; /* reset theoretical stream pos */ stream->timer_buf_periods = 0; stream->timer_is_synced = 0; stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number; pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, stream->pipe->first_audio, 0, stream_mask); chip = snd_pcm_substream_chip(stream->substream); err = pcxhr_send_msg(chip->mgr, &rmh); if (err) dev_err(chip->card->dev, "ERROR %s err=%x;\n", __func__, err); stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; return err; } #define HEADER_FMT_BASE_LIN 0xfed00000 #define HEADER_FMT_BASE_FLOAT 0xfad00000 #define HEADER_FMT_INTEL 0x00008000 #define HEADER_FMT_24BITS 0x00004000 #define HEADER_FMT_16BITS 0x00002000 #define HEADER_FMT_UPTO11 0x00000200 #define HEADER_FMT_UPTO32 0x00000100 #define HEADER_FMT_MONO 0x00000080 static int pcxhr_set_format(struct pcxhr_stream *stream) { int err, is_capture, sample_rate, stream_num; struct snd_pcxhr *chip; struct pcxhr_rmh rmh; unsigned int header; chip = snd_pcm_substream_chip(stream->substream); switch (stream->format) { case SNDRV_PCM_FORMAT_U8: header = HEADER_FMT_BASE_LIN; break; case SNDRV_PCM_FORMAT_S16_LE: header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL; break; case SNDRV_PCM_FORMAT_S16_BE: header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; break; case SNDRV_PCM_FORMAT_S24_3LE: header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL; break; case SNDRV_PCM_FORMAT_S24_3BE: header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; break; case SNDRV_PCM_FORMAT_FLOAT_LE: header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; break; default: dev_err(chip->card->dev, "error %s() : unknown format\n", __func__); return -EINVAL; } sample_rate = chip->mgr->sample_rate; if (sample_rate <= 32000 && sample_rate !=0) { if (sample_rate <= 11025) header |= HEADER_FMT_UPTO11; else header |= HEADER_FMT_UPTO32; } if (stream->channels == 1) header |= HEADER_FMT_MONO; is_capture = stream->pipe->is_capture; stream_num = is_capture ? 0 : stream->substream->number; pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); if (is_capture) { /* bug with old dsp versions: */ /* bit 12 also sets the format of the playback stream */ if (DSP_EXT_CMD_SET(chip->mgr)) rmh.cmd[0] |= 1<<10; else rmh.cmd[0] |= 1<<12; } rmh.cmd[1] = 0; rmh.cmd_len = 2; if (DSP_EXT_CMD_SET(chip->mgr)) { /* add channels and set bit 19 if channels>2 */ rmh.cmd[1] = stream->channels; if (!is_capture) { /* playback : add channel mask to command */ rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03; rmh.cmd_len = 3; } } rmh.cmd[rmh.cmd_len++] = header >> 8; rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16; err = pcxhr_send_msg(chip->mgr, &rmh); if (err) dev_err(chip->card->dev, "ERROR %s err=%x;\n", __func__, err); return err; } static int pcxhr_update_r_buffer(struct pcxhr_stream *stream) { int err, is_capture, stream_num; struct pcxhr_rmh rmh; struct snd_pcm_substream *subs = stream->substream; struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); stream_num = is_capture ? 0 : subs->number; dev_dbg(chip->card->dev, "%s(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", __func__, is_capture ? 'c' : 'p', chip->chip_idx, (void *)(long)subs->runtime->dma_addr, subs->runtime->dma_bytes, subs->number); pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); /* max buffer size is 2 MByte */ snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000); /* size in bits */ rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* most significant byte */ rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* this is a circular buffer */ rmh.cmd[2] |= 1<<19; /* least 3 significant bytes */ rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; rmh.cmd_len = 4; err = pcxhr_send_msg(chip->mgr, &rmh); if (err) dev_err(chip->card->dev, "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); return err; } #if 0 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count) { struct pcxhr_rmh rmh; int err; pcxhr_t *chip = snd_pcm_substream_chip(stream->substream); pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT); pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0, 1<<stream->pipe->first_audio); err = pcxhr_send_msg(chip->mgr, &rmh); if (err == 0) { *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24; *sample_count += (snd_pcm_uframes_t)rmh.stat[1]; } dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count); return err; } #endif static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream, struct pcxhr_pipe **pipe) { if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) { *pipe = stream->pipe; return 1; } return 0; } static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr) { int i, j, err; struct pcxhr_pipe *pipe; struct snd_pcxhr *chip; int capture_mask = 0; int playback_mask = 0; #ifdef CONFIG_SND_DEBUG_VERBOSE ktime_t start_time, stop_time, diff_time; start_time = ktime_get(); #endif mutex_lock(&mgr->setup_mutex); /* check the pipes concerned and build pipe_array */ for (i = 0; i < mgr->num_cards; i++) { chip = mgr->chip[i]; for (j = 0; j < chip->nb_streams_capt; j++) { if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe)) capture_mask |= (1 << pipe->first_audio); } for (j = 0; j < chip->nb_streams_play; j++) { if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { playback_mask |= (1 << pipe->first_audio); break; /* add only once, as all playback * streams of one chip use the same pipe */ } } } if (capture_mask == 0 && playback_mask == 0) { mutex_unlock(&mgr->setup_mutex); dev_err(&mgr->pci->dev, "%s : no pipes\n", __func__); return; } dev_dbg(&mgr->pci->dev, "%s : playback_mask=%x capture_mask=%x\n", __func__, playback_mask, capture_mask); /* synchronous stop of all the pipes concerned */ err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); if (err) { mutex_unlock(&mgr->setup_mutex); dev_err(&mgr->pci->dev, "%s : " "error stop pipes (P%x C%x)\n", __func__, playback_mask, capture_mask); return; } /* the dsp lost format and buffer info with the stop pipe */ for (i = 0; i < mgr->num_cards; i++) { struct pcxhr_stream *stream; chip = mgr->chip[i]; for (j = 0; j < chip->nb_streams_capt; j++) { stream = &chip->capture_stream[j]; if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { err = pcxhr_set_format(stream); err = pcxhr_update_r_buffer(stream); } } for (j = 0; j < chip->nb_streams_play; j++) { stream = &chip->playback_stream[j]; if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { err = pcxhr_set_format(stream); err = pcxhr_update_r_buffer(stream); } } } /* start all the streams */ for (i = 0; i < mgr->num_cards; i++) { struct pcxhr_stream *stream; chip = mgr->chip[i]; for (j = 0; j < chip->nb_streams_capt; j++) { stream = &chip->capture_stream[j]; if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) err = pcxhr_set_stream_state(chip, stream); } for (j = 0; j < chip->nb_streams_play; j++) { stream = &chip->playback_stream[j]; if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) err = pcxhr_set_stream_state(chip, stream); } } /* synchronous start of all the pipes concerned */ err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); if (err) { mutex_unlock(&mgr->setup_mutex); dev_err(&mgr->pci->dev, "%s : " "error start pipes (P%x C%x)\n", __func__, playback_mask, capture_mask); return; } /* put the streams into the running state now * (increment pointer by interrupt) */ mutex_lock(&mgr->lock); for ( i =0; i < mgr->num_cards; i++) { struct pcxhr_stream *stream; chip = mgr->chip[i]; for(j = 0; j < chip->nb_streams_capt; j++) { stream = &chip->capture_stream[j]; if(stream->status == PCXHR_STREAM_STATUS_STARTED) stream->status = PCXHR_STREAM_STATUS_RUNNING; } for (j = 0; j < chip->nb_streams_play; j++) { stream = &chip->playback_stream[j]; if (stream->status == PCXHR_STREAM_STATUS_STARTED) { /* playback will already have advanced ! */ stream->timer_period_frag += mgr->granularity; stream->status = PCXHR_STREAM_STATUS_RUNNING; } } } mutex_unlock(&mgr->lock); mutex_unlock(&mgr->setup_mutex); #ifdef CONFIG_SND_DEBUG_VERBOSE stop_time = ktime_get(); diff_time = ktime_sub(stop_time, start_time); dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n", (long)(ktime_to_ns(diff_time)), err); #endif } /* * trigger callback */ static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd) { struct pcxhr_stream *stream; struct snd_pcm_substream *s; struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); switch (cmd) { case SNDRV_PCM_TRIGGER_START: dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n"); if (snd_pcm_stream_linked(subs)) { snd_pcm_group_for_each_entry(s, subs) { if (snd_pcm_substream_chip(s) != chip) continue; stream = s->runtime->private_data; stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN; snd_pcm_trigger_done(s, subs); } pcxhr_start_linked_stream(chip->mgr); } else { stream = subs->runtime->private_data; dev_dbg(chip->card->dev, "Only one Substream %c %d\n", stream->pipe->is_capture ? 'C' : 'P', stream->pipe->first_audio); if (pcxhr_set_format(stream)) return -EINVAL; if (pcxhr_update_r_buffer(stream)) return -EINVAL; stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN; if (pcxhr_set_stream_state(chip, stream)) return -EINVAL; stream->status = PCXHR_STREAM_STATUS_RUNNING; } break; case SNDRV_PCM_TRIGGER_STOP: dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n"); snd_pcm_group_for_each_entry(s, subs) { stream = s->runtime->private_data; stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP; if (pcxhr_set_stream_state(chip, stream)) return -EINVAL; snd_pcm_trigger_done(s, subs); } break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* TODO */ default: return -EINVAL; } return 0; } static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start) { struct pcxhr_rmh rmh; int err; pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); if (start) { /* last dsp time invalid */ mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; rmh.cmd[0] |= mgr->granularity; } err = pcxhr_send_msg(mgr, &rmh); if (err < 0) dev_err(&mgr->pci->dev, "error %s err(%x)\n", __func__, err); return err; } /* * prepare callback for all pcms */ static int pcxhr_prepare(struct snd_pcm_substream *subs) { struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); struct pcxhr_mgr *mgr = chip->mgr; int err = 0; dev_dbg(chip->card->dev, "%s : period_size(%lx) periods(%x) buffer_size(%lx)\n", __func__, subs->runtime->period_size, subs->runtime->periods, subs->runtime->buffer_size); mutex_lock(&mgr->setup_mutex); do { /* only the first stream can choose the sample rate */ /* set the clock only once (first stream) */ if (mgr->sample_rate != subs->runtime->rate) { err = pcxhr_set_clock(mgr, subs->runtime->rate); if (err) break; if (mgr->sample_rate == 0) /* start the DSP-timer */ err = pcxhr_hardware_timer(mgr, 1); mgr->sample_rate = subs->runtime->rate; } } while(0); /* do only once (so we can use break instead of goto) */ mutex_unlock(&mgr->setup_mutex); return err; } /* * HW_PARAMS callback for all pcms */ static int pcxhr_hw_params(struct snd_pcm_substream *subs, struct snd_pcm_hw_params *hw) { struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); struct pcxhr_mgr *mgr = chip->mgr; struct pcxhr_stream *stream = subs->runtime->private_data; mutex_lock(&mgr->setup_mutex); /* set up channels */ stream->channels = params_channels(hw); /* set up format for the stream */ stream->format = params_format(hw); mutex_unlock(&mgr->setup_mutex); return 0; } /* * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max */ static const struct snd_pcm_hardware pcxhr_caps = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_FLOAT_LE), .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000), .rate_min = 8000, .rate_max = 192000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (32*1024), /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */ .period_bytes_min = (2*PCXHR_GRANULARITY), .period_bytes_max = (16*1024), .periods_min = 2, .periods_max = (32*1024/PCXHR_GRANULARITY), }; static int pcxhr_open(struct snd_pcm_substream *subs) { struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); struct pcxhr_mgr *mgr = chip->mgr; struct snd_pcm_runtime *runtime = subs->runtime; struct pcxhr_stream *stream; int err; mutex_lock(&mgr->setup_mutex); /* copy the struct snd_pcm_hardware struct */ runtime->hw = pcxhr_caps; if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) { dev_dbg(chip->card->dev, "%s playback chip%d subs%d\n", __func__, chip->chip_idx, subs->number); stream = &chip->playback_stream[subs->number]; } else { dev_dbg(chip->card->dev, "%s capture chip%d subs%d\n", __func__, chip->chip_idx, subs->number); if (mgr->mono_capture) runtime->hw.channels_max = 1; else runtime->hw.channels_min = 2; stream = &chip->capture_stream[subs->number]; } if (stream->status != PCXHR_STREAM_STATUS_FREE){ /* streams in use */ dev_err(chip->card->dev, "%s chip%d subs%d in use\n", __func__, chip->chip_idx, subs->number); mutex_unlock(&mgr->setup_mutex); return -EBUSY; } /* float format support is in some cases buggy on stereo cards */ if (mgr->is_hr_stereo) runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE; /* buffer-size should better be multiple of period-size */ err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (err < 0) { mutex_unlock(&mgr->setup_mutex); return err; } /* if a sample rate is already used or fixed by external clock, * the stream cannot change */ if (mgr->sample_rate) runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate; else { if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { int external_rate; if (pcxhr_get_external_clock(mgr, mgr->use_clock_type, &external_rate) || external_rate == 0) { /* cannot detect the external clock rate */ mutex_unlock(&mgr->setup_mutex); return -EBUSY; } runtime->hw.rate_min = external_rate; runtime->hw.rate_max = external_rate; } } stream->status = PCXHR_STREAM_STATUS_OPEN; stream->substream = subs; stream->channels = 0; /* not configured yet */ runtime->private_data = stream; /* better get a divisor of granularity values (96 or 192) */ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32); snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32); snd_pcm_set_sync(subs); mgr->ref_count_rate++; mutex_unlock(&mgr->setup_mutex); return 0; } static int pcxhr_close(struct snd_pcm_substream *subs) { struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); struct pcxhr_mgr *mgr = chip->mgr; struct pcxhr_stream *stream = subs->runtime->private_data; mutex_lock(&mgr->setup_mutex); dev_dbg(chip->card->dev, "%s chip%d subs%d\n", __func__, chip->chip_idx, subs->number); /* sample rate released */ if (--mgr->ref_count_rate == 0) { mgr->sample_rate = 0; /* the sample rate is no more locked */ pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ } stream->status = PCXHR_STREAM_STATUS_FREE; stream->substream = NULL; mutex_unlock(&mgr->setup_mutex); return 0; } static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs) { u_int32_t timer_period_frag; int timer_buf_periods; struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); struct snd_pcm_runtime *runtime = subs->runtime; struct pcxhr_stream *stream = runtime->private_data; mutex_lock(&chip->mgr->lock); /* get the period fragment and the nb of periods in the buffer */ timer_period_frag = stream->timer_period_frag; timer_buf_periods = stream->timer_buf_periods; mutex_unlock(&chip->mgr->lock); return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) + timer_period_frag); } static const struct snd_pcm_ops pcxhr_ops = { .open = pcxhr_open, .close = pcxhr_close, .prepare = pcxhr_prepare, .hw_params = pcxhr_hw_params, .trigger = pcxhr_trigger, .pointer = pcxhr_stream_pointer, }; /* */ int pcxhr_create_pcm(struct snd_pcxhr *chip) { int err; struct snd_pcm *pcm; char name[32]; snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx); err = snd_pcm_new(chip->card, name, 0, chip->nb_streams_play, chip->nb_streams_capt, &pcm); if (err < 0) { dev_err(chip->card->dev, "cannot create pcm %s\n", name); return err; } pcm->private_data = chip; if (chip->nb_streams_play) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops); if (chip->nb_streams_capt) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops); pcm->info_flags = 0; pcm->nonatomic = true; strcpy(pcm->name, name); snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->mgr->pci->dev, 32*1024, 32*1024); chip->pcm = pcm; return 0; } static int pcxhr_chip_free(struct snd_pcxhr *chip) { kfree(chip); return 0; } static int pcxhr_chip_dev_free(struct snd_device *device) { struct snd_pcxhr *chip = device->device_data; return pcxhr_chip_free(chip); } /* */ static int pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx) { int err; struct snd_pcxhr *chip; static const struct snd_device_ops ops = { .dev_free = pcxhr_chip_dev_free, }; chip = kzalloc(sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; chip->card = card; chip->chip_idx = idx; chip->mgr = mgr; card->sync_irq = mgr->irq; if (idx < mgr->playback_chips) /* stereo or mono streams */ chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS; if (idx < mgr->capture_chips) { if (mgr->mono_capture) chip->nb_streams_capt = 2; /* 2 mono streams */ else chip->nb_streams_capt = 1; /* or 1 stereo stream */ } err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); if (err < 0) { pcxhr_chip_free(chip); return err; } mgr->chip[idx] = chip; return 0; } /* proc interface */ static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_pcxhr *chip = entry->private_data; struct pcxhr_mgr *mgr = chip->mgr; snd_iprintf(buffer, "\n%s\n", mgr->name); /* stats available when embedded DSP is running */ if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { struct pcxhr_rmh rmh; short ver_maj = (mgr->dsp_version >> 16) & 0xff; short ver_min = (mgr->dsp_version >> 8) & 0xff; short ver_build = mgr->dsp_version & 0xff; snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING); snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build); if (mgr->board_has_analog) snd_iprintf(buffer, "analog io available\n"); else snd_iprintf(buffer, "digital only board\n"); /* calc cpu load of the dsp */ pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES); if( ! pcxhr_send_msg(mgr, &rmh) ) { int cur = rmh.stat[0]; int ref = rmh.stat[1]; if (ref > 0) { if (mgr->sample_rate_real != 0 && mgr->sample_rate_real != 48000) { ref = (ref * 48000) / mgr->sample_rate_real; if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ) ref *= 2; } cur = 100 - (100 * cur) / ref; snd_iprintf(buffer, "cpu load %d%%\n", cur); snd_iprintf(buffer, "buffer pool %d/%d\n", rmh.stat[2], rmh.stat[3]); } } snd_iprintf(buffer, "dma granularity : %d\n", mgr->granularity); snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err); snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", mgr->async_err_pipe_xrun); snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", mgr->async_err_stream_xrun); snd_iprintf(buffer, "dsp async last other error : %x\n", mgr->async_err_other_last); /* debug zone dsp */ rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS; rmh.cmd_len = 1; rmh.stat_len = PCXHR_SIZE_MAX_STATUS; rmh.dsp_stat = 0; rmh.cmd_idx = CMD_LAST_INDEX; if( ! pcxhr_send_msg(mgr, &rmh) ) { int i; if (rmh.stat_len > 8) rmh.stat_len = 8; for (i = 0; i < rmh.stat_len; i++) snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]); } } else snd_iprintf(buffer, "no firmware loaded\n"); snd_iprintf(buffer, "\n"); } static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_pcxhr *chip = entry->private_data; struct pcxhr_mgr *mgr = chip->mgr; static const char *textsHR22[3] = { "Internal", "AES Sync", "AES 1" }; static const char *textsPCXHR[7] = { "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" }; const char **texts; int max_clock; if (mgr->is_hr_stereo) { texts = textsHR22; max_clock = HR22_CLOCK_TYPE_MAX; } else { texts = textsPCXHR; max_clock = PCXHR_CLOCK_TYPE_MAX; } snd_iprintf(buffer, "\n%s\n", mgr->name); snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]); snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real); /* commands available when embedded DSP is running */ if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { int i, err, sample_rate; for (i = 1; i <= max_clock; i++) { err = pcxhr_get_external_clock(mgr, i, &sample_rate); if (err) break; snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate); } } else snd_iprintf(buffer, "no firmware loaded\n"); snd_iprintf(buffer, "\n"); } static void pcxhr_proc_gpio_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_pcxhr *chip = entry->private_data; struct pcxhr_mgr *mgr = chip->mgr; /* commands available when embedded DSP is running */ if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { /* gpio ports on stereo boards only available */ int value = 0; hr222_read_gpio(mgr, 1, &value); /* GPI */ snd_iprintf(buffer, "GPI: 0x%x\n", value); hr222_read_gpio(mgr, 0, &value); /* GP0 */ snd_iprintf(buffer, "GPO: 0x%x\n", value); } else snd_iprintf(buffer, "no firmware loaded\n"); snd_iprintf(buffer, "\n"); } static void pcxhr_proc_gpo_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_pcxhr *chip = entry->private_data; struct pcxhr_mgr *mgr = chip->mgr; char line[64]; int value; /* commands available when embedded DSP is running */ if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) return; while (!snd_info_get_line(buffer, line, sizeof(line))) { if (sscanf(line, "GPO: 0x%x", &value) != 1) continue; hr222_write_gpo(mgr, value); /* GP0 */ } } /* Access to the results of the CMD_GET_TIME_CODE RMH */ #define TIME_CODE_VALID_MASK 0x00800000 #define TIME_CODE_NEW_MASK 0x00400000 #define TIME_CODE_BACK_MASK 0x00200000 #define TIME_CODE_WAIT_MASK 0x00100000 /* Values for the CMD_MANAGE_SIGNAL RMH */ #define MANAGE_SIGNAL_TIME_CODE 0x01 #define MANAGE_SIGNAL_MIDI 0x02 /* linear time code read proc*/ static void pcxhr_proc_ltc(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_pcxhr *chip = entry->private_data; struct pcxhr_mgr *mgr = chip->mgr; struct pcxhr_rmh rmh; unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm; int err; /* commands available when embedded DSP is running */ if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) { snd_iprintf(buffer, "no firmware loaded\n"); return; } if (!mgr->capture_ltc) { pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL); rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE; err = pcxhr_send_msg(mgr, &rmh); if (err) { snd_iprintf(buffer, "ltc not activated (%d)\n", err); return; } if (mgr->is_hr_stereo) hr222_manage_timecode(mgr, 1); else pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE, REG_CONT_VALSMPTE, NULL); mgr->capture_ltc = 1; } pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE); err = pcxhr_send_msg(mgr, &rmh); if (err) { snd_iprintf(buffer, "ltc read error (err=%d)\n", err); return ; } ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf); ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf); ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf); ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf); snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n", ltcHrs, ltcMin, ltcSec, ltcFrm); snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff, rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff); /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n", rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/ if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) { snd_iprintf(buffer, "warning: linear timecode not valid\n"); } } static void pcxhr_proc_init(struct snd_pcxhr *chip) { snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info); snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync); /* gpio available on stereo sound cards only */ if (chip->mgr->is_hr_stereo) snd_card_rw_proc_new(chip->card, "gpio", chip, pcxhr_proc_gpio_read, pcxhr_proc_gpo_write); snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc); } /* end of proc interface */ /* * release all the cards assigned to a manager instance */ static int pcxhr_free(struct pcxhr_mgr *mgr) { unsigned int i; for (i = 0; i < mgr->num_cards; i++) { if (mgr->chip[i]) snd_card_free(mgr->chip[i]->card); } /* reset board if some firmware was loaded */ if(mgr->dsp_loaded) { pcxhr_reset_board(mgr); dev_dbg(&mgr->pci->dev, "reset pcxhr !\n"); } /* release irq */ if (mgr->irq >= 0) free_irq(mgr->irq, mgr); pci_release_regions(mgr->pci); /* free hostport purgebuffer */ if (mgr->hostport.area) { snd_dma_free_pages(&mgr->hostport); mgr->hostport.area = NULL; } kfree(mgr->prmh); pci_disable_device(mgr->pci); kfree(mgr); return 0; } /* * probe function - creates the card manager */ static int pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct pcxhr_mgr *mgr; unsigned int i; int err; size_t size; char *card_name; if (dev >= SNDRV_CARDS) return -ENODEV; if (! enable[dev]) { dev++; return -ENOENT; } /* enable PCI device */ err = pci_enable_device(pci); if (err < 0) return err; pci_set_master(pci); /* check if we can restrict PCI DMA transfers to 32 bits */ if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) { dev_err(&pci->dev, "architecture does not support 32bit PCI busmaster DMA\n"); pci_disable_device(pci); return -ENXIO; } /* alloc card manager */ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); if (! mgr) { pci_disable_device(pci); return -ENOMEM; } if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) { kfree(mgr); pci_disable_device(pci); return -ENODEV; } card_name = pcxhr_board_params[pci_id->driver_data].board_name; mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips; mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips; mgr->fw_file_set = pcxhr_board_params[pci_id->driver_data].fw_file_set; mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num; mgr->mono_capture = mono[dev]; mgr->is_hr_stereo = (mgr->playback_chips == 1); mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr); mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr); if (mgr->is_hr_stereo) mgr->granularity = PCXHR_GRANULARITY_HR22; else mgr->granularity = PCXHR_GRANULARITY; /* resource assignment */ err = pci_request_regions(pci, card_name); if (err < 0) { kfree(mgr); pci_disable_device(pci); return err; } for (i = 0; i < 3; i++) mgr->port[i] = pci_resource_start(pci, i); mgr->pci = pci; mgr->irq = -1; if (request_threaded_irq(pci->irq, pcxhr_interrupt, pcxhr_threaded_irq, IRQF_SHARED, KBUILD_MODNAME, mgr)) { dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq); pcxhr_free(mgr); return -EBUSY; } mgr->irq = pci->irq; snprintf(mgr->name, sizeof(mgr->name), "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); /* ISR lock */ mutex_init(&mgr->lock); mutex_init(&mgr->msg_lock); /* init setup mutex*/ mutex_init(&mgr->setup_mutex); mgr->prmh = kmalloc(sizeof(*mgr->prmh) + sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS), GFP_KERNEL); if (! mgr->prmh) { pcxhr_free(mgr); return -ENOMEM; } for (i=0; i < PCXHR_MAX_CARDS; i++) { struct snd_card *card; char tmpid[16]; int idx; if (i >= max(mgr->playback_chips, mgr->capture_chips)) break; mgr->num_cards++; if (index[dev] < 0) idx = index[dev]; else idx = index[dev] + i; snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i); err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE, 0, &card); if (err < 0) { dev_err(&pci->dev, "cannot allocate the card %d\n", i); pcxhr_free(mgr); return err; } strcpy(card->driver, DRIVER_NAME); snprintf(card->shortname, sizeof(card->shortname), "Digigram [PCM #%d]", i); snprintf(card->longname, sizeof(card->longname), "%s [PCM #%d]", mgr->name, i); err = pcxhr_create(mgr, card, i); if (err < 0) { snd_card_free(card); pcxhr_free(mgr); return err; } if (i == 0) /* init proc interface only for chip0 */ pcxhr_proc_init(mgr->chip[i]); err = snd_card_register(card); if (err < 0) { pcxhr_free(mgr); return err; } } /* create hostport purgebuffer */ size = PAGE_ALIGN(sizeof(struct pcxhr_hostport)); if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, &mgr->hostport) < 0) { pcxhr_free(mgr); return -ENOMEM; } /* init purgebuffer */ memset(mgr->hostport.area, 0, size); /* create a DSP loader */ err = pcxhr_setup_firmware(mgr); if (err < 0) { pcxhr_free(mgr); return err; } pci_set_drvdata(pci, mgr); dev++; return 0; } static void pcxhr_remove(struct pci_dev *pci) { pcxhr_free(pci_get_drvdata(pci)); } static struct pci_driver pcxhr_driver = { .name = KBUILD_MODNAME, .id_table = pcxhr_ids, .probe = pcxhr_probe, .remove = pcxhr_remove, }; module_pci_driver(pcxhr_driver);
linux-master
sound/pci/pcxhr/pcxhr.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Digigram pcxhr compatible soundcards * * hwdep device manager * * Copyright (c) 2004 by Digigram <[email protected]> */ #include <linux/interrupt.h> #include <linux/vmalloc.h> #include <linux/firmware.h> #include <linux/pci.h> #include <linux/module.h> #include <linux/io.h> #include <sound/core.h> #include <sound/hwdep.h> #include "pcxhr.h" #include "pcxhr_mixer.h" #include "pcxhr_hwdep.h" #include "pcxhr_core.h" #include "pcxhr_mix22.h" static int pcxhr_sub_init(struct pcxhr_mgr *mgr); /* * get basic information and init pcxhr card */ static int pcxhr_init_board(struct pcxhr_mgr *mgr) { int err; struct pcxhr_rmh rmh; int card_streams; /* calc the number of all streams used */ if (mgr->mono_capture) card_streams = mgr->capture_chips * 2; else card_streams = mgr->capture_chips; card_streams += mgr->playback_chips * PCXHR_PLAYBACK_STREAMS; /* enable interrupts */ pcxhr_enable_dsp(mgr); pcxhr_init_rmh(&rmh, CMD_SUPPORTED); err = pcxhr_send_msg(mgr, &rmh); if (err) return err; /* test 4, 8 or 12 phys out */ if ((rmh.stat[0] & MASK_FIRST_FIELD) < mgr->playback_chips * 2) return -EINVAL; /* test 4, 8 or 2 phys in */ if (((rmh.stat[0] >> (2 * FIELD_SIZE)) & MASK_FIRST_FIELD) < mgr->capture_chips * 2) return -EINVAL; /* test max nb substream per board */ if ((rmh.stat[1] & 0x5F) < card_streams) return -EINVAL; /* test max nb substream per pipe */ if (((rmh.stat[1] >> 7) & 0x5F) < PCXHR_PLAYBACK_STREAMS) return -EINVAL; dev_dbg(&mgr->pci->dev, "supported formats : playback=%x capture=%x\n", rmh.stat[2], rmh.stat[3]); pcxhr_init_rmh(&rmh, CMD_VERSION); /* firmware num for DSP */ rmh.cmd[0] |= mgr->firmware_num; /* transfer granularity in samples (should be multiple of 48) */ rmh.cmd[1] = (1<<23) + mgr->granularity; rmh.cmd_len = 2; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; dev_dbg(&mgr->pci->dev, "PCXHR DSP version is %d.%d.%d\n", (rmh.stat[0]>>16)&0xff, (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff); mgr->dsp_version = rmh.stat[0]; if (mgr->is_hr_stereo) err = hr222_sub_init(mgr); else err = pcxhr_sub_init(mgr); return err; } static int pcxhr_sub_init(struct pcxhr_mgr *mgr) { int err; struct pcxhr_rmh rmh; /* get options */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); rmh.cmd[0] |= IO_NUM_REG_STATUS; rmh.cmd[1] = REG_STATUS_OPTIONS; rmh.cmd_len = 2; err = pcxhr_send_msg(mgr, &rmh); if (err) return err; if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) == REG_STATUS_OPT_ANALOG_BOARD) mgr->board_has_analog = 1; /* analog addon board found */ /* unmute inputs */ err = pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS, REG_CONT_UNMUTE_INPUTS, NULL); if (err) return err; /* unmute outputs (a write to IO_NUM_REG_MUTE_OUT mutes!) */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; if (DSP_EXT_CMD_SET(mgr)) { rmh.cmd[1] = 1; /* unmute digital plugs */ rmh.cmd_len = 2; } err = pcxhr_send_msg(mgr, &rmh); return err; } void pcxhr_reset_board(struct pcxhr_mgr *mgr) { struct pcxhr_rmh rmh; if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { /* mute outputs */ if (!mgr->is_hr_stereo) { /* a read to IO_NUM_REG_MUTE_OUT register unmutes! */ pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; pcxhr_send_msg(mgr, &rmh); /* mute inputs */ pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS, 0, NULL); } /* stereo cards mute with reset of dsp */ } /* reset pcxhr dsp */ if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_EPRM_INDEX)) pcxhr_reset_dsp(mgr); /* reset second xilinx */ if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_XLX_COM_INDEX)) { pcxhr_reset_xilinx_com(mgr); mgr->dsp_loaded = 1; } return; } /* * allocate a playback/capture pipe (pcmp0/pcmc0) */ static int pcxhr_dsp_allocate_pipe(struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe, int is_capture, int pin) { int stream_count, audio_count; int err; struct pcxhr_rmh rmh; if (is_capture) { stream_count = 1; if (mgr->mono_capture) audio_count = 1; else audio_count = 2; } else { stream_count = PCXHR_PLAYBACK_STREAMS; audio_count = 2; /* always stereo */ } dev_dbg(&mgr->pci->dev, "snd_add_ref_pipe pin(%d) pcm%c0\n", pin, is_capture ? 'c' : 'p'); pipe->is_capture = is_capture; pipe->first_audio = pin; /* define pipe (P_PCM_ONLY_MASK (0x020000) is not necessary) */ pcxhr_init_rmh(&rmh, CMD_RES_PIPE); pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin, audio_count, stream_count); rmh.cmd[1] |= 0x020000; /* add P_PCM_ONLY_MASK */ if (DSP_EXT_CMD_SET(mgr)) { /* add channel mask to command */ rmh.cmd[rmh.cmd_len++] = (audio_count == 1) ? 0x01 : 0x03; } err = pcxhr_send_msg(mgr, &rmh); if (err < 0) { dev_err(&mgr->pci->dev, "error pipe allocation " "(CMD_RES_PIPE) err=%x!\n", err); return err; } pipe->status = PCXHR_PIPE_DEFINED; return 0; } /* * free playback/capture pipe (pcmp0/pcmc0) */ #if 0 static int pcxhr_dsp_free_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe) { struct pcxhr_rmh rmh; int capture_mask = 0; int playback_mask = 0; int err = 0; if (pipe->is_capture) capture_mask = (1 << pipe->first_audio); else playback_mask = (1 << pipe->first_audio); /* stop one pipe */ err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); if (err < 0) dev_err(&mgr->pci->dev, "error stopping pipe!\n"); /* release the pipe */ pcxhr_init_rmh(&rmh, CMD_FREE_PIPE); pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio, 0, 0); err = pcxhr_send_msg(mgr, &rmh); if (err < 0) dev_err(&mgr->pci->dev, "error pipe release " "(CMD_FREE_PIPE) err(%x)\n", err); pipe->status = PCXHR_PIPE_UNDEFINED; return err; } #endif static int pcxhr_config_pipes(struct pcxhr_mgr *mgr) { int err, i, j; struct snd_pcxhr *chip; struct pcxhr_pipe *pipe; /* allocate the pipes on the dsp */ for (i = 0; i < mgr->num_cards; i++) { chip = mgr->chip[i]; if (chip->nb_streams_play) { pipe = &chip->playback_pipe; err = pcxhr_dsp_allocate_pipe( mgr, pipe, 0, i*2); if (err) return err; for(j = 0; j < chip->nb_streams_play; j++) chip->playback_stream[j].pipe = pipe; } for (j = 0; j < chip->nb_streams_capt; j++) { pipe = &chip->capture_pipe[j]; err = pcxhr_dsp_allocate_pipe(mgr, pipe, 1, i*2 + j); if (err) return err; chip->capture_stream[j].pipe = pipe; } } return 0; } static int pcxhr_start_pipes(struct pcxhr_mgr *mgr) { int i, j; struct snd_pcxhr *chip; int playback_mask = 0; int capture_mask = 0; /* start all the pipes on the dsp */ for (i = 0; i < mgr->num_cards; i++) { chip = mgr->chip[i]; if (chip->nb_streams_play) playback_mask |= 1 << chip->playback_pipe.first_audio; for (j = 0; j < chip->nb_streams_capt; j++) capture_mask |= 1 << chip->capture_pipe[j].first_audio; } return pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); } static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index, const struct firmware *dsp) { int err, card_index; dev_dbg(&mgr->pci->dev, "loading dsp [%d] size = %zd\n", index, dsp->size); switch (index) { case PCXHR_FIRMWARE_XLX_INT_INDEX: pcxhr_reset_xilinx_com(mgr); return pcxhr_load_xilinx_binary(mgr, dsp, 0); case PCXHR_FIRMWARE_XLX_COM_INDEX: pcxhr_reset_xilinx_com(mgr); return pcxhr_load_xilinx_binary(mgr, dsp, 1); case PCXHR_FIRMWARE_DSP_EPRM_INDEX: pcxhr_reset_dsp(mgr); return pcxhr_load_eeprom_binary(mgr, dsp); case PCXHR_FIRMWARE_DSP_BOOT_INDEX: return pcxhr_load_boot_binary(mgr, dsp); case PCXHR_FIRMWARE_DSP_MAIN_INDEX: err = pcxhr_load_dsp_binary(mgr, dsp); if (err) return err; break; /* continue with first init */ default: dev_err(&mgr->pci->dev, "wrong file index\n"); return -EFAULT; } /* end of switch file index*/ /* first communication with embedded */ err = pcxhr_init_board(mgr); if (err < 0) { dev_err(&mgr->pci->dev, "pcxhr could not be set up\n"); return err; } err = pcxhr_config_pipes(mgr); if (err < 0) { dev_err(&mgr->pci->dev, "pcxhr pipes could not be set up\n"); return err; } /* create devices and mixer in accordance with HW options*/ for (card_index = 0; card_index < mgr->num_cards; card_index++) { struct snd_pcxhr *chip = mgr->chip[card_index]; err = pcxhr_create_pcm(chip); if (err < 0) return err; if (card_index == 0) { err = pcxhr_create_mixer(chip->mgr); if (err < 0) return err; } err = snd_card_register(chip->card); if (err < 0) return err; } err = pcxhr_start_pipes(mgr); if (err < 0) { dev_err(&mgr->pci->dev, "pcxhr pipes could not be started\n"); return err; } dev_dbg(&mgr->pci->dev, "pcxhr firmware downloaded and successfully set up\n"); return 0; } /* * fw loader entry */ int pcxhr_setup_firmware(struct pcxhr_mgr *mgr) { static const char * const fw_files[][5] = { [0] = { "xlxint.dat", "xlxc882hr.dat", "dspe882.e56", "dspb882hr.b56", "dspd882.d56" }, [1] = { "xlxint.dat", "xlxc882e.dat", "dspe882.e56", "dspb882e.b56", "dspd882.d56" }, [2] = { "xlxint.dat", "xlxc1222hr.dat", "dspe882.e56", "dspb1222hr.b56", "dspd1222.d56" }, [3] = { "xlxint.dat", "xlxc1222e.dat", "dspe882.e56", "dspb1222e.b56", "dspd1222.d56" }, [4] = { NULL, "xlxc222.dat", "dspe924.e56", "dspb924.b56", "dspd222.d56" }, [5] = { NULL, "xlxc924.dat", "dspe924.e56", "dspb924.b56", "dspd222.d56" }, }; char path[32]; const struct firmware *fw_entry; int i, err; int fw_set = mgr->fw_file_set; for (i = 0; i < 5; i++) { if (!fw_files[fw_set][i]) continue; sprintf(path, "pcxhr/%s", fw_files[fw_set][i]); if (request_firmware(&fw_entry, path, &mgr->pci->dev)) { dev_err(&mgr->pci->dev, "pcxhr: can't load firmware %s\n", path); return -ENOENT; } /* fake hwdep dsp record */ err = pcxhr_dsp_load(mgr, i, fw_entry); release_firmware(fw_entry); if (err < 0) return err; mgr->dsp_loaded |= 1 << i; } return 0; } MODULE_FIRMWARE("pcxhr/xlxint.dat"); MODULE_FIRMWARE("pcxhr/xlxc882hr.dat"); MODULE_FIRMWARE("pcxhr/xlxc882e.dat"); MODULE_FIRMWARE("pcxhr/dspe882.e56"); MODULE_FIRMWARE("pcxhr/dspb882hr.b56"); MODULE_FIRMWARE("pcxhr/dspb882e.b56"); MODULE_FIRMWARE("pcxhr/dspd882.d56"); MODULE_FIRMWARE("pcxhr/xlxc1222hr.dat"); MODULE_FIRMWARE("pcxhr/xlxc1222e.dat"); MODULE_FIRMWARE("pcxhr/dspb1222hr.b56"); MODULE_FIRMWARE("pcxhr/dspb1222e.b56"); MODULE_FIRMWARE("pcxhr/dspd1222.d56"); MODULE_FIRMWARE("pcxhr/xlxc222.dat"); MODULE_FIRMWARE("pcxhr/xlxc924.dat"); MODULE_FIRMWARE("pcxhr/dspe924.e56"); MODULE_FIRMWARE("pcxhr/dspb924.b56"); MODULE_FIRMWARE("pcxhr/dspd222.d56");
linux-master
sound/pci/pcxhr/pcxhr_hwdep.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for the Conexant Riptide Soundchip * * Copyright (c) 2004 Peter Gruber <[email protected]> */ /* History: - 02/15/2004 first release This Driver is based on the OSS Driver version from Linuxant (riptide-0.6lnxtbeta03111100) credits from the original files: MODULE NAME: cnxt_rt.h AUTHOR: K. Lazarev (Transcribed by KNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 02/1/2000 KNL MODULE NAME: int_mdl.c AUTHOR: Konstantin Lazarev (Transcribed by KNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 10/01/99 KNL MODULE NAME: riptide.h AUTHOR: O. Druzhinin (Transcribed by OLD) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 10/16/97 OLD MODULE NAME: Rp_Cmdif.cpp AUTHOR: O. Druzhinin (Transcribed by OLD) K. Lazarev (Transcribed by KNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Adopted from NT4 driver 6/22/99 OLD Ported to Linux 9/01/99 KNL MODULE NAME: rt_hw.c AUTHOR: O. Druzhinin (Transcribed by OLD) C. Lazarev (Transcribed by CNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 11/18/97 OLD Hardware functions for RipTide 11/24/97 CNL (ES1) are coded Hardware functions for RipTide 12/24/97 CNL (A0) are coded Hardware functions for RipTide 03/20/98 CNL (A1) are coded Boot loader is included 05/07/98 CNL Redesigned for WDM 07/27/98 CNL Redesigned for Linux 09/01/99 CNL MODULE NAME: rt_hw.h AUTHOR: C. Lazarev (Transcribed by CNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 11/18/97 CNL MODULE NAME: rt_mdl.c AUTHOR: Konstantin Lazarev (Transcribed by KNL) HISTORY: Major Revision Date By ----------------------------- -------- ----- Created 10/01/99 KNL MODULE NAME: mixer.h AUTHOR: K. Kenney HISTORY: Major Revision Date By ----------------------------- -------- ----- Created from MS W95 Sample 11/28/95 KRS RipTide 10/15/97 KRS Adopted for Windows NT driver 01/20/98 CNL */ #include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/wait.h> #include <linux/gameport.h> #include <linux/device.h> #include <linux/firmware.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/io.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/ac97_codec.h> #include <sound/mpu401.h> #include <sound/opl3.h> #include <sound/initval.h> #if IS_REACHABLE(CONFIG_GAMEPORT) #define SUPPORT_JOYSTICK 1 #endif MODULE_AUTHOR("Peter Gruber <[email protected]>"); MODULE_DESCRIPTION("riptide"); MODULE_LICENSE("GPL"); MODULE_FIRMWARE("riptide.hex"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; #ifdef SUPPORT_JOYSTICK static int joystick_port[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS - 1)] = 0x200 }; #endif static int mpu_port[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS - 1)] = 0x330 }; static int opl3_port[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS - 1)] = 0x388 }; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Riptide soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Riptide soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Riptide soundcard."); #ifdef SUPPORT_JOYSTICK module_param_hw_array(joystick_port, int, ioport, NULL, 0444); MODULE_PARM_DESC(joystick_port, "Joystick port # for Riptide soundcard."); #endif module_param_hw_array(mpu_port, int, ioport, NULL, 0444); MODULE_PARM_DESC(mpu_port, "MPU401 port # for Riptide driver."); module_param_hw_array(opl3_port, int, ioport, NULL, 0444); MODULE_PARM_DESC(opl3_port, "OPL3 port # for Riptide driver."); /* */ #define MPU401_HW_RIPTIDE MPU401_HW_MPU401 #define OPL3_HW_RIPTIDE OPL3_HW_OPL3 #define PCI_EXT_CapId 0x40 #define PCI_EXT_NextCapPrt 0x41 #define PCI_EXT_PWMC 0x42 #define PCI_EXT_PWSCR 0x44 #define PCI_EXT_Data00 0x46 #define PCI_EXT_PMSCR_BSE 0x47 #define PCI_EXT_SB_Base 0x48 #define PCI_EXT_FM_Base 0x4a #define PCI_EXT_MPU_Base 0x4C #define PCI_EXT_Game_Base 0x4E #define PCI_EXT_Legacy_Mask 0x50 #define PCI_EXT_AsicRev 0x52 #define PCI_EXT_Reserved3 0x53 #define LEGACY_ENABLE_ALL 0x8000 /* legacy device options */ #define LEGACY_ENABLE_SB 0x4000 #define LEGACY_ENABLE_FM 0x2000 #define LEGACY_ENABLE_MPU_INT 0x1000 #define LEGACY_ENABLE_MPU 0x0800 #define LEGACY_ENABLE_GAMEPORT 0x0400 #define MAX_WRITE_RETRY 10 /* cmd interface limits */ #define MAX_ERROR_COUNT 10 #define CMDIF_TIMEOUT 50000 #define RESET_TRIES 5 #define READ_PORT_ULONG(p) inl((unsigned long)&(p)) #define WRITE_PORT_ULONG(p,x) outl(x,(unsigned long)&(p)) #define READ_AUDIO_CONTROL(p) READ_PORT_ULONG(p->audio_control) #define WRITE_AUDIO_CONTROL(p,x) WRITE_PORT_ULONG(p->audio_control,x) #define UMASK_AUDIO_CONTROL(p,x) WRITE_PORT_ULONG(p->audio_control,READ_PORT_ULONG(p->audio_control)|x) #define MASK_AUDIO_CONTROL(p,x) WRITE_PORT_ULONG(p->audio_control,READ_PORT_ULONG(p->audio_control)&x) #define READ_AUDIO_STATUS(p) READ_PORT_ULONG(p->audio_status) #define SET_GRESET(p) UMASK_AUDIO_CONTROL(p,0x0001) /* global reset switch */ #define UNSET_GRESET(p) MASK_AUDIO_CONTROL(p,~0x0001) #define SET_AIE(p) UMASK_AUDIO_CONTROL(p,0x0004) /* interrupt enable */ #define UNSET_AIE(p) MASK_AUDIO_CONTROL(p,~0x0004) #define SET_AIACK(p) UMASK_AUDIO_CONTROL(p,0x0008) /* interrupt acknowledge */ #define UNSET_AIACKT(p) MASKAUDIO_CONTROL(p,~0x0008) #define SET_ECMDAE(p) UMASK_AUDIO_CONTROL(p,0x0010) #define UNSET_ECMDAE(p) MASK_AUDIO_CONTROL(p,~0x0010) #define SET_ECMDBE(p) UMASK_AUDIO_CONTROL(p,0x0020) #define UNSET_ECMDBE(p) MASK_AUDIO_CONTROL(p,~0x0020) #define SET_EDATAF(p) UMASK_AUDIO_CONTROL(p,0x0040) #define UNSET_EDATAF(p) MASK_AUDIO_CONTROL(p,~0x0040) #define SET_EDATBF(p) UMASK_AUDIO_CONTROL(p,0x0080) #define UNSET_EDATBF(p) MASK_AUDIO_CONTROL(p,~0x0080) #define SET_ESBIRQON(p) UMASK_AUDIO_CONTROL(p,0x0100) #define UNSET_ESBIRQON(p) MASK_AUDIO_CONTROL(p,~0x0100) #define SET_EMPUIRQ(p) UMASK_AUDIO_CONTROL(p,0x0200) #define UNSET_EMPUIRQ(p) MASK_AUDIO_CONTROL(p,~0x0200) #define IS_CMDE(a) (READ_PORT_ULONG(a->stat)&0x1) /* cmd empty */ #define IS_DATF(a) (READ_PORT_ULONG(a->stat)&0x2) /* data filled */ #define IS_READY(p) (READ_AUDIO_STATUS(p)&0x0001) #define IS_DLREADY(p) (READ_AUDIO_STATUS(p)&0x0002) #define IS_DLERR(p) (READ_AUDIO_STATUS(p)&0x0004) #define IS_GERR(p) (READ_AUDIO_STATUS(p)&0x0008) /* error ! */ #define IS_CMDAEIRQ(p) (READ_AUDIO_STATUS(p)&0x0010) #define IS_CMDBEIRQ(p) (READ_AUDIO_STATUS(p)&0x0020) #define IS_DATAFIRQ(p) (READ_AUDIO_STATUS(p)&0x0040) #define IS_DATBFIRQ(p) (READ_AUDIO_STATUS(p)&0x0080) #define IS_EOBIRQ(p) (READ_AUDIO_STATUS(p)&0x0100) /* interrupt status */ #define IS_EOSIRQ(p) (READ_AUDIO_STATUS(p)&0x0200) #define IS_EOCIRQ(p) (READ_AUDIO_STATUS(p)&0x0400) #define IS_UNSLIRQ(p) (READ_AUDIO_STATUS(p)&0x0800) #define IS_SBIRQ(p) (READ_AUDIO_STATUS(p)&0x1000) #define IS_MPUIRQ(p) (READ_AUDIO_STATUS(p)&0x2000) #define RESP 0x00000001 /* command flags */ #define PARM 0x00000002 #define CMDA 0x00000004 #define CMDB 0x00000008 #define NILL 0x00000000 #define LONG0(a) ((u32)a) /* shifts and masks */ #define BYTE0(a) (LONG0(a)&0xff) #define BYTE1(a) (BYTE0(a)<<8) #define BYTE2(a) (BYTE0(a)<<16) #define BYTE3(a) (BYTE0(a)<<24) #define WORD0(a) (LONG0(a)&0xffff) #define WORD1(a) (WORD0(a)<<8) #define WORD2(a) (WORD0(a)<<16) #define TRINIB0(a) (LONG0(a)&0xffffff) #define TRINIB1(a) (TRINIB0(a)<<8) #define RET(a) ((union cmdret *)(a)) #define SEND_GETV(p,b) sendcmd(p,RESP,GETV,0,RET(b)) /* get version */ #define SEND_GETC(p,b,c) sendcmd(p,PARM|RESP,GETC,c,RET(b)) #define SEND_GUNS(p,b) sendcmd(p,RESP,GUNS,0,RET(b)) #define SEND_SCID(p,b) sendcmd(p,RESP,SCID,0,RET(b)) #define SEND_RMEM(p,b,c,d) sendcmd(p,PARM|RESP,RMEM|BYTE1(b),LONG0(c),RET(d)) /* memory access for firmware write */ #define SEND_SMEM(p,b,c) sendcmd(p,PARM,SMEM|BYTE1(b),LONG0(c),RET(0)) /* memory access for firmware write */ #define SEND_WMEM(p,b,c) sendcmd(p,PARM,WMEM|BYTE1(b),LONG0(c),RET(0)) /* memory access for firmware write */ #define SEND_SDTM(p,b,c) sendcmd(p,PARM|RESP,SDTM|TRINIB1(b),0,RET(c)) /* memory access for firmware write */ #define SEND_GOTO(p,b) sendcmd(p,PARM,GOTO,LONG0(b),RET(0)) /* memory access for firmware write */ #define SEND_SETDPLL(p) sendcmd(p,0,ARM_SETDPLL,0,RET(0)) #define SEND_SSTR(p,b,c) sendcmd(p,PARM,SSTR|BYTE3(b),LONG0(c),RET(0)) /* start stream */ #define SEND_PSTR(p,b) sendcmd(p,PARM,PSTR,BYTE3(b),RET(0)) /* pause stream */ #define SEND_KSTR(p,b) sendcmd(p,PARM,KSTR,BYTE3(b),RET(0)) /* stop stream */ #define SEND_KDMA(p) sendcmd(p,0,KDMA,0,RET(0)) /* stop all dma */ #define SEND_GPOS(p,b,c,d) sendcmd(p,PARM|RESP,GPOS,BYTE3(c)|BYTE2(b),RET(d)) /* get position in dma */ #define SEND_SETF(p,b,c,d,e,f,g) sendcmd(p,PARM,SETF|WORD1(b)|BYTE3(c),d|BYTE1(e)|BYTE2(f)|BYTE3(g),RET(0)) /* set sample format at mixer */ #define SEND_GSTS(p,b,c,d) sendcmd(p,PARM|RESP,GSTS,BYTE3(c)|BYTE2(b),RET(d)) #define SEND_NGPOS(p,b,c,d) sendcmd(p,PARM|RESP,NGPOS,BYTE3(c)|BYTE2(b),RET(d)) #define SEND_PSEL(p,b,c) sendcmd(p,PARM,PSEL,BYTE2(b)|BYTE3(c),RET(0)) /* activate lbus path */ #define SEND_PCLR(p,b,c) sendcmd(p,PARM,PCLR,BYTE2(b)|BYTE3(c),RET(0)) /* deactivate lbus path */ #define SEND_PLST(p,b) sendcmd(p,PARM,PLST,BYTE3(b),RET(0)) #define SEND_RSSV(p,b,c,d) sendcmd(p,PARM|RESP,RSSV,BYTE2(b)|BYTE3(c),RET(d)) #define SEND_LSEL(p,b,c,d,e,f,g,h) sendcmd(p,PARM,LSEL|BYTE1(b)|BYTE2(c)|BYTE3(d),BYTE0(e)|BYTE1(f)|BYTE2(g)|BYTE3(h),RET(0)) /* select paths for internal connections */ #define SEND_SSRC(p,b,c,d,e) sendcmd(p,PARM,SSRC|BYTE1(b)|WORD2(c),WORD0(d)|WORD2(e),RET(0)) /* configure source */ #define SEND_SLST(p,b) sendcmd(p,PARM,SLST,BYTE3(b),RET(0)) #define SEND_RSRC(p,b,c) sendcmd(p,RESP,RSRC|BYTE1(b),0,RET(c)) /* read source config */ #define SEND_SSRB(p,b,c) sendcmd(p,PARM,SSRB|BYTE1(b),WORD2(c),RET(0)) #define SEND_SDGV(p,b,c,d,e) sendcmd(p,PARM,SDGV|BYTE2(b)|BYTE3(c),WORD0(d)|WORD2(e),RET(0)) /* set digital mixer */ #define SEND_RDGV(p,b,c,d) sendcmd(p,PARM|RESP,RDGV|BYTE2(b)|BYTE3(c),0,RET(d)) /* read digital mixer */ #define SEND_DLST(p,b) sendcmd(p,PARM,DLST,BYTE3(b),RET(0)) #define SEND_SACR(p,b,c) sendcmd(p,PARM,SACR,WORD0(b)|WORD2(c),RET(0)) /* set AC97 register */ #define SEND_RACR(p,b,c) sendcmd(p,PARM|RESP,RACR,WORD2(b),RET(c)) /* get AC97 register */ #define SEND_ALST(p,b) sendcmd(p,PARM,ALST,BYTE3(b),RET(0)) #define SEND_TXAC(p,b,c,d,e,f) sendcmd(p,PARM,TXAC|BYTE1(b)|WORD2(c),WORD0(d)|BYTE2(e)|BYTE3(f),RET(0)) #define SEND_RXAC(p,b,c,d) sendcmd(p,PARM|RESP,RXAC,BYTE2(b)|BYTE3(c),RET(d)) #define SEND_SI2S(p,b) sendcmd(p,PARM,SI2S,WORD2(b),RET(0)) #define EOB_STATUS 0x80000000 /* status flags : block boundary */ #define EOS_STATUS 0x40000000 /* : stoppped */ #define EOC_STATUS 0x20000000 /* : stream end */ #define ERR_STATUS 0x10000000 #define EMPTY_STATUS 0x08000000 #define IEOB_ENABLE 0x1 /* enable interrupts for status notification above */ #define IEOS_ENABLE 0x2 #define IEOC_ENABLE 0x4 #define RDONCE 0x8 #define DESC_MAX_MASK 0xff #define ST_PLAY 0x1 /* stream states */ #define ST_STOP 0x2 #define ST_PAUSE 0x4 #define I2S_INTDEC 3 /* config for I2S link */ #define I2S_MERGER 0 #define I2S_SPLITTER 0 #define I2S_MIXER 7 #define I2S_RATE 44100 #define MODEM_INTDEC 4 /* config for modem link */ #define MODEM_MERGER 3 #define MODEM_SPLITTER 0 #define MODEM_MIXER 11 #define FM_INTDEC 3 /* config for FM/OPL3 link */ #define FM_MERGER 0 #define FM_SPLITTER 0 #define FM_MIXER 9 #define SPLIT_PATH 0x80 /* path splitting flag */ enum FIRMWARE { DATA_REC = 0, EXT_END_OF_FILE, EXT_SEG_ADDR_REC, EXT_GOTO_CMD_REC, EXT_LIN_ADDR_REC, }; enum CMDS { GETV = 0x00, GETC, GUNS, SCID, RMEM = 0x10, SMEM, WMEM, SDTM, GOTO, SSTR = 0x20, PSTR, KSTR, KDMA, GPOS, SETF, GSTS, NGPOS, PSEL = 0x30, PCLR, PLST, RSSV, LSEL, SSRC = 0x40, SLST, RSRC, SSRB, SDGV = 0x50, RDGV, DLST, SACR = 0x60, RACR, ALST, TXAC, RXAC, SI2S = 0x70, ARM_SETDPLL = 0x72, }; enum E1SOURCE { ARM2LBUS_FIFO0 = 0, ARM2LBUS_FIFO1, ARM2LBUS_FIFO2, ARM2LBUS_FIFO3, ARM2LBUS_FIFO4, ARM2LBUS_FIFO5, ARM2LBUS_FIFO6, ARM2LBUS_FIFO7, ARM2LBUS_FIFO8, ARM2LBUS_FIFO9, ARM2LBUS_FIFO10, ARM2LBUS_FIFO11, ARM2LBUS_FIFO12, ARM2LBUS_FIFO13, ARM2LBUS_FIFO14, ARM2LBUS_FIFO15, INTER0_OUT, INTER1_OUT, INTER2_OUT, INTER3_OUT, INTER4_OUT, INTERM0_OUT, INTERM1_OUT, INTERM2_OUT, INTERM3_OUT, INTERM4_OUT, INTERM5_OUT, INTERM6_OUT, DECIMM0_OUT, DECIMM1_OUT, DECIMM2_OUT, DECIMM3_OUT, DECIM0_OUT, SR3_4_OUT, OPL3_SAMPLE, ASRC0, ASRC1, ACLNK2PADC, ACLNK2MODEM0RX, ACLNK2MIC, ACLNK2MODEM1RX, ACLNK2HNDMIC, DIGITAL_MIXER_OUT0, GAINFUNC0_OUT, GAINFUNC1_OUT, GAINFUNC2_OUT, GAINFUNC3_OUT, GAINFUNC4_OUT, SOFTMODEMTX, SPLITTER0_OUTL, SPLITTER0_OUTR, SPLITTER1_OUTL, SPLITTER1_OUTR, SPLITTER2_OUTL, SPLITTER2_OUTR, SPLITTER3_OUTL, SPLITTER3_OUTR, MERGER0_OUT, MERGER1_OUT, MERGER2_OUT, MERGER3_OUT, ARM2LBUS_FIFO_DIRECT, NO_OUT }; enum E2SINK { LBUS2ARM_FIFO0 = 0, LBUS2ARM_FIFO1, LBUS2ARM_FIFO2, LBUS2ARM_FIFO3, LBUS2ARM_FIFO4, LBUS2ARM_FIFO5, LBUS2ARM_FIFO6, LBUS2ARM_FIFO7, INTER0_IN, INTER1_IN, INTER2_IN, INTER3_IN, INTER4_IN, INTERM0_IN, INTERM1_IN, INTERM2_IN, INTERM3_IN, INTERM4_IN, INTERM5_IN, INTERM6_IN, DECIMM0_IN, DECIMM1_IN, DECIMM2_IN, DECIMM3_IN, DECIM0_IN, SR3_4_IN, PDAC2ACLNK, MODEM0TX2ACLNK, MODEM1TX2ACLNK, HNDSPK2ACLNK, DIGITAL_MIXER_IN0, DIGITAL_MIXER_IN1, DIGITAL_MIXER_IN2, DIGITAL_MIXER_IN3, DIGITAL_MIXER_IN4, DIGITAL_MIXER_IN5, DIGITAL_MIXER_IN6, DIGITAL_MIXER_IN7, DIGITAL_MIXER_IN8, DIGITAL_MIXER_IN9, DIGITAL_MIXER_IN10, DIGITAL_MIXER_IN11, GAINFUNC0_IN, GAINFUNC1_IN, GAINFUNC2_IN, GAINFUNC3_IN, GAINFUNC4_IN, SOFTMODEMRX, SPLITTER0_IN, SPLITTER1_IN, SPLITTER2_IN, SPLITTER3_IN, MERGER0_INL, MERGER0_INR, MERGER1_INL, MERGER1_INR, MERGER2_INL, MERGER2_INR, MERGER3_INL, MERGER3_INR, E2SINK_MAX }; enum LBUS_SINK { LS_SRC_INTERPOLATOR = 0, LS_SRC_INTERPOLATORM, LS_SRC_DECIMATOR, LS_SRC_DECIMATORM, LS_MIXER_IN, LS_MIXER_GAIN_FUNCTION, LS_SRC_SPLITTER, LS_SRC_MERGER, LS_NONE1, LS_NONE2, }; enum RT_CHANNEL_IDS { M0TX = 0, M1TX, TAMTX, HSSPKR, PDAC, DSNDTX0, DSNDTX1, DSNDTX2, DSNDTX3, DSNDTX4, DSNDTX5, DSNDTX6, DSNDTX7, WVSTRTX, COP3DTX, SPARE, M0RX, HSMIC, M1RX, CLEANRX, MICADC, PADC, COPRX1, COPRX2, CHANNEL_ID_COUNTER }; enum { SB_CMD = 0, MODEM_CMD, I2S_CMD0, I2S_CMD1, FM_CMD, MAX_CMD }; struct lbuspath { const unsigned char *noconv; const unsigned char *stereo; const unsigned char *mono; }; struct cmdport { u32 data1; /* cmd,param */ u32 data2; /* param */ u32 stat; /* status */ u32 pad[5]; }; struct riptideport { u32 audio_control; /* status registers */ u32 audio_status; u32 pad[2]; struct cmdport port[2]; /* command ports */ }; struct cmdif { struct riptideport *hwport; spinlock_t lock; unsigned int cmdcnt; /* cmd statistics */ unsigned int cmdtime; unsigned int cmdtimemax; unsigned int cmdtimemin; unsigned int errcnt; int is_reset; }; struct riptide_firmware { u16 ASIC; u16 CODEC; u16 AUXDSP; u16 PROG; }; union cmdret { u8 retbytes[8]; u16 retwords[4]; u32 retlongs[2]; }; union firmware_version { union cmdret ret; struct riptide_firmware firmware; }; #define get_pcmhwdev(substream) (struct pcmhw *)(substream->runtime->private_data) #define PLAYBACK_SUBSTREAMS 3 struct snd_riptide { struct snd_card *card; struct pci_dev *pci; const struct firmware *fw_entry; struct cmdif *cif; struct snd_pcm *pcm; struct snd_pcm *pcm_i2s; struct snd_rawmidi *rmidi; struct snd_opl3 *opl3; struct snd_ac97 *ac97; struct snd_ac97_bus *ac97_bus; struct snd_pcm_substream *playback_substream[PLAYBACK_SUBSTREAMS]; struct snd_pcm_substream *capture_substream; int openstreams; int irq; unsigned long port; unsigned short mpuaddr; unsigned short opladdr; #ifdef SUPPORT_JOYSTICK unsigned short gameaddr; #endif struct resource *res_port; unsigned short device_id; union firmware_version firmware; spinlock_t lock; struct snd_info_entry *proc_entry; unsigned long received_irqs; unsigned long handled_irqs; #ifdef CONFIG_PM_SLEEP int in_suspend; #endif }; struct sgd { /* scatter gather desriptor */ __le32 dwNextLink; __le32 dwSegPtrPhys; __le32 dwSegLen; __le32 dwStat_Ctl; }; struct pcmhw { /* pcm descriptor */ struct lbuspath paths; const unsigned char *lbuspath; unsigned char source; unsigned char intdec[2]; unsigned char mixer; unsigned char id; unsigned char state; unsigned int rate; unsigned int channels; snd_pcm_format_t format; struct snd_dma_buffer sgdlist; struct sgd *sgdbuf; unsigned int size; unsigned int pages; unsigned int oldpos; unsigned int pointer; }; #define CMDRET_ZERO (union cmdret){{(u32)0, (u32) 0}} static int sendcmd(struct cmdif *cif, u32 flags, u32 cmd, u32 parm, union cmdret *ret); static int getsourcesink(struct cmdif *cif, unsigned char source, unsigned char sink, unsigned char *a, unsigned char *b); static int snd_riptide_initialize(struct snd_riptide *chip); static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip); /* */ static const struct pci_device_id snd_riptide_ids[] = { { PCI_DEVICE(0x127a, 0x4310) }, { PCI_DEVICE(0x127a, 0x4320) }, { PCI_DEVICE(0x127a, 0x4330) }, { PCI_DEVICE(0x127a, 0x4340) }, {0,}, }; #ifdef SUPPORT_JOYSTICK static const struct pci_device_id snd_riptide_joystick_ids[] = { { PCI_DEVICE(0x127a, 0x4312) }, { PCI_DEVICE(0x127a, 0x4322) }, { PCI_DEVICE(0x127a, 0x4332) }, { PCI_DEVICE(0x127a, 0x4342) }, {0,}, }; #endif MODULE_DEVICE_TABLE(pci, snd_riptide_ids); /* */ static const unsigned char lbusin2out[E2SINK_MAX + 1][2] = { {NO_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {NO_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {NO_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {NO_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {INTER0_OUT, LS_SRC_INTERPOLATOR}, {INTER1_OUT, LS_SRC_INTERPOLATOR}, {INTER2_OUT, LS_SRC_INTERPOLATOR}, {INTER3_OUT, LS_SRC_INTERPOLATOR}, {INTER4_OUT, LS_SRC_INTERPOLATOR}, {INTERM0_OUT, LS_SRC_INTERPOLATORM}, {INTERM1_OUT, LS_SRC_INTERPOLATORM}, {INTERM2_OUT, LS_SRC_INTERPOLATORM}, {INTERM3_OUT, LS_SRC_INTERPOLATORM}, {INTERM4_OUT, LS_SRC_INTERPOLATORM}, {INTERM5_OUT, LS_SRC_INTERPOLATORM}, {INTERM6_OUT, LS_SRC_INTERPOLATORM}, {DECIMM0_OUT, LS_SRC_DECIMATORM}, {DECIMM1_OUT, LS_SRC_DECIMATORM}, {DECIMM2_OUT, LS_SRC_DECIMATORM}, {DECIMM3_OUT, LS_SRC_DECIMATORM}, {DECIM0_OUT, LS_SRC_DECIMATOR}, {SR3_4_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {NO_OUT, LS_NONE1}, {NO_OUT, LS_NONE2}, {NO_OUT, LS_NONE1}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {DIGITAL_MIXER_OUT0, LS_MIXER_IN}, {GAINFUNC0_OUT, LS_MIXER_GAIN_FUNCTION}, {GAINFUNC1_OUT, LS_MIXER_GAIN_FUNCTION}, {GAINFUNC2_OUT, LS_MIXER_GAIN_FUNCTION}, {GAINFUNC3_OUT, LS_MIXER_GAIN_FUNCTION}, {GAINFUNC4_OUT, LS_MIXER_GAIN_FUNCTION}, {SOFTMODEMTX, LS_NONE1}, {SPLITTER0_OUTL, LS_SRC_SPLITTER}, {SPLITTER1_OUTL, LS_SRC_SPLITTER}, {SPLITTER2_OUTL, LS_SRC_SPLITTER}, {SPLITTER3_OUTL, LS_SRC_SPLITTER}, {MERGER0_OUT, LS_SRC_MERGER}, {MERGER0_OUT, LS_SRC_MERGER}, {MERGER1_OUT, LS_SRC_MERGER}, {MERGER1_OUT, LS_SRC_MERGER}, {MERGER2_OUT, LS_SRC_MERGER}, {MERGER2_OUT, LS_SRC_MERGER}, {MERGER3_OUT, LS_SRC_MERGER}, {MERGER3_OUT, LS_SRC_MERGER}, {NO_OUT, LS_NONE2}, }; static const unsigned char lbus_play_opl3[] = { DIGITAL_MIXER_IN0 + FM_MIXER, 0xff }; static const unsigned char lbus_play_modem[] = { DIGITAL_MIXER_IN0 + MODEM_MIXER, 0xff }; static const unsigned char lbus_play_i2s[] = { INTER0_IN + I2S_INTDEC, DIGITAL_MIXER_IN0 + I2S_MIXER, 0xff }; static const unsigned char lbus_play_out[] = { PDAC2ACLNK, 0xff }; static const unsigned char lbus_play_outhp[] = { HNDSPK2ACLNK, 0xff }; static const unsigned char lbus_play_noconv1[] = { DIGITAL_MIXER_IN0, 0xff }; static const unsigned char lbus_play_stereo1[] = { INTER0_IN, DIGITAL_MIXER_IN0, 0xff }; static const unsigned char lbus_play_mono1[] = { INTERM0_IN, DIGITAL_MIXER_IN0, 0xff }; static const unsigned char lbus_play_noconv2[] = { DIGITAL_MIXER_IN1, 0xff }; static const unsigned char lbus_play_stereo2[] = { INTER1_IN, DIGITAL_MIXER_IN1, 0xff }; static const unsigned char lbus_play_mono2[] = { INTERM1_IN, DIGITAL_MIXER_IN1, 0xff }; static const unsigned char lbus_play_noconv3[] = { DIGITAL_MIXER_IN2, 0xff }; static const unsigned char lbus_play_stereo3[] = { INTER2_IN, DIGITAL_MIXER_IN2, 0xff }; static const unsigned char lbus_play_mono3[] = { INTERM2_IN, DIGITAL_MIXER_IN2, 0xff }; static const unsigned char lbus_rec_noconv1[] = { LBUS2ARM_FIFO5, 0xff }; static const unsigned char lbus_rec_stereo1[] = { DECIM0_IN, LBUS2ARM_FIFO5, 0xff }; static const unsigned char lbus_rec_mono1[] = { DECIMM3_IN, LBUS2ARM_FIFO5, 0xff }; static const unsigned char play_ids[] = { 4, 1, 2, }; static const unsigned char play_sources[] = { ARM2LBUS_FIFO4, ARM2LBUS_FIFO1, ARM2LBUS_FIFO2, }; static const struct lbuspath lbus_play_paths[] = { { .noconv = lbus_play_noconv1, .stereo = lbus_play_stereo1, .mono = lbus_play_mono1, }, { .noconv = lbus_play_noconv2, .stereo = lbus_play_stereo2, .mono = lbus_play_mono2, }, { .noconv = lbus_play_noconv3, .stereo = lbus_play_stereo3, .mono = lbus_play_mono3, }, }; static const struct lbuspath lbus_rec_path = { .noconv = lbus_rec_noconv1, .stereo = lbus_rec_stereo1, .mono = lbus_rec_mono1, }; #define FIRMWARE_VERSIONS 1 static union firmware_version firmware_versions[] = { { .firmware = { .ASIC = 3, .CODEC = 2, .AUXDSP = 3, .PROG = 773, }, }, }; static u32 atoh(const unsigned char *in, unsigned int len) { u32 sum = 0; unsigned int mult = 1; unsigned char c; while (len) { int value; c = in[len - 1]; value = hex_to_bin(c); if (value >= 0) sum += mult * value; mult *= 16; --len; } return sum; } static int senddata(struct cmdif *cif, const unsigned char *in, u32 offset) { u32 addr; u32 data; u32 i; const unsigned char *p; i = atoh(&in[1], 2); addr = offset + atoh(&in[3], 4); if (SEND_SMEM(cif, 0, addr) != 0) return -EACCES; p = in + 9; while (i) { data = atoh(p, 8); if (SEND_WMEM(cif, 2, ((data & 0x0f0f0f0f) << 4) | ((data & 0xf0f0f0f0) >> 4))) return -EACCES; i -= 4; p += 8; } return 0; } static int loadfirmware(struct cmdif *cif, const unsigned char *img, unsigned int size) { const unsigned char *in; u32 laddr, saddr, t, val; int err = 0; laddr = saddr = 0; while (size > 0 && err == 0) { in = img; if (in[0] == ':') { t = atoh(&in[7], 2); switch (t) { case DATA_REC: err = senddata(cif, in, laddr + saddr); break; case EXT_SEG_ADDR_REC: saddr = atoh(&in[9], 4) << 4; break; case EXT_LIN_ADDR_REC: laddr = atoh(&in[9], 4) << 16; break; case EXT_GOTO_CMD_REC: val = atoh(&in[9], 8); if (SEND_GOTO(cif, val) != 0) err = -EACCES; break; case EXT_END_OF_FILE: size = 0; break; default: break; } while (size > 0) { size--; if (*img++ == '\n') break; } } } snd_printdd("load firmware return %d\n", err); return err; } static void alloclbuspath(struct cmdif *cif, unsigned char source, const unsigned char *path, unsigned char *mixer, unsigned char *s) { while (*path != 0xff) { unsigned char sink, type; sink = *path & (~SPLIT_PATH); if (sink != E2SINK_MAX) { snd_printdd("alloc path 0x%x->0x%x\n", source, sink); SEND_PSEL(cif, source, sink); source = lbusin2out[sink][0]; type = lbusin2out[sink][1]; if (type == LS_MIXER_IN) { if (mixer) *mixer = sink - DIGITAL_MIXER_IN0; } if (type == LS_SRC_DECIMATORM || type == LS_SRC_DECIMATOR || type == LS_SRC_INTERPOLATORM || type == LS_SRC_INTERPOLATOR) { if (s) { if (s[0] != 0xff) s[1] = sink; else s[0] = sink; } } } if (*path++ & SPLIT_PATH) { const unsigned char *npath = path; while (*npath != 0xff) npath++; alloclbuspath(cif, source + 1, ++npath, mixer, s); } } } static void freelbuspath(struct cmdif *cif, unsigned char source, const unsigned char *path) { while (*path != 0xff) { unsigned char sink; sink = *path & (~SPLIT_PATH); if (sink != E2SINK_MAX) { snd_printdd("free path 0x%x->0x%x\n", source, sink); SEND_PCLR(cif, source, sink); source = lbusin2out[sink][0]; } if (*path++ & SPLIT_PATH) { const unsigned char *npath = path; while (*npath != 0xff) npath++; freelbuspath(cif, source + 1, ++npath); } } } static int writearm(struct cmdif *cif, u32 addr, u32 data, u32 mask) { union cmdret rptr = CMDRET_ZERO; unsigned int i = MAX_WRITE_RETRY; int flag = 1; SEND_RMEM(cif, 0x02, addr, &rptr); rptr.retlongs[0] &= (~mask); while (--i) { SEND_SMEM(cif, 0x01, addr); SEND_WMEM(cif, 0x02, (rptr.retlongs[0] | data)); SEND_RMEM(cif, 0x02, addr, &rptr); if ((rptr.retlongs[0] & data) == data) { flag = 0; break; } else rptr.retlongs[0] &= ~mask; } snd_printdd("send arm 0x%x 0x%x 0x%x return %d\n", addr, data, mask, flag); return flag; } static int sendcmd(struct cmdif *cif, u32 flags, u32 cmd, u32 parm, union cmdret *ret) { int i, j; int err; unsigned int time = 0; unsigned long irqflags; struct riptideport *hwport; struct cmdport *cmdport = NULL; if (snd_BUG_ON(!cif)) return -EINVAL; hwport = cif->hwport; if (cif->errcnt > MAX_ERROR_COUNT) { if (cif->is_reset) { snd_printk(KERN_ERR "Riptide: Too many failed cmds, reinitializing\n"); if (riptide_reset(cif, NULL) == 0) { cif->errcnt = 0; return -EIO; } } snd_printk(KERN_ERR "Riptide: Initialization failed.\n"); return -EINVAL; } if (ret) { ret->retlongs[0] = 0; ret->retlongs[1] = 0; } i = 0; spin_lock_irqsave(&cif->lock, irqflags); while (i++ < CMDIF_TIMEOUT && !IS_READY(cif->hwport)) udelay(10); if (i > CMDIF_TIMEOUT) { err = -EBUSY; goto errout; } err = 0; for (j = 0, time = 0; time < CMDIF_TIMEOUT; j++, time += 2) { cmdport = &(hwport->port[j % 2]); if (IS_DATF(cmdport)) { /* free pending data */ READ_PORT_ULONG(cmdport->data1); READ_PORT_ULONG(cmdport->data2); } if (IS_CMDE(cmdport)) { if (flags & PARM) /* put data */ WRITE_PORT_ULONG(cmdport->data2, parm); WRITE_PORT_ULONG(cmdport->data1, cmd); /* write cmd */ if ((flags & RESP) && ret) { while (!IS_DATF(cmdport) && time < CMDIF_TIMEOUT) { udelay(10); time++; } if (time < CMDIF_TIMEOUT) { /* read response */ ret->retlongs[0] = READ_PORT_ULONG(cmdport->data1); ret->retlongs[1] = READ_PORT_ULONG(cmdport->data2); } else { err = -ENOSYS; goto errout; } } break; } udelay(20); } if (time == CMDIF_TIMEOUT) { err = -ENODATA; goto errout; } spin_unlock_irqrestore(&cif->lock, irqflags); cif->cmdcnt++; /* update command statistics */ cif->cmdtime += time; if (time > cif->cmdtimemax) cif->cmdtimemax = time; if (time < cif->cmdtimemin) cif->cmdtimemin = time; if ((cif->cmdcnt) % 1000 == 0) snd_printdd ("send cmd %d time: %d mintime: %d maxtime %d err: %d\n", cif->cmdcnt, cif->cmdtime, cif->cmdtimemin, cif->cmdtimemax, cif->errcnt); return 0; errout: cif->errcnt++; spin_unlock_irqrestore(&cif->lock, irqflags); snd_printdd ("send cmd %d hw: 0x%x flag: 0x%x cmd: 0x%x parm: 0x%x ret: 0x%x 0x%x CMDE: %d DATF: %d failed %d\n", cif->cmdcnt, (int)((void *)&(cmdport->stat) - (void *)hwport), flags, cmd, parm, ret ? ret->retlongs[0] : 0, ret ? ret->retlongs[1] : 0, IS_CMDE(cmdport), IS_DATF(cmdport), err); return err; } static int setmixer(struct cmdif *cif, short num, unsigned short rval, unsigned short lval) { union cmdret rptr = CMDRET_ZERO; int i = 0; snd_printdd("sent mixer %d: 0x%x 0x%x\n", num, rval, lval); do { SEND_SDGV(cif, num, num, rval, lval); SEND_RDGV(cif, num, num, &rptr); if (rptr.retwords[0] == lval && rptr.retwords[1] == rval) return 0; } while (i++ < MAX_WRITE_RETRY); snd_printdd("sent mixer failed\n"); return -EIO; } static int getpaths(struct cmdif *cif, unsigned char *o) { unsigned char src[E2SINK_MAX]; unsigned char sink[E2SINK_MAX]; int i, j = 0; for (i = 0; i < E2SINK_MAX; i++) { getsourcesink(cif, i, i, &src[i], &sink[i]); if (sink[i] < E2SINK_MAX) { o[j++] = sink[i]; o[j++] = i; } } return j; } static int getsourcesink(struct cmdif *cif, unsigned char source, unsigned char sink, unsigned char *a, unsigned char *b) { union cmdret rptr = CMDRET_ZERO; if (SEND_RSSV(cif, source, sink, &rptr) && SEND_RSSV(cif, source, sink, &rptr)) return -EIO; *a = rptr.retbytes[0]; *b = rptr.retbytes[1]; snd_printdd("getsourcesink 0x%x 0x%x\n", *a, *b); return 0; } static int getsamplerate(struct cmdif *cif, unsigned char *intdec, unsigned int *rate) { unsigned char *s; unsigned int p[2] = { 0, 0 }; int i; union cmdret rptr = CMDRET_ZERO; s = intdec; for (i = 0; i < 2; i++) { if (*s != 0xff) { if (SEND_RSRC(cif, *s, &rptr) && SEND_RSRC(cif, *s, &rptr)) return -EIO; p[i] += rptr.retwords[1]; p[i] *= rptr.retwords[2]; p[i] += rptr.retwords[3]; p[i] /= 65536; } s++; } if (p[0]) { if (p[1] != p[0]) snd_printdd("rates differ %d %d\n", p[0], p[1]); *rate = (unsigned int)p[0]; } else *rate = (unsigned int)p[1]; snd_printdd("getsampleformat %d %d %d\n", intdec[0], intdec[1], *rate); return 0; } static int setsampleformat(struct cmdif *cif, unsigned char mixer, unsigned char id, unsigned char channels, snd_pcm_format_t format) { unsigned char w, ch, sig, order; snd_printdd ("setsampleformat mixer: %d id: %d channels: %d format: %d\n", mixer, id, channels, format); ch = channels == 1; w = snd_pcm_format_width(format) == 8; sig = snd_pcm_format_unsigned(format) != 0; order = snd_pcm_format_big_endian(format) != 0; if (SEND_SETF(cif, mixer, w, ch, order, sig, id) && SEND_SETF(cif, mixer, w, ch, order, sig, id)) { snd_printdd("setsampleformat failed\n"); return -EIO; } return 0; } static int setsamplerate(struct cmdif *cif, unsigned char *intdec, unsigned int rate) { u32 D, M, N; union cmdret rptr = CMDRET_ZERO; int i; snd_printdd("setsamplerate intdec: %d,%d rate: %d\n", intdec[0], intdec[1], rate); D = 48000; M = ((rate == 48000) ? 47999 : rate) * 65536; N = M % D; M /= D; for (i = 0; i < 2; i++) { if (*intdec != 0xff) { do { SEND_SSRC(cif, *intdec, D, M, N); SEND_RSRC(cif, *intdec, &rptr); } while (rptr.retwords[1] != D && rptr.retwords[2] != M && rptr.retwords[3] != N && i++ < MAX_WRITE_RETRY); if (i > MAX_WRITE_RETRY) { snd_printdd("sent samplerate %d: %d failed\n", *intdec, rate); return -EIO; } } intdec++; } return 0; } static int getmixer(struct cmdif *cif, short num, unsigned short *rval, unsigned short *lval) { union cmdret rptr = CMDRET_ZERO; if (SEND_RDGV(cif, num, num, &rptr) && SEND_RDGV(cif, num, num, &rptr)) return -EIO; *rval = rptr.retwords[0]; *lval = rptr.retwords[1]; snd_printdd("got mixer %d: 0x%x 0x%x\n", num, *rval, *lval); return 0; } static irqreturn_t riptide_handleirq(int irq, void *dev_id) { struct snd_riptide *chip = dev_id; struct cmdif *cif = chip->cif; struct snd_pcm_substream *substream[PLAYBACK_SUBSTREAMS + 1]; struct snd_pcm_runtime *runtime; struct pcmhw *data = NULL; unsigned int pos, period_bytes; struct sgd *c; int i, j; unsigned int flag; if (!cif) return IRQ_HANDLED; for (i = 0; i < PLAYBACK_SUBSTREAMS; i++) substream[i] = chip->playback_substream[i]; substream[i] = chip->capture_substream; for (i = 0; i < PLAYBACK_SUBSTREAMS + 1; i++) { if (!substream[i]) continue; runtime = substream[i]->runtime; if (!runtime) continue; data = runtime->private_data; if (!data) continue; if (data->state != ST_STOP) { pos = 0; for (j = 0; j < data->pages; j++) { c = &data->sgdbuf[j]; flag = le32_to_cpu(c->dwStat_Ctl); if (flag & EOB_STATUS) pos += le32_to_cpu(c->dwSegLen); if (flag & EOC_STATUS) pos += le32_to_cpu(c->dwSegLen); if ((flag & EOS_STATUS) && (data->state == ST_PLAY)) { data->state = ST_STOP; snd_printk(KERN_ERR "Riptide: DMA stopped unexpectedly\n"); } c->dwStat_Ctl = cpu_to_le32(flag & ~(EOS_STATUS | EOB_STATUS | EOC_STATUS)); } data->pointer += pos; pos += data->oldpos; if (data->state != ST_STOP) { period_bytes = frames_to_bytes(runtime, runtime->period_size); snd_printdd ("interrupt 0x%x after 0x%lx of 0x%lx frames in period\n", READ_AUDIO_STATUS(cif->hwport), bytes_to_frames(runtime, pos), runtime->period_size); j = 0; if (pos >= period_bytes) { j++; while (pos >= period_bytes) pos -= period_bytes; } data->oldpos = pos; if (j > 0) snd_pcm_period_elapsed(substream[i]); } } } return IRQ_HANDLED; } #ifdef CONFIG_PM_SLEEP static int riptide_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_riptide *chip = card->private_data; chip->in_suspend = 1; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); snd_ac97_suspend(chip->ac97); return 0; } static int riptide_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct snd_riptide *chip = card->private_data; snd_riptide_initialize(chip); snd_ac97_resume(chip->ac97); snd_power_change_state(card, SNDRV_CTL_POWER_D0); chip->in_suspend = 0; return 0; } static SIMPLE_DEV_PM_OPS(riptide_pm, riptide_suspend, riptide_resume); #define RIPTIDE_PM_OPS &riptide_pm #else #define RIPTIDE_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ static int try_to_load_firmware(struct cmdif *cif, struct snd_riptide *chip) { union firmware_version firmware = { .ret = CMDRET_ZERO }; int i, timeout, err; for (i = 0; i < 2; i++) { WRITE_PORT_ULONG(cif->hwport->port[i].data1, 0); WRITE_PORT_ULONG(cif->hwport->port[i].data2, 0); } SET_GRESET(cif->hwport); udelay(100); UNSET_GRESET(cif->hwport); udelay(100); for (timeout = 100000; --timeout; udelay(10)) { if (IS_READY(cif->hwport) && !IS_GERR(cif->hwport)) break; } if (!timeout) { snd_printk(KERN_ERR "Riptide: device not ready, audio status: 0x%x " "ready: %d gerr: %d\n", READ_AUDIO_STATUS(cif->hwport), IS_READY(cif->hwport), IS_GERR(cif->hwport)); return -EIO; } else { snd_printdd ("Riptide: audio status: 0x%x ready: %d gerr: %d\n", READ_AUDIO_STATUS(cif->hwport), IS_READY(cif->hwport), IS_GERR(cif->hwport)); } SEND_GETV(cif, &firmware.ret); snd_printdd("Firmware version: ASIC: %d CODEC %d AUXDSP %d PROG %d\n", firmware.firmware.ASIC, firmware.firmware.CODEC, firmware.firmware.AUXDSP, firmware.firmware.PROG); if (!chip) return 1; for (i = 0; i < FIRMWARE_VERSIONS; i++) { if (!memcmp(&firmware_versions[i], &firmware, sizeof(firmware))) return 1; /* OK */ } snd_printdd("Writing Firmware\n"); if (!chip->fw_entry) { err = request_firmware(&chip->fw_entry, "riptide.hex", &chip->pci->dev); if (err) { snd_printk(KERN_ERR "Riptide: Firmware not available %d\n", err); return -EIO; } } err = loadfirmware(cif, chip->fw_entry->data, chip->fw_entry->size); if (err) { snd_printk(KERN_ERR "Riptide: Could not load firmware %d\n", err); return err; } chip->firmware = firmware; return 1; /* OK */ } static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip) { union cmdret rptr = CMDRET_ZERO; int err, tries; if (!cif) return -EINVAL; cif->cmdcnt = 0; cif->cmdtime = 0; cif->cmdtimemax = 0; cif->cmdtimemin = 0xffffffff; cif->errcnt = 0; cif->is_reset = 0; tries = RESET_TRIES; do { err = try_to_load_firmware(cif, chip); if (err < 0) return err; } while (!err && --tries); SEND_SACR(cif, 0, AC97_RESET); SEND_RACR(cif, AC97_RESET, &rptr); snd_printdd("AC97: 0x%x 0x%x\n", rptr.retlongs[0], rptr.retlongs[1]); SEND_PLST(cif, 0); SEND_SLST(cif, 0); SEND_DLST(cif, 0); SEND_ALST(cif, 0); SEND_KDMA(cif); writearm(cif, 0x301F8, 1, 1); writearm(cif, 0x301F4, 1, 1); SEND_LSEL(cif, MODEM_CMD, 0, 0, MODEM_INTDEC, MODEM_MERGER, MODEM_SPLITTER, MODEM_MIXER); setmixer(cif, MODEM_MIXER, 0x7fff, 0x7fff); alloclbuspath(cif, ARM2LBUS_FIFO13, lbus_play_modem, NULL, NULL); SEND_LSEL(cif, FM_CMD, 0, 0, FM_INTDEC, FM_MERGER, FM_SPLITTER, FM_MIXER); setmixer(cif, FM_MIXER, 0x7fff, 0x7fff); writearm(cif, 0x30648 + FM_MIXER * 4, 0x01, 0x00000005); writearm(cif, 0x301A8, 0x02, 0x00000002); writearm(cif, 0x30264, 0x08, 0xffffffff); alloclbuspath(cif, OPL3_SAMPLE, lbus_play_opl3, NULL, NULL); SEND_SSRC(cif, I2S_INTDEC, 48000, ((u32) I2S_RATE * 65536) / 48000, ((u32) I2S_RATE * 65536) % 48000); SEND_LSEL(cif, I2S_CMD0, 0, 0, I2S_INTDEC, I2S_MERGER, I2S_SPLITTER, I2S_MIXER); SEND_SI2S(cif, 1); alloclbuspath(cif, ARM2LBUS_FIFO0, lbus_play_i2s, NULL, NULL); alloclbuspath(cif, DIGITAL_MIXER_OUT0, lbus_play_out, NULL, NULL); alloclbuspath(cif, DIGITAL_MIXER_OUT0, lbus_play_outhp, NULL, NULL); SET_AIACK(cif->hwport); SET_AIE(cif->hwport); SET_AIACK(cif->hwport); cif->is_reset = 1; return 0; } static const struct snd_pcm_hardware snd_riptide_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE, .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, .rate_min = 5500, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (64 * 1024), .period_bytes_min = PAGE_SIZE >> 1, .period_bytes_max = PAGE_SIZE << 8, .periods_min = 2, .periods_max = 64, .fifo_size = 0, }; static const struct snd_pcm_hardware snd_riptide_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE, .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, .rate_min = 5500, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = (64 * 1024), .period_bytes_min = PAGE_SIZE >> 1, .period_bytes_max = PAGE_SIZE << 3, .periods_min = 2, .periods_max = 64, .fifo_size = 0, }; static snd_pcm_uframes_t snd_riptide_pointer(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct pcmhw *data = get_pcmhwdev(substream); struct cmdif *cif = chip->cif; union cmdret rptr = CMDRET_ZERO; snd_pcm_uframes_t ret; SEND_GPOS(cif, 0, data->id, &rptr); if (data->size && runtime->period_size) { snd_printdd ("pointer stream %d position 0x%x(0x%x in buffer) bytes 0x%lx(0x%lx in period) frames\n", data->id, rptr.retlongs[1], rptr.retlongs[1] % data->size, bytes_to_frames(runtime, rptr.retlongs[1]), bytes_to_frames(runtime, rptr.retlongs[1]) % runtime->period_size); if (rptr.retlongs[1] > data->pointer) ret = bytes_to_frames(runtime, rptr.retlongs[1] % data->size); else ret = bytes_to_frames(runtime, data->pointer % data->size); } else { snd_printdd("stream not started or strange parms (%d %ld)\n", data->size, runtime->period_size); ret = bytes_to_frames(runtime, 0); } return ret; } static int snd_riptide_trigger(struct snd_pcm_substream *substream, int cmd) { int i, j; struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct pcmhw *data = get_pcmhwdev(substream); struct cmdif *cif = chip->cif; union cmdret rptr = CMDRET_ZERO; spin_lock(&chip->lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: if (!(data->state & ST_PLAY)) { SEND_SSTR(cif, data->id, data->sgdlist.addr); SET_AIE(cif->hwport); data->state = ST_PLAY; if (data->mixer != 0xff) setmixer(cif, data->mixer, 0x7fff, 0x7fff); chip->openstreams++; data->oldpos = 0; data->pointer = 0; } break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: if (data->mixer != 0xff) setmixer(cif, data->mixer, 0, 0); setmixer(cif, data->mixer, 0, 0); SEND_KSTR(cif, data->id); data->state = ST_STOP; chip->openstreams--; j = 0; do { i = rptr.retlongs[1]; SEND_GPOS(cif, 0, data->id, &rptr); udelay(1); } while (i != rptr.retlongs[1] && j++ < MAX_WRITE_RETRY); if (j > MAX_WRITE_RETRY) snd_printk(KERN_ERR "Riptide: Could not stop stream!"); break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (!(data->state & ST_PAUSE)) { SEND_PSTR(cif, data->id); data->state |= ST_PAUSE; chip->openstreams--; } break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (data->state & ST_PAUSE) { SEND_SSTR(cif, data->id, data->sgdlist.addr); data->state &= ~ST_PAUSE; chip->openstreams++; } break; default: spin_unlock(&chip->lock); return -EINVAL; } spin_unlock(&chip->lock); return 0; } static int snd_riptide_prepare(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct pcmhw *data = get_pcmhwdev(substream); struct cmdif *cif = chip->cif; const unsigned char *lbuspath = NULL; unsigned int rate, channels; int err = 0; snd_pcm_format_t format; if (snd_BUG_ON(!cif || !data)) return -EINVAL; snd_printdd("prepare id %d ch: %d f:0x%x r:%d\n", data->id, runtime->channels, runtime->format, runtime->rate); spin_lock_irq(&chip->lock); channels = runtime->channels; format = runtime->format; rate = runtime->rate; switch (channels) { case 1: if (rate == 48000 && format == SNDRV_PCM_FORMAT_S16_LE) lbuspath = data->paths.noconv; else lbuspath = data->paths.mono; break; case 2: if (rate == 48000 && format == SNDRV_PCM_FORMAT_S16_LE) lbuspath = data->paths.noconv; else lbuspath = data->paths.stereo; break; } snd_printdd("use sgdlist at 0x%p\n", data->sgdlist.area); if (data->sgdlist.area) { unsigned int i, j, size, pages, f, pt, period; struct sgd *c, *p = NULL; size = frames_to_bytes(runtime, runtime->buffer_size); period = frames_to_bytes(runtime, runtime->period_size); f = PAGE_SIZE; while ((size + (f >> 1) - 1) <= (f << 7) && (f << 1) > period) f = f >> 1; pages = DIV_ROUND_UP(size, f); data->size = size; data->pages = pages; snd_printdd ("create sgd size: 0x%x pages %d of size 0x%x for period 0x%x\n", size, pages, f, period); pt = 0; j = 0; for (i = 0; i < pages; i++) { unsigned int ofs, addr; c = &data->sgdbuf[i]; if (p) p->dwNextLink = cpu_to_le32(data->sgdlist.addr + (i * sizeof(struct sgd))); c->dwNextLink = cpu_to_le32(data->sgdlist.addr); ofs = j << PAGE_SHIFT; addr = snd_pcm_sgbuf_get_addr(substream, ofs) + pt; c->dwSegPtrPhys = cpu_to_le32(addr); pt = (pt + f) % PAGE_SIZE; if (pt == 0) j++; c->dwSegLen = cpu_to_le32(f); c->dwStat_Ctl = cpu_to_le32(IEOB_ENABLE | IEOS_ENABLE | IEOC_ENABLE); p = c; size -= f; } data->sgdbuf[i].dwSegLen = cpu_to_le32(size); } if (lbuspath && lbuspath != data->lbuspath) { if (data->lbuspath) freelbuspath(cif, data->source, data->lbuspath); alloclbuspath(cif, data->source, lbuspath, &data->mixer, data->intdec); data->lbuspath = lbuspath; data->rate = 0; } if (data->rate != rate || data->format != format || data->channels != channels) { data->rate = rate; data->format = format; data->channels = channels; if (setsampleformat (cif, data->mixer, data->id, channels, format) || setsamplerate(cif, data->intdec, rate)) err = -EIO; } spin_unlock_irq(&chip->lock); return err; } static int snd_riptide_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct pcmhw *data = get_pcmhwdev(substream); struct snd_dma_buffer *sgdlist = &data->sgdlist; int err; snd_printdd("hw params id %d (sgdlist: 0x%p 0x%lx %d)\n", data->id, sgdlist->area, (unsigned long)sgdlist->addr, (int)sgdlist->bytes); if (sgdlist->area) snd_dma_free_pages(sgdlist); err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, sizeof(struct sgd) * (DESC_MAX_MASK + 1), sgdlist); if (err < 0) { snd_printk(KERN_ERR "Riptide: failed to alloc %d dma bytes\n", (int)sizeof(struct sgd) * (DESC_MAX_MASK + 1)); return err; } data->sgdbuf = (struct sgd *)sgdlist->area; return 0; } static int snd_riptide_hw_free(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct pcmhw *data = get_pcmhwdev(substream); struct cmdif *cif = chip->cif; if (cif && data) { if (data->lbuspath) freelbuspath(cif, data->source, data->lbuspath); data->lbuspath = NULL; data->source = 0xff; data->intdec[0] = 0xff; data->intdec[1] = 0xff; if (data->sgdlist.area) { snd_dma_free_pages(&data->sgdlist); data->sgdlist.area = NULL; } } return 0; } static int snd_riptide_playback_open(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct pcmhw *data; int sub_num = substream->number; chip->playback_substream[sub_num] = substream; runtime->hw = snd_riptide_playback; data = kzalloc(sizeof(struct pcmhw), GFP_KERNEL); if (data == NULL) return -ENOMEM; data->paths = lbus_play_paths[sub_num]; data->id = play_ids[sub_num]; data->source = play_sources[sub_num]; data->intdec[0] = 0xff; data->intdec[1] = 0xff; data->state = ST_STOP; runtime->private_data = data; return snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); } static int snd_riptide_capture_open(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct pcmhw *data; chip->capture_substream = substream; runtime->hw = snd_riptide_capture; data = kzalloc(sizeof(struct pcmhw), GFP_KERNEL); if (data == NULL) return -ENOMEM; data->paths = lbus_rec_path; data->id = PADC; data->source = ACLNK2PADC; data->intdec[0] = 0xff; data->intdec[1] = 0xff; data->state = ST_STOP; runtime->private_data = data; return snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); } static int snd_riptide_playback_close(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct pcmhw *data = get_pcmhwdev(substream); int sub_num = substream->number; substream->runtime->private_data = NULL; chip->playback_substream[sub_num] = NULL; kfree(data); return 0; } static int snd_riptide_capture_close(struct snd_pcm_substream *substream) { struct snd_riptide *chip = snd_pcm_substream_chip(substream); struct pcmhw *data = get_pcmhwdev(substream); substream->runtime->private_data = NULL; chip->capture_substream = NULL; kfree(data); return 0; } static const struct snd_pcm_ops snd_riptide_playback_ops = { .open = snd_riptide_playback_open, .close = snd_riptide_playback_close, .hw_params = snd_riptide_hw_params, .hw_free = snd_riptide_hw_free, .prepare = snd_riptide_prepare, .trigger = snd_riptide_trigger, .pointer = snd_riptide_pointer, }; static const struct snd_pcm_ops snd_riptide_capture_ops = { .open = snd_riptide_capture_open, .close = snd_riptide_capture_close, .hw_params = snd_riptide_hw_params, .hw_free = snd_riptide_hw_free, .prepare = snd_riptide_prepare, .trigger = snd_riptide_trigger, .pointer = snd_riptide_pointer, }; static int snd_riptide_pcm(struct snd_riptide *chip, int device) { struct snd_pcm *pcm; int err; err = snd_pcm_new(chip->card, "RIPTIDE", device, PLAYBACK_SUBSTREAMS, 1, &pcm); if (err < 0) return err; snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_riptide_playback_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_riptide_capture_ops); pcm->private_data = chip; pcm->info_flags = 0; strcpy(pcm->name, "RIPTIDE"); chip->pcm = pcm; snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG, &chip->pci->dev, 64 * 1024, 128 * 1024); return 0; } static irqreturn_t snd_riptide_interrupt(int irq, void *dev_id) { struct snd_riptide *chip = dev_id; struct cmdif *cif = chip->cif; irqreturn_t ret = IRQ_HANDLED; if (cif) { chip->received_irqs++; if (IS_EOBIRQ(cif->hwport) || IS_EOSIRQ(cif->hwport) || IS_EOCIRQ(cif->hwport)) { chip->handled_irqs++; ret = IRQ_WAKE_THREAD; } if (chip->rmidi && IS_MPUIRQ(cif->hwport)) { chip->handled_irqs++; snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); } SET_AIACK(cif->hwport); } return ret; } static void snd_riptide_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct snd_riptide *chip = ac97->private_data; struct cmdif *cif = chip->cif; union cmdret rptr = CMDRET_ZERO; int i = 0; if (snd_BUG_ON(!cif)) return; snd_printdd("Write AC97 reg 0x%x 0x%x\n", reg, val); do { SEND_SACR(cif, val, reg); SEND_RACR(cif, reg, &rptr); } while (rptr.retwords[1] != val && i++ < MAX_WRITE_RETRY); if (i > MAX_WRITE_RETRY) snd_printdd("Write AC97 reg failed\n"); } static unsigned short snd_riptide_codec_read(struct snd_ac97 *ac97, unsigned short reg) { struct snd_riptide *chip = ac97->private_data; struct cmdif *cif = chip->cif; union cmdret rptr = CMDRET_ZERO; if (snd_BUG_ON(!cif)) return 0; if (SEND_RACR(cif, reg, &rptr) != 0) SEND_RACR(cif, reg, &rptr); snd_printdd("Read AC97 reg 0x%x got 0x%x\n", reg, rptr.retwords[1]); return rptr.retwords[1]; } static int snd_riptide_initialize(struct snd_riptide *chip) { struct cmdif *cif; unsigned int device_id; int err; if (snd_BUG_ON(!chip)) return -EINVAL; cif = chip->cif; if (!cif) { cif = kzalloc(sizeof(struct cmdif), GFP_KERNEL); if (!cif) return -ENOMEM; cif->hwport = (struct riptideport *)chip->port; spin_lock_init(&cif->lock); chip->cif = cif; } cif->is_reset = 0; err = riptide_reset(cif, chip); if (err) return err; device_id = chip->device_id; switch (device_id) { case 0x4310: case 0x4320: case 0x4330: snd_printdd("Modem enable?\n"); SEND_SETDPLL(cif); break; } snd_printdd("Enabling MPU IRQs\n"); if (chip->rmidi) SET_EMPUIRQ(cif->hwport); return err; } static void snd_riptide_free(struct snd_card *card) { struct snd_riptide *chip = card->private_data; struct cmdif *cif; cif = chip->cif; if (cif) { SET_GRESET(cif->hwport); udelay(100); UNSET_GRESET(cif->hwport); kfree(chip->cif); } release_firmware(chip->fw_entry); } static int snd_riptide_create(struct snd_card *card, struct pci_dev *pci) { struct snd_riptide *chip = card->private_data; struct riptideport *hwport; int err; err = pcim_enable_device(pci); if (err < 0) return err; spin_lock_init(&chip->lock); chip->card = card; chip->pci = pci; chip->irq = -1; chip->openstreams = 0; chip->port = pci_resource_start(pci, 0); chip->received_irqs = 0; chip->handled_irqs = 0; chip->cif = NULL; card->private_free = snd_riptide_free; err = pci_request_regions(pci, "RIPTIDE"); if (err < 0) return err; hwport = (struct riptideport *)chip->port; UNSET_AIE(hwport); if (devm_request_threaded_irq(&pci->dev, pci->irq, snd_riptide_interrupt, riptide_handleirq, IRQF_SHARED, KBUILD_MODNAME, chip)) { snd_printk(KERN_ERR "Riptide: unable to grab IRQ %d\n", pci->irq); return -EBUSY; } chip->irq = pci->irq; card->sync_irq = chip->irq; chip->device_id = pci->device; pci_set_master(pci); err = snd_riptide_initialize(chip); if (err < 0) return err; return 0; } static void snd_riptide_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct snd_riptide *chip = entry->private_data; struct pcmhw *data; int i; struct cmdif *cif = NULL; unsigned char p[256]; unsigned short rval = 0, lval = 0; unsigned int rate; if (!chip) return; snd_iprintf(buffer, "%s\n\n", chip->card->longname); snd_iprintf(buffer, "Device ID: 0x%x\nReceived IRQs: (%ld)%ld\nPorts:", chip->device_id, chip->handled_irqs, chip->received_irqs); for (i = 0; i < 64; i += 4) snd_iprintf(buffer, "%c%02x: %08x", (i % 16) ? ' ' : '\n', i, inl(chip->port + i)); cif = chip->cif; if (cif) { snd_iprintf(buffer, "\nVersion: ASIC: %d CODEC: %d AUXDSP: %d PROG: %d", chip->firmware.firmware.ASIC, chip->firmware.firmware.CODEC, chip->firmware.firmware.AUXDSP, chip->firmware.firmware.PROG); snd_iprintf(buffer, "\nDigital mixer:"); for (i = 0; i < 12; i++) { getmixer(cif, i, &rval, &lval); snd_iprintf(buffer, "\n %d: %d %d", i, rval, lval); } snd_iprintf(buffer, "\nARM Commands num: %d failed: %d time: %d max: %d min: %d", cif->cmdcnt, cif->errcnt, cif->cmdtime, cif->cmdtimemax, cif->cmdtimemin); } snd_iprintf(buffer, "\nOpen streams %d:\n", chip->openstreams); for (i = 0; i < PLAYBACK_SUBSTREAMS; i++) { if (!chip->playback_substream[i] || !chip->playback_substream[i]->runtime) continue; data = chip->playback_substream[i]->runtime->private_data; if (data) { snd_iprintf(buffer, "stream: %d mixer: %d source: %d (%d,%d)\n", data->id, data->mixer, data->source, data->intdec[0], data->intdec[1]); if (!(getsamplerate(cif, data->intdec, &rate))) snd_iprintf(buffer, "rate: %d\n", rate); } } if (chip->capture_substream && chip->capture_substream->runtime) { data = chip->capture_substream->runtime->private_data; if (data) { snd_iprintf(buffer, "stream: %d mixer: %d source: %d (%d,%d)\n", data->id, data->mixer, data->source, data->intdec[0], data->intdec[1]); if (!(getsamplerate(cif, data->intdec, &rate))) snd_iprintf(buffer, "rate: %d\n", rate); } } snd_iprintf(buffer, "Paths:\n"); i = getpaths(cif, p); while (i >= 2) { i -= 2; snd_iprintf(buffer, "%x->%x ", p[i], p[i + 1]); } snd_iprintf(buffer, "\n"); } static void snd_riptide_proc_init(struct snd_riptide *chip) { snd_card_ro_proc_new(chip->card, "riptide", chip, snd_riptide_proc_read); } static int snd_riptide_mixer(struct snd_riptide *chip) { struct snd_ac97_bus *pbus; struct snd_ac97_template ac97; int err = 0; static const struct snd_ac97_bus_ops ops = { .write = snd_riptide_codec_write, .read = snd_riptide_codec_read, }; memset(&ac97, 0, sizeof(ac97)); ac97.private_data = chip; ac97.scaps = AC97_SCAP_SKIP_MODEM; err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus); if (err < 0) return err; chip->ac97_bus = pbus; ac97.pci = chip->pci; err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); if (err < 0) return err; return err; } #ifdef SUPPORT_JOYSTICK static int snd_riptide_joystick_probe(struct pci_dev *pci, const struct pci_device_id *id) { static int dev; struct gameport *gameport; int ret; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { ret = -ENOENT; goto inc_dev; } if (!joystick_port[dev]) { ret = 0; goto inc_dev; } gameport = gameport_allocate_port(); if (!gameport) { ret = -ENOMEM; goto inc_dev; } if (!request_region(joystick_port[dev], 8, "Riptide gameport")) { snd_printk(KERN_WARNING "Riptide: cannot grab gameport 0x%x\n", joystick_port[dev]); gameport_free_port(gameport); ret = -EBUSY; goto inc_dev; } gameport->io = joystick_port[dev]; gameport_register_port(gameport); pci_set_drvdata(pci, gameport); ret = 0; inc_dev: dev++; return ret; } static void snd_riptide_joystick_remove(struct pci_dev *pci) { struct gameport *gameport = pci_get_drvdata(pci); if (gameport) { release_region(gameport->io, 8); gameport_unregister_port(gameport); } } #endif static int __snd_card_riptide_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct snd_card *card; struct snd_riptide *chip; unsigned short val; int err; if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, sizeof(*chip), &card); if (err < 0) return err; chip = card->private_data; err = snd_riptide_create(card, pci); if (err < 0) return err; err = snd_riptide_pcm(chip, 0); if (err < 0) return err; err = snd_riptide_mixer(chip); if (err < 0) return err; val = LEGACY_ENABLE_ALL; if (opl3_port[dev]) val |= LEGACY_ENABLE_FM; #ifdef SUPPORT_JOYSTICK if (joystick_port[dev]) val |= LEGACY_ENABLE_GAMEPORT; #endif if (mpu_port[dev]) val |= LEGACY_ENABLE_MPU_INT | LEGACY_ENABLE_MPU; val |= (chip->irq << 4) & 0xf0; pci_write_config_word(chip->pci, PCI_EXT_Legacy_Mask, val); if (mpu_port[dev]) { val = mpu_port[dev]; pci_write_config_word(chip->pci, PCI_EXT_MPU_Base, val); err = snd_mpu401_uart_new(card, 0, MPU401_HW_RIPTIDE, val, MPU401_INFO_IRQ_HOOK, -1, &chip->rmidi); if (err < 0) snd_printk(KERN_WARNING "Riptide: Can't Allocate MPU at 0x%x\n", val); else chip->mpuaddr = val; } if (opl3_port[dev]) { val = opl3_port[dev]; pci_write_config_word(chip->pci, PCI_EXT_FM_Base, val); err = snd_opl3_create(card, val, val + 2, OPL3_HW_RIPTIDE, 0, &chip->opl3); if (err < 0) snd_printk(KERN_WARNING "Riptide: Can't Allocate OPL3 at 0x%x\n", val); else { chip->opladdr = val; err = snd_opl3_hwdep_new(chip->opl3, 0, 1, NULL); if (err < 0) snd_printk(KERN_WARNING "Riptide: Can't Allocate OPL3-HWDEP\n"); } } #ifdef SUPPORT_JOYSTICK if (joystick_port[dev]) { val = joystick_port[dev]; pci_write_config_word(chip->pci, PCI_EXT_Game_Base, val); chip->gameaddr = val; } #endif strcpy(card->driver, "RIPTIDE"); strcpy(card->shortname, "Riptide"); #ifdef SUPPORT_JOYSTICK scnprintf(card->longname, sizeof(card->longname), "%s at 0x%lx, irq %i mpu 0x%x opl3 0x%x gameport 0x%x", card->shortname, chip->port, chip->irq, chip->mpuaddr, chip->opladdr, chip->gameaddr); #else scnprintf(card->longname, sizeof(card->longname), "%s at 0x%lx, irq %i mpu 0x%x opl3 0x%x", card->shortname, chip->port, chip->irq, chip->mpuaddr, chip->opladdr); #endif snd_riptide_proc_init(chip); err = snd_card_register(card); if (err < 0) return err; pci_set_drvdata(pci, card); dev++; return 0; } static int snd_card_riptide_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { return snd_card_free_on_error(&pci->dev, __snd_card_riptide_probe(pci, pci_id)); } static struct pci_driver driver = { .name = KBUILD_MODNAME, .id_table = snd_riptide_ids, .probe = snd_card_riptide_probe, .driver = { .pm = RIPTIDE_PM_OPS, }, }; #ifdef SUPPORT_JOYSTICK static struct pci_driver joystick_driver = { .name = KBUILD_MODNAME "-joystick", .id_table = snd_riptide_joystick_ids, .probe = snd_riptide_joystick_probe, .remove = snd_riptide_joystick_remove, }; #endif static int __init alsa_card_riptide_init(void) { int err; err = pci_register_driver(&driver); if (err < 0) return err; #if defined(SUPPORT_JOYSTICK) err = pci_register_driver(&joystick_driver); /* On failure unregister formerly registered audio driver */ if (err < 0) pci_unregister_driver(&driver); #endif return err; } static void __exit alsa_card_riptide_exit(void) { pci_unregister_driver(&driver); #if defined(SUPPORT_JOYSTICK) pci_unregister_driver(&joystick_driver); #endif } module_init(alsa_card_riptide_init); module_exit(alsa_card_riptide_exit);
linux-master
sound/pci/riptide/riptide.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Universal Interface for Intel High Definition Audio Codec * * Copyright (c) 2004 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/mutex.h> #include <linux/module.h> #include <linux/pm.h> #include <linux/pm_runtime.h> #include <sound/core.h> #include <sound/hda_codec.h> #include <sound/asoundef.h> #include <sound/tlv.h> #include <sound/initval.h> #include <sound/jack.h> #include "hda_local.h" #include "hda_beep.h" #include "hda_jack.h" #include <sound/hda_hwdep.h> #include <sound/hda_component.h> #define codec_in_pm(codec) snd_hdac_is_in_pm(&codec->core) #define hda_codec_is_power_on(codec) snd_hdac_is_power_on(&codec->core) #define codec_has_epss(codec) \ ((codec)->core.power_caps & AC_PWRST_EPSS) #define codec_has_clkstop(codec) \ ((codec)->core.power_caps & AC_PWRST_CLKSTOP) /* * Send and receive a verb - passed to exec_verb override for hdac_device */ static int codec_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, unsigned int *res) { struct hda_codec *codec = container_of(dev, struct hda_codec, core); struct hda_bus *bus = codec->bus; int err; if (cmd == ~0) return -1; again: snd_hda_power_up_pm(codec); mutex_lock(&bus->core.cmd_mutex); if (flags & HDA_RW_NO_RESPONSE_FALLBACK) bus->no_response_fallback = 1; err = snd_hdac_bus_exec_verb_unlocked(&bus->core, codec->core.addr, cmd, res); bus->no_response_fallback = 0; mutex_unlock(&bus->core.cmd_mutex); snd_hda_power_down_pm(codec); if (!codec_in_pm(codec) && res && err == -EAGAIN) { if (bus->response_reset) { codec_dbg(codec, "resetting BUS due to fatal communication error\n"); snd_hda_bus_reset(bus); } goto again; } /* clear reset-flag when the communication gets recovered */ if (!err || codec_in_pm(codec)) bus->response_reset = 0; return err; } /** * snd_hda_sequence_write - sequence writes * @codec: the HDA codec * @seq: VERB array to send * * Send the commands sequentially from the given array. * The array must be terminated with NID=0. */ void snd_hda_sequence_write(struct hda_codec *codec, const struct hda_verb *seq) { for (; seq->nid; seq++) snd_hda_codec_write(codec, seq->nid, 0, seq->verb, seq->param); } EXPORT_SYMBOL_GPL(snd_hda_sequence_write); /* connection list element */ struct hda_conn_list { struct list_head list; int len; hda_nid_t nid; hda_nid_t conns[]; }; /* look up the cached results */ static struct hda_conn_list * lookup_conn_list(struct hda_codec *codec, hda_nid_t nid) { struct hda_conn_list *p; list_for_each_entry(p, &codec->conn_list, list) { if (p->nid == nid) return p; } return NULL; } static int add_conn_list(struct hda_codec *codec, hda_nid_t nid, int len, const hda_nid_t *list) { struct hda_conn_list *p; p = kmalloc(struct_size(p, conns, len), GFP_KERNEL); if (!p) return -ENOMEM; p->len = len; p->nid = nid; memcpy(p->conns, list, len * sizeof(hda_nid_t)); list_add(&p->list, &codec->conn_list); return 0; } static void remove_conn_list(struct hda_codec *codec) { while (!list_empty(&codec->conn_list)) { struct hda_conn_list *p; p = list_first_entry(&codec->conn_list, typeof(*p), list); list_del(&p->list); kfree(p); } } /* read the connection and add to the cache */ static int read_and_add_raw_conns(struct hda_codec *codec, hda_nid_t nid) { hda_nid_t list[32]; hda_nid_t *result = list; int len; len = snd_hda_get_raw_connections(codec, nid, list, ARRAY_SIZE(list)); if (len == -ENOSPC) { len = snd_hda_get_num_raw_conns(codec, nid); result = kmalloc_array(len, sizeof(hda_nid_t), GFP_KERNEL); if (!result) return -ENOMEM; len = snd_hda_get_raw_connections(codec, nid, result, len); } if (len >= 0) len = snd_hda_override_conn_list(codec, nid, len, result); if (result != list) kfree(result); return len; } /** * snd_hda_get_conn_list - get connection list * @codec: the HDA codec * @nid: NID to parse * @listp: the pointer to store NID list * * Parses the connection list of the given widget and stores the pointer * to the list of NIDs. * * Returns the number of connections, or a negative error code. * * Note that the returned pointer isn't protected against the list * modification. If snd_hda_override_conn_list() might be called * concurrently, protect with a mutex appropriately. */ int snd_hda_get_conn_list(struct hda_codec *codec, hda_nid_t nid, const hda_nid_t **listp) { bool added = false; for (;;) { int err; const struct hda_conn_list *p; /* if the connection-list is already cached, read it */ p = lookup_conn_list(codec, nid); if (p) { if (listp) *listp = p->conns; return p->len; } if (snd_BUG_ON(added)) return -EINVAL; err = read_and_add_raw_conns(codec, nid); if (err < 0) return err; added = true; } } EXPORT_SYMBOL_GPL(snd_hda_get_conn_list); /** * snd_hda_get_connections - copy connection list * @codec: the HDA codec * @nid: NID to parse * @conn_list: connection list array; when NULL, checks only the size * @max_conns: max. number of connections to store * * Parses the connection list of the given widget and stores the list * of NIDs. * * Returns the number of connections, or a negative error code. */ int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid, hda_nid_t *conn_list, int max_conns) { const hda_nid_t *list; int len = snd_hda_get_conn_list(codec, nid, &list); if (len > 0 && conn_list) { if (len > max_conns) { codec_err(codec, "Too many connections %d for NID 0x%x\n", len, nid); return -EINVAL; } memcpy(conn_list, list, len * sizeof(hda_nid_t)); } return len; } EXPORT_SYMBOL_GPL(snd_hda_get_connections); /** * snd_hda_override_conn_list - add/modify the connection-list to cache * @codec: the HDA codec * @nid: NID to parse * @len: number of connection list entries * @list: the list of connection entries * * Add or modify the given connection-list to the cache. If the corresponding * cache already exists, invalidate it and append a new one. * * Returns zero or a negative error code. */ int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int len, const hda_nid_t *list) { struct hda_conn_list *p; p = lookup_conn_list(codec, nid); if (p) { list_del(&p->list); kfree(p); } return add_conn_list(codec, nid, len, list); } EXPORT_SYMBOL_GPL(snd_hda_override_conn_list); /** * snd_hda_get_conn_index - get the connection index of the given NID * @codec: the HDA codec * @mux: NID containing the list * @nid: NID to select * @recursive: 1 when searching NID recursively, otherwise 0 * * Parses the connection list of the widget @mux and checks whether the * widget @nid is present. If it is, return the connection index. * Otherwise it returns -1. */ int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux, hda_nid_t nid, int recursive) { const hda_nid_t *conn; int i, nums; nums = snd_hda_get_conn_list(codec, mux, &conn); for (i = 0; i < nums; i++) if (conn[i] == nid) return i; if (!recursive) return -1; if (recursive > 10) { codec_dbg(codec, "too deep connection for 0x%x\n", nid); return -1; } recursive++; for (i = 0; i < nums; i++) { unsigned int type = get_wcaps_type(get_wcaps(codec, conn[i])); if (type == AC_WID_PIN || type == AC_WID_AUD_OUT) continue; if (snd_hda_get_conn_index(codec, conn[i], nid, recursive) >= 0) return i; } return -1; } EXPORT_SYMBOL_GPL(snd_hda_get_conn_index); /** * snd_hda_get_num_devices - get DEVLIST_LEN parameter of the given widget * @codec: the HDA codec * @nid: NID of the pin to parse * * Get the device entry number on the given widget. This is a feature of * DP MST audio. Each pin can have several device entries in it. */ unsigned int snd_hda_get_num_devices(struct hda_codec *codec, hda_nid_t nid) { unsigned int wcaps = get_wcaps(codec, nid); unsigned int parm; if (!codec->dp_mst || !(wcaps & AC_WCAP_DIGITAL) || get_wcaps_type(wcaps) != AC_WID_PIN) return 0; parm = snd_hdac_read_parm_uncached(&codec->core, nid, AC_PAR_DEVLIST_LEN); if (parm == -1) parm = 0; return parm & AC_DEV_LIST_LEN_MASK; } EXPORT_SYMBOL_GPL(snd_hda_get_num_devices); /** * snd_hda_get_devices - copy device list without cache * @codec: the HDA codec * @nid: NID of the pin to parse * @dev_list: device list array * @max_devices: max. number of devices to store * * Copy the device list. This info is dynamic and so not cached. * Currently called only from hda_proc.c, so not exported. */ int snd_hda_get_devices(struct hda_codec *codec, hda_nid_t nid, u8 *dev_list, int max_devices) { unsigned int parm; int i, dev_len, devices; parm = snd_hda_get_num_devices(codec, nid); if (!parm) /* not multi-stream capable */ return 0; dev_len = parm + 1; dev_len = dev_len < max_devices ? dev_len : max_devices; devices = 0; while (devices < dev_len) { if (snd_hdac_read(&codec->core, nid, AC_VERB_GET_DEVICE_LIST, devices, &parm)) break; /* error */ for (i = 0; i < 8; i++) { dev_list[devices] = (u8)parm; parm >>= 4; devices++; if (devices >= dev_len) break; } } return devices; } /** * snd_hda_get_dev_select - get device entry select on the pin * @codec: the HDA codec * @nid: NID of the pin to get device entry select * * Get the devcie entry select on the pin. Return the device entry * id selected on the pin. Return 0 means the first device entry * is selected or MST is not supported. */ int snd_hda_get_dev_select(struct hda_codec *codec, hda_nid_t nid) { /* not support dp_mst will always return 0, using first dev_entry */ if (!codec->dp_mst) return 0; return snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_DEVICE_SEL, 0); } EXPORT_SYMBOL_GPL(snd_hda_get_dev_select); /** * snd_hda_set_dev_select - set device entry select on the pin * @codec: the HDA codec * @nid: NID of the pin to set device entry select * @dev_id: device entry id to be set * * Set the device entry select on the pin nid. */ int snd_hda_set_dev_select(struct hda_codec *codec, hda_nid_t nid, int dev_id) { int ret, num_devices; /* not support dp_mst will always return 0, using first dev_entry */ if (!codec->dp_mst) return 0; /* AC_PAR_DEVLIST_LEN is 0 based. */ num_devices = snd_hda_get_num_devices(codec, nid) + 1; /* If Device List Length is 0 (num_device = 1), * the pin is not multi stream capable. * Do nothing in this case. */ if (num_devices == 1) return 0; /* Behavior of setting index being equal to or greater than * Device List Length is not predictable */ if (num_devices <= dev_id) return -EINVAL; ret = snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_DEVICE_SEL, dev_id); return ret; } EXPORT_SYMBOL_GPL(snd_hda_set_dev_select); /* * read widget caps for each widget and store in cache */ static int read_widget_caps(struct hda_codec *codec, hda_nid_t fg_node) { int i; hda_nid_t nid; codec->wcaps = kmalloc_array(codec->core.num_nodes, 4, GFP_KERNEL); if (!codec->wcaps) return -ENOMEM; nid = codec->core.start_nid; for (i = 0; i < codec->core.num_nodes; i++, nid++) codec->wcaps[i] = snd_hdac_read_parm_uncached(&codec->core, nid, AC_PAR_AUDIO_WIDGET_CAP); return 0; } /* read all pin default configurations and save codec->init_pins */ static int read_pin_defaults(struct hda_codec *codec) { hda_nid_t nid; for_each_hda_codec_node(nid, codec) { struct hda_pincfg *pin; unsigned int wcaps = get_wcaps(codec, nid); unsigned int wid_type = get_wcaps_type(wcaps); if (wid_type != AC_WID_PIN) continue; pin = snd_array_new(&codec->init_pins); if (!pin) return -ENOMEM; pin->nid = nid; pin->cfg = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONFIG_DEFAULT, 0); /* * all device entries are the same widget control so far * fixme: if any codec is different, need fix here */ pin->ctrl = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); } return 0; } /* look up the given pin config list and return the item matching with NID */ static struct hda_pincfg *look_up_pincfg(struct hda_codec *codec, struct snd_array *array, hda_nid_t nid) { struct hda_pincfg *pin; int i; snd_array_for_each(array, i, pin) { if (pin->nid == nid) return pin; } return NULL; } /* set the current pin config value for the given NID. * the value is cached, and read via snd_hda_codec_get_pincfg() */ int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list, hda_nid_t nid, unsigned int cfg) { struct hda_pincfg *pin; /* the check below may be invalid when pins are added by a fixup * dynamically (e.g. via snd_hda_codec_update_widgets()), so disabled * for now */ /* if (get_wcaps_type(get_wcaps(codec, nid)) != AC_WID_PIN) return -EINVAL; */ pin = look_up_pincfg(codec, list, nid); if (!pin) { pin = snd_array_new(list); if (!pin) return -ENOMEM; pin->nid = nid; } pin->cfg = cfg; return 0; } /** * snd_hda_codec_set_pincfg - Override a pin default configuration * @codec: the HDA codec * @nid: NID to set the pin config * @cfg: the pin default config value * * Override a pin default configuration value in the cache. * This value can be read by snd_hda_codec_get_pincfg() in a higher * priority than the real hardware value. */ int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid, unsigned int cfg) { return snd_hda_add_pincfg(codec, &codec->driver_pins, nid, cfg); } EXPORT_SYMBOL_GPL(snd_hda_codec_set_pincfg); /** * snd_hda_codec_get_pincfg - Obtain a pin-default configuration * @codec: the HDA codec * @nid: NID to get the pin config * * Get the current pin config value of the given pin NID. * If the pincfg value is cached or overridden via sysfs or driver, * returns the cached value. */ unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid) { struct hda_pincfg *pin; #ifdef CONFIG_SND_HDA_RECONFIG { unsigned int cfg = 0; mutex_lock(&codec->user_mutex); pin = look_up_pincfg(codec, &codec->user_pins, nid); if (pin) cfg = pin->cfg; mutex_unlock(&codec->user_mutex); if (cfg) return cfg; } #endif pin = look_up_pincfg(codec, &codec->driver_pins, nid); if (pin) return pin->cfg; pin = look_up_pincfg(codec, &codec->init_pins, nid); if (pin) return pin->cfg; return 0; } EXPORT_SYMBOL_GPL(snd_hda_codec_get_pincfg); /** * snd_hda_codec_set_pin_target - remember the current pinctl target value * @codec: the HDA codec * @nid: pin NID * @val: assigned pinctl value * * This function stores the given value to a pinctl target value in the * pincfg table. This isn't always as same as the actually written value * but can be referred at any time via snd_hda_codec_get_pin_target(). */ int snd_hda_codec_set_pin_target(struct hda_codec *codec, hda_nid_t nid, unsigned int val) { struct hda_pincfg *pin; pin = look_up_pincfg(codec, &codec->init_pins, nid); if (!pin) return -EINVAL; pin->target = val; return 0; } EXPORT_SYMBOL_GPL(snd_hda_codec_set_pin_target); /** * snd_hda_codec_get_pin_target - return the current pinctl target value * @codec: the HDA codec * @nid: pin NID */ int snd_hda_codec_get_pin_target(struct hda_codec *codec, hda_nid_t nid) { struct hda_pincfg *pin; pin = look_up_pincfg(codec, &codec->init_pins, nid); if (!pin) return 0; return pin->target; } EXPORT_SYMBOL_GPL(snd_hda_codec_get_pin_target); /** * snd_hda_shutup_pins - Shut up all pins * @codec: the HDA codec * * Clear all pin controls to shup up before suspend for avoiding click noise. * The controls aren't cached so that they can be resumed properly. */ void snd_hda_shutup_pins(struct hda_codec *codec) { const struct hda_pincfg *pin; int i; /* don't shut up pins when unloading the driver; otherwise it breaks * the default pin setup at the next load of the driver */ if (codec->bus->shutdown) return; snd_array_for_each(&codec->init_pins, i, pin) { /* use read here for syncing after issuing each verb */ snd_hda_codec_read(codec, pin->nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0); } codec->pins_shutup = 1; } EXPORT_SYMBOL_GPL(snd_hda_shutup_pins); #ifdef CONFIG_PM /* Restore the pin controls cleared previously via snd_hda_shutup_pins() */ static void restore_shutup_pins(struct hda_codec *codec) { const struct hda_pincfg *pin; int i; if (!codec->pins_shutup) return; if (codec->bus->shutdown) return; snd_array_for_each(&codec->init_pins, i, pin) { snd_hda_codec_write(codec, pin->nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pin->ctrl); } codec->pins_shutup = 0; } #endif static void hda_jackpoll_work(struct work_struct *work) { struct hda_codec *codec = container_of(work, struct hda_codec, jackpoll_work.work); /* for non-polling trigger: we need nothing if already powered on */ if (!codec->jackpoll_interval && snd_hdac_is_power_on(&codec->core)) return; /* the power-up/down sequence triggers the runtime resume */ snd_hda_power_up_pm(codec); /* update jacks manually if polling is required, too */ if (codec->jackpoll_interval) { snd_hda_jack_set_dirty_all(codec); snd_hda_jack_poll_all(codec); } snd_hda_power_down_pm(codec); if (!codec->jackpoll_interval) return; schedule_delayed_work(&codec->jackpoll_work, codec->jackpoll_interval); } /* release all pincfg lists */ static void free_init_pincfgs(struct hda_codec *codec) { snd_array_free(&codec->driver_pins); #ifdef CONFIG_SND_HDA_RECONFIG snd_array_free(&codec->user_pins); #endif snd_array_free(&codec->init_pins); } /* * audio-converter setup caches */ struct hda_cvt_setup { hda_nid_t nid; u8 stream_tag; u8 channel_id; u16 format_id; unsigned char active; /* cvt is currently used */ unsigned char dirty; /* setups should be cleared */ }; /* get or create a cache entry for the given audio converter NID */ static struct hda_cvt_setup * get_hda_cvt_setup(struct hda_codec *codec, hda_nid_t nid) { struct hda_cvt_setup *p; int i; snd_array_for_each(&codec->cvt_setups, i, p) { if (p->nid == nid) return p; } p = snd_array_new(&codec->cvt_setups); if (p) p->nid = nid; return p; } /* * PCM device */ void snd_hda_codec_pcm_put(struct hda_pcm *pcm) { if (refcount_dec_and_test(&pcm->codec->pcm_ref)) wake_up(&pcm->codec->remove_sleep); } EXPORT_SYMBOL_GPL(snd_hda_codec_pcm_put); struct hda_pcm *snd_hda_codec_pcm_new(struct hda_codec *codec, const char *fmt, ...) { struct hda_pcm *pcm; va_list args; pcm = kzalloc(sizeof(*pcm), GFP_KERNEL); if (!pcm) return NULL; pcm->codec = codec; va_start(args, fmt); pcm->name = kvasprintf(GFP_KERNEL, fmt, args); va_end(args); if (!pcm->name) { kfree(pcm); return NULL; } list_add_tail(&pcm->list, &codec->pcm_list_head); refcount_inc(&codec->pcm_ref); return pcm; } EXPORT_SYMBOL_GPL(snd_hda_codec_pcm_new); /* * codec destructor */ void snd_hda_codec_disconnect_pcms(struct hda_codec *codec) { struct hda_pcm *pcm; list_for_each_entry(pcm, &codec->pcm_list_head, list) { if (pcm->disconnected) continue; if (pcm->pcm) snd_device_disconnect(codec->card, pcm->pcm); snd_hda_codec_pcm_put(pcm); pcm->disconnected = 1; } } static void codec_release_pcms(struct hda_codec *codec) { struct hda_pcm *pcm, *n; list_for_each_entry_safe(pcm, n, &codec->pcm_list_head, list) { list_del(&pcm->list); if (pcm->pcm) snd_device_free(pcm->codec->card, pcm->pcm); clear_bit(pcm->device, pcm->codec->bus->pcm_dev_bits); kfree(pcm->name); kfree(pcm); } } /** * snd_hda_codec_cleanup_for_unbind - Prepare codec for removal * @codec: codec device to cleanup */ void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec) { if (codec->core.registered) { /* pm_runtime_put() is called in snd_hdac_device_exit() */ pm_runtime_get_noresume(hda_codec_dev(codec)); pm_runtime_disable(hda_codec_dev(codec)); codec->core.registered = 0; } snd_hda_codec_disconnect_pcms(codec); cancel_delayed_work_sync(&codec->jackpoll_work); if (!codec->in_freeing) snd_hda_ctls_clear(codec); codec_release_pcms(codec); snd_hda_detach_beep_device(codec); memset(&codec->patch_ops, 0, sizeof(codec->patch_ops)); snd_hda_jack_tbl_clear(codec); codec->proc_widget_hook = NULL; codec->spec = NULL; /* free only driver_pins so that init_pins + user_pins are restored */ snd_array_free(&codec->driver_pins); snd_array_free(&codec->cvt_setups); snd_array_free(&codec->spdif_out); snd_array_free(&codec->verbs); codec->follower_dig_outs = NULL; codec->spdif_status_reset = 0; snd_array_free(&codec->mixers); snd_array_free(&codec->nids); remove_conn_list(codec); snd_hdac_regmap_exit(&codec->core); codec->configured = 0; refcount_set(&codec->pcm_ref, 1); /* reset refcount */ } EXPORT_SYMBOL_GPL(snd_hda_codec_cleanup_for_unbind); static unsigned int hda_set_power_state(struct hda_codec *codec, unsigned int power_state); /* enable/disable display power per codec */ void snd_hda_codec_display_power(struct hda_codec *codec, bool enable) { if (codec->display_power_control) snd_hdac_display_power(&codec->bus->core, codec->addr, enable); } /** * snd_hda_codec_register - Finalize codec initialization * @codec: codec device to register * * Also called from hda_bind.c */ void snd_hda_codec_register(struct hda_codec *codec) { if (codec->core.registered) return; if (device_is_registered(hda_codec_dev(codec))) { snd_hda_codec_display_power(codec, true); pm_runtime_enable(hda_codec_dev(codec)); /* it was powered up in snd_hda_codec_new(), now all done */ snd_hda_power_down(codec); codec->core.registered = 1; } } EXPORT_SYMBOL_GPL(snd_hda_codec_register); static int snd_hda_codec_dev_register(struct snd_device *device) { snd_hda_codec_register(device->device_data); return 0; } /** * snd_hda_codec_unregister - Unregister specified codec device * @codec: codec device to unregister */ void snd_hda_codec_unregister(struct hda_codec *codec) { codec->in_freeing = 1; /* * snd_hda_codec_device_new() is used by legacy HDA and ASoC driver. * We can't unregister ASoC device since it will be unregistered in * snd_hdac_ext_bus_device_remove(). */ if (codec->core.type == HDA_DEV_LEGACY) snd_hdac_device_unregister(&codec->core); snd_hda_codec_display_power(codec, false); /* * In the case of ASoC HD-audio bus, the device refcount is released in * snd_hdac_ext_bus_device_remove() explicitly. */ if (codec->core.type == HDA_DEV_LEGACY) put_device(hda_codec_dev(codec)); } EXPORT_SYMBOL_GPL(snd_hda_codec_unregister); static int snd_hda_codec_dev_free(struct snd_device *device) { snd_hda_codec_unregister(device->device_data); return 0; } static void snd_hda_codec_dev_release(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); free_init_pincfgs(codec); snd_hdac_device_exit(&codec->core); snd_hda_sysfs_clear(codec); kfree(codec->modelname); kfree(codec->wcaps); kfree(codec); } #define DEV_NAME_LEN 31 /** * snd_hda_codec_device_init - allocate HDA codec device * @bus: codec's parent bus * @codec_addr: the codec address on the parent bus * @fmt: format string for the device's name * * Returns newly allocated codec device or ERR_PTR() on failure. */ struct hda_codec * snd_hda_codec_device_init(struct hda_bus *bus, unsigned int codec_addr, const char *fmt, ...) { va_list vargs; char name[DEV_NAME_LEN]; struct hda_codec *codec; int err; if (snd_BUG_ON(!bus)) return ERR_PTR(-EINVAL); if (snd_BUG_ON(codec_addr > HDA_MAX_CODEC_ADDRESS)) return ERR_PTR(-EINVAL); codec = kzalloc(sizeof(*codec), GFP_KERNEL); if (!codec) return ERR_PTR(-ENOMEM); va_start(vargs, fmt); vsprintf(name, fmt, vargs); va_end(vargs); err = snd_hdac_device_init(&codec->core, &bus->core, name, codec_addr); if (err < 0) { kfree(codec); return ERR_PTR(err); } codec->bus = bus; codec->depop_delay = -1; codec->fixup_id = HDA_FIXUP_ID_NOT_SET; codec->core.dev.release = snd_hda_codec_dev_release; codec->core.type = HDA_DEV_LEGACY; mutex_init(&codec->spdif_mutex); mutex_init(&codec->control_mutex); snd_array_init(&codec->mixers, sizeof(struct hda_nid_item), 32); snd_array_init(&codec->nids, sizeof(struct hda_nid_item), 32); snd_array_init(&codec->init_pins, sizeof(struct hda_pincfg), 16); snd_array_init(&codec->driver_pins, sizeof(struct hda_pincfg), 16); snd_array_init(&codec->cvt_setups, sizeof(struct hda_cvt_setup), 8); snd_array_init(&codec->spdif_out, sizeof(struct hda_spdif_out), 16); snd_array_init(&codec->jacktbl, sizeof(struct hda_jack_tbl), 16); snd_array_init(&codec->verbs, sizeof(struct hda_verb *), 8); INIT_LIST_HEAD(&codec->conn_list); INIT_LIST_HEAD(&codec->pcm_list_head); INIT_DELAYED_WORK(&codec->jackpoll_work, hda_jackpoll_work); refcount_set(&codec->pcm_ref, 1); init_waitqueue_head(&codec->remove_sleep); return codec; } EXPORT_SYMBOL_GPL(snd_hda_codec_device_init); /** * snd_hda_codec_new - create a HDA codec * @bus: the bus to assign * @card: card for this codec * @codec_addr: the codec address * @codecp: the pointer to store the generated codec * * Returns 0 if successful, or a negative error code. */ int snd_hda_codec_new(struct hda_bus *bus, struct snd_card *card, unsigned int codec_addr, struct hda_codec **codecp) { struct hda_codec *codec; int ret; codec = snd_hda_codec_device_init(bus, codec_addr, "hdaudioC%dD%d", card->number, codec_addr); if (IS_ERR(codec)) return PTR_ERR(codec); *codecp = codec; ret = snd_hda_codec_device_new(bus, card, codec_addr, *codecp, true); if (ret) put_device(hda_codec_dev(*codecp)); return ret; } EXPORT_SYMBOL_GPL(snd_hda_codec_new); int snd_hda_codec_device_new(struct hda_bus *bus, struct snd_card *card, unsigned int codec_addr, struct hda_codec *codec, bool snddev_managed) { char component[31]; hda_nid_t fg; int err; static const struct snd_device_ops dev_ops = { .dev_register = snd_hda_codec_dev_register, .dev_free = snd_hda_codec_dev_free, }; dev_dbg(card->dev, "%s: entry\n", __func__); if (snd_BUG_ON(!bus)) return -EINVAL; if (snd_BUG_ON(codec_addr > HDA_MAX_CODEC_ADDRESS)) return -EINVAL; codec->core.exec_verb = codec_exec_verb; codec->card = card; codec->addr = codec_addr; #ifdef CONFIG_PM codec->power_jiffies = jiffies; #endif snd_hda_sysfs_init(codec); if (codec->bus->modelname) { codec->modelname = kstrdup(codec->bus->modelname, GFP_KERNEL); if (!codec->modelname) return -ENOMEM; } fg = codec->core.afg ? codec->core.afg : codec->core.mfg; err = read_widget_caps(codec, fg); if (err < 0) return err; err = read_pin_defaults(codec); if (err < 0) return err; /* power-up all before initialization */ hda_set_power_state(codec, AC_PWRST_D0); codec->core.dev.power.power_state = PMSG_ON; snd_hda_codec_proc_new(codec); snd_hda_create_hwdep(codec); sprintf(component, "HDA:%08x,%08x,%08x", codec->core.vendor_id, codec->core.subsystem_id, codec->core.revision_id); snd_component_add(card, component); if (snddev_managed) { /* ASoC features component management instead */ err = snd_device_new(card, SNDRV_DEV_CODEC, codec, &dev_ops); if (err < 0) return err; } #ifdef CONFIG_PM /* PM runtime needs to be enabled later after binding codec */ if (codec->core.dev.power.runtime_auto) pm_runtime_forbid(&codec->core.dev); else /* Keep the usage_count consistent across subsequent probing */ pm_runtime_get_noresume(&codec->core.dev); #endif return 0; } EXPORT_SYMBOL_GPL(snd_hda_codec_device_new); /** * snd_hda_codec_update_widgets - Refresh widget caps and pin defaults * @codec: the HDA codec * * Forcibly refresh the all widget caps and the init pin configurations of * the given codec. */ int snd_hda_codec_update_widgets(struct hda_codec *codec) { hda_nid_t fg; int err; err = snd_hdac_refresh_widgets(&codec->core); if (err < 0) return err; /* Assume the function group node does not change, * only the widget nodes may change. */ kfree(codec->wcaps); fg = codec->core.afg ? codec->core.afg : codec->core.mfg; err = read_widget_caps(codec, fg); if (err < 0) return err; snd_array_free(&codec->init_pins); err = read_pin_defaults(codec); return err; } EXPORT_SYMBOL_GPL(snd_hda_codec_update_widgets); /* update the stream-id if changed */ static void update_pcm_stream_id(struct hda_codec *codec, struct hda_cvt_setup *p, hda_nid_t nid, u32 stream_tag, int channel_id) { unsigned int oldval, newval; if (p->stream_tag != stream_tag || p->channel_id != channel_id) { oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0); newval = (stream_tag << 4) | channel_id; if (oldval != newval) snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, newval); p->stream_tag = stream_tag; p->channel_id = channel_id; } } /* update the format-id if changed */ static void update_pcm_format(struct hda_codec *codec, struct hda_cvt_setup *p, hda_nid_t nid, int format) { unsigned int oldval; if (p->format_id != format) { oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_STREAM_FORMAT, 0); if (oldval != format) { msleep(1); snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, format); } p->format_id = format; } } /** * snd_hda_codec_setup_stream - set up the codec for streaming * @codec: the CODEC to set up * @nid: the NID to set up * @stream_tag: stream tag to pass, it's between 0x1 and 0xf. * @channel_id: channel id to pass, zero based. * @format: stream format. */ void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid, u32 stream_tag, int channel_id, int format) { struct hda_codec *c; struct hda_cvt_setup *p; int type; int i; if (!nid) return; codec_dbg(codec, "hda_codec_setup_stream: NID=0x%x, stream=0x%x, channel=%d, format=0x%x\n", nid, stream_tag, channel_id, format); p = get_hda_cvt_setup(codec, nid); if (!p) return; if (codec->patch_ops.stream_pm) codec->patch_ops.stream_pm(codec, nid, true); if (codec->pcm_format_first) update_pcm_format(codec, p, nid, format); update_pcm_stream_id(codec, p, nid, stream_tag, channel_id); if (!codec->pcm_format_first) update_pcm_format(codec, p, nid, format); p->active = 1; p->dirty = 0; /* make other inactive cvts with the same stream-tag dirty */ type = get_wcaps_type(get_wcaps(codec, nid)); list_for_each_codec(c, codec->bus) { snd_array_for_each(&c->cvt_setups, i, p) { if (!p->active && p->stream_tag == stream_tag && get_wcaps_type(get_wcaps(c, p->nid)) == type) p->dirty = 1; } } } EXPORT_SYMBOL_GPL(snd_hda_codec_setup_stream); static void really_cleanup_stream(struct hda_codec *codec, struct hda_cvt_setup *q); /** * __snd_hda_codec_cleanup_stream - clean up the codec for closing * @codec: the CODEC to clean up * @nid: the NID to clean up * @do_now: really clean up the stream instead of clearing the active flag */ void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid, int do_now) { struct hda_cvt_setup *p; if (!nid) return; if (codec->no_sticky_stream) do_now = 1; codec_dbg(codec, "hda_codec_cleanup_stream: NID=0x%x\n", nid); p = get_hda_cvt_setup(codec, nid); if (p) { /* here we just clear the active flag when do_now isn't set; * actual clean-ups will be done later in * purify_inactive_streams() called from snd_hda_codec_prpapre() */ if (do_now) really_cleanup_stream(codec, p); else p->active = 0; } } EXPORT_SYMBOL_GPL(__snd_hda_codec_cleanup_stream); static void really_cleanup_stream(struct hda_codec *codec, struct hda_cvt_setup *q) { hda_nid_t nid = q->nid; if (q->stream_tag || q->channel_id) snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0); if (q->format_id) snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0 ); memset(q, 0, sizeof(*q)); q->nid = nid; if (codec->patch_ops.stream_pm) codec->patch_ops.stream_pm(codec, nid, false); } /* clean up the all conflicting obsolete streams */ static void purify_inactive_streams(struct hda_codec *codec) { struct hda_codec *c; struct hda_cvt_setup *p; int i; list_for_each_codec(c, codec->bus) { snd_array_for_each(&c->cvt_setups, i, p) { if (p->dirty) really_cleanup_stream(c, p); } } } #ifdef CONFIG_PM /* clean up all streams; called from suspend */ static void hda_cleanup_all_streams(struct hda_codec *codec) { struct hda_cvt_setup *p; int i; snd_array_for_each(&codec->cvt_setups, i, p) { if (p->stream_tag) really_cleanup_stream(codec, p); } } #endif /* * amp access functions */ /** * query_amp_caps - query AMP capabilities * @codec: the HD-auio codec * @nid: the NID to query * @direction: either #HDA_INPUT or #HDA_OUTPUT * * Query AMP capabilities for the given widget and direction. * Returns the obtained capability bits. * * When cap bits have been already read, this doesn't read again but * returns the cached value. */ u32 query_amp_caps(struct hda_codec *codec, hda_nid_t nid, int direction) { if (!(get_wcaps(codec, nid) & AC_WCAP_AMP_OVRD)) nid = codec->core.afg; return snd_hda_param_read(codec, nid, direction == HDA_OUTPUT ? AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); } EXPORT_SYMBOL_GPL(query_amp_caps); /** * snd_hda_check_amp_caps - query AMP capabilities * @codec: the HD-audio codec * @nid: the NID to query * @dir: either #HDA_INPUT or #HDA_OUTPUT * @bits: bit mask to check the result * * Check whether the widget has the given amp capability for the direction. */ bool snd_hda_check_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir, unsigned int bits) { if (!nid) return false; if (get_wcaps(codec, nid) & (1 << (dir + 1))) if (query_amp_caps(codec, nid, dir) & bits) return true; return false; } EXPORT_SYMBOL_GPL(snd_hda_check_amp_caps); /** * snd_hda_override_amp_caps - Override the AMP capabilities * @codec: the CODEC to clean up * @nid: the NID to clean up * @dir: either #HDA_INPUT or #HDA_OUTPUT * @caps: the capability bits to set * * Override the cached AMP caps bits value by the given one. * This function is useful if the driver needs to adjust the AMP ranges, * e.g. limit to 0dB, etc. * * Returns zero if successful or a negative error code. */ int snd_hda_override_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir, unsigned int caps) { unsigned int parm; snd_hda_override_wcaps(codec, nid, get_wcaps(codec, nid) | AC_WCAP_AMP_OVRD); parm = dir == HDA_OUTPUT ? AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP; return snd_hdac_override_parm(&codec->core, nid, parm, caps); } EXPORT_SYMBOL_GPL(snd_hda_override_amp_caps); static unsigned int encode_amp(struct hda_codec *codec, hda_nid_t nid, int ch, int dir, int idx) { unsigned int cmd = snd_hdac_regmap_encode_amp(nid, ch, dir, idx); /* enable fake mute if no h/w mute but min=mute */ if ((query_amp_caps(codec, nid, dir) & (AC_AMPCAP_MUTE | AC_AMPCAP_MIN_MUTE)) == AC_AMPCAP_MIN_MUTE) cmd |= AC_AMP_FAKE_MUTE; return cmd; } /** * snd_hda_codec_amp_update - update the AMP mono value * @codec: HD-audio codec * @nid: NID to read the AMP value * @ch: channel to update (0 or 1) * @dir: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Update the AMP values for the given channel, direction and index. */ int snd_hda_codec_amp_update(struct hda_codec *codec, hda_nid_t nid, int ch, int dir, int idx, int mask, int val) { unsigned int cmd = encode_amp(codec, nid, ch, dir, idx); return snd_hdac_regmap_update_raw(&codec->core, cmd, mask, val); } EXPORT_SYMBOL_GPL(snd_hda_codec_amp_update); /** * snd_hda_codec_amp_stereo - update the AMP stereo values * @codec: HD-audio codec * @nid: NID to read the AMP value * @direction: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Update the AMP values like snd_hda_codec_amp_update(), but for a * stereo widget with the same mask and value. */ int snd_hda_codec_amp_stereo(struct hda_codec *codec, hda_nid_t nid, int direction, int idx, int mask, int val) { int ch, ret = 0; if (snd_BUG_ON(mask & ~0xff)) mask &= 0xff; for (ch = 0; ch < 2; ch++) ret |= snd_hda_codec_amp_update(codec, nid, ch, direction, idx, mask, val); return ret; } EXPORT_SYMBOL_GPL(snd_hda_codec_amp_stereo); /** * snd_hda_codec_amp_init - initialize the AMP value * @codec: the HDA codec * @nid: NID to read the AMP value * @ch: channel (left=0 or right=1) * @dir: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Works like snd_hda_codec_amp_update() but it writes the value only at * the first access. If the amp was already initialized / updated beforehand, * this does nothing. */ int snd_hda_codec_amp_init(struct hda_codec *codec, hda_nid_t nid, int ch, int dir, int idx, int mask, int val) { unsigned int cmd = encode_amp(codec, nid, ch, dir, idx); if (!codec->core.regmap) return -EINVAL; return snd_hdac_regmap_update_raw_once(&codec->core, cmd, mask, val); } EXPORT_SYMBOL_GPL(snd_hda_codec_amp_init); /** * snd_hda_codec_amp_init_stereo - initialize the stereo AMP value * @codec: the HDA codec * @nid: NID to read the AMP value * @dir: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Call snd_hda_codec_amp_init() for both stereo channels. */ int snd_hda_codec_amp_init_stereo(struct hda_codec *codec, hda_nid_t nid, int dir, int idx, int mask, int val) { int ch, ret = 0; if (snd_BUG_ON(mask & ~0xff)) mask &= 0xff; for (ch = 0; ch < 2; ch++) ret |= snd_hda_codec_amp_init(codec, nid, ch, dir, idx, mask, val); return ret; } EXPORT_SYMBOL_GPL(snd_hda_codec_amp_init_stereo); static u32 get_amp_max_value(struct hda_codec *codec, hda_nid_t nid, int dir, unsigned int ofs) { u32 caps = query_amp_caps(codec, nid, dir); /* get num steps */ caps = (caps & AC_AMPCAP_NUM_STEPS) >> AC_AMPCAP_NUM_STEPS_SHIFT; if (ofs < caps) caps -= ofs; return caps; } /** * snd_hda_mixer_amp_volume_info - Info callback for a standard AMP mixer * @kcontrol: referred ctl element * @uinfo: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); u16 nid = get_amp_nid(kcontrol); u8 chs = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); unsigned int ofs = get_amp_offset(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = get_amp_max_value(codec, nid, dir, ofs); if (!uinfo->value.integer.max) { codec_warn(codec, "num_steps = 0 for NID=0x%x (ctl = %s)\n", nid, kcontrol->id.name); return -EINVAL; } return 0; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_volume_info); static inline unsigned int read_amp_value(struct hda_codec *codec, hda_nid_t nid, int ch, int dir, int idx, unsigned int ofs) { unsigned int val; val = snd_hda_codec_amp_read(codec, nid, ch, dir, idx); val &= HDA_AMP_VOLMASK; if (val >= ofs) val -= ofs; else val = 0; return val; } static inline int update_amp_value(struct hda_codec *codec, hda_nid_t nid, int ch, int dir, int idx, unsigned int ofs, unsigned int val) { unsigned int maxval; if (val > 0) val += ofs; /* ofs = 0: raw max value */ maxval = get_amp_max_value(codec, nid, dir, 0); if (val > maxval) val = maxval; return snd_hda_codec_amp_update(codec, nid, ch, dir, idx, HDA_AMP_VOLMASK, val); } /** * snd_hda_mixer_amp_volume_get - Get callback for a standard AMP mixer volume * @kcontrol: ctl element * @ucontrol: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); int chs = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); int idx = get_amp_index(kcontrol); unsigned int ofs = get_amp_offset(kcontrol); long *valp = ucontrol->value.integer.value; if (chs & 1) *valp++ = read_amp_value(codec, nid, 0, dir, idx, ofs); if (chs & 2) *valp = read_amp_value(codec, nid, 1, dir, idx, ofs); return 0; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_volume_get); /** * snd_hda_mixer_amp_volume_put - Put callback for a standard AMP mixer volume * @kcontrol: ctl element * @ucontrol: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); int chs = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); int idx = get_amp_index(kcontrol); unsigned int ofs = get_amp_offset(kcontrol); long *valp = ucontrol->value.integer.value; int change = 0; if (chs & 1) { change = update_amp_value(codec, nid, 0, dir, idx, ofs, *valp); valp++; } if (chs & 2) change |= update_amp_value(codec, nid, 1, dir, idx, ofs, *valp); return change; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_volume_put); /* inquiry the amp caps and convert to TLV */ static void get_ctl_amp_tlv(struct snd_kcontrol *kcontrol, unsigned int *tlv) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); int dir = get_amp_direction(kcontrol); unsigned int ofs = get_amp_offset(kcontrol); bool min_mute = get_amp_min_mute(kcontrol); u32 caps, val1, val2; caps = query_amp_caps(codec, nid, dir); val2 = (caps & AC_AMPCAP_STEP_SIZE) >> AC_AMPCAP_STEP_SIZE_SHIFT; val2 = (val2 + 1) * 25; val1 = -((caps & AC_AMPCAP_OFFSET) >> AC_AMPCAP_OFFSET_SHIFT); val1 += ofs; val1 = ((int)val1) * ((int)val2); if (min_mute || (caps & AC_AMPCAP_MIN_MUTE)) val2 |= TLV_DB_SCALE_MUTE; tlv[SNDRV_CTL_TLVO_TYPE] = SNDRV_CTL_TLVT_DB_SCALE; tlv[SNDRV_CTL_TLVO_LEN] = 2 * sizeof(unsigned int); tlv[SNDRV_CTL_TLVO_DB_SCALE_MIN] = val1; tlv[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP] = val2; } /** * snd_hda_mixer_amp_tlv - TLV callback for a standard AMP mixer volume * @kcontrol: ctl element * @op_flag: operation flag * @size: byte size of input TLV * @_tlv: TLV data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_tlv(struct snd_kcontrol *kcontrol, int op_flag, unsigned int size, unsigned int __user *_tlv) { unsigned int tlv[4]; if (size < 4 * sizeof(unsigned int)) return -ENOMEM; get_ctl_amp_tlv(kcontrol, tlv); if (copy_to_user(_tlv, tlv, sizeof(tlv))) return -EFAULT; return 0; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_tlv); /** * snd_hda_set_vmaster_tlv - Set TLV for a virtual master control * @codec: HD-audio codec * @nid: NID of a reference widget * @dir: #HDA_INPUT or #HDA_OUTPUT * @tlv: TLV data to be stored, at least 4 elements * * Set (static) TLV data for a virtual master volume using the AMP caps * obtained from the reference NID. * The volume range is recalculated as if the max volume is 0dB. */ void snd_hda_set_vmaster_tlv(struct hda_codec *codec, hda_nid_t nid, int dir, unsigned int *tlv) { u32 caps; int nums, step; caps = query_amp_caps(codec, nid, dir); nums = (caps & AC_AMPCAP_NUM_STEPS) >> AC_AMPCAP_NUM_STEPS_SHIFT; step = (caps & AC_AMPCAP_STEP_SIZE) >> AC_AMPCAP_STEP_SIZE_SHIFT; step = (step + 1) * 25; tlv[SNDRV_CTL_TLVO_TYPE] = SNDRV_CTL_TLVT_DB_SCALE; tlv[SNDRV_CTL_TLVO_LEN] = 2 * sizeof(unsigned int); tlv[SNDRV_CTL_TLVO_DB_SCALE_MIN] = -nums * step; tlv[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP] = step; } EXPORT_SYMBOL_GPL(snd_hda_set_vmaster_tlv); /* find a mixer control element with the given name */ static struct snd_kcontrol * find_mixer_ctl(struct hda_codec *codec, const char *name, int dev, int idx) { struct snd_ctl_elem_id id; memset(&id, 0, sizeof(id)); id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; id.device = dev; id.index = idx; if (snd_BUG_ON(strlen(name) >= sizeof(id.name))) return NULL; strcpy(id.name, name); return snd_ctl_find_id(codec->card, &id); } /** * snd_hda_find_mixer_ctl - Find a mixer control element with the given name * @codec: HD-audio codec * @name: ctl id name string * * Get the control element with the given id string and IFACE_MIXER. */ struct snd_kcontrol *snd_hda_find_mixer_ctl(struct hda_codec *codec, const char *name) { return find_mixer_ctl(codec, name, 0, 0); } EXPORT_SYMBOL_GPL(snd_hda_find_mixer_ctl); static int find_empty_mixer_ctl_idx(struct hda_codec *codec, const char *name, int start_idx) { int i, idx; /* 16 ctlrs should be large enough */ for (i = 0, idx = start_idx; i < 16; i++, idx++) { if (!find_mixer_ctl(codec, name, 0, idx)) return idx; } return -EBUSY; } /** * snd_hda_ctl_add - Add a control element and assign to the codec * @codec: HD-audio codec * @nid: corresponding NID (optional) * @kctl: the control element to assign * * Add the given control element to an array inside the codec instance. * All control elements belonging to a codec are supposed to be added * by this function so that a proper clean-up works at the free or * reconfiguration time. * * If non-zero @nid is passed, the NID is assigned to the control element. * The assignment is shown in the codec proc file. * * snd_hda_ctl_add() checks the control subdev id field whether * #HDA_SUBDEV_NID_FLAG bit is set. If set (and @nid is zero), the lower * bits value is taken as the NID to assign. The #HDA_NID_ITEM_AMP bit * specifies if kctl->private_value is a HDA amplifier value. */ int snd_hda_ctl_add(struct hda_codec *codec, hda_nid_t nid, struct snd_kcontrol *kctl) { int err; unsigned short flags = 0; struct hda_nid_item *item; if (kctl->id.subdevice & HDA_SUBDEV_AMP_FLAG) { flags |= HDA_NID_ITEM_AMP; if (nid == 0) nid = get_amp_nid_(kctl->private_value); } if ((kctl->id.subdevice & HDA_SUBDEV_NID_FLAG) != 0 && nid == 0) nid = kctl->id.subdevice & 0xffff; if (kctl->id.subdevice & (HDA_SUBDEV_NID_FLAG|HDA_SUBDEV_AMP_FLAG)) kctl->id.subdevice = 0; err = snd_ctl_add(codec->card, kctl); if (err < 0) return err; item = snd_array_new(&codec->mixers); if (!item) return -ENOMEM; item->kctl = kctl; item->nid = nid; item->flags = flags; return 0; } EXPORT_SYMBOL_GPL(snd_hda_ctl_add); /** * snd_hda_add_nid - Assign a NID to a control element * @codec: HD-audio codec * @nid: corresponding NID (optional) * @kctl: the control element to assign * @index: index to kctl * * Add the given control element to an array inside the codec instance. * This function is used when #snd_hda_ctl_add cannot be used for 1:1 * NID:KCTL mapping - for example "Capture Source" selector. */ int snd_hda_add_nid(struct hda_codec *codec, struct snd_kcontrol *kctl, unsigned int index, hda_nid_t nid) { struct hda_nid_item *item; if (nid > 0) { item = snd_array_new(&codec->nids); if (!item) return -ENOMEM; item->kctl = kctl; item->index = index; item->nid = nid; return 0; } codec_err(codec, "no NID for mapping control %s:%d:%d\n", kctl->id.name, kctl->id.index, index); return -EINVAL; } EXPORT_SYMBOL_GPL(snd_hda_add_nid); /** * snd_hda_ctls_clear - Clear all controls assigned to the given codec * @codec: HD-audio codec */ void snd_hda_ctls_clear(struct hda_codec *codec) { int i; struct hda_nid_item *items = codec->mixers.list; for (i = 0; i < codec->mixers.used; i++) snd_ctl_remove(codec->card, items[i].kctl); snd_array_free(&codec->mixers); snd_array_free(&codec->nids); } /** * snd_hda_lock_devices - pseudo device locking * @bus: the BUS * * toggle card->shutdown to allow/disallow the device access (as a hack) */ int snd_hda_lock_devices(struct hda_bus *bus) { struct snd_card *card = bus->card; struct hda_codec *codec; spin_lock(&card->files_lock); if (card->shutdown) goto err_unlock; card->shutdown = 1; if (!list_empty(&card->ctl_files)) goto err_clear; list_for_each_codec(codec, bus) { struct hda_pcm *cpcm; list_for_each_entry(cpcm, &codec->pcm_list_head, list) { if (!cpcm->pcm) continue; if (cpcm->pcm->streams[0].substream_opened || cpcm->pcm->streams[1].substream_opened) goto err_clear; } } spin_unlock(&card->files_lock); return 0; err_clear: card->shutdown = 0; err_unlock: spin_unlock(&card->files_lock); return -EINVAL; } EXPORT_SYMBOL_GPL(snd_hda_lock_devices); /** * snd_hda_unlock_devices - pseudo device unlocking * @bus: the BUS */ void snd_hda_unlock_devices(struct hda_bus *bus) { struct snd_card *card = bus->card; spin_lock(&card->files_lock); card->shutdown = 0; spin_unlock(&card->files_lock); } EXPORT_SYMBOL_GPL(snd_hda_unlock_devices); /** * snd_hda_codec_reset - Clear all objects assigned to the codec * @codec: HD-audio codec * * This frees the all PCM and control elements assigned to the codec, and * clears the caches and restores the pin default configurations. * * When a device is being used, it returns -EBSY. If successfully freed, * returns zero. */ int snd_hda_codec_reset(struct hda_codec *codec) { struct hda_bus *bus = codec->bus; if (snd_hda_lock_devices(bus) < 0) return -EBUSY; /* OK, let it free */ device_release_driver(hda_codec_dev(codec)); /* allow device access again */ snd_hda_unlock_devices(bus); return 0; } typedef int (*map_follower_func_t)(struct hda_codec *, void *, struct snd_kcontrol *); /* apply the function to all matching follower ctls in the mixer list */ static int map_followers(struct hda_codec *codec, const char * const *followers, const char *suffix, map_follower_func_t func, void *data) { struct hda_nid_item *items; const char * const *s; int i, err; items = codec->mixers.list; for (i = 0; i < codec->mixers.used; i++) { struct snd_kcontrol *sctl = items[i].kctl; if (!sctl || sctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER) continue; for (s = followers; *s; s++) { char tmpname[sizeof(sctl->id.name)]; const char *name = *s; if (suffix) { snprintf(tmpname, sizeof(tmpname), "%s %s", name, suffix); name = tmpname; } if (!strcmp(sctl->id.name, name)) { err = func(codec, data, sctl); if (err) return err; break; } } } return 0; } static int check_follower_present(struct hda_codec *codec, void *data, struct snd_kcontrol *sctl) { return 1; } /* call kctl->put with the given value(s) */ static int put_kctl_with_value(struct snd_kcontrol *kctl, int val) { struct snd_ctl_elem_value *ucontrol; ucontrol = kzalloc(sizeof(*ucontrol), GFP_KERNEL); if (!ucontrol) return -ENOMEM; ucontrol->value.integer.value[0] = val; ucontrol->value.integer.value[1] = val; kctl->put(kctl, ucontrol); kfree(ucontrol); return 0; } struct follower_init_arg { struct hda_codec *codec; int step; }; /* initialize the follower volume with 0dB via snd_ctl_apply_vmaster_followers() */ static int init_follower_0dB(struct snd_kcontrol *follower, struct snd_kcontrol *kctl, void *_arg) { struct follower_init_arg *arg = _arg; int _tlv[4]; const int *tlv = NULL; int step; int val; if (kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { if (kctl->tlv.c != snd_hda_mixer_amp_tlv) { codec_err(arg->codec, "Unexpected TLV callback for follower %s:%d\n", kctl->id.name, kctl->id.index); return 0; /* ignore */ } get_ctl_amp_tlv(kctl, _tlv); tlv = _tlv; } else if (kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_TLV_READ) tlv = kctl->tlv.p; if (!tlv || tlv[SNDRV_CTL_TLVO_TYPE] != SNDRV_CTL_TLVT_DB_SCALE) return 0; step = tlv[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP]; step &= ~TLV_DB_SCALE_MUTE; if (!step) return 0; if (arg->step && arg->step != step) { codec_err(arg->codec, "Mismatching dB step for vmaster follower (%d!=%d)\n", arg->step, step); return 0; } arg->step = step; val = -tlv[SNDRV_CTL_TLVO_DB_SCALE_MIN] / step; if (val > 0) { put_kctl_with_value(follower, val); return val; } return 0; } /* unmute the follower via snd_ctl_apply_vmaster_followers() */ static int init_follower_unmute(struct snd_kcontrol *follower, struct snd_kcontrol *kctl, void *_arg) { return put_kctl_with_value(follower, 1); } static int add_follower(struct hda_codec *codec, void *data, struct snd_kcontrol *follower) { return snd_ctl_add_follower(data, follower); } /** * __snd_hda_add_vmaster - create a virtual master control and add followers * @codec: HD-audio codec * @name: vmaster control name * @tlv: TLV data (optional) * @followers: follower control names (optional) * @suffix: suffix string to each follower name (optional) * @init_follower_vol: initialize followers to unmute/0dB * @access: kcontrol access rights * @ctl_ret: store the vmaster kcontrol in return * * Create a virtual master control with the given name. The TLV data * must be either NULL or a valid data. * * @followers is a NULL-terminated array of strings, each of which is a * follower control name. All controls with these names are assigned to * the new virtual master control. * * This function returns zero if successful or a negative error code. */ int __snd_hda_add_vmaster(struct hda_codec *codec, char *name, unsigned int *tlv, const char * const *followers, const char *suffix, bool init_follower_vol, unsigned int access, struct snd_kcontrol **ctl_ret) { struct snd_kcontrol *kctl; int err; if (ctl_ret) *ctl_ret = NULL; err = map_followers(codec, followers, suffix, check_follower_present, NULL); if (err != 1) { codec_dbg(codec, "No follower found for %s\n", name); return 0; } kctl = snd_ctl_make_virtual_master(name, tlv); if (!kctl) return -ENOMEM; kctl->vd[0].access |= access; err = snd_hda_ctl_add(codec, 0, kctl); if (err < 0) return err; err = map_followers(codec, followers, suffix, add_follower, kctl); if (err < 0) return err; /* init with master mute & zero volume */ put_kctl_with_value(kctl, 0); if (init_follower_vol) { struct follower_init_arg arg = { .codec = codec, .step = 0, }; snd_ctl_apply_vmaster_followers(kctl, tlv ? init_follower_0dB : init_follower_unmute, &arg); } if (ctl_ret) *ctl_ret = kctl; return 0; } EXPORT_SYMBOL_GPL(__snd_hda_add_vmaster); /* meta hook to call each driver's vmaster hook */ static void vmaster_hook(void *private_data, int enabled) { struct hda_vmaster_mute_hook *hook = private_data; hook->hook(hook->codec, enabled); } /** * snd_hda_add_vmaster_hook - Add a vmaster hw specific hook * @codec: the HDA codec * @hook: the vmaster hook object * * Add a hw specific hook (like EAPD) with the given vmaster switch kctl. */ int snd_hda_add_vmaster_hook(struct hda_codec *codec, struct hda_vmaster_mute_hook *hook) { if (!hook->hook || !hook->sw_kctl) return 0; hook->codec = codec; snd_ctl_add_vmaster_hook(hook->sw_kctl, vmaster_hook, hook); return 0; } EXPORT_SYMBOL_GPL(snd_hda_add_vmaster_hook); /** * snd_hda_sync_vmaster_hook - Sync vmaster hook * @hook: the vmaster hook * * Call the hook with the current value for synchronization. * Should be called in init callback. */ void snd_hda_sync_vmaster_hook(struct hda_vmaster_mute_hook *hook) { if (!hook->hook || !hook->codec) return; /* don't call vmaster hook in the destructor since it might have * been already destroyed */ if (hook->codec->bus->shutdown) return; snd_ctl_sync_vmaster_hook(hook->sw_kctl); } EXPORT_SYMBOL_GPL(snd_hda_sync_vmaster_hook); /** * snd_hda_mixer_amp_switch_info - Info callback for a standard AMP mixer switch * @kcontrol: referred ctl element * @uinfo: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_switch_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int chs = get_amp_channels(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 1; return 0; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_info); /** * snd_hda_mixer_amp_switch_get - Get callback for a standard AMP mixer switch * @kcontrol: ctl element * @ucontrol: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); int chs = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); int idx = get_amp_index(kcontrol); long *valp = ucontrol->value.integer.value; if (chs & 1) *valp++ = (snd_hda_codec_amp_read(codec, nid, 0, dir, idx) & HDA_AMP_MUTE) ? 0 : 1; if (chs & 2) *valp = (snd_hda_codec_amp_read(codec, nid, 1, dir, idx) & HDA_AMP_MUTE) ? 0 : 1; return 0; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_get); /** * snd_hda_mixer_amp_switch_put - Put callback for a standard AMP mixer switch * @kcontrol: ctl element * @ucontrol: pointer to get/store the data * * The control element is supposed to have the private_value field * set up via HDA_COMPOSE_AMP_VAL*() or related macros. */ int snd_hda_mixer_amp_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); int chs = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); int idx = get_amp_index(kcontrol); long *valp = ucontrol->value.integer.value; int change = 0; if (chs & 1) { change = snd_hda_codec_amp_update(codec, nid, 0, dir, idx, HDA_AMP_MUTE, *valp ? 0 : HDA_AMP_MUTE); valp++; } if (chs & 2) change |= snd_hda_codec_amp_update(codec, nid, 1, dir, idx, HDA_AMP_MUTE, *valp ? 0 : HDA_AMP_MUTE); hda_call_check_power_status(codec, nid); return change; } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_put); /* * SPDIF out controls */ static int snd_hda_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_hda_spdif_cmask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_NONAUDIO | IEC958_AES0_CON_EMPHASIS_5015 | IEC958_AES0_CON_NOT_COPYRIGHT; ucontrol->value.iec958.status[1] = IEC958_AES1_CON_CATEGORY | IEC958_AES1_CON_ORIGINAL; return 0; } static int snd_hda_spdif_pmask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_NONAUDIO | IEC958_AES0_PRO_EMPHASIS_5015; return 0; } static int snd_hda_spdif_default_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); int idx = kcontrol->private_value; struct hda_spdif_out *spdif; if (WARN_ON(codec->spdif_out.used <= idx)) return -EINVAL; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); ucontrol->value.iec958.status[0] = spdif->status & 0xff; ucontrol->value.iec958.status[1] = (spdif->status >> 8) & 0xff; ucontrol->value.iec958.status[2] = (spdif->status >> 16) & 0xff; ucontrol->value.iec958.status[3] = (spdif->status >> 24) & 0xff; mutex_unlock(&codec->spdif_mutex); return 0; } /* convert from SPDIF status bits to HDA SPDIF bits * bit 0 (DigEn) is always set zero (to be filled later) */ static unsigned short convert_from_spdif_status(unsigned int sbits) { unsigned short val = 0; if (sbits & IEC958_AES0_PROFESSIONAL) val |= AC_DIG1_PROFESSIONAL; if (sbits & IEC958_AES0_NONAUDIO) val |= AC_DIG1_NONAUDIO; if (sbits & IEC958_AES0_PROFESSIONAL) { if ((sbits & IEC958_AES0_PRO_EMPHASIS) == IEC958_AES0_PRO_EMPHASIS_5015) val |= AC_DIG1_EMPHASIS; } else { if ((sbits & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_5015) val |= AC_DIG1_EMPHASIS; if (!(sbits & IEC958_AES0_CON_NOT_COPYRIGHT)) val |= AC_DIG1_COPYRIGHT; if (sbits & (IEC958_AES1_CON_ORIGINAL << 8)) val |= AC_DIG1_LEVEL; val |= sbits & (IEC958_AES1_CON_CATEGORY << 8); } return val; } /* convert to SPDIF status bits from HDA SPDIF bits */ static unsigned int convert_to_spdif_status(unsigned short val) { unsigned int sbits = 0; if (val & AC_DIG1_NONAUDIO) sbits |= IEC958_AES0_NONAUDIO; if (val & AC_DIG1_PROFESSIONAL) sbits |= IEC958_AES0_PROFESSIONAL; if (sbits & IEC958_AES0_PROFESSIONAL) { if (val & AC_DIG1_EMPHASIS) sbits |= IEC958_AES0_PRO_EMPHASIS_5015; } else { if (val & AC_DIG1_EMPHASIS) sbits |= IEC958_AES0_CON_EMPHASIS_5015; if (!(val & AC_DIG1_COPYRIGHT)) sbits |= IEC958_AES0_CON_NOT_COPYRIGHT; if (val & AC_DIG1_LEVEL) sbits |= (IEC958_AES1_CON_ORIGINAL << 8); sbits |= val & (0x7f << 8); } return sbits; } /* set digital convert verbs both for the given NID and its followers */ static void set_dig_out(struct hda_codec *codec, hda_nid_t nid, int mask, int val) { const hda_nid_t *d; snd_hdac_regmap_update(&codec->core, nid, AC_VERB_SET_DIGI_CONVERT_1, mask, val); d = codec->follower_dig_outs; if (!d) return; for (; *d; d++) snd_hdac_regmap_update(&codec->core, *d, AC_VERB_SET_DIGI_CONVERT_1, mask, val); } static inline void set_dig_out_convert(struct hda_codec *codec, hda_nid_t nid, int dig1, int dig2) { unsigned int mask = 0; unsigned int val = 0; if (dig1 != -1) { mask |= 0xff; val = dig1; } if (dig2 != -1) { mask |= 0xff00; val |= dig2 << 8; } set_dig_out(codec, nid, mask, val); } static int snd_hda_spdif_default_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); int idx = kcontrol->private_value; struct hda_spdif_out *spdif; hda_nid_t nid; unsigned short val; int change; if (WARN_ON(codec->spdif_out.used <= idx)) return -EINVAL; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); nid = spdif->nid; spdif->status = ucontrol->value.iec958.status[0] | ((unsigned int)ucontrol->value.iec958.status[1] << 8) | ((unsigned int)ucontrol->value.iec958.status[2] << 16) | ((unsigned int)ucontrol->value.iec958.status[3] << 24); val = convert_from_spdif_status(spdif->status); val |= spdif->ctls & 1; change = spdif->ctls != val; spdif->ctls = val; if (change && nid != (u16)-1) set_dig_out_convert(codec, nid, val & 0xff, (val >> 8) & 0xff); mutex_unlock(&codec->spdif_mutex); return change; } #define snd_hda_spdif_out_switch_info snd_ctl_boolean_mono_info static int snd_hda_spdif_out_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); int idx = kcontrol->private_value; struct hda_spdif_out *spdif; if (WARN_ON(codec->spdif_out.used <= idx)) return -EINVAL; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); ucontrol->value.integer.value[0] = spdif->ctls & AC_DIG1_ENABLE; mutex_unlock(&codec->spdif_mutex); return 0; } static inline void set_spdif_ctls(struct hda_codec *codec, hda_nid_t nid, int dig1, int dig2) { set_dig_out_convert(codec, nid, dig1, dig2); /* unmute amp switch (if any) */ if ((get_wcaps(codec, nid) & AC_WCAP_OUT_AMP) && (dig1 & AC_DIG1_ENABLE)) snd_hda_codec_amp_stereo(codec, nid, HDA_OUTPUT, 0, HDA_AMP_MUTE, 0); } static int snd_hda_spdif_out_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); int idx = kcontrol->private_value; struct hda_spdif_out *spdif; hda_nid_t nid; unsigned short val; int change; if (WARN_ON(codec->spdif_out.used <= idx)) return -EINVAL; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); nid = spdif->nid; val = spdif->ctls & ~AC_DIG1_ENABLE; if (ucontrol->value.integer.value[0]) val |= AC_DIG1_ENABLE; change = spdif->ctls != val; spdif->ctls = val; if (change && nid != (u16)-1) set_spdif_ctls(codec, nid, val & 0xff, -1); mutex_unlock(&codec->spdif_mutex); return change; } static const struct snd_kcontrol_new dig_mixes[] = { { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), .info = snd_hda_spdif_mask_info, .get = snd_hda_spdif_cmask_get, }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), .info = snd_hda_spdif_mask_info, .get = snd_hda_spdif_pmask_get, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), .info = snd_hda_spdif_mask_info, .get = snd_hda_spdif_default_get, .put = snd_hda_spdif_default_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), .info = snd_hda_spdif_out_switch_info, .get = snd_hda_spdif_out_switch_get, .put = snd_hda_spdif_out_switch_put, }, { } /* end */ }; /** * snd_hda_create_dig_out_ctls - create Output SPDIF-related controls * @codec: the HDA codec * @associated_nid: NID that new ctls associated with * @cvt_nid: converter NID * @type: HDA_PCM_TYPE_* * Creates controls related with the digital output. * Called from each patch supporting the digital out. * * Returns 0 if successful, or a negative error code. */ int snd_hda_create_dig_out_ctls(struct hda_codec *codec, hda_nid_t associated_nid, hda_nid_t cvt_nid, int type) { int err; struct snd_kcontrol *kctl; const struct snd_kcontrol_new *dig_mix; int idx = 0; int val = 0; const int spdif_index = 16; struct hda_spdif_out *spdif; struct hda_bus *bus = codec->bus; if (bus->primary_dig_out_type == HDA_PCM_TYPE_HDMI && type == HDA_PCM_TYPE_SPDIF) { idx = spdif_index; } else if (bus->primary_dig_out_type == HDA_PCM_TYPE_SPDIF && type == HDA_PCM_TYPE_HDMI) { /* suppose a single SPDIF device */ for (dig_mix = dig_mixes; dig_mix->name; dig_mix++) { struct snd_ctl_elem_id id; kctl = find_mixer_ctl(codec, dig_mix->name, 0, 0); if (!kctl) break; id = kctl->id; id.index = spdif_index; snd_ctl_rename_id(codec->card, &kctl->id, &id); } bus->primary_dig_out_type = HDA_PCM_TYPE_HDMI; } if (!bus->primary_dig_out_type) bus->primary_dig_out_type = type; idx = find_empty_mixer_ctl_idx(codec, "IEC958 Playback Switch", idx); if (idx < 0) { codec_err(codec, "too many IEC958 outputs\n"); return -EBUSY; } spdif = snd_array_new(&codec->spdif_out); if (!spdif) return -ENOMEM; for (dig_mix = dig_mixes; dig_mix->name; dig_mix++) { kctl = snd_ctl_new1(dig_mix, codec); if (!kctl) return -ENOMEM; kctl->id.index = idx; kctl->private_value = codec->spdif_out.used - 1; err = snd_hda_ctl_add(codec, associated_nid, kctl); if (err < 0) return err; } spdif->nid = cvt_nid; snd_hdac_regmap_read(&codec->core, cvt_nid, AC_VERB_GET_DIGI_CONVERT_1, &val); spdif->ctls = val; spdif->status = convert_to_spdif_status(spdif->ctls); return 0; } EXPORT_SYMBOL_GPL(snd_hda_create_dig_out_ctls); /** * snd_hda_spdif_out_of_nid - get the hda_spdif_out entry from the given NID * @codec: the HDA codec * @nid: widget NID * * call within spdif_mutex lock */ struct hda_spdif_out *snd_hda_spdif_out_of_nid(struct hda_codec *codec, hda_nid_t nid) { struct hda_spdif_out *spdif; int i; snd_array_for_each(&codec->spdif_out, i, spdif) { if (spdif->nid == nid) return spdif; } return NULL; } EXPORT_SYMBOL_GPL(snd_hda_spdif_out_of_nid); /** * snd_hda_spdif_ctls_unassign - Unassign the given SPDIF ctl * @codec: the HDA codec * @idx: the SPDIF ctl index * * Unassign the widget from the given SPDIF control. */ void snd_hda_spdif_ctls_unassign(struct hda_codec *codec, int idx) { struct hda_spdif_out *spdif; if (WARN_ON(codec->spdif_out.used <= idx)) return; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); spdif->nid = (u16)-1; mutex_unlock(&codec->spdif_mutex); } EXPORT_SYMBOL_GPL(snd_hda_spdif_ctls_unassign); /** * snd_hda_spdif_ctls_assign - Assign the SPDIF controls to the given NID * @codec: the HDA codec * @idx: the SPDIF ctl idx * @nid: widget NID * * Assign the widget to the SPDIF control with the given index. */ void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid) { struct hda_spdif_out *spdif; unsigned short val; if (WARN_ON(codec->spdif_out.used <= idx)) return; mutex_lock(&codec->spdif_mutex); spdif = snd_array_elem(&codec->spdif_out, idx); if (spdif->nid != nid) { spdif->nid = nid; val = spdif->ctls; set_spdif_ctls(codec, nid, val & 0xff, (val >> 8) & 0xff); } mutex_unlock(&codec->spdif_mutex); } EXPORT_SYMBOL_GPL(snd_hda_spdif_ctls_assign); /* * SPDIF sharing with analog output */ static int spdif_share_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_multi_out *mout = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = mout->share_spdif; return 0; } static int spdif_share_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_multi_out *mout = snd_kcontrol_chip(kcontrol); mout->share_spdif = !!ucontrol->value.integer.value[0]; return 0; } static const struct snd_kcontrol_new spdif_share_sw = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "IEC958 Default PCM Playback Switch", .info = snd_ctl_boolean_mono_info, .get = spdif_share_sw_get, .put = spdif_share_sw_put, }; /** * snd_hda_create_spdif_share_sw - create Default PCM switch * @codec: the HDA codec * @mout: multi-out instance */ int snd_hda_create_spdif_share_sw(struct hda_codec *codec, struct hda_multi_out *mout) { struct snd_kcontrol *kctl; if (!mout->dig_out_nid) return 0; kctl = snd_ctl_new1(&spdif_share_sw, mout); if (!kctl) return -ENOMEM; /* ATTENTION: here mout is passed as private_data, instead of codec */ return snd_hda_ctl_add(codec, mout->dig_out_nid, kctl); } EXPORT_SYMBOL_GPL(snd_hda_create_spdif_share_sw); /* * SPDIF input */ #define snd_hda_spdif_in_switch_info snd_hda_spdif_out_switch_info static int snd_hda_spdif_in_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = codec->spdif_in_enable; return 0; } static int snd_hda_spdif_in_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = kcontrol->private_value; unsigned int val = !!ucontrol->value.integer.value[0]; int change; mutex_lock(&codec->spdif_mutex); change = codec->spdif_in_enable != val; if (change) { codec->spdif_in_enable = val; snd_hdac_regmap_write(&codec->core, nid, AC_VERB_SET_DIGI_CONVERT_1, val); } mutex_unlock(&codec->spdif_mutex); return change; } static int snd_hda_spdif_in_status_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = kcontrol->private_value; unsigned int val; unsigned int sbits; snd_hdac_regmap_read(&codec->core, nid, AC_VERB_GET_DIGI_CONVERT_1, &val); sbits = convert_to_spdif_status(val); ucontrol->value.iec958.status[0] = sbits; ucontrol->value.iec958.status[1] = sbits >> 8; ucontrol->value.iec958.status[2] = sbits >> 16; ucontrol->value.iec958.status[3] = sbits >> 24; return 0; } static const struct snd_kcontrol_new dig_in_ctls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, SWITCH), .info = snd_hda_spdif_in_switch_info, .get = snd_hda_spdif_in_switch_get, .put = snd_hda_spdif_in_switch_put, }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), .info = snd_hda_spdif_mask_info, .get = snd_hda_spdif_in_status_get, }, { } /* end */ }; /** * snd_hda_create_spdif_in_ctls - create Input SPDIF-related controls * @codec: the HDA codec * @nid: audio in widget NID * * Creates controls related with the SPDIF input. * Called from each patch supporting the SPDIF in. * * Returns 0 if successful, or a negative error code. */ int snd_hda_create_spdif_in_ctls(struct hda_codec *codec, hda_nid_t nid) { int err; struct snd_kcontrol *kctl; const struct snd_kcontrol_new *dig_mix; int idx; idx = find_empty_mixer_ctl_idx(codec, "IEC958 Capture Switch", 0); if (idx < 0) { codec_err(codec, "too many IEC958 inputs\n"); return -EBUSY; } for (dig_mix = dig_in_ctls; dig_mix->name; dig_mix++) { kctl = snd_ctl_new1(dig_mix, codec); if (!kctl) return -ENOMEM; kctl->private_value = nid; err = snd_hda_ctl_add(codec, nid, kctl); if (err < 0) return err; } codec->spdif_in_enable = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0) & AC_DIG1_ENABLE; return 0; } EXPORT_SYMBOL_GPL(snd_hda_create_spdif_in_ctls); /** * snd_hda_codec_set_power_to_all - Set the power state to all widgets * @codec: the HDA codec * @fg: function group (not used now) * @power_state: the power state to set (AC_PWRST_*) * * Set the given power state to all widgets that have the power control. * If the codec has power_filter set, it evaluates the power state and * filter out if it's unchanged as D3. */ void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg, unsigned int power_state) { hda_nid_t nid; for_each_hda_codec_node(nid, codec) { unsigned int wcaps = get_wcaps(codec, nid); unsigned int state = power_state; if (!(wcaps & AC_WCAP_POWER)) continue; if (codec->power_filter) { state = codec->power_filter(codec, nid, power_state); if (state != power_state && power_state == AC_PWRST_D3) continue; } snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, state); } } EXPORT_SYMBOL_GPL(snd_hda_codec_set_power_to_all); /** * snd_hda_codec_eapd_power_filter - A power filter callback for EAPD * @codec: the HDA codec * @nid: widget NID * @power_state: power state to evalue * * Don't power down the widget if it controls eapd and EAPD_BTLENABLE is set. * This can be used a codec power_filter callback. */ unsigned int snd_hda_codec_eapd_power_filter(struct hda_codec *codec, hda_nid_t nid, unsigned int power_state) { if (nid == codec->core.afg || nid == codec->core.mfg) return power_state; if (power_state == AC_PWRST_D3 && get_wcaps_type(get_wcaps(codec, nid)) == AC_WID_PIN && (snd_hda_query_pin_caps(codec, nid) & AC_PINCAP_EAPD)) { int eapd = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_EAPD_BTLENABLE, 0); if (eapd & 0x02) return AC_PWRST_D0; } return power_state; } EXPORT_SYMBOL_GPL(snd_hda_codec_eapd_power_filter); /* * set power state of the codec, and return the power state */ static unsigned int hda_set_power_state(struct hda_codec *codec, unsigned int power_state) { hda_nid_t fg = codec->core.afg ? codec->core.afg : codec->core.mfg; int count; unsigned int state; int flags = 0; /* this delay seems necessary to avoid click noise at power-down */ if (power_state == AC_PWRST_D3) { if (codec->depop_delay < 0) msleep(codec_has_epss(codec) ? 10 : 100); else if (codec->depop_delay > 0) msleep(codec->depop_delay); flags = HDA_RW_NO_RESPONSE_FALLBACK; } /* repeat power states setting at most 10 times*/ for (count = 0; count < 10; count++) { if (codec->patch_ops.set_power_state) codec->patch_ops.set_power_state(codec, fg, power_state); else { state = power_state; if (codec->power_filter) state = codec->power_filter(codec, fg, state); if (state == power_state || power_state != AC_PWRST_D3) snd_hda_codec_read(codec, fg, flags, AC_VERB_SET_POWER_STATE, state); snd_hda_codec_set_power_to_all(codec, fg, power_state); } state = snd_hda_sync_power_state(codec, fg, power_state); if (!(state & AC_PWRST_ERROR)) break; } return state; } /* sync power states of all widgets; * this is called at the end of codec parsing */ static void sync_power_up_states(struct hda_codec *codec) { hda_nid_t nid; /* don't care if no filter is used */ if (!codec->power_filter) return; for_each_hda_codec_node(nid, codec) { unsigned int wcaps = get_wcaps(codec, nid); unsigned int target; if (!(wcaps & AC_WCAP_POWER)) continue; target = codec->power_filter(codec, nid, AC_PWRST_D0); if (target == AC_PWRST_D0) continue; if (!snd_hda_check_power_state(codec, nid, target)) snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, target); } } #ifdef CONFIG_SND_HDA_RECONFIG /* execute additional init verbs */ static void hda_exec_init_verbs(struct hda_codec *codec) { if (codec->init_verbs.list) snd_hda_sequence_write(codec, codec->init_verbs.list); } #else static inline void hda_exec_init_verbs(struct hda_codec *codec) {} #endif #ifdef CONFIG_PM /* update the power on/off account with the current jiffies */ static void update_power_acct(struct hda_codec *codec, bool on) { unsigned long delta = jiffies - codec->power_jiffies; if (on) codec->power_on_acct += delta; else codec->power_off_acct += delta; codec->power_jiffies += delta; } void snd_hda_update_power_acct(struct hda_codec *codec) { update_power_acct(codec, hda_codec_is_power_on(codec)); } /* * call suspend and power-down; used both from PM and power-save * this function returns the power state in the end */ static unsigned int hda_call_codec_suspend(struct hda_codec *codec) { unsigned int state; snd_hdac_enter_pm(&codec->core); if (codec->patch_ops.suspend) codec->patch_ops.suspend(codec); if (!codec->no_stream_clean_at_suspend) hda_cleanup_all_streams(codec); state = hda_set_power_state(codec, AC_PWRST_D3); update_power_acct(codec, true); snd_hdac_leave_pm(&codec->core); return state; } /* * kick up codec; used both from PM and power-save */ static void hda_call_codec_resume(struct hda_codec *codec) { snd_hdac_enter_pm(&codec->core); if (codec->core.regmap) regcache_mark_dirty(codec->core.regmap); codec->power_jiffies = jiffies; hda_set_power_state(codec, AC_PWRST_D0); restore_shutup_pins(codec); hda_exec_init_verbs(codec); snd_hda_jack_set_dirty_all(codec); if (codec->patch_ops.resume) codec->patch_ops.resume(codec); else { if (codec->patch_ops.init) codec->patch_ops.init(codec); snd_hda_regmap_sync(codec); } if (codec->jackpoll_interval) hda_jackpoll_work(&codec->jackpoll_work.work); else snd_hda_jack_report_sync(codec); codec->core.dev.power.power_state = PMSG_ON; snd_hdac_leave_pm(&codec->core); } static int hda_codec_runtime_suspend(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); unsigned int state; /* Nothing to do if card registration fails and the component driver never probes */ if (!codec->card) return 0; cancel_delayed_work_sync(&codec->jackpoll_work); state = hda_call_codec_suspend(codec); if (codec->link_down_at_suspend || (codec_has_clkstop(codec) && codec_has_epss(codec) && (state & AC_PWRST_CLK_STOP_OK))) snd_hdac_codec_link_down(&codec->core); snd_hda_codec_display_power(codec, false); if (codec->bus->jackpoll_in_suspend && (dev->power.power_state.event != PM_EVENT_SUSPEND)) schedule_delayed_work(&codec->jackpoll_work, codec->jackpoll_interval); return 0; } static int hda_codec_runtime_resume(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); /* Nothing to do if card registration fails and the component driver never probes */ if (!codec->card) return 0; snd_hda_codec_display_power(codec, true); snd_hdac_codec_link_up(&codec->core); hda_call_codec_resume(codec); pm_runtime_mark_last_busy(dev); return 0; } #endif /* CONFIG_PM */ #ifdef CONFIG_PM_SLEEP static int hda_codec_pm_prepare(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); cancel_delayed_work_sync(&codec->jackpoll_work); dev->power.power_state = PMSG_SUSPEND; return pm_runtime_suspended(dev); } static void hda_codec_pm_complete(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); /* If no other pm-functions are called between prepare() and complete() */ if (dev->power.power_state.event == PM_EVENT_SUSPEND) dev->power.power_state = PMSG_RESUME; if (pm_runtime_suspended(dev) && (codec->jackpoll_interval || hda_codec_need_resume(codec) || codec->forced_resume)) pm_request_resume(dev); } static int hda_codec_pm_suspend(struct device *dev) { dev->power.power_state = PMSG_SUSPEND; return pm_runtime_force_suspend(dev); } static int hda_codec_pm_resume(struct device *dev) { dev->power.power_state = PMSG_RESUME; return pm_runtime_force_resume(dev); } static int hda_codec_pm_freeze(struct device *dev) { struct hda_codec *codec = dev_to_hda_codec(dev); cancel_delayed_work_sync(&codec->jackpoll_work); dev->power.power_state = PMSG_FREEZE; return pm_runtime_force_suspend(dev); } static int hda_codec_pm_thaw(struct device *dev) { dev->power.power_state = PMSG_THAW; return pm_runtime_force_resume(dev); } static int hda_codec_pm_restore(struct device *dev) { dev->power.power_state = PMSG_RESTORE; return pm_runtime_force_resume(dev); } #endif /* CONFIG_PM_SLEEP */ /* referred in hda_bind.c */ const struct dev_pm_ops hda_codec_driver_pm = { #ifdef CONFIG_PM_SLEEP .prepare = hda_codec_pm_prepare, .complete = hda_codec_pm_complete, .suspend = hda_codec_pm_suspend, .resume = hda_codec_pm_resume, .freeze = hda_codec_pm_freeze, .thaw = hda_codec_pm_thaw, .poweroff = hda_codec_pm_suspend, .restore = hda_codec_pm_restore, #endif /* CONFIG_PM_SLEEP */ SET_RUNTIME_PM_OPS(hda_codec_runtime_suspend, hda_codec_runtime_resume, NULL) }; /* suspend the codec at shutdown; called from driver's shutdown callback */ void snd_hda_codec_shutdown(struct hda_codec *codec) { struct hda_pcm *cpcm; /* Skip the shutdown if codec is not registered */ if (!codec->core.registered) return; cancel_delayed_work_sync(&codec->jackpoll_work); list_for_each_entry(cpcm, &codec->pcm_list_head, list) snd_pcm_suspend_all(cpcm->pcm); pm_runtime_force_suspend(hda_codec_dev(codec)); pm_runtime_disable(hda_codec_dev(codec)); } /* * add standard channel maps if not specified */ static int add_std_chmaps(struct hda_codec *codec) { struct hda_pcm *pcm; int str, err; list_for_each_entry(pcm, &codec->pcm_list_head, list) { for (str = 0; str < 2; str++) { struct hda_pcm_stream *hinfo = &pcm->stream[str]; struct snd_pcm_chmap *chmap; const struct snd_pcm_chmap_elem *elem; if (!pcm->pcm || pcm->own_chmap || !hinfo->substreams) continue; elem = hinfo->chmap ? hinfo->chmap : snd_pcm_std_chmaps; err = snd_pcm_add_chmap_ctls(pcm->pcm, str, elem, hinfo->channels_max, 0, &chmap); if (err < 0) return err; chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; } } return 0; } /* default channel maps for 2.1 speakers; * since HD-audio supports only stereo, odd number channels are omitted */ const struct snd_pcm_chmap_elem snd_pcm_2_1_chmaps[] = { { .channels = 2, .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, { .channels = 4, .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE, SNDRV_CHMAP_LFE } }, { } }; EXPORT_SYMBOL_GPL(snd_pcm_2_1_chmaps); int snd_hda_codec_build_controls(struct hda_codec *codec) { int err = 0; hda_exec_init_verbs(codec); /* continue to initialize... */ if (codec->patch_ops.init) err = codec->patch_ops.init(codec); if (!err && codec->patch_ops.build_controls) err = codec->patch_ops.build_controls(codec); if (err < 0) return err; /* we create chmaps here instead of build_pcms */ err = add_std_chmaps(codec); if (err < 0) return err; if (codec->jackpoll_interval) hda_jackpoll_work(&codec->jackpoll_work.work); else snd_hda_jack_report_sync(codec); /* call at the last init point */ sync_power_up_states(codec); return 0; } EXPORT_SYMBOL_GPL(snd_hda_codec_build_controls); /* * PCM stuff */ static int hda_pcm_default_open_close(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { return 0; } static int hda_pcm_default_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { snd_hda_codec_setup_stream(codec, hinfo->nid, stream_tag, 0, format); return 0; } static int hda_pcm_default_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { snd_hda_codec_cleanup_stream(codec, hinfo->nid); return 0; } static int set_pcm_default_values(struct hda_codec *codec, struct hda_pcm_stream *info) { int err; /* query support PCM information from the given NID */ if (info->nid && (!info->rates || !info->formats)) { err = snd_hda_query_supported_pcm(codec, info->nid, info->rates ? NULL : &info->rates, info->formats ? NULL : &info->formats, info->maxbps ? NULL : &info->maxbps); if (err < 0) return err; } if (info->ops.open == NULL) info->ops.open = hda_pcm_default_open_close; if (info->ops.close == NULL) info->ops.close = hda_pcm_default_open_close; if (info->ops.prepare == NULL) { if (snd_BUG_ON(!info->nid)) return -EINVAL; info->ops.prepare = hda_pcm_default_prepare; } if (info->ops.cleanup == NULL) { if (snd_BUG_ON(!info->nid)) return -EINVAL; info->ops.cleanup = hda_pcm_default_cleanup; } return 0; } /* * codec prepare/cleanup entries */ /** * snd_hda_codec_prepare - Prepare a stream * @codec: the HDA codec * @hinfo: PCM information * @stream: stream tag to assign * @format: format id to assign * @substream: PCM substream to assign * * Calls the prepare callback set by the codec with the given arguments. * Clean up the inactive streams when successful. */ int snd_hda_codec_prepare(struct hda_codec *codec, struct hda_pcm_stream *hinfo, unsigned int stream, unsigned int format, struct snd_pcm_substream *substream) { int ret; mutex_lock(&codec->bus->prepare_mutex); if (hinfo->ops.prepare) ret = hinfo->ops.prepare(hinfo, codec, stream, format, substream); else ret = -ENODEV; if (ret >= 0) purify_inactive_streams(codec); mutex_unlock(&codec->bus->prepare_mutex); return ret; } EXPORT_SYMBOL_GPL(snd_hda_codec_prepare); /** * snd_hda_codec_cleanup - Clean up stream resources * @codec: the HDA codec * @hinfo: PCM information * @substream: PCM substream * * Calls the cleanup callback set by the codec with the given arguments. */ void snd_hda_codec_cleanup(struct hda_codec *codec, struct hda_pcm_stream *hinfo, struct snd_pcm_substream *substream) { mutex_lock(&codec->bus->prepare_mutex); if (hinfo->ops.cleanup) hinfo->ops.cleanup(hinfo, codec, substream); mutex_unlock(&codec->bus->prepare_mutex); } EXPORT_SYMBOL_GPL(snd_hda_codec_cleanup); /* global */ const char *snd_hda_pcm_type_name[HDA_PCM_NTYPES] = { "Audio", "SPDIF", "HDMI", "Modem" }; /* * get the empty PCM device number to assign */ static int get_empty_pcm_device(struct hda_bus *bus, unsigned int type) { /* audio device indices; not linear to keep compatibility */ /* assigned to static slots up to dev#10; if more needed, assign * the later slot dynamically (when CONFIG_SND_DYNAMIC_MINORS=y) */ static const int audio_idx[HDA_PCM_NTYPES][5] = { [HDA_PCM_TYPE_AUDIO] = { 0, 2, 4, 5, -1 }, [HDA_PCM_TYPE_SPDIF] = { 1, -1 }, [HDA_PCM_TYPE_HDMI] = { 3, 7, 8, 9, -1 }, [HDA_PCM_TYPE_MODEM] = { 6, -1 }, }; int i; if (type >= HDA_PCM_NTYPES) { dev_err(bus->card->dev, "Invalid PCM type %d\n", type); return -EINVAL; } for (i = 0; audio_idx[type][i] >= 0; i++) { #ifndef CONFIG_SND_DYNAMIC_MINORS if (audio_idx[type][i] >= 8) break; #endif if (!test_and_set_bit(audio_idx[type][i], bus->pcm_dev_bits)) return audio_idx[type][i]; } #ifdef CONFIG_SND_DYNAMIC_MINORS /* non-fixed slots starting from 10 */ for (i = 10; i < 32; i++) { if (!test_and_set_bit(i, bus->pcm_dev_bits)) return i; } #endif dev_warn(bus->card->dev, "Too many %s devices\n", snd_hda_pcm_type_name[type]); #ifndef CONFIG_SND_DYNAMIC_MINORS dev_warn(bus->card->dev, "Consider building the kernel with CONFIG_SND_DYNAMIC_MINORS=y\n"); #endif return -EAGAIN; } /* call build_pcms ops of the given codec and set up the default parameters */ int snd_hda_codec_parse_pcms(struct hda_codec *codec) { struct hda_pcm *cpcm; int err; if (!list_empty(&codec->pcm_list_head)) return 0; /* already parsed */ if (!codec->patch_ops.build_pcms) return 0; err = codec->patch_ops.build_pcms(codec); if (err < 0) { codec_err(codec, "cannot build PCMs for #%d (error %d)\n", codec->core.addr, err); return err; } list_for_each_entry(cpcm, &codec->pcm_list_head, list) { int stream; for (stream = 0; stream < 2; stream++) { struct hda_pcm_stream *info = &cpcm->stream[stream]; if (!info->substreams) continue; err = set_pcm_default_values(codec, info); if (err < 0) { codec_warn(codec, "fail to setup default for PCM %s\n", cpcm->name); return err; } } } return 0; } EXPORT_SYMBOL_GPL(snd_hda_codec_parse_pcms); /* assign all PCMs of the given codec */ int snd_hda_codec_build_pcms(struct hda_codec *codec) { struct hda_bus *bus = codec->bus; struct hda_pcm *cpcm; int dev, err; err = snd_hda_codec_parse_pcms(codec); if (err < 0) return err; /* attach a new PCM streams */ list_for_each_entry(cpcm, &codec->pcm_list_head, list) { if (cpcm->pcm) continue; /* already attached */ if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams) continue; /* no substreams assigned */ dev = get_empty_pcm_device(bus, cpcm->pcm_type); if (dev < 0) { cpcm->device = SNDRV_PCM_INVALID_DEVICE; continue; /* no fatal error */ } cpcm->device = dev; err = snd_hda_attach_pcm_stream(bus, codec, cpcm); if (err < 0) { codec_err(codec, "cannot attach PCM stream %d for codec #%d\n", dev, codec->core.addr); continue; /* no fatal error */ } } return 0; } /** * snd_hda_add_new_ctls - create controls from the array * @codec: the HDA codec * @knew: the array of struct snd_kcontrol_new * * This helper function creates and add new controls in the given array. * The array must be terminated with an empty entry as terminator. * * Returns 0 if successful, or a negative error code. */ int snd_hda_add_new_ctls(struct hda_codec *codec, const struct snd_kcontrol_new *knew) { int err; for (; knew->name; knew++) { struct snd_kcontrol *kctl; int addr = 0, idx = 0; if (knew->iface == (__force snd_ctl_elem_iface_t)-1) continue; /* skip this codec private value */ for (;;) { kctl = snd_ctl_new1(knew, codec); if (!kctl) return -ENOMEM; /* Do not use the id.device field for MIXER elements. * This field is for real device numbers (like PCM) but codecs * are hidden components from the user space view (unrelated * to the mixer element identification). */ if (addr > 0 && codec->ctl_dev_id) kctl->id.device = addr; if (idx > 0) kctl->id.index = idx; err = snd_hda_ctl_add(codec, 0, kctl); if (!err) break; /* try first with another device index corresponding to * the codec addr; if it still fails (or it's the * primary codec), then try another control index */ if (!addr && codec->core.addr) { addr = codec->core.addr; if (!codec->ctl_dev_id) idx += 10 * addr; } else if (!idx && !knew->index) { idx = find_empty_mixer_ctl_idx(codec, knew->name, 0); if (idx <= 0) return err; } else return err; } } return 0; } EXPORT_SYMBOL_GPL(snd_hda_add_new_ctls); #ifdef CONFIG_PM /** * snd_hda_codec_set_power_save - Configure codec's runtime PM * @codec: codec device to configure * @delay: autosuspend delay */ void snd_hda_codec_set_power_save(struct hda_codec *codec, int delay) { struct device *dev = hda_codec_dev(codec); if (delay == 0 && codec->auto_runtime_pm) delay = 3000; if (delay > 0) { pm_runtime_set_autosuspend_delay(dev, delay); pm_runtime_use_autosuspend(dev); pm_runtime_allow(dev); if (!pm_runtime_suspended(dev)) pm_runtime_mark_last_busy(dev); } else { pm_runtime_dont_use_autosuspend(dev); pm_runtime_forbid(dev); } } EXPORT_SYMBOL_GPL(snd_hda_codec_set_power_save); /** * snd_hda_set_power_save - reprogram autosuspend for the given delay * @bus: HD-audio bus * @delay: autosuspend delay in msec, 0 = off * * Synchronize the runtime PM autosuspend state from the power_save option. */ void snd_hda_set_power_save(struct hda_bus *bus, int delay) { struct hda_codec *c; list_for_each_codec(c, bus) snd_hda_codec_set_power_save(c, delay); } EXPORT_SYMBOL_GPL(snd_hda_set_power_save); /** * snd_hda_check_amp_list_power - Check the amp list and update the power * @codec: HD-audio codec * @check: the object containing an AMP list and the status * @nid: NID to check / update * * Check whether the given NID is in the amp list. If it's in the list, * check the current AMP status, and update the power-status according * to the mute status. * * This function is supposed to be set or called from the check_power_status * patch ops. */ int snd_hda_check_amp_list_power(struct hda_codec *codec, struct hda_loopback_check *check, hda_nid_t nid) { const struct hda_amp_list *p; int ch, v; if (!check->amplist) return 0; for (p = check->amplist; p->nid; p++) { if (p->nid == nid) break; } if (!p->nid) return 0; /* nothing changed */ for (p = check->amplist; p->nid; p++) { for (ch = 0; ch < 2; ch++) { v = snd_hda_codec_amp_read(codec, p->nid, ch, p->dir, p->idx); if (!(v & HDA_AMP_MUTE) && v > 0) { if (!check->power_on) { check->power_on = 1; snd_hda_power_up_pm(codec); } return 1; } } } if (check->power_on) { check->power_on = 0; snd_hda_power_down_pm(codec); } return 0; } EXPORT_SYMBOL_GPL(snd_hda_check_amp_list_power); #endif /* * input MUX helper */ /** * snd_hda_input_mux_info - Info callback helper for the input-mux enum * @imux: imux helper object * @uinfo: pointer to get/store the data */ int snd_hda_input_mux_info(const struct hda_input_mux *imux, struct snd_ctl_elem_info *uinfo) { unsigned int index; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = imux->num_items; if (!imux->num_items) return 0; index = uinfo->value.enumerated.item; if (index >= imux->num_items) index = imux->num_items - 1; strcpy(uinfo->value.enumerated.name, imux->items[index].label); return 0; } EXPORT_SYMBOL_GPL(snd_hda_input_mux_info); /** * snd_hda_input_mux_put - Put callback helper for the input-mux enum * @codec: the HDA codec * @imux: imux helper object * @ucontrol: pointer to get/store the data * @nid: input mux NID * @cur_val: pointer to get/store the current imux value */ int snd_hda_input_mux_put(struct hda_codec *codec, const struct hda_input_mux *imux, struct snd_ctl_elem_value *ucontrol, hda_nid_t nid, unsigned int *cur_val) { unsigned int idx; if (!imux->num_items) return 0; idx = ucontrol->value.enumerated.item[0]; if (idx >= imux->num_items) idx = imux->num_items - 1; if (*cur_val == idx) return 0; snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_CONNECT_SEL, imux->items[idx].index); *cur_val = idx; return 1; } EXPORT_SYMBOL_GPL(snd_hda_input_mux_put); /** * snd_hda_enum_helper_info - Helper for simple enum ctls * @kcontrol: ctl element * @uinfo: pointer to get/store the data * @num_items: number of enum items * @texts: enum item string array * * process kcontrol info callback of a simple string enum array * when @num_items is 0 or @texts is NULL, assume a boolean enum array */ int snd_hda_enum_helper_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo, int num_items, const char * const *texts) { static const char * const texts_default[] = { "Disabled", "Enabled" }; if (!texts || !num_items) { num_items = 2; texts = texts_default; } return snd_ctl_enum_info(uinfo, 1, num_items, texts); } EXPORT_SYMBOL_GPL(snd_hda_enum_helper_info); /* * Multi-channel / digital-out PCM helper functions */ /* setup SPDIF output stream */ static void setup_dig_out_stream(struct hda_codec *codec, hda_nid_t nid, unsigned int stream_tag, unsigned int format) { struct hda_spdif_out *spdif; unsigned int curr_fmt; bool reset; spdif = snd_hda_spdif_out_of_nid(codec, nid); /* Add sanity check to pass klockwork check. * This should never happen. */ if (WARN_ON(spdif == NULL)) return; curr_fmt = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_STREAM_FORMAT, 0); reset = codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE) && curr_fmt != format; /* turn off SPDIF if needed; otherwise the IEC958 bits won't be updated */ if (reset) set_dig_out_convert(codec, nid, spdif->ctls & ~AC_DIG1_ENABLE & 0xff, -1); snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format); if (codec->follower_dig_outs) { const hda_nid_t *d; for (d = codec->follower_dig_outs; *d; d++) snd_hda_codec_setup_stream(codec, *d, stream_tag, 0, format); } /* turn on again (if needed) */ if (reset) set_dig_out_convert(codec, nid, spdif->ctls & 0xff, -1); } static void cleanup_dig_out_stream(struct hda_codec *codec, hda_nid_t nid) { snd_hda_codec_cleanup_stream(codec, nid); if (codec->follower_dig_outs) { const hda_nid_t *d; for (d = codec->follower_dig_outs; *d; d++) snd_hda_codec_cleanup_stream(codec, *d); } } /** * snd_hda_multi_out_dig_open - open the digital out in the exclusive mode * @codec: the HDA codec * @mout: hda_multi_out object */ int snd_hda_multi_out_dig_open(struct hda_codec *codec, struct hda_multi_out *mout) { mutex_lock(&codec->spdif_mutex); if (mout->dig_out_used == HDA_DIG_ANALOG_DUP) /* already opened as analog dup; reset it once */ cleanup_dig_out_stream(codec, mout->dig_out_nid); mout->dig_out_used = HDA_DIG_EXCLUSIVE; mutex_unlock(&codec->spdif_mutex); return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_dig_open); /** * snd_hda_multi_out_dig_prepare - prepare the digital out stream * @codec: the HDA codec * @mout: hda_multi_out object * @stream_tag: stream tag to assign * @format: format id to assign * @substream: PCM substream to assign */ int snd_hda_multi_out_dig_prepare(struct hda_codec *codec, struct hda_multi_out *mout, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { mutex_lock(&codec->spdif_mutex); setup_dig_out_stream(codec, mout->dig_out_nid, stream_tag, format); mutex_unlock(&codec->spdif_mutex); return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_dig_prepare); /** * snd_hda_multi_out_dig_cleanup - clean-up the digital out stream * @codec: the HDA codec * @mout: hda_multi_out object */ int snd_hda_multi_out_dig_cleanup(struct hda_codec *codec, struct hda_multi_out *mout) { mutex_lock(&codec->spdif_mutex); cleanup_dig_out_stream(codec, mout->dig_out_nid); mutex_unlock(&codec->spdif_mutex); return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_dig_cleanup); /** * snd_hda_multi_out_dig_close - release the digital out stream * @codec: the HDA codec * @mout: hda_multi_out object */ int snd_hda_multi_out_dig_close(struct hda_codec *codec, struct hda_multi_out *mout) { mutex_lock(&codec->spdif_mutex); mout->dig_out_used = 0; mutex_unlock(&codec->spdif_mutex); return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_dig_close); /** * snd_hda_multi_out_analog_open - open analog outputs * @codec: the HDA codec * @mout: hda_multi_out object * @substream: PCM substream to assign * @hinfo: PCM information to assign * * Open analog outputs and set up the hw-constraints. * If the digital outputs can be opened as follower, open the digital * outputs, too. */ int snd_hda_multi_out_analog_open(struct hda_codec *codec, struct hda_multi_out *mout, struct snd_pcm_substream *substream, struct hda_pcm_stream *hinfo) { struct snd_pcm_runtime *runtime = substream->runtime; runtime->hw.channels_max = mout->max_channels; if (mout->dig_out_nid) { if (!mout->analog_rates) { mout->analog_rates = hinfo->rates; mout->analog_formats = hinfo->formats; mout->analog_maxbps = hinfo->maxbps; } else { runtime->hw.rates = mout->analog_rates; runtime->hw.formats = mout->analog_formats; hinfo->maxbps = mout->analog_maxbps; } if (!mout->spdif_rates) { snd_hda_query_supported_pcm(codec, mout->dig_out_nid, &mout->spdif_rates, &mout->spdif_formats, &mout->spdif_maxbps); } mutex_lock(&codec->spdif_mutex); if (mout->share_spdif) { if ((runtime->hw.rates & mout->spdif_rates) && (runtime->hw.formats & mout->spdif_formats)) { runtime->hw.rates &= mout->spdif_rates; runtime->hw.formats &= mout->spdif_formats; if (mout->spdif_maxbps < hinfo->maxbps) hinfo->maxbps = mout->spdif_maxbps; } else { mout->share_spdif = 0; /* FIXME: need notify? */ } } mutex_unlock(&codec->spdif_mutex); } return snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); } EXPORT_SYMBOL_GPL(snd_hda_multi_out_analog_open); /** * snd_hda_multi_out_analog_prepare - Preapre the analog outputs. * @codec: the HDA codec * @mout: hda_multi_out object * @stream_tag: stream tag to assign * @format: format id to assign * @substream: PCM substream to assign * * Set up the i/o for analog out. * When the digital out is available, copy the front out to digital out, too. */ int snd_hda_multi_out_analog_prepare(struct hda_codec *codec, struct hda_multi_out *mout, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { const hda_nid_t *nids = mout->dac_nids; int chs = substream->runtime->channels; struct hda_spdif_out *spdif; int i; mutex_lock(&codec->spdif_mutex); spdif = snd_hda_spdif_out_of_nid(codec, mout->dig_out_nid); if (mout->dig_out_nid && mout->share_spdif && mout->dig_out_used != HDA_DIG_EXCLUSIVE) { if (chs == 2 && spdif != NULL && snd_hda_is_supported_format(codec, mout->dig_out_nid, format) && !(spdif->status & IEC958_AES0_NONAUDIO)) { mout->dig_out_used = HDA_DIG_ANALOG_DUP; setup_dig_out_stream(codec, mout->dig_out_nid, stream_tag, format); } else { mout->dig_out_used = 0; cleanup_dig_out_stream(codec, mout->dig_out_nid); } } mutex_unlock(&codec->spdif_mutex); /* front */ snd_hda_codec_setup_stream(codec, nids[HDA_FRONT], stream_tag, 0, format); if (!mout->no_share_stream && mout->hp_nid && mout->hp_nid != nids[HDA_FRONT]) /* headphone out will just decode front left/right (stereo) */ snd_hda_codec_setup_stream(codec, mout->hp_nid, stream_tag, 0, format); /* extra outputs copied from front */ for (i = 0; i < ARRAY_SIZE(mout->hp_out_nid); i++) if (!mout->no_share_stream && mout->hp_out_nid[i]) snd_hda_codec_setup_stream(codec, mout->hp_out_nid[i], stream_tag, 0, format); /* surrounds */ for (i = 1; i < mout->num_dacs; i++) { if (chs >= (i + 1) * 2) /* independent out */ snd_hda_codec_setup_stream(codec, nids[i], stream_tag, i * 2, format); else if (!mout->no_share_stream) /* copy front */ snd_hda_codec_setup_stream(codec, nids[i], stream_tag, 0, format); } /* extra surrounds */ for (i = 0; i < ARRAY_SIZE(mout->extra_out_nid); i++) { int ch = 0; if (!mout->extra_out_nid[i]) break; if (chs >= (i + 1) * 2) ch = i * 2; else if (!mout->no_share_stream) break; snd_hda_codec_setup_stream(codec, mout->extra_out_nid[i], stream_tag, ch, format); } return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_analog_prepare); /** * snd_hda_multi_out_analog_cleanup - clean up the setting for analog out * @codec: the HDA codec * @mout: hda_multi_out object */ int snd_hda_multi_out_analog_cleanup(struct hda_codec *codec, struct hda_multi_out *mout) { const hda_nid_t *nids = mout->dac_nids; int i; for (i = 0; i < mout->num_dacs; i++) snd_hda_codec_cleanup_stream(codec, nids[i]); if (mout->hp_nid) snd_hda_codec_cleanup_stream(codec, mout->hp_nid); for (i = 0; i < ARRAY_SIZE(mout->hp_out_nid); i++) if (mout->hp_out_nid[i]) snd_hda_codec_cleanup_stream(codec, mout->hp_out_nid[i]); for (i = 0; i < ARRAY_SIZE(mout->extra_out_nid); i++) if (mout->extra_out_nid[i]) snd_hda_codec_cleanup_stream(codec, mout->extra_out_nid[i]); mutex_lock(&codec->spdif_mutex); if (mout->dig_out_nid && mout->dig_out_used == HDA_DIG_ANALOG_DUP) { cleanup_dig_out_stream(codec, mout->dig_out_nid); mout->dig_out_used = 0; } mutex_unlock(&codec->spdif_mutex); return 0; } EXPORT_SYMBOL_GPL(snd_hda_multi_out_analog_cleanup); /** * snd_hda_get_default_vref - Get the default (mic) VREF pin bits * @codec: the HDA codec * @pin: referred pin NID * * Guess the suitable VREF pin bits to be set as the pin-control value. * Note: the function doesn't set the AC_PINCTL_IN_EN bit. */ unsigned int snd_hda_get_default_vref(struct hda_codec *codec, hda_nid_t pin) { unsigned int pincap; unsigned int oldval; oldval = snd_hda_codec_read(codec, pin, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); pincap = snd_hda_query_pin_caps(codec, pin); pincap = (pincap & AC_PINCAP_VREF) >> AC_PINCAP_VREF_SHIFT; /* Exception: if the default pin setup is vref50, we give it priority */ if ((pincap & AC_PINCAP_VREF_80) && oldval != PIN_VREF50) return AC_PINCTL_VREF_80; else if (pincap & AC_PINCAP_VREF_50) return AC_PINCTL_VREF_50; else if (pincap & AC_PINCAP_VREF_100) return AC_PINCTL_VREF_100; else if (pincap & AC_PINCAP_VREF_GRD) return AC_PINCTL_VREF_GRD; return AC_PINCTL_VREF_HIZ; } EXPORT_SYMBOL_GPL(snd_hda_get_default_vref); /** * snd_hda_correct_pin_ctl - correct the pin ctl value for matching with the pin cap * @codec: the HDA codec * @pin: referred pin NID * @val: pin ctl value to audit */ unsigned int snd_hda_correct_pin_ctl(struct hda_codec *codec, hda_nid_t pin, unsigned int val) { static const unsigned int cap_lists[][2] = { { AC_PINCTL_VREF_100, AC_PINCAP_VREF_100 }, { AC_PINCTL_VREF_80, AC_PINCAP_VREF_80 }, { AC_PINCTL_VREF_50, AC_PINCAP_VREF_50 }, { AC_PINCTL_VREF_GRD, AC_PINCAP_VREF_GRD }, }; unsigned int cap; if (!val) return 0; cap = snd_hda_query_pin_caps(codec, pin); if (!cap) return val; /* don't know what to do... */ if (val & AC_PINCTL_OUT_EN) { if (!(cap & AC_PINCAP_OUT)) val &= ~(AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN); else if ((val & AC_PINCTL_HP_EN) && !(cap & AC_PINCAP_HP_DRV)) val &= ~AC_PINCTL_HP_EN; } if (val & AC_PINCTL_IN_EN) { if (!(cap & AC_PINCAP_IN)) val &= ~(AC_PINCTL_IN_EN | AC_PINCTL_VREFEN); else { unsigned int vcap, vref; int i; vcap = (cap & AC_PINCAP_VREF) >> AC_PINCAP_VREF_SHIFT; vref = val & AC_PINCTL_VREFEN; for (i = 0; i < ARRAY_SIZE(cap_lists); i++) { if (vref == cap_lists[i][0] && !(vcap & cap_lists[i][1])) { if (i == ARRAY_SIZE(cap_lists) - 1) vref = AC_PINCTL_VREF_HIZ; else vref = cap_lists[i + 1][0]; } } val &= ~AC_PINCTL_VREFEN; val |= vref; } } return val; } EXPORT_SYMBOL_GPL(snd_hda_correct_pin_ctl); /** * _snd_hda_set_pin_ctl - Helper to set pin ctl value * @codec: the HDA codec * @pin: referred pin NID * @val: pin control value to set * @cached: access over codec pinctl cache or direct write * * This function is a helper to set a pin ctl value more safely. * It corrects the pin ctl value via snd_hda_correct_pin_ctl(), stores the * value in pin target array via snd_hda_codec_set_pin_target(), then * actually writes the value via either snd_hda_codec_write_cache() or * snd_hda_codec_write() depending on @cached flag. */ int _snd_hda_set_pin_ctl(struct hda_codec *codec, hda_nid_t pin, unsigned int val, bool cached) { val = snd_hda_correct_pin_ctl(codec, pin, val); snd_hda_codec_set_pin_target(codec, pin, val); if (cached) return snd_hda_codec_write_cache(codec, pin, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, val); else return snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, val); } EXPORT_SYMBOL_GPL(_snd_hda_set_pin_ctl); /** * snd_hda_add_imux_item - Add an item to input_mux * @codec: the HDA codec * @imux: imux helper object * @label: the name of imux item to assign * @index: index number of imux item to assign * @type_idx: pointer to store the resultant label index * * When the same label is used already in the existing items, the number * suffix is appended to the label. This label index number is stored * to type_idx when non-NULL pointer is given. */ int snd_hda_add_imux_item(struct hda_codec *codec, struct hda_input_mux *imux, const char *label, int index, int *type_idx) { int i, label_idx = 0; if (imux->num_items >= HDA_MAX_NUM_INPUTS) { codec_err(codec, "hda_codec: Too many imux items!\n"); return -EINVAL; } for (i = 0; i < imux->num_items; i++) { if (!strncmp(label, imux->items[i].label, strlen(label))) label_idx++; } if (type_idx) *type_idx = label_idx; if (label_idx > 0) snprintf(imux->items[imux->num_items].label, sizeof(imux->items[imux->num_items].label), "%s %d", label, label_idx); else strscpy(imux->items[imux->num_items].label, label, sizeof(imux->items[imux->num_items].label)); imux->items[imux->num_items].index = index; imux->num_items++; return 0; } EXPORT_SYMBOL_GPL(snd_hda_add_imux_item); /** * snd_hda_bus_reset_codecs - Reset the bus * @bus: HD-audio bus */ void snd_hda_bus_reset_codecs(struct hda_bus *bus) { struct hda_codec *codec; list_for_each_codec(codec, bus) { /* FIXME: maybe a better way needed for forced reset */ if (current_work() != &codec->jackpoll_work.work) cancel_delayed_work_sync(&codec->jackpoll_work); #ifdef CONFIG_PM if (hda_codec_is_power_on(codec)) { hda_call_codec_suspend(codec); hda_call_codec_resume(codec); } #endif } } /** * snd_print_pcm_bits - Print the supported PCM fmt bits to the string buffer * @pcm: PCM caps bits * @buf: the string buffer to write * @buflen: the max buffer length * * used by hda_proc.c and hda_eld.c */ void snd_print_pcm_bits(int pcm, char *buf, int buflen) { static const unsigned int bits[] = { 8, 16, 20, 24, 32 }; int i, j; for (i = 0, j = 0; i < ARRAY_SIZE(bits); i++) if (pcm & (AC_SUPPCM_BITS_8 << i)) j += scnprintf(buf + j, buflen - j, " %d", bits[i]); buf[j] = '\0'; /* necessary when j == 0 */ } EXPORT_SYMBOL_GPL(snd_print_pcm_bits); MODULE_DESCRIPTION("HDA codec core"); MODULE_LICENSE("GPL");
linux-master
sound/pci/hda/hda_codec.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * BIOS auto-parser helper functions for HD-audio * * Copyright (c) 2012 Takashi Iwai <[email protected]> */ #include <linux/slab.h> #include <linux/export.h> #include <linux/sort.h> #include <sound/core.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" /* * Helper for automatic pin configuration */ static int is_in_nid_list(hda_nid_t nid, const hda_nid_t *list) { for (; *list; list++) if (*list == nid) return 1; return 0; } /* a pair of input pin and its sequence */ struct auto_out_pin { hda_nid_t pin; short seq; }; static int compare_seq(const void *ap, const void *bp) { const struct auto_out_pin *a = ap; const struct auto_out_pin *b = bp; return (int)(a->seq - b->seq); } /* * Sort an associated group of pins according to their sequence numbers. * then store it to a pin array. */ static void sort_pins_by_sequence(hda_nid_t *pins, struct auto_out_pin *list, int num_pins) { int i; sort(list, num_pins, sizeof(list[0]), compare_seq, NULL); for (i = 0; i < num_pins; i++) pins[i] = list[i].pin; } /* add the found input-pin to the cfg->inputs[] table */ static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, hda_nid_t nid, int type) { if (cfg->num_inputs < AUTO_CFG_MAX_INS) { cfg->inputs[cfg->num_inputs].pin = nid; cfg->inputs[cfg->num_inputs].type = type; cfg->inputs[cfg->num_inputs].has_boost_on_pin = nid_has_volume(codec, nid, HDA_INPUT); cfg->num_inputs++; } } static int compare_input_type(const void *ap, const void *bp) { const struct auto_pin_cfg_item *a = ap; const struct auto_pin_cfg_item *b = bp; if (a->type != b->type) return (int)(a->type - b->type); /* If has both hs_mic and hp_mic, pick the hs_mic ahead of hp_mic. */ if (a->is_headset_mic && b->is_headphone_mic) return -1; /* don't swap */ else if (a->is_headphone_mic && b->is_headset_mic) return 1; /* swap */ /* In case one has boost and the other one has not, pick the one with boost first. */ return (int)(b->has_boost_on_pin - a->has_boost_on_pin); } /* Reorder the surround channels * ALSA sequence is front/surr/clfe/side * HDA sequence is: * 4-ch: front/surr => OK as it is * 6-ch: front/clfe/surr * 8-ch: front/clfe/rear/side|fc */ static void reorder_outputs(unsigned int nums, hda_nid_t *pins) { switch (nums) { case 3: case 4: swap(pins[1], pins[2]); break; } } /* check whether the given pin has a proper pin I/O capability bit */ static bool check_pincap_validity(struct hda_codec *codec, hda_nid_t pin, unsigned int dev) { unsigned int pincap = snd_hda_query_pin_caps(codec, pin); /* some old hardware don't return the proper pincaps */ if (!pincap) return true; switch (dev) { case AC_JACK_LINE_OUT: case AC_JACK_SPEAKER: case AC_JACK_HP_OUT: case AC_JACK_SPDIF_OUT: case AC_JACK_DIG_OTHER_OUT: return !!(pincap & AC_PINCAP_OUT); default: return !!(pincap & AC_PINCAP_IN); } } static bool can_be_headset_mic(struct hda_codec *codec, struct auto_pin_cfg_item *item, int seq_number) { int attr; unsigned int def_conf; if (item->type != AUTO_PIN_MIC) return false; if (item->is_headset_mic || item->is_headphone_mic) return false; /* Already assigned */ def_conf = snd_hda_codec_get_pincfg(codec, item->pin); attr = snd_hda_get_input_pin_attr(def_conf); if (attr <= INPUT_PIN_ATTR_DOCK) return false; if (seq_number >= 0) { int seq = get_defcfg_sequence(def_conf); if (seq != seq_number) return false; } return true; } /* * Parse all pin widgets and store the useful pin nids to cfg * * The number of line-outs or any primary output is stored in line_outs, * and the corresponding output pins are assigned to line_out_pins[], * in the order of front, rear, CLFE, side, ... * * If more extra outputs (speaker and headphone) are found, the pins are * assisnged to hp_pins[] and speaker_pins[], respectively. If no line-out jack * is detected, one of speaker of HP pins is assigned as the primary * output, i.e. to line_out_pins[0]. So, line_outs is always positive * if any analog output exists. * * The analog input pins are assigned to inputs array. * The digital input/output pins are assigned to dig_in_pin and dig_out_pin, * respectively. */ int snd_hda_parse_pin_defcfg(struct hda_codec *codec, struct auto_pin_cfg *cfg, const hda_nid_t *ignore_nids, unsigned int cond_flags) { hda_nid_t nid; short seq, assoc_line_out; struct auto_out_pin line_out[ARRAY_SIZE(cfg->line_out_pins)]; struct auto_out_pin speaker_out[ARRAY_SIZE(cfg->speaker_pins)]; struct auto_out_pin hp_out[ARRAY_SIZE(cfg->hp_pins)]; int i; if (!snd_hda_get_int_hint(codec, "parser_flags", &i)) cond_flags = i; memset(cfg, 0, sizeof(*cfg)); memset(line_out, 0, sizeof(line_out)); memset(speaker_out, 0, sizeof(speaker_out)); memset(hp_out, 0, sizeof(hp_out)); assoc_line_out = 0; for_each_hda_codec_node(nid, codec) { unsigned int wid_caps = get_wcaps(codec, nid); unsigned int wid_type = get_wcaps_type(wid_caps); unsigned int def_conf; short assoc, loc, conn, dev; /* read all default configuration for pin complex */ if (wid_type != AC_WID_PIN) continue; /* ignore the given nids (e.g. pc-beep returns error) */ if (ignore_nids && is_in_nid_list(nid, ignore_nids)) continue; def_conf = snd_hda_codec_get_pincfg(codec, nid); conn = get_defcfg_connect(def_conf); if (conn == AC_JACK_PORT_NONE) continue; loc = get_defcfg_location(def_conf); dev = get_defcfg_device(def_conf); /* workaround for buggy BIOS setups */ if (dev == AC_JACK_LINE_OUT) { if (conn == AC_JACK_PORT_FIXED || conn == AC_JACK_PORT_BOTH) dev = AC_JACK_SPEAKER; } if (!check_pincap_validity(codec, nid, dev)) continue; switch (dev) { case AC_JACK_LINE_OUT: seq = get_defcfg_sequence(def_conf); assoc = get_defcfg_association(def_conf); if (!(wid_caps & AC_WCAP_STEREO)) if (!cfg->mono_out_pin) cfg->mono_out_pin = nid; if (!assoc) continue; if (!assoc_line_out) assoc_line_out = assoc; else if (assoc_line_out != assoc) { codec_info(codec, "ignore pin 0x%x with mismatching assoc# 0x%x vs 0x%x\n", nid, assoc, assoc_line_out); continue; } if (cfg->line_outs >= ARRAY_SIZE(cfg->line_out_pins)) { codec_info(codec, "ignore pin 0x%x, too many assigned pins\n", nid); continue; } line_out[cfg->line_outs].pin = nid; line_out[cfg->line_outs].seq = seq; cfg->line_outs++; break; case AC_JACK_SPEAKER: seq = get_defcfg_sequence(def_conf); assoc = get_defcfg_association(def_conf); if (cfg->speaker_outs >= ARRAY_SIZE(cfg->speaker_pins)) { codec_info(codec, "ignore pin 0x%x, too many assigned pins\n", nid); continue; } speaker_out[cfg->speaker_outs].pin = nid; speaker_out[cfg->speaker_outs].seq = (assoc << 4) | seq; cfg->speaker_outs++; break; case AC_JACK_HP_OUT: seq = get_defcfg_sequence(def_conf); assoc = get_defcfg_association(def_conf); if (cfg->hp_outs >= ARRAY_SIZE(cfg->hp_pins)) { codec_info(codec, "ignore pin 0x%x, too many assigned pins\n", nid); continue; } hp_out[cfg->hp_outs].pin = nid; hp_out[cfg->hp_outs].seq = (assoc << 4) | seq; cfg->hp_outs++; break; case AC_JACK_MIC_IN: add_auto_cfg_input_pin(codec, cfg, nid, AUTO_PIN_MIC); break; case AC_JACK_LINE_IN: add_auto_cfg_input_pin(codec, cfg, nid, AUTO_PIN_LINE_IN); break; case AC_JACK_CD: add_auto_cfg_input_pin(codec, cfg, nid, AUTO_PIN_CD); break; case AC_JACK_AUX: add_auto_cfg_input_pin(codec, cfg, nid, AUTO_PIN_AUX); break; case AC_JACK_SPDIF_OUT: case AC_JACK_DIG_OTHER_OUT: if (cfg->dig_outs >= ARRAY_SIZE(cfg->dig_out_pins)) { codec_info(codec, "ignore pin 0x%x, too many assigned pins\n", nid); continue; } cfg->dig_out_pins[cfg->dig_outs] = nid; cfg->dig_out_type[cfg->dig_outs] = (loc == AC_JACK_LOC_HDMI) ? HDA_PCM_TYPE_HDMI : HDA_PCM_TYPE_SPDIF; cfg->dig_outs++; break; case AC_JACK_SPDIF_IN: case AC_JACK_DIG_OTHER_IN: cfg->dig_in_pin = nid; if (loc == AC_JACK_LOC_HDMI) cfg->dig_in_type = HDA_PCM_TYPE_HDMI; else cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; break; } } /* Find a pin that could be a headset or headphone mic */ if (cond_flags & HDA_PINCFG_HEADSET_MIC || cond_flags & HDA_PINCFG_HEADPHONE_MIC) { bool hsmic = !!(cond_flags & HDA_PINCFG_HEADSET_MIC); bool hpmic = !!(cond_flags & HDA_PINCFG_HEADPHONE_MIC); for (i = 0; (hsmic || hpmic) && (i < cfg->num_inputs); i++) if (hsmic && can_be_headset_mic(codec, &cfg->inputs[i], 0xc)) { cfg->inputs[i].is_headset_mic = 1; hsmic = false; } else if (hpmic && can_be_headset_mic(codec, &cfg->inputs[i], 0xd)) { cfg->inputs[i].is_headphone_mic = 1; hpmic = false; } /* If we didn't find our sequence number mark, fall back to any sequence number */ for (i = 0; (hsmic || hpmic) && (i < cfg->num_inputs); i++) { if (!can_be_headset_mic(codec, &cfg->inputs[i], -1)) continue; if (hsmic) { cfg->inputs[i].is_headset_mic = 1; hsmic = false; } else if (hpmic) { cfg->inputs[i].is_headphone_mic = 1; hpmic = false; } } if (hsmic) codec_dbg(codec, "Told to look for a headset mic, but didn't find any.\n"); if (hpmic) codec_dbg(codec, "Told to look for a headphone mic, but didn't find any.\n"); } /* FIX-UP: * If no line-out is defined but multiple HPs are found, * some of them might be the real line-outs. */ if (!cfg->line_outs && cfg->hp_outs > 1 && !(cond_flags & HDA_PINCFG_NO_HP_FIXUP)) { i = 0; while (i < cfg->hp_outs) { /* The real HPs should have the sequence 0x0f */ if ((hp_out[i].seq & 0x0f) == 0x0f) { i++; continue; } /* Move it to the line-out table */ line_out[cfg->line_outs++] = hp_out[i]; cfg->hp_outs--; memmove(hp_out + i, hp_out + i + 1, sizeof(hp_out[0]) * (cfg->hp_outs - i)); } memset(hp_out + cfg->hp_outs, 0, sizeof(hp_out[0]) * (AUTO_CFG_MAX_OUTS - cfg->hp_outs)); if (!cfg->hp_outs) cfg->line_out_type = AUTO_PIN_HP_OUT; } /* sort by sequence */ sort_pins_by_sequence(cfg->line_out_pins, line_out, cfg->line_outs); sort_pins_by_sequence(cfg->speaker_pins, speaker_out, cfg->speaker_outs); sort_pins_by_sequence(cfg->hp_pins, hp_out, cfg->hp_outs); /* * FIX-UP: if no line-outs are detected, try to use speaker or HP pin * as a primary output */ if (!cfg->line_outs && !(cond_flags & HDA_PINCFG_NO_LO_FIXUP)) { if (cfg->speaker_outs) { cfg->line_outs = cfg->speaker_outs; memcpy(cfg->line_out_pins, cfg->speaker_pins, sizeof(cfg->speaker_pins)); cfg->speaker_outs = 0; memset(cfg->speaker_pins, 0, sizeof(cfg->speaker_pins)); cfg->line_out_type = AUTO_PIN_SPEAKER_OUT; } else if (cfg->hp_outs) { cfg->line_outs = cfg->hp_outs; memcpy(cfg->line_out_pins, cfg->hp_pins, sizeof(cfg->hp_pins)); cfg->hp_outs = 0; memset(cfg->hp_pins, 0, sizeof(cfg->hp_pins)); cfg->line_out_type = AUTO_PIN_HP_OUT; } } reorder_outputs(cfg->line_outs, cfg->line_out_pins); reorder_outputs(cfg->hp_outs, cfg->hp_pins); reorder_outputs(cfg->speaker_outs, cfg->speaker_pins); /* sort inputs in the order of AUTO_PIN_* type */ sort(cfg->inputs, cfg->num_inputs, sizeof(cfg->inputs[0]), compare_input_type, NULL); /* * debug prints of the parsed results */ codec_info(codec, "autoconfig for %s: line_outs=%d (0x%x/0x%x/0x%x/0x%x/0x%x) type:%s\n", codec->core.chip_name, cfg->line_outs, cfg->line_out_pins[0], cfg->line_out_pins[1], cfg->line_out_pins[2], cfg->line_out_pins[3], cfg->line_out_pins[4], cfg->line_out_type == AUTO_PIN_HP_OUT ? "hp" : (cfg->line_out_type == AUTO_PIN_SPEAKER_OUT ? "speaker" : "line")); codec_info(codec, " speaker_outs=%d (0x%x/0x%x/0x%x/0x%x/0x%x)\n", cfg->speaker_outs, cfg->speaker_pins[0], cfg->speaker_pins[1], cfg->speaker_pins[2], cfg->speaker_pins[3], cfg->speaker_pins[4]); codec_info(codec, " hp_outs=%d (0x%x/0x%x/0x%x/0x%x/0x%x)\n", cfg->hp_outs, cfg->hp_pins[0], cfg->hp_pins[1], cfg->hp_pins[2], cfg->hp_pins[3], cfg->hp_pins[4]); codec_info(codec, " mono: mono_out=0x%x\n", cfg->mono_out_pin); if (cfg->dig_outs) codec_info(codec, " dig-out=0x%x/0x%x\n", cfg->dig_out_pins[0], cfg->dig_out_pins[1]); codec_info(codec, " inputs:\n"); for (i = 0; i < cfg->num_inputs; i++) { codec_info(codec, " %s=0x%x\n", hda_get_autocfg_input_label(codec, cfg, i), cfg->inputs[i].pin); } if (cfg->dig_in_pin) codec_info(codec, " dig-in=0x%x\n", cfg->dig_in_pin); return 0; } EXPORT_SYMBOL_GPL(snd_hda_parse_pin_defcfg); /** * snd_hda_get_input_pin_attr - Get the input pin attribute from pin config * @def_conf: pin configuration value * * Guess the input pin attribute (INPUT_PIN_ATTR_XXX) from the given * default pin configuration value. */ int snd_hda_get_input_pin_attr(unsigned int def_conf) { unsigned int loc = get_defcfg_location(def_conf); unsigned int conn = get_defcfg_connect(def_conf); if (conn == AC_JACK_PORT_NONE) return INPUT_PIN_ATTR_UNUSED; /* Windows may claim the internal mic to be BOTH, too */ if (conn == AC_JACK_PORT_FIXED || conn == AC_JACK_PORT_BOTH) return INPUT_PIN_ATTR_INT; if ((loc & 0x30) == AC_JACK_LOC_INTERNAL) return INPUT_PIN_ATTR_INT; if ((loc & 0x30) == AC_JACK_LOC_SEPARATE) return INPUT_PIN_ATTR_DOCK; if (loc == AC_JACK_LOC_REAR) return INPUT_PIN_ATTR_REAR; if (loc == AC_JACK_LOC_FRONT) return INPUT_PIN_ATTR_FRONT; return INPUT_PIN_ATTR_NORMAL; } EXPORT_SYMBOL_GPL(snd_hda_get_input_pin_attr); /** * hda_get_input_pin_label - Give a label for the given input pin * @codec: the HDA codec * @item: ping config item to refer * @pin: the pin NID * @check_location: flag to add the jack location prefix * * When @check_location is true, the function checks the pin location * for mic and line-in pins, and set an appropriate prefix like "Front", * "Rear", "Internal". */ static const char *hda_get_input_pin_label(struct hda_codec *codec, const struct auto_pin_cfg_item *item, hda_nid_t pin, bool check_location) { unsigned int def_conf; static const char * const mic_names[] = { "Internal Mic", "Dock Mic", "Mic", "Rear Mic", "Front Mic" }; int attr; def_conf = snd_hda_codec_get_pincfg(codec, pin); switch (get_defcfg_device(def_conf)) { case AC_JACK_MIC_IN: if (item && item->is_headset_mic) return "Headset Mic"; if (item && item->is_headphone_mic) return "Headphone Mic"; if (!check_location) return "Mic"; attr = snd_hda_get_input_pin_attr(def_conf); if (!attr) return "None"; return mic_names[attr - 1]; case AC_JACK_LINE_IN: if (!check_location) return "Line"; attr = snd_hda_get_input_pin_attr(def_conf); if (!attr) return "None"; if (attr == INPUT_PIN_ATTR_DOCK) return "Dock Line"; return "Line"; case AC_JACK_AUX: return "Aux"; case AC_JACK_CD: return "CD"; case AC_JACK_SPDIF_IN: return "SPDIF In"; case AC_JACK_DIG_OTHER_IN: return "Digital In"; case AC_JACK_HP_OUT: return "Headphone Mic"; default: return "Misc"; } } /* Check whether the location prefix needs to be added to the label. * If all mic-jacks are in the same location (e.g. rear panel), we don't * have to put "Front" prefix to each label. In such a case, returns false. */ static int check_mic_location_need(struct hda_codec *codec, const struct auto_pin_cfg *cfg, int input) { unsigned int defc; int i, attr, attr2; defc = snd_hda_codec_get_pincfg(codec, cfg->inputs[input].pin); attr = snd_hda_get_input_pin_attr(defc); /* for internal or docking mics, we need locations */ if (attr <= INPUT_PIN_ATTR_NORMAL) return 1; attr = 0; for (i = 0; i < cfg->num_inputs; i++) { defc = snd_hda_codec_get_pincfg(codec, cfg->inputs[i].pin); attr2 = snd_hda_get_input_pin_attr(defc); if (attr2 >= INPUT_PIN_ATTR_NORMAL) { if (attr && attr != attr2) return 1; /* different locations found */ attr = attr2; } } return 0; } /** * hda_get_autocfg_input_label - Get a label for the given input * @codec: the HDA codec * @cfg: the parsed pin configuration * @input: the input index number * * Get a label for the given input pin defined by the autocfg item. * Unlike hda_get_input_pin_label(), this function checks all inputs * defined in autocfg and avoids the redundant mic/line prefix as much as * possible. */ const char *hda_get_autocfg_input_label(struct hda_codec *codec, const struct auto_pin_cfg *cfg, int input) { int type = cfg->inputs[input].type; int has_multiple_pins = 0; if ((input > 0 && cfg->inputs[input - 1].type == type) || (input < cfg->num_inputs - 1 && cfg->inputs[input + 1].type == type)) has_multiple_pins = 1; if (has_multiple_pins && type == AUTO_PIN_MIC) has_multiple_pins &= check_mic_location_need(codec, cfg, input); has_multiple_pins |= codec->force_pin_prefix; return hda_get_input_pin_label(codec, &cfg->inputs[input], cfg->inputs[input].pin, has_multiple_pins); } EXPORT_SYMBOL_GPL(hda_get_autocfg_input_label); /* return the position of NID in the list, or -1 if not found */ static int find_idx_in_nid_list(hda_nid_t nid, const hda_nid_t *list, int nums) { int i; for (i = 0; i < nums; i++) if (list[i] == nid) return i; return -1; } /* get a unique suffix or an index number */ static const char *check_output_sfx(hda_nid_t nid, const hda_nid_t *pins, int num_pins, int *indexp) { static const char * const channel_sfx[] = { " Front", " Surround", " CLFE", " Side" }; int i; i = find_idx_in_nid_list(nid, pins, num_pins); if (i < 0) return NULL; if (num_pins == 1) return ""; if (num_pins > ARRAY_SIZE(channel_sfx)) { if (indexp) *indexp = i; return ""; } return channel_sfx[i]; } static const char *check_output_pfx(struct hda_codec *codec, hda_nid_t nid) { unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid); int attr = snd_hda_get_input_pin_attr(def_conf); /* check the location */ switch (attr) { case INPUT_PIN_ATTR_DOCK: return "Dock "; case INPUT_PIN_ATTR_FRONT: return "Front "; } return ""; } static int get_hp_label_index(struct hda_codec *codec, hda_nid_t nid, const hda_nid_t *pins, int num_pins) { int i, j, idx = 0; const char *pfx = check_output_pfx(codec, nid); i = find_idx_in_nid_list(nid, pins, num_pins); if (i < 0) return -1; for (j = 0; j < i; j++) if (pfx == check_output_pfx(codec, pins[j])) idx++; return idx; } static int fill_audio_out_name(struct hda_codec *codec, hda_nid_t nid, const struct auto_pin_cfg *cfg, const char *name, char *label, int maxlen, int *indexp) { unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid); int attr = snd_hda_get_input_pin_attr(def_conf); const char *pfx, *sfx = ""; /* handle as a speaker if it's a fixed line-out */ if (!strcmp(name, "Line Out") && attr == INPUT_PIN_ATTR_INT) name = "Speaker"; pfx = check_output_pfx(codec, nid); if (cfg) { /* try to give a unique suffix if needed */ sfx = check_output_sfx(nid, cfg->line_out_pins, cfg->line_outs, indexp); if (!sfx) sfx = check_output_sfx(nid, cfg->speaker_pins, cfg->speaker_outs, indexp); if (!sfx) { /* don't add channel suffix for Headphone controls */ int idx = get_hp_label_index(codec, nid, cfg->hp_pins, cfg->hp_outs); if (idx >= 0 && indexp) *indexp = idx; sfx = ""; } } snprintf(label, maxlen, "%s%s%s", pfx, name, sfx); return 1; } #define is_hdmi_cfg(conf) \ (get_defcfg_location(conf) == AC_JACK_LOC_HDMI) /** * snd_hda_get_pin_label - Get a label for the given I/O pin * @codec: the HDA codec * @nid: pin NID * @cfg: the parsed pin configuration * @label: the string buffer to store * @maxlen: the max length of string buffer (including termination) * @indexp: the pointer to return the index number (for multiple ctls) * * Get a label for the given pin. This function works for both input and * output pins. When @cfg is given as non-NULL, the function tries to get * an optimized label using hda_get_autocfg_input_label(). * * This function tries to give a unique label string for the pin as much as * possible. For example, when the multiple line-outs are present, it adds * the channel suffix like "Front", "Surround", etc (only when @cfg is given). * If no unique name with a suffix is available and @indexp is non-NULL, the * index number is stored in the pointer. */ int snd_hda_get_pin_label(struct hda_codec *codec, hda_nid_t nid, const struct auto_pin_cfg *cfg, char *label, int maxlen, int *indexp) { unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid); const char *name = NULL; int i; bool hdmi; if (indexp) *indexp = 0; if (get_defcfg_connect(def_conf) == AC_JACK_PORT_NONE) return 0; switch (get_defcfg_device(def_conf)) { case AC_JACK_LINE_OUT: return fill_audio_out_name(codec, nid, cfg, "Line Out", label, maxlen, indexp); case AC_JACK_SPEAKER: return fill_audio_out_name(codec, nid, cfg, "Speaker", label, maxlen, indexp); case AC_JACK_HP_OUT: return fill_audio_out_name(codec, nid, cfg, "Headphone", label, maxlen, indexp); case AC_JACK_SPDIF_OUT: case AC_JACK_DIG_OTHER_OUT: hdmi = is_hdmi_cfg(def_conf); name = hdmi ? "HDMI" : "SPDIF"; if (cfg && indexp) for (i = 0; i < cfg->dig_outs; i++) { hda_nid_t pin = cfg->dig_out_pins[i]; unsigned int c; if (pin == nid) break; c = snd_hda_codec_get_pincfg(codec, pin); if (hdmi == is_hdmi_cfg(c)) (*indexp)++; } break; default: if (cfg) { for (i = 0; i < cfg->num_inputs; i++) { if (cfg->inputs[i].pin != nid) continue; name = hda_get_autocfg_input_label(codec, cfg, i); if (name) break; } } if (!name) name = hda_get_input_pin_label(codec, NULL, nid, true); break; } if (!name) return 0; strscpy(label, name, maxlen); return 1; } EXPORT_SYMBOL_GPL(snd_hda_get_pin_label); /** * snd_hda_add_verbs - Add verbs to the init list * @codec: the HDA codec * @list: zero-terminated verb list to add * * Append the given verb list to the execution list. The verbs will be * performed at init and resume time via snd_hda_apply_verbs(). */ int snd_hda_add_verbs(struct hda_codec *codec, const struct hda_verb *list) { const struct hda_verb **v; v = snd_array_new(&codec->verbs); if (!v) return -ENOMEM; *v = list; return 0; } EXPORT_SYMBOL_GPL(snd_hda_add_verbs); /** * snd_hda_apply_verbs - Execute the init verb lists * @codec: the HDA codec */ void snd_hda_apply_verbs(struct hda_codec *codec) { const struct hda_verb **v; int i; snd_array_for_each(&codec->verbs, i, v) snd_hda_sequence_write(codec, *v); } EXPORT_SYMBOL_GPL(snd_hda_apply_verbs); /** * snd_hda_apply_pincfgs - Set each pin config in the given list * @codec: the HDA codec * @cfg: NULL-terminated pin config table */ void snd_hda_apply_pincfgs(struct hda_codec *codec, const struct hda_pintbl *cfg) { for (; cfg->nid; cfg++) snd_hda_codec_set_pincfg(codec, cfg->nid, cfg->val); } EXPORT_SYMBOL_GPL(snd_hda_apply_pincfgs); static void set_pin_targets(struct hda_codec *codec, const struct hda_pintbl *cfg) { for (; cfg->nid; cfg++) snd_hda_set_pin_ctl_cache(codec, cfg->nid, cfg->val); } void __snd_hda_apply_fixup(struct hda_codec *codec, int id, int action, int depth) { const char *modelname = codec->fixup_name; while (id >= 0) { const struct hda_fixup *fix = codec->fixup_list + id; if (++depth > 10) break; if (fix->chained_before) __snd_hda_apply_fixup(codec, fix->chain_id, action, depth + 1); switch (fix->type) { case HDA_FIXUP_PINS: if (action != HDA_FIXUP_ACT_PRE_PROBE || !fix->v.pins) break; codec_dbg(codec, "%s: Apply pincfg for %s\n", codec->core.chip_name, modelname); snd_hda_apply_pincfgs(codec, fix->v.pins); break; case HDA_FIXUP_VERBS: if (action != HDA_FIXUP_ACT_PROBE || !fix->v.verbs) break; codec_dbg(codec, "%s: Apply fix-verbs for %s\n", codec->core.chip_name, modelname); snd_hda_add_verbs(codec, fix->v.verbs); break; case HDA_FIXUP_FUNC: if (!fix->v.func) break; codec_dbg(codec, "%s: Apply fix-func for %s\n", codec->core.chip_name, modelname); fix->v.func(codec, fix, action); break; case HDA_FIXUP_PINCTLS: if (action != HDA_FIXUP_ACT_PROBE || !fix->v.pins) break; codec_dbg(codec, "%s: Apply pinctl for %s\n", codec->core.chip_name, modelname); set_pin_targets(codec, fix->v.pins); break; default: codec_err(codec, "%s: Invalid fixup type %d\n", codec->core.chip_name, fix->type); break; } if (!fix->chained || fix->chained_before) break; id = fix->chain_id; } } EXPORT_SYMBOL_GPL(__snd_hda_apply_fixup); /** * snd_hda_apply_fixup - Apply the fixup chain with the given action * @codec: the HDA codec * @action: fixup action (HDA_FIXUP_ACT_XXX) */ void snd_hda_apply_fixup(struct hda_codec *codec, int action) { if (codec->fixup_list) __snd_hda_apply_fixup(codec, codec->fixup_id, action, 0); } EXPORT_SYMBOL_GPL(snd_hda_apply_fixup); #define IGNORE_SEQ_ASSOC (~(AC_DEFCFG_SEQUENCE | AC_DEFCFG_DEF_ASSOC)) static bool pin_config_match(struct hda_codec *codec, const struct hda_pintbl *pins, bool match_all_pins) { const struct hda_pincfg *pin; int i; snd_array_for_each(&codec->init_pins, i, pin) { hda_nid_t nid = pin->nid; u32 cfg = pin->cfg; const struct hda_pintbl *t_pins; int found; t_pins = pins; found = 0; for (; t_pins->nid; t_pins++) { if (t_pins->nid == nid) { found = 1; if ((t_pins->val & IGNORE_SEQ_ASSOC) == (cfg & IGNORE_SEQ_ASSOC)) break; else if ((cfg & 0xf0000000) == 0x40000000 && (t_pins->val & 0xf0000000) == 0x40000000) break; else return false; } } if (match_all_pins && !found && (cfg & 0xf0000000) != 0x40000000) return false; } return true; } /** * snd_hda_pick_pin_fixup - Pick up a fixup matching with the pin quirk list * @codec: the HDA codec * @pin_quirk: zero-terminated pin quirk list * @fixlist: the fixup list * @match_all_pins: all valid pins must match with the table entries */ void snd_hda_pick_pin_fixup(struct hda_codec *codec, const struct snd_hda_pin_quirk *pin_quirk, const struct hda_fixup *fixlist, bool match_all_pins) { const struct snd_hda_pin_quirk *pq; if (codec->fixup_id != HDA_FIXUP_ID_NOT_SET) return; for (pq = pin_quirk; pq->subvendor; pq++) { if ((codec->core.subsystem_id & 0xffff0000) != (pq->subvendor << 16)) continue; if (codec->core.vendor_id != pq->codec) continue; if (pin_config_match(codec, pq->pins, match_all_pins)) { codec->fixup_id = pq->value; #ifdef CONFIG_SND_DEBUG_VERBOSE codec->fixup_name = pq->name; codec_dbg(codec, "%s: picked fixup %s (pin match)\n", codec->core.chip_name, codec->fixup_name); #endif codec->fixup_list = fixlist; return; } } } EXPORT_SYMBOL_GPL(snd_hda_pick_pin_fixup); /** * snd_hda_pick_fixup - Pick up a fixup matching with PCI/codec SSID or model string * @codec: the HDA codec * @models: NULL-terminated model string list * @quirk: zero-terminated PCI/codec SSID quirk list * @fixlist: the fixup list * * Pick up a fixup entry matching with the given model string or SSID. * If a fixup was already set beforehand, the function doesn't do anything. * When a special model string "nofixup" is given, also no fixup is applied. * * The function tries to find the matching model name at first, if given. * If the model string contains the SSID alias, try to look up with the given * alias ID. * If nothing matched, try to look up the PCI SSID. * If still nothing matched, try to look up the codec SSID. */ void snd_hda_pick_fixup(struct hda_codec *codec, const struct hda_model_fixup *models, const struct snd_pci_quirk *quirk, const struct hda_fixup *fixlist) { const struct snd_pci_quirk *q; int id = HDA_FIXUP_ID_NOT_SET; const char *name = NULL; const char *type = NULL; unsigned int vendor, device; if (codec->fixup_id != HDA_FIXUP_ID_NOT_SET) return; /* when model=nofixup is given, don't pick up any fixups */ if (codec->modelname && !strcmp(codec->modelname, "nofixup")) { id = HDA_FIXUP_ID_NO_FIXUP; fixlist = NULL; codec_dbg(codec, "%s: picked no fixup (nofixup specified)\n", codec->core.chip_name); goto found; } /* match with the model name string */ if (codec->modelname && models) { while (models->name) { if (!strcmp(codec->modelname, models->name)) { id = models->id; name = models->name; codec_dbg(codec, "%s: picked fixup %s (model specified)\n", codec->core.chip_name, codec->fixup_name); goto found; } models++; } } if (!quirk) return; /* match with the SSID alias given by the model string "XXXX:YYYY" */ if (codec->modelname && sscanf(codec->modelname, "%04x:%04x", &vendor, &device) == 2) { q = snd_pci_quirk_lookup_id(vendor, device, quirk); if (q) { type = "alias SSID"; goto found_device; } } /* match with the PCI SSID */ q = snd_pci_quirk_lookup(codec->bus->pci, quirk); if (q) { type = "PCI SSID"; goto found_device; } /* match with the codec SSID */ q = snd_pci_quirk_lookup_id(codec->core.subsystem_id >> 16, codec->core.subsystem_id & 0xffff, quirk); if (q) { type = "codec SSID"; goto found_device; } return; /* no matching */ found_device: id = q->value; #ifdef CONFIG_SND_DEBUG_VERBOSE name = q->name; #endif codec_dbg(codec, "%s: picked fixup %s for %s %04x:%04x\n", codec->core.chip_name, name ? name : "", type, q->subvendor, q->subdevice); found: codec->fixup_id = id; codec->fixup_list = fixlist; codec->fixup_name = name; } EXPORT_SYMBOL_GPL(snd_hda_pick_fixup);
linux-master
sound/pci/hda/hda_auto_parser.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * HD audio interface patch for Cirrus Logic CS420x chip * * Copyright (c) 2009 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <linux/pci.h> #include <sound/tlv.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_jack.h" #include "hda_generic.h" /* */ struct cs_spec { struct hda_gen_spec gen; unsigned int gpio_mask; unsigned int gpio_dir; unsigned int gpio_data; unsigned int gpio_eapd_hp; /* EAPD GPIO bit for headphones */ unsigned int gpio_eapd_speaker; /* EAPD GPIO bit for speakers */ /* CS421x */ unsigned int spdif_detect:1; unsigned int spdif_present:1; unsigned int sense_b:1; hda_nid_t vendor_nid; /* for MBP SPDIF control */ int (*spdif_sw_put)(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); }; /* available models with CS420x */ enum { CS420X_MBP53, CS420X_MBP55, CS420X_IMAC27, CS420X_GPIO_13, CS420X_GPIO_23, CS420X_MBP101, CS420X_MBP81, CS420X_MBA42, CS420X_AUTO, /* aliases */ CS420X_IMAC27_122 = CS420X_GPIO_23, CS420X_APPLE = CS420X_GPIO_13, }; /* CS421x boards */ enum { CS421X_CDB4210, CS421X_SENSE_B, CS421X_STUMPY, }; /* Vendor-specific processing widget */ #define CS420X_VENDOR_NID 0x11 #define CS_DIG_OUT1_PIN_NID 0x10 #define CS_DIG_OUT2_PIN_NID 0x15 #define CS_DMIC1_PIN_NID 0x0e #define CS_DMIC2_PIN_NID 0x12 /* coef indices */ #define IDX_SPDIF_STAT 0x0000 #define IDX_SPDIF_CTL 0x0001 #define IDX_ADC_CFG 0x0002 /* SZC bitmask, 4 modes below: * 0 = immediate, * 1 = digital immediate, analog zero-cross * 2 = digtail & analog soft-ramp * 3 = digital soft-ramp, analog zero-cross */ #define CS_COEF_ADC_SZC_MASK (3 << 0) #define CS_COEF_ADC_MIC_SZC_MODE (3 << 0) /* SZC setup for mic */ #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */ /* PGA mode: 0 = differential, 1 = signle-ended */ #define CS_COEF_ADC_MIC_PGA_MODE (1 << 5) /* PGA setup for mic */ #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */ #define IDX_DAC_CFG 0x0003 /* SZC bitmask, 4 modes below: * 0 = Immediate * 1 = zero-cross * 2 = soft-ramp * 3 = soft-ramp on zero-cross */ #define CS_COEF_DAC_HP_SZC_MODE (3 << 0) /* nid 0x02 */ #define CS_COEF_DAC_LO_SZC_MODE (3 << 2) /* nid 0x03 */ #define CS_COEF_DAC_SPK_SZC_MODE (3 << 4) /* nid 0x04 */ #define IDX_BEEP_CFG 0x0004 /* 0x0008 - test reg key */ /* 0x0009 - 0x0014 -> 12 test regs */ /* 0x0015 - visibility reg */ /* Cirrus Logic CS4208 */ #define CS4208_VENDOR_NID 0x24 /* * Cirrus Logic CS4210 * * 1 DAC => HP(sense) / Speakers, * 1 ADC <= LineIn(sense) / MicIn / DMicIn, * 1 SPDIF OUT => SPDIF Trasmitter(sense) */ #define CS4210_DAC_NID 0x02 #define CS4210_ADC_NID 0x03 #define CS4210_VENDOR_NID 0x0B #define CS421X_DMIC_PIN_NID 0x09 /* Port E */ #define CS421X_SPDIF_PIN_NID 0x0A /* Port H */ #define CS421X_IDX_DEV_CFG 0x01 #define CS421X_IDX_ADC_CFG 0x02 #define CS421X_IDX_DAC_CFG 0x03 #define CS421X_IDX_SPK_CTL 0x04 /* Cirrus Logic CS4213 is like CS4210 but does not have SPDIF input/output */ #define CS4213_VENDOR_NID 0x09 static inline int cs_vendor_coef_get(struct hda_codec *codec, unsigned int idx) { struct cs_spec *spec = codec->spec; snd_hda_codec_write(codec, spec->vendor_nid, 0, AC_VERB_SET_COEF_INDEX, idx); return snd_hda_codec_read(codec, spec->vendor_nid, 0, AC_VERB_GET_PROC_COEF, 0); } static inline void cs_vendor_coef_set(struct hda_codec *codec, unsigned int idx, unsigned int coef) { struct cs_spec *spec = codec->spec; snd_hda_codec_write(codec, spec->vendor_nid, 0, AC_VERB_SET_COEF_INDEX, idx); snd_hda_codec_write(codec, spec->vendor_nid, 0, AC_VERB_SET_PROC_COEF, coef); } /* * auto-mute and auto-mic switching * CS421x auto-output redirecting * HP/SPK/SPDIF */ static void cs_automute(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; /* mute HPs if spdif jack (SENSE_B) is present */ spec->gen.master_mute = !!(spec->spdif_present && spec->sense_b); snd_hda_gen_update_outputs(codec); if (spec->gpio_eapd_hp || spec->gpio_eapd_speaker) { if (spec->gen.automute_speaker) spec->gpio_data = spec->gen.hp_jack_present ? spec->gpio_eapd_hp : spec->gpio_eapd_speaker; else spec->gpio_data = spec->gpio_eapd_hp | spec->gpio_eapd_speaker; snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } } static bool is_active_pin(struct hda_codec *codec, hda_nid_t nid) { unsigned int val; val = snd_hda_codec_get_pincfg(codec, nid); return (get_defcfg_connect(val) != AC_JACK_PORT_NONE); } static void init_input_coef(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; unsigned int coef; /* CS420x has multiple ADC, CS421x has single ADC */ if (spec->vendor_nid == CS420X_VENDOR_NID) { coef = cs_vendor_coef_get(codec, IDX_BEEP_CFG); if (is_active_pin(codec, CS_DMIC2_PIN_NID)) coef |= 1 << 4; /* DMIC2 2 chan on, GPIO1 off */ if (is_active_pin(codec, CS_DMIC1_PIN_NID)) coef |= 1 << 3; /* DMIC1 2 chan on, GPIO0 off * No effect if SPDIF_OUT2 is * selected in IDX_SPDIF_CTL. */ cs_vendor_coef_set(codec, IDX_BEEP_CFG, coef); } } static const struct hda_verb cs_coef_init_verbs[] = { {0x11, AC_VERB_SET_PROC_STATE, 1}, {0x11, AC_VERB_SET_COEF_INDEX, IDX_DAC_CFG}, {0x11, AC_VERB_SET_PROC_COEF, (0x002a /* DAC1/2/3 SZCMode Soft Ramp */ | 0x0040 /* Mute DACs on FIFO error */ | 0x1000 /* Enable DACs High Pass Filter */ | 0x0400 /* Disable Coefficient Auto increment */ )}, /* ADC1/2 - Digital and Analog Soft Ramp */ {0x11, AC_VERB_SET_COEF_INDEX, IDX_ADC_CFG}, {0x11, AC_VERB_SET_PROC_COEF, 0x000a}, /* Beep */ {0x11, AC_VERB_SET_COEF_INDEX, IDX_BEEP_CFG}, {0x11, AC_VERB_SET_PROC_COEF, 0x0007}, /* Enable Beep thru DAC1/2/3 */ {} /* terminator */ }; static const struct hda_verb cs4208_coef_init_verbs[] = { {0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */ {0x24, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ {0x24, AC_VERB_SET_COEF_INDEX, 0x0033}, {0x24, AC_VERB_SET_PROC_COEF, 0x0001}, /* A1 ICS */ {0x24, AC_VERB_SET_COEF_INDEX, 0x0034}, {0x24, AC_VERB_SET_PROC_COEF, 0x1C01}, /* A1 Enable, A Thresh = 300mV */ {} /* terminator */ }; /* Errata: CS4207 rev C0/C1/C2 Silicon * * http://www.cirrus.com/en/pubs/errata/ER880C3.pdf * * 6. At high temperature (TA > +85°C), the digital supply current (IVD) * may be excessive (up to an additional 200 μA), which is most easily * observed while the part is being held in reset (RESET# active low). * * Root Cause: At initial powerup of the device, the logic that drives * the clock and write enable to the S/PDIF SRC RAMs is not properly * initialized. * Certain random patterns will cause a steady leakage current in those * RAM cells. The issue will resolve once the SRCs are used (turned on). * * Workaround: The following verb sequence briefly turns on the S/PDIF SRC * blocks, which will alleviate the issue. */ static const struct hda_verb cs_errata_init_verbs[] = { {0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */ {0x11, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ {0x11, AC_VERB_SET_COEF_INDEX, 0x0008}, {0x11, AC_VERB_SET_PROC_COEF, 0x9999}, {0x11, AC_VERB_SET_COEF_INDEX, 0x0017}, {0x11, AC_VERB_SET_PROC_COEF, 0xa412}, {0x11, AC_VERB_SET_COEF_INDEX, 0x0001}, {0x11, AC_VERB_SET_PROC_COEF, 0x0009}, {0x07, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Rx: D0 */ {0x08, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Tx: D0 */ {0x11, AC_VERB_SET_COEF_INDEX, 0x0017}, {0x11, AC_VERB_SET_PROC_COEF, 0x2412}, {0x11, AC_VERB_SET_COEF_INDEX, 0x0008}, {0x11, AC_VERB_SET_PROC_COEF, 0x0000}, {0x11, AC_VERB_SET_COEF_INDEX, 0x0001}, {0x11, AC_VERB_SET_PROC_COEF, 0x0008}, {0x11, AC_VERB_SET_PROC_STATE, 0x00}, {} /* terminator */ }; /* SPDIF setup */ static void init_digital_coef(struct hda_codec *codec) { unsigned int coef; coef = 0x0002; /* SRC_MUTE soft-mute on SPDIF (if no lock) */ coef |= 0x0008; /* Replace with mute on error */ if (is_active_pin(codec, CS_DIG_OUT2_PIN_NID)) coef |= 0x4000; /* RX to TX1 or TX2 Loopthru / SPDIF2 * SPDIF_OUT2 is shared with GPIO1 and * DMIC_SDA2. */ cs_vendor_coef_set(codec, IDX_SPDIF_CTL, coef); } static int cs_init(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; if (spec->vendor_nid == CS420X_VENDOR_NID) { /* init_verb sequence for C0/C1/C2 errata*/ snd_hda_sequence_write(codec, cs_errata_init_verbs); snd_hda_sequence_write(codec, cs_coef_init_verbs); } else if (spec->vendor_nid == CS4208_VENDOR_NID) { snd_hda_sequence_write(codec, cs4208_coef_init_verbs); } snd_hda_gen_init(codec); if (spec->gpio_mask) { snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, spec->gpio_mask); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, spec->gpio_dir); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } if (spec->vendor_nid == CS420X_VENDOR_NID) { init_input_coef(codec); init_digital_coef(codec); } return 0; } static int cs_build_controls(struct hda_codec *codec) { int err; err = snd_hda_gen_build_controls(codec); if (err < 0) return err; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD); return 0; } #define cs_free snd_hda_gen_free static const struct hda_codec_ops cs_patch_ops = { .build_controls = cs_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = cs_init, .free = cs_free, .unsol_event = snd_hda_jack_unsol_event, }; static int cs_parse_auto_config(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; int err; int i; err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); if (err < 0) return err; err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) return err; /* keep the ADCs powered up when it's dynamically switchable */ if (spec->gen.dyn_adc_switch) { unsigned int done = 0; for (i = 0; i < spec->gen.input_mux.num_items; i++) { int idx = spec->gen.dyn_adc_idx[i]; if (done & (1 << idx)) continue; snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]); done |= 1 << idx; } } return 0; } static const struct hda_model_fixup cs420x_models[] = { { .id = CS420X_MBP53, .name = "mbp53" }, { .id = CS420X_MBP55, .name = "mbp55" }, { .id = CS420X_IMAC27, .name = "imac27" }, { .id = CS420X_IMAC27_122, .name = "imac27_122" }, { .id = CS420X_APPLE, .name = "apple" }, { .id = CS420X_MBP101, .name = "mbp101" }, { .id = CS420X_MBP81, .name = "mbp81" }, { .id = CS420X_MBA42, .name = "mba42" }, {} }; static const struct snd_pci_quirk cs420x_fixup_tbl[] = { SND_PCI_QUIRK(0x10de, 0x0ac0, "MacBookPro 5,3", CS420X_MBP53), SND_PCI_QUIRK(0x10de, 0x0d94, "MacBookAir 3,1(2)", CS420X_MBP55), SND_PCI_QUIRK(0x10de, 0xcb79, "MacBookPro 5,5", CS420X_MBP55), SND_PCI_QUIRK(0x10de, 0xcb89, "MacBookPro 7,1", CS420X_MBP55), /* this conflicts with too many other models */ /*SND_PCI_QUIRK(0x8086, 0x7270, "IMac 27 Inch", CS420X_IMAC27),*/ /* codec SSID */ SND_PCI_QUIRK(0x106b, 0x0600, "iMac 14,1", CS420X_IMAC27_122), SND_PCI_QUIRK(0x106b, 0x0900, "iMac 12,1", CS420X_IMAC27_122), SND_PCI_QUIRK(0x106b, 0x1c00, "MacBookPro 8,1", CS420X_MBP81), SND_PCI_QUIRK(0x106b, 0x2000, "iMac 12,2", CS420X_IMAC27_122), SND_PCI_QUIRK(0x106b, 0x2800, "MacBookPro 10,1", CS420X_MBP101), SND_PCI_QUIRK(0x106b, 0x5600, "MacBookAir 5,2", CS420X_MBP81), SND_PCI_QUIRK(0x106b, 0x5b00, "MacBookAir 4,2", CS420X_MBA42), SND_PCI_QUIRK_VENDOR(0x106b, "Apple", CS420X_APPLE), {} /* terminator */ }; static const struct hda_pintbl mbp53_pincfgs[] = { { 0x09, 0x012b4050 }, { 0x0a, 0x90100141 }, { 0x0b, 0x90100140 }, { 0x0c, 0x018b3020 }, { 0x0d, 0x90a00110 }, { 0x0e, 0x400000f0 }, { 0x0f, 0x01cbe030 }, { 0x10, 0x014be060 }, { 0x12, 0x400000f0 }, { 0x15, 0x400000f0 }, {} /* terminator */ }; static const struct hda_pintbl mbp55_pincfgs[] = { { 0x09, 0x012b4030 }, { 0x0a, 0x90100121 }, { 0x0b, 0x90100120 }, { 0x0c, 0x400000f0 }, { 0x0d, 0x90a00110 }, { 0x0e, 0x400000f0 }, { 0x0f, 0x400000f0 }, { 0x10, 0x014be040 }, { 0x12, 0x400000f0 }, { 0x15, 0x400000f0 }, {} /* terminator */ }; static const struct hda_pintbl imac27_pincfgs[] = { { 0x09, 0x012b4050 }, { 0x0a, 0x90100140 }, { 0x0b, 0x90100142 }, { 0x0c, 0x018b3020 }, { 0x0d, 0x90a00110 }, { 0x0e, 0x400000f0 }, { 0x0f, 0x01cbe030 }, { 0x10, 0x014be060 }, { 0x12, 0x01ab9070 }, { 0x15, 0x400000f0 }, {} /* terminator */ }; static const struct hda_pintbl mbp101_pincfgs[] = { { 0x0d, 0x40ab90f0 }, { 0x0e, 0x90a600f0 }, { 0x12, 0x50a600f0 }, {} /* terminator */ }; static const struct hda_pintbl mba42_pincfgs[] = { { 0x09, 0x012b4030 }, /* HP */ { 0x0a, 0x400000f0 }, { 0x0b, 0x90100120 }, /* speaker */ { 0x0c, 0x400000f0 }, { 0x0d, 0x90a00110 }, /* mic */ { 0x0e, 0x400000f0 }, { 0x0f, 0x400000f0 }, { 0x10, 0x400000f0 }, { 0x12, 0x400000f0 }, { 0x15, 0x400000f0 }, {} /* terminator */ }; static const struct hda_pintbl mba6_pincfgs[] = { { 0x10, 0x032120f0 }, /* HP */ { 0x11, 0x500000f0 }, { 0x12, 0x90100010 }, /* Speaker */ { 0x13, 0x500000f0 }, { 0x14, 0x500000f0 }, { 0x15, 0x770000f0 }, { 0x16, 0x770000f0 }, { 0x17, 0x430000f0 }, { 0x18, 0x43ab9030 }, /* Mic */ { 0x19, 0x770000f0 }, { 0x1a, 0x770000f0 }, { 0x1b, 0x770000f0 }, { 0x1c, 0x90a00090 }, { 0x1d, 0x500000f0 }, { 0x1e, 0x500000f0 }, { 0x1f, 0x500000f0 }, { 0x20, 0x500000f0 }, { 0x21, 0x430000f0 }, { 0x22, 0x430000f0 }, {} /* terminator */ }; static void cs420x_fixup_gpio_13(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) { struct cs_spec *spec = codec->spec; spec->gpio_eapd_hp = 2; /* GPIO1 = headphones */ spec->gpio_eapd_speaker = 8; /* GPIO3 = speakers */ spec->gpio_mask = spec->gpio_dir = spec->gpio_eapd_hp | spec->gpio_eapd_speaker; } } static void cs420x_fixup_gpio_23(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) { struct cs_spec *spec = codec->spec; spec->gpio_eapd_hp = 4; /* GPIO2 = headphones */ spec->gpio_eapd_speaker = 8; /* GPIO3 = speakers */ spec->gpio_mask = spec->gpio_dir = spec->gpio_eapd_hp | spec->gpio_eapd_speaker; } } static const struct hda_fixup cs420x_fixups[] = { [CS420X_MBP53] = { .type = HDA_FIXUP_PINS, .v.pins = mbp53_pincfgs, .chained = true, .chain_id = CS420X_APPLE, }, [CS420X_MBP55] = { .type = HDA_FIXUP_PINS, .v.pins = mbp55_pincfgs, .chained = true, .chain_id = CS420X_GPIO_13, }, [CS420X_IMAC27] = { .type = HDA_FIXUP_PINS, .v.pins = imac27_pincfgs, .chained = true, .chain_id = CS420X_GPIO_13, }, [CS420X_GPIO_13] = { .type = HDA_FIXUP_FUNC, .v.func = cs420x_fixup_gpio_13, }, [CS420X_GPIO_23] = { .type = HDA_FIXUP_FUNC, .v.func = cs420x_fixup_gpio_23, }, [CS420X_MBP101] = { .type = HDA_FIXUP_PINS, .v.pins = mbp101_pincfgs, .chained = true, .chain_id = CS420X_GPIO_13, }, [CS420X_MBP81] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { /* internal mic ADC2: right only, single ended */ {0x11, AC_VERB_SET_COEF_INDEX, IDX_ADC_CFG}, {0x11, AC_VERB_SET_PROC_COEF, 0x102a}, {} }, .chained = true, .chain_id = CS420X_GPIO_13, }, [CS420X_MBA42] = { .type = HDA_FIXUP_PINS, .v.pins = mba42_pincfgs, .chained = true, .chain_id = CS420X_GPIO_13, }, }; static struct cs_spec *cs_alloc_spec(struct hda_codec *codec, int vendor_nid) { struct cs_spec *spec; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return NULL; codec->spec = spec; spec->vendor_nid = vendor_nid; codec->power_save_node = 1; snd_hda_gen_spec_init(&spec->gen); return spec; } static int patch_cs420x(struct hda_codec *codec) { struct cs_spec *spec; int err; spec = cs_alloc_spec(codec, CS420X_VENDOR_NID); if (!spec) return -ENOMEM; codec->patch_ops = cs_patch_ops; spec->gen.automute_hook = cs_automute; codec->single_adc_amp = 1; snd_hda_pick_fixup(codec, cs420x_models, cs420x_fixup_tbl, cs420x_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = cs_parse_auto_config(codec); if (err < 0) goto error; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; error: cs_free(codec); return err; } /* * CS4208 support: * Its layout is no longer compatible with CS4206/CS4207 */ enum { CS4208_MAC_AUTO, CS4208_MBA6, CS4208_MBP11, CS4208_MACMINI, CS4208_GPIO0, }; static const struct hda_model_fixup cs4208_models[] = { { .id = CS4208_GPIO0, .name = "gpio0" }, { .id = CS4208_MBA6, .name = "mba6" }, { .id = CS4208_MBP11, .name = "mbp11" }, { .id = CS4208_MACMINI, .name = "macmini" }, {} }; static const struct snd_pci_quirk cs4208_fixup_tbl[] = { SND_PCI_QUIRK_VENDOR(0x106b, "Apple", CS4208_MAC_AUTO), {} /* terminator */ }; /* codec SSID matching */ static const struct snd_pci_quirk cs4208_mac_fixup_tbl[] = { SND_PCI_QUIRK(0x106b, 0x5e00, "MacBookPro 11,2", CS4208_MBP11), SND_PCI_QUIRK(0x106b, 0x6c00, "MacMini 7,1", CS4208_MACMINI), SND_PCI_QUIRK(0x106b, 0x7100, "MacBookAir 6,1", CS4208_MBA6), SND_PCI_QUIRK(0x106b, 0x7200, "MacBookAir 6,2", CS4208_MBA6), SND_PCI_QUIRK(0x106b, 0x7b00, "MacBookPro 12,1", CS4208_MBP11), {} /* terminator */ }; static void cs4208_fixup_gpio0(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) { struct cs_spec *spec = codec->spec; spec->gpio_eapd_hp = 0; spec->gpio_eapd_speaker = 1; spec->gpio_mask = spec->gpio_dir = spec->gpio_eapd_hp | spec->gpio_eapd_speaker; } } static const struct hda_fixup cs4208_fixups[]; /* remap the fixup from codec SSID and apply it */ static void cs4208_fixup_mac(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; codec->fixup_id = HDA_FIXUP_ID_NOT_SET; snd_hda_pick_fixup(codec, NULL, cs4208_mac_fixup_tbl, cs4208_fixups); if (codec->fixup_id == HDA_FIXUP_ID_NOT_SET) codec->fixup_id = CS4208_GPIO0; /* default fixup */ snd_hda_apply_fixup(codec, action); } /* MacMini 7,1 has the inverted jack detection */ static void cs4208_fixup_macmini(struct hda_codec *codec, const struct hda_fixup *fix, int action) { static const struct hda_pintbl pincfgs[] = { { 0x18, 0x00ab9150 }, /* mic (audio-in) jack: disable detect */ { 0x21, 0x004be140 }, /* SPDIF: disable detect */ { } }; if (action == HDA_FIXUP_ACT_PRE_PROBE) { /* HP pin (0x10) has an inverted detection */ codec->inv_jack_detect = 1; /* disable the bogus Mic and SPDIF jack detections */ snd_hda_apply_pincfgs(codec, pincfgs); } } static int cs4208_spdif_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct cs_spec *spec = codec->spec; hda_nid_t pin = spec->gen.autocfg.dig_out_pins[0]; int pinctl = ucontrol->value.integer.value[0] ? PIN_OUT : 0; snd_hda_set_pin_ctl_cache(codec, pin, pinctl); return spec->spdif_sw_put(kcontrol, ucontrol); } /* hook the SPDIF switch */ static void cs4208_fixup_spdif_switch(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_BUILD) { struct cs_spec *spec = codec->spec; struct snd_kcontrol *kctl; if (!spec->gen.autocfg.dig_out_pins[0]) return; kctl = snd_hda_find_mixer_ctl(codec, "IEC958 Playback Switch"); if (!kctl) return; spec->spdif_sw_put = kctl->put; kctl->put = cs4208_spdif_sw_put; } } static const struct hda_fixup cs4208_fixups[] = { [CS4208_MBA6] = { .type = HDA_FIXUP_PINS, .v.pins = mba6_pincfgs, .chained = true, .chain_id = CS4208_GPIO0, }, [CS4208_MBP11] = { .type = HDA_FIXUP_FUNC, .v.func = cs4208_fixup_spdif_switch, .chained = true, .chain_id = CS4208_GPIO0, }, [CS4208_MACMINI] = { .type = HDA_FIXUP_FUNC, .v.func = cs4208_fixup_macmini, .chained = true, .chain_id = CS4208_GPIO0, }, [CS4208_GPIO0] = { .type = HDA_FIXUP_FUNC, .v.func = cs4208_fixup_gpio0, }, [CS4208_MAC_AUTO] = { .type = HDA_FIXUP_FUNC, .v.func = cs4208_fixup_mac, }, }; /* correct the 0dB offset of input pins */ static void cs4208_fix_amp_caps(struct hda_codec *codec, hda_nid_t adc) { unsigned int caps; caps = query_amp_caps(codec, adc, HDA_INPUT); caps &= ~(AC_AMPCAP_OFFSET); caps |= 0x02; snd_hda_override_amp_caps(codec, adc, HDA_INPUT, caps); } static int patch_cs4208(struct hda_codec *codec) { struct cs_spec *spec; int err; spec = cs_alloc_spec(codec, CS4208_VENDOR_NID); if (!spec) return -ENOMEM; codec->patch_ops = cs_patch_ops; spec->gen.automute_hook = cs_automute; /* exclude NID 0x10 (HP) from output volumes due to different steps */ spec->gen.out_vol_mask = 1ULL << 0x10; snd_hda_pick_fixup(codec, cs4208_models, cs4208_fixup_tbl, cs4208_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); snd_hda_override_wcaps(codec, 0x18, get_wcaps(codec, 0x18) | AC_WCAP_STEREO); cs4208_fix_amp_caps(codec, 0x18); cs4208_fix_amp_caps(codec, 0x1b); cs4208_fix_amp_caps(codec, 0x1c); err = cs_parse_auto_config(codec); if (err < 0) goto error; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; error: cs_free(codec); return err; } /* * Cirrus Logic CS4210 * * 1 DAC => HP(sense) / Speakers, * 1 ADC <= LineIn(sense) / MicIn / DMicIn, * 1 SPDIF OUT => SPDIF Trasmitter(sense) */ /* CS4210 board names */ static const struct hda_model_fixup cs421x_models[] = { { .id = CS421X_CDB4210, .name = "cdb4210" }, { .id = CS421X_STUMPY, .name = "stumpy" }, {} }; static const struct snd_pci_quirk cs421x_fixup_tbl[] = { /* Test Intel board + CDB2410 */ SND_PCI_QUIRK(0x8086, 0x5001, "DP45SG/CDB4210", CS421X_CDB4210), {} /* terminator */ }; /* CS4210 board pinconfigs */ /* Default CS4210 (CDB4210)*/ static const struct hda_pintbl cdb4210_pincfgs[] = { { 0x05, 0x0321401f }, { 0x06, 0x90170010 }, { 0x07, 0x03813031 }, { 0x08, 0xb7a70037 }, { 0x09, 0xb7a6003e }, { 0x0a, 0x034510f0 }, {} /* terminator */ }; /* Stumpy ChromeBox */ static const struct hda_pintbl stumpy_pincfgs[] = { { 0x05, 0x022120f0 }, { 0x06, 0x901700f0 }, { 0x07, 0x02a120f0 }, { 0x08, 0x77a70037 }, { 0x09, 0x77a6003e }, { 0x0a, 0x434510f0 }, {} /* terminator */ }; /* Setup GPIO/SENSE for each board (if used) */ static void cs421x_fixup_sense_b(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct cs_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) spec->sense_b = 1; } static const struct hda_fixup cs421x_fixups[] = { [CS421X_CDB4210] = { .type = HDA_FIXUP_PINS, .v.pins = cdb4210_pincfgs, .chained = true, .chain_id = CS421X_SENSE_B, }, [CS421X_SENSE_B] = { .type = HDA_FIXUP_FUNC, .v.func = cs421x_fixup_sense_b, }, [CS421X_STUMPY] = { .type = HDA_FIXUP_PINS, .v.pins = stumpy_pincfgs, }, }; static const struct hda_verb cs421x_coef_init_verbs[] = { {0x0B, AC_VERB_SET_PROC_STATE, 1}, {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_DEV_CFG}, /* * Disable Coefficient Index Auto-Increment(DAI)=1, * PDREF=0 */ {0x0B, AC_VERB_SET_PROC_COEF, 0x0001 }, {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_ADC_CFG}, /* ADC SZCMode = Digital Soft Ramp */ {0x0B, AC_VERB_SET_PROC_COEF, 0x0002 }, {0x0B, AC_VERB_SET_COEF_INDEX, CS421X_IDX_DAC_CFG}, {0x0B, AC_VERB_SET_PROC_COEF, (0x0002 /* DAC SZCMode = Digital Soft Ramp */ | 0x0004 /* Mute DAC on FIFO error */ | 0x0008 /* Enable DAC High Pass Filter */ )}, {} /* terminator */ }; /* Errata: CS4210 rev A1 Silicon * * http://www.cirrus.com/en/pubs/errata/ * * Description: * 1. Performance degredation is present in the ADC. * 2. Speaker output is not completely muted upon HP detect. * 3. Noise is present when clipping occurs on the amplified * speaker outputs. * * Workaround: * The following verb sequence written to the registers during * initialization will correct the issues listed above. */ static const struct hda_verb cs421x_coef_init_verbs_A1_silicon_fixes[] = { {0x0B, AC_VERB_SET_PROC_STATE, 0x01}, /* VPW: processing on */ {0x0B, AC_VERB_SET_COEF_INDEX, 0x0006}, {0x0B, AC_VERB_SET_PROC_COEF, 0x9999}, /* Test mode: on */ {0x0B, AC_VERB_SET_COEF_INDEX, 0x000A}, {0x0B, AC_VERB_SET_PROC_COEF, 0x14CB}, /* Chop double */ {0x0B, AC_VERB_SET_COEF_INDEX, 0x0011}, {0x0B, AC_VERB_SET_PROC_COEF, 0xA2D0}, /* Increase ADC current */ {0x0B, AC_VERB_SET_COEF_INDEX, 0x001A}, {0x0B, AC_VERB_SET_PROC_COEF, 0x02A9}, /* Mute speaker */ {0x0B, AC_VERB_SET_COEF_INDEX, 0x001B}, {0x0B, AC_VERB_SET_PROC_COEF, 0X1006}, /* Remove noise */ {} /* terminator */ }; /* Speaker Amp Gain is controlled by the vendor widget's coef 4 */ static const DECLARE_TLV_DB_SCALE(cs421x_speaker_boost_db_scale, 900, 300, 0); static int cs421x_boost_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 3; return 0; } static int cs421x_boost_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = cs_vendor_coef_get(codec, CS421X_IDX_SPK_CTL) & 0x0003; return 0; } static int cs421x_boost_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); unsigned int vol = ucontrol->value.integer.value[0]; unsigned int coef = cs_vendor_coef_get(codec, CS421X_IDX_SPK_CTL); unsigned int original_coef = coef; coef &= ~0x0003; coef |= (vol & 0x0003); if (original_coef != coef) { cs_vendor_coef_set(codec, CS421X_IDX_SPK_CTL, coef); return 1; } return 0; } static const struct snd_kcontrol_new cs421x_speaker_boost_ctl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), .name = "Speaker Boost Playback Volume", .info = cs421x_boost_vol_info, .get = cs421x_boost_vol_get, .put = cs421x_boost_vol_put, .tlv = { .p = cs421x_speaker_boost_db_scale }, }; static void cs4210_pinmux_init(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; unsigned int def_conf, coef; /* GPIO, DMIC_SCL, DMIC_SDA and SENSE_B are multiplexed */ coef = cs_vendor_coef_get(codec, CS421X_IDX_DEV_CFG); if (spec->gpio_mask) coef |= 0x0008; /* B1,B2 are GPIOs */ else coef &= ~0x0008; if (spec->sense_b) coef |= 0x0010; /* B2 is SENSE_B, not inverted */ else coef &= ~0x0010; cs_vendor_coef_set(codec, CS421X_IDX_DEV_CFG, coef); if ((spec->gpio_mask || spec->sense_b) && is_active_pin(codec, CS421X_DMIC_PIN_NID)) { /* * GPIO or SENSE_B forced - disconnect the DMIC pin. */ def_conf = snd_hda_codec_get_pincfg(codec, CS421X_DMIC_PIN_NID); def_conf &= ~AC_DEFCFG_PORT_CONN; def_conf |= (AC_JACK_PORT_NONE << AC_DEFCFG_PORT_CONN_SHIFT); snd_hda_codec_set_pincfg(codec, CS421X_DMIC_PIN_NID, def_conf); } } static void cs4210_spdif_automute(struct hda_codec *codec, struct hda_jack_callback *tbl) { struct cs_spec *spec = codec->spec; bool spdif_present = false; hda_nid_t spdif_pin = spec->gen.autocfg.dig_out_pins[0]; /* detect on spdif is specific to CS4210 */ if (!spec->spdif_detect || spec->vendor_nid != CS4210_VENDOR_NID) return; spdif_present = snd_hda_jack_detect(codec, spdif_pin); if (spdif_present == spec->spdif_present) return; spec->spdif_present = spdif_present; /* SPDIF TX on/off */ snd_hda_set_pin_ctl(codec, spdif_pin, spdif_present ? PIN_OUT : 0); cs_automute(codec); } static void parse_cs421x_digital(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->gen.autocfg; int i; for (i = 0; i < cfg->dig_outs; i++) { hda_nid_t nid = cfg->dig_out_pins[i]; if (get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP) { spec->spdif_detect = 1; snd_hda_jack_detect_enable_callback(codec, nid, cs4210_spdif_automute); } } } static int cs421x_init(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; if (spec->vendor_nid == CS4210_VENDOR_NID) { snd_hda_sequence_write(codec, cs421x_coef_init_verbs); snd_hda_sequence_write(codec, cs421x_coef_init_verbs_A1_silicon_fixes); cs4210_pinmux_init(codec); } snd_hda_gen_init(codec); if (spec->gpio_mask) { snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, spec->gpio_mask); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, spec->gpio_dir); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } init_input_coef(codec); cs4210_spdif_automute(codec, NULL); return 0; } static void fix_volume_caps(struct hda_codec *codec, hda_nid_t dac) { unsigned int caps; /* set the upper-limit for mixer amp to 0dB */ caps = query_amp_caps(codec, dac, HDA_OUTPUT); caps &= ~(0x7f << AC_AMPCAP_NUM_STEPS_SHIFT); caps |= ((caps >> AC_AMPCAP_OFFSET_SHIFT) & 0x7f) << AC_AMPCAP_NUM_STEPS_SHIFT; snd_hda_override_amp_caps(codec, dac, HDA_OUTPUT, caps); } static int cs421x_parse_auto_config(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; hda_nid_t dac = CS4210_DAC_NID; int err; fix_volume_caps(codec, dac); err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); if (err < 0) return err; err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) return err; parse_cs421x_digital(codec); if (spec->gen.autocfg.speaker_outs && spec->vendor_nid == CS4210_VENDOR_NID) { if (!snd_hda_gen_add_kctl(&spec->gen, NULL, &cs421x_speaker_boost_ctl)) return -ENOMEM; } return 0; } #ifdef CONFIG_PM /* * Manage PDREF, when transitioning to D3hot * (DAC,ADC) -> D3, PDREF=1, AFG->D3 */ static int cs421x_suspend(struct hda_codec *codec) { struct cs_spec *spec = codec->spec; unsigned int coef; snd_hda_shutup_pins(codec); snd_hda_codec_write(codec, CS4210_DAC_NID, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D3); snd_hda_codec_write(codec, CS4210_ADC_NID, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D3); if (spec->vendor_nid == CS4210_VENDOR_NID) { coef = cs_vendor_coef_get(codec, CS421X_IDX_DEV_CFG); coef |= 0x0004; /* PDREF */ cs_vendor_coef_set(codec, CS421X_IDX_DEV_CFG, coef); } return 0; } #endif static const struct hda_codec_ops cs421x_patch_ops = { .build_controls = snd_hda_gen_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = cs421x_init, .free = cs_free, .unsol_event = snd_hda_jack_unsol_event, #ifdef CONFIG_PM .suspend = cs421x_suspend, #endif }; static int patch_cs4210(struct hda_codec *codec) { struct cs_spec *spec; int err; spec = cs_alloc_spec(codec, CS4210_VENDOR_NID); if (!spec) return -ENOMEM; codec->patch_ops = cs421x_patch_ops; spec->gen.automute_hook = cs_automute; snd_hda_pick_fixup(codec, cs421x_models, cs421x_fixup_tbl, cs421x_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); /* * Update the GPIO/DMIC/SENSE_B pinmux before the configuration * is auto-parsed. If GPIO or SENSE_B is forced, DMIC input * is disabled. */ cs4210_pinmux_init(codec); err = cs421x_parse_auto_config(codec); if (err < 0) goto error; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; error: cs_free(codec); return err; } static int patch_cs4213(struct hda_codec *codec) { struct cs_spec *spec; int err; spec = cs_alloc_spec(codec, CS4213_VENDOR_NID); if (!spec) return -ENOMEM; codec->patch_ops = cs421x_patch_ops; err = cs421x_parse_auto_config(codec); if (err < 0) goto error; return 0; error: cs_free(codec); return err; } /* * patch entries */ static const struct hda_device_id snd_hda_id_cirrus[] = { HDA_CODEC_ENTRY(0x10134206, "CS4206", patch_cs420x), HDA_CODEC_ENTRY(0x10134207, "CS4207", patch_cs420x), HDA_CODEC_ENTRY(0x10134208, "CS4208", patch_cs4208), HDA_CODEC_ENTRY(0x10134210, "CS4210", patch_cs4210), HDA_CODEC_ENTRY(0x10134213, "CS4213", patch_cs4213), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cirrus); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cirrus Logic HD-audio codec"); static struct hda_codec_driver cirrus_driver = { .id = snd_hda_id_cirrus, }; module_hda_codec_driver(cirrus_driver);
linux-master
sound/pci/hda/patch_cirrus.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * HD audio interface patch for Conexant HDA audio codec * * Copyright (c) 2006 Pototskiy Akex <[email protected]> * Takashi Iwai <[email protected]> * Tobin Davis <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_beep.h" #include "hda_jack.h" #include "hda_generic.h" struct conexant_spec { struct hda_gen_spec gen; /* extra EAPD pins */ unsigned int num_eapds; hda_nid_t eapds[4]; bool dynamic_eapd; hda_nid_t mute_led_eapd; unsigned int parse_flags; /* flag for snd_hda_parse_pin_defcfg() */ /* OPLC XO specific */ bool recording; bool dc_enable; unsigned int dc_input_bias; /* offset into olpc_xo_dc_bias */ struct nid_path *dc_mode_path; int mute_led_polarity; unsigned int gpio_led; unsigned int gpio_mute_led_mask; unsigned int gpio_mic_led_mask; }; #ifdef CONFIG_SND_HDA_INPUT_BEEP /* additional beep mixers; private_value will be overwritten */ static const struct snd_kcontrol_new cxt_beep_mixer[] = { HDA_CODEC_VOLUME_MONO("Beep Playback Volume", 0, 1, 0, HDA_OUTPUT), HDA_CODEC_MUTE_BEEP_MONO("Beep Playback Switch", 0, 1, 0, HDA_OUTPUT), }; static int set_beep_amp(struct conexant_spec *spec, hda_nid_t nid, int idx, int dir) { struct snd_kcontrol_new *knew; unsigned int beep_amp = HDA_COMPOSE_AMP_VAL(nid, 1, idx, dir); int i; spec->gen.beep_nid = nid; for (i = 0; i < ARRAY_SIZE(cxt_beep_mixer); i++) { knew = snd_hda_gen_add_kctl(&spec->gen, NULL, &cxt_beep_mixer[i]); if (!knew) return -ENOMEM; knew->private_value = beep_amp; } return 0; } static int cx_auto_parse_beep(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; hda_nid_t nid; for_each_hda_codec_node(nid, codec) if (get_wcaps_type(get_wcaps(codec, nid)) == AC_WID_BEEP) return set_beep_amp(spec, nid, 0, HDA_OUTPUT); return 0; } #else #define cx_auto_parse_beep(codec) 0 #endif /* * Automatic parser for CX20641 & co */ /* parse EAPDs */ static void cx_auto_parse_eapd(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; hda_nid_t nid; for_each_hda_codec_node(nid, codec) { if (get_wcaps_type(get_wcaps(codec, nid)) != AC_WID_PIN) continue; if (!(snd_hda_query_pin_caps(codec, nid) & AC_PINCAP_EAPD)) continue; spec->eapds[spec->num_eapds++] = nid; if (spec->num_eapds >= ARRAY_SIZE(spec->eapds)) break; } /* NOTE: below is a wild guess; if we have more than two EAPDs, * it's a new chip, where EAPDs are supposed to be associated to * pins, and we can control EAPD per pin. * OTOH, if only one or two EAPDs are found, it's an old chip, * thus it might control over all pins. */ if (spec->num_eapds > 2) spec->dynamic_eapd = 1; } static void cx_auto_turn_eapd(struct hda_codec *codec, int num_pins, const hda_nid_t *pins, bool on) { int i; for (i = 0; i < num_pins; i++) { if (snd_hda_query_pin_caps(codec, pins[i]) & AC_PINCAP_EAPD) snd_hda_codec_write(codec, pins[i], 0, AC_VERB_SET_EAPD_BTLENABLE, on ? 0x02 : 0); } } /* turn on/off EAPD according to Master switch */ static void cx_auto_vmaster_hook(void *private_data, int enabled) { struct hda_codec *codec = private_data; struct conexant_spec *spec = codec->spec; cx_auto_turn_eapd(codec, spec->num_eapds, spec->eapds, enabled); } /* turn on/off EAPD according to Master switch (inversely!) for mute LED */ static int cx_auto_vmaster_mute_led(struct led_classdev *led_cdev, enum led_brightness brightness) { struct hda_codec *codec = dev_to_hda_codec(led_cdev->dev->parent); struct conexant_spec *spec = codec->spec; snd_hda_codec_write(codec, spec->mute_led_eapd, 0, AC_VERB_SET_EAPD_BTLENABLE, brightness ? 0x02 : 0x00); return 0; } static void cxt_init_gpio_led(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; unsigned int mask = spec->gpio_mute_led_mask | spec->gpio_mic_led_mask; if (mask) { snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, mask); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, mask); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_led); } } static int cx_auto_init(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; snd_hda_gen_init(codec); if (!spec->dynamic_eapd) cx_auto_turn_eapd(codec, spec->num_eapds, spec->eapds, true); cxt_init_gpio_led(codec); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT); return 0; } static void cx_auto_shutdown(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; /* Turn the problematic codec into D3 to avoid spurious noises from the internal speaker during (and after) reboot */ cx_auto_turn_eapd(codec, spec->num_eapds, spec->eapds, false); } static void cx_auto_free(struct hda_codec *codec) { cx_auto_shutdown(codec); snd_hda_gen_free(codec); } #ifdef CONFIG_PM static int cx_auto_suspend(struct hda_codec *codec) { cx_auto_shutdown(codec); return 0; } #endif static const struct hda_codec_ops cx_auto_patch_ops = { .build_controls = snd_hda_gen_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = cx_auto_init, .free = cx_auto_free, .unsol_event = snd_hda_jack_unsol_event, #ifdef CONFIG_PM .suspend = cx_auto_suspend, .check_power_status = snd_hda_gen_check_power_status, #endif }; /* * pin fix-up */ enum { CXT_PINCFG_LENOVO_X200, CXT_PINCFG_LENOVO_TP410, CXT_PINCFG_LEMOTE_A1004, CXT_PINCFG_LEMOTE_A1205, CXT_PINCFG_COMPAQ_CQ60, CXT_FIXUP_STEREO_DMIC, CXT_PINCFG_LENOVO_NOTEBOOK, CXT_FIXUP_INC_MIC_BOOST, CXT_FIXUP_HEADPHONE_MIC_PIN, CXT_FIXUP_HEADPHONE_MIC, CXT_FIXUP_GPIO1, CXT_FIXUP_ASPIRE_DMIC, CXT_FIXUP_THINKPAD_ACPI, CXT_FIXUP_OLPC_XO, CXT_FIXUP_CAP_MIX_AMP, CXT_FIXUP_TOSHIBA_P105, CXT_FIXUP_HP_530, CXT_FIXUP_CAP_MIX_AMP_5047, CXT_FIXUP_MUTE_LED_EAPD, CXT_FIXUP_HP_DOCK, CXT_FIXUP_HP_SPECTRE, CXT_FIXUP_HP_GATE_MIC, CXT_FIXUP_MUTE_LED_GPIO, CXT_FIXUP_HP_ZBOOK_MUTE_LED, CXT_FIXUP_HEADSET_MIC, CXT_FIXUP_HP_MIC_NO_PRESENCE, }; /* for hda_fixup_thinkpad_acpi() */ #include "thinkpad_helper.c" static void cxt_fixup_stereo_dmic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct conexant_spec *spec = codec->spec; spec->gen.inv_dmic_split = 1; } static void cxt5066_increase_mic_boost(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; snd_hda_override_amp_caps(codec, 0x17, HDA_OUTPUT, (0x3 << AC_AMPCAP_OFFSET_SHIFT) | (0x4 << AC_AMPCAP_NUM_STEPS_SHIFT) | (0x27 << AC_AMPCAP_STEP_SIZE_SHIFT) | (0 << AC_AMPCAP_MUTE_SHIFT)); } static void cxt_update_headset_mode(struct hda_codec *codec) { /* The verbs used in this function were tested on a Conexant CX20751/2 codec. */ int i; bool mic_mode = false; struct conexant_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->gen.autocfg; hda_nid_t mux_pin = spec->gen.imux_pins[spec->gen.cur_mux[0]]; for (i = 0; i < cfg->num_inputs; i++) if (cfg->inputs[i].pin == mux_pin) { mic_mode = !!cfg->inputs[i].is_headphone_mic; break; } if (mic_mode) { snd_hda_codec_write_cache(codec, 0x1c, 0, 0x410, 0x7c); /* enable merged mode for analog int-mic */ spec->gen.hp_jack_present = false; } else { snd_hda_codec_write_cache(codec, 0x1c, 0, 0x410, 0x54); /* disable merged mode for analog int-mic */ spec->gen.hp_jack_present = snd_hda_jack_detect(codec, spec->gen.autocfg.hp_pins[0]); } snd_hda_gen_update_outputs(codec); } static void cxt_update_headset_mode_hook(struct hda_codec *codec, struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { cxt_update_headset_mode(codec); } static void cxt_fixup_headphone_mic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct conexant_spec *spec = codec->spec; switch (action) { case HDA_FIXUP_ACT_PRE_PROBE: spec->parse_flags |= HDA_PINCFG_HEADPHONE_MIC; snd_hdac_regmap_add_vendor_verb(&codec->core, 0x410); break; case HDA_FIXUP_ACT_PROBE: WARN_ON(spec->gen.cap_sync_hook); spec->gen.cap_sync_hook = cxt_update_headset_mode_hook; spec->gen.automute_hook = cxt_update_headset_mode; break; case HDA_FIXUP_ACT_INIT: cxt_update_headset_mode(codec); break; } } static void cxt_fixup_headset_mic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct conexant_spec *spec = codec->spec; switch (action) { case HDA_FIXUP_ACT_PRE_PROBE: spec->parse_flags |= HDA_PINCFG_HEADSET_MIC; break; } } /* OPLC XO 1.5 fixup */ /* OLPC XO-1.5 supports DC input mode (e.g. for use with analog sensors) * through the microphone jack. * When the user enables this through a mixer switch, both internal and * external microphones are disabled. Gain is fixed at 0dB. In this mode, * we also allow the bias to be configured through a separate mixer * control. */ #define update_mic_pin(codec, nid, val) \ snd_hda_codec_write_cache(codec, nid, 0, \ AC_VERB_SET_PIN_WIDGET_CONTROL, val) static const struct hda_input_mux olpc_xo_dc_bias = { .num_items = 3, .items = { { "Off", PIN_IN }, { "50%", PIN_VREF50 }, { "80%", PIN_VREF80 }, }, }; static void olpc_xo_update_mic_boost(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; int ch, val; for (ch = 0; ch < 2; ch++) { val = AC_AMP_SET_OUTPUT | (ch ? AC_AMP_SET_RIGHT : AC_AMP_SET_LEFT); if (!spec->dc_enable) val |= snd_hda_codec_amp_read(codec, 0x17, ch, HDA_OUTPUT, 0); snd_hda_codec_write(codec, 0x17, 0, AC_VERB_SET_AMP_GAIN_MUTE, val); } } static void olpc_xo_update_mic_pins(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; int cur_input, val; struct nid_path *path; cur_input = spec->gen.input_paths[0][spec->gen.cur_mux[0]]; /* Set up mic pins for port-B, C and F dynamically as the recording * LED is turned on/off by these pin controls */ if (!spec->dc_enable) { /* disable DC bias path and pin for port F */ update_mic_pin(codec, 0x1e, 0); snd_hda_activate_path(codec, spec->dc_mode_path, false, false); /* update port B (ext mic) and C (int mic) */ /* OLPC defers mic widget control until when capture is * started because the microphone LED comes on as soon as * these settings are put in place. if we did this before * recording, it would give the false indication that * recording is happening when it is not. */ update_mic_pin(codec, 0x1a, spec->recording ? snd_hda_codec_get_pin_target(codec, 0x1a) : 0); update_mic_pin(codec, 0x1b, spec->recording ? snd_hda_codec_get_pin_target(codec, 0x1b) : 0); /* enable normal mic path */ path = snd_hda_get_path_from_idx(codec, cur_input); if (path) snd_hda_activate_path(codec, path, true, false); } else { /* disable normal mic path */ path = snd_hda_get_path_from_idx(codec, cur_input); if (path) snd_hda_activate_path(codec, path, false, false); /* Even though port F is the DC input, the bias is controlled * on port B. We also leave that port as an active input (but * unselected) in DC mode just in case that is necessary to * make the bias setting take effect. */ if (spec->recording) val = olpc_xo_dc_bias.items[spec->dc_input_bias].index; else val = 0; update_mic_pin(codec, 0x1a, val); update_mic_pin(codec, 0x1b, 0); /* enable DC bias path and pin */ update_mic_pin(codec, 0x1e, spec->recording ? PIN_IN : 0); snd_hda_activate_path(codec, spec->dc_mode_path, true, false); } } /* mic_autoswitch hook */ static void olpc_xo_automic(struct hda_codec *codec, struct hda_jack_callback *jack) { struct conexant_spec *spec = codec->spec; /* in DC mode, we don't handle automic */ if (!spec->dc_enable) snd_hda_gen_mic_autoswitch(codec, jack); olpc_xo_update_mic_pins(codec); if (spec->dc_enable) olpc_xo_update_mic_boost(codec); } /* pcm_capture hook */ static void olpc_xo_capture_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { struct conexant_spec *spec = codec->spec; /* toggle spec->recording flag and update mic pins accordingly * for turning on/off LED */ switch (action) { case HDA_GEN_PCM_ACT_PREPARE: spec->recording = 1; olpc_xo_update_mic_pins(codec); break; case HDA_GEN_PCM_ACT_CLEANUP: spec->recording = 0; olpc_xo_update_mic_pins(codec); break; } } static int olpc_xo_dc_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct conexant_spec *spec = codec->spec; ucontrol->value.integer.value[0] = spec->dc_enable; return 0; } static int olpc_xo_dc_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct conexant_spec *spec = codec->spec; int dc_enable = !!ucontrol->value.integer.value[0]; if (dc_enable == spec->dc_enable) return 0; spec->dc_enable = dc_enable; olpc_xo_update_mic_pins(codec); olpc_xo_update_mic_boost(codec); return 1; } static int olpc_xo_dc_bias_enum_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct conexant_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->dc_input_bias; return 0; } static int olpc_xo_dc_bias_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { return snd_hda_input_mux_info(&olpc_xo_dc_bias, uinfo); } static int olpc_xo_dc_bias_enum_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct conexant_spec *spec = codec->spec; const struct hda_input_mux *imux = &olpc_xo_dc_bias; unsigned int idx; idx = ucontrol->value.enumerated.item[0]; if (idx >= imux->num_items) idx = imux->num_items - 1; if (spec->dc_input_bias == idx) return 0; spec->dc_input_bias = idx; if (spec->dc_enable) olpc_xo_update_mic_pins(codec); return 1; } static const struct snd_kcontrol_new olpc_xo_mixers[] = { { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DC Mode Enable Switch", .info = snd_ctl_boolean_mono_info, .get = olpc_xo_dc_mode_get, .put = olpc_xo_dc_mode_put, }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DC Input Bias Enum", .info = olpc_xo_dc_bias_enum_info, .get = olpc_xo_dc_bias_enum_get, .put = olpc_xo_dc_bias_enum_put, }, {} }; /* overriding mic boost put callback; update mic boost volume only when * DC mode is disabled */ static int olpc_xo_mic_boost_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct conexant_spec *spec = codec->spec; int ret = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); if (ret > 0 && spec->dc_enable) olpc_xo_update_mic_boost(codec); return ret; } static void cxt_fixup_olpc_xo(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct conexant_spec *spec = codec->spec; struct snd_kcontrol_new *kctl; int i; if (action != HDA_FIXUP_ACT_PROBE) return; spec->gen.mic_autoswitch_hook = olpc_xo_automic; spec->gen.pcm_capture_hook = olpc_xo_capture_hook; spec->dc_mode_path = snd_hda_add_new_path(codec, 0x1e, 0x14, 0); snd_hda_add_new_ctls(codec, olpc_xo_mixers); /* OLPC's microphone port is DC coupled for use with external sensors, * therefore we use a 50% mic bias in order to center the input signal * with the DC input range of the codec. */ snd_hda_codec_set_pin_target(codec, 0x1a, PIN_VREF50); /* override mic boost control */ snd_array_for_each(&spec->gen.kctls, i, kctl) { if (!strcmp(kctl->name, "Mic Boost Volume")) { kctl->put = olpc_xo_mic_boost_put; break; } } } static void cxt_fixup_mute_led_eapd(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct conexant_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { spec->mute_led_eapd = 0x1b; spec->dynamic_eapd = true; snd_hda_gen_add_mute_led_cdev(codec, cx_auto_vmaster_mute_led); } } /* * Fix max input level on mixer widget to 0dB * (originally it has 0x2b steps with 0dB offset 0x14) */ static void cxt_fixup_cap_mix_amp(struct hda_codec *codec, const struct hda_fixup *fix, int action) { snd_hda_override_amp_caps(codec, 0x17, HDA_INPUT, (0x14 << AC_AMPCAP_OFFSET_SHIFT) | (0x14 << AC_AMPCAP_NUM_STEPS_SHIFT) | (0x05 << AC_AMPCAP_STEP_SIZE_SHIFT) | (1 << AC_AMPCAP_MUTE_SHIFT)); } /* * Fix max input level on mixer widget to 0dB * (originally it has 0x1e steps with 0 dB offset 0x17) */ static void cxt_fixup_cap_mix_amp_5047(struct hda_codec *codec, const struct hda_fixup *fix, int action) { snd_hda_override_amp_caps(codec, 0x10, HDA_INPUT, (0x17 << AC_AMPCAP_OFFSET_SHIFT) | (0x17 << AC_AMPCAP_NUM_STEPS_SHIFT) | (0x05 << AC_AMPCAP_STEP_SIZE_SHIFT) | (1 << AC_AMPCAP_MUTE_SHIFT)); } static void cxt_fixup_hp_gate_mic_jack(struct hda_codec *codec, const struct hda_fixup *fix, int action) { /* the mic pin (0x19) doesn't give an unsolicited event; * probe the mic pin together with the headphone pin (0x16) */ if (action == HDA_FIXUP_ACT_PROBE) snd_hda_jack_set_gating_jack(codec, 0x19, 0x16); } /* update LED status via GPIO */ static void cxt_update_gpio_led(struct hda_codec *codec, unsigned int mask, bool led_on) { struct conexant_spec *spec = codec->spec; unsigned int oldval = spec->gpio_led; if (spec->mute_led_polarity) led_on = !led_on; if (led_on) spec->gpio_led |= mask; else spec->gpio_led &= ~mask; codec_dbg(codec, "mask:%d enabled:%d gpio_led:%d\n", mask, led_on, spec->gpio_led); if (spec->gpio_led != oldval) snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_led); } /* turn on/off mute LED via GPIO per vmaster hook */ static int cxt_gpio_mute_update(struct led_classdev *led_cdev, enum led_brightness brightness) { struct hda_codec *codec = dev_to_hda_codec(led_cdev->dev->parent); struct conexant_spec *spec = codec->spec; cxt_update_gpio_led(codec, spec->gpio_mute_led_mask, brightness); return 0; } /* turn on/off mic-mute LED via GPIO per capture hook */ static int cxt_gpio_micmute_update(struct led_classdev *led_cdev, enum led_brightness brightness) { struct hda_codec *codec = dev_to_hda_codec(led_cdev->dev->parent); struct conexant_spec *spec = codec->spec; cxt_update_gpio_led(codec, spec->gpio_mic_led_mask, brightness); return 0; } static void cxt_setup_mute_led(struct hda_codec *codec, unsigned int mute, unsigned int mic_mute) { struct conexant_spec *spec = codec->spec; spec->gpio_led = 0; spec->mute_led_polarity = 0; if (mute) { snd_hda_gen_add_mute_led_cdev(codec, cxt_gpio_mute_update); spec->gpio_mute_led_mask = mute; } if (mic_mute) { snd_hda_gen_add_micmute_led_cdev(codec, cxt_gpio_micmute_update); spec->gpio_mic_led_mask = mic_mute; } } static void cxt_fixup_mute_led_gpio(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) cxt_setup_mute_led(codec, 0x01, 0x02); } static void cxt_fixup_hp_zbook_mute_led(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) cxt_setup_mute_led(codec, 0x10, 0x20); } /* ThinkPad X200 & co with cxt5051 */ static const struct hda_pintbl cxt_pincfg_lenovo_x200[] = { { 0x16, 0x042140ff }, /* HP (seq# overridden) */ { 0x17, 0x21a11000 }, /* dock-mic */ { 0x19, 0x2121103f }, /* dock-HP */ { 0x1c, 0x21440100 }, /* dock SPDIF out */ {} }; /* ThinkPad 410/420/510/520, X201 & co with cxt5066 */ static const struct hda_pintbl cxt_pincfg_lenovo_tp410[] = { { 0x19, 0x042110ff }, /* HP (seq# overridden) */ { 0x1a, 0x21a190f0 }, /* dock-mic */ { 0x1c, 0x212140ff }, /* dock-HP */ {} }; /* Lemote A1004/A1205 with cxt5066 */ static const struct hda_pintbl cxt_pincfg_lemote[] = { { 0x1a, 0x90a10020 }, /* Internal mic */ { 0x1b, 0x03a11020 }, /* External mic */ { 0x1d, 0x400101f0 }, /* Not used */ { 0x1e, 0x40a701f0 }, /* Not used */ { 0x20, 0x404501f0 }, /* Not used */ { 0x22, 0x404401f0 }, /* Not used */ { 0x23, 0x40a701f0 }, /* Not used */ {} }; static const struct hda_fixup cxt_fixups[] = { [CXT_PINCFG_LENOVO_X200] = { .type = HDA_FIXUP_PINS, .v.pins = cxt_pincfg_lenovo_x200, }, [CXT_PINCFG_LENOVO_TP410] = { .type = HDA_FIXUP_PINS, .v.pins = cxt_pincfg_lenovo_tp410, .chained = true, .chain_id = CXT_FIXUP_THINKPAD_ACPI, }, [CXT_PINCFG_LEMOTE_A1004] = { .type = HDA_FIXUP_PINS, .chained = true, .chain_id = CXT_FIXUP_INC_MIC_BOOST, .v.pins = cxt_pincfg_lemote, }, [CXT_PINCFG_LEMOTE_A1205] = { .type = HDA_FIXUP_PINS, .v.pins = cxt_pincfg_lemote, }, [CXT_PINCFG_COMPAQ_CQ60] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* 0x17 was falsely set up as a mic, it should 0x1d */ { 0x17, 0x400001f0 }, { 0x1d, 0x97a70120 }, { } } }, [CXT_FIXUP_STEREO_DMIC] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_stereo_dmic, }, [CXT_PINCFG_LENOVO_NOTEBOOK] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x1a, 0x05d71030 }, { } }, .chain_id = CXT_FIXUP_STEREO_DMIC, }, [CXT_FIXUP_INC_MIC_BOOST] = { .type = HDA_FIXUP_FUNC, .v.func = cxt5066_increase_mic_boost, }, [CXT_FIXUP_HEADPHONE_MIC_PIN] = { .type = HDA_FIXUP_PINS, .chained = true, .chain_id = CXT_FIXUP_HEADPHONE_MIC, .v.pins = (const struct hda_pintbl[]) { { 0x18, 0x03a1913d }, /* use as headphone mic, without its own jack detect */ { } } }, [CXT_FIXUP_HEADPHONE_MIC] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_headphone_mic, }, [CXT_FIXUP_GPIO1] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { { 0x01, AC_VERB_SET_GPIO_MASK, 0x01 }, { 0x01, AC_VERB_SET_GPIO_DIRECTION, 0x01 }, { 0x01, AC_VERB_SET_GPIO_DATA, 0x01 }, { } }, }, [CXT_FIXUP_ASPIRE_DMIC] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_stereo_dmic, .chained = true, .chain_id = CXT_FIXUP_GPIO1, }, [CXT_FIXUP_THINKPAD_ACPI] = { .type = HDA_FIXUP_FUNC, .v.func = hda_fixup_thinkpad_acpi, }, [CXT_FIXUP_OLPC_XO] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_olpc_xo, }, [CXT_FIXUP_CAP_MIX_AMP] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_cap_mix_amp, }, [CXT_FIXUP_TOSHIBA_P105] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x10, 0x961701f0 }, /* speaker/hp */ { 0x12, 0x02a1901e }, /* ext mic */ { 0x14, 0x95a70110 }, /* int mic */ {} }, }, [CXT_FIXUP_HP_530] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x12, 0x90a60160 }, /* int mic */ {} }, .chained = true, .chain_id = CXT_FIXUP_CAP_MIX_AMP, }, [CXT_FIXUP_CAP_MIX_AMP_5047] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_cap_mix_amp_5047, }, [CXT_FIXUP_MUTE_LED_EAPD] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_mute_led_eapd, }, [CXT_FIXUP_HP_DOCK] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x16, 0x21011020 }, /* line-out */ { 0x18, 0x2181103f }, /* line-in */ { } }, .chained = true, .chain_id = CXT_FIXUP_MUTE_LED_GPIO, }, [CXT_FIXUP_HP_SPECTRE] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* enable NID 0x1d for the speaker on top */ { 0x1d, 0x91170111 }, { } } }, [CXT_FIXUP_HP_GATE_MIC] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_hp_gate_mic_jack, }, [CXT_FIXUP_MUTE_LED_GPIO] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_mute_led_gpio, }, [CXT_FIXUP_HP_ZBOOK_MUTE_LED] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_hp_zbook_mute_led, }, [CXT_FIXUP_HEADSET_MIC] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_headset_mic, }, [CXT_FIXUP_HP_MIC_NO_PRESENCE] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x1a, 0x02a1113c }, { } }, .chained = true, .chain_id = CXT_FIXUP_HEADSET_MIC, }, }; static const struct snd_pci_quirk cxt5045_fixups[] = { SND_PCI_QUIRK(0x103c, 0x30d5, "HP 530", CXT_FIXUP_HP_530), SND_PCI_QUIRK(0x1179, 0xff31, "Toshiba P105", CXT_FIXUP_TOSHIBA_P105), /* HP, Packard Bell, Fujitsu-Siemens & Lenovo laptops have * really bad sound over 0dB on NID 0x17. */ SND_PCI_QUIRK_VENDOR(0x103c, "HP", CXT_FIXUP_CAP_MIX_AMP), SND_PCI_QUIRK_VENDOR(0x1631, "Packard Bell", CXT_FIXUP_CAP_MIX_AMP), SND_PCI_QUIRK_VENDOR(0x1734, "Fujitsu", CXT_FIXUP_CAP_MIX_AMP), SND_PCI_QUIRK_VENDOR(0x17aa, "Lenovo", CXT_FIXUP_CAP_MIX_AMP), {} }; static const struct hda_model_fixup cxt5045_fixup_models[] = { { .id = CXT_FIXUP_CAP_MIX_AMP, .name = "cap-mix-amp" }, { .id = CXT_FIXUP_TOSHIBA_P105, .name = "toshiba-p105" }, { .id = CXT_FIXUP_HP_530, .name = "hp-530" }, {} }; static const struct snd_pci_quirk cxt5047_fixups[] = { /* HP laptops have really bad sound over 0 dB on NID 0x10. */ SND_PCI_QUIRK_VENDOR(0x103c, "HP", CXT_FIXUP_CAP_MIX_AMP_5047), {} }; static const struct hda_model_fixup cxt5047_fixup_models[] = { { .id = CXT_FIXUP_CAP_MIX_AMP_5047, .name = "cap-mix-amp" }, {} }; static const struct snd_pci_quirk cxt5051_fixups[] = { SND_PCI_QUIRK(0x103c, 0x360b, "Compaq CQ60", CXT_PINCFG_COMPAQ_CQ60), SND_PCI_QUIRK(0x17aa, 0x20f2, "Lenovo X200", CXT_PINCFG_LENOVO_X200), {} }; static const struct hda_model_fixup cxt5051_fixup_models[] = { { .id = CXT_PINCFG_LENOVO_X200, .name = "lenovo-x200" }, {} }; static const struct snd_pci_quirk cxt5066_fixups[] = { SND_PCI_QUIRK(0x1025, 0x0543, "Acer Aspire One 522", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x1025, 0x054c, "Acer Aspire 3830TG", CXT_FIXUP_ASPIRE_DMIC), SND_PCI_QUIRK(0x1025, 0x054f, "Acer Aspire 4830T", CXT_FIXUP_ASPIRE_DMIC), SND_PCI_QUIRK(0x103c, 0x8079, "HP EliteBook 840 G3", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x807C, "HP EliteBook 820 G3", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x80FD, "HP ProBook 640 G2", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x8115, "HP Z1 Gen3", CXT_FIXUP_HP_GATE_MIC), SND_PCI_QUIRK(0x103c, 0x814f, "HP ZBook 15u G3", CXT_FIXUP_MUTE_LED_GPIO), SND_PCI_QUIRK(0x103c, 0x8174, "HP Spectre x360", CXT_FIXUP_HP_SPECTRE), SND_PCI_QUIRK(0x103c, 0x822e, "HP ProBook 440 G4", CXT_FIXUP_MUTE_LED_GPIO), SND_PCI_QUIRK(0x103c, 0x828c, "HP EliteBook 840 G4", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x8299, "HP 800 G3 SFF", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x829a, "HP 800 G3 DM", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x82b4, "HP ProDesk 600 G3", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x836e, "HP ProBook 455 G5", CXT_FIXUP_MUTE_LED_GPIO), SND_PCI_QUIRK(0x103c, 0x837f, "HP ProBook 470 G5", CXT_FIXUP_MUTE_LED_GPIO), SND_PCI_QUIRK(0x103c, 0x83b2, "HP EliteBook 840 G5", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x83b3, "HP EliteBook 830 G5", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x83d3, "HP ProBook 640 G4", CXT_FIXUP_HP_DOCK), SND_PCI_QUIRK(0x103c, 0x8402, "HP ProBook 645 G4", CXT_FIXUP_MUTE_LED_GPIO), SND_PCI_QUIRK(0x103c, 0x8427, "HP ZBook Studio G5", CXT_FIXUP_HP_ZBOOK_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x844f, "HP ZBook Studio G5", CXT_FIXUP_HP_ZBOOK_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x8455, "HP Z2 G4", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x8456, "HP Z2 G4 SFF", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x8457, "HP Z2 G4 mini", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x8458, "HP Z2 G4 mini premium", CXT_FIXUP_HP_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1043, 0x138d, "Asus", CXT_FIXUP_HEADPHONE_MIC_PIN), SND_PCI_QUIRK(0x152d, 0x0833, "OLPC XO-1.5", CXT_FIXUP_OLPC_XO), SND_PCI_QUIRK(0x17aa, 0x20f2, "Lenovo T400", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x215e, "Lenovo T410", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x215f, "Lenovo T510", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x21ce, "Lenovo T420", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x21cf, "Lenovo T520", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x21d2, "Lenovo T420s", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x21da, "Lenovo X220", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x21db, "Lenovo X220-tablet", CXT_PINCFG_LENOVO_TP410), SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo IdeaPad Z560", CXT_FIXUP_MUTE_LED_EAPD), SND_PCI_QUIRK(0x17aa, 0x3905, "Lenovo G50-30", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x390b, "Lenovo G50-80", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC), /* NOTE: we'd need to extend the quirk for 17aa:3977 as the same * PCI SSID is used on multiple Lenovo models */ SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3978, "Lenovo G50-70", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI), SND_PCI_QUIRK(0x1c06, 0x2011, "Lemote A1004", CXT_PINCFG_LEMOTE_A1004), SND_PCI_QUIRK(0x1c06, 0x2012, "Lemote A1205", CXT_PINCFG_LEMOTE_A1205), {} }; static const struct hda_model_fixup cxt5066_fixup_models[] = { { .id = CXT_FIXUP_STEREO_DMIC, .name = "stereo-dmic" }, { .id = CXT_FIXUP_GPIO1, .name = "gpio1" }, { .id = CXT_FIXUP_HEADPHONE_MIC_PIN, .name = "headphone-mic-pin" }, { .id = CXT_PINCFG_LENOVO_TP410, .name = "tp410" }, { .id = CXT_FIXUP_THINKPAD_ACPI, .name = "thinkpad" }, { .id = CXT_PINCFG_LEMOTE_A1004, .name = "lemote-a1004" }, { .id = CXT_PINCFG_LEMOTE_A1205, .name = "lemote-a1205" }, { .id = CXT_FIXUP_OLPC_XO, .name = "olpc-xo" }, { .id = CXT_FIXUP_MUTE_LED_EAPD, .name = "mute-led-eapd" }, { .id = CXT_FIXUP_HP_DOCK, .name = "hp-dock" }, { .id = CXT_FIXUP_MUTE_LED_GPIO, .name = "mute-led-gpio" }, { .id = CXT_FIXUP_HP_ZBOOK_MUTE_LED, .name = "hp-zbook-mute-led" }, { .id = CXT_FIXUP_HP_MIC_NO_PRESENCE, .name = "hp-mic-fix" }, { .id = CXT_PINCFG_LENOVO_NOTEBOOK, .name = "lenovo-20149" }, {} }; /* add "fake" mute amp-caps to DACs on cx5051 so that mixer mute switches * can be created (bko#42825) */ static void add_cx5051_fake_mutes(struct hda_codec *codec) { struct conexant_spec *spec = codec->spec; static const hda_nid_t out_nids[] = { 0x10, 0x11, 0 }; const hda_nid_t *p; for (p = out_nids; *p; p++) snd_hda_override_amp_caps(codec, *p, HDA_OUTPUT, AC_AMPCAP_MIN_MUTE | query_amp_caps(codec, *p, HDA_OUTPUT)); spec->gen.dac_min_mute = true; } static int patch_conexant_auto(struct hda_codec *codec) { struct conexant_spec *spec; int err; codec_info(codec, "%s: BIOS auto-probing.\n", codec->core.chip_name); spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return -ENOMEM; snd_hda_gen_spec_init(&spec->gen); codec->spec = spec; codec->patch_ops = cx_auto_patch_ops; cx_auto_parse_eapd(codec); spec->gen.own_eapd_ctl = 1; switch (codec->core.vendor_id) { case 0x14f15045: codec->single_adc_amp = 1; spec->gen.mixer_nid = 0x17; spec->gen.add_stereo_mix_input = HDA_HINT_STEREO_MIX_AUTO; snd_hda_pick_fixup(codec, cxt5045_fixup_models, cxt5045_fixups, cxt_fixups); break; case 0x14f15047: codec->pin_amp_workaround = 1; spec->gen.mixer_nid = 0x19; spec->gen.add_stereo_mix_input = HDA_HINT_STEREO_MIX_AUTO; snd_hda_pick_fixup(codec, cxt5047_fixup_models, cxt5047_fixups, cxt_fixups); break; case 0x14f15051: add_cx5051_fake_mutes(codec); codec->pin_amp_workaround = 1; snd_hda_pick_fixup(codec, cxt5051_fixup_models, cxt5051_fixups, cxt_fixups); break; case 0x14f15098: codec->pin_amp_workaround = 1; spec->gen.mixer_nid = 0x22; spec->gen.add_stereo_mix_input = HDA_HINT_STEREO_MIX_AUTO; snd_hda_pick_fixup(codec, cxt5066_fixup_models, cxt5066_fixups, cxt_fixups); break; case 0x14f150f2: codec->power_save_node = 1; fallthrough; default: codec->pin_amp_workaround = 1; snd_hda_pick_fixup(codec, cxt5066_fixup_models, cxt5066_fixups, cxt_fixups); break; } if (!spec->gen.vmaster_mute.hook && spec->dynamic_eapd) spec->gen.vmaster_mute.hook = cx_auto_vmaster_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, spec->parse_flags); if (err < 0) goto error; err = cx_auto_parse_beep(codec); if (err < 0) goto error; err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) goto error; /* Some laptops with Conexant chips show stalls in S3 resume, * which falls into the single-cmd mode. * Better to make reset, then. */ if (!codec->bus->core.sync_write) { codec_info(codec, "Enable sync_write for stable communication\n"); codec->bus->core.sync_write = 1; codec->bus->allow_bus_reset = 1; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; error: cx_auto_free(codec); return err; } /* */ static const struct hda_device_id snd_hda_id_conexant[] = { HDA_CODEC_ENTRY(0x14f11f86, "CX8070", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f11f87, "SN6140", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f12008, "CX8200", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f120d0, "CX11970", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f120d1, "SN6180", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15045, "CX20549 (Venice)", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15047, "CX20551 (Waikiki)", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15051, "CX20561 (Hermosa)", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15066, "CX20582 (Pebble)", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15067, "CX20583 (Pebble HSF)", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15068, "CX20584", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15069, "CX20585", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f1506c, "CX20588", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f1506e, "CX20590", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15097, "CX20631", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15098, "CX20632", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150a1, "CX20641", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150a2, "CX20642", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150ab, "CX20651", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150ac, "CX20652", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150b8, "CX20664", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150b9, "CX20665", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150f1, "CX21722", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150f2, "CX20722", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150f3, "CX21724", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f150f4, "CX20724", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f1510f, "CX20751/2", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15110, "CX20751/2", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15111, "CX20753/4", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15113, "CX20755", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15114, "CX20756", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f15115, "CX20757", patch_conexant_auto), HDA_CODEC_ENTRY(0x14f151d7, "CX20952", patch_conexant_auto), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_conexant); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Conexant HD-audio codec"); static struct hda_codec_driver conexant_driver = { .id = snd_hda_id_conexant, }; module_hda_codec_driver(conexant_driver);
linux-master
sound/pci/hda/patch_conexant.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * * hda_intel.c - Implementation of primary alsa driver code base * for Intel HD Audio. * * Copyright(c) 2004 Intel Corporation. All rights reserved. * * Copyright (c) 2004 Takashi Iwai <[email protected]> * PeiSen Hou <[email protected]> * * CONTACTS: * * Matt Jared [email protected] * Andy Kopp [email protected] * Dan Kogan [email protected] * * CHANGES: * * 2004.12.01 Major rewrite by tiwai, merged the work of pshou */ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/dma-mapping.h> #include <linux/moduleparam.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/mutex.h> #include <linux/io.h> #include <linux/pm_runtime.h> #include <linux/clocksource.h> #include <linux/time.h> #include <linux/completion.h> #include <linux/acpi.h> #include <linux/pgtable.h> #ifdef CONFIG_X86 /* for snoop control */ #include <asm/set_memory.h> #include <asm/cpufeature.h> #endif #include <sound/core.h> #include <sound/initval.h> #include <sound/hdaudio.h> #include <sound/hda_i915.h> #include <sound/intel-dsp-config.h> #include <linux/vgaarb.h> #include <linux/vga_switcheroo.h> #include <linux/apple-gmux.h> #include <linux/firmware.h> #include <sound/hda_codec.h> #include "hda_controller.h" #include "hda_intel.h" #define CREATE_TRACE_POINTS #include "hda_intel_trace.h" /* position fix mode */ enum { POS_FIX_AUTO, POS_FIX_LPIB, POS_FIX_POSBUF, POS_FIX_VIACOMBO, POS_FIX_COMBO, POS_FIX_SKL, POS_FIX_FIFO, }; /* Defines for ATI HD Audio support in SB450 south bridge */ #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 /* Defines for Nvidia HDA support */ #define NVIDIA_HDA_TRANSREG_ADDR 0x4e #define NVIDIA_HDA_ENABLE_COHBITS 0x0f #define NVIDIA_HDA_ISTRM_COH 0x4d #define NVIDIA_HDA_OSTRM_COH 0x4c #define NVIDIA_HDA_ENABLE_COHBIT 0x01 /* Defines for Intel SCH HDA snoop control */ #define INTEL_HDA_CGCTL 0x48 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) #define INTEL_SCH_HDA_DEVC 0x78 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) /* max number of SDs */ /* ICH, ATI and VIA have 4 playback and 4 capture */ #define ICH6_NUM_CAPTURE 4 #define ICH6_NUM_PLAYBACK 4 /* ULI has 6 playback and 5 capture */ #define ULI_NUM_CAPTURE 5 #define ULI_NUM_PLAYBACK 6 /* ATI HDMI may have up to 8 playbacks and 0 capture */ #define ATIHDMI_NUM_CAPTURE 0 #define ATIHDMI_NUM_PLAYBACK 8 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; static char *model[SNDRV_CARDS]; static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; static int probe_only[SNDRV_CARDS]; static int jackpoll_ms[SNDRV_CARDS]; static int single_cmd = -1; static int enable_msi = -1; #ifdef CONFIG_SND_HDA_PATCH_LOADER static char *patch[SNDRV_CARDS]; #endif #ifdef CONFIG_SND_HDA_INPUT_BEEP static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = CONFIG_SND_HDA_INPUT_BEEP_MODE}; #endif static bool dmic_detect = 1; static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); module_param_array(model, charp, NULL, 0444); MODULE_PARM_DESC(model, "Use the given board model."); module_param_array(position_fix, int, NULL, 0444); MODULE_PARM_DESC(position_fix, "DMA pointer read method." "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); module_param_array(bdl_pos_adj, int, NULL, 0644); MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); module_param_array(probe_mask, int, NULL, 0444); MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); module_param_array(probe_only, int, NULL, 0444); MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); module_param_array(jackpoll_ms, int, NULL, 0444); MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); module_param(single_cmd, bint, 0444); MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " "(for debugging only)."); module_param(enable_msi, bint, 0444); MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); #ifdef CONFIG_SND_HDA_PATCH_LOADER module_param_array(patch, charp, NULL, 0444); MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); #endif #ifdef CONFIG_SND_HDA_INPUT_BEEP module_param_array(beep_mode, bool, NULL, 0444); MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " "(0=off, 1=on) (default=1)."); #endif module_param(dmic_detect, bool, 0444); MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " "(0=off, 1=on) (default=1); " "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); module_param(ctl_dev_id, bool, 0444); MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); #ifdef CONFIG_PM static int param_set_xint(const char *val, const struct kernel_param *kp); static const struct kernel_param_ops param_ops_xint = { .set = param_set_xint, .get = param_get_int, }; #define param_check_xint param_check_int static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; module_param(power_save, xint, 0644); MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " "(in second, 0 = disable)."); static bool pm_blacklist = true; module_param(pm_blacklist, bool, 0644); MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); /* reset the HD-audio controller in power save mode. * this may give more power-saving, but will take longer time to * wake up. */ static bool power_save_controller = 1; module_param(power_save_controller, bool, 0644); MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); #else #define power_save 0 #endif /* CONFIG_PM */ static int align_buffer_size = -1; module_param(align_buffer_size, bint, 0644); MODULE_PARM_DESC(align_buffer_size, "Force buffer and period sizes to be multiple of 128 bytes."); #ifdef CONFIG_X86 static int hda_snoop = -1; module_param_named(snoop, hda_snoop, bint, 0444); MODULE_PARM_DESC(snoop, "Enable/disable snooping"); #else #define hda_snoop true #endif MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Intel HDA driver"); #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) #define SUPPORT_VGA_SWITCHEROO #endif #endif /* */ /* driver types */ enum { AZX_DRIVER_ICH, AZX_DRIVER_PCH, AZX_DRIVER_SCH, AZX_DRIVER_SKL, AZX_DRIVER_HDMI, AZX_DRIVER_ATI, AZX_DRIVER_ATIHDMI, AZX_DRIVER_ATIHDMI_NS, AZX_DRIVER_GFHDMI, AZX_DRIVER_VIA, AZX_DRIVER_SIS, AZX_DRIVER_ULI, AZX_DRIVER_NVIDIA, AZX_DRIVER_TERA, AZX_DRIVER_CTX, AZX_DRIVER_CTHDA, AZX_DRIVER_CMEDIA, AZX_DRIVER_ZHAOXIN, AZX_DRIVER_LOONGSON, AZX_DRIVER_GENERIC, AZX_NUM_DRIVERS, /* keep this as last entry */ }; #define azx_get_snoop_type(chip) \ (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) /* quirks for old Intel chipsets */ #define AZX_DCAPS_INTEL_ICH \ (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) /* quirks for Intel PCH */ #define AZX_DCAPS_INTEL_PCH_BASE \ (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ AZX_DCAPS_SNOOP_TYPE(SCH)) /* PCH up to IVB; no runtime PM; bind with i915 gfx */ #define AZX_DCAPS_INTEL_PCH_NOPM \ (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) /* PCH for HSW/BDW; with runtime PM */ /* no i915 binding for this as HSW/BDW has another controller for HDMI */ #define AZX_DCAPS_INTEL_PCH \ (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) /* HSW HDMI */ #define AZX_DCAPS_INTEL_HASWELL \ (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ AZX_DCAPS_SNOOP_TYPE(SCH)) /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ #define AZX_DCAPS_INTEL_BROADWELL \ (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ AZX_DCAPS_SNOOP_TYPE(SCH)) #define AZX_DCAPS_INTEL_BAYTRAIL \ (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) #define AZX_DCAPS_INTEL_BRASWELL \ (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ AZX_DCAPS_I915_COMPONENT) #define AZX_DCAPS_INTEL_SKYLAKE \ (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE /* quirks for ATI SB / AMD Hudson */ #define AZX_DCAPS_PRESET_ATI_SB \ (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ AZX_DCAPS_SNOOP_TYPE(ATI)) /* quirks for ATI/AMD HDMI */ #define AZX_DCAPS_PRESET_ATI_HDMI \ (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ AZX_DCAPS_NO_MSI64) /* quirks for ATI HDMI with snoop off */ #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) /* quirks for AMD SB */ #define AZX_DCAPS_PRESET_AMD_SB \ (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ AZX_DCAPS_RETRY_PROBE) /* quirks for Nvidia */ #define AZX_DCAPS_PRESET_NVIDIA \ (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ AZX_DCAPS_SNOOP_TYPE(NVIDIA)) #define AZX_DCAPS_PRESET_CTHDA \ (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ AZX_DCAPS_NO_64BIT |\ AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) /* * vga_switcheroo support */ #ifdef SUPPORT_VGA_SWITCHEROO #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) #else #define use_vga_switcheroo(chip) 0 #define needs_eld_notify_link(chip) false #endif static const char * const driver_short_names[] = { [AZX_DRIVER_ICH] = "HDA Intel", [AZX_DRIVER_PCH] = "HDA Intel PCH", [AZX_DRIVER_SCH] = "HDA Intel MID", [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ [AZX_DRIVER_HDMI] = "HDA Intel HDMI", [AZX_DRIVER_ATI] = "HDA ATI SB", [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", [AZX_DRIVER_VIA] = "HDA VIA VT82xx", [AZX_DRIVER_SIS] = "HDA SIS966", [AZX_DRIVER_ULI] = "HDA ULI M5461", [AZX_DRIVER_NVIDIA] = "HDA NVidia", [AZX_DRIVER_TERA] = "HDA Teradici", [AZX_DRIVER_CTX] = "HDA Creative", [AZX_DRIVER_CTHDA] = "HDA Creative", [AZX_DRIVER_CMEDIA] = "HDA C-Media", [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", [AZX_DRIVER_LOONGSON] = "HDA Loongson", [AZX_DRIVER_GENERIC] = "HD-Audio Generic", }; static int azx_acquire_irq(struct azx *chip, int do_disconnect); static void set_default_power_save(struct azx *chip); /* * initialize the PCI registers */ /* update bits in a PCI register byte */ static void update_pci_byte(struct pci_dev *pci, unsigned int reg, unsigned char mask, unsigned char val) { unsigned char data; pci_read_config_byte(pci, reg, &data); data &= ~mask; data |= (val & mask); pci_write_config_byte(pci, reg, data); } static void azx_init_pci(struct azx *chip) { int snoop_type = azx_get_snoop_type(chip); /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) * TCSEL == Traffic Class Select Register, which sets PCI express QOS * Ensuring these bits are 0 clears playback static on some HD Audio * codecs. * The PCI register TCSEL is defined in the Intel manuals. */ if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { dev_dbg(chip->card->dev, "Clearing TCSEL\n"); update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); } /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, * we need to enable snoop. */ if (snoop_type == AZX_SNOOP_TYPE_ATI) { dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", azx_snoop(chip)); update_pci_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); } /* For NVIDIA HDA, enable snoop */ if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", azx_snoop(chip)); update_pci_byte(chip->pci, NVIDIA_HDA_TRANSREG_ADDR, 0x0f, NVIDIA_HDA_ENABLE_COHBITS); update_pci_byte(chip->pci, NVIDIA_HDA_ISTRM_COH, 0x01, NVIDIA_HDA_ENABLE_COHBIT); update_pci_byte(chip->pci, NVIDIA_HDA_OSTRM_COH, 0x01, NVIDIA_HDA_ENABLE_COHBIT); } /* Enable SCH/PCH snoop if needed */ if (snoop_type == AZX_SNOOP_TYPE_SCH) { unsigned short snoop; pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; if (!azx_snoop(chip)) snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); } dev_dbg(chip->card->dev, "SCH snoop: %s\n", (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? "Disabled" : "Enabled"); } } /* * In BXT-P A0, HD-Audio DMA requests is later than expected, * and makes an audio stream sensitive to system latencies when * 24/32 bits are playing. * Adjusting threshold of DMA fifo to force the DMA request * sooner to improve latency tolerance at the expense of power. */ static void bxt_reduce_dma_latency(struct azx *chip) { u32 val; val = azx_readl(chip, VS_EM4L); val &= (0x3 << 20); azx_writel(chip, VS_EM4L, val); } /* * ML_LCAP bits: * bit 0: 6 MHz Supported * bit 1: 12 MHz Supported * bit 2: 24 MHz Supported * bit 3: 48 MHz Supported * bit 4: 96 MHz Supported * bit 5: 192 MHz Supported */ static int intel_get_lctl_scf(struct azx *chip) { struct hdac_bus *bus = azx_bus(chip); static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; u32 val, t; int i; val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { t = preferred_bits[i]; if (val & (1 << t)) return t; } dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); return 0; } static int intel_ml_lctl_set_power(struct azx *chip, int state) { struct hdac_bus *bus = azx_bus(chip); u32 val; int timeout; /* * Changes to LCTL.SCF are only needed for the first multi-link dealing * with external codecs */ val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); val &= ~AZX_ML_LCTL_SPA; val |= state << AZX_ML_LCTL_SPA_SHIFT; writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); /* wait for CPA */ timeout = 50; while (timeout) { if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) return 0; timeout--; udelay(10); } return -1; } static void intel_init_lctl(struct azx *chip) { struct hdac_bus *bus = azx_bus(chip); u32 val; int ret; /* 0. check lctl register value is correct or not */ val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); /* only perform additional configurations if the SCF is initially based on 6MHz */ if ((val & AZX_ML_LCTL_SCF) != 0) return; /* * Before operating on SPA, CPA must match SPA. * Any deviation may result in undefined behavior. */ if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) return; /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ ret = intel_ml_lctl_set_power(chip, 0); udelay(100); if (ret) goto set_spa; /* 2. update SCF to select an audio clock different from 6MHz */ val &= ~AZX_ML_LCTL_SCF; val |= intel_get_lctl_scf(chip); writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); set_spa: /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ intel_ml_lctl_set_power(chip, 1); udelay(100); } static void hda_intel_init_chip(struct azx *chip, bool full_reset) { struct hdac_bus *bus = azx_bus(chip); struct pci_dev *pci = chip->pci; u32 val; snd_hdac_set_codec_wakeup(bus, true); if (chip->driver_type == AZX_DRIVER_SKL) { pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); } azx_init_chip(chip, full_reset); if (chip->driver_type == AZX_DRIVER_SKL) { pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); val = val | INTEL_HDA_CGCTL_MISCBDCGE; pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); } snd_hdac_set_codec_wakeup(bus, false); /* reduce dma latency to avoid noise */ if (HDA_CONTROLLER_IS_APL(pci)) bxt_reduce_dma_latency(chip); if (bus->mlcap != NULL) intel_init_lctl(chip); } /* calculate runtime delay from LPIB */ static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, unsigned int pos) { struct snd_pcm_substream *substream = azx_dev->core.substream; int stream = substream->stream; unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); int delay; if (stream == SNDRV_PCM_STREAM_PLAYBACK) delay = pos - lpib_pos; else delay = lpib_pos - pos; if (delay < 0) { if (delay >= azx_dev->core.delay_negative_threshold) delay = 0; else delay += azx_dev->core.bufsize; } if (delay >= azx_dev->core.period_bytes) { dev_info(chip->card->dev, "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", delay, azx_dev->core.period_bytes); delay = 0; chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; chip->get_delay[stream] = NULL; } return bytes_to_frames(substream->runtime, delay); } static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); /* called from IRQ */ static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); int ok; ok = azx_position_ok(chip, azx_dev); if (ok == 1) { azx_dev->irq_pending = 0; return ok; } else if (ok == 0) { /* bogus IRQ, process it later */ azx_dev->irq_pending = 1; schedule_work(&hda->irq_pending_work); } return 0; } #define display_power(chip, enable) \ snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) /* * Check whether the current DMA position is acceptable for updating * periods. Returns non-zero if it's OK. * * Many HD-audio controllers appear pretty inaccurate about * the update-IRQ timing. The IRQ is issued before actually the * data is processed. So, we need to process it afterwords in a * workqueue. * * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update */ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) { struct snd_pcm_substream *substream = azx_dev->core.substream; struct snd_pcm_runtime *runtime = substream->runtime; int stream = substream->stream; u32 wallclk; unsigned int pos; snd_pcm_uframes_t hwptr, target; /* * The value of the WALLCLK register is always 0 * on the Loongson controller, so we return directly. */ if (chip->driver_type == AZX_DRIVER_LOONGSON) return 1; wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) return -1; /* bogus (too early) interrupt */ if (chip->get_position[stream]) pos = chip->get_position[stream](chip, azx_dev); else { /* use the position buffer as default */ pos = azx_get_pos_posbuf(chip, azx_dev); if (!pos || pos == (u32)-1) { dev_info(chip->card->dev, "Invalid position buffer, using LPIB read method instead.\n"); chip->get_position[stream] = azx_get_pos_lpib; if (chip->get_position[0] == azx_get_pos_lpib && chip->get_position[1] == azx_get_pos_lpib) azx_bus(chip)->use_posbuf = false; pos = azx_get_pos_lpib(chip, azx_dev); chip->get_delay[stream] = NULL; } else { chip->get_position[stream] = azx_get_pos_posbuf; if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) chip->get_delay[stream] = azx_get_delay_from_lpib; } } if (pos >= azx_dev->core.bufsize) pos = 0; if (WARN_ONCE(!azx_dev->core.period_bytes, "hda-intel: zero azx_dev->period_bytes")) return -1; /* this shouldn't happen! */ if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) /* NG - it's below the first next period boundary */ return chip->bdl_pos_adj ? 0 : -1; azx_dev->core.start_wallclk += wallclk; if (azx_dev->core.no_period_wakeup) return 1; /* OK, no need to check period boundary */ if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) return 1; /* OK, already in hwptr updating process */ /* check whether the period gets really elapsed */ pos = bytes_to_frames(runtime, pos); hwptr = runtime->hw_ptr_base + pos; if (hwptr < runtime->status->hw_ptr) hwptr += runtime->buffer_size; target = runtime->hw_ptr_interrupt + runtime->period_size; if (hwptr < target) { /* too early wakeup, process it later */ return chip->bdl_pos_adj ? 0 : -1; } return 1; /* OK, it's fine */ } /* * The work for pending PCM period updates. */ static void azx_irq_pending_work(struct work_struct *work) { struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); struct azx *chip = &hda->chip; struct hdac_bus *bus = azx_bus(chip); struct hdac_stream *s; int pending, ok; if (!hda->irq_pending_warned) { dev_info(chip->card->dev, "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", chip->card->number); hda->irq_pending_warned = 1; } for (;;) { pending = 0; spin_lock_irq(&bus->reg_lock); list_for_each_entry(s, &bus->stream_list, list) { struct azx_dev *azx_dev = stream_to_azx_dev(s); if (!azx_dev->irq_pending || !s->substream || !s->running) continue; ok = azx_position_ok(chip, azx_dev); if (ok > 0) { azx_dev->irq_pending = 0; spin_unlock(&bus->reg_lock); snd_pcm_period_elapsed(s->substream); spin_lock(&bus->reg_lock); } else if (ok < 0) { pending = 0; /* too early */ } else pending++; } spin_unlock_irq(&bus->reg_lock); if (!pending) return; msleep(1); } } /* clear irq_pending flags and assure no on-going workq */ static void azx_clear_irq_pending(struct azx *chip) { struct hdac_bus *bus = azx_bus(chip); struct hdac_stream *s; spin_lock_irq(&bus->reg_lock); list_for_each_entry(s, &bus->stream_list, list) { struct azx_dev *azx_dev = stream_to_azx_dev(s); azx_dev->irq_pending = 0; } spin_unlock_irq(&bus->reg_lock); } static int azx_acquire_irq(struct azx *chip, int do_disconnect) { struct hdac_bus *bus = azx_bus(chip); if (request_irq(chip->pci->irq, azx_interrupt, chip->msi ? 0 : IRQF_SHARED, chip->card->irq_descr, chip)) { dev_err(chip->card->dev, "unable to grab IRQ %d, disabling device\n", chip->pci->irq); if (do_disconnect) snd_card_disconnect(chip->card); return -1; } bus->irq = chip->pci->irq; chip->card->sync_irq = bus->irq; pci_intx(chip->pci, !chip->msi); return 0; } /* get the current DMA position with correction on VIA chips */ static unsigned int azx_via_get_position(struct azx *chip, struct azx_dev *azx_dev) { unsigned int link_pos, mini_pos, bound_pos; unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; unsigned int fifo_size; link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /* Playback, no problem using link position */ return link_pos; } /* Capture */ /* For new chipset, * use mod to get the DMA position just like old chipset */ mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); mod_dma_pos %= azx_dev->core.period_bytes; fifo_size = azx_stream(azx_dev)->fifo_size - 1; if (azx_dev->insufficient) { /* Link position never gather than FIFO size */ if (link_pos <= fifo_size) return 0; azx_dev->insufficient = 0; } if (link_pos <= fifo_size) mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; else mini_pos = link_pos - fifo_size; /* Find nearest previous boudary */ mod_mini_pos = mini_pos % azx_dev->core.period_bytes; mod_link_pos = link_pos % azx_dev->core.period_bytes; if (mod_link_pos >= fifo_size) bound_pos = link_pos - mod_link_pos; else if (mod_dma_pos >= mod_mini_pos) bound_pos = mini_pos - mod_mini_pos; else { bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; if (bound_pos >= azx_dev->core.bufsize) bound_pos = 0; } /* Calculate real DMA position we want */ return bound_pos + mod_dma_pos; } #define AMD_FIFO_SIZE 32 /* get the current DMA position with FIFO size correction */ static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) { struct snd_pcm_substream *substream = azx_dev->core.substream; struct snd_pcm_runtime *runtime = substream->runtime; unsigned int pos, delay; pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); if (!runtime) return pos; runtime->delay = AMD_FIFO_SIZE; delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); if (azx_dev->insufficient) { if (pos < delay) { delay = pos; runtime->delay = bytes_to_frames(runtime, pos); } else { azx_dev->insufficient = 0; } } /* correct the DMA position for capture stream */ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { if (pos < delay) pos += azx_dev->core.bufsize; pos -= delay; } return pos; } static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, unsigned int pos) { struct snd_pcm_substream *substream = azx_dev->core.substream; /* just read back the calculated value in the above */ return substream->runtime->delay; } static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) { azx_stop_chip(chip); if (!skip_link_reset) azx_enter_link_reset(chip); azx_clear_irq_pending(chip); display_power(chip, false); } #ifdef CONFIG_PM static DEFINE_MUTEX(card_list_lock); static LIST_HEAD(card_list); static void azx_shutdown_chip(struct azx *chip) { __azx_shutdown_chip(chip, false); } static void azx_add_card_list(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); mutex_lock(&card_list_lock); list_add(&hda->list, &card_list); mutex_unlock(&card_list_lock); } static void azx_del_card_list(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); mutex_lock(&card_list_lock); list_del_init(&hda->list); mutex_unlock(&card_list_lock); } /* trigger power-save check at writing parameter */ static int param_set_xint(const char *val, const struct kernel_param *kp) { struct hda_intel *hda; struct azx *chip; int prev = power_save; int ret = param_set_int(val, kp); if (ret || prev == power_save) return ret; mutex_lock(&card_list_lock); list_for_each_entry(hda, &card_list, list) { chip = &hda->chip; if (!hda->probe_continued || chip->disabled) continue; snd_hda_set_power_save(&chip->bus, power_save * 1000); } mutex_unlock(&card_list_lock); return 0; } /* * power management */ static bool azx_is_pm_ready(struct snd_card *card) { struct azx *chip; struct hda_intel *hda; if (!card) return false; chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); if (chip->disabled || hda->init_failed || !chip->running) return false; return true; } static void __azx_runtime_resume(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hdac_bus *bus = azx_bus(chip); struct hda_codec *codec; int status; display_power(chip, true); if (hda->need_i915_power) snd_hdac_i915_set_bclk(bus); /* Read STATESTS before controller reset */ status = azx_readw(chip, STATESTS); azx_init_pci(chip); hda_intel_init_chip(chip, true); /* Avoid codec resume if runtime resume is for system suspend */ if (!chip->pm_prepared) { list_for_each_codec(codec, &chip->bus) { if (codec->relaxed_resume) continue; if (codec->forced_resume || (status & (1 << codec->addr))) pm_request_resume(hda_codec_dev(codec)); } } /* power down again for link-controlled chips */ if (!hda->need_i915_power) display_power(chip, false); } #ifdef CONFIG_PM_SLEEP static int azx_prepare(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; if (!azx_is_pm_ready(card)) return 0; chip = card->private_data; chip->pm_prepared = 1; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); flush_work(&azx_bus(chip)->unsol_work); /* HDA controller always requires different WAKEEN for runtime suspend * and system suspend, so don't use direct-complete here. */ return 0; } static void azx_complete(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; if (!azx_is_pm_ready(card)) return; chip = card->private_data; snd_power_change_state(card, SNDRV_CTL_POWER_D0); chip->pm_prepared = 0; } static int azx_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; struct hdac_bus *bus; if (!azx_is_pm_ready(card)) return 0; chip = card->private_data; bus = azx_bus(chip); azx_shutdown_chip(chip); if (bus->irq >= 0) { free_irq(bus->irq, chip); bus->irq = -1; chip->card->sync_irq = -1; } if (chip->msi) pci_disable_msi(chip->pci); trace_azx_suspend(chip); return 0; } static int azx_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; if (!azx_is_pm_ready(card)) return 0; chip = card->private_data; if (chip->msi) if (pci_enable_msi(chip->pci) < 0) chip->msi = 0; if (azx_acquire_irq(chip, 1) < 0) return -EIO; __azx_runtime_resume(chip); trace_azx_resume(chip); return 0; } /* put codec down to D3 at hibernation for Intel SKL+; * otherwise BIOS may still access the codec and screw up the driver */ static int azx_freeze_noirq(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; struct pci_dev *pci = to_pci_dev(dev); if (!azx_is_pm_ready(card)) return 0; if (chip->driver_type == AZX_DRIVER_SKL) pci_set_power_state(pci, PCI_D3hot); return 0; } static int azx_thaw_noirq(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; struct pci_dev *pci = to_pci_dev(dev); if (!azx_is_pm_ready(card)) return 0; if (chip->driver_type == AZX_DRIVER_SKL) pci_set_power_state(pci, PCI_D0); return 0; } #endif /* CONFIG_PM_SLEEP */ static int azx_runtime_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; if (!azx_is_pm_ready(card)) return 0; chip = card->private_data; /* enable controller wake up event */ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); azx_shutdown_chip(chip); trace_azx_runtime_suspend(chip); return 0; } static int azx_runtime_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; if (!azx_is_pm_ready(card)) return 0; chip = card->private_data; __azx_runtime_resume(chip); /* disable controller Wake Up event*/ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); trace_azx_runtime_resume(chip); return 0; } static int azx_runtime_idle(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; struct hda_intel *hda; if (!card) return 0; chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); if (chip->disabled || hda->init_failed) return 0; if (!power_save_controller || !azx_has_pm_runtime(chip) || azx_bus(chip)->codec_powered || !chip->running) return -EBUSY; /* ELD notification gets broken when HD-audio bus is off */ if (needs_eld_notify_link(chip)) return -EBUSY; return 0; } static const struct dev_pm_ops azx_pm = { SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) #ifdef CONFIG_PM_SLEEP .prepare = azx_prepare, .complete = azx_complete, .freeze_noirq = azx_freeze_noirq, .thaw_noirq = azx_thaw_noirq, #endif SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) }; #define AZX_PM_OPS &azx_pm #else #define azx_add_card_list(chip) /* NOP */ #define azx_del_card_list(chip) /* NOP */ #define AZX_PM_OPS NULL #endif /* CONFIG_PM */ static int azx_probe_continue(struct azx *chip); #ifdef SUPPORT_VGA_SWITCHEROO static struct pci_dev *get_bound_vga(struct pci_dev *pci); static void azx_vs_set_state(struct pci_dev *pci, enum vga_switcheroo_state state) { struct snd_card *card = pci_get_drvdata(pci); struct azx *chip = card->private_data; struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hda_codec *codec; bool disabled; wait_for_completion(&hda->probe_wait); if (hda->init_failed) return; disabled = (state == VGA_SWITCHEROO_OFF); if (chip->disabled == disabled) return; if (!hda->probe_continued) { chip->disabled = disabled; if (!disabled) { dev_info(chip->card->dev, "Start delayed initialization\n"); if (azx_probe_continue(chip) < 0) dev_err(chip->card->dev, "initialization error\n"); } } else { dev_info(chip->card->dev, "%s via vga_switcheroo\n", disabled ? "Disabling" : "Enabling"); if (disabled) { list_for_each_codec(codec, &chip->bus) { pm_runtime_suspend(hda_codec_dev(codec)); pm_runtime_disable(hda_codec_dev(codec)); } pm_runtime_suspend(card->dev); pm_runtime_disable(card->dev); /* when we get suspended by vga_switcheroo we end up in D3cold, * however we have no ACPI handle, so pci/acpi can't put us there, * put ourselves there */ pci->current_state = PCI_D3cold; chip->disabled = true; if (snd_hda_lock_devices(&chip->bus)) dev_warn(chip->card->dev, "Cannot lock devices!\n"); } else { snd_hda_unlock_devices(&chip->bus); chip->disabled = false; pm_runtime_enable(card->dev); list_for_each_codec(codec, &chip->bus) { pm_runtime_enable(hda_codec_dev(codec)); pm_runtime_resume(hda_codec_dev(codec)); } } } } static bool azx_vs_can_switch(struct pci_dev *pci) { struct snd_card *card = pci_get_drvdata(pci); struct azx *chip = card->private_data; struct hda_intel *hda = container_of(chip, struct hda_intel, chip); wait_for_completion(&hda->probe_wait); if (hda->init_failed) return false; if (chip->disabled || !hda->probe_continued) return true; if (snd_hda_lock_devices(&chip->bus)) return false; snd_hda_unlock_devices(&chip->bus); return true; } /* * The discrete GPU cannot power down unless the HDA controller runtime * suspends, so activate runtime PM on codecs even if power_save == 0. */ static void setup_vga_switcheroo_runtime_pm(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hda_codec *codec; if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { list_for_each_codec(codec, &chip->bus) codec->auto_runtime_pm = 1; /* reset the power save setup */ if (chip->running) set_default_power_save(chip); } } static void azx_vs_gpu_bound(struct pci_dev *pci, enum vga_switcheroo_client_id client_id) { struct snd_card *card = pci_get_drvdata(pci); struct azx *chip = card->private_data; if (client_id == VGA_SWITCHEROO_DIS) chip->bus.keep_power = 0; setup_vga_switcheroo_runtime_pm(chip); } static void init_vga_switcheroo(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct pci_dev *p = get_bound_vga(chip->pci); struct pci_dev *parent; if (p) { dev_info(chip->card->dev, "Handle vga_switcheroo audio client\n"); hda->use_vga_switcheroo = 1; /* cleared in either gpu_bound op or codec probe, or when its * upstream port has _PR3 (i.e. dGPU). */ parent = pci_upstream_bridge(p); chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; pci_dev_put(p); } } static const struct vga_switcheroo_client_ops azx_vs_ops = { .set_gpu_state = azx_vs_set_state, .can_switch = azx_vs_can_switch, .gpu_bound = azx_vs_gpu_bound, }; static int register_vga_switcheroo(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct pci_dev *p; int err; if (!hda->use_vga_switcheroo) return 0; p = get_bound_vga(chip->pci); err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); pci_dev_put(p); if (err < 0) return err; hda->vga_switcheroo_registered = 1; return 0; } #else #define init_vga_switcheroo(chip) /* NOP */ #define register_vga_switcheroo(chip) 0 #define check_hdmi_disabled(pci) false #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ #endif /* SUPPORT_VGA_SWITCHER */ /* * destructor */ static void azx_free(struct azx *chip) { struct pci_dev *pci = chip->pci; struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hdac_bus *bus = azx_bus(chip); if (hda->freed) return; if (azx_has_pm_runtime(chip) && chip->running) { pm_runtime_get_noresume(&pci->dev); pm_runtime_forbid(&pci->dev); pm_runtime_dont_use_autosuspend(&pci->dev); } chip->running = 0; azx_del_card_list(chip); hda->init_failed = 1; /* to be sure */ complete_all(&hda->probe_wait); if (use_vga_switcheroo(hda)) { if (chip->disabled && hda->probe_continued) snd_hda_unlock_devices(&chip->bus); if (hda->vga_switcheroo_registered) vga_switcheroo_unregister_client(chip->pci); } if (bus->chip_init) { azx_clear_irq_pending(chip); azx_stop_all_streams(chip); azx_stop_chip(chip); } if (bus->irq >= 0) free_irq(bus->irq, (void*)chip); azx_free_stream_pages(chip); azx_free_streams(chip); snd_hdac_bus_exit(bus); #ifdef CONFIG_SND_HDA_PATCH_LOADER release_firmware(chip->fw); #endif display_power(chip, false); if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) snd_hdac_i915_exit(bus); hda->freed = 1; } static int azx_dev_disconnect(struct snd_device *device) { struct azx *chip = device->device_data; struct hdac_bus *bus = azx_bus(chip); chip->bus.shutdown = 1; cancel_work_sync(&bus->unsol_work); return 0; } static int azx_dev_free(struct snd_device *device) { azx_free(device->device_data); return 0; } #ifdef SUPPORT_VGA_SWITCHEROO #ifdef CONFIG_ACPI /* ATPX is in the integrated GPU's namespace */ static bool atpx_present(void) { struct pci_dev *pdev = NULL; acpi_handle dhandle, atpx_handle; acpi_status status; while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { dhandle = ACPI_HANDLE(&pdev->dev); if (dhandle) { status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); if (ACPI_SUCCESS(status)) { pci_dev_put(pdev); return true; } } } while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { dhandle = ACPI_HANDLE(&pdev->dev); if (dhandle) { status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); if (ACPI_SUCCESS(status)) { pci_dev_put(pdev); return true; } } } return false; } #else static bool atpx_present(void) { return false; } #endif /* * Check of disabled HDMI controller by vga_switcheroo */ static struct pci_dev *get_bound_vga(struct pci_dev *pci) { struct pci_dev *p; /* check only discrete GPU */ switch (pci->vendor) { case PCI_VENDOR_ID_ATI: case PCI_VENDOR_ID_AMD: if (pci->devfn == 1) { p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), pci->bus->number, 0); if (p) { /* ATPX is in the integrated GPU's ACPI namespace * rather than the dGPU's namespace. However, * the dGPU is the one who is involved in * vgaswitcheroo. */ if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && (atpx_present() || apple_gmux_detect(NULL, NULL))) return p; pci_dev_put(p); } } break; case PCI_VENDOR_ID_NVIDIA: if (pci->devfn == 1) { p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), pci->bus->number, 0); if (p) { if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) return p; pci_dev_put(p); } } break; } return NULL; } static bool check_hdmi_disabled(struct pci_dev *pci) { bool vga_inactive = false; struct pci_dev *p = get_bound_vga(pci); if (p) { if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) vga_inactive = true; pci_dev_put(p); } return vga_inactive; } #endif /* SUPPORT_VGA_SWITCHEROO */ /* * allow/deny-listing for position_fix */ static const struct snd_pci_quirk position_fix_list[] = { SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), {} }; static int check_position_fix(struct azx *chip, int fix) { const struct snd_pci_quirk *q; switch (fix) { case POS_FIX_AUTO: case POS_FIX_LPIB: case POS_FIX_POSBUF: case POS_FIX_VIACOMBO: case POS_FIX_COMBO: case POS_FIX_SKL: case POS_FIX_FIFO: return fix; } q = snd_pci_quirk_lookup(chip->pci, position_fix_list); if (q) { dev_info(chip->card->dev, "position_fix set to %d for device %04x:%04x\n", q->value, q->subvendor, q->subdevice); return q->value; } /* Check VIA/ATI HD Audio Controller exist */ if (chip->driver_type == AZX_DRIVER_VIA) { dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); return POS_FIX_VIACOMBO; } if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { dev_dbg(chip->card->dev, "Using FIFO position fix\n"); return POS_FIX_FIFO; } if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { dev_dbg(chip->card->dev, "Using LPIB position fix\n"); return POS_FIX_LPIB; } if (chip->driver_type == AZX_DRIVER_SKL) { dev_dbg(chip->card->dev, "Using SKL position fix\n"); return POS_FIX_SKL; } return POS_FIX_AUTO; } static void assign_position_fix(struct azx *chip, int fix) { static const azx_get_pos_callback_t callbacks[] = { [POS_FIX_AUTO] = NULL, [POS_FIX_LPIB] = azx_get_pos_lpib, [POS_FIX_POSBUF] = azx_get_pos_posbuf, [POS_FIX_VIACOMBO] = azx_via_get_position, [POS_FIX_COMBO] = azx_get_pos_lpib, [POS_FIX_SKL] = azx_get_pos_posbuf, [POS_FIX_FIFO] = azx_get_pos_fifo, }; chip->get_position[0] = chip->get_position[1] = callbacks[fix]; /* combo mode uses LPIB only for playback */ if (fix == POS_FIX_COMBO) chip->get_position[1] = NULL; if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { chip->get_delay[0] = chip->get_delay[1] = azx_get_delay_from_lpib; } if (fix == POS_FIX_FIFO) chip->get_delay[0] = chip->get_delay[1] = azx_get_delay_from_fifo; } /* * deny-lists for probe_mask */ static const struct snd_pci_quirk probe_mask_list[] = { /* Thinkpad often breaks the controller communication when accessing * to the non-working (or non-existing) modem codec slot. */ SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), /* broken BIOS */ SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), /* forced codec slots */ SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), /* WinFast VP200 H (Teradici) user reported broken communication */ SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), {} }; #define AZX_FORCE_CODEC_MASK 0x100 static void check_probe_mask(struct azx *chip, int dev) { const struct snd_pci_quirk *q; chip->codec_probe_mask = probe_mask[dev]; if (chip->codec_probe_mask == -1) { q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); if (q) { dev_info(chip->card->dev, "probe_mask set to 0x%x for device %04x:%04x\n", q->value, q->subvendor, q->subdevice); chip->codec_probe_mask = q->value; } } /* check forced option */ if (chip->codec_probe_mask != -1 && (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", (int)azx_bus(chip)->codec_mask); } } /* * allow/deny-list for enable_msi */ static const struct snd_pci_quirk msi_deny_list[] = { SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ {} }; static void check_msi(struct azx *chip) { const struct snd_pci_quirk *q; if (enable_msi >= 0) { chip->msi = !!enable_msi; return; } chip->msi = 1; /* enable MSI as default */ q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); if (q) { dev_info(chip->card->dev, "msi for device %04x:%04x set to %d\n", q->subvendor, q->subdevice, q->value); chip->msi = q->value; return; } /* NVidia chipsets seem to cause troubles with MSI */ if (chip->driver_caps & AZX_DCAPS_NO_MSI) { dev_info(chip->card->dev, "Disabling MSI\n"); chip->msi = 0; } } /* check the snoop mode availability */ static void azx_check_snoop_available(struct azx *chip) { int snoop = hda_snoop; if (snoop >= 0) { dev_info(chip->card->dev, "Force to %s mode by module option\n", snoop ? "snoop" : "non-snoop"); chip->snoop = snoop; chip->uc_buffer = !snoop; return; } snoop = true; if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && chip->driver_type == AZX_DRIVER_VIA) { /* force to non-snoop mode for a new VIA controller * when BIOS is set */ u8 val; pci_read_config_byte(chip->pci, 0x42, &val); if (!(val & 0x80) && (chip->pci->revision == 0x30 || chip->pci->revision == 0x20)) snoop = false; } if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) snoop = false; chip->snoop = snoop; if (!snoop) { dev_info(chip->card->dev, "Force to non-snoop mode\n"); /* C-Media requires non-cached pages only for CORB/RIRB */ if (chip->driver_type != AZX_DRIVER_CMEDIA) chip->uc_buffer = true; } } static void azx_probe_work(struct work_struct *work) { struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); azx_probe_continue(&hda->chip); } static int default_bdl_pos_adj(struct azx *chip) { /* some exceptions: Atoms seem problematic with value 1 */ if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { switch (chip->pci->device) { case 0x0f04: /* Baytrail */ case 0x2284: /* Braswell */ return 32; } } switch (chip->driver_type) { /* * increase the bdl size for Glenfly Gpus for hardware * limitation on hdac interrupt interval */ case AZX_DRIVER_GFHDMI: return 128; case AZX_DRIVER_ICH: case AZX_DRIVER_PCH: return 1; default: return 32; } } /* * constructor */ static const struct hda_controller_ops pci_hda_ops; static int azx_create(struct snd_card *card, struct pci_dev *pci, int dev, unsigned int driver_caps, struct azx **rchip) { static const struct snd_device_ops ops = { .dev_disconnect = azx_dev_disconnect, .dev_free = azx_dev_free, }; struct hda_intel *hda; struct azx *chip; int err; *rchip = NULL; err = pcim_enable_device(pci); if (err < 0) return err; hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); if (!hda) return -ENOMEM; chip = &hda->chip; mutex_init(&chip->open_mutex); chip->card = card; chip->pci = pci; chip->ops = &pci_hda_ops; chip->driver_caps = driver_caps; chip->driver_type = driver_caps & 0xff; check_msi(chip); chip->dev_index = dev; if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); INIT_LIST_HEAD(&chip->pcm_list); INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); INIT_LIST_HEAD(&hda->list); init_vga_switcheroo(chip); init_completion(&hda->probe_wait); assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); if (single_cmd < 0) /* allow fallback to single_cmd at errors */ chip->fallback_to_single_cmd = 1; else /* explicitly set to single_cmd or not */ chip->single_cmd = single_cmd; azx_check_snoop_available(chip); if (bdl_pos_adj[dev] < 0) chip->bdl_pos_adj = default_bdl_pos_adj(chip); else chip->bdl_pos_adj = bdl_pos_adj[dev]; err = azx_bus_init(chip, model[dev]); if (err < 0) return err; /* use the non-cached pages in non-snoop mode */ if (!azx_snoop(chip)) azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; if (chip->driver_type == AZX_DRIVER_NVIDIA) { dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); chip->bus.core.needs_damn_long_delay = 1; } check_probe_mask(chip, dev); err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); if (err < 0) { dev_err(card->dev, "Error creating device [card]!\n"); azx_free(chip); return err; } /* continue probing in work context as may trigger request module */ INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); *rchip = chip; return 0; } static int azx_first_init(struct azx *chip) { int dev = chip->dev_index; struct pci_dev *pci = chip->pci; struct snd_card *card = chip->card; struct hdac_bus *bus = azx_bus(chip); int err; unsigned short gcap; unsigned int dma_bits = 64; #if BITS_PER_LONG != 64 /* Fix up base address on ULI M5461 */ if (chip->driver_type == AZX_DRIVER_ULI) { u16 tmp3; pci_read_config_word(pci, 0x40, &tmp3); pci_write_config_word(pci, 0x40, tmp3 | 0x10); pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); } #endif /* * Fix response write request not synced to memory when handle * hdac interrupt on Glenfly Gpus */ if (chip->driver_type == AZX_DRIVER_GFHDMI) bus->polling_mode = 1; if (chip->driver_type == AZX_DRIVER_LOONGSON) { bus->polling_mode = 1; bus->not_use_interrupts = 1; bus->access_sdnctl_in_dword = 1; } err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); if (err < 0) return err; bus->addr = pci_resource_start(pci, 0); bus->remap_addr = pcim_iomap_table(pci)[0]; if (chip->driver_type == AZX_DRIVER_SKL) snd_hdac_bus_parse_capabilities(bus); /* * Some Intel CPUs has always running timer (ART) feature and * controller may have Global time sync reporting capability, so * check both of these before declaring synchronized time reporting * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME */ chip->gts_present = false; #ifdef CONFIG_X86 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) chip->gts_present = true; #endif if (chip->msi) { if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { dev_dbg(card->dev, "Disabling 64bit MSI\n"); pci->no_64bit_msi = true; } if (pci_enable_msi(pci) < 0) chip->msi = 0; } pci_set_master(pci); gcap = azx_readw(chip, GCAP); dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); /* AMD devices support 40 or 48bit DMA, take the safe one */ if (chip->pci->vendor == PCI_VENDOR_ID_AMD) dma_bits = 40; /* disable SB600 64bit support for safety */ if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { struct pci_dev *p_smbus; dma_bits = 40; p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); if (p_smbus) { if (p_smbus->revision < 0x30) gcap &= ~AZX_GCAP_64OK; pci_dev_put(p_smbus); } } /* NVidia hardware normally only supports up to 40 bits of DMA */ if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) dma_bits = 40; /* disable 64bit DMA address on some devices */ if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { dev_dbg(card->dev, "Disabling 64bit DMA\n"); gcap &= ~AZX_GCAP_64OK; } /* disable buffer size rounding to 128-byte multiples if supported */ if (align_buffer_size >= 0) chip->align_buffer_size = !!align_buffer_size; else { if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) chip->align_buffer_size = 0; else chip->align_buffer_size = 1; } /* allow 64bit DMA address if supported by H/W */ if (!(gcap & AZX_GCAP_64OK)) dma_bits = 32; if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); dma_set_max_seg_size(&pci->dev, UINT_MAX); /* read number of streams from GCAP register instead of using * hardcoded value */ chip->capture_streams = (gcap >> 8) & 0x0f; chip->playback_streams = (gcap >> 12) & 0x0f; if (!chip->playback_streams && !chip->capture_streams) { /* gcap didn't give any info, switching to old method */ switch (chip->driver_type) { case AZX_DRIVER_ULI: chip->playback_streams = ULI_NUM_PLAYBACK; chip->capture_streams = ULI_NUM_CAPTURE; break; case AZX_DRIVER_ATIHDMI: case AZX_DRIVER_ATIHDMI_NS: chip->playback_streams = ATIHDMI_NUM_PLAYBACK; chip->capture_streams = ATIHDMI_NUM_CAPTURE; break; case AZX_DRIVER_GFHDMI: case AZX_DRIVER_GENERIC: default: chip->playback_streams = ICH6_NUM_PLAYBACK; chip->capture_streams = ICH6_NUM_CAPTURE; break; } } chip->capture_index_offset = 0; chip->playback_index_offset = chip->capture_streams; chip->num_streams = chip->playback_streams + chip->capture_streams; /* sanity check for the SDxCTL.STRM field overflow */ if (chip->num_streams > 15 && (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { dev_warn(chip->card->dev, "number of I/O streams is %d, " "forcing separate stream tags", chip->num_streams); chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; } /* initialize streams */ err = azx_init_streams(chip); if (err < 0) return err; err = azx_alloc_stream_pages(chip); if (err < 0) return err; /* initialize chip */ azx_init_pci(chip); snd_hdac_i915_set_bclk(bus); hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); /* codec detection */ if (!azx_bus(chip)->codec_mask) { dev_err(card->dev, "no codecs found!\n"); /* keep running the rest for the runtime PM */ } if (azx_acquire_irq(chip, 0) < 0) return -EBUSY; strcpy(card->driver, "HDA-Intel"); strscpy(card->shortname, driver_short_names[chip->driver_type], sizeof(card->shortname)); snprintf(card->longname, sizeof(card->longname), "%s at 0x%lx irq %i", card->shortname, bus->addr, bus->irq); return 0; } #ifdef CONFIG_SND_HDA_PATCH_LOADER /* callback from request_firmware_nowait() */ static void azx_firmware_cb(const struct firmware *fw, void *context) { struct snd_card *card = context; struct azx *chip = card->private_data; if (fw) chip->fw = fw; else dev_err(card->dev, "Cannot load firmware, continue without patching\n"); if (!chip->disabled) { /* continue probing */ azx_probe_continue(chip); } } #endif static int disable_msi_reset_irq(struct azx *chip) { struct hdac_bus *bus = azx_bus(chip); int err; free_irq(bus->irq, chip); bus->irq = -1; chip->card->sync_irq = -1; pci_disable_msi(chip->pci); chip->msi = 0; err = azx_acquire_irq(chip, 1); if (err < 0) return err; return 0; } /* Denylist for skipping the whole probe: * some HD-audio PCI entries are exposed without any codecs, and such devices * should be ignored from the beginning. */ static const struct pci_device_id driver_denylist[] = { { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ {} }; static const struct hda_controller_ops pci_hda_ops = { .disable_msi_reset_irq = disable_msi_reset_irq, .position_check = azx_position_check, }; static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); static int azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { struct snd_card *card; struct hda_intel *hda; struct azx *chip; bool schedule_probe; int dev; int err; if (pci_match_id(driver_denylist, pci)) { dev_info(&pci->dev, "Skipping the device on the denylist\n"); return -ENODEV; } dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { set_bit(dev, probed_devs); return -ENOENT; } /* * stop probe if another Intel's DSP driver should be activated */ if (dmic_detect) { err = snd_intel_dsp_driver_probe(pci); if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); return -ENODEV; } } else { dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); } err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 0, &card); if (err < 0) { dev_err(&pci->dev, "Error creating card!\n"); return err; } err = azx_create(card, pci, dev, pci_id->driver_data, &chip); if (err < 0) goto out_free; card->private_data = chip; hda = container_of(chip, struct hda_intel, chip); pci_set_drvdata(pci, card); err = register_vga_switcheroo(chip); if (err < 0) { dev_err(card->dev, "Error registering vga_switcheroo client\n"); goto out_free; } if (check_hdmi_disabled(pci)) { dev_info(card->dev, "VGA controller is disabled\n"); dev_info(card->dev, "Delaying initialization\n"); chip->disabled = true; } schedule_probe = !chip->disabled; #ifdef CONFIG_SND_HDA_PATCH_LOADER if (patch[dev] && *patch[dev]) { dev_info(card->dev, "Applying patch firmware '%s'\n", patch[dev]); err = request_firmware_nowait(THIS_MODULE, true, patch[dev], &pci->dev, GFP_KERNEL, card, azx_firmware_cb); if (err < 0) goto out_free; schedule_probe = false; /* continued in azx_firmware_cb() */ } #endif /* CONFIG_SND_HDA_PATCH_LOADER */ #ifndef CONFIG_SND_HDA_I915 if (HDA_CONTROLLER_IN_GPU(pci)) dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); #endif if (schedule_probe) schedule_delayed_work(&hda->probe_work, 0); set_bit(dev, probed_devs); if (chip->disabled) complete_all(&hda->probe_wait); return 0; out_free: snd_card_free(card); return err; } #ifdef CONFIG_PM /* On some boards setting power_save to a non 0 value leads to clicking / * popping sounds when ever we enter/leave powersaving mode. Ideally we would * figure out how to avoid these sounds, but that is not always feasible. * So we keep a list of devices where we disable powersaving as its known * to causes problems on these devices. */ static const struct snd_pci_quirk power_save_denylist[] = { /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), /* https://bugs.launchpad.net/bugs/1821663 */ SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), /* https://bugs.launchpad.net/bugs/1821663 */ SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), {} }; #endif /* CONFIG_PM */ static void set_default_power_save(struct azx *chip) { int val = power_save; #ifdef CONFIG_PM if (pm_blacklist) { const struct snd_pci_quirk *q; q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); if (q && val) { dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", q->subvendor, q->subdevice); val = 0; } } #endif /* CONFIG_PM */ snd_hda_set_power_save(&chip->bus, val * 1000); } /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { [AZX_DRIVER_NVIDIA] = 8, [AZX_DRIVER_TERA] = 1, }; static int azx_probe_continue(struct azx *chip) { struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hdac_bus *bus = azx_bus(chip); struct pci_dev *pci = chip->pci; int dev = chip->dev_index; int err; if (chip->disabled || hda->init_failed) return -EIO; if (hda->probe_retry) goto probe_retry; to_hda_bus(bus)->bus_probing = 1; hda->probe_continued = 1; /* bind with i915 if needed */ if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { err = snd_hdac_i915_init(bus); if (err < 0) { /* if the controller is bound only with HDMI/DP * (for HSW and BDW), we need to abort the probe; * for other chips, still continue probing as other * codecs can be on the same link. */ if (HDA_CONTROLLER_IN_GPU(pci)) { dev_err(chip->card->dev, "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); goto out_free; } else { /* don't bother any longer */ chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; } } /* HSW/BDW controllers need this power */ if (HDA_CONTROLLER_IN_GPU(pci)) hda->need_i915_power = true; } /* Request display power well for the HDA controller or codec. For * Haswell/Broadwell, both the display HDA controller and codec need * this power. For other platforms, like Baytrail/Braswell, only the * display codec needs the power and it can be released after probe. */ display_power(chip, true); err = azx_first_init(chip); if (err < 0) goto out_free; #ifdef CONFIG_SND_HDA_INPUT_BEEP chip->beep_mode = beep_mode[dev]; #endif chip->ctl_dev_id = ctl_dev_id; /* create codec instances */ if (bus->codec_mask) { err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); if (err < 0) goto out_free; } #ifdef CONFIG_SND_HDA_PATCH_LOADER if (chip->fw) { err = snd_hda_load_patch(&chip->bus, chip->fw->size, chip->fw->data); if (err < 0) goto out_free; #ifndef CONFIG_PM release_firmware(chip->fw); /* no longer needed */ chip->fw = NULL; #endif } #endif probe_retry: if (bus->codec_mask && !(probe_only[dev] & 1)) { err = azx_codec_configure(chip); if (err) { if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && ++hda->probe_retry < 60) { schedule_delayed_work(&hda->probe_work, msecs_to_jiffies(1000)); return 0; /* keep things up */ } dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); goto out_free; } } err = snd_card_register(chip->card); if (err < 0) goto out_free; setup_vga_switcheroo_runtime_pm(chip); chip->running = 1; azx_add_card_list(chip); set_default_power_save(chip); if (azx_has_pm_runtime(chip)) { pm_runtime_use_autosuspend(&pci->dev); pm_runtime_allow(&pci->dev); pm_runtime_put_autosuspend(&pci->dev); } out_free: if (err < 0) { pci_set_drvdata(pci, NULL); snd_card_free(chip->card); return err; } if (!hda->need_i915_power) display_power(chip, false); complete_all(&hda->probe_wait); to_hda_bus(bus)->bus_probing = 0; hda->probe_retry = 0; return 0; } static void azx_remove(struct pci_dev *pci) { struct snd_card *card = pci_get_drvdata(pci); struct azx *chip; struct hda_intel *hda; if (card) { /* cancel the pending probing work */ chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); /* FIXME: below is an ugly workaround. * Both device_release_driver() and driver_probe_device() * take *both* the device's and its parent's lock before * calling the remove() and probe() callbacks. The codec * probe takes the locks of both the codec itself and its * parent, i.e. the PCI controller dev. Meanwhile, when * the PCI controller is unbound, it takes its lock, too * ==> ouch, a deadlock! * As a workaround, we unlock temporarily here the controller * device during cancel_work_sync() call. */ device_unlock(&pci->dev); cancel_delayed_work_sync(&hda->probe_work); device_lock(&pci->dev); clear_bit(chip->dev_index, probed_devs); pci_set_drvdata(pci, NULL); snd_card_free(card); } } static void azx_shutdown(struct pci_dev *pci) { struct snd_card *card = pci_get_drvdata(pci); struct azx *chip; if (!card) return; chip = card->private_data; if (chip && chip->running) __azx_shutdown_chip(chip, true); } /* PCI IDs */ static const struct pci_device_id azx_ids[] = { /* CPT */ { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, /* PBG */ { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, /* Panther Point */ { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, /* Lynx Point */ { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* 9 Series */ { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* Wellsburg */ { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* Lewisburg */ { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, /* Lynx Point-LP */ { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* Lynx Point-LP */ { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* Wildcat Point-LP */ { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, /* Skylake (Sunrise Point) */ { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Skylake-LP (Sunrise Point-LP) */ { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Kabylake */ { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Kabylake-LP */ { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Kabylake-H */ { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Coffelake */ { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Cannonlake */ { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* CometLake-LP */ { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* CometLake-H */ { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* CometLake-S */ { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* CometLake-R */ { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Icelake */ { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Icelake-H */ { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Jasperlake */ { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Tigerlake */ { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Tigerlake-H */ { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* DG1 */ { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* DG2 */ { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Alderlake-S */ { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Alderlake-P */ { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Alderlake-M */ { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Alderlake-N */ { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Elkhart Lake */ { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Raptor Lake */ { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Lunarlake-P */ { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Arrow Lake-S */ { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, /* Apollolake (Broxton-P) */ { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, /* Gemini-Lake */ { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, /* Haswell */ { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, /* Broadwell */ { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, /* 5 Series/3400 */ { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, /* Poulsbo */ { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_POSFIX_LPIB) }, /* Oaktrail */ { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, /* BayTrail */ { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, /* Braswell */ { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, /* ICH6 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH7 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ESB2 */ { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH8 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH9 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH9 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH10 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* ICH10 */ { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, /* Generic Intel */ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, /* ATI SB 450/600/700/800/900 */ { PCI_VDEVICE(ATI, 0x437b), .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, { PCI_VDEVICE(ATI, 0x4383), .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, /* AMD Hudson */ { PCI_VDEVICE(AMD, 0x780d), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, /* AMD, X370 & co */ { PCI_VDEVICE(AMD, 0x1457), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, /* AMD, X570 & co */ { PCI_VDEVICE(AMD, 0x1487), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, /* AMD Stoney */ { PCI_VDEVICE(AMD, 0x157a), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | AZX_DCAPS_PM_RUNTIME }, /* AMD Raven */ { PCI_VDEVICE(AMD, 0x15e3), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, /* ATI HDMI */ { PCI_VDEVICE(ATI, 0x0002), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0x1308), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0x157a), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0x15b3), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0x9840), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa50), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa58), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa60), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa68), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa80), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa88), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa90), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0xaa98), .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_VDEVICE(ATI, 0x9902), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0xaaa0), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0xaaa8), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0xaab0), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, { PCI_VDEVICE(ATI, 0xaac0), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaac8), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaad8), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaae0), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaae8), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaaf0), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xaaf8), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab00), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab08), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab10), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab18), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab20), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab28), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab30), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, { PCI_VDEVICE(ATI, 0xab38), .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | AZX_DCAPS_PM_RUNTIME }, /* GLENFLY */ { PCI_DEVICE(0x6766, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, /* VIA VT8251/VT8237A */ { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, /* VIA GFX VT7122/VX900 */ { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, /* VIA GFX VT6122/VX11 */ { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, /* SIS966 */ { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, /* ULI M5461 */ { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, /* NVIDIA MCP */ { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, /* Teradici */ { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, { PCI_DEVICE(0x6549, 0x2200), .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, /* Creative X-Fi (CA0110-IBG) */ /* CTHDA chips */ { PCI_VDEVICE(CREATIVE, 0x0010), .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, { PCI_VDEVICE(CREATIVE, 0x0012), .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, #if !IS_ENABLED(CONFIG_SND_CTXFI) /* the following entry conflicts with snd-ctxfi driver, * as ctxfi driver mutates from HD-audio to native mode with * a special command sequence. */ { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, #else /* this entry seems still valid -- i.e. without emu20kx chip */ { PCI_VDEVICE(CREATIVE, 0x0009), .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, #endif /* CM8888 */ { PCI_VDEVICE(CMEDIA, 0x5011), .driver_data = AZX_DRIVER_CMEDIA | AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, /* Vortex86MX */ { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, /* VMware HDAudio */ { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, .class_mask = 0xffffff, .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, /* Zhaoxin */ { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, /* Loongson HDAudio*/ { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), .driver_data = AZX_DRIVER_LOONGSON }, { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), .driver_data = AZX_DRIVER_LOONGSON }, { 0, } }; MODULE_DEVICE_TABLE(pci, azx_ids); /* pci_driver definition */ static struct pci_driver azx_driver = { .name = KBUILD_MODNAME, .id_table = azx_ids, .probe = azx_probe, .remove = azx_remove, .shutdown = azx_shutdown, .driver = { .pm = AZX_PM_OPS, }, }; module_pci_driver(azx_driver);
linux-master
sound/pci/hda/hda_intel.c
// SPDX-License-Identifier: GPL-2.0 // // CS35l41 HDA SPI driver // // Copyright 2021 Cirrus Logic, Inc. // // Author: Lucas Tanure <[email protected]> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/spi/spi.h> #include "cs35l41_hda.h" static int cs35l41_hda_spi_probe(struct spi_device *spi) { const char *device_name; /* * Compare against the device name so it works for SPI, normal ACPI * and for ACPI by serial-multi-instantiate matching cases. */ if (strstr(dev_name(&spi->dev), "CSC3551")) device_name = "CSC3551"; else return -ENODEV; return cs35l41_hda_probe(&spi->dev, device_name, spi_get_chipselect(spi, 0), spi->irq, devm_regmap_init_spi(spi, &cs35l41_regmap_spi)); } static void cs35l41_hda_spi_remove(struct spi_device *spi) { cs35l41_hda_remove(&spi->dev); } static const struct spi_device_id cs35l41_hda_spi_id[] = { { "cs35l41-hda", 0 }, {} }; static const struct acpi_device_id cs35l41_acpi_hda_match[] = { { "CSC3551", 0 }, {} }; MODULE_DEVICE_TABLE(acpi, cs35l41_acpi_hda_match); static struct spi_driver cs35l41_spi_driver = { .driver = { .name = "cs35l41-hda", .acpi_match_table = cs35l41_acpi_hda_match, .pm = &cs35l41_hda_pm_ops, }, .id_table = cs35l41_hda_spi_id, .probe = cs35l41_hda_spi_probe, .remove = cs35l41_hda_spi_remove, }; module_spi_driver(cs35l41_spi_driver); MODULE_DESCRIPTION("HDA CS35L41 driver"); MODULE_IMPORT_NS(SND_HDA_SCODEC_CS35L41); MODULE_AUTHOR("Lucas Tanure <[email protected]>"); MODULE_LICENSE("GPL");
linux-master
sound/pci/hda/cs35l41_hda_spi.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Universal Interface for Intel High Definition Audio Codec * * HD audio interface patch for VIA VT17xx/VT18xx/VT20xx codec * * (C) 2006-2009 VIA Technology, Inc. * (C) 2006-2008 Takashi Iwai <[email protected]> */ /* * * * * * * * * * * * * * Release History * * * * * * * * * * * * * * * * */ /* */ /* 2006-03-03 Lydia Wang Create the basic patch to support VT1708 codec */ /* 2006-03-14 Lydia Wang Modify hard code for some pin widget nid */ /* 2006-08-02 Lydia Wang Add support to VT1709 codec */ /* 2006-09-08 Lydia Wang Fix internal loopback recording source select bug */ /* 2007-09-12 Lydia Wang Add EAPD enable during driver initialization */ /* 2007-09-17 Lydia Wang Add VT1708B codec support */ /* 2007-11-14 Lydia Wang Add VT1708A codec HP and CD pin connect config */ /* 2008-02-03 Lydia Wang Fix Rear channels and Back channels inverse issue */ /* 2008-03-06 Lydia Wang Add VT1702 codec and VT1708S codec support */ /* 2008-04-09 Lydia Wang Add mute front speaker when HP plugin */ /* 2008-04-09 Lydia Wang Add Independent HP feature */ /* 2008-05-28 Lydia Wang Add second S/PDIF Out support for VT1702 */ /* 2008-09-15 Logan Li Add VT1708S Mic Boost workaround/backdoor */ /* 2009-02-16 Logan Li Add support for VT1718S */ /* 2009-03-13 Logan Li Add support for VT1716S */ /* 2009-04-14 Lydai Wang Add support for VT1828S and VT2020 */ /* 2009-07-08 Lydia Wang Add support for VT2002P */ /* 2009-07-21 Lydia Wang Add support for VT1812 */ /* 2009-09-19 Lydia Wang Add support for VT1818S */ /* */ /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/asoundef.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_jack.h" #include "hda_generic.h" /* Pin Widget NID */ #define VT1708_HP_PIN_NID 0x20 #define VT1708_CD_PIN_NID 0x24 enum VIA_HDA_CODEC { UNKNOWN = -1, VT1708, VT1709_10CH, VT1709_6CH, VT1708B_8CH, VT1708B_4CH, VT1708S, VT1708BCE, VT1702, VT1718S, VT1716S, VT2002P, VT1812, VT1802, VT1705CF, VT1808, CODEC_TYPES, }; #define VT2002P_COMPATIBLE(spec) \ ((spec)->codec_type == VT2002P ||\ (spec)->codec_type == VT1812 ||\ (spec)->codec_type == VT1802) struct via_spec { struct hda_gen_spec gen; /* HP mode source */ unsigned int dmic_enabled; enum VIA_HDA_CODEC codec_type; /* analog low-power control */ bool alc_mode; /* work to check hp jack state */ int hp_work_active; int vt1708_jack_detect; }; static enum VIA_HDA_CODEC get_codec_type(struct hda_codec *codec); static void via_playback_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action); static const struct hda_codec_ops via_patch_ops; /* defined below */ static struct via_spec *via_new_spec(struct hda_codec *codec) { struct via_spec *spec; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (spec == NULL) return NULL; codec->spec = spec; snd_hda_gen_spec_init(&spec->gen); spec->codec_type = get_codec_type(codec); /* VT1708BCE & VT1708S are almost same */ if (spec->codec_type == VT1708BCE) spec->codec_type = VT1708S; spec->gen.indep_hp = 1; spec->gen.keep_eapd_on = 1; spec->gen.dac_min_mute = 1; spec->gen.pcm_playback_hook = via_playback_pcm_hook; spec->gen.add_stereo_mix_input = HDA_HINT_STEREO_MIX_AUTO; codec->power_save_node = 1; spec->gen.power_down_unused = 1; codec->patch_ops = via_patch_ops; return spec; } static enum VIA_HDA_CODEC get_codec_type(struct hda_codec *codec) { u32 vendor_id = codec->core.vendor_id; u16 ven_id = vendor_id >> 16; u16 dev_id = vendor_id & 0xffff; enum VIA_HDA_CODEC codec_type; /* get codec type */ if (ven_id != 0x1106) codec_type = UNKNOWN; else if (dev_id >= 0x1708 && dev_id <= 0x170b) codec_type = VT1708; else if (dev_id >= 0xe710 && dev_id <= 0xe713) codec_type = VT1709_10CH; else if (dev_id >= 0xe714 && dev_id <= 0xe717) codec_type = VT1709_6CH; else if (dev_id >= 0xe720 && dev_id <= 0xe723) { codec_type = VT1708B_8CH; if (snd_hda_param_read(codec, 0x16, AC_PAR_CONNLIST_LEN) == 0x7) codec_type = VT1708BCE; } else if (dev_id >= 0xe724 && dev_id <= 0xe727) codec_type = VT1708B_4CH; else if ((dev_id & 0xfff) == 0x397 && (dev_id >> 12) < 8) codec_type = VT1708S; else if ((dev_id & 0xfff) == 0x398 && (dev_id >> 12) < 8) codec_type = VT1702; else if ((dev_id & 0xfff) == 0x428 && (dev_id >> 12) < 8) codec_type = VT1718S; else if (dev_id == 0x0433 || dev_id == 0xa721) codec_type = VT1716S; else if (dev_id == 0x0441 || dev_id == 0x4441) codec_type = VT1718S; else if (dev_id == 0x0438 || dev_id == 0x4438) codec_type = VT2002P; else if (dev_id == 0x0448) codec_type = VT1812; else if (dev_id == 0x0440) codec_type = VT1708S; else if ((dev_id & 0xfff) == 0x446) codec_type = VT1802; else if (dev_id == 0x4760) codec_type = VT1705CF; else if (dev_id == 0x4761 || dev_id == 0x4762) codec_type = VT1808; else codec_type = UNKNOWN; return codec_type; }; static void analog_low_current_mode(struct hda_codec *codec); static bool is_aa_path_mute(struct hda_codec *codec); #define hp_detect_with_aa(codec) \ (snd_hda_get_bool_hint(codec, "analog_loopback_hp_detect") == 1 && \ !is_aa_path_mute(codec)) static void vt1708_stop_hp_work(struct hda_codec *codec) { struct via_spec *spec = codec->spec; if (spec->codec_type != VT1708 || !spec->gen.autocfg.hp_outs) return; if (spec->hp_work_active) { snd_hda_codec_write(codec, 0x1, 0, 0xf81, 1); codec->jackpoll_interval = 0; cancel_delayed_work_sync(&codec->jackpoll_work); spec->hp_work_active = false; } } static void vt1708_update_hp_work(struct hda_codec *codec) { struct via_spec *spec = codec->spec; if (spec->codec_type != VT1708 || !spec->gen.autocfg.hp_outs) return; if (spec->vt1708_jack_detect) { if (!spec->hp_work_active) { codec->jackpoll_interval = msecs_to_jiffies(100); snd_hda_codec_write(codec, 0x1, 0, 0xf81, 0); schedule_delayed_work(&codec->jackpoll_work, 0); spec->hp_work_active = true; } } else if (!hp_detect_with_aa(codec)) vt1708_stop_hp_work(codec); } static int via_pin_power_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { return snd_hda_enum_bool_helper_info(kcontrol, uinfo); } static int via_pin_power_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct via_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->gen.power_down_unused; return 0; } static int via_pin_power_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct via_spec *spec = codec->spec; bool val = !!ucontrol->value.enumerated.item[0]; if (val == spec->gen.power_down_unused) return 0; /* codec->power_save_node = val; */ /* widget PM seems yet broken */ spec->gen.power_down_unused = val; analog_low_current_mode(codec); return 1; } static const struct snd_kcontrol_new via_pin_power_ctl_enum = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Dynamic Power-Control", .info = via_pin_power_ctl_info, .get = via_pin_power_ctl_get, .put = via_pin_power_ctl_put, }; #ifdef CONFIG_SND_HDA_INPUT_BEEP /* additional beep mixers; the actual parameters are overwritten at build */ static const struct snd_kcontrol_new via_beep_mixer[] = { HDA_CODEC_VOLUME_MONO("Beep Playback Volume", 0, 1, 0, HDA_OUTPUT), HDA_CODEC_MUTE_BEEP_MONO("Beep Playback Switch", 0, 1, 0, HDA_OUTPUT), }; static int set_beep_amp(struct via_spec *spec, hda_nid_t nid, int idx, int dir) { struct snd_kcontrol_new *knew; unsigned int beep_amp = HDA_COMPOSE_AMP_VAL(nid, 1, idx, dir); int i; spec->gen.beep_nid = nid; for (i = 0; i < ARRAY_SIZE(via_beep_mixer); i++) { knew = snd_hda_gen_add_kctl(&spec->gen, NULL, &via_beep_mixer[i]); if (!knew) return -ENOMEM; knew->private_value = beep_amp; } return 0; } static int auto_parse_beep(struct hda_codec *codec) { struct via_spec *spec = codec->spec; hda_nid_t nid; for_each_hda_codec_node(nid, codec) if (get_wcaps_type(get_wcaps(codec, nid)) == AC_WID_BEEP) return set_beep_amp(spec, nid, 0, HDA_OUTPUT); return 0; } #else #define auto_parse_beep(codec) 0 #endif /* check AA path's mute status */ static bool is_aa_path_mute(struct hda_codec *codec) { struct via_spec *spec = codec->spec; const struct hda_amp_list *p; int ch, v; p = spec->gen.loopback.amplist; if (!p) return true; for (; p->nid; p++) { for (ch = 0; ch < 2; ch++) { v = snd_hda_codec_amp_read(codec, p->nid, ch, p->dir, p->idx); if (!(v & HDA_AMP_MUTE) && v > 0) return false; } } return true; } /* enter/exit analog low-current mode */ static void __analog_low_current_mode(struct hda_codec *codec, bool force) { struct via_spec *spec = codec->spec; bool enable; unsigned int verb, parm; if (!codec->power_save_node) enable = false; else enable = is_aa_path_mute(codec) && !spec->gen.active_streams; if (enable == spec->alc_mode && !force) return; spec->alc_mode = enable; /* decide low current mode's verb & parameter */ switch (spec->codec_type) { case VT1708B_8CH: case VT1708B_4CH: verb = 0xf70; parm = enable ? 0x02 : 0x00; /* 0x02: 2/3x, 0x00: 1x */ break; case VT1708S: case VT1718S: case VT1716S: verb = 0xf73; parm = enable ? 0x51 : 0xe1; /* 0x51: 4/28x, 0xe1: 1x */ break; case VT1702: verb = 0xf73; parm = enable ? 0x01 : 0x1d; /* 0x01: 4/40x, 0x1d: 1x */ break; case VT2002P: case VT1812: case VT1802: verb = 0xf93; parm = enable ? 0x00 : 0xe0; /* 0x00: 4/40x, 0xe0: 1x */ break; case VT1705CF: case VT1808: verb = 0xf82; parm = enable ? 0x00 : 0xe0; /* 0x00: 4/40x, 0xe0: 1x */ break; default: return; /* other codecs are not supported */ } /* send verb */ snd_hda_codec_write(codec, codec->core.afg, 0, verb, parm); } static void analog_low_current_mode(struct hda_codec *codec) { return __analog_low_current_mode(codec, false); } static void via_playback_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { analog_low_current_mode(codec); vt1708_update_hp_work(codec); } static void via_free(struct hda_codec *codec) { vt1708_stop_hp_work(codec); snd_hda_gen_free(codec); } #ifdef CONFIG_PM static int via_suspend(struct hda_codec *codec) { struct via_spec *spec = codec->spec; vt1708_stop_hp_work(codec); /* Fix pop noise on headphones */ if (spec->codec_type == VT1802) snd_hda_shutup_pins(codec); return 0; } static int via_resume(struct hda_codec *codec) { /* some delay here to make jack detection working (bko#98921) */ msleep(10); codec->patch_ops.init(codec); snd_hda_regmap_sync(codec); return 0; } #endif #ifdef CONFIG_PM static int via_check_power_status(struct hda_codec *codec, hda_nid_t nid) { struct via_spec *spec = codec->spec; analog_low_current_mode(codec); vt1708_update_hp_work(codec); return snd_hda_check_amp_list_power(codec, &spec->gen.loopback, nid); } #endif /* */ static int via_init(struct hda_codec *codec); static const struct hda_codec_ops via_patch_ops = { .build_controls = snd_hda_gen_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = via_init, .free = via_free, .unsol_event = snd_hda_jack_unsol_event, #ifdef CONFIG_PM .suspend = via_suspend, .resume = via_resume, .check_power_status = via_check_power_status, #endif }; static const struct hda_verb vt1708_init_verbs[] = { /* power down jack detect function */ {0x1, 0xf81, 0x1}, { } }; static void vt1708_set_pinconfig_connect(struct hda_codec *codec, hda_nid_t nid) { unsigned int def_conf; unsigned char seqassoc; def_conf = snd_hda_codec_get_pincfg(codec, nid); seqassoc = (unsigned char) get_defcfg_association(def_conf); seqassoc = (seqassoc << 4) | get_defcfg_sequence(def_conf); if (get_defcfg_connect(def_conf) == AC_JACK_PORT_NONE && (seqassoc == 0xf0 || seqassoc == 0xff)) { def_conf = def_conf & (~(AC_JACK_PORT_BOTH << 30)); snd_hda_codec_set_pincfg(codec, nid, def_conf); } } static int vt1708_jack_detect_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct via_spec *spec = codec->spec; if (spec->codec_type != VT1708) return 0; ucontrol->value.integer.value[0] = spec->vt1708_jack_detect; return 0; } static int vt1708_jack_detect_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct via_spec *spec = codec->spec; int val; if (spec->codec_type != VT1708) return 0; val = !!ucontrol->value.integer.value[0]; if (spec->vt1708_jack_detect == val) return 0; spec->vt1708_jack_detect = val; vt1708_update_hp_work(codec); return 1; } static const struct snd_kcontrol_new vt1708_jack_detect_ctl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Jack Detect", .count = 1, .info = snd_ctl_boolean_mono_info, .get = vt1708_jack_detect_get, .put = vt1708_jack_detect_put, }; static const struct badness_table via_main_out_badness = { .no_primary_dac = 0x10000, .no_dac = 0x4000, .shared_primary = 0x10000, .shared_surr = 0x20, .shared_clfe = 0x20, .shared_surr_main = 0x20, }; static const struct badness_table via_extra_out_badness = { .no_primary_dac = 0x4000, .no_dac = 0x4000, .shared_primary = 0x12, .shared_surr = 0x20, .shared_clfe = 0x20, .shared_surr_main = 0x10, }; static int via_parse_auto_config(struct hda_codec *codec) { struct via_spec *spec = codec->spec; int err; spec->gen.main_out_badness = &via_main_out_badness; spec->gen.extra_out_badness = &via_extra_out_badness; err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); if (err < 0) return err; err = auto_parse_beep(codec); if (err < 0) return err; err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) return err; if (!snd_hda_gen_add_kctl(&spec->gen, NULL, &via_pin_power_ctl_enum)) return -ENOMEM; /* disable widget PM at start for compatibility */ codec->power_save_node = 0; spec->gen.power_down_unused = 0; return 0; } static int via_init(struct hda_codec *codec) { /* init power states */ __analog_low_current_mode(codec, true); snd_hda_gen_init(codec); vt1708_update_hp_work(codec); return 0; } static int vt1708_build_controls(struct hda_codec *codec) { /* In order not to create "Phantom Jack" controls, temporary enable jackpoll */ int err; int old_interval = codec->jackpoll_interval; codec->jackpoll_interval = msecs_to_jiffies(100); err = snd_hda_gen_build_controls(codec); codec->jackpoll_interval = old_interval; return err; } static int vt1708_build_pcms(struct hda_codec *codec) { struct via_spec *spec = codec->spec; int i, err; err = snd_hda_gen_build_pcms(codec); if (err < 0 || codec->core.vendor_id != 0x11061708) return err; /* We got noisy outputs on the right channel on VT1708 when * 24bit samples are used. Until any workaround is found, * disable the 24bit format, so far. */ for (i = 0; i < ARRAY_SIZE(spec->gen.pcm_rec); i++) { struct hda_pcm *info = spec->gen.pcm_rec[i]; if (!info) continue; if (!info->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams || info->pcm_type != HDA_PCM_TYPE_AUDIO) continue; info->stream[SNDRV_PCM_STREAM_PLAYBACK].formats = SNDRV_PCM_FMTBIT_S16_LE; } return 0; } static int patch_vt1708(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; /* override some patch_ops */ codec->patch_ops.build_controls = vt1708_build_controls; codec->patch_ops.build_pcms = vt1708_build_pcms; spec->gen.mixer_nid = 0x17; /* set jackpoll_interval while parsing the codec */ codec->jackpoll_interval = msecs_to_jiffies(100); spec->vt1708_jack_detect = 1; /* don't support the input jack switching due to lack of unsol event */ /* (it may work with polling, though, but it needs testing) */ spec->gen.suppress_auto_mic = 1; /* Some machines show the broken speaker mute */ spec->gen.auto_mute_via_amp = 1; /* Add HP and CD pin config connect bit re-config action */ vt1708_set_pinconfig_connect(codec, VT1708_HP_PIN_NID); vt1708_set_pinconfig_connect(codec, VT1708_CD_PIN_NID); err = snd_hda_add_verbs(codec, vt1708_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; /* add jack detect on/off control */ if (!snd_hda_gen_add_kctl(&spec->gen, NULL, &vt1708_jack_detect_ctl)) { err = -ENOMEM; goto error; } /* clear jackpoll_interval again; it's set dynamically */ codec->jackpoll_interval = 0; return 0; error: via_free(codec); return err; } static int patch_vt1709(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x18; err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } static int patch_vt1708S(struct hda_codec *codec); static int patch_vt1708B(struct hda_codec *codec) { struct via_spec *spec; int err; if (get_codec_type(codec) == VT1708BCE) return patch_vt1708S(codec); /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x16; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* Patch for VT1708S */ static const struct hda_verb vt1708S_init_verbs[] = { /* Enable Mic Boost Volume backdoor */ {0x1, 0xf98, 0x1}, /* don't bybass mixer */ {0x1, 0xf88, 0xc0}, { } }; static void override_mic_boost(struct hda_codec *codec, hda_nid_t pin, int offset, int num_steps, int step_size) { snd_hda_override_wcaps(codec, pin, get_wcaps(codec, pin) | AC_WCAP_IN_AMP); snd_hda_override_amp_caps(codec, pin, HDA_INPUT, (offset << AC_AMPCAP_OFFSET_SHIFT) | (num_steps << AC_AMPCAP_NUM_STEPS_SHIFT) | (step_size << AC_AMPCAP_STEP_SIZE_SHIFT) | (0 << AC_AMPCAP_MUTE_SHIFT)); } static int patch_vt1708S(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x16; override_mic_boost(codec, 0x1a, 0, 3, 40); override_mic_boost(codec, 0x1e, 0, 3, 40); /* correct names for VT1708BCE */ if (get_codec_type(codec) == VT1708BCE) snd_hda_codec_set_name(codec, "VT1708BCE"); /* correct names for VT1705 */ if (codec->core.vendor_id == 0x11064397) snd_hda_codec_set_name(codec, "VT1705"); err = snd_hda_add_verbs(codec, vt1708S_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* Patch for VT1702 */ static const struct hda_verb vt1702_init_verbs[] = { /* mixer enable */ {0x1, 0xF88, 0x3}, /* GPIO 0~2 */ {0x1, 0xF82, 0x3F}, { } }; static int patch_vt1702(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x1a; /* limit AA path volume to 0 dB */ snd_hda_override_amp_caps(codec, 0x1A, HDA_INPUT, (0x17 << AC_AMPCAP_OFFSET_SHIFT) | (0x17 << AC_AMPCAP_NUM_STEPS_SHIFT) | (0x5 << AC_AMPCAP_STEP_SIZE_SHIFT) | (1 << AC_AMPCAP_MUTE_SHIFT)); err = snd_hda_add_verbs(codec, vt1702_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* Patch for VT1718S */ static const struct hda_verb vt1718S_init_verbs[] = { /* Enable MW0 adjust Gain 5 */ {0x1, 0xfb2, 0x10}, /* Enable Boost Volume backdoor */ {0x1, 0xf88, 0x8}, { } }; /* Add a connection to the primary DAC from AA-mixer for some codecs * This isn't listed from the raw info, but the chip has a secret connection. */ static int add_secret_dac_path(struct hda_codec *codec) { struct via_spec *spec = codec->spec; int i, nums; hda_nid_t conn[8]; hda_nid_t nid; if (!spec->gen.mixer_nid) return 0; nums = snd_hda_get_connections(codec, spec->gen.mixer_nid, conn, ARRAY_SIZE(conn) - 1); if (nums < 0) return nums; for (i = 0; i < nums; i++) { if (get_wcaps_type(get_wcaps(codec, conn[i])) == AC_WID_AUD_OUT) return 0; } /* find the primary DAC and add to the connection list */ for_each_hda_codec_node(nid, codec) { unsigned int caps = get_wcaps(codec, nid); if (get_wcaps_type(caps) == AC_WID_AUD_OUT && !(caps & AC_WCAP_DIGITAL)) { conn[nums++] = nid; return snd_hda_override_conn_list(codec, spec->gen.mixer_nid, nums, conn); } } return 0; } static int patch_vt1718S(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x21; override_mic_boost(codec, 0x2b, 0, 3, 40); override_mic_boost(codec, 0x29, 0, 3, 40); add_secret_dac_path(codec); err = snd_hda_add_verbs(codec, vt1718S_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* Patch for VT1716S */ static int vt1716s_dmic_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 1; return 0; } static int vt1716s_dmic_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); int index = 0; index = snd_hda_codec_read(codec, 0x26, 0, AC_VERB_GET_CONNECT_SEL, 0); if (index != -1) *ucontrol->value.integer.value = index; return 0; } static int vt1716s_dmic_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct via_spec *spec = codec->spec; int index = *ucontrol->value.integer.value; snd_hda_codec_write(codec, 0x26, 0, AC_VERB_SET_CONNECT_SEL, index); spec->dmic_enabled = index; return 1; } static const struct snd_kcontrol_new vt1716s_dmic_mixer_vol = HDA_CODEC_VOLUME("Digital Mic Capture Volume", 0x22, 0x0, HDA_INPUT); static const struct snd_kcontrol_new vt1716s_dmic_mixer_sw = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Digital Mic Capture Switch", .subdevice = HDA_SUBDEV_NID_FLAG | 0x26, .count = 1, .info = vt1716s_dmic_info, .get = vt1716s_dmic_get, .put = vt1716s_dmic_put, }; /* mono-out mixer elements */ static const struct snd_kcontrol_new vt1716S_mono_out_mixer = HDA_CODEC_MUTE("Mono Playback Switch", 0x2a, 0x0, HDA_OUTPUT); static const struct hda_verb vt1716S_init_verbs[] = { /* Enable Boost Volume backdoor */ {0x1, 0xf8a, 0x80}, /* don't bybass mixer */ {0x1, 0xf88, 0xc0}, /* Enable mono output */ {0x1, 0xf90, 0x08}, { } }; static int patch_vt1716S(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x16; override_mic_boost(codec, 0x1a, 0, 3, 40); override_mic_boost(codec, 0x1e, 0, 3, 40); err = snd_hda_add_verbs(codec, vt1716S_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; if (!snd_hda_gen_add_kctl(&spec->gen, NULL, &vt1716s_dmic_mixer_vol) || !snd_hda_gen_add_kctl(&spec->gen, NULL, &vt1716s_dmic_mixer_sw) || !snd_hda_gen_add_kctl(&spec->gen, NULL, &vt1716S_mono_out_mixer)) { err = -ENOMEM; goto error; } return 0; error: via_free(codec); return err; } /* for vt2002P */ static const struct hda_verb vt2002P_init_verbs[] = { /* Class-D speaker related verbs */ {0x1, 0xfe0, 0x4}, {0x1, 0xfe9, 0x80}, {0x1, 0xfe2, 0x22}, /* Enable Boost Volume backdoor */ {0x1, 0xfb9, 0x24}, /* Enable AOW0 to MW9 */ {0x1, 0xfb8, 0x88}, { } }; static const struct hda_verb vt1802_init_verbs[] = { /* Enable Boost Volume backdoor */ {0x1, 0xfb9, 0x24}, /* Enable AOW0 to MW9 */ {0x1, 0xfb8, 0x88}, { } }; /* * pin fix-up */ enum { VIA_FIXUP_INTMIC_BOOST, VIA_FIXUP_ASUS_G75, VIA_FIXUP_POWER_SAVE, }; static void via_fixup_intmic_boost(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) override_mic_boost(codec, 0x30, 0, 2, 40); } static void via_fixup_power_save(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) codec->power_save_node = 0; } static const struct hda_fixup via_fixups[] = { [VIA_FIXUP_INTMIC_BOOST] = { .type = HDA_FIXUP_FUNC, .v.func = via_fixup_intmic_boost, }, [VIA_FIXUP_ASUS_G75] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* set 0x24 and 0x33 as speakers */ { 0x24, 0x991301f0 }, { 0x33, 0x991301f1 }, /* subwoofer */ { } } }, [VIA_FIXUP_POWER_SAVE] = { .type = HDA_FIXUP_FUNC, .v.func = via_fixup_power_save, }, }; static const struct snd_pci_quirk vt2002p_fixups[] = { SND_PCI_QUIRK(0x1043, 0x13f7, "Asus B23E", VIA_FIXUP_POWER_SAVE), SND_PCI_QUIRK(0x1043, 0x1487, "Asus G75", VIA_FIXUP_ASUS_G75), SND_PCI_QUIRK(0x1043, 0x8532, "Asus X202E", VIA_FIXUP_INTMIC_BOOST), SND_PCI_QUIRK_VENDOR(0x1558, "Clevo", VIA_FIXUP_POWER_SAVE), {} }; /* NIDs 0x24 and 0x33 on VT1802 have connections to non-existing NID 0x3e * Replace this with mixer NID 0x1c */ static void fix_vt1802_connections(struct hda_codec *codec) { static const hda_nid_t conn_24[] = { 0x14, 0x1c }; static const hda_nid_t conn_33[] = { 0x1c }; snd_hda_override_conn_list(codec, 0x24, ARRAY_SIZE(conn_24), conn_24); snd_hda_override_conn_list(codec, 0x33, ARRAY_SIZE(conn_33), conn_33); } /* patch for vt2002P */ static int patch_vt2002P(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x21; override_mic_boost(codec, 0x2b, 0, 3, 40); override_mic_boost(codec, 0x29, 0, 3, 40); if (spec->codec_type == VT1802) fix_vt1802_connections(codec); add_secret_dac_path(codec); snd_hda_pick_fixup(codec, NULL, vt2002p_fixups, via_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); if (spec->codec_type == VT1802) err = snd_hda_add_verbs(codec, vt1802_init_verbs); else err = snd_hda_add_verbs(codec, vt2002P_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* for vt1812 */ static const struct hda_verb vt1812_init_verbs[] = { /* Enable Boost Volume backdoor */ {0x1, 0xfb9, 0x24}, /* Enable AOW0 to MW9 */ {0x1, 0xfb8, 0xa8}, { } }; /* patch for vt1812 */ static int patch_vt1812(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x21; override_mic_boost(codec, 0x2b, 0, 3, 40); override_mic_boost(codec, 0x29, 0, 3, 40); add_secret_dac_path(codec); err = snd_hda_add_verbs(codec, vt1812_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* patch for vt3476 */ static const struct hda_verb vt3476_init_verbs[] = { /* Enable DMic 8/16/32K */ {0x1, 0xF7B, 0x30}, /* Enable Boost Volume backdoor */ {0x1, 0xFB9, 0x20}, /* Enable AOW-MW9 path */ {0x1, 0xFB8, 0x10}, { } }; static int patch_vt3476(struct hda_codec *codec) { struct via_spec *spec; int err; /* create a codec specific record */ spec = via_new_spec(codec); if (spec == NULL) return -ENOMEM; spec->gen.mixer_nid = 0x3f; add_secret_dac_path(codec); err = snd_hda_add_verbs(codec, vt3476_init_verbs); if (err < 0) goto error; /* automatic parse from the BIOS config */ err = via_parse_auto_config(codec); if (err < 0) goto error; return 0; error: via_free(codec); return err; } /* * patch entries */ static const struct hda_device_id snd_hda_id_via[] = { HDA_CODEC_ENTRY(0x11061708, "VT1708", patch_vt1708), HDA_CODEC_ENTRY(0x11061709, "VT1708", patch_vt1708), HDA_CODEC_ENTRY(0x1106170a, "VT1708", patch_vt1708), HDA_CODEC_ENTRY(0x1106170b, "VT1708", patch_vt1708), HDA_CODEC_ENTRY(0x1106e710, "VT1709 10-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e711, "VT1709 10-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e712, "VT1709 10-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e713, "VT1709 10-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e714, "VT1709 6-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e715, "VT1709 6-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e716, "VT1709 6-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e717, "VT1709 6-Ch", patch_vt1709), HDA_CODEC_ENTRY(0x1106e720, "VT1708B 8-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e721, "VT1708B 8-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e722, "VT1708B 8-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e723, "VT1708B 8-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e724, "VT1708B 4-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e725, "VT1708B 4-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e726, "VT1708B 4-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x1106e727, "VT1708B 4-Ch", patch_vt1708B), HDA_CODEC_ENTRY(0x11060397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11061397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11062397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11063397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11064397, "VT1705", patch_vt1708S), HDA_CODEC_ENTRY(0x11065397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11066397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11067397, "VT1708S", patch_vt1708S), HDA_CODEC_ENTRY(0x11060398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11061398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11062398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11063398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11064398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11065398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11066398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11067398, "VT1702", patch_vt1702), HDA_CODEC_ENTRY(0x11060428, "VT1718S", patch_vt1718S), HDA_CODEC_ENTRY(0x11064428, "VT1718S", patch_vt1718S), HDA_CODEC_ENTRY(0x11060441, "VT2020", patch_vt1718S), HDA_CODEC_ENTRY(0x11064441, "VT1828S", patch_vt1718S), HDA_CODEC_ENTRY(0x11060433, "VT1716S", patch_vt1716S), HDA_CODEC_ENTRY(0x1106a721, "VT1716S", patch_vt1716S), HDA_CODEC_ENTRY(0x11060438, "VT2002P", patch_vt2002P), HDA_CODEC_ENTRY(0x11064438, "VT2002P", patch_vt2002P), HDA_CODEC_ENTRY(0x11060448, "VT1812", patch_vt1812), HDA_CODEC_ENTRY(0x11060440, "VT1818S", patch_vt1708S), HDA_CODEC_ENTRY(0x11060446, "VT1802", patch_vt2002P), HDA_CODEC_ENTRY(0x11068446, "VT1802", patch_vt2002P), HDA_CODEC_ENTRY(0x11064760, "VT1705CF", patch_vt3476), HDA_CODEC_ENTRY(0x11064761, "VT1708SCE", patch_vt3476), HDA_CODEC_ENTRY(0x11064762, "VT1808", patch_vt3476), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_via); static struct hda_codec_driver via_driver = { .id = snd_hda_id_via, }; MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("VIA HD-audio codec"); module_hda_codec_driver(via_driver);
linux-master
sound/pci/hda/patch_via.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Universal Interface for Intel High Definition Audio Codec * * HD audio interface patch for SigmaTel STAC92xx * * Copyright (c) 2005 Embedded Alley Solutions, Inc. * Matt Porter <[email protected]> * * Based on patch_cmedia.c and patch_realtek.c * Copyright (c) 2004 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/dmi.h> #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_beep.h" #include "hda_jack.h" #include "hda_generic.h" enum { STAC_REF, STAC_9200_OQO, STAC_9200_DELL_D21, STAC_9200_DELL_D22, STAC_9200_DELL_D23, STAC_9200_DELL_M21, STAC_9200_DELL_M22, STAC_9200_DELL_M23, STAC_9200_DELL_M24, STAC_9200_DELL_M25, STAC_9200_DELL_M26, STAC_9200_DELL_M27, STAC_9200_M4, STAC_9200_M4_2, STAC_9200_PANASONIC, STAC_9200_EAPD_INIT, STAC_9200_MODELS }; enum { STAC_9205_REF, STAC_9205_DELL_M42, STAC_9205_DELL_M43, STAC_9205_DELL_M44, STAC_9205_EAPD, STAC_9205_MODELS }; enum { STAC_92HD73XX_NO_JD, /* no jack-detection */ STAC_92HD73XX_REF, STAC_92HD73XX_INTEL, STAC_DELL_M6_AMIC, STAC_DELL_M6_DMIC, STAC_DELL_M6_BOTH, STAC_DELL_EQ, STAC_ALIENWARE_M17X, STAC_ELO_VUPOINT_15MX, STAC_92HD89XX_HP_FRONT_JACK, STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK, STAC_92HD73XX_ASUS_MOBO, STAC_92HD73XX_MODELS }; enum { STAC_92HD83XXX_REF, STAC_92HD83XXX_PWR_REF, STAC_DELL_S14, STAC_DELL_VOSTRO_3500, STAC_92HD83XXX_HP_cNB11_INTQUAD, STAC_HP_DV7_4000, STAC_HP_ZEPHYR, STAC_92HD83XXX_HP_LED, STAC_92HD83XXX_HP_INV_LED, STAC_92HD83XXX_HP_MIC_LED, STAC_HP_LED_GPIO10, STAC_92HD83XXX_HEADSET_JACK, STAC_92HD83XXX_HP, STAC_HP_ENVY_BASS, STAC_HP_BNB13_EQ, STAC_HP_ENVY_TS_BASS, STAC_HP_ENVY_TS_DAC_BIND, STAC_92HD83XXX_GPIO10_EAPD, STAC_92HD83XXX_MODELS }; enum { STAC_92HD71BXX_REF, STAC_DELL_M4_1, STAC_DELL_M4_2, STAC_DELL_M4_3, STAC_HP_M4, STAC_HP_DV4, STAC_HP_DV5, STAC_HP_HDX, STAC_92HD71BXX_HP, STAC_92HD71BXX_NO_DMIC, STAC_92HD71BXX_NO_SMUX, STAC_92HD71BXX_MODELS }; enum { STAC_92HD95_HP_LED, STAC_92HD95_HP_BASS, STAC_92HD95_MODELS }; enum { STAC_925x_REF, STAC_M1, STAC_M1_2, STAC_M2, STAC_M2_2, STAC_M3, STAC_M5, STAC_M6, STAC_925x_MODELS }; enum { STAC_D945_REF, STAC_D945GTP3, STAC_D945GTP5, STAC_INTEL_MAC_V1, STAC_INTEL_MAC_V2, STAC_INTEL_MAC_V3, STAC_INTEL_MAC_V4, STAC_INTEL_MAC_V5, STAC_INTEL_MAC_AUTO, STAC_ECS_202, STAC_922X_DELL_D81, STAC_922X_DELL_D82, STAC_922X_DELL_M81, STAC_922X_DELL_M82, STAC_922X_INTEL_MAC_GPIO, STAC_922X_MODELS }; enum { STAC_D965_REF_NO_JD, /* no jack-detection */ STAC_D965_REF, STAC_D965_3ST, STAC_D965_5ST, STAC_D965_5ST_NO_FP, STAC_D965_VERBS, STAC_DELL_3ST, STAC_DELL_BIOS, STAC_NEMO_DEFAULT, STAC_DELL_BIOS_AMIC, STAC_DELL_BIOS_SPDIF, STAC_927X_DELL_DMIC, STAC_927X_VOLKNOB, STAC_927X_MODELS }; enum { STAC_9872_VAIO, STAC_9872_MODELS }; struct sigmatel_spec { struct hda_gen_spec gen; unsigned int eapd_switch: 1; unsigned int linear_tone_beep:1; unsigned int headset_jack:1; /* 4-pin headset jack (hp + mono mic) */ unsigned int volknob_init:1; /* special volume-knob initialization */ unsigned int powerdown_adcs:1; unsigned int have_spdif_mux:1; /* gpio lines */ unsigned int eapd_mask; unsigned int gpio_mask; unsigned int gpio_dir; unsigned int gpio_data; unsigned int gpio_mute; unsigned int gpio_led; unsigned int gpio_led_polarity; unsigned int vref_mute_led_nid; /* pin NID for mute-LED vref control */ unsigned int vref_led; int default_polarity; unsigned int mic_mute_led_gpio; /* capture mute LED GPIO */ unsigned int mic_enabled; /* current mic mute state (bitmask) */ /* stream */ unsigned int stream_delay; /* analog loopback */ const struct snd_kcontrol_new *aloopback_ctl; unsigned int aloopback; unsigned char aloopback_mask; unsigned char aloopback_shift; /* power management */ unsigned int power_map_bits; unsigned int num_pwrs; const hda_nid_t *pwr_nids; unsigned int active_adcs; /* beep widgets */ hda_nid_t anabeep_nid; bool beep_power_on; /* SPDIF-out mux */ const char * const *spdif_labels; struct hda_input_mux spdif_mux; unsigned int cur_smux[2]; }; #define AC_VERB_IDT_SET_POWER_MAP 0x7ec #define AC_VERB_IDT_GET_POWER_MAP 0xfec static const hda_nid_t stac92hd73xx_pwr_nids[8] = { 0x0a, 0x0b, 0x0c, 0xd, 0x0e, 0x0f, 0x10, 0x11 }; static const hda_nid_t stac92hd83xxx_pwr_nids[7] = { 0x0a, 0x0b, 0x0c, 0xd, 0x0e, 0x0f, 0x10 }; static const hda_nid_t stac92hd71bxx_pwr_nids[3] = { 0x0a, 0x0d, 0x0f }; /* * PCM hooks */ static void stac_playback_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_GEN_PCM_ACT_OPEN && spec->stream_delay) msleep(spec->stream_delay); } static void stac_capture_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { struct sigmatel_spec *spec = codec->spec; int i, idx = 0; if (!spec->powerdown_adcs) return; for (i = 0; i < spec->gen.num_all_adcs; i++) { if (spec->gen.all_adcs[i] == hinfo->nid) { idx = i; break; } } switch (action) { case HDA_GEN_PCM_ACT_OPEN: msleep(40); snd_hda_codec_write(codec, hinfo->nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); spec->active_adcs |= (1 << idx); break; case HDA_GEN_PCM_ACT_CLOSE: snd_hda_codec_write(codec, hinfo->nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D3); spec->active_adcs &= ~(1 << idx); break; } } /* * Early 2006 Intel Macintoshes with STAC9220X5 codecs seem to have a * funky external mute control using GPIO pins. */ static void stac_gpio_set(struct hda_codec *codec, unsigned int mask, unsigned int dir_mask, unsigned int data) { unsigned int gpiostate, gpiomask, gpiodir; hda_nid_t fg = codec->core.afg; codec_dbg(codec, "%s msk %x dir %x gpio %x\n", __func__, mask, dir_mask, data); gpiostate = snd_hda_codec_read(codec, fg, 0, AC_VERB_GET_GPIO_DATA, 0); gpiostate = (gpiostate & ~dir_mask) | (data & dir_mask); gpiomask = snd_hda_codec_read(codec, fg, 0, AC_VERB_GET_GPIO_MASK, 0); gpiomask |= mask; gpiodir = snd_hda_codec_read(codec, fg, 0, AC_VERB_GET_GPIO_DIRECTION, 0); gpiodir |= dir_mask; /* Configure GPIOx as CMOS */ snd_hda_codec_write(codec, fg, 0, 0x7e7, 0); snd_hda_codec_write(codec, fg, 0, AC_VERB_SET_GPIO_MASK, gpiomask); snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_GPIO_DIRECTION, gpiodir); /* sync */ msleep(1); snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_GPIO_DATA, gpiostate); /* sync */ } /* hook for controlling mic-mute LED GPIO */ static int stac_capture_led_update(struct led_classdev *led_cdev, enum led_brightness brightness) { struct hda_codec *codec = dev_to_hda_codec(led_cdev->dev->parent); struct sigmatel_spec *spec = codec->spec; if (brightness) spec->gpio_data |= spec->mic_mute_led_gpio; else spec->gpio_data &= ~spec->mic_mute_led_gpio; stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data); return 0; } static int stac_vrefout_set(struct hda_codec *codec, hda_nid_t nid, unsigned int new_vref) { int error, pinctl; codec_dbg(codec, "%s, nid %x ctl %x\n", __func__, nid, new_vref); pinctl = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); if (pinctl < 0) return pinctl; pinctl &= 0xff; pinctl &= ~AC_PINCTL_VREFEN; pinctl |= (new_vref & AC_PINCTL_VREFEN); error = snd_hda_set_pin_ctl_cache(codec, nid, pinctl); if (error < 0) return error; return 1; } /* prevent codec AFG to D3 state when vref-out pin is used for mute LED */ /* this hook is set in stac_setup_gpio() */ static unsigned int stac_vref_led_power_filter(struct hda_codec *codec, hda_nid_t nid, unsigned int power_state) { if (nid == codec->core.afg && power_state == AC_PWRST_D3) return AC_PWRST_D1; return snd_hda_gen_path_power_filter(codec, nid, power_state); } /* update mute-LED accoring to the master switch */ static void stac_update_led_status(struct hda_codec *codec, bool muted) { struct sigmatel_spec *spec = codec->spec; if (!spec->gpio_led) return; /* LED state is inverted on these systems */ if (spec->gpio_led_polarity) muted = !muted; if (!spec->vref_mute_led_nid) { if (muted) spec->gpio_data |= spec->gpio_led; else spec->gpio_data &= ~spec->gpio_led; stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data); } else { spec->vref_led = muted ? AC_PINCTL_VREF_50 : AC_PINCTL_VREF_GRD; stac_vrefout_set(codec, spec->vref_mute_led_nid, spec->vref_led); } } /* vmaster hook to update mute LED */ static int stac_vmaster_hook(struct led_classdev *led_cdev, enum led_brightness brightness) { struct hda_codec *codec = dev_to_hda_codec(led_cdev->dev->parent); stac_update_led_status(codec, brightness); return 0; } /* automute hook to handle GPIO mute and EAPD updates */ static void stac_update_outputs(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; if (spec->gpio_mute) spec->gen.master_mute = !(snd_hda_codec_read(codec, codec->core.afg, 0, AC_VERB_GET_GPIO_DATA, 0) & spec->gpio_mute); snd_hda_gen_update_outputs(codec); if (spec->eapd_mask && spec->eapd_switch) { unsigned int val = spec->gpio_data; if (spec->gen.speaker_muted) val &= ~spec->eapd_mask; else val |= spec->eapd_mask; if (spec->gpio_data != val) { spec->gpio_data = val; stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, val); } } } static void stac_toggle_power_map(struct hda_codec *codec, hda_nid_t nid, bool enable, bool do_write) { struct sigmatel_spec *spec = codec->spec; unsigned int idx, val; for (idx = 0; idx < spec->num_pwrs; idx++) { if (spec->pwr_nids[idx] == nid) break; } if (idx >= spec->num_pwrs) return; idx = 1 << idx; val = spec->power_map_bits; if (enable) val &= ~idx; else val |= idx; /* power down unused output ports */ if (val != spec->power_map_bits) { spec->power_map_bits = val; if (do_write) snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_IDT_SET_POWER_MAP, val); } } /* update power bit per jack plug/unplug */ static void jack_update_power(struct hda_codec *codec, struct hda_jack_callback *jack) { struct sigmatel_spec *spec = codec->spec; int i; if (!spec->num_pwrs) return; if (jack && jack->nid) { stac_toggle_power_map(codec, jack->nid, snd_hda_jack_detect(codec, jack->nid), true); return; } /* update all jacks */ for (i = 0; i < spec->num_pwrs; i++) { hda_nid_t nid = spec->pwr_nids[i]; if (!snd_hda_jack_tbl_get(codec, nid)) continue; stac_toggle_power_map(codec, nid, snd_hda_jack_detect(codec, nid), false); } snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_IDT_SET_POWER_MAP, spec->power_map_bits); } static void stac_vref_event(struct hda_codec *codec, struct hda_jack_callback *event) { unsigned int data; data = snd_hda_codec_read(codec, codec->core.afg, 0, AC_VERB_GET_GPIO_DATA, 0); /* toggle VREF state based on GPIOx status */ snd_hda_codec_write(codec, codec->core.afg, 0, 0x7e0, !!(data & (1 << event->private_data))); } /* initialize the power map and enable the power event to jacks that * haven't been assigned to automute */ static void stac_init_power_map(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; int i; for (i = 0; i < spec->num_pwrs; i++) { hda_nid_t nid = spec->pwr_nids[i]; unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid); def_conf = get_defcfg_connect(def_conf); if (def_conf == AC_JACK_PORT_COMPLEX && spec->vref_mute_led_nid != nid && is_jack_detectable(codec, nid)) { snd_hda_jack_detect_enable_callback(codec, nid, jack_update_power); } else { if (def_conf == AC_JACK_PORT_NONE) stac_toggle_power_map(codec, nid, false, false); else stac_toggle_power_map(codec, nid, true, false); } } } /* */ static inline bool get_int_hint(struct hda_codec *codec, const char *key, int *valp) { return !snd_hda_get_int_hint(codec, key, valp); } /* override some hints from the hwdep entry */ static void stac_store_hints(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; int val; if (get_int_hint(codec, "gpio_mask", &spec->gpio_mask)) { spec->eapd_mask = spec->gpio_dir = spec->gpio_data = spec->gpio_mask; } if (get_int_hint(codec, "gpio_dir", &spec->gpio_dir)) spec->gpio_dir &= spec->gpio_mask; if (get_int_hint(codec, "gpio_data", &spec->gpio_data)) spec->gpio_data &= spec->gpio_mask; if (get_int_hint(codec, "eapd_mask", &spec->eapd_mask)) spec->eapd_mask &= spec->gpio_mask; if (get_int_hint(codec, "gpio_mute", &spec->gpio_mute)) spec->gpio_mute &= spec->gpio_mask; val = snd_hda_get_bool_hint(codec, "eapd_switch"); if (val >= 0) spec->eapd_switch = val; } /* * loopback controls */ #define stac_aloopback_info snd_ctl_boolean_mono_info static int stac_aloopback_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); struct sigmatel_spec *spec = codec->spec; ucontrol->value.integer.value[0] = !!(spec->aloopback & (spec->aloopback_mask << idx)); return 0; } static int stac_aloopback_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); unsigned int dac_mode; unsigned int val, idx_val; idx_val = spec->aloopback_mask << idx; if (ucontrol->value.integer.value[0]) val = spec->aloopback | idx_val; else val = spec->aloopback & ~idx_val; if (spec->aloopback == val) return 0; spec->aloopback = val; /* Only return the bits defined by the shift value of the * first two bytes of the mask */ dac_mode = snd_hda_codec_read(codec, codec->core.afg, 0, kcontrol->private_value & 0xFFFF, 0x0); dac_mode >>= spec->aloopback_shift; if (spec->aloopback & idx_val) { snd_hda_power_up(codec); dac_mode |= idx_val; } else { snd_hda_power_down(codec); dac_mode &= ~idx_val; } snd_hda_codec_write_cache(codec, codec->core.afg, 0, kcontrol->private_value >> 16, dac_mode); return 1; } #define STAC_ANALOG_LOOPBACK(verb_read, verb_write, cnt) \ { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = "Analog Loopback", \ .count = cnt, \ .info = stac_aloopback_info, \ .get = stac_aloopback_get, \ .put = stac_aloopback_put, \ .private_value = verb_read | (verb_write << 16), \ } /* * Mute LED handling on HP laptops */ /* check whether it's a HP laptop with a docking port */ static bool hp_bnb2011_with_dock(struct hda_codec *codec) { if (codec->core.vendor_id != 0x111d7605 && codec->core.vendor_id != 0x111d76d1) return false; switch (codec->core.subsystem_id) { case 0x103c1618: case 0x103c1619: case 0x103c161a: case 0x103c161b: case 0x103c161c: case 0x103c161d: case 0x103c161e: case 0x103c161f: case 0x103c162a: case 0x103c162b: case 0x103c1630: case 0x103c1631: case 0x103c1633: case 0x103c1634: case 0x103c1635: case 0x103c3587: case 0x103c3588: case 0x103c3589: case 0x103c358a: case 0x103c3667: case 0x103c3668: case 0x103c3669: return true; } return false; } static bool hp_blike_system(u32 subsystem_id) { switch (subsystem_id) { case 0x103c1473: /* HP ProBook 6550b */ case 0x103c1520: case 0x103c1521: case 0x103c1523: case 0x103c1524: case 0x103c1525: case 0x103c1722: case 0x103c1723: case 0x103c1724: case 0x103c1725: case 0x103c1726: case 0x103c1727: case 0x103c1728: case 0x103c1729: case 0x103c172a: case 0x103c172b: case 0x103c307e: case 0x103c307f: case 0x103c3080: case 0x103c3081: case 0x103c7007: case 0x103c7008: return true; } return false; } static void set_hp_led_gpio(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; unsigned int gpio; if (spec->gpio_led) return; gpio = snd_hda_param_read(codec, codec->core.afg, AC_PAR_GPIO_CAP); gpio &= AC_GPIO_IO_COUNT; if (gpio > 3) spec->gpio_led = 0x08; /* GPIO 3 */ else spec->gpio_led = 0x01; /* GPIO 0 */ } /* * This method searches for the mute LED GPIO configuration * provided as OEM string in SMBIOS. The format of that string * is HP_Mute_LED_P_G or HP_Mute_LED_P * where P can be 0 or 1 and defines mute LED GPIO control state (low/high) * that corresponds to the NOT muted state of the master volume * and G is the index of the GPIO to use as the mute LED control (0..9) * If _G portion is missing it is assigned based on the codec ID * * So, HP B-series like systems may have HP_Mute_LED_0 (current models) * or HP_Mute_LED_0_3 (future models) OEM SMBIOS strings * * * The dv-series laptops don't seem to have the HP_Mute_LED* strings in * SMBIOS - at least the ones I have seen do not have them - which include * my own system (HP Pavilion dv6-1110ax) and my cousin's * HP Pavilion dv9500t CTO. * Need more information on whether it is true across the entire series. * -- kunal */ static int find_mute_led_cfg(struct hda_codec *codec, int default_polarity) { struct sigmatel_spec *spec = codec->spec; const struct dmi_device *dev = NULL; if (get_int_hint(codec, "gpio_led", &spec->gpio_led)) { get_int_hint(codec, "gpio_led_polarity", &spec->gpio_led_polarity); return 1; } while ((dev = dmi_find_device(DMI_DEV_TYPE_OEM_STRING, NULL, dev))) { if (sscanf(dev->name, "HP_Mute_LED_%u_%x", &spec->gpio_led_polarity, &spec->gpio_led) == 2) { unsigned int max_gpio; max_gpio = snd_hda_param_read(codec, codec->core.afg, AC_PAR_GPIO_CAP); max_gpio &= AC_GPIO_IO_COUNT; if (spec->gpio_led < max_gpio) spec->gpio_led = 1 << spec->gpio_led; else spec->vref_mute_led_nid = spec->gpio_led; return 1; } if (sscanf(dev->name, "HP_Mute_LED_%u", &spec->gpio_led_polarity) == 1) { set_hp_led_gpio(codec); return 1; } /* BIOS bug: unfilled OEM string */ if (strstr(dev->name, "HP_Mute_LED_P_G")) { set_hp_led_gpio(codec); if (default_polarity >= 0) spec->gpio_led_polarity = default_polarity; else spec->gpio_led_polarity = 1; return 1; } } /* * Fallback case - if we don't find the DMI strings, * we statically set the GPIO - if not a B-series system * and default polarity is provided */ if (!hp_blike_system(codec->core.subsystem_id) && (default_polarity == 0 || default_polarity == 1)) { set_hp_led_gpio(codec); spec->gpio_led_polarity = default_polarity; return 1; } return 0; } /* check whether a built-in speaker is included in parsed pins */ static bool has_builtin_speaker(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; const hda_nid_t *nid_pin; int nids, i; if (spec->gen.autocfg.line_out_type == AUTO_PIN_SPEAKER_OUT) { nid_pin = spec->gen.autocfg.line_out_pins; nids = spec->gen.autocfg.line_outs; } else { nid_pin = spec->gen.autocfg.speaker_pins; nids = spec->gen.autocfg.speaker_outs; } for (i = 0; i < nids; i++) { unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid_pin[i]); if (snd_hda_get_input_pin_attr(def_conf) == INPUT_PIN_ATTR_INT) return true; } return false; } /* * PC beep controls */ /* create PC beep volume controls */ static int stac_auto_create_beep_ctls(struct hda_codec *codec, hda_nid_t nid) { struct sigmatel_spec *spec = codec->spec; u32 caps = query_amp_caps(codec, nid, HDA_OUTPUT); struct snd_kcontrol_new *knew; static const struct snd_kcontrol_new abeep_mute_ctl = HDA_CODEC_MUTE(NULL, 0, 0, 0); static const struct snd_kcontrol_new dbeep_mute_ctl = HDA_CODEC_MUTE_BEEP(NULL, 0, 0, 0); static const struct snd_kcontrol_new beep_vol_ctl = HDA_CODEC_VOLUME(NULL, 0, 0, 0); /* check for mute support for the amp */ if ((caps & AC_AMPCAP_MUTE) >> AC_AMPCAP_MUTE_SHIFT) { const struct snd_kcontrol_new *temp; if (spec->anabeep_nid == nid) temp = &abeep_mute_ctl; else temp = &dbeep_mute_ctl; knew = snd_hda_gen_add_kctl(&spec->gen, "Beep Playback Switch", temp); if (!knew) return -ENOMEM; knew->private_value = HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT); } /* check to see if there is volume support for the amp */ if ((caps & AC_AMPCAP_NUM_STEPS) >> AC_AMPCAP_NUM_STEPS_SHIFT) { knew = snd_hda_gen_add_kctl(&spec->gen, "Beep Playback Volume", &beep_vol_ctl); if (!knew) return -ENOMEM; knew->private_value = HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT); } return 0; } #ifdef CONFIG_SND_HDA_INPUT_BEEP #define stac_dig_beep_switch_info snd_ctl_boolean_mono_info static int stac_dig_beep_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); ucontrol->value.integer.value[0] = codec->beep->enabled; return 0; } static int stac_dig_beep_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); return snd_hda_enable_beep_device(codec, ucontrol->value.integer.value[0]); } static const struct snd_kcontrol_new stac_dig_beep_ctrl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Beep Playback Switch", .info = stac_dig_beep_switch_info, .get = stac_dig_beep_switch_get, .put = stac_dig_beep_switch_put, }; static int stac_beep_switch_ctl(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; if (!snd_hda_gen_add_kctl(&spec->gen, NULL, &stac_dig_beep_ctrl)) return -ENOMEM; return 0; } #endif /* * SPDIF-out mux controls */ static int stac_smux_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; return snd_hda_input_mux_info(&spec->spdif_mux, uinfo); } static int stac_smux_enum_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; unsigned int smux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); ucontrol->value.enumerated.item[0] = spec->cur_smux[smux_idx]; return 0; } static int stac_smux_enum_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; unsigned int smux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); return snd_hda_input_mux_put(codec, &spec->spdif_mux, ucontrol, spec->gen.autocfg.dig_out_pins[smux_idx], &spec->cur_smux[smux_idx]); } static const struct snd_kcontrol_new stac_smux_mixer = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "IEC958 Playback Source", /* count set later */ .info = stac_smux_enum_info, .get = stac_smux_enum_get, .put = stac_smux_enum_put, }; static const char * const stac_spdif_labels[] = { "Digital Playback", "Analog Mux 1", "Analog Mux 2", NULL }; static int stac_create_spdif_mux_ctls(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->gen.autocfg; const char * const *labels = spec->spdif_labels; struct snd_kcontrol_new *kctl; int i, num_cons; if (cfg->dig_outs < 1) return 0; num_cons = snd_hda_get_num_conns(codec, cfg->dig_out_pins[0]); if (num_cons <= 1) return 0; if (!labels) labels = stac_spdif_labels; for (i = 0; i < num_cons; i++) { if (snd_BUG_ON(!labels[i])) return -EINVAL; snd_hda_add_imux_item(codec, &spec->spdif_mux, labels[i], i, NULL); } kctl = snd_hda_gen_add_kctl(&spec->gen, NULL, &stac_smux_mixer); if (!kctl) return -ENOMEM; kctl->count = cfg->dig_outs; return 0; } static const struct hda_verb stac9200_eapd_init[] = { /* set dac0mux for dac converter */ {0x07, AC_VERB_SET_CONNECT_SEL, 0x00}, {0x08, AC_VERB_SET_EAPD_BTLENABLE, 0x02}, {} }; static const struct hda_verb dell_eq_core_init[] = { /* set master volume to max value without distortion * and direct control */ { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xec}, {} }; static const struct hda_verb stac92hd73xx_core_init[] = { /* set master volume and direct control */ { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, {} }; static const struct hda_verb stac92hd83xxx_core_init[] = { /* power state controls amps */ { 0x01, AC_VERB_SET_EAPD, 1 << 2}, {} }; static const struct hda_verb stac92hd83xxx_hp_zephyr_init[] = { { 0x22, 0x785, 0x43 }, { 0x22, 0x782, 0xe0 }, { 0x22, 0x795, 0x00 }, {} }; static const struct hda_verb stac92hd71bxx_core_init[] = { /* set master volume and direct control */ { 0x28, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, {} }; static const hda_nid_t stac92hd71bxx_unmute_nids[] = { /* unmute right and left channels for nodes 0x0f, 0xa, 0x0d */ 0x0f, 0x0a, 0x0d, 0 }; static const struct hda_verb stac925x_core_init[] = { /* set dac0mux for dac converter */ { 0x06, AC_VERB_SET_CONNECT_SEL, 0x00}, /* mute the master volume */ { 0x0e, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE }, {} }; static const struct hda_verb stac922x_core_init[] = { /* set master volume and direct control */ { 0x16, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, {} }; static const struct hda_verb d965_core_init[] = { /* unmute node 0x1b */ { 0x1b, AC_VERB_SET_AMP_GAIN_MUTE, 0xb000}, /* select node 0x03 as DAC */ { 0x0b, AC_VERB_SET_CONNECT_SEL, 0x01}, {} }; static const struct hda_verb dell_3st_core_init[] = { /* don't set delta bit */ {0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0x7f}, /* unmute node 0x1b */ {0x1b, AC_VERB_SET_AMP_GAIN_MUTE, 0xb000}, /* select node 0x03 as DAC */ {0x0b, AC_VERB_SET_CONNECT_SEL, 0x01}, {} }; static const struct hda_verb stac927x_core_init[] = { /* set master volume and direct control */ { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, /* enable analog pc beep path */ { 0x01, AC_VERB_SET_DIGI_CONVERT_2, 1 << 5}, {} }; static const struct hda_verb stac927x_volknob_core_init[] = { /* don't set delta bit */ {0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0x7f}, /* enable analog pc beep path */ {0x01, AC_VERB_SET_DIGI_CONVERT_2, 1 << 5}, {} }; static const struct hda_verb stac9205_core_init[] = { /* set master volume and direct control */ { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, /* enable analog pc beep path */ { 0x01, AC_VERB_SET_DIGI_CONVERT_2, 1 << 5}, {} }; static const struct snd_kcontrol_new stac92hd73xx_6ch_loopback = STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 3); static const struct snd_kcontrol_new stac92hd73xx_8ch_loopback = STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 4); static const struct snd_kcontrol_new stac92hd73xx_10ch_loopback = STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 5); static const struct snd_kcontrol_new stac92hd71bxx_loopback = STAC_ANALOG_LOOPBACK(0xFA0, 0x7A0, 2); static const struct snd_kcontrol_new stac9205_loopback = STAC_ANALOG_LOOPBACK(0xFE0, 0x7E0, 1); static const struct snd_kcontrol_new stac927x_loopback = STAC_ANALOG_LOOPBACK(0xFEB, 0x7EB, 1); static const struct hda_pintbl ref9200_pin_configs[] = { { 0x08, 0x01c47010 }, { 0x09, 0x01447010 }, { 0x0d, 0x0221401f }, { 0x0e, 0x01114010 }, { 0x0f, 0x02a19020 }, { 0x10, 0x01a19021 }, { 0x11, 0x90100140 }, { 0x12, 0x01813122 }, {} }; static const struct hda_pintbl gateway9200_m4_pin_configs[] = { { 0x08, 0x400000fe }, { 0x09, 0x404500f4 }, { 0x0d, 0x400100f0 }, { 0x0e, 0x90110010 }, { 0x0f, 0x400100f1 }, { 0x10, 0x02a1902e }, { 0x11, 0x500000f2 }, { 0x12, 0x500000f3 }, {} }; static const struct hda_pintbl gateway9200_m4_2_pin_configs[] = { { 0x08, 0x400000fe }, { 0x09, 0x404500f4 }, { 0x0d, 0x400100f0 }, { 0x0e, 0x90110010 }, { 0x0f, 0x400100f1 }, { 0x10, 0x02a1902e }, { 0x11, 0x500000f2 }, { 0x12, 0x500000f3 }, {} }; /* STAC 9200 pin configs for 102801A8 102801DE 102801E8 */ static const struct hda_pintbl dell9200_d21_pin_configs[] = { { 0x08, 0x400001f0 }, { 0x09, 0x400001f1 }, { 0x0d, 0x02214030 }, { 0x0e, 0x01014010 }, { 0x0f, 0x02a19020 }, { 0x10, 0x01a19021 }, { 0x11, 0x90100140 }, { 0x12, 0x01813122 }, {} }; /* STAC 9200 pin configs for 102801C0 102801C1 */ static const struct hda_pintbl dell9200_d22_pin_configs[] = { { 0x08, 0x400001f0 }, { 0x09, 0x400001f1 }, { 0x0d, 0x0221401f }, { 0x0e, 0x01014010 }, { 0x0f, 0x01813020 }, { 0x10, 0x02a19021 }, { 0x11, 0x90100140 }, { 0x12, 0x400001f2 }, {} }; /* STAC 9200 pin configs for 102801C4 (Dell Dimension E310) 102801C5 102801C7 102801D9 102801DA 102801E3 */ static const struct hda_pintbl dell9200_d23_pin_configs[] = { { 0x08, 0x400001f0 }, { 0x09, 0x400001f1 }, { 0x0d, 0x0221401f }, { 0x0e, 0x01014010 }, { 0x0f, 0x01813020 }, { 0x10, 0x01a19021 }, { 0x11, 0x90100140 }, { 0x12, 0x400001f2 }, {} }; /* STAC 9200-32 pin configs for 102801B5 (Dell Inspiron 630m) 102801D8 (Dell Inspiron 640m) */ static const struct hda_pintbl dell9200_m21_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x03441340 }, { 0x0d, 0x0321121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x408003fb }, { 0x10, 0x03a11020 }, { 0x11, 0x401003fc }, { 0x12, 0x403003fd }, {} }; /* STAC 9200-32 pin configs for 102801C2 (Dell Latitude D620) 102801C8 102801CC (Dell Latitude D820) 102801D4 102801D6 */ static const struct hda_pintbl dell9200_m22_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x0144131f }, { 0x0d, 0x0321121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x90a70321 }, { 0x10, 0x03a11020 }, { 0x11, 0x401003fb }, { 0x12, 0x40f000fc }, {} }; /* STAC 9200-32 pin configs for 102801CE (Dell XPS M1710) 102801CF (Dell Precision M90) */ static const struct hda_pintbl dell9200_m23_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x01441340 }, { 0x0d, 0x0421421f }, { 0x0e, 0x90170310 }, { 0x0f, 0x408003fb }, { 0x10, 0x04a1102e }, { 0x11, 0x90170311 }, { 0x12, 0x403003fc }, {} }; /* STAC 9200-32 pin configs for 102801C9 102801CA 102801CB (Dell Latitude 120L) 102801D3 */ static const struct hda_pintbl dell9200_m24_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x404003fb }, { 0x0d, 0x0321121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x408003fc }, { 0x10, 0x03a11020 }, { 0x11, 0x401003fd }, { 0x12, 0x403003fe }, {} }; /* STAC 9200-32 pin configs for 102801BD (Dell Inspiron E1505n) 102801EE 102801EF */ static const struct hda_pintbl dell9200_m25_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x01441340 }, { 0x0d, 0x0421121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x408003fb }, { 0x10, 0x04a11020 }, { 0x11, 0x401003fc }, { 0x12, 0x403003fd }, {} }; /* STAC 9200-32 pin configs for 102801F5 (Dell Inspiron 1501) 102801F6 */ static const struct hda_pintbl dell9200_m26_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x404003fb }, { 0x0d, 0x0421121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x408003fc }, { 0x10, 0x04a11020 }, { 0x11, 0x401003fd }, { 0x12, 0x403003fe }, {} }; /* STAC 9200-32 102801CD (Dell Inspiron E1705/9400) */ static const struct hda_pintbl dell9200_m27_pin_configs[] = { { 0x08, 0x40c003fa }, { 0x09, 0x01441340 }, { 0x0d, 0x0421121f }, { 0x0e, 0x90170310 }, { 0x0f, 0x90170310 }, { 0x10, 0x04a11020 }, { 0x11, 0x90170310 }, { 0x12, 0x40f003fc }, {} }; static const struct hda_pintbl oqo9200_pin_configs[] = { { 0x08, 0x40c000f0 }, { 0x09, 0x404000f1 }, { 0x0d, 0x0221121f }, { 0x0e, 0x02211210 }, { 0x0f, 0x90170111 }, { 0x10, 0x90a70120 }, { 0x11, 0x400000f2 }, { 0x12, 0x400000f3 }, {} }; /* * STAC 92HD700 * 18881000 Amigaone X1000 */ static const struct hda_pintbl nemo_pin_configs[] = { { 0x0a, 0x02214020 }, /* Front panel HP socket */ { 0x0b, 0x02a19080 }, /* Front Mic */ { 0x0c, 0x0181304e }, /* Line in */ { 0x0d, 0x01014010 }, /* Line out */ { 0x0e, 0x01a19040 }, /* Rear Mic */ { 0x0f, 0x01011012 }, /* Rear speakers */ { 0x10, 0x01016011 }, /* Center speaker */ { 0x11, 0x01012014 }, /* Side speakers (7.1) */ { 0x12, 0x103301f0 }, /* Motherboard CD line in connector */ { 0x13, 0x411111f0 }, /* Unused */ { 0x14, 0x411111f0 }, /* Unused */ { 0x21, 0x01442170 }, /* S/PDIF line out */ { 0x22, 0x411111f0 }, /* Unused */ { 0x23, 0x411111f0 }, /* Unused */ {} }; static void stac9200_fixup_panasonic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { spec->gpio_mask = spec->gpio_dir = 0x09; spec->gpio_data = 0x00; /* CF-74 has no headphone detection, and the driver should *NOT* * do detection and HP/speaker toggle because the hardware does it. */ spec->gen.suppress_auto_mute = 1; } } static const struct hda_fixup stac9200_fixups[] = { [STAC_REF] = { .type = HDA_FIXUP_PINS, .v.pins = ref9200_pin_configs, }, [STAC_9200_OQO] = { .type = HDA_FIXUP_PINS, .v.pins = oqo9200_pin_configs, .chained = true, .chain_id = STAC_9200_EAPD_INIT, }, [STAC_9200_DELL_D21] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_d21_pin_configs, }, [STAC_9200_DELL_D22] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_d22_pin_configs, }, [STAC_9200_DELL_D23] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_d23_pin_configs, }, [STAC_9200_DELL_M21] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m21_pin_configs, }, [STAC_9200_DELL_M22] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m22_pin_configs, }, [STAC_9200_DELL_M23] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m23_pin_configs, }, [STAC_9200_DELL_M24] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m24_pin_configs, }, [STAC_9200_DELL_M25] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m25_pin_configs, }, [STAC_9200_DELL_M26] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m26_pin_configs, }, [STAC_9200_DELL_M27] = { .type = HDA_FIXUP_PINS, .v.pins = dell9200_m27_pin_configs, }, [STAC_9200_M4] = { .type = HDA_FIXUP_PINS, .v.pins = gateway9200_m4_pin_configs, .chained = true, .chain_id = STAC_9200_EAPD_INIT, }, [STAC_9200_M4_2] = { .type = HDA_FIXUP_PINS, .v.pins = gateway9200_m4_2_pin_configs, .chained = true, .chain_id = STAC_9200_EAPD_INIT, }, [STAC_9200_PANASONIC] = { .type = HDA_FIXUP_FUNC, .v.func = stac9200_fixup_panasonic, }, [STAC_9200_EAPD_INIT] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { {0x08, AC_VERB_SET_EAPD_BTLENABLE, 0x02}, {} }, }, }; static const struct hda_model_fixup stac9200_models[] = { { .id = STAC_REF, .name = "ref" }, { .id = STAC_9200_OQO, .name = "oqo" }, { .id = STAC_9200_DELL_D21, .name = "dell-d21" }, { .id = STAC_9200_DELL_D22, .name = "dell-d22" }, { .id = STAC_9200_DELL_D23, .name = "dell-d23" }, { .id = STAC_9200_DELL_M21, .name = "dell-m21" }, { .id = STAC_9200_DELL_M22, .name = "dell-m22" }, { .id = STAC_9200_DELL_M23, .name = "dell-m23" }, { .id = STAC_9200_DELL_M24, .name = "dell-m24" }, { .id = STAC_9200_DELL_M25, .name = "dell-m25" }, { .id = STAC_9200_DELL_M26, .name = "dell-m26" }, { .id = STAC_9200_DELL_M27, .name = "dell-m27" }, { .id = STAC_9200_M4, .name = "gateway-m4" }, { .id = STAC_9200_M4_2, .name = "gateway-m4-2" }, { .id = STAC_9200_PANASONIC, .name = "panasonic" }, {} }; static const struct snd_pci_quirk stac9200_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_REF), /* Dell laptops have BIOS problem */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a8, "unknown Dell", STAC_9200_DELL_D21), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01b5, "Dell Inspiron 630m", STAC_9200_DELL_M21), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bd, "Dell Inspiron E1505n", STAC_9200_DELL_M25), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c0, "unknown Dell", STAC_9200_DELL_D22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c1, "unknown Dell", STAC_9200_DELL_D22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c2, "Dell Latitude D620", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c5, "unknown Dell", STAC_9200_DELL_D23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c7, "unknown Dell", STAC_9200_DELL_D23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c8, "unknown Dell", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c9, "unknown Dell", STAC_9200_DELL_M24), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ca, "unknown Dell", STAC_9200_DELL_M24), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cb, "Dell Latitude 120L", STAC_9200_DELL_M24), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cc, "Dell Latitude D820", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cd, "Dell Inspiron E1705/9400", STAC_9200_DELL_M27), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ce, "Dell XPS M1710", STAC_9200_DELL_M23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cf, "Dell Precision M90", STAC_9200_DELL_M23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d3, "unknown Dell", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d4, "unknown Dell", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d6, "unknown Dell", STAC_9200_DELL_M22), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d8, "Dell Inspiron 640m", STAC_9200_DELL_M21), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d9, "unknown Dell", STAC_9200_DELL_D23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01da, "unknown Dell", STAC_9200_DELL_D23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01de, "unknown Dell", STAC_9200_DELL_D21), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e3, "unknown Dell", STAC_9200_DELL_D23), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e8, "unknown Dell", STAC_9200_DELL_D21), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ee, "unknown Dell", STAC_9200_DELL_M25), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ef, "unknown Dell", STAC_9200_DELL_M25), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f5, "Dell Inspiron 1501", STAC_9200_DELL_M26), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f6, "unknown Dell", STAC_9200_DELL_M26), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0201, "Dell Latitude D430", STAC_9200_DELL_M22), /* Panasonic */ SND_PCI_QUIRK(0x10f7, 0x8338, "Panasonic CF-74", STAC_9200_PANASONIC), /* Gateway machines needs EAPD to be set on resume */ SND_PCI_QUIRK(0x107b, 0x0205, "Gateway S-7110M", STAC_9200_M4), SND_PCI_QUIRK(0x107b, 0x0317, "Gateway MT3423, MX341*", STAC_9200_M4_2), SND_PCI_QUIRK(0x107b, 0x0318, "Gateway ML3019, MT3707", STAC_9200_M4_2), /* OQO Mobile */ SND_PCI_QUIRK(0x1106, 0x3288, "OQO Model 2", STAC_9200_OQO), {} /* terminator */ }; static const struct hda_pintbl ref925x_pin_configs[] = { { 0x07, 0x40c003f0 }, { 0x08, 0x424503f2 }, { 0x0a, 0x01813022 }, { 0x0b, 0x02a19021 }, { 0x0c, 0x90a70320 }, { 0x0d, 0x02214210 }, { 0x10, 0x01019020 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM1_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM1_2_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM2_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM2_2_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM3_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x503303f3 }, {} }; static const struct hda_pintbl stac925xM5_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x9033032e }, {} }; static const struct hda_pintbl stac925xM6_pin_configs[] = { { 0x07, 0x40c003f4 }, { 0x08, 0x424503f2 }, { 0x0a, 0x400000f3 }, { 0x0b, 0x02a19020 }, { 0x0c, 0x40a000f0 }, { 0x0d, 0x90100210 }, { 0x10, 0x400003f1 }, { 0x11, 0x90330320 }, {} }; static const struct hda_fixup stac925x_fixups[] = { [STAC_REF] = { .type = HDA_FIXUP_PINS, .v.pins = ref925x_pin_configs, }, [STAC_M1] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM1_pin_configs, }, [STAC_M1_2] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM1_2_pin_configs, }, [STAC_M2] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM2_pin_configs, }, [STAC_M2_2] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM2_2_pin_configs, }, [STAC_M3] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM3_pin_configs, }, [STAC_M5] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM5_pin_configs, }, [STAC_M6] = { .type = HDA_FIXUP_PINS, .v.pins = stac925xM6_pin_configs, }, }; static const struct hda_model_fixup stac925x_models[] = { { .id = STAC_REF, .name = "ref" }, { .id = STAC_M1, .name = "m1" }, { .id = STAC_M1_2, .name = "m1-2" }, { .id = STAC_M2, .name = "m2" }, { .id = STAC_M2_2, .name = "m2-2" }, { .id = STAC_M3, .name = "m3" }, { .id = STAC_M5, .name = "m5" }, { .id = STAC_M6, .name = "m6" }, {} }; static const struct snd_pci_quirk stac925x_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_REF), SND_PCI_QUIRK(0x8384, 0x7632, "Stac9202 Reference Board", STAC_REF), /* Default table for unknown ID */ SND_PCI_QUIRK(0x1002, 0x437b, "Gateway mobile", STAC_M2_2), /* gateway machines are checked via codec ssid */ SND_PCI_QUIRK(0x107b, 0x0316, "Gateway M255", STAC_M2), SND_PCI_QUIRK(0x107b, 0x0366, "Gateway MP6954", STAC_M5), SND_PCI_QUIRK(0x107b, 0x0461, "Gateway NX560XL", STAC_M1), SND_PCI_QUIRK(0x107b, 0x0681, "Gateway NX860", STAC_M2), SND_PCI_QUIRK(0x107b, 0x0367, "Gateway MX6453", STAC_M1_2), /* Not sure about the brand name for those */ SND_PCI_QUIRK(0x107b, 0x0281, "Gateway mobile", STAC_M1), SND_PCI_QUIRK(0x107b, 0x0507, "Gateway mobile", STAC_M3), SND_PCI_QUIRK(0x107b, 0x0281, "Gateway mobile", STAC_M6), SND_PCI_QUIRK(0x107b, 0x0685, "Gateway mobile", STAC_M2_2), {} /* terminator */ }; static const struct hda_pintbl ref92hd73xx_pin_configs[] = { // Port A-H { 0x0a, 0x02214030 }, { 0x0b, 0x02a19040 }, { 0x0c, 0x01a19020 }, { 0x0d, 0x02214030 }, { 0x0e, 0x0181302e }, { 0x0f, 0x01014010 }, { 0x10, 0x01014020 }, { 0x11, 0x01014030 }, // CD in { 0x12, 0x02319040 }, // Digial Mic ins { 0x13, 0x90a000f0 }, { 0x14, 0x90a000f0 }, // Digital outs { 0x22, 0x01452050 }, { 0x23, 0x01452050 }, {} }; static const struct hda_pintbl dell_m6_pin_configs[] = { { 0x0a, 0x0321101f }, { 0x0b, 0x4f00000f }, { 0x0c, 0x4f0000f0 }, { 0x0d, 0x90170110 }, { 0x0e, 0x03a11020 }, { 0x0f, 0x0321101f }, { 0x10, 0x4f0000f0 }, { 0x11, 0x4f0000f0 }, { 0x12, 0x4f0000f0 }, { 0x13, 0x90a60160 }, { 0x14, 0x4f0000f0 }, { 0x22, 0x4f0000f0 }, { 0x23, 0x4f0000f0 }, {} }; static const struct hda_pintbl alienware_m17x_pin_configs[] = { { 0x0a, 0x0321101f }, { 0x0b, 0x0321101f }, { 0x0c, 0x03a11020 }, { 0x0d, 0x03014020 }, { 0x0e, 0x90170110 }, { 0x0f, 0x4f0000f0 }, { 0x10, 0x4f0000f0 }, { 0x11, 0x4f0000f0 }, { 0x12, 0x4f0000f0 }, { 0x13, 0x90a60160 }, { 0x14, 0x4f0000f0 }, { 0x22, 0x4f0000f0 }, { 0x23, 0x904601b0 }, {} }; static const struct hda_pintbl intel_dg45id_pin_configs[] = { // Analog outputs { 0x0a, 0x02214230 }, { 0x0b, 0x02A19240 }, { 0x0c, 0x01013214 }, { 0x0d, 0x01014210 }, { 0x0e, 0x01A19250 }, { 0x0f, 0x01011212 }, { 0x10, 0x01016211 }, // Digital output { 0x22, 0x01451380 }, { 0x23, 0x40f000f0 }, {} }; static const struct hda_pintbl stac92hd89xx_hp_front_jack_pin_configs[] = { { 0x0a, 0x02214030 }, { 0x0b, 0x02A19010 }, {} }; static const struct hda_pintbl stac92hd89xx_hp_z1_g2_right_mic_jack_pin_configs[] = { { 0x0e, 0x400000f0 }, {} }; static void stac92hd73xx_fixup_ref(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; snd_hda_apply_pincfgs(codec, ref92hd73xx_pin_configs); spec->gpio_mask = spec->gpio_dir = spec->gpio_data = 0; } static void stac92hd73xx_fixup_dell(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; snd_hda_apply_pincfgs(codec, dell_m6_pin_configs); spec->eapd_switch = 0; } static void stac92hd73xx_fixup_dell_eq(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; stac92hd73xx_fixup_dell(codec); snd_hda_add_verbs(codec, dell_eq_core_init); spec->volknob_init = 1; } /* Analog Mics */ static void stac92hd73xx_fixup_dell_m6_amic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; stac92hd73xx_fixup_dell(codec); snd_hda_codec_set_pincfg(codec, 0x0b, 0x90A70170); } /* Digital Mics */ static void stac92hd73xx_fixup_dell_m6_dmic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; stac92hd73xx_fixup_dell(codec); snd_hda_codec_set_pincfg(codec, 0x13, 0x90A60160); } /* Both */ static void stac92hd73xx_fixup_dell_m6_both(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; stac92hd73xx_fixup_dell(codec); snd_hda_codec_set_pincfg(codec, 0x0b, 0x90A70170); snd_hda_codec_set_pincfg(codec, 0x13, 0x90A60160); } static void stac92hd73xx_fixup_alienware_m17x(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; snd_hda_apply_pincfgs(codec, alienware_m17x_pin_configs); spec->eapd_switch = 0; } static void stac92hd73xx_fixup_no_jd(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action == HDA_FIXUP_ACT_PRE_PROBE) codec->no_jack_detect = 1; } static void stac92hd73xx_disable_automute(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; spec->gen.suppress_auto_mute = 1; } static const struct hda_fixup stac92hd73xx_fixups[] = { [STAC_92HD73XX_REF] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_ref, }, [STAC_DELL_M6_AMIC] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_dell_m6_amic, }, [STAC_DELL_M6_DMIC] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_dell_m6_dmic, }, [STAC_DELL_M6_BOTH] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_dell_m6_both, }, [STAC_DELL_EQ] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_dell_eq, }, [STAC_ALIENWARE_M17X] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_alienware_m17x, }, [STAC_ELO_VUPOINT_15MX] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_disable_automute, }, [STAC_92HD73XX_INTEL] = { .type = HDA_FIXUP_PINS, .v.pins = intel_dg45id_pin_configs, }, [STAC_92HD73XX_NO_JD] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd73xx_fixup_no_jd, }, [STAC_92HD89XX_HP_FRONT_JACK] = { .type = HDA_FIXUP_PINS, .v.pins = stac92hd89xx_hp_front_jack_pin_configs, }, [STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK] = { .type = HDA_FIXUP_PINS, .v.pins = stac92hd89xx_hp_z1_g2_right_mic_jack_pin_configs, }, [STAC_92HD73XX_ASUS_MOBO] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* enable 5.1 and SPDIF out */ { 0x0c, 0x01014411 }, { 0x0d, 0x01014410 }, { 0x0e, 0x01014412 }, { 0x22, 0x014b1180 }, { } } }, }; static const struct hda_model_fixup stac92hd73xx_models[] = { { .id = STAC_92HD73XX_NO_JD, .name = "no-jd" }, { .id = STAC_92HD73XX_REF, .name = "ref" }, { .id = STAC_92HD73XX_INTEL, .name = "intel" }, { .id = STAC_DELL_M6_AMIC, .name = "dell-m6-amic" }, { .id = STAC_DELL_M6_DMIC, .name = "dell-m6-dmic" }, { .id = STAC_DELL_M6_BOTH, .name = "dell-m6" }, { .id = STAC_DELL_EQ, .name = "dell-eq" }, { .id = STAC_ALIENWARE_M17X, .name = "alienware" }, { .id = STAC_ELO_VUPOINT_15MX, .name = "elo-vupoint-15mx" }, { .id = STAC_92HD73XX_ASUS_MOBO, .name = "asus-mobo" }, {} }; static const struct snd_pci_quirk stac92hd73xx_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_92HD73XX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_92HD73XX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5001, "Intel DP45SG", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5002, "Intel DG45ID", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5003, "Intel DG45FC", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0254, "Dell Studio 1535", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0255, "unknown Dell", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0256, "unknown Dell", STAC_DELL_M6_BOTH), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0257, "unknown Dell", STAC_DELL_M6_BOTH), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x025e, "unknown Dell", STAC_DELL_M6_AMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x025f, "unknown Dell", STAC_DELL_M6_AMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0271, "unknown Dell", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0272, "unknown Dell", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x029f, "Dell Studio 1537", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02a0, "Dell Studio 17", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02be, "Dell Studio 1555", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02bd, "Dell Studio 1557", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02fe, "Dell Studio XPS 1645", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0413, "Dell Studio 1558", STAC_DELL_M6_DMIC), /* codec SSID matching */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02a1, "Alienware M17x", STAC_ALIENWARE_M17X), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x043a, "Alienware M17x", STAC_ALIENWARE_M17X), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0490, "Alienware M17x R3", STAC_DELL_EQ), SND_PCI_QUIRK(0x1059, 0x1011, "ELO VuPoint 15MX", STAC_ELO_VUPOINT_15MX), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1927, "HP Z1 G2", STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2b17, "unknown HP", STAC_92HD89XX_HP_FRONT_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_ASUSTEK, 0x83f8, "ASUS AT4NM10", STAC_92HD73XX_ASUS_MOBO), {} /* terminator */ }; static const struct hda_pintbl ref92hd83xxx_pin_configs[] = { { 0x0a, 0x02214030 }, { 0x0b, 0x02211010 }, { 0x0c, 0x02a19020 }, { 0x0d, 0x02170130 }, { 0x0e, 0x01014050 }, { 0x0f, 0x01819040 }, { 0x10, 0x01014020 }, { 0x11, 0x90a3014e }, { 0x1f, 0x01451160 }, { 0x20, 0x98560170 }, {} }; static const struct hda_pintbl dell_s14_pin_configs[] = { { 0x0a, 0x0221403f }, { 0x0b, 0x0221101f }, { 0x0c, 0x02a19020 }, { 0x0d, 0x90170110 }, { 0x0e, 0x40f000f0 }, { 0x0f, 0x40f000f0 }, { 0x10, 0x40f000f0 }, { 0x11, 0x90a60160 }, { 0x1f, 0x40f000f0 }, { 0x20, 0x40f000f0 }, {} }; static const struct hda_pintbl dell_vostro_3500_pin_configs[] = { { 0x0a, 0x02a11020 }, { 0x0b, 0x0221101f }, { 0x0c, 0x400000f0 }, { 0x0d, 0x90170110 }, { 0x0e, 0x400000f1 }, { 0x0f, 0x400000f2 }, { 0x10, 0x400000f3 }, { 0x11, 0x90a60160 }, { 0x1f, 0x400000f4 }, { 0x20, 0x400000f5 }, {} }; static const struct hda_pintbl hp_dv7_4000_pin_configs[] = { { 0x0a, 0x03a12050 }, { 0x0b, 0x0321201f }, { 0x0c, 0x40f000f0 }, { 0x0d, 0x90170110 }, { 0x0e, 0x40f000f0 }, { 0x0f, 0x40f000f0 }, { 0x10, 0x90170110 }, { 0x11, 0xd5a30140 }, { 0x1f, 0x40f000f0 }, { 0x20, 0x40f000f0 }, {} }; static const struct hda_pintbl hp_zephyr_pin_configs[] = { { 0x0a, 0x01813050 }, { 0x0b, 0x0421201f }, { 0x0c, 0x04a1205e }, { 0x0d, 0x96130310 }, { 0x0e, 0x96130310 }, { 0x0f, 0x0101401f }, { 0x10, 0x1111611f }, { 0x11, 0xd5a30130 }, {} }; static const struct hda_pintbl hp_cNB11_intquad_pin_configs[] = { { 0x0a, 0x40f000f0 }, { 0x0b, 0x0221101f }, { 0x0c, 0x02a11020 }, { 0x0d, 0x92170110 }, { 0x0e, 0x40f000f0 }, { 0x0f, 0x92170110 }, { 0x10, 0x40f000f0 }, { 0x11, 0xd5a30130 }, { 0x1f, 0x40f000f0 }, { 0x20, 0x40f000f0 }, {} }; static void stac92hd83xxx_fixup_hp(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; if (hp_bnb2011_with_dock(codec)) { snd_hda_codec_set_pincfg(codec, 0xa, 0x2101201f); snd_hda_codec_set_pincfg(codec, 0xf, 0x2181205e); } if (find_mute_led_cfg(codec, spec->default_polarity)) codec_dbg(codec, "mute LED gpio %d polarity %d\n", spec->gpio_led, spec->gpio_led_polarity); /* allow auto-switching of dock line-in */ spec->gen.line_in_auto_switch = true; } static void stac92hd83xxx_fixup_hp_zephyr(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; snd_hda_apply_pincfgs(codec, hp_zephyr_pin_configs); snd_hda_add_verbs(codec, stac92hd83xxx_hp_zephyr_init); } static void stac92hd83xxx_fixup_hp_led(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) spec->default_polarity = 0; } static void stac92hd83xxx_fixup_hp_inv_led(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) spec->default_polarity = 1; } static void stac92hd83xxx_fixup_hp_mic_led(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { spec->mic_mute_led_gpio = 0x08; /* GPIO3 */ #ifdef CONFIG_PM /* resetting controller clears GPIO, so we need to keep on */ codec->core.power_caps &= ~AC_PWRST_CLKSTOP; #endif } } static void stac92hd83xxx_fixup_hp_led_gpio10(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { spec->gpio_led = 0x10; /* GPIO4 */ spec->default_polarity = 0; } } static void stac92hd83xxx_fixup_headset_jack(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) spec->headset_jack = 1; } static void stac92hd83xxx_fixup_gpio10_eapd(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = spec->gpio_data = 0x10; spec->eapd_switch = 0; } static void hp_envy_ts_fixup_dac_bind(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; static const hda_nid_t preferred_pairs[] = { 0xd, 0x13, 0 }; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; spec->gen.preferred_dacs = preferred_pairs; } static const struct hda_verb hp_bnb13_eq_verbs[] = { /* 44.1KHz base */ { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x68 }, { 0x22, 0x7A8, 0x17 }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x68 }, { 0x22, 0x7AB, 0x17 }, { 0x22, 0x7AC, 0x00 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x83 }, { 0x22, 0x7A7, 0x2F }, { 0x22, 0x7A8, 0xD1 }, { 0x22, 0x7A9, 0x83 }, { 0x22, 0x7AA, 0x2F }, { 0x22, 0x7AB, 0xD1 }, { 0x22, 0x7AC, 0x01 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x68 }, { 0x22, 0x7A8, 0x17 }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x68 }, { 0x22, 0x7AB, 0x17 }, { 0x22, 0x7AC, 0x02 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x7C }, { 0x22, 0x7A7, 0xC6 }, { 0x22, 0x7A8, 0x0C }, { 0x22, 0x7A9, 0x7C }, { 0x22, 0x7AA, 0xC6 }, { 0x22, 0x7AB, 0x0C }, { 0x22, 0x7AC, 0x03 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC3 }, { 0x22, 0x7A7, 0x25 }, { 0x22, 0x7A8, 0xAF }, { 0x22, 0x7A9, 0xC3 }, { 0x22, 0x7AA, 0x25 }, { 0x22, 0x7AB, 0xAF }, { 0x22, 0x7AC, 0x04 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x85 }, { 0x22, 0x7A8, 0x73 }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x85 }, { 0x22, 0x7AB, 0x73 }, { 0x22, 0x7AC, 0x05 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x85 }, { 0x22, 0x7A7, 0x39 }, { 0x22, 0x7A8, 0xC7 }, { 0x22, 0x7A9, 0x85 }, { 0x22, 0x7AA, 0x39 }, { 0x22, 0x7AB, 0xC7 }, { 0x22, 0x7AC, 0x06 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3C }, { 0x22, 0x7A7, 0x90 }, { 0x22, 0x7A8, 0xB0 }, { 0x22, 0x7A9, 0x3C }, { 0x22, 0x7AA, 0x90 }, { 0x22, 0x7AB, 0xB0 }, { 0x22, 0x7AC, 0x07 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x7A }, { 0x22, 0x7A7, 0xC6 }, { 0x22, 0x7A8, 0x39 }, { 0x22, 0x7A9, 0x7A }, { 0x22, 0x7AA, 0xC6 }, { 0x22, 0x7AB, 0x39 }, { 0x22, 0x7AC, 0x08 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC4 }, { 0x22, 0x7A7, 0xE9 }, { 0x22, 0x7A8, 0xDC }, { 0x22, 0x7A9, 0xC4 }, { 0x22, 0x7AA, 0xE9 }, { 0x22, 0x7AB, 0xDC }, { 0x22, 0x7AC, 0x09 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3D }, { 0x22, 0x7A7, 0xE1 }, { 0x22, 0x7A8, 0x0D }, { 0x22, 0x7A9, 0x3D }, { 0x22, 0x7AA, 0xE1 }, { 0x22, 0x7AB, 0x0D }, { 0x22, 0x7AC, 0x0A }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x89 }, { 0x22, 0x7A7, 0xB6 }, { 0x22, 0x7A8, 0xEB }, { 0x22, 0x7A9, 0x89 }, { 0x22, 0x7AA, 0xB6 }, { 0x22, 0x7AB, 0xEB }, { 0x22, 0x7AC, 0x0B }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x39 }, { 0x22, 0x7A7, 0x9D }, { 0x22, 0x7A8, 0xFE }, { 0x22, 0x7A9, 0x39 }, { 0x22, 0x7AA, 0x9D }, { 0x22, 0x7AB, 0xFE }, { 0x22, 0x7AC, 0x0C }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x76 }, { 0x22, 0x7A7, 0x49 }, { 0x22, 0x7A8, 0x15 }, { 0x22, 0x7A9, 0x76 }, { 0x22, 0x7AA, 0x49 }, { 0x22, 0x7AB, 0x15 }, { 0x22, 0x7AC, 0x0D }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC8 }, { 0x22, 0x7A7, 0x80 }, { 0x22, 0x7A8, 0xF5 }, { 0x22, 0x7A9, 0xC8 }, { 0x22, 0x7AA, 0x80 }, { 0x22, 0x7AB, 0xF5 }, { 0x22, 0x7AC, 0x0E }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x0F }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x90 }, { 0x22, 0x7A7, 0x68 }, { 0x22, 0x7A8, 0xF1 }, { 0x22, 0x7A9, 0x90 }, { 0x22, 0x7AA, 0x68 }, { 0x22, 0x7AB, 0xF1 }, { 0x22, 0x7AC, 0x10 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x34 }, { 0x22, 0x7A7, 0x47 }, { 0x22, 0x7A8, 0x6C }, { 0x22, 0x7A9, 0x34 }, { 0x22, 0x7AA, 0x47 }, { 0x22, 0x7AB, 0x6C }, { 0x22, 0x7AC, 0x11 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x6F }, { 0x22, 0x7A7, 0x97 }, { 0x22, 0x7A8, 0x0F }, { 0x22, 0x7A9, 0x6F }, { 0x22, 0x7AA, 0x97 }, { 0x22, 0x7AB, 0x0F }, { 0x22, 0x7AC, 0x12 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xCB }, { 0x22, 0x7A7, 0xB8 }, { 0x22, 0x7A8, 0x94 }, { 0x22, 0x7A9, 0xCB }, { 0x22, 0x7AA, 0xB8 }, { 0x22, 0x7AB, 0x94 }, { 0x22, 0x7AC, 0x13 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x14 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x95 }, { 0x22, 0x7A7, 0x76 }, { 0x22, 0x7A8, 0x5B }, { 0x22, 0x7A9, 0x95 }, { 0x22, 0x7AA, 0x76 }, { 0x22, 0x7AB, 0x5B }, { 0x22, 0x7AC, 0x15 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x31 }, { 0x22, 0x7A7, 0xAC }, { 0x22, 0x7A8, 0x31 }, { 0x22, 0x7A9, 0x31 }, { 0x22, 0x7AA, 0xAC }, { 0x22, 0x7AB, 0x31 }, { 0x22, 0x7AC, 0x16 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x6A }, { 0x22, 0x7A7, 0x89 }, { 0x22, 0x7A8, 0xA5 }, { 0x22, 0x7A9, 0x6A }, { 0x22, 0x7AA, 0x89 }, { 0x22, 0x7AB, 0xA5 }, { 0x22, 0x7AC, 0x17 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xCE }, { 0x22, 0x7A7, 0x53 }, { 0x22, 0x7A8, 0xCF }, { 0x22, 0x7A9, 0xCE }, { 0x22, 0x7AA, 0x53 }, { 0x22, 0x7AB, 0xCF }, { 0x22, 0x7AC, 0x18 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x19 }, { 0x22, 0x7AD, 0x80 }, /* 48KHz base */ { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x88 }, { 0x22, 0x7A8, 0xDC }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x88 }, { 0x22, 0x7AB, 0xDC }, { 0x22, 0x7AC, 0x1A }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x82 }, { 0x22, 0x7A7, 0xEE }, { 0x22, 0x7A8, 0x46 }, { 0x22, 0x7A9, 0x82 }, { 0x22, 0x7AA, 0xEE }, { 0x22, 0x7AB, 0x46 }, { 0x22, 0x7AC, 0x1B }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x88 }, { 0x22, 0x7A8, 0xDC }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x88 }, { 0x22, 0x7AB, 0xDC }, { 0x22, 0x7AC, 0x1C }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x7D }, { 0x22, 0x7A7, 0x09 }, { 0x22, 0x7A8, 0x28 }, { 0x22, 0x7A9, 0x7D }, { 0x22, 0x7AA, 0x09 }, { 0x22, 0x7AB, 0x28 }, { 0x22, 0x7AC, 0x1D }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC2 }, { 0x22, 0x7A7, 0xE5 }, { 0x22, 0x7A8, 0xB4 }, { 0x22, 0x7A9, 0xC2 }, { 0x22, 0x7AA, 0xE5 }, { 0x22, 0x7AB, 0xB4 }, { 0x22, 0x7AC, 0x1E }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0xA3 }, { 0x22, 0x7A8, 0x1F }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0xA3 }, { 0x22, 0x7AB, 0x1F }, { 0x22, 0x7AC, 0x1F }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x84 }, { 0x22, 0x7A7, 0xCA }, { 0x22, 0x7A8, 0xF1 }, { 0x22, 0x7A9, 0x84 }, { 0x22, 0x7AA, 0xCA }, { 0x22, 0x7AB, 0xF1 }, { 0x22, 0x7AC, 0x20 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3C }, { 0x22, 0x7A7, 0xD5 }, { 0x22, 0x7A8, 0x9C }, { 0x22, 0x7A9, 0x3C }, { 0x22, 0x7AA, 0xD5 }, { 0x22, 0x7AB, 0x9C }, { 0x22, 0x7AC, 0x21 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x7B }, { 0x22, 0x7A7, 0x35 }, { 0x22, 0x7A8, 0x0F }, { 0x22, 0x7A9, 0x7B }, { 0x22, 0x7AA, 0x35 }, { 0x22, 0x7AB, 0x0F }, { 0x22, 0x7AC, 0x22 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC4 }, { 0x22, 0x7A7, 0x87 }, { 0x22, 0x7A8, 0x45 }, { 0x22, 0x7A9, 0xC4 }, { 0x22, 0x7AA, 0x87 }, { 0x22, 0x7AB, 0x45 }, { 0x22, 0x7AC, 0x23 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3E }, { 0x22, 0x7A7, 0x0A }, { 0x22, 0x7A8, 0x78 }, { 0x22, 0x7A9, 0x3E }, { 0x22, 0x7AA, 0x0A }, { 0x22, 0x7AB, 0x78 }, { 0x22, 0x7AC, 0x24 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x88 }, { 0x22, 0x7A7, 0xE2 }, { 0x22, 0x7A8, 0x05 }, { 0x22, 0x7A9, 0x88 }, { 0x22, 0x7AA, 0xE2 }, { 0x22, 0x7AB, 0x05 }, { 0x22, 0x7AC, 0x25 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x3A }, { 0x22, 0x7A7, 0x1A }, { 0x22, 0x7A8, 0xA3 }, { 0x22, 0x7A9, 0x3A }, { 0x22, 0x7AA, 0x1A }, { 0x22, 0x7AB, 0xA3 }, { 0x22, 0x7AC, 0x26 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x77 }, { 0x22, 0x7A7, 0x1D }, { 0x22, 0x7A8, 0xFB }, { 0x22, 0x7A9, 0x77 }, { 0x22, 0x7AA, 0x1D }, { 0x22, 0x7AB, 0xFB }, { 0x22, 0x7AC, 0x27 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xC7 }, { 0x22, 0x7A7, 0xDA }, { 0x22, 0x7A8, 0xE5 }, { 0x22, 0x7A9, 0xC7 }, { 0x22, 0x7AA, 0xDA }, { 0x22, 0x7AB, 0xE5 }, { 0x22, 0x7AC, 0x28 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x29 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x8E }, { 0x22, 0x7A7, 0xD7 }, { 0x22, 0x7A8, 0x22 }, { 0x22, 0x7A9, 0x8E }, { 0x22, 0x7AA, 0xD7 }, { 0x22, 0x7AB, 0x22 }, { 0x22, 0x7AC, 0x2A }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x35 }, { 0x22, 0x7A7, 0x26 }, { 0x22, 0x7A8, 0xC6 }, { 0x22, 0x7A9, 0x35 }, { 0x22, 0x7AA, 0x26 }, { 0x22, 0x7AB, 0xC6 }, { 0x22, 0x7AC, 0x2B }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x71 }, { 0x22, 0x7A7, 0x28 }, { 0x22, 0x7A8, 0xDE }, { 0x22, 0x7A9, 0x71 }, { 0x22, 0x7AA, 0x28 }, { 0x22, 0x7AB, 0xDE }, { 0x22, 0x7AC, 0x2C }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xCA }, { 0x22, 0x7A7, 0xD9 }, { 0x22, 0x7A8, 0x3A }, { 0x22, 0x7A9, 0xCA }, { 0x22, 0x7AA, 0xD9 }, { 0x22, 0x7AB, 0x3A }, { 0x22, 0x7AC, 0x2D }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x2E }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x93 }, { 0x22, 0x7A7, 0x5E }, { 0x22, 0x7A8, 0xD8 }, { 0x22, 0x7A9, 0x93 }, { 0x22, 0x7AA, 0x5E }, { 0x22, 0x7AB, 0xD8 }, { 0x22, 0x7AC, 0x2F }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x32 }, { 0x22, 0x7A7, 0xB7 }, { 0x22, 0x7A8, 0xB1 }, { 0x22, 0x7A9, 0x32 }, { 0x22, 0x7AA, 0xB7 }, { 0x22, 0x7AB, 0xB1 }, { 0x22, 0x7AC, 0x30 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x6C }, { 0x22, 0x7A7, 0xA1 }, { 0x22, 0x7A8, 0x28 }, { 0x22, 0x7A9, 0x6C }, { 0x22, 0x7AA, 0xA1 }, { 0x22, 0x7AB, 0x28 }, { 0x22, 0x7AC, 0x31 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0xCD }, { 0x22, 0x7A7, 0x48 }, { 0x22, 0x7A8, 0x4F }, { 0x22, 0x7A9, 0xCD }, { 0x22, 0x7AA, 0x48 }, { 0x22, 0x7AB, 0x4F }, { 0x22, 0x7AC, 0x32 }, { 0x22, 0x7AD, 0x80 }, { 0x22, 0x7A6, 0x40 }, { 0x22, 0x7A7, 0x00 }, { 0x22, 0x7A8, 0x00 }, { 0x22, 0x7A9, 0x40 }, { 0x22, 0x7AA, 0x00 }, { 0x22, 0x7AB, 0x00 }, { 0x22, 0x7AC, 0x33 }, { 0x22, 0x7AD, 0x80 }, /* common */ { 0x22, 0x782, 0xC1 }, { 0x22, 0x771, 0x2C }, { 0x22, 0x772, 0x2C }, { 0x22, 0x788, 0x04 }, { 0x01, 0x7B0, 0x08 }, {} }; static const struct hda_fixup stac92hd83xxx_fixups[] = { [STAC_92HD83XXX_REF] = { .type = HDA_FIXUP_PINS, .v.pins = ref92hd83xxx_pin_configs, }, [STAC_92HD83XXX_PWR_REF] = { .type = HDA_FIXUP_PINS, .v.pins = ref92hd83xxx_pin_configs, }, [STAC_DELL_S14] = { .type = HDA_FIXUP_PINS, .v.pins = dell_s14_pin_configs, }, [STAC_DELL_VOSTRO_3500] = { .type = HDA_FIXUP_PINS, .v.pins = dell_vostro_3500_pin_configs, }, [STAC_92HD83XXX_HP_cNB11_INTQUAD] = { .type = HDA_FIXUP_PINS, .v.pins = hp_cNB11_intquad_pin_configs, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_92HD83XXX_HP] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp, }, [STAC_HP_DV7_4000] = { .type = HDA_FIXUP_PINS, .v.pins = hp_dv7_4000_pin_configs, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_HP_ZEPHYR] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp_zephyr, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_92HD83XXX_HP_LED] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp_led, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_92HD83XXX_HP_INV_LED] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp_inv_led, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_92HD83XXX_HP_MIC_LED] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp_mic_led, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_HP_LED_GPIO10] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_hp_led_gpio10, .chained = true, .chain_id = STAC_92HD83XXX_HP, }, [STAC_92HD83XXX_HEADSET_JACK] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_headset_jack, }, [STAC_HP_ENVY_BASS] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x0f, 0x90170111 }, {} }, }, [STAC_HP_BNB13_EQ] = { .type = HDA_FIXUP_VERBS, .v.verbs = hp_bnb13_eq_verbs, .chained = true, .chain_id = STAC_92HD83XXX_HP_MIC_LED, }, [STAC_HP_ENVY_TS_BASS] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { { 0x10, 0x92170111 }, {} }, }, [STAC_HP_ENVY_TS_DAC_BIND] = { .type = HDA_FIXUP_FUNC, .v.func = hp_envy_ts_fixup_dac_bind, .chained = true, .chain_id = STAC_HP_ENVY_TS_BASS, }, [STAC_92HD83XXX_GPIO10_EAPD] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd83xxx_fixup_gpio10_eapd, }, }; static const struct hda_model_fixup stac92hd83xxx_models[] = { { .id = STAC_92HD83XXX_REF, .name = "ref" }, { .id = STAC_92HD83XXX_PWR_REF, .name = "mic-ref" }, { .id = STAC_DELL_S14, .name = "dell-s14" }, { .id = STAC_DELL_VOSTRO_3500, .name = "dell-vostro-3500" }, { .id = STAC_92HD83XXX_HP_cNB11_INTQUAD, .name = "hp_cNB11_intquad" }, { .id = STAC_HP_DV7_4000, .name = "hp-dv7-4000" }, { .id = STAC_HP_ZEPHYR, .name = "hp-zephyr" }, { .id = STAC_92HD83XXX_HP_LED, .name = "hp-led" }, { .id = STAC_92HD83XXX_HP_INV_LED, .name = "hp-inv-led" }, { .id = STAC_92HD83XXX_HP_MIC_LED, .name = "hp-mic-led" }, { .id = STAC_92HD83XXX_HEADSET_JACK, .name = "headset-jack" }, { .id = STAC_HP_ENVY_BASS, .name = "hp-envy-bass" }, { .id = STAC_HP_BNB13_EQ, .name = "hp-bnb13-eq" }, { .id = STAC_HP_ENVY_TS_BASS, .name = "hp-envy-ts-bass" }, {} }; static const struct snd_pci_quirk stac92hd83xxx_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_92HD83XXX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_92HD83XXX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ba, "unknown Dell", STAC_DELL_S14), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0532, "Dell Latitude E6230", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0533, "Dell Latitude E6330", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0534, "Dell Latitude E6430", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0535, "Dell Latitude E6530", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x053c, "Dell Latitude E5430", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x053d, "Dell Latitude E5530", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0549, "Dell Latitude E5430", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x057d, "Dell Latitude E6430s", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0584, "Dell Latitude E6430U", STAC_92HD83XXX_HEADSET_JACK), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x1028, "Dell Vostro 3500", STAC_DELL_VOSTRO_3500), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1656, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1657, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1658, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1659, "HP Pavilion dv7", STAC_HP_DV7_4000), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x165A, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x165B, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1888, "HP Envy Spectre", STAC_HP_ENVY_BASS), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1899, "HP Folio 13", STAC_HP_LED_GPIO10), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x18df, "HP Folio", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x18F8, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1909, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x190A, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x190e, "HP ENVY TS", STAC_HP_ENVY_TS_BASS), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1967, "HP ENVY TS", STAC_HP_ENVY_TS_DAC_BIND), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1940, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1941, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1942, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1943, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1944, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1945, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1946, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1948, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1949, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x194A, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x194B, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x194C, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x194E, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x194F, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1950, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1951, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x195A, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x195B, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x195C, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1991, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2103, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2104, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2105, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2106, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2107, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2108, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2109, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x210A, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x210B, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x211C, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x211D, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x211E, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x211F, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2120, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2121, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2122, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2123, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x213E, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x213F, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2140, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x21B2, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x21B3, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x21B5, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x21B6, "HP bNB13", STAC_HP_BNB13_EQ), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xff00, 0x1900, "HP", STAC_92HD83XXX_HP_MIC_LED), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xff00, 0x2000, "HP", STAC_92HD83XXX_HP_MIC_LED), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xff00, 0x2100, "HP", STAC_92HD83XXX_HP_MIC_LED), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3388, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3389, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x355B, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x355C, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x355D, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x355E, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x355F, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3560, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x358B, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x358C, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x358D, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3591, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3592, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3593, "HP", STAC_92HD83XXX_HP_cNB11_INTQUAD), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3561, "HP", STAC_HP_ZEPHYR), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3660, "HP Mini", STAC_92HD83XXX_HP_LED), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x144E, "HP Pavilion dv5", STAC_92HD83XXX_HP_INV_LED), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x148a, "HP Mini", STAC_92HD83XXX_HP_LED), SND_PCI_QUIRK_VENDOR(PCI_VENDOR_ID_HP, "HP", STAC_92HD83XXX_HP), /* match both for 0xfa91 and 0xfa93 */ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_TOSHIBA, 0xfffd, 0xfa91, "Toshiba Satellite S50D", STAC_92HD83XXX_GPIO10_EAPD), {} /* terminator */ }; /* HP dv7 bass switch - GPIO5 */ #define stac_hp_bass_gpio_info snd_ctl_boolean_mono_info static int stac_hp_bass_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; ucontrol->value.integer.value[0] = !!(spec->gpio_data & 0x20); return 0; } static int stac_hp_bass_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; unsigned int gpio_data; gpio_data = (spec->gpio_data & ~0x20) | (ucontrol->value.integer.value[0] ? 0x20 : 0); if (gpio_data == spec->gpio_data) return 0; spec->gpio_data = gpio_data; stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data); return 1; } static const struct snd_kcontrol_new stac_hp_bass_sw_ctrl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = stac_hp_bass_gpio_info, .get = stac_hp_bass_gpio_get, .put = stac_hp_bass_gpio_put, }; static int stac_add_hp_bass_switch(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; if (!snd_hda_gen_add_kctl(&spec->gen, "Bass Speaker Playback Switch", &stac_hp_bass_sw_ctrl)) return -ENOMEM; spec->gpio_mask |= 0x20; spec->gpio_dir |= 0x20; spec->gpio_data |= 0x20; return 0; } static const struct hda_pintbl ref92hd71bxx_pin_configs[] = { { 0x0a, 0x02214030 }, { 0x0b, 0x02a19040 }, { 0x0c, 0x01a19020 }, { 0x0d, 0x01014010 }, { 0x0e, 0x0181302e }, { 0x0f, 0x01014010 }, { 0x14, 0x01019020 }, { 0x18, 0x90a000f0 }, { 0x19, 0x90a000f0 }, { 0x1e, 0x01452050 }, { 0x1f, 0x01452050 }, {} }; static const struct hda_pintbl dell_m4_1_pin_configs[] = { { 0x0a, 0x0421101f }, { 0x0b, 0x04a11221 }, { 0x0c, 0x40f000f0 }, { 0x0d, 0x90170110 }, { 0x0e, 0x23a1902e }, { 0x0f, 0x23014250 }, { 0x14, 0x40f000f0 }, { 0x18, 0x90a000f0 }, { 0x19, 0x40f000f0 }, { 0x1e, 0x4f0000f0 }, { 0x1f, 0x4f0000f0 }, {} }; static const struct hda_pintbl dell_m4_2_pin_configs[] = { { 0x0a, 0x0421101f }, { 0x0b, 0x04a11221 }, { 0x0c, 0x90a70330 }, { 0x0d, 0x90170110 }, { 0x0e, 0x23a1902e }, { 0x0f, 0x23014250 }, { 0x14, 0x40f000f0 }, { 0x18, 0x40f000f0 }, { 0x19, 0x40f000f0 }, { 0x1e, 0x044413b0 }, { 0x1f, 0x044413b0 }, {} }; static const struct hda_pintbl dell_m4_3_pin_configs[] = { { 0x0a, 0x0421101f }, { 0x0b, 0x04a11221 }, { 0x0c, 0x90a70330 }, { 0x0d, 0x90170110 }, { 0x0e, 0x40f000f0 }, { 0x0f, 0x40f000f0 }, { 0x14, 0x40f000f0 }, { 0x18, 0x90a000f0 }, { 0x19, 0x40f000f0 }, { 0x1e, 0x044413b0 }, { 0x1f, 0x044413b0 }, {} }; static void stac92hd71bxx_fixup_ref(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; snd_hda_apply_pincfgs(codec, ref92hd71bxx_pin_configs); spec->gpio_mask = spec->gpio_dir = spec->gpio_data = 0; } static void stac92hd71bxx_fixup_hp_m4(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; struct hda_jack_callback *jack; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; /* Enable VREF power saving on GPIO1 detect */ snd_hda_codec_write_cache(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 0x02); jack = snd_hda_jack_detect_enable_callback(codec, codec->core.afg, stac_vref_event); if (!IS_ERR(jack)) jack->private_data = 0x02; spec->gpio_mask |= 0x02; /* enable internal microphone */ snd_hda_codec_set_pincfg(codec, 0x0e, 0x01813040); } static void stac92hd71bxx_fixup_hp_dv4(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; spec->gpio_led = 0x01; } static void stac92hd71bxx_fixup_hp_dv5(struct hda_codec *codec, const struct hda_fixup *fix, int action) { unsigned int cap; switch (action) { case HDA_FIXUP_ACT_PRE_PROBE: snd_hda_codec_set_pincfg(codec, 0x0d, 0x90170010); break; case HDA_FIXUP_ACT_PROBE: /* enable bass on HP dv7 */ cap = snd_hda_param_read(codec, 0x1, AC_PAR_GPIO_CAP); cap &= AC_GPIO_IO_COUNT; if (cap >= 6) stac_add_hp_bass_switch(codec); break; } } static void stac92hd71bxx_fixup_hp_hdx(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; spec->gpio_led = 0x08; } static bool is_hp_output(struct hda_codec *codec, hda_nid_t pin) { unsigned int pin_cfg = snd_hda_codec_get_pincfg(codec, pin); /* count line-out, too, as BIOS sets often so */ return get_defcfg_connect(pin_cfg) != AC_JACK_PORT_NONE && (get_defcfg_device(pin_cfg) == AC_JACK_LINE_OUT || get_defcfg_device(pin_cfg) == AC_JACK_HP_OUT); } static void fixup_hp_headphone(struct hda_codec *codec, hda_nid_t pin) { unsigned int pin_cfg = snd_hda_codec_get_pincfg(codec, pin); /* It was changed in the BIOS to just satisfy MS DTM. * Lets turn it back into follower HP */ pin_cfg = (pin_cfg & (~AC_DEFCFG_DEVICE)) | (AC_JACK_HP_OUT << AC_DEFCFG_DEVICE_SHIFT); pin_cfg = (pin_cfg & (~(AC_DEFCFG_DEF_ASSOC | AC_DEFCFG_SEQUENCE))) | 0x1f; snd_hda_codec_set_pincfg(codec, pin, pin_cfg); } static void stac92hd71bxx_fixup_hp(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; /* when both output A and F are assigned, these are supposedly * dock and built-in headphones; fix both pin configs */ if (is_hp_output(codec, 0x0a) && is_hp_output(codec, 0x0f)) { fixup_hp_headphone(codec, 0x0a); fixup_hp_headphone(codec, 0x0f); } if (find_mute_led_cfg(codec, 1)) codec_dbg(codec, "mute LED gpio %d polarity %d\n", spec->gpio_led, spec->gpio_led_polarity); } static const struct hda_fixup stac92hd71bxx_fixups[] = { [STAC_92HD71BXX_REF] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_ref, }, [STAC_DELL_M4_1] = { .type = HDA_FIXUP_PINS, .v.pins = dell_m4_1_pin_configs, }, [STAC_DELL_M4_2] = { .type = HDA_FIXUP_PINS, .v.pins = dell_m4_2_pin_configs, }, [STAC_DELL_M4_3] = { .type = HDA_FIXUP_PINS, .v.pins = dell_m4_3_pin_configs, }, [STAC_HP_M4] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_hp_m4, .chained = true, .chain_id = STAC_92HD71BXX_HP, }, [STAC_HP_DV4] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_hp_dv4, .chained = true, .chain_id = STAC_HP_DV5, }, [STAC_HP_DV5] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_hp_dv5, .chained = true, .chain_id = STAC_92HD71BXX_HP, }, [STAC_HP_HDX] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_hp_hdx, .chained = true, .chain_id = STAC_92HD71BXX_HP, }, [STAC_92HD71BXX_HP] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd71bxx_fixup_hp, }, }; static const struct hda_model_fixup stac92hd71bxx_models[] = { { .id = STAC_92HD71BXX_REF, .name = "ref" }, { .id = STAC_DELL_M4_1, .name = "dell-m4-1" }, { .id = STAC_DELL_M4_2, .name = "dell-m4-2" }, { .id = STAC_DELL_M4_3, .name = "dell-m4-3" }, { .id = STAC_HP_M4, .name = "hp-m4" }, { .id = STAC_HP_DV4, .name = "hp-dv4" }, { .id = STAC_HP_DV5, .name = "hp-dv5" }, { .id = STAC_HP_HDX, .name = "hp-hdx" }, { .id = STAC_HP_DV4, .name = "hp-dv4-1222nr" }, {} }; static const struct snd_pci_quirk stac92hd71bxx_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_92HD71BXX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_92HD71BXX_REF), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x1720, "HP", STAC_HP_DV5), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x3080, "HP", STAC_HP_DV5), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x30f0, "HP dv4-7", STAC_HP_DV4), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x3600, "HP dv4-7", STAC_HP_DV5), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3610, "HP HDX", STAC_HP_HDX), /* HDX18 */ SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x361a, "HP mini 1000", STAC_HP_M4), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x361b, "HP HDX", STAC_HP_HDX), /* HDX16 */ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x3620, "HP dv6", STAC_HP_DV5), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x3061, "HP dv6", STAC_HP_DV5), /* HP dv6-1110ax */ SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x363e, "HP DV6", STAC_HP_DV5), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_HP, 0xfff0, 0x7010, "HP", STAC_HP_DV5), SND_PCI_QUIRK_VENDOR(PCI_VENDOR_ID_HP, "HP", STAC_92HD71BXX_HP), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0233, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0234, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0250, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x024f, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x024d, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0251, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0277, "unknown Dell", STAC_DELL_M4_1), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0263, "unknown Dell", STAC_DELL_M4_2), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0265, "unknown Dell", STAC_DELL_M4_2), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0262, "unknown Dell", STAC_DELL_M4_2), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0264, "unknown Dell", STAC_DELL_M4_2), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02aa, "unknown Dell", STAC_DELL_M4_3), {} /* terminator */ }; static const struct hda_pintbl ref922x_pin_configs[] = { { 0x0a, 0x01014010 }, { 0x0b, 0x01016011 }, { 0x0c, 0x01012012 }, { 0x0d, 0x0221401f }, { 0x0e, 0x01813122 }, { 0x0f, 0x01011014 }, { 0x10, 0x01441030 }, { 0x11, 0x01c41030 }, { 0x15, 0x40000100 }, { 0x1b, 0x40000100 }, {} }; /* STAC 922X pin configs for 102801A7 102801AB 102801A9 102801D1 102801D2 */ static const struct hda_pintbl dell_922x_d81_pin_configs[] = { { 0x0a, 0x02214030 }, { 0x0b, 0x01a19021 }, { 0x0c, 0x01111012 }, { 0x0d, 0x01114010 }, { 0x0e, 0x02a19020 }, { 0x0f, 0x01117011 }, { 0x10, 0x400001f0 }, { 0x11, 0x400001f1 }, { 0x15, 0x01813122 }, { 0x1b, 0x400001f2 }, {} }; /* STAC 922X pin configs for 102801AC 102801D0 */ static const struct hda_pintbl dell_922x_d82_pin_configs[] = { { 0x0a, 0x02214030 }, { 0x0b, 0x01a19021 }, { 0x0c, 0x01111012 }, { 0x0d, 0x01114010 }, { 0x0e, 0x02a19020 }, { 0x0f, 0x01117011 }, { 0x10, 0x01451140 }, { 0x11, 0x400001f0 }, { 0x15, 0x01813122 }, { 0x1b, 0x400001f1 }, {} }; /* STAC 922X pin configs for 102801BF */ static const struct hda_pintbl dell_922x_m81_pin_configs[] = { { 0x0a, 0x0321101f }, { 0x0b, 0x01112024 }, { 0x0c, 0x01111222 }, { 0x0d, 0x91174220 }, { 0x0e, 0x03a11050 }, { 0x0f, 0x01116221 }, { 0x10, 0x90a70330 }, { 0x11, 0x01452340 }, { 0x15, 0x40C003f1 }, { 0x1b, 0x405003f0 }, {} }; /* STAC 9221 A1 pin configs for 102801D7 (Dell XPS M1210) */ static const struct hda_pintbl dell_922x_m82_pin_configs[] = { { 0x0a, 0x02211211 }, { 0x0b, 0x408103ff }, { 0x0c, 0x02a1123e }, { 0x0d, 0x90100310 }, { 0x0e, 0x408003f1 }, { 0x0f, 0x0221121f }, { 0x10, 0x03451340 }, { 0x11, 0x40c003f2 }, { 0x15, 0x508003f3 }, { 0x1b, 0x405003f4 }, {} }; static const struct hda_pintbl d945gtp3_pin_configs[] = { { 0x0a, 0x0221401f }, { 0x0b, 0x01a19022 }, { 0x0c, 0x01813021 }, { 0x0d, 0x01014010 }, { 0x0e, 0x40000100 }, { 0x0f, 0x40000100 }, { 0x10, 0x40000100 }, { 0x11, 0x40000100 }, { 0x15, 0x02a19120 }, { 0x1b, 0x40000100 }, {} }; static const struct hda_pintbl d945gtp5_pin_configs[] = { { 0x0a, 0x0221401f }, { 0x0b, 0x01011012 }, { 0x0c, 0x01813024 }, { 0x0d, 0x01014010 }, { 0x0e, 0x01a19021 }, { 0x0f, 0x01016011 }, { 0x10, 0x01452130 }, { 0x11, 0x40000100 }, { 0x15, 0x02a19320 }, { 0x1b, 0x40000100 }, {} }; static const struct hda_pintbl intel_mac_v1_pin_configs[] = { { 0x0a, 0x0121e21f }, { 0x0b, 0x400000ff }, { 0x0c, 0x9017e110 }, { 0x0d, 0x400000fd }, { 0x0e, 0x400000fe }, { 0x0f, 0x0181e020 }, { 0x10, 0x1145e030 }, { 0x11, 0x11c5e240 }, { 0x15, 0x400000fc }, { 0x1b, 0x400000fb }, {} }; static const struct hda_pintbl intel_mac_v2_pin_configs[] = { { 0x0a, 0x0121e21f }, { 0x0b, 0x90a7012e }, { 0x0c, 0x9017e110 }, { 0x0d, 0x400000fd }, { 0x0e, 0x400000fe }, { 0x0f, 0x0181e020 }, { 0x10, 0x1145e230 }, { 0x11, 0x500000fa }, { 0x15, 0x400000fc }, { 0x1b, 0x400000fb }, {} }; static const struct hda_pintbl intel_mac_v3_pin_configs[] = { { 0x0a, 0x0121e21f }, { 0x0b, 0x90a7012e }, { 0x0c, 0x9017e110 }, { 0x0d, 0x400000fd }, { 0x0e, 0x400000fe }, { 0x0f, 0x0181e020 }, { 0x10, 0x1145e230 }, { 0x11, 0x11c5e240 }, { 0x15, 0x400000fc }, { 0x1b, 0x400000fb }, {} }; static const struct hda_pintbl intel_mac_v4_pin_configs[] = { { 0x0a, 0x0321e21f }, { 0x0b, 0x03a1e02e }, { 0x0c, 0x9017e110 }, { 0x0d, 0x9017e11f }, { 0x0e, 0x400000fe }, { 0x0f, 0x0381e020 }, { 0x10, 0x1345e230 }, { 0x11, 0x13c5e240 }, { 0x15, 0x400000fc }, { 0x1b, 0x400000fb }, {} }; static const struct hda_pintbl intel_mac_v5_pin_configs[] = { { 0x0a, 0x0321e21f }, { 0x0b, 0x03a1e02e }, { 0x0c, 0x9017e110 }, { 0x0d, 0x9017e11f }, { 0x0e, 0x400000fe }, { 0x0f, 0x0381e020 }, { 0x10, 0x1345e230 }, { 0x11, 0x13c5e240 }, { 0x15, 0x400000fc }, { 0x1b, 0x400000fb }, {} }; static const struct hda_pintbl ecs202_pin_configs[] = { { 0x0a, 0x0221401f }, { 0x0b, 0x02a19020 }, { 0x0c, 0x01a19020 }, { 0x0d, 0x01114010 }, { 0x0e, 0x408000f0 }, { 0x0f, 0x01813022 }, { 0x10, 0x074510a0 }, { 0x11, 0x40c400f1 }, { 0x15, 0x9037012e }, { 0x1b, 0x40e000f2 }, {} }; /* codec SSIDs for Intel Mac sharing the same PCI SSID 8384:7680 */ static const struct snd_pci_quirk stac922x_intel_mac_fixup_tbl[] = { SND_PCI_QUIRK(0x0000, 0x0100, "Mac Mini", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x0800, "Mac", STAC_INTEL_MAC_V1), SND_PCI_QUIRK(0x106b, 0x0600, "Mac", STAC_INTEL_MAC_V2), SND_PCI_QUIRK(0x106b, 0x0700, "Mac", STAC_INTEL_MAC_V2), SND_PCI_QUIRK(0x106b, 0x0e00, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x0f00, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x1600, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x1700, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x0200, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x1e00, "Mac", STAC_INTEL_MAC_V3), SND_PCI_QUIRK(0x106b, 0x1a00, "Mac", STAC_INTEL_MAC_V4), SND_PCI_QUIRK(0x106b, 0x0a00, "Mac", STAC_INTEL_MAC_V5), SND_PCI_QUIRK(0x106b, 0x2200, "Mac", STAC_INTEL_MAC_V5), {} }; static const struct hda_fixup stac922x_fixups[]; /* remap the fixup from codec SSID and apply it */ static void stac922x_fixup_intel_mac_auto(struct hda_codec *codec, const struct hda_fixup *fix, int action) { if (action != HDA_FIXUP_ACT_PRE_PROBE) return; codec->fixup_id = HDA_FIXUP_ID_NOT_SET; snd_hda_pick_fixup(codec, NULL, stac922x_intel_mac_fixup_tbl, stac922x_fixups); if (codec->fixup_id != HDA_FIXUP_ID_NOT_SET) snd_hda_apply_fixup(codec, action); } static void stac922x_fixup_intel_mac_gpio(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { spec->gpio_mask = spec->gpio_dir = 0x03; spec->gpio_data = 0x03; } } static const struct hda_fixup stac922x_fixups[] = { [STAC_D945_REF] = { .type = HDA_FIXUP_PINS, .v.pins = ref922x_pin_configs, }, [STAC_D945GTP3] = { .type = HDA_FIXUP_PINS, .v.pins = d945gtp3_pin_configs, }, [STAC_D945GTP5] = { .type = HDA_FIXUP_PINS, .v.pins = d945gtp5_pin_configs, }, [STAC_INTEL_MAC_AUTO] = { .type = HDA_FIXUP_FUNC, .v.func = stac922x_fixup_intel_mac_auto, }, [STAC_INTEL_MAC_V1] = { .type = HDA_FIXUP_PINS, .v.pins = intel_mac_v1_pin_configs, .chained = true, .chain_id = STAC_922X_INTEL_MAC_GPIO, }, [STAC_INTEL_MAC_V2] = { .type = HDA_FIXUP_PINS, .v.pins = intel_mac_v2_pin_configs, .chained = true, .chain_id = STAC_922X_INTEL_MAC_GPIO, }, [STAC_INTEL_MAC_V3] = { .type = HDA_FIXUP_PINS, .v.pins = intel_mac_v3_pin_configs, .chained = true, .chain_id = STAC_922X_INTEL_MAC_GPIO, }, [STAC_INTEL_MAC_V4] = { .type = HDA_FIXUP_PINS, .v.pins = intel_mac_v4_pin_configs, .chained = true, .chain_id = STAC_922X_INTEL_MAC_GPIO, }, [STAC_INTEL_MAC_V5] = { .type = HDA_FIXUP_PINS, .v.pins = intel_mac_v5_pin_configs, .chained = true, .chain_id = STAC_922X_INTEL_MAC_GPIO, }, [STAC_922X_INTEL_MAC_GPIO] = { .type = HDA_FIXUP_FUNC, .v.func = stac922x_fixup_intel_mac_gpio, }, [STAC_ECS_202] = { .type = HDA_FIXUP_PINS, .v.pins = ecs202_pin_configs, }, [STAC_922X_DELL_D81] = { .type = HDA_FIXUP_PINS, .v.pins = dell_922x_d81_pin_configs, }, [STAC_922X_DELL_D82] = { .type = HDA_FIXUP_PINS, .v.pins = dell_922x_d82_pin_configs, }, [STAC_922X_DELL_M81] = { .type = HDA_FIXUP_PINS, .v.pins = dell_922x_m81_pin_configs, }, [STAC_922X_DELL_M82] = { .type = HDA_FIXUP_PINS, .v.pins = dell_922x_m82_pin_configs, }, }; static const struct hda_model_fixup stac922x_models[] = { { .id = STAC_D945_REF, .name = "ref" }, { .id = STAC_D945GTP5, .name = "5stack" }, { .id = STAC_D945GTP3, .name = "3stack" }, { .id = STAC_INTEL_MAC_V1, .name = "intel-mac-v1" }, { .id = STAC_INTEL_MAC_V2, .name = "intel-mac-v2" }, { .id = STAC_INTEL_MAC_V3, .name = "intel-mac-v3" }, { .id = STAC_INTEL_MAC_V4, .name = "intel-mac-v4" }, { .id = STAC_INTEL_MAC_V5, .name = "intel-mac-v5" }, { .id = STAC_INTEL_MAC_AUTO, .name = "intel-mac-auto" }, { .id = STAC_ECS_202, .name = "ecs202" }, { .id = STAC_922X_DELL_D81, .name = "dell-d81" }, { .id = STAC_922X_DELL_D82, .name = "dell-d82" }, { .id = STAC_922X_DELL_M81, .name = "dell-m81" }, { .id = STAC_922X_DELL_M82, .name = "dell-m82" }, /* for backward compatibility */ { .id = STAC_INTEL_MAC_V3, .name = "macmini" }, { .id = STAC_INTEL_MAC_V5, .name = "macbook" }, { .id = STAC_INTEL_MAC_V3, .name = "macbook-pro-v1" }, { .id = STAC_INTEL_MAC_V3, .name = "macbook-pro" }, { .id = STAC_INTEL_MAC_V2, .name = "imac-intel" }, { .id = STAC_INTEL_MAC_V3, .name = "imac-intel-20" }, {} }; static const struct snd_pci_quirk stac922x_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_D945_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_D945_REF), /* Intel 945G based systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0101, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0202, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0606, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0601, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0111, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1115, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1116, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1117, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1118, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1119, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x8826, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5049, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5055, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5048, "Intel D945G", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0110, "Intel D945G", STAC_D945GTP3), /* Intel D945G 5-stack systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0404, "Intel D945G", STAC_D945GTP5), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0303, "Intel D945G", STAC_D945GTP5), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0013, "Intel D945G", STAC_D945GTP5), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0417, "Intel D945G", STAC_D945GTP5), /* Intel 945P based systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0b0b, "Intel D945P", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0112, "Intel D945P", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0d0d, "Intel D945P", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0909, "Intel D945P", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0505, "Intel D945P", STAC_D945GTP3), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0707, "Intel D945P", STAC_D945GTP5), /* other intel */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0204, "Intel D945", STAC_D945_REF), /* other systems */ /* Apple Intel Mac (Mac Mini, MacBook, MacBook Pro...) */ SND_PCI_QUIRK(0x8384, 0x7680, "Mac", STAC_INTEL_MAC_AUTO), /* Dell systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a7, "unknown Dell", STAC_922X_DELL_D81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a9, "unknown Dell", STAC_922X_DELL_D81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ab, "unknown Dell", STAC_922X_DELL_D81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ac, "unknown Dell", STAC_922X_DELL_D82), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bf, "unknown Dell", STAC_922X_DELL_M81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d0, "unknown Dell", STAC_922X_DELL_D82), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d1, "unknown Dell", STAC_922X_DELL_D81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d2, "unknown Dell", STAC_922X_DELL_D81), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d7, "Dell XPS M1210", STAC_922X_DELL_M82), /* ECS/PC Chips boards */ SND_PCI_QUIRK_MASK(0x1019, 0xf000, 0x2000, "ECS/PC chips", STAC_ECS_202), {} /* terminator */ }; static const struct hda_pintbl ref927x_pin_configs[] = { { 0x0a, 0x02214020 }, { 0x0b, 0x02a19080 }, { 0x0c, 0x0181304e }, { 0x0d, 0x01014010 }, { 0x0e, 0x01a19040 }, { 0x0f, 0x01011012 }, { 0x10, 0x01016011 }, { 0x11, 0x0101201f }, { 0x12, 0x183301f0 }, { 0x13, 0x18a001f0 }, { 0x14, 0x18a001f0 }, { 0x21, 0x01442070 }, { 0x22, 0x01c42190 }, { 0x23, 0x40000100 }, {} }; static const struct hda_pintbl d965_3st_pin_configs[] = { { 0x0a, 0x0221401f }, { 0x0b, 0x02a19120 }, { 0x0c, 0x40000100 }, { 0x0d, 0x01014011 }, { 0x0e, 0x01a19021 }, { 0x0f, 0x01813024 }, { 0x10, 0x40000100 }, { 0x11, 0x40000100 }, { 0x12, 0x40000100 }, { 0x13, 0x40000100 }, { 0x14, 0x40000100 }, { 0x21, 0x40000100 }, { 0x22, 0x40000100 }, { 0x23, 0x40000100 }, {} }; static const struct hda_pintbl d965_5st_pin_configs[] = { { 0x0a, 0x02214020 }, { 0x0b, 0x02a19080 }, { 0x0c, 0x0181304e }, { 0x0d, 0x01014010 }, { 0x0e, 0x01a19040 }, { 0x0f, 0x01011012 }, { 0x10, 0x01016011 }, { 0x11, 0x40000100 }, { 0x12, 0x40000100 }, { 0x13, 0x40000100 }, { 0x14, 0x40000100 }, { 0x21, 0x01442070 }, { 0x22, 0x40000100 }, { 0x23, 0x40000100 }, {} }; static const struct hda_pintbl d965_5st_no_fp_pin_configs[] = { { 0x0a, 0x40000100 }, { 0x0b, 0x40000100 }, { 0x0c, 0x0181304e }, { 0x0d, 0x01014010 }, { 0x0e, 0x01a19040 }, { 0x0f, 0x01011012 }, { 0x10, 0x01016011 }, { 0x11, 0x40000100 }, { 0x12, 0x40000100 }, { 0x13, 0x40000100 }, { 0x14, 0x40000100 }, { 0x21, 0x01442070 }, { 0x22, 0x40000100 }, { 0x23, 0x40000100 }, {} }; static const struct hda_pintbl dell_3st_pin_configs[] = { { 0x0a, 0x02211230 }, { 0x0b, 0x02a11220 }, { 0x0c, 0x01a19040 }, { 0x0d, 0x01114210 }, { 0x0e, 0x01111212 }, { 0x0f, 0x01116211 }, { 0x10, 0x01813050 }, { 0x11, 0x01112214 }, { 0x12, 0x403003fa }, { 0x13, 0x90a60040 }, { 0x14, 0x90a60040 }, { 0x21, 0x404003fb }, { 0x22, 0x40c003fc }, { 0x23, 0x40000100 }, {} }; static void stac927x_fixup_ref_no_jd(struct hda_codec *codec, const struct hda_fixup *fix, int action) { /* no jack detecion for ref-no-jd model */ if (action == HDA_FIXUP_ACT_PRE_PROBE) codec->no_jack_detect = 1; } static void stac927x_fixup_ref(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { snd_hda_apply_pincfgs(codec, ref927x_pin_configs); spec->eapd_mask = spec->gpio_mask = 0; spec->gpio_dir = spec->gpio_data = 0; } } static void stac927x_fixup_dell_dmic(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; if (codec->core.subsystem_id != 0x1028022f) { /* GPIO2 High = Enable EAPD */ spec->eapd_mask = spec->gpio_mask = 0x04; spec->gpio_dir = spec->gpio_data = 0x04; } snd_hda_add_verbs(codec, dell_3st_core_init); spec->volknob_init = 1; } static void stac927x_fixup_volknob(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { snd_hda_add_verbs(codec, stac927x_volknob_core_init); spec->volknob_init = 1; } } static const struct hda_fixup stac927x_fixups[] = { [STAC_D965_REF_NO_JD] = { .type = HDA_FIXUP_FUNC, .v.func = stac927x_fixup_ref_no_jd, .chained = true, .chain_id = STAC_D965_REF, }, [STAC_D965_REF] = { .type = HDA_FIXUP_FUNC, .v.func = stac927x_fixup_ref, }, [STAC_D965_3ST] = { .type = HDA_FIXUP_PINS, .v.pins = d965_3st_pin_configs, .chained = true, .chain_id = STAC_D965_VERBS, }, [STAC_D965_5ST] = { .type = HDA_FIXUP_PINS, .v.pins = d965_5st_pin_configs, .chained = true, .chain_id = STAC_D965_VERBS, }, [STAC_D965_VERBS] = { .type = HDA_FIXUP_VERBS, .v.verbs = d965_core_init, }, [STAC_D965_5ST_NO_FP] = { .type = HDA_FIXUP_PINS, .v.pins = d965_5st_no_fp_pin_configs, }, [STAC_NEMO_DEFAULT] = { .type = HDA_FIXUP_PINS, .v.pins = nemo_pin_configs, }, [STAC_DELL_3ST] = { .type = HDA_FIXUP_PINS, .v.pins = dell_3st_pin_configs, .chained = true, .chain_id = STAC_927X_DELL_DMIC, }, [STAC_DELL_BIOS] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* correct the front output jack as a hp out */ { 0x0f, 0x0221101f }, /* correct the front input jack as a mic */ { 0x0e, 0x02a79130 }, {} }, .chained = true, .chain_id = STAC_927X_DELL_DMIC, }, [STAC_DELL_BIOS_AMIC] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* configure the analog microphone on some laptops */ { 0x0c, 0x90a79130 }, {} }, .chained = true, .chain_id = STAC_DELL_BIOS, }, [STAC_DELL_BIOS_SPDIF] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { /* correct the device field to SPDIF out */ { 0x21, 0x01442070 }, {} }, .chained = true, .chain_id = STAC_DELL_BIOS, }, [STAC_927X_DELL_DMIC] = { .type = HDA_FIXUP_FUNC, .v.func = stac927x_fixup_dell_dmic, }, [STAC_927X_VOLKNOB] = { .type = HDA_FIXUP_FUNC, .v.func = stac927x_fixup_volknob, }, }; static const struct hda_model_fixup stac927x_models[] = { { .id = STAC_D965_REF_NO_JD, .name = "ref-no-jd" }, { .id = STAC_D965_REF, .name = "ref" }, { .id = STAC_D965_3ST, .name = "3stack" }, { .id = STAC_D965_5ST, .name = "5stack" }, { .id = STAC_D965_5ST_NO_FP, .name = "5stack-no-fp" }, { .id = STAC_DELL_3ST, .name = "dell-3stack" }, { .id = STAC_DELL_BIOS, .name = "dell-bios" }, { .id = STAC_NEMO_DEFAULT, .name = "nemo-default" }, { .id = STAC_DELL_BIOS_AMIC, .name = "dell-bios-amic" }, { .id = STAC_927X_VOLKNOB, .name = "volknob" }, {} }; static const struct snd_pci_quirk stac927x_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_D965_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_D965_REF), /* Intel 946 based systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x3d01, "Intel D946", STAC_D965_3ST), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xa301, "Intel D946", STAC_D965_3ST), /* 965 based 3 stack systems */ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2100, "Intel D965", STAC_D965_3ST), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2000, "Intel D965", STAC_D965_3ST), /* Dell 3 stack systems */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01dd, "Dell Dimension E520", STAC_DELL_3ST), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ed, "Dell ", STAC_DELL_3ST), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f4, "Dell ", STAC_DELL_3ST), /* Dell 3 stack systems with verb table in BIOS */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f3, "Dell Inspiron 1420", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f7, "Dell XPS M1730", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0227, "Dell Vostro 1400 ", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022e, "Dell ", STAC_DELL_BIOS_SPDIF), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell Inspiron 1525", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0242, "Dell ", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0243, "Dell ", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ff, "Dell ", STAC_DELL_BIOS), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0209, "Dell XPS 1330", STAC_DELL_BIOS_SPDIF), /* 965 based 5 stack systems */ SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2300, "Intel D965", STAC_D965_5ST), SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_INTEL, 0xff00, 0x2500, "Intel D965", STAC_D965_5ST), /* Nemo */ SND_PCI_QUIRK(0x1888, 0x1000, "AmigaOne X1000", STAC_NEMO_DEFAULT), /* volume-knob fixes */ SND_PCI_QUIRK_VENDOR(0x10cf, "FSC", STAC_927X_VOLKNOB), {} /* terminator */ }; static const struct hda_pintbl ref9205_pin_configs[] = { { 0x0a, 0x40000100 }, { 0x0b, 0x40000100 }, { 0x0c, 0x01016011 }, { 0x0d, 0x01014010 }, { 0x0e, 0x01813122 }, { 0x0f, 0x01a19021 }, { 0x14, 0x01019020 }, { 0x16, 0x40000100 }, { 0x17, 0x90a000f0 }, { 0x18, 0x90a000f0 }, { 0x21, 0x01441030 }, { 0x22, 0x01c41030 }, {} }; /* STAC 9205 pin configs for 102801F1 102801F2 102801FC 102801FD 10280204 1028021F 10280228 (Dell Vostro 1500) 10280229 (Dell Vostro 1700) */ static const struct hda_pintbl dell_9205_m42_pin_configs[] = { { 0x0a, 0x0321101F }, { 0x0b, 0x03A11020 }, { 0x0c, 0x400003FA }, { 0x0d, 0x90170310 }, { 0x0e, 0x400003FB }, { 0x0f, 0x400003FC }, { 0x14, 0x400003FD }, { 0x16, 0x40F000F9 }, { 0x17, 0x90A60330 }, { 0x18, 0x400003FF }, { 0x21, 0x0144131F }, { 0x22, 0x40C003FE }, {} }; /* STAC 9205 pin configs for 102801F9 102801FA 102801FE 102801FF (Dell Precision M4300) 10280206 10280200 10280201 */ static const struct hda_pintbl dell_9205_m43_pin_configs[] = { { 0x0a, 0x0321101f }, { 0x0b, 0x03a11020 }, { 0x0c, 0x90a70330 }, { 0x0d, 0x90170310 }, { 0x0e, 0x400000fe }, { 0x0f, 0x400000ff }, { 0x14, 0x400000fd }, { 0x16, 0x40f000f9 }, { 0x17, 0x400000fa }, { 0x18, 0x400000fc }, { 0x21, 0x0144131f }, { 0x22, 0x40c003f8 }, /* Enable SPDIF in/out */ { 0x1f, 0x01441030 }, { 0x20, 0x1c410030 }, {} }; static const struct hda_pintbl dell_9205_m44_pin_configs[] = { { 0x0a, 0x0421101f }, { 0x0b, 0x04a11020 }, { 0x0c, 0x400003fa }, { 0x0d, 0x90170310 }, { 0x0e, 0x400003fb }, { 0x0f, 0x400003fc }, { 0x14, 0x400003fd }, { 0x16, 0x400003f9 }, { 0x17, 0x90a60330 }, { 0x18, 0x400003ff }, { 0x21, 0x01441340 }, { 0x22, 0x40c003fe }, {} }; static void stac9205_fixup_ref(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { snd_hda_apply_pincfgs(codec, ref9205_pin_configs); /* SPDIF-In enabled */ spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0; } } static void stac9205_fixup_dell_m43(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; struct hda_jack_callback *jack; if (action == HDA_FIXUP_ACT_PRE_PROBE) { snd_hda_apply_pincfgs(codec, dell_9205_m43_pin_configs); /* Enable unsol response for GPIO4/Dock HP connection */ snd_hda_codec_write_cache(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 0x10); jack = snd_hda_jack_detect_enable_callback(codec, codec->core.afg, stac_vref_event); if (!IS_ERR(jack)) jack->private_data = 0x01; spec->gpio_dir = 0x0b; spec->eapd_mask = 0x01; spec->gpio_mask = 0x1b; spec->gpio_mute = 0x10; /* GPIO0 High = EAPD, GPIO1 Low = Headphone Mute, * GPIO3 Low = DRM */ spec->gpio_data = 0x01; } } static void stac9205_fixup_eapd(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) spec->eapd_switch = 0; } static const struct hda_fixup stac9205_fixups[] = { [STAC_9205_REF] = { .type = HDA_FIXUP_FUNC, .v.func = stac9205_fixup_ref, }, [STAC_9205_DELL_M42] = { .type = HDA_FIXUP_PINS, .v.pins = dell_9205_m42_pin_configs, }, [STAC_9205_DELL_M43] = { .type = HDA_FIXUP_FUNC, .v.func = stac9205_fixup_dell_m43, }, [STAC_9205_DELL_M44] = { .type = HDA_FIXUP_PINS, .v.pins = dell_9205_m44_pin_configs, }, [STAC_9205_EAPD] = { .type = HDA_FIXUP_FUNC, .v.func = stac9205_fixup_eapd, }, {} }; static const struct hda_model_fixup stac9205_models[] = { { .id = STAC_9205_REF, .name = "ref" }, { .id = STAC_9205_DELL_M42, .name = "dell-m42" }, { .id = STAC_9205_DELL_M43, .name = "dell-m43" }, { .id = STAC_9205_DELL_M44, .name = "dell-m44" }, { .id = STAC_9205_EAPD, .name = "eapd" }, {} }; static const struct snd_pci_quirk stac9205_fixup_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_9205_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xfb30, "SigmaTel", STAC_9205_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_9205_REF), /* Dell */ SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1, "unknown Dell", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f2, "unknown Dell", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f8, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f9, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fa, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fc, "unknown Dell", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fd, "unknown Dell", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fe, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ff, "Dell Precision M4300", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0204, "unknown Dell", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0206, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021b, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021c, "Dell Precision", STAC_9205_DELL_M43), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021f, "Dell Inspiron", STAC_9205_DELL_M44), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0228, "Dell Vostro 1500", STAC_9205_DELL_M42), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0229, "Dell Vostro 1700", STAC_9205_DELL_M42), /* Gateway */ SND_PCI_QUIRK(0x107b, 0x0560, "Gateway T6834c", STAC_9205_EAPD), SND_PCI_QUIRK(0x107b, 0x0565, "Gateway T1616", STAC_9205_EAPD), {} /* terminator */ }; static void stac92hd95_fixup_hp_led(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct sigmatel_spec *spec = codec->spec; if (action != HDA_FIXUP_ACT_PRE_PROBE) return; if (find_mute_led_cfg(codec, spec->default_polarity)) codec_dbg(codec, "mute LED gpio %d polarity %d\n", spec->gpio_led, spec->gpio_led_polarity); } static const struct hda_fixup stac92hd95_fixups[] = { [STAC_92HD95_HP_LED] = { .type = HDA_FIXUP_FUNC, .v.func = stac92hd95_fixup_hp_led, }, [STAC_92HD95_HP_BASS] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { {0x1a, 0x795, 0x00}, /* HPF to 100Hz */ {} }, .chained = true, .chain_id = STAC_92HD95_HP_LED, }, }; static const struct snd_pci_quirk stac92hd95_fixup_tbl[] = { SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x1911, "HP Spectre 13", STAC_92HD95_HP_BASS), {} /* terminator */ }; static const struct hda_model_fixup stac92hd95_models[] = { { .id = STAC_92HD95_HP_LED, .name = "hp-led" }, { .id = STAC_92HD95_HP_BASS, .name = "hp-bass" }, {} }; static int stac_parse_auto_config(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; int err; int flags = 0; if (spec->headset_jack) flags |= HDA_PINCFG_HEADSET_MIC; err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, flags); if (err < 0) return err; /* add hooks */ spec->gen.pcm_playback_hook = stac_playback_pcm_hook; spec->gen.pcm_capture_hook = stac_capture_pcm_hook; spec->gen.automute_hook = stac_update_outputs; if (spec->gpio_led) snd_hda_gen_add_mute_led_cdev(codec, stac_vmaster_hook); err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) return err; if (spec->vref_mute_led_nid) { err = snd_hda_gen_fix_pin_power(codec, spec->vref_mute_led_nid); if (err < 0) return err; } /* setup analog beep controls */ if (spec->anabeep_nid > 0) { err = stac_auto_create_beep_ctls(codec, spec->anabeep_nid); if (err < 0) return err; } /* setup digital beep controls and input device */ #ifdef CONFIG_SND_HDA_INPUT_BEEP if (spec->gen.beep_nid) { hda_nid_t nid = spec->gen.beep_nid; unsigned int caps; err = stac_auto_create_beep_ctls(codec, nid); if (err < 0) return err; if (codec->beep) { /* IDT/STAC codecs have linear beep tone parameter */ codec->beep->linear_tone = spec->linear_tone_beep; /* keep power up while beep is enabled */ codec->beep->keep_power_at_enable = 1; /* if no beep switch is available, make its own one */ caps = query_amp_caps(codec, nid, HDA_OUTPUT); if (!(caps & AC_AMPCAP_MUTE)) { err = stac_beep_switch_ctl(codec); if (err < 0) return err; } } } #endif if (spec->aloopback_ctl && snd_hda_get_bool_hint(codec, "loopback") == 1) { unsigned int wr_verb = spec->aloopback_ctl->private_value >> 16; if (snd_hdac_regmap_add_vendor_verb(&codec->core, wr_verb)) return -ENOMEM; if (!snd_hda_gen_add_kctl(&spec->gen, NULL, spec->aloopback_ctl)) return -ENOMEM; } if (spec->have_spdif_mux) { err = stac_create_spdif_mux_ctls(codec); if (err < 0) return err; } stac_init_power_map(codec); return 0; } static int stac_init(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; int i; /* override some hints */ stac_store_hints(codec); /* set up GPIO */ /* turn on EAPD statically when spec->eapd_switch isn't set. * otherwise, unsol event will turn it on/off dynamically */ if (!spec->eapd_switch) spec->gpio_data |= spec->eapd_mask; stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data); snd_hda_gen_init(codec); /* sync the power-map */ if (spec->num_pwrs) snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_IDT_SET_POWER_MAP, spec->power_map_bits); /* power down inactive ADCs */ if (spec->powerdown_adcs) { for (i = 0; i < spec->gen.num_all_adcs; i++) { if (spec->active_adcs & (1 << i)) continue; snd_hda_codec_write(codec, spec->gen.all_adcs[i], 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D3); } } return 0; } #define stac_free snd_hda_gen_free #ifdef CONFIG_SND_PROC_FS static void stac92hd_proc_hook(struct snd_info_buffer *buffer, struct hda_codec *codec, hda_nid_t nid) { if (nid == codec->core.afg) snd_iprintf(buffer, "Power-Map: 0x%02x\n", snd_hda_codec_read(codec, nid, 0, AC_VERB_IDT_GET_POWER_MAP, 0)); } static void analog_loop_proc_hook(struct snd_info_buffer *buffer, struct hda_codec *codec, unsigned int verb) { snd_iprintf(buffer, "Analog Loopback: 0x%02x\n", snd_hda_codec_read(codec, codec->core.afg, 0, verb, 0)); } /* stac92hd71bxx, stac92hd73xx */ static void stac92hd7x_proc_hook(struct snd_info_buffer *buffer, struct hda_codec *codec, hda_nid_t nid) { stac92hd_proc_hook(buffer, codec, nid); if (nid == codec->core.afg) analog_loop_proc_hook(buffer, codec, 0xfa0); } static void stac9205_proc_hook(struct snd_info_buffer *buffer, struct hda_codec *codec, hda_nid_t nid) { if (nid == codec->core.afg) analog_loop_proc_hook(buffer, codec, 0xfe0); } static void stac927x_proc_hook(struct snd_info_buffer *buffer, struct hda_codec *codec, hda_nid_t nid) { if (nid == codec->core.afg) analog_loop_proc_hook(buffer, codec, 0xfeb); } #else #define stac92hd_proc_hook NULL #define stac92hd7x_proc_hook NULL #define stac9205_proc_hook NULL #define stac927x_proc_hook NULL #endif #ifdef CONFIG_PM static int stac_suspend(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; snd_hda_shutup_pins(codec); if (spec->eapd_mask) stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data & ~spec->eapd_mask); return 0; } #else #define stac_suspend NULL #endif /* CONFIG_PM */ static const struct hda_codec_ops stac_patch_ops = { .build_controls = snd_hda_gen_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = stac_init, .free = stac_free, .unsol_event = snd_hda_jack_unsol_event, #ifdef CONFIG_PM .suspend = stac_suspend, #endif }; static int alloc_stac_spec(struct hda_codec *codec) { struct sigmatel_spec *spec; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return -ENOMEM; snd_hda_gen_spec_init(&spec->gen); codec->spec = spec; codec->no_trigger_sense = 1; /* seems common with STAC/IDT codecs */ spec->gen.dac_min_mute = true; codec->patch_ops = stac_patch_ops; return 0; } static int patch_stac9200(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; codec->power_filter = snd_hda_codec_eapd_power_filter; snd_hda_add_verbs(codec, stac9200_eapd_init); snd_hda_pick_fixup(codec, stac9200_models, stac9200_fixup_tbl, stac9200_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static int patch_stac925x(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; snd_hda_add_verbs(codec, stac925x_core_init); snd_hda_pick_fixup(codec, stac925x_models, stac925x_fixup_tbl, stac925x_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static int patch_stac92hd73xx(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; int num_dacs; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; /* enable power_save_node only for new 92HD89xx chips, as it causes * click noises on old 92HD73xx chips. */ if ((codec->core.vendor_id & 0xfffffff0) != 0x111d7670) codec->power_save_node = 1; spec->linear_tone_beep = 0; spec->gen.mixer_nid = 0x1d; spec->have_spdif_mux = 1; num_dacs = snd_hda_get_num_conns(codec, 0x0a) - 1; if (num_dacs < 3 || num_dacs > 5) { codec_warn(codec, "Could not determine number of channels defaulting to DAC count\n"); num_dacs = 5; } switch (num_dacs) { case 0x3: /* 6 Channel */ spec->aloopback_ctl = &stac92hd73xx_6ch_loopback; break; case 0x4: /* 8 Channel */ spec->aloopback_ctl = &stac92hd73xx_8ch_loopback; break; case 0x5: /* 10 Channel */ spec->aloopback_ctl = &stac92hd73xx_10ch_loopback; break; } spec->aloopback_mask = 0x01; spec->aloopback_shift = 8; spec->gen.beep_nid = 0x1c; /* digital beep */ /* GPIO0 High = Enable EAPD */ spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x1; spec->gpio_data = 0x01; spec->eapd_switch = 1; spec->num_pwrs = ARRAY_SIZE(stac92hd73xx_pwr_nids); spec->pwr_nids = stac92hd73xx_pwr_nids; spec->gen.own_eapd_ctl = 1; spec->gen.power_down_unused = 1; snd_hda_pick_fixup(codec, stac92hd73xx_models, stac92hd73xx_fixup_tbl, stac92hd73xx_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); if (!spec->volknob_init) snd_hda_add_verbs(codec, stac92hd73xx_core_init); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } /* Don't GPIO-mute speakers if there are no internal speakers, because * the GPIO might be necessary for Headphone */ if (spec->eapd_switch && !has_builtin_speaker(codec)) spec->eapd_switch = 0; codec->proc_widget_hook = stac92hd7x_proc_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static void stac_setup_gpio(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; spec->gpio_mask |= spec->eapd_mask; if (spec->gpio_led) { if (!spec->vref_mute_led_nid) { spec->gpio_mask |= spec->gpio_led; spec->gpio_dir |= spec->gpio_led; spec->gpio_data |= spec->gpio_led; } else { codec->power_filter = stac_vref_led_power_filter; } } if (spec->mic_mute_led_gpio) { spec->gpio_mask |= spec->mic_mute_led_gpio; spec->gpio_dir |= spec->mic_mute_led_gpio; spec->mic_enabled = 0; spec->gpio_data |= spec->mic_mute_led_gpio; snd_hda_gen_add_micmute_led_cdev(codec, stac_capture_led_update); } } static int patch_stac92hd83xxx(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; /* longer delay needed for D3 */ codec->core.power_caps &= ~AC_PWRST_EPSS; spec = codec->spec; codec->power_save_node = 1; spec->linear_tone_beep = 0; spec->gen.own_eapd_ctl = 1; spec->gen.power_down_unused = 1; spec->gen.mixer_nid = 0x1b; spec->gen.beep_nid = 0x21; /* digital beep */ spec->pwr_nids = stac92hd83xxx_pwr_nids; spec->num_pwrs = ARRAY_SIZE(stac92hd83xxx_pwr_nids); spec->default_polarity = -1; /* no default cfg */ snd_hda_add_verbs(codec, stac92hd83xxx_core_init); snd_hda_pick_fixup(codec, stac92hd83xxx_models, stac92hd83xxx_fixup_tbl, stac92hd83xxx_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); stac_setup_gpio(codec); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } codec->proc_widget_hook = stac92hd_proc_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static const hda_nid_t stac92hd95_pwr_nids[] = { 0x0a, 0x0b, 0x0c, 0x0d }; static int patch_stac92hd95(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; /* longer delay needed for D3 */ codec->core.power_caps &= ~AC_PWRST_EPSS; spec = codec->spec; codec->power_save_node = 1; spec->linear_tone_beep = 0; spec->gen.own_eapd_ctl = 1; spec->gen.power_down_unused = 1; spec->gen.beep_nid = 0x19; /* digital beep */ spec->pwr_nids = stac92hd95_pwr_nids; spec->num_pwrs = ARRAY_SIZE(stac92hd95_pwr_nids); spec->default_polarity = 0; snd_hda_pick_fixup(codec, stac92hd95_models, stac92hd95_fixup_tbl, stac92hd95_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); stac_setup_gpio(codec); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } codec->proc_widget_hook = stac92hd_proc_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static int patch_stac92hd71bxx(struct hda_codec *codec) { struct sigmatel_spec *spec; const hda_nid_t *unmute_nids = stac92hd71bxx_unmute_nids; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; /* disabled power_save_node since it causes noises on a Dell machine */ /* codec->power_save_node = 1; */ spec->linear_tone_beep = 0; spec->gen.own_eapd_ctl = 1; spec->gen.power_down_unused = 1; spec->gen.mixer_nid = 0x17; spec->have_spdif_mux = 1; /* GPIO0 = EAPD */ spec->gpio_mask = 0x01; spec->gpio_dir = 0x01; spec->gpio_data = 0x01; switch (codec->core.vendor_id) { case 0x111d76b6: /* 4 Port without Analog Mixer */ case 0x111d76b7: unmute_nids++; break; case 0x111d7608: /* 5 Port with Analog Mixer */ if ((codec->core.revision_id & 0xf) == 0 || (codec->core.revision_id & 0xf) == 1) spec->stream_delay = 40; /* 40 milliseconds */ /* disable VSW */ unmute_nids++; snd_hda_codec_set_pincfg(codec, 0x0f, 0x40f000f0); snd_hda_codec_set_pincfg(codec, 0x19, 0x40f000f3); break; case 0x111d7603: /* 6 Port with Analog Mixer */ if ((codec->core.revision_id & 0xf) == 1) spec->stream_delay = 40; /* 40 milliseconds */ break; } if (get_wcaps_type(get_wcaps(codec, 0x28)) == AC_WID_VOL_KNB) snd_hda_add_verbs(codec, stac92hd71bxx_core_init); if (get_wcaps(codec, 0xa) & AC_WCAP_IN_AMP) { const hda_nid_t *p; for (p = unmute_nids; *p; p++) snd_hda_codec_amp_init_stereo(codec, *p, HDA_INPUT, 0, 0xff, 0x00); } spec->aloopback_ctl = &stac92hd71bxx_loopback; spec->aloopback_mask = 0x50; spec->aloopback_shift = 0; spec->powerdown_adcs = 1; spec->gen.beep_nid = 0x26; /* digital beep */ spec->num_pwrs = ARRAY_SIZE(stac92hd71bxx_pwr_nids); spec->pwr_nids = stac92hd71bxx_pwr_nids; snd_hda_pick_fixup(codec, stac92hd71bxx_models, stac92hd71bxx_fixup_tbl, stac92hd71bxx_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); stac_setup_gpio(codec); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } codec->proc_widget_hook = stac92hd7x_proc_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static int patch_stac922x(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; snd_hda_add_verbs(codec, stac922x_core_init); /* Fix Mux capture level; max to 2 */ snd_hda_override_amp_caps(codec, 0x12, HDA_OUTPUT, (0 << AC_AMPCAP_OFFSET_SHIFT) | (2 << AC_AMPCAP_NUM_STEPS_SHIFT) | (0x27 << AC_AMPCAP_STEP_SIZE_SHIFT) | (0 << AC_AMPCAP_MUTE_SHIFT)); snd_hda_pick_fixup(codec, stac922x_models, stac922x_fixup_tbl, stac922x_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static const char * const stac927x_spdif_labels[] = { "Digital Playback", "ADAT", "Analog Mux 1", "Analog Mux 2", "Analog Mux 3", NULL }; static int patch_stac927x(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; spec->have_spdif_mux = 1; spec->spdif_labels = stac927x_spdif_labels; spec->gen.beep_nid = 0x23; /* digital beep */ /* GPIO0 High = Enable EAPD */ spec->eapd_mask = spec->gpio_mask = 0x01; spec->gpio_dir = spec->gpio_data = 0x01; spec->aloopback_ctl = &stac927x_loopback; spec->aloopback_mask = 0x40; spec->aloopback_shift = 0; spec->eapd_switch = 1; snd_hda_pick_fixup(codec, stac927x_models, stac927x_fixup_tbl, stac927x_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); if (!spec->volknob_init) snd_hda_add_verbs(codec, stac927x_core_init); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } codec->proc_widget_hook = stac927x_proc_hook; /* * !!FIXME!! * The STAC927x seem to require fairly long delays for certain * command sequences. With too short delays (even if the answer * is set to RIRB properly), it results in the silence output * on some hardwares like Dell. * * The below flag enables the longer delay (see get_response * in hda_intel.c). */ codec->bus->core.needs_damn_long_delay = 1; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static int patch_stac9205(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; spec->have_spdif_mux = 1; spec->gen.beep_nid = 0x23; /* digital beep */ snd_hda_add_verbs(codec, stac9205_core_init); spec->aloopback_ctl = &stac9205_loopback; spec->aloopback_mask = 0x40; spec->aloopback_shift = 0; /* GPIO0 High = EAPD */ spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x1; spec->gpio_data = 0x01; /* Turn on/off EAPD per HP plugging */ spec->eapd_switch = 1; snd_hda_pick_fixup(codec, stac9205_models, stac9205_fixup_tbl, stac9205_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return err; } codec->proc_widget_hook = stac9205_proc_hook; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } /* * STAC9872 hack */ static const struct hda_verb stac9872_core_init[] = { {0x15, AC_VERB_SET_CONNECT_SEL, 0x1}, /* mic-sel: 0a,0d,14,02 */ {0x15, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, /* Mic-in -> 0x9 */ {} }; static const struct hda_pintbl stac9872_vaio_pin_configs[] = { { 0x0a, 0x03211020 }, { 0x0b, 0x411111f0 }, { 0x0c, 0x411111f0 }, { 0x0d, 0x03a15030 }, { 0x0e, 0x411111f0 }, { 0x0f, 0x90170110 }, { 0x11, 0x411111f0 }, { 0x13, 0x411111f0 }, { 0x14, 0x90a7013e }, {} }; static const struct hda_model_fixup stac9872_models[] = { { .id = STAC_9872_VAIO, .name = "vaio" }, {} }; static const struct hda_fixup stac9872_fixups[] = { [STAC_9872_VAIO] = { .type = HDA_FIXUP_PINS, .v.pins = stac9872_vaio_pin_configs, }, }; static const struct snd_pci_quirk stac9872_fixup_tbl[] = { SND_PCI_QUIRK_MASK(0x104d, 0xfff0, 0x81e0, "Sony VAIO F/S", STAC_9872_VAIO), {} /* terminator */ }; static int patch_stac9872(struct hda_codec *codec) { struct sigmatel_spec *spec; int err; err = alloc_stac_spec(codec); if (err < 0) return err; spec = codec->spec; spec->linear_tone_beep = 1; spec->gen.own_eapd_ctl = 1; snd_hda_add_verbs(codec, stac9872_core_init); snd_hda_pick_fixup(codec, stac9872_models, stac9872_fixup_tbl, stac9872_fixups); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = stac_parse_auto_config(codec); if (err < 0) { stac_free(codec); return -EINVAL; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } /* * patch entries */ static const struct hda_device_id snd_hda_id_sigmatel[] = { HDA_CODEC_ENTRY(0x83847690, "STAC9200", patch_stac9200), HDA_CODEC_ENTRY(0x83847882, "STAC9220 A1", patch_stac922x), HDA_CODEC_ENTRY(0x83847680, "STAC9221 A1", patch_stac922x), HDA_CODEC_ENTRY(0x83847880, "STAC9220 A2", patch_stac922x), HDA_CODEC_ENTRY(0x83847681, "STAC9220D/9223D A2", patch_stac922x), HDA_CODEC_ENTRY(0x83847682, "STAC9221 A2", patch_stac922x), HDA_CODEC_ENTRY(0x83847683, "STAC9221D A2", patch_stac922x), HDA_CODEC_ENTRY(0x83847618, "STAC9227", patch_stac927x), HDA_CODEC_ENTRY(0x83847619, "STAC9227", patch_stac927x), HDA_CODEC_ENTRY(0x83847638, "STAC92HD700", patch_stac927x), HDA_CODEC_ENTRY(0x83847616, "STAC9228", patch_stac927x), HDA_CODEC_ENTRY(0x83847617, "STAC9228", patch_stac927x), HDA_CODEC_ENTRY(0x83847614, "STAC9229", patch_stac927x), HDA_CODEC_ENTRY(0x83847615, "STAC9229", patch_stac927x), HDA_CODEC_ENTRY(0x83847620, "STAC9274", patch_stac927x), HDA_CODEC_ENTRY(0x83847621, "STAC9274D", patch_stac927x), HDA_CODEC_ENTRY(0x83847622, "STAC9273X", patch_stac927x), HDA_CODEC_ENTRY(0x83847623, "STAC9273D", patch_stac927x), HDA_CODEC_ENTRY(0x83847624, "STAC9272X", patch_stac927x), HDA_CODEC_ENTRY(0x83847625, "STAC9272D", patch_stac927x), HDA_CODEC_ENTRY(0x83847626, "STAC9271X", patch_stac927x), HDA_CODEC_ENTRY(0x83847627, "STAC9271D", patch_stac927x), HDA_CODEC_ENTRY(0x83847628, "STAC9274X5NH", patch_stac927x), HDA_CODEC_ENTRY(0x83847629, "STAC9274D5NH", patch_stac927x), HDA_CODEC_ENTRY(0x83847632, "STAC9202", patch_stac925x), HDA_CODEC_ENTRY(0x83847633, "STAC9202D", patch_stac925x), HDA_CODEC_ENTRY(0x83847634, "STAC9250", patch_stac925x), HDA_CODEC_ENTRY(0x83847635, "STAC9250D", patch_stac925x), HDA_CODEC_ENTRY(0x83847636, "STAC9251", patch_stac925x), HDA_CODEC_ENTRY(0x83847637, "STAC9250D", patch_stac925x), HDA_CODEC_ENTRY(0x83847645, "92HD206X", patch_stac927x), HDA_CODEC_ENTRY(0x83847646, "92HD206D", patch_stac927x), /* The following does not take into account .id=0x83847661 when subsys = * 104D0C00 which is STAC9225s. Because of this, some SZ Notebooks are * currently not fully supported. */ HDA_CODEC_ENTRY(0x83847661, "CXD9872RD/K", patch_stac9872), HDA_CODEC_ENTRY(0x83847662, "STAC9872AK", patch_stac9872), HDA_CODEC_ENTRY(0x83847664, "CXD9872AKD", patch_stac9872), HDA_CODEC_ENTRY(0x83847698, "STAC9205", patch_stac9205), HDA_CODEC_ENTRY(0x838476a0, "STAC9205", patch_stac9205), HDA_CODEC_ENTRY(0x838476a1, "STAC9205D", patch_stac9205), HDA_CODEC_ENTRY(0x838476a2, "STAC9204", patch_stac9205), HDA_CODEC_ENTRY(0x838476a3, "STAC9204D", patch_stac9205), HDA_CODEC_ENTRY(0x838476a4, "STAC9255", patch_stac9205), HDA_CODEC_ENTRY(0x838476a5, "STAC9255D", patch_stac9205), HDA_CODEC_ENTRY(0x838476a6, "STAC9254", patch_stac9205), HDA_CODEC_ENTRY(0x838476a7, "STAC9254D", patch_stac9205), HDA_CODEC_ENTRY(0x111d7603, "92HD75B3X5", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d7604, "92HD83C1X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76d4, "92HD83C1C5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7605, "92HD81B1X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76d5, "92HD81B1C5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76d1, "92HD87B1/3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76d9, "92HD87B2/4", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7666, "92HD88B3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7667, "92HD88B1", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7668, "92HD88B2", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7669, "92HD88B4", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d7608, "92HD75B2X5", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d7674, "92HD73D1X5", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d7675, "92HD73C1X5", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d7676, "92HD73E1X5", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d7695, "92HD95", patch_stac92hd95), HDA_CODEC_ENTRY(0x111d76b0, "92HD71B8X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b1, "92HD71B8X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b2, "92HD71B7X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b3, "92HD71B7X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b4, "92HD71B6X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b5, "92HD71B6X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b6, "92HD71B5X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76b7, "92HD71B5X", patch_stac92hd71bxx), HDA_CODEC_ENTRY(0x111d76c0, "92HD89C3", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c1, "92HD89C2", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c2, "92HD89C1", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c3, "92HD89B3", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c4, "92HD89B2", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c5, "92HD89B1", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c6, "92HD89E3", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c7, "92HD89E2", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c8, "92HD89E1", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76c9, "92HD89D3", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76ca, "92HD89D2", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76cb, "92HD89D1", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76cc, "92HD89F3", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76cd, "92HD89F2", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76ce, "92HD89F1", patch_stac92hd73xx), HDA_CODEC_ENTRY(0x111d76df, "92HD93BXX", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e0, "92HD91BXX", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e3, "92HD98BXX", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e5, "92HD99BXX", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e7, "92HD90BXX", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e8, "92HD66B1X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76e9, "92HD66B2X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76ea, "92HD66B3X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76eb, "92HD66C1X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76ec, "92HD66C2X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76ed, "92HD66C3X5", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76ee, "92HD66B1X3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76ef, "92HD66B2X3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76f0, "92HD66B3X3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76f1, "92HD66C1X3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76f2, "92HD66C2X3", patch_stac92hd83xxx), HDA_CODEC_ENTRY(0x111d76f3, "92HD66C3/65", patch_stac92hd83xxx), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_sigmatel); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("IDT/Sigmatel HD-audio codec"); static struct hda_codec_driver sigmatel_driver = { .id = snd_hda_id_sigmatel, }; module_hda_codec_driver(sigmatel_driver);
linux-master
sound/pci/hda/patch_sigmatel.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Universal Interface for Intel High Definition Audio Codec * * HD audio interface patch for Silicon Labs 3054/5 modem codec * * Copyright (c) 2005 Sasha Khapyorsky <[email protected]> * Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/hda_codec.h> #include "hda_local.h" /* si3054 verbs */ #define SI3054_VERB_READ_NODE 0x900 #define SI3054_VERB_WRITE_NODE 0x100 /* si3054 nodes (registers) */ #define SI3054_EXTENDED_MID 2 #define SI3054_LINE_RATE 3 #define SI3054_LINE_LEVEL 4 #define SI3054_GPIO_CFG 5 #define SI3054_GPIO_POLARITY 6 #define SI3054_GPIO_STICKY 7 #define SI3054_GPIO_WAKEUP 8 #define SI3054_GPIO_STATUS 9 #define SI3054_GPIO_CONTROL 10 #define SI3054_MISC_AFE 11 #define SI3054_CHIPID 12 #define SI3054_LINE_CFG1 13 #define SI3054_LINE_STATUS 14 #define SI3054_DC_TERMINATION 15 #define SI3054_LINE_CONFIG 16 #define SI3054_CALLPROG_ATT 17 #define SI3054_SQ_CONTROL 18 #define SI3054_MISC_CONTROL 19 #define SI3054_RING_CTRL1 20 #define SI3054_RING_CTRL2 21 /* extended MID */ #define SI3054_MEI_READY 0xf /* line level */ #define SI3054_ATAG_MASK 0x00f0 #define SI3054_DTAG_MASK 0xf000 /* GPIO bits */ #define SI3054_GPIO_OH 0x0001 #define SI3054_GPIO_CID 0x0002 /* chipid and revisions */ #define SI3054_CHIPID_CODEC_REV_MASK 0x000f #define SI3054_CHIPID_DAA_REV_MASK 0x00f0 #define SI3054_CHIPID_INTERNATIONAL 0x0100 #define SI3054_CHIPID_DAA_ID 0x0f00 #define SI3054_CHIPID_CODEC_ID (1<<12) /* si3054 codec registers (nodes) access macros */ #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0)) #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) #define SET_REG_CACHE(codec,reg,val) \ snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val) struct si3054_spec { unsigned international; }; /* * Modem mixer */ #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff)) #define PRIVATE_REG(val) ((val>>16)&0xffff) #define PRIVATE_MASK(val) (val&0xffff) #define si3054_switch_info snd_ctl_boolean_mono_info static int si3054_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *uvalue) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); u16 reg = PRIVATE_REG(kcontrol->private_value); u16 mask = PRIVATE_MASK(kcontrol->private_value); uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ; return 0; } static int si3054_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *uvalue) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); u16 reg = PRIVATE_REG(kcontrol->private_value); u16 mask = PRIVATE_MASK(kcontrol->private_value); if (uvalue->value.integer.value[0]) SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask); else SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask); return 0; } #define SI3054_KCONTROL(kname,reg,mask) { \ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = kname, \ .subdevice = HDA_SUBDEV_NID_FLAG | reg, \ .info = si3054_switch_info, \ .get = si3054_switch_get, \ .put = si3054_switch_put, \ .private_value = PRIVATE_VALUE(reg,mask), \ } static const struct snd_kcontrol_new si3054_modem_mixer[] = { SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH), SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID), {} }; static int si3054_build_controls(struct hda_codec *codec) { return snd_hda_add_new_ctls(codec, si3054_modem_mixer); } /* * PCM callbacks */ static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { u16 val; SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate); val = GET_REG(codec, SI3054_LINE_LEVEL); val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)); val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)); SET_REG(codec, SI3054_LINE_LEVEL, val); snd_hda_codec_setup_stream(codec, hinfo->nid, stream_tag, 0, format); return 0; } static int si3054_pcm_open(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { static const unsigned int rates[] = { 8000, 9600, 16000 }; static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { .count = ARRAY_SIZE(rates), .list = rates, .mask = 0, }; substream->runtime->hw.period_bytes_min = 80; return snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); } static const struct hda_pcm_stream si3054_pcm = { .substreams = 1, .channels_min = 1, .channels_max = 1, .nid = 0x1, .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT, .formats = SNDRV_PCM_FMTBIT_S16_LE, .maxbps = 16, .ops = { .open = si3054_pcm_open, .prepare = si3054_pcm_prepare, }, }; static int si3054_build_pcms(struct hda_codec *codec) { struct hda_pcm *info; info = snd_hda_codec_pcm_new(codec, "Si3054 Modem"); if (!info) return -ENOMEM; info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm; info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm; info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = codec->core.mfg; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = codec->core.mfg; info->pcm_type = HDA_PCM_TYPE_MODEM; return 0; } /* * Init part */ static int si3054_init(struct hda_codec *codec) { struct si3054_spec *spec = codec->spec; unsigned wait_count; u16 val; if (snd_hdac_regmap_add_vendor_verb(&codec->core, SI3054_VERB_WRITE_NODE)) return -ENOMEM; snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0); snd_hda_codec_write(codec, codec->core.mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0); SET_REG(codec, SI3054_LINE_RATE, 9600); SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK); SET_REG(codec, SI3054_EXTENDED_MID, 0); wait_count = 10; do { msleep(2); val = GET_REG(codec, SI3054_EXTENDED_MID); } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--); if((val&SI3054_MEI_READY) != SI3054_MEI_READY) { codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val); /* let's pray that this is no fatal error */ /* return -EACCES; */ } SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff); SET_REG(codec, SI3054_GPIO_CFG, 0x0); SET_REG(codec, SI3054_MISC_AFE, 0); SET_REG(codec, SI3054_LINE_CFG1,0x200); if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) { codec_dbg(codec, "Link Frame Detect(FDT) is not ready (line status: %04x)\n", GET_REG(codec,SI3054_LINE_STATUS)); } spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL; return 0; } static void si3054_free(struct hda_codec *codec) { kfree(codec->spec); } /* */ static const struct hda_codec_ops si3054_patch_ops = { .build_controls = si3054_build_controls, .build_pcms = si3054_build_pcms, .init = si3054_init, .free = si3054_free, }; static int patch_si3054(struct hda_codec *codec) { struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (spec == NULL) return -ENOMEM; codec->spec = spec; codec->patch_ops = si3054_patch_ops; return 0; } /* * patch entries */ static const struct hda_device_id snd_hda_id_si3054[] = { HDA_CODEC_ENTRY(0x163c3055, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x163c3155, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x11c13026, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x11c13055, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x11c13155, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x10573055, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x10573057, "Si3054", patch_si3054), HDA_CODEC_ENTRY(0x10573155, "Si3054", patch_si3054), /* VIA HDA on Clevo m540 */ HDA_CODEC_ENTRY(0x11063288, "Si3054", patch_si3054), /* Asus A8J Modem (SM56) */ HDA_CODEC_ENTRY(0x15433155, "Si3054", patch_si3054), /* LG LW20 modem */ HDA_CODEC_ENTRY(0x18540018, "Si3054", patch_si3054), {} }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_si3054); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Si3054 HD-audio modem codec"); static struct hda_codec_driver si3054_driver = { .id = snd_hda_id_si3054, }; module_hda_codec_driver(si3054_driver);
linux-master
sound/pci/hda/patch_si3054.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip * * Copyright (C) 2021 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. */ #include <linux/init.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <linux/mutex.h> #include <linux/iopoll.h> #include "patch_cs8409.h" /****************************************************************************** * CS8409 Specific Functions ******************************************************************************/ static int cs8409_parse_auto_config(struct hda_codec *codec) { struct cs8409_spec *spec = codec->spec; int err; int i; err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); if (err < 0) return err; err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); if (err < 0) return err; /* keep the ADCs powered up when it's dynamically switchable */ if (spec->gen.dyn_adc_switch) { unsigned int done = 0; for (i = 0; i < spec->gen.input_mux.num_items; i++) { int idx = spec->gen.dyn_adc_idx[i]; if (done & (1 << idx)) continue; snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]); done |= 1 << idx; } } return 0; } static void cs8409_disable_i2c_clock_worker(struct work_struct *work); static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec) { struct cs8409_spec *spec; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return NULL; codec->spec = spec; spec->codec = codec; codec->power_save_node = 1; mutex_init(&spec->i2c_mux); INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker); snd_hda_gen_spec_init(&spec->gen); return spec; } static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx) { snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0); } static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx, unsigned int coef) { snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef); } /* * cs8409_enable_i2c_clock - Disable I2C clocks * @codec: the codec instance * Disable I2C clocks. * This must be called when the i2c mutex is unlocked. */ static void cs8409_disable_i2c_clock(struct hda_codec *codec) { struct cs8409_spec *spec = codec->spec; mutex_lock(&spec->i2c_mux); if (spec->i2c_clck_enabled) { cs8409_vendor_coef_set(spec->codec, 0x0, cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7); spec->i2c_clck_enabled = 0; } mutex_unlock(&spec->i2c_mux); } /* * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use */ static void cs8409_disable_i2c_clock_worker(struct work_struct *work) { struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work); cs8409_disable_i2c_clock(spec->codec); } /* * cs8409_enable_i2c_clock - Enable I2C clocks * @codec: the codec instance * Enable I2C clocks. * This must be called when the i2c mutex is locked. */ static void cs8409_enable_i2c_clock(struct hda_codec *codec) { struct cs8409_spec *spec = codec->spec; /* Cancel the disable timer, but do not wait for any running disable functions to finish. * If the disable timer runs out before cancel, the delayed work thread will be blocked, * waiting for the mutex to become unlocked. This mutex will be locked for the duration of * any i2c transaction, so the disable function will run to completion immediately * afterwards in the scenario. The next enable call will re-enable the clock, regardless. */ cancel_delayed_work(&spec->i2c_clk_work); if (!spec->i2c_clck_enabled) { cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8); spec->i2c_clck_enabled = 1; } queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25)); } /** * cs8409_i2c_wait_complete - Wait for I2C transaction * @codec: the codec instance * * Wait for I2C transaction to complete. * Return -ETIMEDOUT if transaction wait times out. */ static int cs8409_i2c_wait_complete(struct hda_codec *codec) { unsigned int retval; return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18, CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS); } /** * cs8409_set_i2c_dev_addr - Set i2c address for transaction * @codec: the codec instance * @addr: I2C Address */ static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr) { struct cs8409_spec *spec = codec->spec; if (spec->dev_addr != addr) { cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr); spec->dev_addr = addr; } } /** * cs8409_i2c_set_page - CS8409 I2C set page register. * @scodec: the codec instance * @i2c_reg: Page register * * Returns negative on error. */ static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg) { struct hda_codec *codec = scodec->codec; if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) { cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8); if (cs8409_i2c_wait_complete(codec) < 0) return -EIO; scodec->last_page = i2c_reg >> 8; } return 0; } /** * cs8409_i2c_read - CS8409 I2C Read. * @scodec: the codec instance * @addr: Register to read * * Returns negative on error, otherwise returns read value in bits 0-7. */ static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr) { struct hda_codec *codec = scodec->codec; struct cs8409_spec *spec = codec->spec; unsigned int i2c_reg_data; unsigned int read_data; if (scodec->suspended) return -EPERM; mutex_lock(&spec->i2c_mux); cs8409_enable_i2c_clock(codec); cs8409_set_i2c_dev_addr(codec, scodec->addr); if (cs8409_i2c_set_page(scodec, addr)) goto error; i2c_reg_data = (addr << 8) & 0x0ffff; cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); if (cs8409_i2c_wait_complete(codec) < 0) goto error; /* Register in bits 15-8 and the data in 7-0 */ read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD); mutex_unlock(&spec->i2c_mux); return read_data & 0x0ff; error: mutex_unlock(&spec->i2c_mux); codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); return -EIO; } /** * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence. * @scodec: the codec instance * @seq: Register Sequence to read * @count: Number of registeres to read * * Returns negative on error, values are read into value element of cs8409_i2c_param sequence. */ static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count) { struct hda_codec *codec = scodec->codec; struct cs8409_spec *spec = codec->spec; unsigned int i2c_reg_data; int i; if (scodec->suspended) return -EPERM; mutex_lock(&spec->i2c_mux); cs8409_set_i2c_dev_addr(codec, scodec->addr); for (i = 0; i < count; i++) { cs8409_enable_i2c_clock(codec); if (cs8409_i2c_set_page(scodec, seq[i].addr)) goto error; i2c_reg_data = (seq[i].addr << 8) & 0x0ffff; cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); if (cs8409_i2c_wait_complete(codec) < 0) goto error; seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff; } mutex_unlock(&spec->i2c_mux); return 0; error: mutex_unlock(&spec->i2c_mux); codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr); return -EIO; } /** * cs8409_i2c_write - CS8409 I2C Write. * @scodec: the codec instance * @addr: Register to write to * @value: Data to write * * Returns negative on error, otherwise returns 0. */ static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value) { struct hda_codec *codec = scodec->codec; struct cs8409_spec *spec = codec->spec; unsigned int i2c_reg_data; if (scodec->suspended) return -EPERM; mutex_lock(&spec->i2c_mux); cs8409_enable_i2c_clock(codec); cs8409_set_i2c_dev_addr(codec, scodec->addr); if (cs8409_i2c_set_page(scodec, addr)) goto error; i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff); cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); if (cs8409_i2c_wait_complete(codec) < 0) goto error; mutex_unlock(&spec->i2c_mux); return 0; error: mutex_unlock(&spec->i2c_mux); codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); return -EIO; } /** * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence. * @scodec: the codec instance * @seq: Register Sequence to write * @count: Number of registeres to write * * Returns negative on error. */ static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq, int count) { struct hda_codec *codec = scodec->codec; struct cs8409_spec *spec = codec->spec; unsigned int i2c_reg_data; int i; if (scodec->suspended) return -EPERM; mutex_lock(&spec->i2c_mux); cs8409_set_i2c_dev_addr(codec, scodec->addr); for (i = 0; i < count; i++) { cs8409_enable_i2c_clock(codec); if (cs8409_i2c_set_page(scodec, seq[i].addr)) goto error; i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff); cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); if (cs8409_i2c_wait_complete(codec) < 0) goto error; } mutex_unlock(&spec->i2c_mux); return 0; error: mutex_unlock(&spec->i2c_mux); codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr); return -EIO; } static int cs8409_init(struct hda_codec *codec) { int ret = snd_hda_gen_init(codec); if (!ret) snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT); return ret; } static int cs8409_build_controls(struct hda_codec *codec) { int err; err = snd_hda_gen_build_controls(codec); if (err < 0) return err; snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD); return 0; } /* Enable/Disable Unsolicited Response */ static void cs8409_enable_ur(struct hda_codec *codec, int flag) { struct cs8409_spec *spec = codec->spec; unsigned int ur_gpios = 0; int i; for (i = 0; i < spec->num_scodecs; i++) ur_gpios |= spec->scodecs[i]->irq_mask; snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, flag ? ur_gpios : 0); snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE, flag ? AC_UNSOL_ENABLED : 0); } static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid) { int caps; /* CS8409 is simple HDA bridge and intended to be used with a remote * companion codec. Most of input/output PIN(s) have only basic * capabilities. Receive and Transmit NID(s) have only OUTC and INC * capabilities and no presence detect capable (PDC) and call to * snd_hda_gen_build_controls() will mark them as non detectable * phantom jacks. However, a companion codec may be * connected to these pins which supports jack detect * capabilities. We have to override pin capabilities, * otherwise they will not be created as input devices. */ caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP); if (caps >= 0) snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP, (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT))); snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP)); } static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct cs8409_spec *spec = codec->spec; ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio); return 0; } static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct cs8409_spec *spec = codec->spec; unsigned int gpio_data; gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) | (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0); if (gpio_data == spec->gpio_data) return 0; spec->gpio_data = gpio_data; snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); return 1; } static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .info = snd_ctl_boolean_mono_info, .get = cs8409_spk_sw_gpio_get, .put = cs8409_spk_sw_gpio_put, }; /****************************************************************************** * CS42L42 Specific Functions ******************************************************************************/ int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo) { unsigned int ofs = get_amp_offset(kctrl); u8 chs = get_amp_channels(kctrl); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->value.integer.step = 1; uinfo->count = chs == 3 ? 2 : 1; switch (ofs) { case CS42L42_VOL_DAC: uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN; uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX; break; case CS42L42_VOL_ADC: uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN; uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX; break; default: break; } return 0; } int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) { struct hda_codec *codec = snd_kcontrol_chip(kctrl); struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; int chs = get_amp_channels(kctrl); unsigned int ofs = get_amp_offset(kctrl); long *valp = uctrl->value.integer.value; switch (ofs) { case CS42L42_VOL_DAC: if (chs & BIT(0)) *valp++ = cs42l42->vol[ofs]; if (chs & BIT(1)) *valp = cs42l42->vol[ofs+1]; break; case CS42L42_VOL_ADC: if (chs & BIT(0)) *valp = cs42l42->vol[ofs]; break; default: break; } return 0; } static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type, unsigned int chs, bool mute) { if (mute) { if (vol_type == CS42L42_VOL_DAC) { if (chs & BIT(0)) cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f); if (chs & BIT(1)) cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f); } else if (vol_type == CS42L42_VOL_ADC) { if (chs & BIT(0)) cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f); } } else { if (vol_type == CS42L42_VOL_DAC) { if (chs & BIT(0)) cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET]) & CS42L42_MIXER_CH_VOL_MASK); if (chs & BIT(1)) cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET]) & CS42L42_MIXER_CH_VOL_MASK); } else if (vol_type == CS42L42_VOL_ADC) { if (chs & BIT(0)) cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, cs42l42->vol[CS42L42_ADC_VOL_OFFSET] & CS42L42_REG_AMIC_VOL_MASK); } } } int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) { struct hda_codec *codec = snd_kcontrol_chip(kctrl); struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; int chs = get_amp_channels(kctrl); unsigned int ofs = get_amp_offset(kctrl); long *valp = uctrl->value.integer.value; switch (ofs) { case CS42L42_VOL_DAC: if (chs & BIT(0)) cs42l42->vol[ofs] = *valp; if (chs & BIT(1)) { valp++; cs42l42->vol[ofs + 1] = *valp; } if (spec->playback_started) cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false); break; case CS42L42_VOL_ADC: if (chs & BIT(0)) cs42l42->vol[ofs] = *valp; if (spec->capture_started) cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false); break; default: break; } return 0; } static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42; int i; bool mute; switch (action) { case HDA_GEN_PCM_ACT_PREPARE: mute = false; spec->playback_started = 1; break; case HDA_GEN_PCM_ACT_CLEANUP: mute = true; spec->playback_started = 0; break; default: return; } for (i = 0; i < spec->num_scodecs; i++) { cs42l42 = spec->scodecs[i]; cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute); } } static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream, int action) { struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42; int i; bool mute; switch (action) { case HDA_GEN_PCM_ACT_PREPARE: mute = false; spec->capture_started = 1; break; case HDA_GEN_PCM_ACT_CLEANUP: mute = true; spec->capture_started = 0; break; default: return; } for (i = 0; i < spec->num_scodecs; i++) { cs42l42 = spec->scodecs[i]; cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute); } } /* Configure CS42L42 slave codec for jack autodetect */ static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42) { cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz); /* Clear WAKE# */ cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1); /* Wait ~2.5ms */ usleep_range(2500, 3000); /* Set mode WAKE# output follows the combination logic directly */ cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0); /* Clear interrupts status */ cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); /* Enable interrupt */ cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); } /* Enable and run CS42L42 slave codec jack auto detect */ static void cs42l42_run_jack_detect(struct sub_codec *cs42l42) { /* Clear interrupts */ cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1); cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF); cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87); cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86); cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07); cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD); cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); /* Wait ~20ms*/ usleep_range(20000, 25000); cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77); cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0); } static int cs42l42_manual_hs_det(struct sub_codec *cs42l42) { unsigned int hs_det_status; unsigned int hs_det_comp1; unsigned int hs_det_comp2; unsigned int hs_det_sw; unsigned int hs_type; /* Set hs detect to manual, active mode */ cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, (1 << CS42L42_HSDET_CTRL_SHIFT) | (0 << CS42L42_HSDET_SET_SHIFT) | (0 << CS42L42_HSBIAS_REF_SHIFT) | (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); /* Configure HS DET comparator reference levels. */ cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); msleep(100); hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> CS42L42_HSDET_COMP1_OUT_SHIFT; hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> CS42L42_HSDET_COMP2_OUT_SHIFT; /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); msleep(100); hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; /* Use Comparator 1 with 1.25V Threshold. */ switch (hs_det_comp1) { case CS42L42_HSDET_COMP_TYPE1: hs_type = CS42L42_PLUG_CTIA; hs_det_sw = CS42L42_HSDET_SW_TYPE1; break; case CS42L42_HSDET_COMP_TYPE2: hs_type = CS42L42_PLUG_OMTP; hs_det_sw = CS42L42_HSDET_SW_TYPE2; break; default: /* Fallback to Comparator 2 with 1.75V Threshold. */ switch (hs_det_comp2) { case CS42L42_HSDET_COMP_TYPE1: hs_type = CS42L42_PLUG_CTIA; hs_det_sw = CS42L42_HSDET_SW_TYPE1; break; case CS42L42_HSDET_COMP_TYPE2: hs_type = CS42L42_PLUG_OMTP; hs_det_sw = CS42L42_HSDET_SW_TYPE2; break; case CS42L42_HSDET_COMP_TYPE3: hs_type = CS42L42_PLUG_HEADPHONE; hs_det_sw = CS42L42_HSDET_SW_TYPE3; break; default: hs_type = CS42L42_PLUG_INVALID; hs_det_sw = CS42L42_HSDET_SW_TYPE4; break; } } /* Set Switches */ cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw); /* Set HSDET mode to Manual—Disabled */ cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, (0 << CS42L42_HSDET_CTRL_SHIFT) | (0 << CS42L42_HSDET_SET_SHIFT) | (0 << CS42L42_HSBIAS_REF_SHIFT) | (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); /* Configure HS DET comparator reference levels. */ cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); return hs_type; } static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status) { int status_changed = 0; /* TIP_SENSE INSERT/REMOVE */ switch (reg_ts_status) { case CS42L42_TS_PLUG: if (cs42l42->no_type_dect) { status_changed = 1; cs42l42->hp_jack_in = 1; cs42l42->mic_jack_in = 0; } else { cs42l42_run_jack_detect(cs42l42); } break; case CS42L42_TS_UNPLUG: status_changed = 1; cs42l42->hp_jack_in = 0; cs42l42->mic_jack_in = 0; break; default: /* jack in transition */ break; } codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status); return status_changed; } static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42) { int current_plug_status; int status_changed = 0; int reg_cdc_status; int reg_hs_status; int reg_ts_status; int type; /* Read jack detect status registers */ reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); /* If status values are < 0, read error has occurred. */ if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0) return -EIO; current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> CS42L42_TS_PLUG_SHIFT; /* HSDET_AUTO_DONE */ if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) { /* Disable HSDET_AUTO_DONE */ cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF); type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT; /* Configure the HSDET mode. */ cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); if (cs42l42->no_type_dect) { status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); } else { if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) { codec_dbg(cs42l42->codec, "Auto detect value not valid (%d), running manual det\n", type); type = cs42l42_manual_hs_det(cs42l42); } switch (type) { case CS42L42_PLUG_CTIA: case CS42L42_PLUG_OMTP: status_changed = 1; cs42l42->hp_jack_in = 1; cs42l42->mic_jack_in = 1; break; case CS42L42_PLUG_HEADPHONE: status_changed = 1; cs42l42->hp_jack_in = 1; cs42l42->mic_jack_in = 0; break; default: status_changed = 1; cs42l42->hp_jack_in = 0; cs42l42->mic_jack_in = 0; break; } codec_dbg(cs42l42->codec, "Detection done (%d)\n", type); } /* Enable the HPOUT ground clamp and configure the HP pull-down */ cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02); /* Re-Enable Tip Sense Interrupt */ cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); } else { status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); } return status_changed; } static void cs42l42_resume(struct sub_codec *cs42l42) { struct hda_codec *codec = cs42l42->codec; struct cs8409_spec *spec = codec->spec; struct cs8409_i2c_param irq_regs[] = { { CS42L42_CODEC_STATUS, 0x00 }, { CS42L42_DET_INT_STATUS1, 0x00 }, { CS42L42_DET_INT_STATUS2, 0x00 }, { CS42L42_TSRS_PLUG_STATUS, 0x00 }, }; int fsv_old, fsv_new; /* Bring CS42L42 out of Reset */ spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); spec->gpio_data |= cs42l42->reset_gpio; snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); usleep_range(10000, 15000); cs42l42->suspended = 0; /* Initialize CS42L42 companion codec */ cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num); msleep(CS42L42_INIT_TIMEOUT_MS); /* Clear interrupts, by reading interrupt status registers */ cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs)); fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL); if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB) fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK; else fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK; if (fsv_new != fsv_old) cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new); /* we have to explicitly allow unsol event handling even during the * resume phase so that the jack event is processed properly */ snd_hda_codec_allow_unsol_events(cs42l42->codec); cs42l42_enable_jack_detect(cs42l42); } #ifdef CONFIG_PM static void cs42l42_suspend(struct sub_codec *cs42l42) { struct hda_codec *codec = cs42l42->codec; struct cs8409_spec *spec = codec->spec; int reg_cdc_status = 0; const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = { { CS42L42_DAC_CTL2, 0x02 }, { CS42L42_HS_CLAMP_DISABLE, 0x00 }, { CS42L42_MIXER_CHA_VOL, 0x3F }, { CS42L42_MIXER_ADC_VOL, 0x3F }, { CS42L42_MIXER_CHB_VOL, 0x3F }, { CS42L42_HP_CTL, 0x0F }, { CS42L42_ASP_RX_DAI0_EN, 0x00 }, { CS42L42_ASP_CLK_CFG, 0x00 }, { CS42L42_PWR_CTL1, 0xFE }, { CS42L42_PWR_CTL2, 0x8C }, { CS42L42_PWR_CTL1, 0xFF }, }; cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq)); if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status, (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US, true, cs42l42, CS42L42_CODEC_STATUS) < 0) codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n"); /* Power down CS42L42 ASP/EQ/MIX/HP */ cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C); cs42l42->suspended = 1; cs42l42->last_page = 0; cs42l42->hp_jack_in = 0; cs42l42->mic_jack_in = 0; /* Put CS42L42 into Reset */ spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); spec->gpio_data &= ~cs42l42->reset_gpio; snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } #endif static void cs8409_free(struct hda_codec *codec) { struct cs8409_spec *spec = codec->spec; /* Cancel i2c clock disable timer, and disable clock if left enabled */ cancel_delayed_work_sync(&spec->i2c_clk_work); cs8409_disable_i2c_clock(codec); snd_hda_gen_free(codec); } /****************************************************************************** * BULLSEYE / WARLOCK / CYBORG Specific Functions * CS8409/CS42L42 ******************************************************************************/ /* * In the case of CS8409 we do not have unsolicited events from NID's 0x24 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will * generate interrupt via gpio 4 to notify jack events. We have to overwrite * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers * and then notify status via generic snd_hda_jack_unsol_event() call. */ static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res) { struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; struct hda_jack_tbl *jk; /* jack_unsol_event() will be called every time gpio line changing state. * In this case gpio4 line goes up as a result of reading interrupt status * registers in previous cs8409_jack_unsol_event() call. * We don't need to handle this event, ignoring... */ if (res & cs42l42->irq_mask) return; if (cs42l42_jack_unsol_event(cs42l42)) { snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID, cs42l42->hp_jack_in ? 0 : PIN_OUT); /* Report jack*/ jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0); if (jk) snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); /* Report jack*/ jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0); if (jk) snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); } } #ifdef CONFIG_PM /* Manage PDREF, when transition to D3hot */ static int cs8409_cs42l42_suspend(struct hda_codec *codec) { struct cs8409_spec *spec = codec->spec; int i; spec->init_done = 0; cs8409_enable_ur(codec, 0); for (i = 0; i < spec->num_scodecs; i++) cs42l42_suspend(spec->scodecs[i]); /* Cancel i2c clock disable timer, and disable clock if left enabled */ cancel_delayed_work_sync(&spec->i2c_clk_work); cs8409_disable_i2c_clock(codec); snd_hda_shutup_pins(codec); return 0; } #endif /* Vendor specific HW configuration * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... */ static void cs8409_cs42l42_hw_init(struct hda_codec *codec) { const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg; const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn; struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; if (spec->gpio_mask) { snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK, spec->gpio_mask); snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION, spec->gpio_dir); snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } for (; seq->nid; seq++) cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); if (codec->fixup_id == CS8409_BULLSEYE) { for (; seq_bullseye->nid; seq_bullseye++) cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff); } switch (codec->fixup_id) { case CS8409_CYBORG: case CS8409_WARLOCK_MLK_DUAL_MIC: /* DMIC1_MO=00b, DMIC1/2_SR=1 */ cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003); break; case CS8409_ODIN: /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */ cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00); break; default: break; } cs42l42_resume(cs42l42); /* Enable Unsolicited Response */ cs8409_enable_ur(codec, 1); } static const struct hda_codec_ops cs8409_cs42l42_patch_ops = { .build_controls = cs8409_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = cs8409_init, .free = cs8409_free, .unsol_event = cs8409_cs42l42_jack_unsol_event, #ifdef CONFIG_PM .suspend = cs8409_cs42l42_suspend, #endif }; static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, unsigned int *res) { struct hda_codec *codec = container_of(dev, struct hda_codec, core); struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; unsigned int nid = ((cmd >> 20) & 0x07f); unsigned int verb = ((cmd >> 8) & 0x0fff); /* CS8409 pins have no AC_PINSENSE_PRESENCE * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34 * and return correct pin sense values for read_pin_sense() call from * hda_jack based on CS42L42 jack detect status. */ switch (nid) { case CS8409_CS42L42_HP_PIN_NID: if (verb == AC_VERB_GET_PIN_SENSE) { *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; return 0; } break; case CS8409_CS42L42_AMIC_PIN_NID: if (verb == AC_VERB_GET_PIN_SENSE) { *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; return 0; } break; default: break; } return spec->exec_verb(dev, cmd, flags, res); } void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct cs8409_spec *spec = codec->spec; switch (action) { case HDA_FIXUP_ACT_PRE_PROBE: snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs); /* verb exec op override */ spec->exec_verb = codec->core.exec_verb; codec->core.exec_verb = cs8409_cs42l42_exec_verb; spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec; spec->num_scodecs = 1; spec->scodecs[CS8409_CODEC0]->codec = codec; codec->patch_ops = cs8409_cs42l42_patch_ops; spec->gen.suppress_auto_mute = 1; spec->gen.no_primary_hp = 1; spec->gen.suppress_vmaster = 1; spec->speaker_pdn_gpio = 0; /* GPIO 5 out, 3,4 in */ spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio; spec->gpio_data = 0; spec->gpio_mask = 0x03f; /* Basic initial sequence for specific hw configuration */ snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs); cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID); cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID); spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020; switch (codec->fixup_id) { case CS8409_CYBORG: spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; break; case CS8409_ODIN: spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; break; case CS8409_WARLOCK_MLK: case CS8409_WARLOCK_MLK_DUAL_MIC: spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; break; default: spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; break; } if (spec->speaker_pdn_gpio > 0) { spec->gpio_dir |= spec->speaker_pdn_gpio; spec->gpio_data |= spec->speaker_pdn_gpio; } break; case HDA_FIXUP_ACT_PROBE: /* Fix Sample Rate to 48kHz */ spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; /* add hooks */ spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; if (codec->fixup_id != CS8409_ODIN) /* Set initial DMIC volume to -26 dB */ snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID, HDA_INPUT, 0, 0xff, 0x19); snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", &cs42l42_dac_volume_mixer); snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer); if (spec->speaker_pdn_gpio > 0) snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch", &cs8409_spk_sw_ctrl); /* Disable Unsolicited Response during boot */ cs8409_enable_ur(codec, 0); snd_hda_codec_set_name(codec, "CS8409/CS42L42"); break; case HDA_FIXUP_ACT_INIT: cs8409_cs42l42_hw_init(codec); spec->init_done = 1; if (spec->init_done && spec->build_ctrl_done && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); break; case HDA_FIXUP_ACT_BUILD: spec->build_ctrl_done = 1; /* Run jack auto detect first time on boot * after controls have been added, to check if jack has * been already plugged in. * Run immediately after init. */ if (spec->init_done && spec->build_ctrl_done && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); break; default: break; } } /****************************************************************************** * Dolphin Specific Functions * CS8409/ 2 X CS42L42 ******************************************************************************/ /* * In the case of CS8409 we do not have unsolicited events when * hs mic and hp are connected. Companion codec CS42L42 will * generate interrupt via irq_mask to notify jack events. We have to overwrite * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers * and then notify status via generic snd_hda_jack_unsol_event() call. */ static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res) { struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42; struct hda_jack_tbl *jk; cs42l42 = spec->scodecs[CS8409_CODEC0]; if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && cs42l42_jack_unsol_event(cs42l42)) { jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0); if (jk) snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0); if (jk) snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); } cs42l42 = spec->scodecs[CS8409_CODEC1]; if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && cs42l42_jack_unsol_event(cs42l42)) { jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0); if (jk) snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & AC_UNSOL_RES_TAG); } } /* Vendor specific HW configuration * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... */ static void dolphin_hw_init(struct hda_codec *codec) { const struct cs8409_cir_param *seq = dolphin_hw_cfg; struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42; int i; if (spec->gpio_mask) { snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK, spec->gpio_mask); snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION, spec->gpio_dir); snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); } for (; seq->nid; seq++) cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); for (i = 0; i < spec->num_scodecs; i++) { cs42l42 = spec->scodecs[i]; cs42l42_resume(cs42l42); } /* Enable Unsolicited Response */ cs8409_enable_ur(codec, 1); } static const struct hda_codec_ops cs8409_dolphin_patch_ops = { .build_controls = cs8409_build_controls, .build_pcms = snd_hda_gen_build_pcms, .init = cs8409_init, .free = cs8409_free, .unsol_event = dolphin_jack_unsol_event, #ifdef CONFIG_PM .suspend = cs8409_cs42l42_suspend, #endif }; static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, unsigned int *res) { struct hda_codec *codec = container_of(dev, struct hda_codec, core); struct cs8409_spec *spec = codec->spec; struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; unsigned int nid = ((cmd >> 20) & 0x07f); unsigned int verb = ((cmd >> 8) & 0x0fff); /* CS8409 pins have no AC_PINSENSE_PRESENCE * capabilities. We have to intercept calls for CS42L42 pins * and return correct pin sense values for read_pin_sense() call from * hda_jack based on CS42L42 jack detect status. */ switch (nid) { case DOLPHIN_HP_PIN_NID: case DOLPHIN_LO_PIN_NID: if (nid == DOLPHIN_LO_PIN_NID) cs42l42 = spec->scodecs[CS8409_CODEC1]; if (verb == AC_VERB_GET_PIN_SENSE) { *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; return 0; } break; case DOLPHIN_AMIC_PIN_NID: if (verb == AC_VERB_GET_PIN_SENSE) { *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; return 0; } break; default: break; } return spec->exec_verb(dev, cmd, flags, res); } void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) { struct cs8409_spec *spec = codec->spec; struct snd_kcontrol_new *kctrl; int i; switch (action) { case HDA_FIXUP_ACT_PRE_PROBE: snd_hda_add_verbs(codec, dolphin_init_verbs); /* verb exec op override */ spec->exec_verb = codec->core.exec_verb; codec->core.exec_verb = dolphin_exec_verb; spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0; spec->scodecs[CS8409_CODEC0]->codec = codec; spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1; spec->scodecs[CS8409_CODEC1]->codec = codec; spec->num_scodecs = 2; codec->patch_ops = cs8409_dolphin_patch_ops; /* GPIO 1,5 out, 0,4 in */ spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio | spec->scodecs[CS8409_CODEC1]->reset_gpio; spec->gpio_data = 0; spec->gpio_mask = 0x03f; /* Basic initial sequence for specific hw configuration */ snd_hda_sequence_write(codec, dolphin_init_verbs); snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true, SND_JACK_HEADPHONE, NULL); snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true, SND_JACK_MICROPHONE, NULL); cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID); cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID); cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID); spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; break; case HDA_FIXUP_ACT_PROBE: /* Fix Sample Rate to 48kHz */ spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; /* add hooks */ spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", &cs42l42_dac_volume_mixer); snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer); kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume", &cs42l42_dac_volume_mixer); /* Update Line Out kcontrol template */ kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1, HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE; cs8409_enable_ur(codec, 0); snd_hda_codec_set_name(codec, "CS8409/CS42L42"); break; case HDA_FIXUP_ACT_INIT: dolphin_hw_init(codec); spec->init_done = 1; if (spec->init_done && spec->build_ctrl_done) { for (i = 0; i < spec->num_scodecs; i++) { if (!spec->scodecs[i]->hp_jack_in) cs42l42_run_jack_detect(spec->scodecs[i]); } } break; case HDA_FIXUP_ACT_BUILD: spec->build_ctrl_done = 1; /* Run jack auto detect first time on boot * after controls have been added, to check if jack has * been already plugged in. * Run immediately after init. */ if (spec->init_done && spec->build_ctrl_done) { for (i = 0; i < spec->num_scodecs; i++) { if (!spec->scodecs[i]->hp_jack_in) cs42l42_run_jack_detect(spec->scodecs[i]); } } break; default: break; } } static int patch_cs8409(struct hda_codec *codec) { int err; if (!cs8409_alloc_spec(codec)) return -ENOMEM; snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups); codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id, codec->bus->pci->subsystem_vendor, codec->bus->pci->subsystem_device); snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); err = cs8409_parse_auto_config(codec); if (err < 0) { cs8409_free(codec); return err; } snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); return 0; } static const struct hda_device_id snd_hda_id_cs8409[] = { HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409); static struct hda_codec_driver cs8409_driver = { .id = snd_hda_id_cs8409, }; module_hda_codec_driver(cs8409_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cirrus Logic HDA bridge");
linux-master
sound/pci/hda/patch_cs8409.c
// SPDX-License-Identifier: GPL-2.0-only /* * sysfs interface for HD-audio codec * * Copyright (c) 2014 Takashi Iwai <[email protected]> * * split from hda_hwdep.c */ #include <linux/init.h> #include <linux/slab.h> #include <linux/compat.h> #include <linux/mutex.h> #include <linux/ctype.h> #include <linux/string.h> #include <linux/export.h> #include <sound/core.h> #include <sound/hda_codec.h> #include "hda_local.h" #include <sound/hda_hwdep.h> #include <sound/minors.h> /* hint string pair */ struct hda_hint { const char *key; const char *val; /* contained in the same alloc as key */ }; #ifdef CONFIG_PM static ssize_t power_on_acct_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); snd_hda_update_power_acct(codec); return sysfs_emit(buf, "%u\n", jiffies_to_msecs(codec->power_on_acct)); } static ssize_t power_off_acct_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); snd_hda_update_power_acct(codec); return sysfs_emit(buf, "%u\n", jiffies_to_msecs(codec->power_off_acct)); } static DEVICE_ATTR_RO(power_on_acct); static DEVICE_ATTR_RO(power_off_acct); #endif /* CONFIG_PM */ #define CODEC_INFO_SHOW(type, field) \ static ssize_t type##_show(struct device *dev, \ struct device_attribute *attr, \ char *buf) \ { \ struct hda_codec *codec = dev_get_drvdata(dev); \ return sysfs_emit(buf, "0x%x\n", codec->field); \ } #define CODEC_INFO_STR_SHOW(type, field) \ static ssize_t type##_show(struct device *dev, \ struct device_attribute *attr, \ char *buf) \ { \ struct hda_codec *codec = dev_get_drvdata(dev); \ return sysfs_emit(buf, "%s\n", \ codec->field ? codec->field : ""); \ } CODEC_INFO_SHOW(vendor_id, core.vendor_id); CODEC_INFO_SHOW(subsystem_id, core.subsystem_id); CODEC_INFO_SHOW(revision_id, core.revision_id); CODEC_INFO_SHOW(afg, core.afg); CODEC_INFO_SHOW(mfg, core.mfg); CODEC_INFO_STR_SHOW(vendor_name, core.vendor_name); CODEC_INFO_STR_SHOW(chip_name, core.chip_name); CODEC_INFO_STR_SHOW(modelname, modelname); static ssize_t pin_configs_show(struct hda_codec *codec, struct snd_array *list, char *buf) { const struct hda_pincfg *pin; int i, len = 0; mutex_lock(&codec->user_mutex); snd_array_for_each(list, i, pin) { len += sysfs_emit_at(buf, len, "0x%02x 0x%08x\n", pin->nid, pin->cfg); } mutex_unlock(&codec->user_mutex); return len; } static ssize_t init_pin_configs_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); return pin_configs_show(codec, &codec->init_pins, buf); } static ssize_t driver_pin_configs_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); return pin_configs_show(codec, &codec->driver_pins, buf); } #ifdef CONFIG_SND_HDA_RECONFIG /* * sysfs interface */ static int clear_codec(struct hda_codec *codec) { int err; err = snd_hda_codec_reset(codec); if (err < 0) { codec_err(codec, "The codec is being used, can't free.\n"); return err; } snd_hda_sysfs_clear(codec); return 0; } static int reconfig_codec(struct hda_codec *codec) { int err; snd_hda_power_up(codec); codec_info(codec, "hda-codec: reconfiguring\n"); err = snd_hda_codec_reset(codec); if (err < 0) { codec_err(codec, "The codec is being used, can't reconfigure.\n"); goto error; } err = device_reprobe(hda_codec_dev(codec)); if (err < 0) goto error; err = snd_card_register(codec->card); error: snd_hda_power_down(codec); return err; } /* * allocate a string at most len chars, and remove the trailing EOL */ static char *kstrndup_noeol(const char *src, size_t len) { char *s = kstrndup(src, len, GFP_KERNEL); char *p; if (!s) return NULL; p = strchr(s, '\n'); if (p) *p = 0; return s; } #define CODEC_INFO_STORE(type, field) \ static ssize_t type##_store(struct device *dev, \ struct device_attribute *attr, \ const char *buf, size_t count) \ { \ struct hda_codec *codec = dev_get_drvdata(dev); \ unsigned long val; \ int err = kstrtoul(buf, 0, &val); \ if (err < 0) \ return err; \ codec->field = val; \ return count; \ } #define CODEC_INFO_STR_STORE(type, field) \ static ssize_t type##_store(struct device *dev, \ struct device_attribute *attr, \ const char *buf, size_t count) \ { \ struct hda_codec *codec = dev_get_drvdata(dev); \ char *s = kstrndup_noeol(buf, 64); \ if (!s) \ return -ENOMEM; \ kfree(codec->field); \ codec->field = s; \ return count; \ } CODEC_INFO_STORE(vendor_id, core.vendor_id); CODEC_INFO_STORE(subsystem_id, core.subsystem_id); CODEC_INFO_STORE(revision_id, core.revision_id); CODEC_INFO_STR_STORE(vendor_name, core.vendor_name); CODEC_INFO_STR_STORE(chip_name, core.chip_name); CODEC_INFO_STR_STORE(modelname, modelname); #define CODEC_ACTION_STORE(type) \ static ssize_t type##_store(struct device *dev, \ struct device_attribute *attr, \ const char *buf, size_t count) \ { \ struct hda_codec *codec = dev_get_drvdata(dev); \ int err = 0; \ if (*buf) \ err = type##_codec(codec); \ return err < 0 ? err : count; \ } CODEC_ACTION_STORE(reconfig); CODEC_ACTION_STORE(clear); static ssize_t init_verbs_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); const struct hda_verb *v; int i, len = 0; mutex_lock(&codec->user_mutex); snd_array_for_each(&codec->init_verbs, i, v) { len += sysfs_emit_at(buf, len, "0x%02x 0x%03x 0x%04x\n", v->nid, v->verb, v->param); } mutex_unlock(&codec->user_mutex); return len; } static int parse_init_verbs(struct hda_codec *codec, const char *buf) { struct hda_verb *v; int nid, verb, param; if (sscanf(buf, "%i %i %i", &nid, &verb, &param) != 3) return -EINVAL; if (!nid || !verb) return -EINVAL; mutex_lock(&codec->user_mutex); v = snd_array_new(&codec->init_verbs); if (!v) { mutex_unlock(&codec->user_mutex); return -ENOMEM; } v->nid = nid; v->verb = verb; v->param = param; mutex_unlock(&codec->user_mutex); return 0; } static ssize_t init_verbs_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct hda_codec *codec = dev_get_drvdata(dev); int err = parse_init_verbs(codec, buf); if (err < 0) return err; return count; } static ssize_t hints_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); const struct hda_hint *hint; int i, len = 0; mutex_lock(&codec->user_mutex); snd_array_for_each(&codec->hints, i, hint) { len += sysfs_emit_at(buf, len, "%s = %s\n", hint->key, hint->val); } mutex_unlock(&codec->user_mutex); return len; } static struct hda_hint *get_hint(struct hda_codec *codec, const char *key) { struct hda_hint *hint; int i; snd_array_for_each(&codec->hints, i, hint) { if (!strcmp(hint->key, key)) return hint; } return NULL; } static void remove_trail_spaces(char *str) { char *p; if (!*str) return; p = str + strlen(str) - 1; for (; isspace(*p); p--) { *p = 0; if (p == str) return; } } #define MAX_HINTS 1024 static int parse_hints(struct hda_codec *codec, const char *buf) { char *key, *val; struct hda_hint *hint; int err = 0; buf = skip_spaces(buf); if (!*buf || *buf == '#' || *buf == '\n') return 0; if (*buf == '=') return -EINVAL; key = kstrndup_noeol(buf, 1024); if (!key) return -ENOMEM; /* extract key and val */ val = strchr(key, '='); if (!val) { kfree(key); return -EINVAL; } *val++ = 0; val = skip_spaces(val); remove_trail_spaces(key); remove_trail_spaces(val); mutex_lock(&codec->user_mutex); hint = get_hint(codec, key); if (hint) { /* replace */ kfree(hint->key); hint->key = key; hint->val = val; goto unlock; } /* allocate a new hint entry */ if (codec->hints.used >= MAX_HINTS) hint = NULL; else hint = snd_array_new(&codec->hints); if (hint) { hint->key = key; hint->val = val; } else { err = -ENOMEM; } unlock: mutex_unlock(&codec->user_mutex); if (err) kfree(key); return err; } static ssize_t hints_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct hda_codec *codec = dev_get_drvdata(dev); int err = parse_hints(codec, buf); if (err < 0) return err; return count; } static ssize_t user_pin_configs_show(struct device *dev, struct device_attribute *attr, char *buf) { struct hda_codec *codec = dev_get_drvdata(dev); return pin_configs_show(codec, &codec->user_pins, buf); } static int parse_user_pin_configs(struct hda_codec *codec, const char *buf) { int nid, cfg, err; if (sscanf(buf, "%i %i", &nid, &cfg) != 2) return -EINVAL; if (!nid) return -EINVAL; mutex_lock(&codec->user_mutex); err = snd_hda_add_pincfg(codec, &codec->user_pins, nid, cfg); mutex_unlock(&codec->user_mutex); return err; } static ssize_t user_pin_configs_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct hda_codec *codec = dev_get_drvdata(dev); int err = parse_user_pin_configs(codec, buf); if (err < 0) return err; return count; } /* sysfs attributes exposed only when CONFIG_SND_HDA_RECONFIG=y */ static DEVICE_ATTR_RW(init_verbs); static DEVICE_ATTR_RW(hints); static DEVICE_ATTR_RW(user_pin_configs); static DEVICE_ATTR_WO(reconfig); static DEVICE_ATTR_WO(clear); /** * snd_hda_get_hint - Look for hint string * @codec: the HDA codec * @key: the hint key string * * Look for a hint key/value pair matching with the given key string * and returns the value string. If nothing found, returns NULL. */ const char *snd_hda_get_hint(struct hda_codec *codec, const char *key) { struct hda_hint *hint = get_hint(codec, key); return hint ? hint->val : NULL; } EXPORT_SYMBOL_GPL(snd_hda_get_hint); /** * snd_hda_get_bool_hint - Get a boolean hint value * @codec: the HDA codec * @key: the hint key string * * Look for a hint key/value pair matching with the given key string * and returns a boolean value parsed from the value. If no matching * key is found, return a negative value. */ int snd_hda_get_bool_hint(struct hda_codec *codec, const char *key) { const char *p; int ret; mutex_lock(&codec->user_mutex); p = snd_hda_get_hint(codec, key); if (!p || !*p) ret = -ENOENT; else { switch (toupper(*p)) { case 'T': /* true */ case 'Y': /* yes */ case '1': ret = 1; break; default: ret = 0; break; } } mutex_unlock(&codec->user_mutex); return ret; } EXPORT_SYMBOL_GPL(snd_hda_get_bool_hint); /** * snd_hda_get_int_hint - Get an integer hint value * @codec: the HDA codec * @key: the hint key string * @valp: pointer to store a value * * Look for a hint key/value pair matching with the given key string * and stores the integer value to @valp. If no matching key is found, * return a negative error code. Otherwise it returns zero. */ int snd_hda_get_int_hint(struct hda_codec *codec, const char *key, int *valp) { const char *p; unsigned long val; int ret; mutex_lock(&codec->user_mutex); p = snd_hda_get_hint(codec, key); if (!p) ret = -ENOENT; else if (kstrtoul(p, 0, &val)) ret = -EINVAL; else { *valp = val; ret = 0; } mutex_unlock(&codec->user_mutex); return ret; } EXPORT_SYMBOL_GPL(snd_hda_get_int_hint); #endif /* CONFIG_SND_HDA_RECONFIG */ /* * common sysfs attributes */ #ifdef CONFIG_SND_HDA_RECONFIG #define RECONFIG_DEVICE_ATTR(name) DEVICE_ATTR_RW(name) #else #define RECONFIG_DEVICE_ATTR(name) DEVICE_ATTR_RO(name) #endif static RECONFIG_DEVICE_ATTR(vendor_id); static RECONFIG_DEVICE_ATTR(subsystem_id); static RECONFIG_DEVICE_ATTR(revision_id); static DEVICE_ATTR_RO(afg); static DEVICE_ATTR_RO(mfg); static RECONFIG_DEVICE_ATTR(vendor_name); static RECONFIG_DEVICE_ATTR(chip_name); static RECONFIG_DEVICE_ATTR(modelname); static DEVICE_ATTR_RO(init_pin_configs); static DEVICE_ATTR_RO(driver_pin_configs); #ifdef CONFIG_SND_HDA_PATCH_LOADER /* parser mode */ enum { LINE_MODE_NONE, LINE_MODE_CODEC, LINE_MODE_MODEL, LINE_MODE_PINCFG, LINE_MODE_VERB, LINE_MODE_HINT, LINE_MODE_VENDOR_ID, LINE_MODE_SUBSYSTEM_ID, LINE_MODE_REVISION_ID, LINE_MODE_CHIP_NAME, NUM_LINE_MODES, }; static inline int strmatch(const char *a, const char *b) { return strncasecmp(a, b, strlen(b)) == 0; } /* parse the contents after the line "[codec]" * accept only the line with three numbers, and assign the current codec */ static void parse_codec_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { int vendorid, subid, caddr; struct hda_codec *codec; *codecp = NULL; if (sscanf(buf, "%i %i %i", &vendorid, &subid, &caddr) == 3) { list_for_each_codec(codec, bus) { if ((vendorid <= 0 || codec->core.vendor_id == vendorid) && (subid <= 0 || codec->core.subsystem_id == subid) && codec->core.addr == caddr) { *codecp = codec; break; } } } } /* parse the contents after the other command tags, [pincfg], [verb], * [vendor_id], [subsystem_id], [revision_id], [chip_name], [hint] and [model] * just pass to the sysfs helper (only when any codec was specified) */ static void parse_pincfg_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { parse_user_pin_configs(*codecp, buf); } static void parse_verb_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { parse_init_verbs(*codecp, buf); } static void parse_hint_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { parse_hints(*codecp, buf); } static void parse_model_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { kfree((*codecp)->modelname); (*codecp)->modelname = kstrdup(buf, GFP_KERNEL); } static void parse_chip_name_mode(char *buf, struct hda_bus *bus, struct hda_codec **codecp) { snd_hda_codec_set_name(*codecp, buf); } #define DEFINE_PARSE_ID_MODE(name) \ static void parse_##name##_mode(char *buf, struct hda_bus *bus, \ struct hda_codec **codecp) \ { \ unsigned long val; \ if (!kstrtoul(buf, 0, &val)) \ (*codecp)->core.name = val; \ } DEFINE_PARSE_ID_MODE(vendor_id); DEFINE_PARSE_ID_MODE(subsystem_id); DEFINE_PARSE_ID_MODE(revision_id); struct hda_patch_item { const char *tag; const char *alias; void (*parser)(char *buf, struct hda_bus *bus, struct hda_codec **retc); }; static const struct hda_patch_item patch_items[NUM_LINE_MODES] = { [LINE_MODE_CODEC] = { .tag = "[codec]", .parser = parse_codec_mode, }, [LINE_MODE_MODEL] = { .tag = "[model]", .parser = parse_model_mode, }, [LINE_MODE_VERB] = { .tag = "[verb]", .alias = "[init_verbs]", .parser = parse_verb_mode, }, [LINE_MODE_PINCFG] = { .tag = "[pincfg]", .alias = "[user_pin_configs]", .parser = parse_pincfg_mode, }, [LINE_MODE_HINT] = { .tag = "[hint]", .alias = "[hints]", .parser = parse_hint_mode }, [LINE_MODE_VENDOR_ID] = { .tag = "[vendor_id]", .parser = parse_vendor_id_mode, }, [LINE_MODE_SUBSYSTEM_ID] = { .tag = "[subsystem_id]", .parser = parse_subsystem_id_mode, }, [LINE_MODE_REVISION_ID] = { .tag = "[revision_id]", .parser = parse_revision_id_mode, }, [LINE_MODE_CHIP_NAME] = { .tag = "[chip_name]", .parser = parse_chip_name_mode, }, }; /* check the line starting with '[' -- change the parser mode accodingly */ static int parse_line_mode(char *buf, struct hda_bus *bus) { int i; for (i = 0; i < ARRAY_SIZE(patch_items); i++) { if (!patch_items[i].tag) continue; if (strmatch(buf, patch_items[i].tag)) return i; if (patch_items[i].alias && strmatch(buf, patch_items[i].alias)) return i; } return LINE_MODE_NONE; } /* copy one line from the buffer in fw, and update the fields in fw * return zero if it reaches to the end of the buffer, or non-zero * if successfully copied a line * * the spaces at the beginning and the end of the line are stripped */ static int get_line_from_fw(char *buf, int size, size_t *fw_size_p, const void **fw_data_p) { int len; size_t fw_size = *fw_size_p; const char *p = *fw_data_p; while (isspace(*p) && fw_size) { p++; fw_size--; } if (!fw_size) return 0; for (len = 0; len < fw_size; len++) { if (!*p) break; if (*p == '\n') { p++; len++; break; } if (len < size) *buf++ = *p++; } *buf = 0; *fw_size_p = fw_size - len; *fw_data_p = p; remove_trail_spaces(buf); return 1; } /** * snd_hda_load_patch - load a "patch" firmware file and parse it * @bus: HD-audio bus * @fw_size: the firmware byte size * @fw_buf: the firmware data */ int snd_hda_load_patch(struct hda_bus *bus, size_t fw_size, const void *fw_buf) { char buf[128]; struct hda_codec *codec; int line_mode; line_mode = LINE_MODE_NONE; codec = NULL; while (get_line_from_fw(buf, sizeof(buf) - 1, &fw_size, &fw_buf)) { if (!*buf || *buf == '#' || *buf == '\n') continue; if (*buf == '[') line_mode = parse_line_mode(buf, bus); else if (patch_items[line_mode].parser && (codec || line_mode <= LINE_MODE_CODEC)) patch_items[line_mode].parser(buf, bus, &codec); } return 0; } EXPORT_SYMBOL_GPL(snd_hda_load_patch); #endif /* CONFIG_SND_HDA_PATCH_LOADER */ /* * sysfs entries */ static struct attribute *hda_dev_attrs[] = { &dev_attr_vendor_id.attr, &dev_attr_subsystem_id.attr, &dev_attr_revision_id.attr, &dev_attr_afg.attr, &dev_attr_mfg.attr, &dev_attr_vendor_name.attr, &dev_attr_chip_name.attr, &dev_attr_modelname.attr, &dev_attr_init_pin_configs.attr, &dev_attr_driver_pin_configs.attr, #ifdef CONFIG_PM &dev_attr_power_on_acct.attr, &dev_attr_power_off_acct.attr, #endif #ifdef CONFIG_SND_HDA_RECONFIG &dev_attr_init_verbs.attr, &dev_attr_hints.attr, &dev_attr_user_pin_configs.attr, &dev_attr_reconfig.attr, &dev_attr_clear.attr, #endif NULL }; static const struct attribute_group hda_dev_attr_group = { .attrs = hda_dev_attrs, }; const struct attribute_group *snd_hda_dev_attr_groups[] = { &hda_dev_attr_group, NULL }; void snd_hda_sysfs_init(struct hda_codec *codec) { mutex_init(&codec->user_mutex); #ifdef CONFIG_SND_HDA_RECONFIG snd_array_init(&codec->init_verbs, sizeof(struct hda_verb), 32); snd_array_init(&codec->hints, sizeof(struct hda_hint), 32); snd_array_init(&codec->user_pins, sizeof(struct hda_pincfg), 16); #endif } void snd_hda_sysfs_clear(struct hda_codec *codec) { #ifdef CONFIG_SND_HDA_RECONFIG struct hda_hint *hint; int i; /* clear init verbs */ snd_array_free(&codec->init_verbs); /* clear hints */ snd_array_for_each(&codec->hints, i, hint) { kfree(hint->key); /* we don't need to free hint->val */ } snd_array_free(&codec->hints); snd_array_free(&codec->user_pins); #endif }
linux-master
sound/pci/hda/hda_sysfs.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * HD audio interface patch for Creative CA0132 chip * * Copyright (c) 2011, Creative Technology Ltd. * * Based on patch_ca0110.c * Copyright (c) 2008 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/mutex.h> #include <linux/module.h> #include <linux/firmware.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/io.h> #include <linux/pci.h> #include <asm/io.h> #include <sound/core.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_jack.h" #include "ca0132_regs.h" /* Enable this to see controls for tuning purpose. */ /*#define ENABLE_TUNING_CONTROLS*/ #ifdef ENABLE_TUNING_CONTROLS #include <sound/tlv.h> #endif #define FLOAT_ZERO 0x00000000 #define FLOAT_ONE 0x3f800000 #define FLOAT_TWO 0x40000000 #define FLOAT_THREE 0x40400000 #define FLOAT_FIVE 0x40a00000 #define FLOAT_SIX 0x40c00000 #define FLOAT_EIGHT 0x41000000 #define FLOAT_MINUS_5 0xc0a00000 #define UNSOL_TAG_DSP 0x16 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 #define MASTERCONTROL 0x80 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 #define WIDGET_CHIP_CTRL 0x15 #define WIDGET_DSP_CTRL 0x16 #define MEM_CONNID_MICIN1 3 #define MEM_CONNID_MICIN2 5 #define MEM_CONNID_MICOUT1 12 #define MEM_CONNID_MICOUT2 14 #define MEM_CONNID_WUH 10 #define MEM_CONNID_DSP 16 #define MEM_CONNID_DMIC 100 #define SCP_SET 0 #define SCP_GET 1 #define EFX_FILE "ctefx.bin" #define DESKTOP_EFX_FILE "ctefx-desktop.bin" #define R3DI_EFX_FILE "ctefx-r3di.bin" #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP MODULE_FIRMWARE(EFX_FILE); MODULE_FIRMWARE(DESKTOP_EFX_FILE); MODULE_FIRMWARE(R3DI_EFX_FILE); #endif static const char *const dirstr[2] = { "Playback", "Capture" }; #define NUM_OF_OUTPUTS 2 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; enum { SPEAKER_OUT, HEADPHONE_OUT, }; enum { DIGITAL_MIC, LINE_MIC_IN }; /* Strings for Input Source Enum Control */ static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; #define IN_SRC_NUM_OF_INPUTS 3 enum { REAR_MIC, REAR_LINE_IN, FRONT_MIC, }; enum { #define VNODE_START_NID 0x80 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ VNID_MIC, VNID_HP_SEL, VNID_AMIC1_SEL, VNID_HP_ASEL, VNID_AMIC1_ASEL, VNODE_END_NID, #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) #define EFFECT_START_NID 0x90 #define OUT_EFFECT_START_NID EFFECT_START_NID SURROUND = OUT_EFFECT_START_NID, CRYSTALIZER, DIALOG_PLUS, SMART_VOLUME, X_BASS, EQUALIZER, OUT_EFFECT_END_NID, #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) #define IN_EFFECT_START_NID OUT_EFFECT_END_NID ECHO_CANCELLATION = IN_EFFECT_START_NID, VOICE_FOCUS, MIC_SVM, NOISE_REDUCTION, IN_EFFECT_END_NID, #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) VOICEFX = IN_EFFECT_END_NID, PLAY_ENHANCEMENT, CRYSTAL_VOICE, EFFECT_END_NID, OUTPUT_SOURCE_ENUM, INPUT_SOURCE_ENUM, XBASS_XOVER, EQ_PRESET_ENUM, SMART_VOLUME_ENUM, MIC_BOOST_ENUM, AE5_HEADPHONE_GAIN_ENUM, AE5_SOUND_FILTER_ENUM, ZXR_HEADPHONE_GAIN, SPEAKER_CHANNEL_CFG_ENUM, SPEAKER_FULL_RANGE_FRONT, SPEAKER_FULL_RANGE_REAR, BASS_REDIRECTION, BASS_REDIRECTION_XOVER, #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) }; /* Effects values size*/ #define EFFECT_VALS_MAX_COUNT 12 /* * Default values for the effect slider controls, they are in order of their * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then * X-bass. */ static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; /* Amount of effect level sliders for ca0132_alt controls. */ #define EFFECT_LEVEL_SLIDERS 5 /* Latency introduced by DSP blocks in milliseconds. */ #define DSP_CAPTURE_INIT_LATENCY 0 #define DSP_CRYSTAL_VOICE_LATENCY 124 #define DSP_PLAYBACK_INIT_LATENCY 13 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 #define DSP_SPEAKER_OUT_LATENCY 7 struct ct_effect { char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; hda_nid_t nid; int mid; /*effect module ID*/ int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ int direct; /* 0:output; 1:input*/ int params; /* number of default non-on/off params */ /*effect default values, 1st is on/off. */ unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; }; #define EFX_DIR_OUT 0 #define EFX_DIR_IN 1 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { { .name = "Surround", .nid = SURROUND, .mid = 0x96, .reqs = {0, 1}, .direct = EFX_DIR_OUT, .params = 1, .def_vals = {0x3F800000, 0x3F2B851F} }, { .name = "Crystalizer", .nid = CRYSTALIZER, .mid = 0x96, .reqs = {7, 8}, .direct = EFX_DIR_OUT, .params = 1, .def_vals = {0x3F800000, 0x3F266666} }, { .name = "Dialog Plus", .nid = DIALOG_PLUS, .mid = 0x96, .reqs = {2, 3}, .direct = EFX_DIR_OUT, .params = 1, .def_vals = {0x00000000, 0x3F000000} }, { .name = "Smart Volume", .nid = SMART_VOLUME, .mid = 0x96, .reqs = {4, 5, 6}, .direct = EFX_DIR_OUT, .params = 2, .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} }, { .name = "X-Bass", .nid = X_BASS, .mid = 0x96, .reqs = {24, 23, 25}, .direct = EFX_DIR_OUT, .params = 2, .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} }, { .name = "Equalizer", .nid = EQUALIZER, .mid = 0x96, .reqs = {9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}, .direct = EFX_DIR_OUT, .params = 11, .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000} }, { .name = "Echo Cancellation", .nid = ECHO_CANCELLATION, .mid = 0x95, .reqs = {0, 1, 2, 3}, .direct = EFX_DIR_IN, .params = 3, .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} }, { .name = "Voice Focus", .nid = VOICE_FOCUS, .mid = 0x95, .reqs = {6, 7, 8, 9}, .direct = EFX_DIR_IN, .params = 3, .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} }, { .name = "Mic SVM", .nid = MIC_SVM, .mid = 0x95, .reqs = {44, 45}, .direct = EFX_DIR_IN, .params = 1, .def_vals = {0x00000000, 0x3F3D70A4} }, { .name = "Noise Reduction", .nid = NOISE_REDUCTION, .mid = 0x95, .reqs = {4, 5}, .direct = EFX_DIR_IN, .params = 1, .def_vals = {0x3F800000, 0x3F000000} }, { .name = "VoiceFX", .nid = VOICEFX, .mid = 0x95, .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, .direct = EFX_DIR_IN, .params = 8, .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 0x00000000} } }; /* Tuning controls */ #ifdef ENABLE_TUNING_CONTROLS enum { #define TUNING_CTL_START_NID 0xC0 WEDGE_ANGLE = TUNING_CTL_START_NID, SVM_LEVEL, EQUALIZER_BAND_0, EQUALIZER_BAND_1, EQUALIZER_BAND_2, EQUALIZER_BAND_3, EQUALIZER_BAND_4, EQUALIZER_BAND_5, EQUALIZER_BAND_6, EQUALIZER_BAND_7, EQUALIZER_BAND_8, EQUALIZER_BAND_9, TUNING_CTL_END_NID #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) }; struct ct_tuning_ctl { char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; hda_nid_t parent_nid; hda_nid_t nid; int mid; /*effect module ID*/ int req; /*effect module request*/ int direct; /* 0:output; 1:input*/ unsigned int def_val;/*effect default values*/ }; static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { { .name = "Wedge Angle", .parent_nid = VOICE_FOCUS, .nid = WEDGE_ANGLE, .mid = 0x95, .req = 8, .direct = EFX_DIR_IN, .def_val = 0x41F00000 }, { .name = "SVM Level", .parent_nid = MIC_SVM, .nid = SVM_LEVEL, .mid = 0x95, .req = 45, .direct = EFX_DIR_IN, .def_val = 0x3F3D70A4 }, { .name = "EQ Band0", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_0, .mid = 0x96, .req = 11, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band1", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_1, .mid = 0x96, .req = 12, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band2", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_2, .mid = 0x96, .req = 13, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band3", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_3, .mid = 0x96, .req = 14, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band4", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_4, .mid = 0x96, .req = 15, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band5", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_5, .mid = 0x96, .req = 16, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band6", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_6, .mid = 0x96, .req = 17, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band7", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_7, .mid = 0x96, .req = 18, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band8", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_8, .mid = 0x96, .req = 19, .direct = EFX_DIR_OUT, .def_val = 0x00000000 }, { .name = "EQ Band9", .parent_nid = EQUALIZER, .nid = EQUALIZER_BAND_9, .mid = 0x96, .req = 20, .direct = EFX_DIR_OUT, .def_val = 0x00000000 } }; #endif /* Voice FX Presets */ #define VOICEFX_MAX_PARAM_COUNT 9 struct ct_voicefx { char *name; hda_nid_t nid; int mid; int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ }; struct ct_voicefx_preset { char *name; /*preset name*/ unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; }; static const struct ct_voicefx ca0132_voicefx = { .name = "VoiceFX Capture Switch", .nid = VOICEFX, .mid = 0x95, .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} }; static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { { .name = "Neutral", .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Female2Male", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F19999A, 0x3F866666, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Male2Female", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x450AC000, 0x4017AE14, 0x3F6B851F, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "ScrappyKid", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x40400000, 0x3F28F5C3, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Elderly", .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 0x44E10000, 0x3FB33333, 0x3FB9999A, 0x3F800000, 0x3E3A2E43, 0x00000000 } }, { .name = "Orc", .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 0x45098000, 0x3F266666, 0x3FC00000, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Elf", .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 0x45193000, 0x3F8E147B, 0x3F75C28F, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Dwarf", .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 0x45007000, 0x3F451EB8, 0x3F7851EC, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "AlienBrute", .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 0x451F6000, 0x3F266666, 0x3FA7D945, 0x3F800000, 0x3CF5C28F, 0x00000000 } }, { .name = "Robot", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3FB2718B, 0x3F800000, 0xBC07010E, 0x00000000, 0x00000000 } }, { .name = "Marine", .vals = { 0x3F800000, 0x43C20000, 0x44906000, 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 0x3F0A3D71, 0x00000000, 0x00000000 } }, { .name = "Emo", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000, 0x3F800000, 0x3E4CCCCD, 0x00000000, 0x00000000 } }, { .name = "DeepVoice", .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 0x3F800000, 0x00000000, 0x00000000 } }, { .name = "Munchkin", .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000, 0x3F1A043C, 0x3F800000, 0x00000000, 0x00000000 } } }; /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ #define EQ_PRESET_MAX_PARAM_COUNT 11 struct ct_eq { char *name; hda_nid_t nid; int mid; int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ }; struct ct_eq_preset { char *name; /*preset name*/ unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; }; static const struct ct_eq ca0132_alt_eq_enum = { .name = "FX: Equalizer Preset Switch", .nid = EQ_PRESET_ENUM, .mid = 0x96, .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} }; static const struct ct_eq_preset ca0132_alt_eq_presets[] = { { .name = "Flat", .vals = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { .name = "Acoustic", .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x40000000, 0x40000000 } }, { .name = "Classical", .vals = { 0x00000000, 0x00000000, 0x40C00000, 0x40C00000, 0x40466666, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40466666, 0x40466666 } }, { .name = "Country", .vals = { 0x00000000, 0xBF99999A, 0x00000000, 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 0x00000000, 0x00000000, 0x40000000, 0x40466666, 0x40800000 } }, { .name = "Dance", .vals = { 0x00000000, 0xBF99999A, 0x40000000, 0x40466666, 0x40866666, 0xBF99999A, 0xBF99999A, 0x00000000, 0x00000000, 0x40800000, 0x40800000 } }, { .name = "Jazz", .vals = { 0x00000000, 0x00000000, 0x00000000, 0x3F8CCCCD, 0x40800000, 0x40800000, 0x40800000, 0x00000000, 0x3F8CCCCD, 0x40466666, 0x40466666 } }, { .name = "New Age", .vals = { 0x00000000, 0x00000000, 0x40000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x3F8CCCCD, 0x40000000, 0x40000000, 0x40000000 } }, { .name = "Pop", .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 0x40000000, 0x40000000, 0x00000000, 0xBF99999A, 0xBF99999A, 0x00000000, 0x40466666, 0x40C00000 } }, { .name = "Rock", .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 0x3F8CCCCD, 0x40000000, 0xBF99999A, 0xBF99999A, 0x00000000, 0x00000000, 0x40800000, 0x40800000 } }, { .name = "Vocal", .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 0xBF99999A, 0x00000000, 0x40466666, 0x40800000, 0x40466666, 0x00000000, 0x00000000, 0x3F8CCCCD } } }; /* * DSP reqs for handling full-range speakers/bass redirection. If a speaker is * set as not being full range, and bass redirection is enabled, all * frequencies below the crossover frequency are redirected to the LFE * channel. If the surround configuration has no LFE channel, this can't be * enabled. X-Bass must be disabled when using these. */ enum speaker_range_reqs { SPEAKER_BASS_REDIRECT = 0x15, SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, /* Between 0x16-0x1a are the X-Bass reqs. */ SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, }; /* * Definitions for the DSP req's to handle speaker tuning. These all belong to * module ID 0x96, the output effects module. */ enum speaker_tuning_reqs { /* * Currently, this value is always set to 0.0f. However, on Windows, * when selecting certain headphone profiles on the new Sound Blaster * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is * sent. This gets the speaker EQ address area, which is then used to * send over (presumably) an equalizer profile for the specific * headphone setup. It is sent using the same method the DSP * firmware is uploaded with, which I believe is why the 'ctspeq.bin' * file exists in linux firmware tree but goes unused. It would also * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is * set to 1.0f. */ SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, /* * Inversion is used when setting headphone virtualization to line * out. Not sure why this is, but it's the only place it's ever used. */ SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, SPEAKER_TUNING_CENTER_INVERT = 0x2b, SPEAKER_TUNING_LFE_INVERT = 0x2c, SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, /* Delay is used when setting surround speaker distance in Windows. */ SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, SPEAKER_TUNING_CENTER_DELAY = 0x33, SPEAKER_TUNING_LFE_DELAY = 0x34, SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, /* Of these two, only mute seems to ever be used. */ SPEAKER_TUNING_MAIN_VOLUME = 0x39, SPEAKER_TUNING_MUTE = 0x3a, }; /* Surround output channel count configuration structures. */ #define SPEAKER_CHANNEL_CFG_COUNT 5 enum { SPEAKER_CHANNELS_2_0, SPEAKER_CHANNELS_2_1, SPEAKER_CHANNELS_4_0, SPEAKER_CHANNELS_4_1, SPEAKER_CHANNELS_5_1, }; struct ca0132_alt_speaker_channel_cfg { char *name; unsigned int val; }; static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { { .name = "2.0", .val = FLOAT_ONE }, { .name = "2.1", .val = FLOAT_TWO }, { .name = "4.0", .val = FLOAT_FIVE }, { .name = "4.1", .val = FLOAT_SIX }, { .name = "5.1", .val = FLOAT_EIGHT } }; /* * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, * and I don't know what the third req is, but it's always zero. I assume it's * some sort of update or set command to tell the DSP there's new volume info. */ #define DSP_VOL_OUT 0 #define DSP_VOL_IN 1 struct ct_dsp_volume_ctl { hda_nid_t vnid; int mid; /* module ID*/ unsigned int reqs[3]; /* scp req ID */ }; static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { { .vnid = VNID_SPK, .mid = 0x32, .reqs = {3, 4, 2} }, { .vnid = VNID_MIC, .mid = 0x37, .reqs = {2, 3, 1} } }; /* Values for ca0113_mmio_command_set for selecting output. */ #define AE_CA0113_OUT_SET_COMMANDS 6 struct ae_ca0113_output_set { unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; }; static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, /* Speakers. */ .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, /* Headphones. */ { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, }; static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, /* Speakers. */ .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, /* Headphones. */ { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, }; /* ae5 ca0113 command sequences to set headphone gain levels. */ #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 struct ae5_headphone_gain_set { char *name; unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; }; static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { { .name = "Low (16-31", .vals = { 0xff, 0x2c, 0xf5, 0x32 } }, { .name = "Medium (32-149", .vals = { 0x38, 0xa8, 0x3e, 0x4c } }, { .name = "High (150-600", .vals = { 0xff, 0xff, 0xff, 0x7f } } }; struct ae5_filter_set { char *name; unsigned int val; }; static const struct ae5_filter_set ae5_filter_presets[] = { { .name = "Slow Roll Off", .val = 0xa0 }, { .name = "Minimum Phase", .val = 0xc0 }, { .name = "Fast Roll Off", .val = 0x80 } }; /* * Data structures for storing audio router remapping data. These are used to * remap a currently active streams ports. */ struct chipio_stream_remap_data { unsigned int stream_id; unsigned int count; unsigned int offset[16]; unsigned int value[16]; }; static const struct chipio_stream_remap_data stream_remap_data[] = { { .stream_id = 0x14, .count = 0x04, .offset = { 0x00, 0x04, 0x08, 0x0c }, .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, }, { .stream_id = 0x0c, .count = 0x0c, .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20, 0x24, 0x28, 0x2c }, .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, }, { .stream_id = 0x0c, .count = 0x08, .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, } }; enum hda_cmd_vendor_io { /* for DspIO node */ VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, VENDOR_DSPIO_STATUS = 0xF01, VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, VENDOR_DSPIO_SCP_READ_DATA = 0xF02, VENDOR_DSPIO_DSP_INIT = 0x703, VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, /* for ChipIO node */ VENDOR_CHIPIO_ADDRESS_LOW = 0x000, VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, VENDOR_CHIPIO_STREAM_FORMAT = 0x200, VENDOR_CHIPIO_DATA_LOW = 0x300, VENDOR_CHIPIO_DATA_HIGH = 0x400, VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, VENDOR_CHIPIO_GET_PARAMETER = 0xF00, VENDOR_CHIPIO_STATUS = 0xF01, VENDOR_CHIPIO_HIC_POST_READ = 0x702, VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, VENDOR_CHIPIO_8051_DATA_READ = 0xF07, VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, VENDOR_CHIPIO_FLAG_SET = 0x70F, VENDOR_CHIPIO_FLAGS_GET = 0xF0F, VENDOR_CHIPIO_PARAM_SET = 0x710, VENDOR_CHIPIO_PARAM_GET = 0xF10, VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, VENDOR_CHIPIO_PORT_FREE_SET = 0x713, VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D }; /* * Control flag IDs */ enum control_flag_id { /* Connection manager stream setup is bypassed/enabled */ CONTROL_FLAG_C_MGR = 0, /* DSP DMA is bypassed/enabled */ CONTROL_FLAG_DMA = 1, /* 8051 'idle' mode is disabled/enabled */ CONTROL_FLAG_IDLE_ENABLE = 2, /* Tracker for the SPDIF-in path is bypassed/enabled */ CONTROL_FLAG_TRACKER = 3, /* DigitalOut to Spdif2Out connection is disabled/enabled */ CONTROL_FLAG_SPDIF2OUT = 4, /* Digital Microphone is disabled/enabled */ CONTROL_FLAG_DMIC = 5, /* ADC_B rate is 48 kHz/96 kHz */ CONTROL_FLAG_ADC_B_96KHZ = 6, /* ADC_C rate is 48 kHz/96 kHz */ CONTROL_FLAG_ADC_C_96KHZ = 7, /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ CONTROL_FLAG_DAC_96KHZ = 8, /* DSP rate is 48 kHz/96 kHz */ CONTROL_FLAG_DSP_96KHZ = 9, /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ CONTROL_FLAG_SRC_RATE_96KHZ = 11, /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ CONTROL_FLAG_DECODE_LOOP = 12, /* De-emphasis filter on DAC-1 disabled/enabled */ CONTROL_FLAG_DAC1_DEEMPHASIS = 13, /* De-emphasis filter on DAC-2 disabled/enabled */ CONTROL_FLAG_DAC2_DEEMPHASIS = 14, /* De-emphasis filter on DAC-3 disabled/enabled */ CONTROL_FLAG_DAC3_DEEMPHASIS = 15, /* High-pass filter on ADC_B disabled/enabled */ CONTROL_FLAG_ADC_B_HIGH_PASS = 16, /* High-pass filter on ADC_C disabled/enabled */ CONTROL_FLAG_ADC_C_HIGH_PASS = 17, /* Common mode on Port_A disabled/enabled */ CONTROL_FLAG_PORT_A_COMMON_MODE = 18, /* Common mode on Port_D disabled/enabled */ CONTROL_FLAG_PORT_D_COMMON_MODE = 19, /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, /* ASI rate is 48kHz/96kHz */ CONTROL_FLAG_ASI_96KHZ = 22, /* DAC power settings able to control attached ports no/yes */ CONTROL_FLAG_DACS_CONTROL_PORTS = 23, /* Clock Stop OK reporting is disabled/enabled */ CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, /* Number of control flags */ CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) }; /* * Control parameter IDs */ enum control_param_id { /* 0: None, 1: Mic1In*/ CONTROL_PARAM_VIP_SOURCE = 1, /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ CONTROL_PARAM_SPDIF1_SOURCE = 2, /* Port A output stage gain setting to use when 16 Ohm output * impedance is selected*/ CONTROL_PARAM_PORTA_160OHM_GAIN = 8, /* Port D output stage gain setting to use when 16 Ohm output * impedance is selected*/ CONTROL_PARAM_PORTD_160OHM_GAIN = 10, /* * This control param name was found in the 8051 memory, and makes * sense given the fact the AE-5 uses it and has the ASI flag set. */ CONTROL_PARAM_ASI = 23, /* Stream Control */ /* Select stream with the given ID */ CONTROL_PARAM_STREAM_ID = 24, /* Source connection point for the selected stream */ CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, /* Destination connection point for the selected stream */ CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, /* Number of audio channels in the selected stream */ CONTROL_PARAM_STREAMS_CHANNELS = 27, /*Enable control for the selected stream */ CONTROL_PARAM_STREAM_CONTROL = 28, /* Connection Point Control */ /* Select connection point with the given ID */ CONTROL_PARAM_CONN_POINT_ID = 29, /* Connection point sample rate */ CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, /* Node Control */ /* Select HDA node with the given ID */ CONTROL_PARAM_NODE_ID = 31 }; /* * Dsp Io Status codes */ enum hda_vendor_status_dspio { /* Success */ VENDOR_STATUS_DSPIO_OK = 0x00, /* Busy, unable to accept new command, the host must retry */ VENDOR_STATUS_DSPIO_BUSY = 0x01, /* SCP command queue is full */ VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, /* SCP response queue is empty */ VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 }; /* * Chip Io Status codes */ enum hda_vendor_status_chipio { /* Success */ VENDOR_STATUS_CHIPIO_OK = 0x00, /* Busy, unable to accept new command, the host must retry */ VENDOR_STATUS_CHIPIO_BUSY = 0x01 }; /* * CA0132 sample rate */ enum ca0132_sample_rate { SR_6_000 = 0x00, SR_8_000 = 0x01, SR_9_600 = 0x02, SR_11_025 = 0x03, SR_16_000 = 0x04, SR_22_050 = 0x05, SR_24_000 = 0x06, SR_32_000 = 0x07, SR_44_100 = 0x08, SR_48_000 = 0x09, SR_88_200 = 0x0A, SR_96_000 = 0x0B, SR_144_000 = 0x0C, SR_176_400 = 0x0D, SR_192_000 = 0x0E, SR_384_000 = 0x0F, SR_COUNT = 0x10, SR_RATE_UNKNOWN = 0x1F }; enum dsp_download_state { DSP_DOWNLOAD_FAILED = -1, DSP_DOWNLOAD_INIT = 0, DSP_DOWNLOADING = 1, DSP_DOWNLOADED = 2 }; /* retrieve parameters from hda format */ #define get_hdafmt_chs(fmt) (fmt & 0xf) #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) /* * CA0132 specific */ struct ca0132_spec { const struct snd_kcontrol_new *mixers[5]; unsigned int num_mixers; const struct hda_verb *base_init_verbs; const struct hda_verb *base_exit_verbs; const struct hda_verb *chip_init_verbs; const struct hda_verb *desktop_init_verbs; struct hda_verb *spec_init_verbs; struct auto_pin_cfg autocfg; /* Nodes configurations */ struct hda_multi_out multiout; hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; unsigned int num_outputs; hda_nid_t input_pins[AUTO_PIN_LAST]; hda_nid_t adcs[AUTO_PIN_LAST]; hda_nid_t dig_out; hda_nid_t dig_in; unsigned int num_inputs; hda_nid_t shared_mic_nid; hda_nid_t shared_out_nid; hda_nid_t unsol_tag_hp; hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ hda_nid_t unsol_tag_amic1; /* chip access */ struct mutex chipio_mutex; /* chip access mutex */ u32 curr_chip_addx; /* DSP download related */ enum dsp_download_state dsp_state; unsigned int dsp_stream_id; unsigned int wait_scp; unsigned int wait_scp_header; unsigned int wait_num_data; unsigned int scp_resp_header; unsigned int scp_resp_data[4]; unsigned int scp_resp_count; bool startup_check_entered; bool dsp_reload; /* mixer and effects related */ unsigned char dmic_ctl; int cur_out_type; int cur_mic_type; long vnode_lvol[VNODES_COUNT]; long vnode_rvol[VNODES_COUNT]; long vnode_lswitch[VNODES_COUNT]; long vnode_rswitch[VNODES_COUNT]; long effects_switch[EFFECTS_COUNT]; long voicefx_val; long cur_mic_boost; /* ca0132_alt control related values */ unsigned char in_enum_val; unsigned char out_enum_val; unsigned char channel_cfg_val; unsigned char speaker_range_val[2]; unsigned char mic_boost_enum_val; unsigned char smart_volume_setting; unsigned char bass_redirection_val; long bass_redirect_xover_freq; long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; long xbass_xover_freq; long eq_preset_val; unsigned int tlv[4]; struct hda_vmaster_mute_hook vmaster_mute; /* AE-5 Control values */ unsigned char ae5_headphone_gain_val; unsigned char ae5_filter_val; /* ZxR Control Values */ unsigned char zxr_gain_set; struct hda_codec *codec; struct delayed_work unsol_hp_work; int quirk; #ifdef ENABLE_TUNING_CONTROLS long cur_ctl_vals[TUNING_CTLS_COUNT]; #endif /* * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown * things. */ bool use_pci_mmio; void __iomem *mem_base; /* * Whether or not to use the alt functions like alt_select_out, * alt_select_in, etc. Only used on desktop codecs for now, because of * surround sound support. */ bool use_alt_functions; /* * Whether or not to use alt controls: volume effect sliders, EQ * presets, smart volume presets, and new control names with FX prefix. * Renames PlayEnhancement and CrystalVoice too. */ bool use_alt_controls; }; /* * CA0132 quirks table */ enum { QUIRK_NONE, QUIRK_ALIENWARE, QUIRK_ALIENWARE_M17XR4, QUIRK_SBZ, QUIRK_ZXR, QUIRK_ZXR_DBPRO, QUIRK_R3DI, QUIRK_R3D, QUIRK_AE5, QUIRK_AE7, }; #ifdef CONFIG_PCI #define ca0132_quirk(spec) ((spec)->quirk) #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) #else #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) #endif static const struct hda_pintbl alienware_pincfgs[] = { { 0x0b, 0x90170110 }, /* Builtin Speaker */ { 0x0c, 0x411111f0 }, /* N/A */ { 0x0d, 0x411111f0 }, /* N/A */ { 0x0e, 0x411111f0 }, /* N/A */ { 0x0f, 0x0321101f }, /* HP */ { 0x10, 0x411111f0 }, /* Headset? disabled for now */ { 0x11, 0x03a11021 }, /* Mic */ { 0x12, 0xd5a30140 }, /* Builtin Mic */ { 0x13, 0x411111f0 }, /* N/A */ { 0x18, 0x411111f0 }, /* N/A */ {} }; /* Sound Blaster Z pin configs taken from Windows Driver */ static const struct hda_pintbl sbz_pincfgs[] = { { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ { 0x0d, 0x014510f0 }, /* Digital Out */ { 0x0e, 0x01c510f0 }, /* SPDIF In */ { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ { 0x13, 0x908700f0 }, /* What U Hear In*/ { 0x18, 0x50d000f0 }, /* N/A */ {} }; /* Sound Blaster ZxR pin configs taken from Windows Driver */ static const struct hda_pintbl zxr_pincfgs[] = { { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ { 0x0d, 0x014510f0 }, /* Digital Out */ { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ { 0x13, 0x908700f0 }, /* What U Hear In*/ { 0x18, 0x50d000f0 }, /* N/A */ {} }; /* Recon3D pin configs taken from Windows Driver */ static const struct hda_pintbl r3d_pincfgs[] = { { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ { 0x0d, 0x014510f0 }, /* Digital Out */ { 0x0e, 0x01c520f0 }, /* SPDIF In */ { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ { 0x13, 0x908700f0 }, /* What U Hear In*/ { 0x18, 0x50d000f0 }, /* N/A */ {} }; /* Sound Blaster AE-5 pin configs taken from Windows Driver */ static const struct hda_pintbl ae5_pincfgs[] = { { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ { 0x0d, 0x014510f0 }, /* Digital Out */ { 0x0e, 0x01c510f0 }, /* SPDIF In */ { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ { 0x13, 0x908700f0 }, /* What U Hear In*/ { 0x18, 0x50d000f0 }, /* N/A */ {} }; /* Recon3D integrated pin configs taken from Windows Driver */ static const struct hda_pintbl r3di_pincfgs[] = { { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ { 0x0d, 0x014510f0 }, /* Digital Out */ { 0x0e, 0x41c520f0 }, /* SPDIF In */ { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ { 0x13, 0x908700f0 }, /* What U Hear In*/ { 0x18, 0x500000f0 }, /* N/A */ {} }; static const struct hda_pintbl ae7_pincfgs[] = { { 0x0b, 0x01017010 }, { 0x0c, 0x014510f0 }, { 0x0d, 0x414510f0 }, { 0x0e, 0x01c520f0 }, { 0x0f, 0x01017114 }, { 0x10, 0x01017011 }, { 0x11, 0x018170ff }, { 0x12, 0x01a170f0 }, { 0x13, 0x908700f0 }, { 0x18, 0x500000f0 }, {} }; static const struct snd_pci_quirk ca0132_quirks[] = { SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), {} }; /* Output selection quirk info structures. */ #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 #define MAX_QUIRK_SCP_SET_VALS 2 struct ca0132_alt_out_set_info { unsigned int dac2port; /* ParamID 0x0d value. */ bool has_hda_gpio; char hda_gpio_pin; char hda_gpio_set; unsigned int mmio_gpio_count; char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; unsigned int scp_cmds_count; unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; bool has_chipio_write; unsigned int chipio_write_addr; unsigned int chipio_write_data; }; struct ca0132_alt_out_set_quirk_data { int quirk_id; bool has_headphone_gain; bool is_ae_series; struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; }; static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { { .quirk_id = QUIRK_R3DI, .has_headphone_gain = false, .is_ae_series = false, .out_set_info = { /* Speakers. */ { .dac2port = 0x24, .has_hda_gpio = true, .hda_gpio_pin = 2, .hda_gpio_set = 1, .mmio_gpio_count = 0, .scp_cmds_count = 0, .has_chipio_write = false, }, /* Headphones. */ { .dac2port = 0x21, .has_hda_gpio = true, .hda_gpio_pin = 2, .hda_gpio_set = 0, .mmio_gpio_count = 0, .scp_cmds_count = 0, .has_chipio_write = false, } }, }, { .quirk_id = QUIRK_R3D, .has_headphone_gain = false, .is_ae_series = false, .out_set_info = { /* Speakers. */ { .dac2port = 0x24, .has_hda_gpio = false, .mmio_gpio_count = 1, .mmio_gpio_pin = { 1 }, .mmio_gpio_set = { 1 }, .scp_cmds_count = 0, .has_chipio_write = false, }, /* Headphones. */ { .dac2port = 0x21, .has_hda_gpio = false, .mmio_gpio_count = 1, .mmio_gpio_pin = { 1 }, .mmio_gpio_set = { 0 }, .scp_cmds_count = 0, .has_chipio_write = false, } }, }, { .quirk_id = QUIRK_SBZ, .has_headphone_gain = false, .is_ae_series = false, .out_set_info = { /* Speakers. */ { .dac2port = 0x18, .has_hda_gpio = false, .mmio_gpio_count = 3, .mmio_gpio_pin = { 7, 4, 1 }, .mmio_gpio_set = { 0, 1, 1 }, .scp_cmds_count = 0, .has_chipio_write = false, }, /* Headphones. */ { .dac2port = 0x12, .has_hda_gpio = false, .mmio_gpio_count = 3, .mmio_gpio_pin = { 7, 4, 1 }, .mmio_gpio_set = { 1, 1, 0 }, .scp_cmds_count = 0, .has_chipio_write = false, } }, }, { .quirk_id = QUIRK_ZXR, .has_headphone_gain = true, .is_ae_series = false, .out_set_info = { /* Speakers. */ { .dac2port = 0x24, .has_hda_gpio = false, .mmio_gpio_count = 3, .mmio_gpio_pin = { 2, 3, 5 }, .mmio_gpio_set = { 1, 1, 0 }, .scp_cmds_count = 0, .has_chipio_write = false, }, /* Headphones. */ { .dac2port = 0x21, .has_hda_gpio = false, .mmio_gpio_count = 3, .mmio_gpio_pin = { 2, 3, 5 }, .mmio_gpio_set = { 0, 1, 1 }, .scp_cmds_count = 0, .has_chipio_write = false, } }, }, { .quirk_id = QUIRK_AE5, .has_headphone_gain = true, .is_ae_series = true, .out_set_info = { /* Speakers. */ { .dac2port = 0xa4, .has_hda_gpio = false, .mmio_gpio_count = 0, .scp_cmds_count = 2, .scp_cmd_mid = { 0x96, 0x96 }, .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, SPEAKER_TUNING_FRONT_RIGHT_INVERT }, .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, .has_chipio_write = true, .chipio_write_addr = 0x0018b03c, .chipio_write_data = 0x00000012 }, /* Headphones. */ { .dac2port = 0xa1, .has_hda_gpio = false, .mmio_gpio_count = 0, .scp_cmds_count = 2, .scp_cmd_mid = { 0x96, 0x96 }, .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, SPEAKER_TUNING_FRONT_RIGHT_INVERT }, .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, .has_chipio_write = true, .chipio_write_addr = 0x0018b03c, .chipio_write_data = 0x00000012 } }, }, { .quirk_id = QUIRK_AE7, .has_headphone_gain = true, .is_ae_series = true, .out_set_info = { /* Speakers. */ { .dac2port = 0x58, .has_hda_gpio = false, .mmio_gpio_count = 1, .mmio_gpio_pin = { 0 }, .mmio_gpio_set = { 1 }, .scp_cmds_count = 2, .scp_cmd_mid = { 0x96, 0x96 }, .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, SPEAKER_TUNING_FRONT_RIGHT_INVERT }, .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, .has_chipio_write = true, .chipio_write_addr = 0x0018b03c, .chipio_write_data = 0x00000000 }, /* Headphones. */ { .dac2port = 0x58, .has_hda_gpio = false, .mmio_gpio_count = 1, .mmio_gpio_pin = { 0 }, .mmio_gpio_set = { 1 }, .scp_cmds_count = 2, .scp_cmd_mid = { 0x96, 0x96 }, .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, SPEAKER_TUNING_FRONT_RIGHT_INVERT }, .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, .has_chipio_write = true, .chipio_write_addr = 0x0018b03c, .chipio_write_data = 0x00000010 } }, } }; /* * CA0132 codec access */ static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, unsigned int verb, unsigned int parm, unsigned int *res) { unsigned int response; response = snd_hda_codec_read(codec, nid, 0, verb, parm); *res = response; return ((response == -1) ? -1 : 0); } static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, unsigned short converter_format, unsigned int *res) { return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, converter_format & 0xffff, res); } static int codec_set_converter_stream_channel(struct hda_codec *codec, hda_nid_t nid, unsigned char stream, unsigned char channel, unsigned int *res) { unsigned char converter_stream_channel = 0; converter_stream_channel = (stream << 4) | (channel & 0x0f); return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, converter_stream_channel, res); } /* Chip access helper function */ static int chipio_send(struct hda_codec *codec, unsigned int reg, unsigned int data) { unsigned int res; unsigned long timeout = jiffies + msecs_to_jiffies(1000); /* send bits of data specified by reg */ do { res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, reg, data); if (res == VENDOR_STATUS_CHIPIO_OK) return 0; msleep(20); } while (time_before(jiffies, timeout)); return -EIO; } /* * Write chip address through the vendor widget -- NOT protected by the Mutex! */ static int chipio_write_address(struct hda_codec *codec, unsigned int chip_addx) { struct ca0132_spec *spec = codec->spec; int res; if (spec->curr_chip_addx == chip_addx) return 0; /* send low 16 bits of the address */ res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, chip_addx & 0xffff); if (res != -EIO) { /* send high 16 bits of the address */ res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, chip_addx >> 16); } spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; return res; } /* * Write data through the vendor widget -- NOT protected by the Mutex! */ static int chipio_write_data(struct hda_codec *codec, unsigned int data) { struct ca0132_spec *spec = codec->spec; int res; /* send low 16 bits of the data */ res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); if (res != -EIO) { /* send high 16 bits of the data */ res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, data >> 16); } /*If no error encountered, automatically increment the address as per chip behaviour*/ spec->curr_chip_addx = (res != -EIO) ? (spec->curr_chip_addx + 4) : ~0U; return res; } /* * Write multiple data through the vendor widget -- NOT protected by the Mutex! */ static int chipio_write_data_multiple(struct hda_codec *codec, const u32 *data, unsigned int count) { int status = 0; if (data == NULL) { codec_dbg(codec, "chipio_write_data null ptr\n"); return -EINVAL; } while ((count-- != 0) && (status == 0)) status = chipio_write_data(codec, *data++); return status; } /* * Read data through the vendor widget -- NOT protected by the Mutex! */ static int chipio_read_data(struct hda_codec *codec, unsigned int *data) { struct ca0132_spec *spec = codec->spec; int res; /* post read */ res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); if (res != -EIO) { /* read status */ res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); } if (res != -EIO) { /* read data */ *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_HIC_READ_DATA, 0); } /*If no error encountered, automatically increment the address as per chip behaviour*/ spec->curr_chip_addx = (res != -EIO) ? (spec->curr_chip_addx + 4) : ~0U; return res; } /* * Write given value to the given address through the chip I/O widget. * protected by the Mutex */ static int chipio_write(struct hda_codec *codec, unsigned int chip_addx, const unsigned int data) { struct ca0132_spec *spec = codec->spec; int err; mutex_lock(&spec->chipio_mutex); /* write the address, and if successful proceed to write data */ err = chipio_write_address(codec, chip_addx); if (err < 0) goto exit; err = chipio_write_data(codec, data); if (err < 0) goto exit; exit: mutex_unlock(&spec->chipio_mutex); return err; } /* * Write given value to the given address through the chip I/O widget. * not protected by the Mutex */ static int chipio_write_no_mutex(struct hda_codec *codec, unsigned int chip_addx, const unsigned int data) { int err; /* write the address, and if successful proceed to write data */ err = chipio_write_address(codec, chip_addx); if (err < 0) goto exit; err = chipio_write_data(codec, data); if (err < 0) goto exit; exit: return err; } /* * Write multiple values to the given address through the chip I/O widget. * protected by the Mutex */ static int chipio_write_multiple(struct hda_codec *codec, u32 chip_addx, const u32 *data, unsigned int count) { struct ca0132_spec *spec = codec->spec; int status; mutex_lock(&spec->chipio_mutex); status = chipio_write_address(codec, chip_addx); if (status < 0) goto error; status = chipio_write_data_multiple(codec, data, count); error: mutex_unlock(&spec->chipio_mutex); return status; } /* * Read the given address through the chip I/O widget * protected by the Mutex */ static int chipio_read(struct hda_codec *codec, unsigned int chip_addx, unsigned int *data) { struct ca0132_spec *spec = codec->spec; int err; mutex_lock(&spec->chipio_mutex); /* write the address, and if successful proceed to write data */ err = chipio_write_address(codec, chip_addx); if (err < 0) goto exit; err = chipio_read_data(codec, data); if (err < 0) goto exit; exit: mutex_unlock(&spec->chipio_mutex); return err; } /* * Set chip control flags through the chip I/O widget. */ static void chipio_set_control_flag(struct hda_codec *codec, enum control_flag_id flag_id, bool flag_state) { unsigned int val; unsigned int flag_bit; flag_bit = (flag_state ? 1 : 0); val = (flag_bit << 7) | (flag_id); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_FLAG_SET, val); } /* * Set chip parameters through the chip I/O widget. */ static void chipio_set_control_param(struct hda_codec *codec, enum control_param_id param_id, int param_val) { struct ca0132_spec *spec = codec->spec; int val; if ((param_id < 32) && (param_val < 8)) { val = (param_val << 5) | (param_id); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_SET, val); } else { mutex_lock(&spec->chipio_mutex); if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_ID_SET, param_id); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_VALUE_SET, param_val); } mutex_unlock(&spec->chipio_mutex); } } /* * Set chip parameters through the chip I/O widget. NO MUTEX. */ static void chipio_set_control_param_no_mutex(struct hda_codec *codec, enum control_param_id param_id, int param_val) { int val; if ((param_id < 32) && (param_val < 8)) { val = (param_val << 5) | (param_id); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_SET, val); } else { if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_ID_SET, param_id); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_VALUE_SET, param_val); } } } /* * Connect stream to a source point, and then connect * that source point to a destination point. */ static void chipio_set_stream_source_dest(struct hda_codec *codec, int streamid, int source_point, int dest_point) { chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_ID, streamid); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); } /* * Set number of channels in the selected stream. */ static void chipio_set_stream_channels(struct hda_codec *codec, int streamid, unsigned int channels) { chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_ID, streamid); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAMS_CHANNELS, channels); } /* * Enable/Disable audio stream. */ static void chipio_set_stream_control(struct hda_codec *codec, int streamid, int enable) { chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_ID, streamid); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_CONTROL, enable); } /* * Get ChipIO audio stream's status. */ static void chipio_get_stream_control(struct hda_codec *codec, int streamid, unsigned int *enable) { chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_STREAM_ID, streamid); *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_GET, CONTROL_PARAM_STREAM_CONTROL); } /* * Set sampling rate of the connection point. NO MUTEX. */ static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, int connid, enum ca0132_sample_rate rate) { chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_CONN_POINT_ID, connid); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); } /* * Set sampling rate of the connection point. */ static void chipio_set_conn_rate(struct hda_codec *codec, int connid, enum ca0132_sample_rate rate) { chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); } /* * Writes to the 8051's internal address space directly instead of indirectly, * giving access to the special function registers located at addresses * 0x80-0xFF. */ static void chipio_8051_write_direct(struct hda_codec *codec, unsigned int addr, unsigned int data) { unsigned int verb; verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); } /* * Writes to the 8051's exram, which has 16-bits of address space. * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by * setting the pmem bank selection SFR. * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff * being writable. */ static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) { unsigned int tmp; /* Lower 8-bits. */ tmp = addr & 0xff; snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); /* Upper 8-bits. */ tmp = (addr >> 8) & 0xff; snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); } static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) { /* 8-bits of data. */ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); } static unsigned int chipio_8051_get_data(struct hda_codec *codec) { return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_8051_DATA_READ, 0); } /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) { /* 8-bits of data. */ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); } static void chipio_8051_write_exram(struct hda_codec *codec, unsigned int addr, unsigned int data) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); chipio_8051_set_address(codec, addr); chipio_8051_set_data(codec, data); mutex_unlock(&spec->chipio_mutex); } static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, unsigned int addr, unsigned int data) { chipio_8051_set_address(codec, addr); chipio_8051_set_data(codec, data); } /* Readback data from the 8051's exram. No mutex. */ static void chipio_8051_read_exram(struct hda_codec *codec, unsigned int addr, unsigned int *data) { chipio_8051_set_address(codec, addr); *data = chipio_8051_get_data(codec); } static void chipio_8051_write_pll_pmu(struct hda_codec *codec, unsigned int addr, unsigned int data) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); chipio_8051_set_address(codec, addr & 0xff); chipio_8051_set_data_pll(codec, data); mutex_unlock(&spec->chipio_mutex); } static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, unsigned int addr, unsigned int data) { chipio_8051_set_address(codec, addr & 0xff); chipio_8051_set_data_pll(codec, data); } /* * Enable clocks. */ static void chipio_enable_clocks(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); mutex_unlock(&spec->chipio_mutex); } /* * CA0132 DSP IO stuffs */ static int dspio_send(struct hda_codec *codec, unsigned int reg, unsigned int data) { int res; unsigned long timeout = jiffies + msecs_to_jiffies(1000); /* send bits of data specified by reg to dsp */ do { res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) return res; msleep(20); } while (time_before(jiffies, timeout)); return -EIO; } /* * Wait for DSP to be ready for commands */ static void dspio_write_wait(struct hda_codec *codec) { int status; unsigned long timeout = jiffies + msecs_to_jiffies(1000); do { status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, VENDOR_DSPIO_STATUS, 0); if ((status == VENDOR_STATUS_DSPIO_OK) || (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) break; msleep(1); } while (time_before(jiffies, timeout)); } /* * Write SCP data to DSP */ static int dspio_write(struct hda_codec *codec, unsigned int scp_data) { struct ca0132_spec *spec = codec->spec; int status; dspio_write_wait(codec); mutex_lock(&spec->chipio_mutex); status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, scp_data & 0xffff); if (status < 0) goto error; status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, scp_data >> 16); if (status < 0) goto error; /* OK, now check if the write itself has executed*/ status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, VENDOR_DSPIO_STATUS, 0); error: mutex_unlock(&spec->chipio_mutex); return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? -EIO : 0; } /* * Write multiple SCP data to DSP */ static int dspio_write_multiple(struct hda_codec *codec, unsigned int *buffer, unsigned int size) { int status = 0; unsigned int count; if (buffer == NULL) return -EINVAL; count = 0; while (count < size) { status = dspio_write(codec, *buffer++); if (status != 0) break; count++; } return status; } static int dspio_read(struct hda_codec *codec, unsigned int *data) { int status; status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); if (status == -EIO) return status; status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); if (status == -EIO || status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) return -EIO; *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, VENDOR_DSPIO_SCP_READ_DATA, 0); return 0; } static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, unsigned int *buf_size, unsigned int size_count) { int status = 0; unsigned int size = *buf_size; unsigned int count; unsigned int skip_count; unsigned int dummy; if (buffer == NULL) return -1; count = 0; while (count < size && count < size_count) { status = dspio_read(codec, buffer++); if (status != 0) break; count++; } skip_count = count; if (status == 0) { while (skip_count < size) { status = dspio_read(codec, &dummy); if (status != 0) break; skip_count++; } } *buf_size = count; return status; } /* * Construct the SCP header using corresponding fields */ static inline unsigned int make_scp_header(unsigned int target_id, unsigned int source_id, unsigned int get_flag, unsigned int req, unsigned int device_flag, unsigned int resp_flag, unsigned int error_flag, unsigned int data_size) { unsigned int header = 0; header = (data_size & 0x1f) << 27; header |= (error_flag & 0x01) << 26; header |= (resp_flag & 0x01) << 25; header |= (device_flag & 0x01) << 24; header |= (req & 0x7f) << 17; header |= (get_flag & 0x01) << 16; header |= (source_id & 0xff) << 8; header |= target_id & 0xff; return header; } /* * Extract corresponding fields from SCP header */ static inline void extract_scp_header(unsigned int header, unsigned int *target_id, unsigned int *source_id, unsigned int *get_flag, unsigned int *req, unsigned int *device_flag, unsigned int *resp_flag, unsigned int *error_flag, unsigned int *data_size) { if (data_size) *data_size = (header >> 27) & 0x1f; if (error_flag) *error_flag = (header >> 26) & 0x01; if (resp_flag) *resp_flag = (header >> 25) & 0x01; if (device_flag) *device_flag = (header >> 24) & 0x01; if (req) *req = (header >> 17) & 0x7f; if (get_flag) *get_flag = (header >> 16) & 0x01; if (source_id) *source_id = (header >> 8) & 0xff; if (target_id) *target_id = header & 0xff; } #define SCP_MAX_DATA_WORDS (16) /* Structure to contain any SCP message */ struct scp_msg { unsigned int hdr; unsigned int data[SCP_MAX_DATA_WORDS]; }; static void dspio_clear_response_queue(struct hda_codec *codec) { unsigned long timeout = jiffies + msecs_to_jiffies(1000); unsigned int dummy = 0; int status; /* clear all from the response queue */ do { status = dspio_read(codec, &dummy); } while (status == 0 && time_before(jiffies, timeout)); } static int dspio_get_response_data(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int data = 0; unsigned int count; if (dspio_read(codec, &data) < 0) return -EIO; if ((data & 0x00ffffff) == spec->wait_scp_header) { spec->scp_resp_header = data; spec->scp_resp_count = data >> 27; count = spec->wait_num_data; dspio_read_multiple(codec, spec->scp_resp_data, &spec->scp_resp_count, count); return 0; } return -EIO; } /* * Send SCP message to DSP */ static int dspio_send_scp_message(struct hda_codec *codec, unsigned char *send_buf, unsigned int send_buf_size, unsigned char *return_buf, unsigned int return_buf_size, unsigned int *bytes_returned) { struct ca0132_spec *spec = codec->spec; int status; unsigned int scp_send_size = 0; unsigned int total_size; bool waiting_for_resp = false; unsigned int header; struct scp_msg *ret_msg; unsigned int resp_src_id, resp_target_id; unsigned int data_size, src_id, target_id, get_flag, device_flag; if (bytes_returned) *bytes_returned = 0; /* get scp header from buffer */ header = *((unsigned int *)send_buf); extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, &device_flag, NULL, NULL, &data_size); scp_send_size = data_size + 1; total_size = (scp_send_size * 4); if (send_buf_size < total_size) return -EINVAL; if (get_flag || device_flag) { if (!return_buf || return_buf_size < 4 || !bytes_returned) return -EINVAL; spec->wait_scp_header = *((unsigned int *)send_buf); /* swap source id with target id */ resp_target_id = src_id; resp_src_id = target_id; spec->wait_scp_header &= 0xffff0000; spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; spec->wait_scp = 1; waiting_for_resp = true; } status = dspio_write_multiple(codec, (unsigned int *)send_buf, scp_send_size); if (status < 0) { spec->wait_scp = 0; return status; } if (waiting_for_resp) { unsigned long timeout = jiffies + msecs_to_jiffies(1000); memset(return_buf, 0, return_buf_size); do { msleep(20); } while (spec->wait_scp && time_before(jiffies, timeout)); waiting_for_resp = false; if (!spec->wait_scp) { ret_msg = (struct scp_msg *)return_buf; memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); memcpy(&ret_msg->data, spec->scp_resp_data, spec->wait_num_data); *bytes_returned = (spec->scp_resp_count + 1) * 4; status = 0; } else { status = -EIO; } spec->wait_scp = 0; } return status; } /** * dspio_scp - Prepare and send the SCP message to DSP * @codec: the HDA codec * @mod_id: ID of the DSP module to send the command * @src_id: ID of the source * @req: ID of request to send to the DSP module * @dir: SET or GET * @data: pointer to the data to send with the request, request specific * @len: length of the data, in bytes * @reply: point to the buffer to hold data returned for a reply * @reply_len: length of the reply buffer returned from GET * * Returns zero or a negative error code. */ static int dspio_scp(struct hda_codec *codec, int mod_id, int src_id, int req, int dir, const void *data, unsigned int len, void *reply, unsigned int *reply_len) { int status = 0; struct scp_msg scp_send, scp_reply; unsigned int ret_bytes, send_size, ret_size; unsigned int send_get_flag, reply_resp_flag, reply_error_flag; unsigned int reply_data_size; memset(&scp_send, 0, sizeof(scp_send)); memset(&scp_reply, 0, sizeof(scp_reply)); if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) return -EINVAL; if (dir == SCP_GET && reply == NULL) { codec_dbg(codec, "dspio_scp get but has no buffer\n"); return -EINVAL; } if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); return -EINVAL; } scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 0, 0, 0, len/sizeof(unsigned int)); if (data != NULL && len > 0) { len = min((unsigned int)(sizeof(scp_send.data)), len); memcpy(scp_send.data, data, len); } ret_bytes = 0; send_size = sizeof(unsigned int) + len; status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, send_size, (unsigned char *)&scp_reply, sizeof(scp_reply), &ret_bytes); if (status < 0) { codec_dbg(codec, "dspio_scp: send scp msg failed\n"); return status; } /* extract send and reply headers members */ extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, NULL, NULL, NULL, NULL, NULL); extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, &reply_resp_flag, &reply_error_flag, &reply_data_size); if (!send_get_flag) return 0; if (reply_resp_flag && !reply_error_flag) { ret_size = (ret_bytes - sizeof(scp_reply.hdr)) / sizeof(unsigned int); if (*reply_len < ret_size*sizeof(unsigned int)) { codec_dbg(codec, "reply too long for buf\n"); return -EINVAL; } else if (ret_size != reply_data_size) { codec_dbg(codec, "RetLen and HdrLen .NE.\n"); return -EINVAL; } else if (!reply) { codec_dbg(codec, "NULL reply\n"); return -EINVAL; } else { *reply_len = ret_size*sizeof(unsigned int); memcpy(reply, scp_reply.data, *reply_len); } } else { codec_dbg(codec, "reply ill-formed or errflag set\n"); return -EIO; } return status; } /* * Set DSP parameters */ static int dspio_set_param(struct hda_codec *codec, int mod_id, int src_id, int req, const void *data, unsigned int len) { return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, NULL); } static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, int req, const unsigned int data) { return dspio_set_param(codec, mod_id, 0x20, req, &data, sizeof(unsigned int)); } /* * Allocate a DSP DMA channel via an SCP message */ static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) { int status = 0; unsigned int size = sizeof(*dma_chan); codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); status = dspio_scp(codec, MASTERCONTROL, 0x20, MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, dma_chan, &size); if (status < 0) { codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); return status; } if ((*dma_chan + 1) == 0) { codec_dbg(codec, "no free dma channels to allocate\n"); return -EBUSY; } codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); return status; } /* * Free a DSP DMA via an SCP message */ static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) { int status = 0; unsigned int dummy = 0; codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); status = dspio_scp(codec, MASTERCONTROL, 0x20, MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy); if (status < 0) { codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); return status; } codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); return status; } /* * (Re)start the DSP */ static int dsp_set_run_state(struct hda_codec *codec) { unsigned int dbg_ctrl_reg; unsigned int halt_state; int err; err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); if (err < 0) return err; halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> DSP_DBGCNTL_STATE_LOBIT; if (halt_state != 0) { dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & DSP_DBGCNTL_SS_MASK); err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, dbg_ctrl_reg); if (err < 0) return err; dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & DSP_DBGCNTL_EXEC_MASK; err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, dbg_ctrl_reg); if (err < 0) return err; } return 0; } /* * Reset the DSP */ static int dsp_reset(struct hda_codec *codec) { unsigned int res; int retry = 20; codec_dbg(codec, "dsp_reset\n"); do { res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); retry--; } while (res == -EIO && retry); if (!retry) { codec_dbg(codec, "dsp_reset timeout\n"); return -EIO; } return 0; } /* * Convert chip address to DSP address */ static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, bool *code, bool *yram) { *code = *yram = false; if (UC_RANGE(chip_addx, 1)) { *code = true; return UC_OFF(chip_addx); } else if (X_RANGE_ALL(chip_addx, 1)) { return X_OFF(chip_addx); } else if (Y_RANGE_ALL(chip_addx, 1)) { *yram = true; return Y_OFF(chip_addx); } return INVALID_CHIP_ADDRESS; } /* * Check if the DSP DMA is active */ static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) { unsigned int dma_chnlstart_reg; chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); return ((dma_chnlstart_reg & (1 << (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); } static int dsp_dma_setup_common(struct hda_codec *codec, unsigned int chip_addx, unsigned int dma_chan, unsigned int port_map_mask, bool ovly) { int status = 0; unsigned int chnl_prop; unsigned int dsp_addx; unsigned int active; bool code, yram; codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { codec_dbg(codec, "dma chan num invalid\n"); return -EINVAL; } if (dsp_is_dma_active(codec, dma_chan)) { codec_dbg(codec, "dma already active\n"); return -EBUSY; } dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); if (dsp_addx == INVALID_CHIP_ADDRESS) { codec_dbg(codec, "invalid chip addr\n"); return -ENXIO; } chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; active = 0; codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); if (ovly) { status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, &chnl_prop); if (status < 0) { codec_dbg(codec, "read CHNLPROP Reg fail\n"); return status; } codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); } if (!code) chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); else chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); if (status < 0) { codec_dbg(codec, "write CHNLPROP Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); if (ovly) { status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, &active); if (status < 0) { codec_dbg(codec, "read ACTIVE Reg fail\n"); return status; } codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); } active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & DSPDMAC_ACTIVE_AAR_MASK; status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); if (status < 0) { codec_dbg(codec, "write ACTIVE Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), port_map_mask); if (status < 0) { codec_dbg(codec, "write AUDCHSEL Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); if (status < 0) { codec_dbg(codec, "write IRQCNT Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); codec_dbg(codec, "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", chip_addx, dsp_addx, dma_chan, port_map_mask, chnl_prop, active); codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); return 0; } /* * Setup the DSP DMA per-transfer-specific registers */ static int dsp_dma_setup(struct hda_codec *codec, unsigned int chip_addx, unsigned int count, unsigned int dma_chan) { int status = 0; bool code, yram; unsigned int dsp_addx; unsigned int addr_field; unsigned int incr_field; unsigned int base_cnt; unsigned int cur_cnt; unsigned int dma_cfg = 0; unsigned int adr_ofs = 0; unsigned int xfr_cnt = 0; const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - DSPDMAC_XFRCNT_BCNT_LOBIT + 1); codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); if (count > max_dma_count) { codec_dbg(codec, "count too big\n"); return -EINVAL; } dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); if (dsp_addx == INVALID_CHIP_ADDRESS) { codec_dbg(codec, "invalid chip addr\n"); return -ENXIO; } codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; incr_field = 0; if (!code) { addr_field <<= 1; if (yram) addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); } dma_cfg = addr_field + incr_field; status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), dma_cfg); if (status < 0) { codec_dbg(codec, "write DMACFG Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + (code ? 0 : 1)); status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), adr_ofs); if (status < 0) { codec_dbg(codec, "write DSPADROFS Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; xfr_cnt = base_cnt | cur_cnt; status = chipio_write(codec, DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); if (status < 0) { codec_dbg(codec, "write XFRCNT Reg fail\n"); return status; } codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); codec_dbg(codec, "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " "ADROFS=0x%x, XFRCNT=0x%x\n", chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); return 0; } /* * Start the DSP DMA */ static int dsp_dma_start(struct hda_codec *codec, unsigned int dma_chan, bool ovly) { unsigned int reg = 0; int status = 0; codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); if (ovly) { status = chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &reg); if (status < 0) { codec_dbg(codec, "read CHNLSTART reg fail\n"); return status; } codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | DSPDMAC_CHNLSTART_DIS_MASK); } status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); if (status < 0) { codec_dbg(codec, "write CHNLSTART reg fail\n"); return status; } codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); return status; } /* * Stop the DSP DMA */ static int dsp_dma_stop(struct hda_codec *codec, unsigned int dma_chan, bool ovly) { unsigned int reg = 0; int status = 0; codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); if (ovly) { status = chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &reg); if (status < 0) { codec_dbg(codec, "read CHNLSTART reg fail\n"); return status; } codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | DSPDMAC_CHNLSTART_DIS_MASK); } status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); if (status < 0) { codec_dbg(codec, "write CHNLSTART reg fail\n"); return status; } codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); return status; } /** * dsp_allocate_router_ports - Allocate router ports * * @codec: the HDA codec * @num_chans: number of channels in the stream * @ports_per_channel: number of ports per channel * @start_device: start device * @port_map: pointer to the port list to hold the allocated ports * * Returns zero or a negative error code. */ static int dsp_allocate_router_ports(struct hda_codec *codec, unsigned int num_chans, unsigned int ports_per_channel, unsigned int start_device, unsigned int *port_map) { int status = 0; int res; u8 val; status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); if (status < 0) return status; val = start_device << 6; val |= (ports_per_channel - 1) << 4; val |= num_chans - 1; snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, val); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PORT_ALLOC_SET, MEM_CONNID_DSP); status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); if (status < 0) return status; res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PORT_ALLOC_GET, 0); *port_map = res; return (res < 0) ? res : 0; } /* * Free router ports */ static int dsp_free_router_ports(struct hda_codec *codec) { int status = 0; status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); if (status < 0) return status; snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PORT_FREE_SET, MEM_CONNID_DSP); status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); return status; } /* * Allocate DSP ports for the download stream */ static int dsp_allocate_ports(struct hda_codec *codec, unsigned int num_chans, unsigned int rate_multi, unsigned int *port_map) { int status; codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { codec_dbg(codec, "bad rate multiple\n"); return -EINVAL; } status = dsp_allocate_router_ports(codec, num_chans, rate_multi, 0, port_map); codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); return status; } static int dsp_allocate_ports_format(struct hda_codec *codec, const unsigned short fmt, unsigned int *port_map) { unsigned int num_chans; unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; unsigned int rate_multi = sample_rate_mul / sample_rate_div; if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { codec_dbg(codec, "bad rate multiple\n"); return -EINVAL; } num_chans = get_hdafmt_chs(fmt) + 1; return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); } /* * free DSP ports */ static int dsp_free_ports(struct hda_codec *codec) { int status; codec_dbg(codec, " dsp_free_ports() -- begin\n"); status = dsp_free_router_ports(codec); if (status < 0) { codec_dbg(codec, "free router ports fail\n"); return status; } codec_dbg(codec, " dsp_free_ports() -- complete\n"); return status; } /* * HDA DMA engine stuffs for DSP code download */ struct dma_engine { struct hda_codec *codec; unsigned short m_converter_format; struct snd_dma_buffer *dmab; unsigned int buf_size; }; enum dma_state { DMA_STATE_STOP = 0, DMA_STATE_RUN = 1 }; static int dma_convert_to_hda_format(struct hda_codec *codec, unsigned int sample_rate, unsigned short channels, unsigned short *hda_format) { unsigned int format_val; format_val = snd_hdac_calc_stream_format(sample_rate, channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); if (hda_format) *hda_format = (unsigned short)format_val; return 0; } /* * Reset DMA for DSP download */ static int dma_reset(struct dma_engine *dma) { struct hda_codec *codec = dma->codec; struct ca0132_spec *spec = codec->spec; int status; if (dma->dmab->area) snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); status = snd_hda_codec_load_dsp_prepare(codec, dma->m_converter_format, dma->buf_size, dma->dmab); if (status < 0) return status; spec->dsp_stream_id = status; return 0; } static int dma_set_state(struct dma_engine *dma, enum dma_state state) { bool cmd; switch (state) { case DMA_STATE_STOP: cmd = false; break; case DMA_STATE_RUN: cmd = true; break; default: return 0; } snd_hda_codec_load_dsp_trigger(dma->codec, cmd); return 0; } static unsigned int dma_get_buffer_size(struct dma_engine *dma) { return dma->dmab->bytes; } static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) { return dma->dmab->area; } static int dma_xfer(struct dma_engine *dma, const unsigned int *data, unsigned int count) { memcpy(dma->dmab->area, data, count); return 0; } static void dma_get_converter_format( struct dma_engine *dma, unsigned short *format) { if (format) *format = dma->m_converter_format; } static unsigned int dma_get_stream_id(struct dma_engine *dma) { struct ca0132_spec *spec = dma->codec->spec; return spec->dsp_stream_id; } struct dsp_image_seg { u32 magic; u32 chip_addr; u32 count; u32 data[]; }; static const u32 g_magic_value = 0x4c46584d; static const u32 g_chip_addr_magic_value = 0xFFFFFF01; static bool is_valid(const struct dsp_image_seg *p) { return p->magic == g_magic_value; } static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) { return g_chip_addr_magic_value == p->chip_addr; } static bool is_last(const struct dsp_image_seg *p) { return p->count == 0; } static size_t dsp_sizeof(const struct dsp_image_seg *p) { return struct_size(p, data, p->count); } static const struct dsp_image_seg *get_next_seg_ptr( const struct dsp_image_seg *p) { return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); } /* * CA0132 chip DSP transfer stuffs. For DSP download. */ #define INVALID_DMA_CHANNEL (~0U) /* * Program a list of address/data pairs via the ChipIO widget. * The segment data is in the format of successive pairs of words. * These are repeated as indicated by the segment's count field. */ static int dspxfr_hci_write(struct hda_codec *codec, const struct dsp_image_seg *fls) { int status; const u32 *data; unsigned int count; if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { codec_dbg(codec, "hci_write invalid params\n"); return -EINVAL; } count = fls->count; data = (u32 *)(fls->data); while (count >= 2) { status = chipio_write(codec, data[0], data[1]); if (status < 0) { codec_dbg(codec, "hci_write chipio failed\n"); return status; } count -= 2; data += 2; } return 0; } /** * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. * * @codec: the HDA codec * @fls: pointer to a fast load image * @reloc: Relocation address for loading single-segment overlays, or 0 for * no relocation * @dma_engine: pointer to DMA engine to be used for DSP download * @dma_chan: The number of DMA channels used for DSP download * @port_map_mask: port mapping * @ovly: TRUE if overlay format is required * * Returns zero or a negative error code. */ static int dspxfr_one_seg(struct hda_codec *codec, const struct dsp_image_seg *fls, unsigned int reloc, struct dma_engine *dma_engine, unsigned int dma_chan, unsigned int port_map_mask, bool ovly) { int status = 0; bool comm_dma_setup_done = false; const unsigned int *data; unsigned int chip_addx; unsigned int words_to_write; unsigned int buffer_size_words; unsigned char *buffer_addx; unsigned short hda_format; unsigned int sample_rate_div; unsigned int sample_rate_mul; unsigned int num_chans; unsigned int hda_frame_size_words; unsigned int remainder_words; const u32 *data_remainder; u32 chip_addx_remainder; unsigned int run_size_words; const struct dsp_image_seg *hci_write = NULL; unsigned long timeout; bool dma_active; if (fls == NULL) return -EINVAL; if (is_hci_prog_list_seg(fls)) { hci_write = fls; fls = get_next_seg_ptr(fls); } if (hci_write && (!fls || is_last(fls))) { codec_dbg(codec, "hci_write\n"); return dspxfr_hci_write(codec, hci_write); } if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { codec_dbg(codec, "Invalid Params\n"); return -EINVAL; } data = fls->data; chip_addx = fls->chip_addr; words_to_write = fls->count; if (!words_to_write) return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; if (reloc) chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); if (!UC_RANGE(chip_addx, words_to_write) && !X_RANGE_ALL(chip_addx, words_to_write) && !Y_RANGE_ALL(chip_addx, words_to_write)) { codec_dbg(codec, "Invalid chip_addx Params\n"); return -EINVAL; } buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / sizeof(u32); buffer_addx = dma_get_buffer_addr(dma_engine); if (buffer_addx == NULL) { codec_dbg(codec, "dma_engine buffer NULL\n"); return -EINVAL; } dma_get_converter_format(dma_engine, &hda_format); sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; num_chans = get_hdafmt_chs(hda_format) + 1; hda_frame_size_words = ((sample_rate_div == 0) ? 0 : (num_chans * sample_rate_mul / sample_rate_div)); if (hda_frame_size_words == 0) { codec_dbg(codec, "frmsz zero\n"); return -EINVAL; } buffer_size_words = min(buffer_size_words, (unsigned int)(UC_RANGE(chip_addx, 1) ? 65536 : 32768)); buffer_size_words -= buffer_size_words % hda_frame_size_words; codec_dbg(codec, "chpadr=0x%08x frmsz=%u nchan=%u " "rate_mul=%u div=%u bufsz=%u\n", chip_addx, hda_frame_size_words, num_chans, sample_rate_mul, sample_rate_div, buffer_size_words); if (buffer_size_words < hda_frame_size_words) { codec_dbg(codec, "dspxfr_one_seg:failed\n"); return -EINVAL; } remainder_words = words_to_write % hda_frame_size_words; data_remainder = data; chip_addx_remainder = chip_addx; data += remainder_words; chip_addx += remainder_words*sizeof(u32); words_to_write -= remainder_words; while (words_to_write != 0) { run_size_words = min(buffer_size_words, words_to_write); codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", words_to_write, run_size_words, remainder_words); dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); if (!comm_dma_setup_done) { status = dsp_dma_stop(codec, dma_chan, ovly); if (status < 0) return status; status = dsp_dma_setup_common(codec, chip_addx, dma_chan, port_map_mask, ovly); if (status < 0) return status; comm_dma_setup_done = true; } status = dsp_dma_setup(codec, chip_addx, run_size_words, dma_chan); if (status < 0) return status; status = dsp_dma_start(codec, dma_chan, ovly); if (status < 0) return status; if (!dsp_is_dma_active(codec, dma_chan)) { codec_dbg(codec, "dspxfr:DMA did not start\n"); return -EIO; } status = dma_set_state(dma_engine, DMA_STATE_RUN); if (status < 0) return status; if (remainder_words != 0) { status = chipio_write_multiple(codec, chip_addx_remainder, data_remainder, remainder_words); if (status < 0) return status; remainder_words = 0; } if (hci_write) { status = dspxfr_hci_write(codec, hci_write); if (status < 0) return status; hci_write = NULL; } timeout = jiffies + msecs_to_jiffies(2000); do { dma_active = dsp_is_dma_active(codec, dma_chan); if (!dma_active) break; msleep(20); } while (time_before(jiffies, timeout)); if (dma_active) break; codec_dbg(codec, "+++++ DMA complete\n"); dma_set_state(dma_engine, DMA_STATE_STOP); status = dma_reset(dma_engine); if (status < 0) return status; data += run_size_words; chip_addx += run_size_words*sizeof(u32); words_to_write -= run_size_words; } if (remainder_words != 0) { status = chipio_write_multiple(codec, chip_addx_remainder, data_remainder, remainder_words); } return status; } /** * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories * * @codec: the HDA codec * @fls_data: pointer to a fast load image * @reloc: Relocation address for loading single-segment overlays, or 0 for * no relocation * @sample_rate: sampling rate of the stream used for DSP download * @channels: channels of the stream used for DSP download * @ovly: TRUE if overlay format is required * * Returns zero or a negative error code. */ static int dspxfr_image(struct hda_codec *codec, const struct dsp_image_seg *fls_data, unsigned int reloc, unsigned int sample_rate, unsigned short channels, bool ovly) { struct ca0132_spec *spec = codec->spec; int status; unsigned short hda_format = 0; unsigned int response; unsigned char stream_id = 0; struct dma_engine *dma_engine; unsigned int dma_chan; unsigned int port_map_mask; if (fls_data == NULL) return -EINVAL; dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); if (!dma_engine) return -ENOMEM; dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); if (!dma_engine->dmab) { kfree(dma_engine); return -ENOMEM; } dma_engine->codec = codec; dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); dma_engine->m_converter_format = hda_format; dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : DSP_DMA_WRITE_BUFLEN_INIT) * 2; dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, hda_format, &response); if (status < 0) { codec_dbg(codec, "set converter format fail\n"); goto exit; } status = snd_hda_codec_load_dsp_prepare(codec, dma_engine->m_converter_format, dma_engine->buf_size, dma_engine->dmab); if (status < 0) goto exit; spec->dsp_stream_id = status; if (ovly) { status = dspio_alloc_dma_chan(codec, &dma_chan); if (status < 0) { codec_dbg(codec, "alloc dmachan fail\n"); dma_chan = INVALID_DMA_CHANNEL; goto exit; } } port_map_mask = 0; status = dsp_allocate_ports_format(codec, hda_format, &port_map_mask); if (status < 0) { codec_dbg(codec, "alloc ports fail\n"); goto exit; } stream_id = dma_get_stream_id(dma_engine); status = codec_set_converter_stream_channel(codec, WIDGET_CHIP_CTRL, stream_id, 0, &response); if (status < 0) { codec_dbg(codec, "set stream chan fail\n"); goto exit; } while ((fls_data != NULL) && !is_last(fls_data)) { if (!is_valid(fls_data)) { codec_dbg(codec, "FLS check fail\n"); status = -EINVAL; goto exit; } status = dspxfr_one_seg(codec, fls_data, reloc, dma_engine, dma_chan, port_map_mask, ovly); if (status < 0) break; if (is_hci_prog_list_seg(fls_data)) fls_data = get_next_seg_ptr(fls_data); if ((fls_data != NULL) && !is_last(fls_data)) fls_data = get_next_seg_ptr(fls_data); } if (port_map_mask != 0) status = dsp_free_ports(codec); if (status < 0) goto exit; status = codec_set_converter_stream_channel(codec, WIDGET_CHIP_CTRL, 0, 0, &response); exit: if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) dspio_free_dma_chan(codec, dma_chan); if (dma_engine->dmab->area) snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); kfree(dma_engine->dmab); kfree(dma_engine); return status; } /* * CA0132 DSP download stuffs. */ static void dspload_post_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; codec_dbg(codec, "---- dspload_post_setup ------\n"); if (!ca0132_use_alt_functions(spec)) { /*set DSP speaker to 2.0 configuration*/ chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); /*update write pointer*/ chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); } } /** * dspload_image - Download DSP from a DSP Image Fast Load structure. * * @codec: the HDA codec * @fls: pointer to a fast load image * @ovly: TRUE if overlay format is required * @reloc: Relocation address for loading single-segment overlays, or 0 for * no relocation * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE * @router_chans: number of audio router channels to be allocated (0 means use * internal defaults; max is 32) * * Download DSP from a DSP Image Fast Load structure. This structure is a * linear, non-constant sized element array of structures, each of which * contain the count of the data to be loaded, the data itself, and the * corresponding starting chip address of the starting data location. * Returns zero or a negative error code. */ static int dspload_image(struct hda_codec *codec, const struct dsp_image_seg *fls, bool ovly, unsigned int reloc, bool autostart, int router_chans) { int status = 0; unsigned int sample_rate; unsigned short channels; codec_dbg(codec, "---- dspload_image begin ------\n"); if (router_chans == 0) { if (!ovly) router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; else router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; } sample_rate = 48000; channels = (unsigned short)router_chans; while (channels > 16) { sample_rate *= 2; channels /= 2; } do { codec_dbg(codec, "Ready to program DMA\n"); if (!ovly) status = dsp_reset(codec); if (status < 0) break; codec_dbg(codec, "dsp_reset() complete\n"); status = dspxfr_image(codec, fls, reloc, sample_rate, channels, ovly); if (status < 0) break; codec_dbg(codec, "dspxfr_image() complete\n"); if (autostart && !ovly) { dspload_post_setup(codec); status = dsp_set_run_state(codec); } codec_dbg(codec, "LOAD FINISHED\n"); } while (0); return status; } #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP static bool dspload_is_loaded(struct hda_codec *codec) { unsigned int data = 0; int status = 0; status = chipio_read(codec, 0x40004, &data); if ((status < 0) || (data != 1)) return false; return true; } #else #define dspload_is_loaded(codec) false #endif static bool dspload_wait_loaded(struct hda_codec *codec) { unsigned long timeout = jiffies + msecs_to_jiffies(2000); do { if (dspload_is_loaded(codec)) { codec_info(codec, "ca0132 DSP downloaded and running\n"); return true; } msleep(20); } while (time_before(jiffies, timeout)); codec_err(codec, "ca0132 failed to download DSP\n"); return false; } /* * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e * based cards, and has a second mmio region, region2, that's used for special * commands. */ /* * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) * the mmio address 0x320 is used to set GPIO pins. The format for the data * The first eight bits are just the number of the pin. So far, I've only seen * this number go to 7. * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and * then off to send that bit. */ static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, bool enable) { struct ca0132_spec *spec = codec->spec; unsigned short gpio_data; gpio_data = gpio_pin & 0xF; gpio_data |= ((enable << 8) & 0x100); writew(gpio_data, spec->mem_base + 0x320); } /* * Special pci region2 commands that are only used by the AE-5. They follow * a set format, and require reads at certain points to seemingly 'clear' * the response data. My first tests didn't do these reads, and would cause * the card to get locked up until the memory was read. These commands * seem to work with three distinct values that I've taken to calling group, * target-id, and value. */ static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, unsigned int target, unsigned int value) { struct ca0132_spec *spec = codec->spec; unsigned int write_val; writel(0x0000007e, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); writel(0x0000005a, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); readl(spec->mem_base + 0x210); writel(0x00800005, spec->mem_base + 0x20c); writel(group, spec->mem_base + 0x804); writel(0x00800005, spec->mem_base + 0x20c); write_val = (target & 0xff); write_val |= (value << 8); writel(write_val, spec->mem_base + 0x204); /* * Need delay here or else it goes too fast and works inconsistently. */ msleep(20); readl(spec->mem_base + 0x860); readl(spec->mem_base + 0x854); readl(spec->mem_base + 0x840); writel(0x00800004, spec->mem_base + 0x20c); writel(0x00000000, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); readl(spec->mem_base + 0x210); } /* * This second type of command is used for setting the sound filter type. */ static void ca0113_mmio_command_set_type2(struct hda_codec *codec, unsigned int group, unsigned int target, unsigned int value) { struct ca0132_spec *spec = codec->spec; unsigned int write_val; writel(0x0000007e, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); writel(0x0000005a, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); readl(spec->mem_base + 0x210); writel(0x00800003, spec->mem_base + 0x20c); writel(group, spec->mem_base + 0x804); writel(0x00800005, spec->mem_base + 0x20c); write_val = (target & 0xff); write_val |= (value << 8); writel(write_val, spec->mem_base + 0x204); msleep(20); readl(spec->mem_base + 0x860); readl(spec->mem_base + 0x854); readl(spec->mem_base + 0x840); writel(0x00800004, spec->mem_base + 0x20c); writel(0x00000000, spec->mem_base + 0x210); readl(spec->mem_base + 0x210); readl(spec->mem_base + 0x210); } /* * Setup GPIO for the other variants of Core3D. */ /* * Sets up the GPIO pins so that they are discoverable. If this isn't done, * the card shows as having no GPIO pins. */ static void ca0132_gpio_init(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_AE5: case QUIRK_AE7: snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); break; case QUIRK_R3DI: snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); break; default: break; } } /* Sets the GPIO for audio output. */ static void ca0132_gpio_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; switch (ca0132_quirk(spec)) { case QUIRK_SBZ: snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, 0x07); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, 0x07); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x04); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x06); break; case QUIRK_R3DI: snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, 0x1E); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, 0x1F); snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x0C); break; default: break; } } /* * GPIO control functions for the Recon3D integrated. */ enum r3di_gpio_bit { /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ R3DI_MIC_SELECT_BIT = 1, /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ R3DI_OUT_SELECT_BIT = 2, /* * I dunno what this actually does, but it stays on until the dsp * is downloaded. */ R3DI_GPIO_DSP_DOWNLOADING = 3, /* * Same as above, no clue what it does, but it comes on after the dsp * is downloaded. */ R3DI_GPIO_DSP_DOWNLOADED = 4 }; enum r3di_mic_select { /* Set GPIO bit 1 to 0 for rear mic */ R3DI_REAR_MIC = 0, /* Set GPIO bit 1 to 1 for front microphone*/ R3DI_FRONT_MIC = 1 }; enum r3di_out_select { /* Set GPIO bit 2 to 0 for headphone */ R3DI_HEADPHONE_OUT = 0, /* Set GPIO bit 2 to 1 for speaker */ R3DI_LINE_OUT = 1 }; enum r3di_dsp_status { /* Set GPIO bit 3 to 1 until DSP is downloaded */ R3DI_DSP_DOWNLOADING = 0, /* Set GPIO bit 4 to 1 once DSP is downloaded */ R3DI_DSP_DOWNLOADED = 1 }; static void r3di_gpio_mic_set(struct hda_codec *codec, enum r3di_mic_select cur_mic) { unsigned int cur_gpio; /* Get the current GPIO Data setup */ cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); switch (cur_mic) { case R3DI_REAR_MIC: cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); break; case R3DI_FRONT_MIC: cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); break; } snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, cur_gpio); } static void r3di_gpio_dsp_status_set(struct hda_codec *codec, enum r3di_dsp_status dsp_status) { unsigned int cur_gpio; /* Get the current GPIO Data setup */ cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); switch (dsp_status) { case R3DI_DSP_DOWNLOADING: cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, cur_gpio); break; case R3DI_DSP_DOWNLOADED: /* Set DOWNLOADING bit to 0. */ cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, cur_gpio); cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); break; } snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, cur_gpio); } /* * PCM callbacks */ static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); return 0; } static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; if (spec->dsp_state == DSP_DOWNLOADING) return 0; /*If Playback effects are on, allow stream some time to flush *effects tail*/ if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) msleep(50); snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); return 0; } static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; struct snd_pcm_runtime *runtime = substream->runtime; if (spec->dsp_state != DSP_DOWNLOADED) return 0; /* Add latency if playback enhancement and either effect is enabled. */ if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) latency += DSP_PLAY_ENHANCEMENT_LATENCY; } /* Applying Speaker EQ adds latency as well. */ if (spec->cur_out_type == SPEAKER_OUT) latency += DSP_SPEAKER_OUT_LATENCY; return (latency * runtime->rate) / 1000; } /* * Digital out */ static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; return snd_hda_multi_out_dig_open(codec, &spec->multiout); } static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag, format, substream); } static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); } static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; return snd_hda_multi_out_dig_close(codec, &spec->multiout); } /* * Analog capture */ static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { snd_hda_codec_setup_stream(codec, hinfo->nid, stream_tag, 0, format); return 0; } static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; if (spec->dsp_state == DSP_DOWNLOADING) return 0; snd_hda_codec_cleanup_stream(codec, hinfo->nid); return 0; } static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct ca0132_spec *spec = codec->spec; unsigned int latency = DSP_CAPTURE_INIT_LATENCY; struct snd_pcm_runtime *runtime = substream->runtime; if (spec->dsp_state != DSP_DOWNLOADED) return 0; if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) latency += DSP_CRYSTAL_VOICE_LATENCY; return (latency * runtime->rate) / 1000; } /* * Controls stuffs. */ /* * Mixer controls helpers. */ #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .subdevice = HDA_SUBDEV_AMP_FLAG, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ .info = ca0132_volume_info, \ .get = ca0132_volume_get, \ .put = ca0132_volume_put, \ .tlv = { .c = ca0132_volume_tlv }, \ .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } /* * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the * volume put, which is used for setting the DSP volume. This was done because * the ca0132 functions were taking too much time and causing lag. */ #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .subdevice = HDA_SUBDEV_AMP_FLAG, \ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ .info = snd_hda_mixer_amp_volume_info, \ .get = snd_hda_mixer_amp_volume_get, \ .put = ca0132_alt_volume_put, \ .tlv = { .c = snd_hda_mixer_amp_tlv }, \ .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ .name = xname, \ .subdevice = HDA_SUBDEV_AMP_FLAG, \ .info = snd_hda_mixer_amp_switch_info, \ .get = ca0132_switch_get, \ .put = ca0132_switch_put, \ .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } /* stereo */ #define CA0132_CODEC_VOL(xname, nid, dir) \ CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) #define CA0132_CODEC_MUTE(xname, nid, dir) \ CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) /* lookup tables */ /* * Lookup table with decibel values for the DSP. When volume is changed in * Windows, the DSP is also sent the dB value in floating point. In Windows, * these values have decimal points, probably because the Windows driver * actually uses floating point. We can't here, so I made a lookup table of * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the * DAC's, and 9 is the maximum. */ static const unsigned int float_vol_db_lookup[] = { 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 }; /* * This table counts from float 0 to 1 in increments of .01, which is * useful for a few different sliders. */ static const unsigned int float_zero_to_one_lookup[] = { 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 }; /* * This table counts from float 10 to 1000, which is the range of the x-bass * crossover slider in Windows. */ static const unsigned int float_xbass_xover_lookup[] = { 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 0x44728000, 0x44750000, 0x44778000, 0x447A0000 }; /* The following are for tuning of products */ #ifdef ENABLE_TUNING_CONTROLS static const unsigned int voice_focus_vals_lookup[] = { 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 }; static const unsigned int mic_svm_vals_lookup[] = { 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 }; static const unsigned int equalizer_vals_lookup[] = { 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000 }; static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, const unsigned int *lookup, int idx) { int i = 0; for (i = 0; i < TUNING_CTLS_COUNT; i++) if (nid == ca0132_tuning_ctls[i].nid) goto found; return -EINVAL; found: snd_hda_power_up(codec); dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, ca0132_tuning_ctls[i].req, &(lookup[idx]), sizeof(unsigned int)); snd_hda_power_down(codec); return 1; } static int tuning_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx = nid - TUNING_CTL_START_NID; *valp = spec->cur_ctl_vals[idx]; return 0; } static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int chs = get_amp_channels(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 20; uinfo->value.integer.max = 180; uinfo->value.integer.step = 1; return 0; } static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx; idx = nid - TUNING_CTL_START_NID; /* any change? */ if (spec->cur_ctl_vals[idx] == *valp) return 0; spec->cur_ctl_vals[idx] = *valp; idx = *valp - 20; tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); return 1; } static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int chs = get_amp_channels(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 100; uinfo->value.integer.step = 1; return 0; } static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx; idx = nid - TUNING_CTL_START_NID; /* any change? */ if (spec->cur_ctl_vals[idx] == *valp) return 0; spec->cur_ctl_vals[idx] = *valp; idx = *valp; tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); return 0; } static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int chs = get_amp_channels(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 48; uinfo->value.integer.step = 1; return 0; } static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx; idx = nid - TUNING_CTL_START_NID; /* any change? */ if (spec->cur_ctl_vals[idx] == *valp) return 0; spec->cur_ctl_vals[idx] = *valp; idx = *valp; tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); return 1; } static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); static int add_tuning_control(struct hda_codec *codec, hda_nid_t pnid, hda_nid_t nid, const char *name, int dir) { char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; int type = dir ? HDA_INPUT : HDA_OUTPUT; struct snd_kcontrol_new knew = HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ; knew.tlv.c = 0; knew.tlv.p = 0; switch (pnid) { case VOICE_FOCUS: knew.info = voice_focus_ctl_info; knew.get = tuning_ctl_get; knew.put = voice_focus_ctl_put; knew.tlv.p = voice_focus_db_scale; break; case MIC_SVM: knew.info = mic_svm_ctl_info; knew.get = tuning_ctl_get; knew.put = mic_svm_ctl_put; break; case EQUALIZER: knew.info = equalizer_ctl_info; knew.get = tuning_ctl_get; knew.put = equalizer_ctl_put; knew.tlv.p = eq_db_scale; break; default: return 0; } knew.private_value = HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); sprintf(namestr, "%s %s Volume", name, dirstr[dir]); return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); } static int add_tuning_ctls(struct hda_codec *codec) { int i; int err; for (i = 0; i < TUNING_CTLS_COUNT; i++) { err = add_tuning_control(codec, ca0132_tuning_ctls[i].parent_nid, ca0132_tuning_ctls[i].nid, ca0132_tuning_ctls[i].name, ca0132_tuning_ctls[i].direct); if (err < 0) return err; } return 0; } static void ca0132_init_tuning_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int i; /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; /* SVM level defaults to 0.74. */ spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; /* EQ defaults to 0dB. */ for (i = 2; i < TUNING_CTLS_COUNT; i++) spec->cur_ctl_vals[i] = 24; } #endif /*ENABLE_TUNING_CONTROLS*/ /* * Select the active output. * If autodetect is enabled, output will be selected based on jack detection. * If jack inserted, headphone will be selected, else built-in speakers * If autodetect is disabled, output will be selected based on selection. */ static int ca0132_select_out(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int pin_ctl; int jack_present; int auto_jack; unsigned int tmp; int err; codec_dbg(codec, "ca0132_select_out\n"); snd_hda_power_up_pm(codec); auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; if (auto_jack) jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); else jack_present = spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; if (jack_present) spec->cur_out_type = HEADPHONE_OUT; else spec->cur_out_type = SPEAKER_OUT; if (spec->cur_out_type == SPEAKER_OUT) { codec_dbg(codec, "ca0132_select_out speaker\n"); /*speaker out config*/ tmp = FLOAT_ONE; err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); if (err < 0) goto exit; /*enable speaker EQ*/ tmp = FLOAT_ONE; err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); if (err < 0) goto exit; /* Setup EAPD */ snd_hda_codec_write(codec, spec->out_pins[1], 0, VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); snd_hda_codec_write(codec, spec->out_pins[0], 0, VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x02); /* disable headphone node */ pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_set_pin_ctl(codec, spec->out_pins[1], pin_ctl & ~PIN_HP); /* enable speaker node */ pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_set_pin_ctl(codec, spec->out_pins[0], pin_ctl | PIN_OUT); } else { codec_dbg(codec, "ca0132_select_out hp\n"); /*headphone out config*/ tmp = FLOAT_ZERO; err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); if (err < 0) goto exit; /*disable speaker EQ*/ tmp = FLOAT_ZERO; err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); if (err < 0) goto exit; /* Setup EAPD */ snd_hda_codec_write(codec, spec->out_pins[0], 0, VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); snd_hda_codec_write(codec, spec->out_pins[1], 0, VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x02); /* disable speaker*/ pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_set_pin_ctl(codec, spec->out_pins[0], pin_ctl & ~PIN_HP); /* enable headphone*/ pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_set_pin_ctl(codec, spec->out_pins[1], pin_ctl | PIN_HP); } exit: snd_hda_power_down_pm(codec); return err < 0 ? err : 0; } static int ae5_headphone_gain_set(struct hda_codec *codec, long val); static int zxr_headphone_gain_set(struct hda_codec *codec, long val); static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); static void ae5_mmio_select_out(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; const struct ae_ca0113_output_set *out_cmds; unsigned int i; if (ca0132_quirk(spec) == QUIRK_AE5) out_cmds = &ae5_ca0113_output_presets; else out_cmds = &ae7_ca0113_output_presets; for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) ca0113_mmio_command_set(codec, out_cmds->group[i], out_cmds->target[i], out_cmds->vals[spec->cur_out_type][i]); } static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int quirk = ca0132_quirk(spec); unsigned int tmp; int err; /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) return 0; /* Set front L/R full range. Zero for full-range, one for redirection. */ tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; err = dspio_set_uint_param(codec, 0x96, SPEAKER_FULL_RANGE_FRONT_L_R, tmp); if (err < 0) return err; /* When setting full-range rear, both rear and center/lfe are set. */ tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; err = dspio_set_uint_param(codec, 0x96, SPEAKER_FULL_RANGE_CENTER_LFE, tmp); if (err < 0) return err; err = dspio_set_uint_param(codec, 0x96, SPEAKER_FULL_RANGE_REAR_L_R, tmp); if (err < 0) return err; /* * Only the AE series cards set this value when setting full-range, * and it's always 1.0f. */ if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { err = dspio_set_uint_param(codec, 0x96, SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); if (err < 0) return err; } return 0; } static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, bool val) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int err; if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) tmp = FLOAT_ONE; else tmp = FLOAT_ZERO; err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); if (err < 0) return err; /* If it is enabled, make sure to set the crossover frequency. */ if (tmp) { tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); if (err < 0) return err; } return 0; } /* * These are the commands needed to setup output on each of the different card * types. */ static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, const struct ca0132_alt_out_set_quirk_data **quirk_data) { struct ca0132_spec *spec = codec->spec; int quirk = ca0132_quirk(spec); unsigned int i; *quirk_data = NULL; for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { if (quirk_out_set_data[i].quirk_id == quirk) { *quirk_data = &quirk_out_set_data[i]; return; } } } static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) { const struct ca0132_alt_out_set_quirk_data *quirk_data; const struct ca0132_alt_out_set_info *out_info; struct ca0132_spec *spec = codec->spec; unsigned int i, gpio_data; int err; ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); if (!quirk_data) return 0; out_info = &quirk_data->out_set_info[spec->cur_out_type]; if (quirk_data->is_ae_series) ae5_mmio_select_out(codec); if (out_info->has_hda_gpio) { gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, AC_VERB_GET_GPIO_DATA, 0); if (out_info->hda_gpio_set) gpio_data |= (1 << out_info->hda_gpio_pin); else gpio_data &= ~(1 << out_info->hda_gpio_pin); snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, gpio_data); } if (out_info->mmio_gpio_count) { for (i = 0; i < out_info->mmio_gpio_count; i++) { ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], out_info->mmio_gpio_set[i]); } } if (out_info->scp_cmds_count) { for (i = 0; i < out_info->scp_cmds_count; i++) { err = dspio_set_uint_param(codec, out_info->scp_cmd_mid[i], out_info->scp_cmd_req[i], out_info->scp_cmd_val[i]); if (err < 0) return err; } } chipio_set_control_param(codec, 0x0d, out_info->dac2port); if (out_info->has_chipio_write) { chipio_write(codec, out_info->chipio_write_addr, out_info->chipio_write_data); } if (quirk_data->has_headphone_gain) { if (spec->cur_out_type != HEADPHONE_OUT) { if (quirk_data->is_ae_series) ae5_headphone_gain_set(codec, 2); else zxr_headphone_gain_set(codec, 0); } else { if (quirk_data->is_ae_series) ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); else zxr_headphone_gain_set(codec, spec->zxr_gain_set); } } return 0; } static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, bool out_enable, bool hp_enable) { unsigned int pin_ctl; pin_ctl = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; snd_hda_set_pin_ctl(codec, nid, pin_ctl); } /* * This function behaves similarly to the ca0132_select_out funciton above, * except with a few differences. It adds the ability to select the current * output with an enumerated control "output source" if the auto detect * mute switch is set to off. If the auto detect mute switch is enabled, it * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. * It also adds the ability to auto-detect the front headphone port. */ static int ca0132_alt_select_out(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp, outfx_set; int jack_present; int auto_jack; int err; /* Default Headphone is rear headphone */ hda_nid_t headphone_nid = spec->out_pins[1]; codec_dbg(codec, "%s\n", __func__); snd_hda_power_up_pm(codec); auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; /* * If headphone rear or front is plugged in, set to headphone. * If neither is plugged in, set to rear line out. Only if * hp/speaker auto detect is enabled. */ if (auto_jack) { jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); if (jack_present) spec->cur_out_type = HEADPHONE_OUT; else spec->cur_out_type = SPEAKER_OUT; } else spec->cur_out_type = spec->out_enum_val; outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; /* Begin DSP output switch, mute DSP volume. */ err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); if (err < 0) goto exit; if (ca0132_alt_select_out_quirk_set(codec) < 0) goto exit; switch (spec->cur_out_type) { case SPEAKER_OUT: codec_dbg(codec, "%s speaker\n", __func__); /* Enable EAPD */ snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x01); /* Disable headphone node. */ ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); /* Set front L-R to output. */ ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); /* Set Center/LFE to output. */ ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); /* Set rear surround to output. */ ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); /* * Without PlayEnhancement being enabled, if we've got a 2.0 * setup, set it to floating point eight to disable any DSP * processing effects. */ if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) tmp = FLOAT_EIGHT; else tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); if (err < 0) goto exit; break; case HEADPHONE_OUT: codec_dbg(codec, "%s hp\n", __func__); snd_hda_codec_write(codec, spec->out_pins[0], 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); /* Disable all speaker nodes. */ ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); /* enable headphone, either front or rear */ if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) headphone_nid = spec->out_pins[2]; else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) headphone_nid = spec->out_pins[1]; ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); if (outfx_set) err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); else err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); if (err < 0) goto exit; break; } /* * If output effects are enabled, set the X-Bass effect value again to * make sure that it's properly enabled/disabled for speaker * configurations with an LFE channel. */ if (outfx_set) ca0132_effects_set(codec, X_BASS, spec->effects_switch[X_BASS - EFFECT_START_NID]); /* Set speaker EQ bypass attenuation to 0. */ err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); if (err < 0) goto exit; /* * Although unused on all cards but the AE series, this is always set * to zero when setting the output. */ err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); if (err < 0) goto exit; if (spec->cur_out_type == SPEAKER_OUT) err = ca0132_alt_surround_set_bass_redirection(codec, spec->bass_redirection_val); else err = ca0132_alt_surround_set_bass_redirection(codec, 0); /* Unmute DSP now that we're done with output selection. */ err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ZERO); if (err < 0) goto exit; if (spec->cur_out_type == SPEAKER_OUT) { err = ca0132_alt_set_full_range_speaker(codec); if (err < 0) goto exit; } exit: snd_hda_power_down_pm(codec); return err < 0 ? err : 0; } static void ca0132_unsol_hp_delayed(struct work_struct *work) { struct ca0132_spec *spec = container_of( to_delayed_work(work), struct ca0132_spec, unsol_hp_work); struct hda_jack_tbl *jack; if (ca0132_use_alt_functions(spec)) ca0132_alt_select_out(spec->codec); else ca0132_select_out(spec->codec); jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); if (jack) { jack->block_report = 0; snd_hda_jack_report_sync(spec->codec); } } static void ca0132_set_dmic(struct hda_codec *codec, int enable); static int ca0132_mic_boost_set(struct hda_codec *codec, long val); static void resume_mic1(struct hda_codec *codec, unsigned int oldval); static int stop_mic1(struct hda_codec *codec); static int ca0132_cvoice_switch_set(struct hda_codec *codec); static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); /* * Select the active VIP source */ static int ca0132_set_vipsource(struct hda_codec *codec, int val) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; if (spec->dsp_state != DSP_DOWNLOADED) return 0; /* if CrystalVoice if off, vipsource should be 0 */ if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || (val == 0)) { chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (spec->cur_mic_type == DIGITAL_MIC) tmp = FLOAT_TWO; else tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x80, 0x05, tmp); } else { chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); if (spec->cur_mic_type == DIGITAL_MIC) tmp = FLOAT_TWO; else tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x05, tmp); msleep(20); chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); } return 1; } static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; if (spec->dsp_state != DSP_DOWNLOADED) return 0; codec_dbg(codec, "%s\n", __func__); chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); /* if CrystalVoice is off, vipsource should be 0 */ if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || (val == 0) || spec->in_enum_val == REAR_LINE_IN) { codec_dbg(codec, "%s: off.", __func__); chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x80, 0x05, tmp); chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_96_000); if (spec->in_enum_val == REAR_LINE_IN) tmp = FLOAT_ZERO; else { if (ca0132_quirk(spec) == QUIRK_SBZ) tmp = FLOAT_THREE; else tmp = FLOAT_ONE; } dspio_set_uint_param(codec, 0x80, 0x00, tmp); } else { codec_dbg(codec, "%s: on.", __func__); chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_16_000); if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) tmp = FLOAT_TWO; else tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x05, tmp); msleep(20); chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); } chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); return 1; } /* * Select the active microphone. * If autodetect is enabled, mic will be selected based on jack detection. * If jack inserted, ext.mic will be selected, else built-in mic * If autodetect is disabled, mic will be selected based on selection. */ static int ca0132_select_mic(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int jack_present; int auto_jack; codec_dbg(codec, "ca0132_select_mic\n"); snd_hda_power_up_pm(codec); auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; if (auto_jack) jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); else jack_present = spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; if (jack_present) spec->cur_mic_type = LINE_MIC_IN; else spec->cur_mic_type = DIGITAL_MIC; if (spec->cur_mic_type == DIGITAL_MIC) { /* enable digital Mic */ chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); ca0132_set_dmic(codec, 1); ca0132_mic_boost_set(codec, 0); /* set voice focus */ ca0132_effects_set(codec, VOICE_FOCUS, spec->effects_switch [VOICE_FOCUS - EFFECT_START_NID]); } else { /* disable digital Mic */ chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); ca0132_set_dmic(codec, 0); ca0132_mic_boost_set(codec, spec->cur_mic_boost); /* disable voice focus */ ca0132_effects_set(codec, VOICE_FOCUS, 0); } snd_hda_power_down_pm(codec); return 0; } /* * Select the active input. * Mic detection isn't used, because it's kind of pointless on the SBZ. * The front mic has no jack-detection, so the only way to switch to it * is to do it manually in alsamixer. */ static int ca0132_alt_select_in(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; codec_dbg(codec, "%s\n", __func__); snd_hda_power_up_pm(codec); chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); spec->cur_mic_type = spec->in_enum_val; switch (spec->cur_mic_type) { case REAR_MIC: switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_R3D: ca0113_mmio_gpio_set(codec, 0, false); tmp = FLOAT_THREE; break; case QUIRK_ZXR: tmp = FLOAT_THREE; break; case QUIRK_R3DI: r3di_gpio_mic_set(codec, R3DI_REAR_MIC); tmp = FLOAT_ONE; break; case QUIRK_AE5: ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); tmp = FLOAT_THREE; break; case QUIRK_AE7: ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); tmp = FLOAT_THREE; chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); break; default: tmp = FLOAT_ONE; break; } chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_96_000); dspio_set_uint_param(codec, 0x80, 0x00, tmp); chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: chipio_write(codec, 0x18B098, 0x0000000C); chipio_write(codec, 0x18B09C, 0x0000000C); break; case QUIRK_ZXR: chipio_write(codec, 0x18B098, 0x0000000C); chipio_write(codec, 0x18B09C, 0x000000CC); break; case QUIRK_AE5: chipio_write(codec, 0x18B098, 0x0000000C); chipio_write(codec, 0x18B09C, 0x0000004C); break; default: break; } ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); break; case REAR_LINE_IN: ca0132_mic_boost_set(codec, 0); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_R3D: ca0113_mmio_gpio_set(codec, 0, false); break; case QUIRK_R3DI: r3di_gpio_mic_set(codec, R3DI_REAR_MIC); break; case QUIRK_AE5: ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); break; case QUIRK_AE7: ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); break; default: break; } chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_96_000); if (ca0132_quirk(spec) == QUIRK_AE7) tmp = FLOAT_THREE; else tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x80, 0x00, tmp); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_AE5: chipio_write(codec, 0x18B098, 0x00000000); chipio_write(codec, 0x18B09C, 0x00000000); break; default: break; } chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); break; case FRONT_MIC: switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_R3D: ca0113_mmio_gpio_set(codec, 0, true); ca0113_mmio_gpio_set(codec, 5, false); tmp = FLOAT_THREE; break; case QUIRK_R3DI: r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); tmp = FLOAT_ONE; break; case QUIRK_AE5: ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); tmp = FLOAT_THREE; break; default: tmp = FLOAT_ONE; break; } chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_96_000); dspio_set_uint_param(codec, 0x80, 0x00, tmp); chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: chipio_write(codec, 0x18B098, 0x0000000C); chipio_write(codec, 0x18B09C, 0x000000CC); break; case QUIRK_AE5: chipio_write(codec, 0x18B098, 0x0000000C); chipio_write(codec, 0x18B09C, 0x0000004C); break; default: break; } ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); break; } ca0132_cvoice_switch_set(codec); snd_hda_power_down_pm(codec); return 0; } /* * Check if VNODE settings take effect immediately. */ static bool ca0132_is_vnode_effective(struct hda_codec *codec, hda_nid_t vnid, hda_nid_t *shared_nid) { struct ca0132_spec *spec = codec->spec; hda_nid_t nid; switch (vnid) { case VNID_SPK: nid = spec->shared_out_nid; break; case VNID_MIC: nid = spec->shared_mic_nid; break; default: return false; } if (shared_nid) *shared_nid = nid; return true; } /* * The following functions are control change helpers. * They return 0 if no changed. Return 1 if changed. */ static int ca0132_voicefx_set(struct hda_codec *codec, int enable) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; /* based on CrystalVoice state to enable VoiceFX. */ if (enable) { tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? FLOAT_ONE : FLOAT_ZERO; } else { tmp = FLOAT_ZERO; } dspio_set_uint_param(codec, ca0132_voicefx.mid, ca0132_voicefx.reqs[0], tmp); return 1; } /* * Set the effects parameters */ static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) { struct ca0132_spec *spec = codec->spec; unsigned int on, tmp, channel_cfg; int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; int err = 0; int idx = nid - EFFECT_START_NID; if ((idx < 0) || (idx >= num_fx)) return 0; /* no changed */ /* for out effect, qualify with PE */ if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { /* if PE if off, turn off out effects. */ if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) val = 0; if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { channel_cfg = spec->channel_cfg_val; if (channel_cfg != SPEAKER_CHANNELS_2_0 && channel_cfg != SPEAKER_CHANNELS_4_0) val = 0; } } /* for in effect, qualify with CrystalVoice */ if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { /* if CrystalVoice if off, turn off in effects. */ if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) val = 0; /* Voice Focus applies to 2-ch Mic, Digital Mic */ if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) val = 0; /* If Voice Focus on SBZ, set to two channel. */ if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) && (spec->cur_mic_type != REAR_LINE_IN)) { if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) { if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) { tmp = FLOAT_TWO; val = 1; } else tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); } } /* * For SBZ noise reduction, there's an extra command * to module ID 0x47. No clue why. */ if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) && (spec->cur_mic_type != REAR_LINE_IN)) { if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) { if (spec->effects_switch[NOISE_REDUCTION - EFFECT_START_NID]) tmp = FLOAT_ONE; else tmp = FLOAT_ZERO; } else tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x47, 0x00, tmp); } /* If rear line in disable effects. */ if (ca0132_use_alt_functions(spec) && spec->in_enum_val == REAR_LINE_IN) val = 0; } codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", nid, val); on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[0], on); if (err < 0) return 0; /* no changed */ return 1; } /* * Turn on/off Playback Enhancements */ static int ca0132_pe_switch_set(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; hda_nid_t nid; int i, ret = 0; codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); if (ca0132_use_alt_functions(spec)) ca0132_alt_select_out(codec); i = OUT_EFFECT_START_NID - EFFECT_START_NID; nid = OUT_EFFECT_START_NID; /* PE affects all out effects */ for (; nid < OUT_EFFECT_END_NID; nid++, i++) ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); return ret; } /* Check if Mic1 is streaming, if so, stop streaming */ static int stop_mic1(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, AC_VERB_GET_CONV, 0); if (oldval != 0) snd_hda_codec_write(codec, spec->adcs[0], 0, AC_VERB_SET_CHANNEL_STREAMID, 0); return oldval; } /* Resume Mic1 streaming if it was stopped. */ static void resume_mic1(struct hda_codec *codec, unsigned int oldval) { struct ca0132_spec *spec = codec->spec; /* Restore the previous stream and channel */ if (oldval != 0) snd_hda_codec_write(codec, spec->adcs[0], 0, AC_VERB_SET_CHANNEL_STREAMID, oldval); } /* * Turn on/off CrystalVoice */ static int ca0132_cvoice_switch_set(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; hda_nid_t nid; int i, ret = 0; unsigned int oldval; codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); i = IN_EFFECT_START_NID - EFFECT_START_NID; nid = IN_EFFECT_START_NID; /* CrystalVoice affects all in effects */ for (; nid < IN_EFFECT_END_NID; nid++, i++) ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); /* including VoiceFX */ ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); /* set correct vipsource */ oldval = stop_mic1(codec); if (ca0132_use_alt_functions(spec)) ret |= ca0132_alt_set_vipsource(codec, 1); else ret |= ca0132_set_vipsource(codec, 1); resume_mic1(codec, oldval); return ret; } static int ca0132_mic_boost_set(struct hda_codec *codec, long val) { struct ca0132_spec *spec = codec->spec; int ret = 0; if (val) /* on */ ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); else /* off */ ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); return ret; } static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) { struct ca0132_spec *spec = codec->spec; int ret = 0; ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, HDA_INPUT, 0, HDA_AMP_VOLMASK, val); return ret; } static int ae5_headphone_gain_set(struct hda_codec *codec, long val) { unsigned int i; for (i = 0; i < 4; i++) ca0113_mmio_command_set(codec, 0x48, 0x11 + i, ae5_headphone_gain_presets[val].vals[i]); return 0; } /* * gpio pin 1 is a relay that switches on/off, apparently setting the headphone * amplifier to handle a 600 ohm load. */ static int zxr_headphone_gain_set(struct hda_codec *codec, long val) { ca0113_mmio_gpio_set(codec, 1, val); return 0; } static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); hda_nid_t nid = get_amp_nid(kcontrol); hda_nid_t shared_nid = 0; bool effective; int ret = 0; struct ca0132_spec *spec = codec->spec; int auto_jack; if (nid == VNID_HP_SEL) { auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; if (!auto_jack) { if (ca0132_use_alt_functions(spec)) ca0132_alt_select_out(codec); else ca0132_select_out(codec); } return 1; } if (nid == VNID_AMIC1_SEL) { auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; if (!auto_jack) ca0132_select_mic(codec); return 1; } if (nid == VNID_HP_ASEL) { if (ca0132_use_alt_functions(spec)) ca0132_alt_select_out(codec); else ca0132_select_out(codec); return 1; } if (nid == VNID_AMIC1_ASEL) { ca0132_select_mic(codec); return 1; } /* if effective conditions, then update hw immediately. */ effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); if (effective) { int dir = get_amp_direction(kcontrol); int ch = get_amp_channels(kcontrol); unsigned long pval; mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 0, dir); ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); } return ret; } /* End of control change helpers. */ static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, long idx) { snd_hda_power_up(codec); dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); snd_hda_power_down(codec); } /* * Below I've added controls to mess with the effect levels, I've only enabled * them on the Sound Blaster Z, but they would probably also work on the * Chromebook. I figured they were probably tuned specifically for it, and left * out for a reason. */ /* Sets DSP effect level from the sliders above the controls */ static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, const unsigned int *lookup, int idx) { int i = 0; unsigned int y; /* * For X_BASS, req 2 is actually crossover freq instead of * effect level */ if (nid == X_BASS) y = 2; else y = 1; snd_hda_power_up(codec); if (nid == XBASS_XOVER) { for (i = 0; i < OUT_EFFECTS_COUNT; i++) if (ca0132_effects[i].nid == X_BASS) break; dspio_set_param(codec, ca0132_effects[i].mid, 0x20, ca0132_effects[i].reqs[1], &(lookup[idx - 1]), sizeof(unsigned int)); } else { /* Find the actual effect structure */ for (i = 0; i < OUT_EFFECTS_COUNT; i++) if (nid == ca0132_effects[i].nid) break; dspio_set_param(codec, ca0132_effects[i].mid, 0x20, ca0132_effects[i].reqs[y], &(lookup[idx]), sizeof(unsigned int)); } snd_hda_power_down(codec); return 0; } static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; long *valp = ucontrol->value.integer.value; hda_nid_t nid = get_amp_nid(kcontrol); if (nid == BASS_REDIRECTION_XOVER) *valp = spec->bass_redirect_xover_freq; else *valp = spec->xbass_xover_freq; return 0; } static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx = nid - OUT_EFFECT_START_NID; *valp = spec->fx_ctl_val[idx]; return 0; } /* * The X-bass crossover starts at 10hz, so the min is 1. The * frequency is set in multiples of 10. */ static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 1; uinfo->value.integer.max = 100; uinfo->value.integer.step = 1; return 0; } static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { int chs = get_amp_channels(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = chs == 3 ? 2 : 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = 100; uinfo->value.integer.step = 1; return 0; } static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; long *cur_val; int idx; if (nid == BASS_REDIRECTION_XOVER) cur_val = &spec->bass_redirect_xover_freq; else cur_val = &spec->xbass_xover_freq; /* any change? */ if (*cur_val == *valp) return 0; *cur_val = *valp; idx = *valp; if (nid == BASS_REDIRECTION_XOVER) ca0132_alt_bass_redirection_xover_set(codec, *cur_val); else ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); return 0; } static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); long *valp = ucontrol->value.integer.value; int idx; idx = nid - EFFECT_START_NID; /* any change? */ if (spec->fx_ctl_val[idx] == *valp) return 0; spec->fx_ctl_val[idx] = *valp; idx = *valp; ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); return 0; } /* * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original * only has off or full 30 dB, and didn't like making a volume slider that has * traditional 0-100 in alsamixer that goes in big steps. I like enum better. */ #define MIC_BOOST_NUM_OF_STEPS 4 #define MIC_BOOST_ENUM_MAX_STRLEN 10 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { char *sfx = "dB"; char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); strcpy(uinfo->value.enumerated.name, namestr); return 0; } static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; return 0; } static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = MIC_BOOST_NUM_OF_STEPS; if (sel >= items) return 0; codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", sel); spec->mic_boost_enum_val = sel; if (spec->in_enum_val != REAR_LINE_IN) ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); return 1; } /* * Sound BlasterX AE-5 Headphone Gain Controls. */ #define AE5_HEADPHONE_GAIN_MAX 3 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { char *sfx = " Ohms)"; char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; sprintf(namestr, "%s %s", ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, sfx); strcpy(uinfo->value.enumerated.name, namestr); return 0; } static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; return 0; } static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = AE5_HEADPHONE_GAIN_MAX; if (sel >= items) return 0; codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", sel); spec->ae5_headphone_gain_val = sel; if (spec->out_enum_val == HEADPHONE_OUT) ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); return 1; } /* * Sound BlasterX AE-5 sound filter enumerated control. */ #define AE5_SOUND_FILTER_MAX 3 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; sprintf(namestr, "%s", ae5_filter_presets[uinfo->value.enumerated.item].name); strcpy(uinfo->value.enumerated.name, namestr); return 0; } static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; return 0; } static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = AE5_SOUND_FILTER_MAX; if (sel >= items) return 0; codec_dbg(codec, "ae5_sound_filter: %s\n", ae5_filter_presets[sel].name); spec->ae5_filter_val = sel; ca0113_mmio_command_set_type2(codec, 0x48, 0x07, ae5_filter_presets[sel].val); return 1; } /* * Input Select Control for alternative ca0132 codecs. This exists because * front microphone has no auto-detect, and we need a way to set the rear * as line-in */ static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; strcpy(uinfo->value.enumerated.name, in_src_str[uinfo->value.enumerated.item]); return 0; } static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->in_enum_val; return 0; } static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = IN_SRC_NUM_OF_INPUTS; /* * The AE-7 has no front microphone, so limit items to 2: rear mic and * line-in. */ if (ca0132_quirk(spec) == QUIRK_AE7) items = 2; if (sel >= items) return 0; codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", sel, in_src_str[sel]); spec->in_enum_val = sel; ca0132_alt_select_in(codec); return 1; } /* Sound Blaster Z Output Select Control */ static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = NUM_OF_OUTPUTS; if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; strcpy(uinfo->value.enumerated.name, out_type_str[uinfo->value.enumerated.item]); return 0; } static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->out_enum_val; return 0; } static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = NUM_OF_OUTPUTS; unsigned int auto_jack; if (sel >= items) return 0; codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", sel, out_type_str[sel]); spec->out_enum_val = sel; auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; if (!auto_jack) ca0132_alt_select_out(codec); return 1; } /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = items; if (uinfo->value.enumerated.item >= items) uinfo->value.enumerated.item = items - 1; strcpy(uinfo->value.enumerated.name, speaker_channel_cfgs[uinfo->value.enumerated.item].name); return 0; } static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; return 0; } static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; if (sel >= items) return 0; codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", sel, speaker_channel_cfgs[sel].name); spec->channel_cfg_val = sel; if (spec->out_enum_val == SPEAKER_OUT) ca0132_alt_select_out(codec); return 1; } /* * Smart Volume output setting control. Three different settings, Normal, * which takes the value from the smart volume slider. The two others, loud * and night, disregard the slider value and have uneditable values. */ #define NUM_OF_SVM_SETTINGS 3 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; strcpy(uinfo->value.enumerated.name, out_svm_set_enum_str[uinfo->value.enumerated.item]); return 0; } static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; return 0; } static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = NUM_OF_SVM_SETTINGS; unsigned int idx = SMART_VOLUME - EFFECT_START_NID; unsigned int tmp; if (sel >= items) return 0; codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", sel, out_svm_set_enum_str[sel]); spec->smart_volume_setting = sel; switch (sel) { case 0: tmp = FLOAT_ZERO; break; case 1: tmp = FLOAT_ONE; break; case 2: tmp = FLOAT_TWO; break; default: tmp = FLOAT_ZERO; break; } /* Req 2 is the Smart Volume Setting req. */ dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[2], tmp); return 1; } /* Sound Blaster Z EQ preset controls */ static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = items; if (uinfo->value.enumerated.item >= items) uinfo->value.enumerated.item = items - 1; strcpy(uinfo->value.enumerated.name, ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); return 0; } static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->eq_preset_val; return 0; } static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int i, err = 0; int sel = ucontrol->value.enumerated.item[0]; unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); if (sel >= items) return 0; codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, ca0132_alt_eq_presets[sel].name); /* * Idx 0 is default. * Default needs to qualify with CrystalVoice state. */ for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, ca0132_alt_eq_enum.reqs[i], ca0132_alt_eq_presets[sel].vals[i]); if (err < 0) break; } if (err >= 0) spec->eq_preset_val = sel; return 1; } static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = items; if (uinfo->value.enumerated.item >= items) uinfo->value.enumerated.item = items - 1; strcpy(uinfo->value.enumerated.name, ca0132_voicefx_presets[uinfo->value.enumerated.item].name); return 0; } static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; ucontrol->value.enumerated.item[0] = spec->voicefx_val; return 0; } static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; int i, err = 0; int sel = ucontrol->value.enumerated.item[0]; if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) return 0; codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", sel, ca0132_voicefx_presets[sel].name); /* * Idx 0 is default. * Default needs to qualify with CrystalVoice state. */ for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { err = dspio_set_uint_param(codec, ca0132_voicefx.mid, ca0132_voicefx.reqs[i], ca0132_voicefx_presets[sel].vals[i]); if (err < 0) break; } if (err >= 0) { spec->voicefx_val = sel; /* enable voice fx */ ca0132_voicefx_set(codec, (sel ? 1 : 0)); } return 1; } static int ca0132_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); long *valp = ucontrol->value.integer.value; /* vnode */ if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { if (ch & 1) { *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; valp++; } if (ch & 2) { *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; valp++; } return 0; } /* effects, include PE and CrystalVoice */ if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { *valp = spec->effects_switch[nid - EFFECT_START_NID]; return 0; } /* mic boost */ if (nid == spec->input_pins[0]) { *valp = spec->cur_mic_boost; return 0; } if (nid == ZXR_HEADPHONE_GAIN) { *valp = spec->zxr_gain_set; return 0; } if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; return 0; } if (nid == BASS_REDIRECTION) { *valp = spec->bass_redirection_val; return 0; } return 0; } static int ca0132_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); long *valp = ucontrol->value.integer.value; int changed = 1; codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", nid, *valp); snd_hda_power_up(codec); /* vnode */ if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { if (ch & 1) { spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; valp++; } if (ch & 2) { spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; valp++; } changed = ca0132_vnode_switch_set(kcontrol, ucontrol); goto exit; } /* PE */ if (nid == PLAY_ENHANCEMENT) { spec->effects_switch[nid - EFFECT_START_NID] = *valp; changed = ca0132_pe_switch_set(codec); goto exit; } /* CrystalVoice */ if (nid == CRYSTAL_VOICE) { spec->effects_switch[nid - EFFECT_START_NID] = *valp; changed = ca0132_cvoice_switch_set(codec); goto exit; } /* out and in effects */ if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { spec->effects_switch[nid - EFFECT_START_NID] = *valp; changed = ca0132_effects_set(codec, nid, *valp); goto exit; } /* mic boost */ if (nid == spec->input_pins[0]) { spec->cur_mic_boost = *valp; if (ca0132_use_alt_functions(spec)) { if (spec->in_enum_val != REAR_LINE_IN) changed = ca0132_mic_boost_set(codec, *valp); } else { /* Mic boost does not apply to Digital Mic */ if (spec->cur_mic_type != DIGITAL_MIC) changed = ca0132_mic_boost_set(codec, *valp); } goto exit; } if (nid == ZXR_HEADPHONE_GAIN) { spec->zxr_gain_set = *valp; if (spec->cur_out_type == HEADPHONE_OUT) changed = zxr_headphone_gain_set(codec, *valp); else changed = 0; goto exit; } if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; if (spec->cur_out_type == SPEAKER_OUT) ca0132_alt_set_full_range_speaker(codec); changed = 0; } if (nid == BASS_REDIRECTION) { spec->bass_redirection_val = *valp; if (spec->cur_out_type == SPEAKER_OUT) ca0132_alt_surround_set_bass_redirection(codec, *valp); changed = 0; } exit: snd_hda_power_down(codec); return changed; } /* * Volume related */ /* * Sets the internal DSP decibel level to match the DAC for output, and the * ADC for input. Currently only the SBZ sets dsp capture volume level, and * all alternative codecs set DSP playback volume. */ static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) { struct ca0132_spec *spec = codec->spec; unsigned int dsp_dir; unsigned int lookup_val; if (nid == VNID_SPK) dsp_dir = DSP_VOL_OUT; else dsp_dir = DSP_VOL_IN; lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; dspio_set_uint_param(codec, ca0132_alt_vol_ctls[dsp_dir].mid, ca0132_alt_vol_ctls[dsp_dir].reqs[0], float_vol_db_lookup[lookup_val]); lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; dspio_set_uint_param(codec, ca0132_alt_vol_ctls[dsp_dir].mid, ca0132_alt_vol_ctls[dsp_dir].reqs[1], float_vol_db_lookup[lookup_val]); dspio_set_uint_param(codec, ca0132_alt_vol_ctls[dsp_dir].mid, ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); } static int ca0132_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); unsigned long pval; int err; switch (nid) { case VNID_SPK: /* follow shared_out info */ nid = spec->shared_out_nid; mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); break; case VNID_MIC: /* follow shared_mic info */ nid = spec->shared_mic_nid; mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); break; default: err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); } return err; } static int ca0132_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); long *valp = ucontrol->value.integer.value; /* store the left and right volume */ if (ch & 1) { *valp = spec->vnode_lvol[nid - VNODE_START_NID]; valp++; } if (ch & 2) { *valp = spec->vnode_rvol[nid - VNODE_START_NID]; valp++; } return 0; } static int ca0132_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); long *valp = ucontrol->value.integer.value; hda_nid_t shared_nid = 0; bool effective; int changed = 1; /* store the left and right volume */ if (ch & 1) { spec->vnode_lvol[nid - VNODE_START_NID] = *valp; valp++; } if (ch & 2) { spec->vnode_rvol[nid - VNODE_START_NID] = *valp; valp++; } /* if effective conditions, then update hw immediately. */ effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); if (effective) { int dir = get_amp_direction(kcontrol); unsigned long pval; snd_hda_power_up(codec); mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 0, dir); changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); snd_hda_power_down(codec); } return changed; } /* * This function is the same as the one above, because using an if statement * inside of the above volume control for the DSP volume would cause too much * lag. This is a lot more smooth. */ static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); long *valp = ucontrol->value.integer.value; hda_nid_t vnid = 0; int changed; switch (nid) { case 0x02: vnid = VNID_SPK; break; case 0x07: vnid = VNID_MIC; break; } /* store the left and right volume */ if (ch & 1) { spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; valp++; } if (ch & 2) { spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; valp++; } snd_hda_power_up(codec); ca0132_alt_dsp_volume_put(codec, vnid); mutex_lock(&codec->control_mutex); changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); mutex_unlock(&codec->control_mutex); snd_hda_power_down(codec); return changed; } static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, unsigned int size, unsigned int __user *tlv) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct ca0132_spec *spec = codec->spec; hda_nid_t nid = get_amp_nid(kcontrol); int ch = get_amp_channels(kcontrol); int dir = get_amp_direction(kcontrol); unsigned long pval; int err; switch (nid) { case VNID_SPK: /* follow shared_out tlv */ nid = spec->shared_out_nid; mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); break; case VNID_MIC: /* follow shared_mic tlv */ nid = spec->shared_mic_nid; mutex_lock(&codec->control_mutex); pval = kcontrol->private_value; kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); kcontrol->private_value = pval; mutex_unlock(&codec->control_mutex); break; default: err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); } return err; } /* Add volume slider control for effect level */ static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, const char *pfx, int dir) { char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; int type = dir ? HDA_INPUT : HDA_OUTPUT; struct snd_kcontrol_new knew = HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); knew.tlv.c = NULL; switch (nid) { case XBASS_XOVER: knew.info = ca0132_alt_xbass_xover_slider_info; knew.get = ca0132_alt_xbass_xover_slider_ctl_get; knew.put = ca0132_alt_xbass_xover_slider_put; break; default: knew.info = ca0132_alt_effect_slider_info; knew.get = ca0132_alt_slider_ctl_get; knew.put = ca0132_alt_effect_slider_put; knew.private_value = HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); break; } return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); } /* * Added FX: prefix for the alternative codecs, because otherwise the surround * effect would conflict with the Surround sound volume control. Also seems more * clear as to what the switches do. Left alone for others. */ static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx, int dir) { struct ca0132_spec *spec = codec->spec; char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; int type = dir ? HDA_INPUT : HDA_OUTPUT; struct snd_kcontrol_new knew = CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); /* If using alt_controls, add FX: prefix. But, don't add FX: * prefix to OutFX or InFX enable controls. */ if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); else sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); } static int add_voicefx(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, VOICEFX, 1, 0, HDA_INPUT); knew.info = ca0132_voicefx_info; knew.get = ca0132_voicefx_get; knew.put = ca0132_voicefx_put; return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); } /* Create the EQ Preset control */ static int add_ca0132_alt_eq_presets(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); knew.info = ca0132_alt_eq_preset_info; knew.get = ca0132_alt_eq_preset_get; knew.put = ca0132_alt_eq_preset_put; return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, snd_ctl_new1(&knew, codec)); } /* * Add enumerated control for the three different settings of the smart volume * output effect. Normal just uses the slider value, and loud and night are * their own things that ignore that value. */ static int ca0132_alt_add_svm_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); knew.info = ca0132_alt_svm_setting_info; knew.get = ca0132_alt_svm_setting_get; knew.put = ca0132_alt_svm_setting_put; return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, snd_ctl_new1(&knew, codec)); } /* * Create an Output Select enumerated control for codecs with surround * out capabilities. */ static int ca0132_alt_add_output_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("Output Select", OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); knew.info = ca0132_alt_output_select_get_info; knew.get = ca0132_alt_output_select_get; knew.put = ca0132_alt_output_select_put; return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, snd_ctl_new1(&knew, codec)); } /* * Add a control for selecting channel count on speaker output. Setting this * allows the DSP to do bass redirection and channel upmixing on surround * configurations. */ static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("Surround Channel Config", SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); knew.info = ca0132_alt_speaker_channel_cfg_get_info; knew.get = ca0132_alt_speaker_channel_cfg_get; knew.put = ca0132_alt_speaker_channel_cfg_put; return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, snd_ctl_new1(&knew, codec)); } /* * Full range front stereo and rear surround switches. When these are set to * full range, the lower frequencies from these channels are no longer * redirected to the LFE channel. */ static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) { struct snd_kcontrol_new knew = CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, snd_ctl_new1(&knew, codec)); } static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) { struct snd_kcontrol_new knew = CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, snd_ctl_new1(&knew, codec)); } /* * Bass redirection redirects audio below the crossover frequency to the LFE * channel on speakers that are set as not being full-range. On configurations * without an LFE channel, it does nothing. Bass redirection seems to be the * replacement for X-Bass on configurations with an LFE channel. */ static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) { const char *namestr = "Bass Redirection Crossover"; struct snd_kcontrol_new knew = HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, HDA_OUTPUT); knew.tlv.c = NULL; knew.info = ca0132_alt_xbass_xover_slider_info; knew.get = ca0132_alt_xbass_xover_slider_ctl_get; knew.put = ca0132_alt_xbass_xover_slider_put; return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, snd_ctl_new1(&knew, codec)); } static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) { const char *namestr = "Bass Redirection"; struct snd_kcontrol_new knew = CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, HDA_OUTPUT); return snd_hda_ctl_add(codec, BASS_REDIRECTION, snd_ctl_new1(&knew, codec)); } /* * Create an Input Source enumerated control for the alternate ca0132 codecs * because the front microphone has no auto-detect, and Line-in has to be set * somehow. */ static int ca0132_alt_add_input_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("Input Source", INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); knew.info = ca0132_alt_input_source_info; knew.get = ca0132_alt_input_source_get; knew.put = ca0132_alt_input_source_put; return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, snd_ctl_new1(&knew, codec)); } /* * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds * more control than the original mic boost, which is either full 30dB or off. */ static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", MIC_BOOST_ENUM, 1, 0, HDA_INPUT); knew.info = ca0132_alt_mic_boost_info; knew.get = ca0132_alt_mic_boost_get; knew.put = ca0132_alt_mic_boost_put; return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, snd_ctl_new1(&knew, codec)); } /* * Add headphone gain enumerated control for the AE-5. This switches between * three modes, low, medium, and high. When non-headphone outputs are selected, * it is automatically set to high. This is the same behavior as Windows. */ static int ae5_add_headphone_gain_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); knew.info = ae5_headphone_gain_info; knew.get = ae5_headphone_gain_get; knew.put = ae5_headphone_gain_put; return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, snd_ctl_new1(&knew, codec)); } /* * Add sound filter enumerated control for the AE-5. This adds three different * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've * read into it, it changes the DAC's interpolation filter. */ static int ae5_add_sound_filter_enum(struct hda_codec *codec) { struct snd_kcontrol_new knew = HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); knew.info = ae5_sound_filter_info; knew.get = ae5_sound_filter_get; knew.put = ae5_sound_filter_put; return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, snd_ctl_new1(&knew, codec)); } static int zxr_add_headphone_gain_switch(struct hda_codec *codec) { struct snd_kcontrol_new knew = CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, snd_ctl_new1(&knew, codec)); } /* * Need to create follower controls for the alternate codecs that have surround * capabilities. */ static const char * const ca0132_alt_follower_pfxs[] = { "Front", "Surround", "Center", "LFE", NULL, }; /* * Also need special channel map, because the default one is incorrect. * I think this has to do with the pin for rear surround being 0x11, * and the center/lfe being 0x10. Usually the pin order is the opposite. */ static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { { .channels = 2, .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, { .channels = 4, .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, { .channels = 6, .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, { } }; /* Add the correct chmap for streams with 6 channels. */ static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) { int err = 0; struct hda_pcm *pcm; list_for_each_entry(pcm, &codec->pcm_list_head, list) { struct hda_pcm_stream *hinfo = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; struct snd_pcm_chmap *chmap; const struct snd_pcm_chmap_elem *elem; elem = ca0132_alt_chmaps; if (hinfo->channels_max == 6) { err = snd_pcm_add_chmap_ctls(pcm->pcm, SNDRV_PCM_STREAM_PLAYBACK, elem, hinfo->channels_max, 0, &chmap); if (err < 0) codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); } } } /* * When changing Node IDs for Mixer Controls below, make sure to update * Node IDs in ca0132_config() as well. */ static const struct snd_kcontrol_new ca0132_mixer[] = { CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 0x12, 1, HDA_INPUT), CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", VNID_HP_SEL, 1, HDA_OUTPUT), CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", VNID_AMIC1_SEL, 1, HDA_INPUT), CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", VNID_HP_ASEL, 1, HDA_OUTPUT), CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", VNID_AMIC1_ASEL, 1, HDA_INPUT), { } /* end */ }; /* * Desktop specific control mixer. Removes auto-detect for mic, and adds * surround controls. Also sets both the Front Playback and Capture Volume * controls to alt so they set the DSP's decibel level. */ static const struct snd_kcontrol_new desktop_mixer[] = { CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", VNID_HP_ASEL, 1, HDA_OUTPUT), { } /* end */ }; /* * Same as the Sound Blaster Z, except doesn't use the alt volume for capture * because it doesn't set decibel levels for the DSP for capture. */ static const struct snd_kcontrol_new r3di_mixer[] = { CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", VNID_HP_ASEL, 1, HDA_OUTPUT), { } /* end */ }; static int ca0132_build_controls(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int i, num_fx, num_sliders; int err = 0; /* Add Mixer controls */ for (i = 0; i < spec->num_mixers; i++) { err = snd_hda_add_new_ctls(codec, spec->mixers[i]); if (err < 0) return err; } /* Setup vmaster with surround followers for desktop ca0132 devices */ if (ca0132_use_alt_functions(spec)) { snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, spec->tlv); snd_hda_add_vmaster(codec, "Master Playback Volume", spec->tlv, ca0132_alt_follower_pfxs, "Playback Volume", 0); err = __snd_hda_add_vmaster(codec, "Master Playback Switch", NULL, ca0132_alt_follower_pfxs, "Playback Switch", true, 0, &spec->vmaster_mute.sw_kctl); if (err < 0) return err; } /* Add in and out effects controls. * VoiceFX, PE and CrystalVoice are added separately. */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; for (i = 0; i < num_fx; i++) { /* Desktop cards break if Echo Cancellation is used. */ if (ca0132_use_pci_mmio(spec)) { if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + OUT_EFFECTS_COUNT)) continue; } err = add_fx_switch(codec, ca0132_effects[i].nid, ca0132_effects[i].name, ca0132_effects[i].direct); if (err < 0) return err; } /* * If codec has use_alt_controls set to true, add effect level sliders, * EQ presets, and Smart Volume presets. Also, change names to add FX * prefix, and change PlayEnhancement and CrystalVoice to match. */ if (ca0132_use_alt_controls(spec)) { err = ca0132_alt_add_svm_enum(codec); if (err < 0) return err; err = add_ca0132_alt_eq_presets(codec); if (err < 0) return err; err = add_fx_switch(codec, PLAY_ENHANCEMENT, "Enable OutFX", 0); if (err < 0) return err; err = add_fx_switch(codec, CRYSTAL_VOICE, "Enable InFX", 1); if (err < 0) return err; num_sliders = OUT_EFFECTS_COUNT - 1; for (i = 0; i < num_sliders; i++) { err = ca0132_alt_add_effect_slider(codec, ca0132_effects[i].nid, ca0132_effects[i].name, ca0132_effects[i].direct); if (err < 0) return err; } err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, "X-Bass Crossover", EFX_DIR_OUT); if (err < 0) return err; } else { err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0); if (err < 0) return err; err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1); if (err < 0) return err; } err = add_voicefx(codec); if (err < 0) return err; /* * If the codec uses alt_functions, you need the enumerated controls * to select the new outputs and inputs, plus add the new mic boost * setting control. */ if (ca0132_use_alt_functions(spec)) { err = ca0132_alt_add_output_enum(codec); if (err < 0) return err; err = ca0132_alt_add_speaker_channel_cfg_enum(codec); if (err < 0) return err; err = ca0132_alt_add_front_full_range_switch(codec); if (err < 0) return err; err = ca0132_alt_add_rear_full_range_switch(codec); if (err < 0) return err; err = ca0132_alt_add_bass_redirection_crossover(codec); if (err < 0) return err; err = ca0132_alt_add_bass_redirection_switch(codec); if (err < 0) return err; err = ca0132_alt_add_mic_boost_enum(codec); if (err < 0) return err; /* * ZxR only has microphone input, there is no front panel * header on the card, and aux-in is handled by the DBPro board. */ if (ca0132_quirk(spec) != QUIRK_ZXR) { err = ca0132_alt_add_input_enum(codec); if (err < 0) return err; } } switch (ca0132_quirk(spec)) { case QUIRK_AE5: case QUIRK_AE7: err = ae5_add_headphone_gain_enum(codec); if (err < 0) return err; err = ae5_add_sound_filter_enum(codec); if (err < 0) return err; break; case QUIRK_ZXR: err = zxr_add_headphone_gain_switch(codec); if (err < 0) return err; break; default: break; } #ifdef ENABLE_TUNING_CONTROLS add_tuning_ctls(codec); #endif err = snd_hda_jack_add_kctls(codec, &spec->autocfg); if (err < 0) return err; if (spec->dig_out) { err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, spec->dig_out); if (err < 0) return err; err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); if (err < 0) return err; /* spec->multiout.share_spdif = 1; */ } if (spec->dig_in) { err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); if (err < 0) return err; } if (ca0132_use_alt_functions(spec)) ca0132_alt_add_chmap_ctls(codec); return 0; } static int dbpro_build_controls(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int err = 0; if (spec->dig_out) { err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, spec->dig_out); if (err < 0) return err; } if (spec->dig_in) { err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); if (err < 0) return err; } return 0; } /* * PCM */ static const struct hda_pcm_stream ca0132_pcm_analog_playback = { .substreams = 1, .channels_min = 2, .channels_max = 6, .ops = { .prepare = ca0132_playback_pcm_prepare, .cleanup = ca0132_playback_pcm_cleanup, .get_delay = ca0132_playback_pcm_delay, }, }; static const struct hda_pcm_stream ca0132_pcm_analog_capture = { .substreams = 1, .channels_min = 2, .channels_max = 2, .ops = { .prepare = ca0132_capture_pcm_prepare, .cleanup = ca0132_capture_pcm_cleanup, .get_delay = ca0132_capture_pcm_delay, }, }; static const struct hda_pcm_stream ca0132_pcm_digital_playback = { .substreams = 1, .channels_min = 2, .channels_max = 2, .ops = { .open = ca0132_dig_playback_pcm_open, .close = ca0132_dig_playback_pcm_close, .prepare = ca0132_dig_playback_pcm_prepare, .cleanup = ca0132_dig_playback_pcm_cleanup }, }; static const struct hda_pcm_stream ca0132_pcm_digital_capture = { .substreams = 1, .channels_min = 2, .channels_max = 2, }; static int ca0132_build_pcms(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; struct hda_pcm *info; info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); if (!info) return -ENOMEM; if (ca0132_use_alt_functions(spec)) { info->own_chmap = true; info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap = ca0132_alt_chmaps; } info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = spec->multiout.max_channels; info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; /* With the DSP enabled, desktops don't use this ADC. */ if (!ca0132_use_alt_functions(spec)) { info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); if (!info) return -ENOMEM; info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; } info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); if (!info) return -ENOMEM; info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; if (!spec->dig_out && !spec->dig_in) return 0; info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); if (!info) return -ENOMEM; info->pcm_type = HDA_PCM_TYPE_SPDIF; if (spec->dig_out) { info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_digital_playback; info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; } if (spec->dig_in) { info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_digital_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; } return 0; } static int dbpro_build_pcms(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; struct hda_pcm *info; info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); if (!info) return -ENOMEM; info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; if (!spec->dig_out && !spec->dig_in) return 0; info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); if (!info) return -ENOMEM; info->pcm_type = HDA_PCM_TYPE_SPDIF; if (spec->dig_out) { info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_digital_playback; info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; } if (spec->dig_in) { info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_digital_capture; info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; } return 0; } static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) { if (pin) { snd_hda_set_pin_ctl(codec, pin, PIN_HP); if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); } if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) snd_hda_codec_write(codec, dac, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); } static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) { if (pin) { snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)); } if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)); /* init to 0 dB and unmute. */ snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, HDA_AMP_VOLMASK, 0x5a); snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, HDA_AMP_MUTE, 0); } } static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) { unsigned int caps; caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); snd_hda_override_amp_caps(codec, nid, dir, caps); } /* * Switch between Digital built-in mic and analog mic. */ static void ca0132_set_dmic(struct hda_codec *codec, int enable) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; u8 val; unsigned int oldval; codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); oldval = stop_mic1(codec); ca0132_set_vipsource(codec, 0); if (enable) { /* set DMic input as 2-ch */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x80, 0x00, tmp); val = spec->dmic_ctl; val |= 0x80; snd_hda_codec_write(codec, spec->input_pins[0], 0, VENDOR_CHIPIO_DMIC_CTL_SET, val); if (!(spec->dmic_ctl & 0x20)) chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); } else { /* set AMic input as mono */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); val = spec->dmic_ctl; /* clear bit7 and bit5 to disable dmic */ val &= 0x5f; snd_hda_codec_write(codec, spec->input_pins[0], 0, VENDOR_CHIPIO_DMIC_CTL_SET, val); if (!(spec->dmic_ctl & 0x20)) chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); } ca0132_set_vipsource(codec, 1); resume_mic1(codec, oldval); } /* * Initialization for Digital Mic. */ static void ca0132_init_dmic(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; u8 val; /* Setup Digital Mic here, but don't enable. * Enable based on jack detect. */ /* MCLK uses MPIO1, set to enable. * Bit 2-0: MPIO select * Bit 3: set to disable * Bit 7-4: reserved */ val = 0x01; snd_hda_codec_write(codec, spec->input_pins[0], 0, VENDOR_CHIPIO_DMIC_MCLK_SET, val); /* Data1 uses MPIO3. Data2 not use * Bit 2-0: Data1 MPIO select * Bit 3: set disable Data1 * Bit 6-4: Data2 MPIO select * Bit 7: set disable Data2 */ val = 0x83; snd_hda_codec_write(codec, spec->input_pins[0], 0, VENDOR_CHIPIO_DMIC_PIN_SET, val); /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. * Bit 3-0: Channel mask * Bit 4: set for 48KHz, clear for 32KHz * Bit 5: mode * Bit 6: set to select Data2, clear for Data1 * Bit 7: set to enable DMic, clear for AMic */ if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) val = 0x33; else val = 0x23; /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ spec->dmic_ctl = val; snd_hda_codec_write(codec, spec->input_pins[0], 0, VENDOR_CHIPIO_DMIC_CTL_SET, val); } /* * Initialization for Analog Mic 2 */ static void ca0132_init_analog_mic2(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); mutex_unlock(&spec->chipio_mutex); } static void ca0132_refresh_widget_caps(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int i; codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); snd_hda_codec_update_widgets(codec); for (i = 0; i < spec->multiout.num_dacs; i++) refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); for (i = 0; i < spec->num_outputs; i++) refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); for (i = 0; i < spec->num_inputs; i++) { refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); } } /* If there is an active channel for some reason, find it and free it. */ static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) { unsigned int i, tmp; int status; /* Read active DSPDMAC channel register. */ status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); if (status >= 0) { /* AND against 0xfff to get the active channel bits. */ tmp = tmp & 0xfff; /* If there are no active channels, nothing to free. */ if (!tmp) return; } else { codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", __func__); return; } /* * Check each DSP DMA channel for activity, and if the channel is * active, free it. */ for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { if (dsp_is_dma_active(codec, i)) { status = dspio_free_dma_chan(codec, i); if (status < 0) codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", __func__, i); } } } /* * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. * Instead, audio is now routed through the DSP's DMA controllers, which * the DSP is tasked with setting up itself. Through debugging, it seems the * cause of most of the no-audio on startup issues were due to improperly * configured DSP DMA channels. * * Normally, the DSP configures these the first time an HDA audio stream is * started post DSP firmware download. That is why creating a 'dummy' stream * worked in fixing the audio in some cases. This works most of the time, but * sometimes if a stream is started/stopped before the DSP can setup the DMA * configuration registers, it ends up in a broken state. Issues can also * arise if streams are started in an unusual order, i.e the audio output dma * channel being sandwiched between the mic1 and mic2 dma channels. * * The solution to this is to make sure that the DSP has no DMA channels * in use post DSP firmware download, and then to manually start each default * DSP stream that uses the DMA channels. These are 0x0c, the audio output * stream, 0x03, analog mic 1, and 0x04, analog mic 2. */ static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) { static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; struct ca0132_spec *spec = codec->spec; unsigned int i, tmp; /* * Check if any of the default streams are active, and if they are, * stop them. */ mutex_lock(&spec->chipio_mutex); for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); if (tmp) { chipio_set_stream_control(codec, dsp_dma_stream_ids[i], 0); } } mutex_unlock(&spec->chipio_mutex); /* * If all DSP streams are inactive, there should be no active DSP DMA * channels. Check and make sure this is the case, and if it isn't, * free any active channels. */ ca0132_alt_free_active_dma_channels(codec); mutex_lock(&spec->chipio_mutex); /* Make sure stream 0x0c is six channels. */ chipio_set_stream_channels(codec, 0x0c, 6); for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { chipio_set_stream_control(codec, dsp_dma_stream_ids[i], 1); /* Give the DSP some time to setup the DMA channel. */ msleep(75); } mutex_unlock(&spec->chipio_mutex); } /* * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio * router', where each entry represents a 48khz audio channel, with a format * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, * and 3 if it's using Sample Rate Converter ports. * An example is: * 0x0001f8c0 * In this case, f8 is the destination, and c0 is the source. The number value * is 1. * This region of memory is normally managed internally by the 8051, where * the region of exram memory from 0x1477-0x1575 has each byte represent an * entry within the 0x190000 range, and when a range of entries is in use, the * ending value is overwritten with 0xff. * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO * streamID's, where each entry is a starting 0x190000 port offset. * 0x159d in exram is the same as 0x1578, except it contains the ending port * offset for the corresponding streamID. * * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by * the 8051, then manually overwritten to remap the ports to work with the * new DACs. * * Currently known portID's: * 0x00-0x1f: HDA audio stream input/output ports. * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to * have the lower-nibble set to 0x1, 0x2, and 0x9. * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. * 0xe0-0xff: DAC/ADC audio input/output ports. * * Currently known streamID's: * 0x03: Mic1 ADC to DSP. * 0x04: Mic2 ADC to DSP. * 0x05: HDA node 0x02 audio stream to DSP. * 0x0f: DSP Mic exit to HDA node 0x07. * 0x0c: DSP processed audio to DACs. * 0x14: DAC0, front L/R. * * It is possible to route the HDA audio streams directly to the DAC and * bypass the DSP entirely, with the only downside being that since the DSP * does volume control, the only volume control you'll get is through PCM on * the PC side, in the same way volume is handled for optical out. This may be * useful for debugging. */ static void chipio_remap_stream(struct hda_codec *codec, const struct chipio_stream_remap_data *remap_data) { unsigned int i, stream_offset; /* Get the starting port for the stream to be remapped. */ chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, &stream_offset); /* * Check if the stream's port value is 0xff, because the 8051 may not * have gotten around to setting up the stream yet. Wait until it's * setup to remap it's ports. */ if (stream_offset == 0xff) { for (i = 0; i < 5; i++) { msleep(25); chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, &stream_offset); if (stream_offset != 0xff) break; } } if (stream_offset == 0xff) { codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", __func__, remap_data->stream_id); return; } /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ stream_offset *= 0x04; stream_offset += 0x190000; for (i = 0; i < remap_data->count; i++) { chipio_write_no_mutex(codec, stream_offset + remap_data->offset[i], remap_data->value[i]); } /* Update stream map configuration. */ chipio_write_no_mutex(codec, 0x19042c, 0x00000001); } /* * Default speaker tuning values setup for alternative codecs. */ static const unsigned int sbz_default_delay_values[] = { /* Non-zero values are floating point 0.000198. */ 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; static const unsigned int zxr_default_delay_values[] = { /* Non-zero values are floating point 0.000220. */ 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd }; static const unsigned int ae5_default_delay_values[] = { /* Non-zero values are floating point 0.000100. */ 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 }; /* * If we never change these, probably only need them on initialization. */ static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int i, tmp, start_req, end_req; const unsigned int *values; switch (ca0132_quirk(spec)) { case QUIRK_SBZ: values = sbz_default_delay_values; break; case QUIRK_ZXR: values = zxr_default_delay_values; break; case QUIRK_AE5: case QUIRK_AE7: values = ae5_default_delay_values; break; default: values = sbz_default_delay_values; break; } tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; for (i = start_req; i < end_req + 1; i++) dspio_set_uint_param(codec, 0x96, i, tmp); start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; for (i = start_req; i < end_req + 1; i++) dspio_set_uint_param(codec, 0x96, i, tmp); for (i = 0; i < 6; i++) dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); } /* * Initialize mic for non-chromebook ca0132 implementations. */ static void ca0132_alt_init_analog_mics(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; /* Mic 1 Setup */ chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) { chipio_set_conn_rate(codec, 0x0F, SR_96_000); tmp = FLOAT_ONE; } else tmp = FLOAT_THREE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); /* Mic 2 setup (not present on desktop cards) */ chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); if (ca0132_quirk(spec) == QUIRK_R3DI) chipio_set_conn_rate(codec, 0x0F, SR_96_000); tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x80, 0x01, tmp); } /* * Sets the source of stream 0x14 to connpointID 0x48, and the destination * connpointID to 0x91. If this isn't done, the destination is 0x71, and * you get no sound. I'm guessing this has to do with the Sound Blaster Z * having an updated DAC, which changes the destination to that DAC. */ static void sbz_connect_streams(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ chipio_write_no_mutex(codec, 0x18a020, 0x00000043); /* Setup stream 0x14 with it's source and destination points */ chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); chipio_set_stream_channels(codec, 0x14, 2); chipio_set_stream_control(codec, 0x14, 1); codec_dbg(codec, "Connect Streams exited, mutex released.\n"); mutex_unlock(&spec->chipio_mutex); } /* * Write data through ChipIO to setup proper stream destinations. * Not sure how it exactly works, but it seems to direct data * to different destinations. Example is f8 to c0, e0 to c0. * All I know is, if you don't set these, you get no sound. */ static void sbz_chipio_startup_data(struct hda_codec *codec) { const struct chipio_stream_remap_data *dsp_out_remap_data; struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); /* Remap DAC0's output ports. */ chipio_remap_stream(codec, &stream_remap_data[0]); /* Remap DSP audio output stream ports. */ switch (ca0132_quirk(spec)) { case QUIRK_SBZ: dsp_out_remap_data = &stream_remap_data[1]; break; case QUIRK_ZXR: dsp_out_remap_data = &stream_remap_data[2]; break; default: dsp_out_remap_data = NULL; break; } if (dsp_out_remap_data) chipio_remap_stream(codec, dsp_out_remap_data); codec_dbg(codec, "Startup Data exited, mutex released.\n"); mutex_unlock(&spec->chipio_mutex); } static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); tmp = FLOAT_THREE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: chipio_write(codec, 0x18b098, 0x0000000c); chipio_write(codec, 0x18b09C, 0x0000000c); break; case QUIRK_AE5: chipio_write(codec, 0x18b098, 0x0000000c); chipio_write(codec, 0x18b09c, 0x0000004c); break; default: break; } } static void ae5_post_dsp_register_set(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; chipio_8051_write_direct(codec, 0x93, 0x10); chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); writeb(0xff, spec->mem_base + 0x304); writeb(0xff, spec->mem_base + 0x304); writeb(0xff, spec->mem_base + 0x304); writeb(0xff, spec->mem_base + 0x304); writeb(0x00, spec->mem_base + 0x100); writeb(0xff, spec->mem_base + 0x304); writeb(0x00, spec->mem_base + 0x100); writeb(0xff, spec->mem_base + 0x304); writeb(0x00, spec->mem_base + 0x100); writeb(0xff, spec->mem_base + 0x304); writeb(0x00, spec->mem_base + 0x100); writeb(0xff, spec->mem_base + 0x304); ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); } static void ae5_post_dsp_param_setup(struct hda_codec *codec) { /* * Param3 in the 8051's memory is represented by the ascii string 'mch' * which seems to be 'multichannel'. This is also mentioned in the * AE-5's registry values in Windows. */ chipio_set_control_param(codec, 3, 0); /* * I believe ASI is 'audio serial interface' and that it's used to * change colors on the external LED strip connected to the AE-5. */ chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); chipio_8051_write_exram(codec, 0xfa92, 0x22); } static void ae5_post_dsp_pll_setup(struct hda_codec *codec) { chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); } static void ae5_post_dsp_stream_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); chipio_set_stream_channels(codec, 0x18, 6); chipio_set_stream_control(codec, 0x18, 1); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); mutex_unlock(&spec->chipio_mutex); } static void ae5_post_dsp_startup_data(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); chipio_write_no_mutex(codec, 0x189000, 0x0001f101); chipio_write_no_mutex(codec, 0x189004, 0x0001f101); chipio_write_no_mutex(codec, 0x189024, 0x00014004); chipio_write_no_mutex(codec, 0x189028, 0x0002000f); ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); ca0113_mmio_gpio_set(codec, 0, true); ca0113_mmio_gpio_set(codec, 1, true); ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); mutex_unlock(&spec->chipio_mutex); } static void ae7_post_dsp_setup_ports(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); /* Seems to share the same port remapping as the SBZ. */ chipio_remap_stream(codec, &stream_remap_data[1]); ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); mutex_unlock(&spec->chipio_mutex); } static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; mutex_lock(&spec->chipio_mutex); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); chipio_set_stream_channels(codec, 0x18, 6); chipio_set_stream_control(codec, 0x18, 1); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); mutex_unlock(&spec->chipio_mutex); } static void ae7_post_dsp_pll_setup(struct hda_codec *codec) { static const unsigned int addr[] = { 0x41, 0x45, 0x40, 0x43, 0x51 }; static const unsigned int data[] = { 0xc8, 0xcc, 0xcb, 0xc7, 0x8d }; unsigned int i; for (i = 0; i < ARRAY_SIZE(addr); i++) chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); } static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; static const unsigned int target[] = { 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 }; static const unsigned int data[] = { 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f }; unsigned int i; mutex_lock(&spec->chipio_mutex); chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); chipio_write_no_mutex(codec, 0x189000, 0x0001f101); chipio_write_no_mutex(codec, 0x189004, 0x0001f101); chipio_write_no_mutex(codec, 0x189024, 0x00014004); chipio_write_no_mutex(codec, 0x189028, 0x0002000f); ae7_post_dsp_pll_setup(codec); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); for (i = 0; i < ARRAY_SIZE(target); i++) ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); chipio_set_stream_channels(codec, 0x21, 2); chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); /* * In the 8051's memory, this param is referred to as 'n2sid', which I * believe is 'node to streamID'. It seems to be a way to assign a * stream to a given HDA node. */ chipio_set_control_param_no_mutex(codec, 0x20, 0x21); chipio_write_no_mutex(codec, 0x18b038, 0x00000088); /* * Now, at this point on Windows, an actual stream is setup and * seemingly sends data to the HDA node 0x09, which is the digital * audio input node. This is left out here, because obviously I don't * know what data is being sent. Interestingly, the AE-5 seems to go * through the motions of getting here and never actually takes this * step, but the AE-7 does. */ ca0113_mmio_gpio_set(codec, 0, 1); ca0113_mmio_gpio_set(codec, 1, 1); ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); chipio_set_stream_channels(codec, 0x18, 6); /* * Runs again, this has been repeated a few times, but I'm just * following what the Windows driver does. */ ae7_post_dsp_pll_setup(codec); chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); mutex_unlock(&spec->chipio_mutex); } /* * The Windows driver has commands that seem to setup ASI, which I believe to * be some sort of audio serial interface. My current speculation is that it's * related to communicating with the new DAC. */ static void ae7_post_dsp_asi_setup(struct hda_codec *codec) { chipio_8051_write_direct(codec, 0x93, 0x10); chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); chipio_set_control_param(codec, 3, 3); chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); chipio_8051_write_exram(codec, 0xfa92, 0x22); ae7_post_dsp_pll_setup(codec); ae7_post_dsp_asi_stream_setup(codec); chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); ae7_post_dsp_asi_setup_ports(codec); } /* * Setup default parameters for DSP */ static void ca0132_setup_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int num_fx; int idx, i; if (spec->dsp_state != DSP_DOWNLOADED) return; /* out, in effects + voicefx */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; for (idx = 0; idx < num_fx; idx++) { for (i = 0; i <= ca0132_effects[idx].params; i++) { dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[i], ca0132_effects[idx].def_vals[i]); } } /*remove DSP headroom*/ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x3C, tmp); /*set speaker EQ bypass attenuation*/ dspio_set_uint_param(codec, 0x8f, 0x01, tmp); /* set AMic1 and AMic2 as mono mic */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x00, tmp); dspio_set_uint_param(codec, 0x80, 0x01, tmp); /* set AMic1 as CrystalVoice input */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x80, 0x05, tmp); /* set WUH source */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x31, 0x00, tmp); } /* * Setup default parameters for Recon3D/Recon3Di DSP. */ static void r3d_setup_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int num_fx; int idx, i; if (spec->dsp_state != DSP_DOWNLOADED) return; ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); /*remove DSP headroom*/ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x3C, tmp); /* set WUH source */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x31, 0x00, tmp); chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); /* Set speaker source? */ dspio_set_uint_param(codec, 0x32, 0x00, tmp); if (ca0132_quirk(spec) == QUIRK_R3DI) r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); /* Disable mute on Center/LFE. */ if (ca0132_quirk(spec) == QUIRK_R3D) { ca0113_mmio_gpio_set(codec, 2, false); ca0113_mmio_gpio_set(codec, 4, true); } /* Setup effect defaults */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; for (idx = 0; idx < num_fx; idx++) { for (i = 0; i <= ca0132_effects[idx].params; i++) { dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[i], ca0132_effects[idx].def_vals[i]); } } } /* * Setup default parameters for the Sound Blaster Z DSP. A lot more going on * than the Chromebook setup. */ static void sbz_setup_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int num_fx; int idx, i; if (spec->dsp_state != DSP_DOWNLOADED) return; ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); sbz_connect_streams(codec); sbz_chipio_startup_data(codec); /* * Sets internal input loopback to off, used to have a switch to * enable input loopback, but turned out to be way too buggy. */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x37, 0x08, tmp); dspio_set_uint_param(codec, 0x37, 0x10, tmp); /*remove DSP headroom*/ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x3C, tmp); /* set WUH source */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x31, 0x00, tmp); chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); /* Set speaker source? */ dspio_set_uint_param(codec, 0x32, 0x00, tmp); ca0132_alt_dsp_initial_mic_setup(codec); /* out, in effects + voicefx */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; for (idx = 0; idx < num_fx; idx++) { for (i = 0; i <= ca0132_effects[idx].params; i++) { dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[i], ca0132_effects[idx].def_vals[i]); } } ca0132_alt_init_speaker_tuning(codec); } /* * Setup default parameters for the Sound BlasterX AE-5 DSP. */ static void ae5_setup_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int num_fx; int idx, i; if (spec->dsp_state != DSP_DOWNLOADED) return; ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); /* New, unknown SCP req's */ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x29, tmp); dspio_set_uint_param(codec, 0x96, 0x2a, tmp); dspio_set_uint_param(codec, 0x80, 0x0d, tmp); dspio_set_uint_param(codec, 0x80, 0x0e, tmp); ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); ca0113_mmio_gpio_set(codec, 0, false); ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); /* Internal loopback off */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x37, 0x08, tmp); dspio_set_uint_param(codec, 0x37, 0x10, tmp); /*remove DSP headroom*/ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x3C, tmp); /* set WUH source */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x31, 0x00, tmp); chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); /* Set speaker source? */ dspio_set_uint_param(codec, 0x32, 0x00, tmp); ca0132_alt_dsp_initial_mic_setup(codec); ae5_post_dsp_register_set(codec); ae5_post_dsp_param_setup(codec); ae5_post_dsp_pll_setup(codec); ae5_post_dsp_stream_setup(codec); ae5_post_dsp_startup_data(codec); /* out, in effects + voicefx */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; for (idx = 0; idx < num_fx; idx++) { for (i = 0; i <= ca0132_effects[idx].params; i++) { dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[i], ca0132_effects[idx].def_vals[i]); } } ca0132_alt_init_speaker_tuning(codec); } /* * Setup default parameters for the Sound Blaster AE-7 DSP. */ static void ae7_setup_defaults(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp; int num_fx; int idx, i; if (spec->dsp_state != DSP_DOWNLOADED) return; ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); ae7_post_dsp_setup_ports(codec); tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); /* New, unknown SCP req's */ dspio_set_uint_param(codec, 0x80, 0x0d, tmp); dspio_set_uint_param(codec, 0x80, 0x0e, tmp); ca0113_mmio_gpio_set(codec, 0, false); /* Internal loopback off */ tmp = FLOAT_ONE; dspio_set_uint_param(codec, 0x37, 0x08, tmp); dspio_set_uint_param(codec, 0x37, 0x10, tmp); /*remove DSP headroom*/ tmp = FLOAT_ZERO; dspio_set_uint_param(codec, 0x96, 0x3C, tmp); /* set WUH source */ tmp = FLOAT_TWO; dspio_set_uint_param(codec, 0x31, 0x00, tmp); chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); /* Set speaker source? */ dspio_set_uint_param(codec, 0x32, 0x00, tmp); ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); /* * This is the second time we've called this, but this is seemingly * what Windows does. */ ca0132_alt_init_analog_mics(codec); ae7_post_dsp_asi_setup(codec); /* * Not sure why, but these are both set to 1. They're only set to 0 * upon shutdown. */ ca0113_mmio_gpio_set(codec, 0, true); ca0113_mmio_gpio_set(codec, 1, true); /* Volume control related. */ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); /* out, in effects + voicefx */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; for (idx = 0; idx < num_fx; idx++) { for (i = 0; i <= ca0132_effects[idx].params; i++) { dspio_set_uint_param(codec, ca0132_effects[idx].mid, ca0132_effects[idx].reqs[i], ca0132_effects[idx].def_vals[i]); } } ca0132_alt_init_speaker_tuning(codec); } /* * Initialization of flags in chip */ static void ca0132_init_flags(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; if (ca0132_use_alt_functions(spec)) { chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); } else { chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); } } /* * Initialization of parameters in chip */ static void ca0132_init_params(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; if (ca0132_use_alt_functions(spec)) { chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); chipio_set_conn_rate(codec, 0x0B, SR_48_000); chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); chipio_set_control_param(codec, 0, 0); chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); } chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); } static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) { chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); } static bool ca0132_download_dsp_images(struct hda_codec *codec) { bool dsp_loaded = false; struct ca0132_spec *spec = codec->spec; const struct dsp_image_seg *dsp_os_image; const struct firmware *fw_entry = NULL; /* * Alternate firmwares for different variants. The Recon3Di apparently * can use the default firmware, but I'll leave the option in case * it needs it again. */ switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_R3D: case QUIRK_AE5: if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, codec->card->dev) != 0) codec_dbg(codec, "Desktop firmware not found."); else codec_dbg(codec, "Desktop firmware selected."); break; case QUIRK_R3DI: if (request_firmware(&fw_entry, R3DI_EFX_FILE, codec->card->dev) != 0) codec_dbg(codec, "Recon3Di alt firmware not detected."); else codec_dbg(codec, "Recon3Di firmware selected."); break; default: break; } /* * Use default ctefx.bin if no alt firmware is detected, or if none * exists for your particular codec. */ if (!fw_entry) { codec_dbg(codec, "Default firmware selected."); if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0) return false; } dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { codec_err(codec, "ca0132 DSP load image failed\n"); goto exit_download; } dsp_loaded = dspload_wait_loaded(codec); exit_download: release_firmware(fw_entry); return dsp_loaded; } static void ca0132_download_dsp(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP return; /* NOP */ #endif if (spec->dsp_state == DSP_DOWNLOAD_FAILED) return; /* don't retry failures */ chipio_enable_clocks(codec); if (spec->dsp_state != DSP_DOWNLOADED) { spec->dsp_state = DSP_DOWNLOADING; if (!ca0132_download_dsp_images(codec)) spec->dsp_state = DSP_DOWNLOAD_FAILED; else spec->dsp_state = DSP_DOWNLOADED; } /* For codecs using alt functions, this is already done earlier */ if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) ca0132_set_dsp_msr(codec, true); } static void ca0132_process_dsp_response(struct hda_codec *codec, struct hda_jack_callback *callback) { struct ca0132_spec *spec = codec->spec; codec_dbg(codec, "ca0132_process_dsp_response\n"); snd_hda_power_up_pm(codec); if (spec->wait_scp) { if (dspio_get_response_data(codec) >= 0) spec->wait_scp = 0; } dspio_clear_response_queue(codec); snd_hda_power_down_pm(codec); } static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) { struct ca0132_spec *spec = codec->spec; struct hda_jack_tbl *tbl; /* Delay enabling the HP amp, to let the mic-detection * state machine run. */ tbl = snd_hda_jack_tbl_get(codec, cb->nid); if (tbl) tbl->block_report = 1; schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); } static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) { struct ca0132_spec *spec = codec->spec; if (ca0132_use_alt_functions(spec)) ca0132_alt_select_in(codec); else ca0132_select_mic(codec); } static void ca0132_setup_unsol(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, amic_callback); snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, ca0132_process_dsp_response); /* Front headphone jack detection */ if (ca0132_use_alt_functions(spec)) snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_front_hp, hp_callback); } /* * Verbs tables. */ /* Sends before DSP download. */ static const struct hda_verb ca0132_base_init_verbs[] = { /*enable ct extension*/ {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, {} }; /* Send at exit. */ static const struct hda_verb ca0132_base_exit_verbs[] = { /*set afg to D3*/ {0x01, AC_VERB_SET_POWER_STATE, 0x03}, /*disable ct extension*/ {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, {} }; /* Other verbs tables. Sends after DSP download. */ static const struct hda_verb ca0132_init_verbs0[] = { /* chip init verbs */ {0x15, 0x70D, 0xF0}, {0x15, 0x70E, 0xFE}, {0x15, 0x707, 0x75}, {0x15, 0x707, 0xD3}, {0x15, 0x707, 0x09}, {0x15, 0x707, 0x53}, {0x15, 0x707, 0xD4}, {0x15, 0x707, 0xEF}, {0x15, 0x707, 0x75}, {0x15, 0x707, 0xD3}, {0x15, 0x707, 0x09}, {0x15, 0x707, 0x02}, {0x15, 0x707, 0x37}, {0x15, 0x707, 0x78}, {0x15, 0x53C, 0xCE}, {0x15, 0x575, 0xC9}, {0x15, 0x53D, 0xCE}, {0x15, 0x5B7, 0xC9}, {0x15, 0x70D, 0xE8}, {0x15, 0x70E, 0xFE}, {0x15, 0x707, 0x02}, {0x15, 0x707, 0x68}, {0x15, 0x707, 0x62}, {0x15, 0x53A, 0xCE}, {0x15, 0x546, 0xC9}, {0x15, 0x53B, 0xCE}, {0x15, 0x5E8, 0xC9}, {} }; /* Extra init verbs for desktop cards. */ static const struct hda_verb ca0132_init_verbs1[] = { {0x15, 0x70D, 0x20}, {0x15, 0x70E, 0x19}, {0x15, 0x707, 0x00}, {0x15, 0x539, 0xCE}, {0x15, 0x546, 0xC9}, {0x15, 0x70D, 0xB7}, {0x15, 0x70E, 0x09}, {0x15, 0x707, 0x10}, {0x15, 0x70D, 0xAF}, {0x15, 0x70E, 0x09}, {0x15, 0x707, 0x01}, {0x15, 0x707, 0x05}, {0x15, 0x70D, 0x73}, {0x15, 0x70E, 0x09}, {0x15, 0x707, 0x14}, {0x15, 0x6FF, 0xC4}, {} }; static void ca0132_init_chip(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; int num_fx; int i; unsigned int on; mutex_init(&spec->chipio_mutex); /* * The Windows driver always does this upon startup, which seems to * clear out any previous configuration. This should help issues where * a boot into Windows prior to a boot into Linux breaks things. Also, * Windows always sends the reset twice. */ if (ca0132_use_alt_functions(spec)) { chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_CODEC_RESET, 0); snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_CODEC_RESET, 0); } spec->cur_out_type = SPEAKER_OUT; if (!ca0132_use_alt_functions(spec)) spec->cur_mic_type = DIGITAL_MIC; else spec->cur_mic_type = REAR_MIC; spec->cur_mic_boost = 0; for (i = 0; i < VNODES_COUNT; i++) { spec->vnode_lvol[i] = 0x5a; spec->vnode_rvol[i] = 0x5a; spec->vnode_lswitch[i] = 0; spec->vnode_rswitch[i] = 0; } /* * Default states for effects are in ca0132_effects[]. */ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; for (i = 0; i < num_fx; i++) { on = (unsigned int)ca0132_effects[i].reqs[0]; spec->effects_switch[i] = on ? 1 : 0; } /* * Sets defaults for the effect slider controls, only for alternative * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. */ if (ca0132_use_alt_controls(spec)) { /* Set speakers to default to full range. */ spec->speaker_range_val[0] = 1; spec->speaker_range_val[1] = 1; spec->xbass_xover_freq = 8; for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) spec->fx_ctl_val[i] = effect_slider_defaults[i]; spec->bass_redirect_xover_freq = 8; } spec->voicefx_val = 0; spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; /* * The ZxR doesn't have a front panel header, and it's line-in is on * the daughter board. So, there is no input enum control, and we need * to make sure that spec->in_enum_val is set properly. */ if (ca0132_quirk(spec) == QUIRK_ZXR) spec->in_enum_val = REAR_MIC; #ifdef ENABLE_TUNING_CONTROLS ca0132_init_tuning_defaults(codec); #endif } /* * Recon3Di exit specific commands. */ /* prevents popping noise on shutdown */ static void r3di_gpio_shutdown(struct hda_codec *codec) { snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); } /* * Sound Blaster Z exit specific commands. */ static void sbz_region2_exit(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int i; for (i = 0; i < 4; i++) writeb(0x0, spec->mem_base + 0x100); for (i = 0; i < 8; i++) writeb(0xb3, spec->mem_base + 0x304); ca0113_mmio_gpio_set(codec, 0, false); ca0113_mmio_gpio_set(codec, 1, false); ca0113_mmio_gpio_set(codec, 4, true); ca0113_mmio_gpio_set(codec, 5, false); ca0113_mmio_gpio_set(codec, 7, false); } static void sbz_set_pin_ctl_default(struct hda_codec *codec) { static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; unsigned int i; snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); for (i = 0; i < ARRAY_SIZE(pins); i++) snd_hda_codec_write(codec, pins[i], 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); } static void ca0132_clear_unsolicited(struct hda_codec *codec) { static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; unsigned int i; for (i = 0; i < ARRAY_SIZE(pins); i++) { snd_hda_codec_write(codec, pins[i], 0, AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); } } /* On shutdown, sends commands in sets of three */ static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, int mask, int data) { if (dir >= 0) snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, dir); if (mask >= 0) snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, mask); if (data >= 0) snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, data); } static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) { static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; unsigned int i; for (i = 0; i < ARRAY_SIZE(pins); i++) snd_hda_codec_write(codec, pins[i], 0, AC_VERB_SET_POWER_STATE, 0x03); } static void sbz_exit_chip(struct hda_codec *codec) { chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); /* Mess with GPIO */ sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); chipio_set_stream_control(codec, 0x14, 0); chipio_set_stream_control(codec, 0x0C, 0); chipio_set_conn_rate(codec, 0x41, SR_192_000); chipio_set_conn_rate(codec, 0x91, SR_192_000); chipio_write(codec, 0x18a020, 0x00000083); sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); chipio_set_stream_control(codec, 0x0C, 0); chipio_set_control_param(codec, 0x0D, 0x24); ca0132_clear_unsolicited(codec); sbz_set_pin_ctl_default(codec); snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); sbz_region2_exit(codec); } static void r3d_exit_chip(struct hda_codec *codec) { ca0132_clear_unsolicited(codec); snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); } static void ae5_exit_chip(struct hda_codec *codec) { chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); ca0113_mmio_gpio_set(codec, 0, false); ca0113_mmio_gpio_set(codec, 1, false); snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); chipio_set_stream_control(codec, 0x18, 0); chipio_set_stream_control(codec, 0x0c, 0); snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); } static void ae7_exit_chip(struct hda_codec *codec) { chipio_set_stream_control(codec, 0x18, 0); chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); chipio_set_stream_channels(codec, 0x21, 0); chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); chipio_set_control_param(codec, 0x20, 0x01); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); chipio_set_stream_control(codec, 0x18, 0); chipio_set_stream_control(codec, 0x0c, 0); ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); ca0113_mmio_gpio_set(codec, 0, false); ca0113_mmio_gpio_set(codec, 1, false); ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); } static void zxr_exit_chip(struct hda_codec *codec) { chipio_set_stream_control(codec, 0x03, 0); chipio_set_stream_control(codec, 0x04, 0); chipio_set_stream_control(codec, 0x14, 0); chipio_set_stream_control(codec, 0x0C, 0); chipio_set_conn_rate(codec, 0x41, SR_192_000); chipio_set_conn_rate(codec, 0x91, SR_192_000); chipio_write(codec, 0x18a020, 0x00000083); snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); ca0132_clear_unsolicited(codec); sbz_set_pin_ctl_default(codec); snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); ca0113_mmio_gpio_set(codec, 5, false); ca0113_mmio_gpio_set(codec, 2, false); ca0113_mmio_gpio_set(codec, 3, false); ca0113_mmio_gpio_set(codec, 0, false); ca0113_mmio_gpio_set(codec, 4, true); ca0113_mmio_gpio_set(codec, 0, true); ca0113_mmio_gpio_set(codec, 5, true); ca0113_mmio_gpio_set(codec, 2, false); ca0113_mmio_gpio_set(codec, 3, false); } static void ca0132_exit_chip(struct hda_codec *codec) { /* put any chip cleanup stuffs here. */ if (dspload_is_loaded(codec)) dsp_reset(codec); } /* * This fixes a problem that was hard to reproduce. Very rarely, I would * boot up, and there would be no sound, but the DSP indicated it had loaded * properly. I did a few memory dumps to see if anything was different, and * there were a few areas of memory uninitialized with a1a2a3a4. This function * checks if those areas are uninitialized, and if they are, it'll attempt to * reload the card 3 times. Usually it fixes by the second. */ static void sbz_dsp_startup_check(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int dsp_data_check[4]; unsigned int cur_address = 0x390; unsigned int i; unsigned int failure = 0; unsigned int reload = 3; if (spec->startup_check_entered) return; spec->startup_check_entered = true; for (i = 0; i < 4; i++) { chipio_read(codec, cur_address, &dsp_data_check[i]); cur_address += 0x4; } for (i = 0; i < 4; i++) { if (dsp_data_check[i] == 0xa1a2a3a4) failure = 1; } codec_dbg(codec, "Startup Check: %d ", failure); if (failure) codec_info(codec, "DSP not initialized properly. Attempting to fix."); /* * While the failure condition is true, and we haven't reached our * three reload limit, continue trying to reload the driver and * fix the issue. */ while (failure && (reload != 0)) { codec_info(codec, "Reloading... Tries left: %d", reload); sbz_exit_chip(codec); spec->dsp_state = DSP_DOWNLOAD_INIT; codec->patch_ops.init(codec); failure = 0; for (i = 0; i < 4; i++) { chipio_read(codec, cur_address, &dsp_data_check[i]); cur_address += 0x4; } for (i = 0; i < 4; i++) { if (dsp_data_check[i] == 0xa1a2a3a4) failure = 1; } reload--; } if (!failure && reload < 3) codec_info(codec, "DSP fixed."); if (!failure) return; codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); } /* * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add * extra precision for decibel values. If you had the dB value in floating point * you would take the value after the decimal point, multiply by 64, and divide * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to * implement fixed point or floating point dB volumes. For now, I'll set them * to 0 just incase a value has lingered from a boot into Windows. */ static void ca0132_alt_vol_setup(struct hda_codec *codec) { snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); } /* * Extra commands that don't really fit anywhere else. */ static void sbz_pre_dsp_setup(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; writel(0x00820680, spec->mem_base + 0x01C); writel(0x00820680, spec->mem_base + 0x01C); chipio_write(codec, 0x18b0a4, 0x000000c2); snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); } static void r3d_pre_dsp_setup(struct hda_codec *codec) { chipio_write(codec, 0x18b0a4, 0x000000c2); chipio_8051_write_exram(codec, 0x1c1e, 0x5b); snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); } static void r3di_pre_dsp_setup(struct hda_codec *codec) { chipio_write(codec, 0x18b0a4, 0x000000c2); chipio_8051_write_exram(codec, 0x1c1e, 0x5b); chipio_8051_write_exram(codec, 0x1920, 0x00); chipio_8051_write_exram(codec, 0x1921, 0x40); snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); } /* * The ZxR seems to use alternative DAC's for the surround channels, which * require PLL PMU setup for the clock rate, I'm guessing. Without setting * this up, we get no audio out of the surround jacks. */ static void zxr_pre_dsp_setup(struct hda_codec *codec) { static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; unsigned int i; chipio_write(codec, 0x189000, 0x0001f100); msleep(50); chipio_write(codec, 0x18900c, 0x0001f100); msleep(50); /* * This writes a RET instruction at the entry point of the function at * 0xfa92 in exram. This function seems to have something to do with * ASI. Might be some way to prevent the card from reconfiguring the * ASI stuff itself. */ chipio_8051_write_exram(codec, 0xfa92, 0x22); chipio_8051_write_pll_pmu(codec, 0x51, 0x98); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); chipio_write(codec, 0x18902c, 0x00000000); msleep(50); chipio_write(codec, 0x18902c, 0x00000003); msleep(50); for (i = 0; i < ARRAY_SIZE(addr); i++) chipio_8051_write_pll_pmu(codec, addr[i], data[i]); } /* * These are sent before the DSP is downloaded. Not sure * what they do, or if they're necessary. Could possibly * be removed. Figure they're better to leave in. */ static const unsigned int ca0113_mmio_init_address_sbz[] = { 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 }; static const unsigned int ca0113_mmio_init_data_sbz[] = { 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 0x00000080 }; static const unsigned int ca0113_mmio_init_data_zxr[] = { 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 0x00000080 }; static const unsigned int ca0113_mmio_init_address_ae5[] = { 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c }; static const unsigned int ca0113_mmio_init_data_ae5[] = { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 0x00000080, 0x00880680 }; static void ca0132_mmio_init_sbz(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int tmp[2], i, count, cur_addr; const unsigned int *addr, *data; addr = ca0113_mmio_init_address_sbz; for (i = 0; i < 3; i++) writel(0x00000000, spec->mem_base + addr[i]); cur_addr = i; switch (ca0132_quirk(spec)) { case QUIRK_ZXR: tmp[0] = 0x00880480; tmp[1] = 0x00000080; break; case QUIRK_SBZ: tmp[0] = 0x00820680; tmp[1] = 0x00000083; break; case QUIRK_R3D: tmp[0] = 0x00880680; tmp[1] = 0x00000083; break; default: tmp[0] = 0x00000000; tmp[1] = 0x00000000; break; } for (i = 0; i < 2; i++) writel(tmp[i], spec->mem_base + addr[cur_addr + i]); cur_addr += i; switch (ca0132_quirk(spec)) { case QUIRK_ZXR: count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); data = ca0113_mmio_init_data_zxr; break; default: count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); data = ca0113_mmio_init_data_sbz; break; } for (i = 0; i < count; i++) writel(data[i], spec->mem_base + addr[cur_addr + i]); } static void ca0132_mmio_init_ae5(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; const unsigned int *addr, *data; unsigned int i, count; addr = ca0113_mmio_init_address_ae5; data = ca0113_mmio_init_data_ae5; count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); if (ca0132_quirk(spec) == QUIRK_AE7) { writel(0x00000680, spec->mem_base + 0x1c); writel(0x00880680, spec->mem_base + 0x1c); } for (i = 0; i < count; i++) { /* * AE-7 shares all writes with the AE-5, except that it writes * a different value to 0x20c. */ if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { writel(0x00800001, spec->mem_base + addr[i]); continue; } writel(data[i], spec->mem_base + addr[i]); } if (ca0132_quirk(spec) == QUIRK_AE5) writel(0x00880680, spec->mem_base + 0x1c); } static void ca0132_mmio_init(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; switch (ca0132_quirk(spec)) { case QUIRK_R3D: case QUIRK_SBZ: case QUIRK_ZXR: ca0132_mmio_init_sbz(codec); break; case QUIRK_AE5: ca0132_mmio_init_ae5(codec); break; default: break; } } static const unsigned int ca0132_ae5_register_set_addresses[] = { 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 }; static const unsigned char ca0132_ae5_register_set_data[] = { 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 0x01, 0x6b, 0x57 }; /* * This function writes to some SFR's, does some region2 writes, and then * eventually resets the codec with the 0x7ff verb. Not quite sure why it does * what it does. */ static void ae5_register_set(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); const unsigned int *addr = ca0132_ae5_register_set_addresses; const unsigned char *data = ca0132_ae5_register_set_data; unsigned int i, cur_addr; unsigned char tmp[3]; if (ca0132_quirk(spec) == QUIRK_AE7) chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); chipio_8051_write_direct(codec, 0x93, 0x10); chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); if (ca0132_quirk(spec) == QUIRK_AE7) { tmp[0] = 0x03; tmp[1] = 0x03; tmp[2] = 0x07; } else { tmp[0] = 0x0f; tmp[1] = 0x0f; tmp[2] = 0x0f; } for (i = cur_addr = 0; i < 3; i++, cur_addr++) writeb(tmp[i], spec->mem_base + addr[cur_addr]); /* * First writes are in single bytes, final are in 4 bytes. So, we use * writeb, then writel. */ for (i = 0; cur_addr < 12; i++, cur_addr++) writeb(data[i], spec->mem_base + addr[cur_addr]); for (; cur_addr < count; i++, cur_addr++) writel(data[i], spec->mem_base + addr[cur_addr]); writel(0x00800001, spec->mem_base + 0x20c); if (ca0132_quirk(spec) == QUIRK_AE7) { ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); } else { ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); } chipio_8051_write_direct(codec, 0x90, 0x00); chipio_8051_write_direct(codec, 0x90, 0x10); if (ca0132_quirk(spec) == QUIRK_AE5) ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); } /* * Extra init functions for alternative ca0132 codecs. Done * here so they don't clutter up the main ca0132_init function * anymore than they have to. */ static void ca0132_alt_init(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; ca0132_alt_vol_setup(codec); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: codec_dbg(codec, "SBZ alt_init"); ca0132_gpio_init(codec); sbz_pre_dsp_setup(codec); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_sequence_write(codec, spec->desktop_init_verbs); break; case QUIRK_R3DI: codec_dbg(codec, "R3DI alt_init"); ca0132_gpio_init(codec); ca0132_gpio_setup(codec); r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); r3di_pre_dsp_setup(codec); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); break; case QUIRK_R3D: r3d_pre_dsp_setup(codec); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_sequence_write(codec, spec->desktop_init_verbs); break; case QUIRK_AE5: ca0132_gpio_init(codec); chipio_8051_write_pll_pmu(codec, 0x49, 0x88); chipio_write(codec, 0x18b030, 0x00000020); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_sequence_write(codec, spec->desktop_init_verbs); ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); break; case QUIRK_AE7: ca0132_gpio_init(codec); chipio_8051_write_pll_pmu(codec, 0x49, 0x88); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_sequence_write(codec, spec->desktop_init_verbs); chipio_write(codec, 0x18b008, 0x000000f8); chipio_write(codec, 0x18b008, 0x000000f0); chipio_write(codec, 0x18b030, 0x00000020); ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); break; case QUIRK_ZXR: chipio_8051_write_pll_pmu(codec, 0x49, 0x88); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_sequence_write(codec, spec->desktop_init_verbs); zxr_pre_dsp_setup(codec); break; default: break; } } static int ca0132_init(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->autocfg; int i; bool dsp_loaded; /* * If the DSP is already downloaded, and init has been entered again, * there's only two reasons for it. One, the codec has awaken from a * suspended state, and in that case dspload_is_loaded will return * false, and the init will be ran again. The other reason it gets * re entered is on startup for some reason it triggers a suspend and * resume state. In this case, it will check if the DSP is downloaded, * and not run the init function again. For codecs using alt_functions, * it will check if the DSP is loaded properly. */ if (spec->dsp_state == DSP_DOWNLOADED) { dsp_loaded = dspload_is_loaded(codec); if (!dsp_loaded) { spec->dsp_reload = true; spec->dsp_state = DSP_DOWNLOAD_INIT; } else { if (ca0132_quirk(spec) == QUIRK_SBZ) sbz_dsp_startup_check(codec); return 0; } } if (spec->dsp_state != DSP_DOWNLOAD_FAILED) spec->dsp_state = DSP_DOWNLOAD_INIT; spec->curr_chip_addx = INVALID_CHIP_ADDRESS; if (ca0132_use_pci_mmio(spec)) ca0132_mmio_init(codec); snd_hda_power_up_pm(codec); if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) ae5_register_set(codec); ca0132_init_params(codec); ca0132_init_flags(codec); snd_hda_sequence_write(codec, spec->base_init_verbs); if (ca0132_use_alt_functions(spec)) ca0132_alt_init(codec); ca0132_download_dsp(codec); ca0132_refresh_widget_caps(codec); switch (ca0132_quirk(spec)) { case QUIRK_R3DI: case QUIRK_R3D: r3d_setup_defaults(codec); break; case QUIRK_SBZ: case QUIRK_ZXR: sbz_setup_defaults(codec); break; case QUIRK_AE5: ae5_setup_defaults(codec); break; case QUIRK_AE7: ae7_setup_defaults(codec); break; default: ca0132_setup_defaults(codec); ca0132_init_analog_mic2(codec); ca0132_init_dmic(codec); break; } for (i = 0; i < spec->num_outputs; i++) init_output(codec, spec->out_pins[i], spec->dacs[0]); init_output(codec, cfg->dig_out_pins[0], spec->dig_out); for (i = 0; i < spec->num_inputs; i++) init_input(codec, spec->input_pins[i], spec->adcs[i]); init_input(codec, cfg->dig_in_pin, spec->dig_in); if (!ca0132_use_alt_functions(spec)) { snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); } if (ca0132_quirk(spec) == QUIRK_SBZ) ca0132_gpio_setup(codec); snd_hda_sequence_write(codec, spec->spec_init_verbs); if (ca0132_use_alt_functions(spec)) { ca0132_alt_select_out(codec); ca0132_alt_select_in(codec); } else { ca0132_select_out(codec); ca0132_select_mic(codec); } snd_hda_jack_report_sync(codec); /* * Re set the PlayEnhancement switch on a resume event, because the * controls will not be reloaded. */ if (spec->dsp_reload) { spec->dsp_reload = false; ca0132_pe_switch_set(codec); } snd_hda_power_down_pm(codec); return 0; } static int dbpro_init(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->autocfg; unsigned int i; init_output(codec, cfg->dig_out_pins[0], spec->dig_out); init_input(codec, cfg->dig_in_pin, spec->dig_in); for (i = 0; i < spec->num_inputs; i++) init_input(codec, spec->input_pins[i], spec->adcs[i]); return 0; } static void ca0132_free(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; cancel_delayed_work_sync(&spec->unsol_hp_work); snd_hda_power_up(codec); switch (ca0132_quirk(spec)) { case QUIRK_SBZ: sbz_exit_chip(codec); break; case QUIRK_ZXR: zxr_exit_chip(codec); break; case QUIRK_R3D: r3d_exit_chip(codec); break; case QUIRK_AE5: ae5_exit_chip(codec); break; case QUIRK_AE7: ae7_exit_chip(codec); break; case QUIRK_R3DI: r3di_gpio_shutdown(codec); break; default: break; } snd_hda_sequence_write(codec, spec->base_exit_verbs); ca0132_exit_chip(codec); snd_hda_power_down(codec); #ifdef CONFIG_PCI if (spec->mem_base) pci_iounmap(codec->bus->pci, spec->mem_base); #endif kfree(spec->spec_init_verbs); kfree(codec->spec); } static void dbpro_free(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; zxr_dbpro_power_state_shutdown(codec); kfree(spec->spec_init_verbs); kfree(codec->spec); } #ifdef CONFIG_PM static int ca0132_suspend(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; cancel_delayed_work_sync(&spec->unsol_hp_work); return 0; } #endif static const struct hda_codec_ops ca0132_patch_ops = { .build_controls = ca0132_build_controls, .build_pcms = ca0132_build_pcms, .init = ca0132_init, .free = ca0132_free, .unsol_event = snd_hda_jack_unsol_event, #ifdef CONFIG_PM .suspend = ca0132_suspend, #endif }; static const struct hda_codec_ops dbpro_patch_ops = { .build_controls = dbpro_build_controls, .build_pcms = dbpro_build_pcms, .init = dbpro_init, .free = dbpro_free, }; static void ca0132_config(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; spec->dacs[0] = 0x2; spec->dacs[1] = 0x3; spec->dacs[2] = 0x4; spec->multiout.dac_nids = spec->dacs; spec->multiout.num_dacs = 3; if (!ca0132_use_alt_functions(spec)) spec->multiout.max_channels = 2; else spec->multiout.max_channels = 6; switch (ca0132_quirk(spec)) { case QUIRK_ALIENWARE: codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); snd_hda_apply_pincfgs(codec, alienware_pincfgs); break; case QUIRK_SBZ: codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); snd_hda_apply_pincfgs(codec, sbz_pincfgs); break; case QUIRK_ZXR: codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); snd_hda_apply_pincfgs(codec, zxr_pincfgs); break; case QUIRK_R3D: codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); snd_hda_apply_pincfgs(codec, r3d_pincfgs); break; case QUIRK_R3DI: codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); snd_hda_apply_pincfgs(codec, r3di_pincfgs); break; case QUIRK_AE5: codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); snd_hda_apply_pincfgs(codec, ae5_pincfgs); break; case QUIRK_AE7: codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); snd_hda_apply_pincfgs(codec, ae7_pincfgs); break; default: break; } switch (ca0132_quirk(spec)) { case QUIRK_ALIENWARE: spec->num_outputs = 2; spec->out_pins[0] = 0x0b; /* speaker out */ spec->out_pins[1] = 0x0f; spec->shared_out_nid = 0x2; spec->unsol_tag_hp = 0x0f; spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ spec->adcs[1] = 0x8; /* analog mic2 */ spec->adcs[2] = 0xa; /* what u hear */ spec->num_inputs = 3; spec->input_pins[0] = 0x12; spec->input_pins[1] = 0x11; spec->input_pins[2] = 0x13; spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = 0x11; break; case QUIRK_SBZ: case QUIRK_R3D: spec->num_outputs = 2; spec->out_pins[0] = 0x0B; /* Line out */ spec->out_pins[1] = 0x0F; /* Rear headphone out */ spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ spec->out_pins[3] = 0x11; /* Rear surround */ spec->shared_out_nid = 0x2; spec->unsol_tag_hp = spec->out_pins[1]; spec->unsol_tag_front_hp = spec->out_pins[2]; spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ spec->adcs[2] = 0xa; /* what u hear */ spec->num_inputs = 2; spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ spec->input_pins[1] = 0x13; /* What U Hear */ spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = spec->input_pins[0]; /* SPDIF I/O */ spec->dig_out = 0x05; spec->multiout.dig_out_nid = spec->dig_out; spec->dig_in = 0x09; break; case QUIRK_ZXR: spec->num_outputs = 2; spec->out_pins[0] = 0x0B; /* Line out */ spec->out_pins[1] = 0x0F; /* Rear headphone out */ spec->out_pins[2] = 0x10; /* Center/LFE */ spec->out_pins[3] = 0x11; /* Rear surround */ spec->shared_out_nid = 0x2; spec->unsol_tag_hp = spec->out_pins[1]; spec->unsol_tag_front_hp = spec->out_pins[2]; spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ spec->adcs[1] = 0x8; /* Not connected, no front mic */ spec->adcs[2] = 0xa; /* what u hear */ spec->num_inputs = 2; spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ spec->input_pins[1] = 0x13; /* What U Hear */ spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = spec->input_pins[0]; break; case QUIRK_ZXR_DBPRO: spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ spec->num_inputs = 1; spec->input_pins[0] = 0x11; /* RCA Line-in */ spec->dig_out = 0x05; spec->multiout.dig_out_nid = spec->dig_out; spec->dig_in = 0x09; break; case QUIRK_AE5: case QUIRK_AE7: spec->num_outputs = 2; spec->out_pins[0] = 0x0B; /* Line out */ spec->out_pins[1] = 0x11; /* Rear headphone out */ spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ spec->out_pins[3] = 0x0F; /* Rear surround */ spec->shared_out_nid = 0x2; spec->unsol_tag_hp = spec->out_pins[1]; spec->unsol_tag_front_hp = spec->out_pins[2]; spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ spec->adcs[2] = 0xa; /* what u hear */ spec->num_inputs = 2; spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ spec->input_pins[1] = 0x13; /* What U Hear */ spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = spec->input_pins[0]; /* SPDIF I/O */ spec->dig_out = 0x05; spec->multiout.dig_out_nid = spec->dig_out; break; case QUIRK_R3DI: spec->num_outputs = 2; spec->out_pins[0] = 0x0B; /* Line out */ spec->out_pins[1] = 0x0F; /* Rear headphone out */ spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ spec->out_pins[3] = 0x11; /* Rear surround */ spec->shared_out_nid = 0x2; spec->unsol_tag_hp = spec->out_pins[1]; spec->unsol_tag_front_hp = spec->out_pins[2]; spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ spec->adcs[2] = 0x0a; /* what u hear */ spec->num_inputs = 2; spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ spec->input_pins[1] = 0x13; /* What U Hear */ spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = spec->input_pins[0]; /* SPDIF I/O */ spec->dig_out = 0x05; spec->multiout.dig_out_nid = spec->dig_out; break; default: spec->num_outputs = 2; spec->out_pins[0] = 0x0b; /* speaker out */ spec->out_pins[1] = 0x10; /* headphone out */ spec->shared_out_nid = 0x2; spec->unsol_tag_hp = spec->out_pins[1]; spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ spec->adcs[1] = 0x8; /* analog mic2 */ spec->adcs[2] = 0xa; /* what u hear */ spec->num_inputs = 3; spec->input_pins[0] = 0x12; spec->input_pins[1] = 0x11; spec->input_pins[2] = 0x13; spec->shared_mic_nid = 0x7; spec->unsol_tag_amic1 = spec->input_pins[0]; /* SPDIF I/O */ spec->dig_out = 0x05; spec->multiout.dig_out_nid = spec->dig_out; spec->dig_in = 0x09; break; } } static int ca0132_prepare_verbs(struct hda_codec *codec) { /* Verbs + terminator (an empty element) */ #define NUM_SPEC_VERBS 2 struct ca0132_spec *spec = codec->spec; spec->chip_init_verbs = ca0132_init_verbs0; /* * Since desktop cards use pci_mmio, this can be used to determine * whether or not to use these verbs instead of a separate bool. */ if (ca0132_use_pci_mmio(spec)) spec->desktop_init_verbs = ca0132_init_verbs1; spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, sizeof(struct hda_verb), GFP_KERNEL); if (!spec->spec_init_verbs) return -ENOMEM; /* config EAPD */ spec->spec_init_verbs[0].nid = 0x0b; spec->spec_init_verbs[0].param = 0x78D; spec->spec_init_verbs[0].verb = 0x00; /* Previously commented configuration */ /* spec->spec_init_verbs[2].nid = 0x0b; spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; spec->spec_init_verbs[2].verb = 0x02; spec->spec_init_verbs[3].nid = 0x10; spec->spec_init_verbs[3].param = 0x78D; spec->spec_init_verbs[3].verb = 0x02; spec->spec_init_verbs[4].nid = 0x10; spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; spec->spec_init_verbs[4].verb = 0x02; */ /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ return 0; } /* * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular * Sound Blaster Z cards. However, they have different HDA codec subsystem * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro * daughter boards ID. */ static void sbz_detect_quirk(struct hda_codec *codec) { struct ca0132_spec *spec = codec->spec; switch (codec->core.subsystem_id) { case 0x11020033: spec->quirk = QUIRK_ZXR; break; case 0x1102003f: spec->quirk = QUIRK_ZXR_DBPRO; break; default: spec->quirk = QUIRK_SBZ; break; } } static int patch_ca0132(struct hda_codec *codec) { struct ca0132_spec *spec; int err; const struct snd_pci_quirk *quirk; codec_dbg(codec, "patch_ca0132\n"); spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return -ENOMEM; codec->spec = spec; spec->codec = codec; /* Detect codec quirk */ quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); if (quirk) spec->quirk = quirk->value; else spec->quirk = QUIRK_NONE; if (ca0132_quirk(spec) == QUIRK_SBZ) sbz_detect_quirk(codec); if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) codec->patch_ops = dbpro_patch_ops; else codec->patch_ops = ca0132_patch_ops; codec->pcm_format_first = 1; codec->no_sticky_stream = 1; spec->dsp_state = DSP_DOWNLOAD_INIT; spec->num_mixers = 1; /* Set which mixers each quirk uses. */ switch (ca0132_quirk(spec)) { case QUIRK_SBZ: spec->mixers[0] = desktop_mixer; snd_hda_codec_set_name(codec, "Sound Blaster Z"); break; case QUIRK_ZXR: spec->mixers[0] = desktop_mixer; snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); break; case QUIRK_ZXR_DBPRO: break; case QUIRK_R3D: spec->mixers[0] = desktop_mixer; snd_hda_codec_set_name(codec, "Recon3D"); break; case QUIRK_R3DI: spec->mixers[0] = r3di_mixer; snd_hda_codec_set_name(codec, "Recon3Di"); break; case QUIRK_AE5: spec->mixers[0] = desktop_mixer; snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); break; case QUIRK_AE7: spec->mixers[0] = desktop_mixer; snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); break; default: spec->mixers[0] = ca0132_mixer; break; } /* Setup whether or not to use alt functions/controls/pci_mmio */ switch (ca0132_quirk(spec)) { case QUIRK_SBZ: case QUIRK_R3D: case QUIRK_AE5: case QUIRK_AE7: case QUIRK_ZXR: spec->use_alt_controls = true; spec->use_alt_functions = true; spec->use_pci_mmio = true; break; case QUIRK_R3DI: spec->use_alt_controls = true; spec->use_alt_functions = true; spec->use_pci_mmio = false; break; default: spec->use_alt_controls = false; spec->use_alt_functions = false; spec->use_pci_mmio = false; break; } #ifdef CONFIG_PCI if (spec->use_pci_mmio) { spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); if (spec->mem_base == NULL) { codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); spec->quirk = QUIRK_NONE; } } #endif spec->base_init_verbs = ca0132_base_init_verbs; spec->base_exit_verbs = ca0132_base_exit_verbs; INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); ca0132_init_chip(codec); ca0132_config(codec); err = ca0132_prepare_verbs(codec); if (err < 0) goto error; err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); if (err < 0) goto error; ca0132_setup_unsol(codec); return 0; error: ca0132_free(codec); return err; } /* * patch entries */ static const struct hda_device_id snd_hda_id_ca0132[] = { HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Creative Sound Core3D codec"); static struct hda_codec_driver ca0132_driver = { .id = snd_hda_id_ca0132, }; module_hda_codec_driver(ca0132_driver);
linux-master
sound/pci/hda/patch_ca0132.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * HWDEP Interface for HD-audio codec * * Copyright (c) 2007 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/slab.h> #include <linux/compat.h> #include <linux/nospec.h> #include <sound/core.h> #include <sound/hda_codec.h> #include "hda_local.h" #include <sound/hda_hwdep.h> #include <sound/minors.h> /* * write/read an out-of-bound verb */ static int verb_write_ioctl(struct hda_codec *codec, struct hda_verb_ioctl __user *arg) { u32 verb, res; if (get_user(verb, &arg->verb)) return -EFAULT; res = snd_hda_codec_read(codec, verb >> 24, 0, (verb >> 8) & 0xffff, verb & 0xff); if (put_user(res, &arg->res)) return -EFAULT; return 0; } static int get_wcap_ioctl(struct hda_codec *codec, struct hda_verb_ioctl __user *arg) { u32 verb, res; if (get_user(verb, &arg->verb)) return -EFAULT; /* open-code get_wcaps(verb>>24) with nospec */ verb >>= 24; if (verb < codec->core.start_nid || verb >= codec->core.start_nid + codec->core.num_nodes) { res = 0; } else { verb -= codec->core.start_nid; verb = array_index_nospec(verb, codec->core.num_nodes); res = codec->wcaps[verb]; } if (put_user(res, &arg->res)) return -EFAULT; return 0; } /* */ static int hda_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) { struct hda_codec *codec = hw->private_data; void __user *argp = (void __user *)arg; switch (cmd) { case HDA_IOCTL_PVERSION: return put_user(HDA_HWDEP_VERSION, (int __user *)argp); case HDA_IOCTL_VERB_WRITE: return verb_write_ioctl(codec, argp); case HDA_IOCTL_GET_WCAP: return get_wcap_ioctl(codec, argp); } return -ENOIOCTLCMD; } #ifdef CONFIG_COMPAT static int hda_hwdep_ioctl_compat(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) { return hda_hwdep_ioctl(hw, file, cmd, (unsigned long)compat_ptr(arg)); } #endif static int hda_hwdep_open(struct snd_hwdep *hw, struct file *file) { #ifndef CONFIG_SND_DEBUG_VERBOSE if (!capable(CAP_SYS_RAWIO)) return -EACCES; #endif return 0; } int snd_hda_create_hwdep(struct hda_codec *codec) { char hwname[16]; struct snd_hwdep *hwdep; int err; sprintf(hwname, "HDA Codec %d", codec->addr); err = snd_hwdep_new(codec->card, hwname, codec->addr, &hwdep); if (err < 0) return err; codec->hwdep = hwdep; sprintf(hwdep->name, "HDA Codec %d", codec->addr); hwdep->iface = SNDRV_HWDEP_IFACE_HDA; hwdep->private_data = codec; hwdep->exclusive = 1; hwdep->ops.open = hda_hwdep_open; hwdep->ops.ioctl = hda_hwdep_ioctl; #ifdef CONFIG_COMPAT hwdep->ops.ioctl_compat = hda_hwdep_ioctl_compat; #endif /* for sysfs */ hwdep->dev->groups = snd_hda_dev_attr_groups; dev_set_drvdata(hwdep->dev, codec); return 0; }
linux-master
sound/pci/hda/hda_hwdep.c
// SPDX-License-Identifier: GPL-2.0-only /* * * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. */ #include <linux/clk.h> #include <linux/clocksource.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/time.h> #include <linux/string.h> #include <linux/pm_runtime.h> #include <sound/core.h> #include <sound/initval.h> #include <sound/hda_codec.h> #include "hda_controller.h" /* Defines for Nvidia Tegra HDA support */ #define HDA_BAR0 0x8000 #define HDA_CFG_CMD 0x1004 #define HDA_CFG_BAR0 0x1010 #define HDA_ENABLE_IO_SPACE (1 << 0) #define HDA_ENABLE_MEM_SPACE (1 << 1) #define HDA_ENABLE_BUS_MASTER (1 << 2) #define HDA_ENABLE_SERR (1 << 8) #define HDA_DISABLE_INTR (1 << 10) #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF #define HDA_BAR0_FINAL_PROGRAM (1 << 14) /* IPFS */ #define HDA_IPFS_CONFIG 0x180 #define HDA_IPFS_EN_FPCI 0x1 #define HDA_IPFS_FPCI_BAR0 0x80 #define HDA_FPCI_BAR0_START 0x40 #define HDA_IPFS_INTR_MASK 0x188 #define HDA_IPFS_EN_INTR (1 << 16) /* FPCI */ #define FPCI_DBG_CFG_2 0x10F4 #define FPCI_GCAP_NSDO_SHIFT 18 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) /* max number of SDs */ #define NUM_CAPTURE_SD 1 #define NUM_PLAYBACK_SD 1 /* * Tegra194 does not reflect correct number of SDO lines. Below macro * is used to update the GCAP register to workaround the issue. */ #define TEGRA194_NUM_SDO_LINES 4 struct hda_tegra_soc { bool has_hda2codec_2x_reset; bool has_hda2hdmi; }; struct hda_tegra { struct azx chip; struct device *dev; struct reset_control_bulk_data resets[3]; struct clk_bulk_data clocks[3]; unsigned int nresets; unsigned int nclocks; void __iomem *regs; struct work_struct probe_work; const struct hda_tegra_soc *soc; }; #ifdef CONFIG_PM static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; module_param(power_save, bint, 0644); MODULE_PARM_DESC(power_save, "Automatic power-saving timeout (in seconds, 0 = disable)."); #else #define power_save 0 #endif static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ static void hda_tegra_init(struct hda_tegra *hda) { u32 v; /* Enable PCI access */ v = readl(hda->regs + HDA_IPFS_CONFIG); v |= HDA_IPFS_EN_FPCI; writel(v, hda->regs + HDA_IPFS_CONFIG); /* Enable MEM/IO space and bus master */ v = readl(hda->regs + HDA_CFG_CMD); v &= ~HDA_DISABLE_INTR; v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; writel(v, hda->regs + HDA_CFG_CMD); writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); v = readl(hda->regs + HDA_IPFS_INTR_MASK); v |= HDA_IPFS_EN_INTR; writel(v, hda->regs + HDA_IPFS_INTR_MASK); } /* * power management */ static int __maybe_unused hda_tegra_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); int rc; rc = pm_runtime_force_suspend(dev); if (rc < 0) return rc; snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); return 0; } static int __maybe_unused hda_tegra_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); int rc; rc = pm_runtime_force_resume(dev); if (rc < 0) return rc; snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; } static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); if (chip && chip->running) { /* enable controller wake up event */ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); azx_stop_chip(chip); azx_enter_link_reset(chip); } clk_bulk_disable_unprepare(hda->nclocks, hda->clocks); return 0; } static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) { struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); int rc; if (!chip->running) { rc = reset_control_bulk_assert(hda->nresets, hda->resets); if (rc) return rc; } rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); if (rc != 0) return rc; if (chip->running) { hda_tegra_init(hda); azx_init_chip(chip, 1); /* disable controller wake up event*/ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); } else { usleep_range(10, 100); rc = reset_control_bulk_deassert(hda->nresets, hda->resets); if (rc) return rc; } return 0; } static const struct dev_pm_ops hda_tegra_pm = { SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, hda_tegra_runtime_resume, NULL) }; static int hda_tegra_dev_disconnect(struct snd_device *device) { struct azx *chip = device->device_data; chip->bus.shutdown = 1; return 0; } /* * destructor */ static int hda_tegra_dev_free(struct snd_device *device) { struct azx *chip = device->device_data; struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); cancel_work_sync(&hda->probe_work); if (azx_bus(chip)->chip_init) { azx_stop_all_streams(chip); azx_stop_chip(chip); } azx_free_stream_pages(chip); azx_free_streams(chip); snd_hdac_bus_exit(azx_bus(chip)); return 0; } static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) { struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); struct hdac_bus *bus = azx_bus(chip); struct resource *res; hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(hda->regs)) return PTR_ERR(hda->regs); bus->remap_addr = hda->regs + HDA_BAR0; bus->addr = res->start + HDA_BAR0; hda_tegra_init(hda); return 0; } static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) { struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); struct hdac_bus *bus = azx_bus(chip); struct snd_card *card = chip->card; int err; unsigned short gcap; int irq_id = platform_get_irq(pdev, 0); const char *sname, *drv_name = "tegra-hda"; struct device_node *np = pdev->dev.of_node; if (irq_id < 0) return irq_id; err = hda_tegra_init_chip(chip, pdev); if (err) return err; err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, IRQF_SHARED, KBUILD_MODNAME, chip); if (err) { dev_err(chip->card->dev, "unable to request IRQ %d, disabling device\n", irq_id); return err; } bus->irq = irq_id; bus->dma_stop_delay = 100; card->sync_irq = bus->irq; /* * Tegra194 has 4 SDO lines and the STRIPE can be used to * indicate how many of the SDO lines the stream should be * striped. But GCAP register does not reflect the true * capability of HW. Below workaround helps to fix this. * * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. */ if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { u32 val; dev_info(card->dev, "Override SDO lines to %u\n", TEGRA194_NUM_SDO_LINES); val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; writel(val, hda->regs + FPCI_DBG_CFG_2); } gcap = azx_readw(chip, GCAP); dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); chip->align_buffer_size = 1; /* read number of streams from GCAP register instead of using * hardcoded value */ chip->capture_streams = (gcap >> 8) & 0x0f; /* The GCAP register on Tegra234 implies no Input Streams(ISS) support, * but the HW output stream descriptor programming should start with * offset 0x20*4 from base stream descriptor address. This will be a * problem while calculating the offset for output stream descriptor * which will be considering input stream also. So here output stream * starts with offset 0 which is wrong as HW register for output stream * offset starts with 4. */ if (of_device_is_compatible(np, "nvidia,tegra234-hda")) chip->capture_streams = 4; chip->playback_streams = (gcap >> 12) & 0x0f; if (!chip->playback_streams && !chip->capture_streams) { /* gcap didn't give any info, switching to old method */ chip->playback_streams = NUM_PLAYBACK_SD; chip->capture_streams = NUM_CAPTURE_SD; } chip->capture_index_offset = 0; chip->playback_index_offset = chip->capture_streams; chip->num_streams = chip->playback_streams + chip->capture_streams; /* initialize streams */ err = azx_init_streams(chip); if (err < 0) { dev_err(card->dev, "failed to initialize streams: %d\n", err); return err; } err = azx_alloc_stream_pages(chip); if (err < 0) { dev_err(card->dev, "failed to allocate stream pages: %d\n", err); return err; } /* initialize chip */ azx_init_chip(chip, 1); /* * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with * 4 SDO lines due to legacy design limitation. Following * is, from HD Audio Specification (Revision 1.0a), used to * control striping of the stream across multiple SDO lines * for sample rates <= 48K. * * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } * * Due to legacy design issue it is recommended that above * ratio must be greater than 8. Since number of SDO lines is * in powers of 2, next available ratio is 16 which can be * used as a limiting factor here. */ if (of_device_is_compatible(np, "nvidia,tegra30-hda")) chip->bus.core.sdo_limit = 16; /* codec detection */ if (!bus->codec_mask) { dev_err(card->dev, "no codecs found!\n"); return -ENODEV; } /* driver name */ strscpy(card->driver, drv_name, sizeof(card->driver)); /* shortname for card */ sname = of_get_property(np, "nvidia,model", NULL); if (!sname) sname = drv_name; if (strlen(sname) > sizeof(card->shortname)) dev_info(card->dev, "truncating shortname for card\n"); strscpy(card->shortname, sname, sizeof(card->shortname)); /* longname for card */ snprintf(card->longname, sizeof(card->longname), "%s at 0x%lx irq %i", card->shortname, bus->addr, bus->irq); return 0; } /* * constructor */ static void hda_tegra_probe_work(struct work_struct *work); static int hda_tegra_create(struct snd_card *card, unsigned int driver_caps, struct hda_tegra *hda) { static const struct snd_device_ops ops = { .dev_disconnect = hda_tegra_dev_disconnect, .dev_free = hda_tegra_dev_free, }; struct azx *chip; int err; chip = &hda->chip; mutex_init(&chip->open_mutex); chip->card = card; chip->ops = &hda_tegra_ops; chip->driver_caps = driver_caps; chip->driver_type = driver_caps & 0xff; chip->dev_index = 0; chip->jackpoll_interval = msecs_to_jiffies(5000); INIT_LIST_HEAD(&chip->pcm_list); chip->codec_probe_mask = -1; chip->single_cmd = false; chip->snoop = true; INIT_WORK(&hda->probe_work, hda_tegra_probe_work); err = azx_bus_init(chip, NULL); if (err < 0) return err; chip->bus.core.sync_write = 0; chip->bus.core.needs_damn_long_delay = 1; chip->bus.core.aligned_mmio = 1; chip->bus.jackpoll_in_suspend = 1; err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); if (err < 0) { dev_err(card->dev, "Error creating device\n"); return err; } return 0; } static const struct hda_tegra_soc tegra30_data = { .has_hda2codec_2x_reset = true, .has_hda2hdmi = true, }; static const struct hda_tegra_soc tegra194_data = { .has_hda2codec_2x_reset = false, .has_hda2hdmi = true, }; static const struct hda_tegra_soc tegra234_data = { .has_hda2codec_2x_reset = true, .has_hda2hdmi = false, }; static const struct of_device_id hda_tegra_match[] = { { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data }, { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data }, { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data }, {}, }; MODULE_DEVICE_TABLE(of, hda_tegra_match); static int hda_tegra_probe(struct platform_device *pdev) { const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_4K_BDLE_BOUNDARY; struct snd_card *card; struct azx *chip; struct hda_tegra *hda; int err; hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); if (!hda) return -ENOMEM; hda->dev = &pdev->dev; chip = &hda->chip; hda->soc = of_device_get_match_data(&pdev->dev); err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, THIS_MODULE, 0, &card); if (err < 0) { dev_err(&pdev->dev, "Error creating card!\n"); return err; } hda->resets[hda->nresets++].id = "hda"; /* * "hda2hdmi" is not applicable for Tegra234. This is because the * codec is separate IP and not under display SOR partition now. */ if (hda->soc->has_hda2hdmi) hda->resets[hda->nresets++].id = "hda2hdmi"; /* * "hda2codec_2x" reset is not present on Tegra194. Though DT would * be updated to reflect this, but to have backward compatibility * below is necessary. */ if (hda->soc->has_hda2codec_2x_reset) hda->resets[hda->nresets++].id = "hda2codec_2x"; err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets, hda->resets); if (err) goto out_free; hda->clocks[hda->nclocks++].id = "hda"; if (hda->soc->has_hda2hdmi) hda->clocks[hda->nclocks++].id = "hda2hdmi"; hda->clocks[hda->nclocks++].id = "hda2codec_2x"; err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); if (err < 0) goto out_free; err = hda_tegra_create(card, driver_flags, hda); if (err < 0) goto out_free; card->private_data = chip; dev_set_drvdata(&pdev->dev, card); pm_runtime_enable(hda->dev); if (!azx_has_pm_runtime(chip)) pm_runtime_forbid(hda->dev); schedule_work(&hda->probe_work); return 0; out_free: snd_card_free(card); return err; } static void hda_tegra_probe_work(struct work_struct *work) { struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); struct azx *chip = &hda->chip; struct platform_device *pdev = to_platform_device(hda->dev); int err; pm_runtime_get_sync(hda->dev); err = hda_tegra_first_init(chip, pdev); if (err < 0) goto out_free; /* create codec instances */ err = azx_probe_codecs(chip, 8); if (err < 0) goto out_free; err = azx_codec_configure(chip); if (err < 0) goto out_free; err = snd_card_register(chip->card); if (err < 0) goto out_free; chip->running = 1; snd_hda_set_power_save(&chip->bus, power_save * 1000); out_free: pm_runtime_put(hda->dev); return; /* no error return from async probe */ } static void hda_tegra_remove(struct platform_device *pdev) { snd_card_free(dev_get_drvdata(&pdev->dev)); pm_runtime_disable(&pdev->dev); } static void hda_tegra_shutdown(struct platform_device *pdev) { struct snd_card *card = dev_get_drvdata(&pdev->dev); struct azx *chip; if (!card) return; chip = card->private_data; if (chip && chip->running) azx_stop_chip(chip); } static struct platform_driver tegra_platform_hda = { .driver = { .name = "tegra-hda", .pm = &hda_tegra_pm, .of_match_table = hda_tegra_match, }, .probe = hda_tegra_probe, .remove_new = hda_tegra_remove, .shutdown = hda_tegra_shutdown, }; module_platform_driver(tegra_platform_hda); MODULE_DESCRIPTION("Tegra HDA bus driver"); MODULE_LICENSE("GPL v2");
linux-master
sound/pci/hda/hda_tegra.c
// SPDX-License-Identifier: GPL-2.0+ /* * Digital Beep Input Interface for HD-audio codec * * Author: Matt Ranostay <[email protected]> * Copyright (c) 2008 Embedded Alley Solutions Inc */ #include <linux/input.h> #include <linux/slab.h> #include <linux/workqueue.h> #include <linux/export.h> #include <sound/core.h> #include "hda_beep.h" #include "hda_local.h" enum { DIGBEEP_HZ_STEP = 46875, /* 46.875 Hz */ DIGBEEP_HZ_MIN = 93750, /* 93.750 Hz */ DIGBEEP_HZ_MAX = 12000000, /* 12 KHz */ }; /* generate or stop tone */ static void generate_tone(struct hda_beep *beep, int tone) { struct hda_codec *codec = beep->codec; if (tone && !beep->playing) { snd_hda_power_up(codec); if (beep->power_hook) beep->power_hook(beep, true); beep->playing = 1; } snd_hda_codec_write(codec, beep->nid, 0, AC_VERB_SET_BEEP_CONTROL, tone); if (!tone && beep->playing) { beep->playing = 0; if (beep->power_hook) beep->power_hook(beep, false); snd_hda_power_down(codec); } } static void snd_hda_generate_beep(struct work_struct *work) { struct hda_beep *beep = container_of(work, struct hda_beep, beep_work); if (beep->enabled) generate_tone(beep, beep->tone); } /* (non-standard) Linear beep tone calculation for IDT/STAC codecs * * The tone frequency of beep generator on IDT/STAC codecs is * defined from the 8bit tone parameter, in Hz, * freq = 48000 * (257 - tone) / 1024 * that is from 12kHz to 93.75Hz in steps of 46.875 Hz */ static int beep_linear_tone(struct hda_beep *beep, int hz) { if (hz <= 0) return 0; hz *= 1000; /* fixed point */ hz = hz - DIGBEEP_HZ_MIN + DIGBEEP_HZ_STEP / 2; /* round to nearest step */ if (hz < 0) hz = 0; /* turn off PC beep*/ else if (hz >= (DIGBEEP_HZ_MAX - DIGBEEP_HZ_MIN)) hz = 1; /* max frequency */ else { hz /= DIGBEEP_HZ_STEP; hz = 255 - hz; } return hz; } /* HD-audio standard beep tone parameter calculation * * The tone frequency in Hz is calculated as * freq = 48000 / (tone * 4) * from 47Hz to 12kHz */ static int beep_standard_tone(struct hda_beep *beep, int hz) { if (hz <= 0) return 0; /* disabled */ hz = 12000 / hz; if (hz > 0xff) return 0xff; if (hz <= 0) return 1; return hz; } static int snd_hda_beep_event(struct input_dev *dev, unsigned int type, unsigned int code, int hz) { struct hda_beep *beep = input_get_drvdata(dev); switch (code) { case SND_BELL: if (hz) hz = 1000; fallthrough; case SND_TONE: if (beep->linear_tone) beep->tone = beep_linear_tone(beep, hz); else beep->tone = beep_standard_tone(beep, hz); break; default: return -1; } /* schedule beep event */ schedule_work(&beep->beep_work); return 0; } static void turn_on_beep(struct hda_beep *beep) { if (beep->keep_power_at_enable) snd_hda_power_up_pm(beep->codec); } static void turn_off_beep(struct hda_beep *beep) { cancel_work_sync(&beep->beep_work); if (beep->playing) { /* turn off beep */ generate_tone(beep, 0); } if (beep->keep_power_at_enable) snd_hda_power_down_pm(beep->codec); } /** * snd_hda_enable_beep_device - Turn on/off beep sound * @codec: the HDA codec * @enable: flag to turn on/off */ int snd_hda_enable_beep_device(struct hda_codec *codec, int enable) { struct hda_beep *beep = codec->beep; if (!beep) return 0; enable = !!enable; if (beep->enabled != enable) { beep->enabled = enable; if (enable) turn_on_beep(beep); else turn_off_beep(beep); return 1; } return 0; } EXPORT_SYMBOL_GPL(snd_hda_enable_beep_device); static int beep_dev_register(struct snd_device *device) { struct hda_beep *beep = device->device_data; int err; err = input_register_device(beep->dev); if (!err) beep->registered = true; return err; } static int beep_dev_disconnect(struct snd_device *device) { struct hda_beep *beep = device->device_data; if (beep->registered) input_unregister_device(beep->dev); else input_free_device(beep->dev); if (beep->enabled) turn_off_beep(beep); return 0; } static int beep_dev_free(struct snd_device *device) { struct hda_beep *beep = device->device_data; beep->codec->beep = NULL; kfree(beep); return 0; } /** * snd_hda_attach_beep_device - Attach a beep input device * @codec: the HDA codec * @nid: beep NID * * Attach a beep object to the given widget. If beep hint is turned off * explicitly or beep_mode of the codec is turned off, this doesn't nothing. * * Currently, only one beep device is allowed to each codec. */ int snd_hda_attach_beep_device(struct hda_codec *codec, int nid) { static const struct snd_device_ops ops = { .dev_register = beep_dev_register, .dev_disconnect = beep_dev_disconnect, .dev_free = beep_dev_free, }; struct input_dev *input_dev; struct hda_beep *beep; int err; if (!snd_hda_get_bool_hint(codec, "beep")) return 0; /* disabled explicitly by hints */ if (codec->beep_mode == HDA_BEEP_MODE_OFF) return 0; /* disabled by module option */ beep = kzalloc(sizeof(*beep), GFP_KERNEL); if (beep == NULL) return -ENOMEM; snprintf(beep->phys, sizeof(beep->phys), "card%d/codec#%d/beep0", codec->card->number, codec->addr); /* enable linear scale */ snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_DIGI_CONVERT_2, 0x01); beep->nid = nid; beep->codec = codec; codec->beep = beep; INIT_WORK(&beep->beep_work, &snd_hda_generate_beep); mutex_init(&beep->mutex); input_dev = input_allocate_device(); if (!input_dev) { err = -ENOMEM; goto err_free; } /* setup digital beep device */ input_dev->name = "HDA Digital PCBeep"; input_dev->phys = beep->phys; input_dev->id.bustype = BUS_PCI; input_dev->dev.parent = &codec->card->card_dev; input_dev->id.vendor = codec->core.vendor_id >> 16; input_dev->id.product = codec->core.vendor_id & 0xffff; input_dev->id.version = 0x01; input_dev->evbit[0] = BIT_MASK(EV_SND); input_dev->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); input_dev->event = snd_hda_beep_event; input_set_drvdata(input_dev, beep); beep->dev = input_dev; err = snd_device_new(codec->card, SNDRV_DEV_JACK, beep, &ops); if (err < 0) goto err_input; return 0; err_input: input_free_device(beep->dev); err_free: kfree(beep); codec->beep = NULL; return err; } EXPORT_SYMBOL_GPL(snd_hda_attach_beep_device); /** * snd_hda_detach_beep_device - Detach the beep device * @codec: the HDA codec */ void snd_hda_detach_beep_device(struct hda_codec *codec) { if (!codec->bus->shutdown && codec->beep) snd_device_free(codec->card, codec->beep); } EXPORT_SYMBOL_GPL(snd_hda_detach_beep_device); static bool ctl_has_mute(struct snd_kcontrol *kcontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); return query_amp_caps(codec, get_amp_nid(kcontrol), get_amp_direction(kcontrol)) & AC_AMPCAP_MUTE; } /* get/put callbacks for beep mute mixer switches */ /** * snd_hda_mixer_amp_switch_get_beep - Get callback for beep controls * @kcontrol: ctl element * @ucontrol: pointer to get/store the data */ int snd_hda_mixer_amp_switch_get_beep(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct hda_beep *beep = codec->beep; int chs = get_amp_channels(kcontrol); if (beep && (!beep->enabled || !ctl_has_mute(kcontrol))) { if (chs & 1) ucontrol->value.integer.value[0] = beep->enabled; if (chs & 2) ucontrol->value.integer.value[1] = beep->enabled; return 0; } return snd_hda_mixer_amp_switch_get(kcontrol, ucontrol); } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_get_beep); /** * snd_hda_mixer_amp_switch_put_beep - Put callback for beep controls * @kcontrol: ctl element * @ucontrol: pointer to get/store the data */ int snd_hda_mixer_amp_switch_put_beep(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct hda_beep *beep = codec->beep; if (beep) { u8 chs = get_amp_channels(kcontrol); int enable = 0; long *valp = ucontrol->value.integer.value; if (chs & 1) { enable |= *valp; valp++; } if (chs & 2) enable |= *valp; snd_hda_enable_beep_device(codec, enable); } if (!ctl_has_mute(kcontrol)) return 0; return snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); } EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_put_beep);
linux-master
sound/pci/hda/hda_beep.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Jack-detection handling for HD-audio * * Copyright (c) 2011 Takashi Iwai <[email protected]> */ #include <linux/init.h> #include <linux/slab.h> #include <linux/export.h> #include <sound/core.h> #include <sound/control.h> #include <sound/jack.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_auto_parser.h" #include "hda_jack.h" /** * is_jack_detectable - Check whether the given pin is jack-detectable * @codec: the HDA codec * @nid: pin NID * * Check whether the given pin is capable to report the jack detection. * The jack detection might not work by various reasons, e.g. the jack * detection is prohibited in the codec level, the pin config has * AC_DEFCFG_MISC_NO_PRESENCE bit, no unsol support, etc. */ bool is_jack_detectable(struct hda_codec *codec, hda_nid_t nid) { if (codec->no_jack_detect) return false; if (!(snd_hda_query_pin_caps(codec, nid) & AC_PINCAP_PRES_DETECT)) return false; if (get_defcfg_misc(snd_hda_codec_get_pincfg(codec, nid)) & AC_DEFCFG_MISC_NO_PRESENCE) return false; if (!(get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP) && !codec->jackpoll_interval) return false; return true; } EXPORT_SYMBOL_GPL(is_jack_detectable); /* execute pin sense measurement */ static u32 read_pin_sense(struct hda_codec *codec, hda_nid_t nid, int dev_id) { u32 pincap; u32 val; if (!codec->no_trigger_sense) { pincap = snd_hda_query_pin_caps(codec, nid); if (pincap & AC_PINCAP_TRIG_REQ) /* need trigger? */ snd_hda_codec_read(codec, nid, 0, AC_VERB_SET_PIN_SENSE, 0); } val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_SENSE, dev_id); if (codec->inv_jack_detect) val ^= AC_PINSENSE_PRESENCE; return val; } /** * snd_hda_jack_tbl_get_mst - query the jack-table entry for the given NID * @codec: the HDA codec * @nid: pin NID to refer to * @dev_id: pin device entry id */ struct hda_jack_tbl * snd_hda_jack_tbl_get_mst(struct hda_codec *codec, hda_nid_t nid, int dev_id) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; if (!nid || !jack) return NULL; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->nid == nid && jack->dev_id == dev_id) return jack; return NULL; } EXPORT_SYMBOL_GPL(snd_hda_jack_tbl_get_mst); /** * snd_hda_jack_tbl_get_from_tag - query the jack-table entry for the given tag * @codec: the HDA codec * @tag: tag value to refer to * @dev_id: pin device entry id */ struct hda_jack_tbl * snd_hda_jack_tbl_get_from_tag(struct hda_codec *codec, unsigned char tag, int dev_id) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; if (!tag || !jack) return NULL; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->tag == tag && jack->dev_id == dev_id) return jack; return NULL; } EXPORT_SYMBOL_GPL(snd_hda_jack_tbl_get_from_tag); static struct hda_jack_tbl * any_jack_tbl_get_from_nid(struct hda_codec *codec, hda_nid_t nid) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; if (!nid || !jack) return NULL; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->nid == nid) return jack; return NULL; } /** * snd_hda_jack_tbl_new - create a jack-table entry for the given NID * @codec: the HDA codec * @nid: pin NID to assign * @dev_id: pin device entry id */ static struct hda_jack_tbl * snd_hda_jack_tbl_new(struct hda_codec *codec, hda_nid_t nid, int dev_id) { struct hda_jack_tbl *jack = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); struct hda_jack_tbl *existing_nid_jack = any_jack_tbl_get_from_nid(codec, nid); WARN_ON(dev_id != 0 && !codec->dp_mst); if (jack) return jack; jack = snd_array_new(&codec->jacktbl); if (!jack) return NULL; jack->nid = nid; jack->dev_id = dev_id; jack->jack_dirty = 1; if (existing_nid_jack) { jack->tag = existing_nid_jack->tag; /* * Copy jack_detect from existing_nid_jack to avoid * snd_hda_jack_detect_enable_callback_mst() making multiple * SET_UNSOLICITED_ENABLE calls on the same pin. */ jack->jack_detect = existing_nid_jack->jack_detect; } else { jack->tag = codec->jacktbl.used; } return jack; } void snd_hda_jack_tbl_disconnect(struct hda_codec *codec) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; for (i = 0; i < codec->jacktbl.used; i++, jack++) { if (!codec->bus->shutdown && jack->jack) snd_device_disconnect(codec->card, jack->jack); } } void snd_hda_jack_tbl_clear(struct hda_codec *codec) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; for (i = 0; i < codec->jacktbl.used; i++, jack++) { struct hda_jack_callback *cb, *next; /* free jack instances manually when clearing/reconfiguring */ if (!codec->bus->shutdown && jack->jack) snd_device_free(codec->card, jack->jack); for (cb = jack->callback; cb; cb = next) { next = cb->next; kfree(cb); } } snd_array_free(&codec->jacktbl); } #define get_jack_plug_state(sense) !!(sense & AC_PINSENSE_PRESENCE) /* update the cached value and notification flag if needed */ static void jack_detect_update(struct hda_codec *codec, struct hda_jack_tbl *jack) { if (!jack->jack_dirty) return; if (jack->phantom_jack) jack->pin_sense = AC_PINSENSE_PRESENCE; else jack->pin_sense = read_pin_sense(codec, jack->nid, jack->dev_id); /* A gating jack indicates the jack is invalid if gating is unplugged */ if (jack->gating_jack && !snd_hda_jack_detect_mst(codec, jack->gating_jack, jack->dev_id)) jack->pin_sense &= ~AC_PINSENSE_PRESENCE; jack->jack_dirty = 0; /* If a jack is gated by this one update it. */ if (jack->gated_jack) { struct hda_jack_tbl *gated = snd_hda_jack_tbl_get_mst(codec, jack->gated_jack, jack->dev_id); if (gated) { gated->jack_dirty = 1; jack_detect_update(codec, gated); } } } /** * snd_hda_jack_set_dirty_all - Mark all the cached as dirty * @codec: the HDA codec * * This function sets the dirty flag to all entries of jack table. * It's called from the resume path in hda_codec.c. */ void snd_hda_jack_set_dirty_all(struct hda_codec *codec) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->nid) jack->jack_dirty = 1; } EXPORT_SYMBOL_GPL(snd_hda_jack_set_dirty_all); /** * snd_hda_jack_pin_sense - execute pin sense measurement * @codec: the CODEC to sense * @nid: the pin NID to sense * @dev_id: pin device entry id * * Execute necessary pin sense measurement and return its Presence Detect, * Impedance, ELD Valid etc. status bits. */ u32 snd_hda_jack_pin_sense(struct hda_codec *codec, hda_nid_t nid, int dev_id) { struct hda_jack_tbl *jack = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); if (jack) { jack_detect_update(codec, jack); return jack->pin_sense; } return read_pin_sense(codec, nid, dev_id); } EXPORT_SYMBOL_GPL(snd_hda_jack_pin_sense); /** * snd_hda_jack_detect_state_mst - query pin Presence Detect status * @codec: the CODEC to sense * @nid: the pin NID to sense * @dev_id: pin device entry id * * Query and return the pin's Presence Detect status, as either * HDA_JACK_NOT_PRESENT, HDA_JACK_PRESENT or HDA_JACK_PHANTOM. */ int snd_hda_jack_detect_state_mst(struct hda_codec *codec, hda_nid_t nid, int dev_id) { struct hda_jack_tbl *jack = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); if (jack && jack->phantom_jack) return HDA_JACK_PHANTOM; else if (snd_hda_jack_pin_sense(codec, nid, dev_id) & AC_PINSENSE_PRESENCE) return HDA_JACK_PRESENT; else return HDA_JACK_NOT_PRESENT; } EXPORT_SYMBOL_GPL(snd_hda_jack_detect_state_mst); static struct hda_jack_callback * find_callback_from_list(struct hda_jack_tbl *jack, hda_jack_callback_fn func) { struct hda_jack_callback *cb; if (!func) return NULL; for (cb = jack->callback; cb; cb = cb->next) { if (cb->func == func) return cb; } return NULL; } /** * snd_hda_jack_detect_enable_callback_mst - enable the jack-detection * @codec: the HDA codec * @nid: pin NID to enable * @func: callback function to register * @dev_id: pin device entry id * * In the case of error, the return value will be a pointer embedded with * errno. Check and handle the return value appropriately with standard * macros such as @IS_ERR() and @PTR_ERR(). */ struct hda_jack_callback * snd_hda_jack_detect_enable_callback_mst(struct hda_codec *codec, hda_nid_t nid, int dev_id, hda_jack_callback_fn func) { struct hda_jack_tbl *jack; struct hda_jack_callback *callback = NULL; int err; jack = snd_hda_jack_tbl_new(codec, nid, dev_id); if (!jack) return ERR_PTR(-ENOMEM); callback = find_callback_from_list(jack, func); if (func && !callback) { callback = kzalloc(sizeof(*callback), GFP_KERNEL); if (!callback) return ERR_PTR(-ENOMEM); callback->func = func; callback->nid = jack->nid; callback->dev_id = jack->dev_id; callback->next = jack->callback; jack->callback = callback; } if (jack->jack_detect) return callback; /* already registered */ jack->jack_detect = 1; if (codec->jackpoll_interval > 0) return callback; /* No unsol if we're polling instead */ err = snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | jack->tag); if (err < 0) return ERR_PTR(err); return callback; } EXPORT_SYMBOL_GPL(snd_hda_jack_detect_enable_callback_mst); /** * snd_hda_jack_detect_enable - Enable the jack detection on the given pin * @codec: the HDA codec * @nid: pin NID to enable jack detection * @dev_id: pin device entry id * * Enable the jack detection with the default callback. Returns zero if * successful or a negative error code. */ int snd_hda_jack_detect_enable(struct hda_codec *codec, hda_nid_t nid, int dev_id) { return PTR_ERR_OR_ZERO(snd_hda_jack_detect_enable_callback_mst(codec, nid, dev_id, NULL)); } EXPORT_SYMBOL_GPL(snd_hda_jack_detect_enable); /** * snd_hda_jack_set_gating_jack - Set gating jack. * @codec: the HDA codec * @gated_nid: gated pin NID * @gating_nid: gating pin NID * * Indicates the gated jack is only valid when the gating jack is plugged. */ int snd_hda_jack_set_gating_jack(struct hda_codec *codec, hda_nid_t gated_nid, hda_nid_t gating_nid) { struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); struct hda_jack_tbl *gating = snd_hda_jack_tbl_new(codec, gating_nid, 0); WARN_ON(codec->dp_mst); if (!gated || !gating) return -EINVAL; gated->gating_jack = gating_nid; gating->gated_jack = gated_nid; return 0; } EXPORT_SYMBOL_GPL(snd_hda_jack_set_gating_jack); /** * snd_hda_jack_bind_keymap - bind keys generated from one NID to another jack. * @codec: the HDA codec * @key_nid: key event is generated by this pin NID * @keymap: map of key type and key code * @jack_nid: key reports to the jack of this pin NID * * This function is used in the case of key is generated from one NID while is * reported to the jack of another NID. */ int snd_hda_jack_bind_keymap(struct hda_codec *codec, hda_nid_t key_nid, const struct hda_jack_keymap *keymap, hda_nid_t jack_nid) { const struct hda_jack_keymap *map; struct hda_jack_tbl *key_gen = snd_hda_jack_tbl_get(codec, key_nid); struct hda_jack_tbl *report_to = snd_hda_jack_tbl_get(codec, jack_nid); WARN_ON(codec->dp_mst); if (!key_gen || !report_to || !report_to->jack) return -EINVAL; key_gen->key_report_jack = jack_nid; if (keymap) for (map = keymap; map->type; map++) snd_jack_set_key(report_to->jack, map->type, map->key); return 0; } EXPORT_SYMBOL_GPL(snd_hda_jack_bind_keymap); /** * snd_hda_jack_set_button_state - report button event to the hda_jack_tbl button_state. * @codec: the HDA codec * @jack_nid: the button event reports to the jack_tbl of this NID * @button_state: the button event captured by codec * * Codec driver calls this function to report the button event. */ void snd_hda_jack_set_button_state(struct hda_codec *codec, hda_nid_t jack_nid, int button_state) { struct hda_jack_tbl *jack = snd_hda_jack_tbl_get(codec, jack_nid); if (!jack) return; if (jack->key_report_jack) { struct hda_jack_tbl *report_to = snd_hda_jack_tbl_get(codec, jack->key_report_jack); if (report_to) { report_to->button_state = button_state; return; } } jack->button_state = button_state; } EXPORT_SYMBOL_GPL(snd_hda_jack_set_button_state); /** * snd_hda_jack_report_sync - sync the states of all jacks and report if changed * @codec: the HDA codec */ void snd_hda_jack_report_sync(struct hda_codec *codec) { struct hda_jack_tbl *jack; int i, state; /* update all jacks at first */ jack = codec->jacktbl.list; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->nid) jack_detect_update(codec, jack); /* report the updated jacks; it's done after updating all jacks * to make sure that all gating jacks properly have been set */ jack = codec->jacktbl.list; for (i = 0; i < codec->jacktbl.used; i++, jack++) if (jack->nid) { if (!jack->jack || jack->block_report) continue; state = jack->button_state; if (get_jack_plug_state(jack->pin_sense)) state |= jack->type; snd_jack_report(jack->jack, state); if (jack->button_state) { snd_jack_report(jack->jack, state & ~jack->button_state); jack->button_state = 0; /* button released */ } } } EXPORT_SYMBOL_GPL(snd_hda_jack_report_sync); /* guess the jack type from the pin-config */ static int get_input_jack_type(struct hda_codec *codec, hda_nid_t nid) { unsigned int def_conf = snd_hda_codec_get_pincfg(codec, nid); switch (get_defcfg_device(def_conf)) { case AC_JACK_LINE_OUT: case AC_JACK_SPEAKER: return SND_JACK_LINEOUT; case AC_JACK_HP_OUT: return SND_JACK_HEADPHONE; case AC_JACK_SPDIF_OUT: case AC_JACK_DIG_OTHER_OUT: return SND_JACK_AVOUT; case AC_JACK_MIC_IN: return SND_JACK_MICROPHONE; default: return SND_JACK_LINEIN; } } static void hda_free_jack_priv(struct snd_jack *jack) { struct hda_jack_tbl *jacks = jack->private_data; jacks->nid = 0; jacks->jack = NULL; } /** * snd_hda_jack_add_kctl_mst - Add a kctl for the given pin * @codec: the HDA codec * @nid: pin NID to assign * @dev_id : pin device entry id * @name: string name for the jack * @phantom_jack: flag to deal as a phantom jack * @type: jack type bits to be reported, 0 for guessing from pincfg * @keymap: optional jack / key mapping * * This assigns a jack-detection kctl to the given pin. The kcontrol * will have the given name and index. */ int snd_hda_jack_add_kctl_mst(struct hda_codec *codec, hda_nid_t nid, int dev_id, const char *name, bool phantom_jack, int type, const struct hda_jack_keymap *keymap) { struct hda_jack_tbl *jack; const struct hda_jack_keymap *map; int err, state, buttons; jack = snd_hda_jack_tbl_new(codec, nid, dev_id); if (!jack) return 0; if (jack->jack) return 0; /* already created */ if (!type) type = get_input_jack_type(codec, nid); buttons = 0; if (keymap) { for (map = keymap; map->type; map++) buttons |= map->type; } err = snd_jack_new(codec->card, name, type | buttons, &jack->jack, true, phantom_jack); if (err < 0) return err; jack->phantom_jack = !!phantom_jack; jack->type = type; jack->button_state = 0; jack->jack->private_data = jack; jack->jack->private_free = hda_free_jack_priv; if (keymap) { for (map = keymap; map->type; map++) snd_jack_set_key(jack->jack, map->type, map->key); } state = snd_hda_jack_detect_mst(codec, nid, dev_id); snd_jack_report(jack->jack, state ? jack->type : 0); return 0; } EXPORT_SYMBOL_GPL(snd_hda_jack_add_kctl_mst); static int add_jack_kctl(struct hda_codec *codec, hda_nid_t nid, const struct auto_pin_cfg *cfg, const char *base_name) { unsigned int def_conf, conn; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; int err; bool phantom_jack; WARN_ON(codec->dp_mst); if (!nid) return 0; def_conf = snd_hda_codec_get_pincfg(codec, nid); conn = get_defcfg_connect(def_conf); if (conn == AC_JACK_PORT_NONE) return 0; phantom_jack = (conn != AC_JACK_PORT_COMPLEX) || !is_jack_detectable(codec, nid); if (base_name) strscpy(name, base_name, sizeof(name)); else snd_hda_get_pin_label(codec, nid, cfg, name, sizeof(name), NULL); if (phantom_jack) /* Example final name: "Internal Mic Phantom Jack" */ strncat(name, " Phantom", sizeof(name) - strlen(name) - 1); err = snd_hda_jack_add_kctl(codec, nid, name, phantom_jack, 0, NULL); if (err < 0) return err; if (!phantom_jack) return snd_hda_jack_detect_enable(codec, nid, 0); return 0; } /** * snd_hda_jack_add_kctls - Add kctls for all pins included in the given pincfg * @codec: the HDA codec * @cfg: pin config table to parse */ int snd_hda_jack_add_kctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg) { const hda_nid_t *p; int i, err; for (i = 0; i < cfg->num_inputs; i++) { /* If we have headphone mics; make sure they get the right name before grabbed by output pins */ if (cfg->inputs[i].is_headphone_mic) { if (auto_cfg_hp_outs(cfg) == 1) err = add_jack_kctl(codec, auto_cfg_hp_pins(cfg)[0], cfg, "Headphone Mic"); else err = add_jack_kctl(codec, cfg->inputs[i].pin, cfg, "Headphone Mic"); } else err = add_jack_kctl(codec, cfg->inputs[i].pin, cfg, NULL); if (err < 0) return err; } for (i = 0, p = cfg->line_out_pins; i < cfg->line_outs; i++, p++) { err = add_jack_kctl(codec, *p, cfg, NULL); if (err < 0) return err; } for (i = 0, p = cfg->hp_pins; i < cfg->hp_outs; i++, p++) { if (*p == *cfg->line_out_pins) /* might be duplicated */ break; err = add_jack_kctl(codec, *p, cfg, NULL); if (err < 0) return err; } for (i = 0, p = cfg->speaker_pins; i < cfg->speaker_outs; i++, p++) { if (*p == *cfg->line_out_pins) /* might be duplicated */ break; err = add_jack_kctl(codec, *p, cfg, NULL); if (err < 0) return err; } for (i = 0, p = cfg->dig_out_pins; i < cfg->dig_outs; i++, p++) { err = add_jack_kctl(codec, *p, cfg, NULL); if (err < 0) return err; } err = add_jack_kctl(codec, cfg->dig_in_pin, cfg, NULL); if (err < 0) return err; err = add_jack_kctl(codec, cfg->mono_out_pin, cfg, NULL); if (err < 0) return err; return 0; } EXPORT_SYMBOL_GPL(snd_hda_jack_add_kctls); static void call_jack_callback(struct hda_codec *codec, unsigned int res, struct hda_jack_tbl *jack) { struct hda_jack_callback *cb; for (cb = jack->callback; cb; cb = cb->next) { cb->jack = jack; cb->unsol_res = res; cb->func(codec, cb); } if (jack->gated_jack) { struct hda_jack_tbl *gated = snd_hda_jack_tbl_get_mst(codec, jack->gated_jack, jack->dev_id); if (gated) { for (cb = gated->callback; cb; cb = cb->next) { cb->jack = gated; cb->unsol_res = res; cb->func(codec, cb); } } } } /** * snd_hda_jack_unsol_event - Handle an unsolicited event * @codec: the HDA codec * @res: the unsolicited event data */ void snd_hda_jack_unsol_event(struct hda_codec *codec, unsigned int res) { struct hda_jack_tbl *event; int tag = (res & AC_UNSOL_RES_TAG) >> AC_UNSOL_RES_TAG_SHIFT; if (codec->dp_mst) { int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; event = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); } else { event = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); } if (!event) return; if (event->key_report_jack) { struct hda_jack_tbl *report_to = snd_hda_jack_tbl_get_mst(codec, event->key_report_jack, event->dev_id); if (report_to) report_to->jack_dirty = 1; } else event->jack_dirty = 1; call_jack_callback(codec, res, event); snd_hda_jack_report_sync(codec); } EXPORT_SYMBOL_GPL(snd_hda_jack_unsol_event); /** * snd_hda_jack_poll_all - Poll all jacks * @codec: the HDA codec * * Poll all detectable jacks with dirty flag, update the status, call * callbacks and call snd_hda_jack_report_sync() if any changes are found. */ void snd_hda_jack_poll_all(struct hda_codec *codec) { struct hda_jack_tbl *jack = codec->jacktbl.list; int i, changes = 0; for (i = 0; i < codec->jacktbl.used; i++, jack++) { unsigned int old_sense; if (!jack->nid || !jack->jack_dirty || jack->phantom_jack) continue; old_sense = get_jack_plug_state(jack->pin_sense); jack_detect_update(codec, jack); if (old_sense == get_jack_plug_state(jack->pin_sense)) continue; changes = 1; call_jack_callback(codec, 0, jack); } if (changes) snd_hda_jack_report_sync(codec); } EXPORT_SYMBOL_GPL(snd_hda_jack_poll_all);
linux-master
sound/pci/hda/hda_jack.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * * patch_hdmi.c - routines for HDMI/DisplayPort codecs * * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. * Copyright (c) 2006 ATI Technologies Inc. * Copyright (c) 2008 NVIDIA Corp. All rights reserved. * Copyright (c) 2008 Wei Ni <[email protected]> * Copyright (c) 2013 Anssi Hannula <[email protected]> * * Authors: * Wu Fengguang <[email protected]> * * Maintained by: * Wu Fengguang <[email protected]> */ #include <linux/init.h> #include <linux/delay.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/pm_runtime.h> #include <sound/core.h> #include <sound/jack.h> #include <sound/asoundef.h> #include <sound/tlv.h> #include <sound/hdaudio.h> #include <sound/hda_i915.h> #include <sound/hda_chmap.h> #include <sound/hda_codec.h> #include "hda_local.h" #include "hda_jack.h" #include "hda_controller.h" static bool static_hdmi_pcm; module_param(static_hdmi_pcm, bool, 0644); MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); static bool enable_acomp = true; module_param(enable_acomp, bool, 0444); MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); static bool enable_silent_stream = IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); module_param(enable_silent_stream, bool, 0644); MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); static bool enable_all_pins; module_param(enable_all_pins, bool, 0444); MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); struct hdmi_spec_per_cvt { hda_nid_t cvt_nid; bool assigned; /* the stream has been assigned */ bool silent_stream; /* silent stream activated */ unsigned int channels_min; unsigned int channels_max; u32 rates; u64 formats; unsigned int maxbps; }; /* max. connections to a widget */ #define HDA_MAX_CONNECTIONS 32 struct hdmi_spec_per_pin { hda_nid_t pin_nid; int dev_id; /* pin idx, different device entries on the same pin use the same idx */ int pin_nid_idx; int num_mux_nids; hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; int mux_idx; hda_nid_t cvt_nid; struct hda_codec *codec; struct hdmi_eld sink_eld; struct mutex lock; struct delayed_work work; struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ int prev_pcm_idx; /* previously assigned pcm index */ int repoll_count; bool setup; /* the stream has been set up by prepare callback */ bool silent_stream; int channels; /* current number of channels */ bool non_pcm; bool chmap_set; /* channel-map override by ALSA API? */ unsigned char chmap[8]; /* ALSA API channel-map */ #ifdef CONFIG_SND_PROC_FS struct snd_info_entry *proc_entry; #endif }; /* operations used by generic code that can be overridden by patches */ struct hdmi_ops { int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, unsigned char *buf, int *eld_size); void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, int ca, int active_channels, int conn_type); /* enable/disable HBR (HD passthrough) */ int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, bool hbr); int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t pin_nid, int dev_id, u32 stream_tag, int format); void (*pin_cvt_fixup)(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid); }; struct hdmi_pcm { struct hda_pcm *pcm; struct snd_jack *jack; struct snd_kcontrol *eld_ctl; }; enum { SILENT_STREAM_OFF = 0, SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ SILENT_STREAM_I915, /* Intel i915 extension */ }; struct hdmi_spec { struct hda_codec *codec; int num_cvts; struct snd_array cvts; /* struct hdmi_spec_per_cvt */ hda_nid_t cvt_nids[4]; /* only for haswell fix */ /* * num_pins is the number of virtual pins * for example, there are 3 pins, and each pin * has 4 device entries, then the num_pins is 12 */ int num_pins; /* * num_nids is the number of real pins * In the above example, num_nids is 3 */ int num_nids; /* * dev_num is the number of device entries * on each pin. * In the above example, dev_num is 4 */ int dev_num; struct snd_array pins; /* struct hdmi_spec_per_pin */ struct hdmi_pcm pcm_rec[8]; struct mutex pcm_lock; struct mutex bind_lock; /* for audio component binding */ /* pcm_bitmap means which pcms have been assigned to pins*/ unsigned long pcm_bitmap; int pcm_used; /* counter of pcm_rec[] */ /* bitmap shows whether the pcm is opened in user space * bit 0 means the first playback PCM (PCM3); * bit 1 means the second playback PCM, and so on. */ unsigned long pcm_in_use; struct hdmi_eld temp_eld; struct hdmi_ops ops; bool dyn_pin_out; bool static_pcm_mapping; /* hdmi interrupt trigger control flag for Nvidia codec */ bool hdmi_intr_trig_ctrl; bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ /* * Non-generic VIA/NVIDIA specific */ struct hda_multi_out multiout; struct hda_pcm_stream pcm_playback; bool use_acomp_notifier; /* use eld_notify callback for hotplug */ bool acomp_registered; /* audio component registered in this driver */ bool force_connect; /* force connectivity */ struct drm_audio_component_audio_ops drm_audio_ops; int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ struct hdac_chmap chmap; hda_nid_t vendor_nid; const int *port_map; int port_num; int silent_stream_type; }; #ifdef CONFIG_SND_HDA_COMPONENT static inline bool codec_has_acomp(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; return spec->use_acomp_notifier; } #else #define codec_has_acomp(codec) false #endif struct hdmi_audio_infoframe { u8 type; /* 0x84 */ u8 ver; /* 0x01 */ u8 len; /* 0x0a */ u8 checksum; u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ u8 SS01_SF24; u8 CXT04; u8 CA; u8 LFEPBL01_LSV36_DM_INH7; }; struct dp_audio_infoframe { u8 type; /* 0x84 */ u8 len; /* 0x1b */ u8 ver; /* 0x11 << 2 */ u8 CC02_CT47; /* match with HDMI infoframe from this on */ u8 SS01_SF24; u8 CXT04; u8 CA; u8 LFEPBL01_LSV36_DM_INH7; }; union audio_infoframe { struct hdmi_audio_infoframe hdmi; struct dp_audio_infoframe dp; DECLARE_FLEX_ARRAY(u8, bytes); }; /* * HDMI routines */ #define get_pin(spec, idx) \ ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) #define get_cvt(spec, idx) \ ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) /* obtain hdmi_pcm object assigned to idx */ #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) /* obtain hda_pcm object assigned to idx */ #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) static int pin_id_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id) { struct hdmi_spec *spec = codec->spec; int pin_idx; struct hdmi_spec_per_pin *per_pin; /* * (dev_id == -1) means it is NON-MST pin * return the first virtual pin on this port */ if (dev_id == -1) dev_id = 0; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { per_pin = get_pin(spec, pin_idx); if ((per_pin->pin_nid == pin_nid) && (per_pin->dev_id == dev_id)) return pin_idx; } codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); return -EINVAL; } static int hinfo_to_pcm_index(struct hda_codec *codec, struct hda_pcm_stream *hinfo) { struct hdmi_spec *spec = codec->spec; int pcm_idx; for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) return pcm_idx; codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); return -EINVAL; } static int hinfo_to_pin_index(struct hda_codec *codec, struct hda_pcm_stream *hinfo) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin; int pin_idx; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { per_pin = get_pin(spec, pin_idx); if (per_pin->pcm && per_pin->pcm->pcm->stream == hinfo) return pin_idx; } codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, hinfo_to_pcm_index(codec, hinfo)); return -EINVAL; } static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, int pcm_idx) { int i; struct hdmi_spec_per_pin *per_pin; for (i = 0; i < spec->num_pins; i++) { per_pin = get_pin(spec, i); if (per_pin->pcm_idx == pcm_idx) return per_pin; } return NULL; } static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) { struct hdmi_spec *spec = codec->spec; int cvt_idx; for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) return cvt_idx; codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); return -EINVAL; } static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin; struct hdmi_eld *eld; int pcm_idx; uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; pcm_idx = kcontrol->private_value; mutex_lock(&spec->pcm_lock); per_pin = pcm_idx_to_pin(spec, pcm_idx); if (!per_pin) { /* no pin is bound to the pcm */ uinfo->count = 0; goto unlock; } eld = &per_pin->sink_eld; uinfo->count = eld->eld_valid ? eld->eld_size : 0; unlock: mutex_unlock(&spec->pcm_lock); return 0; } static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin; struct hdmi_eld *eld; int pcm_idx; int err = 0; pcm_idx = kcontrol->private_value; mutex_lock(&spec->pcm_lock); per_pin = pcm_idx_to_pin(spec, pcm_idx); if (!per_pin) { /* no pin is bound to the pcm */ memset(ucontrol->value.bytes.data, 0, ARRAY_SIZE(ucontrol->value.bytes.data)); goto unlock; } eld = &per_pin->sink_eld; if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || eld->eld_size > ELD_MAX_SIZE) { snd_BUG(); err = -EINVAL; goto unlock; } memset(ucontrol->value.bytes.data, 0, ARRAY_SIZE(ucontrol->value.bytes.data)); if (eld->eld_valid) memcpy(ucontrol->value.bytes.data, eld->eld_buffer, eld->eld_size); unlock: mutex_unlock(&spec->pcm_lock); return err; } static const struct snd_kcontrol_new eld_bytes_ctl = { .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = "ELD", .info = hdmi_eld_ctl_info, .get = hdmi_eld_ctl_get, }; static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, int device) { struct snd_kcontrol *kctl; struct hdmi_spec *spec = codec->spec; int err; kctl = snd_ctl_new1(&eld_bytes_ctl, codec); if (!kctl) return -ENOMEM; kctl->private_value = pcm_idx; kctl->id.device = device; /* no pin nid is associated with the kctl now * tbd: associate pin nid to eld ctl later */ err = snd_hda_ctl_add(codec, 0, kctl); if (err < 0) return err; get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; return 0; } #ifdef BE_PARANOID static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, int *packet_index, int *byte_index) { int val; val = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_INDEX, 0); *packet_index = val >> 5; *byte_index = val & 0x1f; } #endif static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, int packet_index, int byte_index) { int val; val = (packet_index << 5) | (byte_index & 0x1f); snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); } static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, unsigned char val) { snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); } static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) { struct hdmi_spec *spec = codec->spec; int pin_out; /* Unmute */ if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); if (spec->dyn_pin_out) /* Disable pin out until stream is active */ pin_out = 0; else /* Enable pin out: some machines with GM965 gets broken output * when the pin is disabled or changed while using with HDMI */ pin_out = PIN_OUT; snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); } /* * ELD proc files */ #ifdef CONFIG_SND_PROC_FS static void print_eld_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct hdmi_spec_per_pin *per_pin = entry->private_data; mutex_lock(&per_pin->lock); snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, per_pin->dev_id, per_pin->cvt_nid); mutex_unlock(&per_pin->lock); } static void write_eld_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { struct hdmi_spec_per_pin *per_pin = entry->private_data; mutex_lock(&per_pin->lock); snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); mutex_unlock(&per_pin->lock); } static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) { char name[32]; struct hda_codec *codec = per_pin->codec; struct snd_info_entry *entry; int err; snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); err = snd_card_proc_new(codec->card, name, &entry); if (err < 0) return err; snd_info_set_text_ops(entry, per_pin, print_eld_info); entry->c.text.write = write_eld_info; entry->mode |= 0200; per_pin->proc_entry = entry; return 0; } static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) { if (!per_pin->codec->bus->shutdown) { snd_info_free_entry(per_pin->proc_entry); per_pin->proc_entry = NULL; } } #else static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) { return 0; } static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) { } #endif /* * Audio InfoFrame routines */ /* * Enable Audio InfoFrame Transmission */ static void hdmi_start_infoframe_trans(struct hda_codec *codec, hda_nid_t pin_nid) { hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, AC_DIPXMIT_BEST); } /* * Disable Audio InfoFrame Transmission */ static void hdmi_stop_infoframe_trans(struct hda_codec *codec, hda_nid_t pin_nid) { hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, AC_DIPXMIT_DISABLE); } static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) { #ifdef CONFIG_SND_DEBUG_VERBOSE int i; int size; size = snd_hdmi_get_eld_size(codec, pin_nid); codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); for (i = 0; i < 8; i++) { size = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_SIZE, i); codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); } #endif } static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) { #ifdef BE_PARANOID int i, j; int size; int pi, bi; for (i = 0; i < 8; i++) { size = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_SIZE, i); if (size == 0) continue; hdmi_set_dip_index(codec, pin_nid, i, 0x0); for (j = 1; j < 1000; j++) { hdmi_write_dip_byte(codec, pin_nid, 0x0); hdmi_get_dip_index(codec, pin_nid, &pi, &bi); if (pi != i) codec_dbg(codec, "dip index %d: %d != %d\n", bi, pi, i); if (bi == 0) /* byte index wrapped around */ break; } codec_dbg(codec, "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", i, size, j); } #endif } static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) { u8 *bytes = (u8 *)hdmi_ai; u8 sum = 0; int i; hdmi_ai->checksum = 0; for (i = 0; i < sizeof(*hdmi_ai); i++) sum += bytes[i]; hdmi_ai->checksum = -sum; } static void hdmi_fill_audio_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, u8 *dip, int size) { int i; hdmi_debug_dip_size(codec, pin_nid); hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); for (i = 0; i < size; i++) hdmi_write_dip_byte(codec, pin_nid, dip[i]); } static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, u8 *dip, int size) { u8 val; int i; hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) != AC_DIPXMIT_BEST) return false; for (i = 0; i < size; i++) { val = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_DATA, 0); if (val != dip[i]) return false; } return true; } static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, int dev_id, unsigned char *buf, int *eld_size) { snd_hda_set_dev_select(codec, nid, dev_id); return snd_hdmi_get_eld(codec, nid, buf, eld_size); } static void hdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, int ca, int active_channels, int conn_type) { struct hdmi_spec *spec = codec->spec; union audio_infoframe ai; memset(&ai, 0, sizeof(ai)); if ((conn_type == 0) || /* HDMI */ /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ (conn_type == 1 && spec->nv_dp_workaround)) { struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; if (conn_type == 0) { /* HDMI */ hdmi_ai->type = 0x84; hdmi_ai->ver = 0x01; hdmi_ai->len = 0x0a; } else {/* Nvidia DP */ hdmi_ai->type = 0x84; hdmi_ai->ver = 0x1b; hdmi_ai->len = 0x11 << 2; } hdmi_ai->CC02_CT47 = active_channels - 1; hdmi_ai->CA = ca; hdmi_checksum_audio_infoframe(hdmi_ai); } else if (conn_type == 1) { /* DisplayPort */ struct dp_audio_infoframe *dp_ai = &ai.dp; dp_ai->type = 0x84; dp_ai->len = 0x1b; dp_ai->ver = 0x11 << 2; dp_ai->CC02_CT47 = active_channels - 1; dp_ai->CA = ca; } else { codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); return; } snd_hda_set_dev_select(codec, pin_nid, dev_id); /* * sizeof(ai) is used instead of sizeof(*hdmi_ai) or * sizeof(*dp_ai) to avoid partial match/update problems when * the user switches between HDMI/DP monitors. */ if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, sizeof(ai))) { codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", __func__, pin_nid, active_channels, ca); hdmi_stop_infoframe_trans(codec, pin_nid); hdmi_fill_audio_infoframe(codec, pin_nid, ai.bytes, sizeof(ai)); hdmi_start_infoframe_trans(codec, pin_nid); } } static void hdmi_setup_audio_infoframe(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, bool non_pcm) { struct hdmi_spec *spec = codec->spec; struct hdac_chmap *chmap = &spec->chmap; hda_nid_t pin_nid = per_pin->pin_nid; int dev_id = per_pin->dev_id; int channels = per_pin->channels; int active_channels; struct hdmi_eld *eld; int ca; if (!channels) return; snd_hda_set_dev_select(codec, pin_nid, dev_id); /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); eld = &per_pin->sink_eld; ca = snd_hdac_channel_allocation(&codec->core, eld->info.spk_alloc, channels, per_pin->chmap_set, non_pcm, per_pin->chmap); active_channels = snd_hdac_get_active_channels(ca); chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, active_channels); /* * always configure channel mapping, it may have been changed by the * user in the meantime */ snd_hdac_setup_channel_mapping(&spec->chmap, pin_nid, non_pcm, ca, channels, per_pin->chmap, per_pin->chmap_set); spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, ca, active_channels, eld->info.conn_type); per_pin->non_pcm = non_pcm; } /* * Unsolicited events */ static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, int dev_id) { struct hdmi_spec *spec = codec->spec; int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); if (pin_idx < 0) return; mutex_lock(&spec->pcm_lock); hdmi_present_sense(get_pin(spec, pin_idx), 1); mutex_unlock(&spec->pcm_lock); } static void jack_callback(struct hda_codec *codec, struct hda_jack_callback *jack) { /* stop polling when notification is enabled */ if (codec_has_acomp(codec)) return; check_presence_and_report(codec, jack->nid, jack->dev_id); } static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, struct hda_jack_tbl *jack) { jack->jack_dirty = 1; codec_dbg(codec, "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); check_presence_and_report(codec, jack->nid, jack->dev_id); } static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) { int tag = res >> AC_UNSOL_RES_TAG_SHIFT; int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); codec_info(codec, "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", codec->addr, tag, subtag, cp_state, cp_ready); /* TODO */ if (cp_state) { ; } if (cp_ready) { ; } } static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) { int tag = res >> AC_UNSOL_RES_TAG_SHIFT; int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; struct hda_jack_tbl *jack; if (codec_has_acomp(codec)) return; if (codec->dp_mst) { int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); } else { jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); } if (!jack) { codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); return; } if (subtag == 0) hdmi_intrinsic_event(codec, res, jack); else hdmi_non_intrinsic_event(codec, res); } static void haswell_verify_D0(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t nid) { int pwr; /* For Haswell, the converter 1/2 may keep in D3 state after bootup, * thus pins could only choose converter 0 for use. Make sure the * converters are in correct power state */ if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); msleep(40); pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); } } /* * Callbacks */ /* HBR should be Non-PCM, 8 channels */ #define is_hbr_format(format) \ ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, bool hbr) { int pinctl, new_pinctl; if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { snd_hda_set_dev_select(codec, pin_nid, dev_id); pinctl = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); if (pinctl < 0) return hbr ? -EINVAL : 0; new_pinctl = pinctl & ~AC_PINCTL_EPT; if (hbr) new_pinctl |= AC_PINCTL_EPT_HBR; else new_pinctl |= AC_PINCTL_EPT_NATIVE; codec_dbg(codec, "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", pin_nid, pinctl == new_pinctl ? "" : "new-", new_pinctl); if (pinctl != new_pinctl) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, new_pinctl); } else if (hbr) return -EINVAL; return 0; } static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t pin_nid, int dev_id, u32 stream_tag, int format) { struct hdmi_spec *spec = codec->spec; unsigned int param; int err; err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, is_hbr_format(format)); if (err) { codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); return err; } if (spec->intel_hsw_fixup) { /* * on recent platforms IEC Coding Type is required for HBR * support, read current Digital Converter settings and set * ICT bitfield if needed. */ param = snd_hda_codec_read(codec, cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); param = (param >> 16) & ~(AC_DIG3_ICT); /* on recent platforms ICT mode is required for HBR support */ if (is_hbr_format(format)) param |= 0x1; snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); } snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); return 0; } /* Try to find an available converter * If pin_idx is less then zero, just try to find an available converter. * Otherwise, try to find an available converter and get the cvt mux index * of the pin. */ static int hdmi_choose_cvt(struct hda_codec *codec, int pin_idx, int *cvt_id, bool silent) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin; struct hdmi_spec_per_cvt *per_cvt = NULL; int cvt_idx, mux_idx = 0; /* pin_idx < 0 means no pin will be bound to the converter */ if (pin_idx < 0) per_pin = NULL; else per_pin = get_pin(spec, pin_idx); if (per_pin && per_pin->silent_stream) { cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); per_cvt = get_cvt(spec, cvt_idx); if (per_cvt->assigned && !silent) return -EBUSY; if (cvt_id) *cvt_id = cvt_idx; return 0; } /* Dynamically assign converter to stream */ for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { per_cvt = get_cvt(spec, cvt_idx); /* Must not already be assigned */ if (per_cvt->assigned || per_cvt->silent_stream) continue; if (per_pin == NULL) break; /* Must be in pin's mux's list of converters */ for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) break; /* Not in mux list */ if (mux_idx == per_pin->num_mux_nids) continue; break; } /* No free converters */ if (cvt_idx == spec->num_cvts) return -EBUSY; if (per_pin != NULL) per_pin->mux_idx = mux_idx; if (cvt_id) *cvt_id = cvt_idx; return 0; } /* Assure the pin select the right convetor */ static void intel_verify_pin_cvt_connect(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { hda_nid_t pin_nid = per_pin->pin_nid; int mux_idx, curr; mux_idx = per_pin->mux_idx; curr = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_CONNECT_SEL, 0); if (curr != mux_idx) snd_hda_codec_write_cache(codec, pin_nid, 0, AC_VERB_SET_CONNECT_SEL, mux_idx); } /* get the mux index for the converter of the pins * converter's mux index is the same for all pins on Intel platform */ static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, hda_nid_t cvt_nid) { int i; for (i = 0; i < spec->num_cvts; i++) if (spec->cvt_nids[i] == cvt_nid) return i; return -EINVAL; } /* Intel HDMI workaround to fix audio routing issue: * For some Intel display codecs, pins share the same connection list. * So a conveter can be selected by multiple pins and playback on any of these * pins will generate sound on the external display, because audio flows from * the same converter to the display pipeline. Also muting one pin may make * other pins have no sound output. * So this function assures that an assigned converter for a pin is not selected * by any other pins. */ static void intel_not_share_assigned_cvt(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, int mux_idx) { struct hdmi_spec *spec = codec->spec; hda_nid_t nid; int cvt_idx, curr; struct hdmi_spec_per_cvt *per_cvt; struct hdmi_spec_per_pin *per_pin; int pin_idx; /* configure the pins connections */ for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { int dev_id_saved; int dev_num; per_pin = get_pin(spec, pin_idx); /* * pin not connected to monitor * no need to operate on it */ if (!per_pin->pcm) continue; if ((per_pin->pin_nid == pin_nid) && (per_pin->dev_id == dev_id)) continue; /* * if per_pin->dev_id >= dev_num, * snd_hda_get_dev_select() will fail, * and the following operation is unpredictable. * So skip this situation. */ dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; if (per_pin->dev_id >= dev_num) continue; nid = per_pin->pin_nid; /* * Calling this function should not impact * on the device entry selection * So let's save the dev id for each pin, * and restore it when return */ dev_id_saved = snd_hda_get_dev_select(codec, nid); snd_hda_set_dev_select(codec, nid, per_pin->dev_id); curr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONNECT_SEL, 0); if (curr != mux_idx) { snd_hda_set_dev_select(codec, nid, dev_id_saved); continue; } /* choose an unassigned converter. The conveters in the * connection list are in the same order as in the codec. */ for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { per_cvt = get_cvt(spec, cvt_idx); if (!per_cvt->assigned) { codec_dbg(codec, "choose cvt %d for pin NID 0x%x\n", cvt_idx, nid); snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_CONNECT_SEL, cvt_idx); break; } } snd_hda_set_dev_select(codec, nid, dev_id_saved); } } /* A wrapper of intel_not_share_asigned_cvt() */ static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) { int mux_idx; struct hdmi_spec *spec = codec->spec; /* On Intel platform, the mapping of converter nid to * mux index of the pins are always the same. * The pin nid may be 0, this means all pins will not * share the converter. */ mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); if (mux_idx >= 0) intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); } /* skeleton caller of pin_cvt_fixup ops */ static void pin_cvt_fixup(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) { struct hdmi_spec *spec = codec->spec; if (spec->ops.pin_cvt_fixup) spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); } /* called in hdmi_pcm_open when no pin is assigned to the PCM */ static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; struct snd_pcm_runtime *runtime = substream->runtime; int cvt_idx, pcm_idx; struct hdmi_spec_per_cvt *per_cvt = NULL; int err; pcm_idx = hinfo_to_pcm_index(codec, hinfo); if (pcm_idx < 0) return -EINVAL; err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); if (err) return err; per_cvt = get_cvt(spec, cvt_idx); per_cvt->assigned = true; hinfo->nid = per_cvt->cvt_nid; pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); set_bit(pcm_idx, &spec->pcm_in_use); /* todo: setup spdif ctls assign */ /* Initially set the converter's capabilities */ hinfo->channels_min = per_cvt->channels_min; hinfo->channels_max = per_cvt->channels_max; hinfo->rates = per_cvt->rates; hinfo->formats = per_cvt->formats; hinfo->maxbps = per_cvt->maxbps; /* Store the updated parameters */ runtime->hw.channels_min = hinfo->channels_min; runtime->hw.channels_max = hinfo->channels_max; runtime->hw.formats = hinfo->formats; runtime->hw.rates = hinfo->rates; snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); return 0; } /* * HDA PCM callbacks */ static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; struct snd_pcm_runtime *runtime = substream->runtime; int pin_idx, cvt_idx, pcm_idx; struct hdmi_spec_per_pin *per_pin; struct hdmi_eld *eld; struct hdmi_spec_per_cvt *per_cvt = NULL; int err; /* Validate hinfo */ pcm_idx = hinfo_to_pcm_index(codec, hinfo); if (pcm_idx < 0) return -EINVAL; mutex_lock(&spec->pcm_lock); pin_idx = hinfo_to_pin_index(codec, hinfo); /* no pin is assigned to the PCM * PA need pcm open successfully when probe */ if (pin_idx < 0) { err = hdmi_pcm_open_no_pin(hinfo, codec, substream); goto unlock; } err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); if (err < 0) goto unlock; per_cvt = get_cvt(spec, cvt_idx); /* Claim converter */ per_cvt->assigned = true; set_bit(pcm_idx, &spec->pcm_in_use); per_pin = get_pin(spec, pin_idx); per_pin->cvt_nid = per_cvt->cvt_nid; hinfo->nid = per_cvt->cvt_nid; /* flip stripe flag for the assigned stream if supported */ if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) azx_stream(get_azx_dev(substream))->stripe = 1; snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, AC_VERB_SET_CONNECT_SEL, per_pin->mux_idx); /* configure unused pins to choose other converters */ pin_cvt_fixup(codec, per_pin, 0); snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); /* Initially set the converter's capabilities */ hinfo->channels_min = per_cvt->channels_min; hinfo->channels_max = per_cvt->channels_max; hinfo->rates = per_cvt->rates; hinfo->formats = per_cvt->formats; hinfo->maxbps = per_cvt->maxbps; eld = &per_pin->sink_eld; /* Restrict capabilities by ELD if this isn't disabled */ if (!static_hdmi_pcm && eld->eld_valid) { snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); if (hinfo->channels_min > hinfo->channels_max || !hinfo->rates || !hinfo->formats) { per_cvt->assigned = false; hinfo->nid = 0; snd_hda_spdif_ctls_unassign(codec, pcm_idx); err = -ENODEV; goto unlock; } } /* Store the updated parameters */ runtime->hw.channels_min = hinfo->channels_min; runtime->hw.channels_max = hinfo->channels_max; runtime->hw.formats = hinfo->formats; runtime->hw.rates = hinfo->rates; snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); unlock: mutex_unlock(&spec->pcm_lock); return err; } /* * HDA/HDMI auto parsing */ static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); hda_nid_t pin_nid = per_pin->pin_nid; int dev_id = per_pin->dev_id; int conns; if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { codec_warn(codec, "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", pin_nid, get_wcaps(codec, pin_nid)); return -EINVAL; } snd_hda_set_dev_select(codec, pin_nid, dev_id); if (spec->intel_hsw_fixup) { conns = spec->num_cvts; memcpy(per_pin->mux_nids, spec->cvt_nids, sizeof(hda_nid_t) * conns); } else { conns = snd_hda_get_raw_connections(codec, pin_nid, per_pin->mux_nids, HDA_MAX_CONNECTIONS); } /* all the device entries on the same pin have the same conn list */ per_pin->num_mux_nids = conns; return 0; } static int hdmi_find_pcm_slot(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin) { int i; for (i = 0; i < spec->pcm_used; i++) { if (!test_bit(i, &spec->pcm_bitmap)) return i; } return -EBUSY; } static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin) { int idx; /* pcm already be attached to the pin */ if (per_pin->pcm) return; /* try the previously used slot at first */ idx = per_pin->prev_pcm_idx; if (idx >= 0) { if (!test_bit(idx, &spec->pcm_bitmap)) goto found; per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */ } idx = hdmi_find_pcm_slot(spec, per_pin); if (idx == -EBUSY) return; found: per_pin->pcm_idx = idx; per_pin->pcm = get_hdmi_pcm(spec, idx); set_bit(idx, &spec->pcm_bitmap); } static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin) { int idx; /* pcm already be detached from the pin */ if (!per_pin->pcm) return; idx = per_pin->pcm_idx; per_pin->pcm_idx = -1; per_pin->prev_pcm_idx = idx; /* remember the previous index */ per_pin->pcm = NULL; if (idx >= 0 && idx < spec->pcm_used) clear_bit(idx, &spec->pcm_bitmap); } static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) { int mux_idx; for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) if (per_pin->mux_nids[mux_idx] == cvt_nid) break; return mux_idx; } static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin) { struct hda_codec *codec = per_pin->codec; struct hda_pcm *pcm; struct hda_pcm_stream *hinfo; struct snd_pcm_substream *substream; int mux_idx; bool non_pcm; if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) return; pcm = get_pcm_rec(spec, per_pin->pcm_idx); if (!pcm->pcm) return; if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) return; /* hdmi audio only uses playback and one substream */ hinfo = pcm->stream; substream = pcm->pcm->streams[0].substream; per_pin->cvt_nid = hinfo->nid; mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); if (mux_idx < per_pin->num_mux_nids) { snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, AC_VERB_SET_CONNECT_SEL, mux_idx); } snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); if (substream->runtime) per_pin->channels = substream->runtime->channels; per_pin->setup = true; per_pin->mux_idx = mux_idx; hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); } static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, struct hdmi_spec_per_pin *per_pin) { if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); per_pin->chmap_set = false; memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); per_pin->setup = false; per_pin->channels = 0; } static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { struct hdmi_spec *spec = codec->spec; if (per_pin->pcm_idx >= 0) return spec->pcm_rec[per_pin->pcm_idx].jack; else return NULL; } /* update per_pin ELD from the given new ELD; * setup info frame and notification accordingly * also notify ELD kctl and report jack status changes */ static void update_eld(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, struct hdmi_eld *eld, int repoll) { struct hdmi_eld *pin_eld = &per_pin->sink_eld; struct hdmi_spec *spec = codec->spec; struct snd_jack *pcm_jack; bool old_eld_valid = pin_eld->eld_valid; bool eld_changed; int pcm_idx; if (eld->eld_valid) { if (eld->eld_size <= 0 || snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, eld->eld_size) < 0) { eld->eld_valid = false; if (repoll) { schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); return; } } } if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { eld->eld_valid = false; eld->eld_size = 0; } /* for monitor disconnection, save pcm_idx firstly */ pcm_idx = per_pin->pcm_idx; /* * pcm_idx >=0 before update_eld() means it is in monitor * disconnected event. Jack must be fetched before update_eld(). */ pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); if (!spec->static_pcm_mapping) { if (eld->eld_valid) { hdmi_attach_hda_pcm(spec, per_pin); hdmi_pcm_setup_pin(spec, per_pin); } else { hdmi_pcm_reset_pin(spec, per_pin); hdmi_detach_hda_pcm(spec, per_pin); } } /* if pcm_idx == -1, it means this is in monitor connection event * we can get the correct pcm_idx now. */ if (pcm_idx == -1) pcm_idx = per_pin->pcm_idx; if (!pcm_jack) pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); if (eld->eld_valid) snd_hdmi_show_eld(codec, &eld->info); eld_changed = (pin_eld->eld_valid != eld->eld_valid); eld_changed |= (pin_eld->monitor_present != eld->monitor_present); if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) if (pin_eld->eld_size != eld->eld_size || memcmp(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size) != 0) eld_changed = true; if (eld_changed) { pin_eld->monitor_present = eld->monitor_present; pin_eld->eld_valid = eld->eld_valid; pin_eld->eld_size = eld->eld_size; if (eld->eld_valid) memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); pin_eld->info = eld->info; } /* * Re-setup pin and infoframe. This is needed e.g. when * - sink is first plugged-in * - transcoder can change during stream playback on Haswell * and this can make HW reset converter selection on a pin. */ if (eld->eld_valid && !old_eld_valid && per_pin->setup) { pin_cvt_fixup(codec, per_pin, 0); hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); } if (eld_changed && pcm_idx >= 0) snd_ctl_notify(codec->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); if (eld_changed && pcm_jack) snd_jack_report(pcm_jack, (eld->monitor_present && eld->eld_valid) ? SND_JACK_AVOUT : 0); } /* update ELD and jack state via HD-audio verbs */ static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, int repoll) { struct hda_codec *codec = per_pin->codec; struct hdmi_spec *spec = codec->spec; struct hdmi_eld *eld = &spec->temp_eld; struct device *dev = hda_codec_dev(codec); hda_nid_t pin_nid = per_pin->pin_nid; int dev_id = per_pin->dev_id; /* * Always execute a GetPinSense verb here, even when called from * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited * response's PD bit is not the real PD value, but indicates that * the real PD value changed. An older version of the HD-audio * specification worked this way. Hence, we just ignore the data in * the unsolicited response to avoid custom WARs. */ int present; int ret; #ifdef CONFIG_PM if (dev->power.runtime_status == RPM_SUSPENDING) return; #endif ret = snd_hda_power_up_pm(codec); if (ret < 0 && pm_runtime_suspended(dev)) goto out; present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); mutex_lock(&per_pin->lock); eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); if (eld->monitor_present) eld->eld_valid = !!(present & AC_PINSENSE_ELDV); else eld->eld_valid = false; codec_dbg(codec, "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); if (eld->eld_valid) { if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, eld->eld_buffer, &eld->eld_size) < 0) eld->eld_valid = false; } update_eld(codec, per_pin, eld, repoll); mutex_unlock(&per_pin->lock); out: snd_hda_power_down_pm(codec); } #define I915_SILENT_RATE 48000 #define I915_SILENT_CHANNELS 2 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE #define I915_SILENT_FORMAT_BITS 16 #define I915_SILENT_FMT_MASK 0xf static void silent_stream_enable_i915(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { unsigned int format; snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, per_pin->dev_id, I915_SILENT_RATE); /* trigger silent stream generation in hw */ format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); usleep_range(100, 200); snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); per_pin->channels = I915_SILENT_CHANNELS; hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); } static void silent_stream_set_kae(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, bool enable) { unsigned int param; codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); param = (param >> 16) & 0xff; if (enable) param |= AC_DIG3_KAE; else param &= ~AC_DIG3_KAE; snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); } static void silent_stream_enable(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_cvt *per_cvt; int cvt_idx, pin_idx, err; int keep_power = 0; /* * Power-up will call hdmi_present_sense, so the PM calls * have to be done without mutex held. */ err = snd_hda_power_up_pm(codec); if (err < 0 && err != -EACCES) { codec_err(codec, "Failed to power up codec for silent stream enable ret=[%d]\n", err); snd_hda_power_down_pm(codec); return; } mutex_lock(&per_pin->lock); if (per_pin->setup) { codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); err = -EBUSY; goto unlock_out; } pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); if (err) { codec_err(codec, "hdmi: no free converter to enable silent mode\n"); goto unlock_out; } per_cvt = get_cvt(spec, cvt_idx); per_cvt->silent_stream = true; per_pin->cvt_nid = per_cvt->cvt_nid; per_pin->silent_stream = true; codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", per_pin->pin_nid, per_cvt->cvt_nid); snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, AC_VERB_SET_CONNECT_SEL, per_pin->mux_idx); /* configure unused pins to choose other converters */ pin_cvt_fixup(codec, per_pin, 0); switch (spec->silent_stream_type) { case SILENT_STREAM_KAE: silent_stream_enable_i915(codec, per_pin); silent_stream_set_kae(codec, per_pin, true); break; case SILENT_STREAM_I915: silent_stream_enable_i915(codec, per_pin); keep_power = 1; break; default: break; } unlock_out: mutex_unlock(&per_pin->lock); if (err || !keep_power) snd_hda_power_down_pm(codec); } static void silent_stream_disable(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_cvt *per_cvt; int cvt_idx, err; err = snd_hda_power_up_pm(codec); if (err < 0 && err != -EACCES) { codec_err(codec, "Failed to power up codec for silent stream disable ret=[%d]\n", err); snd_hda_power_down_pm(codec); return; } mutex_lock(&per_pin->lock); if (!per_pin->silent_stream) goto unlock_out; codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", per_pin->pin_nid, per_pin->cvt_nid); cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { per_cvt = get_cvt(spec, cvt_idx); per_cvt->silent_stream = false; } if (spec->silent_stream_type == SILENT_STREAM_I915) { /* release ref taken in silent_stream_enable() */ snd_hda_power_down_pm(codec); } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { silent_stream_set_kae(codec, per_pin, false); } per_pin->cvt_nid = 0; per_pin->silent_stream = false; unlock_out: mutex_unlock(&per_pin->lock); snd_hda_power_down_pm(codec); } /* update ELD and jack state via audio component */ static void sync_eld_via_acomp(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin) { struct hdmi_spec *spec = codec->spec; struct hdmi_eld *eld = &spec->temp_eld; bool monitor_prev, monitor_next; mutex_lock(&per_pin->lock); eld->monitor_present = false; monitor_prev = per_pin->sink_eld.monitor_present; eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, per_pin->dev_id, &eld->monitor_present, eld->eld_buffer, ELD_MAX_SIZE); eld->eld_valid = (eld->eld_size > 0); update_eld(codec, per_pin, eld, 0); monitor_next = per_pin->sink_eld.monitor_present; mutex_unlock(&per_pin->lock); if (spec->silent_stream_type) { if (!monitor_prev && monitor_next) silent_stream_enable(codec, per_pin); else if (monitor_prev && !monitor_next) silent_stream_disable(codec, per_pin); } } static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) { struct hda_codec *codec = per_pin->codec; if (!codec_has_acomp(codec)) hdmi_present_sense_via_verbs(per_pin, repoll); else sync_eld_via_acomp(codec, per_pin); } static void hdmi_repoll_eld(struct work_struct *work) { struct hdmi_spec_per_pin *per_pin = container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); struct hda_codec *codec = per_pin->codec; struct hdmi_spec *spec = codec->spec; struct hda_jack_tbl *jack; jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, per_pin->dev_id); if (jack) jack->jack_dirty = 1; if (per_pin->repoll_count++ > 6) per_pin->repoll_count = 0; mutex_lock(&spec->pcm_lock); hdmi_present_sense(per_pin, per_pin->repoll_count); mutex_unlock(&spec->pcm_lock); } static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) { struct hdmi_spec *spec = codec->spec; unsigned int caps, config; int pin_idx; struct hdmi_spec_per_pin *per_pin; int err; int dev_num, i; caps = snd_hda_query_pin_caps(codec, pin_nid); if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) return 0; /* * For DP MST audio, Configuration Default is the same for * all device entries on the same pin */ config = snd_hda_codec_get_pincfg(codec, pin_nid); if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && !spec->force_connect) return 0; /* * To simplify the implementation, malloc all * the virtual pins in the initialization statically */ if (spec->intel_hsw_fixup) { /* * On Intel platforms, device entries count returned * by AC_PAR_DEVLIST_LEN is dynamic, and depends on * the type of receiver that is connected. Allocate pin * structures based on worst case. */ dev_num = spec->dev_num; } else if (codec->dp_mst) { dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; /* * spec->dev_num is the maxinum number of device entries * among all the pins */ spec->dev_num = (spec->dev_num > dev_num) ? spec->dev_num : dev_num; } else { /* * If the platform doesn't support DP MST, * manually set dev_num to 1. This means * the pin has only one device entry. */ dev_num = 1; spec->dev_num = 1; } for (i = 0; i < dev_num; i++) { pin_idx = spec->num_pins; per_pin = snd_array_new(&spec->pins); if (!per_pin) return -ENOMEM; per_pin->pcm = NULL; per_pin->pcm_idx = -1; per_pin->prev_pcm_idx = -1; per_pin->pin_nid = pin_nid; per_pin->pin_nid_idx = spec->num_nids; per_pin->dev_id = i; per_pin->non_pcm = false; snd_hda_set_dev_select(codec, pin_nid, i); err = hdmi_read_pin_conn(codec, pin_idx); if (err < 0) return err; if (!is_jack_detectable(codec, pin_nid)) codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); spec->num_pins++; } spec->num_nids++; return 0; } static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_cvt *per_cvt; unsigned int chans; int err; chans = get_wcaps(codec, cvt_nid); chans = get_wcaps_channels(chans); per_cvt = snd_array_new(&spec->cvts); if (!per_cvt) return -ENOMEM; per_cvt->cvt_nid = cvt_nid; per_cvt->channels_min = 2; if (chans <= 16) { per_cvt->channels_max = chans; if (chans > spec->chmap.channels_max) spec->chmap.channels_max = chans; } err = snd_hda_query_supported_pcm(codec, cvt_nid, &per_cvt->rates, &per_cvt->formats, &per_cvt->maxbps); if (err < 0) return err; if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) spec->cvt_nids[spec->num_cvts] = cvt_nid; spec->num_cvts++; return 0; } static const struct snd_pci_quirk force_connect_list[] = { SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1), SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1), SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), {} }; static int hdmi_parse_codec(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; hda_nid_t start_nid; unsigned int caps; int i, nodes; const struct snd_pci_quirk *q; nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); if (!start_nid || nodes < 0) { codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); return -EINVAL; } if (enable_all_pins) spec->force_connect = true; q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); if (q && q->value) spec->force_connect = true; /* * hdmi_add_pin() assumes total amount of converters to * be known, so first discover all converters */ for (i = 0; i < nodes; i++) { hda_nid_t nid = start_nid + i; caps = get_wcaps(codec, nid); if (!(caps & AC_WCAP_DIGITAL)) continue; if (get_wcaps_type(caps) == AC_WID_AUD_OUT) hdmi_add_cvt(codec, nid); } /* discover audio pins */ for (i = 0; i < nodes; i++) { hda_nid_t nid = start_nid + i; caps = get_wcaps(codec, nid); if (!(caps & AC_WCAP_DIGITAL)) continue; if (get_wcaps_type(caps) == AC_WID_PIN) hdmi_add_pin(codec, nid); } return 0; } /* */ static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) { struct hda_spdif_out *spdif; bool non_pcm; mutex_lock(&codec->spdif_mutex); spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); /* Add sanity check to pass klockwork check. * This should never happen. */ if (WARN_ON(spdif == NULL)) { mutex_unlock(&codec->spdif_mutex); return true; } non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); mutex_unlock(&codec->spdif_mutex); return non_pcm; } /* * HDMI callbacks */ static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { hda_nid_t cvt_nid = hinfo->nid; struct hdmi_spec *spec = codec->spec; int pin_idx; struct hdmi_spec_per_pin *per_pin; struct snd_pcm_runtime *runtime = substream->runtime; bool non_pcm; int pinctl, stripe; int err = 0; mutex_lock(&spec->pcm_lock); pin_idx = hinfo_to_pin_index(codec, hinfo); if (pin_idx < 0) { /* when pcm is not bound to a pin skip pin setup and return 0 * to make audio playback be ongoing */ pin_cvt_fixup(codec, NULL, cvt_nid); snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); goto unlock; } per_pin = get_pin(spec, pin_idx); /* Verify pin:cvt selections to avoid silent audio after S3. * After S3, the audio driver restores pin:cvt selections * but this can happen before gfx is ready and such selection * is overlooked by HW. Thus multiple pins can share a same * default convertor and mute control will affect each other, * which can cause a resumed audio playback become silent * after S3. */ pin_cvt_fixup(codec, per_pin, 0); /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ /* Todo: add DP1.2 MST audio support later */ if (codec_has_acomp(codec)) snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, per_pin->dev_id, runtime->rate); non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); mutex_lock(&per_pin->lock); per_pin->channels = substream->runtime->channels; per_pin->setup = true; if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, substream); snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_STRIPE_CONTROL, stripe); } hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); mutex_unlock(&per_pin->lock); if (spec->dyn_pin_out) { snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_codec_write(codec, per_pin->pin_nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pinctl | PIN_OUT); } /* snd_hda_set_dev_select() has been called before */ err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, per_pin->dev_id, stream_tag, format); unlock: mutex_unlock(&spec->pcm_lock); return err; } static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { snd_hda_codec_cleanup_stream(codec, hinfo->nid); return 0; } static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; int cvt_idx, pin_idx, pcm_idx; struct hdmi_spec_per_cvt *per_cvt; struct hdmi_spec_per_pin *per_pin; int pinctl; int err = 0; mutex_lock(&spec->pcm_lock); if (hinfo->nid) { pcm_idx = hinfo_to_pcm_index(codec, hinfo); if (snd_BUG_ON(pcm_idx < 0)) { err = -EINVAL; goto unlock; } cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); if (snd_BUG_ON(cvt_idx < 0)) { err = -EINVAL; goto unlock; } per_cvt = get_cvt(spec, cvt_idx); per_cvt->assigned = false; hinfo->nid = 0; azx_stream(get_azx_dev(substream))->stripe = 0; snd_hda_spdif_ctls_unassign(codec, pcm_idx); clear_bit(pcm_idx, &spec->pcm_in_use); pin_idx = hinfo_to_pin_index(codec, hinfo); /* * In such a case, return 0 to match the behavior in * hdmi_pcm_open() */ if (pin_idx < 0) goto unlock; per_pin = get_pin(spec, pin_idx); if (spec->dyn_pin_out) { snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); snd_hda_codec_write(codec, per_pin->pin_nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pinctl & ~PIN_OUT); } mutex_lock(&per_pin->lock); per_pin->chmap_set = false; memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); per_pin->setup = false; per_pin->channels = 0; mutex_unlock(&per_pin->lock); } unlock: mutex_unlock(&spec->pcm_lock); return err; } static const struct hda_pcm_ops generic_ops = { .open = hdmi_pcm_open, .close = hdmi_pcm_close, .prepare = generic_hdmi_playback_pcm_prepare, .cleanup = generic_hdmi_playback_pcm_cleanup, }; static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) { struct hda_codec *codec = hdac_to_hda_codec(hdac); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); if (!per_pin) return 0; return per_pin->sink_eld.info.spk_alloc; } static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, unsigned char *chmap) { struct hda_codec *codec = hdac_to_hda_codec(hdac); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); /* chmap is already set to 0 in caller */ if (!per_pin) return; memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); } static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, unsigned char *chmap, int prepared) { struct hda_codec *codec = hdac_to_hda_codec(hdac); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); if (!per_pin) return; mutex_lock(&per_pin->lock); per_pin->chmap_set = true; memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); if (prepared) hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); mutex_unlock(&per_pin->lock); } static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) { struct hda_codec *codec = hdac_to_hda_codec(hdac); struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); return per_pin ? true:false; } static int generic_hdmi_build_pcms(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int idx, pcm_num; /* limit the PCM devices to the codec converters or available PINs */ pcm_num = min(spec->num_cvts, spec->num_pins); codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); for (idx = 0; idx < pcm_num; idx++) { struct hda_pcm *info; struct hda_pcm_stream *pstr; info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); if (!info) return -ENOMEM; spec->pcm_rec[idx].pcm = info; spec->pcm_used++; info->pcm_type = HDA_PCM_TYPE_HDMI; info->own_chmap = true; pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; pstr->substreams = 1; pstr->ops = generic_ops; /* pcm number is less than pcm_rec array size */ if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) break; /* other pstr fields are set in open */ } return 0; } static void free_hdmi_jack_priv(struct snd_jack *jack) { struct hdmi_pcm *pcm = jack->private_data; pcm->jack = NULL; } static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) { char hdmi_str[32] = "HDMI/DP"; struct hdmi_spec *spec = codec->spec; struct snd_jack *jack; int pcmdev = get_pcm_rec(spec, pcm_idx)->device; int err; if (pcmdev > 0) sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, true, false); if (err < 0) return err; spec->pcm_rec[pcm_idx].jack = jack; jack->private_data = &spec->pcm_rec[pcm_idx]; jack->private_free = free_hdmi_jack_priv; return 0; } static int generic_hdmi_build_controls(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int dev, err; int pin_idx, pcm_idx; for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { if (!get_pcm_rec(spec, pcm_idx)->pcm) { /* no PCM: mark this for skipping permanently */ set_bit(pcm_idx, &spec->pcm_bitmap); continue; } err = generic_hdmi_build_jack(codec, pcm_idx); if (err < 0) return err; /* create the spdif for each pcm * pin will be bound when monitor is connected */ err = snd_hda_create_dig_out_ctls(codec, 0, spec->cvt_nids[0], HDA_PCM_TYPE_HDMI); if (err < 0) return err; snd_hda_spdif_ctls_unassign(codec, pcm_idx); dev = get_pcm_rec(spec, pcm_idx)->device; if (dev != SNDRV_PCM_INVALID_DEVICE) { /* add control for ELD Bytes */ err = hdmi_create_eld_ctl(codec, pcm_idx, dev); if (err < 0) return err; } } for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); struct hdmi_eld *pin_eld = &per_pin->sink_eld; if (spec->static_pcm_mapping) { hdmi_attach_hda_pcm(spec, per_pin); hdmi_pcm_setup_pin(spec, per_pin); } pin_eld->eld_valid = false; hdmi_present_sense(per_pin, 0); } /* add channel maps */ for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { struct hda_pcm *pcm; pcm = get_pcm_rec(spec, pcm_idx); if (!pcm || !pcm->pcm) break; err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); if (err < 0) return err; } return 0; } static int generic_hdmi_init_per_pins(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); per_pin->codec = codec; mutex_init(&per_pin->lock); INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); eld_proc_new(per_pin, pin_idx); } return 0; } static int generic_hdmi_init(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx; mutex_lock(&spec->bind_lock); for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); hda_nid_t pin_nid = per_pin->pin_nid; int dev_id = per_pin->dev_id; snd_hda_set_dev_select(codec, pin_nid, dev_id); hdmi_init_pin(codec, pin_nid); if (codec_has_acomp(codec)) continue; snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, jack_callback); } mutex_unlock(&spec->bind_lock); return 0; } static void hdmi_array_init(struct hdmi_spec *spec, int nums) { snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); } static void hdmi_array_free(struct hdmi_spec *spec) { snd_array_free(&spec->pins); snd_array_free(&spec->cvts); } static void generic_spec_free(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; if (spec) { hdmi_array_free(spec); kfree(spec); codec->spec = NULL; } codec->dp_mst = false; } static void generic_hdmi_free(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx, pcm_idx; if (spec->acomp_registered) { snd_hdac_acomp_exit(&codec->bus->core); } else if (codec_has_acomp(codec)) { snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); } codec->relaxed_resume = 0; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); cancel_delayed_work_sync(&per_pin->work); eld_proc_free(per_pin); } for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { if (spec->pcm_rec[pcm_idx].jack == NULL) continue; snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); } generic_spec_free(codec); } #ifdef CONFIG_PM static int generic_hdmi_suspend(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); cancel_delayed_work_sync(&per_pin->work); } return 0; } static int generic_hdmi_resume(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx; codec->patch_ops.init(codec); snd_hda_regmap_sync(codec); for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); hdmi_present_sense(per_pin, 1); } return 0; } #endif static const struct hda_codec_ops generic_hdmi_patch_ops = { .init = generic_hdmi_init, .free = generic_hdmi_free, .build_pcms = generic_hdmi_build_pcms, .build_controls = generic_hdmi_build_controls, .unsol_event = hdmi_unsol_event, #ifdef CONFIG_PM .suspend = generic_hdmi_suspend, .resume = generic_hdmi_resume, #endif }; static const struct hdmi_ops generic_standard_hdmi_ops = { .pin_get_eld = hdmi_pin_get_eld, .pin_setup_infoframe = hdmi_pin_setup_infoframe, .pin_hbr_setup = hdmi_pin_hbr_setup, .setup_stream = hdmi_setup_stream, }; /* allocate codec->spec and assign/initialize generic parser ops */ static int alloc_generic_hdmi(struct hda_codec *codec) { struct hdmi_spec *spec; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return -ENOMEM; spec->codec = codec; spec->ops = generic_standard_hdmi_ops; spec->dev_num = 1; /* initialize to 1 */ mutex_init(&spec->pcm_lock); mutex_init(&spec->bind_lock); snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); spec->chmap.ops.get_chmap = hdmi_get_chmap; spec->chmap.ops.set_chmap = hdmi_set_chmap; spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; codec->spec = spec; hdmi_array_init(spec, 4); codec->patch_ops = generic_hdmi_patch_ops; return 0; } /* generic HDMI parser */ static int patch_generic_hdmi(struct hda_codec *codec) { int err; err = alloc_generic_hdmi(codec); if (err < 0) return err; err = hdmi_parse_codec(codec); if (err < 0) { generic_spec_free(codec); return err; } generic_hdmi_init_per_pins(codec); return 0; } /* * generic audio component binding */ /* turn on / off the unsol event jack detection dynamically */ static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, int dev_id, bool use_acomp) { struct hda_jack_tbl *tbl; tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); if (tbl) { /* clear unsol even if component notifier is used, or re-enable * if notifier is cleared */ unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_UNSOLICITED_ENABLE, val); } } /* set up / clear component notifier dynamically */ static void generic_acomp_notifier_set(struct drm_audio_component *acomp, bool use_acomp) { struct hdmi_spec *spec; int i; spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); mutex_lock(&spec->bind_lock); spec->use_acomp_notifier = use_acomp; spec->codec->relaxed_resume = use_acomp; spec->codec->bus->keep_power = 0; /* reprogram each jack detection logic depending on the notifier */ for (i = 0; i < spec->num_pins; i++) reprogram_jack_detect(spec->codec, get_pin(spec, i)->pin_nid, get_pin(spec, i)->dev_id, use_acomp); mutex_unlock(&spec->bind_lock); } /* enable / disable the notifier via master bind / unbind */ static int generic_acomp_master_bind(struct device *dev, struct drm_audio_component *acomp) { generic_acomp_notifier_set(acomp, true); return 0; } static void generic_acomp_master_unbind(struct device *dev, struct drm_audio_component *acomp) { generic_acomp_notifier_set(acomp, false); } /* check whether both HD-audio and DRM PCI devices belong to the same bus */ static int match_bound_vga(struct device *dev, int subtype, void *data) { struct hdac_bus *bus = data; struct pci_dev *pci, *master; if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) return 0; master = to_pci_dev(bus->dev); pci = to_pci_dev(dev); return master->bus == pci->bus; } /* audio component notifier for AMD/Nvidia HDMI codecs */ static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) { struct hda_codec *codec = audio_ptr; struct hdmi_spec *spec = codec->spec; hda_nid_t pin_nid = spec->port2pin(codec, port); if (!pin_nid) return; if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) return; /* skip notification during system suspend (but not in runtime PM); * the state will be updated at resume */ if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) return; check_presence_and_report(codec, pin_nid, dev_id); } /* set up the private drm_audio_ops from the template */ static void setup_drm_audio_ops(struct hda_codec *codec, const struct drm_audio_component_audio_ops *ops) { struct hdmi_spec *spec = codec->spec; spec->drm_audio_ops.audio_ptr = codec; /* intel_audio_codec_enable() or intel_audio_codec_disable() * will call pin_eld_notify with using audio_ptr pointer * We need make sure audio_ptr is really setup */ wmb(); spec->drm_audio_ops.pin2port = ops->pin2port; spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; spec->drm_audio_ops.master_bind = ops->master_bind; spec->drm_audio_ops.master_unbind = ops->master_unbind; } /* initialize the generic HDMI audio component */ static void generic_acomp_init(struct hda_codec *codec, const struct drm_audio_component_audio_ops *ops, int (*port2pin)(struct hda_codec *, int)) { struct hdmi_spec *spec = codec->spec; if (!enable_acomp) { codec_info(codec, "audio component disabled by module option\n"); return; } spec->port2pin = port2pin; setup_drm_audio_ops(codec, ops); if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, match_bound_vga, 0)) { spec->acomp_registered = true; } } /* * Intel codec parsers and helpers */ #define INTEL_GET_VENDOR_VERB 0xf81 #define INTEL_SET_VENDOR_VERB 0x781 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ static void intel_haswell_enable_all_pins(struct hda_codec *codec, bool update_tree) { unsigned int vendor_param; struct hdmi_spec *spec = codec->spec; vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, INTEL_GET_VENDOR_VERB, 0); if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) return; vendor_param |= INTEL_EN_ALL_PIN_CVTS; vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, INTEL_SET_VENDOR_VERB, vendor_param); if (vendor_param == -1) return; if (update_tree) snd_hda_codec_update_widgets(codec); } static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) { unsigned int vendor_param; struct hdmi_spec *spec = codec->spec; vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, INTEL_GET_VENDOR_VERB, 0); if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) return; /* enable DP1.2 mode */ vendor_param |= INTEL_EN_DP12; snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, INTEL_SET_VENDOR_VERB, vendor_param); } /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. * Otherwise you may get severe h/w communication errors. */ static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, unsigned int power_state) { if (power_state == AC_PWRST_D0) { intel_haswell_enable_all_pins(codec, false); intel_haswell_fixup_enable_dp12(codec); } snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); snd_hda_codec_set_power_to_all(codec, fg, power_state); } /* There is a fixed mapping between audio pin node and display port. * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: * Pin Widget 5 - PORT B (port = 1 in i915 driver) * Pin Widget 6 - PORT C (port = 2 in i915 driver) * Pin Widget 7 - PORT D (port = 3 in i915 driver) * * on VLV, ILK: * Pin Widget 4 - PORT B (port = 1 in i915 driver) * Pin Widget 5 - PORT C (port = 2 in i915 driver) * Pin Widget 6 - PORT D (port = 3 in i915 driver) */ static int intel_base_nid(struct hda_codec *codec) { switch (codec->core.vendor_id) { case 0x80860054: /* ILK */ case 0x80862804: /* ILK */ case 0x80862882: /* VLV */ return 4; default: return 5; } } static int intel_pin2port(void *audio_ptr, int pin_nid) { struct hda_codec *codec = audio_ptr; struct hdmi_spec *spec = codec->spec; int base_nid, i; if (!spec->port_num) { base_nid = intel_base_nid(codec); if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) return -1; return pin_nid - base_nid + 1; } /* * looking for the pin number in the mapping table and return * the index which indicate the port number */ for (i = 0; i < spec->port_num; i++) { if (pin_nid == spec->port_map[i]) return i; } codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); return -1; } static int intel_port2pin(struct hda_codec *codec, int port) { struct hdmi_spec *spec = codec->spec; if (!spec->port_num) { /* we assume only from port-B to port-D */ if (port < 1 || port > 3) return 0; return port + intel_base_nid(codec) - 1; } if (port < 0 || port >= spec->port_num) return 0; return spec->port_map[port]; } static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) { struct hda_codec *codec = audio_ptr; int pin_nid; int dev_id = pipe; pin_nid = intel_port2pin(codec, port); if (!pin_nid) return; /* skip notification during system suspend (but not in runtime PM); * the state will be updated at resume */ if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) return; snd_hdac_i915_set_bclk(&codec->bus->core); check_presence_and_report(codec, pin_nid, dev_id); } static const struct drm_audio_component_audio_ops intel_audio_ops = { .pin2port = intel_pin2port, .pin_eld_notify = intel_pin_eld_notify, }; /* register i915 component pin_eld_notify callback */ static void register_i915_notifier(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; spec->use_acomp_notifier = true; spec->port2pin = intel_port2pin; setup_drm_audio_ops(codec, &intel_audio_ops); snd_hdac_acomp_register_notifier(&codec->bus->core, &spec->drm_audio_ops); /* no need for forcible resume for jack check thanks to notifier */ codec->relaxed_resume = 1; } /* setup_stream ops override for HSW+ */ static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t pin_nid, int dev_id, u32 stream_tag, int format) { struct hdmi_spec *spec = codec->spec; int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id); struct hdmi_spec_per_pin *per_pin; int res; if (pin_idx < 0) per_pin = NULL; else per_pin = get_pin(spec, pin_idx); haswell_verify_D0(codec, cvt_nid, pin_nid); if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { silent_stream_set_kae(codec, per_pin, false); /* wait for pending transfers in codec to clear */ usleep_range(100, 200); } res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, stream_tag, format); if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { usleep_range(100, 200); silent_stream_set_kae(codec, per_pin, true); } return res; } /* pin_cvt_fixup ops override for HSW+ and VLV+ */ static void i915_pin_cvt_fixup(struct hda_codec *codec, struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) { if (per_pin) { haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); intel_verify_pin_cvt_connect(codec, per_pin); intel_not_share_assigned_cvt(codec, per_pin->pin_nid, per_pin->dev_id, per_pin->mux_idx); } else { intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); } } #ifdef CONFIG_PM static int i915_adlp_hdmi_suspend(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; bool silent_streams = false; int pin_idx, res; res = generic_hdmi_suspend(codec); for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); if (per_pin->silent_stream) { silent_streams = true; break; } } if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) { /* * stream-id should remain programmed when codec goes * to runtime suspend */ codec->no_stream_clean_at_suspend = 1; /* * the system might go to S3, in which case keep-alive * must be reprogrammed upon resume */ codec->forced_resume = 1; codec_dbg(codec, "HDMI: KAE active at suspend\n"); } else { codec->no_stream_clean_at_suspend = 0; codec->forced_resume = 0; } return res; } static int i915_adlp_hdmi_resume(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx, res; res = generic_hdmi_resume(codec); /* KAE not programmed at suspend, nothing to do here */ if (!codec->no_stream_clean_at_suspend) return res; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); /* * If system was in suspend with monitor connected, * the codec setting may have been lost. Re-enable * keep-alive. */ if (per_pin->silent_stream) { unsigned int param; param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_CONV, 0); if (!param) { codec_dbg(codec, "HDMI: KAE: restore stream id\n"); silent_stream_enable_i915(codec, per_pin); } param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); if (!(param & (AC_DIG3_KAE << 16))) { codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n"); silent_stream_set_kae(codec, per_pin, true); } } } return res; } #endif /* precondition and allocation for Intel codecs */ static int alloc_intel_hdmi(struct hda_codec *codec) { int err; /* requires i915 binding */ if (!codec->bus->core.audio_component) { codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); /* set probe_id here to prevent generic fallback binding */ codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; return -ENODEV; } err = alloc_generic_hdmi(codec); if (err < 0) return err; /* no need to handle unsol events */ codec->patch_ops.unsol_event = NULL; return 0; } /* parse and post-process for Intel codecs */ static int parse_intel_hdmi(struct hda_codec *codec) { int err, retries = 3; do { err = hdmi_parse_codec(codec); } while (err < 0 && retries--); if (err < 0) { generic_spec_free(codec); return err; } generic_hdmi_init_per_pins(codec); register_i915_notifier(codec); return 0; } /* Intel Haswell and onwards; audio component with eld notifier */ static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, const int *port_map, int port_num, int dev_num, bool send_silent_stream) { struct hdmi_spec *spec; int err; err = alloc_intel_hdmi(codec); if (err < 0) return err; spec = codec->spec; codec->dp_mst = true; spec->vendor_nid = vendor_nid; spec->port_map = port_map; spec->port_num = port_num; spec->intel_hsw_fixup = true; spec->dev_num = dev_num; intel_haswell_enable_all_pins(codec, true); intel_haswell_fixup_enable_dp12(codec); codec->display_power_control = 1; codec->patch_ops.set_power_state = haswell_set_power_state; codec->depop_delay = 0; codec->auto_runtime_pm = 1; spec->ops.setup_stream = i915_hsw_setup_stream; spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; /* * Enable silent stream feature, if it is enabled via * module param or Kconfig option */ if (send_silent_stream) spec->silent_stream_type = SILENT_STREAM_I915; return parse_intel_hdmi(codec); } static int patch_i915_hsw_hdmi(struct hda_codec *codec) { return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, enable_silent_stream); } static int patch_i915_glk_hdmi(struct hda_codec *codec) { /* * Silent stream calls audio component .get_power() from * .pin_eld_notify(). On GLK this will deadlock in i915 due * to the audio vs. CDCLK workaround. */ return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); } static int patch_i915_icl_hdmi(struct hda_codec *codec) { /* * pin to port mapping table where the value indicate the pin number and * the index indicate the port number. */ static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, enable_silent_stream); } static int patch_i915_tgl_hdmi(struct hda_codec *codec) { /* * pin to port mapping table where the value indicate the pin number and * the index indicate the port number. */ static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, enable_silent_stream); } static int patch_i915_adlp_hdmi(struct hda_codec *codec) { struct hdmi_spec *spec; int res; res = patch_i915_tgl_hdmi(codec); if (!res) { spec = codec->spec; if (spec->silent_stream_type) { spec->silent_stream_type = SILENT_STREAM_KAE; #ifdef CONFIG_PM codec->patch_ops.resume = i915_adlp_hdmi_resume; codec->patch_ops.suspend = i915_adlp_hdmi_suspend; #endif } } return res; } /* Intel Baytrail and Braswell; with eld notifier */ static int patch_i915_byt_hdmi(struct hda_codec *codec) { struct hdmi_spec *spec; int err; err = alloc_intel_hdmi(codec); if (err < 0) return err; spec = codec->spec; /* For Valleyview/Cherryview, only the display codec is in the display * power well and can use link_power ops to request/release the power. */ codec->display_power_control = 1; codec->depop_delay = 0; codec->auto_runtime_pm = 1; spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; return parse_intel_hdmi(codec); } /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ static int patch_i915_cpt_hdmi(struct hda_codec *codec) { int err; err = alloc_intel_hdmi(codec); if (err < 0) return err; return parse_intel_hdmi(codec); } /* * Shared non-generic implementations */ static int simple_playback_build_pcms(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; struct hda_pcm *info; unsigned int chans; struct hda_pcm_stream *pstr; struct hdmi_spec_per_cvt *per_cvt; per_cvt = get_cvt(spec, 0); chans = get_wcaps(codec, per_cvt->cvt_nid); chans = get_wcaps_channels(chans); info = snd_hda_codec_pcm_new(codec, "HDMI 0"); if (!info) return -ENOMEM; spec->pcm_rec[0].pcm = info; info->pcm_type = HDA_PCM_TYPE_HDMI; pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; *pstr = spec->pcm_playback; pstr->nid = per_cvt->cvt_nid; if (pstr->channels_max <= 2 && chans && chans <= 16) pstr->channels_max = chans; return 0; } /* unsolicited event for jack sensing */ static void simple_hdmi_unsol_event(struct hda_codec *codec, unsigned int res) { snd_hda_jack_set_dirty_all(codec); snd_hda_jack_report_sync(codec); } /* generic_hdmi_build_jack can be used for simple_hdmi, too, * as long as spec->pins[] is set correctly */ #define simple_hdmi_build_jack generic_hdmi_build_jack static int simple_playback_build_controls(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_cvt *per_cvt; int err; per_cvt = get_cvt(spec, 0); err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, per_cvt->cvt_nid, HDA_PCM_TYPE_HDMI); if (err < 0) return err; return simple_hdmi_build_jack(codec, 0); } static int simple_playback_init(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); hda_nid_t pin = per_pin->pin_nid; snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); /* some codecs require to unmute the pin */ if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); return 0; } static void simple_playback_free(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; hdmi_array_free(spec); kfree(spec); } /* * Nvidia specific implementations */ #define Nv_VERB_SET_Channel_Allocation 0xF79 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A #define Nv_VERB_SET_Audio_Protection_On 0xF98 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 #define nvhdmi_master_con_nid_7x 0x04 #define nvhdmi_master_pin_nid_7x 0x05 static const hda_nid_t nvhdmi_con_nids_7x[4] = { /*front, rear, clfe, rear_surr */ 0x6, 0x8, 0xa, 0xc, }; static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { /* set audio protect on */ { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, /* enable digital output on pin widget */ { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, {} /* terminator */ }; static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { /* set audio protect on */ { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, /* enable digital output on pin widget */ { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, {} /* terminator */ }; #ifdef LIMITED_RATE_FMT_SUPPORT /* support only the safe format and rate */ #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 #define SUPPORTED_MAXBPS 16 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE #else /* support all rates and formats */ #define SUPPORTED_RATES \ (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ SNDRV_PCM_RATE_192000) #define SUPPORTED_MAXBPS 24 #define SUPPORTED_FORMATS \ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) #endif static int nvhdmi_7x_init_2ch(struct hda_codec *codec) { snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); return 0; } static int nvhdmi_7x_init_8ch(struct hda_codec *codec) { snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); return 0; } static const unsigned int channels_2_6_8[] = { 2, 6, 8 }; static const unsigned int channels_2_8[] = { 2, 8 }; static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { .count = ARRAY_SIZE(channels_2_6_8), .list = channels_2_6_8, .mask = 0, }; static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { .count = ARRAY_SIZE(channels_2_8), .list = channels_2_8, .mask = 0, }; static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; switch (codec->preset->vendor_id) { case 0x10de0002: case 0x10de0003: case 0x10de0005: case 0x10de0006: hw_constraints_channels = &hw_constraints_2_8_channels; break; case 0x10de0007: hw_constraints_channels = &hw_constraints_2_6_8_channels; break; default: break; } if (hw_constraints_channels != NULL) { snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, hw_constraints_channels); } else { snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); } return snd_hda_multi_out_dig_open(codec, &spec->multiout); } static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; return snd_hda_multi_out_dig_close(codec, &spec->multiout); } static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag, format, substream); } static const struct hda_pcm_stream simple_pcm_playback = { .substreams = 1, .channels_min = 2, .channels_max = 2, .ops = { .open = simple_playback_pcm_open, .close = simple_playback_pcm_close, .prepare = simple_playback_pcm_prepare }, }; static const struct hda_codec_ops simple_hdmi_patch_ops = { .build_controls = simple_playback_build_controls, .build_pcms = simple_playback_build_pcms, .init = simple_playback_init, .free = simple_playback_free, .unsol_event = simple_hdmi_unsol_event, }; static int patch_simple_hdmi(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t pin_nid) { struct hdmi_spec *spec; struct hdmi_spec_per_cvt *per_cvt; struct hdmi_spec_per_pin *per_pin; spec = kzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) return -ENOMEM; spec->codec = codec; codec->spec = spec; hdmi_array_init(spec, 1); spec->multiout.num_dacs = 0; /* no analog */ spec->multiout.max_channels = 2; spec->multiout.dig_out_nid = cvt_nid; spec->num_cvts = 1; spec->num_pins = 1; per_pin = snd_array_new(&spec->pins); per_cvt = snd_array_new(&spec->cvts); if (!per_pin || !per_cvt) { simple_playback_free(codec); return -ENOMEM; } per_cvt->cvt_nid = cvt_nid; per_pin->pin_nid = pin_nid; spec->pcm_playback = simple_pcm_playback; codec->patch_ops = simple_hdmi_patch_ops; return 0; } static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, int channels) { unsigned int chanmask; int chan = channels ? (channels - 1) : 1; switch (channels) { default: case 0: case 2: chanmask = 0x00; break; case 4: chanmask = 0x08; break; case 6: chanmask = 0x0b; break; case 8: chanmask = 0x13; break; } /* Set the audio infoframe channel allocation and checksum fields. The * channel count is computed implicitly by the hardware. */ snd_hda_codec_write(codec, 0x1, 0, Nv_VERB_SET_Channel_Allocation, chanmask); snd_hda_codec_write(codec, 0x1, 0, Nv_VERB_SET_Info_Frame_Checksum, (0x71 - chan - chanmask)); } static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; int i; snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_CHANNEL_STREAMID, 0); for (i = 0; i < 4; i++) { /* set the stream id */ snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_CHANNEL_STREAMID, 0); /* set the stream format */ snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_STREAM_FORMAT, 0); } /* The audio hardware sends a channel count of 0x7 (8ch) when all the * streams are disabled. */ nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); return snd_hda_multi_out_dig_close(codec, &spec->multiout); } static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { int chs; unsigned int dataDCC2, channel_id; int i; struct hdmi_spec *spec = codec->spec; struct hda_spdif_out *spdif; struct hdmi_spec_per_cvt *per_cvt; mutex_lock(&codec->spdif_mutex); per_cvt = get_cvt(spec, 0); spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); chs = substream->runtime->channels; dataDCC2 = 0x2; /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_DIGI_CONVERT_1, spdif->ctls & ~AC_DIG1_ENABLE & 0xff); /* set the stream id */ snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); /* set the stream format */ snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_STREAM_FORMAT, format); /* turn on again (if needed) */ /* enable and set the channel status audio/data flag */ if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_DIGI_CONVERT_1, spdif->ctls & 0xff); snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); } for (i = 0; i < 4; i++) { if (chs == 2) channel_id = 0; else channel_id = i * 2; /* turn off SPDIF once; *otherwise the IEC958 bits won't be updated */ if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_DIGI_CONVERT_1, spdif->ctls & ~AC_DIG1_ENABLE & 0xff); /* set the stream id */ snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | channel_id); /* set the stream format */ snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_STREAM_FORMAT, format); /* turn on again (if needed) */ /* enable and set the channel status audio/data flag */ if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_DIGI_CONVERT_1, spdif->ctls & 0xff); snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); } } nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); mutex_unlock(&codec->spdif_mutex); return 0; } static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { .substreams = 1, .channels_min = 2, .channels_max = 8, .nid = nvhdmi_master_con_nid_7x, .rates = SUPPORTED_RATES, .maxbps = SUPPORTED_MAXBPS, .formats = SUPPORTED_FORMATS, .ops = { .open = simple_playback_pcm_open, .close = nvhdmi_8ch_7x_pcm_close, .prepare = nvhdmi_8ch_7x_pcm_prepare }, }; static int patch_nvhdmi_2ch(struct hda_codec *codec) { struct hdmi_spec *spec; int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, nvhdmi_master_pin_nid_7x); if (err < 0) return err; codec->patch_ops.init = nvhdmi_7x_init_2ch; /* override the PCM rates, etc, as the codec doesn't give full list */ spec = codec->spec; spec->pcm_playback.rates = SUPPORTED_RATES; spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; spec->pcm_playback.formats = SUPPORTED_FORMATS; spec->nv_dp_workaround = true; return 0; } static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int err = simple_playback_build_pcms(codec); if (!err) { struct hda_pcm *info = get_pcm_rec(spec, 0); info->own_chmap = true; } return err; } static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; struct hda_pcm *info; struct snd_pcm_chmap *chmap; int err; err = simple_playback_build_controls(codec); if (err < 0) return err; /* add channel maps */ info = get_pcm_rec(spec, 0); err = snd_pcm_add_chmap_ctls(info->pcm, SNDRV_PCM_STREAM_PLAYBACK, snd_pcm_alt_chmaps, 8, 0, &chmap); if (err < 0) return err; switch (codec->preset->vendor_id) { case 0x10de0002: case 0x10de0003: case 0x10de0005: case 0x10de0006: chmap->channel_mask = (1U << 2) | (1U << 8); break; case 0x10de0007: chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); } return 0; } static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) { struct hdmi_spec *spec; int err = patch_nvhdmi_2ch(codec); if (err < 0) return err; spec = codec->spec; spec->multiout.max_channels = 8; spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; codec->patch_ops.init = nvhdmi_7x_init_8ch; codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; /* Initialize the audio infoframe channel mask and checksum to something * valid */ nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); return 0; } /* * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: * - 0x10de0015 * - 0x10de0040 */ static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, struct hdac_cea_channel_speaker_allocation *cap, int channels) { if (cap->ca_index == 0x00 && channels == 2) return SNDRV_CTL_TLVT_CHMAP_FIXED; /* If the speaker allocation matches the channel count, it is OK. */ if (cap->channels != channels) return -1; /* all channels are remappable freely */ return SNDRV_CTL_TLVT_CHMAP_VAR; } static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, int ca, int chs, unsigned char *map) { if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) return -EINVAL; return 0; } /* map from pin NID to port; port is 0-based */ /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) { return pin_nid - 4; } /* reverse-map from port to pin NID: see above */ static int nvhdmi_port2pin(struct hda_codec *codec, int port) { return port + 4; } static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { .pin2port = nvhdmi_pin2port, .pin_eld_notify = generic_acomp_pin_eld_notify, .master_bind = generic_acomp_master_bind, .master_unbind = generic_acomp_master_unbind, }; static int patch_nvhdmi(struct hda_codec *codec) { struct hdmi_spec *spec; int err; err = alloc_generic_hdmi(codec); if (err < 0) return err; codec->dp_mst = true; spec = codec->spec; err = hdmi_parse_codec(codec); if (err < 0) { generic_spec_free(codec); return err; } generic_hdmi_init_per_pins(codec); spec->dyn_pin_out = true; spec->chmap.ops.chmap_cea_alloc_validate_get_type = nvhdmi_chmap_cea_alloc_validate_get_type; spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; spec->nv_dp_workaround = true; codec->link_down_at_suspend = 1; generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); return 0; } static int patch_nvhdmi_legacy(struct hda_codec *codec) { struct hdmi_spec *spec; int err; err = patch_generic_hdmi(codec); if (err) return err; spec = codec->spec; spec->dyn_pin_out = true; spec->chmap.ops.chmap_cea_alloc_validate_get_type = nvhdmi_chmap_cea_alloc_validate_get_type; spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; spec->nv_dp_workaround = true; codec->link_down_at_suspend = 1; return 0; } /* * The HDA codec on NVIDIA Tegra contains two scratch registers that are * accessed using vendor-defined verbs. These registers can be used for * interoperability between the HDA and HDMI drivers. */ /* Audio Function Group node */ #define NVIDIA_AFG_NID 0x01 /* * The SCRATCH0 register is used to notify the HDMI codec of changes in audio * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to * be raised in the HDMI codec. The remainder of the bits is arbitrary. This * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an * additional bit (at position 30) to signal the validity of the format. * * | 31 | 30 | 29 16 | 15 0 | * +---------+-------+--------+--------+ * | TRIGGER | VALID | UNUSED | FORMAT | * +-----------------------------------| * * Note that for the trigger bit to take effect it needs to change value * (i.e. it needs to be toggled). The trigger bit is not applicable from * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt * trigger to hdmi. */ #define NVIDIA_SET_HOST_INTR 0xf80 #define NVIDIA_GET_SCRATCH0 0xfa6 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa #define NVIDIA_SCRATCH_TRIGGER (1 << 7) #define NVIDIA_SCRATCH_VALID (1 << 6) #define NVIDIA_GET_SCRATCH1 0xfab #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf /* * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, * the format is invalidated so that the HDMI codec can be disabled. */ static void tegra_hdmi_set_format(struct hda_codec *codec, hda_nid_t cvt_nid, unsigned int format) { unsigned int value; unsigned int nid = NVIDIA_AFG_NID; struct hdmi_spec *spec = codec->spec; /* * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. * This resulted in moving scratch registers from audio function * group to converter widget context. So CVT NID should be used for * scratch register read/write for DP MST supported Tegra HDA codec. */ if (codec->dp_mst) nid = cvt_nid; /* bits [31:30] contain the trigger and valid bits */ value = snd_hda_codec_read(codec, nid, 0, NVIDIA_GET_SCRATCH0, 0); value = (value >> 24) & 0xff; /* bits [15:0] are used to store the HDA format */ snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_SCRATCH0_BYTE0, (format >> 0) & 0xff); snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_SCRATCH0_BYTE1, (format >> 8) & 0xff); /* bits [16:24] are unused */ snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_SCRATCH0_BYTE2, 0); /* * Bit 30 signals that the data is valid and hence that HDMI audio can * be enabled. */ if (format == 0) value &= ~NVIDIA_SCRATCH_VALID; else value |= NVIDIA_SCRATCH_VALID; if (spec->hdmi_intr_trig_ctrl) { /* * For Tegra HDA Codec design from TEGRA234 onwards, the * Interrupt to hdmi driver is triggered by writing * non-zero values to verb 0xF80 instead of 31st bit of * scratch register. */ snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_SCRATCH0_BYTE3, value); snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_HOST_INTR, 0x1); } else { /* * Whenever the 31st trigger bit is toggled, an interrupt is raised * in the HDMI codec. The HDMI driver will use that as trigger * to update its configuration. */ value ^= NVIDIA_SCRATCH_TRIGGER; snd_hda_codec_write(codec, nid, 0, NVIDIA_SET_SCRATCH0_BYTE3, value); } } static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, struct hda_codec *codec, unsigned int stream_tag, unsigned int format, struct snd_pcm_substream *substream) { int err; err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, format, substream); if (err < 0) return err; /* notify the HDMI codec of the format change */ tegra_hdmi_set_format(codec, hinfo->nid, format); return 0; } static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, struct hda_codec *codec, struct snd_pcm_substream *substream) { /* invalidate the format in the HDMI codec */ tegra_hdmi_set_format(codec, hinfo->nid, 0); return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); } static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) { struct hdmi_spec *spec = codec->spec; unsigned int i; for (i = 0; i < spec->num_pins; i++) { struct hda_pcm *pcm = get_pcm_rec(spec, i); if (pcm->pcm_type == type) return pcm; } return NULL; } static int tegra_hdmi_build_pcms(struct hda_codec *codec) { struct hda_pcm_stream *stream; struct hda_pcm *pcm; int err; err = generic_hdmi_build_pcms(codec); if (err < 0) return err; pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); if (!pcm) return -ENODEV; /* * Override ->prepare() and ->cleanup() operations to notify the HDMI * codec about format changes. */ stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; stream->ops.prepare = tegra_hdmi_pcm_prepare; stream->ops.cleanup = tegra_hdmi_pcm_cleanup; return 0; } static int tegra_hdmi_init(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int i, err; err = hdmi_parse_codec(codec); if (err < 0) { generic_spec_free(codec); return err; } for (i = 0; i < spec->num_cvts; i++) snd_hda_codec_write(codec, spec->cvt_nids[i], 0, AC_VERB_SET_DIGI_CONVERT_1, AC_DIG1_ENABLE); generic_hdmi_init_per_pins(codec); codec->depop_delay = 10; codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; spec->chmap.ops.chmap_cea_alloc_validate_get_type = nvhdmi_chmap_cea_alloc_validate_get_type; spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; spec->chmap.ops.chmap_cea_alloc_validate_get_type = nvhdmi_chmap_cea_alloc_validate_get_type; spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; spec->nv_dp_workaround = true; return 0; } static int patch_tegra_hdmi(struct hda_codec *codec) { int err; err = alloc_generic_hdmi(codec); if (err < 0) return err; return tegra_hdmi_init(codec); } static int patch_tegra234_hdmi(struct hda_codec *codec) { struct hdmi_spec *spec; int err; err = alloc_generic_hdmi(codec); if (err < 0) return err; codec->dp_mst = true; spec = codec->spec; spec->dyn_pin_out = true; spec->hdmi_intr_trig_ctrl = true; return tegra_hdmi_init(codec); } /* * ATI/AMD-specific implementations */ #define is_amdhdmi_rev3_or_later(codec) \ ((codec)->core.vendor_id == 0x1002aa01 && \ ((codec)->core.revision_id & 0xff00) >= 0x0300) #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a #define ATI_VERB_SET_HBR_CONTROL 0x77c #define ATI_VERB_SET_MULTICHANNEL_1 0x785 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a #define ATI_VERB_GET_HBR_CONTROL 0xf7c #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 /* AMD specific HDA cvt verbs */ #define ATI_VERB_SET_RAMP_RATE 0x770 #define ATI_VERB_GET_RAMP_RATE 0xf70 #define ATI_OUT_ENABLE 0x1 #define ATI_MULTICHANNEL_MODE_PAIRED 0 #define ATI_MULTICHANNEL_MODE_SINGLE 1 #define ATI_HBR_CAPABLE 0x01 #define ATI_HBR_ENABLE 0x10 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, int dev_id, unsigned char *buf, int *eld_size) { WARN_ON(dev_id != 0); /* call hda_eld.c ATI/AMD-specific function */ return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, is_amdhdmi_rev3_or_later(codec)); } static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, int ca, int active_channels, int conn_type) { WARN_ON(dev_id != 0); snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); } static int atihdmi_paired_swap_fc_lfe(int pos) { /* * ATI/AMD have automatic FC/LFE swap built-in * when in pairwise mapping mode. */ switch (pos) { /* see channel_allocations[].speakers[] */ case 2: return 3; case 3: return 2; default: break; } return pos; } static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, int ca, int chs, unsigned char *map) { struct hdac_cea_channel_speaker_allocation *cap; int i, j; /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ cap = snd_hdac_get_ch_alloc_from_ca(ca); for (i = 0; i < chs; ++i) { int mask = snd_hdac_chmap_to_spk_mask(map[i]); bool ok = false; bool companion_ok = false; if (!mask) continue; for (j = 0 + i % 2; j < 8; j += 2) { int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); if (cap->speakers[chan_idx] == mask) { /* channel is in a supported position */ ok = true; if (i % 2 == 0 && i + 1 < chs) { /* even channel, check the odd companion */ int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); int comp_mask_act = cap->speakers[comp_chan_idx]; if (comp_mask_req == comp_mask_act) companion_ok = true; else return -EINVAL; } break; } } if (!ok) return -EINVAL; if (companion_ok) i++; /* companion channel already checked */ } return 0; } static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, hda_nid_t pin_nid, int hdmi_slot, int stream_channel) { struct hda_codec *codec = hdac_to_hda_codec(hdac); int verb; int ati_channel_setup = 0; if (hdmi_slot > 7) return -EINVAL; if (!has_amd_full_remap_support(codec)) { hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); /* In case this is an odd slot but without stream channel, do not * disable the slot since the corresponding even slot could have a * channel. In case neither have a channel, the slot pair will be * disabled when this function is called for the even slot. */ if (hdmi_slot % 2 != 0 && stream_channel == 0xf) return 0; hdmi_slot -= hdmi_slot % 2; if (stream_channel != 0xf) stream_channel -= stream_channel % 2; } verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ if (stream_channel != 0xf) ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); } static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, hda_nid_t pin_nid, int asp_slot) { struct hda_codec *codec = hdac_to_hda_codec(hdac); bool was_odd = false; int ati_asp_slot = asp_slot; int verb; int ati_channel_setup; if (asp_slot > 7) return -EINVAL; if (!has_amd_full_remap_support(codec)) { ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); if (ati_asp_slot % 2 != 0) { ati_asp_slot -= 1; was_odd = true; } } verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); if (!(ati_channel_setup & ATI_OUT_ENABLE)) return 0xf; return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; } static int atihdmi_paired_chmap_cea_alloc_validate_get_type( struct hdac_chmap *chmap, struct hdac_cea_channel_speaker_allocation *cap, int channels) { int c; /* * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so * we need to take that into account (a single channel may take 2 * channel slots if we need to carry a silent channel next to it). * On Rev3+ AMD codecs this function is not used. */ int chanpairs = 0; /* We only produce even-numbered channel count TLVs */ if ((channels % 2) != 0) return -1; for (c = 0; c < 7; c += 2) { if (cap->speakers[c] || cap->speakers[c+1]) chanpairs++; } if (chanpairs * 2 != channels) return -1; return SNDRV_CTL_TLVT_CHMAP_PAIRED; } static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, struct hdac_cea_channel_speaker_allocation *cap, unsigned int *chmap, int channels) { /* produce paired maps for pre-rev3 ATI/AMD codecs */ int count = 0; int c; for (c = 7; c >= 0; c--) { int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); int spk = cap->speakers[chan]; if (!spk) { /* add N/A channel if the companion channel is occupied */ if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) chmap[count++] = SNDRV_CHMAP_NA; continue; } chmap[count++] = snd_hdac_spk_to_chmap(spk); } WARN_ON(count != channels); } static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, int dev_id, bool hbr) { int hbr_ctl, hbr_ctl_new; WARN_ON(dev_id != 0); hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { if (hbr) hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; else hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; codec_dbg(codec, "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", pin_nid, hbr_ctl == hbr_ctl_new ? "" : "new-", hbr_ctl_new); if (hbr_ctl != hbr_ctl_new) snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_HBR_CONTROL, hbr_ctl_new); } else if (hbr) return -EINVAL; return 0; } static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, hda_nid_t pin_nid, int dev_id, u32 stream_tag, int format) { if (is_amdhdmi_rev3_or_later(codec)) { int ramp_rate = 180; /* default as per AMD spec */ /* disable ramp-up/down for non-pcm as per AMD spec */ if (format & AC_FMT_TYPE_NON_PCM) ramp_rate = 0; snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); } return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, stream_tag, format); } static int atihdmi_init(struct hda_codec *codec) { struct hdmi_spec *spec = codec->spec; int pin_idx, err; err = generic_hdmi_init(codec); if (err) return err; for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); /* make sure downmix information in infoframe is zero */ snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); /* enable channel-wise remap mode if supported */ if (has_amd_full_remap_support(codec)) snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_MULTICHANNEL_MODE, ATI_MULTICHANNEL_MODE_SINGLE); } codec->auto_runtime_pm = 1; return 0; } /* map from pin NID to port; port is 0-based */ /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ static int atihdmi_pin2port(void *audio_ptr, int pin_nid) { return pin_nid / 2 - 1; } /* reverse-map from port to pin NID: see above */ static int atihdmi_port2pin(struct hda_codec *codec, int port) { return port * 2 + 3; } static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { .pin2port = atihdmi_pin2port, .pin_eld_notify = generic_acomp_pin_eld_notify, .master_bind = generic_acomp_master_bind, .master_unbind = generic_acomp_master_unbind, }; static int patch_atihdmi(struct hda_codec *codec) { struct hdmi_spec *spec; struct hdmi_spec_per_cvt *per_cvt; int err, cvt_idx; err = patch_generic_hdmi(codec); if (err) return err; codec->patch_ops.init = atihdmi_init; spec = codec->spec; spec->static_pcm_mapping = true; spec->ops.pin_get_eld = atihdmi_pin_get_eld; spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; spec->ops.setup_stream = atihdmi_setup_stream; spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; if (!has_amd_full_remap_support(codec)) { /* override to ATI/AMD-specific versions with pairwise mapping */ spec->chmap.ops.chmap_cea_alloc_validate_get_type = atihdmi_paired_chmap_cea_alloc_validate_get_type; spec->chmap.ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap; spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; } /* ATI/AMD converters do not advertise all of their capabilities */ for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { per_cvt = get_cvt(spec, cvt_idx); per_cvt->channels_max = max(per_cvt->channels_max, 8u); per_cvt->rates |= SUPPORTED_RATES; per_cvt->formats |= SUPPORTED_FORMATS; per_cvt->maxbps = max(per_cvt->maxbps, 24u); } spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing * the link-down as is. Tell the core to allow it. */ codec->link_down_at_suspend = 1; generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); return 0; } /* VIA HDMI Implementation */ #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ static int patch_via_hdmi(struct hda_codec *codec) { return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); } static int patch_gf_hdmi(struct hda_codec *codec) { int err; err = patch_generic_hdmi(codec); if (err) return err; /* * Glenfly GPUs have two codecs, stream switches from one codec to * another, need to do actual clean-ups in codec_cleanup_stream */ codec->no_sticky_stream = 1; return 0; } /* * patch entries */ static const struct hda_device_id snd_hda_id_hdmi[] = { HDA_CODEC_ENTRY(0x00147a47, "Loongson HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), /* 17 is known to be absent */ HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi), HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi), HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI", patch_i915_adlp_hdmi), HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi), HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi), HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), /* special ID for generic HDMI */ HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), {} /* terminator */ }; MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("HDMI HD-audio codec"); MODULE_ALIAS("snd-hda-codec-intelhdmi"); MODULE_ALIAS("snd-hda-codec-nvhdmi"); MODULE_ALIAS("snd-hda-codec-atihdmi"); static struct hda_codec_driver hdmi_driver = { .id = snd_hda_id_hdmi, }; module_hda_codec_driver(hdmi_driver);
linux-master
sound/pci/hda/patch_hdmi.c