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// SPDX-License-Identifier: GPL-2.0-only
/*
* FM Driver for Connectivity chip of Texas Instruments.
* This sub-module of FM driver implements FM RX functionality.
*
* Copyright (C) 2011 Texas Instruments
* Author: Raja Mani <[email protected]>
* Author: Manjunatha Halli <[email protected]>
*/
#include "fmdrv.h"
#include "fmdrv_common.h"
#include "fmdrv_rx.h"
void fm_rx_reset_rds_cache(struct fmdev *fmdev)
{
fmdev->rx.rds.flag = FM_RDS_DISABLE;
fmdev->rx.rds.last_blk_idx = 0;
fmdev->rx.rds.wr_idx = 0;
fmdev->rx.rds.rd_idx = 0;
if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
fmdev->irq_info.mask |= FM_LEV_EVENT;
}
void fm_rx_reset_station_info(struct fmdev *fmdev)
{
fmdev->rx.stat_info.picode = FM_NO_PI_CODE;
fmdev->rx.stat_info.afcache_size = 0;
fmdev->rx.stat_info.af_list_max = 0;
}
int fm_rx_set_freq(struct fmdev *fmdev, u32 freq)
{
unsigned long timeleft;
u16 payload, curr_frq, intr_flag;
u32 curr_frq_in_khz;
u32 resp_len;
int ret;
if (freq < fmdev->rx.region.bot_freq || freq > fmdev->rx.region.top_freq) {
fmerr("Invalid frequency %d\n", freq);
return -EINVAL;
}
/* Set audio enable */
payload = FM_RX_AUDIO_ENABLE_I2S_AND_ANALOG;
ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set hilo to automatic selection */
payload = FM_RX_IFFREQ_HILO_AUTOMATIC;
ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Calculate frequency index and set*/
payload = (freq - fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts if we had */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
if (ret < 0)
return ret;
/* Enable FR, BL interrupts */
intr_flag = fmdev->irq_info.mask;
fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT);
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Start tune */
payload = FM_TUNER_PRESET_MODE;
ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
goto exit;
/* Wait for tune ended interrupt */
init_completion(&fmdev->maintask_comp);
timeleft = wait_for_completion_timeout(&fmdev->maintask_comp,
FM_DRV_TX_TIMEOUT);
if (!timeleft) {
fmerr("Timeout(%d sec),didn't get tune ended int\n",
jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
ret = -ETIMEDOUT;
goto exit;
}
/* Read freq back to confirm */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len);
if (ret < 0)
goto exit;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
curr_frq_in_khz = (fmdev->rx.region.bot_freq + ((u32)curr_frq * FM_FREQ_MUL));
if (curr_frq_in_khz != freq) {
pr_info("Frequency is set to (%d) but requested freq is (%d)\n",
curr_frq_in_khz, freq);
}
/* Update local cache */
fmdev->rx.freq = curr_frq_in_khz;
exit:
/* Re-enable default FM interrupts */
fmdev->irq_info.mask = intr_flag;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Reset RDS cache and current station pointers */
fm_rx_reset_rds_cache(fmdev);
fm_rx_reset_station_info(fmdev);
return ret;
}
static int fm_rx_set_channel_spacing(struct fmdev *fmdev, u32 spacing)
{
u16 payload;
int ret;
if (spacing > 0 && spacing <= 50000)
spacing = FM_CHANNEL_SPACING_50KHZ;
else if (spacing > 50000 && spacing <= 100000)
spacing = FM_CHANNEL_SPACING_100KHZ;
else
spacing = FM_CHANNEL_SPACING_200KHZ;
/* set channel spacing */
payload = spacing;
ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.region.chanl_space = spacing * FM_FREQ_MUL;
return ret;
}
int fm_rx_seek(struct fmdev *fmdev, u32 seek_upward,
u32 wrap_around, u32 spacing)
{
u32 resp_len;
u16 curr_frq, next_frq, last_frq;
u16 payload, int_reason, intr_flag;
u16 offset, space_idx;
unsigned long timeleft;
int ret;
/* Set channel spacing */
ret = fm_rx_set_channel_spacing(fmdev, spacing);
if (ret < 0) {
fmerr("Failed to set channel spacing\n");
return ret;
}
/* Read the current frequency from chip */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL,
sizeof(curr_frq), &curr_frq, &resp_len);
if (ret < 0)
return ret;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
last_frq = (fmdev->rx.region.top_freq - fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
/* Check the offset in order to be aligned to the channel spacing*/
space_idx = fmdev->rx.region.chanl_space / FM_FREQ_MUL;
offset = curr_frq % space_idx;
next_frq = seek_upward ? curr_frq + space_idx /* Seek Up */ :
curr_frq - space_idx /* Seek Down */ ;
/*
* Add or subtract offset in order to stay aligned to the channel
* spacing.
*/
if ((short)next_frq < 0)
next_frq = last_frq - offset;
else if (next_frq > last_frq)
next_frq = 0 + offset;
again:
/* Set calculated next frequency to perform seek */
payload = next_frq;
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set search direction (0:Seek Down, 1:Seek Up) */
payload = (seek_upward ? FM_SEARCH_DIRECTION_UP : FM_SEARCH_DIRECTION_DOWN);
ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts if we had */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
if (ret < 0)
return ret;
/* Enable FR, BL interrupts */
intr_flag = fmdev->irq_info.mask;
fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT);
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Start seek */
payload = FM_TUNER_AUTONOMOUS_SEARCH_MODE;
ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Wait for tune ended/band limit reached interrupt */
init_completion(&fmdev->maintask_comp);
timeleft = wait_for_completion_timeout(&fmdev->maintask_comp,
FM_DRV_RX_SEEK_TIMEOUT);
if (!timeleft) {
fmerr("Timeout(%d sec),didn't get tune ended int\n",
jiffies_to_msecs(FM_DRV_RX_SEEK_TIMEOUT) / 1000);
return -ENODATA;
}
int_reason = fmdev->irq_info.flag & (FM_TUNE_COMPLETE | FM_BAND_LIMIT);
/* Re-enable default FM interrupts */
fmdev->irq_info.mask = intr_flag;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
if (int_reason & FM_BL_EVENT) {
if (wrap_around == 0) {
fmdev->rx.freq = seek_upward ?
fmdev->rx.region.top_freq :
fmdev->rx.region.bot_freq;
} else {
fmdev->rx.freq = seek_upward ?
fmdev->rx.region.bot_freq :
fmdev->rx.region.top_freq;
/* Calculate frequency index to write */
next_frq = (fmdev->rx.freq -
fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
goto again;
}
} else {
/* Read freq to know where operation tune operation stopped */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2,
&curr_frq, &resp_len);
if (ret < 0)
return ret;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
fmdev->rx.freq = (fmdev->rx.region.bot_freq +
((u32)curr_frq * FM_FREQ_MUL));
}
/* Reset RDS cache and current station pointers */
fm_rx_reset_rds_cache(fmdev);
fm_rx_reset_station_info(fmdev);
return ret;
}
int fm_rx_set_volume(struct fmdev *fmdev, u16 vol_to_set)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (vol_to_set > FM_RX_VOLUME_MAX) {
fmerr("Volume is not within(%d-%d) range\n",
FM_RX_VOLUME_MIN, FM_RX_VOLUME_MAX);
return -EINVAL;
}
vol_to_set *= FM_RX_VOLUME_GAIN_STEP;
payload = vol_to_set;
ret = fmc_send_cmd(fmdev, VOLUME_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.volume = vol_to_set;
return ret;
}
/* Get volume */
int fm_rx_get_volume(struct fmdev *fmdev, u16 *curr_vol)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_vol == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_vol = fmdev->rx.volume / FM_RX_VOLUME_GAIN_STEP;
return 0;
}
/* To get current band's bottom and top frequency */
int fm_rx_get_band_freq_range(struct fmdev *fmdev, u32 *bot_freq, u32 *top_freq)
{
if (bot_freq != NULL)
*bot_freq = fmdev->rx.region.bot_freq;
if (top_freq != NULL)
*top_freq = fmdev->rx.region.top_freq;
return 0;
}
/* Returns current band index (0-Europe/US; 1-Japan) */
void fm_rx_get_region(struct fmdev *fmdev, u8 *region)
{
*region = fmdev->rx.region.fm_band;
}
/* Sets band (0-Europe/US; 1-Japan) */
int fm_rx_set_region(struct fmdev *fmdev, u8 region_to_set)
{
u16 payload;
u32 new_frq = 0;
int ret;
if (region_to_set != FM_BAND_EUROPE_US &&
region_to_set != FM_BAND_JAPAN) {
fmerr("Invalid band\n");
return -EINVAL;
}
if (fmdev->rx.region.fm_band == region_to_set) {
fmerr("Requested band is already configured\n");
return 0;
}
/* Send cmd to set the band */
payload = (u16)region_to_set;
ret = fmc_send_cmd(fmdev, BAND_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmc_update_region_info(fmdev, region_to_set);
/* Check whether current RX frequency is within band boundary */
if (fmdev->rx.freq < fmdev->rx.region.bot_freq)
new_frq = fmdev->rx.region.bot_freq;
else if (fmdev->rx.freq > fmdev->rx.region.top_freq)
new_frq = fmdev->rx.region.top_freq;
if (new_frq) {
fmdbg("Current freq is not within band limit boundary,switching to %d KHz\n",
new_frq);
/* Current RX frequency is not in range. So, update it */
ret = fm_rx_set_freq(fmdev, new_frq);
}
return ret;
}
/* Reads current mute mode (Mute Off/On/Attenuate)*/
int fm_rx_get_mute_mode(struct fmdev *fmdev, u8 *curr_mute_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_mute_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_mute_mode = fmdev->rx.mute_mode;
return 0;
}
static int fm_config_rx_mute_reg(struct fmdev *fmdev)
{
u16 payload, muteval;
int ret;
muteval = 0;
switch (fmdev->rx.mute_mode) {
case FM_MUTE_ON:
muteval = FM_RX_AC_MUTE_MODE;
break;
case FM_MUTE_OFF:
muteval = FM_RX_UNMUTE_MODE;
break;
case FM_MUTE_ATTENUATE:
muteval = FM_RX_SOFT_MUTE_FORCE_MODE;
break;
}
if (fmdev->rx.rf_depend_mute == FM_RX_RF_DEPENDENT_MUTE_ON)
muteval |= FM_RX_RF_DEP_MODE;
else
muteval &= ~FM_RX_RF_DEP_MODE;
payload = muteval;
ret = fmc_send_cmd(fmdev, MUTE_STATUS_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
/* Configures mute mode (Mute Off/On/Attenuate) */
int fm_rx_set_mute_mode(struct fmdev *fmdev, u8 mute_mode_toset)
{
u8 org_state;
int ret;
if (fmdev->rx.mute_mode == mute_mode_toset)
return 0;
org_state = fmdev->rx.mute_mode;
fmdev->rx.mute_mode = mute_mode_toset;
ret = fm_config_rx_mute_reg(fmdev);
if (ret < 0) {
fmdev->rx.mute_mode = org_state;
return ret;
}
return 0;
}
/* Gets RF dependent soft mute mode enable/disable status */
int fm_rx_get_rfdepend_softmute(struct fmdev *fmdev, u8 *curr_mute_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_mute_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_mute_mode = fmdev->rx.rf_depend_mute;
return 0;
}
/* Sets RF dependent soft mute mode */
int fm_rx_set_rfdepend_softmute(struct fmdev *fmdev, u8 rfdepend_mute)
{
u8 org_state;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_ON &&
rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_OFF) {
fmerr("Invalid RF dependent soft mute\n");
return -EINVAL;
}
if (fmdev->rx.rf_depend_mute == rfdepend_mute)
return 0;
org_state = fmdev->rx.rf_depend_mute;
fmdev->rx.rf_depend_mute = rfdepend_mute;
ret = fm_config_rx_mute_reg(fmdev);
if (ret < 0) {
fmdev->rx.rf_depend_mute = org_state;
return ret;
}
return 0;
}
/* Returns the signal strength level of current channel */
int fm_rx_get_rssi_level(struct fmdev *fmdev, u16 *rssilvl)
{
__be16 curr_rssi_lel;
u32 resp_len;
int ret;
if (rssilvl == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
/* Read current RSSI level */
ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2,
&curr_rssi_lel, &resp_len);
if (ret < 0)
return ret;
*rssilvl = be16_to_cpu(curr_rssi_lel);
return 0;
}
/*
* Sets the signal strength level that once reached
* will stop the auto search process
*/
int fm_rx_set_rssi_threshold(struct fmdev *fmdev, short rssi_lvl_toset)
{
u16 payload;
int ret;
if (rssi_lvl_toset < FM_RX_RSSI_THRESHOLD_MIN ||
rssi_lvl_toset > FM_RX_RSSI_THRESHOLD_MAX) {
fmerr("Invalid RSSI threshold level\n");
return -EINVAL;
}
payload = (u16)rssi_lvl_toset;
ret = fmc_send_cmd(fmdev, SEARCH_LVL_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.rssi_threshold = rssi_lvl_toset;
return 0;
}
/* Returns current RX RSSI threshold value */
int fm_rx_get_rssi_threshold(struct fmdev *fmdev, short *curr_rssi_lvl)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_rssi_lvl == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_rssi_lvl = fmdev->rx.rssi_threshold;
return 0;
}
/* Sets RX stereo/mono modes */
int fm_rx_set_stereo_mono(struct fmdev *fmdev, u16 mode)
{
u16 payload;
int ret;
if (mode != FM_STEREO_MODE && mode != FM_MONO_MODE) {
fmerr("Invalid mode\n");
return -EINVAL;
}
/* Set stereo/mono mode */
payload = (u16)mode;
ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set stereo blending mode */
payload = FM_STEREO_SOFT_BLEND;
ret = fmc_send_cmd(fmdev, MOST_BLEND_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
/* Gets current RX stereo/mono mode */
int fm_rx_get_stereo_mono(struct fmdev *fmdev, u16 *mode)
{
__be16 curr_mode;
u32 resp_len;
int ret;
if (mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2,
&curr_mode, &resp_len);
if (ret < 0)
return ret;
*mode = be16_to_cpu(curr_mode);
return 0;
}
/* Choose RX de-emphasis filter mode (50us/75us) */
int fm_rx_set_deemphasis_mode(struct fmdev *fmdev, u16 mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (mode != FM_RX_EMPHASIS_FILTER_50_USEC &&
mode != FM_RX_EMPHASIS_FILTER_75_USEC) {
fmerr("Invalid rx de-emphasis mode (%d)\n", mode);
return -EINVAL;
}
payload = mode;
ret = fmc_send_cmd(fmdev, DEMPH_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.deemphasis_mode = mode;
return 0;
}
/* Gets current RX de-emphasis filter mode */
int fm_rx_get_deemph_mode(struct fmdev *fmdev, u16 *curr_deemphasis_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_deemphasis_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_deemphasis_mode = fmdev->rx.deemphasis_mode;
return 0;
}
/* Enable/Disable RX RDS */
int fm_rx_set_rds_mode(struct fmdev *fmdev, u8 rds_en_dis)
{
u16 payload;
int ret;
if (rds_en_dis != FM_RDS_ENABLE && rds_en_dis != FM_RDS_DISABLE) {
fmerr("Invalid rds option\n");
return -EINVAL;
}
if (rds_en_dis == FM_RDS_ENABLE
&& fmdev->rx.rds.flag == FM_RDS_DISABLE) {
/* Turn on RX RDS and RDS circuit */
payload = FM_RX_PWR_SET_FM_AND_RDS_BLK_ON;
ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Clear and reset RDS FIFO */
payload = FM_RX_RDS_FLUSH_FIFO;
ret = fmc_send_cmd(fmdev, RDS_CNTRL_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts. */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2,
NULL, NULL);
if (ret < 0)
return ret;
/* Set RDS FIFO threshold value */
payload = FM_RX_RDS_FIFO_THRESHOLD;
ret = fmc_send_cmd(fmdev, RDS_MEM_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Enable RDS interrupt */
fmdev->irq_info.mask |= FM_RDS_EVENT;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0) {
fmdev->irq_info.mask &= ~FM_RDS_EVENT;
return ret;
}
/* Update our local flag */
fmdev->rx.rds.flag = FM_RDS_ENABLE;
} else if (rds_en_dis == FM_RDS_DISABLE
&& fmdev->rx.rds.flag == FM_RDS_ENABLE) {
/* Turn off RX RDS */
payload = FM_RX_PWR_SET_FM_ON_RDS_OFF;
ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Reset RDS pointers */
fmdev->rx.rds.last_blk_idx = 0;
fmdev->rx.rds.wr_idx = 0;
fmdev->rx.rds.rd_idx = 0;
fm_rx_reset_station_info(fmdev);
/* Update RDS local cache */
fmdev->irq_info.mask &= ~(FM_RDS_EVENT);
fmdev->rx.rds.flag = FM_RDS_DISABLE;
}
return 0;
}
/* Returns current RX RDS enable/disable status */
int fm_rx_get_rds_mode(struct fmdev *fmdev, u8 *curr_rds_en_dis)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_rds_en_dis == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_rds_en_dis = fmdev->rx.rds.flag;
return 0;
}
/* Sets RDS operation mode (RDS/RDBS) */
int fm_rx_set_rds_system(struct fmdev *fmdev, u8 rds_mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (rds_mode != FM_RDS_SYSTEM_RDS && rds_mode != FM_RDS_SYSTEM_RBDS) {
fmerr("Invalid rds mode\n");
return -EINVAL;
}
/* Set RDS operation mode */
payload = (u16)rds_mode;
ret = fmc_send_cmd(fmdev, RDS_SYSTEM_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.rds_mode = rds_mode;
return 0;
}
/* Configures Alternate Frequency switch mode */
int fm_rx_set_af_switch(struct fmdev *fmdev, u8 af_mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (af_mode != FM_RX_RDS_AF_SWITCH_MODE_ON &&
af_mode != FM_RX_RDS_AF_SWITCH_MODE_OFF) {
fmerr("Invalid af mode\n");
return -EINVAL;
}
/* Enable/disable low RSSI interrupt based on af_mode */
if (af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
fmdev->irq_info.mask |= FM_LEV_EVENT;
else
fmdev->irq_info.mask &= ~FM_LEV_EVENT;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.af_mode = af_mode;
return 0;
}
/* Returns Alternate Frequency switch status */
int fm_rx_get_af_switch(struct fmdev *fmdev, u8 *af_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (af_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*af_mode = fmdev->rx.af_mode;
return 0;
}
| linux-master | drivers/media/radio/wl128x/fmdrv_rx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* FM Driver for Connectivity chip of Texas Instruments.
* This file provides interfaces to V4L2 subsystem.
*
* This module registers with V4L2 subsystem as Radio
* data system interface (/dev/radio). During the registration,
* it will expose two set of function pointers.
*
* 1) File operation related API (open, close, read, write, poll...etc).
* 2) Set of V4L2 IOCTL complaint API.
*
* Copyright (C) 2011 Texas Instruments
* Author: Raja Mani <[email protected]>
* Author: Manjunatha Halli <[email protected]>
*/
#include <linux/export.h>
#include "fmdrv.h"
#include "fmdrv_v4l2.h"
#include "fmdrv_common.h"
#include "fmdrv_rx.h"
#include "fmdrv_tx.h"
static struct video_device gradio_dev;
static u8 radio_disconnected;
/* -- V4L2 RADIO (/dev/radioX) device file operation interfaces --- */
/* Read RX RDS data */
static ssize_t fm_v4l2_fops_read(struct file *file, char __user * buf,
size_t count, loff_t *ppos)
{
u8 rds_mode;
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
if (!radio_disconnected) {
fmerr("FM device is already disconnected\n");
return -EIO;
}
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
/* Turn on RDS mode if it is disabled */
ret = fm_rx_get_rds_mode(fmdev, &rds_mode);
if (ret < 0) {
fmerr("Unable to read current rds mode\n");
goto read_unlock;
}
if (rds_mode == FM_RDS_DISABLE) {
ret = fmc_set_rds_mode(fmdev, FM_RDS_ENABLE);
if (ret < 0) {
fmerr("Failed to enable rds mode\n");
goto read_unlock;
}
}
/* Copy RDS data from internal buffer to user buffer */
ret = fmc_transfer_rds_from_internal_buff(fmdev, file, buf, count);
read_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
/* Write TX RDS data */
static ssize_t fm_v4l2_fops_write(struct file *file, const char __user * buf,
size_t count, loff_t *ppos)
{
struct tx_rds rds;
int ret;
struct fmdev *fmdev;
ret = copy_from_user(&rds, buf, sizeof(rds));
rds.text[sizeof(rds.text) - 1] = '\0';
fmdbg("(%d)type: %d, text %s, af %d\n",
ret, rds.text_type, rds.text, rds.af_freq);
if (ret)
return -EFAULT;
fmdev = video_drvdata(file);
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
fm_tx_set_radio_text(fmdev, rds.text, rds.text_type);
fm_tx_set_af(fmdev, rds.af_freq);
mutex_unlock(&fmdev->mutex);
return sizeof(rds);
}
static __poll_t fm_v4l2_fops_poll(struct file *file, struct poll_table_struct *pts)
{
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
mutex_lock(&fmdev->mutex);
ret = fmc_is_rds_data_available(fmdev, file, pts);
mutex_unlock(&fmdev->mutex);
if (ret < 0)
return EPOLLIN | EPOLLRDNORM;
return 0;
}
/*
* Handle open request for "/dev/radioX" device.
* Start with FM RX mode as default.
*/
static int fm_v4l2_fops_open(struct file *file)
{
int ret;
struct fmdev *fmdev = NULL;
/* Don't allow multiple open */
if (radio_disconnected) {
fmerr("FM device is already opened\n");
return -EBUSY;
}
fmdev = video_drvdata(file);
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
ret = fmc_prepare(fmdev);
if (ret < 0) {
fmerr("Unable to prepare FM CORE\n");
goto open_unlock;
}
fmdbg("Load FM RX firmware..\n");
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret < 0) {
fmerr("Unable to load FM RX firmware\n");
goto open_unlock;
}
radio_disconnected = 1;
open_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
static int fm_v4l2_fops_release(struct file *file)
{
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
if (!radio_disconnected) {
fmdbg("FM device is already closed\n");
return 0;
}
mutex_lock(&fmdev->mutex);
ret = fmc_set_mode(fmdev, FM_MODE_OFF);
if (ret < 0) {
fmerr("Unable to turn off the chip\n");
goto release_unlock;
}
ret = fmc_release(fmdev);
if (ret < 0) {
fmerr("FM CORE release failed\n");
goto release_unlock;
}
radio_disconnected = 0;
release_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
/* V4L2 RADIO (/dev/radioX) device IOCTL interfaces */
static int fm_v4l2_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
strscpy(capability->driver, FM_DRV_NAME, sizeof(capability->driver));
strscpy(capability->card, FM_DRV_CARD_SHORT_NAME,
sizeof(capability->card));
sprintf(capability->bus_info, "UART");
return 0;
}
static int fm_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct fmdev *fmdev = container_of(ctrl->handler,
struct fmdev, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_TUNE_ANTENNA_CAPACITOR:
ctrl->val = fm_tx_get_tune_cap_val(fmdev);
break;
default:
fmwarn("%s: Unknown IOCTL: %d\n", __func__, ctrl->id);
break;
}
return 0;
}
static int fm_v4l2_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct fmdev *fmdev = container_of(ctrl->handler,
struct fmdev, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME: /* set volume */
return fm_rx_set_volume(fmdev, (u16)ctrl->val);
case V4L2_CID_AUDIO_MUTE: /* set mute */
return fmc_set_mute_mode(fmdev, (u8)ctrl->val);
case V4L2_CID_TUNE_POWER_LEVEL:
/* set TX power level - ext control */
return fm_tx_set_pwr_lvl(fmdev, (u8)ctrl->val);
case V4L2_CID_TUNE_PREEMPHASIS:
return fm_tx_set_preemph_filter(fmdev, (u8) ctrl->val);
default:
return -EINVAL;
}
}
static int fm_v4l2_vidioc_g_audio(struct file *file, void *priv,
struct v4l2_audio *audio)
{
memset(audio, 0, sizeof(*audio));
strscpy(audio->name, "Radio", sizeof(audio->name));
audio->capability = V4L2_AUDCAP_STEREO;
return 0;
}
static int fm_v4l2_vidioc_s_audio(struct file *file, void *priv,
const struct v4l2_audio *audio)
{
if (audio->index != 0)
return -EINVAL;
return 0;
}
/* Get tuner attributes. If current mode is NOT RX, return error */
static int fm_v4l2_vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *tuner)
{
struct fmdev *fmdev = video_drvdata(file);
u32 bottom_freq;
u32 top_freq;
u16 stereo_mono_mode;
u16 rssilvl;
int ret;
if (tuner->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
ret = fm_rx_get_band_freq_range(fmdev, &bottom_freq, &top_freq);
if (ret != 0)
return ret;
ret = fm_rx_get_stereo_mono(fmdev, &stereo_mono_mode);
if (ret != 0)
return ret;
ret = fm_rx_get_rssi_level(fmdev, &rssilvl);
if (ret != 0)
return ret;
strscpy(tuner->name, "FM", sizeof(tuner->name));
tuner->type = V4L2_TUNER_RADIO;
/* Store rangelow and rangehigh freq in unit of 62.5 Hz */
tuner->rangelow = bottom_freq * 16;
tuner->rangehigh = top_freq * 16;
tuner->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO |
((fmdev->rx.rds.flag == FM_RDS_ENABLE) ? V4L2_TUNER_SUB_RDS : 0);
tuner->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS |
V4L2_TUNER_CAP_LOW |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP;
tuner->audmode = (stereo_mono_mode ?
V4L2_TUNER_MODE_MONO : V4L2_TUNER_MODE_STEREO);
/*
* Actual rssi value lies in between -128 to +127.
* Convert this range from 0 to 255 by adding +128
*/
rssilvl += 128;
/*
* Return signal strength value should be within 0 to 65535.
* Find out correct signal radio by multiplying (65535/255) = 257
*/
tuner->signal = rssilvl * 257;
tuner->afc = 0;
return ret;
}
/*
* Set tuner attributes. If current mode is NOT RX, set to RX.
* Currently, we set only audio mode (mono/stereo) and RDS state (on/off).
* Should we set other tuner attributes, too?
*/
static int fm_v4l2_vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *tuner)
{
struct fmdev *fmdev = video_drvdata(file);
u16 aud_mode;
u8 rds_mode;
int ret;
if (tuner->index != 0)
return -EINVAL;
aud_mode = (tuner->audmode == V4L2_TUNER_MODE_STEREO) ?
FM_STEREO_MODE : FM_MONO_MODE;
rds_mode = (tuner->rxsubchans & V4L2_TUNER_SUB_RDS) ?
FM_RDS_ENABLE : FM_RDS_DISABLE;
if (fmdev->curr_fmmode != FM_MODE_RX) {
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret < 0) {
fmerr("Failed to set RX mode\n");
return ret;
}
}
ret = fmc_set_stereo_mono(fmdev, aud_mode);
if (ret < 0) {
fmerr("Failed to set RX stereo/mono mode\n");
return ret;
}
ret = fmc_set_rds_mode(fmdev, rds_mode);
if (ret < 0)
fmerr("Failed to set RX RDS mode\n");
return ret;
}
/* Get tuner or modulator radio frequency */
static int fm_v4l2_vidioc_g_freq(struct file *file, void *priv,
struct v4l2_frequency *freq)
{
struct fmdev *fmdev = video_drvdata(file);
int ret;
ret = fmc_get_freq(fmdev, &freq->frequency);
if (ret < 0) {
fmerr("Failed to get frequency\n");
return ret;
}
/* Frequency unit of 62.5 Hz*/
freq->frequency = (u32) freq->frequency * 16;
return 0;
}
/* Set tuner or modulator radio frequency */
static int fm_v4l2_vidioc_s_freq(struct file *file, void *priv,
const struct v4l2_frequency *freq)
{
struct fmdev *fmdev = video_drvdata(file);
/*
* As V4L2_TUNER_CAP_LOW is set 1 user sends the frequency
* in units of 62.5 Hz.
*/
return fmc_set_freq(fmdev, freq->frequency / 16);
}
/* Set hardware frequency seek. If current mode is NOT RX, set it RX. */
static int fm_v4l2_vidioc_s_hw_freq_seek(struct file *file, void *priv,
const struct v4l2_hw_freq_seek *seek)
{
struct fmdev *fmdev = video_drvdata(file);
int ret;
if (file->f_flags & O_NONBLOCK)
return -EWOULDBLOCK;
if (fmdev->curr_fmmode != FM_MODE_RX) {
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret != 0) {
fmerr("Failed to set RX mode\n");
return ret;
}
}
ret = fm_rx_seek(fmdev, seek->seek_upward, seek->wrap_around,
seek->spacing);
if (ret < 0)
fmerr("RX seek failed - %d\n", ret);
return ret;
}
/* Get modulator attributes. If mode is not TX, return no attributes. */
static int fm_v4l2_vidioc_g_modulator(struct file *file, void *priv,
struct v4l2_modulator *mod)
{
struct fmdev *fmdev = video_drvdata(file);
if (mod->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
mod->txsubchans = ((fmdev->tx_data.aud_mode == FM_STEREO_MODE) ?
V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO) |
((fmdev->tx_data.rds.flag == FM_RDS_ENABLE) ?
V4L2_TUNER_SUB_RDS : 0);
mod->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS |
V4L2_TUNER_CAP_LOW;
return 0;
}
/* Set modulator attributes. If mode is not TX, set to TX. */
static int fm_v4l2_vidioc_s_modulator(struct file *file, void *priv,
const struct v4l2_modulator *mod)
{
struct fmdev *fmdev = video_drvdata(file);
u8 rds_mode;
u16 aud_mode;
int ret;
if (mod->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_TX) {
ret = fmc_set_mode(fmdev, FM_MODE_TX);
if (ret != 0) {
fmerr("Failed to set TX mode\n");
return ret;
}
}
aud_mode = (mod->txsubchans & V4L2_TUNER_SUB_STEREO) ?
FM_STEREO_MODE : FM_MONO_MODE;
rds_mode = (mod->txsubchans & V4L2_TUNER_SUB_RDS) ?
FM_RDS_ENABLE : FM_RDS_DISABLE;
ret = fm_tx_set_stereo_mono(fmdev, aud_mode);
if (ret < 0) {
fmerr("Failed to set mono/stereo mode for TX\n");
return ret;
}
ret = fm_tx_set_rds_mode(fmdev, rds_mode);
if (ret < 0)
fmerr("Failed to set rds mode for TX\n");
return ret;
}
static const struct v4l2_file_operations fm_drv_fops = {
.owner = THIS_MODULE,
.read = fm_v4l2_fops_read,
.write = fm_v4l2_fops_write,
.poll = fm_v4l2_fops_poll,
.unlocked_ioctl = video_ioctl2,
.open = fm_v4l2_fops_open,
.release = fm_v4l2_fops_release,
};
static const struct v4l2_ctrl_ops fm_ctrl_ops = {
.s_ctrl = fm_v4l2_s_ctrl,
.g_volatile_ctrl = fm_g_volatile_ctrl,
};
static const struct v4l2_ioctl_ops fm_drv_ioctl_ops = {
.vidioc_querycap = fm_v4l2_vidioc_querycap,
.vidioc_g_audio = fm_v4l2_vidioc_g_audio,
.vidioc_s_audio = fm_v4l2_vidioc_s_audio,
.vidioc_g_tuner = fm_v4l2_vidioc_g_tuner,
.vidioc_s_tuner = fm_v4l2_vidioc_s_tuner,
.vidioc_g_frequency = fm_v4l2_vidioc_g_freq,
.vidioc_s_frequency = fm_v4l2_vidioc_s_freq,
.vidioc_s_hw_freq_seek = fm_v4l2_vidioc_s_hw_freq_seek,
.vidioc_g_modulator = fm_v4l2_vidioc_g_modulator,
.vidioc_s_modulator = fm_v4l2_vidioc_s_modulator
};
/* V4L2 RADIO device parent structure */
static const struct video_device fm_viddev_template = {
.fops = &fm_drv_fops,
.ioctl_ops = &fm_drv_ioctl_ops,
.name = FM_DRV_NAME,
.release = video_device_release_empty,
/*
* To ensure both the tuner and modulator ioctls are accessible we
* set the vfl_dir to M2M to indicate this.
*
* It is not really a mem2mem device of course, but it can both receive
* and transmit using the same radio device. It's the only radio driver
* that does this and it should really be split in two radio devices,
* but that would affect applications using this driver.
*/
.vfl_dir = VFL_DIR_M2M,
.device_caps = V4L2_CAP_HW_FREQ_SEEK | V4L2_CAP_TUNER | V4L2_CAP_RADIO |
V4L2_CAP_MODULATOR | V4L2_CAP_AUDIO |
V4L2_CAP_READWRITE | V4L2_CAP_RDS_CAPTURE,
};
int fm_v4l2_init_video_device(struct fmdev *fmdev, int radio_nr)
{
struct v4l2_ctrl *ctrl;
int ret;
strscpy(fmdev->v4l2_dev.name, FM_DRV_NAME,
sizeof(fmdev->v4l2_dev.name));
ret = v4l2_device_register(NULL, &fmdev->v4l2_dev);
if (ret < 0)
return ret;
/* Init mutex for core locking */
mutex_init(&fmdev->mutex);
/* Setup FM driver's V4L2 properties */
gradio_dev = fm_viddev_template;
video_set_drvdata(&gradio_dev, fmdev);
gradio_dev.lock = &fmdev->mutex;
gradio_dev.v4l2_dev = &fmdev->v4l2_dev;
/* Register with V4L2 subsystem as RADIO device */
if (video_register_device(&gradio_dev, VFL_TYPE_RADIO, radio_nr)) {
v4l2_device_unregister(&fmdev->v4l2_dev);
fmerr("Could not register video device\n");
return -ENOMEM;
}
fmdev->radio_dev = &gradio_dev;
/* Register to v4l2 ctrl handler framework */
fmdev->radio_dev->ctrl_handler = &fmdev->ctrl_handler;
ret = v4l2_ctrl_handler_init(&fmdev->ctrl_handler, 5);
if (ret < 0) {
fmerr("(fmdev): Can't init ctrl handler\n");
v4l2_ctrl_handler_free(&fmdev->ctrl_handler);
video_unregister_device(fmdev->radio_dev);
v4l2_device_unregister(&fmdev->v4l2_dev);
return -EBUSY;
}
/*
* Following controls are handled by V4L2 control framework.
* Added in ascending ID order.
*/
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_AUDIO_VOLUME, FM_RX_VOLUME_MIN,
FM_RX_VOLUME_MAX, 1, FM_RX_VOLUME_MAX);
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1);
v4l2_ctrl_new_std_menu(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_PREEMPHASIS, V4L2_PREEMPHASIS_75_uS,
0, V4L2_PREEMPHASIS_75_uS);
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_POWER_LEVEL, FM_PWR_LVL_LOW,
FM_PWR_LVL_HIGH, 1, FM_PWR_LVL_HIGH);
ctrl = v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_ANTENNA_CAPACITOR, 0,
255, 1, 255);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
return 0;
}
void *fm_v4l2_deinit_video_device(void)
{
struct fmdev *fmdev;
fmdev = video_get_drvdata(&gradio_dev);
/* Unregister to v4l2 ctrl handler framework*/
v4l2_ctrl_handler_free(&fmdev->ctrl_handler);
/* Unregister RADIO device from V4L2 subsystem */
video_unregister_device(&gradio_dev);
v4l2_device_unregister(&fmdev->v4l2_dev);
return fmdev;
}
| linux-master | drivers/media/radio/wl128x/fmdrv_v4l2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/media/radio/radio-si4713.c
*
* Platform Driver for Silicon Labs Si4713 FM Radio Transmitter:
*
* Copyright (c) 2008 Instituto Nokia de Tecnologia - INdT
* Contact: Eduardo Valentin <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/slab.h>
#include <media/v4l2-device.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include "si4713.h"
/* module parameters */
static int radio_nr = -1; /* radio device minor (-1 ==> auto assign) */
module_param(radio_nr, int, 0);
MODULE_PARM_DESC(radio_nr,
"Minor number for radio device (-1 ==> auto assign)");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Eduardo Valentin <[email protected]>");
MODULE_DESCRIPTION("Platform driver for Si4713 FM Radio Transmitter");
MODULE_VERSION("0.0.1");
MODULE_ALIAS("platform:radio-si4713");
/* Driver state struct */
struct radio_si4713_device {
struct v4l2_device v4l2_dev;
struct video_device radio_dev;
struct mutex lock;
};
/* radio_si4713_fops - file operations interface */
static const struct v4l2_file_operations radio_si4713_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = v4l2_fh_release,
.poll = v4l2_ctrl_poll,
/* Note: locking is done at the subdev level in the i2c driver. */
.unlocked_ioctl = video_ioctl2,
};
/* Video4Linux Interface */
/* radio_si4713_querycap - query device capabilities */
static int radio_si4713_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
strscpy(capability->driver, "radio-si4713", sizeof(capability->driver));
strscpy(capability->card, "Silicon Labs Si4713 Modulator",
sizeof(capability->card));
strscpy(capability->bus_info, "platform:radio-si4713",
sizeof(capability->bus_info));
return 0;
}
/*
* v4l2 ioctl call backs.
* we are just a wrapper for v4l2_sub_devs.
*/
static inline struct v4l2_device *get_v4l2_dev(struct file *file)
{
return &((struct radio_si4713_device *)video_drvdata(file))->v4l2_dev;
}
static int radio_si4713_g_modulator(struct file *file, void *p,
struct v4l2_modulator *vm)
{
return v4l2_device_call_until_err(get_v4l2_dev(file), 0, tuner,
g_modulator, vm);
}
static int radio_si4713_s_modulator(struct file *file, void *p,
const struct v4l2_modulator *vm)
{
return v4l2_device_call_until_err(get_v4l2_dev(file), 0, tuner,
s_modulator, vm);
}
static int radio_si4713_g_frequency(struct file *file, void *p,
struct v4l2_frequency *vf)
{
return v4l2_device_call_until_err(get_v4l2_dev(file), 0, tuner,
g_frequency, vf);
}
static int radio_si4713_s_frequency(struct file *file, void *p,
const struct v4l2_frequency *vf)
{
return v4l2_device_call_until_err(get_v4l2_dev(file), 0, tuner,
s_frequency, vf);
}
static long radio_si4713_default(struct file *file, void *p,
bool valid_prio, unsigned int cmd, void *arg)
{
return v4l2_device_call_until_err(get_v4l2_dev(file), 0, core,
ioctl, cmd, arg);
}
static const struct v4l2_ioctl_ops radio_si4713_ioctl_ops = {
.vidioc_querycap = radio_si4713_querycap,
.vidioc_g_modulator = radio_si4713_g_modulator,
.vidioc_s_modulator = radio_si4713_s_modulator,
.vidioc_g_frequency = radio_si4713_g_frequency,
.vidioc_s_frequency = radio_si4713_s_frequency,
.vidioc_log_status = v4l2_ctrl_log_status,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_default = radio_si4713_default,
};
/* radio_si4713_vdev_template - video device interface */
static const struct video_device radio_si4713_vdev_template = {
.fops = &radio_si4713_fops,
.name = "radio-si4713",
.release = video_device_release_empty,
.ioctl_ops = &radio_si4713_ioctl_ops,
.vfl_dir = VFL_DIR_TX,
};
/* Platform driver interface */
/* radio_si4713_pdriver_probe - probe for the device */
static int radio_si4713_pdriver_probe(struct platform_device *pdev)
{
struct radio_si4713_platform_data *pdata = pdev->dev.platform_data;
struct radio_si4713_device *rsdev;
struct v4l2_subdev *sd;
int rval = 0;
if (!pdata) {
dev_err(&pdev->dev, "Cannot proceed without platform data.\n");
rval = -EINVAL;
goto exit;
}
rsdev = devm_kzalloc(&pdev->dev, sizeof(*rsdev), GFP_KERNEL);
if (!rsdev) {
dev_err(&pdev->dev, "Failed to alloc video device.\n");
rval = -ENOMEM;
goto exit;
}
mutex_init(&rsdev->lock);
rval = v4l2_device_register(&pdev->dev, &rsdev->v4l2_dev);
if (rval) {
dev_err(&pdev->dev, "Failed to register v4l2 device.\n");
goto exit;
}
sd = i2c_get_clientdata(pdata->subdev);
rval = v4l2_device_register_subdev(&rsdev->v4l2_dev, sd);
if (rval) {
dev_err(&pdev->dev, "Cannot get v4l2 subdevice\n");
goto unregister_v4l2_dev;
}
rsdev->radio_dev = radio_si4713_vdev_template;
rsdev->radio_dev.v4l2_dev = &rsdev->v4l2_dev;
rsdev->radio_dev.ctrl_handler = sd->ctrl_handler;
/* Serialize all access to the si4713 */
rsdev->radio_dev.lock = &rsdev->lock;
rsdev->radio_dev.device_caps = V4L2_CAP_MODULATOR | V4L2_CAP_RDS_OUTPUT;
video_set_drvdata(&rsdev->radio_dev, rsdev);
if (video_register_device(&rsdev->radio_dev, VFL_TYPE_RADIO, radio_nr)) {
dev_err(&pdev->dev, "Could not register video device.\n");
rval = -EIO;
goto unregister_v4l2_dev;
}
dev_info(&pdev->dev, "New device successfully probed\n");
goto exit;
unregister_v4l2_dev:
v4l2_device_unregister(&rsdev->v4l2_dev);
exit:
return rval;
}
/* radio_si4713_pdriver_remove - remove the device */
static void radio_si4713_pdriver_remove(struct platform_device *pdev)
{
struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
struct radio_si4713_device *rsdev;
rsdev = container_of(v4l2_dev, struct radio_si4713_device, v4l2_dev);
video_unregister_device(&rsdev->radio_dev);
v4l2_device_unregister(&rsdev->v4l2_dev);
}
static struct platform_driver radio_si4713_pdriver = {
.driver = {
.name = "radio-si4713",
},
.probe = radio_si4713_pdriver_probe,
.remove_new = radio_si4713_pdriver_remove,
};
module_platform_driver(radio_si4713_pdriver);
| linux-master | drivers/media/radio/si4713/radio-platform-si4713.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
* All rights reserved.
*/
/* kernel includes */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/usb.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/input.h>
#include <linux/mutex.h>
#include <linux/i2c.h>
/* V4l includes */
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <linux/platform_data/media/si4713.h>
#include "si4713.h"
/* driver and module definitions */
MODULE_AUTHOR("Dinesh Ram <[email protected]>");
MODULE_DESCRIPTION("Si4713 FM Transmitter USB driver");
MODULE_LICENSE("GPL v2");
/* The Device announces itself as Cygnal Integrated Products, Inc. */
#define USB_SI4713_VENDOR 0x10c4
#define USB_SI4713_PRODUCT 0x8244
#define BUFFER_LENGTH 64
#define USB_TIMEOUT 1000
#define USB_RESP_TIMEOUT 50000
/* USB Device ID List */
static const struct usb_device_id usb_si4713_usb_device_table[] = {
{USB_DEVICE_AND_INTERFACE_INFO(USB_SI4713_VENDOR, USB_SI4713_PRODUCT,
USB_CLASS_HID, 0, 0) },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, usb_si4713_usb_device_table);
struct si4713_usb_device {
struct usb_device *usbdev;
struct usb_interface *intf;
struct video_device vdev;
struct v4l2_device v4l2_dev;
struct v4l2_subdev *v4l2_subdev;
struct mutex lock;
struct i2c_adapter i2c_adapter;
u8 *buffer;
};
static inline struct si4713_usb_device *to_si4713_dev(struct v4l2_device *v4l2_dev)
{
return container_of(v4l2_dev, struct si4713_usb_device, v4l2_dev);
}
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *v)
{
struct si4713_usb_device *radio = video_drvdata(file);
strscpy(v->driver, "radio-usb-si4713", sizeof(v->driver));
strscpy(v->card, "Si4713 FM Transmitter", sizeof(v->card));
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
return 0;
}
static int vidioc_g_modulator(struct file *file, void *priv,
struct v4l2_modulator *vm)
{
struct si4713_usb_device *radio = video_drvdata(file);
return v4l2_subdev_call(radio->v4l2_subdev, tuner, g_modulator, vm);
}
static int vidioc_s_modulator(struct file *file, void *priv,
const struct v4l2_modulator *vm)
{
struct si4713_usb_device *radio = video_drvdata(file);
return v4l2_subdev_call(radio->v4l2_subdev, tuner, s_modulator, vm);
}
static int vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *vf)
{
struct si4713_usb_device *radio = video_drvdata(file);
return v4l2_subdev_call(radio->v4l2_subdev, tuner, s_frequency, vf);
}
static int vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *vf)
{
struct si4713_usb_device *radio = video_drvdata(file);
return v4l2_subdev_call(radio->v4l2_subdev, tuner, g_frequency, vf);
}
static const struct v4l2_ioctl_ops usb_si4713_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_modulator = vidioc_g_modulator,
.vidioc_s_modulator = vidioc_s_modulator,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
.vidioc_log_status = v4l2_ctrl_log_status,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/* File system interface */
static const struct v4l2_file_operations usb_si4713_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = v4l2_fh_release,
.poll = v4l2_ctrl_poll,
.unlocked_ioctl = video_ioctl2,
};
static void usb_si4713_video_device_release(struct v4l2_device *v4l2_dev)
{
struct si4713_usb_device *radio = to_si4713_dev(v4l2_dev);
struct i2c_adapter *adapter = &radio->i2c_adapter;
i2c_del_adapter(adapter);
v4l2_device_unregister(&radio->v4l2_dev);
kfree(radio->buffer);
kfree(radio);
}
/*
* This command sequence emulates the behaviour of the Windows driver.
* The structure of these commands was determined by sniffing the
* usb traffic of the device during startup.
* Most likely, these commands make some queries to the device.
* Commands are sent to enquire parameters like the bus mode,
* component revision, boot mode, the device serial number etc.
*
* These commands are necessary to be sent in this order during startup.
* The device fails to powerup if these commands are not sent.
*
* The complete list of startup commands is given in the start_seq table below.
*/
static int si4713_send_startup_command(struct si4713_usb_device *radio)
{
unsigned long until_jiffies = jiffies + usecs_to_jiffies(USB_RESP_TIMEOUT) + 1;
u8 *buffer = radio->buffer;
int retval;
/* send the command */
retval = usb_control_msg(radio->usbdev, usb_sndctrlpipe(radio->usbdev, 0),
0x09, 0x21, 0x033f, 0, radio->buffer,
BUFFER_LENGTH, USB_TIMEOUT);
if (retval < 0)
return retval;
for (;;) {
/* receive the response */
retval = usb_control_msg(radio->usbdev, usb_rcvctrlpipe(radio->usbdev, 0),
0x01, 0xa1, 0x033f, 0, radio->buffer,
BUFFER_LENGTH, USB_TIMEOUT);
if (retval < 0)
return retval;
if (!radio->buffer[1]) {
/* USB traffic sniffing showed that some commands require
* additional checks. */
switch (buffer[1]) {
case 0x32:
if (radio->buffer[2] == 0)
return 0;
break;
case 0x14:
case 0x12:
if (radio->buffer[2] & SI4713_CTS)
return 0;
break;
case 0x06:
if ((radio->buffer[2] & SI4713_CTS) && radio->buffer[9] == 0x08)
return 0;
break;
default:
return 0;
}
}
if (time_is_before_jiffies(until_jiffies))
return -EIO;
msleep(3);
}
return retval;
}
struct si4713_start_seq_table {
int len;
u8 payload[8];
};
/*
* Some of the startup commands that could be recognized are :
* (0x03): Get serial number of the board (Response : CB000-00-00)
* (0x06, 0x03, 0x03, 0x08, 0x01, 0x0f) : Get Component revision
*/
static const struct si4713_start_seq_table start_seq[] = {
{ 1, { 0x03 } },
{ 2, { 0x32, 0x7f } },
{ 6, { 0x06, 0x03, 0x03, 0x08, 0x01, 0x0f } },
{ 2, { 0x14, 0x02 } },
{ 2, { 0x09, 0x90 } },
{ 3, { 0x08, 0x90, 0xfa } },
{ 2, { 0x36, 0x01 } },
{ 2, { 0x05, 0x03 } },
{ 7, { 0x06, 0x00, 0x06, 0x0e, 0x01, 0x0f, 0x05 } },
{ 1, { 0x12 } },
/* Commands that are sent after pressing the 'Initialize'
button in the windows application */
{ 1, { 0x03 } },
{ 1, { 0x01 } },
{ 2, { 0x09, 0x90 } },
{ 3, { 0x08, 0x90, 0xfa } },
{ 1, { 0x34 } },
{ 2, { 0x35, 0x01 } },
{ 2, { 0x36, 0x01 } },
{ 2, { 0x30, 0x09 } },
{ 4, { 0x30, 0x06, 0x00, 0xe2 } },
{ 3, { 0x31, 0x01, 0x30 } },
{ 3, { 0x31, 0x04, 0x09 } },
{ 2, { 0x05, 0x02 } },
{ 6, { 0x06, 0x03, 0x03, 0x08, 0x01, 0x0f } },
};
static int si4713_start_seq(struct si4713_usb_device *radio)
{
int retval = 0;
int i;
radio->buffer[0] = 0x3f;
for (i = 0; i < ARRAY_SIZE(start_seq); i++) {
int len = start_seq[i].len;
const u8 *payload = start_seq[i].payload;
memcpy(radio->buffer + 1, payload, len);
memset(radio->buffer + len + 1, 0, BUFFER_LENGTH - 1 - len);
retval = si4713_send_startup_command(radio);
}
return retval;
}
static struct i2c_board_info si4713_board_info = {
I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
};
struct si4713_command_table {
int command_id;
u8 payload[8];
};
/*
* Structure of a command :
* Byte 1 : 0x3f (always)
* Byte 2 : 0x06 (send a command)
* Byte 3 : Unknown
* Byte 4 : Number of arguments + 1 (for the command byte)
* Byte 5 : Number of response bytes
*/
static struct si4713_command_table command_table[] = {
{ SI4713_CMD_POWER_UP, { 0x00, SI4713_PWUP_NARGS + 1, SI4713_PWUP_NRESP} },
{ SI4713_CMD_GET_REV, { 0x03, 0x01, SI4713_GETREV_NRESP } },
{ SI4713_CMD_POWER_DOWN, { 0x00, 0x01, SI4713_PWDN_NRESP} },
{ SI4713_CMD_SET_PROPERTY, { 0x00, SI4713_SET_PROP_NARGS + 1, SI4713_SET_PROP_NRESP } },
{ SI4713_CMD_GET_PROPERTY, { 0x00, SI4713_GET_PROP_NARGS + 1, SI4713_GET_PROP_NRESP } },
{ SI4713_CMD_TX_TUNE_FREQ, { 0x03, SI4713_TXFREQ_NARGS + 1, SI4713_TXFREQ_NRESP } },
{ SI4713_CMD_TX_TUNE_POWER, { 0x03, SI4713_TXPWR_NARGS + 1, SI4713_TXPWR_NRESP } },
{ SI4713_CMD_TX_TUNE_MEASURE, { 0x03, SI4713_TXMEA_NARGS + 1, SI4713_TXMEA_NRESP } },
{ SI4713_CMD_TX_TUNE_STATUS, { 0x00, SI4713_TXSTATUS_NARGS + 1, SI4713_TXSTATUS_NRESP } },
{ SI4713_CMD_TX_ASQ_STATUS, { 0x03, SI4713_ASQSTATUS_NARGS + 1, SI4713_ASQSTATUS_NRESP } },
{ SI4713_CMD_GET_INT_STATUS, { 0x03, 0x01, SI4713_GET_STATUS_NRESP } },
{ SI4713_CMD_TX_RDS_BUFF, { 0x03, SI4713_RDSBUFF_NARGS + 1, SI4713_RDSBUFF_NRESP } },
{ SI4713_CMD_TX_RDS_PS, { 0x00, SI4713_RDSPS_NARGS + 1, SI4713_RDSPS_NRESP } },
};
static int send_command(struct si4713_usb_device *radio, u8 *payload, char *data, int len)
{
int retval;
radio->buffer[0] = 0x3f;
radio->buffer[1] = 0x06;
memcpy(radio->buffer + 2, payload, 3);
memcpy(radio->buffer + 5, data, len);
memset(radio->buffer + 5 + len, 0, BUFFER_LENGTH - 5 - len);
/* send the command */
retval = usb_control_msg(radio->usbdev, usb_sndctrlpipe(radio->usbdev, 0),
0x09, 0x21, 0x033f, 0, radio->buffer,
BUFFER_LENGTH, USB_TIMEOUT);
return retval < 0 ? retval : 0;
}
static int si4713_i2c_read(struct si4713_usb_device *radio, char *data, int len)
{
unsigned long until_jiffies = jiffies + usecs_to_jiffies(USB_RESP_TIMEOUT) + 1;
int retval;
/* receive the response */
for (;;) {
retval = usb_control_msg(radio->usbdev,
usb_rcvctrlpipe(radio->usbdev, 0),
0x01, 0xa1, 0x033f, 0, radio->buffer,
BUFFER_LENGTH, USB_TIMEOUT);
if (retval < 0)
return retval;
/*
* Check that we get a valid reply back (buffer[1] == 0) and
* that CTS is set before returning, otherwise we wait and try
* again. The i2c driver also does the CTS check, but the timeouts
* used there are much too small for this USB driver, so we wait
* for it here.
*/
if (radio->buffer[1] == 0 && (radio->buffer[2] & SI4713_CTS)) {
memcpy(data, radio->buffer + 2, len);
return 0;
}
if (time_is_before_jiffies(until_jiffies)) {
/* Zero the status value, ensuring CTS isn't set */
data[0] = 0;
return 0;
}
msleep(3);
}
}
static int si4713_i2c_write(struct si4713_usb_device *radio, char *data, int len)
{
int retval = -EINVAL;
int i;
if (len > BUFFER_LENGTH - 5)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(command_table); i++) {
if (data[0] == command_table[i].command_id)
retval = send_command(radio, command_table[i].payload,
data, len);
}
return retval < 0 ? retval : 0;
}
static int si4713_transfer(struct i2c_adapter *i2c_adapter,
struct i2c_msg *msgs, int num)
{
struct si4713_usb_device *radio = i2c_get_adapdata(i2c_adapter);
int retval = -EINVAL;
int i;
for (i = 0; i < num; i++) {
if (msgs[i].flags & I2C_M_RD)
retval = si4713_i2c_read(radio, msgs[i].buf, msgs[i].len);
else
retval = si4713_i2c_write(radio, msgs[i].buf, msgs[i].len);
if (retval)
break;
}
return retval ? retval : num;
}
static u32 si4713_functionality(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm si4713_algo = {
.master_xfer = si4713_transfer,
.functionality = si4713_functionality,
};
/* This name value shows up in the sysfs filename associated
with this I2C adapter */
static const struct i2c_adapter si4713_i2c_adapter_template = {
.name = "si4713-i2c",
.owner = THIS_MODULE,
.algo = &si4713_algo,
};
static int si4713_register_i2c_adapter(struct si4713_usb_device *radio)
{
radio->i2c_adapter = si4713_i2c_adapter_template;
/* set up sysfs linkage to our parent device */
radio->i2c_adapter.dev.parent = &radio->usbdev->dev;
i2c_set_adapdata(&radio->i2c_adapter, radio);
return i2c_add_adapter(&radio->i2c_adapter);
}
/* check if the device is present and register with v4l and usb if it is */
static int usb_si4713_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
struct si4713_usb_device *radio;
struct i2c_adapter *adapter;
struct v4l2_subdev *sd;
int retval;
dev_info(&intf->dev, "Si4713 development board discovered: (%04X:%04X)\n",
id->idVendor, id->idProduct);
/* Initialize local device structure */
radio = kzalloc(sizeof(struct si4713_usb_device), GFP_KERNEL);
if (radio)
radio->buffer = kmalloc(BUFFER_LENGTH, GFP_KERNEL);
if (!radio || !radio->buffer) {
dev_err(&intf->dev, "kmalloc for si4713_usb_device failed\n");
kfree(radio);
return -ENOMEM;
}
mutex_init(&radio->lock);
radio->usbdev = interface_to_usbdev(intf);
radio->intf = intf;
usb_set_intfdata(intf, &radio->v4l2_dev);
retval = si4713_start_seq(radio);
if (retval < 0)
goto err_v4l2;
retval = v4l2_device_register(&intf->dev, &radio->v4l2_dev);
if (retval < 0) {
dev_err(&intf->dev, "couldn't register v4l2_device\n");
goto err_v4l2;
}
retval = si4713_register_i2c_adapter(radio);
if (retval < 0) {
dev_err(&intf->dev, "could not register i2c device\n");
goto err_i2cdev;
}
adapter = &radio->i2c_adapter;
sd = v4l2_i2c_new_subdev_board(&radio->v4l2_dev, adapter,
&si4713_board_info, NULL);
radio->v4l2_subdev = sd;
if (!sd) {
dev_err(&intf->dev, "cannot get v4l2 subdevice\n");
retval = -ENODEV;
goto del_adapter;
}
radio->vdev.ctrl_handler = sd->ctrl_handler;
radio->v4l2_dev.release = usb_si4713_video_device_release;
strscpy(radio->vdev.name, radio->v4l2_dev.name,
sizeof(radio->vdev.name));
radio->vdev.v4l2_dev = &radio->v4l2_dev;
radio->vdev.fops = &usb_si4713_fops;
radio->vdev.ioctl_ops = &usb_si4713_ioctl_ops;
radio->vdev.lock = &radio->lock;
radio->vdev.release = video_device_release_empty;
radio->vdev.vfl_dir = VFL_DIR_TX;
radio->vdev.device_caps = V4L2_CAP_MODULATOR | V4L2_CAP_RDS_OUTPUT;
video_set_drvdata(&radio->vdev, radio);
retval = video_register_device(&radio->vdev, VFL_TYPE_RADIO, -1);
if (retval < 0) {
dev_err(&intf->dev, "could not register video device\n");
goto del_adapter;
}
dev_info(&intf->dev, "V4L2 device registered as %s\n",
video_device_node_name(&radio->vdev));
return 0;
del_adapter:
i2c_del_adapter(adapter);
err_i2cdev:
v4l2_device_unregister(&radio->v4l2_dev);
err_v4l2:
kfree(radio->buffer);
kfree(radio);
return retval;
}
static void usb_si4713_disconnect(struct usb_interface *intf)
{
struct si4713_usb_device *radio = to_si4713_dev(usb_get_intfdata(intf));
dev_info(&intf->dev, "Si4713 development board now disconnected\n");
mutex_lock(&radio->lock);
usb_set_intfdata(intf, NULL);
video_unregister_device(&radio->vdev);
v4l2_device_disconnect(&radio->v4l2_dev);
mutex_unlock(&radio->lock);
v4l2_device_put(&radio->v4l2_dev);
}
/* USB subsystem interface */
static struct usb_driver usb_si4713_driver = {
.name = "radio-usb-si4713",
.probe = usb_si4713_probe,
.disconnect = usb_si4713_disconnect,
.id_table = usb_si4713_usb_device_table,
};
module_usb_driver(usb_si4713_driver);
| linux-master | drivers/media/radio/si4713/radio-usb-si4713.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/media/radio/si4713-i2c.c
*
* Silicon Labs Si4713 FM Radio Transmitter I2C commands.
*
* Copyright (c) 2009 Nokia Corporation
* Contact: Eduardo Valentin <[email protected]>
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include "si4713.h"
/* module parameters */
static int debug;
module_param(debug, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(debug, "Debug level (0 - 2)");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Eduardo Valentin <[email protected]>");
MODULE_DESCRIPTION("I2C driver for Si4713 FM Radio Transmitter");
MODULE_VERSION("0.0.1");
#define DEFAULT_RDS_PI 0x00
#define DEFAULT_RDS_PTY 0x00
#define DEFAULT_RDS_DEVIATION 0x00C8
#define DEFAULT_RDS_PS_REPEAT_COUNT 0x0003
#define DEFAULT_LIMITER_RTIME 0x1392
#define DEFAULT_LIMITER_DEV 0x102CA
#define DEFAULT_PILOT_FREQUENCY 0x4A38
#define DEFAULT_PILOT_DEVIATION 0x1A5E
#define DEFAULT_ACOMP_ATIME 0x0000
#define DEFAULT_ACOMP_RTIME 0xF4240L
#define DEFAULT_ACOMP_GAIN 0x0F
#define DEFAULT_ACOMP_THRESHOLD (-0x28)
#define DEFAULT_MUTE 0x01
#define DEFAULT_POWER_LEVEL 88
#define DEFAULT_FREQUENCY 8800
#define DEFAULT_PREEMPHASIS FMPE_EU
#define DEFAULT_TUNE_RNL 0xFF
#define to_si4713_device(sd) container_of(sd, struct si4713_device, sd)
/* frequency domain transformation (using times 10 to avoid floats) */
#define FREQDEV_UNIT 100000
#define FREQV4L2_MULTI 625
#define si4713_to_v4l2(f) ((f * FREQDEV_UNIT) / FREQV4L2_MULTI)
#define v4l2_to_si4713(f) ((f * FREQV4L2_MULTI) / FREQDEV_UNIT)
#define FREQ_RANGE_LOW 7600
#define FREQ_RANGE_HIGH 10800
#define MAX_ARGS 7
#define RDS_BLOCK 8
#define RDS_BLOCK_CLEAR 0x03
#define RDS_BLOCK_LOAD 0x04
#define RDS_RADIOTEXT_2A 0x20
#define RDS_RADIOTEXT_BLK_SIZE 4
#define RDS_RADIOTEXT_INDEX_MAX 0x0F
#define RDS_CARRIAGE_RETURN 0x0D
#define rds_ps_nblocks(len) ((len / RDS_BLOCK) + (len % RDS_BLOCK ? 1 : 0))
#define get_status_bit(p, b, m) (((p) & (m)) >> (b))
#define set_bits(p, v, b, m) (((p) & ~(m)) | ((v) << (b)))
#define ATTACK_TIME_UNIT 500
#define POWER_OFF 0x00
#define POWER_ON 0x01
#define msb(x) ((u8)((u16) x >> 8))
#define lsb(x) ((u8)((u16) x & 0x00FF))
#define compose_u16(msb, lsb) (((u16)msb << 8) | lsb)
#define check_command_failed(status) (!(status & SI4713_CTS) || \
(status & SI4713_ERR))
/* mute definition */
#define set_mute(p) (((p) & 1) | (((p) & 1) << 1))
#ifdef DEBUG
#define DBG_BUFFER(device, message, buffer, size) \
{ \
int i; \
char str[(size)*5]; \
for (i = 0; i < size; i++) \
sprintf(str + i * 5, " 0x%02x", buffer[i]); \
v4l2_dbg(2, debug, device, "%s:%s\n", message, str); \
}
#else
#define DBG_BUFFER(device, message, buffer, size)
#endif
/*
* Values for limiter release time (sorted by second column)
* device release
* value time (us)
*/
static long limiter_times[] = {
2000, 250,
1000, 500,
510, 1000,
255, 2000,
170, 3000,
127, 4020,
102, 5010,
85, 6020,
73, 7010,
64, 7990,
57, 8970,
51, 10030,
25, 20470,
17, 30110,
13, 39380,
10, 51190,
8, 63690,
7, 73140,
6, 85330,
5, 102390,
};
/*
* Values for audio compression release time (sorted by second column)
* device release
* value time (us)
*/
static unsigned long acomp_rtimes[] = {
0, 100000,
1, 200000,
2, 350000,
3, 525000,
4, 1000000,
};
/*
* Values for preemphasis (sorted by second column)
* device preemphasis
* value value (v4l2)
*/
static unsigned long preemphasis_values[] = {
FMPE_DISABLED, V4L2_PREEMPHASIS_DISABLED,
FMPE_EU, V4L2_PREEMPHASIS_50_uS,
FMPE_USA, V4L2_PREEMPHASIS_75_uS,
};
static int usecs_to_dev(unsigned long usecs, unsigned long const array[],
int size)
{
int i;
int rval = -EINVAL;
for (i = 0; i < size / 2; i++)
if (array[(i * 2) + 1] >= usecs) {
rval = array[i * 2];
break;
}
return rval;
}
/* si4713_handler: IRQ handler, just complete work */
static irqreturn_t si4713_handler(int irq, void *dev)
{
struct si4713_device *sdev = dev;
v4l2_dbg(2, debug, &sdev->sd,
"%s: sending signal to completion work.\n", __func__);
complete(&sdev->work);
return IRQ_HANDLED;
}
/*
* si4713_send_command - sends a command to si4713 and waits its response
* @sdev: si4713_device structure for the device we are communicating
* @command: command id
* @args: command arguments we are sending (up to 7)
* @argn: actual size of @args
* @response: buffer to place the expected response from the device (up to 15)
* @respn: actual size of @response
* @usecs: amount of time to wait before reading the response (in usecs)
*/
static int si4713_send_command(struct si4713_device *sdev, const u8 command,
const u8 args[], const int argn,
u8 response[], const int respn, const int usecs)
{
struct i2c_client *client = v4l2_get_subdevdata(&sdev->sd);
unsigned long until_jiffies;
u8 data1[MAX_ARGS + 1];
int err;
if (!client->adapter)
return -ENODEV;
/* First send the command and its arguments */
data1[0] = command;
memcpy(data1 + 1, args, argn);
DBG_BUFFER(&sdev->sd, "Parameters", data1, argn + 1);
err = i2c_master_send(client, data1, argn + 1);
if (err != argn + 1) {
v4l2_err(&sdev->sd, "Error while sending command 0x%02x\n",
command);
return err < 0 ? err : -EIO;
}
until_jiffies = jiffies + usecs_to_jiffies(usecs) + 1;
/* Wait response from interrupt */
if (client->irq) {
if (!wait_for_completion_timeout(&sdev->work,
usecs_to_jiffies(usecs) + 1))
v4l2_warn(&sdev->sd,
"(%s) Device took too much time to answer.\n",
__func__);
}
do {
err = i2c_master_recv(client, response, respn);
if (err != respn) {
v4l2_err(&sdev->sd,
"Error %d while reading response for command 0x%02x\n",
err, command);
return err < 0 ? err : -EIO;
}
DBG_BUFFER(&sdev->sd, "Response", response, respn);
if (!check_command_failed(response[0]))
return 0;
if (client->irq)
return -EBUSY;
if (usecs <= 1000)
usleep_range(usecs, 1000);
else
usleep_range(1000, 2000);
} while (time_is_after_jiffies(until_jiffies));
return -EBUSY;
}
/*
* si4713_read_property - reads a si4713 property
* @sdev: si4713_device structure for the device we are communicating
* @prop: property identification number
* @pv: property value to be returned on success
*/
static int si4713_read_property(struct si4713_device *sdev, u16 prop, u32 *pv)
{
int err;
u8 val[SI4713_GET_PROP_NRESP];
/*
* .First byte = 0
* .Second byte = property's MSB
* .Third byte = property's LSB
*/
const u8 args[SI4713_GET_PROP_NARGS] = {
0x00,
msb(prop),
lsb(prop),
};
err = si4713_send_command(sdev, SI4713_CMD_GET_PROPERTY,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (err < 0)
return err;
*pv = compose_u16(val[2], val[3]);
v4l2_dbg(1, debug, &sdev->sd,
"%s: property=0x%02x value=0x%02x status=0x%02x\n",
__func__, prop, *pv, val[0]);
return err;
}
/*
* si4713_write_property - modifies a si4713 property
* @sdev: si4713_device structure for the device we are communicating
* @prop: property identification number
* @val: new value for that property
*/
static int si4713_write_property(struct si4713_device *sdev, u16 prop, u16 val)
{
int rval;
u8 resp[SI4713_SET_PROP_NRESP];
/*
* .First byte = 0
* .Second byte = property's MSB
* .Third byte = property's LSB
* .Fourth byte = value's MSB
* .Fifth byte = value's LSB
*/
const u8 args[SI4713_SET_PROP_NARGS] = {
0x00,
msb(prop),
lsb(prop),
msb(val),
lsb(val),
};
rval = si4713_send_command(sdev, SI4713_CMD_SET_PROPERTY,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
DEFAULT_TIMEOUT);
if (rval < 0)
return rval;
v4l2_dbg(1, debug, &sdev->sd,
"%s: property=0x%02x value=0x%02x status=0x%02x\n",
__func__, prop, val, resp[0]);
/*
* As there is no command response for SET_PROPERTY,
* wait Tcomp time to finish before proceed, in order
* to have property properly set.
*/
msleep(TIMEOUT_SET_PROPERTY);
return rval;
}
/*
* si4713_powerup - Powers the device up
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_powerup(struct si4713_device *sdev)
{
struct i2c_client *client = v4l2_get_subdevdata(&sdev->sd);
int err;
u8 resp[SI4713_PWUP_NRESP];
/*
* .First byte = Enabled interrupts and boot function
* .Second byte = Input operation mode
*/
u8 args[SI4713_PWUP_NARGS] = {
SI4713_PWUP_GPO2OEN | SI4713_PWUP_FUNC_TX,
SI4713_PWUP_OPMOD_ANALOG,
};
if (sdev->power_state)
return 0;
if (sdev->vdd) {
err = regulator_enable(sdev->vdd);
if (err) {
v4l2_err(&sdev->sd, "Failed to enable vdd: %d\n", err);
return err;
}
}
if (sdev->vio) {
err = regulator_enable(sdev->vio);
if (err) {
v4l2_err(&sdev->sd, "Failed to enable vio: %d\n", err);
return err;
}
}
if (sdev->gpio_reset) {
udelay(50);
gpiod_set_value(sdev->gpio_reset, 1);
}
if (client->irq)
args[0] |= SI4713_PWUP_CTSIEN;
err = si4713_send_command(sdev, SI4713_CMD_POWER_UP,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
TIMEOUT_POWER_UP);
if (!err) {
v4l2_dbg(1, debug, &sdev->sd, "Powerup response: 0x%02x\n",
resp[0]);
v4l2_dbg(1, debug, &sdev->sd, "Device in power up mode\n");
sdev->power_state = POWER_ON;
if (client->irq)
err = si4713_write_property(sdev, SI4713_GPO_IEN,
SI4713_STC_INT | SI4713_CTS);
return err;
}
gpiod_set_value(sdev->gpio_reset, 0);
if (sdev->vdd) {
err = regulator_disable(sdev->vdd);
if (err)
v4l2_err(&sdev->sd, "Failed to disable vdd: %d\n", err);
}
if (sdev->vio) {
err = regulator_disable(sdev->vio);
if (err)
v4l2_err(&sdev->sd, "Failed to disable vio: %d\n", err);
}
return err;
}
/*
* si4713_powerdown - Powers the device down
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_powerdown(struct si4713_device *sdev)
{
int err;
u8 resp[SI4713_PWDN_NRESP];
if (!sdev->power_state)
return 0;
err = si4713_send_command(sdev, SI4713_CMD_POWER_DOWN,
NULL, 0,
resp, ARRAY_SIZE(resp),
DEFAULT_TIMEOUT);
if (!err) {
v4l2_dbg(1, debug, &sdev->sd, "Power down response: 0x%02x\n",
resp[0]);
v4l2_dbg(1, debug, &sdev->sd, "Device in reset mode\n");
if (sdev->gpio_reset)
gpiod_set_value(sdev->gpio_reset, 0);
if (sdev->vdd) {
err = regulator_disable(sdev->vdd);
if (err) {
v4l2_err(&sdev->sd,
"Failed to disable vdd: %d\n", err);
}
}
if (sdev->vio) {
err = regulator_disable(sdev->vio);
if (err) {
v4l2_err(&sdev->sd,
"Failed to disable vio: %d\n", err);
}
}
sdev->power_state = POWER_OFF;
}
return err;
}
/*
* si4713_checkrev - Checks if we are treating a device with the correct rev.
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_checkrev(struct si4713_device *sdev)
{
struct i2c_client *client = v4l2_get_subdevdata(&sdev->sd);
int rval;
u8 resp[SI4713_GETREV_NRESP];
rval = si4713_send_command(sdev, SI4713_CMD_GET_REV,
NULL, 0,
resp, ARRAY_SIZE(resp),
DEFAULT_TIMEOUT);
if (rval < 0)
return rval;
if (resp[1] == SI4713_PRODUCT_NUMBER) {
v4l2_info(&sdev->sd, "chip found @ 0x%02x (%s)\n",
client->addr << 1, client->adapter->name);
} else {
v4l2_err(&sdev->sd, "Invalid product number 0x%X\n", resp[1]);
rval = -EINVAL;
}
return rval;
}
/*
* si4713_wait_stc - Waits STC interrupt and clears status bits. Useful
* for TX_TUNE_POWER, TX_TUNE_FREQ and TX_TUNE_MEAS
* @sdev: si4713_device structure for the device we are communicating
* @usecs: timeout to wait for STC interrupt signal
*/
static int si4713_wait_stc(struct si4713_device *sdev, const int usecs)
{
struct i2c_client *client = v4l2_get_subdevdata(&sdev->sd);
u8 resp[SI4713_GET_STATUS_NRESP];
unsigned long start_jiffies = jiffies;
int err;
if (client->irq &&
!wait_for_completion_timeout(&sdev->work, usecs_to_jiffies(usecs) + 1))
v4l2_warn(&sdev->sd,
"(%s) Device took too much time to answer.\n", __func__);
for (;;) {
/* Clear status bits */
err = si4713_send_command(sdev, SI4713_CMD_GET_INT_STATUS,
NULL, 0,
resp, ARRAY_SIZE(resp),
DEFAULT_TIMEOUT);
/* The USB device returns errors when it waits for the
* STC bit to be set. Hence polling */
if (err >= 0) {
v4l2_dbg(1, debug, &sdev->sd,
"%s: status bits: 0x%02x\n", __func__, resp[0]);
if (resp[0] & SI4713_STC_INT)
return 0;
}
if (jiffies_to_usecs(jiffies - start_jiffies) > usecs)
return err < 0 ? err : -EIO;
/* We sleep here for 3-4 ms in order to avoid flooding the device
* with USB requests. The si4713 USB driver was developed
* by reverse engineering the Windows USB driver. The windows
* driver also has a ~2.5 ms delay between responses. */
usleep_range(3000, 4000);
}
}
/*
* si4713_tx_tune_freq - Sets the state of the RF carrier and sets the tuning
* frequency between 76 and 108 MHz in 10 kHz units and
* steps of 50 kHz.
* @sdev: si4713_device structure for the device we are communicating
* @frequency: desired frequency (76 - 108 MHz, unit 10 KHz, step 50 kHz)
*/
static int si4713_tx_tune_freq(struct si4713_device *sdev, u16 frequency)
{
int err;
u8 val[SI4713_TXFREQ_NRESP];
/*
* .First byte = 0
* .Second byte = frequency's MSB
* .Third byte = frequency's LSB
*/
const u8 args[SI4713_TXFREQ_NARGS] = {
0x00,
msb(frequency),
lsb(frequency),
};
err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_FREQ,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (err < 0)
return err;
v4l2_dbg(1, debug, &sdev->sd,
"%s: frequency=0x%02x status=0x%02x\n", __func__,
frequency, val[0]);
err = si4713_wait_stc(sdev, TIMEOUT_TX_TUNE);
if (err < 0)
return err;
return compose_u16(args[1], args[2]);
}
/*
* si4713_tx_tune_power - Sets the RF voltage level between 88 and 120 dBuV in
* 1 dB units. A value of 0x00 indicates off. The command
* also sets the antenna tuning capacitance. A value of 0
* indicates autotuning, and a value of 1 - 191 indicates
* a manual override, which results in a tuning
* capacitance of 0.25 pF x @antcap.
* @sdev: si4713_device structure for the device we are communicating
* @power: tuning power (88 - 120 dBuV, unit/step 1 dB)
* @antcap: value of antenna tuning capacitor (0 - 191)
*/
static int si4713_tx_tune_power(struct si4713_device *sdev, u8 power,
u8 antcap)
{
int err;
u8 val[SI4713_TXPWR_NRESP];
/*
* .First byte = 0
* .Second byte = 0
* .Third byte = power
* .Fourth byte = antcap
*/
u8 args[SI4713_TXPWR_NARGS] = {
0x00,
0x00,
power,
antcap,
};
/* Map power values 1-87 to MIN_POWER (88) */
if (power > 0 && power < SI4713_MIN_POWER)
args[2] = power = SI4713_MIN_POWER;
err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_POWER,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (err < 0)
return err;
v4l2_dbg(1, debug, &sdev->sd,
"%s: power=0x%02x antcap=0x%02x status=0x%02x\n",
__func__, power, antcap, val[0]);
return si4713_wait_stc(sdev, TIMEOUT_TX_TUNE_POWER);
}
/*
* si4713_tx_tune_measure - Enters receive mode and measures the received noise
* level in units of dBuV on the selected frequency.
* The Frequency must be between 76 and 108 MHz in 10 kHz
* units and steps of 50 kHz. The command also sets the
* antenna tuning capacitance. A value of 0 means
* autotuning, and a value of 1 to 191 indicates manual
* override.
* @sdev: si4713_device structure for the device we are communicating
* @frequency: desired frequency (76 - 108 MHz, unit 10 KHz, step 50 kHz)
* @antcap: value of antenna tuning capacitor (0 - 191)
*/
static int si4713_tx_tune_measure(struct si4713_device *sdev, u16 frequency,
u8 antcap)
{
int err;
u8 val[SI4713_TXMEA_NRESP];
/*
* .First byte = 0
* .Second byte = frequency's MSB
* .Third byte = frequency's LSB
* .Fourth byte = antcap
*/
const u8 args[SI4713_TXMEA_NARGS] = {
0x00,
msb(frequency),
lsb(frequency),
antcap,
};
sdev->tune_rnl = DEFAULT_TUNE_RNL;
if (antcap > SI4713_MAX_ANTCAP)
return -EDOM;
err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_MEASURE,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (err < 0)
return err;
v4l2_dbg(1, debug, &sdev->sd,
"%s: frequency=0x%02x antcap=0x%02x status=0x%02x\n",
__func__, frequency, antcap, val[0]);
return si4713_wait_stc(sdev, TIMEOUT_TX_TUNE);
}
/*
* si4713_tx_tune_status- Returns the status of the tx_tune_freq, tx_tune_mea or
* tx_tune_power commands. This command return the current
* frequency, output voltage in dBuV, the antenna tunning
* capacitance value and the received noise level. The
* command also clears the stcint interrupt bit when the
* first bit of its arguments is high.
* @sdev: si4713_device structure for the device we are communicating
* @intack: 0x01 to clear the seek/tune complete interrupt status indicator.
* @frequency: returned frequency
* @power: returned power
* @antcap: returned antenna capacitance
* @noise: returned noise level
*/
static int si4713_tx_tune_status(struct si4713_device *sdev, u8 intack,
u16 *frequency, u8 *power,
u8 *antcap, u8 *noise)
{
int err;
u8 val[SI4713_TXSTATUS_NRESP];
/*
* .First byte = intack bit
*/
const u8 args[SI4713_TXSTATUS_NARGS] = {
intack & SI4713_INTACK_MASK,
};
err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_STATUS,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (!err) {
v4l2_dbg(1, debug, &sdev->sd,
"%s: status=0x%02x\n", __func__, val[0]);
*frequency = compose_u16(val[2], val[3]);
sdev->frequency = *frequency;
*power = val[5];
*antcap = val[6];
*noise = val[7];
v4l2_dbg(1, debug, &sdev->sd,
"%s: response: %d x 10 kHz (power %d, antcap %d, rnl %d)\n",
__func__, *frequency, *power, *antcap, *noise);
}
return err;
}
/*
* si4713_tx_rds_buff - Loads the RDS group buffer FIFO or circular buffer.
* @sdev: si4713_device structure for the device we are communicating
* @mode: the buffer operation mode.
* @rdsb: RDS Block B
* @rdsc: RDS Block C
* @rdsd: RDS Block D
* @cbleft: returns the number of available circular buffer blocks minus the
* number of used circular buffer blocks.
*/
static int si4713_tx_rds_buff(struct si4713_device *sdev, u8 mode, u16 rdsb,
u16 rdsc, u16 rdsd, s8 *cbleft)
{
int err;
u8 val[SI4713_RDSBUFF_NRESP];
const u8 args[SI4713_RDSBUFF_NARGS] = {
mode & SI4713_RDSBUFF_MODE_MASK,
msb(rdsb),
lsb(rdsb),
msb(rdsc),
lsb(rdsc),
msb(rdsd),
lsb(rdsd),
};
err = si4713_send_command(sdev, SI4713_CMD_TX_RDS_BUFF,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (!err) {
v4l2_dbg(1, debug, &sdev->sd,
"%s: status=0x%02x\n", __func__, val[0]);
*cbleft = (s8)val[2] - val[3];
v4l2_dbg(1, debug, &sdev->sd,
"%s: response: interrupts 0x%02x cb avail: %d cb used %d fifo avail %d fifo used %d\n",
__func__, val[1], val[2], val[3], val[4], val[5]);
}
return err;
}
/*
* si4713_tx_rds_ps - Loads the program service buffer.
* @sdev: si4713_device structure for the device we are communicating
* @psid: program service id to be loaded.
* @pschar: assumed 4 size char array to be loaded into the program service
*/
static int si4713_tx_rds_ps(struct si4713_device *sdev, u8 psid,
unsigned char *pschar)
{
int err;
u8 val[SI4713_RDSPS_NRESP];
const u8 args[SI4713_RDSPS_NARGS] = {
psid & SI4713_RDSPS_PSID_MASK,
pschar[0],
pschar[1],
pschar[2],
pschar[3],
};
err = si4713_send_command(sdev, SI4713_CMD_TX_RDS_PS,
args, ARRAY_SIZE(args), val,
ARRAY_SIZE(val), DEFAULT_TIMEOUT);
if (err < 0)
return err;
v4l2_dbg(1, debug, &sdev->sd, "%s: status=0x%02x\n", __func__, val[0]);
return err;
}
static int si4713_set_power_state(struct si4713_device *sdev, u8 value)
{
if (value)
return si4713_powerup(sdev);
return si4713_powerdown(sdev);
}
static int si4713_set_mute(struct si4713_device *sdev, u16 mute)
{
int rval = 0;
mute = set_mute(mute);
if (sdev->power_state)
rval = si4713_write_property(sdev,
SI4713_TX_LINE_INPUT_MUTE, mute);
return rval;
}
static int si4713_set_rds_ps_name(struct si4713_device *sdev, char *ps_name)
{
int rval = 0, i;
u8 len = 0;
/* We want to clear the whole thing */
if (!strlen(ps_name))
memset(ps_name, 0, MAX_RDS_PS_NAME + 1);
if (sdev->power_state) {
/* Write the new ps name and clear the padding */
for (i = 0; i < MAX_RDS_PS_NAME; i += (RDS_BLOCK / 2)) {
rval = si4713_tx_rds_ps(sdev, (i / (RDS_BLOCK / 2)),
ps_name + i);
if (rval < 0)
return rval;
}
/* Setup the size to be sent */
if (strlen(ps_name))
len = strlen(ps_name) - 1;
else
len = 1;
rval = si4713_write_property(sdev,
SI4713_TX_RDS_PS_MESSAGE_COUNT,
rds_ps_nblocks(len));
if (rval < 0)
return rval;
rval = si4713_write_property(sdev,
SI4713_TX_RDS_PS_REPEAT_COUNT,
DEFAULT_RDS_PS_REPEAT_COUNT * 2);
if (rval < 0)
return rval;
}
return rval;
}
static int si4713_set_rds_radio_text(struct si4713_device *sdev, const char *rt)
{
static const char cr[RDS_RADIOTEXT_BLK_SIZE] = { RDS_CARRIAGE_RETURN, 0 };
int rval = 0, i;
u16 t_index = 0;
u8 b_index = 0, cr_inserted = 0;
s8 left;
if (!sdev->power_state)
return rval;
rval = si4713_tx_rds_buff(sdev, RDS_BLOCK_CLEAR, 0, 0, 0, &left);
if (rval < 0)
return rval;
if (!strlen(rt))
return rval;
do {
/* RDS spec says that if the last block isn't used,
* then apply a carriage return
*/
if (t_index < (RDS_RADIOTEXT_INDEX_MAX * RDS_RADIOTEXT_BLK_SIZE)) {
for (i = 0; i < RDS_RADIOTEXT_BLK_SIZE; i++) {
if (!rt[t_index + i] ||
rt[t_index + i] == RDS_CARRIAGE_RETURN) {
rt = cr;
cr_inserted = 1;
break;
}
}
}
rval = si4713_tx_rds_buff(sdev, RDS_BLOCK_LOAD,
compose_u16(RDS_RADIOTEXT_2A, b_index++),
compose_u16(rt[t_index], rt[t_index + 1]),
compose_u16(rt[t_index + 2], rt[t_index + 3]),
&left);
if (rval < 0)
return rval;
t_index += RDS_RADIOTEXT_BLK_SIZE;
if (cr_inserted)
break;
} while (left > 0);
return rval;
}
/*
* si4713_update_tune_status - update properties from tx_tune_status
* command. Must be called with sdev->mutex held.
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_update_tune_status(struct si4713_device *sdev)
{
int rval;
u16 f = 0;
u8 p = 0, a = 0, n = 0;
rval = si4713_tx_tune_status(sdev, 0x00, &f, &p, &a, &n);
if (rval < 0)
goto exit;
/* TODO: check that power_level and antenna_capacitor really are not
changed by the hardware. If they are, then these controls should become
volatiles.
sdev->power_level = p;
sdev->antenna_capacitor = a;*/
sdev->tune_rnl = n;
exit:
return rval;
}
static int si4713_choose_econtrol_action(struct si4713_device *sdev, u32 id,
s32 *bit, s32 *mask, u16 *property, int *mul,
unsigned long **table, int *size)
{
s32 rval = 0;
switch (id) {
/* FM_TX class controls */
case V4L2_CID_RDS_TX_PI:
*property = SI4713_TX_RDS_PI;
*mul = 1;
break;
case V4L2_CID_AUDIO_COMPRESSION_THRESHOLD:
*property = SI4713_TX_ACOMP_THRESHOLD;
*mul = 1;
break;
case V4L2_CID_AUDIO_COMPRESSION_GAIN:
*property = SI4713_TX_ACOMP_GAIN;
*mul = 1;
break;
case V4L2_CID_PILOT_TONE_FREQUENCY:
*property = SI4713_TX_PILOT_FREQUENCY;
*mul = 1;
break;
case V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME:
*property = SI4713_TX_ACOMP_ATTACK_TIME;
*mul = ATTACK_TIME_UNIT;
break;
case V4L2_CID_PILOT_TONE_DEVIATION:
*property = SI4713_TX_PILOT_DEVIATION;
*mul = 10;
break;
case V4L2_CID_AUDIO_LIMITER_DEVIATION:
*property = SI4713_TX_AUDIO_DEVIATION;
*mul = 10;
break;
case V4L2_CID_RDS_TX_DEVIATION:
*property = SI4713_TX_RDS_DEVIATION;
*mul = 1;
break;
case V4L2_CID_RDS_TX_PTY:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 5;
*mask = 0x1F << 5;
break;
case V4L2_CID_RDS_TX_DYNAMIC_PTY:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 15;
*mask = 1 << 15;
break;
case V4L2_CID_RDS_TX_COMPRESSED:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 14;
*mask = 1 << 14;
break;
case V4L2_CID_RDS_TX_ARTIFICIAL_HEAD:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 13;
*mask = 1 << 13;
break;
case V4L2_CID_RDS_TX_MONO_STEREO:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 12;
*mask = 1 << 12;
break;
case V4L2_CID_RDS_TX_TRAFFIC_PROGRAM:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 10;
*mask = 1 << 10;
break;
case V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 4;
*mask = 1 << 4;
break;
case V4L2_CID_RDS_TX_MUSIC_SPEECH:
*property = SI4713_TX_RDS_PS_MISC;
*bit = 3;
*mask = 1 << 3;
break;
case V4L2_CID_AUDIO_LIMITER_ENABLED:
*property = SI4713_TX_ACOMP_ENABLE;
*bit = 1;
*mask = 1 << 1;
break;
case V4L2_CID_AUDIO_COMPRESSION_ENABLED:
*property = SI4713_TX_ACOMP_ENABLE;
*bit = 0;
*mask = 1 << 0;
break;
case V4L2_CID_PILOT_TONE_ENABLED:
*property = SI4713_TX_COMPONENT_ENABLE;
*bit = 0;
*mask = 1 << 0;
break;
case V4L2_CID_AUDIO_LIMITER_RELEASE_TIME:
*property = SI4713_TX_LIMITER_RELEASE_TIME;
*table = limiter_times;
*size = ARRAY_SIZE(limiter_times);
break;
case V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME:
*property = SI4713_TX_ACOMP_RELEASE_TIME;
*table = acomp_rtimes;
*size = ARRAY_SIZE(acomp_rtimes);
break;
case V4L2_CID_TUNE_PREEMPHASIS:
*property = SI4713_TX_PREEMPHASIS;
*table = preemphasis_values;
*size = ARRAY_SIZE(preemphasis_values);
break;
default:
rval = -EINVAL;
break;
}
return rval;
}
static int si4713_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *f);
static int si4713_s_modulator(struct v4l2_subdev *sd, const struct v4l2_modulator *);
/*
* si4713_setup - Sets the device up with current configuration.
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_setup(struct si4713_device *sdev)
{
struct v4l2_frequency f;
struct v4l2_modulator vm;
int rval;
/* Device procedure needs to set frequency first */
f.tuner = 0;
f.frequency = sdev->frequency ? sdev->frequency : DEFAULT_FREQUENCY;
f.frequency = si4713_to_v4l2(f.frequency);
rval = si4713_s_frequency(&sdev->sd, &f);
vm.index = 0;
if (sdev->stereo)
vm.txsubchans = V4L2_TUNER_SUB_STEREO;
else
vm.txsubchans = V4L2_TUNER_SUB_MONO;
if (sdev->rds_enabled)
vm.txsubchans |= V4L2_TUNER_SUB_RDS;
si4713_s_modulator(&sdev->sd, &vm);
return rval;
}
/*
* si4713_initialize - Sets the device up with default configuration.
* @sdev: si4713_device structure for the device we are communicating
*/
static int si4713_initialize(struct si4713_device *sdev)
{
int rval;
rval = si4713_set_power_state(sdev, POWER_ON);
if (rval < 0)
return rval;
rval = si4713_checkrev(sdev);
if (rval < 0)
return rval;
rval = si4713_set_power_state(sdev, POWER_OFF);
if (rval < 0)
return rval;
sdev->frequency = DEFAULT_FREQUENCY;
sdev->stereo = 1;
sdev->tune_rnl = DEFAULT_TUNE_RNL;
return 0;
}
/* si4713_s_ctrl - set the value of a control */
static int si4713_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct si4713_device *sdev =
container_of(ctrl->handler, struct si4713_device, ctrl_handler);
u32 val = 0;
s32 bit = 0, mask = 0;
u16 property = 0;
int mul = 0;
unsigned long *table = NULL;
int size = 0;
bool force = false;
int c;
int ret = 0;
if (ctrl->id != V4L2_CID_AUDIO_MUTE)
return -EINVAL;
if (ctrl->is_new) {
if (ctrl->val) {
ret = si4713_set_mute(sdev, ctrl->val);
if (!ret)
ret = si4713_set_power_state(sdev, POWER_DOWN);
return ret;
}
ret = si4713_set_power_state(sdev, POWER_UP);
if (!ret)
ret = si4713_set_mute(sdev, ctrl->val);
if (!ret)
ret = si4713_setup(sdev);
if (ret)
return ret;
force = true;
}
if (!sdev->power_state)
return 0;
for (c = 1; !ret && c < ctrl->ncontrols; c++) {
ctrl = ctrl->cluster[c];
if (!force && !ctrl->is_new)
continue;
switch (ctrl->id) {
case V4L2_CID_RDS_TX_PS_NAME:
ret = si4713_set_rds_ps_name(sdev, ctrl->p_new.p_char);
break;
case V4L2_CID_RDS_TX_RADIO_TEXT:
ret = si4713_set_rds_radio_text(sdev, ctrl->p_new.p_char);
break;
case V4L2_CID_TUNE_ANTENNA_CAPACITOR:
/* don't handle this control if we force setting all
* controls since in that case it will be handled by
* V4L2_CID_TUNE_POWER_LEVEL. */
if (force)
break;
fallthrough;
case V4L2_CID_TUNE_POWER_LEVEL:
ret = si4713_tx_tune_power(sdev,
sdev->tune_pwr_level->val, sdev->tune_ant_cap->val);
if (!ret) {
/* Make sure we don't set this twice */
sdev->tune_ant_cap->is_new = false;
sdev->tune_pwr_level->is_new = false;
}
break;
case V4L2_CID_RDS_TX_ALT_FREQS_ENABLE:
case V4L2_CID_RDS_TX_ALT_FREQS:
if (sdev->rds_alt_freqs_enable->val) {
val = sdev->rds_alt_freqs->p_new.p_u32[0];
val = val / 100 - 876 + 0xe101;
} else {
val = 0xe0e0;
}
ret = si4713_write_property(sdev, SI4713_TX_RDS_PS_AF, val);
break;
default:
ret = si4713_choose_econtrol_action(sdev, ctrl->id, &bit,
&mask, &property, &mul, &table, &size);
if (ret < 0)
break;
val = ctrl->val;
if (mul) {
val = val / mul;
} else if (table) {
ret = usecs_to_dev(val, table, size);
if (ret < 0)
break;
val = ret;
ret = 0;
}
if (mask) {
ret = si4713_read_property(sdev, property, &val);
if (ret < 0)
break;
val = set_bits(val, ctrl->val, bit, mask);
}
ret = si4713_write_property(sdev, property, val);
if (ret < 0)
break;
if (mask)
val = ctrl->val;
break;
}
}
return ret;
}
/* si4713_ioctl - deal with private ioctls (only rnl for now) */
static long si4713_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct si4713_device *sdev = to_si4713_device(sd);
struct si4713_rnl *rnl = arg;
u16 frequency;
int rval = 0;
if (!arg)
return -EINVAL;
switch (cmd) {
case SI4713_IOC_MEASURE_RNL:
frequency = v4l2_to_si4713(rnl->frequency);
if (sdev->power_state) {
/* Set desired measurement frequency */
rval = si4713_tx_tune_measure(sdev, frequency, 0);
if (rval < 0)
return rval;
/* get results from tune status */
rval = si4713_update_tune_status(sdev);
if (rval < 0)
return rval;
}
rnl->rnl = sdev->tune_rnl;
break;
default:
/* nothing */
rval = -ENOIOCTLCMD;
}
return rval;
}
/* si4713_g_modulator - get modulator attributes */
static int si4713_g_modulator(struct v4l2_subdev *sd, struct v4l2_modulator *vm)
{
struct si4713_device *sdev = to_si4713_device(sd);
int rval = 0;
if (!sdev)
return -ENODEV;
if (vm->index > 0)
return -EINVAL;
strscpy(vm->name, "FM Modulator", sizeof(vm->name));
vm->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LOW |
V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_CONTROLS;
/* Report current frequency range limits */
vm->rangelow = si4713_to_v4l2(FREQ_RANGE_LOW);
vm->rangehigh = si4713_to_v4l2(FREQ_RANGE_HIGH);
if (sdev->power_state) {
u32 comp_en = 0;
rval = si4713_read_property(sdev, SI4713_TX_COMPONENT_ENABLE,
&comp_en);
if (rval < 0)
return rval;
sdev->stereo = get_status_bit(comp_en, 1, 1 << 1);
}
/* Report current audio mode: mono or stereo */
if (sdev->stereo)
vm->txsubchans = V4L2_TUNER_SUB_STEREO;
else
vm->txsubchans = V4L2_TUNER_SUB_MONO;
/* Report rds feature status */
if (sdev->rds_enabled)
vm->txsubchans |= V4L2_TUNER_SUB_RDS;
else
vm->txsubchans &= ~V4L2_TUNER_SUB_RDS;
return rval;
}
/* si4713_s_modulator - set modulator attributes */
static int si4713_s_modulator(struct v4l2_subdev *sd, const struct v4l2_modulator *vm)
{
struct si4713_device *sdev = to_si4713_device(sd);
int rval = 0;
u16 stereo, rds;
u32 p;
if (!sdev)
return -ENODEV;
if (vm->index > 0)
return -EINVAL;
/* Set audio mode: mono or stereo */
if (vm->txsubchans & V4L2_TUNER_SUB_STEREO)
stereo = 1;
else if (vm->txsubchans & V4L2_TUNER_SUB_MONO)
stereo = 0;
else
return -EINVAL;
rds = !!(vm->txsubchans & V4L2_TUNER_SUB_RDS);
if (sdev->power_state) {
rval = si4713_read_property(sdev,
SI4713_TX_COMPONENT_ENABLE, &p);
if (rval < 0)
return rval;
p = set_bits(p, stereo, 1, 1 << 1);
p = set_bits(p, rds, 2, 1 << 2);
rval = si4713_write_property(sdev,
SI4713_TX_COMPONENT_ENABLE, p);
if (rval < 0)
return rval;
}
sdev->stereo = stereo;
sdev->rds_enabled = rds;
return rval;
}
/* si4713_g_frequency - get tuner or modulator radio frequency */
static int si4713_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
{
struct si4713_device *sdev = to_si4713_device(sd);
int rval = 0;
if (f->tuner)
return -EINVAL;
if (sdev->power_state) {
u16 freq;
u8 p, a, n;
rval = si4713_tx_tune_status(sdev, 0x00, &freq, &p, &a, &n);
if (rval < 0)
return rval;
sdev->frequency = freq;
}
f->frequency = si4713_to_v4l2(sdev->frequency);
return rval;
}
/* si4713_s_frequency - set tuner or modulator radio frequency */
static int si4713_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *f)
{
struct si4713_device *sdev = to_si4713_device(sd);
int rval = 0;
u16 frequency = v4l2_to_si4713(f->frequency);
if (f->tuner)
return -EINVAL;
/* Check frequency range */
frequency = clamp_t(u16, frequency, FREQ_RANGE_LOW, FREQ_RANGE_HIGH);
if (sdev->power_state) {
rval = si4713_tx_tune_freq(sdev, frequency);
if (rval < 0)
return rval;
frequency = rval;
rval = 0;
}
sdev->frequency = frequency;
return rval;
}
static const struct v4l2_ctrl_ops si4713_ctrl_ops = {
.s_ctrl = si4713_s_ctrl,
};
static const struct v4l2_subdev_core_ops si4713_subdev_core_ops = {
.ioctl = si4713_ioctl,
};
static const struct v4l2_subdev_tuner_ops si4713_subdev_tuner_ops = {
.g_frequency = si4713_g_frequency,
.s_frequency = si4713_s_frequency,
.g_modulator = si4713_g_modulator,
.s_modulator = si4713_s_modulator,
};
static const struct v4l2_subdev_ops si4713_subdev_ops = {
.core = &si4713_subdev_core_ops,
.tuner = &si4713_subdev_tuner_ops,
};
static const struct v4l2_ctrl_config si4713_alt_freqs_ctrl = {
.id = V4L2_CID_RDS_TX_ALT_FREQS,
.type = V4L2_CTRL_TYPE_U32,
.min = 87600,
.max = 107900,
.step = 100,
.def = 87600,
.dims = { 1 },
.elem_size = sizeof(u32),
};
/*
* I2C driver interface
*/
/* si4713_probe - probe for the device */
static int si4713_probe(struct i2c_client *client)
{
struct si4713_device *sdev;
struct v4l2_ctrl_handler *hdl;
struct si4713_platform_data *pdata = client->dev.platform_data;
struct device_node *np = client->dev.of_node;
struct radio_si4713_platform_data si4713_pdev_pdata;
struct platform_device *si4713_pdev;
int rval;
sdev = devm_kzalloc(&client->dev, sizeof(*sdev), GFP_KERNEL);
if (!sdev) {
dev_err(&client->dev, "Failed to alloc video device.\n");
rval = -ENOMEM;
goto exit;
}
sdev->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(sdev->gpio_reset)) {
rval = PTR_ERR(sdev->gpio_reset);
dev_err(&client->dev, "Failed to request gpio: %d\n", rval);
goto exit;
}
sdev->vdd = devm_regulator_get_optional(&client->dev, "vdd");
if (IS_ERR(sdev->vdd)) {
rval = PTR_ERR(sdev->vdd);
if (rval == -EPROBE_DEFER)
goto exit;
dev_dbg(&client->dev, "no vdd regulator found: %d\n", rval);
sdev->vdd = NULL;
}
sdev->vio = devm_regulator_get_optional(&client->dev, "vio");
if (IS_ERR(sdev->vio)) {
rval = PTR_ERR(sdev->vio);
if (rval == -EPROBE_DEFER)
goto exit;
dev_dbg(&client->dev, "no vio regulator found: %d\n", rval);
sdev->vio = NULL;
}
v4l2_i2c_subdev_init(&sdev->sd, client, &si4713_subdev_ops);
init_completion(&sdev->work);
hdl = &sdev->ctrl_handler;
v4l2_ctrl_handler_init(hdl, 20);
sdev->mute = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, DEFAULT_MUTE);
sdev->rds_pi = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_PI, 0, 0xffff, 1, DEFAULT_RDS_PI);
sdev->rds_pty = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_PTY, 0, 31, 1, DEFAULT_RDS_PTY);
sdev->rds_compressed = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_COMPRESSED, 0, 1, 1, 0);
sdev->rds_art_head = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_ARTIFICIAL_HEAD, 0, 1, 1, 0);
sdev->rds_stereo = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_MONO_STEREO, 0, 1, 1, 1);
sdev->rds_tp = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_TRAFFIC_PROGRAM, 0, 1, 1, 0);
sdev->rds_ta = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT, 0, 1, 1, 0);
sdev->rds_ms = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_MUSIC_SPEECH, 0, 1, 1, 1);
sdev->rds_dyn_pty = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_DYNAMIC_PTY, 0, 1, 1, 0);
sdev->rds_alt_freqs_enable = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_ALT_FREQS_ENABLE, 0, 1, 1, 0);
sdev->rds_alt_freqs = v4l2_ctrl_new_custom(hdl, &si4713_alt_freqs_ctrl, NULL);
sdev->rds_deviation = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_DEVIATION, 0, MAX_RDS_DEVIATION,
10, DEFAULT_RDS_DEVIATION);
/*
* Report step as 8. From RDS spec, psname
* should be 8. But there are receivers which scroll strings
* sized as 8xN.
*/
sdev->rds_ps_name = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_PS_NAME, 0, MAX_RDS_PS_NAME, 8, 0);
/*
* Report step as 32 (2A block). From RDS spec,
* radio text should be 32 for 2A block. But there are receivers
* which scroll strings sized as 32xN. Setting default to 32.
*/
sdev->rds_radio_text = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_RDS_TX_RADIO_TEXT, 0, MAX_RDS_RADIO_TEXT, 32, 0);
sdev->limiter_enabled = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_LIMITER_ENABLED, 0, 1, 1, 1);
sdev->limiter_release_time = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_LIMITER_RELEASE_TIME, 250,
MAX_LIMITER_RELEASE_TIME, 10, DEFAULT_LIMITER_RTIME);
sdev->limiter_deviation = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_LIMITER_DEVIATION, 0,
MAX_LIMITER_DEVIATION, 10, DEFAULT_LIMITER_DEV);
sdev->compression_enabled = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_COMPRESSION_ENABLED, 0, 1, 1, 1);
sdev->compression_gain = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_COMPRESSION_GAIN, 0, MAX_ACOMP_GAIN, 1,
DEFAULT_ACOMP_GAIN);
sdev->compression_threshold = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_COMPRESSION_THRESHOLD,
MIN_ACOMP_THRESHOLD, MAX_ACOMP_THRESHOLD, 1,
DEFAULT_ACOMP_THRESHOLD);
sdev->compression_attack_time = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME, 0,
MAX_ACOMP_ATTACK_TIME, 500, DEFAULT_ACOMP_ATIME);
sdev->compression_release_time = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME, 100000,
MAX_ACOMP_RELEASE_TIME, 100000, DEFAULT_ACOMP_RTIME);
sdev->pilot_tone_enabled = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_PILOT_TONE_ENABLED, 0, 1, 1, 1);
sdev->pilot_tone_deviation = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_PILOT_TONE_DEVIATION, 0, MAX_PILOT_DEVIATION,
10, DEFAULT_PILOT_DEVIATION);
sdev->pilot_tone_freq = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_PILOT_TONE_FREQUENCY, 0, MAX_PILOT_FREQUENCY,
1, DEFAULT_PILOT_FREQUENCY);
sdev->tune_preemphasis = v4l2_ctrl_new_std_menu(hdl, &si4713_ctrl_ops,
V4L2_CID_TUNE_PREEMPHASIS,
V4L2_PREEMPHASIS_75_uS, 0, V4L2_PREEMPHASIS_50_uS);
sdev->tune_pwr_level = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_TUNE_POWER_LEVEL, 0, SI4713_MAX_POWER,
1, DEFAULT_POWER_LEVEL);
sdev->tune_ant_cap = v4l2_ctrl_new_std(hdl, &si4713_ctrl_ops,
V4L2_CID_TUNE_ANTENNA_CAPACITOR, 0, SI4713_MAX_ANTCAP,
1, 0);
if (hdl->error) {
rval = hdl->error;
goto free_ctrls;
}
v4l2_ctrl_cluster(29, &sdev->mute);
sdev->sd.ctrl_handler = hdl;
if (client->irq) {
rval = devm_request_irq(&client->dev, client->irq,
si4713_handler, IRQF_TRIGGER_FALLING,
client->name, sdev);
if (rval < 0) {
v4l2_err(&sdev->sd, "Could not request IRQ\n");
goto free_ctrls;
}
v4l2_dbg(1, debug, &sdev->sd, "IRQ requested.\n");
} else {
v4l2_warn(&sdev->sd, "IRQ not configured. Using timeouts.\n");
}
rval = si4713_initialize(sdev);
if (rval < 0) {
v4l2_err(&sdev->sd, "Failed to probe device information.\n");
goto free_ctrls;
}
if (!np && (!pdata || !pdata->is_platform_device))
return 0;
si4713_pdev = platform_device_alloc("radio-si4713", -1);
if (!si4713_pdev) {
rval = -ENOMEM;
goto put_main_pdev;
}
si4713_pdev_pdata.subdev = client;
rval = platform_device_add_data(si4713_pdev, &si4713_pdev_pdata,
sizeof(si4713_pdev_pdata));
if (rval)
goto put_main_pdev;
rval = platform_device_add(si4713_pdev);
if (rval)
goto put_main_pdev;
sdev->pd = si4713_pdev;
return 0;
put_main_pdev:
platform_device_put(si4713_pdev);
v4l2_device_unregister_subdev(&sdev->sd);
free_ctrls:
v4l2_ctrl_handler_free(hdl);
exit:
return rval;
}
/* si4713_remove - remove the device */
static void si4713_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct si4713_device *sdev = to_si4713_device(sd);
platform_device_unregister(sdev->pd);
if (sdev->power_state)
si4713_set_power_state(sdev, POWER_DOWN);
v4l2_device_unregister_subdev(sd);
v4l2_ctrl_handler_free(sd->ctrl_handler);
}
/* si4713_i2c_driver - i2c driver interface */
static const struct i2c_device_id si4713_id[] = {
{ "si4713" , 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, si4713_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id si4713_of_match[] = {
{ .compatible = "silabs,si4713" },
{ },
};
MODULE_DEVICE_TABLE(of, si4713_of_match);
#endif
static struct i2c_driver si4713_i2c_driver = {
.driver = {
.name = "si4713",
.of_match_table = of_match_ptr(si4713_of_match),
},
.probe = si4713_probe,
.remove = si4713_remove,
.id_table = si4713_id,
};
module_i2c_driver(si4713_i2c_driver);
| linux-master | drivers/media/radio/si4713/si4713.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/media/radio/si470x/radio-si470x-common.c
*
* Driver for radios with Silicon Labs Si470x FM Radio Receivers
*
* Copyright (c) 2009 Tobias Lorenz <[email protected]>
* Copyright (c) 2012 Hans de Goede <[email protected]>
*/
/*
* History:
* 2008-01-12 Tobias Lorenz <[email protected]>
* Version 1.0.0
* - First working version
* 2008-01-13 Tobias Lorenz <[email protected]>
* Version 1.0.1
* - Improved error handling, every function now returns errno
* - Improved multi user access (start/mute/stop)
* - Channel doesn't get lost anymore after start/mute/stop
* - RDS support added (polling mode via interrupt EP 1)
* - marked default module parameters with *value*
* - switched from bit structs to bit masks
* - header file cleaned and integrated
* 2008-01-14 Tobias Lorenz <[email protected]>
* Version 1.0.2
* - hex values are now lower case
* - commented USB ID for ADS/Tech moved on todo list
* - blacklisted si470x in hid-quirks.c
* - rds buffer handling functions integrated into *_work, *_read
* - rds_command in si470x_poll exchanged against simple retval
* - check for firmware version 15
* - code order and prototypes still remain the same
* - spacing and bottom of band codes remain the same
* 2008-01-16 Tobias Lorenz <[email protected]>
* Version 1.0.3
* - code reordered to avoid function prototypes
* - switch/case defaults are now more user-friendly
* - unified comment style
* - applied all checkpatch.pl v1.12 suggestions
* except the warning about the too long lines with bit comments
* - renamed FMRADIO to RADIO to cut line length (checkpatch.pl)
* 2008-01-22 Tobias Lorenz <[email protected]>
* Version 1.0.4
* - avoid poss. locking when doing copy_to_user which may sleep
* - RDS is automatically activated on read now
* - code cleaned of unnecessary rds_commands
* - USB Vendor/Product ID for ADS/Tech FM Radio Receiver verified
* (thanks to Guillaume RAMOUSSE)
* 2008-01-27 Tobias Lorenz <[email protected]>
* Version 1.0.5
* - number of seek_retries changed to tune_timeout
* - fixed problem with incomplete tune operations by own buffers
* - optimization of variables and printf types
* - improved error logging
* 2008-01-31 Tobias Lorenz <[email protected]>
* Oliver Neukum <[email protected]>
* Version 1.0.6
* - fixed coverity checker warnings in *_usb_driver_disconnect
* - probe()/open() race by correct ordering in probe()
* - DMA coherency rules by separate allocation of all buffers
* - use of endianness macros
* - abuse of spinlock, replaced by mutex
* - racy handling of timer in disconnect,
* replaced by delayed_work
* - racy interruptible_sleep_on(),
* replaced with wait_event_interruptible()
* - handle signals in read()
* 2008-02-08 Tobias Lorenz <[email protected]>
* Oliver Neukum <[email protected]>
* Version 1.0.7
* - usb autosuspend support
* - unplugging fixed
* 2008-05-07 Tobias Lorenz <[email protected]>
* Version 1.0.8
* - hardware frequency seek support
* - afc indication
* - more safety checks, let si470x_get_freq return errno
* - vidioc behavior corrected according to v4l2 spec
* 2008-10-20 Alexey Klimov <[email protected]>
* - add support for KWorld USB FM Radio FM700
* - blacklisted KWorld radio in hid-core.c and hid-ids.h
* 2008-12-03 Mark Lord <[email protected]>
* - add support for DealExtreme USB Radio
* 2009-01-31 Bob Ross <[email protected]>
* - correction of stereo detection/setting
* - correction of signal strength indicator scaling
* 2009-01-31 Rick Bronson <[email protected]>
* Tobias Lorenz <[email protected]>
* - add LED status output
* - get HW/SW version from scratchpad
* 2009-06-16 Edouard Lafargue <[email protected]>
* Version 1.0.10
* - add support for interrupt mode for RDS endpoint,
* instead of polling.
* Improves RDS reception significantly
*/
/* kernel includes */
#include "radio-si470x.h"
/**************************************************************************
* Module Parameters
**************************************************************************/
/* Spacing (kHz) */
/* 0: 200 kHz (USA, Australia) */
/* 1: 100 kHz (Europe, Japan) */
/* 2: 50 kHz */
static unsigned short space = 2;
module_param(space, ushort, 0444);
MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
/* De-emphasis */
/* 0: 75 us (USA) */
/* 1: 50 us (Europe, Australia, Japan) */
static unsigned short de = 1;
module_param(de, ushort, 0444);
MODULE_PARM_DESC(de, "De-emphasis: 0=75us *1=50us*");
/* Tune timeout */
static unsigned int tune_timeout = 3000;
module_param(tune_timeout, uint, 0644);
MODULE_PARM_DESC(tune_timeout, "Tune timeout: *3000*");
/* Seek timeout */
static unsigned int seek_timeout = 5000;
module_param(seek_timeout, uint, 0644);
MODULE_PARM_DESC(seek_timeout, "Seek timeout: *5000*");
static const struct v4l2_frequency_band bands[] = {
{
.type = V4L2_TUNER_RADIO,
.index = 0,
.capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO |
V4L2_TUNER_CAP_FREQ_BANDS |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP,
.rangelow = 87500 * 16,
.rangehigh = 108000 * 16,
.modulation = V4L2_BAND_MODULATION_FM,
},
{
.type = V4L2_TUNER_RADIO,
.index = 1,
.capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO |
V4L2_TUNER_CAP_FREQ_BANDS |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP,
.rangelow = 76000 * 16,
.rangehigh = 108000 * 16,
.modulation = V4L2_BAND_MODULATION_FM,
},
{
.type = V4L2_TUNER_RADIO,
.index = 2,
.capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO |
V4L2_TUNER_CAP_FREQ_BANDS |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP,
.rangelow = 76000 * 16,
.rangehigh = 90000 * 16,
.modulation = V4L2_BAND_MODULATION_FM,
},
};
/**************************************************************************
* Generic Functions
**************************************************************************/
/*
* si470x_set_band - set the band
*/
static int si470x_set_band(struct si470x_device *radio, int band)
{
if (radio->band == band)
return 0;
radio->band = band;
radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND;
radio->registers[SYSCONFIG2] |= radio->band << 6;
return radio->set_register(radio, SYSCONFIG2);
}
/*
* si470x_set_chan - set the channel
*/
static int si470x_set_chan(struct si470x_device *radio, unsigned short chan)
{
int retval;
unsigned long time_left;
bool timed_out = false;
retval = radio->get_register(radio, POWERCFG);
if (retval)
return retval;
if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE))
!= (POWERCFG_ENABLE|POWERCFG_DMUTE)) {
return 0;
}
/* start tuning */
radio->registers[CHANNEL] &= ~CHANNEL_CHAN;
radio->registers[CHANNEL] |= CHANNEL_TUNE | chan;
retval = radio->set_register(radio, CHANNEL);
if (retval < 0)
goto done;
/* wait till tune operation has completed */
reinit_completion(&radio->completion);
time_left = wait_for_completion_timeout(&radio->completion,
msecs_to_jiffies(tune_timeout));
if (time_left == 0)
timed_out = true;
if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
dev_warn(&radio->videodev.dev, "tune does not complete\n");
if (timed_out)
dev_warn(&radio->videodev.dev,
"tune timed out after %u ms\n", tune_timeout);
/* stop tuning */
radio->registers[CHANNEL] &= ~CHANNEL_TUNE;
retval = radio->set_register(radio, CHANNEL);
done:
return retval;
}
/*
* si470x_get_step - get channel spacing
*/
static unsigned int si470x_get_step(struct si470x_device *radio)
{
/* Spacing (kHz) */
switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) {
/* 0: 200 kHz (USA, Australia) */
case 0:
return 200 * 16;
/* 1: 100 kHz (Europe, Japan) */
case 1:
return 100 * 16;
/* 2: 50 kHz */
default:
return 50 * 16;
}
}
/*
* si470x_get_freq - get the frequency
*/
static int si470x_get_freq(struct si470x_device *radio, unsigned int *freq)
{
int chan, retval;
/* read channel */
retval = radio->get_register(radio, READCHAN);
chan = radio->registers[READCHAN] & READCHAN_READCHAN;
/* Frequency (MHz) = Spacing (kHz) x Channel + Bottom of Band (MHz) */
*freq = chan * si470x_get_step(radio) + bands[radio->band].rangelow;
return retval;
}
/*
* si470x_set_freq - set the frequency
*/
int si470x_set_freq(struct si470x_device *radio, unsigned int freq)
{
unsigned short chan;
freq = clamp(freq, bands[radio->band].rangelow,
bands[radio->band].rangehigh);
/* Chan = [ Freq (Mhz) - Bottom of Band (MHz) ] / Spacing (kHz) */
chan = (freq - bands[radio->band].rangelow) / si470x_get_step(radio);
return si470x_set_chan(radio, chan);
}
EXPORT_SYMBOL_GPL(si470x_set_freq);
/*
* si470x_set_seek - set seek
*/
static int si470x_set_seek(struct si470x_device *radio,
const struct v4l2_hw_freq_seek *seek)
{
int band, retval;
unsigned int freq;
bool timed_out = false;
unsigned long time_left;
/* set band */
if (seek->rangelow || seek->rangehigh) {
for (band = 0; band < ARRAY_SIZE(bands); band++) {
if (bands[band].rangelow == seek->rangelow &&
bands[band].rangehigh == seek->rangehigh)
break;
}
if (band == ARRAY_SIZE(bands))
return -EINVAL; /* No matching band found */
} else
band = 1; /* If nothing is specified seek 76 - 108 Mhz */
if (radio->band != band) {
retval = si470x_get_freq(radio, &freq);
if (retval)
return retval;
retval = si470x_set_band(radio, band);
if (retval)
return retval;
retval = si470x_set_freq(radio, freq);
if (retval)
return retval;
}
/* start seeking */
radio->registers[POWERCFG] |= POWERCFG_SEEK;
if (seek->wrap_around)
radio->registers[POWERCFG] &= ~POWERCFG_SKMODE;
else
radio->registers[POWERCFG] |= POWERCFG_SKMODE;
if (seek->seek_upward)
radio->registers[POWERCFG] |= POWERCFG_SEEKUP;
else
radio->registers[POWERCFG] &= ~POWERCFG_SEEKUP;
retval = radio->set_register(radio, POWERCFG);
if (retval < 0)
return retval;
/* wait till tune operation has completed */
reinit_completion(&radio->completion);
time_left = wait_for_completion_timeout(&radio->completion,
msecs_to_jiffies(seek_timeout));
if (time_left == 0)
timed_out = true;
if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
dev_warn(&radio->videodev.dev, "seek does not complete\n");
if (radio->registers[STATUSRSSI] & STATUSRSSI_SF)
dev_warn(&radio->videodev.dev,
"seek failed / band limit reached\n");
/* stop seeking */
radio->registers[POWERCFG] &= ~POWERCFG_SEEK;
retval = radio->set_register(radio, POWERCFG);
/* try again, if timed out */
if (retval == 0 && timed_out)
return -ENODATA;
return retval;
}
/*
* si470x_start - switch on radio
*/
int si470x_start(struct si470x_device *radio)
{
int retval;
/* powercfg */
radio->registers[POWERCFG] =
POWERCFG_DMUTE | POWERCFG_ENABLE | POWERCFG_RDSM;
retval = radio->set_register(radio, POWERCFG);
if (retval < 0)
goto done;
/* sysconfig 1 */
radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN | SYSCONFIG1_STCIEN |
SYSCONFIG1_RDS;
radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2;
radio->registers[SYSCONFIG1] |= SYSCONFIG1_GPIO2_INT;
if (de)
radio->registers[SYSCONFIG1] |= SYSCONFIG1_DE;
retval = radio->set_register(radio, SYSCONFIG1);
if (retval < 0)
goto done;
/* sysconfig 2 */
radio->registers[SYSCONFIG2] =
(0x1f << 8) | /* SEEKTH */
((radio->band << 6) & SYSCONFIG2_BAND) |/* BAND */
((space << 4) & SYSCONFIG2_SPACE) | /* SPACE */
15; /* VOLUME (max) */
retval = radio->set_register(radio, SYSCONFIG2);
if (retval < 0)
goto done;
/* reset last channel */
retval = si470x_set_chan(radio,
radio->registers[CHANNEL] & CHANNEL_CHAN);
done:
return retval;
}
EXPORT_SYMBOL_GPL(si470x_start);
/*
* si470x_stop - switch off radio
*/
int si470x_stop(struct si470x_device *radio)
{
int retval;
/* sysconfig 1 */
radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_RDS;
retval = radio->set_register(radio, SYSCONFIG1);
if (retval < 0)
goto done;
/* powercfg */
radio->registers[POWERCFG] &= ~POWERCFG_DMUTE;
/* POWERCFG_ENABLE has to automatically go low */
radio->registers[POWERCFG] |= POWERCFG_ENABLE | POWERCFG_DISABLE;
retval = radio->set_register(radio, POWERCFG);
done:
return retval;
}
EXPORT_SYMBOL_GPL(si470x_stop);
/*
* si470x_rds_on - switch on rds reception
*/
static int si470x_rds_on(struct si470x_device *radio)
{
int retval;
/* sysconfig 1 */
radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDS;
retval = radio->set_register(radio, SYSCONFIG1);
if (retval < 0)
radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_RDS;
return retval;
}
/**************************************************************************
* File Operations Interface
**************************************************************************/
/*
* si470x_fops_read - read RDS data
*/
static ssize_t si470x_fops_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct si470x_device *radio = video_drvdata(file);
int retval = 0;
unsigned int block_count = 0;
/* switch on rds reception */
if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0)
si470x_rds_on(radio);
/* block if no new data available */
while (radio->wr_index == radio->rd_index) {
if (file->f_flags & O_NONBLOCK) {
retval = -EWOULDBLOCK;
goto done;
}
if (wait_event_interruptible(radio->read_queue,
radio->wr_index != radio->rd_index) < 0) {
retval = -EINTR;
goto done;
}
}
/* calculate block count from byte count */
count /= 3;
/* copy RDS block out of internal buffer and to user buffer */
while (block_count < count) {
if (radio->rd_index == radio->wr_index)
break;
/* always transfer rds complete blocks */
if (copy_to_user(buf, &radio->buffer[radio->rd_index], 3))
/* retval = -EFAULT; */
break;
/* increment and wrap read pointer */
radio->rd_index += 3;
if (radio->rd_index >= radio->buf_size)
radio->rd_index = 0;
/* increment counters */
block_count++;
buf += 3;
retval += 3;
}
done:
return retval;
}
/*
* si470x_fops_poll - poll RDS data
*/
static __poll_t si470x_fops_poll(struct file *file,
struct poll_table_struct *pts)
{
struct si470x_device *radio = video_drvdata(file);
__poll_t req_events = poll_requested_events(pts);
__poll_t retval = v4l2_ctrl_poll(file, pts);
if (req_events & (EPOLLIN | EPOLLRDNORM)) {
/* switch on rds reception */
if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0)
si470x_rds_on(radio);
poll_wait(file, &radio->read_queue, pts);
if (radio->rd_index != radio->wr_index)
retval |= EPOLLIN | EPOLLRDNORM;
}
return retval;
}
static int si470x_fops_open(struct file *file)
{
struct si470x_device *radio = video_drvdata(file);
return radio->fops_open(file);
}
/*
* si470x_fops_release - file release
*/
static int si470x_fops_release(struct file *file)
{
struct si470x_device *radio = video_drvdata(file);
return radio->fops_release(file);
}
/*
* si470x_fops - file operations interface
*/
static const struct v4l2_file_operations si470x_fops = {
.owner = THIS_MODULE,
.read = si470x_fops_read,
.poll = si470x_fops_poll,
.unlocked_ioctl = video_ioctl2,
.open = si470x_fops_open,
.release = si470x_fops_release,
};
/**************************************************************************
* Video4Linux Interface
**************************************************************************/
static int si470x_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct si470x_device *radio =
container_of(ctrl->handler, struct si470x_device, hdl);
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME:
radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_VOLUME;
radio->registers[SYSCONFIG2] |= ctrl->val;
return radio->set_register(radio, SYSCONFIG2);
case V4L2_CID_AUDIO_MUTE:
if (ctrl->val)
radio->registers[POWERCFG] &= ~POWERCFG_DMUTE;
else
radio->registers[POWERCFG] |= POWERCFG_DMUTE;
return radio->set_register(radio, POWERCFG);
default:
return -EINVAL;
}
}
/*
* si470x_vidioc_g_tuner - get tuner attributes
*/
static int si470x_vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *tuner)
{
struct si470x_device *radio = video_drvdata(file);
int retval = 0;
if (tuner->index != 0)
return -EINVAL;
if (!radio->status_rssi_auto_update) {
retval = radio->get_register(radio, STATUSRSSI);
if (retval < 0)
return retval;
}
/* driver constants */
strscpy(tuner->name, "FM", sizeof(tuner->name));
tuner->type = V4L2_TUNER_RADIO;
tuner->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP;
tuner->rangelow = 76 * FREQ_MUL;
tuner->rangehigh = 108 * FREQ_MUL;
/* stereo indicator == stereo (instead of mono) */
if ((radio->registers[STATUSRSSI] & STATUSRSSI_ST) == 0)
tuner->rxsubchans = V4L2_TUNER_SUB_MONO;
else
tuner->rxsubchans = V4L2_TUNER_SUB_STEREO;
/* If there is a reliable method of detecting an RDS channel,
then this code should check for that before setting this
RDS subchannel. */
tuner->rxsubchans |= V4L2_TUNER_SUB_RDS;
/* mono/stereo selector */
if ((radio->registers[POWERCFG] & POWERCFG_MONO) == 0)
tuner->audmode = V4L2_TUNER_MODE_STEREO;
else
tuner->audmode = V4L2_TUNER_MODE_MONO;
/* min is worst, max is best; signal:0..0xffff; rssi: 0..0xff */
/* measured in units of dbµV in 1 db increments (max at ~75 dbµV) */
tuner->signal = (radio->registers[STATUSRSSI] & STATUSRSSI_RSSI);
/* the ideal factor is 0xffff/75 = 873,8 */
tuner->signal = (tuner->signal * 873) + (8 * tuner->signal / 10);
if (tuner->signal > 0xffff)
tuner->signal = 0xffff;
/* automatic frequency control: -1: freq to low, 1 freq to high */
/* AFCRL does only indicate that freq. differs, not if too low/high */
tuner->afc = (radio->registers[STATUSRSSI] & STATUSRSSI_AFCRL) ? 1 : 0;
return retval;
}
/*
* si470x_vidioc_s_tuner - set tuner attributes
*/
static int si470x_vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *tuner)
{
struct si470x_device *radio = video_drvdata(file);
if (tuner->index != 0)
return -EINVAL;
/* mono/stereo selector */
switch (tuner->audmode) {
case V4L2_TUNER_MODE_MONO:
radio->registers[POWERCFG] |= POWERCFG_MONO; /* force mono */
break;
case V4L2_TUNER_MODE_STEREO:
default:
radio->registers[POWERCFG] &= ~POWERCFG_MONO; /* try stereo */
break;
}
return radio->set_register(radio, POWERCFG);
}
/*
* si470x_vidioc_g_frequency - get tuner or modulator radio frequency
*/
static int si470x_vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *freq)
{
struct si470x_device *radio = video_drvdata(file);
if (freq->tuner != 0)
return -EINVAL;
freq->type = V4L2_TUNER_RADIO;
return si470x_get_freq(radio, &freq->frequency);
}
/*
* si470x_vidioc_s_frequency - set tuner or modulator radio frequency
*/
static int si470x_vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *freq)
{
struct si470x_device *radio = video_drvdata(file);
int retval;
if (freq->tuner != 0)
return -EINVAL;
if (freq->frequency < bands[radio->band].rangelow ||
freq->frequency > bands[radio->band].rangehigh) {
/* Switch to band 1 which covers everything we support */
retval = si470x_set_band(radio, 1);
if (retval)
return retval;
}
return si470x_set_freq(radio, freq->frequency);
}
/*
* si470x_vidioc_s_hw_freq_seek - set hardware frequency seek
*/
static int si470x_vidioc_s_hw_freq_seek(struct file *file, void *priv,
const struct v4l2_hw_freq_seek *seek)
{
struct si470x_device *radio = video_drvdata(file);
if (seek->tuner != 0)
return -EINVAL;
if (file->f_flags & O_NONBLOCK)
return -EWOULDBLOCK;
return si470x_set_seek(radio, seek);
}
/*
* si470x_vidioc_enum_freq_bands - enumerate supported bands
*/
static int si470x_vidioc_enum_freq_bands(struct file *file, void *priv,
struct v4l2_frequency_band *band)
{
if (band->tuner != 0)
return -EINVAL;
if (band->index >= ARRAY_SIZE(bands))
return -EINVAL;
*band = bands[band->index];
return 0;
}
const struct v4l2_ctrl_ops si470x_ctrl_ops = {
.s_ctrl = si470x_s_ctrl,
};
EXPORT_SYMBOL_GPL(si470x_ctrl_ops);
static int si470x_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
struct si470x_device *radio = video_drvdata(file);
return radio->vidioc_querycap(file, priv, capability);
};
/*
* si470x_ioctl_ops - video device ioctl operations
*/
static const struct v4l2_ioctl_ops si470x_ioctl_ops = {
.vidioc_querycap = si470x_vidioc_querycap,
.vidioc_g_tuner = si470x_vidioc_g_tuner,
.vidioc_s_tuner = si470x_vidioc_s_tuner,
.vidioc_g_frequency = si470x_vidioc_g_frequency,
.vidioc_s_frequency = si470x_vidioc_s_frequency,
.vidioc_s_hw_freq_seek = si470x_vidioc_s_hw_freq_seek,
.vidioc_enum_freq_bands = si470x_vidioc_enum_freq_bands,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/*
* si470x_viddev_template - video device interface
*/
const struct video_device si470x_viddev_template = {
.fops = &si470x_fops,
.name = DRIVER_NAME,
.release = video_device_release_empty,
.ioctl_ops = &si470x_ioctl_ops,
};
EXPORT_SYMBOL_GPL(si470x_viddev_template);
MODULE_LICENSE("GPL");
| linux-master | drivers/media/radio/si470x/radio-si470x-common.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/media/radio/si470x/radio-si470x-usb.c
*
* USB driver for radios with Silicon Labs Si470x FM Radio Receivers
*
* Copyright (c) 2009 Tobias Lorenz <[email protected]>
*/
/*
* ToDo:
* - add firmware download/update support
*/
/* driver definitions */
#define DRIVER_AUTHOR "Tobias Lorenz <[email protected]>"
#define DRIVER_CARD "Silicon Labs Si470x FM Radio"
#define DRIVER_DESC "USB radio driver for Si470x FM Radio Receivers"
#define DRIVER_VERSION "1.0.10"
/* kernel includes */
#include <linux/usb.h>
#include <linux/hid.h>
#include <linux/slab.h>
#include "radio-si470x.h"
/* USB Device ID List */
static const struct usb_device_id si470x_usb_driver_id_table[] = {
/* Silicon Labs USB FM Radio Reference Design */
{ USB_DEVICE_AND_INTERFACE_INFO(0x10c4, 0x818a, USB_CLASS_HID, 0, 0) },
/* ADS/Tech FM Radio Receiver (formerly Instant FM Music) */
{ USB_DEVICE_AND_INTERFACE_INFO(0x06e1, 0xa155, USB_CLASS_HID, 0, 0) },
/* KWorld USB FM Radio SnapMusic Mobile 700 (FM700) */
{ USB_DEVICE_AND_INTERFACE_INFO(0x1b80, 0xd700, USB_CLASS_HID, 0, 0) },
/* Sanei Electric, Inc. FM USB Radio (sold as DealExtreme.com PCear) */
{ USB_DEVICE_AND_INTERFACE_INFO(0x10c5, 0x819a, USB_CLASS_HID, 0, 0) },
/* Axentia ALERT FM USB Receiver */
{ USB_DEVICE_AND_INTERFACE_INFO(0x12cf, 0x7111, USB_CLASS_HID, 0, 0) },
/* Terminating entry */
{ }
};
MODULE_DEVICE_TABLE(usb, si470x_usb_driver_id_table);
/**************************************************************************
* Module Parameters
**************************************************************************/
/* Radio Nr */
static int radio_nr = -1;
module_param(radio_nr, int, 0444);
MODULE_PARM_DESC(radio_nr, "Radio Nr");
/* USB timeout */
static unsigned int usb_timeout = 500;
module_param(usb_timeout, uint, 0644);
MODULE_PARM_DESC(usb_timeout, "USB timeout (ms): *500*");
/* RDS buffer blocks */
static unsigned int rds_buf = 100;
module_param(rds_buf, uint, 0444);
MODULE_PARM_DESC(rds_buf, "RDS buffer entries: *100*");
/* RDS maximum block errors */
static unsigned short max_rds_errors = 1;
/* 0 means 0 errors requiring correction */
/* 1 means 1-2 errors requiring correction (used by original USBRadio.exe) */
/* 2 means 3-5 errors requiring correction */
/* 3 means 6+ errors or errors in checkword, correction not possible */
module_param(max_rds_errors, ushort, 0644);
MODULE_PARM_DESC(max_rds_errors, "RDS maximum block errors: *1*");
/**************************************************************************
* USB HID Reports
**************************************************************************/
/* Reports 1-16 give direct read/write access to the 16 Si470x registers */
/* with the (REPORT_ID - 1) corresponding to the register address across USB */
/* endpoint 0 using GET_REPORT and SET_REPORT */
#define REGISTER_REPORT_SIZE (RADIO_REGISTER_SIZE + 1)
#define REGISTER_REPORT(reg) ((reg) + 1)
/* Report 17 gives direct read/write access to the entire Si470x register */
/* map across endpoint 0 using GET_REPORT and SET_REPORT */
#define ENTIRE_REPORT_SIZE (RADIO_REGISTER_NUM * RADIO_REGISTER_SIZE + 1)
#define ENTIRE_REPORT 17
/* Report 18 is used to send the lowest 6 Si470x registers up the HID */
/* interrupt endpoint 1 to Windows every 20 milliseconds for status */
#define RDS_REPORT_SIZE (RDS_REGISTER_NUM * RADIO_REGISTER_SIZE + 1)
#define RDS_REPORT 18
/* Report 19: LED state */
#define LED_REPORT_SIZE 3
#define LED_REPORT 19
/* Report 19: stream */
#define STREAM_REPORT_SIZE 3
#define STREAM_REPORT 19
/* Report 20: scratch */
#define SCRATCH_PAGE_SIZE 63
#define SCRATCH_REPORT_SIZE (SCRATCH_PAGE_SIZE + 1)
#define SCRATCH_REPORT 20
/* Reports 19-22: flash upgrade of the C8051F321 */
#define WRITE_REPORT_SIZE 4
#define WRITE_REPORT 19
#define FLASH_REPORT_SIZE 64
#define FLASH_REPORT 20
#define CRC_REPORT_SIZE 3
#define CRC_REPORT 21
#define RESPONSE_REPORT_SIZE 2
#define RESPONSE_REPORT 22
/* Report 23: currently unused, but can accept 60 byte reports on the HID */
/* interrupt out endpoint 2 every 1 millisecond */
#define UNUSED_REPORT 23
#define MAX_REPORT_SIZE 64
/**************************************************************************
* Software/Hardware Versions from Scratch Page
**************************************************************************/
#define RADIO_HW_VERSION 1
/**************************************************************************
* LED State Definitions
**************************************************************************/
#define LED_COMMAND 0x35
#define NO_CHANGE_LED 0x00
#define ALL_COLOR_LED 0x01 /* streaming state */
#define BLINK_GREEN_LED 0x02 /* connect state */
#define BLINK_RED_LED 0x04
#define BLINK_ORANGE_LED 0x10 /* disconnect state */
#define SOLID_GREEN_LED 0x20 /* tuning/seeking state */
#define SOLID_RED_LED 0x40 /* bootload state */
#define SOLID_ORANGE_LED 0x80
/**************************************************************************
* Stream State Definitions
**************************************************************************/
#define STREAM_COMMAND 0x36
#define STREAM_VIDPID 0x00
#define STREAM_AUDIO 0xff
/**************************************************************************
* Bootloader / Flash Commands
**************************************************************************/
/* unique id sent to bootloader and required to put into a bootload state */
#define UNIQUE_BL_ID 0x34
/* mask for the flash data */
#define FLASH_DATA_MASK 0x55
/* bootloader commands */
#define GET_SW_VERSION_COMMAND 0x00
#define SET_PAGE_COMMAND 0x01
#define ERASE_PAGE_COMMAND 0x02
#define WRITE_PAGE_COMMAND 0x03
#define CRC_ON_PAGE_COMMAND 0x04
#define READ_FLASH_BYTE_COMMAND 0x05
#define RESET_DEVICE_COMMAND 0x06
#define GET_HW_VERSION_COMMAND 0x07
#define BLANK 0xff
/* bootloader command responses */
#define COMMAND_OK 0x01
#define COMMAND_FAILED 0x02
#define COMMAND_PENDING 0x03
/**************************************************************************
* General Driver Functions - REGISTER_REPORTs
**************************************************************************/
/*
* si470x_get_report - receive a HID report
*/
static int si470x_get_report(struct si470x_device *radio, void *buf, int size)
{
unsigned char *report = buf;
int retval;
retval = usb_control_msg(radio->usbdev,
usb_rcvctrlpipe(radio->usbdev, 0),
HID_REQ_GET_REPORT,
USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
report[0], 2,
buf, size, usb_timeout);
if (retval < 0)
dev_warn(&radio->intf->dev,
"si470x_get_report: usb_control_msg returned %d\n",
retval);
return retval;
}
/*
* si470x_set_report - send a HID report
*/
static int si470x_set_report(struct si470x_device *radio, void *buf, int size)
{
unsigned char *report = buf;
int retval;
retval = usb_control_msg(radio->usbdev,
usb_sndctrlpipe(radio->usbdev, 0),
HID_REQ_SET_REPORT,
USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_OUT,
report[0], 2,
buf, size, usb_timeout);
if (retval < 0)
dev_warn(&radio->intf->dev,
"si470x_set_report: usb_control_msg returned %d\n",
retval);
return retval;
}
/*
* si470x_get_register - read register
*/
static int si470x_get_register(struct si470x_device *radio, int regnr)
{
int retval;
radio->usb_buf[0] = REGISTER_REPORT(regnr);
retval = si470x_get_report(radio, radio->usb_buf, REGISTER_REPORT_SIZE);
if (retval >= 0)
radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]);
return (retval < 0) ? -EINVAL : 0;
}
/*
* si470x_set_register - write register
*/
static int si470x_set_register(struct si470x_device *radio, int regnr)
{
int retval;
radio->usb_buf[0] = REGISTER_REPORT(regnr);
put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]);
retval = si470x_set_report(radio, radio->usb_buf, REGISTER_REPORT_SIZE);
return (retval < 0) ? -EINVAL : 0;
}
/**************************************************************************
* General Driver Functions - ENTIRE_REPORT
**************************************************************************/
/*
* si470x_get_all_registers - read entire registers
*/
static int si470x_get_all_registers(struct si470x_device *radio)
{
int retval;
unsigned char regnr;
radio->usb_buf[0] = ENTIRE_REPORT;
retval = si470x_get_report(radio, radio->usb_buf, ENTIRE_REPORT_SIZE);
if (retval >= 0)
for (regnr = 0; regnr < RADIO_REGISTER_NUM; regnr++)
radio->registers[regnr] = get_unaligned_be16(
&radio->usb_buf[regnr * RADIO_REGISTER_SIZE + 1]);
return (retval < 0) ? -EINVAL : 0;
}
/**************************************************************************
* General Driver Functions - LED_REPORT
**************************************************************************/
/*
* si470x_set_led_state - sets the led state
*/
static int si470x_set_led_state(struct si470x_device *radio,
unsigned char led_state)
{
int retval;
radio->usb_buf[0] = LED_REPORT;
radio->usb_buf[1] = LED_COMMAND;
radio->usb_buf[2] = led_state;
retval = si470x_set_report(radio, radio->usb_buf, LED_REPORT_SIZE);
return (retval < 0) ? -EINVAL : 0;
}
/**************************************************************************
* General Driver Functions - SCRATCH_REPORT
**************************************************************************/
/*
* si470x_get_scratch_versions - gets the scratch page and version infos
*/
static int si470x_get_scratch_page_versions(struct si470x_device *radio)
{
int retval;
radio->usb_buf[0] = SCRATCH_REPORT;
retval = si470x_get_report(radio, radio->usb_buf, SCRATCH_REPORT_SIZE);
if (retval < 0)
dev_warn(&radio->intf->dev, "si470x_get_scratch: si470x_get_report returned %d\n",
retval);
else {
radio->software_version = radio->usb_buf[1];
radio->hardware_version = radio->usb_buf[2];
}
return (retval < 0) ? -EINVAL : 0;
}
/**************************************************************************
* RDS Driver Functions
**************************************************************************/
/*
* si470x_int_in_callback - rds callback and processing function
*
* TODO: do we need to use mutex locks in some sections?
*/
static void si470x_int_in_callback(struct urb *urb)
{
struct si470x_device *radio = urb->context;
int retval;
unsigned char regnr;
unsigned char blocknum;
unsigned short bler; /* rds block errors */
unsigned short rds;
unsigned char tmpbuf[3];
if (urb->status) {
if (urb->status == -ENOENT ||
urb->status == -ECONNRESET ||
urb->status == -ESHUTDOWN) {
return;
} else {
dev_warn(&radio->intf->dev,
"non-zero urb status (%d)\n", urb->status);
goto resubmit; /* Maybe we can recover. */
}
}
/* Sometimes the device returns len 0 packets */
if (urb->actual_length != RDS_REPORT_SIZE)
goto resubmit;
radio->registers[STATUSRSSI] =
get_unaligned_be16(&radio->int_in_buffer[1]);
if (radio->registers[STATUSRSSI] & STATUSRSSI_STC)
complete(&radio->completion);
if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) {
/* Update RDS registers with URB data */
for (regnr = 1; regnr < RDS_REGISTER_NUM; regnr++)
radio->registers[STATUSRSSI + regnr] =
get_unaligned_be16(&radio->int_in_buffer[
regnr * RADIO_REGISTER_SIZE + 1]);
/* get rds blocks */
if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) {
/* No RDS group ready, better luck next time */
goto resubmit;
}
if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) {
/* RDS decoder not synchronized */
goto resubmit;
}
for (blocknum = 0; blocknum < 4; blocknum++) {
switch (blocknum) {
default:
bler = (radio->registers[STATUSRSSI] &
STATUSRSSI_BLERA) >> 9;
rds = radio->registers[RDSA];
break;
case 1:
bler = (radio->registers[READCHAN] &
READCHAN_BLERB) >> 14;
rds = radio->registers[RDSB];
break;
case 2:
bler = (radio->registers[READCHAN] &
READCHAN_BLERC) >> 12;
rds = radio->registers[RDSC];
break;
case 3:
bler = (radio->registers[READCHAN] &
READCHAN_BLERD) >> 10;
rds = radio->registers[RDSD];
break;
}
/* Fill the V4L2 RDS buffer */
put_unaligned_le16(rds, &tmpbuf);
tmpbuf[2] = blocknum; /* offset name */
tmpbuf[2] |= blocknum << 3; /* received offset */
if (bler > max_rds_errors)
tmpbuf[2] |= 0x80; /* uncorrectable errors */
else if (bler > 0)
tmpbuf[2] |= 0x40; /* corrected error(s) */
/* copy RDS block to internal buffer */
memcpy(&radio->buffer[radio->wr_index], &tmpbuf, 3);
radio->wr_index += 3;
/* wrap write pointer */
if (radio->wr_index >= radio->buf_size)
radio->wr_index = 0;
/* check for overflow */
if (radio->wr_index == radio->rd_index) {
/* increment and wrap read pointer */
radio->rd_index += 3;
if (radio->rd_index >= radio->buf_size)
radio->rd_index = 0;
}
}
if (radio->wr_index != radio->rd_index)
wake_up_interruptible(&radio->read_queue);
}
resubmit:
/* Resubmit if we're still running. */
if (radio->int_in_running && radio->usbdev) {
retval = usb_submit_urb(radio->int_in_urb, GFP_ATOMIC);
if (retval) {
dev_warn(&radio->intf->dev,
"resubmitting urb failed (%d)", retval);
radio->int_in_running = 0;
}
}
radio->status_rssi_auto_update = radio->int_in_running;
}
static int si470x_fops_open(struct file *file)
{
return v4l2_fh_open(file);
}
static int si470x_fops_release(struct file *file)
{
return v4l2_fh_release(file);
}
static void si470x_usb_release(struct v4l2_device *v4l2_dev)
{
struct si470x_device *radio =
container_of(v4l2_dev, struct si470x_device, v4l2_dev);
usb_free_urb(radio->int_in_urb);
v4l2_ctrl_handler_free(&radio->hdl);
v4l2_device_unregister(&radio->v4l2_dev);
kfree(radio->int_in_buffer);
kfree(radio->buffer);
kfree(radio->usb_buf);
kfree(radio);
}
/**************************************************************************
* Video4Linux Interface
**************************************************************************/
/*
* si470x_vidioc_querycap - query device capabilities
*/
static int si470x_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
struct si470x_device *radio = video_drvdata(file);
strscpy(capability->driver, DRIVER_NAME, sizeof(capability->driver));
strscpy(capability->card, DRIVER_CARD, sizeof(capability->card));
usb_make_path(radio->usbdev, capability->bus_info,
sizeof(capability->bus_info));
return 0;
}
static int si470x_start_usb(struct si470x_device *radio)
{
int retval;
/* initialize interrupt urb */
usb_fill_int_urb(radio->int_in_urb, radio->usbdev,
usb_rcvintpipe(radio->usbdev,
radio->int_in_endpoint->bEndpointAddress),
radio->int_in_buffer,
le16_to_cpu(radio->int_in_endpoint->wMaxPacketSize),
si470x_int_in_callback,
radio,
radio->int_in_endpoint->bInterval);
radio->int_in_running = 1;
mb();
retval = usb_submit_urb(radio->int_in_urb, GFP_KERNEL);
if (retval) {
dev_info(&radio->intf->dev,
"submitting int urb failed (%d)\n", retval);
radio->int_in_running = 0;
}
radio->status_rssi_auto_update = radio->int_in_running;
/* start radio */
retval = si470x_start(radio);
if (retval < 0)
return retval;
v4l2_ctrl_handler_setup(&radio->hdl);
return retval;
}
/**************************************************************************
* USB Interface
**************************************************************************/
/*
* si470x_usb_driver_probe - probe for the device
*/
static int si470x_usb_driver_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
struct si470x_device *radio;
struct usb_host_interface *iface_desc;
struct usb_endpoint_descriptor *endpoint;
int i, int_end_size, retval;
unsigned char version_warning = 0;
/* private data allocation and initialization */
radio = kzalloc(sizeof(struct si470x_device), GFP_KERNEL);
if (!radio) {
retval = -ENOMEM;
goto err_initial;
}
radio->usb_buf = kmalloc(MAX_REPORT_SIZE, GFP_KERNEL);
if (radio->usb_buf == NULL) {
retval = -ENOMEM;
goto err_radio;
}
radio->usbdev = interface_to_usbdev(intf);
radio->intf = intf;
radio->band = 1; /* Default to 76 - 108 MHz */
mutex_init(&radio->lock);
init_completion(&radio->completion);
radio->get_register = si470x_get_register;
radio->set_register = si470x_set_register;
radio->fops_open = si470x_fops_open;
radio->fops_release = si470x_fops_release;
radio->vidioc_querycap = si470x_vidioc_querycap;
iface_desc = intf->cur_altsetting;
/* Set up interrupt endpoint information. */
for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
endpoint = &iface_desc->endpoint[i].desc;
if (usb_endpoint_is_int_in(endpoint))
radio->int_in_endpoint = endpoint;
}
if (!radio->int_in_endpoint) {
dev_info(&intf->dev, "could not find interrupt in endpoint\n");
retval = -EIO;
goto err_usbbuf;
}
int_end_size = le16_to_cpu(radio->int_in_endpoint->wMaxPacketSize);
radio->int_in_buffer = kmalloc(int_end_size, GFP_KERNEL);
if (!radio->int_in_buffer) {
dev_info(&intf->dev, "could not allocate int_in_buffer");
retval = -ENOMEM;
goto err_usbbuf;
}
radio->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!radio->int_in_urb) {
retval = -ENOMEM;
goto err_intbuffer;
}
radio->v4l2_dev.release = si470x_usb_release;
/*
* The si470x SiLabs reference design uses the same USB IDs as
* 'Thanko's Raremono' si4734 based receiver. So check here which we
* have: attempt to read the device ID from the si470x: the lower 12
* bits should be 0x0242 for the si470x.
*
* We use this check to determine which device we are dealing with.
*/
if (id->idVendor == 0x10c4 && id->idProduct == 0x818a) {
retval = usb_control_msg(radio->usbdev,
usb_rcvctrlpipe(radio->usbdev, 0),
HID_REQ_GET_REPORT,
USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
1, 2,
radio->usb_buf, 3, 500);
if (retval != 3 ||
(get_unaligned_be16(&radio->usb_buf[1]) & 0xfff) != 0x0242) {
dev_info(&intf->dev, "this is not a si470x device.\n");
retval = -ENODEV;
goto err_urb;
}
}
retval = v4l2_device_register(&intf->dev, &radio->v4l2_dev);
if (retval < 0) {
dev_err(&intf->dev, "couldn't register v4l2_device\n");
goto err_urb;
}
v4l2_ctrl_handler_init(&radio->hdl, 2);
v4l2_ctrl_new_std(&radio->hdl, &si470x_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1);
v4l2_ctrl_new_std(&radio->hdl, &si470x_ctrl_ops,
V4L2_CID_AUDIO_VOLUME, 0, 15, 1, 15);
if (radio->hdl.error) {
retval = radio->hdl.error;
dev_err(&intf->dev, "couldn't register control\n");
goto err_dev;
}
radio->videodev = si470x_viddev_template;
radio->videodev.ctrl_handler = &radio->hdl;
radio->videodev.lock = &radio->lock;
radio->videodev.v4l2_dev = &radio->v4l2_dev;
radio->videodev.release = video_device_release_empty;
radio->videodev.device_caps =
V4L2_CAP_HW_FREQ_SEEK | V4L2_CAP_READWRITE | V4L2_CAP_TUNER |
V4L2_CAP_RADIO | V4L2_CAP_RDS_CAPTURE;
video_set_drvdata(&radio->videodev, radio);
/* get device and chip versions */
if (si470x_get_all_registers(radio) < 0) {
retval = -EIO;
goto err_ctrl;
}
dev_info(&intf->dev, "DeviceID=0x%4.4hx ChipID=0x%4.4hx\n",
radio->registers[DEVICEID], radio->registers[SI_CHIPID]);
if ((radio->registers[SI_CHIPID] & SI_CHIPID_FIRMWARE) < RADIO_FW_VERSION) {
dev_warn(&intf->dev,
"This driver is known to work with firmware version %u, but the device has firmware version %u.\n",
RADIO_FW_VERSION,
radio->registers[SI_CHIPID] & SI_CHIPID_FIRMWARE);
version_warning = 1;
}
/* get software and hardware versions */
if (si470x_get_scratch_page_versions(radio) < 0) {
retval = -EIO;
goto err_ctrl;
}
dev_info(&intf->dev, "software version %d, hardware version %d\n",
radio->software_version, radio->hardware_version);
if (radio->hardware_version < RADIO_HW_VERSION) {
dev_warn(&intf->dev,
"This driver is known to work with hardware version %u, but the device has hardware version %u.\n",
RADIO_HW_VERSION,
radio->hardware_version);
version_warning = 1;
}
/* give out version warning */
if (version_warning == 1) {
dev_warn(&intf->dev,
"If you have some trouble using this driver, please report to V4L ML at [email protected]\n");
}
/* set led to connect state */
si470x_set_led_state(radio, BLINK_GREEN_LED);
/* rds buffer allocation */
radio->buf_size = rds_buf * 3;
radio->buffer = kmalloc(radio->buf_size, GFP_KERNEL);
if (!radio->buffer) {
retval = -EIO;
goto err_ctrl;
}
/* rds buffer configuration */
radio->wr_index = 0;
radio->rd_index = 0;
init_waitqueue_head(&radio->read_queue);
usb_set_intfdata(intf, radio);
/* start radio */
retval = si470x_start_usb(radio);
if (retval < 0 && !radio->int_in_running)
goto err_buf;
else if (retval < 0) /* in case of radio->int_in_running == 1 */
goto err_all;
/* set initial frequency */
si470x_set_freq(radio, 87.5 * FREQ_MUL); /* available in all regions */
/* register video device */
retval = video_register_device(&radio->videodev, VFL_TYPE_RADIO,
radio_nr);
if (retval) {
dev_err(&intf->dev, "Could not register video device\n");
goto err_all;
}
return 0;
err_all:
usb_kill_urb(radio->int_in_urb);
err_buf:
kfree(radio->buffer);
err_ctrl:
v4l2_ctrl_handler_free(&radio->hdl);
err_dev:
v4l2_device_unregister(&radio->v4l2_dev);
err_urb:
usb_free_urb(radio->int_in_urb);
err_intbuffer:
kfree(radio->int_in_buffer);
err_usbbuf:
kfree(radio->usb_buf);
err_radio:
kfree(radio);
err_initial:
return retval;
}
/*
* si470x_usb_driver_suspend - suspend the device
*/
static int si470x_usb_driver_suspend(struct usb_interface *intf,
pm_message_t message)
{
struct si470x_device *radio = usb_get_intfdata(intf);
dev_info(&intf->dev, "suspending now...\n");
/* shutdown interrupt handler */
if (radio->int_in_running) {
radio->int_in_running = 0;
if (radio->int_in_urb)
usb_kill_urb(radio->int_in_urb);
}
/* cancel read processes */
wake_up_interruptible(&radio->read_queue);
/* stop radio */
si470x_stop(radio);
return 0;
}
/*
* si470x_usb_driver_resume - resume the device
*/
static int si470x_usb_driver_resume(struct usb_interface *intf)
{
struct si470x_device *radio = usb_get_intfdata(intf);
int ret;
dev_info(&intf->dev, "resuming now...\n");
/* start radio */
ret = si470x_start_usb(radio);
if (ret == 0)
v4l2_ctrl_handler_setup(&radio->hdl);
return ret;
}
/*
* si470x_usb_driver_disconnect - disconnect the device
*/
static void si470x_usb_driver_disconnect(struct usb_interface *intf)
{
struct si470x_device *radio = usb_get_intfdata(intf);
mutex_lock(&radio->lock);
v4l2_device_disconnect(&radio->v4l2_dev);
video_unregister_device(&radio->videodev);
usb_kill_urb(radio->int_in_urb);
usb_set_intfdata(intf, NULL);
mutex_unlock(&radio->lock);
v4l2_device_put(&radio->v4l2_dev);
}
/*
* si470x_usb_driver - usb driver interface
*
* A note on suspend/resume: this driver had only empty suspend/resume
* functions, and when I tried to test suspend/resume it always disconnected
* instead of resuming (using my ADS InstantFM stick). So I've decided to
* remove these callbacks until someone else with better hardware can
* implement and test this.
*/
static struct usb_driver si470x_usb_driver = {
.name = DRIVER_NAME,
.probe = si470x_usb_driver_probe,
.disconnect = si470x_usb_driver_disconnect,
.suspend = si470x_usb_driver_suspend,
.resume = si470x_usb_driver_resume,
.reset_resume = si470x_usb_driver_resume,
.id_table = si470x_usb_driver_id_table,
};
module_usb_driver(si470x_usb_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_VERSION(DRIVER_VERSION);
| linux-master | drivers/media/radio/si470x/radio-si470x-usb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/media/radio/si470x/radio-si470x-i2c.c
*
* I2C driver for radios with Silicon Labs Si470x FM Radio Receivers
*
* Copyright (c) 2009 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <[email protected]>
*/
/* driver definitions */
#define DRIVER_AUTHOR "Joonyoung Shim <[email protected]>";
#define DRIVER_CARD "Silicon Labs Si470x FM Radio"
#define DRIVER_DESC "I2C radio driver for Si470x FM Radio Receivers"
#define DRIVER_VERSION "1.0.2"
/* kernel includes */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include "radio-si470x.h"
/* I2C Device ID List */
static const struct i2c_device_id si470x_i2c_id[] = {
/* Generic Entry */
{ "si470x", 0 },
/* Terminating entry */
{ }
};
MODULE_DEVICE_TABLE(i2c, si470x_i2c_id);
/**************************************************************************
* Module Parameters
**************************************************************************/
/* Radio Nr */
static int radio_nr = -1;
module_param(radio_nr, int, 0444);
MODULE_PARM_DESC(radio_nr, "Radio Nr");
/* RDS buffer blocks */
static unsigned int rds_buf = 100;
module_param(rds_buf, uint, 0444);
MODULE_PARM_DESC(rds_buf, "RDS buffer entries: *100*");
/* RDS maximum block errors */
static unsigned short max_rds_errors = 1;
/* 0 means 0 errors requiring correction */
/* 1 means 1-2 errors requiring correction (used by original USBRadio.exe) */
/* 2 means 3-5 errors requiring correction */
/* 3 means 6+ errors or errors in checkword, correction not possible */
module_param(max_rds_errors, ushort, 0644);
MODULE_PARM_DESC(max_rds_errors, "RDS maximum block errors: *1*");
/**************************************************************************
* I2C Definitions
**************************************************************************/
/* Write starts with the upper byte of register 0x02 */
#define WRITE_REG_NUM 8
#define WRITE_INDEX(i) (i + 0x02)
/* Read starts with the upper byte of register 0x0a */
#define READ_REG_NUM RADIO_REGISTER_NUM
#define READ_INDEX(i) ((i + RADIO_REGISTER_NUM - 0x0a) % READ_REG_NUM)
/**************************************************************************
* General Driver Functions - REGISTERs
**************************************************************************/
/*
* si470x_get_register - read register
*/
static int si470x_get_register(struct si470x_device *radio, int regnr)
{
__be16 buf[READ_REG_NUM];
struct i2c_msg msgs[1] = {
{
.addr = radio->client->addr,
.flags = I2C_M_RD,
.len = sizeof(u16) * READ_REG_NUM,
.buf = (void *)buf
},
};
if (i2c_transfer(radio->client->adapter, msgs, 1) != 1)
return -EIO;
radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]);
return 0;
}
/*
* si470x_set_register - write register
*/
static int si470x_set_register(struct si470x_device *radio, int regnr)
{
int i;
__be16 buf[WRITE_REG_NUM];
struct i2c_msg msgs[1] = {
{
.addr = radio->client->addr,
.len = sizeof(u16) * WRITE_REG_NUM,
.buf = (void *)buf
},
};
for (i = 0; i < WRITE_REG_NUM; i++)
buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]);
if (i2c_transfer(radio->client->adapter, msgs, 1) != 1)
return -EIO;
return 0;
}
/**************************************************************************
* General Driver Functions - ENTIRE REGISTERS
**************************************************************************/
/*
* si470x_get_all_registers - read entire registers
*/
static int si470x_get_all_registers(struct si470x_device *radio)
{
int i;
__be16 buf[READ_REG_NUM];
struct i2c_msg msgs[1] = {
{
.addr = radio->client->addr,
.flags = I2C_M_RD,
.len = sizeof(u16) * READ_REG_NUM,
.buf = (void *)buf
},
};
if (i2c_transfer(radio->client->adapter, msgs, 1) != 1)
return -EIO;
for (i = 0; i < READ_REG_NUM; i++)
radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]);
return 0;
}
/**************************************************************************
* File Operations Interface
**************************************************************************/
/*
* si470x_fops_open - file open
*/
static int si470x_fops_open(struct file *file)
{
struct si470x_device *radio = video_drvdata(file);
int retval = v4l2_fh_open(file);
if (retval)
return retval;
if (v4l2_fh_is_singular_file(file)) {
/* start radio */
retval = si470x_start(radio);
if (retval < 0)
goto done;
/* enable RDS / STC interrupt */
radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN;
radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN;
radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2;
radio->registers[SYSCONFIG1] |= 0x1 << 2;
retval = si470x_set_register(radio, SYSCONFIG1);
}
done:
if (retval)
v4l2_fh_release(file);
return retval;
}
/*
* si470x_fops_release - file release
*/
static int si470x_fops_release(struct file *file)
{
struct si470x_device *radio = video_drvdata(file);
if (v4l2_fh_is_singular_file(file))
/* stop radio */
si470x_stop(radio);
return v4l2_fh_release(file);
}
/**************************************************************************
* Video4Linux Interface
**************************************************************************/
/*
* si470x_vidioc_querycap - query device capabilities
*/
static int si470x_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
strscpy(capability->driver, DRIVER_NAME, sizeof(capability->driver));
strscpy(capability->card, DRIVER_CARD, sizeof(capability->card));
return 0;
}
/**************************************************************************
* I2C Interface
**************************************************************************/
/*
* si470x_i2c_interrupt - interrupt handler
*/
static irqreturn_t si470x_i2c_interrupt(int irq, void *dev_id)
{
struct si470x_device *radio = dev_id;
unsigned char regnr;
unsigned char blocknum;
unsigned short bler; /* rds block errors */
unsigned short rds;
unsigned char tmpbuf[3];
int retval = 0;
/* check Seek/Tune Complete */
retval = si470x_get_register(radio, STATUSRSSI);
if (retval < 0)
goto end;
if (radio->registers[STATUSRSSI] & STATUSRSSI_STC)
complete(&radio->completion);
/* safety checks */
if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0)
goto end;
/* Update RDS registers */
for (regnr = 1; regnr < RDS_REGISTER_NUM; regnr++) {
retval = si470x_get_register(radio, STATUSRSSI + regnr);
if (retval < 0)
goto end;
}
/* get rds blocks */
if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0)
/* No RDS group ready, better luck next time */
goto end;
for (blocknum = 0; blocknum < 4; blocknum++) {
switch (blocknum) {
default:
bler = (radio->registers[STATUSRSSI] &
STATUSRSSI_BLERA) >> 9;
rds = radio->registers[RDSA];
break;
case 1:
bler = (radio->registers[READCHAN] &
READCHAN_BLERB) >> 14;
rds = radio->registers[RDSB];
break;
case 2:
bler = (radio->registers[READCHAN] &
READCHAN_BLERC) >> 12;
rds = radio->registers[RDSC];
break;
case 3:
bler = (radio->registers[READCHAN] &
READCHAN_BLERD) >> 10;
rds = radio->registers[RDSD];
break;
}
/* Fill the V4L2 RDS buffer */
put_unaligned_le16(rds, &tmpbuf);
tmpbuf[2] = blocknum; /* offset name */
tmpbuf[2] |= blocknum << 3; /* received offset */
if (bler > max_rds_errors)
tmpbuf[2] |= 0x80; /* uncorrectable errors */
else if (bler > 0)
tmpbuf[2] |= 0x40; /* corrected error(s) */
/* copy RDS block to internal buffer */
memcpy(&radio->buffer[radio->wr_index], &tmpbuf, 3);
radio->wr_index += 3;
/* wrap write pointer */
if (radio->wr_index >= radio->buf_size)
radio->wr_index = 0;
/* check for overflow */
if (radio->wr_index == radio->rd_index) {
/* increment and wrap read pointer */
radio->rd_index += 3;
if (radio->rd_index >= radio->buf_size)
radio->rd_index = 0;
}
}
if (radio->wr_index != radio->rd_index)
wake_up_interruptible(&radio->read_queue);
end:
return IRQ_HANDLED;
}
/*
* si470x_i2c_probe - probe for the device
*/
static int si470x_i2c_probe(struct i2c_client *client)
{
struct si470x_device *radio;
int retval = 0;
/* private data allocation and initialization */
radio = devm_kzalloc(&client->dev, sizeof(*radio), GFP_KERNEL);
if (!radio) {
retval = -ENOMEM;
goto err_initial;
}
radio->client = client;
radio->band = 1; /* Default to 76 - 108 MHz */
mutex_init(&radio->lock);
init_completion(&radio->completion);
radio->get_register = si470x_get_register;
radio->set_register = si470x_set_register;
radio->fops_open = si470x_fops_open;
radio->fops_release = si470x_fops_release;
radio->vidioc_querycap = si470x_vidioc_querycap;
retval = v4l2_device_register(&client->dev, &radio->v4l2_dev);
if (retval < 0) {
dev_err(&client->dev, "couldn't register v4l2_device\n");
goto err_initial;
}
v4l2_ctrl_handler_init(&radio->hdl, 2);
v4l2_ctrl_new_std(&radio->hdl, &si470x_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1);
v4l2_ctrl_new_std(&radio->hdl, &si470x_ctrl_ops,
V4L2_CID_AUDIO_VOLUME, 0, 15, 1, 15);
if (radio->hdl.error) {
retval = radio->hdl.error;
dev_err(&client->dev, "couldn't register control\n");
goto err_all;
}
/* video device initialization */
radio->videodev = si470x_viddev_template;
radio->videodev.ctrl_handler = &radio->hdl;
radio->videodev.lock = &radio->lock;
radio->videodev.v4l2_dev = &radio->v4l2_dev;
radio->videodev.release = video_device_release_empty;
radio->videodev.device_caps =
V4L2_CAP_HW_FREQ_SEEK | V4L2_CAP_READWRITE | V4L2_CAP_TUNER |
V4L2_CAP_RADIO | V4L2_CAP_RDS_CAPTURE;
video_set_drvdata(&radio->videodev, radio);
radio->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(radio->gpio_reset)) {
retval = PTR_ERR(radio->gpio_reset);
dev_err(&client->dev, "Failed to request gpio: %d\n", retval);
goto err_all;
}
if (radio->gpio_reset)
gpiod_set_value(radio->gpio_reset, 1);
/* power up : need 110ms */
radio->registers[POWERCFG] = POWERCFG_ENABLE;
if (si470x_set_register(radio, POWERCFG) < 0) {
retval = -EIO;
goto err_all;
}
msleep(110);
/* get device and chip versions */
if (si470x_get_all_registers(radio) < 0) {
retval = -EIO;
goto err_all;
}
dev_info(&client->dev, "DeviceID=0x%4.4hx ChipID=0x%4.4hx\n",
radio->registers[DEVICEID], radio->registers[SI_CHIPID]);
if ((radio->registers[SI_CHIPID] & SI_CHIPID_FIRMWARE) < RADIO_FW_VERSION) {
dev_warn(&client->dev,
"This driver is known to work with firmware version %u, but the device has firmware version %u.\n"
"If you have some trouble using this driver, please report to V4L ML at [email protected]\n",
RADIO_FW_VERSION,
radio->registers[SI_CHIPID] & SI_CHIPID_FIRMWARE);
}
/* set initial frequency */
si470x_set_freq(radio, 87.5 * FREQ_MUL); /* available in all regions */
/* rds buffer allocation */
radio->buf_size = rds_buf * 3;
radio->buffer = devm_kmalloc(&client->dev, radio->buf_size, GFP_KERNEL);
if (!radio->buffer) {
retval = -EIO;
goto err_all;
}
/* rds buffer configuration */
radio->wr_index = 0;
radio->rd_index = 0;
init_waitqueue_head(&radio->read_queue);
retval = devm_request_threaded_irq(&client->dev, client->irq, NULL,
si470x_i2c_interrupt,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
DRIVER_NAME, radio);
if (retval) {
dev_err(&client->dev, "Failed to register interrupt\n");
goto err_all;
}
/* register video device */
retval = video_register_device(&radio->videodev, VFL_TYPE_RADIO,
radio_nr);
if (retval) {
dev_warn(&client->dev, "Could not register video device\n");
goto err_all;
}
i2c_set_clientdata(client, radio);
return 0;
err_all:
v4l2_ctrl_handler_free(&radio->hdl);
v4l2_device_unregister(&radio->v4l2_dev);
err_initial:
return retval;
}
/*
* si470x_i2c_remove - remove the device
*/
static void si470x_i2c_remove(struct i2c_client *client)
{
struct si470x_device *radio = i2c_get_clientdata(client);
video_unregister_device(&radio->videodev);
if (radio->gpio_reset)
gpiod_set_value(radio->gpio_reset, 0);
v4l2_ctrl_handler_free(&radio->hdl);
v4l2_device_unregister(&radio->v4l2_dev);
}
#ifdef CONFIG_PM_SLEEP
/*
* si470x_i2c_suspend - suspend the device
*/
static int si470x_i2c_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct si470x_device *radio = i2c_get_clientdata(client);
/* power down */
radio->registers[POWERCFG] |= POWERCFG_DISABLE;
if (si470x_set_register(radio, POWERCFG) < 0)
return -EIO;
return 0;
}
/*
* si470x_i2c_resume - resume the device
*/
static int si470x_i2c_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct si470x_device *radio = i2c_get_clientdata(client);
/* power up : need 110ms */
radio->registers[POWERCFG] |= POWERCFG_ENABLE;
if (si470x_set_register(radio, POWERCFG) < 0)
return -EIO;
msleep(110);
return 0;
}
static SIMPLE_DEV_PM_OPS(si470x_i2c_pm, si470x_i2c_suspend, si470x_i2c_resume);
#endif
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id si470x_of_match[] = {
{ .compatible = "silabs,si470x" },
{ },
};
MODULE_DEVICE_TABLE(of, si470x_of_match);
#endif
/*
* si470x_i2c_driver - i2c driver interface
*/
static struct i2c_driver si470x_i2c_driver = {
.driver = {
.name = "si470x",
.of_match_table = of_match_ptr(si470x_of_match),
#ifdef CONFIG_PM_SLEEP
.pm = &si470x_i2c_pm,
#endif
},
.probe = si470x_i2c_probe,
.remove = si470x_i2c_remove,
.id_table = si470x_i2c_id,
};
module_i2c_driver(si470x_i2c_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_VERSION(DRIVER_VERSION);
| linux-master | drivers/media/radio/si470x/radio-si470x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* dvb_ca.c: generic DVB functions for EN50221 CAM interfaces
*
* Copyright (C) 2004 Andrew de Quincey
*
* Parts of this file were based on sources as follows:
*
* Copyright (C) 2003 Ralph Metzler <[email protected]>
*
* based on code:
*
* Copyright (C) 1999-2002 Ralph Metzler
* & Marcus Metzler for convergence integrated media GmbH
*/
#define pr_fmt(fmt) "dvb_ca_en50221: " fmt
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/nospec.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/sched/signal.h>
#include <linux/kthread.h>
#include <media/dvb_ca_en50221.h>
#include <media/dvb_ringbuffer.h>
static int dvb_ca_en50221_debug;
module_param_named(cam_debug, dvb_ca_en50221_debug, int, 0644);
MODULE_PARM_DESC(cam_debug, "enable verbose debug messages");
#define dprintk(fmt, arg...) do { \
if (dvb_ca_en50221_debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), __func__, ##arg);\
} while (0)
#define INIT_TIMEOUT_SECS 10
#define HOST_LINK_BUF_SIZE 0x200
#define RX_BUFFER_SIZE 65535
#define MAX_RX_PACKETS_PER_ITERATION 10
#define CTRLIF_DATA 0
#define CTRLIF_COMMAND 1
#define CTRLIF_STATUS 1
#define CTRLIF_SIZE_LOW 2
#define CTRLIF_SIZE_HIGH 3
#define CMDREG_HC 1 /* Host control */
#define CMDREG_SW 2 /* Size write */
#define CMDREG_SR 4 /* Size read */
#define CMDREG_RS 8 /* Reset interface */
#define CMDREG_FRIE 0x40 /* Enable FR interrupt */
#define CMDREG_DAIE 0x80 /* Enable DA interrupt */
#define IRQEN (CMDREG_DAIE)
#define STATUSREG_RE 1 /* read error */
#define STATUSREG_WE 2 /* write error */
#define STATUSREG_FR 0x40 /* module free */
#define STATUSREG_DA 0x80 /* data available */
#define DVB_CA_SLOTSTATE_NONE 0
#define DVB_CA_SLOTSTATE_UNINITIALISED 1
#define DVB_CA_SLOTSTATE_RUNNING 2
#define DVB_CA_SLOTSTATE_INVALID 3
#define DVB_CA_SLOTSTATE_WAITREADY 4
#define DVB_CA_SLOTSTATE_VALIDATE 5
#define DVB_CA_SLOTSTATE_WAITFR 6
#define DVB_CA_SLOTSTATE_LINKINIT 7
/* Information on a CA slot */
struct dvb_ca_slot {
/* current state of the CAM */
int slot_state;
/* mutex used for serializing access to one CI slot */
struct mutex slot_lock;
/* Number of CAMCHANGES that have occurred since last processing */
atomic_t camchange_count;
/* Type of last CAMCHANGE */
int camchange_type;
/* base address of CAM config */
u32 config_base;
/* value to write into Config Control register */
u8 config_option;
/* if 1, the CAM supports DA IRQs */
u8 da_irq_supported:1;
/* size of the buffer to use when talking to the CAM */
int link_buf_size;
/* buffer for incoming packets */
struct dvb_ringbuffer rx_buffer;
/* timer used during various states of the slot */
unsigned long timeout;
};
/* Private CA-interface information */
struct dvb_ca_private {
struct kref refcount;
/* pointer back to the public data structure */
struct dvb_ca_en50221 *pub;
/* the DVB device */
struct dvb_device *dvbdev;
/* Flags describing the interface (DVB_CA_FLAG_*) */
u32 flags;
/* number of slots supported by this CA interface */
unsigned int slot_count;
/* information on each slot */
struct dvb_ca_slot *slot_info;
/* wait queues for read() and write() operations */
wait_queue_head_t wait_queue;
/* PID of the monitoring thread */
struct task_struct *thread;
/* Flag indicating if the CA device is open */
unsigned int open:1;
/* Flag indicating the thread should wake up now */
unsigned int wakeup:1;
/* Delay the main thread should use */
unsigned long delay;
/*
* Slot to start looking for data to read from in the next user-space
* read operation
*/
int next_read_slot;
/* mutex serializing ioctls */
struct mutex ioctl_mutex;
/* A mutex used when a device is disconnected */
struct mutex remove_mutex;
/* Whether the device is disconnected */
int exit;
};
static void dvb_ca_private_free(struct dvb_ca_private *ca)
{
unsigned int i;
dvb_device_put(ca->dvbdev);
for (i = 0; i < ca->slot_count; i++)
vfree(ca->slot_info[i].rx_buffer.data);
kfree(ca->slot_info);
kfree(ca);
}
static void dvb_ca_private_release(struct kref *ref)
{
struct dvb_ca_private *ca;
ca = container_of(ref, struct dvb_ca_private, refcount);
dvb_ca_private_free(ca);
}
static void dvb_ca_private_get(struct dvb_ca_private *ca)
{
kref_get(&ca->refcount);
}
static void dvb_ca_private_put(struct dvb_ca_private *ca)
{
kref_put(&ca->refcount, dvb_ca_private_release);
}
static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca);
static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot,
u8 *ebuf, int ecount);
static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot,
u8 *ebuf, int ecount, int size_write_flag);
/**
* findstr - Safely find needle in haystack.
*
* @haystack: Buffer to look in.
* @hlen: Number of bytes in haystack.
* @needle: Buffer to find.
* @nlen: Number of bytes in needle.
* return: Pointer into haystack needle was found at, or NULL if not found.
*/
static char *findstr(char *haystack, int hlen, char *needle, int nlen)
{
int i;
if (hlen < nlen)
return NULL;
for (i = 0; i <= hlen - nlen; i++) {
if (!strncmp(haystack + i, needle, nlen))
return haystack + i;
}
return NULL;
}
/* ************************************************************************** */
/* EN50221 physical interface functions */
/*
* dvb_ca_en50221_check_camstatus - Check CAM status.
*/
static int dvb_ca_en50221_check_camstatus(struct dvb_ca_private *ca, int slot)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int slot_status;
int cam_present_now;
int cam_changed;
/* IRQ mode */
if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)
return (atomic_read(&sl->camchange_count) != 0);
/* poll mode */
slot_status = ca->pub->poll_slot_status(ca->pub, slot, ca->open);
cam_present_now = (slot_status & DVB_CA_EN50221_POLL_CAM_PRESENT) ? 1 : 0;
cam_changed = (slot_status & DVB_CA_EN50221_POLL_CAM_CHANGED) ? 1 : 0;
if (!cam_changed) {
int cam_present_old = (sl->slot_state != DVB_CA_SLOTSTATE_NONE);
cam_changed = (cam_present_now != cam_present_old);
}
if (cam_changed) {
if (!cam_present_now)
sl->camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED;
else
sl->camchange_type = DVB_CA_EN50221_CAMCHANGE_INSERTED;
atomic_set(&sl->camchange_count, 1);
} else {
if ((sl->slot_state == DVB_CA_SLOTSTATE_WAITREADY) &&
(slot_status & DVB_CA_EN50221_POLL_CAM_READY)) {
/* move to validate state if reset is completed */
sl->slot_state = DVB_CA_SLOTSTATE_VALIDATE;
}
}
return cam_changed;
}
/**
* dvb_ca_en50221_wait_if_status - Wait for flags to become set on the STATUS
* register on a CAM interface, checking for errors and timeout.
*
* @ca: CA instance.
* @slot: Slot on interface.
* @waitfor: Flags to wait for.
* @timeout_hz: Timeout in milliseconds.
*
* return: 0 on success, nonzero on error.
*/
static int dvb_ca_en50221_wait_if_status(struct dvb_ca_private *ca, int slot,
u8 waitfor, int timeout_hz)
{
unsigned long timeout;
unsigned long start;
dprintk("%s\n", __func__);
/* loop until timeout elapsed */
start = jiffies;
timeout = jiffies + timeout_hz;
while (1) {
int res;
/* read the status and check for error */
res = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (res < 0)
return -EIO;
/* if we got the flags, it was successful! */
if (res & waitfor) {
dprintk("%s succeeded timeout:%lu\n",
__func__, jiffies - start);
return 0;
}
/* check for timeout */
if (time_after(jiffies, timeout))
break;
/* wait for a bit */
usleep_range(1000, 1100);
}
dprintk("%s failed timeout:%lu\n", __func__, jiffies - start);
/* if we get here, we've timed out */
return -ETIMEDOUT;
}
/**
* dvb_ca_en50221_link_init - Initialise the link layer connection to a CAM.
*
* @ca: CA instance.
* @slot: Slot id.
*
* return: 0 on success, nonzero on failure.
*/
static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int ret;
int buf_size;
u8 buf[2];
dprintk("%s\n", __func__);
/* we'll be determining these during this function */
sl->da_irq_supported = 0;
/*
* set the host link buffer size temporarily. it will be overwritten
* with the real negotiated size later.
*/
sl->link_buf_size = 2;
/* read the buffer size from the CAM */
ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND,
IRQEN | CMDREG_SR);
if (ret)
return ret;
ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_DA, HZ);
if (ret)
return ret;
ret = dvb_ca_en50221_read_data(ca, slot, buf, 2);
if (ret != 2)
return -EIO;
ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN);
if (ret)
return ret;
/*
* store it, and choose the minimum of our buffer and the CAM's buffer
* size
*/
buf_size = (buf[0] << 8) | buf[1];
if (buf_size > HOST_LINK_BUF_SIZE)
buf_size = HOST_LINK_BUF_SIZE;
sl->link_buf_size = buf_size;
buf[0] = buf_size >> 8;
buf[1] = buf_size & 0xff;
dprintk("Chosen link buffer size of %i\n", buf_size);
/* write the buffer size to the CAM */
ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND,
IRQEN | CMDREG_SW);
if (ret)
return ret;
ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10);
if (ret)
return ret;
ret = dvb_ca_en50221_write_data(ca, slot, buf, 2, CMDREG_SW);
if (ret != 2)
return -EIO;
ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN);
if (ret)
return ret;
/* success */
return 0;
}
/**
* dvb_ca_en50221_read_tuple - Read a tuple from attribute memory.
*
* @ca: CA instance.
* @slot: Slot id.
* @address: Address to read from. Updated.
* @tuple_type: Tuple id byte. Updated.
* @tuple_length: Tuple length. Updated.
* @tuple: Dest buffer for tuple (must be 256 bytes). Updated.
*
* return: 0 on success, nonzero on error.
*/
static int dvb_ca_en50221_read_tuple(struct dvb_ca_private *ca, int slot,
int *address, int *tuple_type,
int *tuple_length, u8 *tuple)
{
int i;
int _tuple_type;
int _tuple_length;
int _address = *address;
/* grab the next tuple length and type */
_tuple_type = ca->pub->read_attribute_mem(ca->pub, slot, _address);
if (_tuple_type < 0)
return _tuple_type;
if (_tuple_type == 0xff) {
dprintk("END OF CHAIN TUPLE type:0x%x\n", _tuple_type);
*address += 2;
*tuple_type = _tuple_type;
*tuple_length = 0;
return 0;
}
_tuple_length = ca->pub->read_attribute_mem(ca->pub, slot,
_address + 2);
if (_tuple_length < 0)
return _tuple_length;
_address += 4;
dprintk("TUPLE type:0x%x length:%i\n", _tuple_type, _tuple_length);
/* read in the whole tuple */
for (i = 0; i < _tuple_length; i++) {
tuple[i] = ca->pub->read_attribute_mem(ca->pub, slot,
_address + (i * 2));
dprintk(" 0x%02x: 0x%02x %c\n",
i, tuple[i] & 0xff,
((tuple[i] > 31) && (tuple[i] < 127)) ? tuple[i] : '.');
}
_address += (_tuple_length * 2);
/* success */
*tuple_type = _tuple_type;
*tuple_length = _tuple_length;
*address = _address;
return 0;
}
/**
* dvb_ca_en50221_parse_attributes - Parse attribute memory of a CAM module,
* extracting Config register, and checking it is a DVB CAM module.
*
* @ca: CA instance.
* @slot: Slot id.
*
* return: 0 on success, <0 on failure.
*/
static int dvb_ca_en50221_parse_attributes(struct dvb_ca_private *ca, int slot)
{
struct dvb_ca_slot *sl;
int address = 0;
int tuple_length;
int tuple_type;
u8 tuple[257];
char *dvb_str;
int rasz;
int status;
int got_cftableentry = 0;
int end_chain = 0;
int i;
u16 manfid = 0;
u16 devid = 0;
/* CISTPL_DEVICE_0A */
status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tuple_type,
&tuple_length, tuple);
if (status < 0)
return status;
if (tuple_type != 0x1D)
return -EINVAL;
/* CISTPL_DEVICE_0C */
status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tuple_type,
&tuple_length, tuple);
if (status < 0)
return status;
if (tuple_type != 0x1C)
return -EINVAL;
/* CISTPL_VERS_1 */
status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tuple_type,
&tuple_length, tuple);
if (status < 0)
return status;
if (tuple_type != 0x15)
return -EINVAL;
/* CISTPL_MANFID */
status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tuple_type,
&tuple_length, tuple);
if (status < 0)
return status;
if (tuple_type != 0x20)
return -EINVAL;
if (tuple_length != 4)
return -EINVAL;
manfid = (tuple[1] << 8) | tuple[0];
devid = (tuple[3] << 8) | tuple[2];
/* CISTPL_CONFIG */
status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tuple_type,
&tuple_length, tuple);
if (status < 0)
return status;
if (tuple_type != 0x1A)
return -EINVAL;
if (tuple_length < 3)
return -EINVAL;
/* extract the configbase */
rasz = tuple[0] & 3;
if (tuple_length < (3 + rasz + 14))
return -EINVAL;
sl = &ca->slot_info[slot];
sl->config_base = 0;
for (i = 0; i < rasz + 1; i++)
sl->config_base |= (tuple[2 + i] << (8 * i));
/* check it contains the correct DVB string */
dvb_str = findstr((char *)tuple, tuple_length, "DVB_CI_V", 8);
if (!dvb_str)
return -EINVAL;
if (tuple_length < ((dvb_str - (char *)tuple) + 12))
return -EINVAL;
/* is it a version we support? */
if (strncmp(dvb_str + 8, "1.00", 4)) {
pr_err("dvb_ca adapter %d: Unsupported DVB CAM module version %c%c%c%c\n",
ca->dvbdev->adapter->num, dvb_str[8], dvb_str[9],
dvb_str[10], dvb_str[11]);
return -EINVAL;
}
/* process the CFTABLE_ENTRY tuples, and any after those */
while ((!end_chain) && (address < 0x1000)) {
status = dvb_ca_en50221_read_tuple(ca, slot, &address,
&tuple_type, &tuple_length,
tuple);
if (status < 0)
return status;
switch (tuple_type) {
case 0x1B: /* CISTPL_CFTABLE_ENTRY */
if (tuple_length < (2 + 11 + 17))
break;
/* if we've already parsed one, just use it */
if (got_cftableentry)
break;
/* get the config option */
sl->config_option = tuple[0] & 0x3f;
/* OK, check it contains the correct strings */
if (!findstr((char *)tuple, tuple_length,
"DVB_HOST", 8) ||
!findstr((char *)tuple, tuple_length,
"DVB_CI_MODULE", 13))
break;
got_cftableentry = 1;
break;
case 0x14: /* CISTPL_NO_LINK */
break;
case 0xFF: /* CISTPL_END */
end_chain = 1;
break;
default: /* Unknown tuple type - just skip this tuple */
dprintk("dvb_ca: Skipping unknown tuple type:0x%x length:0x%x\n",
tuple_type, tuple_length);
break;
}
}
if ((address > 0x1000) || (!got_cftableentry))
return -EINVAL;
dprintk("Valid DVB CAM detected MANID:%x DEVID:%x CONFIGBASE:0x%x CONFIGOPTION:0x%x\n",
manfid, devid, sl->config_base, sl->config_option);
/* success! */
return 0;
}
/**
* dvb_ca_en50221_set_configoption - Set CAM's configoption correctly.
*
* @ca: CA instance.
* @slot: Slot containing the CAM.
*/
static int dvb_ca_en50221_set_configoption(struct dvb_ca_private *ca, int slot)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int configoption;
dprintk("%s\n", __func__);
/* set the config option */
ca->pub->write_attribute_mem(ca->pub, slot, sl->config_base,
sl->config_option);
/* check it */
configoption = ca->pub->read_attribute_mem(ca->pub, slot,
sl->config_base);
dprintk("Set configoption 0x%x, read configoption 0x%x\n",
sl->config_option, configoption & 0x3f);
/* fine! */
return 0;
}
/**
* dvb_ca_en50221_read_data - This function talks to an EN50221 CAM control
* interface. It reads a buffer of data from the CAM. The data can either
* be stored in a supplied buffer, or automatically be added to the slot's
* rx_buffer.
*
* @ca: CA instance.
* @slot: Slot to read from.
* @ebuf: If non-NULL, the data will be written to this buffer. If NULL,
* the data will be added into the buffering system as a normal
* fragment.
* @ecount: Size of ebuf. Ignored if ebuf is NULL.
*
* return: Number of bytes read, or < 0 on error
*/
static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot,
u8 *ebuf, int ecount)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int bytes_read;
int status;
u8 buf[HOST_LINK_BUF_SIZE];
int i;
dprintk("%s\n", __func__);
/* check if we have space for a link buf in the rx_buffer */
if (!ebuf) {
int buf_free;
if (!sl->rx_buffer.data) {
status = -EIO;
goto exit;
}
buf_free = dvb_ringbuffer_free(&sl->rx_buffer);
if (buf_free < (sl->link_buf_size +
DVB_RINGBUFFER_PKTHDRSIZE)) {
status = -EAGAIN;
goto exit;
}
}
if (ca->pub->read_data &&
(sl->slot_state != DVB_CA_SLOTSTATE_LINKINIT)) {
if (!ebuf)
status = ca->pub->read_data(ca->pub, slot, buf,
sizeof(buf));
else
status = ca->pub->read_data(ca->pub, slot, buf, ecount);
if (status < 0)
return status;
bytes_read = status;
if (status == 0)
goto exit;
} else {
/* check if there is data available */
status = ca->pub->read_cam_control(ca->pub, slot,
CTRLIF_STATUS);
if (status < 0)
goto exit;
if (!(status & STATUSREG_DA)) {
/* no data */
status = 0;
goto exit;
}
/* read the amount of data */
status = ca->pub->read_cam_control(ca->pub, slot,
CTRLIF_SIZE_HIGH);
if (status < 0)
goto exit;
bytes_read = status << 8;
status = ca->pub->read_cam_control(ca->pub, slot,
CTRLIF_SIZE_LOW);
if (status < 0)
goto exit;
bytes_read |= status;
/* check it will fit */
if (!ebuf) {
if (bytes_read > sl->link_buf_size) {
pr_err("dvb_ca adapter %d: CAM tried to send a buffer larger than the link buffer size (%i > %i)!\n",
ca->dvbdev->adapter->num, bytes_read,
sl->link_buf_size);
sl->slot_state = DVB_CA_SLOTSTATE_LINKINIT;
status = -EIO;
goto exit;
}
if (bytes_read < 2) {
pr_err("dvb_ca adapter %d: CAM sent a buffer that was less than 2 bytes!\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_LINKINIT;
status = -EIO;
goto exit;
}
} else {
if (bytes_read > ecount) {
pr_err("dvb_ca adapter %d: CAM tried to send a buffer larger than the ecount size!\n",
ca->dvbdev->adapter->num);
status = -EIO;
goto exit;
}
}
/* fill the buffer */
for (i = 0; i < bytes_read; i++) {
/* read byte and check */
status = ca->pub->read_cam_control(ca->pub, slot,
CTRLIF_DATA);
if (status < 0)
goto exit;
/* OK, store it in the buffer */
buf[i] = status;
}
/* check for read error (RE should now be 0) */
status = ca->pub->read_cam_control(ca->pub, slot,
CTRLIF_STATUS);
if (status < 0)
goto exit;
if (status & STATUSREG_RE) {
sl->slot_state = DVB_CA_SLOTSTATE_LINKINIT;
status = -EIO;
goto exit;
}
}
/*
* OK, add it to the receive buffer, or copy into external buffer if
* supplied
*/
if (!ebuf) {
if (!sl->rx_buffer.data) {
status = -EIO;
goto exit;
}
dvb_ringbuffer_pkt_write(&sl->rx_buffer, buf, bytes_read);
} else {
memcpy(ebuf, buf, bytes_read);
}
dprintk("Received CA packet for slot %i connection id 0x%x last_frag:%i size:0x%x\n", slot,
buf[0], (buf[1] & 0x80) == 0, bytes_read);
/* wake up readers when a last_fragment is received */
if ((buf[1] & 0x80) == 0x00)
wake_up_interruptible(&ca->wait_queue);
status = bytes_read;
exit:
return status;
}
/**
* dvb_ca_en50221_write_data - This function talks to an EN50221 CAM control
* interface. It writes a buffer of data to a CAM.
*
* @ca: CA instance.
* @slot: Slot to write to.
* @buf: The data in this buffer is treated as a complete link-level packet to
* be written.
* @bytes_write: Size of ebuf.
* @size_write_flag: A flag on Command Register which says whether the link size
* information will be writen or not.
*
* return: Number of bytes written, or < 0 on error.
*/
static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot,
u8 *buf, int bytes_write, int size_write_flag)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int status;
int i;
dprintk("%s\n", __func__);
/* sanity check */
if (bytes_write > sl->link_buf_size)
return -EINVAL;
if (ca->pub->write_data &&
(sl->slot_state != DVB_CA_SLOTSTATE_LINKINIT))
return ca->pub->write_data(ca->pub, slot, buf, bytes_write);
/*
* it is possible we are dealing with a single buffer implementation,
* thus if there is data available for read or if there is even a read
* already in progress, we do nothing but awake the kernel thread to
* process the data if necessary.
*/
status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (status < 0)
goto exitnowrite;
if (status & (STATUSREG_DA | STATUSREG_RE)) {
if (status & STATUSREG_DA)
dvb_ca_en50221_thread_wakeup(ca);
status = -EAGAIN;
goto exitnowrite;
}
/* OK, set HC bit */
status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND,
IRQEN | CMDREG_HC | size_write_flag);
if (status)
goto exit;
/* check if interface is still free */
status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (status < 0)
goto exit;
if (!(status & STATUSREG_FR)) {
/* it wasn't free => try again later */
status = -EAGAIN;
goto exit;
}
/*
* It may need some time for the CAM to settle down, or there might
* be a race condition between the CAM, writing HC and our last
* check for DA. This happens, if the CAM asserts DA, just after
* checking DA before we are setting HC. In this case it might be
* a bug in the CAM to keep the FR bit, the lower layer/HW
* communication requires a longer timeout or the CAM needs more
* time internally. But this happens in reality!
* We need to read the status from the HW again and do the same
* we did for the previous check for DA
*/
status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (status < 0)
goto exit;
if (status & (STATUSREG_DA | STATUSREG_RE)) {
if (status & STATUSREG_DA)
dvb_ca_en50221_thread_wakeup(ca);
status = -EAGAIN;
goto exit;
}
/* send the amount of data */
status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH,
bytes_write >> 8);
if (status)
goto exit;
status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW,
bytes_write & 0xff);
if (status)
goto exit;
/* send the buffer */
for (i = 0; i < bytes_write; i++) {
status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_DATA,
buf[i]);
if (status)
goto exit;
}
/* check for write error (WE should now be 0) */
status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (status < 0)
goto exit;
if (status & STATUSREG_WE) {
sl->slot_state = DVB_CA_SLOTSTATE_LINKINIT;
status = -EIO;
goto exit;
}
status = bytes_write;
dprintk("Wrote CA packet for slot %i, connection id 0x%x last_frag:%i size:0x%x\n", slot,
buf[0], (buf[1] & 0x80) == 0, bytes_write);
exit:
ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN);
exitnowrite:
return status;
}
/* ************************************************************************** */
/* EN50221 higher level functions */
/**
* dvb_ca_en50221_slot_shutdown - A CAM has been removed => shut it down.
*
* @ca: CA instance.
* @slot: Slot to shut down.
*/
static int dvb_ca_en50221_slot_shutdown(struct dvb_ca_private *ca, int slot)
{
dprintk("%s\n", __func__);
ca->pub->slot_shutdown(ca->pub, slot);
ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE;
/*
* need to wake up all processes to check if they're now trying to
* write to a defunct CAM
*/
wake_up_interruptible(&ca->wait_queue);
dprintk("Slot %i shutdown\n", slot);
/* success */
return 0;
}
/**
* dvb_ca_en50221_camchange_irq - A CAMCHANGE IRQ has occurred.
*
* @pubca: CA instance.
* @slot: Slot concerned.
* @change_type: One of the DVB_CA_CAMCHANGE_* values.
*/
void dvb_ca_en50221_camchange_irq(struct dvb_ca_en50221 *pubca, int slot,
int change_type)
{
struct dvb_ca_private *ca = pubca->private;
struct dvb_ca_slot *sl = &ca->slot_info[slot];
dprintk("CAMCHANGE IRQ slot:%i change_type:%i\n", slot, change_type);
switch (change_type) {
case DVB_CA_EN50221_CAMCHANGE_REMOVED:
case DVB_CA_EN50221_CAMCHANGE_INSERTED:
break;
default:
return;
}
sl->camchange_type = change_type;
atomic_inc(&sl->camchange_count);
dvb_ca_en50221_thread_wakeup(ca);
}
EXPORT_SYMBOL(dvb_ca_en50221_camchange_irq);
/**
* dvb_ca_en50221_camready_irq - A CAMREADY IRQ has occurred.
*
* @pubca: CA instance.
* @slot: Slot concerned.
*/
void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221 *pubca, int slot)
{
struct dvb_ca_private *ca = pubca->private;
struct dvb_ca_slot *sl = &ca->slot_info[slot];
dprintk("CAMREADY IRQ slot:%i\n", slot);
if (sl->slot_state == DVB_CA_SLOTSTATE_WAITREADY) {
sl->slot_state = DVB_CA_SLOTSTATE_VALIDATE;
dvb_ca_en50221_thread_wakeup(ca);
}
}
EXPORT_SYMBOL(dvb_ca_en50221_camready_irq);
/**
* dvb_ca_en50221_frda_irq - An FR or DA IRQ has occurred.
*
* @pubca: CA instance.
* @slot: Slot concerned.
*/
void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221 *pubca, int slot)
{
struct dvb_ca_private *ca = pubca->private;
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int flags;
dprintk("FR/DA IRQ slot:%i\n", slot);
switch (sl->slot_state) {
case DVB_CA_SLOTSTATE_LINKINIT:
flags = ca->pub->read_cam_control(pubca, slot, CTRLIF_STATUS);
if (flags & STATUSREG_DA) {
dprintk("CAM supports DA IRQ\n");
sl->da_irq_supported = 1;
}
break;
case DVB_CA_SLOTSTATE_RUNNING:
if (ca->open)
dvb_ca_en50221_thread_wakeup(ca);
break;
}
}
EXPORT_SYMBOL(dvb_ca_en50221_frda_irq);
/* ************************************************************************** */
/* EN50221 thread functions */
/**
* dvb_ca_en50221_thread_wakeup - Wake up the DVB CA thread
*
* @ca: CA instance.
*/
static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca)
{
dprintk("%s\n", __func__);
ca->wakeup = 1;
mb();
wake_up_process(ca->thread);
}
/**
* dvb_ca_en50221_thread_update_delay - Update the delay used by the thread.
*
* @ca: CA instance.
*/
static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca)
{
int delay;
int curdelay = 100000000;
int slot;
/*
* Beware of too high polling frequency, because one polling
* call might take several hundred milliseconds until timeout!
*/
for (slot = 0; slot < ca->slot_count; slot++) {
struct dvb_ca_slot *sl = &ca->slot_info[slot];
switch (sl->slot_state) {
default:
case DVB_CA_SLOTSTATE_NONE:
delay = HZ * 60; /* 60s */
if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
delay = HZ * 5; /* 5s */
break;
case DVB_CA_SLOTSTATE_INVALID:
delay = HZ * 60; /* 60s */
if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
delay = HZ / 10; /* 100ms */
break;
case DVB_CA_SLOTSTATE_UNINITIALISED:
case DVB_CA_SLOTSTATE_WAITREADY:
case DVB_CA_SLOTSTATE_VALIDATE:
case DVB_CA_SLOTSTATE_WAITFR:
case DVB_CA_SLOTSTATE_LINKINIT:
delay = HZ / 10; /* 100ms */
break;
case DVB_CA_SLOTSTATE_RUNNING:
delay = HZ * 60; /* 60s */
if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
delay = HZ / 10; /* 100ms */
if (ca->open) {
if ((!sl->da_irq_supported) ||
(!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA)))
delay = HZ / 10; /* 100ms */
}
break;
}
if (delay < curdelay)
curdelay = delay;
}
ca->delay = curdelay;
}
/**
* dvb_ca_en50221_poll_cam_gone - Poll if the CAM is gone.
*
* @ca: CA instance.
* @slot: Slot to process.
* return:: 0 .. no change
* 1 .. CAM state changed
*/
static int dvb_ca_en50221_poll_cam_gone(struct dvb_ca_private *ca, int slot)
{
int changed = 0;
int status;
/*
* we need this extra check for annoying interfaces like the
* budget-av
*/
if ((!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) &&
(ca->pub->poll_slot_status)) {
status = ca->pub->poll_slot_status(ca->pub, slot, 0);
if (!(status &
DVB_CA_EN50221_POLL_CAM_PRESENT)) {
ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE;
dvb_ca_en50221_thread_update_delay(ca);
changed = 1;
}
}
return changed;
}
/**
* dvb_ca_en50221_thread_state_machine - Thread state machine for one CA slot
* to perform the data transfer.
*
* @ca: CA instance.
* @slot: Slot to process.
*/
static void dvb_ca_en50221_thread_state_machine(struct dvb_ca_private *ca,
int slot)
{
struct dvb_ca_slot *sl = &ca->slot_info[slot];
int flags;
int pktcount;
void *rxbuf;
mutex_lock(&sl->slot_lock);
/* check the cam status + deal with CAMCHANGEs */
while (dvb_ca_en50221_check_camstatus(ca, slot)) {
/* clear down an old CI slot if necessary */
if (sl->slot_state != DVB_CA_SLOTSTATE_NONE)
dvb_ca_en50221_slot_shutdown(ca, slot);
/* if a CAM is NOW present, initialise it */
if (sl->camchange_type == DVB_CA_EN50221_CAMCHANGE_INSERTED)
sl->slot_state = DVB_CA_SLOTSTATE_UNINITIALISED;
/* we've handled one CAMCHANGE */
dvb_ca_en50221_thread_update_delay(ca);
atomic_dec(&sl->camchange_count);
}
/* CAM state machine */
switch (sl->slot_state) {
case DVB_CA_SLOTSTATE_NONE:
case DVB_CA_SLOTSTATE_INVALID:
/* no action needed */
break;
case DVB_CA_SLOTSTATE_UNINITIALISED:
sl->slot_state = DVB_CA_SLOTSTATE_WAITREADY;
ca->pub->slot_reset(ca->pub, slot);
sl->timeout = jiffies + (INIT_TIMEOUT_SECS * HZ);
break;
case DVB_CA_SLOTSTATE_WAITREADY:
if (time_after(jiffies, sl->timeout)) {
pr_err("dvb_ca adaptor %d: PC card did not respond :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
/*
* no other action needed; will automatically change state when
* ready
*/
break;
case DVB_CA_SLOTSTATE_VALIDATE:
if (dvb_ca_en50221_parse_attributes(ca, slot) != 0) {
if (dvb_ca_en50221_poll_cam_gone(ca, slot))
break;
pr_err("dvb_ca adapter %d: Invalid PC card inserted :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
if (dvb_ca_en50221_set_configoption(ca, slot) != 0) {
pr_err("dvb_ca adapter %d: Unable to initialise CAM :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
if (ca->pub->write_cam_control(ca->pub, slot,
CTRLIF_COMMAND,
CMDREG_RS) != 0) {
pr_err("dvb_ca adapter %d: Unable to reset CAM IF\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
dprintk("DVB CAM validated successfully\n");
sl->timeout = jiffies + (INIT_TIMEOUT_SECS * HZ);
sl->slot_state = DVB_CA_SLOTSTATE_WAITFR;
ca->wakeup = 1;
break;
case DVB_CA_SLOTSTATE_WAITFR:
if (time_after(jiffies, sl->timeout)) {
pr_err("dvb_ca adapter %d: DVB CAM did not respond :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
flags = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS);
if (flags & STATUSREG_FR) {
sl->slot_state = DVB_CA_SLOTSTATE_LINKINIT;
ca->wakeup = 1;
}
break;
case DVB_CA_SLOTSTATE_LINKINIT:
if (dvb_ca_en50221_link_init(ca, slot) != 0) {
if (dvb_ca_en50221_poll_cam_gone(ca, slot))
break;
pr_err("dvb_ca adapter %d: DVB CAM link initialisation failed :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_UNINITIALISED;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
if (!sl->rx_buffer.data) {
rxbuf = vmalloc(RX_BUFFER_SIZE);
if (!rxbuf) {
pr_err("dvb_ca adapter %d: Unable to allocate CAM rx buffer :(\n",
ca->dvbdev->adapter->num);
sl->slot_state = DVB_CA_SLOTSTATE_INVALID;
dvb_ca_en50221_thread_update_delay(ca);
break;
}
dvb_ringbuffer_init(&sl->rx_buffer, rxbuf,
RX_BUFFER_SIZE);
}
ca->pub->slot_ts_enable(ca->pub, slot);
sl->slot_state = DVB_CA_SLOTSTATE_RUNNING;
dvb_ca_en50221_thread_update_delay(ca);
pr_info("dvb_ca adapter %d: DVB CAM detected and initialised successfully\n",
ca->dvbdev->adapter->num);
break;
case DVB_CA_SLOTSTATE_RUNNING:
if (!ca->open)
break;
/* poll slots for data */
pktcount = 0;
while (dvb_ca_en50221_read_data(ca, slot, NULL, 0) > 0) {
if (!ca->open)
break;
/*
* if a CAMCHANGE occurred at some point, do not do any
* more processing of this slot
*/
if (dvb_ca_en50221_check_camstatus(ca, slot)) {
/*
* we don't want to sleep on the next iteration
* so we can handle the cam change
*/
ca->wakeup = 1;
break;
}
/* check if we've hit our limit this time */
if (++pktcount >= MAX_RX_PACKETS_PER_ITERATION) {
/*
* don't sleep; there is likely to be more data
* to read
*/
ca->wakeup = 1;
break;
}
}
break;
}
mutex_unlock(&sl->slot_lock);
}
/*
* Kernel thread which monitors CA slots for CAM changes, and performs data
* transfers.
*/
static int dvb_ca_en50221_thread(void *data)
{
struct dvb_ca_private *ca = data;
int slot;
dprintk("%s\n", __func__);
/* choose the correct initial delay */
dvb_ca_en50221_thread_update_delay(ca);
/* main loop */
while (!kthread_should_stop()) {
/* sleep for a bit */
if (!ca->wakeup) {
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(ca->delay);
if (kthread_should_stop())
return 0;
}
ca->wakeup = 0;
/* go through all the slots processing them */
for (slot = 0; slot < ca->slot_count; slot++)
dvb_ca_en50221_thread_state_machine(ca, slot);
}
return 0;
}
/* ************************************************************************** */
/* EN50221 IO interface functions */
/**
* dvb_ca_en50221_io_do_ioctl - Real ioctl implementation.
*
* @file: File concerned.
* @cmd: IOCTL command.
* @parg: Associated argument.
*
* NOTE: CA_SEND_MSG/CA_GET_MSG ioctls have userspace buffers passed to them.
*
* return: 0 on success, <0 on error.
*/
static int dvb_ca_en50221_io_do_ioctl(struct file *file,
unsigned int cmd, void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
int err = 0;
int slot;
dprintk("%s\n", __func__);
if (mutex_lock_interruptible(&ca->ioctl_mutex))
return -ERESTARTSYS;
switch (cmd) {
case CA_RESET:
for (slot = 0; slot < ca->slot_count; slot++) {
struct dvb_ca_slot *sl = &ca->slot_info[slot];
mutex_lock(&sl->slot_lock);
if (sl->slot_state != DVB_CA_SLOTSTATE_NONE) {
dvb_ca_en50221_slot_shutdown(ca, slot);
if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)
dvb_ca_en50221_camchange_irq(ca->pub,
slot,
DVB_CA_EN50221_CAMCHANGE_INSERTED);
}
mutex_unlock(&sl->slot_lock);
}
ca->next_read_slot = 0;
dvb_ca_en50221_thread_wakeup(ca);
break;
case CA_GET_CAP: {
struct ca_caps *caps = parg;
caps->slot_num = ca->slot_count;
caps->slot_type = CA_CI_LINK;
caps->descr_num = 0;
caps->descr_type = 0;
break;
}
case CA_GET_SLOT_INFO: {
struct ca_slot_info *info = parg;
struct dvb_ca_slot *sl;
slot = info->num;
if ((slot >= ca->slot_count) || (slot < 0)) {
err = -EINVAL;
goto out_unlock;
}
slot = array_index_nospec(slot, ca->slot_count);
info->type = CA_CI_LINK;
info->flags = 0;
sl = &ca->slot_info[slot];
if ((sl->slot_state != DVB_CA_SLOTSTATE_NONE) &&
(sl->slot_state != DVB_CA_SLOTSTATE_INVALID)) {
info->flags = CA_CI_MODULE_PRESENT;
}
if (sl->slot_state == DVB_CA_SLOTSTATE_RUNNING)
info->flags |= CA_CI_MODULE_READY;
break;
}
default:
err = -EINVAL;
break;
}
out_unlock:
mutex_unlock(&ca->ioctl_mutex);
return err;
}
/**
* dvb_ca_en50221_io_ioctl - Wrapper for ioctl implementation.
*
* @file: File concerned.
* @cmd: IOCTL command.
* @arg: Associated argument.
*
* return: 0 on success, <0 on error.
*/
static long dvb_ca_en50221_io_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
return dvb_usercopy(file, cmd, arg, dvb_ca_en50221_io_do_ioctl);
}
/**
* dvb_ca_en50221_io_write - Implementation of write() syscall.
*
* @file: File structure.
* @buf: Source buffer.
* @count: Size of source buffer.
* @ppos: Position in file (ignored).
*
* return: Number of bytes read, or <0 on error.
*/
static ssize_t dvb_ca_en50221_io_write(struct file *file,
const char __user *buf, size_t count,
loff_t *ppos)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
struct dvb_ca_slot *sl;
u8 slot, connection_id;
int status;
u8 fragbuf[HOST_LINK_BUF_SIZE];
int fragpos = 0;
int fraglen;
unsigned long timeout;
int written;
dprintk("%s\n", __func__);
/*
* Incoming packet has a 2 byte header.
* hdr[0] = slot_id, hdr[1] = connection_id
*/
if (count < 2)
return -EINVAL;
/* extract slot & connection id */
if (copy_from_user(&slot, buf, 1))
return -EFAULT;
if (copy_from_user(&connection_id, buf + 1, 1))
return -EFAULT;
buf += 2;
count -= 2;
if (slot >= ca->slot_count)
return -EINVAL;
slot = array_index_nospec(slot, ca->slot_count);
sl = &ca->slot_info[slot];
/* check if the slot is actually running */
if (sl->slot_state != DVB_CA_SLOTSTATE_RUNNING)
return -EINVAL;
/* fragment the packets & store in the buffer */
while (fragpos < count) {
fraglen = sl->link_buf_size - 2;
if (fraglen < 0)
break;
if (fraglen > HOST_LINK_BUF_SIZE - 2)
fraglen = HOST_LINK_BUF_SIZE - 2;
if ((count - fragpos) < fraglen)
fraglen = count - fragpos;
fragbuf[0] = connection_id;
fragbuf[1] = ((fragpos + fraglen) < count) ? 0x80 : 0x00;
status = copy_from_user(fragbuf + 2, buf + fragpos, fraglen);
if (status) {
status = -EFAULT;
goto exit;
}
timeout = jiffies + HZ / 2;
written = 0;
while (!time_after(jiffies, timeout)) {
/*
* check the CAM hasn't been removed/reset in the
* meantime
*/
if (sl->slot_state != DVB_CA_SLOTSTATE_RUNNING) {
status = -EIO;
goto exit;
}
mutex_lock(&sl->slot_lock);
status = dvb_ca_en50221_write_data(ca, slot, fragbuf,
fraglen + 2, 0);
mutex_unlock(&sl->slot_lock);
if (status == (fraglen + 2)) {
written = 1;
break;
}
if (status != -EAGAIN)
goto exit;
usleep_range(1000, 1100);
}
if (!written) {
status = -EIO;
goto exit;
}
fragpos += fraglen;
}
status = count + 2;
exit:
return status;
}
/*
* Condition for waking up in dvb_ca_en50221_io_read_condition
*/
static int dvb_ca_en50221_io_read_condition(struct dvb_ca_private *ca,
int *result, int *_slot)
{
int slot;
int slot_count = 0;
int idx;
size_t fraglen;
int connection_id = -1;
int found = 0;
u8 hdr[2];
slot = ca->next_read_slot;
while ((slot_count < ca->slot_count) && (!found)) {
struct dvb_ca_slot *sl = &ca->slot_info[slot];
if (sl->slot_state != DVB_CA_SLOTSTATE_RUNNING)
goto nextslot;
if (!sl->rx_buffer.data)
return 0;
idx = dvb_ringbuffer_pkt_next(&sl->rx_buffer, -1, &fraglen);
while (idx != -1) {
dvb_ringbuffer_pkt_read(&sl->rx_buffer, idx, 0, hdr, 2);
if (connection_id == -1)
connection_id = hdr[0];
if ((hdr[0] == connection_id) &&
((hdr[1] & 0x80) == 0)) {
*_slot = slot;
found = 1;
break;
}
idx = dvb_ringbuffer_pkt_next(&sl->rx_buffer, idx,
&fraglen);
}
nextslot:
slot = (slot + 1) % ca->slot_count;
slot_count++;
}
ca->next_read_slot = slot;
return found;
}
/**
* dvb_ca_en50221_io_read - Implementation of read() syscall.
*
* @file: File structure.
* @buf: Destination buffer.
* @count: Size of destination buffer.
* @ppos: Position in file (ignored).
*
* return: Number of bytes read, or <0 on error.
*/
static ssize_t dvb_ca_en50221_io_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
struct dvb_ca_slot *sl;
int status;
int result = 0;
u8 hdr[2];
int slot;
int connection_id = -1;
size_t idx, idx2;
int last_fragment = 0;
size_t fraglen;
int pktlen;
int dispose = 0;
dprintk("%s\n", __func__);
/*
* Outgoing packet has a 2 byte header.
* hdr[0] = slot_id, hdr[1] = connection_id
*/
if (count < 2)
return -EINVAL;
/* wait for some data */
status = dvb_ca_en50221_io_read_condition(ca, &result, &slot);
if (status == 0) {
/* if we're in nonblocking mode, exit immediately */
if (file->f_flags & O_NONBLOCK)
return -EWOULDBLOCK;
/* wait for some data */
status = wait_event_interruptible(ca->wait_queue,
dvb_ca_en50221_io_read_condition
(ca, &result, &slot));
}
if ((status < 0) || (result < 0)) {
if (result)
return result;
return status;
}
sl = &ca->slot_info[slot];
idx = dvb_ringbuffer_pkt_next(&sl->rx_buffer, -1, &fraglen);
pktlen = 2;
do {
if (idx == -1) {
pr_err("dvb_ca adapter %d: BUG: read packet ended before last_fragment encountered\n",
ca->dvbdev->adapter->num);
status = -EIO;
goto exit;
}
dvb_ringbuffer_pkt_read(&sl->rx_buffer, idx, 0, hdr, 2);
if (connection_id == -1)
connection_id = hdr[0];
if (hdr[0] == connection_id) {
if (pktlen < count) {
if ((pktlen + fraglen - 2) > count)
fraglen = count - pktlen;
else
fraglen -= 2;
status =
dvb_ringbuffer_pkt_read_user(&sl->rx_buffer,
idx, 2,
buf + pktlen,
fraglen);
if (status < 0)
goto exit;
pktlen += fraglen;
}
if ((hdr[1] & 0x80) == 0)
last_fragment = 1;
dispose = 1;
}
idx2 = dvb_ringbuffer_pkt_next(&sl->rx_buffer, idx, &fraglen);
if (dispose)
dvb_ringbuffer_pkt_dispose(&sl->rx_buffer, idx);
idx = idx2;
dispose = 0;
} while (!last_fragment);
hdr[0] = slot;
hdr[1] = connection_id;
status = copy_to_user(buf, hdr, 2);
if (status) {
status = -EFAULT;
goto exit;
}
status = pktlen;
exit:
return status;
}
/**
* dvb_ca_en50221_io_open - Implementation of file open syscall.
*
* @inode: Inode concerned.
* @file: File concerned.
*
* return: 0 on success, <0 on failure.
*/
static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
int err;
int i;
dprintk("%s\n", __func__);
mutex_lock(&ca->remove_mutex);
if (ca->exit) {
mutex_unlock(&ca->remove_mutex);
return -ENODEV;
}
if (!try_module_get(ca->pub->owner)) {
mutex_unlock(&ca->remove_mutex);
return -EIO;
}
err = dvb_generic_open(inode, file);
if (err < 0) {
module_put(ca->pub->owner);
mutex_unlock(&ca->remove_mutex);
return err;
}
for (i = 0; i < ca->slot_count; i++) {
struct dvb_ca_slot *sl = &ca->slot_info[i];
if (sl->slot_state == DVB_CA_SLOTSTATE_RUNNING) {
if (!sl->rx_buffer.data) {
/*
* it is safe to call this here without locks
* because ca->open == 0. Data is not read in
* this case
*/
dvb_ringbuffer_flush(&sl->rx_buffer);
}
}
}
ca->open = 1;
dvb_ca_en50221_thread_update_delay(ca);
dvb_ca_en50221_thread_wakeup(ca);
dvb_ca_private_get(ca);
mutex_unlock(&ca->remove_mutex);
return 0;
}
/**
* dvb_ca_en50221_io_release - Implementation of file close syscall.
*
* @inode: Inode concerned.
* @file: File concerned.
*
* return: 0 on success, <0 on failure.
*/
static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
int err;
dprintk("%s\n", __func__);
mutex_lock(&ca->remove_mutex);
/* mark the CA device as closed */
ca->open = 0;
dvb_ca_en50221_thread_update_delay(ca);
err = dvb_generic_release(inode, file);
module_put(ca->pub->owner);
dvb_ca_private_put(ca);
if (dvbdev->users == 1 && ca->exit == 1) {
mutex_unlock(&ca->remove_mutex);
wake_up(&dvbdev->wait_queue);
} else {
mutex_unlock(&ca->remove_mutex);
}
return err;
}
/**
* dvb_ca_en50221_io_poll - Implementation of poll() syscall.
*
* @file: File concerned.
* @wait: poll wait table.
*
* return: Standard poll mask.
*/
static __poll_t dvb_ca_en50221_io_poll(struct file *file, poll_table *wait)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_ca_private *ca = dvbdev->priv;
__poll_t mask = 0;
int slot;
int result = 0;
dprintk("%s\n", __func__);
poll_wait(file, &ca->wait_queue, wait);
if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1)
mask |= EPOLLIN;
/* if there is something, return now */
if (mask)
return mask;
if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1)
mask |= EPOLLIN;
return mask;
}
static const struct file_operations dvb_ca_fops = {
.owner = THIS_MODULE,
.read = dvb_ca_en50221_io_read,
.write = dvb_ca_en50221_io_write,
.unlocked_ioctl = dvb_ca_en50221_io_ioctl,
.open = dvb_ca_en50221_io_open,
.release = dvb_ca_en50221_io_release,
.poll = dvb_ca_en50221_io_poll,
.llseek = noop_llseek,
};
static const struct dvb_device dvbdev_ca = {
.priv = NULL,
.users = 1,
.readers = 1,
.writers = 1,
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
.name = "dvb-ca-en50221",
#endif
.fops = &dvb_ca_fops,
};
/* ************************************************************************** */
/* Initialisation/shutdown functions */
/**
* dvb_ca_en50221_init - Initialise a new DVB CA EN50221 interface device.
*
* @dvb_adapter: DVB adapter to attach the new CA device to.
* @pubca: The dvb_ca instance.
* @flags: Flags describing the CA device (DVB_CA_FLAG_*).
* @slot_count: Number of slots supported.
*
* return: 0 on success, nonzero on failure
*/
int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter,
struct dvb_ca_en50221 *pubca, int flags, int slot_count)
{
int ret;
struct dvb_ca_private *ca = NULL;
int i;
dprintk("%s\n", __func__);
if (slot_count < 1)
return -EINVAL;
/* initialise the system data */
ca = kzalloc(sizeof(*ca), GFP_KERNEL);
if (!ca) {
ret = -ENOMEM;
goto exit;
}
kref_init(&ca->refcount);
ca->pub = pubca;
ca->flags = flags;
ca->slot_count = slot_count;
ca->slot_info = kcalloc(slot_count, sizeof(struct dvb_ca_slot),
GFP_KERNEL);
if (!ca->slot_info) {
ret = -ENOMEM;
goto free_ca;
}
init_waitqueue_head(&ca->wait_queue);
ca->open = 0;
ca->wakeup = 0;
ca->next_read_slot = 0;
pubca->private = ca;
/* register the DVB device */
ret = dvb_register_device(dvb_adapter, &ca->dvbdev, &dvbdev_ca, ca,
DVB_DEVICE_CA, 0);
if (ret)
goto free_slot_info;
/* now initialise each slot */
for (i = 0; i < slot_count; i++) {
struct dvb_ca_slot *sl = &ca->slot_info[i];
memset(sl, 0, sizeof(struct dvb_ca_slot));
sl->slot_state = DVB_CA_SLOTSTATE_NONE;
atomic_set(&sl->camchange_count, 0);
sl->camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED;
mutex_init(&sl->slot_lock);
}
mutex_init(&ca->ioctl_mutex);
mutex_init(&ca->remove_mutex);
if (signal_pending(current)) {
ret = -EINTR;
goto unregister_device;
}
mb();
/* create a kthread for monitoring this CA device */
ca->thread = kthread_run(dvb_ca_en50221_thread, ca, "kdvb-ca-%i:%i",
ca->dvbdev->adapter->num, ca->dvbdev->id);
if (IS_ERR(ca->thread)) {
ret = PTR_ERR(ca->thread);
pr_err("dvb_ca_init: failed to start kernel_thread (%d)\n",
ret);
goto unregister_device;
}
return 0;
unregister_device:
dvb_unregister_device(ca->dvbdev);
free_slot_info:
kfree(ca->slot_info);
free_ca:
kfree(ca);
exit:
pubca->private = NULL;
return ret;
}
EXPORT_SYMBOL(dvb_ca_en50221_init);
/**
* dvb_ca_en50221_release - Release a DVB CA EN50221 interface device.
*
* @pubca: The associated dvb_ca instance.
*/
void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca)
{
struct dvb_ca_private *ca = pubca->private;
int i;
dprintk("%s\n", __func__);
mutex_lock(&ca->remove_mutex);
ca->exit = 1;
mutex_unlock(&ca->remove_mutex);
if (ca->dvbdev->users < 1)
wait_event(ca->dvbdev->wait_queue,
ca->dvbdev->users == 1);
/* shutdown the thread if there was one */
kthread_stop(ca->thread);
for (i = 0; i < ca->slot_count; i++)
dvb_ca_en50221_slot_shutdown(ca, i);
dvb_remove_device(ca->dvbdev);
dvb_ca_private_put(ca);
pubca->private = NULL;
}
EXPORT_SYMBOL(dvb_ca_en50221_release);
| linux-master | drivers/media/dvb-core/dvb_ca_en50221.c |
// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* dvb_demux.c - DVB kernel demux API
*
* Copyright (C) 2000-2001 Ralph Metzler <[email protected]>
* & Marcus Metzler <[email protected]>
* for convergence integrated media GmbH
*/
#define pr_fmt(fmt) "dvb_demux: " fmt
#include <linux/sched/signal.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <linux/poll.h>
#include <linux/string.h>
#include <linux/crc32.h>
#include <linux/uaccess.h>
#include <asm/div64.h>
#include <media/dvb_demux.h>
static int dvb_demux_tscheck;
module_param(dvb_demux_tscheck, int, 0644);
MODULE_PARM_DESC(dvb_demux_tscheck,
"enable transport stream continuity and TEI check");
static int dvb_demux_speedcheck;
module_param(dvb_demux_speedcheck, int, 0644);
MODULE_PARM_DESC(dvb_demux_speedcheck,
"enable transport stream speed check");
static int dvb_demux_feed_err_pkts = 1;
module_param(dvb_demux_feed_err_pkts, int, 0644);
MODULE_PARM_DESC(dvb_demux_feed_err_pkts,
"when set to 0, drop packets with the TEI bit set (1 by default)");
#define dprintk(fmt, arg...) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), __func__, ##arg)
#define dprintk_tscheck(x...) do { \
if (dvb_demux_tscheck && printk_ratelimit()) \
dprintk(x); \
} while (0)
#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
# define dprintk_sect_loss(x...) dprintk(x)
#else
# define dprintk_sect_loss(x...)
#endif
#define set_buf_flags(__feed, __flag) \
do { \
(__feed)->buffer_flags |= (__flag); \
} while (0)
/******************************************************************************
* static inlined helper functions
******************************************************************************/
static inline u16 section_length(const u8 *buf)
{
return 3 + ((buf[1] & 0x0f) << 8) + buf[2];
}
static inline u16 ts_pid(const u8 *buf)
{
return ((buf[1] & 0x1f) << 8) + buf[2];
}
static inline u8 payload(const u8 *tsp)
{
if (!(tsp[3] & 0x10)) // no payload?
return 0;
if (tsp[3] & 0x20) { // adaptation field?
if (tsp[4] > 183) // corrupted data?
return 0;
else
return 184 - 1 - tsp[4];
}
return 184;
}
static u32 dvb_dmx_crc32(struct dvb_demux_feed *f, const u8 *src, size_t len)
{
return (f->feed.sec.crc_val = crc32_be(f->feed.sec.crc_val, src, len));
}
static void dvb_dmx_memcopy(struct dvb_demux_feed *f, u8 *d, const u8 *s,
size_t len)
{
memcpy(d, s, len);
}
/******************************************************************************
* Software filter functions
******************************************************************************/
static inline int dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed,
const u8 *buf)
{
int count = payload(buf);
int p;
int ccok;
u8 cc;
if (count == 0)
return -1;
p = 188 - count;
cc = buf[3] & 0x0f;
ccok = ((feed->cc + 1) & 0x0f) == cc;
if (!ccok) {
set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("missed packet: %d instead of %d!\n",
cc, (feed->cc + 1) & 0x0f);
}
feed->cc = cc;
if (buf[1] & 0x40) // PUSI ?
feed->peslen = 0xfffa;
feed->peslen += count;
return feed->cb.ts(&buf[p], count, NULL, 0, &feed->feed.ts,
&feed->buffer_flags);
}
static int dvb_dmx_swfilter_sectionfilter(struct dvb_demux_feed *feed,
struct dvb_demux_filter *f)
{
u8 neq = 0;
int i;
for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) {
u8 xor = f->filter.filter_value[i] ^ feed->feed.sec.secbuf[i];
if (f->maskandmode[i] & xor)
return 0;
neq |= f->maskandnotmode[i] & xor;
}
if (f->doneq && !neq)
return 0;
return feed->cb.sec(feed->feed.sec.secbuf, feed->feed.sec.seclen,
NULL, 0, &f->filter, &feed->buffer_flags);
}
static inline int dvb_dmx_swfilter_section_feed(struct dvb_demux_feed *feed)
{
struct dvb_demux *demux = feed->demux;
struct dvb_demux_filter *f = feed->filter;
struct dmx_section_feed *sec = &feed->feed.sec;
int section_syntax_indicator;
if (!sec->is_filtering)
return 0;
if (!f)
return 0;
if (sec->check_crc) {
section_syntax_indicator = ((sec->secbuf[1] & 0x80) != 0);
if (section_syntax_indicator &&
demux->check_crc32(feed, sec->secbuf, sec->seclen)) {
set_buf_flags(feed, DMX_BUFFER_FLAG_HAD_CRC32_DISCARD);
return -1;
}
}
do {
if (dvb_dmx_swfilter_sectionfilter(feed, f) < 0)
return -1;
} while ((f = f->next) && sec->is_filtering);
sec->seclen = 0;
return 0;
}
static void dvb_dmx_swfilter_section_new(struct dvb_demux_feed *feed)
{
struct dmx_section_feed *sec = &feed->feed.sec;
if (sec->secbufp < sec->tsfeedp) {
int n = sec->tsfeedp - sec->secbufp;
/*
* Section padding is done with 0xff bytes entirely.
* Due to speed reasons, we won't check all of them
* but just first and last.
*/
if (sec->secbuf[0] != 0xff || sec->secbuf[n - 1] != 0xff) {
set_buf_flags(feed,
DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("section ts padding loss: %d/%d\n",
n, sec->tsfeedp);
dprintk_sect_loss("pad data: %*ph\n", n, sec->secbuf);
}
}
sec->tsfeedp = sec->secbufp = sec->seclen = 0;
sec->secbuf = sec->secbuf_base;
}
/*
* Losless Section Demux 1.4.1 by Emard
* Valsecchi Patrick:
* - middle of section A (no PUSI)
* - end of section A and start of section B
* (with PUSI pointing to the start of the second section)
*
* In this case, without feed->pusi_seen you'll receive a garbage section
* consisting of the end of section A. Basically because tsfeedp
* is incemented and the use=0 condition is not raised
* when the second packet arrives.
*
* Fix:
* when demux is started, let feed->pusi_seen = false to
* prevent initial feeding of garbage from the end of
* previous section. When you for the first time see PUSI=1
* then set feed->pusi_seen = true
*/
static int dvb_dmx_swfilter_section_copy_dump(struct dvb_demux_feed *feed,
const u8 *buf, u8 len)
{
struct dvb_demux *demux = feed->demux;
struct dmx_section_feed *sec = &feed->feed.sec;
u16 limit, seclen;
if (sec->tsfeedp >= DMX_MAX_SECFEED_SIZE)
return 0;
if (sec->tsfeedp + len > DMX_MAX_SECFEED_SIZE) {
set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("section buffer full loss: %d/%d\n",
sec->tsfeedp + len - DMX_MAX_SECFEED_SIZE,
DMX_MAX_SECFEED_SIZE);
len = DMX_MAX_SECFEED_SIZE - sec->tsfeedp;
}
if (len <= 0)
return 0;
demux->memcopy(feed, sec->secbuf_base + sec->tsfeedp, buf, len);
sec->tsfeedp += len;
/*
* Dump all the sections we can find in the data (Emard)
*/
limit = sec->tsfeedp;
if (limit > DMX_MAX_SECFEED_SIZE)
return -1; /* internal error should never happen */
/* to be sure always set secbuf */
sec->secbuf = sec->secbuf_base + sec->secbufp;
while (sec->secbufp + 2 < limit) {
seclen = section_length(sec->secbuf);
if (seclen <= 0 || seclen > DMX_MAX_SECTION_SIZE
|| seclen + sec->secbufp > limit)
return 0;
sec->seclen = seclen;
sec->crc_val = ~0;
/* dump [secbuf .. secbuf+seclen) */
if (feed->pusi_seen) {
dvb_dmx_swfilter_section_feed(feed);
} else {
set_buf_flags(feed,
DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("pusi not seen, discarding section data\n");
}
sec->secbufp += seclen; /* secbufp and secbuf moving together is */
sec->secbuf += seclen; /* redundant but saves pointer arithmetic */
}
return 0;
}
static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed,
const u8 *buf)
{
u8 p, count;
int ccok, dc_i = 0;
u8 cc;
count = payload(buf);
if (count == 0) /* count == 0 if no payload or out of range */
return -1;
p = 188 - count; /* payload start */
cc = buf[3] & 0x0f;
ccok = ((feed->cc + 1) & 0x0f) == cc;
if (buf[3] & 0x20) {
/* adaption field present, check for discontinuity_indicator */
if ((buf[4] > 0) && (buf[5] & 0x80))
dc_i = 1;
}
if (!ccok || dc_i) {
if (dc_i) {
set_buf_flags(feed,
DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR);
dprintk_sect_loss("%d frame with disconnect indicator\n",
cc);
} else {
set_buf_flags(feed,
DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("discontinuity: %d instead of %d. %d bytes lost\n",
cc, (feed->cc + 1) & 0x0f, count + 4);
}
/*
* those bytes under some circumstances will again be reported
* in the following dvb_dmx_swfilter_section_new
*/
/*
* Discontinuity detected. Reset pusi_seen to
* stop feeding of suspicious data until next PUSI=1 arrives
*
* FIXME: does it make sense if the MPEG-TS is the one
* reporting discontinuity?
*/
feed->pusi_seen = false;
dvb_dmx_swfilter_section_new(feed);
}
feed->cc = cc;
if (buf[1] & 0x40) {
/* PUSI=1 (is set), section boundary is here */
if (count > 1 && buf[p] < count) {
const u8 *before = &buf[p + 1];
u8 before_len = buf[p];
const u8 *after = &before[before_len];
u8 after_len = count - 1 - before_len;
dvb_dmx_swfilter_section_copy_dump(feed, before,
before_len);
/* before start of new section, set pusi_seen */
feed->pusi_seen = true;
dvb_dmx_swfilter_section_new(feed);
dvb_dmx_swfilter_section_copy_dump(feed, after,
after_len);
} else if (count > 0) {
set_buf_flags(feed,
DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
dprintk_sect_loss("PUSI=1 but %d bytes lost\n", count);
}
} else {
/* PUSI=0 (is not set), no section boundary */
dvb_dmx_swfilter_section_copy_dump(feed, &buf[p], count);
}
return 0;
}
static inline void dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed,
const u8 *buf)
{
switch (feed->type) {
case DMX_TYPE_TS:
if (!feed->feed.ts.is_filtering)
break;
if (feed->ts_type & TS_PACKET) {
if (feed->ts_type & TS_PAYLOAD_ONLY)
dvb_dmx_swfilter_payload(feed, buf);
else
feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts,
&feed->buffer_flags);
}
/* Used only on full-featured devices */
if (feed->ts_type & TS_DECODER)
if (feed->demux->write_to_decoder)
feed->demux->write_to_decoder(feed, buf, 188);
break;
case DMX_TYPE_SEC:
if (!feed->feed.sec.is_filtering)
break;
if (dvb_dmx_swfilter_section_packet(feed, buf) < 0)
feed->feed.sec.seclen = feed->feed.sec.secbufp = 0;
break;
default:
break;
}
}
#define DVR_FEED(f) \
(((f)->type == DMX_TYPE_TS) && \
((f)->feed.ts.is_filtering) && \
(((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET))
static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
{
struct dvb_demux_feed *feed;
u16 pid = ts_pid(buf);
int dvr_done = 0;
if (dvb_demux_speedcheck) {
ktime_t cur_time;
u64 speed_bytes, speed_timedelta;
demux->speed_pkts_cnt++;
/* show speed every SPEED_PKTS_INTERVAL packets */
if (!(demux->speed_pkts_cnt % SPEED_PKTS_INTERVAL)) {
cur_time = ktime_get();
if (ktime_to_ns(demux->speed_last_time) != 0) {
speed_bytes = (u64)demux->speed_pkts_cnt
* 188 * 8;
/* convert to 1024 basis */
speed_bytes = 1000 * div64_u64(speed_bytes,
1024);
speed_timedelta = ktime_ms_delta(cur_time,
demux->speed_last_time);
if (speed_timedelta)
dprintk("TS speed %llu Kbits/sec \n",
div64_u64(speed_bytes,
speed_timedelta));
}
demux->speed_last_time = cur_time;
demux->speed_pkts_cnt = 0;
}
}
if (buf[1] & 0x80) {
list_for_each_entry(feed, &demux->feed_list, list_head) {
if ((feed->pid != pid) && (feed->pid != 0x2000))
continue;
set_buf_flags(feed, DMX_BUFFER_FLAG_TEI);
}
dprintk_tscheck("TEI detected. PID=0x%x data1=0x%x\n",
pid, buf[1]);
/* data in this packet can't be trusted - drop it unless
* module option dvb_demux_feed_err_pkts is set */
if (!dvb_demux_feed_err_pkts)
return;
} else /* if TEI bit is set, pid may be wrong- skip pkt counter */
if (demux->cnt_storage && dvb_demux_tscheck) {
/* check pkt counter */
if (pid < MAX_PID) {
if (buf[3] & 0x10)
demux->cnt_storage[pid] =
(demux->cnt_storage[pid] + 1) & 0xf;
if ((buf[3] & 0xf) != demux->cnt_storage[pid]) {
list_for_each_entry(feed, &demux->feed_list, list_head) {
if ((feed->pid != pid) && (feed->pid != 0x2000))
continue;
set_buf_flags(feed,
DMX_BUFFER_PKT_COUNTER_MISMATCH);
}
dprintk_tscheck("TS packet counter mismatch. PID=0x%x expected 0x%x got 0x%x\n",
pid, demux->cnt_storage[pid],
buf[3] & 0xf);
demux->cnt_storage[pid] = buf[3] & 0xf;
}
}
/* end check */
}
list_for_each_entry(feed, &demux->feed_list, list_head) {
if ((feed->pid != pid) && (feed->pid != 0x2000))
continue;
/* copy each packet only once to the dvr device, even
* if a PID is in multiple filters (e.g. video + PCR) */
if ((DVR_FEED(feed)) && (dvr_done++))
continue;
if (feed->pid == pid)
dvb_dmx_swfilter_packet_type(feed, buf);
else if (feed->pid == 0x2000)
feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts,
&feed->buffer_flags);
}
}
void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf,
size_t count)
{
unsigned long flags;
spin_lock_irqsave(&demux->lock, flags);
while (count--) {
if (buf[0] == 0x47)
dvb_dmx_swfilter_packet(demux, buf);
buf += 188;
}
spin_unlock_irqrestore(&demux->lock, flags);
}
EXPORT_SYMBOL(dvb_dmx_swfilter_packets);
static inline int find_next_packet(const u8 *buf, int pos, size_t count,
const int pktsize)
{
int start = pos, lost;
while (pos < count) {
if (buf[pos] == 0x47 ||
(pktsize == 204 && buf[pos] == 0xB8))
break;
pos++;
}
lost = pos - start;
if (lost) {
/* This garbage is part of a valid packet? */
int backtrack = pos - pktsize;
if (backtrack >= 0 && (buf[backtrack] == 0x47 ||
(pktsize == 204 && buf[backtrack] == 0xB8)))
return backtrack;
}
return pos;
}
/* Filter all pktsize= 188 or 204 sized packets and skip garbage. */
static inline void _dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf,
size_t count, const int pktsize)
{
int p = 0, i, j;
const u8 *q;
unsigned long flags;
spin_lock_irqsave(&demux->lock, flags);
if (demux->tsbufp) { /* tsbuf[0] is now 0x47. */
i = demux->tsbufp;
j = pktsize - i;
if (count < j) {
memcpy(&demux->tsbuf[i], buf, count);
demux->tsbufp += count;
goto bailout;
}
memcpy(&demux->tsbuf[i], buf, j);
if (demux->tsbuf[0] == 0x47) /* double check */
dvb_dmx_swfilter_packet(demux, demux->tsbuf);
demux->tsbufp = 0;
p += j;
}
while (1) {
p = find_next_packet(buf, p, count, pktsize);
if (p >= count)
break;
if (count - p < pktsize)
break;
q = &buf[p];
if (pktsize == 204 && (*q == 0xB8)) {
memcpy(demux->tsbuf, q, 188);
demux->tsbuf[0] = 0x47;
q = demux->tsbuf;
}
dvb_dmx_swfilter_packet(demux, q);
p += pktsize;
}
i = count - p;
if (i) {
memcpy(demux->tsbuf, &buf[p], i);
demux->tsbufp = i;
if (pktsize == 204 && demux->tsbuf[0] == 0xB8)
demux->tsbuf[0] = 0x47;
}
bailout:
spin_unlock_irqrestore(&demux->lock, flags);
}
void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count)
{
_dvb_dmx_swfilter(demux, buf, count, 188);
}
EXPORT_SYMBOL(dvb_dmx_swfilter);
void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count)
{
_dvb_dmx_swfilter(demux, buf, count, 204);
}
EXPORT_SYMBOL(dvb_dmx_swfilter_204);
void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, size_t count)
{
unsigned long flags;
spin_lock_irqsave(&demux->lock, flags);
demux->feed->cb.ts(buf, count, NULL, 0, &demux->feed->feed.ts,
&demux->feed->buffer_flags);
spin_unlock_irqrestore(&demux->lock, flags);
}
EXPORT_SYMBOL(dvb_dmx_swfilter_raw);
static struct dvb_demux_filter *dvb_dmx_filter_alloc(struct dvb_demux *demux)
{
int i;
for (i = 0; i < demux->filternum; i++)
if (demux->filter[i].state == DMX_STATE_FREE)
break;
if (i == demux->filternum)
return NULL;
demux->filter[i].state = DMX_STATE_ALLOCATED;
return &demux->filter[i];
}
static struct dvb_demux_feed *dvb_dmx_feed_alloc(struct dvb_demux *demux)
{
int i;
for (i = 0; i < demux->feednum; i++)
if (demux->feed[i].state == DMX_STATE_FREE)
break;
if (i == demux->feednum)
return NULL;
demux->feed[i].state = DMX_STATE_ALLOCATED;
return &demux->feed[i];
}
static int dvb_demux_feed_find(struct dvb_demux_feed *feed)
{
struct dvb_demux_feed *entry;
list_for_each_entry(entry, &feed->demux->feed_list, list_head)
if (entry == feed)
return 1;
return 0;
}
static void dvb_demux_feed_add(struct dvb_demux_feed *feed)
{
spin_lock_irq(&feed->demux->lock);
if (dvb_demux_feed_find(feed)) {
pr_err("%s: feed already in list (type=%x state=%x pid=%x)\n",
__func__, feed->type, feed->state, feed->pid);
goto out;
}
list_add(&feed->list_head, &feed->demux->feed_list);
out:
spin_unlock_irq(&feed->demux->lock);
}
static void dvb_demux_feed_del(struct dvb_demux_feed *feed)
{
spin_lock_irq(&feed->demux->lock);
if (!(dvb_demux_feed_find(feed))) {
pr_err("%s: feed not in list (type=%x state=%x pid=%x)\n",
__func__, feed->type, feed->state, feed->pid);
goto out;
}
list_del(&feed->list_head);
out:
spin_unlock_irq(&feed->demux->lock);
}
static int dmx_ts_feed_set(struct dmx_ts_feed *ts_feed, u16 pid, int ts_type,
enum dmx_ts_pes pes_type, ktime_t timeout)
{
struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed;
struct dvb_demux *demux = feed->demux;
if (pid > DMX_MAX_PID)
return -EINVAL;
if (mutex_lock_interruptible(&demux->mutex))
return -ERESTARTSYS;
if (ts_type & TS_DECODER) {
if (pes_type >= DMX_PES_OTHER) {
mutex_unlock(&demux->mutex);
return -EINVAL;
}
if (demux->pesfilter[pes_type] &&
demux->pesfilter[pes_type] != feed) {
mutex_unlock(&demux->mutex);
return -EINVAL;
}
demux->pesfilter[pes_type] = feed;
demux->pids[pes_type] = pid;
}
dvb_demux_feed_add(feed);
feed->pid = pid;
feed->timeout = timeout;
feed->ts_type = ts_type;
feed->pes_type = pes_type;
feed->state = DMX_STATE_READY;
mutex_unlock(&demux->mutex);
return 0;
}
static int dmx_ts_feed_start_filtering(struct dmx_ts_feed *ts_feed)
{
struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed;
struct dvb_demux *demux = feed->demux;
int ret;
if (mutex_lock_interruptible(&demux->mutex))
return -ERESTARTSYS;
if (feed->state != DMX_STATE_READY || feed->type != DMX_TYPE_TS) {
mutex_unlock(&demux->mutex);
return -EINVAL;
}
if (!demux->start_feed) {
mutex_unlock(&demux->mutex);
return -ENODEV;
}
if ((ret = demux->start_feed(feed)) < 0) {
mutex_unlock(&demux->mutex);
return ret;
}
spin_lock_irq(&demux->lock);
ts_feed->is_filtering = 1;
feed->state = DMX_STATE_GO;
spin_unlock_irq(&demux->lock);
mutex_unlock(&demux->mutex);
return 0;
}
static int dmx_ts_feed_stop_filtering(struct dmx_ts_feed *ts_feed)
{
struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed;
struct dvb_demux *demux = feed->demux;
int ret;
mutex_lock(&demux->mutex);
if (feed->state < DMX_STATE_GO) {
mutex_unlock(&demux->mutex);
return -EINVAL;
}
if (!demux->stop_feed) {
mutex_unlock(&demux->mutex);
return -ENODEV;
}
ret = demux->stop_feed(feed);
spin_lock_irq(&demux->lock);
ts_feed->is_filtering = 0;
feed->state = DMX_STATE_ALLOCATED;
spin_unlock_irq(&demux->lock);
mutex_unlock(&demux->mutex);
return ret;
}
static int dvbdmx_allocate_ts_feed(struct dmx_demux *dmx,
struct dmx_ts_feed **ts_feed,
dmx_ts_cb callback)
{
struct dvb_demux *demux = (struct dvb_demux *)dmx;
struct dvb_demux_feed *feed;
if (mutex_lock_interruptible(&demux->mutex))
return -ERESTARTSYS;
if (!(feed = dvb_dmx_feed_alloc(demux))) {
mutex_unlock(&demux->mutex);
return -EBUSY;
}
feed->type = DMX_TYPE_TS;
feed->cb.ts = callback;
feed->demux = demux;
feed->pid = 0xffff;
feed->peslen = 0xfffa;
feed->buffer_flags = 0;
(*ts_feed) = &feed->feed.ts;
(*ts_feed)->parent = dmx;
(*ts_feed)->priv = NULL;
(*ts_feed)->is_filtering = 0;
(*ts_feed)->start_filtering = dmx_ts_feed_start_filtering;
(*ts_feed)->stop_filtering = dmx_ts_feed_stop_filtering;
(*ts_feed)->set = dmx_ts_feed_set;
if (!(feed->filter = dvb_dmx_filter_alloc(demux))) {
feed->state = DMX_STATE_FREE;
mutex_unlock(&demux->mutex);
return -EBUSY;
}
feed->filter->type = DMX_TYPE_TS;
feed->filter->feed = feed;
feed->filter->state = DMX_STATE_READY;
mutex_unlock(&demux->mutex);
return 0;
}
static int dvbdmx_release_ts_feed(struct dmx_demux *dmx,
struct dmx_ts_feed *ts_feed)
{
struct dvb_demux *demux = (struct dvb_demux *)dmx;
struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed;
mutex_lock(&demux->mutex);
if (feed->state == DMX_STATE_FREE) {
mutex_unlock(&demux->mutex);
return -EINVAL;
}
feed->state = DMX_STATE_FREE;
feed->filter->state = DMX_STATE_FREE;
dvb_demux_feed_del(feed);
feed->pid = 0xffff;
if (feed->ts_type & TS_DECODER && feed->pes_type < DMX_PES_OTHER)
demux->pesfilter[feed->pes_type] = NULL;
mutex_unlock(&demux->mutex);
return 0;
}
/******************************************************************************
* dmx_section_feed API calls
******************************************************************************/
static int dmx_section_feed_allocate_filter(struct dmx_section_feed *feed,
struct dmx_section_filter **filter)
{
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdemux = dvbdmxfeed->demux;
struct dvb_demux_filter *dvbdmxfilter;
if (mutex_lock_interruptible(&dvbdemux->mutex))
return -ERESTARTSYS;
dvbdmxfilter = dvb_dmx_filter_alloc(dvbdemux);
if (!dvbdmxfilter) {
mutex_unlock(&dvbdemux->mutex);
return -EBUSY;
}
spin_lock_irq(&dvbdemux->lock);
*filter = &dvbdmxfilter->filter;
(*filter)->parent = feed;
(*filter)->priv = NULL;
dvbdmxfilter->feed = dvbdmxfeed;
dvbdmxfilter->type = DMX_TYPE_SEC;
dvbdmxfilter->state = DMX_STATE_READY;
dvbdmxfilter->next = dvbdmxfeed->filter;
dvbdmxfeed->filter = dvbdmxfilter;
spin_unlock_irq(&dvbdemux->lock);
mutex_unlock(&dvbdemux->mutex);
return 0;
}
static int dmx_section_feed_set(struct dmx_section_feed *feed,
u16 pid, int check_crc)
{
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
if (pid > 0x1fff)
return -EINVAL;
if (mutex_lock_interruptible(&dvbdmx->mutex))
return -ERESTARTSYS;
dvb_demux_feed_add(dvbdmxfeed);
dvbdmxfeed->pid = pid;
dvbdmxfeed->feed.sec.check_crc = check_crc;
dvbdmxfeed->state = DMX_STATE_READY;
mutex_unlock(&dvbdmx->mutex);
return 0;
}
static void prepare_secfilters(struct dvb_demux_feed *dvbdmxfeed)
{
int i;
struct dvb_demux_filter *f;
struct dmx_section_filter *sf;
u8 mask, mode, doneq;
if (!(f = dvbdmxfeed->filter))
return;
do {
sf = &f->filter;
doneq = false;
for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) {
mode = sf->filter_mode[i];
mask = sf->filter_mask[i];
f->maskandmode[i] = mask & mode;
doneq |= f->maskandnotmode[i] = mask & ~mode;
}
f->doneq = doneq ? true : false;
} while ((f = f->next));
}
static int dmx_section_feed_start_filtering(struct dmx_section_feed *feed)
{
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
int ret;
if (mutex_lock_interruptible(&dvbdmx->mutex))
return -ERESTARTSYS;
if (feed->is_filtering) {
mutex_unlock(&dvbdmx->mutex);
return -EBUSY;
}
if (!dvbdmxfeed->filter) {
mutex_unlock(&dvbdmx->mutex);
return -EINVAL;
}
dvbdmxfeed->feed.sec.tsfeedp = 0;
dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base;
dvbdmxfeed->feed.sec.secbufp = 0;
dvbdmxfeed->feed.sec.seclen = 0;
dvbdmxfeed->pusi_seen = false;
if (!dvbdmx->start_feed) {
mutex_unlock(&dvbdmx->mutex);
return -ENODEV;
}
prepare_secfilters(dvbdmxfeed);
if ((ret = dvbdmx->start_feed(dvbdmxfeed)) < 0) {
mutex_unlock(&dvbdmx->mutex);
return ret;
}
spin_lock_irq(&dvbdmx->lock);
feed->is_filtering = 1;
dvbdmxfeed->state = DMX_STATE_GO;
spin_unlock_irq(&dvbdmx->lock);
mutex_unlock(&dvbdmx->mutex);
return 0;
}
static int dmx_section_feed_stop_filtering(struct dmx_section_feed *feed)
{
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
int ret;
mutex_lock(&dvbdmx->mutex);
if (!dvbdmx->stop_feed) {
mutex_unlock(&dvbdmx->mutex);
return -ENODEV;
}
ret = dvbdmx->stop_feed(dvbdmxfeed);
spin_lock_irq(&dvbdmx->lock);
dvbdmxfeed->state = DMX_STATE_READY;
feed->is_filtering = 0;
spin_unlock_irq(&dvbdmx->lock);
mutex_unlock(&dvbdmx->mutex);
return ret;
}
static int dmx_section_feed_release_filter(struct dmx_section_feed *feed,
struct dmx_section_filter *filter)
{
struct dvb_demux_filter *dvbdmxfilter = (struct dvb_demux_filter *)filter, *f;
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
mutex_lock(&dvbdmx->mutex);
if (dvbdmxfilter->feed != dvbdmxfeed) {
mutex_unlock(&dvbdmx->mutex);
return -EINVAL;
}
if (feed->is_filtering) {
/* release dvbdmx->mutex as far as it is
acquired by stop_filtering() itself */
mutex_unlock(&dvbdmx->mutex);
feed->stop_filtering(feed);
mutex_lock(&dvbdmx->mutex);
}
spin_lock_irq(&dvbdmx->lock);
f = dvbdmxfeed->filter;
if (f == dvbdmxfilter) {
dvbdmxfeed->filter = dvbdmxfilter->next;
} else {
while (f->next != dvbdmxfilter)
f = f->next;
f->next = f->next->next;
}
dvbdmxfilter->state = DMX_STATE_FREE;
spin_unlock_irq(&dvbdmx->lock);
mutex_unlock(&dvbdmx->mutex);
return 0;
}
static int dvbdmx_allocate_section_feed(struct dmx_demux *demux,
struct dmx_section_feed **feed,
dmx_section_cb callback)
{
struct dvb_demux *dvbdmx = (struct dvb_demux *)demux;
struct dvb_demux_feed *dvbdmxfeed;
if (mutex_lock_interruptible(&dvbdmx->mutex))
return -ERESTARTSYS;
if (!(dvbdmxfeed = dvb_dmx_feed_alloc(dvbdmx))) {
mutex_unlock(&dvbdmx->mutex);
return -EBUSY;
}
dvbdmxfeed->type = DMX_TYPE_SEC;
dvbdmxfeed->cb.sec = callback;
dvbdmxfeed->demux = dvbdmx;
dvbdmxfeed->pid = 0xffff;
dvbdmxfeed->buffer_flags = 0;
dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base;
dvbdmxfeed->feed.sec.secbufp = dvbdmxfeed->feed.sec.seclen = 0;
dvbdmxfeed->feed.sec.tsfeedp = 0;
dvbdmxfeed->filter = NULL;
(*feed) = &dvbdmxfeed->feed.sec;
(*feed)->is_filtering = 0;
(*feed)->parent = demux;
(*feed)->priv = NULL;
(*feed)->set = dmx_section_feed_set;
(*feed)->allocate_filter = dmx_section_feed_allocate_filter;
(*feed)->start_filtering = dmx_section_feed_start_filtering;
(*feed)->stop_filtering = dmx_section_feed_stop_filtering;
(*feed)->release_filter = dmx_section_feed_release_filter;
mutex_unlock(&dvbdmx->mutex);
return 0;
}
static int dvbdmx_release_section_feed(struct dmx_demux *demux,
struct dmx_section_feed *feed)
{
struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed;
struct dvb_demux *dvbdmx = (struct dvb_demux *)demux;
mutex_lock(&dvbdmx->mutex);
if (dvbdmxfeed->state == DMX_STATE_FREE) {
mutex_unlock(&dvbdmx->mutex);
return -EINVAL;
}
dvbdmxfeed->state = DMX_STATE_FREE;
dvb_demux_feed_del(dvbdmxfeed);
dvbdmxfeed->pid = 0xffff;
mutex_unlock(&dvbdmx->mutex);
return 0;
}
/******************************************************************************
* dvb_demux kernel data API calls
******************************************************************************/
static int dvbdmx_open(struct dmx_demux *demux)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
if (dvbdemux->users >= MAX_DVB_DEMUX_USERS)
return -EUSERS;
dvbdemux->users++;
return 0;
}
static int dvbdmx_close(struct dmx_demux *demux)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
if (dvbdemux->users == 0)
return -ENODEV;
dvbdemux->users--;
//FIXME: release any unneeded resources if users==0
return 0;
}
static int dvbdmx_write(struct dmx_demux *demux, const char __user *buf, size_t count)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
void *p;
if ((!demux->frontend) || (demux->frontend->source != DMX_MEMORY_FE))
return -EINVAL;
p = memdup_user(buf, count);
if (IS_ERR(p))
return PTR_ERR(p);
if (mutex_lock_interruptible(&dvbdemux->mutex)) {
kfree(p);
return -ERESTARTSYS;
}
dvb_dmx_swfilter(dvbdemux, p, count);
kfree(p);
mutex_unlock(&dvbdemux->mutex);
if (signal_pending(current))
return -EINTR;
return count;
}
static int dvbdmx_add_frontend(struct dmx_demux *demux,
struct dmx_frontend *frontend)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
struct list_head *head = &dvbdemux->frontend_list;
list_add(&(frontend->connectivity_list), head);
return 0;
}
static int dvbdmx_remove_frontend(struct dmx_demux *demux,
struct dmx_frontend *frontend)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
struct list_head *pos, *n, *head = &dvbdemux->frontend_list;
list_for_each_safe(pos, n, head) {
if (DMX_FE_ENTRY(pos) == frontend) {
list_del(pos);
return 0;
}
}
return -ENODEV;
}
static struct list_head *dvbdmx_get_frontends(struct dmx_demux *demux)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
if (list_empty(&dvbdemux->frontend_list))
return NULL;
return &dvbdemux->frontend_list;
}
static int dvbdmx_connect_frontend(struct dmx_demux *demux,
struct dmx_frontend *frontend)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
if (demux->frontend)
return -EINVAL;
mutex_lock(&dvbdemux->mutex);
demux->frontend = frontend;
mutex_unlock(&dvbdemux->mutex);
return 0;
}
static int dvbdmx_disconnect_frontend(struct dmx_demux *demux)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
mutex_lock(&dvbdemux->mutex);
demux->frontend = NULL;
mutex_unlock(&dvbdemux->mutex);
return 0;
}
static int dvbdmx_get_pes_pids(struct dmx_demux *demux, u16 * pids)
{
struct dvb_demux *dvbdemux = (struct dvb_demux *)demux;
memcpy(pids, dvbdemux->pids, 5 * sizeof(u16));
return 0;
}
int dvb_dmx_init(struct dvb_demux *dvbdemux)
{
int i;
struct dmx_demux *dmx = &dvbdemux->dmx;
dvbdemux->cnt_storage = NULL;
dvbdemux->users = 0;
dvbdemux->filter = vmalloc(array_size(sizeof(struct dvb_demux_filter),
dvbdemux->filternum));
if (!dvbdemux->filter)
return -ENOMEM;
dvbdemux->feed = vmalloc(array_size(sizeof(struct dvb_demux_feed),
dvbdemux->feednum));
if (!dvbdemux->feed) {
vfree(dvbdemux->filter);
dvbdemux->filter = NULL;
return -ENOMEM;
}
for (i = 0; i < dvbdemux->filternum; i++) {
dvbdemux->filter[i].state = DMX_STATE_FREE;
dvbdemux->filter[i].index = i;
}
for (i = 0; i < dvbdemux->feednum; i++) {
dvbdemux->feed[i].state = DMX_STATE_FREE;
dvbdemux->feed[i].index = i;
}
dvbdemux->cnt_storage = vmalloc(MAX_PID + 1);
if (!dvbdemux->cnt_storage)
pr_warn("Couldn't allocate memory for TS/TEI check. Disabling it\n");
INIT_LIST_HEAD(&dvbdemux->frontend_list);
for (i = 0; i < DMX_PES_OTHER; i++) {
dvbdemux->pesfilter[i] = NULL;
dvbdemux->pids[i] = 0xffff;
}
INIT_LIST_HEAD(&dvbdemux->feed_list);
dvbdemux->playing = 0;
dvbdemux->recording = 0;
dvbdemux->tsbufp = 0;
if (!dvbdemux->check_crc32)
dvbdemux->check_crc32 = dvb_dmx_crc32;
if (!dvbdemux->memcopy)
dvbdemux->memcopy = dvb_dmx_memcopy;
dmx->frontend = NULL;
dmx->priv = dvbdemux;
dmx->open = dvbdmx_open;
dmx->close = dvbdmx_close;
dmx->write = dvbdmx_write;
dmx->allocate_ts_feed = dvbdmx_allocate_ts_feed;
dmx->release_ts_feed = dvbdmx_release_ts_feed;
dmx->allocate_section_feed = dvbdmx_allocate_section_feed;
dmx->release_section_feed = dvbdmx_release_section_feed;
dmx->add_frontend = dvbdmx_add_frontend;
dmx->remove_frontend = dvbdmx_remove_frontend;
dmx->get_frontends = dvbdmx_get_frontends;
dmx->connect_frontend = dvbdmx_connect_frontend;
dmx->disconnect_frontend = dvbdmx_disconnect_frontend;
dmx->get_pes_pids = dvbdmx_get_pes_pids;
mutex_init(&dvbdemux->mutex);
spin_lock_init(&dvbdemux->lock);
return 0;
}
EXPORT_SYMBOL(dvb_dmx_init);
void dvb_dmx_release(struct dvb_demux *dvbdemux)
{
vfree(dvbdemux->cnt_storage);
vfree(dvbdemux->filter);
vfree(dvbdemux->feed);
}
EXPORT_SYMBOL(dvb_dmx_release);
| linux-master | drivers/media/dvb-core/dvb_demux.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dvb-vb2.c - dvb-vb2
*
* Copyright (C) 2015 Samsung Electronics
*
* Author: [email protected]
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <media/dvbdev.h>
#include <media/dvb_vb2.h>
#define DVB_V2_MAX_SIZE (4096 * 188)
static int vb2_debug;
module_param(vb2_debug, int, 0644);
#define dprintk(level, fmt, arg...) \
do { \
if (vb2_debug >= level) \
pr_info("vb2: %s: " fmt, __func__, ## arg); \
} while (0)
static int _queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vq);
ctx->buf_cnt = *nbuffers;
*nplanes = 1;
sizes[0] = ctx->buf_siz;
/*
* videobuf2-vmalloc allocator is context-less so no need to set
* alloc_ctxs array.
*/
dprintk(3, "[%s] count=%d, size=%d\n", ctx->name,
*nbuffers, sizes[0]);
return 0;
}
static int _buffer_prepare(struct vb2_buffer *vb)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
unsigned long size = ctx->buf_siz;
if (vb2_plane_size(vb, 0) < size) {
dprintk(1, "[%s] data will not fit into plane (%lu < %lu)\n",
ctx->name, vb2_plane_size(vb, 0), size);
return -EINVAL;
}
vb2_set_plane_payload(vb, 0, size);
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
static void _buffer_queue(struct vb2_buffer *vb)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct dvb_buffer *buf = container_of(vb, struct dvb_buffer, vb);
unsigned long flags = 0;
spin_lock_irqsave(&ctx->slock, flags);
list_add_tail(&buf->list, &ctx->dvb_q);
spin_unlock_irqrestore(&ctx->slock, flags);
dprintk(3, "[%s]\n", ctx->name);
}
static int _start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vq);
dprintk(3, "[%s] count=%d\n", ctx->name, count);
return 0;
}
static void _stop_streaming(struct vb2_queue *vq)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vq);
struct dvb_buffer *buf;
unsigned long flags = 0;
dprintk(3, "[%s]\n", ctx->name);
spin_lock_irqsave(&ctx->slock, flags);
while (!list_empty(&ctx->dvb_q)) {
buf = list_entry(ctx->dvb_q.next,
struct dvb_buffer, list);
vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
list_del(&buf->list);
}
spin_unlock_irqrestore(&ctx->slock, flags);
}
static void _dmxdev_lock(struct vb2_queue *vq)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vq);
mutex_lock(&ctx->mutex);
dprintk(3, "[%s]\n", ctx->name);
}
static void _dmxdev_unlock(struct vb2_queue *vq)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vq);
if (mutex_is_locked(&ctx->mutex))
mutex_unlock(&ctx->mutex);
dprintk(3, "[%s]\n", ctx->name);
}
static const struct vb2_ops dvb_vb2_qops = {
.queue_setup = _queue_setup,
.buf_prepare = _buffer_prepare,
.buf_queue = _buffer_queue,
.start_streaming = _start_streaming,
.stop_streaming = _stop_streaming,
.wait_prepare = _dmxdev_unlock,
.wait_finish = _dmxdev_lock,
};
static void _fill_dmx_buffer(struct vb2_buffer *vb, void *pb)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct dmx_buffer *b = pb;
b->index = vb->index;
b->length = vb->planes[0].length;
b->bytesused = vb->planes[0].bytesused;
b->offset = vb->planes[0].m.offset;
dprintk(3, "[%s]\n", ctx->name);
}
static int _fill_vb2_buffer(struct vb2_buffer *vb, struct vb2_plane *planes)
{
struct dvb_vb2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
planes[0].bytesused = 0;
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
static const struct vb2_buf_ops dvb_vb2_buf_ops = {
.fill_user_buffer = _fill_dmx_buffer,
.fill_vb2_buffer = _fill_vb2_buffer,
};
/*
* Videobuf operations
*/
int dvb_vb2_init(struct dvb_vb2_ctx *ctx, const char *name, int nonblocking)
{
struct vb2_queue *q = &ctx->vb_q;
int ret;
memset(ctx, 0, sizeof(struct dvb_vb2_ctx));
q->type = DVB_BUF_TYPE_CAPTURE;
/**capture type*/
q->is_output = 0;
/**only mmap is supported currently*/
q->io_modes = VB2_MMAP;
q->drv_priv = ctx;
q->buf_struct_size = sizeof(struct dvb_buffer);
q->min_buffers_needed = 1;
q->ops = &dvb_vb2_qops;
q->mem_ops = &vb2_vmalloc_memops;
q->buf_ops = &dvb_vb2_buf_ops;
q->num_buffers = 0;
ret = vb2_core_queue_init(q);
if (ret) {
ctx->state = DVB_VB2_STATE_NONE;
dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
return ret;
}
mutex_init(&ctx->mutex);
spin_lock_init(&ctx->slock);
INIT_LIST_HEAD(&ctx->dvb_q);
strscpy(ctx->name, name, DVB_VB2_NAME_MAX);
ctx->nonblocking = nonblocking;
ctx->state = DVB_VB2_STATE_INIT;
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
int dvb_vb2_release(struct dvb_vb2_ctx *ctx)
{
struct vb2_queue *q = (struct vb2_queue *)&ctx->vb_q;
if (ctx->state & DVB_VB2_STATE_INIT)
vb2_core_queue_release(q);
ctx->state = DVB_VB2_STATE_NONE;
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
int dvb_vb2_stream_on(struct dvb_vb2_ctx *ctx)
{
struct vb2_queue *q = &ctx->vb_q;
int ret;
ret = vb2_core_streamon(q, q->type);
if (ret) {
ctx->state = DVB_VB2_STATE_NONE;
dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
return ret;
}
ctx->state |= DVB_VB2_STATE_STREAMON;
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
int dvb_vb2_stream_off(struct dvb_vb2_ctx *ctx)
{
struct vb2_queue *q = (struct vb2_queue *)&ctx->vb_q;
int ret;
ctx->state &= ~DVB_VB2_STATE_STREAMON;
ret = vb2_core_streamoff(q, q->type);
if (ret) {
ctx->state = DVB_VB2_STATE_NONE;
dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
return ret;
}
dprintk(3, "[%s]\n", ctx->name);
return 0;
}
int dvb_vb2_is_streaming(struct dvb_vb2_ctx *ctx)
{
return (ctx->state & DVB_VB2_STATE_STREAMON);
}
int dvb_vb2_fill_buffer(struct dvb_vb2_ctx *ctx,
const unsigned char *src, int len,
enum dmx_buffer_flags *buffer_flags)
{
unsigned long flags = 0;
void *vbuf = NULL;
int todo = len;
unsigned char *psrc = (unsigned char *)src;
int ll = 0;
/*
* normal case: This func is called twice from demux driver
* one with valid src pointer, second time with NULL pointer
*/
if (!src || !len)
return 0;
spin_lock_irqsave(&ctx->slock, flags);
if (buffer_flags && *buffer_flags) {
ctx->flags |= *buffer_flags;
*buffer_flags = 0;
}
while (todo) {
if (!ctx->buf) {
if (list_empty(&ctx->dvb_q)) {
dprintk(3, "[%s] Buffer overflow!!!\n",
ctx->name);
break;
}
ctx->buf = list_entry(ctx->dvb_q.next,
struct dvb_buffer, list);
ctx->remain = vb2_plane_size(&ctx->buf->vb, 0);
ctx->offset = 0;
}
if (!dvb_vb2_is_streaming(ctx)) {
vb2_buffer_done(&ctx->buf->vb, VB2_BUF_STATE_ERROR);
list_del(&ctx->buf->list);
ctx->buf = NULL;
break;
}
/* Fill buffer */
ll = min(todo, ctx->remain);
vbuf = vb2_plane_vaddr(&ctx->buf->vb, 0);
memcpy(vbuf + ctx->offset, psrc, ll);
todo -= ll;
psrc += ll;
ctx->remain -= ll;
ctx->offset += ll;
if (ctx->remain == 0) {
vb2_buffer_done(&ctx->buf->vb, VB2_BUF_STATE_DONE);
list_del(&ctx->buf->list);
ctx->buf = NULL;
}
}
if (ctx->nonblocking && ctx->buf) {
vb2_set_plane_payload(&ctx->buf->vb, 0, ll);
vb2_buffer_done(&ctx->buf->vb, VB2_BUF_STATE_DONE);
list_del(&ctx->buf->list);
ctx->buf = NULL;
}
spin_unlock_irqrestore(&ctx->slock, flags);
if (todo)
dprintk(1, "[%s] %d bytes are dropped.\n", ctx->name, todo);
else
dprintk(3, "[%s]\n", ctx->name);
dprintk(3, "[%s] %d bytes are copied\n", ctx->name, len - todo);
return (len - todo);
}
int dvb_vb2_reqbufs(struct dvb_vb2_ctx *ctx, struct dmx_requestbuffers *req)
{
int ret;
/* Adjust size to a sane value */
if (req->size > DVB_V2_MAX_SIZE)
req->size = DVB_V2_MAX_SIZE;
/* FIXME: round req->size to a 188 or 204 multiple */
ctx->buf_siz = req->size;
ctx->buf_cnt = req->count;
ret = vb2_core_reqbufs(&ctx->vb_q, VB2_MEMORY_MMAP, 0, &req->count);
if (ret) {
ctx->state = DVB_VB2_STATE_NONE;
dprintk(1, "[%s] count=%d size=%d errno=%d\n", ctx->name,
ctx->buf_cnt, ctx->buf_siz, ret);
return ret;
}
ctx->state |= DVB_VB2_STATE_REQBUFS;
dprintk(3, "[%s] count=%d size=%d\n", ctx->name,
ctx->buf_cnt, ctx->buf_siz);
return 0;
}
int dvb_vb2_querybuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
{
struct vb2_queue *q = &ctx->vb_q;
if (b->index >= q->num_buffers) {
dprintk(1, "[%s] buffer index out of range\n", ctx->name);
return -EINVAL;
}
vb2_core_querybuf(&ctx->vb_q, b->index, b);
dprintk(3, "[%s] index=%d\n", ctx->name, b->index);
return 0;
}
int dvb_vb2_expbuf(struct dvb_vb2_ctx *ctx, struct dmx_exportbuffer *exp)
{
struct vb2_queue *q = &ctx->vb_q;
int ret;
ret = vb2_core_expbuf(&ctx->vb_q, &exp->fd, q->type, exp->index,
0, exp->flags);
if (ret) {
dprintk(1, "[%s] index=%d errno=%d\n", ctx->name,
exp->index, ret);
return ret;
}
dprintk(3, "[%s] index=%d fd=%d\n", ctx->name, exp->index, exp->fd);
return 0;
}
int dvb_vb2_qbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
{
struct vb2_queue *q = &ctx->vb_q;
int ret;
if (b->index >= q->num_buffers) {
dprintk(1, "[%s] buffer index out of range\n", ctx->name);
return -EINVAL;
}
ret = vb2_core_qbuf(&ctx->vb_q, b->index, b, NULL);
if (ret) {
dprintk(1, "[%s] index=%d errno=%d\n", ctx->name,
b->index, ret);
return ret;
}
dprintk(5, "[%s] index=%d\n", ctx->name, b->index);
return 0;
}
int dvb_vb2_dqbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
{
unsigned long flags;
int ret;
ret = vb2_core_dqbuf(&ctx->vb_q, &b->index, b, ctx->nonblocking);
if (ret) {
dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
return ret;
}
spin_lock_irqsave(&ctx->slock, flags);
b->count = ctx->count++;
b->flags = ctx->flags;
ctx->flags = 0;
spin_unlock_irqrestore(&ctx->slock, flags);
dprintk(5, "[%s] index=%d, count=%d, flags=%d\n",
ctx->name, b->index, ctx->count, b->flags);
return 0;
}
int dvb_vb2_mmap(struct dvb_vb2_ctx *ctx, struct vm_area_struct *vma)
{
int ret;
ret = vb2_mmap(&ctx->vb_q, vma);
if (ret) {
dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
return ret;
}
dprintk(3, "[%s] ret=%d\n", ctx->name, ret);
return 0;
}
__poll_t dvb_vb2_poll(struct dvb_vb2_ctx *ctx, struct file *file,
poll_table *wait)
{
dprintk(3, "[%s]\n", ctx->name);
return vb2_core_poll(&ctx->vb_q, file, wait);
}
| linux-master | drivers/media/dvb-core/dvb_vb2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* dvb_net.c
*
* Copyright (C) 2001 Convergence integrated media GmbH
* Ralph Metzler <[email protected]>
* Copyright (C) 2002 Ralph Metzler <[email protected]>
*
* ULE Decapsulation code:
* Copyright (C) 2003, 2004 gcs - Global Communication & Services GmbH.
* and Department of Scientific Computing
* Paris Lodron University of Salzburg.
* Hilmar Linder <[email protected]>
* and Wolfram Stering <[email protected]>
*
* ULE Decaps according to RFC 4326.
*/
/*
* ULE ChangeLog:
* Feb 2004: hl/ws v1: Implementing draft-fair-ipdvb-ule-01.txt
*
* Dec 2004: hl/ws v2: Implementing draft-ietf-ipdvb-ule-03.txt:
* ULE Extension header handling.
* Bugreports by Moritz Vieth and Hanno Tersteegen,
* Fraunhofer Institute for Open Communication Systems
* Competence Center for Advanced Satellite Communications.
* Bugfixes and robustness improvements.
* Filtering on dest MAC addresses, if present (D-Bit = 0)
* DVB_ULE_DEBUG compile-time option.
* Apr 2006: cp v3: Bugfixes and compliency with RFC 4326 (ULE) by
* Christian Praehauser <[email protected]>,
* Paris Lodron University of Salzburg.
*/
/*
* FIXME / TODO (dvb_net.c):
*
* Unloading does not work for 2.6.9 kernels: a refcount doesn't go to zero.
*
*/
#define pr_fmt(fmt) "dvb_net: " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/nospec.h>
#include <linux/etherdevice.h>
#include <linux/dvb/net.h>
#include <linux/uio.h>
#include <linux/uaccess.h>
#include <linux/crc32.h>
#include <linux/mutex.h>
#include <linux/sched.h>
#include <media/dvb_demux.h>
#include <media/dvb_net.h>
static inline __u32 iov_crc32( __u32 c, struct kvec *iov, unsigned int cnt )
{
unsigned int j;
for (j = 0; j < cnt; j++)
c = crc32_be( c, iov[j].iov_base, iov[j].iov_len );
return c;
}
#define DVB_NET_MULTICAST_MAX 10
#ifdef DVB_ULE_DEBUG
/*
* The code inside DVB_ULE_DEBUG keeps a history of the
* last 100 TS cells processed.
*/
static unsigned char ule_hist[100*TS_SZ] = { 0 };
static unsigned char *ule_where = ule_hist, ule_dump;
static void hexdump(const unsigned char *buf, unsigned short len)
{
print_hex_dump_debug("", DUMP_PREFIX_OFFSET, 16, 1, buf, len, true);
}
#endif
struct dvb_net_priv {
int in_use;
u16 pid;
struct net_device *net;
struct dvb_net *host;
struct dmx_demux *demux;
struct dmx_section_feed *secfeed;
struct dmx_section_filter *secfilter;
struct dmx_ts_feed *tsfeed;
int multi_num;
struct dmx_section_filter *multi_secfilter[DVB_NET_MULTICAST_MAX];
unsigned char multi_macs[DVB_NET_MULTICAST_MAX][6];
int rx_mode;
#define RX_MODE_UNI 0
#define RX_MODE_MULTI 1
#define RX_MODE_ALL_MULTI 2
#define RX_MODE_PROMISC 3
struct work_struct set_multicast_list_wq;
struct work_struct restart_net_feed_wq;
unsigned char feedtype; /* Either FEED_TYPE_ or FEED_TYPE_ULE */
int need_pusi; /* Set to 1, if synchronization on PUSI required. */
unsigned char tscc; /* TS continuity counter after sync on PUSI. */
struct sk_buff *ule_skb; /* ULE SNDU decodes into this buffer. */
unsigned char *ule_next_hdr; /* Pointer into skb to next ULE extension header. */
unsigned short ule_sndu_len; /* ULE SNDU length in bytes, w/o D-Bit. */
unsigned short ule_sndu_type; /* ULE SNDU type field, complete. */
unsigned char ule_sndu_type_1; /* ULE SNDU type field, if split across 2 TS cells. */
unsigned char ule_dbit; /* Whether the DestMAC address present
* or not (bit is set). */
unsigned char ule_bridged; /* Whether the ULE_BRIDGED extension header was found. */
int ule_sndu_remain; /* Nr. of bytes still required for current ULE SNDU. */
unsigned long ts_count; /* Current ts cell counter. */
struct mutex mutex;
};
/*
* Determine the packet's protocol ID. The rule here is that we
* assume 802.3 if the type field is short enough to be a length.
* This is normal practice and works for any 'now in use' protocol.
*
* stolen from eth.c out of the linux kernel, hacked for dvb-device
* by Michael Holzt <[email protected]>
*/
static __be16 dvb_net_eth_type_trans(struct sk_buff *skb,
struct net_device *dev)
{
struct ethhdr *eth;
unsigned char *rawp;
skb_reset_mac_header(skb);
skb_pull(skb,dev->hard_header_len);
eth = eth_hdr(skb);
if (*eth->h_dest & 1) {
if(ether_addr_equal(eth->h_dest,dev->broadcast))
skb->pkt_type=PACKET_BROADCAST;
else
skb->pkt_type=PACKET_MULTICAST;
}
if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN)
return eth->h_proto;
rawp = skb->data;
/*
* This is a magic hack to spot IPX packets. Older Novell breaks
* the protocol design and runs IPX over 802.3 without an 802.2 LLC
* layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This
* won't work for fault tolerant netware but does for the rest.
*/
if (*(unsigned short *)rawp == 0xFFFF)
return htons(ETH_P_802_3);
/*
* Real 802.2 LLC
*/
return htons(ETH_P_802_2);
}
#define TS_SZ 188
#define TS_SYNC 0x47
#define TS_TEI 0x80
#define TS_SC 0xC0
#define TS_PUSI 0x40
#define TS_AF_A 0x20
#define TS_AF_D 0x10
/* ULE Extension Header handlers. */
#define ULE_TEST 0
#define ULE_BRIDGED 1
#define ULE_OPTEXTHDR_PADDING 0
static int ule_test_sndu( struct dvb_net_priv *p )
{
return -1;
}
static int ule_bridged_sndu( struct dvb_net_priv *p )
{
struct ethhdr *hdr = (struct ethhdr*) p->ule_next_hdr;
if(ntohs(hdr->h_proto) < ETH_P_802_3_MIN) {
int framelen = p->ule_sndu_len - ((p->ule_next_hdr+sizeof(struct ethhdr)) - p->ule_skb->data);
/* A frame Type < ETH_P_802_3_MIN for a bridged frame, introduces a LLC Length field. */
if(framelen != ntohs(hdr->h_proto)) {
return -1;
}
}
/* Note:
* From RFC4326:
* "A bridged SNDU is a Mandatory Extension Header of Type 1.
* It must be the final (or only) extension header specified in the header chain of a SNDU."
* The 'ule_bridged' flag will cause the extension header processing loop to terminate.
*/
p->ule_bridged = 1;
return 0;
}
static int ule_exthdr_padding(struct dvb_net_priv *p)
{
return 0;
}
/*
* Handle ULE extension headers.
* Function is called after a successful CRC32 verification of an ULE SNDU to complete its decoding.
* Returns: >= 0: nr. of bytes consumed by next extension header
* -1: Mandatory extension header that is not recognized or TEST SNDU; discard.
*/
static int handle_one_ule_extension( struct dvb_net_priv *p )
{
/* Table of mandatory extension header handlers. The header type is the index. */
static int (*ule_mandatory_ext_handlers[255])( struct dvb_net_priv *p ) =
{ [0] = ule_test_sndu, [1] = ule_bridged_sndu, [2] = NULL, };
/* Table of optional extension header handlers. The header type is the index. */
static int (*ule_optional_ext_handlers[255])( struct dvb_net_priv *p ) =
{ [0] = ule_exthdr_padding, [1] = NULL, };
int ext_len = 0;
unsigned char hlen = (p->ule_sndu_type & 0x0700) >> 8;
unsigned char htype = p->ule_sndu_type & 0x00FF;
/* Discriminate mandatory and optional extension headers. */
if (hlen == 0) {
/* Mandatory extension header */
if (ule_mandatory_ext_handlers[htype]) {
ext_len = ule_mandatory_ext_handlers[htype]( p );
if(ext_len >= 0) {
p->ule_next_hdr += ext_len;
if (!p->ule_bridged) {
p->ule_sndu_type = ntohs(*(__be16 *)p->ule_next_hdr);
p->ule_next_hdr += 2;
} else {
p->ule_sndu_type = ntohs(*(__be16 *)(p->ule_next_hdr + ((p->ule_dbit ? 2 : 3) * ETH_ALEN)));
/* This assures the extension handling loop will terminate. */
}
}
// else: extension handler failed or SNDU should be discarded
} else
ext_len = -1; /* SNDU has to be discarded. */
} else {
/* Optional extension header. Calculate the length. */
ext_len = hlen << 1;
/* Process the optional extension header according to its type. */
if (ule_optional_ext_handlers[htype])
(void)ule_optional_ext_handlers[htype]( p );
p->ule_next_hdr += ext_len;
p->ule_sndu_type = ntohs( *(__be16 *)(p->ule_next_hdr-2) );
/*
* note: the length of the next header type is included in the
* length of THIS optional extension header
*/
}
return ext_len;
}
static int handle_ule_extensions( struct dvb_net_priv *p )
{
int total_ext_len = 0, l;
p->ule_next_hdr = p->ule_skb->data;
do {
l = handle_one_ule_extension( p );
if (l < 0)
return l; /* Stop extension header processing and discard SNDU. */
total_ext_len += l;
pr_debug("ule_next_hdr=%p, ule_sndu_type=%i, l=%i, total_ext_len=%i\n",
p->ule_next_hdr, (int)p->ule_sndu_type,
l, total_ext_len);
} while (p->ule_sndu_type < ETH_P_802_3_MIN);
return total_ext_len;
}
/* Prepare for a new ULE SNDU: reset the decoder state. */
static inline void reset_ule( struct dvb_net_priv *p )
{
p->ule_skb = NULL;
p->ule_next_hdr = NULL;
p->ule_sndu_len = 0;
p->ule_sndu_type = 0;
p->ule_sndu_type_1 = 0;
p->ule_sndu_remain = 0;
p->ule_dbit = 0xFF;
p->ule_bridged = 0;
}
/*
* Decode ULE SNDUs according to draft-ietf-ipdvb-ule-03.txt from a sequence of
* TS cells of a single PID.
*/
struct dvb_net_ule_handle {
struct net_device *dev;
struct dvb_net_priv *priv;
struct ethhdr *ethh;
const u8 *buf;
size_t buf_len;
unsigned long skipped;
const u8 *ts, *ts_end, *from_where;
u8 ts_remain, how_much, new_ts;
bool error;
};
static int dvb_net_ule_new_ts_cell(struct dvb_net_ule_handle *h)
{
/* We are about to process a new TS cell. */
#ifdef DVB_ULE_DEBUG
if (ule_where >= &ule_hist[100*TS_SZ])
ule_where = ule_hist;
memcpy(ule_where, h->ts, TS_SZ);
if (ule_dump) {
hexdump(ule_where, TS_SZ);
ule_dump = 0;
}
ule_where += TS_SZ;
#endif
/*
* Check TS h->error conditions: sync_byte, transport_error_indicator,
* scrambling_control .
*/
if ((h->ts[0] != TS_SYNC) || (h->ts[1] & TS_TEI) ||
((h->ts[3] & TS_SC) != 0)) {
pr_warn("%lu: Invalid TS cell: SYNC %#x, TEI %u, SC %#x.\n",
h->priv->ts_count, h->ts[0],
(h->ts[1] & TS_TEI) >> 7,
(h->ts[3] & TS_SC) >> 6);
/* Drop partly decoded SNDU, reset state, resync on PUSI. */
if (h->priv->ule_skb) {
dev_kfree_skb(h->priv->ule_skb);
/* Prepare for next SNDU. */
h->dev->stats.rx_errors++;
h->dev->stats.rx_frame_errors++;
}
reset_ule(h->priv);
h->priv->need_pusi = 1;
/* Continue with next TS cell. */
h->ts += TS_SZ;
h->priv->ts_count++;
return 1;
}
h->ts_remain = 184;
h->from_where = h->ts + 4;
return 0;
}
static int dvb_net_ule_ts_pusi(struct dvb_net_ule_handle *h)
{
if (h->ts[1] & TS_PUSI) {
/* Find beginning of first ULE SNDU in current TS cell. */
/* Synchronize continuity counter. */
h->priv->tscc = h->ts[3] & 0x0F;
/* There is a pointer field here. */
if (h->ts[4] > h->ts_remain) {
pr_err("%lu: Invalid ULE packet (pointer field %d)\n",
h->priv->ts_count, h->ts[4]);
h->ts += TS_SZ;
h->priv->ts_count++;
return 1;
}
/* Skip to destination of pointer field. */
h->from_where = &h->ts[5] + h->ts[4];
h->ts_remain -= 1 + h->ts[4];
h->skipped = 0;
} else {
h->skipped++;
h->ts += TS_SZ;
h->priv->ts_count++;
return 1;
}
return 0;
}
static int dvb_net_ule_new_ts(struct dvb_net_ule_handle *h)
{
/* Check continuity counter. */
if ((h->ts[3] & 0x0F) == h->priv->tscc)
h->priv->tscc = (h->priv->tscc + 1) & 0x0F;
else {
/* TS discontinuity handling: */
pr_warn("%lu: TS discontinuity: got %#x, expected %#x.\n",
h->priv->ts_count, h->ts[3] & 0x0F,
h->priv->tscc);
/* Drop partly decoded SNDU, reset state, resync on PUSI. */
if (h->priv->ule_skb) {
dev_kfree_skb(h->priv->ule_skb);
/* Prepare for next SNDU. */
// reset_ule(h->priv); moved to below.
h->dev->stats.rx_errors++;
h->dev->stats.rx_frame_errors++;
}
reset_ule(h->priv);
/* skip to next PUSI. */
h->priv->need_pusi = 1;
return 1;
}
/*
* If we still have an incomplete payload, but PUSI is
* set; some TS cells are missing.
* This is only possible here, if we missed exactly 16 TS
* cells (continuity counter wrap).
*/
if (h->ts[1] & TS_PUSI) {
if (!h->priv->need_pusi) {
if (!(*h->from_where < (h->ts_remain-1)) ||
*h->from_where != h->priv->ule_sndu_remain) {
/*
* Pointer field is invalid.
* Drop this TS cell and any started ULE SNDU.
*/
pr_warn("%lu: Invalid pointer field: %u.\n",
h->priv->ts_count,
*h->from_where);
/*
* Drop partly decoded SNDU, reset state,
* resync on PUSI.
*/
if (h->priv->ule_skb) {
h->error = true;
dev_kfree_skb(h->priv->ule_skb);
}
if (h->error || h->priv->ule_sndu_remain) {
h->dev->stats.rx_errors++;
h->dev->stats.rx_frame_errors++;
h->error = false;
}
reset_ule(h->priv);
h->priv->need_pusi = 1;
return 1;
}
/*
* Skip pointer field (we're processing a
* packed payload).
*/
h->from_where += 1;
h->ts_remain -= 1;
} else
h->priv->need_pusi = 0;
if (h->priv->ule_sndu_remain > 183) {
/*
* Current SNDU lacks more data than there
* could be available in the current TS cell.
*/
h->dev->stats.rx_errors++;
h->dev->stats.rx_length_errors++;
pr_warn("%lu: Expected %d more SNDU bytes, but got PUSI (pf %d, h->ts_remain %d). Flushing incomplete payload.\n",
h->priv->ts_count,
h->priv->ule_sndu_remain,
h->ts[4], h->ts_remain);
dev_kfree_skb(h->priv->ule_skb);
/* Prepare for next SNDU. */
reset_ule(h->priv);
/*
* Resync: go to where pointer field points to:
* start of next ULE SNDU.
*/
h->from_where += h->ts[4];
h->ts_remain -= h->ts[4];
}
}
return 0;
}
/*
* Start a new payload with skb.
* Find ULE header. It is only guaranteed that the
* length field (2 bytes) is contained in the current
* TS.
* Check h.ts_remain has to be >= 2 here.
*/
static int dvb_net_ule_new_payload(struct dvb_net_ule_handle *h)
{
if (h->ts_remain < 2) {
pr_warn("Invalid payload packing: only %d bytes left in TS. Resyncing.\n",
h->ts_remain);
h->priv->ule_sndu_len = 0;
h->priv->need_pusi = 1;
h->ts += TS_SZ;
return 1;
}
if (!h->priv->ule_sndu_len) {
/* Got at least two bytes, thus extrace the SNDU length. */
h->priv->ule_sndu_len = h->from_where[0] << 8 |
h->from_where[1];
if (h->priv->ule_sndu_len & 0x8000) {
/* D-Bit is set: no dest mac present. */
h->priv->ule_sndu_len &= 0x7FFF;
h->priv->ule_dbit = 1;
} else
h->priv->ule_dbit = 0;
if (h->priv->ule_sndu_len < 5) {
pr_warn("%lu: Invalid ULE SNDU length %u. Resyncing.\n",
h->priv->ts_count,
h->priv->ule_sndu_len);
h->dev->stats.rx_errors++;
h->dev->stats.rx_length_errors++;
h->priv->ule_sndu_len = 0;
h->priv->need_pusi = 1;
h->new_ts = 1;
h->ts += TS_SZ;
h->priv->ts_count++;
return 1;
}
h->ts_remain -= 2; /* consume the 2 bytes SNDU length. */
h->from_where += 2;
}
h->priv->ule_sndu_remain = h->priv->ule_sndu_len + 2;
/*
* State of current TS:
* h->ts_remain (remaining bytes in the current TS cell)
* 0 ule_type is not available now, we need the next TS cell
* 1 the first byte of the ule_type is present
* >=2 full ULE header present, maybe some payload data as well.
*/
switch (h->ts_remain) {
case 1:
h->priv->ule_sndu_remain--;
h->priv->ule_sndu_type = h->from_where[0] << 8;
/* first byte of ule_type is set. */
h->priv->ule_sndu_type_1 = 1;
h->ts_remain -= 1;
h->from_where += 1;
fallthrough;
case 0:
h->new_ts = 1;
h->ts += TS_SZ;
h->priv->ts_count++;
return 1;
default: /* complete ULE header is present in current TS. */
/* Extract ULE type field. */
if (h->priv->ule_sndu_type_1) {
h->priv->ule_sndu_type_1 = 0;
h->priv->ule_sndu_type |= h->from_where[0];
h->from_where += 1; /* points to payload start. */
h->ts_remain -= 1;
} else {
/* Complete type is present in new TS. */
h->priv->ule_sndu_type = h->from_where[0] << 8 |
h->from_where[1];
h->from_where += 2; /* points to payload start. */
h->ts_remain -= 2;
}
break;
}
/*
* Allocate the skb (decoder target buffer) with the correct size,
* as follows:
*
* prepare for the largest case: bridged SNDU with MAC address
* (dbit = 0).
*/
h->priv->ule_skb = dev_alloc_skb(h->priv->ule_sndu_len +
ETH_HLEN + ETH_ALEN);
if (!h->priv->ule_skb) {
pr_notice("%s: Memory squeeze, dropping packet.\n",
h->dev->name);
h->dev->stats.rx_dropped++;
return -1;
}
/* This includes the CRC32 _and_ dest mac, if !dbit. */
h->priv->ule_sndu_remain = h->priv->ule_sndu_len;
h->priv->ule_skb->dev = h->dev;
/*
* Leave space for Ethernet or bridged SNDU header
* (eth hdr plus one MAC addr).
*/
skb_reserve(h->priv->ule_skb, ETH_HLEN + ETH_ALEN);
return 0;
}
static int dvb_net_ule_should_drop(struct dvb_net_ule_handle *h)
{
static const u8 bc_addr[ETH_ALEN] = { [0 ... ETH_ALEN - 1] = 0xff };
/*
* The destination MAC address is the next data in the skb. It comes
* before any extension headers.
*
* Check if the payload of this SNDU should be passed up the stack.
*/
if (h->priv->rx_mode == RX_MODE_PROMISC)
return 0;
if (h->priv->ule_skb->data[0] & 0x01) {
/* multicast or broadcast */
if (!ether_addr_equal(h->priv->ule_skb->data, bc_addr)) {
/* multicast */
if (h->priv->rx_mode == RX_MODE_MULTI) {
int i;
for (i = 0; i < h->priv->multi_num &&
!ether_addr_equal(h->priv->ule_skb->data,
h->priv->multi_macs[i]);
i++)
;
if (i == h->priv->multi_num)
return 1;
} else if (h->priv->rx_mode != RX_MODE_ALL_MULTI)
return 1; /* no broadcast; */
/*
* else:
* all multicast mode: accept all multicast packets
*/
}
/* else: broadcast */
} else if (!ether_addr_equal(h->priv->ule_skb->data, h->dev->dev_addr))
return 1;
return 0;
}
static void dvb_net_ule_check_crc(struct dvb_net_ule_handle *h,
struct kvec iov[3],
u32 ule_crc, u32 expected_crc)
{
u8 dest_addr[ETH_ALEN];
if (ule_crc != expected_crc) {
pr_warn("%lu: CRC32 check FAILED: %08x / %08x, SNDU len %d type %#x, ts_remain %d, next 2: %x.\n",
h->priv->ts_count, ule_crc, expected_crc,
h->priv->ule_sndu_len, h->priv->ule_sndu_type,
h->ts_remain,
h->ts_remain > 2 ?
*(unsigned short *)h->from_where : 0);
#ifdef DVB_ULE_DEBUG
hexdump(iov[0].iov_base, iov[0].iov_len);
hexdump(iov[1].iov_base, iov[1].iov_len);
hexdump(iov[2].iov_base, iov[2].iov_len);
if (ule_where == ule_hist) {
hexdump(&ule_hist[98*TS_SZ], TS_SZ);
hexdump(&ule_hist[99*TS_SZ], TS_SZ);
} else if (ule_where == &ule_hist[TS_SZ]) {
hexdump(&ule_hist[99*TS_SZ], TS_SZ);
hexdump(ule_hist, TS_SZ);
} else {
hexdump(ule_where - TS_SZ - TS_SZ, TS_SZ);
hexdump(ule_where - TS_SZ, TS_SZ);
}
ule_dump = 1;
#endif
h->dev->stats.rx_errors++;
h->dev->stats.rx_crc_errors++;
dev_kfree_skb(h->priv->ule_skb);
return;
}
/* CRC32 verified OK. */
/* CRC32 was OK, so remove it from skb. */
h->priv->ule_skb->tail -= 4;
h->priv->ule_skb->len -= 4;
if (!h->priv->ule_dbit) {
if (dvb_net_ule_should_drop(h)) {
netdev_dbg(h->dev,
"Dropping SNDU: MAC destination address does not match: dest addr: %pM, h->dev addr: %pM\n",
h->priv->ule_skb->data, h->dev->dev_addr);
dev_kfree_skb(h->priv->ule_skb);
return;
}
skb_copy_from_linear_data(h->priv->ule_skb, dest_addr,
ETH_ALEN);
skb_pull(h->priv->ule_skb, ETH_ALEN);
} else {
/* dest_addr buffer is only valid if h->priv->ule_dbit == 0 */
eth_zero_addr(dest_addr);
}
/* Handle ULE Extension Headers. */
if (h->priv->ule_sndu_type < ETH_P_802_3_MIN) {
/* There is an extension header. Handle it accordingly. */
int l = handle_ule_extensions(h->priv);
if (l < 0) {
/*
* Mandatory extension header unknown or TEST SNDU.
* Drop it.
*/
// pr_warn("Dropping SNDU, extension headers.\n" );
dev_kfree_skb(h->priv->ule_skb);
return;
}
skb_pull(h->priv->ule_skb, l);
}
/*
* Construct/assure correct ethernet header.
* Note: in bridged mode (h->priv->ule_bridged != 0)
* we already have the (original) ethernet
* header at the start of the payload (after
* optional dest. address and any extension
* headers).
*/
if (!h->priv->ule_bridged) {
skb_push(h->priv->ule_skb, ETH_HLEN);
h->ethh = (struct ethhdr *)h->priv->ule_skb->data;
memcpy(h->ethh->h_dest, dest_addr, ETH_ALEN);
eth_zero_addr(h->ethh->h_source);
h->ethh->h_proto = htons(h->priv->ule_sndu_type);
}
/* else: skb is in correct state; nothing to do. */
h->priv->ule_bridged = 0;
/* Stuff into kernel's protocol stack. */
h->priv->ule_skb->protocol = dvb_net_eth_type_trans(h->priv->ule_skb,
h->dev);
/*
* If D-bit is set (i.e. destination MAC address not present),
* receive the packet anyhow.
*/
#if 0
if (h->priv->ule_dbit && skb->pkt_type == PACKET_OTHERHOST)
h->priv->ule_skb->pkt_type = PACKET_HOST;
#endif
h->dev->stats.rx_packets++;
h->dev->stats.rx_bytes += h->priv->ule_skb->len;
netif_rx(h->priv->ule_skb);
}
static void dvb_net_ule(struct net_device *dev, const u8 *buf, size_t buf_len)
{
int ret;
struct dvb_net_ule_handle h = {
.dev = dev,
.priv = netdev_priv(dev),
.ethh = NULL,
.buf = buf,
.buf_len = buf_len,
.skipped = 0L,
.ts = NULL,
.ts_end = NULL,
.from_where = NULL,
.ts_remain = 0,
.how_much = 0,
.new_ts = 1,
.error = false,
};
/*
* For all TS cells in current buffer.
* Appearently, we are called for every single TS cell.
*/
for (h.ts = h.buf, h.ts_end = h.buf + h.buf_len;
h.ts < h.ts_end; /* no incr. */) {
if (h.new_ts) {
/* We are about to process a new TS cell. */
if (dvb_net_ule_new_ts_cell(&h))
continue;
}
/* Synchronize on PUSI, if required. */
if (h.priv->need_pusi) {
if (dvb_net_ule_ts_pusi(&h))
continue;
}
if (h.new_ts) {
if (dvb_net_ule_new_ts(&h))
continue;
}
/* Check if new payload needs to be started. */
if (h.priv->ule_skb == NULL) {
ret = dvb_net_ule_new_payload(&h);
if (ret < 0)
return;
if (ret)
continue;
}
/* Copy data into our current skb. */
h.how_much = min(h.priv->ule_sndu_remain, (int)h.ts_remain);
skb_put_data(h.priv->ule_skb, h.from_where, h.how_much);
h.priv->ule_sndu_remain -= h.how_much;
h.ts_remain -= h.how_much;
h.from_where += h.how_much;
/* Check for complete payload. */
if (h.priv->ule_sndu_remain <= 0) {
/* Check CRC32, we've got it in our skb already. */
__be16 ulen = htons(h.priv->ule_sndu_len);
__be16 utype = htons(h.priv->ule_sndu_type);
const u8 *tail;
struct kvec iov[3] = {
{ &ulen, sizeof ulen },
{ &utype, sizeof utype },
{ h.priv->ule_skb->data,
h.priv->ule_skb->len - 4 }
};
u32 ule_crc = ~0L, expected_crc;
if (h.priv->ule_dbit) {
/* Set D-bit for CRC32 verification,
* if it was set originally. */
ulen |= htons(0x8000);
}
ule_crc = iov_crc32(ule_crc, iov, 3);
tail = skb_tail_pointer(h.priv->ule_skb);
expected_crc = *(tail - 4) << 24 |
*(tail - 3) << 16 |
*(tail - 2) << 8 |
*(tail - 1);
dvb_net_ule_check_crc(&h, iov, ule_crc, expected_crc);
/* Prepare for next SNDU. */
reset_ule(h.priv);
}
/* More data in current TS (look at the bytes following the CRC32)? */
if (h.ts_remain >= 2 && *((unsigned short *)h.from_where) != 0xFFFF) {
/* Next ULE SNDU starts right there. */
h.new_ts = 0;
h.priv->ule_skb = NULL;
h.priv->ule_sndu_type_1 = 0;
h.priv->ule_sndu_len = 0;
// pr_warn("More data in current TS: [%#x %#x %#x %#x]\n",
// *(h.from_where + 0), *(h.from_where + 1),
// *(h.from_where + 2), *(h.from_where + 3));
// pr_warn("h.ts @ %p, stopped @ %p:\n", h.ts, h.from_where + 0);
// hexdump(h.ts, 188);
} else {
h.new_ts = 1;
h.ts += TS_SZ;
h.priv->ts_count++;
if (h.priv->ule_skb == NULL) {
h.priv->need_pusi = 1;
h.priv->ule_sndu_type_1 = 0;
h.priv->ule_sndu_len = 0;
}
}
} /* for all available TS cells */
}
static int dvb_net_ts_callback(const u8 *buffer1, size_t buffer1_len,
const u8 *buffer2, size_t buffer2_len,
struct dmx_ts_feed *feed,
u32 *buffer_flags)
{
struct net_device *dev = feed->priv;
if (buffer2)
pr_warn("buffer2 not NULL: %p.\n", buffer2);
if (buffer1_len > 32768)
pr_warn("length > 32k: %zu.\n", buffer1_len);
/* pr_info("TS callback: %u bytes, %u TS cells @ %p.\n",
buffer1_len, buffer1_len / TS_SZ, buffer1); */
dvb_net_ule(dev, buffer1, buffer1_len);
return 0;
}
static void dvb_net_sec(struct net_device *dev,
const u8 *pkt, int pkt_len)
{
u8 *eth;
struct sk_buff *skb;
struct net_device_stats *stats = &dev->stats;
int snap = 0;
/* note: pkt_len includes a 32bit checksum */
if (pkt_len < 16) {
pr_warn("%s: IP/MPE packet length = %d too small.\n",
dev->name, pkt_len);
stats->rx_errors++;
stats->rx_length_errors++;
return;
}
/* it seems some ISPs manage to screw up here, so we have to
* relax the error checks... */
#if 0
if ((pkt[5] & 0xfd) != 0xc1) {
/* drop scrambled or broken packets */
#else
if ((pkt[5] & 0x3c) != 0x00) {
/* drop scrambled */
#endif
stats->rx_errors++;
stats->rx_crc_errors++;
return;
}
if (pkt[5] & 0x02) {
/* handle LLC/SNAP, see rfc-1042 */
if (pkt_len < 24 || memcmp(&pkt[12], "\xaa\xaa\x03\0\0\0", 6)) {
stats->rx_dropped++;
return;
}
snap = 8;
}
if (pkt[7]) {
/* FIXME: assemble datagram from multiple sections */
stats->rx_errors++;
stats->rx_frame_errors++;
return;
}
/* we have 14 byte ethernet header (ip header follows);
* 12 byte MPE header; 4 byte checksum; + 2 byte alignment, 8 byte LLC/SNAP
*/
if (!(skb = dev_alloc_skb(pkt_len - 4 - 12 + 14 + 2 - snap))) {
//pr_notice("%s: Memory squeeze, dropping packet.\n", dev->name);
stats->rx_dropped++;
return;
}
skb_reserve(skb, 2); /* longword align L3 header */
skb->dev = dev;
/* copy L3 payload */
eth = skb_put(skb, pkt_len - 12 - 4 + 14 - snap);
memcpy(eth + 14, pkt + 12 + snap, pkt_len - 12 - 4 - snap);
/* create ethernet header: */
eth[0]=pkt[0x0b];
eth[1]=pkt[0x0a];
eth[2]=pkt[0x09];
eth[3]=pkt[0x08];
eth[4]=pkt[0x04];
eth[5]=pkt[0x03];
eth[6]=eth[7]=eth[8]=eth[9]=eth[10]=eth[11]=0;
if (snap) {
eth[12] = pkt[18];
eth[13] = pkt[19];
} else {
/* protocol numbers are from rfc-1700 or
* http://www.iana.org/assignments/ethernet-numbers
*/
if (pkt[12] >> 4 == 6) { /* version field from IP header */
eth[12] = 0x86; /* IPv6 */
eth[13] = 0xdd;
} else {
eth[12] = 0x08; /* IPv4 */
eth[13] = 0x00;
}
}
skb->protocol = dvb_net_eth_type_trans(skb, dev);
stats->rx_packets++;
stats->rx_bytes+=skb->len;
netif_rx(skb);
}
static int dvb_net_sec_callback(const u8 *buffer1, size_t buffer1_len,
const u8 *buffer2, size_t buffer2_len,
struct dmx_section_filter *filter, u32 *buffer_flags)
{
struct net_device *dev = filter->priv;
/*
* we rely on the DVB API definition where exactly one complete
* section is delivered in buffer1
*/
dvb_net_sec (dev, buffer1, buffer1_len);
return 0;
}
static netdev_tx_t dvb_net_tx(struct sk_buff *skb, struct net_device *dev)
{
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
static u8 mask_normal[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
static u8 mask_allmulti[6]={0xff, 0xff, 0xff, 0x00, 0x00, 0x00};
static u8 mac_allmulti[6]={0x01, 0x00, 0x5e, 0x00, 0x00, 0x00};
static u8 mask_promisc[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
static int dvb_net_filter_sec_set(struct net_device *dev,
struct dmx_section_filter **secfilter,
const u8 *mac, u8 *mac_mask)
{
struct dvb_net_priv *priv = netdev_priv(dev);
int ret;
*secfilter=NULL;
ret = priv->secfeed->allocate_filter(priv->secfeed, secfilter);
if (ret<0) {
pr_err("%s: could not get filter\n", dev->name);
return ret;
}
(*secfilter)->priv=(void *) dev;
memset((*secfilter)->filter_value, 0x00, DMX_MAX_FILTER_SIZE);
memset((*secfilter)->filter_mask, 0x00, DMX_MAX_FILTER_SIZE);
memset((*secfilter)->filter_mode, 0xff, DMX_MAX_FILTER_SIZE);
(*secfilter)->filter_value[0]=0x3e;
(*secfilter)->filter_value[3]=mac[5];
(*secfilter)->filter_value[4]=mac[4];
(*secfilter)->filter_value[8]=mac[3];
(*secfilter)->filter_value[9]=mac[2];
(*secfilter)->filter_value[10]=mac[1];
(*secfilter)->filter_value[11]=mac[0];
(*secfilter)->filter_mask[0] = 0xff;
(*secfilter)->filter_mask[3] = mac_mask[5];
(*secfilter)->filter_mask[4] = mac_mask[4];
(*secfilter)->filter_mask[8] = mac_mask[3];
(*secfilter)->filter_mask[9] = mac_mask[2];
(*secfilter)->filter_mask[10] = mac_mask[1];
(*secfilter)->filter_mask[11]=mac_mask[0];
netdev_dbg(dev, "filter mac=%pM mask=%pM\n", mac, mac_mask);
return 0;
}
static int dvb_net_feed_start(struct net_device *dev)
{
int ret = 0, i;
struct dvb_net_priv *priv = netdev_priv(dev);
struct dmx_demux *demux = priv->demux;
const unsigned char *mac = (const unsigned char *) dev->dev_addr;
netdev_dbg(dev, "rx_mode %i\n", priv->rx_mode);
mutex_lock(&priv->mutex);
if (priv->tsfeed || priv->secfeed || priv->secfilter || priv->multi_secfilter[0])
pr_err("%s: BUG %d\n", __func__, __LINE__);
priv->secfeed=NULL;
priv->secfilter=NULL;
priv->tsfeed = NULL;
if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) {
netdev_dbg(dev, "alloc secfeed\n");
ret=demux->allocate_section_feed(demux, &priv->secfeed,
dvb_net_sec_callback);
if (ret<0) {
pr_err("%s: could not allocate section feed\n",
dev->name);
goto error;
}
ret = priv->secfeed->set(priv->secfeed, priv->pid, 1);
if (ret<0) {
pr_err("%s: could not set section feed\n", dev->name);
priv->demux->release_section_feed(priv->demux, priv->secfeed);
priv->secfeed=NULL;
goto error;
}
if (priv->rx_mode != RX_MODE_PROMISC) {
netdev_dbg(dev, "set secfilter\n");
dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_normal);
}
switch (priv->rx_mode) {
case RX_MODE_MULTI:
for (i = 0; i < priv->multi_num; i++) {
netdev_dbg(dev, "set multi_secfilter[%d]\n", i);
dvb_net_filter_sec_set(dev, &priv->multi_secfilter[i],
priv->multi_macs[i], mask_normal);
}
break;
case RX_MODE_ALL_MULTI:
priv->multi_num=1;
netdev_dbg(dev, "set multi_secfilter[0]\n");
dvb_net_filter_sec_set(dev, &priv->multi_secfilter[0],
mac_allmulti, mask_allmulti);
break;
case RX_MODE_PROMISC:
priv->multi_num=0;
netdev_dbg(dev, "set secfilter\n");
dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_promisc);
break;
}
netdev_dbg(dev, "start filtering\n");
priv->secfeed->start_filtering(priv->secfeed);
} else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) {
ktime_t timeout = ns_to_ktime(10 * NSEC_PER_MSEC);
/* we have payloads encapsulated in TS */
netdev_dbg(dev, "alloc tsfeed\n");
ret = demux->allocate_ts_feed(demux, &priv->tsfeed, dvb_net_ts_callback);
if (ret < 0) {
pr_err("%s: could not allocate ts feed\n", dev->name);
goto error;
}
/* Set netdevice pointer for ts decaps callback. */
priv->tsfeed->priv = (void *)dev;
ret = priv->tsfeed->set(priv->tsfeed,
priv->pid, /* pid */
TS_PACKET, /* type */
DMX_PES_OTHER, /* pes type */
timeout /* timeout */
);
if (ret < 0) {
pr_err("%s: could not set ts feed\n", dev->name);
priv->demux->release_ts_feed(priv->demux, priv->tsfeed);
priv->tsfeed = NULL;
goto error;
}
netdev_dbg(dev, "start filtering\n");
priv->tsfeed->start_filtering(priv->tsfeed);
} else
ret = -EINVAL;
error:
mutex_unlock(&priv->mutex);
return ret;
}
static int dvb_net_feed_stop(struct net_device *dev)
{
struct dvb_net_priv *priv = netdev_priv(dev);
int i, ret = 0;
mutex_lock(&priv->mutex);
if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) {
if (priv->secfeed) {
if (priv->secfeed->is_filtering) {
netdev_dbg(dev, "stop secfeed\n");
priv->secfeed->stop_filtering(priv->secfeed);
}
if (priv->secfilter) {
netdev_dbg(dev, "release secfilter\n");
priv->secfeed->release_filter(priv->secfeed,
priv->secfilter);
priv->secfilter=NULL;
}
for (i=0; i<priv->multi_num; i++) {
if (priv->multi_secfilter[i]) {
netdev_dbg(dev, "release multi_filter[%d]\n",
i);
priv->secfeed->release_filter(priv->secfeed,
priv->multi_secfilter[i]);
priv->multi_secfilter[i] = NULL;
}
}
priv->demux->release_section_feed(priv->demux, priv->secfeed);
priv->secfeed = NULL;
} else
pr_err("%s: no feed to stop\n", dev->name);
} else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) {
if (priv->tsfeed) {
if (priv->tsfeed->is_filtering) {
netdev_dbg(dev, "stop tsfeed\n");
priv->tsfeed->stop_filtering(priv->tsfeed);
}
priv->demux->release_ts_feed(priv->demux, priv->tsfeed);
priv->tsfeed = NULL;
}
else
pr_err("%s: no ts feed to stop\n", dev->name);
} else
ret = -EINVAL;
mutex_unlock(&priv->mutex);
return ret;
}
static int dvb_set_mc_filter(struct net_device *dev, unsigned char *addr)
{
struct dvb_net_priv *priv = netdev_priv(dev);
if (priv->multi_num == DVB_NET_MULTICAST_MAX)
return -ENOMEM;
memcpy(priv->multi_macs[priv->multi_num], addr, ETH_ALEN);
priv->multi_num++;
return 0;
}
static void wq_set_multicast_list (struct work_struct *work)
{
struct dvb_net_priv *priv =
container_of(work, struct dvb_net_priv, set_multicast_list_wq);
struct net_device *dev = priv->net;
dvb_net_feed_stop(dev);
priv->rx_mode = RX_MODE_UNI;
netif_addr_lock_bh(dev);
if (dev->flags & IFF_PROMISC) {
netdev_dbg(dev, "promiscuous mode\n");
priv->rx_mode = RX_MODE_PROMISC;
} else if ((dev->flags & IFF_ALLMULTI)) {
netdev_dbg(dev, "allmulti mode\n");
priv->rx_mode = RX_MODE_ALL_MULTI;
} else if (!netdev_mc_empty(dev)) {
struct netdev_hw_addr *ha;
netdev_dbg(dev, "set_mc_list, %d entries\n",
netdev_mc_count(dev));
priv->rx_mode = RX_MODE_MULTI;
priv->multi_num = 0;
netdev_for_each_mc_addr(ha, dev)
dvb_set_mc_filter(dev, ha->addr);
}
netif_addr_unlock_bh(dev);
dvb_net_feed_start(dev);
}
static void dvb_net_set_multicast_list (struct net_device *dev)
{
struct dvb_net_priv *priv = netdev_priv(dev);
schedule_work(&priv->set_multicast_list_wq);
}
static void wq_restart_net_feed (struct work_struct *work)
{
struct dvb_net_priv *priv =
container_of(work, struct dvb_net_priv, restart_net_feed_wq);
struct net_device *dev = priv->net;
if (netif_running(dev)) {
dvb_net_feed_stop(dev);
dvb_net_feed_start(dev);
}
}
static int dvb_net_set_mac (struct net_device *dev, void *p)
{
struct dvb_net_priv *priv = netdev_priv(dev);
struct sockaddr *addr=p;
eth_hw_addr_set(dev, addr->sa_data);
if (netif_running(dev))
schedule_work(&priv->restart_net_feed_wq);
return 0;
}
static int dvb_net_open(struct net_device *dev)
{
struct dvb_net_priv *priv = netdev_priv(dev);
priv->in_use++;
dvb_net_feed_start(dev);
return 0;
}
static int dvb_net_stop(struct net_device *dev)
{
struct dvb_net_priv *priv = netdev_priv(dev);
priv->in_use--;
return dvb_net_feed_stop(dev);
}
static const struct header_ops dvb_header_ops = {
.create = eth_header,
.parse = eth_header_parse,
};
static const struct net_device_ops dvb_netdev_ops = {
.ndo_open = dvb_net_open,
.ndo_stop = dvb_net_stop,
.ndo_start_xmit = dvb_net_tx,
.ndo_set_rx_mode = dvb_net_set_multicast_list,
.ndo_set_mac_address = dvb_net_set_mac,
.ndo_validate_addr = eth_validate_addr,
};
static void dvb_net_setup(struct net_device *dev)
{
ether_setup(dev);
dev->header_ops = &dvb_header_ops;
dev->netdev_ops = &dvb_netdev_ops;
dev->mtu = 4096;
dev->max_mtu = 4096;
dev->flags |= IFF_NOARP;
}
static int get_if(struct dvb_net *dvbnet)
{
int i;
for (i=0; i<DVB_NET_DEVICES_MAX; i++)
if (!dvbnet->state[i])
break;
if (i == DVB_NET_DEVICES_MAX)
return -1;
dvbnet->state[i]=1;
return i;
}
static int dvb_net_add_if(struct dvb_net *dvbnet, u16 pid, u8 feedtype)
{
struct net_device *net;
struct dvb_net_priv *priv;
int result;
int if_num;
if (feedtype != DVB_NET_FEEDTYPE_MPE && feedtype != DVB_NET_FEEDTYPE_ULE)
return -EINVAL;
if ((if_num = get_if(dvbnet)) < 0)
return -EINVAL;
net = alloc_netdev(sizeof(struct dvb_net_priv), "dvb",
NET_NAME_UNKNOWN, dvb_net_setup);
if (!net)
return -ENOMEM;
if (dvbnet->dvbdev->id)
snprintf(net->name, IFNAMSIZ, "dvb%d%u%d",
dvbnet->dvbdev->adapter->num, dvbnet->dvbdev->id, if_num);
else
/* compatibility fix to keep dvb0_0 format */
snprintf(net->name, IFNAMSIZ, "dvb%d_%d",
dvbnet->dvbdev->adapter->num, if_num);
net->addr_len = 6;
eth_hw_addr_set(net, dvbnet->dvbdev->adapter->proposed_mac);
dvbnet->device[if_num] = net;
priv = netdev_priv(net);
priv->net = net;
priv->demux = dvbnet->demux;
priv->pid = pid;
priv->rx_mode = RX_MODE_UNI;
priv->need_pusi = 1;
priv->tscc = 0;
priv->feedtype = feedtype;
reset_ule(priv);
INIT_WORK(&priv->set_multicast_list_wq, wq_set_multicast_list);
INIT_WORK(&priv->restart_net_feed_wq, wq_restart_net_feed);
mutex_init(&priv->mutex);
net->base_addr = pid;
if ((result = register_netdev(net)) < 0) {
dvbnet->device[if_num] = NULL;
free_netdev(net);
return result;
}
pr_info("created network interface %s\n", net->name);
return if_num;
}
static int dvb_net_remove_if(struct dvb_net *dvbnet, unsigned long num)
{
struct net_device *net = dvbnet->device[num];
struct dvb_net_priv *priv;
if (!dvbnet->state[num])
return -EINVAL;
priv = netdev_priv(net);
if (priv->in_use)
return -EBUSY;
dvb_net_stop(net);
flush_work(&priv->set_multicast_list_wq);
flush_work(&priv->restart_net_feed_wq);
pr_info("removed network interface %s\n", net->name);
unregister_netdev(net);
dvbnet->state[num]=0;
dvbnet->device[num] = NULL;
free_netdev(net);
return 0;
}
static int dvb_net_do_ioctl(struct file *file,
unsigned int cmd, void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_net *dvbnet = dvbdev->priv;
int ret = 0;
if (((file->f_flags&O_ACCMODE)==O_RDONLY))
return -EPERM;
if (mutex_lock_interruptible(&dvbnet->ioctl_mutex))
return -ERESTARTSYS;
switch (cmd) {
case NET_ADD_IF:
{
struct dvb_net_if *dvbnetif = parg;
int result;
if (!capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
goto ioctl_error;
}
if (!try_module_get(dvbdev->adapter->module)) {
ret = -EPERM;
goto ioctl_error;
}
result=dvb_net_add_if(dvbnet, dvbnetif->pid, dvbnetif->feedtype);
if (result<0) {
module_put(dvbdev->adapter->module);
ret = result;
goto ioctl_error;
}
dvbnetif->if_num=result;
break;
}
case NET_GET_IF:
{
struct net_device *netdev;
struct dvb_net_priv *priv_data;
struct dvb_net_if *dvbnetif = parg;
int if_num = dvbnetif->if_num;
if (if_num >= DVB_NET_DEVICES_MAX) {
ret = -EINVAL;
goto ioctl_error;
}
if_num = array_index_nospec(if_num, DVB_NET_DEVICES_MAX);
if (!dvbnet->state[if_num]) {
ret = -EINVAL;
goto ioctl_error;
}
netdev = dvbnet->device[if_num];
priv_data = netdev_priv(netdev);
dvbnetif->pid=priv_data->pid;
dvbnetif->feedtype=priv_data->feedtype;
break;
}
case NET_REMOVE_IF:
{
if (!capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
goto ioctl_error;
}
if ((unsigned long) parg >= DVB_NET_DEVICES_MAX) {
ret = -EINVAL;
goto ioctl_error;
}
ret = dvb_net_remove_if(dvbnet, (unsigned long) parg);
if (!ret)
module_put(dvbdev->adapter->module);
break;
}
/* binary compatibility cruft */
case __NET_ADD_IF_OLD:
{
struct __dvb_net_if_old *dvbnetif = parg;
int result;
if (!capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
goto ioctl_error;
}
if (!try_module_get(dvbdev->adapter->module)) {
ret = -EPERM;
goto ioctl_error;
}
result=dvb_net_add_if(dvbnet, dvbnetif->pid, DVB_NET_FEEDTYPE_MPE);
if (result<0) {
module_put(dvbdev->adapter->module);
ret = result;
goto ioctl_error;
}
dvbnetif->if_num=result;
break;
}
case __NET_GET_IF_OLD:
{
struct net_device *netdev;
struct dvb_net_priv *priv_data;
struct __dvb_net_if_old *dvbnetif = parg;
int if_num = dvbnetif->if_num;
if (if_num >= DVB_NET_DEVICES_MAX) {
ret = -EINVAL;
goto ioctl_error;
}
if_num = array_index_nospec(if_num, DVB_NET_DEVICES_MAX);
if (!dvbnet->state[if_num]) {
ret = -EINVAL;
goto ioctl_error;
}
netdev = dvbnet->device[if_num];
priv_data = netdev_priv(netdev);
dvbnetif->pid=priv_data->pid;
break;
}
default:
ret = -ENOTTY;
break;
}
ioctl_error:
mutex_unlock(&dvbnet->ioctl_mutex);
return ret;
}
static long dvb_net_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl);
}
static int locked_dvb_net_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_net *dvbnet = dvbdev->priv;
int ret;
if (mutex_lock_interruptible(&dvbnet->remove_mutex))
return -ERESTARTSYS;
if (dvbnet->exit) {
mutex_unlock(&dvbnet->remove_mutex);
return -ENODEV;
}
ret = dvb_generic_open(inode, file);
mutex_unlock(&dvbnet->remove_mutex);
return ret;
}
static int dvb_net_close(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_net *dvbnet = dvbdev->priv;
mutex_lock(&dvbnet->remove_mutex);
dvb_generic_release(inode, file);
if (dvbdev->users == 1 && dvbnet->exit == 1) {
mutex_unlock(&dvbnet->remove_mutex);
wake_up(&dvbdev->wait_queue);
} else {
mutex_unlock(&dvbnet->remove_mutex);
}
return 0;
}
static const struct file_operations dvb_net_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = dvb_net_ioctl,
.open = locked_dvb_net_open,
.release = dvb_net_close,
.llseek = noop_llseek,
};
static const struct dvb_device dvbdev_net = {
.priv = NULL,
.users = 1,
.writers = 1,
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
.name = "dvb-net",
#endif
.fops = &dvb_net_fops,
};
void dvb_net_release (struct dvb_net *dvbnet)
{
int i;
mutex_lock(&dvbnet->remove_mutex);
dvbnet->exit = 1;
mutex_unlock(&dvbnet->remove_mutex);
if (dvbnet->dvbdev->users < 1)
wait_event(dvbnet->dvbdev->wait_queue,
dvbnet->dvbdev->users == 1);
dvb_unregister_device(dvbnet->dvbdev);
for (i=0; i<DVB_NET_DEVICES_MAX; i++) {
if (!dvbnet->state[i])
continue;
dvb_net_remove_if(dvbnet, i);
}
}
EXPORT_SYMBOL(dvb_net_release);
int dvb_net_init (struct dvb_adapter *adap, struct dvb_net *dvbnet,
struct dmx_demux *dmx)
{
int i;
mutex_init(&dvbnet->ioctl_mutex);
mutex_init(&dvbnet->remove_mutex);
dvbnet->demux = dmx;
for (i=0; i<DVB_NET_DEVICES_MAX; i++)
dvbnet->state[i] = 0;
return dvb_register_device(adap, &dvbnet->dvbdev, &dvbdev_net,
dvbnet, DVB_DEVICE_NET, 0);
}
EXPORT_SYMBOL(dvb_net_init);
| linux-master | drivers/media/dvb-core/dvb_net.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* dvb_frontend.c: DVB frontend tuning interface/thread
*
* Copyright (C) 1999-2001 Ralph Metzler
* Marcus Metzler
* Holger Waechtler
* for convergence integrated media GmbH
*
* Copyright (C) 2004 Andrew de Quincey (tuning thread cleanup)
*/
/* Enables DVBv3 compatibility bits at the headers */
#define __DVB_CORE__
#define pr_fmt(fmt) "dvb_frontend: " fmt
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/sched/signal.h>
#include <linux/wait.h>
#include <linux/slab.h>
#include <linux/poll.h>
#include <linux/semaphore.h>
#include <linux/module.h>
#include <linux/nospec.h>
#include <linux/list.h>
#include <linux/freezer.h>
#include <linux/jiffies.h>
#include <linux/kthread.h>
#include <linux/ktime.h>
#include <linux/compat.h>
#include <asm/processor.h>
#include <media/dvb_frontend.h>
#include <media/dvbdev.h>
#include <linux/dvb/version.h>
static int dvb_frontend_debug;
static int dvb_shutdown_timeout;
static int dvb_force_auto_inversion;
static int dvb_override_tune_delay;
static int dvb_powerdown_on_sleep = 1;
static int dvb_mfe_wait_time = 5;
module_param_named(frontend_debug, dvb_frontend_debug, int, 0644);
MODULE_PARM_DESC(frontend_debug, "Turn on/off frontend core debugging (default:off).");
module_param(dvb_shutdown_timeout, int, 0644);
MODULE_PARM_DESC(dvb_shutdown_timeout, "wait <shutdown_timeout> seconds after close() before suspending hardware");
module_param(dvb_force_auto_inversion, int, 0644);
MODULE_PARM_DESC(dvb_force_auto_inversion, "0: normal (default), 1: INVERSION_AUTO forced always");
module_param(dvb_override_tune_delay, int, 0644);
MODULE_PARM_DESC(dvb_override_tune_delay, "0: normal (default), >0 => delay in milliseconds to wait for lock after a tune attempt");
module_param(dvb_powerdown_on_sleep, int, 0644);
MODULE_PARM_DESC(dvb_powerdown_on_sleep, "0: do not power down, 1: turn LNB voltage off on sleep (default)");
module_param(dvb_mfe_wait_time, int, 0644);
MODULE_PARM_DESC(dvb_mfe_wait_time, "Wait up to <mfe_wait_time> seconds on open() for multi-frontend to become available (default:5 seconds)");
#define dprintk(fmt, arg...) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), __func__, ##arg)
#define FESTATE_IDLE 1
#define FESTATE_RETUNE 2
#define FESTATE_TUNING_FAST 4
#define FESTATE_TUNING_SLOW 8
#define FESTATE_TUNED 16
#define FESTATE_ZIGZAG_FAST 32
#define FESTATE_ZIGZAG_SLOW 64
#define FESTATE_DISEQC 128
#define FESTATE_ERROR 256
#define FESTATE_WAITFORLOCK (FESTATE_TUNING_FAST | FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW | FESTATE_DISEQC)
#define FESTATE_SEARCHING_FAST (FESTATE_TUNING_FAST | FESTATE_ZIGZAG_FAST)
#define FESTATE_SEARCHING_SLOW (FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_SLOW)
#define FESTATE_LOSTLOCK (FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW)
/*
* FESTATE_IDLE. No tuning parameters have been supplied and the loop is idling.
* FESTATE_RETUNE. Parameters have been supplied, but we have not yet performed the first tune.
* FESTATE_TUNING_FAST. Tuning parameters have been supplied and fast zigzag scan is in progress.
* FESTATE_TUNING_SLOW. Tuning parameters have been supplied. Fast zigzag failed, so we're trying again, but slower.
* FESTATE_TUNED. The frontend has successfully locked on.
* FESTATE_ZIGZAG_FAST. The lock has been lost, and a fast zigzag has been initiated to try and regain it.
* FESTATE_ZIGZAG_SLOW. The lock has been lost. Fast zigzag has been failed, so we're trying again, but slower.
* FESTATE_DISEQC. A DISEQC command has just been issued.
* FESTATE_WAITFORLOCK. When we're waiting for a lock.
* FESTATE_SEARCHING_FAST. When we're searching for a signal using a fast zigzag scan.
* FESTATE_SEARCHING_SLOW. When we're searching for a signal using a slow zigzag scan.
* FESTATE_LOSTLOCK. When the lock has been lost, and we're searching it again.
*/
static DEFINE_MUTEX(frontend_mutex);
struct dvb_frontend_private {
/* thread/frontend values */
struct dvb_device *dvbdev;
struct dvb_frontend_parameters parameters_out;
struct dvb_fe_events events;
struct semaphore sem;
struct list_head list_head;
wait_queue_head_t wait_queue;
struct task_struct *thread;
unsigned long release_jiffies;
unsigned int wakeup;
enum fe_status status;
unsigned long tune_mode_flags;
unsigned int delay;
unsigned int reinitialise;
int tone;
int voltage;
/* swzigzag values */
unsigned int state;
unsigned int bending;
int lnb_drift;
unsigned int inversion;
unsigned int auto_step;
unsigned int auto_sub_step;
unsigned int started_auto_step;
unsigned int min_delay;
unsigned int max_drift;
unsigned int step_size;
int quality;
unsigned int check_wrapped;
enum dvbfe_search algo_status;
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
struct media_pipeline pipe;
#endif
};
static void dvb_frontend_invoke_release(struct dvb_frontend *fe,
void (*release)(struct dvb_frontend *fe));
static void __dvb_frontend_free(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
if (fepriv)
dvb_device_put(fepriv->dvbdev);
dvb_frontend_invoke_release(fe, fe->ops.release);
kfree(fepriv);
}
static void dvb_frontend_free(struct kref *ref)
{
struct dvb_frontend *fe =
container_of(ref, struct dvb_frontend, refcount);
__dvb_frontend_free(fe);
}
static void dvb_frontend_put(struct dvb_frontend *fe)
{
/* call detach before dropping the reference count */
if (fe->ops.detach)
fe->ops.detach(fe);
/*
* Check if the frontend was registered, as otherwise
* kref was not initialized yet.
*/
if (fe->frontend_priv)
kref_put(&fe->refcount, dvb_frontend_free);
else
__dvb_frontend_free(fe);
}
static void dvb_frontend_get(struct dvb_frontend *fe)
{
kref_get(&fe->refcount);
}
static void dvb_frontend_wakeup(struct dvb_frontend *fe);
static int dtv_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c,
struct dvb_frontend_parameters *p_out);
static int
dtv_property_legacy_params_sync(struct dvb_frontend *fe,
const struct dtv_frontend_properties *c,
struct dvb_frontend_parameters *p);
static bool has_get_frontend(struct dvb_frontend *fe)
{
return fe->ops.get_frontend;
}
/*
* Due to DVBv3 API calls, a delivery system should be mapped into one of
* the 4 DVBv3 delivery systems (FE_QPSK, FE_QAM, FE_OFDM or FE_ATSC),
* otherwise, a DVBv3 call will fail.
*/
enum dvbv3_emulation_type {
DVBV3_UNKNOWN,
DVBV3_QPSK,
DVBV3_QAM,
DVBV3_OFDM,
DVBV3_ATSC,
};
static enum dvbv3_emulation_type dvbv3_type(u32 delivery_system)
{
switch (delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
return DVBV3_QAM;
case SYS_DVBS:
case SYS_DVBS2:
case SYS_TURBO:
case SYS_ISDBS:
case SYS_DSS:
return DVBV3_QPSK;
case SYS_DVBT:
case SYS_DVBT2:
case SYS_ISDBT:
case SYS_DTMB:
return DVBV3_OFDM;
case SYS_ATSC:
case SYS_ATSCMH:
case SYS_DVBC_ANNEX_B:
return DVBV3_ATSC;
case SYS_UNDEFINED:
case SYS_ISDBC:
case SYS_DVBH:
case SYS_DAB:
default:
/*
* Doesn't know how to emulate those types and/or
* there's no frontend driver from this type yet
* with some emulation code, so, we're not sure yet how
* to handle them, or they're not compatible with a DVBv3 call.
*/
return DVBV3_UNKNOWN;
}
}
static void dvb_frontend_add_event(struct dvb_frontend *fe,
enum fe_status status)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_fe_events *events = &fepriv->events;
struct dvb_frontend_event *e;
int wp;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if ((status & FE_HAS_LOCK) && has_get_frontend(fe))
dtv_get_frontend(fe, c, &fepriv->parameters_out);
mutex_lock(&events->mtx);
wp = (events->eventw + 1) % MAX_EVENT;
if (wp == events->eventr) {
events->overflow = 1;
events->eventr = (events->eventr + 1) % MAX_EVENT;
}
e = &events->events[events->eventw];
e->status = status;
e->parameters = fepriv->parameters_out;
events->eventw = wp;
mutex_unlock(&events->mtx);
wake_up_interruptible(&events->wait_queue);
}
static int dvb_frontend_test_event(struct dvb_frontend_private *fepriv,
struct dvb_fe_events *events)
{
int ret;
up(&fepriv->sem);
ret = events->eventw != events->eventr;
down(&fepriv->sem);
return ret;
}
static int dvb_frontend_get_event(struct dvb_frontend *fe,
struct dvb_frontend_event *event, int flags)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dvb_fe_events *events = &fepriv->events;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if (events->overflow) {
events->overflow = 0;
return -EOVERFLOW;
}
if (events->eventw == events->eventr) {
struct wait_queue_entry wait;
int ret = 0;
if (flags & O_NONBLOCK)
return -EWOULDBLOCK;
init_waitqueue_entry(&wait, current);
add_wait_queue(&events->wait_queue, &wait);
while (!dvb_frontend_test_event(fepriv, events)) {
wait_woken(&wait, TASK_INTERRUPTIBLE, 0);
if (signal_pending(current)) {
ret = -ERESTARTSYS;
break;
}
}
remove_wait_queue(&events->wait_queue, &wait);
if (ret < 0)
return ret;
}
mutex_lock(&events->mtx);
*event = events->events[events->eventr];
events->eventr = (events->eventr + 1) % MAX_EVENT;
mutex_unlock(&events->mtx);
return 0;
}
static void dvb_frontend_clear_events(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dvb_fe_events *events = &fepriv->events;
mutex_lock(&events->mtx);
events->eventr = events->eventw;
mutex_unlock(&events->mtx);
}
static void dvb_frontend_init(struct dvb_frontend *fe)
{
dev_dbg(fe->dvb->device,
"%s: initialising adapter %i frontend %i (%s)...\n",
__func__, fe->dvb->num, fe->id, fe->ops.info.name);
if (fe->ops.init)
fe->ops.init(fe);
if (fe->ops.tuner_ops.init) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.init(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
}
void dvb_frontend_reinitialise(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
fepriv->reinitialise = 1;
dvb_frontend_wakeup(fe);
}
EXPORT_SYMBOL(dvb_frontend_reinitialise);
static void dvb_frontend_swzigzag_update_delay(struct dvb_frontend_private *fepriv, int locked)
{
int q2;
struct dvb_frontend *fe = fepriv->dvbdev->priv;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if (locked)
(fepriv->quality) = (fepriv->quality * 220 + 36 * 256) / 256;
else
(fepriv->quality) = (fepriv->quality * 220 + 0) / 256;
q2 = fepriv->quality - 128;
q2 *= q2;
fepriv->delay = fepriv->min_delay + q2 * HZ / (128 * 128);
}
/**
* dvb_frontend_swzigzag_autotune - Performs automatic twiddling of frontend
* parameters.
*
* @fe: The frontend concerned.
* @check_wrapped: Checks if an iteration has completed.
* DO NOT SET ON THE FIRST ATTEMPT.
*
* return: Number of complete iterations that have been performed.
*/
static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wrapped)
{
int autoinversion;
int ready = 0;
int fe_set_err = 0;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp;
int original_inversion = c->inversion;
u32 original_frequency = c->frequency;
/* are we using autoinversion? */
autoinversion = ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) &&
(c->inversion == INVERSION_AUTO));
/* setup parameters correctly */
while (!ready) {
/* calculate the lnb_drift */
fepriv->lnb_drift = fepriv->auto_step * fepriv->step_size;
/* wrap the auto_step if we've exceeded the maximum drift */
if (fepriv->lnb_drift > fepriv->max_drift) {
fepriv->auto_step = 0;
fepriv->auto_sub_step = 0;
fepriv->lnb_drift = 0;
}
/* perform inversion and +/- zigzag */
switch (fepriv->auto_sub_step) {
case 0:
/* try with the current inversion and current drift setting */
ready = 1;
break;
case 1:
if (!autoinversion) break;
fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF;
ready = 1;
break;
case 2:
if (fepriv->lnb_drift == 0) break;
fepriv->lnb_drift = -fepriv->lnb_drift;
ready = 1;
break;
case 3:
if (fepriv->lnb_drift == 0) break;
if (!autoinversion) break;
fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF;
fepriv->lnb_drift = -fepriv->lnb_drift;
ready = 1;
break;
default:
fepriv->auto_step++;
fepriv->auto_sub_step = -1; /* it'll be incremented to 0 in a moment */
break;
}
if (!ready) fepriv->auto_sub_step++;
}
/* if this attempt would hit where we started, indicate a complete
* iteration has occurred */
if ((fepriv->auto_step == fepriv->started_auto_step) &&
(fepriv->auto_sub_step == 0) && check_wrapped) {
return 1;
}
dev_dbg(fe->dvb->device,
"%s: drift:%i inversion:%i auto_step:%i auto_sub_step:%i started_auto_step:%i\n",
__func__, fepriv->lnb_drift, fepriv->inversion,
fepriv->auto_step, fepriv->auto_sub_step,
fepriv->started_auto_step);
/* set the frontend itself */
c->frequency += fepriv->lnb_drift;
if (autoinversion)
c->inversion = fepriv->inversion;
tmp = *c;
if (fe->ops.set_frontend)
fe_set_err = fe->ops.set_frontend(fe);
*c = tmp;
if (fe_set_err < 0) {
fepriv->state = FESTATE_ERROR;
return fe_set_err;
}
c->frequency = original_frequency;
c->inversion = original_inversion;
fepriv->auto_sub_step++;
return 0;
}
static void dvb_frontend_swzigzag(struct dvb_frontend *fe)
{
enum fe_status s = FE_NONE;
int retval = 0;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp;
if (fepriv->max_drift)
dev_warn_once(fe->dvb->device,
"Frontend requested software zigzag, but didn't set the frequency step size\n");
/* if we've got no parameters, just keep idling */
if (fepriv->state & FESTATE_IDLE) {
fepriv->delay = 3 * HZ;
fepriv->quality = 0;
return;
}
/* in SCAN mode, we just set the frontend when asked and leave it alone */
if (fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT) {
if (fepriv->state & FESTATE_RETUNE) {
tmp = *c;
if (fe->ops.set_frontend)
retval = fe->ops.set_frontend(fe);
*c = tmp;
if (retval < 0)
fepriv->state = FESTATE_ERROR;
else
fepriv->state = FESTATE_TUNED;
}
fepriv->delay = 3 * HZ;
fepriv->quality = 0;
return;
}
/* get the frontend status */
if (fepriv->state & FESTATE_RETUNE) {
s = 0;
} else {
if (fe->ops.read_status)
fe->ops.read_status(fe, &s);
if (s != fepriv->status) {
dvb_frontend_add_event(fe, s);
fepriv->status = s;
}
}
/* if we're not tuned, and we have a lock, move to the TUNED state */
if ((fepriv->state & FESTATE_WAITFORLOCK) && (s & FE_HAS_LOCK)) {
dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK);
fepriv->state = FESTATE_TUNED;
/* if we're tuned, then we have determined the correct inversion */
if ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) &&
(c->inversion == INVERSION_AUTO)) {
c->inversion = fepriv->inversion;
}
return;
}
/* if we are tuned already, check we're still locked */
if (fepriv->state & FESTATE_TUNED) {
dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK);
/* we're tuned, and the lock is still good... */
if (s & FE_HAS_LOCK) {
return;
} else { /* if we _WERE_ tuned, but now don't have a lock */
fepriv->state = FESTATE_ZIGZAG_FAST;
fepriv->started_auto_step = fepriv->auto_step;
fepriv->check_wrapped = 0;
}
}
/* don't actually do anything if we're in the LOSTLOCK state,
* the frontend is set to FE_CAN_RECOVER, and the max_drift is 0 */
if ((fepriv->state & FESTATE_LOSTLOCK) &&
(fe->ops.info.caps & FE_CAN_RECOVER) && (fepriv->max_drift == 0)) {
dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK);
return;
}
/* don't do anything if we're in the DISEQC state, since this
* might be someone with a motorized dish controlled by DISEQC.
* If its actually a re-tune, there will be a SET_FRONTEND soon enough. */
if (fepriv->state & FESTATE_DISEQC) {
dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK);
return;
}
/* if we're in the RETUNE state, set everything up for a brand
* new scan, keeping the current inversion setting, as the next
* tune is _very_ likely to require the same */
if (fepriv->state & FESTATE_RETUNE) {
fepriv->lnb_drift = 0;
fepriv->auto_step = 0;
fepriv->auto_sub_step = 0;
fepriv->started_auto_step = 0;
fepriv->check_wrapped = 0;
}
/* fast zigzag. */
if ((fepriv->state & FESTATE_SEARCHING_FAST) || (fepriv->state & FESTATE_RETUNE)) {
fepriv->delay = fepriv->min_delay;
/* perform a tune */
retval = dvb_frontend_swzigzag_autotune(fe,
fepriv->check_wrapped);
if (retval < 0) {
return;
} else if (retval) {
/* OK, if we've run out of trials at the fast speed.
* Drop back to slow for the _next_ attempt */
fepriv->state = FESTATE_SEARCHING_SLOW;
fepriv->started_auto_step = fepriv->auto_step;
return;
}
fepriv->check_wrapped = 1;
/* if we've just re-tuned, enter the ZIGZAG_FAST state.
* This ensures we cannot return from an
* FE_SET_FRONTEND ioctl before the first frontend tune
* occurs */
if (fepriv->state & FESTATE_RETUNE) {
fepriv->state = FESTATE_TUNING_FAST;
}
}
/* slow zigzag */
if (fepriv->state & FESTATE_SEARCHING_SLOW) {
dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK);
/* Note: don't bother checking for wrapping; we stay in this
* state until we get a lock */
dvb_frontend_swzigzag_autotune(fe, 0);
}
}
static int dvb_frontend_is_exiting(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
if (fe->exit != DVB_FE_NO_EXIT)
return 1;
if (fepriv->dvbdev->writers == 1)
if (time_after_eq(jiffies, fepriv->release_jiffies +
dvb_shutdown_timeout * HZ))
return 1;
return 0;
}
static int dvb_frontend_should_wakeup(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
if (fepriv->wakeup) {
fepriv->wakeup = 0;
return 1;
}
return dvb_frontend_is_exiting(fe);
}
static void dvb_frontend_wakeup(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
fepriv->wakeup = 1;
wake_up_interruptible(&fepriv->wait_queue);
}
static int dvb_frontend_thread(void *data)
{
struct dvb_frontend *fe = data;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
enum fe_status s = FE_NONE;
enum dvbfe_algo algo;
bool re_tune = false;
bool semheld = false;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
fepriv->check_wrapped = 0;
fepriv->quality = 0;
fepriv->delay = 3 * HZ;
fepriv->status = 0;
fepriv->wakeup = 0;
fepriv->reinitialise = 0;
dvb_frontend_init(fe);
set_freezable();
while (1) {
up(&fepriv->sem); /* is locked when we enter the thread... */
restart:
wait_event_interruptible_timeout(fepriv->wait_queue,
dvb_frontend_should_wakeup(fe) ||
kthread_should_stop() ||
freezing(current),
fepriv->delay);
if (kthread_should_stop() || dvb_frontend_is_exiting(fe)) {
/* got signal or quitting */
if (!down_interruptible(&fepriv->sem))
semheld = true;
fe->exit = DVB_FE_NORMAL_EXIT;
break;
}
if (try_to_freeze())
goto restart;
if (down_interruptible(&fepriv->sem))
break;
if (fepriv->reinitialise) {
dvb_frontend_init(fe);
if (fe->ops.set_tone && fepriv->tone != -1)
fe->ops.set_tone(fe, fepriv->tone);
if (fe->ops.set_voltage && fepriv->voltage != -1)
fe->ops.set_voltage(fe, fepriv->voltage);
fepriv->reinitialise = 0;
}
/* do an iteration of the tuning loop */
if (fe->ops.get_frontend_algo) {
algo = fe->ops.get_frontend_algo(fe);
switch (algo) {
case DVBFE_ALGO_HW:
dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_HW\n", __func__);
if (fepriv->state & FESTATE_RETUNE) {
dev_dbg(fe->dvb->device, "%s: Retune requested, FESTATE_RETUNE\n", __func__);
re_tune = true;
fepriv->state = FESTATE_TUNED;
} else {
re_tune = false;
}
if (fe->ops.tune)
fe->ops.tune(fe, re_tune, fepriv->tune_mode_flags, &fepriv->delay, &s);
if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) {
dev_dbg(fe->dvb->device, "%s: state changed, adding current state\n", __func__);
dvb_frontend_add_event(fe, s);
fepriv->status = s;
}
break;
case DVBFE_ALGO_SW:
dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_SW\n", __func__);
dvb_frontend_swzigzag(fe);
break;
case DVBFE_ALGO_CUSTOM:
dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state);
if (fepriv->state & FESTATE_RETUNE) {
dev_dbg(fe->dvb->device, "%s: Retune requested, FESTAT_RETUNE\n", __func__);
fepriv->state = FESTATE_TUNED;
}
/* Case where we are going to search for a carrier
* User asked us to retune again for some reason, possibly
* requesting a search with a new set of parameters
*/
if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) {
if (fe->ops.search) {
fepriv->algo_status = fe->ops.search(fe);
/* We did do a search as was requested, the flags are
* now unset as well and has the flags wrt to search.
*/
} else {
fepriv->algo_status &= ~DVBFE_ALGO_SEARCH_AGAIN;
}
}
/* Track the carrier if the search was successful */
if (fepriv->algo_status != DVBFE_ALGO_SEARCH_SUCCESS) {
fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
fepriv->delay = HZ / 2;
}
dtv_property_legacy_params_sync(fe, c, &fepriv->parameters_out);
fe->ops.read_status(fe, &s);
if (s != fepriv->status) {
dvb_frontend_add_event(fe, s); /* update event list */
fepriv->status = s;
if (!(s & FE_HAS_LOCK)) {
fepriv->delay = HZ / 10;
fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
} else {
fepriv->delay = 60 * HZ;
}
}
break;
default:
dev_dbg(fe->dvb->device, "%s: UNDEFINED ALGO !\n", __func__);
break;
}
} else {
dvb_frontend_swzigzag(fe);
}
}
if (dvb_powerdown_on_sleep) {
if (fe->ops.set_voltage)
fe->ops.set_voltage(fe, SEC_VOLTAGE_OFF);
if (fe->ops.tuner_ops.sleep) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.sleep(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (fe->ops.sleep)
fe->ops.sleep(fe);
}
fepriv->thread = NULL;
if (kthread_should_stop())
fe->exit = DVB_FE_DEVICE_REMOVED;
else
fe->exit = DVB_FE_NO_EXIT;
mb();
if (semheld)
up(&fepriv->sem);
dvb_frontend_wakeup(fe);
return 0;
}
static void dvb_frontend_stop(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if (fe->exit != DVB_FE_DEVICE_REMOVED)
fe->exit = DVB_FE_NORMAL_EXIT;
mb();
if (!fepriv->thread)
return;
kthread_stop(fepriv->thread);
sema_init(&fepriv->sem, 1);
fepriv->state = FESTATE_IDLE;
/* paranoia check in case a signal arrived */
if (fepriv->thread)
dev_warn(fe->dvb->device,
"dvb_frontend_stop: warning: thread %p won't exit\n",
fepriv->thread);
}
/*
* Sleep for the amount of time given by add_usec parameter
*
* This needs to be as precise as possible, as it affects the detection of
* the dish tone command at the satellite subsystem. The precision is improved
* by using a scheduled msleep followed by udelay for the remainder.
*/
void dvb_frontend_sleep_until(ktime_t *waketime, u32 add_usec)
{
s32 delta;
*waketime = ktime_add_us(*waketime, add_usec);
delta = ktime_us_delta(ktime_get_boottime(), *waketime);
if (delta > 2500) {
msleep((delta - 1500) / 1000);
delta = ktime_us_delta(ktime_get_boottime(), *waketime);
}
if (delta > 0)
udelay(delta);
}
EXPORT_SYMBOL(dvb_frontend_sleep_until);
static int dvb_frontend_start(struct dvb_frontend *fe)
{
int ret;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct task_struct *fe_thread;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if (fepriv->thread) {
if (fe->exit == DVB_FE_NO_EXIT)
return 0;
else
dvb_frontend_stop(fe);
}
if (signal_pending(current))
return -EINTR;
if (down_interruptible(&fepriv->sem))
return -EINTR;
fepriv->state = FESTATE_IDLE;
fe->exit = DVB_FE_NO_EXIT;
fepriv->thread = NULL;
mb();
fe_thread = kthread_run(dvb_frontend_thread, fe,
"kdvb-ad-%i-fe-%i", fe->dvb->num, fe->id);
if (IS_ERR(fe_thread)) {
ret = PTR_ERR(fe_thread);
dev_warn(fe->dvb->device,
"dvb_frontend_start: failed to start kthread (%d)\n",
ret);
up(&fepriv->sem);
return ret;
}
fepriv->thread = fe_thread;
return 0;
}
static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe,
u32 *freq_min, u32 *freq_max,
u32 *tolerance)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 tuner_min = fe->ops.tuner_ops.info.frequency_min_hz;
u32 tuner_max = fe->ops.tuner_ops.info.frequency_max_hz;
u32 frontend_min = fe->ops.info.frequency_min_hz;
u32 frontend_max = fe->ops.info.frequency_max_hz;
*freq_min = max(frontend_min, tuner_min);
if (frontend_max == 0)
*freq_max = tuner_max;
else if (tuner_max == 0)
*freq_max = frontend_max;
else
*freq_max = min(frontend_max, tuner_max);
if (*freq_min == 0 || *freq_max == 0)
dev_warn(fe->dvb->device,
"DVB: adapter %i frontend %u frequency limits undefined - fix the driver\n",
fe->dvb->num, fe->id);
dev_dbg(fe->dvb->device, "frequency interval: tuner: %u...%u, frontend: %u...%u",
tuner_min, tuner_max, frontend_min, frontend_max);
/* If the standard is for satellite, convert frequencies to kHz */
switch (c->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
case SYS_DVBS2:
case SYS_TURBO:
case SYS_ISDBS:
*freq_min /= kHz;
*freq_max /= kHz;
if (tolerance)
*tolerance = fe->ops.info.frequency_tolerance_hz / kHz;
break;
default:
if (tolerance)
*tolerance = fe->ops.info.frequency_tolerance_hz;
break;
}
}
static u32 dvb_frontend_get_stepsize(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 fe_step = fe->ops.info.frequency_stepsize_hz;
u32 tuner_step = fe->ops.tuner_ops.info.frequency_step_hz;
u32 step = max(fe_step, tuner_step);
switch (c->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
case SYS_DVBS2:
case SYS_TURBO:
case SYS_ISDBS:
step /= kHz;
break;
default:
break;
}
return step;
}
static int dvb_frontend_check_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 freq_min;
u32 freq_max;
/* range check: frequency */
dvb_frontend_get_frequency_limits(fe, &freq_min, &freq_max, NULL);
if ((freq_min && c->frequency < freq_min) ||
(freq_max && c->frequency > freq_max)) {
dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i frequency %u out of range (%u..%u)\n",
fe->dvb->num, fe->id, c->frequency,
freq_min, freq_max);
return -EINVAL;
}
/* range check: symbol rate */
switch (c->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
case SYS_DVBS2:
case SYS_TURBO:
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
if ((fe->ops.info.symbol_rate_min &&
c->symbol_rate < fe->ops.info.symbol_rate_min) ||
(fe->ops.info.symbol_rate_max &&
c->symbol_rate > fe->ops.info.symbol_rate_max)) {
dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i symbol rate %u out of range (%u..%u)\n",
fe->dvb->num, fe->id, c->symbol_rate,
fe->ops.info.symbol_rate_min,
fe->ops.info.symbol_rate_max);
return -EINVAL;
}
break;
default:
break;
}
return 0;
}
static int dvb_frontend_clear_cache(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int i;
u32 delsys;
delsys = c->delivery_system;
memset(c, 0, offsetof(struct dtv_frontend_properties, strength));
c->delivery_system = delsys;
dev_dbg(fe->dvb->device, "%s: Clearing cache for delivery system %d\n",
__func__, c->delivery_system);
c->transmission_mode = TRANSMISSION_MODE_AUTO;
c->bandwidth_hz = 0; /* AUTO */
c->guard_interval = GUARD_INTERVAL_AUTO;
c->hierarchy = HIERARCHY_AUTO;
c->symbol_rate = 0;
c->code_rate_HP = FEC_AUTO;
c->code_rate_LP = FEC_AUTO;
c->fec_inner = FEC_AUTO;
c->rolloff = ROLLOFF_AUTO;
c->voltage = SEC_VOLTAGE_OFF;
c->sectone = SEC_TONE_OFF;
c->pilot = PILOT_AUTO;
c->isdbt_partial_reception = 0;
c->isdbt_sb_mode = 0;
c->isdbt_sb_subchannel = 0;
c->isdbt_sb_segment_idx = 0;
c->isdbt_sb_segment_count = 0;
c->isdbt_layer_enabled = 7; /* All layers (A,B,C) */
for (i = 0; i < 3; i++) {
c->layer[i].fec = FEC_AUTO;
c->layer[i].modulation = QAM_AUTO;
c->layer[i].interleaving = 0;
c->layer[i].segment_count = 0;
}
c->stream_id = NO_STREAM_ID_FILTER;
c->scrambling_sequence_index = 0;/* default sequence */
switch (c->delivery_system) {
case SYS_DSS:
c->modulation = QPSK;
c->rolloff = ROLLOFF_20;
break;
case SYS_DVBS:
case SYS_DVBS2:
case SYS_TURBO:
c->modulation = QPSK; /* implied for DVB-S in legacy API */
c->rolloff = ROLLOFF_35;/* implied for DVB-S */
break;
case SYS_ATSC:
c->modulation = VSB_8;
break;
case SYS_ISDBS:
c->symbol_rate = 28860000;
c->rolloff = ROLLOFF_35;
c->bandwidth_hz = c->symbol_rate / 100 * 135;
break;
default:
c->modulation = QAM_AUTO;
break;
}
c->lna = LNA_AUTO;
return 0;
}
#define _DTV_CMD(n) \
[n] = #n
static char *dtv_cmds[DTV_MAX_COMMAND + 1] = {
_DTV_CMD(DTV_TUNE),
_DTV_CMD(DTV_CLEAR),
/* Set */
_DTV_CMD(DTV_FREQUENCY),
_DTV_CMD(DTV_BANDWIDTH_HZ),
_DTV_CMD(DTV_MODULATION),
_DTV_CMD(DTV_INVERSION),
_DTV_CMD(DTV_DISEQC_MASTER),
_DTV_CMD(DTV_SYMBOL_RATE),
_DTV_CMD(DTV_INNER_FEC),
_DTV_CMD(DTV_VOLTAGE),
_DTV_CMD(DTV_TONE),
_DTV_CMD(DTV_PILOT),
_DTV_CMD(DTV_ROLLOFF),
_DTV_CMD(DTV_DELIVERY_SYSTEM),
_DTV_CMD(DTV_HIERARCHY),
_DTV_CMD(DTV_CODE_RATE_HP),
_DTV_CMD(DTV_CODE_RATE_LP),
_DTV_CMD(DTV_GUARD_INTERVAL),
_DTV_CMD(DTV_TRANSMISSION_MODE),
_DTV_CMD(DTV_INTERLEAVING),
_DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION),
_DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING),
_DTV_CMD(DTV_ISDBT_SB_SUBCHANNEL_ID),
_DTV_CMD(DTV_ISDBT_SB_SEGMENT_IDX),
_DTV_CMD(DTV_ISDBT_SB_SEGMENT_COUNT),
_DTV_CMD(DTV_ISDBT_LAYER_ENABLED),
_DTV_CMD(DTV_ISDBT_LAYERA_FEC),
_DTV_CMD(DTV_ISDBT_LAYERA_MODULATION),
_DTV_CMD(DTV_ISDBT_LAYERA_SEGMENT_COUNT),
_DTV_CMD(DTV_ISDBT_LAYERA_TIME_INTERLEAVING),
_DTV_CMD(DTV_ISDBT_LAYERB_FEC),
_DTV_CMD(DTV_ISDBT_LAYERB_MODULATION),
_DTV_CMD(DTV_ISDBT_LAYERB_SEGMENT_COUNT),
_DTV_CMD(DTV_ISDBT_LAYERB_TIME_INTERLEAVING),
_DTV_CMD(DTV_ISDBT_LAYERC_FEC),
_DTV_CMD(DTV_ISDBT_LAYERC_MODULATION),
_DTV_CMD(DTV_ISDBT_LAYERC_SEGMENT_COUNT),
_DTV_CMD(DTV_ISDBT_LAYERC_TIME_INTERLEAVING),
_DTV_CMD(DTV_STREAM_ID),
_DTV_CMD(DTV_DVBT2_PLP_ID_LEGACY),
_DTV_CMD(DTV_SCRAMBLING_SEQUENCE_INDEX),
_DTV_CMD(DTV_LNA),
/* Get */
_DTV_CMD(DTV_DISEQC_SLAVE_REPLY),
_DTV_CMD(DTV_API_VERSION),
_DTV_CMD(DTV_ENUM_DELSYS),
_DTV_CMD(DTV_ATSCMH_PARADE_ID),
_DTV_CMD(DTV_ATSCMH_RS_FRAME_ENSEMBLE),
_DTV_CMD(DTV_ATSCMH_FIC_VER),
_DTV_CMD(DTV_ATSCMH_NOG),
_DTV_CMD(DTV_ATSCMH_TNOG),
_DTV_CMD(DTV_ATSCMH_SGN),
_DTV_CMD(DTV_ATSCMH_PRC),
_DTV_CMD(DTV_ATSCMH_RS_FRAME_MODE),
_DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_PRI),
_DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_SEC),
_DTV_CMD(DTV_ATSCMH_SCCC_BLOCK_MODE),
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_A),
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_B),
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_C),
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_D),
/* Statistics API */
_DTV_CMD(DTV_STAT_SIGNAL_STRENGTH),
_DTV_CMD(DTV_STAT_CNR),
_DTV_CMD(DTV_STAT_PRE_ERROR_BIT_COUNT),
_DTV_CMD(DTV_STAT_PRE_TOTAL_BIT_COUNT),
_DTV_CMD(DTV_STAT_POST_ERROR_BIT_COUNT),
_DTV_CMD(DTV_STAT_POST_TOTAL_BIT_COUNT),
_DTV_CMD(DTV_STAT_ERROR_BLOCK_COUNT),
_DTV_CMD(DTV_STAT_TOTAL_BLOCK_COUNT),
};
static char *dtv_cmd_name(u32 cmd)
{
cmd = array_index_nospec(cmd, DTV_MAX_COMMAND);
return dtv_cmds[cmd];
}
/* Synchronise the legacy tuning parameters into the cache, so that demodulator
* drivers can use a single set_frontend tuning function, regardless of whether
* it's being used for the legacy or new API, reducing code and complexity.
*/
static int dtv_property_cache_sync(struct dvb_frontend *fe,
struct dtv_frontend_properties *c,
const struct dvb_frontend_parameters *p)
{
c->frequency = p->frequency;
c->inversion = p->inversion;
switch (dvbv3_type(c->delivery_system)) {
case DVBV3_QPSK:
dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__);
c->symbol_rate = p->u.qpsk.symbol_rate;
c->fec_inner = p->u.qpsk.fec_inner;
break;
case DVBV3_QAM:
dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__);
c->symbol_rate = p->u.qam.symbol_rate;
c->fec_inner = p->u.qam.fec_inner;
c->modulation = p->u.qam.modulation;
break;
case DVBV3_OFDM:
dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__);
switch (p->u.ofdm.bandwidth) {
case BANDWIDTH_10_MHZ:
c->bandwidth_hz = 10000000;
break;
case BANDWIDTH_8_MHZ:
c->bandwidth_hz = 8000000;
break;
case BANDWIDTH_7_MHZ:
c->bandwidth_hz = 7000000;
break;
case BANDWIDTH_6_MHZ:
c->bandwidth_hz = 6000000;
break;
case BANDWIDTH_5_MHZ:
c->bandwidth_hz = 5000000;
break;
case BANDWIDTH_1_712_MHZ:
c->bandwidth_hz = 1712000;
break;
case BANDWIDTH_AUTO:
c->bandwidth_hz = 0;
}
c->code_rate_HP = p->u.ofdm.code_rate_HP;
c->code_rate_LP = p->u.ofdm.code_rate_LP;
c->modulation = p->u.ofdm.constellation;
c->transmission_mode = p->u.ofdm.transmission_mode;
c->guard_interval = p->u.ofdm.guard_interval;
c->hierarchy = p->u.ofdm.hierarchy_information;
break;
case DVBV3_ATSC:
dev_dbg(fe->dvb->device, "%s: Preparing ATSC req\n", __func__);
c->modulation = p->u.vsb.modulation;
if (c->delivery_system == SYS_ATSCMH)
break;
if ((c->modulation == VSB_8) || (c->modulation == VSB_16))
c->delivery_system = SYS_ATSC;
else
c->delivery_system = SYS_DVBC_ANNEX_B;
break;
case DVBV3_UNKNOWN:
dev_err(fe->dvb->device,
"%s: doesn't know how to handle a DVBv3 call to delivery system %i\n",
__func__, c->delivery_system);
return -EINVAL;
}
return 0;
}
/* Ensure the cached values are set correctly in the frontend
* legacy tuning structures, for the advanced tuning API.
*/
static int
dtv_property_legacy_params_sync(struct dvb_frontend *fe,
const struct dtv_frontend_properties *c,
struct dvb_frontend_parameters *p)
{
p->frequency = c->frequency;
p->inversion = c->inversion;
switch (dvbv3_type(c->delivery_system)) {
case DVBV3_UNKNOWN:
dev_err(fe->dvb->device,
"%s: doesn't know how to handle a DVBv3 call to delivery system %i\n",
__func__, c->delivery_system);
return -EINVAL;
case DVBV3_QPSK:
dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__);
p->u.qpsk.symbol_rate = c->symbol_rate;
p->u.qpsk.fec_inner = c->fec_inner;
break;
case DVBV3_QAM:
dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__);
p->u.qam.symbol_rate = c->symbol_rate;
p->u.qam.fec_inner = c->fec_inner;
p->u.qam.modulation = c->modulation;
break;
case DVBV3_OFDM:
dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__);
switch (c->bandwidth_hz) {
case 10000000:
p->u.ofdm.bandwidth = BANDWIDTH_10_MHZ;
break;
case 8000000:
p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
break;
case 7000000:
p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
break;
case 6000000:
p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
break;
case 5000000:
p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ;
break;
case 1712000:
p->u.ofdm.bandwidth = BANDWIDTH_1_712_MHZ;
break;
case 0:
default:
p->u.ofdm.bandwidth = BANDWIDTH_AUTO;
}
p->u.ofdm.code_rate_HP = c->code_rate_HP;
p->u.ofdm.code_rate_LP = c->code_rate_LP;
p->u.ofdm.constellation = c->modulation;
p->u.ofdm.transmission_mode = c->transmission_mode;
p->u.ofdm.guard_interval = c->guard_interval;
p->u.ofdm.hierarchy_information = c->hierarchy;
break;
case DVBV3_ATSC:
dev_dbg(fe->dvb->device, "%s: Preparing VSB req\n", __func__);
p->u.vsb.modulation = c->modulation;
break;
}
return 0;
}
/**
* dtv_get_frontend - calls a callback for retrieving DTV parameters
* @fe: struct dvb_frontend pointer
* @c: struct dtv_frontend_properties pointer (DVBv5 cache)
* @p_out: struct dvb_frontend_parameters pointer (DVBv3 FE struct)
*
* This routine calls either the DVBv3 or DVBv5 get_frontend call.
* If c is not null, it will update the DVBv5 cache struct pointed by it.
* If p_out is not null, it will update the DVBv3 params pointed by it.
*/
static int dtv_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c,
struct dvb_frontend_parameters *p_out)
{
int r;
if (fe->ops.get_frontend) {
r = fe->ops.get_frontend(fe, c);
if (unlikely(r < 0))
return r;
if (p_out)
dtv_property_legacy_params_sync(fe, c, p_out);
return 0;
}
/* As everything is in cache, get_frontend fops are always supported */
return 0;
}
static int dvb_frontend_handle_ioctl(struct file *file,
unsigned int cmd, void *parg);
static int dtv_property_process_get(struct dvb_frontend *fe,
const struct dtv_frontend_properties *c,
struct dtv_property *tvp,
struct file *file)
{
int ncaps;
unsigned int len = 1;
switch (tvp->cmd) {
case DTV_ENUM_DELSYS:
ncaps = 0;
while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) {
tvp->u.buffer.data[ncaps] = fe->ops.delsys[ncaps];
ncaps++;
}
tvp->u.buffer.len = ncaps;
len = ncaps;
break;
case DTV_FREQUENCY:
tvp->u.data = c->frequency;
break;
case DTV_MODULATION:
tvp->u.data = c->modulation;
break;
case DTV_BANDWIDTH_HZ:
tvp->u.data = c->bandwidth_hz;
break;
case DTV_INVERSION:
tvp->u.data = c->inversion;
break;
case DTV_SYMBOL_RATE:
tvp->u.data = c->symbol_rate;
break;
case DTV_INNER_FEC:
tvp->u.data = c->fec_inner;
break;
case DTV_PILOT:
tvp->u.data = c->pilot;
break;
case DTV_ROLLOFF:
tvp->u.data = c->rolloff;
break;
case DTV_DELIVERY_SYSTEM:
tvp->u.data = c->delivery_system;
break;
case DTV_VOLTAGE:
tvp->u.data = c->voltage;
break;
case DTV_TONE:
tvp->u.data = c->sectone;
break;
case DTV_API_VERSION:
tvp->u.data = (DVB_API_VERSION << 8) | DVB_API_VERSION_MINOR;
break;
case DTV_CODE_RATE_HP:
tvp->u.data = c->code_rate_HP;
break;
case DTV_CODE_RATE_LP:
tvp->u.data = c->code_rate_LP;
break;
case DTV_GUARD_INTERVAL:
tvp->u.data = c->guard_interval;
break;
case DTV_TRANSMISSION_MODE:
tvp->u.data = c->transmission_mode;
break;
case DTV_HIERARCHY:
tvp->u.data = c->hierarchy;
break;
case DTV_INTERLEAVING:
tvp->u.data = c->interleaving;
break;
/* ISDB-T Support here */
case DTV_ISDBT_PARTIAL_RECEPTION:
tvp->u.data = c->isdbt_partial_reception;
break;
case DTV_ISDBT_SOUND_BROADCASTING:
tvp->u.data = c->isdbt_sb_mode;
break;
case DTV_ISDBT_SB_SUBCHANNEL_ID:
tvp->u.data = c->isdbt_sb_subchannel;
break;
case DTV_ISDBT_SB_SEGMENT_IDX:
tvp->u.data = c->isdbt_sb_segment_idx;
break;
case DTV_ISDBT_SB_SEGMENT_COUNT:
tvp->u.data = c->isdbt_sb_segment_count;
break;
case DTV_ISDBT_LAYER_ENABLED:
tvp->u.data = c->isdbt_layer_enabled;
break;
case DTV_ISDBT_LAYERA_FEC:
tvp->u.data = c->layer[0].fec;
break;
case DTV_ISDBT_LAYERA_MODULATION:
tvp->u.data = c->layer[0].modulation;
break;
case DTV_ISDBT_LAYERA_SEGMENT_COUNT:
tvp->u.data = c->layer[0].segment_count;
break;
case DTV_ISDBT_LAYERA_TIME_INTERLEAVING:
tvp->u.data = c->layer[0].interleaving;
break;
case DTV_ISDBT_LAYERB_FEC:
tvp->u.data = c->layer[1].fec;
break;
case DTV_ISDBT_LAYERB_MODULATION:
tvp->u.data = c->layer[1].modulation;
break;
case DTV_ISDBT_LAYERB_SEGMENT_COUNT:
tvp->u.data = c->layer[1].segment_count;
break;
case DTV_ISDBT_LAYERB_TIME_INTERLEAVING:
tvp->u.data = c->layer[1].interleaving;
break;
case DTV_ISDBT_LAYERC_FEC:
tvp->u.data = c->layer[2].fec;
break;
case DTV_ISDBT_LAYERC_MODULATION:
tvp->u.data = c->layer[2].modulation;
break;
case DTV_ISDBT_LAYERC_SEGMENT_COUNT:
tvp->u.data = c->layer[2].segment_count;
break;
case DTV_ISDBT_LAYERC_TIME_INTERLEAVING:
tvp->u.data = c->layer[2].interleaving;
break;
/* Multistream support */
case DTV_STREAM_ID:
case DTV_DVBT2_PLP_ID_LEGACY:
tvp->u.data = c->stream_id;
break;
/* Physical layer scrambling support */
case DTV_SCRAMBLING_SEQUENCE_INDEX:
tvp->u.data = c->scrambling_sequence_index;
break;
/* ATSC-MH */
case DTV_ATSCMH_FIC_VER:
tvp->u.data = fe->dtv_property_cache.atscmh_fic_ver;
break;
case DTV_ATSCMH_PARADE_ID:
tvp->u.data = fe->dtv_property_cache.atscmh_parade_id;
break;
case DTV_ATSCMH_NOG:
tvp->u.data = fe->dtv_property_cache.atscmh_nog;
break;
case DTV_ATSCMH_TNOG:
tvp->u.data = fe->dtv_property_cache.atscmh_tnog;
break;
case DTV_ATSCMH_SGN:
tvp->u.data = fe->dtv_property_cache.atscmh_sgn;
break;
case DTV_ATSCMH_PRC:
tvp->u.data = fe->dtv_property_cache.atscmh_prc;
break;
case DTV_ATSCMH_RS_FRAME_MODE:
tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_mode;
break;
case DTV_ATSCMH_RS_FRAME_ENSEMBLE:
tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_ensemble;
break;
case DTV_ATSCMH_RS_CODE_MODE_PRI:
tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_pri;
break;
case DTV_ATSCMH_RS_CODE_MODE_SEC:
tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_sec;
break;
case DTV_ATSCMH_SCCC_BLOCK_MODE:
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_block_mode;
break;
case DTV_ATSCMH_SCCC_CODE_MODE_A:
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_a;
break;
case DTV_ATSCMH_SCCC_CODE_MODE_B:
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_b;
break;
case DTV_ATSCMH_SCCC_CODE_MODE_C:
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_c;
break;
case DTV_ATSCMH_SCCC_CODE_MODE_D:
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_d;
break;
case DTV_LNA:
tvp->u.data = c->lna;
break;
/* Fill quality measures */
case DTV_STAT_SIGNAL_STRENGTH:
tvp->u.st = c->strength;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_CNR:
tvp->u.st = c->cnr;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_PRE_ERROR_BIT_COUNT:
tvp->u.st = c->pre_bit_error;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_PRE_TOTAL_BIT_COUNT:
tvp->u.st = c->pre_bit_count;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_POST_ERROR_BIT_COUNT:
tvp->u.st = c->post_bit_error;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_POST_TOTAL_BIT_COUNT:
tvp->u.st = c->post_bit_count;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_ERROR_BLOCK_COUNT:
tvp->u.st = c->block_error;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
case DTV_STAT_TOTAL_BLOCK_COUNT:
tvp->u.st = c->block_count;
if (tvp->u.buffer.len > MAX_DTV_STATS * sizeof(u32))
tvp->u.buffer.len = MAX_DTV_STATS * sizeof(u32);
len = tvp->u.buffer.len;
break;
default:
dev_dbg(fe->dvb->device,
"%s: FE property %d doesn't exist\n",
__func__, tvp->cmd);
return -EINVAL;
}
if (len < 1)
len = 1;
dev_dbg(fe->dvb->device,
"%s: GET cmd 0x%08x (%s) len %d: %*ph\n",
__func__, tvp->cmd, dtv_cmd_name(tvp->cmd),
tvp->u.buffer.len, tvp->u.buffer.len, tvp->u.buffer.data);
return 0;
}
static int dtv_set_frontend(struct dvb_frontend *fe);
static bool is_dvbv3_delsys(u32 delsys)
{
return (delsys == SYS_DVBT) || (delsys == SYS_DVBC_ANNEX_A) ||
(delsys == SYS_DVBS) || (delsys == SYS_ATSC);
}
/**
* emulate_delivery_system - emulate a DVBv5 delivery system with a DVBv3 type
* @fe: struct frontend;
* @delsys: DVBv5 type that will be used for emulation
*
* Provides emulation for delivery systems that are compatible with the old
* DVBv3 call. Among its usages, it provices support for ISDB-T, and allows
* using a DVB-S2 only frontend just like it were a DVB-S, if the frontend
* parameters are compatible with DVB-S spec.
*/
static int emulate_delivery_system(struct dvb_frontend *fe, u32 delsys)
{
int i;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
c->delivery_system = delsys;
/*
* If the call is for ISDB-T, put it into full-seg, auto mode, TV
*/
if (c->delivery_system == SYS_ISDBT) {
dev_dbg(fe->dvb->device,
"%s: Using defaults for SYS_ISDBT\n",
__func__);
if (!c->bandwidth_hz)
c->bandwidth_hz = 6000000;
c->isdbt_partial_reception = 0;
c->isdbt_sb_mode = 0;
c->isdbt_sb_subchannel = 0;
c->isdbt_sb_segment_idx = 0;
c->isdbt_sb_segment_count = 0;
c->isdbt_layer_enabled = 7;
for (i = 0; i < 3; i++) {
c->layer[i].fec = FEC_AUTO;
c->layer[i].modulation = QAM_AUTO;
c->layer[i].interleaving = 0;
c->layer[i].segment_count = 0;
}
}
dev_dbg(fe->dvb->device, "%s: change delivery system on cache to %d\n",
__func__, c->delivery_system);
return 0;
}
/**
* dvbv5_set_delivery_system - Sets the delivery system for a DVBv5 API call
* @fe: frontend struct
* @desired_system: delivery system requested by the user
*
* A DVBv5 call know what's the desired system it wants. So, set it.
*
* There are, however, a few known issues with early DVBv5 applications that
* are also handled by this logic:
*
* 1) Some early apps use SYS_UNDEFINED as the desired delivery system.
* This is an API violation, but, as we don't want to break userspace,
* convert it to the first supported delivery system.
* 2) Some apps might be using a DVBv5 call in a wrong way, passing, for
* example, SYS_DVBT instead of SYS_ISDBT. This is because early usage of
* ISDB-T provided backward compat with DVB-T.
*/
static int dvbv5_set_delivery_system(struct dvb_frontend *fe,
u32 desired_system)
{
int ncaps;
u32 delsys = SYS_UNDEFINED;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
enum dvbv3_emulation_type type;
/*
* It was reported that some old DVBv5 applications were
* filling delivery_system with SYS_UNDEFINED. If this happens,
* assume that the application wants to use the first supported
* delivery system.
*/
if (desired_system == SYS_UNDEFINED)
desired_system = fe->ops.delsys[0];
/*
* This is a DVBv5 call. So, it likely knows the supported
* delivery systems. So, check if the desired delivery system is
* supported
*/
ncaps = 0;
while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) {
if (fe->ops.delsys[ncaps] == desired_system) {
c->delivery_system = desired_system;
dev_dbg(fe->dvb->device,
"%s: Changing delivery system to %d\n",
__func__, desired_system);
return 0;
}
ncaps++;
}
/*
* The requested delivery system isn't supported. Maybe userspace
* is requesting a DVBv3 compatible delivery system.
*
* The emulation only works if the desired system is one of the
* delivery systems supported by DVBv3 API
*/
if (!is_dvbv3_delsys(desired_system)) {
dev_dbg(fe->dvb->device,
"%s: Delivery system %d not supported.\n",
__func__, desired_system);
return -EINVAL;
}
type = dvbv3_type(desired_system);
/*
* Get the last non-DVBv3 delivery system that has the same type
* of the desired system
*/
ncaps = 0;
while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) {
if (dvbv3_type(fe->ops.delsys[ncaps]) == type)
delsys = fe->ops.delsys[ncaps];
ncaps++;
}
/* There's nothing compatible with the desired delivery system */
if (delsys == SYS_UNDEFINED) {
dev_dbg(fe->dvb->device,
"%s: Delivery system %d not supported on emulation mode.\n",
__func__, desired_system);
return -EINVAL;
}
dev_dbg(fe->dvb->device,
"%s: Using delivery system %d emulated as if it were %d\n",
__func__, delsys, desired_system);
return emulate_delivery_system(fe, desired_system);
}
/**
* dvbv3_set_delivery_system - Sets the delivery system for a DVBv3 API call
* @fe: frontend struct
*
* A DVBv3 call doesn't know what's the desired system it wants. It also
* doesn't allow to switch between different types. Due to that, userspace
* should use DVBv5 instead.
* However, in order to avoid breaking userspace API, limited backward
* compatibility support is provided.
*
* There are some delivery systems that are incompatible with DVBv3 calls.
*
* This routine should work fine for frontends that support just one delivery
* system.
*
* For frontends that support multiple frontends:
* 1) It defaults to use the first supported delivery system. There's an
* userspace application that allows changing it at runtime;
*
* 2) If the current delivery system is not compatible with DVBv3, it gets
* the first one that it is compatible.
*
* NOTE: in order for this to work with applications like Kaffeine that
* uses a DVBv5 call for DVB-S2 and a DVBv3 call to go back to
* DVB-S, drivers that support both DVB-S and DVB-S2 should have the
* SYS_DVBS entry before the SYS_DVBS2, otherwise it won't switch back
* to DVB-S.
*/
static int dvbv3_set_delivery_system(struct dvb_frontend *fe)
{
int ncaps;
u32 delsys = SYS_UNDEFINED;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
/* If not set yet, defaults to the first supported delivery system */
if (c->delivery_system == SYS_UNDEFINED)
c->delivery_system = fe->ops.delsys[0];
/*
* Trivial case: just use the current one, if it already a DVBv3
* delivery system
*/
if (is_dvbv3_delsys(c->delivery_system)) {
dev_dbg(fe->dvb->device,
"%s: Using delivery system to %d\n",
__func__, c->delivery_system);
return 0;
}
/*
* Seek for the first delivery system that it is compatible with a
* DVBv3 standard
*/
ncaps = 0;
while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) {
if (dvbv3_type(fe->ops.delsys[ncaps]) != DVBV3_UNKNOWN) {
delsys = fe->ops.delsys[ncaps];
break;
}
ncaps++;
}
if (delsys == SYS_UNDEFINED) {
dev_dbg(fe->dvb->device,
"%s: Couldn't find a delivery system that works with FE_SET_FRONTEND\n",
__func__);
return -EINVAL;
}
return emulate_delivery_system(fe, delsys);
}
static void prepare_tuning_algo_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dvb_frontend_tune_settings fetunesettings = { 0 };
/* get frontend-specific tuning settings */
if (fe->ops.get_tune_settings && (fe->ops.get_tune_settings(fe, &fetunesettings) == 0)) {
fepriv->min_delay = (fetunesettings.min_delay_ms * HZ) / 1000;
fepriv->max_drift = fetunesettings.max_drift;
fepriv->step_size = fetunesettings.step_size;
} else {
/* default values */
switch (c->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
case SYS_DVBS2:
case SYS_ISDBS:
case SYS_TURBO:
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
fepriv->min_delay = HZ / 20;
fepriv->step_size = c->symbol_rate / 16000;
fepriv->max_drift = c->symbol_rate / 2000;
break;
case SYS_DVBT:
case SYS_DVBT2:
case SYS_ISDBT:
case SYS_DTMB:
fepriv->min_delay = HZ / 20;
fepriv->step_size = dvb_frontend_get_stepsize(fe) * 2;
fepriv->max_drift = fepriv->step_size + 1;
break;
default:
/*
* FIXME: This sounds wrong! if freqency_stepsize is
* defined by the frontend, why not use it???
*/
fepriv->min_delay = HZ / 20;
fepriv->step_size = 0; /* no zigzag */
fepriv->max_drift = 0;
break;
}
}
if (dvb_override_tune_delay > 0)
fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000;
}
/**
* dtv_property_process_set - Sets a single DTV property
* @fe: Pointer to &struct dvb_frontend
* @file: Pointer to &struct file
* @cmd: Digital TV command
* @data: An unsigned 32-bits number
*
* This routine assigns the property
* value to the corresponding member of
* &struct dtv_frontend_properties
*
* Returns:
* Zero on success, negative errno on failure.
*/
static int dtv_property_process_set(struct dvb_frontend *fe,
struct file *file,
u32 cmd, u32 data)
{
int r = 0;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
/** Dump DTV command name and value*/
if (!cmd || cmd > DTV_MAX_COMMAND)
dev_warn(fe->dvb->device, "%s: SET cmd 0x%08x undefined\n",
__func__, cmd);
else
dev_dbg(fe->dvb->device,
"%s: SET cmd 0x%08x (%s) to 0x%08x\n",
__func__, cmd, dtv_cmd_name(cmd), data);
switch (cmd) {
case DTV_CLEAR:
/*
* Reset a cache of data specific to the frontend here. This does
* not effect hardware.
*/
dvb_frontend_clear_cache(fe);
break;
case DTV_TUNE:
/*
* Use the cached Digital TV properties to tune the
* frontend
*/
dev_dbg(fe->dvb->device,
"%s: Setting the frontend from property cache\n",
__func__);
r = dtv_set_frontend(fe);
break;
case DTV_FREQUENCY:
c->frequency = data;
break;
case DTV_MODULATION:
c->modulation = data;
break;
case DTV_BANDWIDTH_HZ:
c->bandwidth_hz = data;
break;
case DTV_INVERSION:
c->inversion = data;
break;
case DTV_SYMBOL_RATE:
c->symbol_rate = data;
break;
case DTV_INNER_FEC:
c->fec_inner = data;
break;
case DTV_PILOT:
c->pilot = data;
break;
case DTV_ROLLOFF:
c->rolloff = data;
break;
case DTV_DELIVERY_SYSTEM:
r = dvbv5_set_delivery_system(fe, data);
break;
case DTV_VOLTAGE:
c->voltage = data;
r = dvb_frontend_handle_ioctl(file, FE_SET_VOLTAGE,
(void *)c->voltage);
break;
case DTV_TONE:
c->sectone = data;
r = dvb_frontend_handle_ioctl(file, FE_SET_TONE,
(void *)c->sectone);
break;
case DTV_CODE_RATE_HP:
c->code_rate_HP = data;
break;
case DTV_CODE_RATE_LP:
c->code_rate_LP = data;
break;
case DTV_GUARD_INTERVAL:
c->guard_interval = data;
break;
case DTV_TRANSMISSION_MODE:
c->transmission_mode = data;
break;
case DTV_HIERARCHY:
c->hierarchy = data;
break;
case DTV_INTERLEAVING:
c->interleaving = data;
break;
/* ISDB-T Support here */
case DTV_ISDBT_PARTIAL_RECEPTION:
c->isdbt_partial_reception = data;
break;
case DTV_ISDBT_SOUND_BROADCASTING:
c->isdbt_sb_mode = data;
break;
case DTV_ISDBT_SB_SUBCHANNEL_ID:
c->isdbt_sb_subchannel = data;
break;
case DTV_ISDBT_SB_SEGMENT_IDX:
c->isdbt_sb_segment_idx = data;
break;
case DTV_ISDBT_SB_SEGMENT_COUNT:
c->isdbt_sb_segment_count = data;
break;
case DTV_ISDBT_LAYER_ENABLED:
c->isdbt_layer_enabled = data;
break;
case DTV_ISDBT_LAYERA_FEC:
c->layer[0].fec = data;
break;
case DTV_ISDBT_LAYERA_MODULATION:
c->layer[0].modulation = data;
break;
case DTV_ISDBT_LAYERA_SEGMENT_COUNT:
c->layer[0].segment_count = data;
break;
case DTV_ISDBT_LAYERA_TIME_INTERLEAVING:
c->layer[0].interleaving = data;
break;
case DTV_ISDBT_LAYERB_FEC:
c->layer[1].fec = data;
break;
case DTV_ISDBT_LAYERB_MODULATION:
c->layer[1].modulation = data;
break;
case DTV_ISDBT_LAYERB_SEGMENT_COUNT:
c->layer[1].segment_count = data;
break;
case DTV_ISDBT_LAYERB_TIME_INTERLEAVING:
c->layer[1].interleaving = data;
break;
case DTV_ISDBT_LAYERC_FEC:
c->layer[2].fec = data;
break;
case DTV_ISDBT_LAYERC_MODULATION:
c->layer[2].modulation = data;
break;
case DTV_ISDBT_LAYERC_SEGMENT_COUNT:
c->layer[2].segment_count = data;
break;
case DTV_ISDBT_LAYERC_TIME_INTERLEAVING:
c->layer[2].interleaving = data;
break;
/* Multistream support */
case DTV_STREAM_ID:
case DTV_DVBT2_PLP_ID_LEGACY:
c->stream_id = data;
break;
/* Physical layer scrambling support */
case DTV_SCRAMBLING_SEQUENCE_INDEX:
c->scrambling_sequence_index = data;
break;
/* ATSC-MH */
case DTV_ATSCMH_PARADE_ID:
fe->dtv_property_cache.atscmh_parade_id = data;
break;
case DTV_ATSCMH_RS_FRAME_ENSEMBLE:
fe->dtv_property_cache.atscmh_rs_frame_ensemble = data;
break;
case DTV_LNA:
c->lna = data;
if (fe->ops.set_lna)
r = fe->ops.set_lna(fe);
if (r < 0)
c->lna = LNA_AUTO;
break;
default:
return -EINVAL;
}
return r;
}
static int dvb_frontend_do_ioctl(struct file *file, unsigned int cmd,
void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int err;
dev_dbg(fe->dvb->device, "%s: (%d)\n", __func__, _IOC_NR(cmd));
if (down_interruptible(&fepriv->sem))
return -ERESTARTSYS;
if (fe->exit != DVB_FE_NO_EXIT) {
up(&fepriv->sem);
return -ENODEV;
}
/*
* If the frontend is opened in read-only mode, only the ioctls
* that don't interfere with the tune logic should be accepted.
* That allows an external application to monitor the DVB QoS and
* statistics parameters.
*
* That matches all _IOR() ioctls, except for two special cases:
* - FE_GET_EVENT is part of the tuning logic on a DVB application;
* - FE_DISEQC_RECV_SLAVE_REPLY is part of DiSEqC 2.0
* setup
* So, those two ioctls should also return -EPERM, as otherwise
* reading from them would interfere with a DVB tune application
*/
if ((file->f_flags & O_ACCMODE) == O_RDONLY
&& (_IOC_DIR(cmd) != _IOC_READ
|| cmd == FE_GET_EVENT
|| cmd == FE_DISEQC_RECV_SLAVE_REPLY)) {
up(&fepriv->sem);
return -EPERM;
}
err = dvb_frontend_handle_ioctl(file, cmd, parg);
up(&fepriv->sem);
return err;
}
static long dvb_frontend_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct dvb_device *dvbdev = file->private_data;
if (!dvbdev)
return -ENODEV;
return dvb_usercopy(file, cmd, arg, dvb_frontend_do_ioctl);
}
#ifdef CONFIG_COMPAT
struct compat_dtv_property {
__u32 cmd;
__u32 reserved[3];
union {
__u32 data;
struct dtv_fe_stats st;
struct {
__u8 data[32];
__u32 len;
__u32 reserved1[3];
compat_uptr_t reserved2;
} buffer;
} u;
int result;
} __attribute__ ((packed));
struct compat_dtv_properties {
__u32 num;
compat_uptr_t props;
};
#define COMPAT_FE_SET_PROPERTY _IOW('o', 82, struct compat_dtv_properties)
#define COMPAT_FE_GET_PROPERTY _IOR('o', 83, struct compat_dtv_properties)
static int dvb_frontend_handle_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int i, err = 0;
if (cmd == COMPAT_FE_SET_PROPERTY) {
struct compat_dtv_properties prop, *tvps = NULL;
struct compat_dtv_property *tvp = NULL;
if (copy_from_user(&prop, compat_ptr(arg), sizeof(prop)))
return -EFAULT;
tvps = ∝
/*
* Put an arbitrary limit on the number of messages that can
* be sent at once
*/
if (!tvps->num || (tvps->num > DTV_IOCTL_MAX_MSGS))
return -EINVAL;
tvp = memdup_user(compat_ptr(tvps->props), tvps->num * sizeof(*tvp));
if (IS_ERR(tvp))
return PTR_ERR(tvp);
for (i = 0; i < tvps->num; i++) {
err = dtv_property_process_set(fe, file,
(tvp + i)->cmd,
(tvp + i)->u.data);
if (err < 0) {
kfree(tvp);
return err;
}
}
kfree(tvp);
} else if (cmd == COMPAT_FE_GET_PROPERTY) {
struct compat_dtv_properties prop, *tvps = NULL;
struct compat_dtv_property *tvp = NULL;
struct dtv_frontend_properties getp = fe->dtv_property_cache;
if (copy_from_user(&prop, compat_ptr(arg), sizeof(prop)))
return -EFAULT;
tvps = ∝
/*
* Put an arbitrary limit on the number of messages that can
* be sent at once
*/
if (!tvps->num || (tvps->num > DTV_IOCTL_MAX_MSGS))
return -EINVAL;
tvp = memdup_user(compat_ptr(tvps->props), tvps->num * sizeof(*tvp));
if (IS_ERR(tvp))
return PTR_ERR(tvp);
/*
* Let's use our own copy of property cache, in order to
* avoid mangling with DTV zigzag logic, as drivers might
* return crap, if they don't check if the data is available
* before updating the properties cache.
*/
if (fepriv->state != FESTATE_IDLE) {
err = dtv_get_frontend(fe, &getp, NULL);
if (err < 0) {
kfree(tvp);
return err;
}
}
for (i = 0; i < tvps->num; i++) {
err = dtv_property_process_get(
fe, &getp, (struct dtv_property *)(tvp + i), file);
if (err < 0) {
kfree(tvp);
return err;
}
}
if (copy_to_user((void __user *)compat_ptr(tvps->props), tvp,
tvps->num * sizeof(struct compat_dtv_property))) {
kfree(tvp);
return -EFAULT;
}
kfree(tvp);
}
return err;
}
static long dvb_frontend_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int err;
if (cmd == COMPAT_FE_SET_PROPERTY || cmd == COMPAT_FE_GET_PROPERTY) {
if (down_interruptible(&fepriv->sem))
return -ERESTARTSYS;
err = dvb_frontend_handle_compat_ioctl(file, cmd, arg);
up(&fepriv->sem);
return err;
}
return dvb_frontend_ioctl(file, cmd, (unsigned long)compat_ptr(arg));
}
#endif
static int dtv_set_frontend(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 rolloff = 0;
if (dvb_frontend_check_parameters(fe) < 0)
return -EINVAL;
/*
* Initialize output parameters to match the values given by
* the user. FE_SET_FRONTEND triggers an initial frontend event
* with status = 0, which copies output parameters to userspace.
*/
dtv_property_legacy_params_sync(fe, c, &fepriv->parameters_out);
/*
* Be sure that the bandwidth will be filled for all
* non-satellite systems, as tuners need to know what
* low pass/Nyquist half filter should be applied, in
* order to avoid inter-channel noise.
*
* ISDB-T and DVB-T/T2 already sets bandwidth.
* ATSC and DVB-C don't set, so, the core should fill it.
*
* On DVB-C Annex A and C, the bandwidth is a function of
* the roll-off and symbol rate. Annex B defines different
* roll-off factors depending on the modulation. Fortunately,
* Annex B is only used with 6MHz, so there's no need to
* calculate it.
*
* While not officially supported, a side effect of handling it at
* the cache level is that a program could retrieve the bandwidth
* via DTV_BANDWIDTH_HZ, which may be useful for test programs.
*/
switch (c->delivery_system) {
case SYS_ATSC:
case SYS_DVBC_ANNEX_B:
c->bandwidth_hz = 6000000;
break;
case SYS_DVBC_ANNEX_A:
rolloff = 115;
break;
case SYS_DVBC_ANNEX_C:
rolloff = 113;
break;
case SYS_DSS:
rolloff = 120;
break;
case SYS_DVBS:
case SYS_TURBO:
case SYS_ISDBS:
rolloff = 135;
break;
case SYS_DVBS2:
switch (c->rolloff) {
case ROLLOFF_20:
rolloff = 120;
break;
case ROLLOFF_25:
rolloff = 125;
break;
default:
case ROLLOFF_35:
rolloff = 135;
}
break;
default:
break;
}
if (rolloff)
c->bandwidth_hz = mult_frac(c->symbol_rate, rolloff, 100);
/* force auto frequency inversion if requested */
if (dvb_force_auto_inversion)
c->inversion = INVERSION_AUTO;
/*
* without hierarchical coding code_rate_LP is irrelevant,
* so we tolerate the otherwise invalid FEC_NONE setting
*/
if (c->hierarchy == HIERARCHY_NONE && c->code_rate_LP == FEC_NONE)
c->code_rate_LP = FEC_AUTO;
prepare_tuning_algo_parameters(fe);
fepriv->state = FESTATE_RETUNE;
/* Request the search algorithm to search */
fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
dvb_frontend_clear_events(fe);
dvb_frontend_add_event(fe, 0);
dvb_frontend_wakeup(fe);
fepriv->status = 0;
return 0;
}
static int dvb_get_property(struct dvb_frontend *fe, struct file *file,
struct dtv_properties *tvps)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_property *tvp = NULL;
struct dtv_frontend_properties getp;
int i, err;
memcpy(&getp, &fe->dtv_property_cache, sizeof(getp));
dev_dbg(fe->dvb->device, "%s: properties.num = %d\n",
__func__, tvps->num);
dev_dbg(fe->dvb->device, "%s: properties.props = %p\n",
__func__, tvps->props);
/*
* Put an arbitrary limit on the number of messages that can
* be sent at once
*/
if (!tvps->num || tvps->num > DTV_IOCTL_MAX_MSGS)
return -EINVAL;
tvp = memdup_user((void __user *)tvps->props, tvps->num * sizeof(*tvp));
if (IS_ERR(tvp))
return PTR_ERR(tvp);
/*
* Let's use our own copy of property cache, in order to
* avoid mangling with DTV zigzag logic, as drivers might
* return crap, if they don't check if the data is available
* before updating the properties cache.
*/
if (fepriv->state != FESTATE_IDLE) {
err = dtv_get_frontend(fe, &getp, NULL);
if (err < 0)
goto out;
}
for (i = 0; i < tvps->num; i++) {
err = dtv_property_process_get(fe, &getp,
tvp + i, file);
if (err < 0)
goto out;
}
if (copy_to_user((void __user *)tvps->props, tvp,
tvps->num * sizeof(struct dtv_property))) {
err = -EFAULT;
goto out;
}
err = 0;
out:
kfree(tvp);
return err;
}
static int dvb_get_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p_out)
{
struct dtv_frontend_properties getp;
/*
* Let's use our own copy of property cache, in order to
* avoid mangling with DTV zigzag logic, as drivers might
* return crap, if they don't check if the data is available
* before updating the properties cache.
*/
memcpy(&getp, &fe->dtv_property_cache, sizeof(getp));
return dtv_get_frontend(fe, &getp, p_out);
}
static int dvb_frontend_handle_ioctl(struct file *file,
unsigned int cmd, void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int i, err = -ENOTSUPP;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
switch (cmd) {
case FE_SET_PROPERTY: {
struct dtv_properties *tvps = parg;
struct dtv_property *tvp = NULL;
dev_dbg(fe->dvb->device, "%s: properties.num = %d\n",
__func__, tvps->num);
dev_dbg(fe->dvb->device, "%s: properties.props = %p\n",
__func__, tvps->props);
/*
* Put an arbitrary limit on the number of messages that can
* be sent at once
*/
if (!tvps->num || (tvps->num > DTV_IOCTL_MAX_MSGS))
return -EINVAL;
tvp = memdup_user((void __user *)tvps->props, tvps->num * sizeof(*tvp));
if (IS_ERR(tvp))
return PTR_ERR(tvp);
for (i = 0; i < tvps->num; i++) {
err = dtv_property_process_set(fe, file,
(tvp + i)->cmd,
(tvp + i)->u.data);
if (err < 0) {
kfree(tvp);
return err;
}
}
kfree(tvp);
err = 0;
break;
}
case FE_GET_PROPERTY:
err = dvb_get_property(fe, file, parg);
break;
case FE_GET_INFO: {
struct dvb_frontend_info *info = parg;
memset(info, 0, sizeof(*info));
strscpy(info->name, fe->ops.info.name, sizeof(info->name));
info->symbol_rate_min = fe->ops.info.symbol_rate_min;
info->symbol_rate_max = fe->ops.info.symbol_rate_max;
info->symbol_rate_tolerance = fe->ops.info.symbol_rate_tolerance;
info->caps = fe->ops.info.caps;
info->frequency_stepsize = dvb_frontend_get_stepsize(fe);
dvb_frontend_get_frequency_limits(fe, &info->frequency_min,
&info->frequency_max,
&info->frequency_tolerance);
/*
* Associate the 4 delivery systems supported by DVBv3
* API with their DVBv5 counterpart. For the other standards,
* use the closest type, assuming that it would hopefully
* work with a DVBv3 application.
* It should be noticed that, on multi-frontend devices with
* different types (terrestrial and cable, for example),
* a pure DVBv3 application won't be able to use all delivery
* systems. Yet, changing the DVBv5 cache to the other delivery
* system should be enough for making it work.
*/
switch (dvbv3_type(c->delivery_system)) {
case DVBV3_QPSK:
info->type = FE_QPSK;
break;
case DVBV3_ATSC:
info->type = FE_ATSC;
break;
case DVBV3_QAM:
info->type = FE_QAM;
break;
case DVBV3_OFDM:
info->type = FE_OFDM;
break;
default:
dev_err(fe->dvb->device,
"%s: doesn't know how to handle a DVBv3 call to delivery system %i\n",
__func__, c->delivery_system);
info->type = FE_OFDM;
}
dev_dbg(fe->dvb->device, "%s: current delivery system on cache: %d, V3 type: %d\n",
__func__, c->delivery_system, info->type);
/* Set CAN_INVERSION_AUTO bit on in other than oneshot mode */
if (!(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT))
info->caps |= FE_CAN_INVERSION_AUTO;
err = 0;
break;
}
case FE_READ_STATUS: {
enum fe_status *status = parg;
/* if retune was requested but hasn't occurred yet, prevent
* that user get signal state from previous tuning */
if (fepriv->state == FESTATE_RETUNE ||
fepriv->state == FESTATE_ERROR) {
err = 0;
*status = 0;
break;
}
if (fe->ops.read_status)
err = fe->ops.read_status(fe, status);
break;
}
case FE_DISEQC_RESET_OVERLOAD:
if (fe->ops.diseqc_reset_overload) {
err = fe->ops.diseqc_reset_overload(fe);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
case FE_DISEQC_SEND_MASTER_CMD:
if (fe->ops.diseqc_send_master_cmd) {
struct dvb_diseqc_master_cmd *cmd = parg;
if (cmd->msg_len > sizeof(cmd->msg)) {
err = -EINVAL;
break;
}
err = fe->ops.diseqc_send_master_cmd(fe, cmd);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
case FE_DISEQC_SEND_BURST:
if (fe->ops.diseqc_send_burst) {
err = fe->ops.diseqc_send_burst(fe, (long)parg);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
case FE_SET_TONE:
if (fe->ops.set_tone) {
fepriv->tone = (long)parg;
err = fe->ops.set_tone(fe, fepriv->tone);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
case FE_SET_VOLTAGE:
if (fe->ops.set_voltage) {
fepriv->voltage = (long)parg;
err = fe->ops.set_voltage(fe, fepriv->voltage);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
case FE_DISEQC_RECV_SLAVE_REPLY:
if (fe->ops.diseqc_recv_slave_reply)
err = fe->ops.diseqc_recv_slave_reply(fe, parg);
break;
case FE_ENABLE_HIGH_LNB_VOLTAGE:
if (fe->ops.enable_high_lnb_voltage)
err = fe->ops.enable_high_lnb_voltage(fe, (long)parg);
break;
case FE_SET_FRONTEND_TUNE_MODE:
fepriv->tune_mode_flags = (unsigned long)parg;
err = 0;
break;
/* DEPRECATED dish control ioctls */
case FE_DISHNETWORK_SEND_LEGACY_CMD:
if (fe->ops.dishnetwork_send_legacy_command) {
err = fe->ops.dishnetwork_send_legacy_command(fe,
(unsigned long)parg);
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
} else if (fe->ops.set_voltage) {
/*
* NOTE: This is a fallback condition. Some frontends
* (stv0299 for instance) take longer than 8msec to
* respond to a set_voltage command. Those switches
* need custom routines to switch properly. For all
* other frontends, the following should work ok.
* Dish network legacy switches (as used by Dish500)
* are controlled by sending 9-bit command words
* spaced 8msec apart.
* the actual command word is switch/port dependent
* so it is up to the userspace application to send
* the right command.
* The command must always start with a '0' after
* initialization, so parg is 8 bits and does not
* include the initialization or start bit
*/
unsigned long swcmd = ((unsigned long)parg) << 1;
ktime_t nexttime;
ktime_t tv[10];
int i;
u8 last = 1;
if (dvb_frontend_debug)
dprintk("switch command: 0x%04lx\n",
swcmd);
nexttime = ktime_get_boottime();
if (dvb_frontend_debug)
tv[0] = nexttime;
/* before sending a command, initialize by sending
* a 32ms 18V to the switch
*/
fe->ops.set_voltage(fe, SEC_VOLTAGE_18);
dvb_frontend_sleep_until(&nexttime, 32000);
for (i = 0; i < 9; i++) {
if (dvb_frontend_debug)
tv[i + 1] = ktime_get_boottime();
if ((swcmd & 0x01) != last) {
/* set voltage to (last ? 13V : 18V) */
fe->ops.set_voltage(fe, (last) ? SEC_VOLTAGE_13 : SEC_VOLTAGE_18);
last = (last) ? 0 : 1;
}
swcmd = swcmd >> 1;
if (i != 8)
dvb_frontend_sleep_until(&nexttime, 8000);
}
if (dvb_frontend_debug) {
dprintk("(adapter %d): switch delay (should be 32k followed by all 8k)\n",
fe->dvb->num);
for (i = 1; i < 10; i++)
pr_info("%d: %d\n", i,
(int)ktime_us_delta(tv[i], tv[i - 1]));
}
err = 0;
fepriv->state = FESTATE_DISEQC;
fepriv->status = 0;
}
break;
/* DEPRECATED statistics ioctls */
case FE_READ_BER:
if (fe->ops.read_ber) {
if (fepriv->thread)
err = fe->ops.read_ber(fe, parg);
else
err = -EAGAIN;
}
break;
case FE_READ_SIGNAL_STRENGTH:
if (fe->ops.read_signal_strength) {
if (fepriv->thread)
err = fe->ops.read_signal_strength(fe, parg);
else
err = -EAGAIN;
}
break;
case FE_READ_SNR:
if (fe->ops.read_snr) {
if (fepriv->thread)
err = fe->ops.read_snr(fe, parg);
else
err = -EAGAIN;
}
break;
case FE_READ_UNCORRECTED_BLOCKS:
if (fe->ops.read_ucblocks) {
if (fepriv->thread)
err = fe->ops.read_ucblocks(fe, parg);
else
err = -EAGAIN;
}
break;
/* DEPRECATED DVBv3 ioctls */
case FE_SET_FRONTEND:
err = dvbv3_set_delivery_system(fe);
if (err)
break;
err = dtv_property_cache_sync(fe, c, parg);
if (err)
break;
err = dtv_set_frontend(fe);
break;
case FE_GET_EVENT:
err = dvb_frontend_get_event(fe, parg, file->f_flags);
break;
case FE_GET_FRONTEND:
err = dvb_get_frontend(fe, parg);
break;
default:
return -ENOTSUPP;
} /* switch */
return err;
}
static __poll_t dvb_frontend_poll(struct file *file, struct poll_table_struct *wait)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
dev_dbg_ratelimited(fe->dvb->device, "%s:\n", __func__);
poll_wait(file, &fepriv->events.wait_queue, wait);
if (fepriv->events.eventw != fepriv->events.eventr)
return (EPOLLIN | EPOLLRDNORM | EPOLLPRI);
return 0;
}
static int dvb_frontend_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dvb_adapter *adapter = fe->dvb;
int ret;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if (fe->exit == DVB_FE_DEVICE_REMOVED)
return -ENODEV;
if (adapter->mfe_shared == 2) {
mutex_lock(&adapter->mfe_lock);
if ((file->f_flags & O_ACCMODE) != O_RDONLY) {
if (adapter->mfe_dvbdev &&
!adapter->mfe_dvbdev->writers) {
mutex_unlock(&adapter->mfe_lock);
return -EBUSY;
}
adapter->mfe_dvbdev = dvbdev;
}
} else if (adapter->mfe_shared) {
mutex_lock(&adapter->mfe_lock);
if (!adapter->mfe_dvbdev)
adapter->mfe_dvbdev = dvbdev;
else if (adapter->mfe_dvbdev != dvbdev) {
struct dvb_device
*mfedev = adapter->mfe_dvbdev;
struct dvb_frontend
*mfe = mfedev->priv;
struct dvb_frontend_private
*mfepriv = mfe->frontend_priv;
int mferetry = (dvb_mfe_wait_time << 1);
mutex_unlock(&adapter->mfe_lock);
while (mferetry-- && (mfedev->users != -1 ||
mfepriv->thread)) {
if (msleep_interruptible(500)) {
if (signal_pending(current))
return -EINTR;
}
}
mutex_lock(&adapter->mfe_lock);
if (adapter->mfe_dvbdev != dvbdev) {
mfedev = adapter->mfe_dvbdev;
mfe = mfedev->priv;
mfepriv = mfe->frontend_priv;
if (mfedev->users != -1 ||
mfepriv->thread) {
mutex_unlock(&adapter->mfe_lock);
return -EBUSY;
}
adapter->mfe_dvbdev = dvbdev;
}
}
}
if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl) {
if ((ret = fe->ops.ts_bus_ctrl(fe, 1)) < 0)
goto err0;
/* If we took control of the bus, we need to force
reinitialization. This is because many ts_bus_ctrl()
functions strobe the RESET pin on the demod, and if the
frontend thread already exists then the dvb_init() routine
won't get called (which is what usually does initial
register configuration). */
fepriv->reinitialise = 1;
}
if ((ret = dvb_generic_open(inode, file)) < 0)
goto err1;
if ((file->f_flags & O_ACCMODE) != O_RDONLY) {
/* normal tune mode when opened R/W */
fepriv->tune_mode_flags &= ~FE_TUNE_MODE_ONESHOT;
fepriv->tone = -1;
fepriv->voltage = -1;
#ifdef CONFIG_MEDIA_CONTROLLER_DVB
mutex_lock(&fe->dvb->mdev_lock);
if (fe->dvb->mdev) {
mutex_lock(&fe->dvb->mdev->graph_mutex);
if (fe->dvb->mdev->enable_source)
ret = fe->dvb->mdev->enable_source(
dvbdev->entity,
&fepriv->pipe);
mutex_unlock(&fe->dvb->mdev->graph_mutex);
if (ret) {
mutex_unlock(&fe->dvb->mdev_lock);
dev_err(fe->dvb->device,
"Tuner is busy. Error %d\n", ret);
goto err2;
}
}
mutex_unlock(&fe->dvb->mdev_lock);
#endif
ret = dvb_frontend_start(fe);
if (ret)
goto err3;
/* empty event queue */
fepriv->events.eventr = fepriv->events.eventw = 0;
}
dvb_frontend_get(fe);
if (adapter->mfe_shared)
mutex_unlock(&adapter->mfe_lock);
return ret;
err3:
#ifdef CONFIG_MEDIA_CONTROLLER_DVB
mutex_lock(&fe->dvb->mdev_lock);
if (fe->dvb->mdev) {
mutex_lock(&fe->dvb->mdev->graph_mutex);
if (fe->dvb->mdev->disable_source)
fe->dvb->mdev->disable_source(dvbdev->entity);
mutex_unlock(&fe->dvb->mdev->graph_mutex);
}
mutex_unlock(&fe->dvb->mdev_lock);
err2:
#endif
dvb_generic_release(inode, file);
err1:
if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl)
fe->ops.ts_bus_ctrl(fe, 0);
err0:
if (adapter->mfe_shared)
mutex_unlock(&adapter->mfe_lock);
return ret;
}
static int dvb_frontend_release(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int ret;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
if ((file->f_flags & O_ACCMODE) != O_RDONLY) {
fepriv->release_jiffies = jiffies;
mb();
}
ret = dvb_generic_release(inode, file);
if (dvbdev->users == -1) {
wake_up(&fepriv->wait_queue);
#ifdef CONFIG_MEDIA_CONTROLLER_DVB
mutex_lock(&fe->dvb->mdev_lock);
if (fe->dvb->mdev) {
mutex_lock(&fe->dvb->mdev->graph_mutex);
if (fe->dvb->mdev->disable_source)
fe->dvb->mdev->disable_source(dvbdev->entity);
mutex_unlock(&fe->dvb->mdev->graph_mutex);
}
mutex_unlock(&fe->dvb->mdev_lock);
#endif
if (fe->exit != DVB_FE_NO_EXIT)
wake_up(&dvbdev->wait_queue);
if (fe->ops.ts_bus_ctrl)
fe->ops.ts_bus_ctrl(fe, 0);
}
dvb_frontend_put(fe);
return ret;
}
static const struct file_operations dvb_frontend_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = dvb_frontend_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl = dvb_frontend_compat_ioctl,
#endif
.poll = dvb_frontend_poll,
.open = dvb_frontend_open,
.release = dvb_frontend_release,
.llseek = noop_llseek,
};
int dvb_frontend_suspend(struct dvb_frontend *fe)
{
int ret = 0;
dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num,
fe->id);
if (fe->ops.tuner_ops.suspend)
ret = fe->ops.tuner_ops.suspend(fe);
else if (fe->ops.tuner_ops.sleep)
ret = fe->ops.tuner_ops.sleep(fe);
if (fe->ops.suspend)
ret = fe->ops.suspend(fe);
else if (fe->ops.sleep)
ret = fe->ops.sleep(fe);
return ret;
}
EXPORT_SYMBOL(dvb_frontend_suspend);
int dvb_frontend_resume(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int ret = 0;
dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num,
fe->id);
fe->exit = DVB_FE_DEVICE_RESUME;
if (fe->ops.resume)
ret = fe->ops.resume(fe);
else if (fe->ops.init)
ret = fe->ops.init(fe);
if (fe->ops.tuner_ops.resume)
ret = fe->ops.tuner_ops.resume(fe);
else if (fe->ops.tuner_ops.init)
ret = fe->ops.tuner_ops.init(fe);
if (fe->ops.set_tone && fepriv->tone != -1)
fe->ops.set_tone(fe, fepriv->tone);
if (fe->ops.set_voltage && fepriv->voltage != -1)
fe->ops.set_voltage(fe, fepriv->voltage);
fe->exit = DVB_FE_NO_EXIT;
fepriv->state = FESTATE_RETUNE;
dvb_frontend_wakeup(fe);
return ret;
}
EXPORT_SYMBOL(dvb_frontend_resume);
int dvb_register_frontend(struct dvb_adapter *dvb,
struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv;
const struct dvb_device dvbdev_template = {
.users = ~0,
.writers = 1,
.readers = (~0) - 1,
.fops = &dvb_frontend_fops,
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
.name = fe->ops.info.name,
#endif
};
int ret;
dev_dbg(dvb->device, "%s:\n", __func__);
if (mutex_lock_interruptible(&frontend_mutex))
return -ERESTARTSYS;
fe->frontend_priv = kzalloc(sizeof(struct dvb_frontend_private), GFP_KERNEL);
if (!fe->frontend_priv) {
mutex_unlock(&frontend_mutex);
return -ENOMEM;
}
fepriv = fe->frontend_priv;
kref_init(&fe->refcount);
/*
* After initialization, there need to be two references: one
* for dvb_unregister_frontend(), and another one for
* dvb_frontend_detach().
*/
dvb_frontend_get(fe);
sema_init(&fepriv->sem, 1);
init_waitqueue_head(&fepriv->wait_queue);
init_waitqueue_head(&fepriv->events.wait_queue);
mutex_init(&fepriv->events.mtx);
fe->dvb = dvb;
fepriv->inversion = INVERSION_OFF;
dev_info(fe->dvb->device,
"DVB: registering adapter %i frontend %i (%s)...\n",
fe->dvb->num, fe->id, fe->ops.info.name);
ret = dvb_register_device(fe->dvb, &fepriv->dvbdev, &dvbdev_template,
fe, DVB_DEVICE_FRONTEND, 0);
if (ret) {
dvb_frontend_put(fe);
mutex_unlock(&frontend_mutex);
return ret;
}
/*
* Initialize the cache to the proper values according with the
* first supported delivery system (ops->delsys[0])
*/
fe->dtv_property_cache.delivery_system = fe->ops.delsys[0];
dvb_frontend_clear_cache(fe);
mutex_unlock(&frontend_mutex);
return 0;
}
EXPORT_SYMBOL(dvb_register_frontend);
int dvb_unregister_frontend(struct dvb_frontend *fe)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
dev_dbg(fe->dvb->device, "%s:\n", __func__);
mutex_lock(&frontend_mutex);
dvb_frontend_stop(fe);
dvb_remove_device(fepriv->dvbdev);
/* fe is invalid now */
mutex_unlock(&frontend_mutex);
dvb_frontend_put(fe);
return 0;
}
EXPORT_SYMBOL(dvb_unregister_frontend);
static void dvb_frontend_invoke_release(struct dvb_frontend *fe,
void (*release)(struct dvb_frontend *fe))
{
if (release) {
release(fe);
#ifdef CONFIG_MEDIA_ATTACH
dvb_detach(release);
#endif
}
}
void dvb_frontend_detach(struct dvb_frontend *fe)
{
dvb_frontend_invoke_release(fe, fe->ops.release_sec);
dvb_frontend_invoke_release(fe, fe->ops.tuner_ops.release);
dvb_frontend_invoke_release(fe, fe->ops.analog_ops.release);
dvb_frontend_put(fe);
}
EXPORT_SYMBOL(dvb_frontend_detach);
| linux-master | drivers/media/dvb-core/dvb_frontend.c |
// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* dmxdev.c - DVB demultiplexer device
*
* Copyright (C) 2000 Ralph Metzler & Marcus Metzler
* for convergence integrated media GmbH
*/
#define pr_fmt(fmt) "dmxdev: " fmt
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/wait.h>
#include <linux/uaccess.h>
#include <media/dmxdev.h>
#include <media/dvb_vb2.h>
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
static int dvb_dmxdev_buffer_write(struct dvb_ringbuffer *buf,
const u8 *src, size_t len)
{
ssize_t free;
if (!len)
return 0;
if (!buf->data)
return 0;
free = dvb_ringbuffer_free(buf);
if (len > free) {
dprintk("buffer overflow\n");
return -EOVERFLOW;
}
return dvb_ringbuffer_write(buf, src, len);
}
static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src,
int non_blocking, char __user *buf,
size_t count, loff_t *ppos)
{
size_t todo;
ssize_t avail;
ssize_t ret = 0;
if (!src->data)
return 0;
if (src->error) {
ret = src->error;
dvb_ringbuffer_flush(src);
return ret;
}
for (todo = count; todo > 0; todo -= ret) {
if (non_blocking && dvb_ringbuffer_empty(src)) {
ret = -EWOULDBLOCK;
break;
}
ret = wait_event_interruptible(src->queue,
!dvb_ringbuffer_empty(src) ||
(src->error != 0));
if (ret < 0)
break;
if (src->error) {
ret = src->error;
dvb_ringbuffer_flush(src);
break;
}
avail = dvb_ringbuffer_avail(src);
if (avail > todo)
avail = todo;
ret = dvb_ringbuffer_read_user(src, buf, avail);
if (ret < 0)
break;
buf += ret;
}
return (count - todo) ? (count - todo) : ret;
}
static struct dmx_frontend *get_fe(struct dmx_demux *demux, int type)
{
struct list_head *head, *pos;
head = demux->get_frontends(demux);
if (!head)
return NULL;
list_for_each(pos, head)
if (DMX_FE_ENTRY(pos)->source == type)
return DMX_FE_ENTRY(pos);
return NULL;
}
static int dvb_dvr_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
struct dmx_frontend *front;
bool need_ringbuffer = false;
dprintk("%s\n", __func__);
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
if (dmxdev->exit) {
mutex_unlock(&dmxdev->mutex);
return -ENODEV;
}
dmxdev->may_do_mmap = 0;
/*
* The logic here is a little tricky due to the ifdef.
*
* The ringbuffer is used for both read and mmap.
*
* It is not needed, however, on two situations:
* - Write devices (access with O_WRONLY);
* - For duplex device nodes, opened with O_RDWR.
*/
if ((file->f_flags & O_ACCMODE) == O_RDONLY)
need_ringbuffer = true;
else if ((file->f_flags & O_ACCMODE) == O_RDWR) {
if (!(dmxdev->capabilities & DMXDEV_CAP_DUPLEX)) {
#ifdef CONFIG_DVB_MMAP
dmxdev->may_do_mmap = 1;
need_ringbuffer = true;
#else
mutex_unlock(&dmxdev->mutex);
return -EOPNOTSUPP;
#endif
}
}
if (need_ringbuffer) {
void *mem;
if (!dvbdev->readers) {
mutex_unlock(&dmxdev->mutex);
return -EBUSY;
}
mem = vmalloc(DVR_BUFFER_SIZE);
if (!mem) {
mutex_unlock(&dmxdev->mutex);
return -ENOMEM;
}
dvb_ringbuffer_init(&dmxdev->dvr_buffer, mem, DVR_BUFFER_SIZE);
if (dmxdev->may_do_mmap)
dvb_vb2_init(&dmxdev->dvr_vb2_ctx, "dvr",
file->f_flags & O_NONBLOCK);
dvbdev->readers--;
}
if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
dmxdev->dvr_orig_fe = dmxdev->demux->frontend;
if (!dmxdev->demux->write) {
mutex_unlock(&dmxdev->mutex);
return -EOPNOTSUPP;
}
front = get_fe(dmxdev->demux, DMX_MEMORY_FE);
if (!front) {
mutex_unlock(&dmxdev->mutex);
return -EINVAL;
}
dmxdev->demux->disconnect_frontend(dmxdev->demux);
dmxdev->demux->connect_frontend(dmxdev->demux, front);
}
dvbdev->users++;
mutex_unlock(&dmxdev->mutex);
return 0;
}
static int dvb_dvr_release(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
mutex_lock(&dmxdev->mutex);
if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
dmxdev->demux->disconnect_frontend(dmxdev->demux);
dmxdev->demux->connect_frontend(dmxdev->demux,
dmxdev->dvr_orig_fe);
}
if (((file->f_flags & O_ACCMODE) == O_RDONLY) ||
dmxdev->may_do_mmap) {
if (dmxdev->may_do_mmap) {
if (dvb_vb2_is_streaming(&dmxdev->dvr_vb2_ctx))
dvb_vb2_stream_off(&dmxdev->dvr_vb2_ctx);
dvb_vb2_release(&dmxdev->dvr_vb2_ctx);
}
dvbdev->readers++;
if (dmxdev->dvr_buffer.data) {
void *mem = dmxdev->dvr_buffer.data;
/*memory barrier*/
mb();
spin_lock_irq(&dmxdev->lock);
dmxdev->dvr_buffer.data = NULL;
spin_unlock_irq(&dmxdev->lock);
vfree(mem);
}
}
/* TODO */
dvbdev->users--;
if (dvbdev->users == 1 && dmxdev->exit == 1) {
mutex_unlock(&dmxdev->mutex);
wake_up(&dvbdev->wait_queue);
} else
mutex_unlock(&dmxdev->mutex);
return 0;
}
static ssize_t dvb_dvr_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
int ret;
if (!dmxdev->demux->write)
return -EOPNOTSUPP;
if ((file->f_flags & O_ACCMODE) != O_WRONLY)
return -EINVAL;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
if (dmxdev->exit) {
mutex_unlock(&dmxdev->mutex);
return -ENODEV;
}
ret = dmxdev->demux->write(dmxdev->demux, buf, count);
mutex_unlock(&dmxdev->mutex);
return ret;
}
static ssize_t dvb_dvr_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
if (dmxdev->exit)
return -ENODEV;
return dvb_dmxdev_buffer_read(&dmxdev->dvr_buffer,
file->f_flags & O_NONBLOCK,
buf, count, ppos);
}
static int dvb_dvr_set_buffer_size(struct dmxdev *dmxdev,
unsigned long size)
{
struct dvb_ringbuffer *buf = &dmxdev->dvr_buffer;
void *newmem;
void *oldmem;
dprintk("%s\n", __func__);
if (buf->size == size)
return 0;
if (!size)
return -EINVAL;
newmem = vmalloc(size);
if (!newmem)
return -ENOMEM;
oldmem = buf->data;
spin_lock_irq(&dmxdev->lock);
buf->data = newmem;
buf->size = size;
/* reset and not flush in case the buffer shrinks */
dvb_ringbuffer_reset(buf);
spin_unlock_irq(&dmxdev->lock);
vfree(oldmem);
return 0;
}
static inline void dvb_dmxdev_filter_state_set(struct dmxdev_filter
*dmxdevfilter, int state)
{
spin_lock_irq(&dmxdevfilter->dev->lock);
dmxdevfilter->state = state;
spin_unlock_irq(&dmxdevfilter->dev->lock);
}
static int dvb_dmxdev_set_buffer_size(struct dmxdev_filter *dmxdevfilter,
unsigned long size)
{
struct dvb_ringbuffer *buf = &dmxdevfilter->buffer;
void *newmem;
void *oldmem;
if (buf->size == size)
return 0;
if (!size)
return -EINVAL;
if (dmxdevfilter->state >= DMXDEV_STATE_GO)
return -EBUSY;
newmem = vmalloc(size);
if (!newmem)
return -ENOMEM;
oldmem = buf->data;
spin_lock_irq(&dmxdevfilter->dev->lock);
buf->data = newmem;
buf->size = size;
/* reset and not flush in case the buffer shrinks */
dvb_ringbuffer_reset(buf);
spin_unlock_irq(&dmxdevfilter->dev->lock);
vfree(oldmem);
return 0;
}
static void dvb_dmxdev_filter_timeout(struct timer_list *t)
{
struct dmxdev_filter *dmxdevfilter = from_timer(dmxdevfilter, t, timer);
dmxdevfilter->buffer.error = -ETIMEDOUT;
spin_lock_irq(&dmxdevfilter->dev->lock);
dmxdevfilter->state = DMXDEV_STATE_TIMEDOUT;
spin_unlock_irq(&dmxdevfilter->dev->lock);
wake_up(&dmxdevfilter->buffer.queue);
}
static void dvb_dmxdev_filter_timer(struct dmxdev_filter *dmxdevfilter)
{
struct dmx_sct_filter_params *para = &dmxdevfilter->params.sec;
del_timer(&dmxdevfilter->timer);
if (para->timeout) {
dmxdevfilter->timer.expires =
jiffies + 1 + (HZ / 2 + HZ * para->timeout) / 1000;
add_timer(&dmxdevfilter->timer);
}
}
static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len,
const u8 *buffer2, size_t buffer2_len,
struct dmx_section_filter *filter,
u32 *buffer_flags)
{
struct dmxdev_filter *dmxdevfilter = filter->priv;
int ret;
if (!dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx) &&
dmxdevfilter->buffer.error) {
wake_up(&dmxdevfilter->buffer.queue);
return 0;
}
spin_lock(&dmxdevfilter->dev->lock);
if (dmxdevfilter->state != DMXDEV_STATE_GO) {
spin_unlock(&dmxdevfilter->dev->lock);
return 0;
}
del_timer(&dmxdevfilter->timer);
dprintk("section callback %*ph\n", 6, buffer1);
if (dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx)) {
ret = dvb_vb2_fill_buffer(&dmxdevfilter->vb2_ctx,
buffer1, buffer1_len,
buffer_flags);
if (ret == buffer1_len)
ret = dvb_vb2_fill_buffer(&dmxdevfilter->vb2_ctx,
buffer2, buffer2_len,
buffer_flags);
} else {
ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer,
buffer1, buffer1_len);
if (ret == buffer1_len) {
ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer,
buffer2, buffer2_len);
}
}
if (ret < 0)
dmxdevfilter->buffer.error = ret;
if (dmxdevfilter->params.sec.flags & DMX_ONESHOT)
dmxdevfilter->state = DMXDEV_STATE_DONE;
spin_unlock(&dmxdevfilter->dev->lock);
wake_up(&dmxdevfilter->buffer.queue);
return 0;
}
static int dvb_dmxdev_ts_callback(const u8 *buffer1, size_t buffer1_len,
const u8 *buffer2, size_t buffer2_len,
struct dmx_ts_feed *feed,
u32 *buffer_flags)
{
struct dmxdev_filter *dmxdevfilter = feed->priv;
struct dvb_ringbuffer *buffer;
#ifdef CONFIG_DVB_MMAP
struct dvb_vb2_ctx *ctx;
#endif
int ret;
spin_lock(&dmxdevfilter->dev->lock);
if (dmxdevfilter->params.pes.output == DMX_OUT_DECODER) {
spin_unlock(&dmxdevfilter->dev->lock);
return 0;
}
if (dmxdevfilter->params.pes.output == DMX_OUT_TAP ||
dmxdevfilter->params.pes.output == DMX_OUT_TSDEMUX_TAP) {
buffer = &dmxdevfilter->buffer;
#ifdef CONFIG_DVB_MMAP
ctx = &dmxdevfilter->vb2_ctx;
#endif
} else {
buffer = &dmxdevfilter->dev->dvr_buffer;
#ifdef CONFIG_DVB_MMAP
ctx = &dmxdevfilter->dev->dvr_vb2_ctx;
#endif
}
if (dvb_vb2_is_streaming(ctx)) {
ret = dvb_vb2_fill_buffer(ctx, buffer1, buffer1_len,
buffer_flags);
if (ret == buffer1_len)
ret = dvb_vb2_fill_buffer(ctx, buffer2, buffer2_len,
buffer_flags);
} else {
if (buffer->error) {
spin_unlock(&dmxdevfilter->dev->lock);
wake_up(&buffer->queue);
return 0;
}
ret = dvb_dmxdev_buffer_write(buffer, buffer1, buffer1_len);
if (ret == buffer1_len)
ret = dvb_dmxdev_buffer_write(buffer,
buffer2, buffer2_len);
}
if (ret < 0)
buffer->error = ret;
spin_unlock(&dmxdevfilter->dev->lock);
wake_up(&buffer->queue);
return 0;
}
/* stop feed but only mark the specified filter as stopped (state set) */
static int dvb_dmxdev_feed_stop(struct dmxdev_filter *dmxdevfilter)
{
struct dmxdev_feed *feed;
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET);
switch (dmxdevfilter->type) {
case DMXDEV_TYPE_SEC:
del_timer(&dmxdevfilter->timer);
dmxdevfilter->feed.sec->stop_filtering(dmxdevfilter->feed.sec);
break;
case DMXDEV_TYPE_PES:
list_for_each_entry(feed, &dmxdevfilter->feed.ts, next)
feed->ts->stop_filtering(feed->ts);
break;
default:
return -EINVAL;
}
return 0;
}
/* start feed associated with the specified filter */
static int dvb_dmxdev_feed_start(struct dmxdev_filter *filter)
{
struct dmxdev_feed *feed;
int ret;
dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO);
switch (filter->type) {
case DMXDEV_TYPE_SEC:
return filter->feed.sec->start_filtering(filter->feed.sec);
case DMXDEV_TYPE_PES:
list_for_each_entry(feed, &filter->feed.ts, next) {
ret = feed->ts->start_filtering(feed->ts);
if (ret < 0) {
dvb_dmxdev_feed_stop(filter);
return ret;
}
}
break;
default:
return -EINVAL;
}
return 0;
}
/* restart section feed if it has filters left associated with it,
otherwise release the feed */
static int dvb_dmxdev_feed_restart(struct dmxdev_filter *filter)
{
int i;
struct dmxdev *dmxdev = filter->dev;
u16 pid = filter->params.sec.pid;
for (i = 0; i < dmxdev->filternum; i++)
if (dmxdev->filter[i].state >= DMXDEV_STATE_GO &&
dmxdev->filter[i].type == DMXDEV_TYPE_SEC &&
dmxdev->filter[i].params.sec.pid == pid) {
dvb_dmxdev_feed_start(&dmxdev->filter[i]);
return 0;
}
filter->dev->demux->release_section_feed(dmxdev->demux,
filter->feed.sec);
return 0;
}
static int dvb_dmxdev_filter_stop(struct dmxdev_filter *dmxdevfilter)
{
struct dmxdev_feed *feed;
struct dmx_demux *demux;
if (dmxdevfilter->state < DMXDEV_STATE_GO)
return 0;
switch (dmxdevfilter->type) {
case DMXDEV_TYPE_SEC:
if (!dmxdevfilter->feed.sec)
break;
dvb_dmxdev_feed_stop(dmxdevfilter);
if (dmxdevfilter->filter.sec)
dmxdevfilter->feed.sec->
release_filter(dmxdevfilter->feed.sec,
dmxdevfilter->filter.sec);
dvb_dmxdev_feed_restart(dmxdevfilter);
dmxdevfilter->feed.sec = NULL;
break;
case DMXDEV_TYPE_PES:
dvb_dmxdev_feed_stop(dmxdevfilter);
demux = dmxdevfilter->dev->demux;
list_for_each_entry(feed, &dmxdevfilter->feed.ts, next) {
demux->release_ts_feed(demux, feed->ts);
feed->ts = NULL;
}
break;
default:
if (dmxdevfilter->state == DMXDEV_STATE_ALLOCATED)
return 0;
return -EINVAL;
}
dvb_ringbuffer_flush(&dmxdevfilter->buffer);
return 0;
}
static void dvb_dmxdev_delete_pids(struct dmxdev_filter *dmxdevfilter)
{
struct dmxdev_feed *feed, *tmp;
/* delete all PIDs */
list_for_each_entry_safe(feed, tmp, &dmxdevfilter->feed.ts, next) {
list_del(&feed->next);
kfree(feed);
}
BUG_ON(!list_empty(&dmxdevfilter->feed.ts));
}
static inline int dvb_dmxdev_filter_reset(struct dmxdev_filter *dmxdevfilter)
{
if (dmxdevfilter->state < DMXDEV_STATE_SET)
return 0;
if (dmxdevfilter->type == DMXDEV_TYPE_PES)
dvb_dmxdev_delete_pids(dmxdevfilter);
dmxdevfilter->type = DMXDEV_TYPE_NONE;
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED);
return 0;
}
static int dvb_dmxdev_start_feed(struct dmxdev *dmxdev,
struct dmxdev_filter *filter,
struct dmxdev_feed *feed)
{
ktime_t timeout = ktime_set(0, 0);
struct dmx_pes_filter_params *para = &filter->params.pes;
enum dmx_output otype;
int ret;
int ts_type;
enum dmx_ts_pes ts_pes;
struct dmx_ts_feed *tsfeed;
feed->ts = NULL;
otype = para->output;
ts_pes = para->pes_type;
if (ts_pes < DMX_PES_OTHER)
ts_type = TS_DECODER;
else
ts_type = 0;
if (otype == DMX_OUT_TS_TAP)
ts_type |= TS_PACKET;
else if (otype == DMX_OUT_TSDEMUX_TAP)
ts_type |= TS_PACKET | TS_DEMUX;
else if (otype == DMX_OUT_TAP)
ts_type |= TS_PACKET | TS_DEMUX | TS_PAYLOAD_ONLY;
ret = dmxdev->demux->allocate_ts_feed(dmxdev->demux, &feed->ts,
dvb_dmxdev_ts_callback);
if (ret < 0)
return ret;
tsfeed = feed->ts;
tsfeed->priv = filter;
ret = tsfeed->set(tsfeed, feed->pid, ts_type, ts_pes, timeout);
if (ret < 0) {
dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed);
return ret;
}
ret = tsfeed->start_filtering(tsfeed);
if (ret < 0) {
dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed);
return ret;
}
return 0;
}
static int dvb_dmxdev_filter_start(struct dmxdev_filter *filter)
{
struct dmxdev *dmxdev = filter->dev;
struct dmxdev_feed *feed;
void *mem;
int ret, i;
if (filter->state < DMXDEV_STATE_SET)
return -EINVAL;
if (filter->state >= DMXDEV_STATE_GO)
dvb_dmxdev_filter_stop(filter);
if (!filter->buffer.data) {
mem = vmalloc(filter->buffer.size);
if (!mem)
return -ENOMEM;
spin_lock_irq(&filter->dev->lock);
filter->buffer.data = mem;
spin_unlock_irq(&filter->dev->lock);
}
dvb_ringbuffer_flush(&filter->buffer);
switch (filter->type) {
case DMXDEV_TYPE_SEC:
{
struct dmx_sct_filter_params *para = &filter->params.sec;
struct dmx_section_filter **secfilter = &filter->filter.sec;
struct dmx_section_feed **secfeed = &filter->feed.sec;
*secfilter = NULL;
*secfeed = NULL;
/* find active filter/feed with same PID */
for (i = 0; i < dmxdev->filternum; i++) {
if (dmxdev->filter[i].state >= DMXDEV_STATE_GO &&
dmxdev->filter[i].type == DMXDEV_TYPE_SEC &&
dmxdev->filter[i].params.sec.pid == para->pid) {
*secfeed = dmxdev->filter[i].feed.sec;
break;
}
}
/* if no feed found, try to allocate new one */
if (!*secfeed) {
ret = dmxdev->demux->allocate_section_feed(dmxdev->demux,
secfeed,
dvb_dmxdev_section_callback);
if (!*secfeed) {
pr_err("DVB (%s): could not alloc feed\n",
__func__);
return ret;
}
ret = (*secfeed)->set(*secfeed, para->pid,
(para->flags & DMX_CHECK_CRC) ? 1 : 0);
if (ret < 0) {
pr_err("DVB (%s): could not set feed\n",
__func__);
dvb_dmxdev_feed_restart(filter);
return ret;
}
} else {
dvb_dmxdev_feed_stop(filter);
}
ret = (*secfeed)->allocate_filter(*secfeed, secfilter);
if (ret < 0) {
dvb_dmxdev_feed_restart(filter);
filter->feed.sec->start_filtering(*secfeed);
dprintk("could not get filter\n");
return ret;
}
(*secfilter)->priv = filter;
memcpy(&((*secfilter)->filter_value[3]),
&(para->filter.filter[1]), DMX_FILTER_SIZE - 1);
memcpy(&(*secfilter)->filter_mask[3],
¶->filter.mask[1], DMX_FILTER_SIZE - 1);
memcpy(&(*secfilter)->filter_mode[3],
¶->filter.mode[1], DMX_FILTER_SIZE - 1);
(*secfilter)->filter_value[0] = para->filter.filter[0];
(*secfilter)->filter_mask[0] = para->filter.mask[0];
(*secfilter)->filter_mode[0] = para->filter.mode[0];
(*secfilter)->filter_mask[1] = 0;
(*secfilter)->filter_mask[2] = 0;
filter->todo = 0;
ret = filter->feed.sec->start_filtering(filter->feed.sec);
if (ret < 0)
return ret;
dvb_dmxdev_filter_timer(filter);
break;
}
case DMXDEV_TYPE_PES:
list_for_each_entry(feed, &filter->feed.ts, next) {
ret = dvb_dmxdev_start_feed(dmxdev, filter, feed);
if (ret < 0) {
dvb_dmxdev_filter_stop(filter);
return ret;
}
}
break;
default:
return -EINVAL;
}
dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO);
return 0;
}
static int dvb_demux_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
int i;
struct dmxdev_filter *dmxdevfilter;
if (!dmxdev->filter)
return -EINVAL;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
if (dmxdev->exit) {
mutex_unlock(&dmxdev->mutex);
return -ENODEV;
}
for (i = 0; i < dmxdev->filternum; i++)
if (dmxdev->filter[i].state == DMXDEV_STATE_FREE)
break;
if (i == dmxdev->filternum) {
mutex_unlock(&dmxdev->mutex);
return -EMFILE;
}
dmxdevfilter = &dmxdev->filter[i];
mutex_init(&dmxdevfilter->mutex);
file->private_data = dmxdevfilter;
#ifdef CONFIG_DVB_MMAP
dmxdev->may_do_mmap = 1;
#else
dmxdev->may_do_mmap = 0;
#endif
dvb_ringbuffer_init(&dmxdevfilter->buffer, NULL, 8192);
dvb_vb2_init(&dmxdevfilter->vb2_ctx, "demux_filter",
file->f_flags & O_NONBLOCK);
dmxdevfilter->type = DMXDEV_TYPE_NONE;
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED);
timer_setup(&dmxdevfilter->timer, dvb_dmxdev_filter_timeout, 0);
dvbdev->users++;
mutex_unlock(&dmxdev->mutex);
return 0;
}
static int dvb_dmxdev_filter_free(struct dmxdev *dmxdev,
struct dmxdev_filter *dmxdevfilter)
{
mutex_lock(&dmxdev->mutex);
mutex_lock(&dmxdevfilter->mutex);
if (dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx))
dvb_vb2_stream_off(&dmxdevfilter->vb2_ctx);
dvb_vb2_release(&dmxdevfilter->vb2_ctx);
dvb_dmxdev_filter_stop(dmxdevfilter);
dvb_dmxdev_filter_reset(dmxdevfilter);
if (dmxdevfilter->buffer.data) {
void *mem = dmxdevfilter->buffer.data;
spin_lock_irq(&dmxdev->lock);
dmxdevfilter->buffer.data = NULL;
spin_unlock_irq(&dmxdev->lock);
vfree(mem);
}
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_FREE);
wake_up(&dmxdevfilter->buffer.queue);
mutex_unlock(&dmxdevfilter->mutex);
mutex_unlock(&dmxdev->mutex);
return 0;
}
static inline void invert_mode(struct dmx_filter *filter)
{
int i;
for (i = 0; i < DMX_FILTER_SIZE; i++)
filter->mode[i] ^= 0xff;
}
static int dvb_dmxdev_add_pid(struct dmxdev *dmxdev,
struct dmxdev_filter *filter, u16 pid)
{
struct dmxdev_feed *feed;
if ((filter->type != DMXDEV_TYPE_PES) ||
(filter->state < DMXDEV_STATE_SET))
return -EINVAL;
/* only TS packet filters may have multiple PIDs */
if ((filter->params.pes.output != DMX_OUT_TSDEMUX_TAP) &&
(!list_empty(&filter->feed.ts)))
return -EINVAL;
feed = kzalloc(sizeof(struct dmxdev_feed), GFP_KERNEL);
if (feed == NULL)
return -ENOMEM;
feed->pid = pid;
list_add(&feed->next, &filter->feed.ts);
if (filter->state >= DMXDEV_STATE_GO)
return dvb_dmxdev_start_feed(dmxdev, filter, feed);
return 0;
}
static int dvb_dmxdev_remove_pid(struct dmxdev *dmxdev,
struct dmxdev_filter *filter, u16 pid)
{
struct dmxdev_feed *feed, *tmp;
if ((filter->type != DMXDEV_TYPE_PES) ||
(filter->state < DMXDEV_STATE_SET))
return -EINVAL;
list_for_each_entry_safe(feed, tmp, &filter->feed.ts, next) {
if ((feed->pid == pid) && (feed->ts != NULL)) {
feed->ts->stop_filtering(feed->ts);
filter->dev->demux->release_ts_feed(filter->dev->demux,
feed->ts);
list_del(&feed->next);
kfree(feed);
}
}
return 0;
}
static int dvb_dmxdev_filter_set(struct dmxdev *dmxdev,
struct dmxdev_filter *dmxdevfilter,
struct dmx_sct_filter_params *params)
{
dprintk("%s: PID=0x%04x, flags=%02x, timeout=%d\n",
__func__, params->pid, params->flags, params->timeout);
dvb_dmxdev_filter_stop(dmxdevfilter);
dmxdevfilter->type = DMXDEV_TYPE_SEC;
memcpy(&dmxdevfilter->params.sec,
params, sizeof(struct dmx_sct_filter_params));
invert_mode(&dmxdevfilter->params.sec.filter);
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET);
if (params->flags & DMX_IMMEDIATE_START)
return dvb_dmxdev_filter_start(dmxdevfilter);
return 0;
}
static int dvb_dmxdev_pes_filter_set(struct dmxdev *dmxdev,
struct dmxdev_filter *dmxdevfilter,
struct dmx_pes_filter_params *params)
{
int ret;
dvb_dmxdev_filter_stop(dmxdevfilter);
dvb_dmxdev_filter_reset(dmxdevfilter);
if ((unsigned int)params->pes_type > DMX_PES_OTHER)
return -EINVAL;
dmxdevfilter->type = DMXDEV_TYPE_PES;
memcpy(&dmxdevfilter->params, params,
sizeof(struct dmx_pes_filter_params));
INIT_LIST_HEAD(&dmxdevfilter->feed.ts);
dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET);
ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter,
dmxdevfilter->params.pes.pid);
if (ret < 0)
return ret;
if (params->flags & DMX_IMMEDIATE_START)
return dvb_dmxdev_filter_start(dmxdevfilter);
return 0;
}
static ssize_t dvb_dmxdev_read_sec(struct dmxdev_filter *dfil,
struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
int result, hcount;
int done = 0;
if (dfil->todo <= 0) {
hcount = 3 + dfil->todo;
if (hcount > count)
hcount = count;
result = dvb_dmxdev_buffer_read(&dfil->buffer,
file->f_flags & O_NONBLOCK,
buf, hcount, ppos);
if (result < 0) {
dfil->todo = 0;
return result;
}
if (copy_from_user(dfil->secheader - dfil->todo, buf, result))
return -EFAULT;
buf += result;
done = result;
count -= result;
dfil->todo -= result;
if (dfil->todo > -3)
return done;
dfil->todo = ((dfil->secheader[1] << 8) | dfil->secheader[2]) & 0xfff;
if (!count)
return done;
}
if (count > dfil->todo)
count = dfil->todo;
result = dvb_dmxdev_buffer_read(&dfil->buffer,
file->f_flags & O_NONBLOCK,
buf, count, ppos);
if (result < 0)
return result;
dfil->todo -= result;
return (result + done);
}
static ssize_t
dvb_demux_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
struct dmxdev_filter *dmxdevfilter = file->private_data;
int ret;
if (mutex_lock_interruptible(&dmxdevfilter->mutex))
return -ERESTARTSYS;
if (dmxdevfilter->type == DMXDEV_TYPE_SEC)
ret = dvb_dmxdev_read_sec(dmxdevfilter, file, buf, count, ppos);
else
ret = dvb_dmxdev_buffer_read(&dmxdevfilter->buffer,
file->f_flags & O_NONBLOCK,
buf, count, ppos);
mutex_unlock(&dmxdevfilter->mutex);
return ret;
}
static int dvb_demux_do_ioctl(struct file *file,
unsigned int cmd, void *parg)
{
struct dmxdev_filter *dmxdevfilter = file->private_data;
struct dmxdev *dmxdev = dmxdevfilter->dev;
unsigned long arg = (unsigned long)parg;
int ret = 0;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
switch (cmd) {
case DMX_START:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
if (dmxdevfilter->state < DMXDEV_STATE_SET)
ret = -EINVAL;
else
ret = dvb_dmxdev_filter_start(dmxdevfilter);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_STOP:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_dmxdev_filter_stop(dmxdevfilter);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_SET_FILTER:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_dmxdev_filter_set(dmxdev, dmxdevfilter, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_SET_PES_FILTER:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_dmxdev_pes_filter_set(dmxdev, dmxdevfilter, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_SET_BUFFER_SIZE:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_dmxdev_set_buffer_size(dmxdevfilter, arg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_GET_PES_PIDS:
if (!dmxdev->demux->get_pes_pids) {
ret = -EINVAL;
break;
}
dmxdev->demux->get_pes_pids(dmxdev->demux, parg);
break;
case DMX_GET_STC:
if (!dmxdev->demux->get_stc) {
ret = -EINVAL;
break;
}
ret = dmxdev->demux->get_stc(dmxdev->demux,
((struct dmx_stc *)parg)->num,
&((struct dmx_stc *)parg)->stc,
&((struct dmx_stc *)parg)->base);
break;
case DMX_ADD_PID:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
ret = -ERESTARTSYS;
break;
}
ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter, *(u16 *)parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_REMOVE_PID:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
ret = -ERESTARTSYS;
break;
}
ret = dvb_dmxdev_remove_pid(dmxdev, dmxdevfilter, *(u16 *)parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
#ifdef CONFIG_DVB_MMAP
case DMX_REQBUFS:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_reqbufs(&dmxdevfilter->vb2_ctx, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_QUERYBUF:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_querybuf(&dmxdevfilter->vb2_ctx, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_EXPBUF:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_expbuf(&dmxdevfilter->vb2_ctx, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_QBUF:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_qbuf(&dmxdevfilter->vb2_ctx, parg);
if (ret == 0 && !dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx))
ret = dvb_vb2_stream_on(&dmxdevfilter->vb2_ctx);
mutex_unlock(&dmxdevfilter->mutex);
break;
case DMX_DQBUF:
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_dqbuf(&dmxdevfilter->vb2_ctx, parg);
mutex_unlock(&dmxdevfilter->mutex);
break;
#endif
default:
ret = -ENOTTY;
break;
}
mutex_unlock(&dmxdev->mutex);
return ret;
}
static long dvb_demux_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
return dvb_usercopy(file, cmd, arg, dvb_demux_do_ioctl);
}
static __poll_t dvb_demux_poll(struct file *file, poll_table *wait)
{
struct dmxdev_filter *dmxdevfilter = file->private_data;
__poll_t mask = 0;
poll_wait(file, &dmxdevfilter->buffer.queue, wait);
if ((!dmxdevfilter) || dmxdevfilter->dev->exit)
return EPOLLERR;
if (dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx))
return dvb_vb2_poll(&dmxdevfilter->vb2_ctx, file, wait);
if (dmxdevfilter->state != DMXDEV_STATE_GO &&
dmxdevfilter->state != DMXDEV_STATE_DONE &&
dmxdevfilter->state != DMXDEV_STATE_TIMEDOUT)
return 0;
if (dmxdevfilter->buffer.error)
mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI | EPOLLERR);
if (!dvb_ringbuffer_empty(&dmxdevfilter->buffer))
mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI);
return mask;
}
#ifdef CONFIG_DVB_MMAP
static int dvb_demux_mmap(struct file *file, struct vm_area_struct *vma)
{
struct dmxdev_filter *dmxdevfilter = file->private_data;
struct dmxdev *dmxdev = dmxdevfilter->dev;
int ret;
if (!dmxdev->may_do_mmap)
return -ENOTTY;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
mutex_unlock(&dmxdev->mutex);
return -ERESTARTSYS;
}
ret = dvb_vb2_mmap(&dmxdevfilter->vb2_ctx, vma);
mutex_unlock(&dmxdevfilter->mutex);
mutex_unlock(&dmxdev->mutex);
return ret;
}
#endif
static int dvb_demux_release(struct inode *inode, struct file *file)
{
struct dmxdev_filter *dmxdevfilter = file->private_data;
struct dmxdev *dmxdev = dmxdevfilter->dev;
int ret;
ret = dvb_dmxdev_filter_free(dmxdev, dmxdevfilter);
mutex_lock(&dmxdev->mutex);
dmxdev->dvbdev->users--;
if (dmxdev->dvbdev->users == 1 && dmxdev->exit == 1) {
mutex_unlock(&dmxdev->mutex);
wake_up(&dmxdev->dvbdev->wait_queue);
} else
mutex_unlock(&dmxdev->mutex);
return ret;
}
static const struct file_operations dvb_demux_fops = {
.owner = THIS_MODULE,
.read = dvb_demux_read,
.unlocked_ioctl = dvb_demux_ioctl,
.compat_ioctl = dvb_demux_ioctl,
.open = dvb_demux_open,
.release = dvb_demux_release,
.poll = dvb_demux_poll,
.llseek = default_llseek,
#ifdef CONFIG_DVB_MMAP
.mmap = dvb_demux_mmap,
#endif
};
static const struct dvb_device dvbdev_demux = {
.priv = NULL,
.users = 1,
.writers = 1,
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
.name = "dvb-demux",
#endif
.fops = &dvb_demux_fops
};
static int dvb_dvr_do_ioctl(struct file *file,
unsigned int cmd, void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
unsigned long arg = (unsigned long)parg;
int ret;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
switch (cmd) {
case DMX_SET_BUFFER_SIZE:
ret = dvb_dvr_set_buffer_size(dmxdev, arg);
break;
#ifdef CONFIG_DVB_MMAP
case DMX_REQBUFS:
ret = dvb_vb2_reqbufs(&dmxdev->dvr_vb2_ctx, parg);
break;
case DMX_QUERYBUF:
ret = dvb_vb2_querybuf(&dmxdev->dvr_vb2_ctx, parg);
break;
case DMX_EXPBUF:
ret = dvb_vb2_expbuf(&dmxdev->dvr_vb2_ctx, parg);
break;
case DMX_QBUF:
ret = dvb_vb2_qbuf(&dmxdev->dvr_vb2_ctx, parg);
if (ret == 0 && !dvb_vb2_is_streaming(&dmxdev->dvr_vb2_ctx))
ret = dvb_vb2_stream_on(&dmxdev->dvr_vb2_ctx);
break;
case DMX_DQBUF:
ret = dvb_vb2_dqbuf(&dmxdev->dvr_vb2_ctx, parg);
break;
#endif
default:
ret = -ENOTTY;
break;
}
mutex_unlock(&dmxdev->mutex);
return ret;
}
static long dvb_dvr_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
return dvb_usercopy(file, cmd, arg, dvb_dvr_do_ioctl);
}
static __poll_t dvb_dvr_poll(struct file *file, poll_table *wait)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
__poll_t mask = 0;
dprintk("%s\n", __func__);
poll_wait(file, &dmxdev->dvr_buffer.queue, wait);
if (dmxdev->exit)
return EPOLLERR;
if (dvb_vb2_is_streaming(&dmxdev->dvr_vb2_ctx))
return dvb_vb2_poll(&dmxdev->dvr_vb2_ctx, file, wait);
if (((file->f_flags & O_ACCMODE) == O_RDONLY) ||
dmxdev->may_do_mmap) {
if (dmxdev->dvr_buffer.error)
mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI | EPOLLERR);
if (!dvb_ringbuffer_empty(&dmxdev->dvr_buffer))
mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI);
} else
mask |= (EPOLLOUT | EPOLLWRNORM | EPOLLPRI);
return mask;
}
#ifdef CONFIG_DVB_MMAP
static int dvb_dvr_mmap(struct file *file, struct vm_area_struct *vma)
{
struct dvb_device *dvbdev = file->private_data;
struct dmxdev *dmxdev = dvbdev->priv;
int ret;
if (!dmxdev->may_do_mmap)
return -ENOTTY;
if (dmxdev->exit)
return -ENODEV;
if (mutex_lock_interruptible(&dmxdev->mutex))
return -ERESTARTSYS;
ret = dvb_vb2_mmap(&dmxdev->dvr_vb2_ctx, vma);
mutex_unlock(&dmxdev->mutex);
return ret;
}
#endif
static const struct file_operations dvb_dvr_fops = {
.owner = THIS_MODULE,
.read = dvb_dvr_read,
.write = dvb_dvr_write,
.unlocked_ioctl = dvb_dvr_ioctl,
.open = dvb_dvr_open,
.release = dvb_dvr_release,
.poll = dvb_dvr_poll,
.llseek = default_llseek,
#ifdef CONFIG_DVB_MMAP
.mmap = dvb_dvr_mmap,
#endif
};
static const struct dvb_device dvbdev_dvr = {
.priv = NULL,
.readers = 1,
.users = 1,
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
.name = "dvb-dvr",
#endif
.fops = &dvb_dvr_fops
};
int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *dvb_adapter)
{
int i, ret;
if (dmxdev->demux->open(dmxdev->demux) < 0)
return -EUSERS;
dmxdev->filter = vmalloc(array_size(sizeof(struct dmxdev_filter),
dmxdev->filternum));
if (!dmxdev->filter)
return -ENOMEM;
mutex_init(&dmxdev->mutex);
spin_lock_init(&dmxdev->lock);
for (i = 0; i < dmxdev->filternum; i++) {
dmxdev->filter[i].dev = dmxdev;
dmxdev->filter[i].buffer.data = NULL;
dvb_dmxdev_filter_state_set(&dmxdev->filter[i],
DMXDEV_STATE_FREE);
}
ret = dvb_register_device(dvb_adapter, &dmxdev->dvbdev, &dvbdev_demux, dmxdev,
DVB_DEVICE_DEMUX, dmxdev->filternum);
if (ret < 0)
goto err_register_dvbdev;
ret = dvb_register_device(dvb_adapter, &dmxdev->dvr_dvbdev, &dvbdev_dvr,
dmxdev, DVB_DEVICE_DVR, dmxdev->filternum);
if (ret < 0)
goto err_register_dvr_dvbdev;
dvb_ringbuffer_init(&dmxdev->dvr_buffer, NULL, 8192);
return 0;
err_register_dvr_dvbdev:
dvb_unregister_device(dmxdev->dvbdev);
err_register_dvbdev:
vfree(dmxdev->filter);
dmxdev->filter = NULL;
return ret;
}
EXPORT_SYMBOL(dvb_dmxdev_init);
void dvb_dmxdev_release(struct dmxdev *dmxdev)
{
mutex_lock(&dmxdev->mutex);
dmxdev->exit = 1;
mutex_unlock(&dmxdev->mutex);
if (dmxdev->dvbdev->users > 1) {
wait_event(dmxdev->dvbdev->wait_queue,
dmxdev->dvbdev->users == 1);
}
if (dmxdev->dvr_dvbdev->users > 1) {
wait_event(dmxdev->dvr_dvbdev->wait_queue,
dmxdev->dvr_dvbdev->users == 1);
}
dvb_unregister_device(dmxdev->dvbdev);
dvb_unregister_device(dmxdev->dvr_dvbdev);
vfree(dmxdev->filter);
dmxdev->filter = NULL;
dmxdev->demux->close(dmxdev->demux);
}
EXPORT_SYMBOL(dvb_dmxdev_release);
| linux-master | drivers/media/dvb-core/dmxdev.c |
// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* dvbdev.c
*
* Copyright (C) 2000 Ralph Metzler <[email protected]>
* & Marcus Metzler <[email protected]>
* for convergence integrated media GmbH
*/
#define pr_fmt(fmt) "dvbdev: " fmt
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/mutex.h>
#include <media/dvbdev.h>
/* Due to enum tuner_pad_index */
#include <media/tuner.h>
static DEFINE_MUTEX(dvbdev_mutex);
static LIST_HEAD(dvbdevfops_list);
static int dvbdev_debug;
module_param(dvbdev_debug, int, 0644);
MODULE_PARM_DESC(dvbdev_debug, "Turn on/off device debugging (default:off).");
#define dprintk(fmt, arg...) do { \
if (dvbdev_debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
static LIST_HEAD(dvb_adapter_list);
static DEFINE_MUTEX(dvbdev_register_lock);
static const char * const dnames[] = {
[DVB_DEVICE_VIDEO] = "video",
[DVB_DEVICE_AUDIO] = "audio",
[DVB_DEVICE_SEC] = "sec",
[DVB_DEVICE_FRONTEND] = "frontend",
[DVB_DEVICE_DEMUX] = "demux",
[DVB_DEVICE_DVR] = "dvr",
[DVB_DEVICE_CA] = "ca",
[DVB_DEVICE_NET] = "net",
[DVB_DEVICE_OSD] = "osd"
};
#ifdef CONFIG_DVB_DYNAMIC_MINORS
#define MAX_DVB_MINORS 256
#define DVB_MAX_IDS MAX_DVB_MINORS
#else
#define DVB_MAX_IDS 4
static const u8 minor_type[] = {
[DVB_DEVICE_VIDEO] = 0,
[DVB_DEVICE_AUDIO] = 1,
[DVB_DEVICE_SEC] = 2,
[DVB_DEVICE_FRONTEND] = 3,
[DVB_DEVICE_DEMUX] = 4,
[DVB_DEVICE_DVR] = 5,
[DVB_DEVICE_CA] = 6,
[DVB_DEVICE_NET] = 7,
[DVB_DEVICE_OSD] = 8,
};
#define nums2minor(num, type, id) \
(((num) << 6) | ((id) << 4) | minor_type[type])
#define MAX_DVB_MINORS (DVB_MAX_ADAPTERS * 64)
#endif
static struct class *dvb_class;
static struct dvb_device *dvb_minors[MAX_DVB_MINORS];
static DECLARE_RWSEM(minor_rwsem);
static int dvb_device_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev;
mutex_lock(&dvbdev_mutex);
down_read(&minor_rwsem);
dvbdev = dvb_minors[iminor(inode)];
if (dvbdev && dvbdev->fops) {
int err = 0;
const struct file_operations *new_fops;
new_fops = fops_get(dvbdev->fops);
if (!new_fops)
goto fail;
file->private_data = dvb_device_get(dvbdev);
replace_fops(file, new_fops);
if (file->f_op->open)
err = file->f_op->open(inode, file);
up_read(&minor_rwsem);
mutex_unlock(&dvbdev_mutex);
return err;
}
fail:
up_read(&minor_rwsem);
mutex_unlock(&dvbdev_mutex);
return -ENODEV;
}
static const struct file_operations dvb_device_fops = {
.owner = THIS_MODULE,
.open = dvb_device_open,
.llseek = noop_llseek,
};
static struct cdev dvb_device_cdev;
int dvb_generic_open(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
if (!dvbdev)
return -ENODEV;
if (!dvbdev->users)
return -EBUSY;
if ((file->f_flags & O_ACCMODE) == O_RDONLY) {
if (!dvbdev->readers)
return -EBUSY;
dvbdev->readers--;
} else {
if (!dvbdev->writers)
return -EBUSY;
dvbdev->writers--;
}
dvbdev->users--;
return 0;
}
EXPORT_SYMBOL(dvb_generic_open);
int dvb_generic_release(struct inode *inode, struct file *file)
{
struct dvb_device *dvbdev = file->private_data;
if (!dvbdev)
return -ENODEV;
if ((file->f_flags & O_ACCMODE) == O_RDONLY)
dvbdev->readers++;
else
dvbdev->writers++;
dvbdev->users++;
dvb_device_put(dvbdev);
return 0;
}
EXPORT_SYMBOL(dvb_generic_release);
long dvb_generic_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
struct dvb_device *dvbdev = file->private_data;
if (!dvbdev)
return -ENODEV;
if (!dvbdev->kernel_ioctl)
return -EINVAL;
return dvb_usercopy(file, cmd, arg, dvbdev->kernel_ioctl);
}
EXPORT_SYMBOL(dvb_generic_ioctl);
static int dvbdev_get_free_id(struct dvb_adapter *adap, int type)
{
u32 id = 0;
while (id < DVB_MAX_IDS) {
struct dvb_device *dev;
list_for_each_entry(dev, &adap->device_list, list_head)
if (dev->type == type && dev->id == id)
goto skip;
return id;
skip:
id++;
}
return -ENFILE;
}
static void dvb_media_device_free(struct dvb_device *dvbdev)
{
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
if (dvbdev->entity) {
media_device_unregister_entity(dvbdev->entity);
kfree(dvbdev->entity);
kfree(dvbdev->pads);
dvbdev->entity = NULL;
dvbdev->pads = NULL;
}
if (dvbdev->tsout_entity) {
int i;
for (i = 0; i < dvbdev->tsout_num_entities; i++) {
media_device_unregister_entity(&dvbdev->tsout_entity[i]);
kfree(dvbdev->tsout_entity[i].name);
}
kfree(dvbdev->tsout_entity);
kfree(dvbdev->tsout_pads);
dvbdev->tsout_entity = NULL;
dvbdev->tsout_pads = NULL;
dvbdev->tsout_num_entities = 0;
}
if (dvbdev->intf_devnode) {
media_devnode_remove(dvbdev->intf_devnode);
dvbdev->intf_devnode = NULL;
}
if (dvbdev->adapter->conn) {
media_device_unregister_entity(dvbdev->adapter->conn);
kfree(dvbdev->adapter->conn);
dvbdev->adapter->conn = NULL;
kfree(dvbdev->adapter->conn_pads);
dvbdev->adapter->conn_pads = NULL;
}
#endif
}
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
static int dvb_create_tsout_entity(struct dvb_device *dvbdev,
const char *name, int npads)
{
int i;
dvbdev->tsout_pads = kcalloc(npads, sizeof(*dvbdev->tsout_pads),
GFP_KERNEL);
if (!dvbdev->tsout_pads)
return -ENOMEM;
dvbdev->tsout_entity = kcalloc(npads, sizeof(*dvbdev->tsout_entity),
GFP_KERNEL);
if (!dvbdev->tsout_entity)
return -ENOMEM;
dvbdev->tsout_num_entities = npads;
for (i = 0; i < npads; i++) {
struct media_pad *pads = &dvbdev->tsout_pads[i];
struct media_entity *entity = &dvbdev->tsout_entity[i];
int ret;
entity->name = kasprintf(GFP_KERNEL, "%s #%d", name, i);
if (!entity->name)
return -ENOMEM;
entity->function = MEDIA_ENT_F_IO_DTV;
pads->flags = MEDIA_PAD_FL_SINK;
ret = media_entity_pads_init(entity, 1, pads);
if (ret < 0)
return ret;
ret = media_device_register_entity(dvbdev->adapter->mdev,
entity);
if (ret < 0)
return ret;
}
return 0;
}
#define DEMUX_TSOUT "demux-tsout"
#define DVR_TSOUT "dvr-tsout"
static int dvb_create_media_entity(struct dvb_device *dvbdev,
int type, int demux_sink_pads)
{
int i, ret, npads;
switch (type) {
case DVB_DEVICE_FRONTEND:
npads = 2;
break;
case DVB_DEVICE_DVR:
ret = dvb_create_tsout_entity(dvbdev, DVR_TSOUT,
demux_sink_pads);
return ret;
case DVB_DEVICE_DEMUX:
npads = 1 + demux_sink_pads;
ret = dvb_create_tsout_entity(dvbdev, DEMUX_TSOUT,
demux_sink_pads);
if (ret < 0)
return ret;
break;
case DVB_DEVICE_CA:
npads = 2;
break;
case DVB_DEVICE_NET:
/*
* We should be creating entities for the MPE/ULE
* decapsulation hardware (or software implementation).
*
* However, the number of for the MPE/ULE decaps may not be
* fixed. As we don't have yet dynamic support for PADs at
* the Media Controller, let's not create the decap
* entities yet.
*/
return 0;
default:
return 0;
}
dvbdev->entity = kzalloc(sizeof(*dvbdev->entity), GFP_KERNEL);
if (!dvbdev->entity)
return -ENOMEM;
dvbdev->entity->name = dvbdev->name;
if (npads) {
dvbdev->pads = kcalloc(npads, sizeof(*dvbdev->pads),
GFP_KERNEL);
if (!dvbdev->pads) {
kfree(dvbdev->entity);
dvbdev->entity = NULL;
return -ENOMEM;
}
}
switch (type) {
case DVB_DEVICE_FRONTEND:
dvbdev->entity->function = MEDIA_ENT_F_DTV_DEMOD;
dvbdev->pads[0].flags = MEDIA_PAD_FL_SINK;
dvbdev->pads[1].flags = MEDIA_PAD_FL_SOURCE;
break;
case DVB_DEVICE_DEMUX:
dvbdev->entity->function = MEDIA_ENT_F_TS_DEMUX;
dvbdev->pads[0].flags = MEDIA_PAD_FL_SINK;
for (i = 1; i < npads; i++)
dvbdev->pads[i].flags = MEDIA_PAD_FL_SOURCE;
break;
case DVB_DEVICE_CA:
dvbdev->entity->function = MEDIA_ENT_F_DTV_CA;
dvbdev->pads[0].flags = MEDIA_PAD_FL_SINK;
dvbdev->pads[1].flags = MEDIA_PAD_FL_SOURCE;
break;
default:
/* Should never happen, as the first switch prevents it */
kfree(dvbdev->entity);
kfree(dvbdev->pads);
dvbdev->entity = NULL;
dvbdev->pads = NULL;
return 0;
}
if (npads) {
ret = media_entity_pads_init(dvbdev->entity, npads, dvbdev->pads);
if (ret)
return ret;
}
ret = media_device_register_entity(dvbdev->adapter->mdev,
dvbdev->entity);
if (ret)
return ret;
pr_info("%s: media entity '%s' registered.\n",
__func__, dvbdev->entity->name);
return 0;
}
#endif
static int dvb_register_media_device(struct dvb_device *dvbdev,
int type, int minor,
unsigned int demux_sink_pads)
{
#if defined(CONFIG_MEDIA_CONTROLLER_DVB)
struct media_link *link;
u32 intf_type;
int ret;
if (!dvbdev->adapter->mdev)
return 0;
ret = dvb_create_media_entity(dvbdev, type, demux_sink_pads);
if (ret)
return ret;
switch (type) {
case DVB_DEVICE_FRONTEND:
intf_type = MEDIA_INTF_T_DVB_FE;
break;
case DVB_DEVICE_DEMUX:
intf_type = MEDIA_INTF_T_DVB_DEMUX;
break;
case DVB_DEVICE_DVR:
intf_type = MEDIA_INTF_T_DVB_DVR;
break;
case DVB_DEVICE_CA:
intf_type = MEDIA_INTF_T_DVB_CA;
break;
case DVB_DEVICE_NET:
intf_type = MEDIA_INTF_T_DVB_NET;
break;
default:
return 0;
}
dvbdev->intf_devnode = media_devnode_create(dvbdev->adapter->mdev,
intf_type, 0,
DVB_MAJOR, minor);
if (!dvbdev->intf_devnode)
return -ENOMEM;
/*
* Create the "obvious" link, e. g. the ones that represent
* a direct association between an interface and an entity.
* Other links should be created elsewhere, like:
* DVB FE intf -> tuner
* DVB demux intf -> dvr
*/
if (!dvbdev->entity)
return 0;
link = media_create_intf_link(dvbdev->entity,
&dvbdev->intf_devnode->intf,
MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
if (!link)
return -ENOMEM;
#endif
return 0;
}
int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev,
const struct dvb_device *template, void *priv,
enum dvb_device_type type, int demux_sink_pads)
{
struct dvb_device *dvbdev;
struct file_operations *dvbdevfops = NULL;
struct dvbdevfops_node *node = NULL, *new_node = NULL;
struct device *clsdev;
int minor;
int id, ret;
mutex_lock(&dvbdev_register_lock);
id = dvbdev_get_free_id(adap, type);
if (id < 0) {
mutex_unlock(&dvbdev_register_lock);
*pdvbdev = NULL;
pr_err("%s: couldn't find free device id\n", __func__);
return -ENFILE;
}
*pdvbdev = dvbdev = kzalloc(sizeof(*dvbdev), GFP_KERNEL);
if (!dvbdev) {
mutex_unlock(&dvbdev_register_lock);
return -ENOMEM;
}
/*
* When a device of the same type is probe()d more than once,
* the first allocated fops are used. This prevents memory leaks
* that can occur when the same device is probe()d repeatedly.
*/
list_for_each_entry(node, &dvbdevfops_list, list_head) {
if (node->fops->owner == adap->module &&
node->type == type && node->template == template) {
dvbdevfops = node->fops;
break;
}
}
if (!dvbdevfops) {
dvbdevfops = kmemdup(template->fops, sizeof(*dvbdevfops), GFP_KERNEL);
if (!dvbdevfops) {
kfree(dvbdev);
mutex_unlock(&dvbdev_register_lock);
return -ENOMEM;
}
new_node = kzalloc(sizeof(*new_node), GFP_KERNEL);
if (!new_node) {
kfree(dvbdevfops);
kfree(dvbdev);
mutex_unlock(&dvbdev_register_lock);
return -ENOMEM;
}
new_node->fops = dvbdevfops;
new_node->type = type;
new_node->template = template;
list_add_tail(&new_node->list_head, &dvbdevfops_list);
}
memcpy(dvbdev, template, sizeof(struct dvb_device));
kref_init(&dvbdev->ref);
dvbdev->type = type;
dvbdev->id = id;
dvbdev->adapter = adap;
dvbdev->priv = priv;
dvbdev->fops = dvbdevfops;
init_waitqueue_head(&dvbdev->wait_queue);
dvbdevfops->owner = adap->module;
list_add_tail(&dvbdev->list_head, &adap->device_list);
down_write(&minor_rwsem);
#ifdef CONFIG_DVB_DYNAMIC_MINORS
for (minor = 0; minor < MAX_DVB_MINORS; minor++)
if (!dvb_minors[minor])
break;
if (minor == MAX_DVB_MINORS) {
if (new_node) {
list_del(&new_node->list_head);
kfree(dvbdevfops);
kfree(new_node);
}
list_del(&dvbdev->list_head);
kfree(dvbdev);
up_write(&minor_rwsem);
mutex_unlock(&dvbdev_register_lock);
return -EINVAL;
}
#else
minor = nums2minor(adap->num, type, id);
#endif
dvbdev->minor = minor;
dvb_minors[minor] = dvb_device_get(dvbdev);
up_write(&minor_rwsem);
ret = dvb_register_media_device(dvbdev, type, minor, demux_sink_pads);
if (ret) {
pr_err("%s: dvb_register_media_device failed to create the mediagraph\n",
__func__);
if (new_node) {
list_del(&new_node->list_head);
kfree(dvbdevfops);
kfree(new_node);
}
dvb_media_device_free(dvbdev);
list_del(&dvbdev->list_head);
kfree(dvbdev);
mutex_unlock(&dvbdev_register_lock);
return ret;
}
clsdev = device_create(dvb_class, adap->device,
MKDEV(DVB_MAJOR, minor),
dvbdev, "dvb%d.%s%d", adap->num, dnames[type], id);
if (IS_ERR(clsdev)) {
pr_err("%s: failed to create device dvb%d.%s%d (%ld)\n",
__func__, adap->num, dnames[type], id, PTR_ERR(clsdev));
if (new_node) {
list_del(&new_node->list_head);
kfree(dvbdevfops);
kfree(new_node);
}
dvb_media_device_free(dvbdev);
list_del(&dvbdev->list_head);
kfree(dvbdev);
mutex_unlock(&dvbdev_register_lock);
return PTR_ERR(clsdev);
}
dprintk("DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n",
adap->num, dnames[type], id, minor, minor);
mutex_unlock(&dvbdev_register_lock);
return 0;
}
EXPORT_SYMBOL(dvb_register_device);
void dvb_remove_device(struct dvb_device *dvbdev)
{
if (!dvbdev)
return;
down_write(&minor_rwsem);
dvb_minors[dvbdev->minor] = NULL;
dvb_device_put(dvbdev);
up_write(&minor_rwsem);
dvb_media_device_free(dvbdev);
device_destroy(dvb_class, MKDEV(DVB_MAJOR, dvbdev->minor));
list_del(&dvbdev->list_head);
}
EXPORT_SYMBOL(dvb_remove_device);
static void dvb_free_device(struct kref *ref)
{
struct dvb_device *dvbdev = container_of(ref, struct dvb_device, ref);
kfree(dvbdev);
}
struct dvb_device *dvb_device_get(struct dvb_device *dvbdev)
{
kref_get(&dvbdev->ref);
return dvbdev;
}
EXPORT_SYMBOL(dvb_device_get);
void dvb_device_put(struct dvb_device *dvbdev)
{
if (dvbdev)
kref_put(&dvbdev->ref, dvb_free_device);
}
void dvb_unregister_device(struct dvb_device *dvbdev)
{
dvb_remove_device(dvbdev);
dvb_device_put(dvbdev);
}
EXPORT_SYMBOL(dvb_unregister_device);
#ifdef CONFIG_MEDIA_CONTROLLER_DVB
static int dvb_create_io_intf_links(struct dvb_adapter *adap,
struct media_interface *intf,
char *name)
{
struct media_device *mdev = adap->mdev;
struct media_entity *entity;
struct media_link *link;
media_device_for_each_entity(entity, mdev) {
if (entity->function == MEDIA_ENT_F_IO_DTV) {
if (strncmp(entity->name, name, strlen(name)))
continue;
link = media_create_intf_link(entity, intf,
MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
if (!link)
return -ENOMEM;
}
}
return 0;
}
int dvb_create_media_graph(struct dvb_adapter *adap,
bool create_rf_connector)
{
struct media_device *mdev = adap->mdev;
struct media_entity *entity, *tuner = NULL, *demod = NULL, *conn;
struct media_entity *demux = NULL, *ca = NULL;
struct media_link *link;
struct media_interface *intf;
unsigned int demux_pad = 0;
unsigned int dvr_pad = 0;
unsigned int ntuner = 0, ndemod = 0;
int ret, pad_source, pad_sink;
static const char *connector_name = "Television";
if (!mdev)
return 0;
media_device_for_each_entity(entity, mdev) {
switch (entity->function) {
case MEDIA_ENT_F_TUNER:
tuner = entity;
ntuner++;
break;
case MEDIA_ENT_F_DTV_DEMOD:
demod = entity;
ndemod++;
break;
case MEDIA_ENT_F_TS_DEMUX:
demux = entity;
break;
case MEDIA_ENT_F_DTV_CA:
ca = entity;
break;
}
}
/*
* Prepare to signalize to media_create_pad_links() that multiple
* entities of the same type exists and a 1:n or n:1 links need to be
* created.
* NOTE: if both tuner and demod have multiple instances, it is up
* to the caller driver to create such links.
*/
if (ntuner > 1)
tuner = NULL;
if (ndemod > 1)
demod = NULL;
if (create_rf_connector) {
conn = kzalloc(sizeof(*conn), GFP_KERNEL);
if (!conn)
return -ENOMEM;
adap->conn = conn;
adap->conn_pads = kzalloc(sizeof(*adap->conn_pads), GFP_KERNEL);
if (!adap->conn_pads)
return -ENOMEM;
conn->flags = MEDIA_ENT_FL_CONNECTOR;
conn->function = MEDIA_ENT_F_CONN_RF;
conn->name = connector_name;
adap->conn_pads->flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(conn, 1, adap->conn_pads);
if (ret)
return ret;
ret = media_device_register_entity(mdev, conn);
if (ret)
return ret;
if (!ntuner) {
ret = media_create_pad_links(mdev,
MEDIA_ENT_F_CONN_RF,
conn, 0,
MEDIA_ENT_F_DTV_DEMOD,
demod, 0,
MEDIA_LNK_FL_ENABLED,
false);
} else {
pad_sink = media_get_pad_index(tuner, MEDIA_PAD_FL_SINK,
PAD_SIGNAL_ANALOG);
if (pad_sink < 0)
return -EINVAL;
ret = media_create_pad_links(mdev,
MEDIA_ENT_F_CONN_RF,
conn, 0,
MEDIA_ENT_F_TUNER,
tuner, pad_sink,
MEDIA_LNK_FL_ENABLED,
false);
}
if (ret)
return ret;
}
if (ntuner && ndemod) {
/* NOTE: first found tuner source pad presumed correct */
pad_source = media_get_pad_index(tuner, MEDIA_PAD_FL_SOURCE,
PAD_SIGNAL_ANALOG);
if (pad_source < 0)
return -EINVAL;
ret = media_create_pad_links(mdev,
MEDIA_ENT_F_TUNER,
tuner, pad_source,
MEDIA_ENT_F_DTV_DEMOD,
demod, 0, MEDIA_LNK_FL_ENABLED,
false);
if (ret)
return ret;
}
if (ndemod && demux) {
ret = media_create_pad_links(mdev,
MEDIA_ENT_F_DTV_DEMOD,
demod, 1,
MEDIA_ENT_F_TS_DEMUX,
demux, 0, MEDIA_LNK_FL_ENABLED,
false);
if (ret)
return ret;
}
if (demux && ca) {
ret = media_create_pad_link(demux, 1, ca,
0, MEDIA_LNK_FL_ENABLED);
if (ret)
return ret;
}
/* Create demux links for each ringbuffer/pad */
if (demux) {
media_device_for_each_entity(entity, mdev) {
if (entity->function == MEDIA_ENT_F_IO_DTV) {
if (!strncmp(entity->name, DVR_TSOUT,
strlen(DVR_TSOUT))) {
ret = media_create_pad_link(demux,
++dvr_pad,
entity, 0, 0);
if (ret)
return ret;
}
if (!strncmp(entity->name, DEMUX_TSOUT,
strlen(DEMUX_TSOUT))) {
ret = media_create_pad_link(demux,
++demux_pad,
entity, 0, 0);
if (ret)
return ret;
}
}
}
}
/* Create interface links for FE->tuner, DVR->demux and CA->ca */
media_device_for_each_intf(intf, mdev) {
if (intf->type == MEDIA_INTF_T_DVB_CA && ca) {
link = media_create_intf_link(ca, intf,
MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
if (!link)
return -ENOMEM;
}
if (intf->type == MEDIA_INTF_T_DVB_FE && tuner) {
link = media_create_intf_link(tuner, intf,
MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
if (!link)
return -ENOMEM;
}
#if 0
/*
* Indirect link - let's not create yet, as we don't know how
* to handle indirect links, nor if this will
* actually be needed.
*/
if (intf->type == MEDIA_INTF_T_DVB_DVR && demux) {
link = media_create_intf_link(demux, intf,
MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
if (!link)
return -ENOMEM;
}
#endif
if (intf->type == MEDIA_INTF_T_DVB_DVR) {
ret = dvb_create_io_intf_links(adap, intf, DVR_TSOUT);
if (ret)
return ret;
}
if (intf->type == MEDIA_INTF_T_DVB_DEMUX) {
ret = dvb_create_io_intf_links(adap, intf, DEMUX_TSOUT);
if (ret)
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(dvb_create_media_graph);
#endif
static int dvbdev_check_free_adapter_num(int num)
{
struct list_head *entry;
list_for_each(entry, &dvb_adapter_list) {
struct dvb_adapter *adap;
adap = list_entry(entry, struct dvb_adapter, list_head);
if (adap->num == num)
return 0;
}
return 1;
}
static int dvbdev_get_free_adapter_num(void)
{
int num = 0;
while (num < DVB_MAX_ADAPTERS) {
if (dvbdev_check_free_adapter_num(num))
return num;
num++;
}
return -ENFILE;
}
int dvb_register_adapter(struct dvb_adapter *adap, const char *name,
struct module *module, struct device *device,
short *adapter_nums)
{
int i, num;
mutex_lock(&dvbdev_register_lock);
for (i = 0; i < DVB_MAX_ADAPTERS; ++i) {
num = adapter_nums[i];
if (num >= 0 && num < DVB_MAX_ADAPTERS) {
/* use the one the driver asked for */
if (dvbdev_check_free_adapter_num(num))
break;
} else {
num = dvbdev_get_free_adapter_num();
break;
}
num = -1;
}
if (num < 0) {
mutex_unlock(&dvbdev_register_lock);
return -ENFILE;
}
memset(adap, 0, sizeof(struct dvb_adapter));
INIT_LIST_HEAD(&adap->device_list);
pr_info("DVB: registering new adapter (%s)\n", name);
adap->num = num;
adap->name = name;
adap->module = module;
adap->device = device;
adap->mfe_shared = 0;
adap->mfe_dvbdev = NULL;
mutex_init(&adap->mfe_lock);
#ifdef CONFIG_MEDIA_CONTROLLER_DVB
mutex_init(&adap->mdev_lock);
#endif
list_add_tail(&adap->list_head, &dvb_adapter_list);
mutex_unlock(&dvbdev_register_lock);
return num;
}
EXPORT_SYMBOL(dvb_register_adapter);
int dvb_unregister_adapter(struct dvb_adapter *adap)
{
mutex_lock(&dvbdev_register_lock);
list_del(&adap->list_head);
mutex_unlock(&dvbdev_register_lock);
return 0;
}
EXPORT_SYMBOL(dvb_unregister_adapter);
/*
* if the miracle happens and "generic_usercopy()" is included into
* the kernel, then this can vanish. please don't make the mistake and
* define this as video_usercopy(). this will introduce a dependency
* to the v4l "videodev.o" module, which is unnecessary for some
* cards (ie. the budget dvb-cards don't need the v4l module...)
*/
int dvb_usercopy(struct file *file,
unsigned int cmd, unsigned long arg,
int (*func)(struct file *file,
unsigned int cmd, void *arg))
{
char sbuf[128];
void *mbuf = NULL;
void *parg = NULL;
int err = -EINVAL;
/* Copy arguments into temp kernel buffer */
switch (_IOC_DIR(cmd)) {
case _IOC_NONE:
/*
* For this command, the pointer is actually an integer
* argument.
*/
parg = (void *)arg;
break;
case _IOC_READ: /* some v4l ioctls are marked wrong ... */
case _IOC_WRITE:
case (_IOC_WRITE | _IOC_READ):
if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
parg = sbuf;
} else {
/* too big to allocate from stack */
mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
if (!mbuf)
return -ENOMEM;
parg = mbuf;
}
err = -EFAULT;
if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
goto out;
break;
}
/* call driver */
err = func(file, cmd, parg);
if (err == -ENOIOCTLCMD)
err = -ENOTTY;
if (err < 0)
goto out;
/* Copy results into user buffer */
switch (_IOC_DIR(cmd)) {
case _IOC_READ:
case (_IOC_WRITE | _IOC_READ):
if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
err = -EFAULT;
break;
}
out:
kfree(mbuf);
return err;
}
#if IS_ENABLED(CONFIG_I2C)
struct i2c_client *dvb_module_probe(const char *module_name,
const char *name,
struct i2c_adapter *adap,
unsigned char addr,
void *platform_data)
{
struct i2c_client *client;
struct i2c_board_info *board_info;
board_info = kzalloc(sizeof(*board_info), GFP_KERNEL);
if (!board_info)
return NULL;
if (name)
strscpy(board_info->type, name, I2C_NAME_SIZE);
else
strscpy(board_info->type, module_name, I2C_NAME_SIZE);
board_info->addr = addr;
board_info->platform_data = platform_data;
request_module(module_name);
client = i2c_new_client_device(adap, board_info);
if (!i2c_client_has_driver(client)) {
kfree(board_info);
return NULL;
}
if (!try_module_get(client->dev.driver->owner)) {
i2c_unregister_device(client);
client = NULL;
}
kfree(board_info);
return client;
}
EXPORT_SYMBOL_GPL(dvb_module_probe);
void dvb_module_release(struct i2c_client *client)
{
if (!client)
return;
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
EXPORT_SYMBOL_GPL(dvb_module_release);
#endif
static int dvb_uevent(const struct device *dev, struct kobj_uevent_env *env)
{
const struct dvb_device *dvbdev = dev_get_drvdata(dev);
add_uevent_var(env, "DVB_ADAPTER_NUM=%d", dvbdev->adapter->num);
add_uevent_var(env, "DVB_DEVICE_TYPE=%s", dnames[dvbdev->type]);
add_uevent_var(env, "DVB_DEVICE_NUM=%d", dvbdev->id);
return 0;
}
static char *dvb_devnode(const struct device *dev, umode_t *mode)
{
const struct dvb_device *dvbdev = dev_get_drvdata(dev);
return kasprintf(GFP_KERNEL, "dvb/adapter%d/%s%d",
dvbdev->adapter->num, dnames[dvbdev->type], dvbdev->id);
}
static int __init init_dvbdev(void)
{
int retval;
dev_t dev = MKDEV(DVB_MAJOR, 0);
retval = register_chrdev_region(dev, MAX_DVB_MINORS, "DVB");
if (retval != 0) {
pr_err("dvb-core: unable to get major %d\n", DVB_MAJOR);
return retval;
}
cdev_init(&dvb_device_cdev, &dvb_device_fops);
retval = cdev_add(&dvb_device_cdev, dev, MAX_DVB_MINORS);
if (retval != 0) {
pr_err("dvb-core: unable register character device\n");
goto error;
}
dvb_class = class_create("dvb");
if (IS_ERR(dvb_class)) {
retval = PTR_ERR(dvb_class);
goto error;
}
dvb_class->dev_uevent = dvb_uevent;
dvb_class->devnode = dvb_devnode;
return 0;
error:
cdev_del(&dvb_device_cdev);
unregister_chrdev_region(dev, MAX_DVB_MINORS);
return retval;
}
static void __exit exit_dvbdev(void)
{
struct dvbdevfops_node *node, *next;
class_destroy(dvb_class);
cdev_del(&dvb_device_cdev);
unregister_chrdev_region(MKDEV(DVB_MAJOR, 0), MAX_DVB_MINORS);
list_for_each_entry_safe(node, next, &dvbdevfops_list, list_head) {
list_del(&node->list_head);
kfree(node->fops);
kfree(node);
}
}
subsys_initcall(init_dvbdev);
module_exit(exit_dvbdev);
MODULE_DESCRIPTION("DVB Core Driver");
MODULE_AUTHOR("Marcus Metzler, Ralph Metzler, Holger Waechtler");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-core/dvbdev.c |
/*
*
* dvb_ringbuffer.c: ring buffer implementation for the dvb driver
*
* Copyright (C) 2003 Oliver Endriss
* Copyright (C) 2004 Andrew de Quincey
*
* based on code originally found in av7110.c & dvb_ci.c:
* Copyright (C) 1999-2003 Ralph Metzler
* & Marcus Metzler for convergence integrated media GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public License
* as published by the Free Software Foundation; either version 2.1
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <media/dvb_ringbuffer.h>
#define PKT_READY 0
#define PKT_DISPOSED 1
void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len)
{
rbuf->pread=rbuf->pwrite=0;
rbuf->data=data;
rbuf->size=len;
rbuf->error=0;
init_waitqueue_head(&rbuf->queue);
spin_lock_init(&(rbuf->lock));
}
int dvb_ringbuffer_empty(struct dvb_ringbuffer *rbuf)
{
/* smp_load_acquire() to load write pointer on reader side
* this pairs with smp_store_release() in dvb_ringbuffer_write(),
* dvb_ringbuffer_write_user(), or dvb_ringbuffer_reset()
*
* for memory barriers also see Documentation/core-api/circular-buffers.rst
*/
return (rbuf->pread == smp_load_acquire(&rbuf->pwrite));
}
ssize_t dvb_ringbuffer_free(struct dvb_ringbuffer *rbuf)
{
ssize_t free;
/* READ_ONCE() to load read pointer on writer side
* this pairs with smp_store_release() in dvb_ringbuffer_read(),
* dvb_ringbuffer_read_user(), dvb_ringbuffer_flush(),
* or dvb_ringbuffer_reset()
*/
free = READ_ONCE(rbuf->pread) - rbuf->pwrite;
if (free <= 0)
free += rbuf->size;
return free-1;
}
ssize_t dvb_ringbuffer_avail(struct dvb_ringbuffer *rbuf)
{
ssize_t avail;
/* smp_load_acquire() to load write pointer on reader side
* this pairs with smp_store_release() in dvb_ringbuffer_write(),
* dvb_ringbuffer_write_user(), or dvb_ringbuffer_reset()
*/
avail = smp_load_acquire(&rbuf->pwrite) - rbuf->pread;
if (avail < 0)
avail += rbuf->size;
return avail;
}
void dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf)
{
/* dvb_ringbuffer_flush() counts as read operation
* smp_load_acquire() to load write pointer
* smp_store_release() to update read pointer, this ensures that the
* correct pointer is visible for subsequent dvb_ringbuffer_free()
* calls on other cpu cores
*/
smp_store_release(&rbuf->pread, smp_load_acquire(&rbuf->pwrite));
rbuf->error = 0;
}
EXPORT_SYMBOL(dvb_ringbuffer_flush);
void dvb_ringbuffer_reset(struct dvb_ringbuffer *rbuf)
{
/* dvb_ringbuffer_reset() counts as read and write operation
* smp_store_release() to update read pointer
*/
smp_store_release(&rbuf->pread, 0);
/* smp_store_release() to update write pointer */
smp_store_release(&rbuf->pwrite, 0);
rbuf->error = 0;
}
void dvb_ringbuffer_flush_spinlock_wakeup(struct dvb_ringbuffer *rbuf)
{
unsigned long flags;
spin_lock_irqsave(&rbuf->lock, flags);
dvb_ringbuffer_flush(rbuf);
spin_unlock_irqrestore(&rbuf->lock, flags);
wake_up(&rbuf->queue);
}
ssize_t dvb_ringbuffer_read_user(struct dvb_ringbuffer *rbuf, u8 __user *buf, size_t len)
{
size_t todo = len;
size_t split;
split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0;
if (split > 0) {
if (copy_to_user(buf, rbuf->data+rbuf->pread, split))
return -EFAULT;
buf += split;
todo -= split;
/* smp_store_release() for read pointer update to ensure
* that buf is not overwritten until read is complete,
* this pairs with READ_ONCE() in dvb_ringbuffer_free()
*/
smp_store_release(&rbuf->pread, 0);
}
if (copy_to_user(buf, rbuf->data+rbuf->pread, todo))
return -EFAULT;
/* smp_store_release() to update read pointer, see above */
smp_store_release(&rbuf->pread, (rbuf->pread + todo) % rbuf->size);
return len;
}
void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, u8 *buf, size_t len)
{
size_t todo = len;
size_t split;
split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0;
if (split > 0) {
memcpy(buf, rbuf->data+rbuf->pread, split);
buf += split;
todo -= split;
/* smp_store_release() for read pointer update to ensure
* that buf is not overwritten until read is complete,
* this pairs with READ_ONCE() in dvb_ringbuffer_free()
*/
smp_store_release(&rbuf->pread, 0);
}
memcpy(buf, rbuf->data+rbuf->pread, todo);
/* smp_store_release() to update read pointer, see above */
smp_store_release(&rbuf->pread, (rbuf->pread + todo) % rbuf->size);
}
ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, size_t len)
{
size_t todo = len;
size_t split;
split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0;
if (split > 0) {
memcpy(rbuf->data+rbuf->pwrite, buf, split);
buf += split;
todo -= split;
/* smp_store_release() for write pointer update to ensure that
* written data is visible on other cpu cores before the pointer
* update, this pairs with smp_load_acquire() in
* dvb_ringbuffer_empty() or dvb_ringbuffer_avail()
*/
smp_store_release(&rbuf->pwrite, 0);
}
memcpy(rbuf->data+rbuf->pwrite, buf, todo);
/* smp_store_release() for write pointer update, see above */
smp_store_release(&rbuf->pwrite, (rbuf->pwrite + todo) % rbuf->size);
return len;
}
ssize_t dvb_ringbuffer_write_user(struct dvb_ringbuffer *rbuf,
const u8 __user *buf, size_t len)
{
int status;
size_t todo = len;
size_t split;
split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0;
if (split > 0) {
status = copy_from_user(rbuf->data+rbuf->pwrite, buf, split);
if (status)
return len - todo;
buf += split;
todo -= split;
/* smp_store_release() for write pointer update to ensure that
* written data is visible on other cpu cores before the pointer
* update, this pairs with smp_load_acquire() in
* dvb_ringbuffer_empty() or dvb_ringbuffer_avail()
*/
smp_store_release(&rbuf->pwrite, 0);
}
status = copy_from_user(rbuf->data+rbuf->pwrite, buf, todo);
if (status)
return len - todo;
/* smp_store_release() for write pointer update, see above */
smp_store_release(&rbuf->pwrite, (rbuf->pwrite + todo) % rbuf->size);
return len;
}
ssize_t dvb_ringbuffer_pkt_write(struct dvb_ringbuffer *rbuf, u8* buf, size_t len)
{
int status;
ssize_t oldpwrite = rbuf->pwrite;
DVB_RINGBUFFER_WRITE_BYTE(rbuf, len >> 8);
DVB_RINGBUFFER_WRITE_BYTE(rbuf, len & 0xff);
DVB_RINGBUFFER_WRITE_BYTE(rbuf, PKT_READY);
status = dvb_ringbuffer_write(rbuf, buf, len);
if (status < 0) rbuf->pwrite = oldpwrite;
return status;
}
ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx,
int offset, u8 __user *buf, size_t len)
{
size_t todo;
size_t split;
size_t pktlen;
pktlen = rbuf->data[idx] << 8;
pktlen |= rbuf->data[(idx + 1) % rbuf->size];
if (offset > pktlen) return -EINVAL;
if ((offset + len) > pktlen) len = pktlen - offset;
idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size;
todo = len;
split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0;
if (split > 0) {
if (copy_to_user(buf, rbuf->data+idx, split))
return -EFAULT;
buf += split;
todo -= split;
idx = 0;
}
if (copy_to_user(buf, rbuf->data+idx, todo))
return -EFAULT;
return len;
}
ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx,
int offset, u8* buf, size_t len)
{
size_t todo;
size_t split;
size_t pktlen;
pktlen = rbuf->data[idx] << 8;
pktlen |= rbuf->data[(idx + 1) % rbuf->size];
if (offset > pktlen) return -EINVAL;
if ((offset + len) > pktlen) len = pktlen - offset;
idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size;
todo = len;
split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0;
if (split > 0) {
memcpy(buf, rbuf->data+idx, split);
buf += split;
todo -= split;
idx = 0;
}
memcpy(buf, rbuf->data+idx, todo);
return len;
}
void dvb_ringbuffer_pkt_dispose(struct dvb_ringbuffer *rbuf, size_t idx)
{
size_t pktlen;
rbuf->data[(idx + 2) % rbuf->size] = PKT_DISPOSED;
// clean up disposed packets
while(dvb_ringbuffer_avail(rbuf) > DVB_RINGBUFFER_PKTHDRSIZE) {
if (DVB_RINGBUFFER_PEEK(rbuf, 2) == PKT_DISPOSED) {
pktlen = DVB_RINGBUFFER_PEEK(rbuf, 0) << 8;
pktlen |= DVB_RINGBUFFER_PEEK(rbuf, 1);
DVB_RINGBUFFER_SKIP(rbuf, pktlen + DVB_RINGBUFFER_PKTHDRSIZE);
} else {
// first packet is not disposed, so we stop cleaning now
break;
}
}
}
ssize_t dvb_ringbuffer_pkt_next(struct dvb_ringbuffer *rbuf, size_t idx, size_t* pktlen)
{
int consumed;
int curpktlen;
int curpktstatus;
if (idx == -1) {
idx = rbuf->pread;
} else {
curpktlen = rbuf->data[idx] << 8;
curpktlen |= rbuf->data[(idx + 1) % rbuf->size];
idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size;
}
consumed = (idx - rbuf->pread);
if (consumed < 0)
consumed += rbuf->size;
while((dvb_ringbuffer_avail(rbuf) - consumed) > DVB_RINGBUFFER_PKTHDRSIZE) {
curpktlen = rbuf->data[idx] << 8;
curpktlen |= rbuf->data[(idx + 1) % rbuf->size];
curpktstatus = rbuf->data[(idx + 2) % rbuf->size];
if (curpktstatus == PKT_READY) {
*pktlen = curpktlen;
return idx;
}
consumed += curpktlen + DVB_RINGBUFFER_PKTHDRSIZE;
idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size;
}
// no packets available
return -1;
}
EXPORT_SYMBOL(dvb_ringbuffer_init);
EXPORT_SYMBOL(dvb_ringbuffer_empty);
EXPORT_SYMBOL(dvb_ringbuffer_free);
EXPORT_SYMBOL(dvb_ringbuffer_avail);
EXPORT_SYMBOL(dvb_ringbuffer_flush_spinlock_wakeup);
EXPORT_SYMBOL(dvb_ringbuffer_read_user);
EXPORT_SYMBOL(dvb_ringbuffer_read);
EXPORT_SYMBOL(dvb_ringbuffer_write);
EXPORT_SYMBOL(dvb_ringbuffer_write_user);
| linux-master | drivers/media/dvb-core/dvb_ringbuffer.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Zarlink ZL10039 DVB-S tuner
*
* Copyright 2007 Jan D. Louw <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/dvb/frontend.h>
#include <media/dvb_frontend.h>
#include "zl10039.h"
static int debug;
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG args); \
} while (0)
enum zl10039_model_id {
ID_ZL10039 = 1
};
struct zl10039_state {
struct i2c_adapter *i2c;
u8 i2c_addr;
u8 id;
};
enum zl10039_reg_addr {
PLL0 = 0,
PLL1,
PLL2,
PLL3,
RFFE,
BASE0,
BASE1,
BASE2,
LO0,
LO1,
LO2,
LO3,
LO4,
LO5,
LO6,
GENERAL
};
static int zl10039_read(const struct zl10039_state *state,
const enum zl10039_reg_addr reg, u8 *buf,
const size_t count)
{
u8 regbuf[] = { reg };
struct i2c_msg msg[] = {
{/* Write register address */
.addr = state->i2c_addr,
.flags = 0,
.buf = regbuf,
.len = 1,
}, {/* Read count bytes */
.addr = state->i2c_addr,
.flags = I2C_M_RD,
.buf = buf,
.len = count,
},
};
dprintk("%s\n", __func__);
if (i2c_transfer(state->i2c, msg, 2) != 2) {
dprintk("%s: i2c read error\n", __func__);
return -EREMOTEIO;
}
return 0; /* Success */
}
static int zl10039_write(struct zl10039_state *state,
const enum zl10039_reg_addr reg, const u8 *src,
const size_t count)
{
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = state->i2c_addr,
.flags = 0,
.buf = buf,
.len = count + 1,
};
if (1 + count > sizeof(buf)) {
printk(KERN_WARNING
"%s: i2c wr reg=%04x: len=%zu is too big!\n",
KBUILD_MODNAME, reg, count);
return -EINVAL;
}
dprintk("%s\n", __func__);
/* Write register address and data in one go */
buf[0] = reg;
memcpy(&buf[1], src, count);
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
dprintk("%s: i2c write error\n", __func__);
return -EREMOTEIO;
}
return 0; /* Success */
}
static inline int zl10039_readreg(struct zl10039_state *state,
const enum zl10039_reg_addr reg, u8 *val)
{
return zl10039_read(state, reg, val, 1);
}
static inline int zl10039_writereg(struct zl10039_state *state,
const enum zl10039_reg_addr reg,
const u8 val)
{
const u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return zl10039_write(state, reg, &tmp, 1);
}
static int zl10039_init(struct dvb_frontend *fe)
{
struct zl10039_state *state = fe->tuner_priv;
int ret;
dprintk("%s\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* Reset logic */
ret = zl10039_writereg(state, GENERAL, 0x40);
if (ret < 0) {
dprintk("Note: i2c write error normal when resetting the tuner\n");
}
/* Wake up */
ret = zl10039_writereg(state, GENERAL, 0x01);
if (ret < 0) {
dprintk("Tuner power up failed\n");
return ret;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int zl10039_sleep(struct dvb_frontend *fe)
{
struct zl10039_state *state = fe->tuner_priv;
int ret;
dprintk("%s\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = zl10039_writereg(state, GENERAL, 0x80);
if (ret < 0) {
dprintk("Tuner sleep failed\n");
return ret;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int zl10039_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct zl10039_state *state = fe->tuner_priv;
u8 buf[6];
u8 bf;
u32 fbw;
u32 div;
int ret;
dprintk("%s\n", __func__);
dprintk("Set frequency = %d, symbol rate = %d\n",
c->frequency, c->symbol_rate);
/* Assumed 10.111 MHz crystal oscillator */
/* Cancelled num/den 80 to prevent overflow */
div = (c->frequency * 1000) / 126387;
fbw = (c->symbol_rate * 27) / 32000;
/* Cancelled num/den 10 to prevent overflow */
bf = ((fbw * 5088) / 1011100) - 1;
/*PLL divider*/
buf[0] = (div >> 8) & 0x7f;
buf[1] = (div >> 0) & 0xff;
/*Reference divider*/
/* Select reference ratio of 80 */
buf[2] = 0x1D;
/*PLL test modes*/
buf[3] = 0x40;
/*RF Control register*/
buf[4] = 0x6E; /* Bypass enable */
/*Baseband filter cutoff */
buf[5] = bf;
/* Open i2c gate */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* BR = 10, Enable filter adjustment */
ret = zl10039_writereg(state, BASE1, 0x0A);
if (ret < 0)
goto error;
/* Write new config values */
ret = zl10039_write(state, PLL0, buf, sizeof(buf));
if (ret < 0)
goto error;
/* BR = 10, Disable filter adjustment */
ret = zl10039_writereg(state, BASE1, 0x6A);
if (ret < 0)
goto error;
/* Close i2c gate */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
error:
dprintk("Error setting tuner\n");
return ret;
}
static void zl10039_release(struct dvb_frontend *fe)
{
struct zl10039_state *state = fe->tuner_priv;
dprintk("%s\n", __func__);
kfree(state);
fe->tuner_priv = NULL;
}
static const struct dvb_tuner_ops zl10039_ops = {
.release = zl10039_release,
.init = zl10039_init,
.sleep = zl10039_sleep,
.set_params = zl10039_set_params,
};
struct dvb_frontend *zl10039_attach(struct dvb_frontend *fe,
u8 i2c_addr, struct i2c_adapter *i2c)
{
struct zl10039_state *state = NULL;
dprintk("%s\n", __func__);
state = kmalloc(sizeof(struct zl10039_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->i2c = i2c;
state->i2c_addr = i2c_addr;
/* Open i2c gate */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* check if this is a valid tuner */
if (zl10039_readreg(state, GENERAL, &state->id) < 0) {
/* Close i2c gate */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
goto error;
}
/* Close i2c gate */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
state->id = state->id & 0x0f;
switch (state->id) {
case ID_ZL10039:
strscpy(fe->ops.tuner_ops.info.name,
"Zarlink ZL10039 DVB-S tuner",
sizeof(fe->ops.tuner_ops.info.name));
break;
default:
dprintk("Chip ID=%x does not match a known type\n", state->id);
goto error;
}
memcpy(&fe->ops.tuner_ops, &zl10039_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = state;
dprintk("Tuner attached @ i2c address 0x%02x\n", i2c_addr);
return fe;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(zl10039_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Zarlink ZL10039 DVB-S tuner driver");
MODULE_AUTHOR("Jan D. Louw <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/zl10039.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Realtek RTL2832U SDR driver
*
* Copyright (C) 2013 Antti Palosaari <[email protected]>
*
* GNU Radio plugin "gr-kernel" for device usage will be on:
* https://git.linuxtv.org/anttip/gr-kernel.git
*/
#include "rtl2832_sdr.h"
#include "dvb_usb.h"
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-vmalloc.h>
#include <linux/platform_device.h>
#include <linux/jiffies.h>
#include <linux/math64.h>
#include <linux/regmap.h>
static bool rtl2832_sdr_emulated_fmt;
module_param_named(emulated_formats, rtl2832_sdr_emulated_fmt, bool, 0644);
MODULE_PARM_DESC(emulated_formats, "enable emulated formats (disappears in future)");
/* Original macro does not contain enough null pointer checks for our need */
#define V4L2_SUBDEV_HAS_OP(sd, o, f) \
((sd) && (sd)->ops && (sd)->ops->o && (sd)->ops->o->f)
#define MAX_BULK_BUFS (10)
#define BULK_BUFFER_SIZE (128 * 512)
static const struct v4l2_frequency_band bands_adc[] = {
{
.tuner = 0,
.type = V4L2_TUNER_ADC,
.index = 0,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 300000,
.rangehigh = 300000,
},
{
.tuner = 0,
.type = V4L2_TUNER_ADC,
.index = 1,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 900001,
.rangehigh = 2800000,
},
{
.tuner = 0,
.type = V4L2_TUNER_ADC,
.index = 2,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 3200000,
.rangehigh = 3200000,
},
};
static const struct v4l2_frequency_band bands_fm[] = {
{
.tuner = 1,
.type = V4L2_TUNER_RF,
.index = 0,
.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
.rangelow = 50000000,
.rangehigh = 2000000000,
},
};
/* stream formats */
struct rtl2832_sdr_format {
char *name;
u32 pixelformat;
u32 buffersize;
};
static struct rtl2832_sdr_format formats[] = {
{
.pixelformat = V4L2_SDR_FMT_CU8,
.buffersize = BULK_BUFFER_SIZE,
}, {
.pixelformat = V4L2_SDR_FMT_CU16LE,
.buffersize = BULK_BUFFER_SIZE * 2,
},
};
static const unsigned int NUM_FORMATS = ARRAY_SIZE(formats);
/* intermediate buffers with raw data from the USB device */
struct rtl2832_sdr_frame_buf {
/* common v4l buffer stuff -- must be first */
struct vb2_v4l2_buffer vb;
struct list_head list;
};
struct rtl2832_sdr_dev {
#define POWER_ON 0 /* BIT(0) */
#define URB_BUF 1 /* BIT(1) */
unsigned long flags;
struct platform_device *pdev;
struct regmap *regmap;
struct video_device vdev;
struct v4l2_device v4l2_dev;
struct v4l2_subdev *v4l2_subdev;
/* videobuf2 queue and queued buffers list */
struct vb2_queue vb_queue;
struct list_head queued_bufs;
spinlock_t queued_bufs_lock; /* Protects queued_bufs */
unsigned sequence; /* buffer sequence counter */
/* Note if taking both locks v4l2_lock must always be locked first! */
struct mutex v4l2_lock; /* Protects everything else */
struct mutex vb_queue_lock; /* Protects vb_queue and capt_file */
/* Pointer to our usb_device, will be NULL after unplug */
struct usb_device *udev; /* Both mutexes most be hold when setting! */
unsigned int vb_full; /* vb is full and packets dropped */
struct urb *urb_list[MAX_BULK_BUFS];
int buf_num;
unsigned long buf_size;
u8 *buf_list[MAX_BULK_BUFS];
dma_addr_t dma_addr[MAX_BULK_BUFS];
int urbs_initialized;
int urbs_submitted;
unsigned int f_adc, f_tuner;
u32 pixelformat;
u32 buffersize;
unsigned int num_formats;
/* Controls */
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *bandwidth_auto;
struct v4l2_ctrl *bandwidth;
/* for sample rate calc */
unsigned int sample;
unsigned int sample_measured;
unsigned long jiffies_next;
};
/* Private functions */
static struct rtl2832_sdr_frame_buf *rtl2832_sdr_get_next_fill_buf(
struct rtl2832_sdr_dev *dev)
{
unsigned long flags;
struct rtl2832_sdr_frame_buf *buf = NULL;
spin_lock_irqsave(&dev->queued_bufs_lock, flags);
if (list_empty(&dev->queued_bufs))
goto leave;
buf = list_entry(dev->queued_bufs.next,
struct rtl2832_sdr_frame_buf, list);
list_del(&buf->list);
leave:
spin_unlock_irqrestore(&dev->queued_bufs_lock, flags);
return buf;
}
static unsigned int rtl2832_sdr_convert_stream(struct rtl2832_sdr_dev *dev,
void *dst, const u8 *src, unsigned int src_len)
{
struct platform_device *pdev = dev->pdev;
unsigned int dst_len;
if (dev->pixelformat == V4L2_SDR_FMT_CU8) {
/* native stream, no need to convert */
memcpy(dst, src, src_len);
dst_len = src_len;
} else if (dev->pixelformat == V4L2_SDR_FMT_CU16LE) {
/* convert u8 to u16 */
unsigned int i;
u16 *u16dst = dst;
for (i = 0; i < src_len; i++)
*u16dst++ = (src[i] << 8) | (src[i] >> 0);
dst_len = 2 * src_len;
} else {
dst_len = 0;
}
/* calculate sample rate and output it in 10 seconds intervals */
if (unlikely(time_is_before_jiffies(dev->jiffies_next))) {
#define MSECS 10000UL
unsigned int msecs = jiffies_to_msecs(jiffies -
dev->jiffies_next + msecs_to_jiffies(MSECS));
unsigned int samples = dev->sample - dev->sample_measured;
dev->jiffies_next = jiffies + msecs_to_jiffies(MSECS);
dev->sample_measured = dev->sample;
dev_dbg(&pdev->dev,
"slen=%u samples=%u msecs=%u sample rate=%lu\n",
src_len, samples, msecs, samples * 1000UL / msecs);
}
/* total number of I+Q pairs */
dev->sample += src_len / 2;
return dst_len;
}
/*
* This gets called for the bulk stream pipe. This is done in interrupt
* time, so it has to be fast, not crash, and not stall. Neat.
*/
static void rtl2832_sdr_urb_complete(struct urb *urb)
{
struct rtl2832_sdr_dev *dev = urb->context;
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_frame_buf *fbuf;
dev_dbg_ratelimited(&pdev->dev, "status=%d length=%d/%d errors=%d\n",
urb->status, urb->actual_length,
urb->transfer_buffer_length, urb->error_count);
switch (urb->status) {
case 0: /* success */
case -ETIMEDOUT: /* NAK */
break;
case -ECONNRESET: /* kill */
case -ENOENT:
case -ESHUTDOWN:
return;
default: /* error */
dev_err_ratelimited(&pdev->dev, "urb failed=%d\n", urb->status);
break;
}
if (likely(urb->actual_length > 0)) {
void *ptr;
unsigned int len;
/* get free framebuffer */
fbuf = rtl2832_sdr_get_next_fill_buf(dev);
if (unlikely(fbuf == NULL)) {
dev->vb_full++;
dev_notice_ratelimited(&pdev->dev,
"video buffer is full, %d packets dropped\n",
dev->vb_full);
goto skip;
}
/* fill framebuffer */
ptr = vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0);
len = rtl2832_sdr_convert_stream(dev, ptr, urb->transfer_buffer,
urb->actual_length);
vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, len);
fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
fbuf->vb.sequence = dev->sequence++;
vb2_buffer_done(&fbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
skip:
usb_submit_urb(urb, GFP_ATOMIC);
}
static int rtl2832_sdr_kill_urbs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
int i;
for (i = dev->urbs_submitted - 1; i >= 0; i--) {
dev_dbg(&pdev->dev, "kill urb=%d\n", i);
/* stop the URB */
usb_kill_urb(dev->urb_list[i]);
}
dev->urbs_submitted = 0;
return 0;
}
static int rtl2832_sdr_submit_urbs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
int i, ret;
for (i = 0; i < dev->urbs_initialized; i++) {
dev_dbg(&pdev->dev, "submit urb=%d\n", i);
ret = usb_submit_urb(dev->urb_list[i], GFP_KERNEL);
if (ret) {
dev_err(&pdev->dev,
"Could not submit urb no. %d - get them all back\n",
i);
rtl2832_sdr_kill_urbs(dev);
return ret;
}
dev->urbs_submitted++;
}
return 0;
}
static int rtl2832_sdr_free_stream_bufs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
if (test_bit(URB_BUF, &dev->flags)) {
while (dev->buf_num) {
dev->buf_num--;
dev_dbg(&pdev->dev, "free buf=%d\n", dev->buf_num);
usb_free_coherent(dev->udev, dev->buf_size,
dev->buf_list[dev->buf_num],
dev->dma_addr[dev->buf_num]);
}
}
clear_bit(URB_BUF, &dev->flags);
return 0;
}
static int rtl2832_sdr_alloc_stream_bufs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
dev->buf_num = 0;
dev->buf_size = BULK_BUFFER_SIZE;
dev_dbg(&pdev->dev, "all in all I will use %u bytes for streaming\n",
MAX_BULK_BUFS * BULK_BUFFER_SIZE);
for (dev->buf_num = 0; dev->buf_num < MAX_BULK_BUFS; dev->buf_num++) {
dev->buf_list[dev->buf_num] = usb_alloc_coherent(dev->udev,
BULK_BUFFER_SIZE, GFP_KERNEL,
&dev->dma_addr[dev->buf_num]);
if (!dev->buf_list[dev->buf_num]) {
dev_dbg(&pdev->dev, "alloc buf=%d failed\n",
dev->buf_num);
rtl2832_sdr_free_stream_bufs(dev);
return -ENOMEM;
}
dev_dbg(&pdev->dev, "alloc buf=%d %p (dma %llu)\n",
dev->buf_num, dev->buf_list[dev->buf_num],
(long long)dev->dma_addr[dev->buf_num]);
set_bit(URB_BUF, &dev->flags);
}
return 0;
}
static int rtl2832_sdr_free_urbs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
int i;
rtl2832_sdr_kill_urbs(dev);
for (i = dev->urbs_initialized - 1; i >= 0; i--) {
if (dev->urb_list[i]) {
dev_dbg(&pdev->dev, "free urb=%d\n", i);
/* free the URBs */
usb_free_urb(dev->urb_list[i]);
}
}
dev->urbs_initialized = 0;
return 0;
}
static int rtl2832_sdr_alloc_urbs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
int i, j;
/* allocate the URBs */
for (i = 0; i < MAX_BULK_BUFS; i++) {
dev_dbg(&pdev->dev, "alloc urb=%d\n", i);
dev->urb_list[i] = usb_alloc_urb(0, GFP_KERNEL);
if (!dev->urb_list[i]) {
for (j = 0; j < i; j++) {
usb_free_urb(dev->urb_list[j]);
dev->urb_list[j] = NULL;
}
dev->urbs_initialized = 0;
return -ENOMEM;
}
usb_fill_bulk_urb(dev->urb_list[i],
dev->udev,
usb_rcvbulkpipe(dev->udev, 0x81),
dev->buf_list[i],
BULK_BUFFER_SIZE,
rtl2832_sdr_urb_complete, dev);
dev->urb_list[i]->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
dev->urb_list[i]->transfer_dma = dev->dma_addr[i];
dev->urbs_initialized++;
}
return 0;
}
/* Must be called with vb_queue_lock hold */
static void rtl2832_sdr_cleanup_queued_bufs(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
unsigned long flags;
dev_dbg(&pdev->dev, "\n");
spin_lock_irqsave(&dev->queued_bufs_lock, flags);
while (!list_empty(&dev->queued_bufs)) {
struct rtl2832_sdr_frame_buf *buf;
buf = list_entry(dev->queued_bufs.next,
struct rtl2832_sdr_frame_buf, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->queued_bufs_lock, flags);
}
static int rtl2832_sdr_querycap(struct file *file, void *fh,
struct v4l2_capability *cap)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "\n");
strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
strscpy(cap->card, dev->vdev.name, sizeof(cap->card));
usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info));
return 0;
}
/* Videobuf2 operations */
static int rtl2832_sdr_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers,
unsigned int *nplanes, unsigned int sizes[], struct device *alloc_devs[])
{
struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vq);
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "nbuffers=%d\n", *nbuffers);
/* Need at least 8 buffers */
if (vq->num_buffers + *nbuffers < 8)
*nbuffers = 8 - vq->num_buffers;
*nplanes = 1;
sizes[0] = PAGE_ALIGN(dev->buffersize);
dev_dbg(&pdev->dev, "nbuffers=%d sizes[0]=%d\n", *nbuffers, sizes[0]);
return 0;
}
static int rtl2832_sdr_buf_prepare(struct vb2_buffer *vb)
{
struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
/* Don't allow queueing new buffers after device disconnection */
if (!dev->udev)
return -ENODEV;
return 0;
}
static void rtl2832_sdr_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
struct rtl2832_sdr_frame_buf *buf =
container_of(vbuf, struct rtl2832_sdr_frame_buf, vb);
unsigned long flags;
/* Check the device has not disconnected between prep and queuing */
if (!dev->udev) {
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
return;
}
spin_lock_irqsave(&dev->queued_bufs_lock, flags);
list_add_tail(&buf->list, &dev->queued_bufs);
spin_unlock_irqrestore(&dev->queued_bufs_lock, flags);
}
static int rtl2832_sdr_set_adc(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
int ret;
unsigned int f_sr, f_if;
u8 buf[4], u8tmp1, u8tmp2;
u64 u64tmp;
u32 u32tmp;
dev_dbg(&pdev->dev, "f_adc=%u\n", dev->f_adc);
if (!test_bit(POWER_ON, &dev->flags))
return 0;
if (dev->f_adc == 0)
return 0;
f_sr = dev->f_adc;
ret = regmap_bulk_write(dev->regmap, 0x13e, "\x00\x00", 2);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x115, "\x00\x00\x00\x00", 4);
if (ret)
goto err;
/* get IF from tuner */
if (fe->ops.tuner_ops.get_if_frequency)
ret = fe->ops.tuner_ops.get_if_frequency(fe, &f_if);
else
ret = -EINVAL;
if (ret)
goto err;
/* program IF */
u64tmp = f_if % pdata->clk;
u64tmp *= 0x400000;
u64tmp = div_u64(u64tmp, pdata->clk);
u64tmp = -u64tmp;
u32tmp = u64tmp & 0x3fffff;
dev_dbg(&pdev->dev, "f_if=%u if_ctl=%08x\n", f_if, u32tmp);
buf[0] = (u32tmp >> 16) & 0xff;
buf[1] = (u32tmp >> 8) & 0xff;
buf[2] = (u32tmp >> 0) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x119, buf, 3);
if (ret)
goto err;
/* BB / IF mode */
/* POR: 0x1b1=0x1f, 0x008=0x0d, 0x006=0x80 */
if (f_if) {
u8tmp1 = 0x1a; /* disable Zero-IF */
u8tmp2 = 0x8d; /* enable ADC I */
} else {
u8tmp1 = 0x1b; /* enable Zero-IF, DC, IQ */
u8tmp2 = 0xcd; /* enable ADC I, ADC Q */
}
ret = regmap_write(dev->regmap, 0x1b1, u8tmp1);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x008, u8tmp2);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x006, 0x80);
if (ret)
goto err;
/* program sampling rate (resampling down) */
u32tmp = div_u64(pdata->clk * 0x400000ULL, f_sr * 4U);
u32tmp <<= 2;
buf[0] = (u32tmp >> 24) & 0xff;
buf[1] = (u32tmp >> 16) & 0xff;
buf[2] = (u32tmp >> 8) & 0xff;
buf[3] = (u32tmp >> 0) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x19f, buf, 4);
if (ret)
goto err;
/* low-pass filter */
ret = regmap_bulk_write(dev->regmap, 0x11c,
"\xca\xdc\xd7\xd8\xe0\xf2\x0e\x35\x06\x50\x9c\x0d\x71\x11\x14\x71\x74\x19\x41\xa5",
20);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x017, "\x11\x10", 2);
if (ret)
goto err;
/* mode */
ret = regmap_write(dev->regmap, 0x019, 0x05);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x01a,
"\x1b\x16\x0d\x06\x01\xff", 6);
if (ret)
goto err;
/* FSM */
ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\xf0\x0f", 3);
if (ret)
goto err;
/* PID filter */
ret = regmap_write(dev->regmap, 0x061, 0x60);
if (ret)
goto err;
/* used RF tuner based settings */
switch (pdata->tuner) {
case RTL2832_SDR_TUNER_E4000:
ret = regmap_write(dev->regmap, 0x112, 0x5a);
ret = regmap_write(dev->regmap, 0x102, 0x40);
ret = regmap_write(dev->regmap, 0x103, 0x5a);
ret = regmap_write(dev->regmap, 0x1c7, 0x30);
ret = regmap_write(dev->regmap, 0x104, 0xd0);
ret = regmap_write(dev->regmap, 0x105, 0xbe);
ret = regmap_write(dev->regmap, 0x1c8, 0x18);
ret = regmap_write(dev->regmap, 0x106, 0x35);
ret = regmap_write(dev->regmap, 0x1c9, 0x21);
ret = regmap_write(dev->regmap, 0x1ca, 0x21);
ret = regmap_write(dev->regmap, 0x1cb, 0x00);
ret = regmap_write(dev->regmap, 0x107, 0x40);
ret = regmap_write(dev->regmap, 0x1cd, 0x10);
ret = regmap_write(dev->regmap, 0x1ce, 0x10);
ret = regmap_write(dev->regmap, 0x108, 0x80);
ret = regmap_write(dev->regmap, 0x109, 0x7f);
ret = regmap_write(dev->regmap, 0x10a, 0x80);
ret = regmap_write(dev->regmap, 0x10b, 0x7f);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x011, 0xd4);
ret = regmap_write(dev->regmap, 0x1e5, 0xf0);
ret = regmap_write(dev->regmap, 0x1d9, 0x00);
ret = regmap_write(dev->regmap, 0x1db, 0x00);
ret = regmap_write(dev->regmap, 0x1dd, 0x14);
ret = regmap_write(dev->regmap, 0x1de, 0xec);
ret = regmap_write(dev->regmap, 0x1d8, 0x0c);
ret = regmap_write(dev->regmap, 0x1e6, 0x02);
ret = regmap_write(dev->regmap, 0x1d7, 0x09);
ret = regmap_write(dev->regmap, 0x00d, 0x83);
ret = regmap_write(dev->regmap, 0x010, 0x49);
ret = regmap_write(dev->regmap, 0x00d, 0x87);
ret = regmap_write(dev->regmap, 0x00d, 0x85);
ret = regmap_write(dev->regmap, 0x013, 0x02);
break;
case RTL2832_SDR_TUNER_FC0012:
case RTL2832_SDR_TUNER_FC0013:
ret = regmap_write(dev->regmap, 0x112, 0x5a);
ret = regmap_write(dev->regmap, 0x102, 0x40);
ret = regmap_write(dev->regmap, 0x103, 0x5a);
ret = regmap_write(dev->regmap, 0x1c7, 0x2c);
ret = regmap_write(dev->regmap, 0x104, 0xcc);
ret = regmap_write(dev->regmap, 0x105, 0xbe);
ret = regmap_write(dev->regmap, 0x1c8, 0x16);
ret = regmap_write(dev->regmap, 0x106, 0x35);
ret = regmap_write(dev->regmap, 0x1c9, 0x21);
ret = regmap_write(dev->regmap, 0x1ca, 0x21);
ret = regmap_write(dev->regmap, 0x1cb, 0x00);
ret = regmap_write(dev->regmap, 0x107, 0x40);
ret = regmap_write(dev->regmap, 0x1cd, 0x10);
ret = regmap_write(dev->regmap, 0x1ce, 0x10);
ret = regmap_write(dev->regmap, 0x108, 0x80);
ret = regmap_write(dev->regmap, 0x109, 0x7f);
ret = regmap_write(dev->regmap, 0x10a, 0x80);
ret = regmap_write(dev->regmap, 0x10b, 0x7f);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_bulk_write(dev->regmap, 0x011, "\xe9\xbf", 2);
ret = regmap_write(dev->regmap, 0x1e5, 0xf0);
ret = regmap_write(dev->regmap, 0x1d9, 0x00);
ret = regmap_write(dev->regmap, 0x1db, 0x00);
ret = regmap_write(dev->regmap, 0x1dd, 0x11);
ret = regmap_write(dev->regmap, 0x1de, 0xef);
ret = regmap_write(dev->regmap, 0x1d8, 0x0c);
ret = regmap_write(dev->regmap, 0x1e6, 0x02);
ret = regmap_write(dev->regmap, 0x1d7, 0x09);
break;
case RTL2832_SDR_TUNER_R820T:
case RTL2832_SDR_TUNER_R828D:
ret = regmap_write(dev->regmap, 0x112, 0x5a);
ret = regmap_write(dev->regmap, 0x102, 0x40);
ret = regmap_write(dev->regmap, 0x115, 0x01);
ret = regmap_write(dev->regmap, 0x103, 0x80);
ret = regmap_write(dev->regmap, 0x1c7, 0x24);
ret = regmap_write(dev->regmap, 0x104, 0xcc);
ret = regmap_write(dev->regmap, 0x105, 0xbe);
ret = regmap_write(dev->regmap, 0x1c8, 0x14);
ret = regmap_write(dev->regmap, 0x106, 0x35);
ret = regmap_write(dev->regmap, 0x1c9, 0x21);
ret = regmap_write(dev->regmap, 0x1ca, 0x21);
ret = regmap_write(dev->regmap, 0x1cb, 0x00);
ret = regmap_write(dev->regmap, 0x107, 0x40);
ret = regmap_write(dev->regmap, 0x1cd, 0x10);
ret = regmap_write(dev->regmap, 0x1ce, 0x10);
ret = regmap_write(dev->regmap, 0x108, 0x80);
ret = regmap_write(dev->regmap, 0x109, 0x7f);
ret = regmap_write(dev->regmap, 0x10a, 0x80);
ret = regmap_write(dev->regmap, 0x10b, 0x7f);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x011, 0xf4);
break;
case RTL2832_SDR_TUNER_FC2580:
ret = regmap_write(dev->regmap, 0x112, 0x39);
ret = regmap_write(dev->regmap, 0x102, 0x40);
ret = regmap_write(dev->regmap, 0x103, 0x5a);
ret = regmap_write(dev->regmap, 0x1c7, 0x2c);
ret = regmap_write(dev->regmap, 0x104, 0xcc);
ret = regmap_write(dev->regmap, 0x105, 0xbe);
ret = regmap_write(dev->regmap, 0x1c8, 0x16);
ret = regmap_write(dev->regmap, 0x106, 0x35);
ret = regmap_write(dev->regmap, 0x1c9, 0x21);
ret = regmap_write(dev->regmap, 0x1ca, 0x21);
ret = regmap_write(dev->regmap, 0x1cb, 0x00);
ret = regmap_write(dev->regmap, 0x107, 0x40);
ret = regmap_write(dev->regmap, 0x1cd, 0x10);
ret = regmap_write(dev->regmap, 0x1ce, 0x10);
ret = regmap_write(dev->regmap, 0x108, 0x80);
ret = regmap_write(dev->regmap, 0x109, 0x7f);
ret = regmap_write(dev->regmap, 0x10a, 0x9c);
ret = regmap_write(dev->regmap, 0x10b, 0x7f);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_write(dev->regmap, 0x00e, 0xfc);
ret = regmap_bulk_write(dev->regmap, 0x011, "\xe9\xf4", 2);
break;
default:
dev_notice(&pdev->dev, "Unsupported tuner\n");
}
/* software reset */
ret = regmap_update_bits(dev->regmap, 0x101, 0x04, 0x04);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x101, 0x04, 0x00);
if (ret)
goto err;
err:
return ret;
};
static void rtl2832_sdr_unset_adc(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "\n");
/* PID filter */
ret = regmap_write(dev->regmap, 0x061, 0xe0);
if (ret)
goto err;
/* mode */
ret = regmap_write(dev->regmap, 0x019, 0x20);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x017, "\x11\x10", 2);
if (ret)
goto err;
/* FSM */
ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x13e, "\x40\x00", 2);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x115, "\x06\x3f\xce\xcc", 4);
if (ret)
goto err;
err:
return;
};
static int rtl2832_sdr_set_tuner_freq(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct v4l2_ctrl *bandwidth_auto;
struct v4l2_ctrl *bandwidth;
/*
* tuner RF (Hz)
*/
if (dev->f_tuner == 0)
return 0;
/*
* bandwidth (Hz)
*/
bandwidth_auto = v4l2_ctrl_find(&dev->hdl,
V4L2_CID_RF_TUNER_BANDWIDTH_AUTO);
bandwidth = v4l2_ctrl_find(&dev->hdl, V4L2_CID_RF_TUNER_BANDWIDTH);
if (v4l2_ctrl_g_ctrl(bandwidth_auto)) {
c->bandwidth_hz = dev->f_adc;
v4l2_ctrl_s_ctrl(bandwidth, dev->f_adc);
} else {
c->bandwidth_hz = v4l2_ctrl_g_ctrl(bandwidth);
}
c->frequency = dev->f_tuner;
c->delivery_system = SYS_DVBT;
dev_dbg(&pdev->dev, "frequency=%u bandwidth=%d\n",
c->frequency, c->bandwidth_hz);
if (!test_bit(POWER_ON, &dev->flags))
return 0;
if (!V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, s_frequency)) {
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
}
return 0;
};
static int rtl2832_sdr_set_tuner(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
dev_dbg(&pdev->dev, "\n");
if (fe->ops.tuner_ops.init)
fe->ops.tuner_ops.init(fe);
return 0;
};
static void rtl2832_sdr_unset_tuner(struct rtl2832_sdr_dev *dev)
{
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
dev_dbg(&pdev->dev, "\n");
if (fe->ops.tuner_ops.sleep)
fe->ops.tuner_ops.sleep(fe);
return;
};
static int rtl2832_sdr_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vq);
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_usb_device *d = pdata->dvb_usb_device;
int ret;
dev_dbg(&pdev->dev, "\n");
if (!dev->udev)
return -ENODEV;
if (mutex_lock_interruptible(&dev->v4l2_lock))
return -ERESTARTSYS;
if (d->props->power_ctrl)
d->props->power_ctrl(d, 1);
/* enable ADC */
if (d->props->frontend_ctrl)
d->props->frontend_ctrl(pdata->dvb_frontend, 1);
set_bit(POWER_ON, &dev->flags);
/* wake-up tuner */
if (V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, core, s_power))
ret = v4l2_subdev_call(dev->v4l2_subdev, core, s_power, 1);
else
ret = rtl2832_sdr_set_tuner(dev);
if (ret)
goto err;
ret = rtl2832_sdr_set_tuner_freq(dev);
if (ret)
goto err;
ret = rtl2832_sdr_set_adc(dev);
if (ret)
goto err;
ret = rtl2832_sdr_alloc_stream_bufs(dev);
if (ret)
goto err;
ret = rtl2832_sdr_alloc_urbs(dev);
if (ret)
goto err;
dev->sequence = 0;
ret = rtl2832_sdr_submit_urbs(dev);
if (ret)
goto err;
err:
mutex_unlock(&dev->v4l2_lock);
return ret;
}
static void rtl2832_sdr_stop_streaming(struct vb2_queue *vq)
{
struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vq);
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_usb_device *d = pdata->dvb_usb_device;
dev_dbg(&pdev->dev, "\n");
mutex_lock(&dev->v4l2_lock);
rtl2832_sdr_kill_urbs(dev);
rtl2832_sdr_free_urbs(dev);
rtl2832_sdr_free_stream_bufs(dev);
rtl2832_sdr_cleanup_queued_bufs(dev);
rtl2832_sdr_unset_adc(dev);
/* sleep tuner */
if (V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, core, s_power))
v4l2_subdev_call(dev->v4l2_subdev, core, s_power, 0);
else
rtl2832_sdr_unset_tuner(dev);
clear_bit(POWER_ON, &dev->flags);
/* disable ADC */
if (d->props->frontend_ctrl)
d->props->frontend_ctrl(pdata->dvb_frontend, 0);
if (d->props->power_ctrl)
d->props->power_ctrl(d, 0);
mutex_unlock(&dev->v4l2_lock);
}
static const struct vb2_ops rtl2832_sdr_vb2_ops = {
.queue_setup = rtl2832_sdr_queue_setup,
.buf_prepare = rtl2832_sdr_buf_prepare,
.buf_queue = rtl2832_sdr_buf_queue,
.start_streaming = rtl2832_sdr_start_streaming,
.stop_streaming = rtl2832_sdr_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int rtl2832_sdr_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *v)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "index=%d type=%d\n", v->index, v->type);
if (v->index == 0) {
strscpy(v->name, "ADC: Realtek RTL2832", sizeof(v->name));
v->type = V4L2_TUNER_ADC;
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
v->rangelow = 300000;
v->rangehigh = 3200000;
ret = 0;
} else if (v->index == 1 &&
V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, g_tuner)) {
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, g_tuner, v);
} else if (v->index == 1) {
strscpy(v->name, "RF: <unknown>", sizeof(v->name));
v->type = V4L2_TUNER_RF;
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
v->rangelow = 50000000;
v->rangehigh = 2000000000;
ret = 0;
} else {
ret = -EINVAL;
}
return ret;
}
static int rtl2832_sdr_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *v)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "\n");
if (v->index == 0) {
ret = 0;
} else if (v->index == 1 &&
V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, s_tuner)) {
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, s_tuner, v);
} else if (v->index == 1) {
ret = 0;
} else {
ret = -EINVAL;
}
return ret;
}
static int rtl2832_sdr_enum_freq_bands(struct file *file, void *priv,
struct v4l2_frequency_band *band)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "tuner=%d type=%d index=%d\n",
band->tuner, band->type, band->index);
if (band->tuner == 0) {
if (band->index >= ARRAY_SIZE(bands_adc))
return -EINVAL;
*band = bands_adc[band->index];
ret = 0;
} else if (band->tuner == 1 &&
V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, enum_freq_bands)) {
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, enum_freq_bands, band);
} else if (band->tuner == 1) {
if (band->index >= ARRAY_SIZE(bands_fm))
return -EINVAL;
*band = bands_fm[band->index];
ret = 0;
} else {
ret = -EINVAL;
}
return ret;
}
static int rtl2832_sdr_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "tuner=%d type=%d\n", f->tuner, f->type);
if (f->tuner == 0) {
f->frequency = dev->f_adc;
f->type = V4L2_TUNER_ADC;
ret = 0;
} else if (f->tuner == 1 &&
V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, g_frequency)) {
f->type = V4L2_TUNER_RF;
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, g_frequency, f);
} else if (f->tuner == 1) {
f->frequency = dev->f_tuner;
f->type = V4L2_TUNER_RF;
ret = 0;
} else {
ret = -EINVAL;
}
return ret;
}
static int rtl2832_sdr_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int ret, band;
dev_dbg(&pdev->dev, "tuner=%d type=%d frequency=%u\n",
f->tuner, f->type, f->frequency);
/* ADC band midpoints */
#define BAND_ADC_0 ((bands_adc[0].rangehigh + bands_adc[1].rangelow) / 2)
#define BAND_ADC_1 ((bands_adc[1].rangehigh + bands_adc[2].rangelow) / 2)
if (f->tuner == 0 && f->type == V4L2_TUNER_ADC) {
if (f->frequency < BAND_ADC_0)
band = 0;
else if (f->frequency < BAND_ADC_1)
band = 1;
else
band = 2;
dev->f_adc = clamp_t(unsigned int, f->frequency,
bands_adc[band].rangelow,
bands_adc[band].rangehigh);
dev_dbg(&pdev->dev, "ADC frequency=%u Hz\n", dev->f_adc);
ret = rtl2832_sdr_set_adc(dev);
} else if (f->tuner == 1 &&
V4L2_SUBDEV_HAS_OP(dev->v4l2_subdev, tuner, s_frequency)) {
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, s_frequency, f);
} else if (f->tuner == 1) {
dev->f_tuner = clamp_t(unsigned int, f->frequency,
bands_fm[0].rangelow,
bands_fm[0].rangehigh);
dev_dbg(&pdev->dev, "RF frequency=%u Hz\n", f->frequency);
ret = rtl2832_sdr_set_tuner_freq(dev);
} else {
ret = -EINVAL;
}
return ret;
}
static int rtl2832_sdr_enum_fmt_sdr_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "\n");
if (f->index >= dev->num_formats)
return -EINVAL;
f->pixelformat = formats[f->index].pixelformat;
return 0;
}
static int rtl2832_sdr_g_fmt_sdr_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "\n");
f->fmt.sdr.pixelformat = dev->pixelformat;
f->fmt.sdr.buffersize = dev->buffersize;
return 0;
}
static int rtl2832_sdr_s_fmt_sdr_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
struct vb2_queue *q = &dev->vb_queue;
int i;
dev_dbg(&pdev->dev, "pixelformat fourcc %4.4s\n",
(char *)&f->fmt.sdr.pixelformat);
if (vb2_is_busy(q))
return -EBUSY;
for (i = 0; i < dev->num_formats; i++) {
if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
dev->pixelformat = formats[i].pixelformat;
dev->buffersize = formats[i].buffersize;
f->fmt.sdr.buffersize = formats[i].buffersize;
return 0;
}
}
dev->pixelformat = formats[0].pixelformat;
dev->buffersize = formats[0].buffersize;
f->fmt.sdr.pixelformat = formats[0].pixelformat;
f->fmt.sdr.buffersize = formats[0].buffersize;
return 0;
}
static int rtl2832_sdr_try_fmt_sdr_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct rtl2832_sdr_dev *dev = video_drvdata(file);
struct platform_device *pdev = dev->pdev;
int i;
dev_dbg(&pdev->dev, "pixelformat fourcc %4.4s\n",
(char *)&f->fmt.sdr.pixelformat);
for (i = 0; i < dev->num_formats; i++) {
if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
f->fmt.sdr.buffersize = formats[i].buffersize;
return 0;
}
}
f->fmt.sdr.pixelformat = formats[0].pixelformat;
f->fmt.sdr.buffersize = formats[0].buffersize;
return 0;
}
static const struct v4l2_ioctl_ops rtl2832_sdr_ioctl_ops = {
.vidioc_querycap = rtl2832_sdr_querycap,
.vidioc_enum_fmt_sdr_cap = rtl2832_sdr_enum_fmt_sdr_cap,
.vidioc_g_fmt_sdr_cap = rtl2832_sdr_g_fmt_sdr_cap,
.vidioc_s_fmt_sdr_cap = rtl2832_sdr_s_fmt_sdr_cap,
.vidioc_try_fmt_sdr_cap = rtl2832_sdr_try_fmt_sdr_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_tuner = rtl2832_sdr_g_tuner,
.vidioc_s_tuner = rtl2832_sdr_s_tuner,
.vidioc_enum_freq_bands = rtl2832_sdr_enum_freq_bands,
.vidioc_g_frequency = rtl2832_sdr_g_frequency,
.vidioc_s_frequency = rtl2832_sdr_s_frequency,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_log_status = v4l2_ctrl_log_status,
};
static const struct v4l2_file_operations rtl2832_sdr_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static struct video_device rtl2832_sdr_template = {
.name = "Realtek RTL2832 SDR",
.release = video_device_release_empty,
.fops = &rtl2832_sdr_fops,
.ioctl_ops = &rtl2832_sdr_ioctl_ops,
.device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_STREAMING |
V4L2_CAP_READWRITE | V4L2_CAP_TUNER,
};
static int rtl2832_sdr_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct rtl2832_sdr_dev *dev =
container_of(ctrl->handler, struct rtl2832_sdr_dev,
hdl);
struct platform_device *pdev = dev->pdev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&pdev->dev, "id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum,
ctrl->step);
switch (ctrl->id) {
case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
case V4L2_CID_RF_TUNER_BANDWIDTH:
/* TODO: these controls should be moved to tuner drivers */
if (dev->bandwidth_auto->val) {
/* Round towards the closest legal value */
s32 val = dev->f_adc + div_u64(dev->bandwidth->step, 2);
u32 offset;
val = clamp_t(s32, val, dev->bandwidth->minimum,
dev->bandwidth->maximum);
offset = val - dev->bandwidth->minimum;
offset = dev->bandwidth->step *
div_u64(offset, dev->bandwidth->step);
dev->bandwidth->val = dev->bandwidth->minimum + offset;
}
c->bandwidth_hz = dev->bandwidth->val;
if (!test_bit(POWER_ON, &dev->flags))
return 0;
if (fe->ops.tuner_ops.set_params)
ret = fe->ops.tuner_ops.set_params(fe);
else
ret = 0;
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct v4l2_ctrl_ops rtl2832_sdr_ctrl_ops = {
.s_ctrl = rtl2832_sdr_s_ctrl,
};
static void rtl2832_sdr_video_release(struct v4l2_device *v)
{
struct rtl2832_sdr_dev *dev =
container_of(v, struct rtl2832_sdr_dev, v4l2_dev);
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "\n");
v4l2_ctrl_handler_free(&dev->hdl);
v4l2_device_unregister(&dev->v4l2_dev);
kfree(dev);
}
/* Platform driver interface */
static int rtl2832_sdr_probe(struct platform_device *pdev)
{
struct rtl2832_sdr_dev *dev;
struct rtl2832_sdr_platform_data *pdata = pdev->dev.platform_data;
const struct v4l2_ctrl_ops *ops = &rtl2832_sdr_ctrl_ops;
struct v4l2_subdev *subdev;
int ret;
dev_dbg(&pdev->dev, "\n");
if (!pdata) {
dev_err(&pdev->dev, "Cannot proceed without platform data\n");
ret = -EINVAL;
goto err;
}
if (!pdev->dev.parent->driver) {
dev_dbg(&pdev->dev, "No parent device\n");
ret = -EINVAL;
goto err;
}
/* try to refcount host drv since we are the consumer */
if (!try_module_get(pdev->dev.parent->driver->owner)) {
dev_err(&pdev->dev, "Refcount fail");
ret = -EINVAL;
goto err;
}
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
goto err_module_put;
}
/* setup the state */
subdev = pdata->v4l2_subdev;
dev->v4l2_subdev = pdata->v4l2_subdev;
dev->pdev = pdev;
dev->regmap = pdata->regmap;
dev->udev = pdata->dvb_usb_device->udev;
dev->f_adc = bands_adc[0].rangelow;
dev->f_tuner = bands_fm[0].rangelow;
dev->pixelformat = formats[0].pixelformat;
dev->buffersize = formats[0].buffersize;
dev->num_formats = NUM_FORMATS;
if (!rtl2832_sdr_emulated_fmt)
dev->num_formats -= 1;
mutex_init(&dev->v4l2_lock);
mutex_init(&dev->vb_queue_lock);
spin_lock_init(&dev->queued_bufs_lock);
INIT_LIST_HEAD(&dev->queued_bufs);
/* Init videobuf2 queue structure */
dev->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
dev->vb_queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
dev->vb_queue.drv_priv = dev;
dev->vb_queue.buf_struct_size = sizeof(struct rtl2832_sdr_frame_buf);
dev->vb_queue.ops = &rtl2832_sdr_vb2_ops;
dev->vb_queue.mem_ops = &vb2_vmalloc_memops;
dev->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
ret = vb2_queue_init(&dev->vb_queue);
if (ret) {
dev_err(&pdev->dev, "Could not initialize vb2 queue\n");
goto err_kfree;
}
/* Register controls */
switch (pdata->tuner) {
case RTL2832_SDR_TUNER_E4000:
v4l2_ctrl_handler_init(&dev->hdl, 9);
if (subdev)
v4l2_ctrl_add_handler(&dev->hdl, subdev->ctrl_handler,
NULL, true);
break;
case RTL2832_SDR_TUNER_R820T:
case RTL2832_SDR_TUNER_R828D:
v4l2_ctrl_handler_init(&dev->hdl, 2);
dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, ops,
V4L2_CID_RF_TUNER_BANDWIDTH_AUTO,
0, 1, 1, 1);
dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, ops,
V4L2_CID_RF_TUNER_BANDWIDTH,
0, 8000000, 100000, 0);
v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
break;
case RTL2832_SDR_TUNER_FC0012:
case RTL2832_SDR_TUNER_FC0013:
v4l2_ctrl_handler_init(&dev->hdl, 2);
dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, ops,
V4L2_CID_RF_TUNER_BANDWIDTH_AUTO,
0, 1, 1, 1);
dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, ops,
V4L2_CID_RF_TUNER_BANDWIDTH,
6000000, 8000000, 1000000,
6000000);
v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
break;
case RTL2832_SDR_TUNER_FC2580:
v4l2_ctrl_handler_init(&dev->hdl, 2);
if (subdev)
v4l2_ctrl_add_handler(&dev->hdl, subdev->ctrl_handler,
NULL, true);
break;
default:
v4l2_ctrl_handler_init(&dev->hdl, 0);
dev_err(&pdev->dev, "Unsupported tuner\n");
ret = -ENODEV;
goto err_v4l2_ctrl_handler_free;
}
if (dev->hdl.error) {
ret = dev->hdl.error;
dev_err(&pdev->dev, "Could not initialize controls\n");
goto err_v4l2_ctrl_handler_free;
}
/* Init video_device structure */
dev->vdev = rtl2832_sdr_template;
dev->vdev.queue = &dev->vb_queue;
dev->vdev.queue->lock = &dev->vb_queue_lock;
video_set_drvdata(&dev->vdev, dev);
/* Register the v4l2_device structure */
dev->v4l2_dev.release = rtl2832_sdr_video_release;
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
if (ret) {
dev_err(&pdev->dev, "Failed to register v4l2-device %d\n", ret);
goto err_v4l2_ctrl_handler_free;
}
dev->v4l2_dev.ctrl_handler = &dev->hdl;
dev->vdev.v4l2_dev = &dev->v4l2_dev;
dev->vdev.lock = &dev->v4l2_lock;
dev->vdev.vfl_dir = VFL_DIR_RX;
ret = video_register_device(&dev->vdev, VFL_TYPE_SDR, -1);
if (ret) {
dev_err(&pdev->dev, "Failed to register as video device %d\n",
ret);
goto err_v4l2_device_unregister;
}
dev_info(&pdev->dev, "Registered as %s\n",
video_device_node_name(&dev->vdev));
dev_info(&pdev->dev, "Realtek RTL2832 SDR attached\n");
dev_notice(&pdev->dev,
"SDR API is still slightly experimental and functionality changes may follow\n");
platform_set_drvdata(pdev, dev);
return 0;
err_v4l2_device_unregister:
v4l2_device_unregister(&dev->v4l2_dev);
err_v4l2_ctrl_handler_free:
v4l2_ctrl_handler_free(&dev->hdl);
err_kfree:
kfree(dev);
err_module_put:
module_put(pdev->dev.parent->driver->owner);
err:
return ret;
}
static void rtl2832_sdr_remove(struct platform_device *pdev)
{
struct rtl2832_sdr_dev *dev = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "\n");
mutex_lock(&dev->vb_queue_lock);
mutex_lock(&dev->v4l2_lock);
/* No need to keep the urbs around after disconnection */
dev->udev = NULL;
v4l2_device_disconnect(&dev->v4l2_dev);
video_unregister_device(&dev->vdev);
mutex_unlock(&dev->v4l2_lock);
mutex_unlock(&dev->vb_queue_lock);
v4l2_device_put(&dev->v4l2_dev);
module_put(pdev->dev.parent->driver->owner);
}
static struct platform_driver rtl2832_sdr_driver = {
.driver = {
.name = "rtl2832_sdr",
},
.probe = rtl2832_sdr_probe,
.remove_new = rtl2832_sdr_remove,
};
module_platform_driver(rtl2832_sdr_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Realtek RTL2832 SDR driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/rtl2832_sdr.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for LNB supply and control IC STMicroelectronics LNBH29
//
// Copyright (c) 2018 Socionext Inc.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "lnbh29.h"
/**
* struct lnbh29_priv - LNBH29 driver private data
* @i2c: Pointer to the I2C adapter structure
* @i2c_address: I2C address of LNBH29 chip
* @config: Registers configuration
* offset 0: 1st register address, always 0x01 (DATA)
* offset 1: DATA register value
*/
struct lnbh29_priv {
struct i2c_adapter *i2c;
u8 i2c_address;
u8 config[2];
};
#define LNBH29_STATUS_OLF BIT(0)
#define LNBH29_STATUS_OTF BIT(1)
#define LNBH29_STATUS_VMON BIT(2)
#define LNBH29_STATUS_PNG BIT(3)
#define LNBH29_STATUS_PDO BIT(4)
#define LNBH29_VSEL_MASK GENMASK(2, 0)
#define LNBH29_VSEL_0 0x00
/* Min: 13.188V, Typ: 13.667V, Max:14V */
#define LNBH29_VSEL_13 0x03
/* Min: 18.158V, Typ: 18.817V, Max:19.475V */
#define LNBH29_VSEL_18 0x07
static int lnbh29_read_vmon(struct lnbh29_priv *priv)
{
u8 addr = 0x00;
u8 status[2];
int ret;
struct i2c_msg msg[2] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = 1,
.buf = &addr
}, {
.addr = priv->i2c_address,
.flags = I2C_M_RD,
.len = sizeof(status),
.buf = status
}
};
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret >= 0 && ret != 2)
ret = -EIO;
if (ret < 0) {
dev_dbg(&priv->i2c->dev, "LNBH29 I2C transfer failed (%d)\n",
ret);
return ret;
}
if (status[0] & (LNBH29_STATUS_OLF | LNBH29_STATUS_VMON)) {
dev_err(&priv->i2c->dev,
"LNBH29 voltage in failure state, status reg 0x%x\n",
status[0]);
return -EIO;
}
return 0;
}
static int lnbh29_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct lnbh29_priv *priv = fe->sec_priv;
u8 data_reg;
int ret;
struct i2c_msg msg = {
.addr = priv->i2c_address,
.flags = 0,
.len = sizeof(priv->config),
.buf = priv->config
};
switch (voltage) {
case SEC_VOLTAGE_OFF:
data_reg = LNBH29_VSEL_0;
break;
case SEC_VOLTAGE_13:
data_reg = LNBH29_VSEL_13;
break;
case SEC_VOLTAGE_18:
data_reg = LNBH29_VSEL_18;
break;
default:
return -EINVAL;
}
priv->config[1] &= ~LNBH29_VSEL_MASK;
priv->config[1] |= data_reg;
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret >= 0 && ret != 1)
ret = -EIO;
if (ret < 0) {
dev_err(&priv->i2c->dev, "LNBH29 I2C transfer error (%d)\n",
ret);
return ret;
}
/* Soft-start time (Vout 0V to 18V) is Typ. 6ms. */
usleep_range(6000, 20000);
if (voltage == SEC_VOLTAGE_OFF)
return 0;
return lnbh29_read_vmon(priv);
}
static void lnbh29_release(struct dvb_frontend *fe)
{
lnbh29_set_voltage(fe, SEC_VOLTAGE_OFF);
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *lnbh29_attach(struct dvb_frontend *fe,
struct lnbh29_config *cfg,
struct i2c_adapter *i2c)
{
struct lnbh29_priv *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return NULL;
priv->i2c_address = (cfg->i2c_address >> 1);
priv->i2c = i2c;
priv->config[0] = 0x01;
priv->config[1] = cfg->data_config;
fe->sec_priv = priv;
if (lnbh29_set_voltage(fe, SEC_VOLTAGE_OFF)) {
dev_err(&i2c->dev, "no LNBH29 found at I2C addr 0x%02x\n",
priv->i2c_address);
kfree(priv);
fe->sec_priv = NULL;
return NULL;
}
fe->ops.release_sec = lnbh29_release;
fe->ops.set_voltage = lnbh29_set_voltage;
dev_info(&i2c->dev, "LNBH29 attached at I2C addr 0x%02x\n",
priv->i2c_address);
return fe;
}
EXPORT_SYMBOL(lnbh29_attach);
MODULE_AUTHOR("Katsuhiro Suzuki <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics LNBH29 driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/lnbh29.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for LGDT3306A - 8VSB/QAM-B
*
* Copyright (C) 2013 Fred Richter <[email protected]>
* - driver structure based on lgdt3305.[ch] by Michael Krufky
* - code based on LG3306_V0.35 API by LG Electronics Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <asm/div64.h>
#include <linux/kernel.h>
#include <linux/dvb/frontend.h>
#include <linux/int_log.h>
#include "lgdt3306a.h"
#include <linux/i2c-mux.h>
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
/*
* Older drivers treated QAM64 and QAM256 the same; that is the HW always
* used "Auto" mode during detection. Setting "forced_manual"=1 allows
* the user to treat these modes as separate. For backwards compatibility,
* it's off by default. QAM_AUTO can now be specified to achive that
* effect even if "forced_manual"=1
*/
static int forced_manual;
module_param(forced_manual, int, 0644);
MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
#define DBG_INFO 1
#define DBG_REG 2
#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
#define lg_debug(fmt, arg...) \
printk(KERN_DEBUG pr_fmt(fmt), ## arg)
#define dbg_info(fmt, arg...) \
do { \
if (debug & DBG_INFO) \
lg_debug(fmt, ## arg); \
} while (0)
#define dbg_reg(fmt, arg...) \
do { \
if (debug & DBG_REG) \
lg_debug(fmt, ## arg); \
} while (0)
#define lg_chkerr(ret) \
({ \
int __ret; \
__ret = (ret < 0); \
if (__ret) \
pr_err("error %d on line %d\n", ret, __LINE__); \
__ret; \
})
struct lgdt3306a_state {
struct i2c_adapter *i2c_adap;
const struct lgdt3306a_config *cfg;
struct dvb_frontend frontend;
enum fe_modulation current_modulation;
u32 current_frequency;
u32 snr;
struct i2c_mux_core *muxc;
};
/*
* LG3306A Register Usage
* (LG does not really name the registers, so this code does not either)
*
* 0000 -> 00FF Common control and status
* 1000 -> 10FF Synchronizer control and status
* 1F00 -> 1FFF Smart Antenna control and status
* 2100 -> 21FF VSB Equalizer control and status
* 2800 -> 28FF QAM Equalizer control and status
* 3000 -> 30FF FEC control and status
*/
enum lgdt3306a_lock_status {
LG3306_UNLOCK = 0x00,
LG3306_LOCK = 0x01,
LG3306_UNKNOWN_LOCK = 0xff
};
enum lgdt3306a_neverlock_status {
LG3306_NL_INIT = 0x00,
LG3306_NL_PROCESS = 0x01,
LG3306_NL_LOCK = 0x02,
LG3306_NL_FAIL = 0x03,
LG3306_NL_UNKNOWN = 0xff
};
enum lgdt3306a_modulation {
LG3306_VSB = 0x00,
LG3306_QAM64 = 0x01,
LG3306_QAM256 = 0x02,
LG3306_UNKNOWN_MODE = 0xff
};
enum lgdt3306a_lock_check {
LG3306_SYNC_LOCK,
LG3306_FEC_LOCK,
LG3306_TR_LOCK,
LG3306_AGC_LOCK,
};
#ifdef DBG_DUMP
static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
#endif
static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
{
int ret;
u8 buf[] = { reg >> 8, reg & 0xff, val };
struct i2c_msg msg = {
.addr = state->cfg->i2c_addr, .flags = 0,
.buf = buf, .len = 3,
};
dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
if (ret != 1) {
pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
msg.buf[0], msg.buf[1], msg.buf[2], ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
return 0;
}
static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
{
int ret;
u8 reg_buf[] = { reg >> 8, reg & 0xff };
struct i2c_msg msg[] = {
{ .addr = state->cfg->i2c_addr,
.flags = 0, .buf = reg_buf, .len = 2 },
{ .addr = state->cfg->i2c_addr,
.flags = I2C_M_RD, .buf = val, .len = 1 },
};
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
pr_err("error (addr %02x reg %04x error (ret == %i)\n",
state->cfg->i2c_addr, reg, ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
return 0;
}
#define read_reg(state, reg) \
({ \
u8 __val; \
int ret = lgdt3306a_read_reg(state, reg, &__val); \
if (lg_chkerr(ret)) \
__val = 0; \
__val; \
})
static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
u16 reg, int bit, int onoff)
{
u8 val;
int ret;
dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
ret = lgdt3306a_read_reg(state, reg, &val);
if (lg_chkerr(ret))
goto fail;
val &= ~(1 << bit);
val |= (onoff & 1) << bit;
ret = lgdt3306a_write_reg(state, reg, val);
lg_chkerr(ret);
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
{
int ret;
dbg_info("\n");
ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
if (lg_chkerr(ret))
goto fail;
msleep(20);
ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
lg_chkerr(ret);
fail:
return ret;
}
static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
enum lgdt3306a_mpeg_mode mode)
{
u8 val;
int ret;
dbg_info("(%d)\n", mode);
/* transport packet format - TPSENB=0x80 */
ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
if (lg_chkerr(ret))
goto fail;
/*
* start of packet signal duration
* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
*/
ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_read_reg(state, 0x0070, &val);
if (lg_chkerr(ret))
goto fail;
val |= 0x10; /* TPCLKSUPB=0x10 */
if (mode == LGDT3306A_MPEG_PARALLEL)
val &= ~0x10;
ret = lgdt3306a_write_reg(state, 0x0070, val);
lg_chkerr(ret);
fail:
return ret;
}
static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
enum lgdt3306a_tp_clock_edge edge,
enum lgdt3306a_tp_valid_polarity valid)
{
u8 val;
int ret;
dbg_info("edge=%d, valid=%d\n", edge, valid);
ret = lgdt3306a_read_reg(state, 0x0070, &val);
if (lg_chkerr(ret))
goto fail;
val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
if (edge == LGDT3306A_TPCLK_RISING_EDGE)
val |= 0x04;
if (valid == LGDT3306A_TP_VALID_HIGH)
val |= 0x02;
ret = lgdt3306a_write_reg(state, 0x0070, val);
lg_chkerr(ret);
fail:
return ret;
}
static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
int mode)
{
u8 val;
int ret;
dbg_info("(%d)\n", mode);
if (mode) {
ret = lgdt3306a_read_reg(state, 0x0070, &val);
if (lg_chkerr(ret))
goto fail;
/*
* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
* TPDATAOUTEN=0x08
*/
val &= ~0xa8;
ret = lgdt3306a_write_reg(state, 0x0070, val);
if (lg_chkerr(ret))
goto fail;
/* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
if (lg_chkerr(ret))
goto fail;
} else {
/* enable IFAGC pin */
ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_read_reg(state, 0x0070, &val);
if (lg_chkerr(ret))
goto fail;
val |= 0xa8; /* enable bus */
ret = lgdt3306a_write_reg(state, 0x0070, val);
if (lg_chkerr(ret))
goto fail;
}
fail:
return ret;
}
static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
dbg_info("acquire=%d\n", acquire);
return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
}
static int lgdt3306a_power(struct lgdt3306a_state *state,
int mode)
{
int ret;
dbg_info("(%d)\n", mode);
if (mode == 0) {
/* into reset */
ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
if (lg_chkerr(ret))
goto fail;
/* power down */
ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
if (lg_chkerr(ret))
goto fail;
} else {
/* out of reset */
ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
if (lg_chkerr(ret))
goto fail;
/* power up */
ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
if (lg_chkerr(ret))
goto fail;
}
#ifdef DBG_DUMP
lgdt3306a_DumpAllRegs(state);
#endif
fail:
return ret;
}
static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
{
u8 val;
int ret;
dbg_info("\n");
/* 0. Spectrum inversion detection manual; spectrum inverted */
ret = lgdt3306a_read_reg(state, 0x0002, &val);
val &= 0xf7; /* SPECINVAUTO Off */
val |= 0x04; /* SPECINV On */
ret = lgdt3306a_write_reg(state, 0x0002, val);
if (lg_chkerr(ret))
goto fail;
/* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
if (lg_chkerr(ret))
goto fail;
/* 2. Bandwidth mode for VSB(6MHz) */
ret = lgdt3306a_read_reg(state, 0x0009, &val);
val &= 0xe3;
val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
ret = lgdt3306a_write_reg(state, 0x0009, val);
if (lg_chkerr(ret))
goto fail;
/* 3. QAM mode detection mode(None) */
ret = lgdt3306a_read_reg(state, 0x0009, &val);
val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
ret = lgdt3306a_write_reg(state, 0x0009, val);
if (lg_chkerr(ret))
goto fail;
/* 4. ADC sampling frequency rate(2x sampling) */
ret = lgdt3306a_read_reg(state, 0x000d, &val);
val &= 0xbf; /* SAMPLING4XFEN=0 */
ret = lgdt3306a_write_reg(state, 0x000d, val);
if (lg_chkerr(ret))
goto fail;
#if 0
/* FGR - disable any AICC filtering, testing only */
ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
if (lg_chkerr(ret))
goto fail;
/* AICCFIXFREQ0 NT N-1(Video rejection) */
ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
/* AICCFIXFREQ1 NT N-1(Audio rejection) */
ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
/* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
/* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
#else
/* FGR - this works well for HVR-1955,1975 */
/* 5. AICCOPMODE NT N-1 Adj. */
ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
if (lg_chkerr(ret))
goto fail;
/* AICCFIXFREQ0 NT N-1(Video rejection) */
ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
/* AICCFIXFREQ1 NT N-1(Audio rejection) */
ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
/* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
/* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
#endif
ret = lgdt3306a_read_reg(state, 0x001e, &val);
val &= 0x0f;
val |= 0xa0;
ret = lgdt3306a_write_reg(state, 0x001e, val);
ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
ret = lgdt3306a_read_reg(state, 0x211f, &val);
val &= 0xef;
ret = lgdt3306a_write_reg(state, 0x211f, val);
ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
ret = lgdt3306a_read_reg(state, 0x1061, &val);
val &= 0xf8;
val |= 0x04;
ret = lgdt3306a_write_reg(state, 0x1061, val);
ret = lgdt3306a_read_reg(state, 0x103d, &val);
val &= 0xcf;
ret = lgdt3306a_write_reg(state, 0x103d, val);
ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
ret = lgdt3306a_read_reg(state, 0x2141, &val);
val &= 0x3f;
ret = lgdt3306a_write_reg(state, 0x2141, val);
ret = lgdt3306a_read_reg(state, 0x2135, &val);
val &= 0x0f;
val |= 0x70;
ret = lgdt3306a_write_reg(state, 0x2135, val);
ret = lgdt3306a_read_reg(state, 0x0003, &val);
val &= 0xf7;
ret = lgdt3306a_write_reg(state, 0x0003, val);
ret = lgdt3306a_read_reg(state, 0x001c, &val);
val &= 0x7f;
ret = lgdt3306a_write_reg(state, 0x001c, val);
/* 6. EQ step size */
ret = lgdt3306a_read_reg(state, 0x2179, &val);
val &= 0xf8;
ret = lgdt3306a_write_reg(state, 0x2179, val);
ret = lgdt3306a_read_reg(state, 0x217a, &val);
val &= 0xf8;
ret = lgdt3306a_write_reg(state, 0x217a, val);
/* 7. Reset */
ret = lgdt3306a_soft_reset(state);
if (lg_chkerr(ret))
goto fail;
dbg_info("complete\n");
fail:
return ret;
}
static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
{
u8 val;
int ret;
dbg_info("modulation=%d\n", modulation);
/* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
if (lg_chkerr(ret))
goto fail;
/* 1a. Spectrum inversion detection to Auto */
ret = lgdt3306a_read_reg(state, 0x0002, &val);
val &= 0xfb; /* SPECINV Off */
val |= 0x08; /* SPECINVAUTO On */
ret = lgdt3306a_write_reg(state, 0x0002, val);
if (lg_chkerr(ret))
goto fail;
/* 2. Bandwidth mode for QAM */
ret = lgdt3306a_read_reg(state, 0x0009, &val);
val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
ret = lgdt3306a_write_reg(state, 0x0009, val);
if (lg_chkerr(ret))
goto fail;
/* 3. : 64QAM/256QAM detection(manual, auto) */
ret = lgdt3306a_read_reg(state, 0x0009, &val);
val &= 0xfc;
/* Check for forced Manual modulation modes; otherwise always "auto" */
if(forced_manual && (modulation != QAM_AUTO)){
val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
} else {
val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
}
ret = lgdt3306a_write_reg(state, 0x0009, val);
if (lg_chkerr(ret))
goto fail;
/* 3a. : 64QAM/256QAM selection for manual */
ret = lgdt3306a_read_reg(state, 0x101a, &val);
val &= 0xf8;
if (modulation == QAM_64)
val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
else
val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
ret = lgdt3306a_write_reg(state, 0x101a, val);
if (lg_chkerr(ret))
goto fail;
/* 4. ADC sampling frequency rate(4x sampling) */
ret = lgdt3306a_read_reg(state, 0x000d, &val);
val &= 0xbf;
val |= 0x40; /* SAMPLING4XFEN=1 */
ret = lgdt3306a_write_reg(state, 0x000d, val);
if (lg_chkerr(ret))
goto fail;
/* 5. No AICC operation in QAM mode */
ret = lgdt3306a_read_reg(state, 0x0024, &val);
val &= 0x00;
ret = lgdt3306a_write_reg(state, 0x0024, val);
if (lg_chkerr(ret))
goto fail;
/* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
ret = lgdt3306a_read_reg(state, 0x000a, &val);
val &= 0xfd;
val |= 0x02;
ret = lgdt3306a_write_reg(state, 0x000a, val);
if (lg_chkerr(ret))
goto fail;
/* 5.2 V0.36 Control of "no signal" detector function */
ret = lgdt3306a_read_reg(state, 0x2849, &val);
val &= 0xdf;
ret = lgdt3306a_write_reg(state, 0x2849, val);
if (lg_chkerr(ret))
goto fail;
/* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
ret = lgdt3306a_read_reg(state, 0x302b, &val);
val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */
ret = lgdt3306a_write_reg(state, 0x302b, val);
if (lg_chkerr(ret))
goto fail;
/* 6. Reset */
ret = lgdt3306a_soft_reset(state);
if (lg_chkerr(ret))
goto fail;
dbg_info("complete\n");
fail:
return ret;
}
static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
struct dtv_frontend_properties *p)
{
int ret;
dbg_info("\n");
switch (p->modulation) {
case VSB_8:
ret = lgdt3306a_set_vsb(state);
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
ret = lgdt3306a_set_qam(state, p->modulation);
break;
default:
return -EINVAL;
}
if (lg_chkerr(ret))
goto fail;
state->current_modulation = p->modulation;
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
struct dtv_frontend_properties *p)
{
/* TODO: anything we want to do here??? */
dbg_info("\n");
switch (p->modulation) {
case VSB_8:
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
break;
default:
return -EINVAL;
}
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
int inversion)
{
int ret;
dbg_info("(%d)\n", inversion);
ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
return ret;
}
static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
int enabled)
{
int ret;
dbg_info("(%d)\n", enabled);
/* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
return ret;
}
static int lgdt3306a_set_if(struct lgdt3306a_state *state,
struct dtv_frontend_properties *p)
{
int ret;
u16 if_freq_khz;
u8 nco1, nco2;
switch (p->modulation) {
case VSB_8:
if_freq_khz = state->cfg->vsb_if_khz;
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
if_freq_khz = state->cfg->qam_if_khz;
break;
default:
return -EINVAL;
}
switch (if_freq_khz) {
default:
pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
if_freq_khz);
fallthrough;
case 3250: /* 3.25Mhz */
nco1 = 0x34;
nco2 = 0x00;
break;
case 3500: /* 3.50Mhz */
nco1 = 0x38;
nco2 = 0x00;
break;
case 4000: /* 4.00Mhz */
nco1 = 0x40;
nco2 = 0x00;
break;
case 5000: /* 5.00Mhz */
nco1 = 0x50;
nco2 = 0x00;
break;
case 5380: /* 5.38Mhz */
nco1 = 0x56;
nco2 = 0x14;
break;
}
ret = lgdt3306a_write_reg(state, 0x0010, nco1);
if (ret)
return ret;
ret = lgdt3306a_write_reg(state, 0x0011, nco2);
if (ret)
return ret;
dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
if (state->cfg->deny_i2c_rptr) {
dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
return 0;
}
dbg_info("(%d)\n", enable);
/* NI2CRPTEN=0x80 */
return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
}
static int lgdt3306a_sleep(struct lgdt3306a_state *state)
{
int ret;
dbg_info("\n");
state->current_frequency = -1; /* force re-tune, when we wake */
ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_power(state, 0); /* power down */
lg_chkerr(ret);
fail:
return 0;
}
static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
return lgdt3306a_sleep(state);
}
static int lgdt3306a_init(struct dvb_frontend *fe)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 val;
int ret;
dbg_info("\n");
/* 1. Normal operation mode */
ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
if (lg_chkerr(ret))
goto fail;
/* 2. Spectrum inversion auto detection (Not valid for VSB) */
ret = lgdt3306a_set_inversion_auto(state, 0);
if (lg_chkerr(ret))
goto fail;
/* 3. Spectrum inversion(According to the tuner configuration) */
ret = lgdt3306a_set_inversion(state, 1);
if (lg_chkerr(ret))
goto fail;
/* 4. Peak-to-peak voltage of ADC input signal */
/* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
if (lg_chkerr(ret))
goto fail;
/* 5. ADC output data capture clock phase */
/* 0=same phase as ADC clock */
ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
if (lg_chkerr(ret))
goto fail;
/* 5a. ADC sampling clock source */
/* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
if (lg_chkerr(ret))
goto fail;
/* 6. Automatic PLL set */
/* PLLSETAUTO=0x40; 0=off */
ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
if (lg_chkerr(ret))
goto fail;
if (state->cfg->xtalMHz == 24) { /* 24MHz */
/* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
ret = lgdt3306a_read_reg(state, 0x0005, &val);
if (lg_chkerr(ret))
goto fail;
val &= 0xc0;
val |= 0x25;
ret = lgdt3306a_write_reg(state, 0x0005, val);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
if (lg_chkerr(ret))
goto fail;
/* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
ret = lgdt3306a_read_reg(state, 0x000d, &val);
if (lg_chkerr(ret))
goto fail;
val &= 0xc0;
val |= 0x18;
ret = lgdt3306a_write_reg(state, 0x000d, val);
if (lg_chkerr(ret))
goto fail;
} else if (state->cfg->xtalMHz == 25) { /* 25MHz */
/* 7. Frequency for PLL output */
ret = lgdt3306a_read_reg(state, 0x0005, &val);
if (lg_chkerr(ret))
goto fail;
val &= 0xc0;
val |= 0x25;
ret = lgdt3306a_write_reg(state, 0x0005, val);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
if (lg_chkerr(ret))
goto fail;
/* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
ret = lgdt3306a_read_reg(state, 0x000d, &val);
if (lg_chkerr(ret))
goto fail;
val &= 0xc0;
val |= 0x19;
ret = lgdt3306a_write_reg(state, 0x000d, val);
if (lg_chkerr(ret))
goto fail;
} else {
pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
}
#if 0
ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
#endif
/* 9. Center frequency of input signal of ADC */
ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
/* 10. Fixed gain error value */
ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
/* 10a. VSB TR BW gear shift initial step */
ret = lgdt3306a_read_reg(state, 0x103c, &val);
val &= 0x0f;
val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
ret = lgdt3306a_write_reg(state, 0x103c, val);
/* 10b. Timing offset calibration in low temperature for VSB */
ret = lgdt3306a_read_reg(state, 0x103d, &val);
val &= 0xfc;
val |= 0x03;
ret = lgdt3306a_write_reg(state, 0x103d, val);
/* 10c. Timing offset calibration in low temperature for QAM */
ret = lgdt3306a_read_reg(state, 0x1036, &val);
val &= 0xf0;
val |= 0x0c;
ret = lgdt3306a_write_reg(state, 0x1036, val);
/* 11. Using the imaginary part of CIR in CIR loading */
ret = lgdt3306a_read_reg(state, 0x211f, &val);
val &= 0xef; /* do not use imaginary of CIR */
ret = lgdt3306a_write_reg(state, 0x211f, val);
/* 12. Control of no signal detector function */
ret = lgdt3306a_read_reg(state, 0x2849, &val);
val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
ret = lgdt3306a_write_reg(state, 0x2849, val);
/* FGR - put demod in some known mode */
ret = lgdt3306a_set_vsb(state);
/* 13. TP stream format */
ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
/* 14. disable output buses */
ret = lgdt3306a_mpeg_tristate(state, 1);
/* 15. Sleep (in reset) */
ret = lgdt3306a_sleep(state);
lg_chkerr(ret);
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
fail:
return ret;
}
static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct lgdt3306a_state *state = fe->demodulator_priv;
int ret;
dbg_info("(%d, %d)\n", p->frequency, p->modulation);
if (state->current_frequency == p->frequency &&
state->current_modulation == p->modulation) {
dbg_info(" (already set, skipping ...)\n");
return 0;
}
state->current_frequency = -1;
state->current_modulation = -1;
ret = lgdt3306a_power(state, 1); /* power up */
if (lg_chkerr(ret))
goto fail;
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
#if 0
if (lg_chkerr(ret))
goto fail;
state->current_frequency = p->frequency;
#endif
}
ret = lgdt3306a_set_modulation(state, p);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_agc_setup(state, p);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_set_if(state, p);
if (lg_chkerr(ret))
goto fail;
/* spectral_inversion defaults already set for VSB and QAM */
ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_mpeg_mode_polarity(state,
state->cfg->tpclk_edge,
state->cfg->tpvalid_polarity);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_soft_reset(state);
if (lg_chkerr(ret))
goto fail;
#ifdef DBG_DUMP
lgdt3306a_DumpAllRegs(state);
#endif
state->current_frequency = p->frequency;
fail:
return ret;
}
static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
dbg_info("(%u, %d)\n",
state->current_frequency, state->current_modulation);
p->modulation = state->current_modulation;
p->frequency = state->current_frequency;
return 0;
}
static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
{
#if 1
return DVBFE_ALGO_CUSTOM;
#else
return DVBFE_ALGO_HW;
#endif
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
{
u8 val;
int ret;
u8 snrRef, maxPowerMan, nCombDet;
u16 fbDlyCir;
ret = lgdt3306a_read_reg(state, 0x21a1, &val);
if (ret)
return ret;
snrRef = val & 0x3f;
ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
if (ret)
return ret;
ret = lgdt3306a_read_reg(state, 0x2191, &val);
if (ret)
return ret;
nCombDet = (val & 0x80) >> 7;
ret = lgdt3306a_read_reg(state, 0x2180, &val);
if (ret)
return ret;
fbDlyCir = (val & 0x03) << 8;
ret = lgdt3306a_read_reg(state, 0x2181, &val);
if (ret)
return ret;
fbDlyCir |= val;
dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
snrRef, maxPowerMan, nCombDet, fbDlyCir);
/* Carrier offset sub loop bandwidth */
ret = lgdt3306a_read_reg(state, 0x1061, &val);
if (ret)
return ret;
val &= 0xf8;
if ((snrRef > 18) && (maxPowerMan > 0x68)
&& (nCombDet == 0x01)
&& ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
/* SNR is over 18dB and no ghosting */
val |= 0x00; /* final bandwidth = 0 */
} else {
val |= 0x04; /* final bandwidth = 4 */
}
ret = lgdt3306a_write_reg(state, 0x1061, val);
if (ret)
return ret;
/* Adjust Notch Filter */
ret = lgdt3306a_read_reg(state, 0x0024, &val);
if (ret)
return ret;
val &= 0x0f;
if (nCombDet == 0) { /* Turn on the Notch Filter */
val |= 0x50;
}
ret = lgdt3306a_write_reg(state, 0x0024, val);
if (ret)
return ret;
/* VSB Timing Recovery output normalization */
ret = lgdt3306a_read_reg(state, 0x103d, &val);
if (ret)
return ret;
val &= 0xcf;
val |= 0x20;
ret = lgdt3306a_write_reg(state, 0x103d, val);
return ret;
}
static enum lgdt3306a_modulation
lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
{
u8 val = 0;
int ret;
ret = lgdt3306a_read_reg(state, 0x0081, &val);
if (ret)
goto err;
if (val & 0x80) {
dbg_info("VSB\n");
return LG3306_VSB;
}
if (val & 0x08) {
ret = lgdt3306a_read_reg(state, 0x00a6, &val);
if (ret)
goto err;
val = val >> 2;
if (val & 0x01) {
dbg_info("QAM256\n");
return LG3306_QAM256;
}
dbg_info("QAM64\n");
return LG3306_QAM64;
}
err:
pr_warn("UNKNOWN\n");
return LG3306_UNKNOWN_MODE;
}
static enum lgdt3306a_lock_status
lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
enum lgdt3306a_lock_check whatLock)
{
u8 val = 0;
int ret;
enum lgdt3306a_modulation modeOper;
enum lgdt3306a_lock_status lockStatus;
modeOper = LG3306_UNKNOWN_MODE;
switch (whatLock) {
case LG3306_SYNC_LOCK:
{
ret = lgdt3306a_read_reg(state, 0x00a6, &val);
if (ret)
return ret;
if ((val & 0x80) == 0x80)
lockStatus = LG3306_LOCK;
else
lockStatus = LG3306_UNLOCK;
dbg_info("SYNC_LOCK=%x\n", lockStatus);
break;
}
case LG3306_AGC_LOCK:
{
ret = lgdt3306a_read_reg(state, 0x0080, &val);
if (ret)
return ret;
if ((val & 0x40) == 0x40)
lockStatus = LG3306_LOCK;
else
lockStatus = LG3306_UNLOCK;
dbg_info("AGC_LOCK=%x\n", lockStatus);
break;
}
case LG3306_TR_LOCK:
{
modeOper = lgdt3306a_check_oper_mode(state);
if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
ret = lgdt3306a_read_reg(state, 0x1094, &val);
if (ret)
return ret;
if ((val & 0x80) == 0x80)
lockStatus = LG3306_LOCK;
else
lockStatus = LG3306_UNLOCK;
} else
lockStatus = LG3306_UNKNOWN_LOCK;
dbg_info("TR_LOCK=%x\n", lockStatus);
break;
}
case LG3306_FEC_LOCK:
{
modeOper = lgdt3306a_check_oper_mode(state);
if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
ret = lgdt3306a_read_reg(state, 0x0080, &val);
if (ret)
return ret;
if ((val & 0x10) == 0x10)
lockStatus = LG3306_LOCK;
else
lockStatus = LG3306_UNLOCK;
} else
lockStatus = LG3306_UNKNOWN_LOCK;
dbg_info("FEC_LOCK=%x\n", lockStatus);
break;
}
default:
lockStatus = LG3306_UNKNOWN_LOCK;
pr_warn("UNKNOWN whatLock=%d\n", whatLock);
break;
}
return lockStatus;
}
static enum lgdt3306a_neverlock_status
lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
{
u8 val = 0;
int ret;
enum lgdt3306a_neverlock_status lockStatus;
ret = lgdt3306a_read_reg(state, 0x0080, &val);
if (ret)
return ret;
lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
dbg_info("NeverLock=%d", lockStatus);
return lockStatus;
}
static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
{
u8 val = 0;
int ret;
u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
/* Channel variation */
ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
if (ret)
return ret;
/* SNR of Frame sync */
ret = lgdt3306a_read_reg(state, 0x21a1, &val);
if (ret)
return ret;
snrRef = val & 0x3f;
/* Strong Main CIR */
ret = lgdt3306a_read_reg(state, 0x2199, &val);
if (ret)
return ret;
mainStrong = (val & 0x40) >> 6;
ret = lgdt3306a_read_reg(state, 0x0090, &val);
if (ret)
return ret;
aiccrejStatus = (val & 0xf0) >> 4;
dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
#if 0
/* Dynamic ghost exists */
if ((mainStrong == 0) && (currChDiffACQ > 0x70))
#endif
if (mainStrong == 0) {
ret = lgdt3306a_read_reg(state, 0x2135, &val);
if (ret)
return ret;
val &= 0x0f;
val |= 0xa0;
ret = lgdt3306a_write_reg(state, 0x2135, val);
if (ret)
return ret;
ret = lgdt3306a_read_reg(state, 0x2141, &val);
if (ret)
return ret;
val &= 0x3f;
val |= 0x80;
ret = lgdt3306a_write_reg(state, 0x2141, val);
if (ret)
return ret;
ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
if (ret)
return ret;
} else { /* Weak ghost or static channel */
ret = lgdt3306a_read_reg(state, 0x2135, &val);
if (ret)
return ret;
val &= 0x0f;
val |= 0x70;
ret = lgdt3306a_write_reg(state, 0x2135, val);
if (ret)
return ret;
ret = lgdt3306a_read_reg(state, 0x2141, &val);
if (ret)
return ret;
val &= 0x3f;
val |= 0x40;
ret = lgdt3306a_write_reg(state, 0x2141, val);
if (ret)
return ret;
ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
if (ret)
return ret;
}
return 0;
}
static enum lgdt3306a_lock_status
lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
int i;
for (i = 0; i < 2; i++) {
msleep(30);
syncLockStatus = lgdt3306a_check_lock_status(state,
LG3306_SYNC_LOCK);
if (syncLockStatus == LG3306_LOCK) {
dbg_info("locked(%d)\n", i);
return LG3306_LOCK;
}
}
dbg_info("not locked\n");
return LG3306_UNLOCK;
}
static enum lgdt3306a_lock_status
lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
int i;
for (i = 0; i < 2; i++) {
msleep(30);
FECLockStatus = lgdt3306a_check_lock_status(state,
LG3306_FEC_LOCK);
if (FECLockStatus == LG3306_LOCK) {
dbg_info("locked(%d)\n", i);
return FECLockStatus;
}
}
dbg_info("not locked\n");
return FECLockStatus;
}
static enum lgdt3306a_neverlock_status
lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
int i;
for (i = 0; i < 5; i++) {
msleep(30);
NLLockStatus = lgdt3306a_check_neverlock_status(state);
if (NLLockStatus == LG3306_NL_LOCK) {
dbg_info("NL_LOCK(%d)\n", i);
return NLLockStatus;
}
}
dbg_info("NLLockStatus=%d\n", NLLockStatus);
return NLLockStatus;
}
static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
{
u8 val;
int ret;
ret = lgdt3306a_read_reg(state, 0x00fa, &val);
if (ret)
return ret;
return val;
}
static const u32 valx_x10[] = {
10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
};
static const u32 log10x_x1000[] = {
0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
};
static u32 log10_x1000(u32 x)
{
u32 diff_val, step_val, step_log10;
u32 log_val = 0;
u32 i;
if (x <= 0)
return -1000000; /* signal error */
if (x == 10)
return 0; /* log(1)=0 */
if (x < 10) {
while (x < 10) {
x = x * 10;
log_val--;
}
} else { /* x > 10 */
while (x >= 100) {
x = x / 10;
log_val++;
}
}
log_val *= 1000;
if (x == 10) /* was our input an exact multiple of 10 */
return log_val; /* don't need to interpolate */
/* find our place on the log curve */
for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
if (valx_x10[i] >= x)
break;
}
if (i == ARRAY_SIZE(valx_x10))
return log_val + log10x_x1000[i - 1];
diff_val = x - valx_x10[i-1];
step_val = valx_x10[i] - valx_x10[i - 1];
step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
/* do a linear interpolation to get in-between values */
return log_val + log10x_x1000[i - 1] +
((diff_val*step_log10) / step_val);
}
static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
{
u32 mse; /* Mean-Square Error */
u32 pwr; /* Constelation power */
u32 snr_x100;
mse = (read_reg(state, 0x00ec) << 8) |
(read_reg(state, 0x00ed));
pwr = (read_reg(state, 0x00e8) << 8) |
(read_reg(state, 0x00e9));
if (mse == 0) /* no signal */
return 0;
snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
return snr_x100;
}
static enum lgdt3306a_lock_status
lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
{
int ret;
u8 cnt = 0;
u8 packet_error;
u32 snr;
for (cnt = 0; cnt < 10; cnt++) {
if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
dbg_info("no sync lock!\n");
return LG3306_UNLOCK;
}
msleep(20);
ret = lgdt3306a_pre_monitoring(state);
if (ret)
break;
packet_error = lgdt3306a_get_packet_error(state);
snr = lgdt3306a_calculate_snr_x100(state);
dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
if ((snr >= 1500) && (packet_error < 0xff))
return LG3306_LOCK;
}
dbg_info("not locked!\n");
return LG3306_UNLOCK;
}
static enum lgdt3306a_lock_status
lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
{
u8 cnt;
u8 packet_error;
u32 snr;
for (cnt = 0; cnt < 10; cnt++) {
if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
dbg_info("no fec lock!\n");
return LG3306_UNLOCK;
}
msleep(20);
packet_error = lgdt3306a_get_packet_error(state);
snr = lgdt3306a_calculate_snr_x100(state);
dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
if ((snr >= 1500) && (packet_error < 0xff))
return LG3306_LOCK;
}
dbg_info("not locked!\n");
return LG3306_UNLOCK;
}
static int lgdt3306a_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u16 strength = 0;
int ret = 0;
if (fe->ops.tuner_ops.get_rf_strength) {
ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
if (ret == 0)
dbg_info("strength=%d\n", strength);
else
dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
}
*status = 0;
if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
case QAM_AUTO:
if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
}
break;
case VSB_8:
if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
ret = lgdt3306a_monitor_vsb(state);
}
break;
default:
ret = -EINVAL;
}
if (*status & FE_HAS_SYNC) {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
}
return ret;
}
static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
state->snr = lgdt3306a_calculate_snr_x100(state);
/* report SNR in dB * 10 */
*snr = state->snr/10;
return 0;
}
static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
/*
* Calculate some sort of "strength" from SNR
*/
struct lgdt3306a_state *state = fe->demodulator_priv;
u8 val;
u16 snr; /* snr_x10 */
int ret;
u32 ref_snr; /* snr*100 */
u32 str;
*strength = 0;
switch (state->current_modulation) {
case VSB_8:
ref_snr = 1600; /* 16dB */
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
/* need to know actual modulation to set proper SNR baseline */
ret = lgdt3306a_read_reg(state, 0x00a6, &val);
if (lg_chkerr(ret))
goto fail;
if(val & 0x04)
ref_snr = 2800; /* QAM-256 28dB */
else
ref_snr = 2200; /* QAM-64 22dB */
break;
default:
return -EINVAL;
}
ret = fe->ops.read_snr(fe, &snr);
if (lg_chkerr(ret))
goto fail;
if (state->snr <= (ref_snr - 100))
str = 0;
else if (state->snr <= ref_snr)
str = (0xffff * 65) / 100; /* 65% */
else {
str = state->snr - ref_snr;
str /= 50;
str += 78; /* 78%-100% */
if (str > 100)
str = 100;
str = (0xffff * str) / 100;
}
*strength = (u16)str;
dbg_info("strength=%u\n", *strength);
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
u32 tmp;
*ber = 0;
#if 1
/* FGR - FIXME - I don't know what value is expected by dvb_core
* what is the scale of the value?? */
tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
*ber = tmp;
dbg_info("ber=%u\n", tmp);
#endif
return 0;
}
static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
*ucblocks = 0;
#if 1
/* FGR - FIXME - I don't know what value is expected by dvb_core
* what happens when value wraps? */
*ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
dbg_info("ucblocks=%u\n", *ucblocks);
#endif
return 0;
}
static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags, unsigned int *delay,
enum fe_status *status)
{
int ret = 0;
struct lgdt3306a_state *state = fe->demodulator_priv;
dbg_info("re_tune=%u\n", re_tune);
if (re_tune) {
state->current_frequency = -1; /* force re-tune */
ret = lgdt3306a_set_parameters(fe);
if (ret != 0)
return ret;
}
*delay = 125;
ret = lgdt3306a_read_status(fe, status);
return ret;
}
static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings
*fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 100;
dbg_info("\n");
return 0;
}
static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
{
enum fe_status status = 0;
int ret;
/* set frontend */
ret = lgdt3306a_set_parameters(fe);
if (ret)
goto error;
ret = lgdt3306a_read_status(fe, &status);
if (ret)
goto error;
/* check if we have a valid signal */
if (status & FE_HAS_LOCK)
return DVBFE_ALGO_SEARCH_SUCCESS;
else
return DVBFE_ALGO_SEARCH_AGAIN;
error:
dbg_info("failed (%d)\n", ret);
return DVBFE_ALGO_SEARCH_ERROR;
}
static void lgdt3306a_release(struct dvb_frontend *fe)
{
struct lgdt3306a_state *state = fe->demodulator_priv;
dbg_info("\n");
kfree(state);
}
static const struct dvb_frontend_ops lgdt3306a_ops;
struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
struct i2c_adapter *i2c_adap)
{
struct lgdt3306a_state *state = NULL;
int ret;
u8 val;
dbg_info("(%d-%04x)\n",
i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
config ? config->i2c_addr : 0);
state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
if (state == NULL)
goto fail;
state->cfg = config;
state->i2c_adap = i2c_adap;
memcpy(&state->frontend.ops, &lgdt3306a_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* verify that we're talking to a lg3306a */
/* FGR - NOTE - there is no obvious ChipId to check; we check
* some "known" bits after reset, but it's still just a guess */
ret = lgdt3306a_read_reg(state, 0x0000, &val);
if (lg_chkerr(ret))
goto fail;
if ((val & 0x74) != 0x74) {
pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
#if 0
/* FIXME - re-enable when we know this is right */
goto fail;
#endif
}
ret = lgdt3306a_read_reg(state, 0x0001, &val);
if (lg_chkerr(ret))
goto fail;
if ((val & 0xf6) != 0xc6) {
pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
#if 0
/* FIXME - re-enable when we know this is right */
goto fail;
#endif
}
ret = lgdt3306a_read_reg(state, 0x0002, &val);
if (lg_chkerr(ret))
goto fail;
if ((val & 0x73) != 0x03) {
pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
#if 0
/* FIXME - re-enable when we know this is right */
goto fail;
#endif
}
state->current_frequency = -1;
state->current_modulation = -1;
lgdt3306a_sleep(state);
return &state->frontend;
fail:
pr_warn("unable to detect LGDT3306A hardware\n");
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(lgdt3306a_attach);
#ifdef DBG_DUMP
static const short regtab[] = {
0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
0x0003, /* AGCRFOUT */
0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
0x0005, /* PLLINDIVSE */
0x0006, /* PLLCTRL[7:0] 11100001 */
0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
0x0008, /* STDOPMODE[7:0] 10000000 */
0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
0x000d, /* x SAMPLING4 */
0x000e, /* SAMFREQ[15:8] 00000000 */
0x000f, /* SAMFREQ[7:0] 00000000 */
0x0010, /* IFFREQ[15:8] 01100000 */
0x0011, /* IFFREQ[7:0] 00000000 */
0x0012, /* AGCEN AGCREFMO */
0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
0x0014, /* AGCFIXVALUE[7:0] 01111111 */
0x0015, /* AGCREF[15:8] 00001010 */
0x0016, /* AGCREF[7:0] 11100100 */
0x0017, /* AGCDELAY[7:0] 00100000 */
0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
0x0020, /* AICCDETTH[15:8] 01111100 */
0x0021, /* AICCDETTH[7:0] 00000000 */
0x0022, /* AICCOFFTH[15:8] 00000101 */
0x0023, /* AICCOFFTH[7:0] 11100000 */
0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
0x0032, /* DAGC1STEN DAGC1STER */
0x0033, /* DAGC1STREF[15:8] 00001010 */
0x0034, /* DAGC1STREF[7:0] 11100100 */
0x0035, /* DAGC2NDE */
0x0036, /* DAGC2NDREF[15:8] 00001010 */
0x0037, /* DAGC2NDREF[7:0] 10000000 */
0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
0x003d, /* 1'b1 SAMGEARS */
0x0040, /* SAMLFGMA */
0x0041, /* SAMLFBWM */
0x0044, /* 1'b1 CRGEARSHE */
0x0045, /* CRLFGMAN */
0x0046, /* CFLFBWMA */
0x0047, /* CRLFGMAN */
0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
0x0049, /* CRLFBWMA */
0x004a, /* CRLFBWMA */
0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
0x0071, /* TPSENB TPSSOPBITE */
0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
0x0078, /* NBERPOLY[31:24] 00000000 */
0x0079, /* NBERPOLY[23:16] 00000000 */
0x007a, /* NBERPOLY[15:8] 00000000 */
0x007b, /* NBERPOLY[7:0] 00000000 */
0x007c, /* NBERPED[31:24] 00000000 */
0x007d, /* NBERPED[23:16] 00000000 */
0x007e, /* NBERPED[15:8] 00000000 */
0x007f, /* NBERPED[7:0] 00000000 */
0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
0x0085, /* SPECINVST */
0x0088, /* SYSLOCKTIME[15:8] */
0x0089, /* SYSLOCKTIME[7:0] */
0x008c, /* FECLOCKTIME[15:8] */
0x008d, /* FECLOCKTIME[7:0] */
0x008e, /* AGCACCOUT[15:8] */
0x008f, /* AGCACCOUT[7:0] */
0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
0x0091, /* AICCVSYNC */
0x009c, /* CARRFREQOFFSET[15:8] */
0x009d, /* CARRFREQOFFSET[7:0] */
0x00a1, /* SAMFREQOFFSET[23:16] */
0x00a2, /* SAMFREQOFFSET[15:8] */
0x00a3, /* SAMFREQOFFSET[7:0] */
0x00a6, /* SYNCLOCK SYNCLOCKH */
#if 0 /* covered elsewhere */
0x00e8, /* CONSTPWR[15:8] */
0x00e9, /* CONSTPWR[7:0] */
0x00ea, /* BMSE[15:8] */
0x00eb, /* BMSE[7:0] */
0x00ec, /* MSE[15:8] */
0x00ed, /* MSE[7:0] */
0x00ee, /* CONSTI[7:0] */
0x00ef, /* CONSTQ[7:0] */
#endif
0x00f4, /* TPIFTPERRCNT[7:0] */
0x00f5, /* TPCORREC */
0x00f6, /* VBBER[15:8] */
0x00f7, /* VBBER[7:0] */
0x00f8, /* VABER[15:8] */
0x00f9, /* VABER[7:0] */
0x00fa, /* TPERRCNT[7:0] */
0x00fb, /* NBERLOCK x x x x x x x */
0x00fc, /* NBERVALUE[31:24] */
0x00fd, /* NBERVALUE[23:16] */
0x00fe, /* NBERVALUE[15:8] */
0x00ff, /* NBERVALUE[7:0] */
0x1000, /* 1'b0 WODAGCOU */
0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
0x103f, /* SAMZTEDSE */
0x105d, /* EQSTATUSE */
0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
0x1060, /* 1'b1 EQSTATUSE */
0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
0x106e, /* x x x x x CREPHNEN_ */
0x106f, /* CREPHNTH_V[7:0] 00010101 */
0x1072, /* CRSWEEPN */
0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
0x1080, /* DAFTSTATUS[1:0] x x x x x x */
0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
#if 0 /* SMART_ANT */
0x1f00, /* MODEDETE */
0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
0x1f03, /* NUMOFANT[7:0] 10000000 */
0x1f04, /* x SELMASK[6:0] x0000000 */
0x1f05, /* x SETMASK[6:0] x0000000 */
0x1f06, /* x TXDATA[6:0] x0000000 */
0x1f07, /* x CHNUMBER[6:0] x0000000 */
0x1f09, /* AGCTIME[23:16] 10011000 */
0x1f0a, /* AGCTIME[15:8] 10010110 */
0x1f0b, /* AGCTIME[7:0] 10000000 */
0x1f0c, /* ANTTIME[31:24] 00000000 */
0x1f0d, /* ANTTIME[23:16] 00000011 */
0x1f0e, /* ANTTIME[15:8] 10010000 */
0x1f0f, /* ANTTIME[7:0] 10010000 */
0x1f11, /* SYNCTIME[23:16] 10011000 */
0x1f12, /* SYNCTIME[15:8] 10010110 */
0x1f13, /* SYNCTIME[7:0] 10000000 */
0x1f14, /* SNRTIME[31:24] 00000001 */
0x1f15, /* SNRTIME[23:16] 01111101 */
0x1f16, /* SNRTIME[15:8] 01111000 */
0x1f17, /* SNRTIME[7:0] 01000000 */
0x1f19, /* FECTIME[23:16] 00000000 */
0x1f1a, /* FECTIME[15:8] 01110010 */
0x1f1b, /* FECTIME[7:0] 01110000 */
0x1f1d, /* FECTHD[7:0] 00000011 */
0x1f1f, /* SNRTHD[23:16] 00001000 */
0x1f20, /* SNRTHD[15:8] 01111111 */
0x1f21, /* SNRTHD[7:0] 10000101 */
0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
0x1f82, /* x x x SCANOPCD[4:0] */
0x1f83, /* x x x x MAINOPCD[3:0] */
0x1f84, /* x x RXDATA[13:8] */
0x1f85, /* RXDATA[7:0] */
0x1f86, /* x x SDTDATA[13:8] */
0x1f87, /* SDTDATA[7:0] */
0x1f89, /* ANTSNR[23:16] */
0x1f8a, /* ANTSNR[15:8] */
0x1f8b, /* ANTSNR[7:0] */
0x1f8c, /* x x x x ANTFEC[13:8] */
0x1f8d, /* ANTFEC[7:0] */
0x1f8e, /* MAXCNT[7:0] */
0x1f8f, /* SCANCNT[7:0] */
0x1f91, /* MAXPW[23:16] */
0x1f92, /* MAXPW[15:8] */
0x1f93, /* MAXPW[7:0] */
0x1f95, /* CURPWMSE[23:16] */
0x1f96, /* CURPWMSE[15:8] */
0x1f97, /* CURPWMSE[7:0] */
#endif /* SMART_ANT */
0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
0x212a, /* EQAUTOST */
0x2122, /* CHFAST[7:0] 01100000 */
0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
0x2162, /* AICCCTRLE */
0x2173, /* PHNCNFCNT[7:0] 00000100 */
0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
0x217e, /* CNFCNTTPIF[7:0] 00001000 */
0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
0x2180, /* x x x x x x FBDLYCIR[9:8] */
0x2181, /* FBDLYCIR[7:0] */
0x2185, /* MAXPWRMAIN[7:0] */
0x2191, /* NCOMBDET x x x x x x x */
0x2199, /* x MAINSTRON */
0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
0x21a1, /* x x SNRREF[5:0] */
0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
0x2847, /* ENNOSIGDE */
0x2849, /* 1'b1 1'b1 NOUSENOSI */
0x284a, /* EQINITWAITTIME[7:0] 01100100 */
0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
0x3031, /* FRAMELOC */
0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
0x30a9, /* VDLOCK_Q FRAMELOCK */
0x30aa, /* MPEGLOCK */
};
#define numDumpRegs (ARRAY_SIZE(regtab))
static u8 regval1[numDumpRegs] = {0, };
static u8 regval2[numDumpRegs] = {0, };
static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
{
memset(regval2, 0xff, sizeof(regval2));
lgdt3306a_DumpRegs(state);
}
static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
{
int i;
int sav_debug = debug;
if ((debug & DBG_DUMP) == 0)
return;
debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
lg_debug("\n");
for (i = 0; i < numDumpRegs; i++) {
lgdt3306a_read_reg(state, regtab[i], ®val1[i]);
if (regval1[i] != regval2[i]) {
lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
regval2[i] = regval1[i];
}
}
debug = sav_debug;
}
#endif /* DBG_DUMP */
static const struct dvb_frontend_ops lgdt3306a_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "LG Electronics LGDT3306A VSB/QAM Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
.init = lgdt3306a_init,
.sleep = lgdt3306a_fe_sleep,
/* if this is set, it overrides the default swzigzag */
.tune = lgdt3306a_tune,
.set_frontend = lgdt3306a_set_parameters,
.get_frontend = lgdt3306a_get_frontend,
.get_frontend_algo = lgdt3306a_get_frontend_algo,
.get_tune_settings = lgdt3306a_get_tune_settings,
.read_status = lgdt3306a_read_status,
.read_ber = lgdt3306a_read_ber,
.read_signal_strength = lgdt3306a_read_signal_strength,
.read_snr = lgdt3306a_read_snr,
.read_ucblocks = lgdt3306a_read_ucblocks,
.release = lgdt3306a_release,
.ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
.search = lgdt3306a_search,
};
static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
{
struct i2c_client *client = i2c_mux_priv(muxc);
struct lgdt3306a_state *state = i2c_get_clientdata(client);
return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
}
static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
{
struct i2c_client *client = i2c_mux_priv(muxc);
struct lgdt3306a_state *state = i2c_get_clientdata(client);
return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
}
static int lgdt3306a_probe(struct i2c_client *client)
{
struct lgdt3306a_config *config;
struct lgdt3306a_state *state;
struct dvb_frontend *fe;
int ret;
config = kmemdup(client->dev.platform_data,
sizeof(struct lgdt3306a_config), GFP_KERNEL);
if (config == NULL) {
ret = -ENOMEM;
goto fail;
}
config->i2c_addr = client->addr;
fe = lgdt3306a_attach(config, client->adapter);
if (fe == NULL) {
ret = -ENODEV;
goto err_fe;
}
i2c_set_clientdata(client, fe->demodulator_priv);
state = fe->demodulator_priv;
state->frontend.ops.release = NULL;
/* create mux i2c adapter for tuner */
state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
1, 0, I2C_MUX_LOCKED,
lgdt3306a_select, lgdt3306a_deselect);
if (!state->muxc) {
ret = -ENOMEM;
goto err_kfree;
}
state->muxc->priv = client;
ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
if (ret)
goto err_kfree;
/* create dvb_frontend */
fe->ops.i2c_gate_ctrl = NULL;
*config->i2c_adapter = state->muxc->adapter[0];
*config->fe = fe;
dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
return 0;
err_kfree:
kfree(state);
err_fe:
kfree(config);
fail:
dev_warn(&client->dev, "probe failed = %d\n", ret);
return ret;
}
static void lgdt3306a_remove(struct i2c_client *client)
{
struct lgdt3306a_state *state = i2c_get_clientdata(client);
i2c_mux_del_adapters(state->muxc);
state->frontend.ops.release = NULL;
state->frontend.demodulator_priv = NULL;
kfree(state->cfg);
kfree(state);
}
static const struct i2c_device_id lgdt3306a_id_table[] = {
{"lgdt3306a", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
static struct i2c_driver lgdt3306a_driver = {
.driver = {
.name = "lgdt3306a",
.suppress_bind_attrs = true,
},
.probe = lgdt3306a_probe,
.remove = lgdt3306a_remove,
.id_table = lgdt3306a_id_table,
};
module_i2c_driver(lgdt3306a_driver);
MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
MODULE_AUTHOR("Fred Richter <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.2");
| linux-master | drivers/media/dvb-frontends/lgdt3306a.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the ST STV0910 DVB-S/S2 demodulator.
*
* Copyright (C) 2014-2015 Ralph Metzler <[email protected]>
* Marcus Metzler <[email protected]>
* developed for Digital Devices GmbH
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "stv0910.h"
#include "stv0910_regs.h"
#define EXT_CLOCK 30000000
#define TUNING_DELAY 200
#define BER_SRC_S 0x20
#define BER_SRC_S2 0x20
static LIST_HEAD(stvlist);
enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
enum dvbs2_mod_cod {
DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
DVBS2_32APSK_9_10
};
enum fe_stv0910_mod_cod {
FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
FE_32APSK_910
};
enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
static inline u32 muldiv32(u32 a, u32 b, u32 c)
{
u64 tmp64;
tmp64 = (u64)a * (u64)b;
do_div(tmp64, c);
return (u32)tmp64;
}
struct stv_base {
struct list_head stvlist;
u8 adr;
struct i2c_adapter *i2c;
struct mutex i2c_lock; /* shared I2C access protect */
struct mutex reg_lock; /* shared register write protect */
int count;
u32 extclk;
u32 mclk;
};
struct stv {
struct stv_base *base;
struct dvb_frontend fe;
int nr;
u16 regoff;
u8 i2crpt;
u8 tscfgh;
u8 tsgeneral;
u8 tsspeed;
u8 single;
unsigned long tune_time;
s32 search_range;
u32 started;
u32 demod_lock_time;
enum receive_mode receive_mode;
u32 demod_timeout;
u32 fec_timeout;
u32 first_time_lock;
u8 demod_bits;
u32 symbol_rate;
u8 last_viterbi_rate;
enum fe_code_rate puncture_rate;
enum fe_stv0910_mod_cod mod_cod;
enum dvbs2_fectype fectype;
u32 pilots;
enum fe_stv0910_roll_off feroll_off;
int is_standard_broadcast;
int is_vcm;
u32 cur_scrambling_code;
u32 last_bernumerator;
u32 last_berdenominator;
u8 berscale;
u8 vth[6];
};
struct sinit_table {
u16 address;
u8 data;
};
struct slookup {
s16 value;
u32 reg_value;
};
static int write_reg(struct stv *state, u16 reg, u8 val)
{
struct i2c_adapter *adap = state->base->i2c;
u8 data[3] = {reg >> 8, reg & 0xff, val};
struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
.buf = data, .len = 3};
if (i2c_transfer(adap, &msg, 1) != 1) {
dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
state->base->adr, reg, val);
return -EIO;
}
return 0;
}
static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
u16 reg, u8 *val, int count)
{
u8 msg[2] = {reg >> 8, reg & 0xff};
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = msg, .len = 2},
{.addr = adr, .flags = I2C_M_RD,
.buf = val, .len = count } };
if (i2c_transfer(adapter, msgs, 2) != 2) {
dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
adr, reg);
return -EIO;
}
return 0;
}
static int read_reg(struct stv *state, u16 reg, u8 *val)
{
return i2c_read_regs16(state->base->i2c, state->base->adr,
reg, val, 1);
}
static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
{
return i2c_read_regs16(state->base->i2c, state->base->adr,
reg, val, len);
}
static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
{
int status;
u8 tmp;
mutex_lock(&state->base->reg_lock);
status = read_reg(state, reg, &tmp);
if (!status)
status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
mutex_unlock(&state->base->reg_lock);
return status;
}
static int write_field(struct stv *state, u32 field, u8 val)
{
int status;
u8 shift, mask, old, new;
status = read_reg(state, field >> 16, &old);
if (status)
return status;
mask = field & 0xff;
shift = (field >> 12) & 0xf;
new = ((val << shift) & mask) | (old & ~mask);
if (new == old)
return 0;
return write_reg(state, field >> 16, new);
}
#define SET_FIELD(_reg, _val) \
write_field(state, state->nr ? FSTV0910_P2_##_reg : \
FSTV0910_P1_##_reg, _val)
#define SET_REG(_reg, _val) \
write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
RSTV0910_P1_##_reg, _val)
#define GET_REG(_reg, _val) \
read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
RSTV0910_P1_##_reg, _val)
static const struct slookup s1_sn_lookup[] = {
{ 0, 9242 }, /* C/N= 0dB */
{ 5, 9105 }, /* C/N= 0.5dB */
{ 10, 8950 }, /* C/N= 1.0dB */
{ 15, 8780 }, /* C/N= 1.5dB */
{ 20, 8566 }, /* C/N= 2.0dB */
{ 25, 8366 }, /* C/N= 2.5dB */
{ 30, 8146 }, /* C/N= 3.0dB */
{ 35, 7908 }, /* C/N= 3.5dB */
{ 40, 7666 }, /* C/N= 4.0dB */
{ 45, 7405 }, /* C/N= 4.5dB */
{ 50, 7136 }, /* C/N= 5.0dB */
{ 55, 6861 }, /* C/N= 5.5dB */
{ 60, 6576 }, /* C/N= 6.0dB */
{ 65, 6330 }, /* C/N= 6.5dB */
{ 70, 6048 }, /* C/N= 7.0dB */
{ 75, 5768 }, /* C/N= 7.5dB */
{ 80, 5492 }, /* C/N= 8.0dB */
{ 85, 5224 }, /* C/N= 8.5dB */
{ 90, 4959 }, /* C/N= 9.0dB */
{ 95, 4709 }, /* C/N= 9.5dB */
{ 100, 4467 }, /* C/N=10.0dB */
{ 105, 4236 }, /* C/N=10.5dB */
{ 110, 4013 }, /* C/N=11.0dB */
{ 115, 3800 }, /* C/N=11.5dB */
{ 120, 3598 }, /* C/N=12.0dB */
{ 125, 3406 }, /* C/N=12.5dB */
{ 130, 3225 }, /* C/N=13.0dB */
{ 135, 3052 }, /* C/N=13.5dB */
{ 140, 2889 }, /* C/N=14.0dB */
{ 145, 2733 }, /* C/N=14.5dB */
{ 150, 2587 }, /* C/N=15.0dB */
{ 160, 2318 }, /* C/N=16.0dB */
{ 170, 2077 }, /* C/N=17.0dB */
{ 180, 1862 }, /* C/N=18.0dB */
{ 190, 1670 }, /* C/N=19.0dB */
{ 200, 1499 }, /* C/N=20.0dB */
{ 210, 1347 }, /* C/N=21.0dB */
{ 220, 1213 }, /* C/N=22.0dB */
{ 230, 1095 }, /* C/N=23.0dB */
{ 240, 992 }, /* C/N=24.0dB */
{ 250, 900 }, /* C/N=25.0dB */
{ 260, 826 }, /* C/N=26.0dB */
{ 270, 758 }, /* C/N=27.0dB */
{ 280, 702 }, /* C/N=28.0dB */
{ 290, 653 }, /* C/N=29.0dB */
{ 300, 613 }, /* C/N=30.0dB */
{ 310, 579 }, /* C/N=31.0dB */
{ 320, 550 }, /* C/N=32.0dB */
{ 330, 526 }, /* C/N=33.0dB */
{ 350, 490 }, /* C/N=33.0dB */
{ 400, 445 }, /* C/N=40.0dB */
{ 450, 430 }, /* C/N=45.0dB */
{ 500, 426 }, /* C/N=50.0dB */
{ 510, 425 } /* C/N=51.0dB */
};
static const struct slookup s2_sn_lookup[] = {
{ -30, 13950 }, /* C/N=-2.5dB */
{ -25, 13580 }, /* C/N=-2.5dB */
{ -20, 13150 }, /* C/N=-2.0dB */
{ -15, 12760 }, /* C/N=-1.5dB */
{ -10, 12345 }, /* C/N=-1.0dB */
{ -5, 11900 }, /* C/N=-0.5dB */
{ 0, 11520 }, /* C/N= 0dB */
{ 5, 11080 }, /* C/N= 0.5dB */
{ 10, 10630 }, /* C/N= 1.0dB */
{ 15, 10210 }, /* C/N= 1.5dB */
{ 20, 9790 }, /* C/N= 2.0dB */
{ 25, 9390 }, /* C/N= 2.5dB */
{ 30, 8970 }, /* C/N= 3.0dB */
{ 35, 8575 }, /* C/N= 3.5dB */
{ 40, 8180 }, /* C/N= 4.0dB */
{ 45, 7800 }, /* C/N= 4.5dB */
{ 50, 7430 }, /* C/N= 5.0dB */
{ 55, 7080 }, /* C/N= 5.5dB */
{ 60, 6720 }, /* C/N= 6.0dB */
{ 65, 6320 }, /* C/N= 6.5dB */
{ 70, 6060 }, /* C/N= 7.0dB */
{ 75, 5760 }, /* C/N= 7.5dB */
{ 80, 5480 }, /* C/N= 8.0dB */
{ 85, 5200 }, /* C/N= 8.5dB */
{ 90, 4930 }, /* C/N= 9.0dB */
{ 95, 4680 }, /* C/N= 9.5dB */
{ 100, 4425 }, /* C/N=10.0dB */
{ 105, 4210 }, /* C/N=10.5dB */
{ 110, 3980 }, /* C/N=11.0dB */
{ 115, 3765 }, /* C/N=11.5dB */
{ 120, 3570 }, /* C/N=12.0dB */
{ 125, 3315 }, /* C/N=12.5dB */
{ 130, 3140 }, /* C/N=13.0dB */
{ 135, 2980 }, /* C/N=13.5dB */
{ 140, 2820 }, /* C/N=14.0dB */
{ 145, 2670 }, /* C/N=14.5dB */
{ 150, 2535 }, /* C/N=15.0dB */
{ 160, 2270 }, /* C/N=16.0dB */
{ 170, 2035 }, /* C/N=17.0dB */
{ 180, 1825 }, /* C/N=18.0dB */
{ 190, 1650 }, /* C/N=19.0dB */
{ 200, 1485 }, /* C/N=20.0dB */
{ 210, 1340 }, /* C/N=21.0dB */
{ 220, 1212 }, /* C/N=22.0dB */
{ 230, 1100 }, /* C/N=23.0dB */
{ 240, 1000 }, /* C/N=24.0dB */
{ 250, 910 }, /* C/N=25.0dB */
{ 260, 836 }, /* C/N=26.0dB */
{ 270, 772 }, /* C/N=27.0dB */
{ 280, 718 }, /* C/N=28.0dB */
{ 290, 671 }, /* C/N=29.0dB */
{ 300, 635 }, /* C/N=30.0dB */
{ 310, 602 }, /* C/N=31.0dB */
{ 320, 575 }, /* C/N=32.0dB */
{ 330, 550 }, /* C/N=33.0dB */
{ 350, 517 }, /* C/N=35.0dB */
{ 400, 480 }, /* C/N=40.0dB */
{ 450, 466 }, /* C/N=45.0dB */
{ 500, 464 }, /* C/N=50.0dB */
{ 510, 463 }, /* C/N=51.0dB */
};
static const struct slookup padc_lookup[] = {
{ 0, 118000 }, /* PADC= +0dBm */
{ -100, 93600 }, /* PADC= -1dBm */
{ -200, 74500 }, /* PADC= -2dBm */
{ -300, 59100 }, /* PADC= -3dBm */
{ -400, 47000 }, /* PADC= -4dBm */
{ -500, 37300 }, /* PADC= -5dBm */
{ -600, 29650 }, /* PADC= -6dBm */
{ -700, 23520 }, /* PADC= -7dBm */
{ -900, 14850 }, /* PADC= -9dBm */
{ -1100, 9380 }, /* PADC=-11dBm */
{ -1300, 5910 }, /* PADC=-13dBm */
{ -1500, 3730 }, /* PADC=-15dBm */
{ -1700, 2354 }, /* PADC=-17dBm */
{ -1900, 1485 }, /* PADC=-19dBm */
{ -2000, 1179 }, /* PADC=-20dBm */
{ -2100, 1000 }, /* PADC=-21dBm */
};
/*********************************************************************
* Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
*********************************************************************/
static const u8 s2car_loop[] = {
/*
* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
* 20MPon 20MPoff 30MPon 30MPoff
*/
/* FE_QPSK_14 */
0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
/* FE_QPSK_13 */
0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
/* FE_QPSK_25 */
0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
/* FE_QPSK_12 */
0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
/* FE_QPSK_35 */
0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
/* FE_QPSK_23 */
0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
/* FE_QPSK_34 */
0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
/* FE_QPSK_45 */
0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
/* FE_QPSK_56 */
0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
/* FE_QPSK_89 */
0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
/* FE_QPSK_910 */
0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
/* FE_8PSK_35 */
0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
/* FE_8PSK_23 */
0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
/* FE_8PSK_34 */
0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
/* FE_8PSK_56 */
0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
/* FE_8PSK_89 */
0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
/* FE_8PSK_910 */
0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
/**********************************************************************
* Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
**********************************************************************/
/*
* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
* 20MPoff 30MPon 30MPoff
*/
/* FE_16APSK_23 */
0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
/* FE_16APSK_34 */
0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
/* FE_16APSK_45 */
0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
/* FE_16APSK_56 */
0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
/* FE_16APSK_89 */
0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
/* FE_16APSK_910 */
0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
/* FE_32APSK_34 */
0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
/* FE_32APSK_45 */
0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
/* FE_32APSK_56 */
0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
/* FE_32APSK_89 */
0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
/* FE_32APSK_910 */
0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
};
static u8 get_optim_cloop(struct stv *state,
enum fe_stv0910_mod_cod mod_cod, u32 pilots)
{
int i = 0;
if (mod_cod >= FE_32APSK_910)
i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
else if (mod_cod >= FE_QPSK_14)
i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
if (state->symbol_rate <= 3000000)
i += 0;
else if (state->symbol_rate <= 7000000)
i += 2;
else if (state->symbol_rate <= 15000000)
i += 4;
else if (state->symbol_rate <= 25000000)
i += 6;
else
i += 8;
if (!pilots)
i += 1;
return s2car_loop[i];
}
static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
{
int status = 0;
u8 symb_freq0;
u8 symb_freq1;
u8 symb_freq2;
u8 symb_freq3;
u8 tim_offs0;
u8 tim_offs1;
u8 tim_offs2;
u32 symbol_rate;
s32 timing_offset;
*p_symbol_rate = 0;
if (!state->started)
return status;
read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
((u32)symb_freq1 << 8) | (u32)symb_freq0;
timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
(u32)tim_offs0;
if ((timing_offset & (1 << 23)) != 0)
timing_offset |= 0xFF000000; /* Sign extent */
symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
*p_symbol_rate = symbol_rate + timing_offset;
return 0;
}
static int get_signal_parameters(struct stv *state)
{
u8 tmp;
if (!state->started)
return -EINVAL;
if (state->receive_mode == RCVMODE_DVBS2) {
read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
state->pilots = (tmp & 0x01) != 0;
state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
} else if (state->receive_mode == RCVMODE_DVBS) {
read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
state->puncture_rate = FEC_NONE;
switch (tmp & 0x1F) {
case 0x0d:
state->puncture_rate = FEC_1_2;
break;
case 0x12:
state->puncture_rate = FEC_2_3;
break;
case 0x15:
state->puncture_rate = FEC_3_4;
break;
case 0x18:
state->puncture_rate = FEC_5_6;
break;
case 0x1a:
state->puncture_rate = FEC_7_8;
break;
}
state->is_vcm = 0;
state->is_standard_broadcast = 1;
state->feroll_off = FE_SAT_35;
}
return 0;
}
static int tracking_optimization(struct stv *state)
{
u8 tmp;
read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
tmp &= ~0xC0;
switch (state->receive_mode) {
case RCVMODE_DVBS:
tmp |= 0x40;
break;
case RCVMODE_DVBS2:
tmp |= 0x80;
break;
default:
tmp |= 0xC0;
break;
}
write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
if (state->receive_mode == RCVMODE_DVBS2) {
/* Disable Reed-Solomon */
write_shared_reg(state,
RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
0x03);
if (state->fectype == DVBS2_64K) {
u8 aclc = get_optim_cloop(state, state->mod_cod,
state->pilots);
if (state->mod_cod <= FE_QPSK_910) {
write_reg(state, RSTV0910_P2_ACLC2S2Q +
state->regoff, aclc);
} else if (state->mod_cod <= FE_8PSK_910) {
write_reg(state, RSTV0910_P2_ACLC2S2Q +
state->regoff, 0x2a);
write_reg(state, RSTV0910_P2_ACLC2S28 +
state->regoff, aclc);
} else if (state->mod_cod <= FE_16APSK_910) {
write_reg(state, RSTV0910_P2_ACLC2S2Q +
state->regoff, 0x2a);
write_reg(state, RSTV0910_P2_ACLC2S216A +
state->regoff, aclc);
} else if (state->mod_cod <= FE_32APSK_910) {
write_reg(state, RSTV0910_P2_ACLC2S2Q +
state->regoff, 0x2a);
write_reg(state, RSTV0910_P2_ACLC2S232A +
state->regoff, aclc);
}
}
}
return 0;
}
static s32 table_lookup(const struct slookup *table,
int table_size, u32 reg_value)
{
s32 value;
int imin = 0;
int imax = table_size - 1;
int i;
s32 reg_diff;
/* Assumes Table[0].RegValue > Table[imax].RegValue */
if (reg_value >= table[0].reg_value) {
value = table[0].value;
} else if (reg_value <= table[imax].reg_value) {
value = table[imax].value;
} else {
while ((imax - imin) > 1) {
i = (imax + imin) / 2;
if ((table[imin].reg_value >= reg_value) &&
(reg_value >= table[i].reg_value))
imax = i;
else
imin = i;
}
reg_diff = table[imax].reg_value - table[imin].reg_value;
value = table[imin].value;
if (reg_diff != 0)
value += ((s32)(reg_value - table[imin].reg_value) *
(s32)(table[imax].value
- table[imin].value))
/ (reg_diff);
}
return value;
}
static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
{
u8 data0;
u8 data1;
u16 data;
int n_lookup;
const struct slookup *lookup;
*signal_to_noise = 0;
if (!state->started)
return -EINVAL;
if (state->receive_mode == RCVMODE_DVBS2) {
read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
&data1);
read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
&data0);
n_lookup = ARRAY_SIZE(s2_sn_lookup);
lookup = s2_sn_lookup;
} else {
read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
&data1);
read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
&data0);
n_lookup = ARRAY_SIZE(s1_sn_lookup);
lookup = s1_sn_lookup;
}
data = (((u16)data1) << 8) | (u16)data0;
*signal_to_noise = table_lookup(lookup, n_lookup, data);
return 0;
}
static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
u32 *berdenominator)
{
u8 regs[3];
int status = read_regs(state,
RSTV0910_P2_ERRCNT12 + state->regoff,
regs, 3);
if (status)
return -EINVAL;
if ((regs[0] & 0x80) == 0) {
state->last_berdenominator = 1ULL << ((state->berscale * 2) +
10 + 3);
state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
((u32)regs[1] << 8) | regs[2];
if (state->last_bernumerator < 256 && state->berscale < 6) {
state->berscale += 1;
status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
state->regoff,
0x20 | state->berscale);
} else if (state->last_bernumerator > 1024 &&
state->berscale > 2) {
state->berscale -= 1;
status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
state->regoff, 0x20 |
state->berscale);
}
}
*bernumerator = state->last_bernumerator;
*berdenominator = state->last_berdenominator;
return 0;
}
static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
{
static const u32 nbch[][2] = {
{ 0, 0}, /* DUMMY_PLF */
{16200, 3240}, /* QPSK_1_4, */
{21600, 5400}, /* QPSK_1_3, */
{25920, 6480}, /* QPSK_2_5, */
{32400, 7200}, /* QPSK_1_2, */
{38880, 9720}, /* QPSK_3_5, */
{43200, 10800}, /* QPSK_2_3, */
{48600, 11880}, /* QPSK_3_4, */
{51840, 12600}, /* QPSK_4_5, */
{54000, 13320}, /* QPSK_5_6, */
{57600, 14400}, /* QPSK_8_9, */
{58320, 16000}, /* QPSK_9_10, */
{43200, 9720}, /* 8PSK_3_5, */
{48600, 10800}, /* 8PSK_2_3, */
{51840, 11880}, /* 8PSK_3_4, */
{54000, 13320}, /* 8PSK_5_6, */
{57600, 14400}, /* 8PSK_8_9, */
{58320, 16000}, /* 8PSK_9_10, */
{43200, 10800}, /* 16APSK_2_3, */
{48600, 11880}, /* 16APSK_3_4, */
{51840, 12600}, /* 16APSK_4_5, */
{54000, 13320}, /* 16APSK_5_6, */
{57600, 14400}, /* 16APSK_8_9, */
{58320, 16000}, /* 16APSK_9_10 */
{48600, 11880}, /* 32APSK_3_4, */
{51840, 12600}, /* 32APSK_4_5, */
{54000, 13320}, /* 32APSK_5_6, */
{57600, 14400}, /* 32APSK_8_9, */
{58320, 16000}, /* 32APSK_9_10 */
};
if (mod_cod >= DVBS2_QPSK_1_4 &&
mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
return nbch[mod_cod][fectype];
return 64800;
}
static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
u32 *berdenominator)
{
u8 regs[3];
int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
regs, 3);
if (status)
return -EINVAL;
if ((regs[0] & 0x80) == 0) {
state->last_berdenominator =
dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
state->fectype) <<
(state->berscale * 2);
state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
((u32)regs[1] << 8) | regs[2];
if (state->last_bernumerator < 256 && state->berscale < 6) {
state->berscale += 1;
write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
0x20 | state->berscale);
} else if (state->last_bernumerator > 1024 &&
state->berscale > 2) {
state->berscale -= 1;
write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
0x20 | state->berscale);
}
}
*bernumerator = state->last_bernumerator;
*berdenominator = state->last_berdenominator;
return status;
}
static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
u32 *berdenominator)
{
*bernumerator = 0;
*berdenominator = 1;
switch (state->receive_mode) {
case RCVMODE_DVBS:
return get_bit_error_rate_s(state,
bernumerator, berdenominator);
case RCVMODE_DVBS2:
return get_bit_error_rate_s2(state,
bernumerator, berdenominator);
default:
break;
}
return 0;
}
static int set_mclock(struct stv *state, u32 master_clock)
{
u32 idf = 1;
u32 odf = 4;
u32 quartz = state->base->extclk / 1000000;
u32 fphi = master_clock / 1000000;
u32 ndiv = (fphi * odf * idf) / quartz;
u32 cp = 7;
u32 fvco;
if (ndiv >= 7 && ndiv <= 71)
cp = 7;
else if (ndiv >= 72 && ndiv <= 79)
cp = 8;
else if (ndiv >= 80 && ndiv <= 87)
cp = 9;
else if (ndiv >= 88 && ndiv <= 95)
cp = 10;
else if (ndiv >= 96 && ndiv <= 103)
cp = 11;
else if (ndiv >= 104 && ndiv <= 111)
cp = 12;
else if (ndiv >= 112 && ndiv <= 119)
cp = 13;
else if (ndiv >= 120 && ndiv <= 127)
cp = 14;
else if (ndiv >= 128 && ndiv <= 135)
cp = 15;
else if (ndiv >= 136 && ndiv <= 143)
cp = 16;
else if (ndiv >= 144 && ndiv <= 151)
cp = 17;
else if (ndiv >= 152 && ndiv <= 159)
cp = 18;
else if (ndiv >= 160 && ndiv <= 167)
cp = 19;
else if (ndiv >= 168 && ndiv <= 175)
cp = 20;
else if (ndiv >= 176 && ndiv <= 183)
cp = 21;
else if (ndiv >= 184 && ndiv <= 191)
cp = 22;
else if (ndiv >= 192 && ndiv <= 199)
cp = 23;
else if (ndiv >= 200 && ndiv <= 207)
cp = 24;
else if (ndiv >= 208 && ndiv <= 215)
cp = 25;
else if (ndiv >= 216 && ndiv <= 223)
cp = 26;
else if (ndiv >= 224 && ndiv <= 225)
cp = 27;
write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
write_reg(state, RSTV0910_NCOARSE2, odf);
write_reg(state, RSTV0910_NCOARSE1, ndiv);
fvco = (quartz * 2 * ndiv) / idf;
state->base->mclk = fvco / (2 * odf) * 1000000;
return 0;
}
static int stop(struct stv *state)
{
if (state->started) {
u8 tmp;
write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
state->tscfgh | 0x01);
read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
tmp &= ~0x01; /* release reset DVBS2 packet delin */
write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
/* Blind optim*/
write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
/* Stop the demod */
write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
state->started = 0;
}
state->receive_mode = RCVMODE_NONE;
return 0;
}
static void set_pls(struct stv *state, u32 pls_code)
{
if (pls_code == state->cur_scrambling_code)
return;
/* PLROOT2 bit 2 = gold code */
write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
pls_code & 0xff);
write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
(pls_code >> 8) & 0xff);
write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
0x04 | ((pls_code >> 16) & 0x03));
state->cur_scrambling_code = pls_code;
}
static void set_isi(struct stv *state, u32 isi)
{
if (isi == NO_STREAM_ID_FILTER)
return;
if (isi == 0x80000000) {
SET_FIELD(FORCE_CONTINUOUS, 1);
SET_FIELD(TSOUT_NOSYNC, 1);
} else {
SET_FIELD(FILTER_EN, 1);
write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
isi & 0xff);
write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
}
SET_FIELD(ALGOSWRST, 1);
SET_FIELD(ALGOSWRST, 0);
}
static void set_stream_modes(struct stv *state,
struct dtv_frontend_properties *p)
{
set_isi(state, p->stream_id);
set_pls(state, p->scrambling_sequence_index);
}
static int init_search_param(struct stv *state,
struct dtv_frontend_properties *p)
{
SET_FIELD(FORCE_CONTINUOUS, 0);
SET_FIELD(FRAME_MODE, 0);
SET_FIELD(FILTER_EN, 0);
SET_FIELD(TSOUT_NOSYNC, 0);
SET_FIELD(TSFIFO_EMBINDVB, 0);
SET_FIELD(TSDEL_SYNCBYTE, 0);
SET_REG(UPLCCST0, 0xe0);
SET_FIELD(TSINS_TOKEN, 0);
SET_FIELD(HYSTERESIS_THRESHOLD, 0);
SET_FIELD(ISIOBS_MODE, 1);
set_stream_modes(state, p);
return 0;
}
static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
{
u8 val;
switch (rate) {
case FEC_1_2:
val = 0x01;
break;
case FEC_2_3:
val = 0x02;
break;
case FEC_3_4:
val = 0x04;
break;
case FEC_5_6:
val = 0x08;
break;
case FEC_7_8:
val = 0x20;
break;
case FEC_NONE:
default:
val = 0x2f;
break;
}
return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
}
static int set_vth_default(struct stv *state)
{
state->vth[0] = 0xd7;
state->vth[1] = 0x85;
state->vth[2] = 0x58;
state->vth[3] = 0x3a;
state->vth[4] = 0x34;
state->vth[5] = 0x28;
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
return 0;
}
static int set_vth(struct stv *state)
{
static const struct slookup vthlookup_table[] = {
{250, 8780}, /* C/N= 1.5dB */
{100, 7405}, /* C/N= 4.5dB */
{40, 6330}, /* C/N= 6.5dB */
{12, 5224}, /* C/N= 8.5dB */
{5, 4236} /* C/N=10.5dB */
};
int i;
u8 tmp[2];
int status = read_regs(state,
RSTV0910_P2_NNOSDATAT1 + state->regoff,
tmp, 2);
u16 reg_value = (tmp[0] << 8) | tmp[1];
s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
reg_value);
for (i = 0; i < 6; i += 1)
if (state->vth[i] > vth)
state->vth[i] = vth;
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
return status;
}
static int start(struct stv *state, struct dtv_frontend_properties *p)
{
s32 freq;
u8 reg_dmdcfgmd;
u16 symb;
if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
return -EINVAL;
state->receive_mode = RCVMODE_NONE;
state->demod_lock_time = 0;
/* Demod Stop */
if (state->started)
write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
init_search_param(state, p);
if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
state->demod_timeout = 3000;
state->fec_timeout = 2000;
} else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
state->demod_timeout = 2500;
state->fec_timeout = 1300;
} else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
state->demod_timeout = 1000;
state->fec_timeout = 650;
} else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
state->demod_timeout = 700;
state->fec_timeout = 350;
} else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
state->demod_timeout = 400;
state->fec_timeout = 200;
} else { /* SR >=20Msps */
state->demod_timeout = 300;
state->fec_timeout = 200;
}
/* Set the Init Symbol rate */
symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
((symb >> 8) & 0x7F));
write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
state->demod_bits |= 0x80;
write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
/* FE_STV0910_SetSearchStandard */
read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
reg_dmdcfgmd |= 0xC0);
write_shared_reg(state,
RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
/* Disable DSS */
write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
enable_puncture_rate(state, FEC_NONE);
/* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
/*
* Reset CAR3, bug DVBS2->DVBS1 lock
* Note: The bit is only pulsed -> no lock on shared register needed
*/
write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
write_reg(state, RSTV0910_TSTRES0, 0);
set_vth_default(state);
/* Reset demod */
write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
if (p->symbol_rate <= 5000000)
freq = (state->search_range / 2000) + 80;
else
freq = (state->search_range / 2000) + 1600;
freq = (freq << 16) / (state->base->mclk / 1000);
write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
(freq >> 8) & 0xff);
write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
/* CFR Low Setting */
freq = -freq;
write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
(freq >> 8) & 0xff);
write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
/* init the demod frequency offset to 0 */
write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
/* Trigger acq */
write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
state->demod_lock_time += TUNING_DELAY;
state->started = 1;
return 0;
}
static int init_diseqc(struct stv *state)
{
u16 offs = state->nr ? 0x40 : 0; /* Address offset */
u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
/* Disable receiver */
write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
return 0;
}
static int probe(struct stv *state)
{
u8 id;
state->receive_mode = RCVMODE_NONE;
state->started = 0;
if (read_reg(state, RSTV0910_MID, &id) < 0)
return -ENODEV;
if (id != 0x51)
return -EINVAL;
/* Configure the I2C repeater to off */
write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
/* Configure the I2C repeater to off */
write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
/* Set the I2C to oversampling ratio */
write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
if (state->single)
write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
else
write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
write_reg(state, RSTV0910_TSTRES0, 0x00);
write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
set_mclock(state, 135000000);
/* TS output */
write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
/* Reset stream merger */
write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
init_diseqc(state);
return 0;
}
static int gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv *state = fe->demodulator_priv;
u8 i2crpt = state->i2crpt & ~0x86;
/*
* mutex_lock note: Concurrent I2C gate bus accesses must be
* prevented (STV0910 = dual demod on a single IC with a single I2C
* gate/bus, and two tuners attached), similar to most (if not all)
* other I2C host interfaces/buses.
*
* enable=1 (open I2C gate) will grab the lock
* enable=0 (close I2C gate) releases the lock
*/
if (enable) {
mutex_lock(&state->base->i2c_lock);
i2crpt |= 0x80;
} else {
i2crpt |= 0x02;
}
if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
RSTV0910_P1_I2CRPT, i2crpt) < 0) {
/* don't hold the I2C bus lock on failure */
if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
mutex_unlock(&state->base->i2c_lock);
dev_err(&state->base->i2c->dev,
"%s() write_reg failure (enable=%d)\n",
__func__, enable);
return -EIO;
}
state->i2crpt = i2crpt;
if (!enable)
if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
mutex_unlock(&state->base->i2c_lock);
return 0;
}
static void release(struct dvb_frontend *fe)
{
struct stv *state = fe->demodulator_priv;
state->base->count--;
if (state->base->count == 0) {
list_del(&state->base->stvlist);
kfree(state->base);
}
kfree(state);
}
static int set_parameters(struct dvb_frontend *fe)
{
int stat = 0;
struct stv *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
stop(state);
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
state->symbol_rate = p->symbol_rate;
stat = start(state, p);
return stat;
}
static int manage_matype_info(struct stv *state)
{
if (!state->started)
return -EINVAL;
if (state->receive_mode == RCVMODE_DVBS2) {
u8 bbheader[2];
read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
bbheader, 2);
state->feroll_off =
(enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
state->is_vcm = (bbheader[0] & 0x10) == 0;
state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
} else if (state->receive_mode == RCVMODE_DVBS) {
state->is_vcm = 0;
state->is_standard_broadcast = 1;
state->feroll_off = FE_SAT_35;
}
return 0;
}
static int read_snr(struct dvb_frontend *fe)
{
struct stv *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
s32 snrval;
if (!get_signal_to_noise(state, &snrval)) {
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
} else {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int read_ber(struct dvb_frontend *fe)
{
struct stv *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 n, d;
get_bit_error_rate(state, &n, &d);
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_error.stat[0].uvalue = n;
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_count.stat[0].uvalue = d;
return 0;
}
static void read_signal_strength(struct dvb_frontend *fe)
{
struct stv *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
u8 reg[2];
u16 agc;
s32 padc, power = 0;
int i;
read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
agc = (((u32)reg[0]) << 8) | reg[1];
for (i = 0; i < 5; i += 1) {
read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
power += (u32)reg[0] * (u32)reg[0]
+ (u32)reg[1] * (u32)reg[1];
usleep_range(3000, 4000);
}
power /= 5;
padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
p->strength.stat[0].svalue = (padc - agc);
}
static int read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stv *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u8 dmd_state = 0;
u8 dstatus = 0;
enum receive_mode cur_receive_mode = RCVMODE_NONE;
u32 feclock = 0;
*status = 0;
read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
if (dmd_state & 0x40) {
read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
if (dstatus & 0x08)
cur_receive_mode = (dmd_state & 0x20) ?
RCVMODE_DVBS : RCVMODE_DVBS2;
}
if (cur_receive_mode == RCVMODE_NONE) {
set_vth(state);
/* reset signal statistics */
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
*status |= (FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC);
if (state->receive_mode == RCVMODE_NONE) {
state->receive_mode = cur_receive_mode;
state->demod_lock_time = jiffies;
state->first_time_lock = 1;
get_signal_parameters(state);
tracking_optimization(state);
write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
state->tscfgh);
usleep_range(3000, 4000);
write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
state->tscfgh | 0x01);
write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
state->tscfgh);
}
if (dmd_state & 0x40) {
if (state->receive_mode == RCVMODE_DVBS2) {
u8 pdelstatus;
read_reg(state,
RSTV0910_P2_PDELSTATUS1 + state->regoff,
&pdelstatus);
feclock = (pdelstatus & 0x02) != 0;
} else {
u8 vstatus;
read_reg(state,
RSTV0910_P2_VSTATUSVIT + state->regoff,
&vstatus);
feclock = (vstatus & 0x08) != 0;
}
}
if (feclock) {
*status |= FE_HAS_LOCK;
if (state->first_time_lock) {
u8 tmp;
state->first_time_lock = 0;
manage_matype_info(state);
if (state->receive_mode == RCVMODE_DVBS2) {
/*
* FSTV0910_P2_MANUALSX_ROLLOFF,
* FSTV0910_P2_MANUALS2_ROLLOFF = 0
*/
state->demod_bits &= ~0x84;
write_reg(state,
RSTV0910_P2_DEMOD + state->regoff,
state->demod_bits);
read_reg(state,
RSTV0910_P2_PDELCTRL2 + state->regoff,
&tmp);
/* reset DVBS2 packet delinator error counter */
tmp |= 0x40;
write_reg(state,
RSTV0910_P2_PDELCTRL2 + state->regoff,
tmp);
/* reset DVBS2 packet delinator error counter */
tmp &= ~0x40;
write_reg(state,
RSTV0910_P2_PDELCTRL2 + state->regoff,
tmp);
state->berscale = 2;
state->last_bernumerator = 0;
state->last_berdenominator = 1;
/* force to PRE BCH Rate */
write_reg(state,
RSTV0910_P2_ERRCTRL1 + state->regoff,
BER_SRC_S2 | state->berscale);
} else {
state->berscale = 2;
state->last_bernumerator = 0;
state->last_berdenominator = 1;
/* force to PRE RS Rate */
write_reg(state,
RSTV0910_P2_ERRCTRL1 + state->regoff,
BER_SRC_S | state->berscale);
}
/* Reset the Total packet counter */
write_reg(state,
RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
/*
* Reset the packet Error counter2 (and Set it to
* infinite error count mode)
*/
write_reg(state,
RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
set_vth_default(state);
if (state->receive_mode == RCVMODE_DVBS)
enable_puncture_rate(state,
state->puncture_rate);
}
/* Use highest signaled ModCod for quality */
if (state->is_vcm) {
u8 tmp;
enum fe_stv0910_mod_cod mod_cod;
read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
&tmp);
mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
if (mod_cod > state->mod_cod)
state->mod_cod = mod_cod;
}
}
/* read signal statistics */
/* read signal strength */
read_signal_strength(fe);
/* read carrier/noise on FE_HAS_CARRIER */
if (*status & FE_HAS_CARRIER)
read_snr(fe);
else
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* read ber */
if (*status & FE_HAS_VITERBI) {
read_ber(fe);
} else {
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv *state = fe->demodulator_priv;
u8 tmp;
u32 symbolrate;
if (state->receive_mode == RCVMODE_DVBS2) {
u32 mc;
const enum fe_modulation modcod2mod[0x20] = {
QPSK, QPSK, QPSK, QPSK,
QPSK, QPSK, QPSK, QPSK,
QPSK, QPSK, QPSK, QPSK,
PSK_8, PSK_8, PSK_8, PSK_8,
PSK_8, PSK_8, APSK_16, APSK_16,
APSK_16, APSK_16, APSK_16, APSK_16,
APSK_32, APSK_32, APSK_32, APSK_32,
APSK_32,
};
const enum fe_code_rate modcod2fec[0x20] = {
FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
FEC_9_10
};
read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
mc = ((tmp & 0x7c) >> 2);
p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
p->modulation = modcod2mod[mc];
p->fec_inner = modcod2fec[mc];
} else if (state->receive_mode == RCVMODE_DVBS) {
read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
switch (tmp & 0x1F) {
case 0x0d:
p->fec_inner = FEC_1_2;
break;
case 0x12:
p->fec_inner = FEC_2_3;
break;
case 0x15:
p->fec_inner = FEC_3_4;
break;
case 0x18:
p->fec_inner = FEC_5_6;
break;
case 0x1a:
p->fec_inner = FEC_7_8;
break;
default:
p->fec_inner = FEC_NONE;
break;
}
p->rolloff = ROLLOFF_35;
}
if (state->receive_mode != RCVMODE_NONE) {
get_cur_symbol_rate(state, &symbolrate);
p->symbol_rate = symbolrate;
}
return 0;
}
static int tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags,
unsigned int *delay, enum fe_status *status)
{
struct stv *state = fe->demodulator_priv;
int r;
if (re_tune) {
r = set_parameters(fe);
if (r)
return r;
state->tune_time = jiffies;
}
r = read_status(fe, status);
if (r)
return r;
if (*status & FE_HAS_LOCK)
return 0;
*delay = HZ;
return 0;
}
static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct stv *state = fe->demodulator_priv;
u16 offs = state->nr ? 0x40 : 0;
switch (tone) {
case SEC_TONE_ON:
return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
case SEC_TONE_OFF:
return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
default:
break;
}
return -EINVAL;
}
static int wait_dis(struct stv *state, u8 flag, u8 val)
{
int i;
u8 stat;
u16 offs = state->nr ? 0x40 : 0;
for (i = 0; i < 10; i++) {
read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
if ((stat & flag) == val)
return 0;
usleep_range(10000, 11000);
}
return -ETIMEDOUT;
}
static int send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct stv *state = fe->demodulator_priv;
int i;
SET_FIELD(DISEQC_MODE, 2);
SET_FIELD(DIS_PRECHARGE, 1);
for (i = 0; i < cmd->msg_len; i++) {
wait_dis(state, 0x40, 0x00);
SET_REG(DISTXFIFO, cmd->msg[i]);
}
SET_FIELD(DIS_PRECHARGE, 0);
wait_dis(state, 0x20, 0x20);
return 0;
}
static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
{
struct stv *state = fe->demodulator_priv;
u8 value;
if (burst == SEC_MINI_A) {
SET_FIELD(DISEQC_MODE, 3);
value = 0x00;
} else {
SET_FIELD(DISEQC_MODE, 2);
value = 0xFF;
}
SET_FIELD(DIS_PRECHARGE, 1);
wait_dis(state, 0x40, 0x00);
SET_REG(DISTXFIFO, value);
SET_FIELD(DIS_PRECHARGE, 0);
wait_dis(state, 0x20, 0x20);
return 0;
}
static int sleep(struct dvb_frontend *fe)
{
struct stv *state = fe->demodulator_priv;
stop(state);
return 0;
}
static const struct dvb_frontend_ops stv0910_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
.info = {
.name = "ST STV0910",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.symbol_rate_min = 100000,
.symbol_rate_max = 70000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_2G_MODULATION |
FE_CAN_MULTISTREAM
},
.sleep = sleep,
.release = release,
.i2c_gate_ctrl = gate_ctrl,
.set_frontend = set_parameters,
.get_frontend_algo = get_algo,
.get_frontend = get_frontend,
.tune = tune,
.read_status = read_status,
.set_tone = set_tone,
.diseqc_send_master_cmd = send_master_cmd,
.diseqc_send_burst = send_burst,
};
static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
{
struct stv_base *p;
list_for_each_entry(p, &stvlist, stvlist)
if (p->i2c == i2c && p->adr == adr)
return p;
return NULL;
}
static void stv0910_init_stats(struct stv *state)
{
struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
p->strength.len = 1;
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.len = 1;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.len = 1;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.len = 1;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
struct stv0910_cfg *cfg,
int nr)
{
struct stv *state;
struct stv_base *base;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
/* use safe tsspeed value if unspecified through stv0910_cfg */
state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
state->nr = nr;
state->regoff = state->nr ? 0 : 0x200;
state->search_range = 16000000;
state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
state->receive_mode = RCVMODE_NONE;
state->cur_scrambling_code = (~0U);
state->single = cfg->single ? 1 : 0;
base = match_base(i2c, cfg->adr);
if (base) {
base->count++;
state->base = base;
} else {
base = kzalloc(sizeof(*base), GFP_KERNEL);
if (!base)
goto fail;
base->i2c = i2c;
base->adr = cfg->adr;
base->count = 1;
base->extclk = cfg->clk ? cfg->clk : 30000000;
mutex_init(&base->i2c_lock);
mutex_init(&base->reg_lock);
state->base = base;
if (probe(state) < 0) {
dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
cfg->adr, dev_name(&i2c->dev));
kfree(base);
goto fail;
}
list_add(&base->stvlist, &stvlist);
}
state->fe.ops = stv0910_ops;
state->fe.demodulator_priv = state;
state->nr = nr;
dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
stv0910_init_stats(state);
return &state->fe;
fail:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0910_attach);
MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/stv0910.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Samsung S5H1409 VSB/QAM demodulator driver
Copyright (C) 2006 Steven Toth <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "s5h1409.h"
struct s5h1409_state {
struct i2c_adapter *i2c;
/* configuration settings */
const struct s5h1409_config *config;
struct dvb_frontend frontend;
/* previous uncorrected block counter */
enum fe_modulation current_modulation;
u32 current_frequency;
int if_freq;
u32 is_qam_locked;
/* QAM tuning state goes through the following state transitions */
#define QAM_STATE_UNTUNED 0
#define QAM_STATE_TUNING_STARTED 1
#define QAM_STATE_INTERLEAVE_SET 2
#define QAM_STATE_QAM_OPTIMIZED_L1 3
#define QAM_STATE_QAM_OPTIMIZED_L2 4
#define QAM_STATE_QAM_OPTIMIZED_L3 5
u8 qam_state;
};
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
#define dprintk if (debug) printk
/* Register values to initialise the demod, this will set VSB by default */
static struct init_tab {
u8 reg;
u16 data;
} init_tab[] = {
{ 0x00, 0x0071, },
{ 0x01, 0x3213, },
{ 0x09, 0x0025, },
{ 0x1c, 0x001d, },
{ 0x1f, 0x002d, },
{ 0x20, 0x001d, },
{ 0x22, 0x0022, },
{ 0x23, 0x0020, },
{ 0x29, 0x110f, },
{ 0x2a, 0x10b4, },
{ 0x2b, 0x10ae, },
{ 0x2c, 0x0031, },
{ 0x31, 0x010d, },
{ 0x32, 0x0100, },
{ 0x44, 0x0510, },
{ 0x54, 0x0104, },
{ 0x58, 0x2222, },
{ 0x59, 0x1162, },
{ 0x5a, 0x3211, },
{ 0x5d, 0x0370, },
{ 0x5e, 0x0296, },
{ 0x61, 0x0010, },
{ 0x63, 0x4a00, },
{ 0x65, 0x0800, },
{ 0x71, 0x0003, },
{ 0x72, 0x0470, },
{ 0x81, 0x0002, },
{ 0x82, 0x0600, },
{ 0x86, 0x0002, },
{ 0x8a, 0x2c38, },
{ 0x8b, 0x2a37, },
{ 0x92, 0x302f, },
{ 0x93, 0x3332, },
{ 0x96, 0x000c, },
{ 0x99, 0x0101, },
{ 0x9c, 0x2e37, },
{ 0x9d, 0x2c37, },
{ 0x9e, 0x2c37, },
{ 0xab, 0x0100, },
{ 0xac, 0x1003, },
{ 0xad, 0x103f, },
{ 0xe2, 0x0100, },
{ 0xe3, 0x1000, },
{ 0x28, 0x1010, },
{ 0xb1, 0x000e, },
};
/* VSB SNR lookup table */
static struct vsb_snr_tab {
u16 val;
u16 data;
} vsb_snr_tab[] = {
{ 924, 300, },
{ 923, 300, },
{ 918, 295, },
{ 915, 290, },
{ 911, 285, },
{ 906, 280, },
{ 901, 275, },
{ 896, 270, },
{ 891, 265, },
{ 885, 260, },
{ 879, 255, },
{ 873, 250, },
{ 864, 245, },
{ 858, 240, },
{ 850, 235, },
{ 841, 230, },
{ 832, 225, },
{ 823, 220, },
{ 812, 215, },
{ 802, 210, },
{ 788, 205, },
{ 778, 200, },
{ 767, 195, },
{ 753, 190, },
{ 740, 185, },
{ 725, 180, },
{ 707, 175, },
{ 689, 170, },
{ 671, 165, },
{ 656, 160, },
{ 637, 155, },
{ 616, 150, },
{ 542, 145, },
{ 519, 140, },
{ 507, 135, },
{ 497, 130, },
{ 492, 125, },
{ 474, 120, },
{ 300, 111, },
{ 0, 0, },
};
/* QAM64 SNR lookup table */
static struct qam64_snr_tab {
u16 val;
u16 data;
} qam64_snr_tab[] = {
{ 1, 0, },
{ 12, 300, },
{ 15, 290, },
{ 18, 280, },
{ 22, 270, },
{ 23, 268, },
{ 24, 266, },
{ 25, 264, },
{ 27, 262, },
{ 28, 260, },
{ 29, 258, },
{ 30, 256, },
{ 32, 254, },
{ 33, 252, },
{ 34, 250, },
{ 35, 249, },
{ 36, 248, },
{ 37, 247, },
{ 38, 246, },
{ 39, 245, },
{ 40, 244, },
{ 41, 243, },
{ 42, 241, },
{ 43, 240, },
{ 44, 239, },
{ 45, 238, },
{ 46, 237, },
{ 47, 236, },
{ 48, 235, },
{ 49, 234, },
{ 50, 233, },
{ 51, 232, },
{ 52, 231, },
{ 53, 230, },
{ 55, 229, },
{ 56, 228, },
{ 57, 227, },
{ 58, 226, },
{ 59, 225, },
{ 60, 224, },
{ 62, 223, },
{ 63, 222, },
{ 65, 221, },
{ 66, 220, },
{ 68, 219, },
{ 69, 218, },
{ 70, 217, },
{ 72, 216, },
{ 73, 215, },
{ 75, 214, },
{ 76, 213, },
{ 78, 212, },
{ 80, 211, },
{ 81, 210, },
{ 83, 209, },
{ 84, 208, },
{ 85, 207, },
{ 87, 206, },
{ 89, 205, },
{ 91, 204, },
{ 93, 203, },
{ 95, 202, },
{ 96, 201, },
{ 104, 200, },
{ 255, 0, },
};
/* QAM256 SNR lookup table */
static struct qam256_snr_tab {
u16 val;
u16 data;
} qam256_snr_tab[] = {
{ 1, 0, },
{ 12, 400, },
{ 13, 390, },
{ 15, 380, },
{ 17, 360, },
{ 19, 350, },
{ 22, 348, },
{ 23, 346, },
{ 24, 344, },
{ 25, 342, },
{ 26, 340, },
{ 27, 336, },
{ 28, 334, },
{ 29, 332, },
{ 30, 330, },
{ 31, 328, },
{ 32, 326, },
{ 33, 325, },
{ 34, 322, },
{ 35, 320, },
{ 37, 318, },
{ 39, 316, },
{ 40, 314, },
{ 41, 312, },
{ 42, 310, },
{ 43, 308, },
{ 46, 306, },
{ 47, 304, },
{ 49, 302, },
{ 51, 300, },
{ 53, 298, },
{ 54, 297, },
{ 55, 296, },
{ 56, 295, },
{ 57, 294, },
{ 59, 293, },
{ 60, 292, },
{ 61, 291, },
{ 63, 290, },
{ 64, 289, },
{ 65, 288, },
{ 66, 287, },
{ 68, 286, },
{ 69, 285, },
{ 71, 284, },
{ 72, 283, },
{ 74, 282, },
{ 75, 281, },
{ 76, 280, },
{ 77, 279, },
{ 78, 278, },
{ 81, 277, },
{ 83, 276, },
{ 84, 275, },
{ 86, 274, },
{ 87, 273, },
{ 89, 272, },
{ 90, 271, },
{ 92, 270, },
{ 93, 269, },
{ 95, 268, },
{ 96, 267, },
{ 98, 266, },
{ 100, 265, },
{ 102, 264, },
{ 104, 263, },
{ 105, 262, },
{ 106, 261, },
{ 110, 260, },
{ 255, 0, },
};
/* 8 bit registers, 16 bit values */
static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data)
{
int ret;
u8 buf[] = { reg, data >> 8, data & 0xff };
struct i2c_msg msg = { .addr = state->config->demod_address,
.flags = 0, .buf = buf, .len = 3 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk(KERN_ERR "%s: error (reg == 0x%02x, val == 0x%04x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0, 0 };
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0,
.buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD,
.buf = b1, .len = 2 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk("%s: readreg error (ret == %i)\n", __func__, ret);
return (b1[0] << 8) | b1[1];
}
static int s5h1409_softreset(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
s5h1409_writereg(state, 0xf5, 0);
s5h1409_writereg(state, 0xf5, 1);
state->is_qam_locked = 0;
state->qam_state = QAM_STATE_UNTUNED;
return 0;
}
#define S5H1409_VSB_IF_FREQ 5380
#define S5H1409_QAM_IF_FREQ (state->config->qam_if)
static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(%d KHz)\n", __func__, KHz);
switch (KHz) {
case 4000:
s5h1409_writereg(state, 0x87, 0x014b);
s5h1409_writereg(state, 0x88, 0x0cb5);
s5h1409_writereg(state, 0x89, 0x03e2);
break;
case 5380:
case 44000:
default:
s5h1409_writereg(state, 0x87, 0x01be);
s5h1409_writereg(state, 0x88, 0x0436);
s5h1409_writereg(state, 0x89, 0x054d);
break;
}
state->if_freq = KHz;
return 0;
}
static int s5h1409_set_spectralinversion(struct dvb_frontend *fe, int inverted)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, inverted);
if (inverted == 1)
return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */
else
return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */
}
static int s5h1409_enable_modulation(struct dvb_frontend *fe,
enum fe_modulation m)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(0x%08x)\n", __func__, m);
switch (m) {
case VSB_8:
dprintk("%s() VSB_8\n", __func__);
if (state->if_freq != S5H1409_VSB_IF_FREQ)
s5h1409_set_if_freq(fe, S5H1409_VSB_IF_FREQ);
s5h1409_writereg(state, 0xf4, 0);
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
dprintk("%s() QAM_AUTO (64/256)\n", __func__);
if (state->if_freq != S5H1409_QAM_IF_FREQ)
s5h1409_set_if_freq(fe, S5H1409_QAM_IF_FREQ);
s5h1409_writereg(state, 0xf4, 1);
s5h1409_writereg(state, 0x85, 0x110);
break;
default:
dprintk("%s() Invalid modulation\n", __func__);
return -EINVAL;
}
state->current_modulation = m;
s5h1409_softreset(fe);
return 0;
}
static int s5h1409_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
return s5h1409_writereg(state, 0xf3, 1);
else
return s5h1409_writereg(state, 0xf3, 0);
}
static int s5h1409_set_gpio(struct dvb_frontend *fe, int enable)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
return s5h1409_writereg(state, 0xe3,
s5h1409_readreg(state, 0xe3) | 0x1100);
else
return s5h1409_writereg(state, 0xe3,
s5h1409_readreg(state, 0xe3) & 0xfeff);
}
static int s5h1409_sleep(struct dvb_frontend *fe, int enable)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
return s5h1409_writereg(state, 0xf2, enable);
}
static int s5h1409_register_reset(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
return s5h1409_writereg(state, 0xfa, 0);
}
static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg;
if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
/* We should not perform amhum optimization until
the interleave mode has been configured */
return;
}
if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
/* We've already reached the maximum optimization level, so
don't bother banging on the status registers */
return;
}
/* QAM EQ lock check */
reg = s5h1409_readreg(state, 0xf0);
if ((reg >> 13) & 0x1) {
reg &= 0xff;
s5h1409_writereg(state, 0x96, 0x000c);
if (reg < 0x68) {
if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
dprintk("%s() setting QAM state to OPT_L3\n",
__func__);
s5h1409_writereg(state, 0x93, 0x3130);
s5h1409_writereg(state, 0x9e, 0x2836);
state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
}
} else {
if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
dprintk("%s() setting QAM state to OPT_L2\n",
__func__);
s5h1409_writereg(state, 0x93, 0x3332);
s5h1409_writereg(state, 0x9e, 0x2c37);
state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
}
}
} else {
if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
dprintk("%s() setting QAM state to OPT_L1\n", __func__);
s5h1409_writereg(state, 0x96, 0x0008);
s5h1409_writereg(state, 0x93, 0x3332);
s5h1409_writereg(state, 0x9e, 0x2c37);
state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
}
}
}
static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg;
if (state->is_qam_locked)
return;
/* QAM EQ lock check */
reg = s5h1409_readreg(state, 0xf0);
if ((reg >> 13) & 0x1) {
state->is_qam_locked = 1;
reg &= 0xff;
s5h1409_writereg(state, 0x96, 0x00c);
if ((reg < 0x38) || (reg > 0x68)) {
s5h1409_writereg(state, 0x93, 0x3332);
s5h1409_writereg(state, 0x9e, 0x2c37);
} else {
s5h1409_writereg(state, 0x93, 0x3130);
s5h1409_writereg(state, 0x9e, 0x2836);
}
} else {
s5h1409_writereg(state, 0x96, 0x0008);
s5h1409_writereg(state, 0x93, 0x3332);
s5h1409_writereg(state, 0x9e, 0x2c37);
}
}
static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg, reg1, reg2;
if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
/* We've done the optimization already */
return;
}
reg = s5h1409_readreg(state, 0xf1);
/* Master lock */
if ((reg >> 15) & 0x1) {
if (state->qam_state == QAM_STATE_UNTUNED ||
state->qam_state == QAM_STATE_TUNING_STARTED) {
dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
__func__);
reg1 = s5h1409_readreg(state, 0xb2);
reg2 = s5h1409_readreg(state, 0xad);
s5h1409_writereg(state, 0x96, 0x0020);
s5h1409_writereg(state, 0xad,
(((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
state->qam_state = QAM_STATE_INTERLEAVE_SET;
}
} else {
if (state->qam_state == QAM_STATE_UNTUNED) {
dprintk("%s() setting QAM state to TUNING_STARTED\n",
__func__);
s5h1409_writereg(state, 0x96, 0x08);
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) | 0x1001);
state->qam_state = QAM_STATE_TUNING_STARTED;
}
}
}
static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg, reg1, reg2;
reg = s5h1409_readreg(state, 0xf1);
/* Master lock */
if ((reg >> 15) & 0x1) {
if (state->qam_state != 2) {
state->qam_state = 2;
reg1 = s5h1409_readreg(state, 0xb2);
reg2 = s5h1409_readreg(state, 0xad);
s5h1409_writereg(state, 0x96, 0x20);
s5h1409_writereg(state, 0xad,
(((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) & 0xeffe);
}
} else {
if (state->qam_state != 1) {
state->qam_state = 1;
s5h1409_writereg(state, 0x96, 0x08);
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) | 0x1001);
}
}
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int s5h1409_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s(frequency=%d)\n", __func__, p->frequency);
s5h1409_softreset(fe);
state->current_frequency = p->frequency;
s5h1409_enable_modulation(fe, p->modulation);
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Issue a reset to the demod so it knows to resync against the
newly tuned frequency */
s5h1409_softreset(fe);
/* Optimize the demod for QAM */
if (state->current_modulation != VSB_8) {
/* This almost certainly applies to all boards, but for now
only do it for the HVR-1600. Once the other boards are
tested, the "legacy" versions can just go away */
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
s5h1409_set_qam_interleave_mode(fe);
s5h1409_set_qam_amhum_mode(fe);
} else {
s5h1409_set_qam_amhum_mode_legacy(fe);
s5h1409_set_qam_interleave_mode_legacy(fe);
}
}
return 0;
}
static int s5h1409_set_mpeg_timing(struct dvb_frontend *fe, int mode)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, mode);
val = s5h1409_readreg(state, 0xac) & 0xcfff;
switch (mode) {
case S5H1409_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
val |= 0x0000;
break;
case S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
val |= 0x1000;
break;
case S5H1409_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
val |= 0x2000;
break;
case S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
val |= 0x3000;
break;
default:
return -EINVAL;
}
/* Configure MPEG Signal Timing charactistics */
return s5h1409_writereg(state, 0xac, val);
}
/* Reset the demod hardware and reset all of the configuration registers
to a default state. */
static int s5h1409_init(struct dvb_frontend *fe)
{
int i;
struct s5h1409_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
s5h1409_sleep(fe, 0);
s5h1409_register_reset(fe);
for (i = 0; i < ARRAY_SIZE(init_tab); i++)
s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data);
/* The datasheet says that after initialisation, VSB is default */
state->current_modulation = VSB_8;
/* Optimize for the HVR-1600 if appropriate. Note that some of these
may get folded into the generic case after testing with other
devices */
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
/* VSB AGC REF */
s5h1409_writereg(state, 0x09, 0x0050);
/* Unknown but Windows driver does it... */
s5h1409_writereg(state, 0x21, 0x0001);
s5h1409_writereg(state, 0x50, 0x030e);
/* QAM AGC REF */
s5h1409_writereg(state, 0x82, 0x0800);
}
if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
else
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */
s5h1409_set_spectralinversion(fe, state->config->inversion);
s5h1409_set_if_freq(fe, state->if_freq);
s5h1409_set_gpio(fe, state->config->gpio);
s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
s5h1409_softreset(fe);
/* Note: Leaving the I2C gate closed. */
s5h1409_i2c_gate_ctrl(fe, 0);
return 0;
}
static int s5h1409_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg;
u32 tuner_status = 0;
*status = 0;
/* Optimize the demod for QAM */
if (state->current_modulation != VSB_8) {
/* This almost certainly applies to all boards, but for now
only do it for the HVR-1600. Once the other boards are
tested, the "legacy" versions can just go away */
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
s5h1409_set_qam_interleave_mode(fe);
s5h1409_set_qam_amhum_mode(fe);
}
}
/* Get the demodulator status */
reg = s5h1409_readreg(state, 0xf1);
if (reg & 0x1000)
*status |= FE_HAS_VITERBI;
if (reg & 0x8000)
*status |= FE_HAS_LOCK | FE_HAS_SYNC;
switch (state->config->status_mode) {
case S5H1409_DEMODLOCKING:
if (*status & FE_HAS_VITERBI)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
case S5H1409_TUNERLOCKING:
/* Get the tuner status */
if (fe->ops.tuner_ops.get_status) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.get_status(fe, &tuner_status);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (tuner_status)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
}
dprintk("%s() status 0x%08x\n", __func__, *status);
return 0;
}
static int s5h1409_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
if (v < qam256_snr_tab[i].val) {
*snr = qam256_snr_tab[i].data;
ret = 0;
break;
}
}
return ret;
}
static int s5h1409_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
if (v < qam64_snr_tab[i].val) {
*snr = qam64_snr_tab[i].data;
ret = 0;
break;
}
}
return ret;
}
static int s5h1409_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
if (v > vsb_snr_tab[i].val) {
*snr = vsb_snr_tab[i].data;
ret = 0;
break;
}
}
dprintk("%s() snr=%d\n", __func__, *snr);
return ret;
}
static int s5h1409_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg;
dprintk("%s()\n", __func__);
switch (state->current_modulation) {
case QAM_64:
reg = s5h1409_readreg(state, 0xf0) & 0xff;
return s5h1409_qam64_lookup_snr(fe, snr, reg);
case QAM_256:
reg = s5h1409_readreg(state, 0xf0) & 0xff;
return s5h1409_qam256_lookup_snr(fe, snr, reg);
case VSB_8:
reg = s5h1409_readreg(state, 0xf1) & 0x3ff;
return s5h1409_vsb_lookup_snr(fe, snr, reg);
default:
break;
}
return -EINVAL;
}
static int s5h1409_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
/* borrowed from lgdt330x.c
*
* Calculate strength from SNR up to 35dB
* Even though the SNR can go higher than 35dB,
* there is some comfort factor in having a range of
* strong signals that can show at 100%
*/
u16 snr;
u32 tmp;
int ret = s5h1409_read_snr(fe, &snr);
*signal_strength = 0;
if (0 == ret) {
/* The following calculation method was chosen
* purely for the sake of code re-use from the
* other demod drivers that use this method */
/* Convert from SNR in dB * 10 to 8.24 fixed-point */
tmp = (snr * ((1 << 24) / 10));
/* Convert from 8.24 fixed-point to
* scale the range 0 - 35*2^24 into 0 - 65535*/
if (tmp >= 8960 * 0x10000)
*signal_strength = 0xffff;
else
*signal_strength = tmp / 8960;
}
return ret;
}
static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct s5h1409_state *state = fe->demodulator_priv;
*ucblocks = s5h1409_readreg(state, 0xb5);
return 0;
}
static int s5h1409_read_ber(struct dvb_frontend *fe, u32 *ber)
{
return s5h1409_read_ucblocks(fe, ber);
}
static int s5h1409_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct s5h1409_state *state = fe->demodulator_priv;
p->frequency = state->current_frequency;
p->modulation = state->current_modulation;
return 0;
}
static int s5h1409_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void s5h1409_release(struct dvb_frontend *fe)
{
struct s5h1409_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops s5h1409_ops;
struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config,
struct i2c_adapter *i2c)
{
struct s5h1409_state *state = NULL;
u16 reg;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->current_modulation = 0;
state->if_freq = S5H1409_VSB_IF_FREQ;
/* check if the demod exists */
reg = s5h1409_readreg(state, 0x04);
if ((reg != 0x0066) && (reg != 0x007f))
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1409_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
if (s5h1409_init(&state->frontend) != 0) {
printk(KERN_ERR "%s: Failed to initialize correctly\n",
__func__);
goto error;
}
/* Note: Leaving the I2C gate open here. */
s5h1409_i2c_gate_ctrl(&state->frontend, 1);
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(s5h1409_attach);
static const struct dvb_frontend_ops s5h1409_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Samsung S5H1409 QAM/8VSB Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = s5h1409_init,
.i2c_gate_ctrl = s5h1409_i2c_gate_ctrl,
.set_frontend = s5h1409_set_frontend,
.get_frontend = s5h1409_get_frontend,
.get_tune_settings = s5h1409_get_tune_settings,
.read_status = s5h1409_read_status,
.read_ber = s5h1409_read_ber,
.read_signal_strength = s5h1409_read_signal_strength,
.read_snr = s5h1409_read_snr,
.read_ucblocks = s5h1409_read_ucblocks,
.release = s5h1409_release,
};
MODULE_DESCRIPTION("Samsung S5H1409 QAM-B/ATSC Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/s5h1409.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Sony CXD2820R demodulator driver
*
* Copyright (C) 2010 Antti Palosaari <[email protected]>
*/
#include "cxd2820r_priv.h"
int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, bw_i;
unsigned int utmp;
u32 if_frequency;
u8 buf[3], bw_param;
u8 bw_params1[][5] = {
{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
};
u8 bw_params2[][2] = {
{ 0x1f, 0xdc }, /* 6 MHz */
{ 0x12, 0xf8 }, /* 7 MHz */
{ 0x01, 0xe0 }, /* 8 MHz */
};
struct reg_val_mask tab[] = {
{ 0x00080, 0x00, 0xff },
{ 0x00081, 0x03, 0xff },
{ 0x00085, 0x07, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x00070, priv->ts_mode, 0xff },
{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
{ 0x000a5, 0x00, 0x01 },
{ 0x00082, 0x20, 0x60 },
{ 0x000c2, 0xc3, 0xff },
{ 0x0016a, 0x50, 0xff },
{ 0x00427, 0x41, 0xff },
};
dev_dbg(&client->dev,
"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
c->delivery_system, c->modulation, c->frequency,
c->bandwidth_hz, c->inversion);
switch (c->bandwidth_hz) {
case 6000000:
bw_i = 0;
bw_param = 2;
break;
case 7000000:
bw_i = 1;
bw_param = 1;
break;
case 8000000:
bw_i = 2;
bw_param = 0;
break;
default:
return -EINVAL;
}
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
if (priv->delivery_system != SYS_DVBT) {
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
}
priv->delivery_system = SYS_DVBT;
priv->ber_running = false; /* tune stops BER counter */
/* program IF frequency */
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto error;
dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
} else {
ret = -EINVAL;
goto error;
}
utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
buf[0] = (utmp >> 16) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 0) & 0xff;
ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
if (ret)
goto error;
ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
if (ret)
goto error;
ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
if (ret)
goto error;
ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
unsigned int utmp;
u8 buf[2];
dev_dbg(&client->dev, "\n");
ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
if (ret)
goto error;
switch ((buf[0] >> 6) & 0x03) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[1] >> 1) & 0x03) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
switch ((buf[1] >> 3) & 0x03) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[0] >> 3) & 0x07) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[0] >> 0) & 0x07) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
}
switch ((buf[1] >> 5) & 0x07) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
}
ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
if (ret)
goto error;
switch ((utmp >> 0) & 0x01) {
case 0:
c->inversion = INVERSION_OFF;
break;
case 1:
c->inversion = INVERSION_ON;
break;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
unsigned int utmp, utmp1, utmp2;
u8 buf[3];
/* Lock detection */
ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
if (ret)
goto error;
ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
if (ret)
goto error;
utmp1 = (buf[0] >> 0) & 0x07;
utmp2 = (buf[1] >> 3) & 0x01;
if (utmp1 == 6 && utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else if (utmp1 == 6 || utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC;
} else {
*status = 0;
}
dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
*status, 2, buf, utmp1, utmp2);
/* Signal strength */
if (*status & FE_HAS_SIGNAL) {
unsigned int strength;
ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
if (ret)
goto error;
utmp = buf[0] << 8 | buf[1] << 0;
utmp = ~utmp & 0x0fff;
/* Scale value to 0x0000-0xffff */
strength = utmp << 4 | utmp >> 8;
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = strength;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (*status & FE_HAS_VITERBI) {
unsigned int cnr;
ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
if (ret)
goto error;
utmp = buf[0] << 8 | buf[1] << 0;
if (utmp)
cnr = div_u64((u64)(intlog10(utmp)
- intlog10(32000 - utmp) + 55532585)
* 10000, (1 << 24));
else
cnr = 0;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (*status & FE_HAS_SYNC) {
unsigned int post_bit_error;
bool start_ber;
if (priv->ber_running) {
ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
if (ret)
goto error;
if ((buf[2] >> 7) & 0x01) {
post_bit_error = buf[2] << 16 | buf[1] << 8 |
buf[0] << 0;
post_bit_error &= 0x0fffff;
start_ber = true;
} else {
post_bit_error = 0;
start_ber = false;
}
} else {
post_bit_error = 0;
start_ber = true;
}
if (start_ber) {
ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
if (ret)
goto error;
priv->ber_running = true;
}
priv->post_bit_error += post_bit_error;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
} else {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_init_t(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
dev_dbg(&client->dev, "\n");
ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_sleep_t(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
static struct reg_val_mask tab[] = {
{ 0x000ff, 0x1f, 0xff },
{ 0x00085, 0x00, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x00081, 0x00, 0xff },
{ 0x00080, 0x00, 0xff },
};
dev_dbg(&client->dev, "\n");
priv->delivery_system = SYS_UNDEFINED;
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 500;
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2820r_t.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for ST STV0299 demodulator
Copyright (C) 2001-2002 Convergence Integrated Media GmbH
<[email protected]>,
<[email protected]>,
<[email protected]>
Philips SU1278/SH
Copyright (C) 2002 by Peter Schildmann <[email protected]>
LG TDQF-S001F
Copyright (C) 2002 Felix Domke <[email protected]>
& Andreas Oberritter <[email protected]>
Support for Samsung TBMU24112IMB used on Technisat SkyStar2 rev. 2.6B
Copyright (C) 2003 Vadim Catana <[email protected]>:
Support for Philips SU1278 on Technotrend hardware
Copyright (C) 2004 Andrew de Quincey <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "stv0299.h"
struct stv0299_state {
struct i2c_adapter* i2c;
const struct stv0299_config* config;
struct dvb_frontend frontend;
u8 initialised:1;
u32 tuner_frequency;
u32 symbol_rate;
enum fe_code_rate fec_inner;
int errmode;
u32 ucblocks;
u8 mcr_reg;
};
#define STATUS_BER 0
#define STATUS_UCBLOCKS 1
static int debug;
static int debug_legacy_dish_switch;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "stv0299: " args); \
} while (0)
static int stv0299_writeregI (struct stv0299_state* state, u8 reg, u8 data)
{
int ret;
u8 buf [] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
ret = i2c_transfer (state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int stv0299_write(struct dvb_frontend* fe, const u8 buf[], int len)
{
struct stv0299_state* state = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return stv0299_writeregI(state, buf[0], buf[1]);
}
static u8 stv0299_readreg (struct stv0299_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
ret = i2c_transfer (state->i2c, msg, 2);
if (ret != 2)
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return b1[0];
}
static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len)
{
int ret;
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } };
ret = i2c_transfer (state->i2c, msg, 2);
if (ret != 2)
dprintk("%s: readreg error (ret == %i)\n", __func__, ret);
return ret == 2 ? 0 : ret;
}
static int stv0299_set_FEC(struct stv0299_state *state, enum fe_code_rate fec)
{
dprintk ("%s\n", __func__);
switch (fec) {
case FEC_AUTO:
{
return stv0299_writeregI (state, 0x31, 0x1f);
}
case FEC_1_2:
{
return stv0299_writeregI (state, 0x31, 0x01);
}
case FEC_2_3:
{
return stv0299_writeregI (state, 0x31, 0x02);
}
case FEC_3_4:
{
return stv0299_writeregI (state, 0x31, 0x04);
}
case FEC_5_6:
{
return stv0299_writeregI (state, 0x31, 0x08);
}
case FEC_7_8:
{
return stv0299_writeregI (state, 0x31, 0x10);
}
default:
{
return -EINVAL;
}
}
}
static enum fe_code_rate stv0299_get_fec(struct stv0299_state *state)
{
static const enum fe_code_rate fec_tab[] = {
FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, FEC_1_2
};
u8 index;
dprintk ("%s\n", __func__);
index = stv0299_readreg (state, 0x1b);
index &= 0x7;
if (index > 4)
return FEC_AUTO;
return fec_tab [index];
}
static int stv0299_wait_diseqc_fifo (struct stv0299_state* state, int timeout)
{
unsigned long start = jiffies;
dprintk ("%s\n", __func__);
while (stv0299_readreg(state, 0x0a) & 1) {
if (time_is_before_jiffies(start + timeout)) {
dprintk ("%s: timeout!!\n", __func__);
return -ETIMEDOUT;
}
msleep(10);
}
return 0;
}
static int stv0299_wait_diseqc_idle (struct stv0299_state* state, int timeout)
{
unsigned long start = jiffies;
dprintk ("%s\n", __func__);
while ((stv0299_readreg(state, 0x0a) & 3) != 2 ) {
if (time_is_before_jiffies(start + timeout)) {
dprintk ("%s: timeout!!\n", __func__);
return -ETIMEDOUT;
}
msleep(10);
}
return 0;
}
static int stv0299_set_symbolrate (struct dvb_frontend* fe, u32 srate)
{
struct stv0299_state* state = fe->demodulator_priv;
u64 big = srate;
u32 ratio;
// check rate is within limits
if ((srate < 1000000) || (srate > 45000000)) return -EINVAL;
// calculate value to program
big = big << 20;
big += (state->config->mclk-1); // round correctly
do_div(big, state->config->mclk);
ratio = big << 4;
return state->config->set_symbol_rate(fe, srate, ratio);
}
static int stv0299_get_symbolrate (struct stv0299_state* state)
{
u32 Mclk = state->config->mclk / 4096L;
u32 srate;
s32 offset;
u8 sfr[3];
s8 rtf;
dprintk ("%s\n", __func__);
stv0299_readregs (state, 0x1f, sfr, 3);
stv0299_readregs (state, 0x1a, (u8 *)&rtf, 1);
srate = (sfr[0] << 8) | sfr[1];
srate *= Mclk;
srate /= 16;
srate += (sfr[2] >> 4) * Mclk / 256;
offset = (s32) rtf * (srate / 4096L);
offset /= 128;
dprintk ("%s : srate = %i\n", __func__, srate);
dprintk ("%s : ofset = %i\n", __func__, offset);
srate += offset;
srate += 1000;
srate /= 2000;
srate *= 2000;
return srate;
}
static int stv0299_send_diseqc_msg (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd *m)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 val;
int i;
dprintk ("%s\n", __func__);
if (stv0299_wait_diseqc_idle (state, 100) < 0)
return -ETIMEDOUT;
val = stv0299_readreg (state, 0x08);
if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x6)) /* DiSEqC mode */
return -EREMOTEIO;
for (i=0; i<m->msg_len; i++) {
if (stv0299_wait_diseqc_fifo (state, 100) < 0)
return -ETIMEDOUT;
if (stv0299_writeregI (state, 0x09, m->msg[i]))
return -EREMOTEIO;
}
if (stv0299_wait_diseqc_idle (state, 100) < 0)
return -ETIMEDOUT;
return 0;
}
static int stv0299_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 val;
dprintk ("%s\n", __func__);
if (stv0299_wait_diseqc_idle (state, 100) < 0)
return -ETIMEDOUT;
val = stv0299_readreg (state, 0x08);
if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x2)) /* burst mode */
return -EREMOTEIO;
if (stv0299_writeregI (state, 0x09, burst == SEC_MINI_A ? 0x00 : 0xff))
return -EREMOTEIO;
if (stv0299_wait_diseqc_idle (state, 100) < 0)
return -ETIMEDOUT;
if (stv0299_writeregI (state, 0x08, val))
return -EREMOTEIO;
return 0;
}
static int stv0299_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 val;
if (stv0299_wait_diseqc_idle (state, 100) < 0)
return -ETIMEDOUT;
val = stv0299_readreg (state, 0x08);
switch (tone) {
case SEC_TONE_ON:
return stv0299_writeregI (state, 0x08, val | 0x3);
case SEC_TONE_OFF:
return stv0299_writeregI (state, 0x08, (val & ~0x3) | 0x02);
default:
return -EINVAL;
}
}
static int stv0299_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 reg0x08;
u8 reg0x0c;
dprintk("%s: %s\n", __func__,
voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
reg0x08 = stv0299_readreg (state, 0x08);
reg0x0c = stv0299_readreg (state, 0x0c);
/*
* H/V switching over OP0, OP1 and OP2 are LNB power enable bits
*/
reg0x0c &= 0x0f;
reg0x08 = (reg0x08 & 0x3f) | (state->config->lock_output << 6);
switch (voltage) {
case SEC_VOLTAGE_13:
if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0)
reg0x0c |= 0x10; /* OP1 off, OP0 on */
else
reg0x0c |= 0x40; /* OP1 on, OP0 off */
break;
case SEC_VOLTAGE_18:
reg0x0c |= 0x50; /* OP1 on, OP0 on */
break;
case SEC_VOLTAGE_OFF:
/* LNB power off! */
reg0x08 = 0x00;
reg0x0c = 0x00;
break;
default:
return -EINVAL;
}
if (state->config->op0_off)
reg0x0c &= ~0x10;
stv0299_writeregI(state, 0x08, reg0x08);
return stv0299_writeregI(state, 0x0c, reg0x0c);
}
static int stv0299_send_legacy_dish_cmd (struct dvb_frontend* fe, unsigned long cmd)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 reg0x08;
u8 reg0x0c;
u8 lv_mask = 0x40;
u8 last = 1;
int i;
ktime_t nexttime;
ktime_t tv[10];
reg0x08 = stv0299_readreg (state, 0x08);
reg0x0c = stv0299_readreg (state, 0x0c);
reg0x0c &= 0x0f;
stv0299_writeregI (state, 0x08, (reg0x08 & 0x3f) | (state->config->lock_output << 6));
if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0)
lv_mask = 0x10;
cmd = cmd << 1;
if (debug_legacy_dish_switch)
printk ("%s switch command: 0x%04lx\n",__func__, cmd);
nexttime = ktime_get_boottime();
if (debug_legacy_dish_switch)
tv[0] = nexttime;
stv0299_writeregI (state, 0x0c, reg0x0c | 0x50); /* set LNB to 18V */
dvb_frontend_sleep_until(&nexttime, 32000);
for (i=0; i<9; i++) {
if (debug_legacy_dish_switch)
tv[i+1] = ktime_get_boottime();
if((cmd & 0x01) != last) {
/* set voltage to (last ? 13V : 18V) */
stv0299_writeregI (state, 0x0c, reg0x0c | (last ? lv_mask : 0x50));
last = (last) ? 0 : 1;
}
cmd = cmd >> 1;
if (i != 8)
dvb_frontend_sleep_until(&nexttime, 8000);
}
if (debug_legacy_dish_switch) {
printk ("%s(%d): switch delay (should be 32k followed by all 8k\n",
__func__, fe->dvb->num);
for (i = 1; i < 10; i++)
printk("%d: %d\n", i,
(int) ktime_us_delta(tv[i], tv[i-1]));
}
return 0;
}
static int stv0299_init (struct dvb_frontend* fe)
{
struct stv0299_state* state = fe->demodulator_priv;
int i;
u8 reg;
u8 val;
dprintk("stv0299: init chip\n");
stv0299_writeregI(state, 0x02, 0x30 | state->mcr_reg);
msleep(50);
for (i = 0; ; i += 2) {
reg = state->config->inittab[i];
val = state->config->inittab[i+1];
if (reg == 0xff && val == 0xff)
break;
if (reg == 0x0c && state->config->op0_off)
val &= ~0x10;
if (reg == 0x2)
state->mcr_reg = val & 0xf;
stv0299_writeregI(state, reg, val);
}
return 0;
}
static int stv0299_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct stv0299_state* state = fe->demodulator_priv;
u8 signal = 0xff - stv0299_readreg (state, 0x18);
u8 sync = stv0299_readreg (state, 0x1b);
dprintk ("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync);
*status = 0;
if (signal > 10)
*status |= FE_HAS_SIGNAL;
if (sync & 0x80)
*status |= FE_HAS_CARRIER;
if (sync & 0x10)
*status |= FE_HAS_VITERBI;
if (sync & 0x08)
*status |= FE_HAS_SYNC;
if ((sync & 0x98) == 0x98)
*status |= FE_HAS_LOCK;
return 0;
}
static int stv0299_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct stv0299_state* state = fe->demodulator_priv;
if (state->errmode != STATUS_BER)
return -ENOSYS;
*ber = stv0299_readreg(state, 0x1e) | (stv0299_readreg(state, 0x1d) << 8);
return 0;
}
static int stv0299_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct stv0299_state* state = fe->demodulator_priv;
s32 signal = 0xffff - ((stv0299_readreg (state, 0x18) << 8)
| stv0299_readreg (state, 0x19));
dprintk ("%s : FE_READ_SIGNAL_STRENGTH : AGC2I: 0x%02x%02x, signal=0x%04x\n", __func__,
stv0299_readreg (state, 0x18),
stv0299_readreg (state, 0x19), (int) signal);
signal = signal * 5 / 4;
*strength = (signal > 0xffff) ? 0xffff : (signal < 0) ? 0 : signal;
return 0;
}
static int stv0299_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct stv0299_state* state = fe->demodulator_priv;
s32 xsnr = 0xffff - ((stv0299_readreg (state, 0x24) << 8)
| stv0299_readreg (state, 0x25));
xsnr = 3 * (xsnr - 0xa100);
*snr = (xsnr > 0xffff) ? 0xffff : (xsnr < 0) ? 0 : xsnr;
return 0;
}
static int stv0299_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct stv0299_state* state = fe->demodulator_priv;
if (state->errmode != STATUS_UCBLOCKS)
return -ENOSYS;
state->ucblocks += stv0299_readreg(state, 0x1e);
state->ucblocks += (stv0299_readreg(state, 0x1d) << 8);
*ucblocks = state->ucblocks;
return 0;
}
static int stv0299_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stv0299_state* state = fe->demodulator_priv;
int invval = 0;
dprintk ("%s : FE_SET_FRONTEND\n", __func__);
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
// set the inversion
if (p->inversion == INVERSION_OFF) invval = 0;
else if (p->inversion == INVERSION_ON) invval = 1;
else {
printk("stv0299 does not support auto-inversion\n");
return -EINVAL;
}
if (state->config->invert) invval = (~invval) & 1;
stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval);
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
stv0299_set_FEC(state, p->fec_inner);
stv0299_set_symbolrate(fe, p->symbol_rate);
stv0299_writeregI(state, 0x22, 0x00);
stv0299_writeregI(state, 0x23, 0x00);
state->tuner_frequency = p->frequency;
state->fec_inner = p->fec_inner;
state->symbol_rate = p->symbol_rate;
return 0;
}
static int stv0299_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0299_state* state = fe->demodulator_priv;
s32 derot_freq;
int invval;
derot_freq = (s32)(s16) ((stv0299_readreg (state, 0x22) << 8)
| stv0299_readreg (state, 0x23));
derot_freq *= (state->config->mclk >> 16);
derot_freq += 500;
derot_freq /= 1000;
p->frequency += derot_freq;
invval = stv0299_readreg (state, 0x0c) & 1;
if (state->config->invert) invval = (~invval) & 1;
p->inversion = invval ? INVERSION_ON : INVERSION_OFF;
p->fec_inner = stv0299_get_fec(state);
p->symbol_rate = stv0299_get_symbolrate(state);
return 0;
}
static int stv0299_sleep(struct dvb_frontend* fe)
{
struct stv0299_state* state = fe->demodulator_priv;
stv0299_writeregI(state, 0x02, 0xb0 | state->mcr_reg);
state->initialised = 0;
return 0;
}
static int stv0299_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct stv0299_state* state = fe->demodulator_priv;
if (enable) {
stv0299_writeregI(state, 0x05, 0xb5);
} else {
stv0299_writeregI(state, 0x05, 0x35);
}
udelay(1);
return 0;
}
static int stv0299_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
struct stv0299_state* state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
fesettings->min_delay_ms = state->config->min_delay_ms;
if (p->symbol_rate < 10000000) {
fesettings->step_size = p->symbol_rate / 32000;
fesettings->max_drift = 5000;
} else {
fesettings->step_size = p->symbol_rate / 16000;
fesettings->max_drift = p->symbol_rate / 2000;
}
return 0;
}
static void stv0299_release(struct dvb_frontend* fe)
{
struct stv0299_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops stv0299_ops;
struct dvb_frontend* stv0299_attach(const struct stv0299_config* config,
struct i2c_adapter* i2c)
{
struct stv0299_state* state = NULL;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0299_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->initialised = 0;
state->tuner_frequency = 0;
state->symbol_rate = 0;
state->fec_inner = 0;
state->errmode = STATUS_BER;
/* check if the demod is there */
stv0299_writeregI(state, 0x02, 0x30); /* standby off */
msleep(200);
id = stv0299_readreg(state, 0x00);
/* register 0x00 contains 0xa1 for STV0299 and STV0299B */
/* register 0x00 might contain 0x80 when returning from standby */
if (id != 0xa1 && id != 0x80) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &stv0299_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops stv0299_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "ST STV0299 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500, /* ppm */
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = stv0299_release,
.init = stv0299_init,
.sleep = stv0299_sleep,
.write = stv0299_write,
.i2c_gate_ctrl = stv0299_i2c_gate_ctrl,
.set_frontend = stv0299_set_frontend,
.get_frontend = stv0299_get_frontend,
.get_tune_settings = stv0299_get_tune_settings,
.read_status = stv0299_read_status,
.read_ber = stv0299_read_ber,
.read_signal_strength = stv0299_read_signal_strength,
.read_snr = stv0299_read_snr,
.read_ucblocks = stv0299_read_ucblocks,
.diseqc_send_master_cmd = stv0299_send_diseqc_msg,
.diseqc_send_burst = stv0299_send_diseqc_burst,
.set_tone = stv0299_set_tone,
.set_voltage = stv0299_set_voltage,
.dishnetwork_send_legacy_command = stv0299_send_legacy_dish_cmd,
};
module_param(debug_legacy_dish_switch, int, 0444);
MODULE_PARM_DESC(debug_legacy_dish_switch, "Enable timing analysis for Dish Network legacy switches");
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("ST STV0299 DVB Demodulator driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Peter Schildmann, Felix Domke, Andreas Oberritter, Andrew de Quincey, Kenneth Aafly");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(stv0299_attach);
| linux-master | drivers/media/dvb-frontends/stv0299.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
*
* Copyright (C) 2005 Steven Toth <[email protected]>
*
* Support for KWorld DVB-S 100 by Vadim Catana <[email protected]>
*
* Support for CX24123/CX24113-NIM by Patrick Boettcher <[email protected]>
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "cx24123.h"
#define XTAL 10111000
static int force_band;
module_param(force_band, int, 0644);
MODULE_PARM_DESC(force_band, "Force a specific band select "\
"(1-9, default:off).");
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
#define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
#define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0)
#define dprintk(args...) \
do { \
if (debug) { \
printk(KERN_DEBUG "CX24123: %s: ", __func__); \
printk(args); \
} \
} while (0)
struct cx24123_state {
struct i2c_adapter *i2c;
const struct cx24123_config *config;
struct dvb_frontend frontend;
/* Some PLL specifics for tuning */
u32 VCAarg;
u32 VGAarg;
u32 bandselectarg;
u32 pllarg;
u32 FILTune;
struct i2c_adapter tuner_i2c_adapter;
u8 demod_rev;
/* The Demod/Tuner can't easily provide these, we cache them */
u32 currentfreq;
u32 currentsymbolrate;
};
/* Various tuner defaults need to be established for a given symbol rate Sps */
static struct cx24123_AGC_val {
u32 symbolrate_low;
u32 symbolrate_high;
u32 VCAprogdata;
u32 VGAprogdata;
u32 FILTune;
} cx24123_AGC_vals[] =
{
{
.symbolrate_low = 1000000,
.symbolrate_high = 4999999,
/* the specs recommend other values for VGA offsets,
but tests show they are wrong */
.VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
.VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
.FILTune = 0x27f /* 0.41 V */
},
{
.symbolrate_low = 5000000,
.symbolrate_high = 14999999,
.VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
.VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
.FILTune = 0x317 /* 0.90 V */
},
{
.symbolrate_low = 15000000,
.symbolrate_high = 45000000,
.VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
.VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
.FILTune = 0x145 /* 2.70 V */
},
};
/*
* Various tuner defaults need to be established for a given frequency kHz.
* fixme: The bounds on the bands do not match the doc in real life.
* fixme: Some of them have been moved, other might need adjustment.
*/
static struct cx24123_bandselect_val {
u32 freq_low;
u32 freq_high;
u32 VCOdivider;
u32 progdata;
} cx24123_bandselect_vals[] =
{
/* band 1 */
{
.freq_low = 950000,
.freq_high = 1074999,
.VCOdivider = 4,
.progdata = (0 << 19) | (0 << 9) | 0x40,
},
/* band 2 */
{
.freq_low = 1075000,
.freq_high = 1177999,
.VCOdivider = 4,
.progdata = (0 << 19) | (0 << 9) | 0x80,
},
/* band 3 */
{
.freq_low = 1178000,
.freq_high = 1295999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x01,
},
/* band 4 */
{
.freq_low = 1296000,
.freq_high = 1431999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x02,
},
/* band 5 */
{
.freq_low = 1432000,
.freq_high = 1575999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x04,
},
/* band 6 */
{
.freq_low = 1576000,
.freq_high = 1717999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x08,
},
/* band 7 */
{
.freq_low = 1718000,
.freq_high = 1855999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x10,
},
/* band 8 */
{
.freq_low = 1856000,
.freq_high = 2035999,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x20,
},
/* band 9 */
{
.freq_low = 2036000,
.freq_high = 2150000,
.VCOdivider = 2,
.progdata = (0 << 19) | (1 << 9) | 0x40,
},
};
static struct {
u8 reg;
u8 data;
} cx24123_regdata[] =
{
{0x00, 0x03}, /* Reset system */
{0x00, 0x00}, /* Clear reset */
{0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
{0x04, 0x10}, /* MPEG */
{0x05, 0x04}, /* MPEG */
{0x06, 0x31}, /* MPEG (default) */
{0x0b, 0x00}, /* Freq search start point (default) */
{0x0c, 0x00}, /* Demodulator sample gain (default) */
{0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
{0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
{0x0f, 0xfe}, /* FEC search mask (all supported codes) */
{0x10, 0x01}, /* Default search inversion, no repeat (default) */
{0x16, 0x00}, /* Enable reading of frequency */
{0x17, 0x01}, /* Enable EsNO Ready Counter */
{0x1c, 0x80}, /* Enable error counter */
{0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
{0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
{0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
{0x29, 0x00}, /* DiSEqC LNB_DC off */
{0x2a, 0xb0}, /* DiSEqC Parameters (default) */
{0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
{0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
{0x2d, 0x00},
{0x2e, 0x00},
{0x2f, 0x00},
{0x30, 0x00},
{0x31, 0x00},
{0x32, 0x8c}, /* DiSEqC Parameters (default) */
{0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
{0x34, 0x00},
{0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
{0x36, 0x02}, /* DiSEqC Parameters (default) */
{0x37, 0x3a}, /* DiSEqC Parameters (default) */
{0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
{0x44, 0x00}, /* Constellation (default) */
{0x45, 0x00}, /* Symbol count (default) */
{0x46, 0x0d}, /* Symbol rate estimator on (default) */
{0x56, 0xc1}, /* Error Counter = Viterbi BER */
{0x57, 0xff}, /* Error Counter Window (default) */
{0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
{0x67, 0x83}, /* Non-DCII symbol clock */
};
static int cx24123_i2c_writereg(struct cx24123_state *state,
u8 i2c_addr, int reg, int data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
};
int err;
/* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n",
__func__, err, reg, data);
return err;
}
return 0;
}
static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg)
{
int ret;
u8 b = 0;
struct i2c_msg msg[] = {
{ .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 }
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret);
return ret;
}
/* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */
return b;
}
#define cx24123_readreg(state, reg) \
cx24123_i2c_readreg(state, state->config->demod_address, reg)
#define cx24123_writereg(state, reg, val) \
cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
static int cx24123_set_inversion(struct cx24123_state *state,
enum fe_spectral_inversion inversion)
{
u8 nom_reg = cx24123_readreg(state, 0x0e);
u8 auto_reg = cx24123_readreg(state, 0x10);
switch (inversion) {
case INVERSION_OFF:
dprintk("inversion off\n");
cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
cx24123_writereg(state, 0x10, auto_reg | 0x80);
break;
case INVERSION_ON:
dprintk("inversion on\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x80);
cx24123_writereg(state, 0x10, auto_reg | 0x80);
break;
case INVERSION_AUTO:
dprintk("inversion auto\n");
cx24123_writereg(state, 0x10, auto_reg & ~0x80);
break;
default:
return -EINVAL;
}
return 0;
}
static int cx24123_get_inversion(struct cx24123_state *state,
enum fe_spectral_inversion *inversion)
{
u8 val;
val = cx24123_readreg(state, 0x1b) >> 7;
if (val == 0) {
dprintk("read inversion off\n");
*inversion = INVERSION_OFF;
} else {
dprintk("read inversion on\n");
*inversion = INVERSION_ON;
}
return 0;
}
static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec)
{
u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
if (((int)fec < FEC_NONE) || (fec > FEC_AUTO))
fec = FEC_AUTO;
/* Set the soft decision threshold */
if (fec == FEC_1_2)
cx24123_writereg(state, 0x43,
cx24123_readreg(state, 0x43) | 0x01);
else
cx24123_writereg(state, 0x43,
cx24123_readreg(state, 0x43) & ~0x01);
switch (fec) {
case FEC_1_2:
dprintk("set FEC to 1/2\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x01);
cx24123_writereg(state, 0x0f, 0x02);
break;
case FEC_2_3:
dprintk("set FEC to 2/3\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x02);
cx24123_writereg(state, 0x0f, 0x04);
break;
case FEC_3_4:
dprintk("set FEC to 3/4\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x03);
cx24123_writereg(state, 0x0f, 0x08);
break;
case FEC_4_5:
dprintk("set FEC to 4/5\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x04);
cx24123_writereg(state, 0x0f, 0x10);
break;
case FEC_5_6:
dprintk("set FEC to 5/6\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x05);
cx24123_writereg(state, 0x0f, 0x20);
break;
case FEC_6_7:
dprintk("set FEC to 6/7\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x06);
cx24123_writereg(state, 0x0f, 0x40);
break;
case FEC_7_8:
dprintk("set FEC to 7/8\n");
cx24123_writereg(state, 0x0e, nom_reg | 0x07);
cx24123_writereg(state, 0x0f, 0x80);
break;
case FEC_AUTO:
dprintk("set FEC to auto\n");
cx24123_writereg(state, 0x0f, 0xfe);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec)
{
int ret;
ret = cx24123_readreg(state, 0x1b);
if (ret < 0)
return ret;
ret = ret & 0x07;
switch (ret) {
case 1:
*fec = FEC_1_2;
break;
case 2:
*fec = FEC_2_3;
break;
case 3:
*fec = FEC_3_4;
break;
case 4:
*fec = FEC_4_5;
break;
case 5:
*fec = FEC_5_6;
break;
case 6:
*fec = FEC_6_7;
break;
case 7:
*fec = FEC_7_8;
break;
default:
/* this can happen when there's no lock */
*fec = FEC_NONE;
}
return 0;
}
/* Approximation of closest integer of log2(a/b). It actually gives the
lowest integer i such that 2^i >= round(a/b) */
static u32 cx24123_int_log2(u32 a, u32 b)
{
u32 exp, nearest = 0;
u32 div = a / b;
if (a % b >= b / 2)
++div;
if (div < (1UL << 31)) {
for (exp = 1; div > exp; nearest++)
exp += exp;
}
return nearest;
}
static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
{
u64 tmp;
u32 sample_rate, ratio, sample_gain;
u8 pll_mult;
/* check if symbol rate is within limits */
if ((srate > state->frontend.ops.info.symbol_rate_max) ||
(srate < state->frontend.ops.info.symbol_rate_min))
return -EOPNOTSUPP;
/* choose the sampling rate high enough for the required operation,
while optimizing the power consumed by the demodulator */
if (srate < (XTAL*2)/2)
pll_mult = 2;
else if (srate < (XTAL*3)/2)
pll_mult = 3;
else if (srate < (XTAL*4)/2)
pll_mult = 4;
else if (srate < (XTAL*5)/2)
pll_mult = 5;
else if (srate < (XTAL*6)/2)
pll_mult = 6;
else if (srate < (XTAL*7)/2)
pll_mult = 7;
else if (srate < (XTAL*8)/2)
pll_mult = 8;
else
pll_mult = 9;
sample_rate = pll_mult * XTAL;
/* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */
tmp = ((u64)srate) << 23;
do_div(tmp, sample_rate);
ratio = (u32) tmp;
cx24123_writereg(state, 0x01, pll_mult * 6);
cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f);
cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff);
cx24123_writereg(state, 0x0a, ratio & 0xff);
/* also set the demodulator sample gain */
sample_gain = cx24123_int_log2(sample_rate, srate);
tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n",
srate, ratio, sample_rate, sample_gain);
return 0;
}
/*
* Based on the required frequency and symbolrate, the tuner AGC has
* to be configured and the correct band selected.
* Calculate those values.
*/
static int cx24123_pll_calculate(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cx24123_state *state = fe->demodulator_priv;
u32 ndiv = 0, adiv = 0, vco_div = 0;
int i = 0;
int pump = 2;
int band = 0;
int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
struct cx24123_bandselect_val *bsv = NULL;
struct cx24123_AGC_val *agcv = NULL;
/* Defaults for low freq, low rate */
state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
state->bandselectarg = cx24123_bandselect_vals[0].progdata;
vco_div = cx24123_bandselect_vals[0].VCOdivider;
/* For the given symbol rate, determine the VCA, VGA and
* FILTUNE programming bits */
for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
agcv = &cx24123_AGC_vals[i];
if ((agcv->symbolrate_low <= p->symbol_rate) &&
(agcv->symbolrate_high >= p->symbol_rate)) {
state->VCAarg = agcv->VCAprogdata;
state->VGAarg = agcv->VGAprogdata;
state->FILTune = agcv->FILTune;
}
}
/* determine the band to use */
if (force_band < 1 || force_band > num_bands) {
for (i = 0; i < num_bands; i++) {
bsv = &cx24123_bandselect_vals[i];
if ((bsv->freq_low <= p->frequency) &&
(bsv->freq_high >= p->frequency))
band = i;
}
} else
band = force_band - 1;
state->bandselectarg = cx24123_bandselect_vals[band].progdata;
vco_div = cx24123_bandselect_vals[band].VCOdivider;
/* determine the charge pump current */
if (p->frequency < (cx24123_bandselect_vals[band].freq_low +
cx24123_bandselect_vals[band].freq_high) / 2)
pump = 0x01;
else
pump = 0x02;
/* Determine the N/A dividers for the requested lband freq (in kHz). */
/* Note: the reference divider R=10, frequency is in KHz,
* XTAL is in Hz */
ndiv = (((p->frequency * vco_div * 10) /
(2 * XTAL / 1000)) / 32) & 0x1ff;
adiv = (((p->frequency * vco_div * 10) /
(2 * XTAL / 1000)) % 32) & 0x1f;
if (adiv == 0 && ndiv > 0)
ndiv--;
/* control bits 11, refdiv 11, charge pump polarity 1,
* charge pump current, ndiv, adiv */
state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) |
(pump << 14) | (ndiv << 5) | adiv;
return 0;
}
/*
* Tuner data is 21 bits long, must be left-aligned in data.
* Tuner cx24109 is written through a dedicated 3wire interface
* on the demod chip.
*/
static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
{
struct cx24123_state *state = fe->demodulator_priv;
unsigned long timeout;
dprintk("pll writereg called, data=0x%08x\n", data);
/* align the 21 bytes into to bit23 boundary */
data = data << 3;
/* Reset the demod pll word length to 0x15 bits */
cx24123_writereg(state, 0x21, 0x15);
/* write the msb 8 bits, wait for the send to be completed */
timeout = jiffies + msecs_to_jiffies(40);
cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
if (time_after(jiffies, timeout)) {
err("%s: demodulator is not responding, "\
"possibly hung, aborting.\n", __func__);
return -EREMOTEIO;
}
msleep(10);
}
/* send another 8 bytes, wait for the send to be completed */
timeout = jiffies + msecs_to_jiffies(40);
cx24123_writereg(state, 0x22, (data >> 8) & 0xff);
while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
if (time_after(jiffies, timeout)) {
err("%s: demodulator is not responding, "\
"possibly hung, aborting.\n", __func__);
return -EREMOTEIO;
}
msleep(10);
}
/* send the lower 5 bits of this byte, padded with 3 LBB,
* wait for the send to be completed */
timeout = jiffies + msecs_to_jiffies(40);
cx24123_writereg(state, 0x22, (data) & 0xff);
while ((cx24123_readreg(state, 0x20) & 0x80)) {
if (time_after(jiffies, timeout)) {
err("%s: demodulator is not responding," \
"possibly hung, aborting.\n", __func__);
return -EREMOTEIO;
}
msleep(10);
}
/* Trigger the demod to configure the tuner */
cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
return 0;
}
static int cx24123_pll_tune(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cx24123_state *state = fe->demodulator_priv;
u8 val;
dprintk("frequency=%i\n", p->frequency);
if (cx24123_pll_calculate(fe) != 0) {
err("%s: cx24123_pll_calculate failed\n", __func__);
return -EINVAL;
}
/* Write the new VCO/VGA */
cx24123_pll_writereg(fe, state->VCAarg);
cx24123_pll_writereg(fe, state->VGAarg);
/* Write the new bandselect and pll args */
cx24123_pll_writereg(fe, state->bandselectarg);
cx24123_pll_writereg(fe, state->pllarg);
/* set the FILTUNE voltage */
val = cx24123_readreg(state, 0x28) & ~0x3;
cx24123_writereg(state, 0x27, state->FILTune >> 2);
cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg,
state->bandselectarg, state->pllarg);
return 0;
}
/*
* 0x23:
* [7:7] = BTI enabled
* [6:6] = I2C repeater enabled
* [5:5] = I2C repeater start
* [0:0] = BTI start
*/
/* mode == 1 -> i2c-repeater, 0 -> bti */
static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start)
{
u8 r = cx24123_readreg(state, 0x23) & 0x1e;
if (mode)
r |= (1 << 6) | (start << 5);
else
r |= (1 << 7) | (start);
return cx24123_writereg(state, 0x23, r);
}
static int cx24123_initfe(struct dvb_frontend *fe)
{
struct cx24123_state *state = fe->demodulator_priv;
int i;
dprintk("init frontend\n");
/* Configure the demod to a good set of defaults */
for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
cx24123_writereg(state, cx24123_regdata[i].reg,
cx24123_regdata[i].data);
/* Set the LNB polarity */
if (state->config->lnb_polarity)
cx24123_writereg(state, 0x32,
cx24123_readreg(state, 0x32) | 0x02);
if (state->config->dont_use_pll)
cx24123_repeater_mode(state, 1, 0);
return 0;
}
static int cx24123_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx24123_state *state = fe->demodulator_priv;
u8 val;
val = cx24123_readreg(state, 0x29) & ~0x40;
switch (voltage) {
case SEC_VOLTAGE_13:
dprintk("setting voltage 13V\n");
return cx24123_writereg(state, 0x29, val & 0x7f);
case SEC_VOLTAGE_18:
dprintk("setting voltage 18V\n");
return cx24123_writereg(state, 0x29, val | 0x80);
case SEC_VOLTAGE_OFF:
/* already handled in cx88-dvb */
return 0;
default:
return -EINVAL;
}
return 0;
}
/* wait for diseqc queue to become ready (or timeout) */
static void cx24123_wait_for_diseqc(struct cx24123_state *state)
{
unsigned long timeout = jiffies + msecs_to_jiffies(200);
while (!(cx24123_readreg(state, 0x29) & 0x40)) {
if (time_after(jiffies, timeout)) {
err("%s: diseqc queue not ready, " \
"command may be lost.\n", __func__);
break;
}
msleep(10);
}
}
static int cx24123_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct cx24123_state *state = fe->demodulator_priv;
int i, val, tone;
dprintk("\n");
/* stop continuous tone if enabled */
tone = cx24123_readreg(state, 0x29);
if (tone & 0x10)
cx24123_writereg(state, 0x29, tone & ~0x50);
/* wait for diseqc queue ready */
cx24123_wait_for_diseqc(state);
/* select tone mode */
cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
for (i = 0; i < cmd->msg_len; i++)
cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
val = cx24123_readreg(state, 0x29);
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) |
((cmd->msg_len-3) & 3));
/* wait for diseqc message to finish sending */
cx24123_wait_for_diseqc(state);
/* restart continuous tone if enabled */
if (tone & 0x10)
cx24123_writereg(state, 0x29, tone & ~0x40);
return 0;
}
static int cx24123_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct cx24123_state *state = fe->demodulator_priv;
int val, tone;
dprintk("\n");
/* stop continuous tone if enabled */
tone = cx24123_readreg(state, 0x29);
if (tone & 0x10)
cx24123_writereg(state, 0x29, tone & ~0x50);
/* wait for diseqc queue ready */
cx24123_wait_for_diseqc(state);
/* select tone mode */
cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
msleep(30);
val = cx24123_readreg(state, 0x29);
if (burst == SEC_MINI_A)
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
else if (burst == SEC_MINI_B)
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
else
return -EINVAL;
cx24123_wait_for_diseqc(state);
cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
/* restart continuous tone if enabled */
if (tone & 0x10)
cx24123_writereg(state, 0x29, tone & ~0x40);
return 0;
}
static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx24123_state *state = fe->demodulator_priv;
int sync = cx24123_readreg(state, 0x14);
*status = 0;
if (state->config->dont_use_pll) {
u32 tun_status = 0;
if (fe->ops.tuner_ops.get_status)
fe->ops.tuner_ops.get_status(fe, &tun_status);
if (tun_status & TUNER_STATUS_LOCKED)
*status |= FE_HAS_SIGNAL;
} else {
int lock = cx24123_readreg(state, 0x20);
if (lock & 0x01)
*status |= FE_HAS_SIGNAL;
}
if (sync & 0x02)
*status |= FE_HAS_CARRIER; /* Phase locked */
if (sync & 0x04)
*status |= FE_HAS_VITERBI;
/* Reed-Solomon Status */
if (sync & 0x08)
*status |= FE_HAS_SYNC;
if (sync & 0x80)
*status |= FE_HAS_LOCK; /*Full Sync */
return 0;
}
/*
* Configured to return the measurement of errors in blocks,
* because no UCBLOCKS value is available, so this value doubles up
* to satisfy both measurements.
*/
static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cx24123_state *state = fe->demodulator_priv;
/* The true bit error rate is this value divided by
the window size (set as 256 * 255) */
*ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
(cx24123_readreg(state, 0x1d) << 8 |
cx24123_readreg(state, 0x1e));
dprintk("BER = %d\n", *ber);
return 0;
}
static int cx24123_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct cx24123_state *state = fe->demodulator_priv;
/* larger = better */
*signal_strength = cx24123_readreg(state, 0x3b) << 8;
dprintk("Signal strength = %d\n", *signal_strength);
return 0;
}
static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct cx24123_state *state = fe->demodulator_priv;
/* Inverted raw Es/N0 count, totally bogus but better than the
BER threshold. */
*snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
(u16)cx24123_readreg(state, 0x19));
dprintk("read S/N index = %d\n", *snr);
return 0;
}
static int cx24123_set_frontend(struct dvb_frontend *fe)
{
struct cx24123_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dprintk("\n");
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
state->currentfreq = p->frequency;
state->currentsymbolrate = p->symbol_rate;
cx24123_set_inversion(state, p->inversion);
cx24123_set_fec(state, p->fec_inner);
cx24123_set_symbolrate(state, p->symbol_rate);
if (!state->config->dont_use_pll)
cx24123_pll_tune(fe);
else if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
else
err("it seems I don't have a tuner...");
/* Enable automatic acquisition and reset cycle */
cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
cx24123_writereg(state, 0x00, 0x10);
cx24123_writereg(state, 0x00, 0);
if (state->config->agc_callback)
state->config->agc_callback(fe);
return 0;
}
static int cx24123_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct cx24123_state *state = fe->demodulator_priv;
dprintk("\n");
if (cx24123_get_inversion(state, &p->inversion) != 0) {
err("%s: Failed to get inversion status\n", __func__);
return -EREMOTEIO;
}
if (cx24123_get_fec(state, &p->fec_inner) != 0) {
err("%s: Failed to get fec status\n", __func__);
return -EREMOTEIO;
}
p->frequency = state->currentfreq;
p->symbol_rate = state->currentsymbolrate;
return 0;
}
static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct cx24123_state *state = fe->demodulator_priv;
u8 val;
/* wait for diseqc queue ready */
cx24123_wait_for_diseqc(state);
val = cx24123_readreg(state, 0x29) & ~0x40;
switch (tone) {
case SEC_TONE_ON:
dprintk("setting tone on\n");
return cx24123_writereg(state, 0x29, val | 0x10);
case SEC_TONE_OFF:
dprintk("setting tone off\n");
return cx24123_writereg(state, 0x29, val & 0xef);
default:
err("CASE reached default with tone=%d\n", tone);
return -EINVAL;
}
return 0;
}
static int cx24123_tune(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
int retval = 0;
if (re_tune)
retval = cx24123_set_frontend(fe);
if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
cx24123_read_status(fe, status);
*delay = HZ/10;
return retval;
}
static enum dvbfe_algo cx24123_get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static void cx24123_release(struct dvb_frontend *fe)
{
struct cx24123_state *state = fe->demodulator_priv;
dprintk("\n");
i2c_del_adapter(&state->tuner_i2c_adapter);
kfree(state);
}
static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct cx24123_state *state = i2c_get_adapdata(i2c_adap);
/* this repeater closes after the first stop */
cx24123_repeater_mode(state, 1, 1);
return i2c_transfer(state->i2c, msg, num);
}
static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm cx24123_tuner_i2c_algo = {
.master_xfer = cx24123_tuner_i2c_tuner_xfer,
.functionality = cx24123_tuner_i2c_func,
};
struct i2c_adapter *
cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
struct cx24123_state *state = fe->demodulator_priv;
return &state->tuner_i2c_adapter;
}
EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter);
static const struct dvb_frontend_ops cx24123_ops;
struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
struct i2c_adapter *i2c)
{
/* allocate memory for the internal state */
struct cx24123_state *state =
kzalloc(sizeof(struct cx24123_state), GFP_KERNEL);
dprintk("\n");
if (state == NULL) {
err("Unable to kzalloc\n");
goto error;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
state->demod_rev = cx24123_readreg(state, 0x00);
switch (state->demod_rev) {
case 0xe1:
info("detected CX24123C\n");
break;
case 0xd1:
info("detected CX24123\n");
break;
default:
err("wrong demod revision: %x\n", state->demod_rev);
goto error;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx24123_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* create tuner i2c adapter */
if (config->dont_use_pll)
cx24123_repeater_mode(state, 1, 0);
strscpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus",
sizeof(state->tuner_i2c_adapter.name));
state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo;
state->tuner_i2c_adapter.algo_data = NULL;
state->tuner_i2c_adapter.dev.parent = i2c->dev.parent;
i2c_set_adapdata(&state->tuner_i2c_adapter, state);
if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
err("tuner i2c bus could not be initialized\n");
goto error;
}
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(cx24123_attach);
static const struct dvb_frontend_ops cx24123_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Conexant CX24123/CX24109",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = cx24123_release,
.init = cx24123_initfe,
.set_frontend = cx24123_set_frontend,
.get_frontend = cx24123_get_frontend,
.read_status = cx24123_read_status,
.read_ber = cx24123_read_ber,
.read_signal_strength = cx24123_read_signal_strength,
.read_snr = cx24123_read_snr,
.diseqc_send_master_cmd = cx24123_send_diseqc_msg,
.diseqc_send_burst = cx24123_diseqc_send_burst,
.set_tone = cx24123_set_tone,
.set_voltage = cx24123_set_voltage,
.tune = cx24123_tune,
.get_frontend_algo = cx24123_get_algo,
};
MODULE_DESCRIPTION("DVB Frontend module for Conexant " \
"CX24123/CX24109/CX24113 hardware");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cx24123.c |
// SPDX-License-Identifier: GPL-2.0-only
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include "dibx000_common.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
mst->i2c_write_buffer[0] = (reg >> 8) & 0xff;
mst->i2c_write_buffer[1] = reg & 0xff;
mst->i2c_write_buffer[2] = (val >> 8) & 0xff;
mst->i2c_write_buffer[3] = val & 0xff;
memset(mst->msg, 0, sizeof(struct i2c_msg));
mst->msg[0].addr = mst->i2c_addr;
mst->msg[0].flags = 0;
mst->msg[0].buf = mst->i2c_write_buffer;
mst->msg[0].len = 4;
ret = i2c_transfer(mst->i2c_adap, mst->msg, 1) != 1 ? -EREMOTEIO : 0;
mutex_unlock(&mst->i2c_buffer_lock);
return ret;
}
static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg)
{
u16 ret;
if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
mst->i2c_write_buffer[0] = reg >> 8;
mst->i2c_write_buffer[1] = reg & 0xff;
memset(mst->msg, 0, 2 * sizeof(struct i2c_msg));
mst->msg[0].addr = mst->i2c_addr;
mst->msg[0].flags = 0;
mst->msg[0].buf = mst->i2c_write_buffer;
mst->msg[0].len = 2;
mst->msg[1].addr = mst->i2c_addr;
mst->msg[1].flags = I2C_M_RD;
mst->msg[1].buf = mst->i2c_read_buffer;
mst->msg[1].len = 2;
if (i2c_transfer(mst->i2c_adap, mst->msg, 2) != 2)
dprintk("i2c read error on %d\n", reg);
ret = (mst->i2c_read_buffer[0] << 8) | mst->i2c_read_buffer[1];
mutex_unlock(&mst->i2c_buffer_lock);
return ret;
}
static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
{
int i = 100;
u16 status;
while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
;
/* i2c timed out */
if (i == 0)
return -EREMOTEIO;
/* no acknowledge */
if ((status & 0x0080) == 0)
return -EREMOTEIO;
return 0;
}
static int dibx000_master_i2c_write(struct dibx000_i2c_master *mst, struct i2c_msg *msg, u8 stop)
{
u16 data;
u16 da;
u16 i;
u16 txlen = msg->len, len;
const u8 *b = msg->buf;
while (txlen) {
dibx000_read_word(mst, mst->base_reg + 2);
len = txlen > 8 ? 8 : txlen;
for (i = 0; i < len; i += 2) {
data = *b++ << 8;
if (i+1 < len)
data |= *b++;
dibx000_write_word(mst, mst->base_reg, data);
}
da = (((u8) (msg->addr)) << 9) |
(1 << 8) |
(1 << 7) |
(0 << 6) |
(0 << 5) |
((len & 0x7) << 2) |
(0 << 1) |
(0 << 0);
if (txlen == msg->len)
da |= 1 << 5; /* start */
if (txlen-len == 0 && stop)
da |= 1 << 6; /* stop */
dibx000_write_word(mst, mst->base_reg+1, da);
if (dibx000_is_i2c_done(mst) != 0)
return -EREMOTEIO;
txlen -= len;
}
return 0;
}
static int dibx000_master_i2c_read(struct dibx000_i2c_master *mst, struct i2c_msg *msg)
{
u16 da;
u8 *b = msg->buf;
u16 rxlen = msg->len, len;
while (rxlen) {
len = rxlen > 8 ? 8 : rxlen;
da = (((u8) (msg->addr)) << 9) |
(1 << 8) |
(1 << 7) |
(0 << 6) |
(0 << 5) |
((len & 0x7) << 2) |
(1 << 1) |
(0 << 0);
if (rxlen == msg->len)
da |= 1 << 5; /* start */
if (rxlen-len == 0)
da |= 1 << 6; /* stop */
dibx000_write_word(mst, mst->base_reg+1, da);
if (dibx000_is_i2c_done(mst) != 0)
return -EREMOTEIO;
rxlen -= len;
while (len) {
da = dibx000_read_word(mst, mst->base_reg);
*b++ = (da >> 8) & 0xff;
len--;
if (len >= 1) {
*b++ = da & 0xff;
len--;
}
}
}
return 0;
}
int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
if (mst->device_rev < DIB7000MC && speed < 235)
speed = 235;
return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
}
EXPORT_SYMBOL(dibx000_i2c_set_speed);
static u32 dibx000_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
enum dibx000_i2c_interface intf)
{
if (mst->device_rev > DIB3000MC && mst->selected_interface != intf) {
dprintk("selecting interface: %d\n", intf);
mst->selected_interface = intf;
return dibx000_write_word(mst, mst->base_reg + 4, intf);
}
return 0;
}
static int dibx000_i2c_master_xfer_gpio12(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
int msg_index;
int ret = 0;
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_1_2);
for (msg_index = 0; msg_index < num; msg_index++) {
if (msg[msg_index].flags & I2C_M_RD) {
ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
if (ret != 0)
return 0;
} else {
ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
if (ret != 0)
return 0;
}
}
return num;
}
static int dibx000_i2c_master_xfer_gpio34(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
int msg_index;
int ret = 0;
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_3_4);
for (msg_index = 0; msg_index < num; msg_index++) {
if (msg[msg_index].flags & I2C_M_RD) {
ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
if (ret != 0)
return 0;
} else {
ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
if (ret != 0)
return 0;
}
}
return num;
}
static struct i2c_algorithm dibx000_i2c_master_gpio12_xfer_algo = {
.master_xfer = dibx000_i2c_master_xfer_gpio12,
.functionality = dibx000_i2c_func,
};
static struct i2c_algorithm dibx000_i2c_master_gpio34_xfer_algo = {
.master_xfer = dibx000_i2c_master_xfer_gpio34,
.functionality = dibx000_i2c_func,
};
static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
u8 addr, int onoff)
{
u16 val;
if (onoff)
val = addr << 8; // bit 7 = use master or not, if 0, the gate is open
else
val = 1 << 7;
if (mst->device_rev > DIB7000)
val <<= 1;
tx[0] = (((mst->base_reg + 1) >> 8) & 0xff);
tx[1] = ((mst->base_reg + 1) & 0xff);
tx[2] = val >> 8;
tx[3] = val & 0xff;
return 0;
}
static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
int ret;
if (num > 32) {
dprintk("%s: too much I2C message to be transmitted (%i). Maximum is 32",
__func__, num);
return -ENOMEM;
}
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7);
if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
/* open the gate */
dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
mst->msg[0].addr = mst->i2c_addr;
mst->msg[0].buf = &mst->i2c_write_buffer[0];
mst->msg[0].len = 4;
memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
/* close the gate */
dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
mst->msg[num + 1].addr = mst->i2c_addr;
mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
mst->msg[num + 1].len = 4;
ret = (i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ?
num : -EIO);
mutex_unlock(&mst->i2c_buffer_lock);
return ret;
}
static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = {
.master_xfer = dibx000_i2c_gated_gpio67_xfer,
.functionality = dibx000_i2c_func,
};
static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
int ret;
if (num > 32) {
dprintk("%s: too much I2C message to be transmitted (%i). Maximum is 32",
__func__, num);
return -ENOMEM;
}
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER);
if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
/* open the gate */
dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
mst->msg[0].addr = mst->i2c_addr;
mst->msg[0].buf = &mst->i2c_write_buffer[0];
mst->msg[0].len = 4;
memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
/* close the gate */
dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
mst->msg[num + 1].addr = mst->i2c_addr;
mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
mst->msg[num + 1].len = 4;
ret = (i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ?
num : -EIO);
mutex_unlock(&mst->i2c_buffer_lock);
return ret;
}
static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = {
.master_xfer = dibx000_i2c_gated_tuner_xfer,
.functionality = dibx000_i2c_func,
};
struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
enum dibx000_i2c_interface intf,
int gating)
{
struct i2c_adapter *i2c = NULL;
switch (intf) {
case DIBX000_I2C_INTERFACE_TUNER:
if (gating)
i2c = &mst->gated_tuner_i2c_adap;
break;
case DIBX000_I2C_INTERFACE_GPIO_1_2:
if (!gating)
i2c = &mst->master_i2c_adap_gpio12;
break;
case DIBX000_I2C_INTERFACE_GPIO_3_4:
if (!gating)
i2c = &mst->master_i2c_adap_gpio34;
break;
case DIBX000_I2C_INTERFACE_GPIO_6_7:
if (gating)
i2c = &mst->master_i2c_adap_gpio67;
break;
default:
pr_err("incorrect I2C interface selected\n");
break;
}
return i2c;
}
EXPORT_SYMBOL(dibx000_get_i2c_adapter);
void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst)
{
/* initialize the i2c-master by closing the gate */
u8 tx[4];
struct i2c_msg m = {.addr = mst->i2c_addr,.buf = tx,.len = 4 };
dibx000_i2c_gate_ctrl(mst, tx, 0, 0);
i2c_transfer(mst->i2c_adap, &m, 1);
mst->selected_interface = 0xff; // the first time force a select of the I2C
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER);
}
EXPORT_SYMBOL(dibx000_reset_i2c_master);
static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
struct i2c_algorithm *algo, const char *name,
struct dibx000_i2c_master *mst)
{
strscpy(i2c_adap->name, name, sizeof(i2c_adap->name));
i2c_adap->algo = algo;
i2c_adap->algo_data = NULL;
i2c_set_adapdata(i2c_adap, mst);
if (i2c_add_adapter(i2c_adap) < 0)
return -ENODEV;
return 0;
}
int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
struct i2c_adapter *i2c_adap, u8 i2c_addr)
{
int ret;
mutex_init(&mst->i2c_buffer_lock);
if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
memset(mst->msg, 0, sizeof(struct i2c_msg));
mst->msg[0].addr = i2c_addr >> 1;
mst->msg[0].flags = 0;
mst->msg[0].buf = mst->i2c_write_buffer;
mst->msg[0].len = 4;
mst->device_rev = device_rev;
mst->i2c_adap = i2c_adap;
mst->i2c_addr = i2c_addr >> 1;
if (device_rev == DIB7000P || device_rev == DIB8000)
mst->base_reg = 1024;
else
mst->base_reg = 768;
mst->gated_tuner_i2c_adap.dev.parent = mst->i2c_adap->dev.parent;
if (i2c_adapter_init
(&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo,
"DiBX000 tuner I2C bus", mst) != 0)
pr_err("could not initialize the tuner i2c_adapter\n");
mst->master_i2c_adap_gpio12.dev.parent = mst->i2c_adap->dev.parent;
if (i2c_adapter_init
(&mst->master_i2c_adap_gpio12, &dibx000_i2c_master_gpio12_xfer_algo,
"DiBX000 master GPIO12 I2C bus", mst) != 0)
pr_err("could not initialize the master i2c_adapter\n");
mst->master_i2c_adap_gpio34.dev.parent = mst->i2c_adap->dev.parent;
if (i2c_adapter_init
(&mst->master_i2c_adap_gpio34, &dibx000_i2c_master_gpio34_xfer_algo,
"DiBX000 master GPIO34 I2C bus", mst) != 0)
pr_err("could not initialize the master i2c_adapter\n");
mst->master_i2c_adap_gpio67.dev.parent = mst->i2c_adap->dev.parent;
if (i2c_adapter_init
(&mst->master_i2c_adap_gpio67, &dibx000_i2c_gated_gpio67_algo,
"DiBX000 master GPIO67 I2C bus", mst) != 0)
pr_err("could not initialize the master i2c_adapter\n");
/* initialize the i2c-master by closing the gate */
dibx000_i2c_gate_ctrl(mst, mst->i2c_write_buffer, 0, 0);
ret = (i2c_transfer(i2c_adap, mst->msg, 1) == 1);
mutex_unlock(&mst->i2c_buffer_lock);
return ret;
}
EXPORT_SYMBOL(dibx000_init_i2c_master);
void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
{
i2c_del_adapter(&mst->gated_tuner_i2c_adap);
i2c_del_adapter(&mst->master_i2c_adap_gpio12);
i2c_del_adapter(&mst->master_i2c_adap_gpio34);
i2c_del_adapter(&mst->master_i2c_adap_gpio67);
}
EXPORT_SYMBOL(dibx000_exit_i2c_master);
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Common function the DiBcom demodulator family");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dibx000_common.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for OR51211 (pcHDTV HD-2000) - VSB
*
* Copyright (C) 2005 Kirk Lapray <[email protected]>
*
* Based on code from Jack Kelliher ([email protected])
* Copyright (C) 2002 & pcHDTV, inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
/*
* This driver needs external firmware. Please use the command
* "<kerneldir>/scripts/get_dvb_firmware or51211" to
* download/extract it, and then copy it to /usr/lib/hotplug/firmware
* or /lib/firmware (depending on configuration of firmware hotplug).
*/
#define OR51211_DEFAULT_FIRMWARE "dvb-fe-or51211.fw"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "or51211.h"
static int debug;
#define dprintk(args...) \
do { if (debug) pr_debug(args); } while (0)
static u8 run_buf[] = {0x7f,0x01};
static u8 cmd_buf[] = {0x04,0x01,0x50,0x80,0x06}; // ATSC
struct or51211_state {
struct i2c_adapter* i2c;
/* Configuration settings */
const struct or51211_config* config;
struct dvb_frontend frontend;
struct bt878* bt;
/* Demodulator private data */
u8 initialized:1;
u32 snr; /* Result of last SNR calculation */
/* Tuner private data */
u32 current_frequency;
};
static int i2c_writebytes (struct or51211_state* state, u8 reg, const u8 *buf,
int len)
{
int err;
struct i2c_msg msg;
msg.addr = reg;
msg.flags = 0;
msg.len = len;
msg.buf = (u8 *)buf;
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
pr_warn("error (addr %02x, err == %i)\n", reg, err);
return -EREMOTEIO;
}
return 0;
}
static int i2c_readbytes(struct or51211_state *state, u8 reg, u8 *buf, int len)
{
int err;
struct i2c_msg msg;
msg.addr = reg;
msg.flags = I2C_M_RD;
msg.len = len;
msg.buf = buf;
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
pr_warn("error (addr %02x, err == %i)\n", reg, err);
return -EREMOTEIO;
}
return 0;
}
static int or51211_load_firmware (struct dvb_frontend* fe,
const struct firmware *fw)
{
struct or51211_state* state = fe->demodulator_priv;
u8 tudata[585];
int i;
dprintk("Firmware is %zu bytes\n", fw->size);
/* Get eprom data */
tudata[0] = 17;
if (i2c_writebytes(state,0x50,tudata,1)) {
pr_warn("error eprom addr\n");
return -1;
}
if (i2c_readbytes(state,0x50,&tudata[145],192)) {
pr_warn("error eprom\n");
return -1;
}
/* Create firmware buffer */
for (i = 0; i < 145; i++)
tudata[i] = fw->data[i];
for (i = 0; i < 248; i++)
tudata[i+337] = fw->data[145+i];
state->config->reset(fe);
if (i2c_writebytes(state,state->config->demod_address,tudata,585)) {
pr_warn("error 1\n");
return -1;
}
msleep(1);
if (i2c_writebytes(state,state->config->demod_address,
&fw->data[393],8125)) {
pr_warn("error 2\n");
return -1;
}
msleep(1);
if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
pr_warn("error 3\n");
return -1;
}
/* Wait at least 5 msec */
msleep(10);
if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
pr_warn("error 4\n");
return -1;
}
msleep(10);
pr_info("Done.\n");
return 0;
};
static int or51211_setmode(struct dvb_frontend* fe, int mode)
{
struct or51211_state* state = fe->demodulator_priv;
u8 rec_buf[14];
state->config->setmode(fe, mode);
if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
pr_warn("error 1\n");
return -1;
}
/* Wait at least 5 msec */
msleep(10);
if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
pr_warn("error 2\n");
return -1;
}
msleep(10);
/* Set operation mode in Receiver 1 register;
* type 1:
* data 0x50h Automatic sets receiver channel conditions
* Automatic NTSC rejection filter
* Enable MPEG serial data output
* MPEG2tr
* High tuner phase noise
* normal +/-150kHz Carrier acquisition range
*/
if (i2c_writebytes(state,state->config->demod_address,cmd_buf,3)) {
pr_warn("error 3\n");
return -1;
}
rec_buf[0] = 0x04;
rec_buf[1] = 0x00;
rec_buf[2] = 0x03;
rec_buf[3] = 0x00;
msleep(20);
if (i2c_writebytes(state,state->config->demod_address,rec_buf,3)) {
pr_warn("error 5\n");
}
msleep(3);
if (i2c_readbytes(state,state->config->demod_address,&rec_buf[10],2)) {
pr_warn("error 6\n");
return -1;
}
dprintk("rec status %02x %02x\n", rec_buf[10], rec_buf[11]);
return 0;
}
static int or51211_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct or51211_state* state = fe->demodulator_priv;
/* Change only if we are actually changing the channel */
if (state->current_frequency != p->frequency) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Set to ATSC mode */
or51211_setmode(fe,0);
/* Update current frequency */
state->current_frequency = p->frequency;
}
return 0;
}
static int or51211_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct or51211_state* state = fe->demodulator_priv;
unsigned char rec_buf[2];
unsigned char snd_buf[] = {0x04,0x00,0x03,0x00};
*status = 0;
/* Receiver Status */
if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) {
pr_warn("write error\n");
return -1;
}
msleep(3);
if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
pr_warn("read error\n");
return -1;
}
dprintk("%x %x\n", rec_buf[0], rec_buf[1]);
if (rec_buf[0] & 0x01) { /* Receiver Lock */
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
}
return 0;
}
/* Calculate SNR estimation (scaled by 2^24)
8-VSB SNR equation from Oren datasheets
For 8-VSB:
SNR[dB] = 10 * log10(219037.9454 / MSE^2 )
We re-write the snr equation as:
SNR * 2^24 = 10*(c - 2*intlog10(MSE))
Where for 8-VSB, c = log10(219037.9454) * 2^24 */
static u32 calculate_snr(u32 mse, u32 c)
{
if (mse == 0) /* No signal */
return 0;
mse = 2*intlog10(mse);
if (mse > c) {
/* Negative SNR, which is possible, but realisticly the
demod will lose lock before the signal gets this bad. The
API only allows for unsigned values, so just return 0 */
return 0;
}
return 10*(c - mse);
}
static int or51211_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct or51211_state* state = fe->demodulator_priv;
u8 rec_buf[2];
u8 snd_buf[3];
/* SNR after Equalizer */
snd_buf[0] = 0x04;
snd_buf[1] = 0x00;
snd_buf[2] = 0x04;
if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) {
pr_warn("error writing snr reg\n");
return -1;
}
if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
pr_warn("read_status read error\n");
return -1;
}
state->snr = calculate_snr(rec_buf[0], 89599047);
*snr = (state->snr) >> 16;
dprintk("noise = 0x%02x, snr = %d.%02d dB\n", rec_buf[0],
state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
return 0;
}
static int or51211_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
/* Calculate Strength from SNR up to 35dB */
/* Even though the SNR can go higher than 35dB, there is some comfort */
/* factor in having a range of strong signals that can show at 100% */
struct or51211_state* state = (struct or51211_state*)fe->demodulator_priv;
u16 snr;
int ret;
ret = fe->ops.read_snr(fe, &snr);
if (ret != 0)
return ret;
/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
/* scale the range 0 - 35*2^24 into 0 - 65535 */
if (state->snr >= 8960 * 0x10000)
*strength = 0xffff;
else
*strength = state->snr / 8960;
return 0;
}
static int or51211_read_ber(struct dvb_frontend* fe, u32* ber)
{
*ber = -ENOSYS;
return 0;
}
static int or51211_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
*ucblocks = -ENOSYS;
return 0;
}
static int or51211_sleep(struct dvb_frontend* fe)
{
return 0;
}
static int or51211_init(struct dvb_frontend* fe)
{
struct or51211_state* state = fe->demodulator_priv;
const struct or51211_config* config = state->config;
const struct firmware* fw;
unsigned char get_ver_buf[] = {0x04,0x00,0x30,0x00,0x00};
unsigned char rec_buf[14];
int ret,i;
if (!state->initialized) {
/* Request the firmware, this will block until it uploads */
pr_info("Waiting for firmware upload (%s)...\n",
OR51211_DEFAULT_FIRMWARE);
ret = config->request_firmware(fe, &fw,
OR51211_DEFAULT_FIRMWARE);
pr_info("Got Hotplug firmware\n");
if (ret) {
pr_warn("No firmware uploaded (timeout or file not found?)\n");
return ret;
}
ret = or51211_load_firmware(fe, fw);
release_firmware(fw);
if (ret) {
pr_warn("Writing firmware to device failed!\n");
return ret;
}
pr_info("Firmware upload complete.\n");
/* Set operation mode in Receiver 1 register;
* type 1:
* data 0x50h Automatic sets receiver channel conditions
* Automatic NTSC rejection filter
* Enable MPEG serial data output
* MPEG2tr
* High tuner phase noise
* normal +/-150kHz Carrier acquisition range
*/
if (i2c_writebytes(state,state->config->demod_address,
cmd_buf,3)) {
pr_warn("Load DVR Error 5\n");
return -1;
}
/* Read back ucode version to besure we loaded correctly */
/* and are really up and running */
rec_buf[0] = 0x04;
rec_buf[1] = 0x00;
rec_buf[2] = 0x03;
rec_buf[3] = 0x00;
msleep(30);
if (i2c_writebytes(state,state->config->demod_address,
rec_buf,3)) {
pr_warn("Load DVR Error A\n");
return -1;
}
msleep(3);
if (i2c_readbytes(state,state->config->demod_address,
&rec_buf[10],2)) {
pr_warn("Load DVR Error B\n");
return -1;
}
rec_buf[0] = 0x04;
rec_buf[1] = 0x00;
rec_buf[2] = 0x01;
rec_buf[3] = 0x00;
msleep(20);
if (i2c_writebytes(state,state->config->demod_address,
rec_buf,3)) {
pr_warn("Load DVR Error C\n");
return -1;
}
msleep(3);
if (i2c_readbytes(state,state->config->demod_address,
&rec_buf[12],2)) {
pr_warn("Load DVR Error D\n");
return -1;
}
for (i = 0; i < 8; i++)
rec_buf[i]=0xed;
for (i = 0; i < 5; i++) {
msleep(30);
get_ver_buf[4] = i+1;
if (i2c_writebytes(state,state->config->demod_address,
get_ver_buf,5)) {
pr_warn("Load DVR Error 6 - %d\n", i);
return -1;
}
msleep(3);
if (i2c_readbytes(state,state->config->demod_address,
&rec_buf[i*2],2)) {
pr_warn("Load DVR Error 7 - %d\n", i);
return -1;
}
/* If we didn't receive the right index, try again */
if ((int)rec_buf[i*2+1]!=i+1){
i--;
}
}
dprintk("read_fwbits %10ph\n", rec_buf);
pr_info("ver TU%02x%02x%02x VSB mode %02x Status %02x\n",
rec_buf[2], rec_buf[4], rec_buf[6], rec_buf[12],
rec_buf[10]);
rec_buf[0] = 0x04;
rec_buf[1] = 0x00;
rec_buf[2] = 0x03;
rec_buf[3] = 0x00;
msleep(20);
if (i2c_writebytes(state,state->config->demod_address,
rec_buf,3)) {
pr_warn("Load DVR Error 8\n");
return -1;
}
msleep(20);
if (i2c_readbytes(state,state->config->demod_address,
&rec_buf[8],2)) {
pr_warn("Load DVR Error 9\n");
return -1;
}
state->initialized = 1;
}
return 0;
}
static int or51211_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 500;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void or51211_release(struct dvb_frontend* fe)
{
struct or51211_state* state = fe->demodulator_priv;
state->config->sleep(fe);
kfree(state);
}
static const struct dvb_frontend_ops or51211_ops;
struct dvb_frontend* or51211_attach(const struct or51211_config* config,
struct i2c_adapter* i2c)
{
struct or51211_state* state = NULL;
/* Allocate memory for the internal state */
state = kzalloc(sizeof(struct or51211_state), GFP_KERNEL);
if (state == NULL)
return NULL;
/* Setup the state */
state->config = config;
state->i2c = i2c;
state->initialized = 0;
state->current_frequency = 0;
/* Create dvb_frontend */
memcpy(&state->frontend.ops, &or51211_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
static const struct dvb_frontend_ops or51211_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Oren OR51211 VSB Frontend",
.frequency_min_hz = 44 * MHz,
.frequency_max_hz = 958 * MHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_8VSB
},
.release = or51211_release,
.init = or51211_init,
.sleep = or51211_sleep,
.set_frontend = or51211_set_parameters,
.get_tune_settings = or51211_get_tune_settings,
.read_status = or51211_read_status,
.read_ber = or51211_read_ber,
.read_signal_strength = or51211_read_signal_strength,
.read_snr = or51211_read_snr,
.read_ucblocks = or51211_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Oren OR51211 VSB [pcHDTV HD-2000] Demodulator Driver");
MODULE_AUTHOR("Kirk Lapray");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(or51211_attach);
| linux-master | drivers/media/dvb-frontends/or51211.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tda18271c2dd: Driver for the TDA18271C2 tuner
*
* Copyright (C) 2010 Digital Devices GmbH
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "tda18271c2dd.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
struct SStandardParam {
s32 m_IFFrequency;
u32 m_BandWidth;
u8 m_EP3_4_0;
u8 m_EB22;
};
struct SMap {
u32 m_Frequency;
u8 m_Param;
};
struct SMapI {
u32 m_Frequency;
s32 m_Param;
};
struct SMap2 {
u32 m_Frequency;
u8 m_Param1;
u8 m_Param2;
};
struct SRFBandMap {
u32 m_RF_max;
u32 m_RF1_Default;
u32 m_RF2_Default;
u32 m_RF3_Default;
};
enum ERegister {
ID = 0,
TM,
PL,
EP1, EP2, EP3, EP4, EP5,
CPD, CD1, CD2, CD3,
MPD, MD1, MD2, MD3,
EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
EB21, EB22, EB23,
NUM_REGS
};
struct tda_state {
struct i2c_adapter *i2c;
u8 adr;
u32 m_Frequency;
u32 IF;
u8 m_IFLevelAnalog;
u8 m_IFLevelDigital;
u8 m_IFLevelDVBC;
u8 m_IFLevelDVBT;
u8 m_EP4;
u8 m_EP3_Standby;
bool m_bMaster;
s32 m_SettlingTime;
u8 m_Regs[NUM_REGS];
/* Tracking filter settings for band 0..6 */
u32 m_RF1[7];
s32 m_RF_A1[7];
s32 m_RF_B1[7];
u32 m_RF2[7];
s32 m_RF_A2[7];
s32 m_RF_B2[7];
u32 m_RF3[7];
u8 m_TMValue_RFCal; /* Calibration temperature */
bool m_bFMInput; /* true to use Pin 8 for FM Radio */
};
static int PowerScan(struct tda_state *state,
u8 RFBand, u32 RF_in,
u32 *pRF_Out, bool *pbcal);
static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
{
struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
.buf = data, .len = len} };
return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
}
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr);
return -1;
}
return 0;
}
static int WriteRegs(struct tda_state *state,
u8 SubAddr, u8 *Regs, u16 nRegs)
{
u8 data[MAX_XFER_SIZE];
if (1 + nRegs > sizeof(data)) {
printk(KERN_WARNING
"%s: i2c wr: len=%d is too big!\n",
KBUILD_MODNAME, nRegs);
return -EINVAL;
}
data[0] = SubAddr;
memcpy(data + 1, Regs, nRegs);
return i2c_write(state->i2c, state->adr, data, nRegs + 1);
}
static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg)
{
u8 msg[2] = {SubAddr, Reg};
return i2c_write(state->i2c, state->adr, msg, 2);
}
static int Read(struct tda_state *state, u8 * Regs)
{
return i2c_readn(state->i2c, state->adr, Regs, 16);
}
static int ReadExtented(struct tda_state *state, u8 * Regs)
{
return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
}
static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo)
{
return WriteRegs(state, RegFrom,
&state->m_Regs[RegFrom], RegTo-RegFrom+1);
}
static int UpdateReg(struct tda_state *state, u8 Reg)
{
return WriteReg(state, Reg, state->m_Regs[Reg]);
}
#include "tda18271c2dd_maps.h"
static void reset(struct tda_state *state)
{
u32 ulIFLevelAnalog = 0;
u32 ulIFLevelDigital = 2;
u32 ulIFLevelDVBC = 7;
u32 ulIFLevelDVBT = 6;
u32 ulXTOut = 0;
u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */
u32 ulSlave = 0;
u32 ulFMInput = 0;
u32 ulSettlingTime = 100;
state->m_Frequency = 0;
state->m_SettlingTime = 100;
state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
state->m_EP4 = 0x20;
if (ulXTOut != 0)
state->m_EP4 |= 0x40;
state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
state->m_bMaster = (ulSlave == 0);
state->m_SettlingTime = ulSettlingTime;
state->m_bFMInput = (ulFMInput == 2);
}
static bool SearchMap1(const struct SMap map[], u32 frequency, u8 *param)
{
int i = 0;
while ((map[i].m_Frequency != 0) && (frequency > map[i].m_Frequency))
i += 1;
if (map[i].m_Frequency == 0)
return false;
*param = map[i].m_Param;
return true;
}
static bool SearchMap2(const struct SMapI map[], u32 frequency, s32 *param)
{
int i = 0;
while ((map[i].m_Frequency != 0) &&
(frequency > map[i].m_Frequency))
i += 1;
if (map[i].m_Frequency == 0)
return false;
*param = map[i].m_Param;
return true;
}
static bool SearchMap3(const struct SMap2 map[], u32 frequency, u8 *param1,
u8 *param2)
{
int i = 0;
while ((map[i].m_Frequency != 0) &&
(frequency > map[i].m_Frequency))
i += 1;
if (map[i].m_Frequency == 0)
return false;
*param1 = map[i].m_Param1;
*param2 = map[i].m_Param2;
return true;
}
static bool SearchMap4(const struct SRFBandMap map[], u32 frequency, u8 *rfband)
{
int i = 0;
while (i < 7 && (frequency > map[i].m_RF_max))
i += 1;
if (i == 7)
return false;
*rfband = i;
return true;
}
static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
{
int status = 0;
do {
u8 Regs[16];
state->m_Regs[TM] |= 0x10;
status = UpdateReg(state, TM);
if (status < 0)
break;
status = Read(state, Regs);
if (status < 0)
break;
if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) ||
((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) {
state->m_Regs[TM] ^= 0x20;
status = UpdateReg(state, TM);
if (status < 0)
break;
msleep(10);
status = Read(state, Regs);
if (status < 0)
break;
}
*pTM_Value = (Regs[TM] & 0x20)
? m_Thermometer_Map_2[Regs[TM] & 0x0F]
: m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
state->m_Regs[TM] &= ~0x10; /* Thermometer off */
status = UpdateReg(state, TM);
if (status < 0)
break;
state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
status = UpdateReg(state, EP4);
if (status < 0)
break;
} while (0);
return status;
}
static int StandBy(struct tda_state *state)
{
int status = 0;
do {
state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */
status = UpdateReg(state, EB12);
if (status < 0)
break;
state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */
status = UpdateReg(state, EB18);
if (status < 0)
break;
state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */
state->m_Regs[EP3] = state->m_EP3_Standby;
status = UpdateReg(state, EP3);
if (status < 0)
break;
state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */
status = UpdateRegs(state, EB21, EB23);
if (status < 0)
break;
} while (0);
return status;
}
static int CalcMainPLL(struct tda_state *state, u32 freq)
{
u8 PostDiv;
u8 Div;
u64 OscFreq;
u32 MainDiv;
if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div))
return -EINVAL;
OscFreq = (u64) freq * (u64) Div;
OscFreq *= (u64) 16384;
do_div(OscFreq, (u64)16000000);
MainDiv = OscFreq;
state->m_Regs[MPD] = PostDiv & 0x77;
state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
state->m_Regs[MD3] = (MainDiv & 0xFF);
return UpdateRegs(state, MPD, MD3);
}
static int CalcCalPLL(struct tda_state *state, u32 freq)
{
u8 PostDiv;
u8 Div;
u64 OscFreq;
u32 CalDiv;
if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div))
return -EINVAL;
OscFreq = (u64)freq * (u64)Div;
/* CalDiv = u32( OscFreq * 16384 / 16000000 ); */
OscFreq *= (u64)16384;
do_div(OscFreq, (u64)16000000);
CalDiv = OscFreq;
state->m_Regs[CPD] = PostDiv;
state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
state->m_Regs[CD3] = (CalDiv & 0xFF);
return UpdateRegs(state, CPD, CD3);
}
static int CalibrateRF(struct tda_state *state,
u8 RFBand, u32 freq, s32 *pCprog)
{
int status = 0;
u8 Regs[NUM_REGS];
do {
u8 BP_Filter = 0;
u8 GainTaper = 0;
u8 RFC_K = 0;
u8 RFC_M = 0;
state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
status = UpdateReg(state, EP4);
if (status < 0)
break;
state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */
status = UpdateReg(state, EB18);
if (status < 0)
break;
/* Switching off LT (as datasheet says) causes calibration on C1 to fail */
/* (Readout of Cprog is always 255) */
if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */
state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */
if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) &&
SearchMap1(m_GainTaper_Map, freq, &GainTaper) &&
SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M)))
return -EINVAL;
state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
status = UpdateRegs(state, EP1, EP3);
if (status < 0)
break;
status = UpdateReg(state, EB13);
if (status < 0)
break;
state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */
status = UpdateReg(state, EB4);
if (status < 0)
break;
state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */
status = UpdateReg(state, EB7);
if (status < 0)
break;
state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */
status = UpdateReg(state, EB14);
if (status < 0)
break;
state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */
status = UpdateReg(state, EB20);
if (status < 0)
break;
state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
status = UpdateRegs(state, EP4, EP5);
if (status < 0)
break;
status = CalcCalPLL(state, freq);
if (status < 0)
break;
status = CalcMainPLL(state, freq + 1000000);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP2);
if (status < 0)
break;
status = UpdateReg(state, EP1);
if (status < 0)
break;
status = UpdateReg(state, EP2);
if (status < 0)
break;
status = UpdateReg(state, EP1);
if (status < 0)
break;
state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */
status = UpdateReg(state, EB4);
if (status < 0)
break;
state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */
status = UpdateReg(state, EB7);
if (status < 0)
break;
msleep(10);
state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */
status = UpdateReg(state, EB20);
if (status < 0)
break;
msleep(60);
state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */
state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */
status = UpdateReg(state, EB18);
if (status < 0)
break;
status = UpdateRegs(state, EP3, EP4);
if (status < 0)
break;
status = UpdateReg(state, EP1);
if (status < 0)
break;
status = ReadExtented(state, Regs);
if (status < 0)
break;
*pCprog = Regs[EB14];
} while (0);
return status;
}
static int RFTrackingFiltersInit(struct tda_state *state,
u8 RFBand)
{
int status = 0;
u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
bool bcal = false;
s32 Cprog_cal1 = 0;
s32 Cprog_table1 = 0;
s32 Cprog_cal2 = 0;
s32 Cprog_table2 = 0;
s32 Cprog_cal3 = 0;
s32 Cprog_table3 = 0;
state->m_RF_A1[RFBand] = 0;
state->m_RF_B1[RFBand] = 0;
state->m_RF_A2[RFBand] = 0;
state->m_RF_B2[RFBand] = 0;
do {
status = PowerScan(state, RFBand, RF1, &RF1, &bcal);
if (status < 0)
break;
if (bcal) {
status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1);
if (status < 0)
break;
}
SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1);
if (!bcal)
Cprog_cal1 = Cprog_table1;
state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
/* state->m_RF_A1[RF_Band] = ???? */
if (RF2 == 0)
break;
status = PowerScan(state, RFBand, RF2, &RF2, &bcal);
if (status < 0)
break;
if (bcal) {
status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2);
if (status < 0)
break;
}
SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2);
if (!bcal)
Cprog_cal2 = Cprog_table2;
state->m_RF_A1[RFBand] =
(Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
((s32)(RF2) - (s32)(RF1));
if (RF3 == 0)
break;
status = PowerScan(state, RFBand, RF3, &RF3, &bcal);
if (status < 0)
break;
if (bcal) {
status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3);
if (status < 0)
break;
}
SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3);
if (!bcal)
Cprog_cal3 = Cprog_table3;
state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2));
state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
} while (0);
state->m_RF1[RFBand] = RF1;
state->m_RF2[RFBand] = RF2;
state->m_RF3[RFBand] = RF3;
#if 0
printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__,
RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2,
state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3);
#endif
return status;
}
static int PowerScan(struct tda_state *state,
u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal)
{
int status = 0;
do {
u8 Gain_Taper = 0;
s32 RFC_Cprog = 0;
u8 CID_Target = 0;
u8 CountLimit = 0;
u32 freq_MainPLL;
u8 Regs[NUM_REGS];
u8 CID_Gain;
s32 Count = 0;
int sign = 1;
bool wait = false;
if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) &&
SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) &&
SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) {
printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__);
return -EINVAL;
}
state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
state->m_Regs[EB14] = (RFC_Cprog);
status = UpdateReg(state, EP2);
if (status < 0)
break;
status = UpdateReg(state, EB14);
if (status < 0)
break;
freq_MainPLL = RF_in + 1000000;
status = CalcMainPLL(state, freq_MainPLL);
if (status < 0)
break;
msleep(5);
state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
status = UpdateReg(state, EP4);
if (status < 0)
break;
status = UpdateReg(state, EP2); /* Launch power measurement */
if (status < 0)
break;
status = ReadExtented(state, Regs);
if (status < 0)
break;
CID_Gain = Regs[EB10] & 0x3F;
state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workaround in CalibrateRF) */
*pRF_Out = RF_in;
while (CID_Gain < CID_Target) {
freq_MainPLL = RF_in + sign * Count + 1000000;
status = CalcMainPLL(state, freq_MainPLL);
if (status < 0)
break;
msleep(wait ? 5 : 1);
wait = false;
status = UpdateReg(state, EP2); /* Launch power measurement */
if (status < 0)
break;
status = ReadExtented(state, Regs);
if (status < 0)
break;
CID_Gain = Regs[EB10] & 0x3F;
Count += 200000;
if (Count < CountLimit * 100000)
continue;
if (sign < 0)
break;
sign = -sign;
Count = 200000;
wait = true;
}
if (status < 0)
break;
if (CID_Gain >= CID_Target) {
*pbcal = true;
*pRF_Out = freq_MainPLL - 1000000;
} else
*pbcal = false;
} while (0);
return status;
}
static int PowerScanInit(struct tda_state *state)
{
int status = 0;
do {
state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
status = UpdateRegs(state, EP3, EP4);
if (status < 0)
break;
state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */
status = UpdateReg(state, EB18);
if (status < 0)
break;
state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */
state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
status = UpdateRegs(state, EB21, EB23);
if (status < 0)
break;
} while (0);
return status;
}
static int CalcRFFilterCurve(struct tda_state *state)
{
int status = 0;
do {
msleep(200); /* Temperature stabilisation */
status = PowerScanInit(state);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 0);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 1);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 2);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 3);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 4);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 5);
if (status < 0)
break;
status = RFTrackingFiltersInit(state, 6);
if (status < 0)
break;
status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */
if (status < 0)
break;
} while (0);
return status;
}
static int FixedContentsI2CUpdate(struct tda_state *state)
{
static u8 InitRegs[] = {
0x08, 0x80, 0xC6,
0xDF, 0x16, 0x60, 0x80,
0x80, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0xFC, 0x01, 0x84, 0x41,
0x01, 0x84, 0x40, 0x07,
0x00, 0x00, 0x96, 0x3F,
0xC1, 0x00, 0x8F, 0x00,
0x00, 0x8C, 0x00, 0x20,
0xB3, 0x48, 0xB0,
};
int status = 0;
memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1);
do {
status = UpdateRegs(state, TM, EB23);
if (status < 0)
break;
/* AGC1 gain setup */
state->m_Regs[EB17] = 0x00;
status = UpdateReg(state, EB17);
if (status < 0)
break;
state->m_Regs[EB17] = 0x03;
status = UpdateReg(state, EB17);
if (status < 0)
break;
state->m_Regs[EB17] = 0x43;
status = UpdateReg(state, EB17);
if (status < 0)
break;
state->m_Regs[EB17] = 0x4C;
status = UpdateReg(state, EB17);
if (status < 0)
break;
/* IRC Cal Low band */
state->m_Regs[EP3] = 0x1F;
state->m_Regs[EP4] = 0x66;
state->m_Regs[EP5] = 0x81;
state->m_Regs[CPD] = 0xCC;
state->m_Regs[CD1] = 0x6C;
state->m_Regs[CD2] = 0x00;
state->m_Regs[CD3] = 0x00;
state->m_Regs[MPD] = 0xC5;
state->m_Regs[MD1] = 0x77;
state->m_Regs[MD2] = 0x08;
state->m_Regs[MD3] = 0x00;
status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */
if (status < 0)
break;
#if 0
state->m_Regs[EB4] = 0x61; /* missing in sw */
status = UpdateReg(state, EB4);
if (status < 0)
break;
msleep(1);
state->m_Regs[EB4] = 0x41;
status = UpdateReg(state, EB4);
if (status < 0)
break;
#endif
msleep(5);
status = UpdateReg(state, EP1);
if (status < 0)
break;
msleep(5);
state->m_Regs[EP5] = 0x85;
state->m_Regs[CPD] = 0xCB;
state->m_Regs[CD1] = 0x66;
state->m_Regs[CD2] = 0x70;
status = UpdateRegs(state, EP3, CD3);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP2);
if (status < 0)
break;
msleep(30);
/* IRC Cal mid band */
state->m_Regs[EP5] = 0x82;
state->m_Regs[CPD] = 0xA8;
state->m_Regs[CD2] = 0x00;
state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */
state->m_Regs[MD1] = 0x73;
state->m_Regs[MD2] = 0x1A;
status = UpdateRegs(state, EP3, MD3);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP1);
if (status < 0)
break;
msleep(5);
state->m_Regs[EP5] = 0x86;
state->m_Regs[CPD] = 0xA8;
state->m_Regs[CD1] = 0x66;
state->m_Regs[CD2] = 0xA0;
status = UpdateRegs(state, EP3, CD3);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP2);
if (status < 0)
break;
msleep(30);
/* IRC Cal high band */
state->m_Regs[EP5] = 0x83;
state->m_Regs[CPD] = 0x98;
state->m_Regs[CD1] = 0x65;
state->m_Regs[CD2] = 0x00;
state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */
state->m_Regs[MD1] = 0x71;
state->m_Regs[MD2] = 0xCD;
status = UpdateRegs(state, EP3, MD3);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP1);
if (status < 0)
break;
msleep(5);
state->m_Regs[EP5] = 0x87;
state->m_Regs[CD1] = 0x65;
state->m_Regs[CD2] = 0x50;
status = UpdateRegs(state, EP3, CD3);
if (status < 0)
break;
msleep(5);
status = UpdateReg(state, EP2);
if (status < 0)
break;
msleep(30);
/* Back to normal */
state->m_Regs[EP4] = 0x64;
status = UpdateReg(state, EP4);
if (status < 0)
break;
status = UpdateReg(state, EP1);
if (status < 0)
break;
} while (0);
return status;
}
static int InitCal(struct tda_state *state)
{
int status = 0;
do {
status = FixedContentsI2CUpdate(state);
if (status < 0)
break;
status = CalcRFFilterCurve(state);
if (status < 0)
break;
status = StandBy(state);
if (status < 0)
break;
/* m_bInitDone = true; */
} while (0);
return status;
};
static int RFTrackingFiltersCorrection(struct tda_state *state,
u32 Frequency)
{
int status = 0;
s32 Cprog_table;
u8 RFBand;
u8 dCoverdT;
if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) ||
!SearchMap4(m_RF_Band_Map, Frequency, &RFBand) ||
!SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT))
return -EINVAL;
do {
u8 TMValue_Current;
u32 RF1 = state->m_RF1[RFBand];
u32 RF2 = state->m_RF1[RFBand];
u32 RF3 = state->m_RF1[RFBand];
s32 RF_A1 = state->m_RF_A1[RFBand];
s32 RF_B1 = state->m_RF_B1[RFBand];
s32 RF_A2 = state->m_RF_A2[RFBand];
s32 RF_B2 = state->m_RF_B2[RFBand];
s32 Capprox = 0;
int TComp;
state->m_Regs[EP3] &= ~0xE0; /* Power up */
status = UpdateReg(state, EP3);
if (status < 0)
break;
status = ThermometerRead(state, &TMValue_Current);
if (status < 0)
break;
if (RF3 == 0 || Frequency < RF2)
Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
else
Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
Capprox += TComp;
if (Capprox < 0)
Capprox = 0;
else if (Capprox > 255)
Capprox = 255;
/* TODO Temperature compensation. There is defenitely a scale factor */
/* missing in the datasheet, so leave it out for now. */
state->m_Regs[EB14] = Capprox;
status = UpdateReg(state, EB14);
if (status < 0)
break;
} while (0);
return status;
}
static int ChannelConfiguration(struct tda_state *state,
u32 Frequency, int Standard)
{
s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
int status = 0;
u8 BP_Filter = 0;
u8 RF_Band = 0;
u8 GainTaper = 0;
u8 IR_Meas = 0;
state->IF = IntermediateFrequency;
/* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
/* get values from tables */
if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) &&
SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) &&
SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) {
printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__);
return -EINVAL;
}
do {
state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */
/* m_EP4 default for XToutOn, CAL_Mode (0) */
state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);
/* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */
if (Standard <= HF_AnalogMax)
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
else if (Standard <= HF_ATSC)
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
else if (Standard <= HF_DVBC)
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
else
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
if ((Standard == HF_FM_Radio) && state->m_bFMInput)
state->m_Regs[EP4] |= 0x80;
state->m_Regs[MPD] &= ~0x80;
if (Standard > HF_AnalogMax)
state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */
state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
/* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */
if (Standard == HF_FM_Radio)
state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
else
state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */
status = UpdateRegs(state, EB22, EB23);
if (status < 0)
break;
state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */
state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
(state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */
/* AGC1_always_master = 0 */
/* AGC_firstn = 0 */
status = UpdateReg(state, EB1);
if (status < 0)
break;
if (state->m_bMaster) {
status = CalcMainPLL(state, Frequency + IntermediateFrequency);
if (status < 0)
break;
status = UpdateRegs(state, TM, EP5);
if (status < 0)
break;
state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */
status = UpdateReg(state, EB4);
if (status < 0)
break;
msleep(1);
state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
status = UpdateReg(state, EB4);
if (status < 0)
break;
} else {
u8 PostDiv = 0;
u8 Div;
status = CalcCalPLL(state, Frequency + IntermediateFrequency);
if (status < 0)
break;
SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div);
state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
status = UpdateReg(state, MPD);
if (status < 0)
break;
status = UpdateRegs(state, TM, EP5);
if (status < 0)
break;
state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */
status = UpdateReg(state, EB7);
if (status < 0)
break;
msleep(1);
state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */
status = UpdateReg(state, EB7);
if (status < 0)
break;
}
msleep(20);
if (Standard != HF_FM_Radio)
state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */
status = UpdateReg(state, EP3);
if (status < 0)
break;
} while (0);
return status;
}
static int sleep(struct dvb_frontend *fe)
{
struct tda_state *state = fe->tuner_priv;
StandBy(state);
return 0;
}
static int init(struct dvb_frontend *fe)
{
return 0;
}
static void release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int set_params(struct dvb_frontend *fe)
{
struct tda_state *state = fe->tuner_priv;
int status = 0;
int Standard;
u32 bw = fe->dtv_property_cache.bandwidth_hz;
u32 delsys = fe->dtv_property_cache.delivery_system;
state->m_Frequency = fe->dtv_property_cache.frequency;
switch (delsys) {
case SYS_DVBT:
case SYS_DVBT2:
switch (bw) {
case 6000000:
Standard = HF_DVBT_6MHZ;
break;
case 7000000:
Standard = HF_DVBT_7MHZ;
break;
case 8000000:
Standard = HF_DVBT_8MHZ;
break;
default:
return -EINVAL;
}
break;
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
if (bw <= 6000000)
Standard = HF_DVBC_6MHZ;
else if (bw <= 7000000)
Standard = HF_DVBC_7MHZ;
else
Standard = HF_DVBC_8MHZ;
break;
default:
return -EINVAL;
}
do {
status = RFTrackingFiltersCorrection(state, state->m_Frequency);
if (status < 0)
break;
status = ChannelConfiguration(state, state->m_Frequency,
Standard);
if (status < 0)
break;
msleep(state->m_SettlingTime); /* Allow AGC's to settle down */
} while (0);
return status;
}
#if 0
static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc)
{
if (IFAgc < 500) {
/* Scale this from 0 to 50000 */
*pSignalStrength = IFAgc * 100;
} else {
/* Scale range 500-1500 to 50000-80000 */
*pSignalStrength = 50000 + (IFAgc - 500) * 30;
}
return 0;
}
#endif
static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda_state *state = fe->tuner_priv;
*frequency = state->IF;
return 0;
}
static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
/* struct tda_state *state = fe->tuner_priv; */
/* *bandwidth = priv->bandwidth; */
return 0;
}
static const struct dvb_tuner_ops tuner_ops = {
.info = {
.name = "NXP TDA18271C2D",
.frequency_min_hz = 47125 * kHz,
.frequency_max_hz = 865 * MHz,
.frequency_step_hz = 62500
},
.init = init,
.sleep = sleep,
.set_params = set_params,
.release = release,
.get_if_frequency = get_if_frequency,
.get_bandwidth = get_bandwidth,
};
struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr)
{
struct tda_state *state;
state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
if (!state)
return NULL;
fe->tuner_priv = state;
state->adr = adr;
state->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
reset(state);
InitCal(state);
return fe;
}
EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
MODULE_DESCRIPTION("TDA18271C2 driver");
MODULE_AUTHOR("DD");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tda18271c2dd.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* helene.c
*
* Sony HELENE DVB-S/S2 DVB-T/T2 DVB-C/C2 ISDB-T/S tuner driver (CXD2858ER)
*
* Copyright 2012 Sony Corporation
* Copyright (C) 2014 NetUP Inc.
* Copyright (C) 2014 Abylay Ospan <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/types.h>
#include "helene.h"
#include <media/dvb_frontend.h>
#define MAX_WRITE_REGSIZE 20
enum helene_state {
STATE_UNKNOWN,
STATE_SLEEP,
STATE_ACTIVE
};
struct helene_priv {
u32 frequency;
u8 i2c_address;
struct i2c_adapter *i2c;
enum helene_state state;
void *set_tuner_data;
int (*set_tuner)(void *, int);
enum helene_xtal xtal;
};
#define TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system) \
(((tv_system) != SONY_HELENE_DTV_DVBC_6) && \
((tv_system) != SONY_HELENE_DTV_DVBC_8)\
&& ((tv_system) != SONY_HELENE_DTV_DVBC2_6) && \
((tv_system) != SONY_HELENE_DTV_DVBC2_8))
#define HELENE_AUTO 0xff
#define HELENE_OFFSET(ofs) ((u8)(ofs) & 0x1F)
#define HELENE_BW_6 0x00
#define HELENE_BW_7 0x01
#define HELENE_BW_8 0x02
#define HELENE_BW_1_7 0x03
enum helene_tv_system_t {
SONY_HELENE_TV_SYSTEM_UNKNOWN,
/* Terrestrial Analog */
SONY_HELENE_ATV_MN_EIAJ,
/**< System-M (Japan) (IF: Fp=5.75MHz in default) */
SONY_HELENE_ATV_MN_SAP,
/**< System-M (US) (IF: Fp=5.75MHz in default) */
SONY_HELENE_ATV_MN_A2,
/**< System-M (Korea) (IF: Fp=5.9MHz in default) */
SONY_HELENE_ATV_BG,
/**< System-B/G (IF: Fp=7.3MHz in default) */
SONY_HELENE_ATV_I,
/**< System-I (IF: Fp=7.85MHz in default) */
SONY_HELENE_ATV_DK,
/**< System-D/K (IF: Fp=7.85MHz in default) */
SONY_HELENE_ATV_L,
/**< System-L (IF: Fp=7.85MHz in default) */
SONY_HELENE_ATV_L_DASH,
/**< System-L DASH (IF: Fp=2.2MHz in default) */
/* Terrestrial/Cable Digital */
SONY_HELENE_DTV_8VSB,
/**< ATSC 8VSB (IF: Fc=3.7MHz in default) */
SONY_HELENE_DTV_QAM,
/**< US QAM (IF: Fc=3.7MHz in default) */
SONY_HELENE_DTV_ISDBT_6,
/**< ISDB-T 6MHzBW (IF: Fc=3.55MHz in default) */
SONY_HELENE_DTV_ISDBT_7,
/**< ISDB-T 7MHzBW (IF: Fc=4.15MHz in default) */
SONY_HELENE_DTV_ISDBT_8,
/**< ISDB-T 8MHzBW (IF: Fc=4.75MHz in default) */
SONY_HELENE_DTV_DVBT_5,
/**< DVB-T 5MHzBW (IF: Fc=3.6MHz in default) */
SONY_HELENE_DTV_DVBT_6,
/**< DVB-T 6MHzBW (IF: Fc=3.6MHz in default) */
SONY_HELENE_DTV_DVBT_7,
/**< DVB-T 7MHzBW (IF: Fc=4.2MHz in default) */
SONY_HELENE_DTV_DVBT_8,
/**< DVB-T 8MHzBW (IF: Fc=4.8MHz in default) */
SONY_HELENE_DTV_DVBT2_1_7,
/**< DVB-T2 1.7MHzBW (IF: Fc=3.5MHz in default) */
SONY_HELENE_DTV_DVBT2_5,
/**< DVB-T2 5MHzBW (IF: Fc=3.6MHz in default) */
SONY_HELENE_DTV_DVBT2_6,
/**< DVB-T2 6MHzBW (IF: Fc=3.6MHz in default) */
SONY_HELENE_DTV_DVBT2_7,
/**< DVB-T2 7MHzBW (IF: Fc=4.2MHz in default) */
SONY_HELENE_DTV_DVBT2_8,
/**< DVB-T2 8MHzBW (IF: Fc=4.8MHz in default) */
SONY_HELENE_DTV_DVBC_6,
/**< DVB-C 6MHzBW (IF: Fc=3.7MHz in default) */
SONY_HELENE_DTV_DVBC_8,
/**< DVB-C 8MHzBW (IF: Fc=4.9MHz in default) */
SONY_HELENE_DTV_DVBC2_6,
/**< DVB-C2 6MHzBW (IF: Fc=3.7MHz in default) */
SONY_HELENE_DTV_DVBC2_8,
/**< DVB-C2 8MHzBW (IF: Fc=4.9MHz in default) */
SONY_HELENE_DTV_DTMB,
/**< DTMB (IF: Fc=5.1MHz in default) */
/* Satellite */
SONY_HELENE_STV_ISDBS,
/**< ISDB-S */
SONY_HELENE_STV_DVBS,
/**< DVB-S */
SONY_HELENE_STV_DVBS2,
/**< DVB-S2 */
SONY_HELENE_ATV_MIN = SONY_HELENE_ATV_MN_EIAJ,
/**< Minimum analog terrestrial system */
SONY_HELENE_ATV_MAX = SONY_HELENE_ATV_L_DASH,
/**< Maximum analog terrestrial system */
SONY_HELENE_DTV_MIN = SONY_HELENE_DTV_8VSB,
/**< Minimum digital terrestrial system */
SONY_HELENE_DTV_MAX = SONY_HELENE_DTV_DTMB,
/**< Maximum digital terrestrial system */
SONY_HELENE_TERR_TV_SYSTEM_NUM,
/**< Number of supported terrestrial broadcasting system */
SONY_HELENE_STV_MIN = SONY_HELENE_STV_ISDBS,
/**< Minimum satellite system */
SONY_HELENE_STV_MAX = SONY_HELENE_STV_DVBS2
/**< Maximum satellite system */
};
struct helene_terr_adjust_param_t {
/* < Addr:0x69 Bit[6:4] : RFVGA gain.
* 0xFF means Auto. (RF_GAIN_SEL = 1)
*/
uint8_t RF_GAIN;
/* < Addr:0x69 Bit[3:0] : IF_BPF gain.
*/
uint8_t IF_BPF_GC;
/* < Addr:0x6B Bit[3:0] : RF overload
* RF input detect level. (FRF <= 172MHz)
*/
uint8_t RFOVLD_DET_LV1_VL;
/* < Addr:0x6B Bit[3:0] : RF overload
* RF input detect level. (172MHz < FRF <= 464MHz)
*/
uint8_t RFOVLD_DET_LV1_VH;
/* < Addr:0x6B Bit[3:0] : RF overload
* RF input detect level. (FRF > 464MHz)
*/
uint8_t RFOVLD_DET_LV1_U;
/* < Addr:0x6C Bit[2:0] :
* Internal RFAGC detect level. (FRF <= 172MHz)
*/
uint8_t IFOVLD_DET_LV_VL;
/* < Addr:0x6C Bit[2:0] :
* Internal RFAGC detect level. (172MHz < FRF <= 464MHz)
*/
uint8_t IFOVLD_DET_LV_VH;
/* < Addr:0x6C Bit[2:0] :
* Internal RFAGC detect level. (FRF > 464MHz)
*/
uint8_t IFOVLD_DET_LV_U;
/* < Addr:0x6D Bit[5:4] :
* IF filter center offset.
*/
uint8_t IF_BPF_F0;
/* < Addr:0x6D Bit[1:0] :
* 6MHzBW(0x00) or 7MHzBW(0x01)
* or 8MHzBW(0x02) or 1.7MHzBW(0x03)
*/
uint8_t BW;
/* < Addr:0x6E Bit[4:0] :
* 5bit signed. IF offset (kHz) = FIF_OFFSET x 50
*/
uint8_t FIF_OFFSET;
/* < Addr:0x6F Bit[4:0] :
* 5bit signed. BW offset (kHz) =
* BW_OFFSET x 50 (BW_OFFSET x 10 in 1.7MHzBW)
*/
uint8_t BW_OFFSET;
/* < Addr:0x9C Bit[0] :
* Local polarity. (0: Upper Local, 1: Lower Local)
*/
uint8_t IS_LOWERLOCAL;
};
static const struct helene_terr_adjust_param_t
terr_params[SONY_HELENE_TERR_TV_SYSTEM_NUM] = {
/*< SONY_HELENE_TV_SYSTEM_UNKNOWN */
{HELENE_AUTO, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
HELENE_BW_6, HELENE_OFFSET(0), HELENE_OFFSET(0), 0x00},
/* Analog */
/**< SONY_HELENE_ATV_MN_EIAJ (System-M (Japan)) */
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_6, HELENE_OFFSET(0), HELENE_OFFSET(1), 0x00},
/**< SONY_HELENE_ATV_MN_SAP (System-M (US)) */
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_6, HELENE_OFFSET(0), HELENE_OFFSET(1), 0x00},
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_6, HELENE_OFFSET(3), HELENE_OFFSET(1), 0x00},
/**< SONY_HELENE_ATV_MN_A2 (System-M (Korea)) */
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_7, HELENE_OFFSET(11), HELENE_OFFSET(5), 0x00},
/**< SONY_HELENE_ATV_BG (System-B/G) */
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_8, HELENE_OFFSET(2), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_ATV_I (System-I) */
{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_8, HELENE_OFFSET(2), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_ATV_DK (System-D/K) */
{HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
HELENE_BW_8, HELENE_OFFSET(2), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_ATV_L (System-L) */
{HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
HELENE_BW_8, HELENE_OFFSET(-1), HELENE_OFFSET(4), 0x00},
/**< SONY_HELENE_ATV_L_DASH (System-L DASH) */
/* Digital */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x03, 0x03, 0x03, 0x00,
HELENE_BW_6, HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_8VSB (ATSC 8VSB) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_QAM (US QAM) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-9), HELENE_OFFSET(-5), 0x00},
/**< SONY_HELENE_DTV_ISDBT_6 (ISDB-T 6MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_7, HELENE_OFFSET(-7), HELENE_OFFSET(-6), 0x00},
/**< SONY_HELENE_DTV_ISDBT_7 (ISDB-T 7MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_8, HELENE_OFFSET(-5), HELENE_OFFSET(-7), 0x00},
/**< SONY_HELENE_DTV_ISDBT_8 (ISDB-T 8MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_DVBT_5 (DVB-T 5MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_DVBT_6 (DVB-T 6MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_7, HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
/**< SONY_HELENE_DTV_DVBT_7 (DVB-T 7MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_8, HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
/**< SONY_HELENE_DTV_DVBT_8 (DVB-T 8MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_1_7, HELENE_OFFSET(-10), HELENE_OFFSET(-10), 0x00},
/**< SONY_HELENE_DTV_DVBT2_1_7 (DVB-T2 1.7MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_DVBT2_5 (DVB-T2 5MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_DVBT2_6 (DVB-T2 6MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_7, HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
/**< SONY_HELENE_DTV_DVBT2_7 (DVB-T2 7MHzBW) */
{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_8, HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
/**< SONY_HELENE_DTV_DVBT2_8 (DVB-T2 8MHzBW) */
{HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_6, HELENE_OFFSET(-6), HELENE_OFFSET(-4), 0x00},
/**< SONY_HELENE_DTV_DVBC_6 (DVB-C 6MHzBW) */
{HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
HELENE_BW_8, HELENE_OFFSET(-2), HELENE_OFFSET(-3), 0x00},
/**< SONY_HELENE_DTV_DVBC_8 (DVB-C 8MHzBW) */
{HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_6, HELENE_OFFSET(-6), HELENE_OFFSET(-2), 0x00},
/**< SONY_HELENE_DTV_DVBC2_6 (DVB-C2 6MHzBW) */
{HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_8, HELENE_OFFSET(-2), HELENE_OFFSET(0), 0x00},
/**< SONY_HELENE_DTV_DVBC2_8 (DVB-C2 8MHzBW) */
{HELENE_AUTO, 0x04, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
HELENE_BW_8, HELENE_OFFSET(2), HELENE_OFFSET(1), 0x00}
/**< SONY_HELENE_DTV_DTMB (DTMB) */
};
static void helene_i2c_debug(struct helene_priv *priv,
u8 reg, u8 write, const u8 *data, u32 len)
{
dev_dbg(&priv->i2c->dev, "helene: I2C %s reg 0x%02x size %d\n",
(write == 0 ? "read" : "write"), reg, len);
print_hex_dump_bytes("helene: I2C data: ",
DUMP_PREFIX_OFFSET, data, len);
}
static int helene_write_regs(struct helene_priv *priv,
u8 reg, const u8 *data, u32 len)
{
int ret;
u8 buf[MAX_WRITE_REGSIZE + 1];
struct i2c_msg msg[1] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = len + 1,
.buf = buf,
}
};
if (len + 1 > sizeof(buf)) {
dev_warn(&priv->i2c->dev,
"wr reg=%04x: len=%d vs %zu is too big!\n",
reg, len + 1, sizeof(buf));
return -E2BIG;
}
helene_i2c_debug(priv, reg, 1, data, len);
buf[0] = reg;
memcpy(&buf[1], data, len);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr failed=%d reg=%02x len=%d\n",
KBUILD_MODNAME, ret, reg, len);
return ret;
}
return 0;
}
static int helene_write_reg(struct helene_priv *priv, u8 reg, u8 val)
{
u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return helene_write_regs(priv, reg, &tmp, 1);
}
static int helene_read_regs(struct helene_priv *priv,
u8 reg, u8 *val, u32 len)
{
int ret;
struct i2c_msg msg[2] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = 1,
.buf = ®,
}, {
.addr = priv->i2c_address,
.flags = I2C_M_RD,
.len = len,
.buf = val,
}
};
ret = i2c_transfer(priv->i2c, &msg[0], 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: I2C rw failed=%d addr=%02x reg=%02x\n",
KBUILD_MODNAME, ret, priv->i2c_address, reg);
return ret;
}
ret = i2c_transfer(priv->i2c, &msg[1], 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c rd failed=%d addr=%02x reg=%02x\n",
KBUILD_MODNAME, ret, priv->i2c_address, reg);
return ret;
}
helene_i2c_debug(priv, reg, 0, val, len);
return 0;
}
static int helene_read_reg(struct helene_priv *priv, u8 reg, u8 *val)
{
return helene_read_regs(priv, reg, val, 1);
}
static int helene_set_reg_bits(struct helene_priv *priv,
u8 reg, u8 data, u8 mask)
{
int res;
u8 rdata;
if (mask != 0xff) {
res = helene_read_reg(priv, reg, &rdata);
if (res != 0)
return res;
data = ((data & mask) | (rdata & (mask ^ 0xFF)));
}
return helene_write_reg(priv, reg, data);
}
static int helene_enter_power_save(struct helene_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_SLEEP)
return 0;
/* Standby setting for CPU */
helene_write_reg(priv, 0x88, 0x0);
/* Standby setting for internal logic block */
helene_write_reg(priv, 0x87, 0xC0);
priv->state = STATE_SLEEP;
return 0;
}
static int helene_leave_power_save(struct helene_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_ACTIVE)
return 0;
/* Standby setting for internal logic block */
helene_write_reg(priv, 0x87, 0xC4);
/* Standby setting for CPU */
helene_write_reg(priv, 0x88, 0x40);
priv->state = STATE_ACTIVE;
return 0;
}
static int helene_init(struct dvb_frontend *fe)
{
struct helene_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
return helene_leave_power_save(priv);
}
static void helene_release(struct dvb_frontend *fe)
{
struct helene_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int helene_sleep(struct dvb_frontend *fe)
{
struct helene_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
helene_enter_power_save(priv);
return 0;
}
static enum helene_tv_system_t helene_get_tv_system(struct dvb_frontend *fe)
{
enum helene_tv_system_t system = SONY_HELENE_TV_SYSTEM_UNKNOWN;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct helene_priv *priv = fe->tuner_priv;
if (p->delivery_system == SYS_DVBT) {
if (p->bandwidth_hz <= 5000000)
system = SONY_HELENE_DTV_DVBT_5;
else if (p->bandwidth_hz <= 6000000)
system = SONY_HELENE_DTV_DVBT_6;
else if (p->bandwidth_hz <= 7000000)
system = SONY_HELENE_DTV_DVBT_7;
else if (p->bandwidth_hz <= 8000000)
system = SONY_HELENE_DTV_DVBT_8;
else {
system = SONY_HELENE_DTV_DVBT_8;
p->bandwidth_hz = 8000000;
}
} else if (p->delivery_system == SYS_DVBT2) {
if (p->bandwidth_hz <= 5000000)
system = SONY_HELENE_DTV_DVBT2_5;
else if (p->bandwidth_hz <= 6000000)
system = SONY_HELENE_DTV_DVBT2_6;
else if (p->bandwidth_hz <= 7000000)
system = SONY_HELENE_DTV_DVBT2_7;
else if (p->bandwidth_hz <= 8000000)
system = SONY_HELENE_DTV_DVBT2_8;
else {
system = SONY_HELENE_DTV_DVBT2_8;
p->bandwidth_hz = 8000000;
}
} else if (p->delivery_system == SYS_DVBS) {
system = SONY_HELENE_STV_DVBS;
} else if (p->delivery_system == SYS_DVBS2) {
system = SONY_HELENE_STV_DVBS2;
} else if (p->delivery_system == SYS_ISDBS) {
system = SONY_HELENE_STV_ISDBS;
} else if (p->delivery_system == SYS_ISDBT) {
if (p->bandwidth_hz <= 6000000)
system = SONY_HELENE_DTV_ISDBT_6;
else if (p->bandwidth_hz <= 7000000)
system = SONY_HELENE_DTV_ISDBT_7;
else if (p->bandwidth_hz <= 8000000)
system = SONY_HELENE_DTV_ISDBT_8;
else {
system = SONY_HELENE_DTV_ISDBT_8;
p->bandwidth_hz = 8000000;
}
} else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
if (p->bandwidth_hz <= 6000000)
system = SONY_HELENE_DTV_DVBC_6;
else if (p->bandwidth_hz <= 8000000)
system = SONY_HELENE_DTV_DVBC_8;
}
dev_dbg(&priv->i2c->dev,
"%s(): HELENE DTV system %d (delsys %d, bandwidth %d)\n",
__func__, (int)system, p->delivery_system,
p->bandwidth_hz);
return system;
}
static int helene_set_params_s(struct dvb_frontend *fe)
{
u8 data[MAX_WRITE_REGSIZE];
u32 frequency;
enum helene_tv_system_t tv_system;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct helene_priv *priv = fe->tuner_priv;
int frequencykHz = p->frequency;
uint32_t frequency4kHz = 0;
u32 symbol_rate = p->symbol_rate/1000;
dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz sr=%uKsps\n",
__func__, frequencykHz, symbol_rate);
tv_system = helene_get_tv_system(fe);
if (tv_system == SONY_HELENE_TV_SYSTEM_UNKNOWN) {
dev_err(&priv->i2c->dev, "%s(): unknown DTV system\n",
__func__);
return -EINVAL;
}
/* RF switch turn to satellite */
if (priv->set_tuner)
priv->set_tuner(priv->set_tuner_data, 0);
frequency = roundup(p->frequency / 1000, 1);
/* Disable IF signal output */
helene_write_reg(priv, 0x15, 0x02);
/* RFIN matching in power save (Sat) reset */
helene_write_reg(priv, 0x43, 0x06);
/* Analog block setting (0x6A, 0x6B) */
data[0] = 0x00;
data[1] = 0x00;
helene_write_regs(priv, 0x6A, data, 2);
helene_write_reg(priv, 0x75, 0x99);
helene_write_reg(priv, 0x9D, 0x00);
/* Tuning setting for CPU (0x61) */
helene_write_reg(priv, 0x61, 0x07);
/* Satellite mode select (0x01) */
helene_write_reg(priv, 0x01, 0x01);
/* Clock enable for internal logic block, CPU wake-up (0x04, 0x05) */
data[0] = 0xC4;
data[1] = 0x40;
switch (priv->xtal) {
case SONY_HELENE_XTAL_16000:
data[2] = 0x02;
break;
case SONY_HELENE_XTAL_20500:
data[2] = 0x02;
break;
case SONY_HELENE_XTAL_24000:
data[2] = 0x03;
break;
case SONY_HELENE_XTAL_41000:
data[2] = 0x05;
break;
default:
dev_err(&priv->i2c->dev, "%s(): unknown xtal %d\n",
__func__, priv->xtal);
return -EINVAL;
}
/* Setting for analog block (0x07). LOOPFILTER INTERNAL */
data[3] = 0x80;
/* Tuning setting for analog block
* (0x08, 0x09, 0x0A, 0x0B). LOOPFILTER INTERNAL
*/
if (priv->xtal == SONY_HELENE_XTAL_20500)
data[4] = 0x58;
else
data[4] = 0x70;
data[5] = 0x1E;
data[6] = 0x02;
data[7] = 0x24;
/* Enable for analog block (0x0C, 0x0D, 0x0E). SAT LNA ON */
data[8] = 0x0F;
data[8] |= 0xE0; /* POWERSAVE_TERR_RF_ACTIVE */
data[9] = 0x02;
data[10] = 0x1E;
/* Setting for LPF cutoff frequency (0x0F) */
switch (tv_system) {
case SONY_HELENE_STV_ISDBS:
data[11] = 0x22; /* 22MHz */
break;
case SONY_HELENE_STV_DVBS:
if (symbol_rate <= 4000)
data[11] = 0x05;
else if (symbol_rate <= 10000)
data[11] = (uint8_t)((symbol_rate * 47
+ (40000-1)) / 40000);
else
data[11] = (uint8_t)((symbol_rate * 27
+ (40000-1)) / 40000 + 5);
if (data[11] > 36)
data[11] = 36; /* 5 <= lpf_cutoff <= 36 is valid */
break;
case SONY_HELENE_STV_DVBS2:
if (symbol_rate <= 4000)
data[11] = 0x05;
else if (symbol_rate <= 10000)
data[11] = (uint8_t)((symbol_rate * 11
+ (10000-1)) / 10000);
else
data[11] = (uint8_t)((symbol_rate * 3
+ (5000-1)) / 5000 + 5);
if (data[11] > 36)
data[11] = 36; /* 5 <= lpf_cutoff <= 36 is valid */
break;
default:
dev_err(&priv->i2c->dev, "%s(): unknown standard %d\n",
__func__, tv_system);
return -EINVAL;
}
/* RF tuning frequency setting (0x10, 0x11, 0x12) */
frequency4kHz = (frequencykHz + 2) / 4;
data[12] = (uint8_t)(frequency4kHz & 0xFF); /* FRF_L */
data[13] = (uint8_t)((frequency4kHz >> 8) & 0xFF); /* FRF_M */
/* FRF_H (bit[3:0]) */
data[14] = (uint8_t)((frequency4kHz >> 16) & 0x0F);
/* Tuning command (0x13) */
data[15] = 0xFF;
/* Setting for IQOUT_LIMIT (0x14) 0.75Vpp */
data[16] = 0x00;
/* Enable IQ output (0x15) */
data[17] = 0x01;
helene_write_regs(priv, 0x04, data, 18);
dev_dbg(&priv->i2c->dev, "%s(): tune done\n",
__func__);
priv->frequency = frequency;
return 0;
}
static int helene_set_params_t(struct dvb_frontend *fe)
{
u8 data[MAX_WRITE_REGSIZE];
u32 frequency;
enum helene_tv_system_t tv_system;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct helene_priv *priv = fe->tuner_priv;
int frequencykHz = p->frequency / 1000;
dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n",
__func__, frequencykHz);
tv_system = helene_get_tv_system(fe);
if (tv_system == SONY_HELENE_TV_SYSTEM_UNKNOWN) {
dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n",
__func__);
return -EINVAL;
}
if (priv->set_tuner)
priv->set_tuner(priv->set_tuner_data, 1);
frequency = roundup(p->frequency / 1000, 25);
/* mode select */
helene_write_reg(priv, 0x01, 0x00);
/* Disable IF signal output */
helene_write_reg(priv, 0x74, 0x02);
if (priv->state == STATE_SLEEP)
helene_leave_power_save(priv);
/* Initial setting for internal analog block (0x91, 0x92) */
if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
(tv_system == SONY_HELENE_DTV_DVBC_8)) {
data[0] = 0x16;
data[1] = 0x26;
} else {
data[0] = 0x10;
data[1] = 0x20;
}
helene_write_regs(priv, 0x91, data, 2);
/* Setting for analog block */
if (TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system))
data[0] = 0x90;
else
data[0] = 0x00;
/* Setting for local polarity (0x9D) */
data[1] = (uint8_t)(terr_params[tv_system].IS_LOWERLOCAL & 0x01);
helene_write_regs(priv, 0x9C, data, 2);
/* Enable for analog block */
data[0] = 0xEE;
data[1] = 0x02;
data[2] = 0x1E;
data[3] = 0x67; /* Tuning setting for CPU */
/* Setting for PLL reference divider for xtal=24MHz */
if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
(tv_system == SONY_HELENE_DTV_DVBC_8))
data[4] = 0x18;
else
data[4] = 0x03;
/* Tuning setting for analog block */
if (TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system)) {
data[5] = 0x38;
data[6] = 0x1E;
data[7] = 0x02;
data[8] = 0x24;
} else if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
(tv_system == SONY_HELENE_DTV_DVBC_8)) {
data[5] = 0x1C;
data[6] = 0x78;
data[7] = 0x08;
data[8] = 0x1C;
} else {
data[5] = 0xB4;
data[6] = 0x78;
data[7] = 0x08;
data[8] = 0x30;
}
helene_write_regs(priv, 0x5E, data, 9);
/* LT_AMP_EN should be 0 */
helene_set_reg_bits(priv, 0x67, 0x0, 0x02);
/* Setting for IFOUT_LIMIT */
data[0] = 0x00; /* 1.5Vpp */
/* RF_GAIN setting */
if (terr_params[tv_system].RF_GAIN == HELENE_AUTO)
data[1] = 0x80; /* RF_GAIN_SEL = 1 */
else
data[1] = (uint8_t)((terr_params[tv_system].RF_GAIN
<< 4) & 0x70);
/* IF_BPF_GC setting */
data[1] |= (uint8_t)(terr_params[tv_system].IF_BPF_GC & 0x0F);
/* Setting for internal RFAGC (0x6A, 0x6B, 0x6C) */
data[2] = 0x00;
if (frequencykHz <= 172000) {
data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VL
& 0x0F);
data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VL
& 0x07);
} else if (frequencykHz <= 464000) {
data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VH
& 0x0F);
data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VH
& 0x07);
} else {
data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_U
& 0x0F);
data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_U
& 0x07);
}
data[4] |= 0x20;
/* Setting for IF frequency and bandwidth */
/* IF filter center frequency offset (IF_BPF_F0) (0x6D) */
data[5] = (uint8_t)((terr_params[tv_system].IF_BPF_F0 << 4) & 0x30);
/* IF filter band width (BW) (0x6D) */
data[5] |= (uint8_t)(terr_params[tv_system].BW & 0x03);
/* IF frequency offset value (FIF_OFFSET) (0x6E) */
data[6] = (uint8_t)(terr_params[tv_system].FIF_OFFSET & 0x1F);
/* IF band width offset value (BW_OFFSET) (0x6F) */
data[7] = (uint8_t)(terr_params[tv_system].BW_OFFSET & 0x1F);
/* RF tuning frequency setting (0x70, 0x71, 0x72) */
data[8] = (uint8_t)(frequencykHz & 0xFF); /* FRF_L */
data[9] = (uint8_t)((frequencykHz >> 8) & 0xFF); /* FRF_M */
data[10] = (uint8_t)((frequencykHz >> 16)
& 0x0F); /* FRF_H (bit[3:0]) */
/* Tuning command */
data[11] = 0xFF;
/* Enable IF output, AGC and IFOUT pin selection (0x74) */
data[12] = 0x01;
if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
(tv_system == SONY_HELENE_DTV_DVBC_8)) {
data[13] = 0xD9;
data[14] = 0x0F;
data[15] = 0x24;
data[16] = 0x87;
} else {
data[13] = 0x99;
data[14] = 0x00;
data[15] = 0x24;
data[16] = 0x87;
}
helene_write_regs(priv, 0x68, data, 17);
dev_dbg(&priv->i2c->dev, "%s(): tune done\n",
__func__);
priv->frequency = frequency;
return 0;
}
static int helene_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->delivery_system == SYS_DVBT ||
p->delivery_system == SYS_DVBT2 ||
p->delivery_system == SYS_ISDBT ||
p->delivery_system == SYS_DVBC_ANNEX_A)
return helene_set_params_t(fe);
return helene_set_params_s(fe);
}
static int helene_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct helene_priv *priv = fe->tuner_priv;
*frequency = priv->frequency * 1000;
return 0;
}
static const struct dvb_tuner_ops helene_tuner_ops_t = {
.info = {
.name = "Sony HELENE Ter tuner",
.frequency_min_hz = 1 * MHz,
.frequency_max_hz = 1200 * MHz,
.frequency_step_hz = 25 * kHz,
},
.init = helene_init,
.release = helene_release,
.sleep = helene_sleep,
.set_params = helene_set_params_t,
.get_frequency = helene_get_frequency,
};
static const struct dvb_tuner_ops helene_tuner_ops_s = {
.info = {
.name = "Sony HELENE Sat tuner",
.frequency_min_hz = 500 * MHz,
.frequency_max_hz = 2500 * MHz,
.frequency_step_hz = 1 * MHz,
},
.init = helene_init,
.release = helene_release,
.sleep = helene_sleep,
.set_params = helene_set_params_s,
.get_frequency = helene_get_frequency,
};
static const struct dvb_tuner_ops helene_tuner_ops = {
.info = {
.name = "Sony HELENE Sat/Ter tuner",
.frequency_min_hz = 1 * MHz,
.frequency_max_hz = 2500 * MHz,
.frequency_step_hz = 25 * kHz,
},
.init = helene_init,
.release = helene_release,
.sleep = helene_sleep,
.set_params = helene_set_params,
.get_frequency = helene_get_frequency,
};
/* power-on tuner
* call once after reset
*/
static int helene_x_pon(struct helene_priv *priv)
{
/* RFIN matching in power save (terrestrial) = ACTIVE */
/* RFIN matching in power save (satellite) = ACTIVE */
u8 dataT[] = { 0x06, 0x00, 0x02, 0x00 };
/* SAT_RF_ACTIVE = true, lnaOff = false, terrRfActive = true */
u8 dataS[] = { 0x05, 0x06 };
u8 cdata[] = {0x7A, 0x01};
u8 data[20];
u8 rdata[2];
/* mode select */
helene_write_reg(priv, 0x01, 0x00);
helene_write_reg(priv, 0x67, dataT[3]);
helene_write_reg(priv, 0x43, dataS[1]);
helene_write_regs(priv, 0x5E, dataT, 3);
helene_write_reg(priv, 0x0C, dataS[0]);
/* Initial setting for internal logic block */
helene_write_regs(priv, 0x99, cdata, sizeof(cdata));
/* 0x81 - 0x94 */
if (priv->xtal == SONY_HELENE_XTAL_16000)
data[0] = 0x10; /* xtal 16 MHz */
else
data[0] = 0x18; /* xtal 24 MHz */
data[1] = (uint8_t)(0x80 | (0x04 & 0x1F)); /* 4 x 25 = 100uA */
data[2] = (uint8_t)(0x80 | (0x26 & 0x7F)); /* 38 x 0.25 = 9.5pF */
data[3] = 0x80; /* REFOUT signal output 500mVpp */
data[4] = 0x00; /* GPIO settings */
data[5] = 0x00; /* GPIO settings */
data[6] = 0xC4; /* Clock enable for internal logic block */
data[7] = 0x40; /* Start CPU boot-up */
data[8] = 0x10; /* For burst-write */
/* Setting for internal RFAGC */
data[9] = 0x00;
data[10] = 0x45;
data[11] = 0x75;
data[12] = 0x07; /* Setting for analog block */
/* Initial setting for internal analog block */
data[13] = 0x1C;
data[14] = 0x3F;
data[15] = 0x02;
data[16] = 0x10;
data[17] = 0x20;
data[18] = 0x0A;
data[19] = 0x00;
helene_write_regs(priv, 0x81, data, sizeof(data));
/* Setting for internal RFAGC */
helene_write_reg(priv, 0x9B, 0x00);
msleep(20);
/* Check CPU_STT/CPU_ERR */
helene_read_regs(priv, 0x1A, rdata, sizeof(rdata));
if (rdata[0] != 0x00) {
dev_err(&priv->i2c->dev,
"HELENE tuner CPU error 0x%x\n", rdata[0]);
return -EIO;
}
/* VCO current setting */
cdata[0] = 0x90;
cdata[1] = 0x06;
helene_write_regs(priv, 0x17, cdata, sizeof(cdata));
msleep(20);
helene_read_reg(priv, 0x19, data);
helene_write_reg(priv, 0x95, (uint8_t)((data[0] >> 4) & 0x0F));
/* Disable IF signal output */
helene_write_reg(priv, 0x74, 0x02);
/* Standby setting for CPU */
helene_write_reg(priv, 0x88, 0x00);
/* Standby setting for internal logic block */
helene_write_reg(priv, 0x87, 0xC0);
/* Load capacitance control setting for crystal oscillator */
helene_write_reg(priv, 0x80, 0x01);
/* Satellite initial setting */
cdata[0] = 0x07;
cdata[1] = 0x00;
helene_write_regs(priv, 0x41, cdata, sizeof(cdata));
dev_info(&priv->i2c->dev,
"HELENE tuner x_pon done\n");
return 0;
}
struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe,
const struct helene_config *config,
struct i2c_adapter *i2c)
{
struct helene_priv *priv = NULL;
priv = kzalloc(sizeof(struct helene_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = (config->i2c_address >> 1);
priv->i2c = i2c;
priv->set_tuner_data = config->set_tuner_priv;
priv->set_tuner = config->set_tuner_callback;
priv->xtal = config->xtal;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (helene_x_pon(priv) != 0) {
kfree(priv);
return NULL;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&fe->ops.tuner_ops, &helene_tuner_ops_s,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
dev_info(&priv->i2c->dev,
"Sony HELENE Sat attached on addr=%x at I2C adapter %p\n",
priv->i2c_address, priv->i2c);
return fe;
}
EXPORT_SYMBOL_GPL(helene_attach_s);
struct dvb_frontend *helene_attach(struct dvb_frontend *fe,
const struct helene_config *config,
struct i2c_adapter *i2c)
{
struct helene_priv *priv = NULL;
priv = kzalloc(sizeof(struct helene_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = (config->i2c_address >> 1);
priv->i2c = i2c;
priv->set_tuner_data = config->set_tuner_priv;
priv->set_tuner = config->set_tuner_callback;
priv->xtal = config->xtal;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (helene_x_pon(priv) != 0) {
kfree(priv);
return NULL;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&fe->ops.tuner_ops, &helene_tuner_ops_t,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
dev_info(&priv->i2c->dev,
"Sony HELENE Ter attached on addr=%x at I2C adapter %p\n",
priv->i2c_address, priv->i2c);
return fe;
}
EXPORT_SYMBOL_GPL(helene_attach);
static int helene_probe(struct i2c_client *client)
{
struct helene_config *config = client->dev.platform_data;
struct dvb_frontend *fe = config->fe;
struct device *dev = &client->dev;
struct helene_priv *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->i2c_address = client->addr;
priv->i2c = client->adapter;
priv->set_tuner_data = config->set_tuner_priv;
priv->set_tuner = config->set_tuner_callback;
priv->xtal = config->xtal;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (helene_x_pon(priv) != 0)
return -EINVAL;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&fe->ops.tuner_ops, &helene_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
i2c_set_clientdata(client, priv);
dev_info(dev, "Sony HELENE attached on addr=%x at I2C adapter %p\n",
priv->i2c_address, priv->i2c);
return 0;
}
static const struct i2c_device_id helene_id[] = {
{ "helene", },
{}
};
MODULE_DEVICE_TABLE(i2c, helene_id);
static struct i2c_driver helene_driver = {
.driver = {
.name = "helene",
},
.probe = helene_probe,
.id_table = helene_id,
};
module_i2c_driver(helene_driver);
MODULE_DESCRIPTION("Sony HELENE Sat/Ter tuner driver");
MODULE_AUTHOR("Abylay Ospan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/helene.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
STB6100 Silicon Tuner
Copyright (C) Manu Abraham ([email protected])
Copyright (C) ST Microelectronics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <media/dvb_frontend.h>
#include "stb6100.h"
static unsigned int verbose;
module_param(verbose, int, 0644);
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
#define FE_ERROR 0
#define FE_NOTICE 1
#define FE_INFO 2
#define FE_DEBUG 3
#define dprintk(x, y, z, format, arg...) do { \
if (z) { \
if ((x > FE_ERROR) && (x > y)) \
printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
else if ((x > FE_NOTICE) && (x > y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
else if ((x > FE_INFO) && (x > y)) \
printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
else if ((x > FE_DEBUG) && (x > y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
} else { \
if (x > y) \
printk(format, ##arg); \
} \
} while (0)
struct stb6100_lkup {
u32 val_low;
u32 val_high;
u8 reg;
};
static void stb6100_release(struct dvb_frontend *fe);
static const struct stb6100_lkup lkup[] = {
{ 0, 950000, 0x0a },
{ 950000, 1000000, 0x0a },
{ 1000000, 1075000, 0x0c },
{ 1075000, 1200000, 0x00 },
{ 1200000, 1300000, 0x01 },
{ 1300000, 1370000, 0x02 },
{ 1370000, 1470000, 0x04 },
{ 1470000, 1530000, 0x05 },
{ 1530000, 1650000, 0x06 },
{ 1650000, 1800000, 0x08 },
{ 1800000, 1950000, 0x0a },
{ 1950000, 2150000, 0x0c },
{ 2150000, 9999999, 0x0c },
{ 0, 0, 0x00 }
};
/* Register names for easy debugging. */
static const char *stb6100_regnames[] = {
[STB6100_LD] = "LD",
[STB6100_VCO] = "VCO",
[STB6100_NI] = "NI",
[STB6100_NF_LSB] = "NF",
[STB6100_K] = "K",
[STB6100_G] = "G",
[STB6100_F] = "F",
[STB6100_DLB] = "DLB",
[STB6100_TEST1] = "TEST1",
[STB6100_FCCK] = "FCCK",
[STB6100_LPEN] = "LPEN",
[STB6100_TEST3] = "TEST3",
};
/* Template for normalisation, i.e. setting unused or undocumented
* bits as required according to the documentation.
*/
struct stb6100_regmask {
u8 mask;
u8 set;
};
static const struct stb6100_regmask stb6100_template[] = {
[STB6100_LD] = { 0xff, 0x00 },
[STB6100_VCO] = { 0xff, 0x00 },
[STB6100_NI] = { 0xff, 0x00 },
[STB6100_NF_LSB] = { 0xff, 0x00 },
[STB6100_K] = { 0xc7, 0x38 },
[STB6100_G] = { 0xef, 0x10 },
[STB6100_F] = { 0x1f, 0xc0 },
[STB6100_DLB] = { 0x38, 0xc4 },
[STB6100_TEST1] = { 0x00, 0x8f },
[STB6100_FCCK] = { 0x40, 0x0d },
[STB6100_LPEN] = { 0xf0, 0x0b },
[STB6100_TEST3] = { 0x00, 0xde },
};
/*
* Currently unused. Some boards might need it in the future
*/
static __always_unused inline void stb6100_normalise_regs(u8 regs[])
{
int i;
for (i = 0; i < STB6100_NUMREGS; i++)
regs[i] = (regs[i] & stb6100_template[i].mask) | stb6100_template[i].set;
}
static int stb6100_read_regs(struct stb6100_state *state, u8 regs[])
{
int rc;
struct i2c_msg msg = {
.addr = state->config->tuner_address,
.flags = I2C_M_RD,
.buf = regs,
.len = STB6100_NUMREGS
};
rc = i2c_transfer(state->i2c, &msg, 1);
if (unlikely(rc != 1)) {
dprintk(verbose, FE_ERROR, 1, "Read (0x%x) err, rc=[%d]",
state->config->tuner_address, rc);
return -EREMOTEIO;
}
if (unlikely(verbose > FE_DEBUG)) {
int i;
dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address);
for (i = 0; i < STB6100_NUMREGS; i++)
dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[i], regs[i]);
}
return 0;
}
static int stb6100_read_reg(struct stb6100_state *state, u8 reg)
{
u8 regs[STB6100_NUMREGS];
struct i2c_msg msg = {
.addr = state->config->tuner_address + reg,
.flags = I2C_M_RD,
.buf = regs,
.len = 1
};
i2c_transfer(state->i2c, &msg, 1);
if (unlikely(reg >= STB6100_NUMREGS)) {
dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg);
return -EINVAL;
}
if (unlikely(verbose > FE_DEBUG)) {
dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address);
dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[reg], regs[0]);
}
return (unsigned int)regs[0];
}
static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int start, int len)
{
int rc;
u8 cmdbuf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = state->config->tuner_address,
.flags = 0,
.buf = cmdbuf,
.len = len + 1
};
if (1 + len > sizeof(cmdbuf)) {
printk(KERN_WARNING
"%s: i2c wr: len=%d is too big!\n",
KBUILD_MODNAME, len);
return -EINVAL;
}
if (unlikely(start < 1 || start + len > STB6100_NUMREGS)) {
dprintk(verbose, FE_ERROR, 1, "Invalid register range %d:%d",
start, len);
return -EINVAL;
}
memcpy(&cmdbuf[1], buf, len);
cmdbuf[0] = start;
if (unlikely(verbose > FE_DEBUG)) {
int i;
dprintk(verbose, FE_DEBUG, 1, " Write @ 0x%02x: [%d:%d]", state->config->tuner_address, start, len);
for (i = 0; i < len; i++)
dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[start + i], buf[i]);
}
rc = i2c_transfer(state->i2c, &msg, 1);
if (unlikely(rc != 1)) {
dprintk(verbose, FE_ERROR, 1, "(0x%x) write err [%d:%d], rc=[%d]",
(unsigned int)state->config->tuner_address, start, len, rc);
return -EREMOTEIO;
}
return 0;
}
static int stb6100_write_reg(struct stb6100_state *state, u8 reg, u8 data)
{
u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
if (unlikely(reg >= STB6100_NUMREGS)) {
dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg);
return -EREMOTEIO;
}
tmp = (tmp & stb6100_template[reg].mask) | stb6100_template[reg].set;
return stb6100_write_reg_range(state, &tmp, reg, 1);
}
static int stb6100_get_status(struct dvb_frontend *fe, u32 *status)
{
int rc;
struct stb6100_state *state = fe->tuner_priv;
rc = stb6100_read_reg(state, STB6100_LD);
if (rc < 0) {
dprintk(verbose, FE_ERROR, 1, "%s failed", __func__);
return rc;
}
return (rc & STB6100_LD_LOCK) ? TUNER_STATUS_LOCKED : 0;
}
static int stb6100_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
int rc;
u8 f;
u32 bw;
struct stb6100_state *state = fe->tuner_priv;
rc = stb6100_read_reg(state, STB6100_F);
if (rc < 0)
return rc;
f = rc & STB6100_F_F;
bw = (f + 5) * 2000; /* x2 for ZIF */
*bandwidth = state->bandwidth = bw * 1000;
dprintk(verbose, FE_DEBUG, 1, "bandwidth = %u Hz", state->bandwidth);
return 0;
}
static int stb6100_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
{
u32 tmp;
int rc;
struct stb6100_state *state = fe->tuner_priv;
dprintk(verbose, FE_DEBUG, 1, "set bandwidth to %u Hz", bandwidth);
bandwidth /= 2; /* ZIF */
if (bandwidth >= 36000000) /* F[4:0] BW/2 max =31+5=36 mhz for F=31 */
tmp = 31;
else if (bandwidth <= 5000000) /* bw/2 min = 5Mhz for F=0 */
tmp = 0;
else /* if 5 < bw/2 < 36 */
tmp = (bandwidth + 500000) / 1000000 - 5;
/* Turn on LPF bandwidth setting clock control,
* set bandwidth, wait 10ms, turn off.
*/
rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d | STB6100_FCCK_FCCK);
if (rc < 0)
return rc;
rc = stb6100_write_reg(state, STB6100_F, 0xc0 | tmp);
if (rc < 0)
return rc;
msleep(5); /* This is dangerous as another (related) thread may start */
rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d);
if (rc < 0)
return rc;
msleep(10); /* This is dangerous as another (related) thread may start */
return 0;
}
static int stb6100_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
int rc;
u32 nint, nfrac, fvco;
int psd2, odiv;
struct stb6100_state *state = fe->tuner_priv;
u8 regs[STB6100_NUMREGS];
rc = stb6100_read_regs(state, regs);
if (rc < 0)
return rc;
odiv = (regs[STB6100_VCO] & STB6100_VCO_ODIV) >> STB6100_VCO_ODIV_SHIFT;
psd2 = (regs[STB6100_K] & STB6100_K_PSD2) >> STB6100_K_PSD2_SHIFT;
nint = regs[STB6100_NI];
nfrac = ((regs[STB6100_K] & STB6100_K_NF_MSB) << 8) | regs[STB6100_NF_LSB];
fvco = (nfrac * state->reference >> (9 - psd2)) + (nint * state->reference << psd2);
*frequency = state->frequency = fvco >> (odiv + 1);
dprintk(verbose, FE_DEBUG, 1,
"frequency = %u kHz, odiv = %u, psd2 = %u, fxtal = %u kHz, fvco = %u kHz, N(I) = %u, N(F) = %u",
state->frequency, odiv, psd2, state->reference, fvco, nint, nfrac);
return 0;
}
static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
{
int rc;
const struct stb6100_lkup *ptr;
struct stb6100_state *state = fe->tuner_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 srate = 0, fvco, nint, nfrac;
u8 regs[STB6100_NUMREGS];
u8 g, psd2, odiv;
dprintk(verbose, FE_DEBUG, 1, "Version 2010-8-14 13:51");
if (fe->ops.get_frontend) {
dprintk(verbose, FE_DEBUG, 1, "Get frontend parameters");
fe->ops.get_frontend(fe, p);
}
srate = p->symbol_rate;
/* Set up tuner cleanly, LPF calibration on */
rc = stb6100_write_reg(state, STB6100_FCCK, 0x4d | STB6100_FCCK_FCCK);
if (rc < 0)
return rc; /* allow LPF calibration */
/* PLL Loop disabled, bias on, VCO on, synth on */
regs[STB6100_LPEN] = 0xeb;
rc = stb6100_write_reg(state, STB6100_LPEN, regs[STB6100_LPEN]);
if (rc < 0)
return rc;
/* Program the registers with their data values */
/* VCO divide ratio (LO divide ratio, VCO prescaler enable). */
if (frequency <= 1075000)
odiv = 1;
else
odiv = 0;
/* VCO enabled, search clock off as per LL3.7, 3.4.1 */
regs[STB6100_VCO] = 0xe0 | (odiv << STB6100_VCO_ODIV_SHIFT);
/* OSM */
for (ptr = lkup;
(ptr->val_high != 0) && !CHKRANGE(frequency, ptr->val_low, ptr->val_high);
ptr++);
if (ptr->val_high == 0) {
printk(KERN_ERR "%s: frequency out of range: %u kHz\n", __func__, frequency);
return -EINVAL;
}
regs[STB6100_VCO] = (regs[STB6100_VCO] & ~STB6100_VCO_OSM) | ptr->reg;
rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]);
if (rc < 0)
return rc;
if ((frequency > 1075000) && (frequency <= 1325000))
psd2 = 0;
else
psd2 = 1;
/* F(VCO) = F(LO) * (ODIV == 0 ? 2 : 4) */
fvco = frequency << (1 + odiv);
/* N(I) = floor(f(VCO) / (f(XTAL) * (PSD2 ? 2 : 1))) */
nint = fvco / (state->reference << psd2);
/* N(F) = round(f(VCO) / f(XTAL) * (PSD2 ? 2 : 1) - N(I)) * 2 ^ 9 */
nfrac = DIV_ROUND_CLOSEST((fvco - (nint * state->reference << psd2))
<< (9 - psd2), state->reference);
/* NI */
regs[STB6100_NI] = nint;
rc = stb6100_write_reg(state, STB6100_NI, regs[STB6100_NI]);
if (rc < 0)
return rc;
/* NF */
regs[STB6100_NF_LSB] = nfrac;
rc = stb6100_write_reg(state, STB6100_NF_LSB, regs[STB6100_NF_LSB]);
if (rc < 0)
return rc;
/* K */
regs[STB6100_K] = (0x38 & ~STB6100_K_PSD2) | (psd2 << STB6100_K_PSD2_SHIFT);
regs[STB6100_K] = (regs[STB6100_K] & ~STB6100_K_NF_MSB) | ((nfrac >> 8) & STB6100_K_NF_MSB);
rc = stb6100_write_reg(state, STB6100_K, regs[STB6100_K]);
if (rc < 0)
return rc;
/* G Baseband gain. */
if (srate >= 15000000)
g = 9; /* +4 dB */
else if (srate >= 5000000)
g = 11; /* +8 dB */
else
g = 14; /* +14 dB */
regs[STB6100_G] = (0x10 & ~STB6100_G_G) | g;
regs[STB6100_G] &= ~STB6100_G_GCT; /* mask GCT */
regs[STB6100_G] |= (1 << 5); /* 2Vp-p Mode */
rc = stb6100_write_reg(state, STB6100_G, regs[STB6100_G]);
if (rc < 0)
return rc;
/* F we don't write as it is set up in BW set */
/* DLB set DC servo loop BW to 160Hz (LLA 3.8 / 2.1) */
regs[STB6100_DLB] = 0xcc;
rc = stb6100_write_reg(state, STB6100_DLB, regs[STB6100_DLB]);
if (rc < 0)
return rc;
dprintk(verbose, FE_DEBUG, 1,
"frequency = %u, srate = %u, g = %u, odiv = %u, psd2 = %u, fxtal = %u, osm = %u, fvco = %u, N(I) = %u, N(F) = %u",
frequency, srate, (unsigned int)g, (unsigned int)odiv,
(unsigned int)psd2, state->reference,
ptr->reg, fvco, nint, nfrac);
/* Set up the test registers */
regs[STB6100_TEST1] = 0x8f;
rc = stb6100_write_reg(state, STB6100_TEST1, regs[STB6100_TEST1]);
if (rc < 0)
return rc;
regs[STB6100_TEST3] = 0xde;
rc = stb6100_write_reg(state, STB6100_TEST3, regs[STB6100_TEST3]);
if (rc < 0)
return rc;
/* Bring up tuner according to LLA 3.7 3.4.1, step 2 */
regs[STB6100_LPEN] = 0xfb; /* PLL Loop enabled, bias on, VCO on, synth on */
rc = stb6100_write_reg(state, STB6100_LPEN, regs[STB6100_LPEN]);
if (rc < 0)
return rc;
msleep(2);
/* Bring up tuner according to LLA 3.7 3.4.1, step 3 */
regs[STB6100_VCO] &= ~STB6100_VCO_OCK; /* VCO fast search */
rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]);
if (rc < 0)
return rc;
msleep(10); /* This is dangerous as another (related) thread may start */ /* wait for LO to lock */
regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */
regs[STB6100_VCO] |= STB6100_VCO_OCK; /* search clock off */
rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]);
if (rc < 0)
return rc;
rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d);
if (rc < 0)
return rc; /* Stop LPF calibration */
msleep(10); /* This is dangerous as another (related) thread may start */
/* wait for stabilisation, (should not be necessary) */
return 0;
}
static int stb6100_sleep(struct dvb_frontend *fe)
{
/* TODO: power down */
return 0;
}
static int stb6100_init(struct dvb_frontend *fe)
{
struct stb6100_state *state = fe->tuner_priv;
int refclk = 27000000; /* Hz */
/*
* iqsense = 1
* tunerstep = 125000
*/
state->bandwidth = 36000000; /* Hz */
state->reference = refclk / 1000; /* kHz */
/* Set default bandwidth. Modified, PN 13-May-10 */
return 0;
}
static int stb6100_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->frequency > 0)
stb6100_set_frequency(fe, c->frequency);
if (c->bandwidth_hz > 0)
stb6100_set_bandwidth(fe, c->bandwidth_hz);
return 0;
}
static const struct dvb_tuner_ops stb6100_ops = {
.info = {
.name = "STB6100 Silicon Tuner",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
},
.init = stb6100_init,
.sleep = stb6100_sleep,
.get_status = stb6100_get_status,
.set_params = stb6100_set_params,
.get_frequency = stb6100_get_frequency,
.get_bandwidth = stb6100_get_bandwidth,
.release = stb6100_release
};
struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
const struct stb6100_config *config,
struct i2c_adapter *i2c)
{
struct stb6100_state *state = NULL;
state = kzalloc(sizeof (struct stb6100_state), GFP_KERNEL);
if (!state)
return NULL;
state->config = config;
state->i2c = i2c;
state->frontend = fe;
state->reference = config->refclock / 1000; /* kHz */
fe->tuner_priv = state;
fe->ops.tuner_ops = stb6100_ops;
printk("%s: Attaching STB6100 \n", __func__);
return fe;
}
static void stb6100_release(struct dvb_frontend *fe)
{
struct stb6100_state *state = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(state);
}
EXPORT_SYMBOL_GPL(stb6100_attach);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("STB6100 Silicon tuner");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stb6100.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Sony CXD2820R demodulator driver
*
* Copyright (C) 2010 Antti Palosaari <[email protected]>
*/
#include "cxd2820r_priv.h"
/* Write register table */
int cxd2820r_wr_reg_val_mask_tab(struct cxd2820r_priv *priv,
const struct reg_val_mask *tab, int tab_len)
{
struct i2c_client *client = priv->client[0];
int ret;
unsigned int i, reg, mask, val;
struct regmap *regmap;
dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
for (i = 0; i < tab_len; i++) {
if ((tab[i].reg >> 16) & 0x1)
regmap = priv->regmap[1];
else
regmap = priv->regmap[0];
reg = (tab[i].reg >> 0) & 0xffff;
val = tab[i].val;
mask = tab[i].mask;
if (mask == 0xff)
ret = regmap_write(regmap, reg, val);
else
ret = regmap_write_bits(regmap, reg, mask, val);
if (ret)
goto error;
}
return 0;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_gpio(struct dvb_frontend *fe, u8 *gpio)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
u8 tmp0, tmp1;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
/* update GPIOs only when needed */
if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio)))
return 0;
tmp0 = 0x00;
tmp1 = 0x00;
for (i = 0; i < sizeof(priv->gpio); i++) {
/* enable / disable */
if (gpio[i] & CXD2820R_GPIO_E)
tmp0 |= (2 << 6) >> (2 * i);
else
tmp0 |= (1 << 6) >> (2 * i);
/* input / output */
if (gpio[i] & CXD2820R_GPIO_I)
tmp1 |= (1 << (3 + i));
else
tmp1 |= (0 << (3 + i));
/* high / low */
if (gpio[i] & CXD2820R_GPIO_H)
tmp1 |= (1 << (0 + i));
else
tmp1 |= (0 << (0 + i));
dev_dbg(&client->dev, "gpio i=%d %02x %02x\n", i, tmp0, tmp1);
}
dev_dbg(&client->dev, "wr gpio=%02x %02x\n", tmp0, tmp1);
/* write bits [7:2] */
ret = regmap_update_bits(priv->regmap[0], 0x0089, 0xfc, tmp0);
if (ret)
goto error;
/* write bits [5:0] */
ret = regmap_update_bits(priv->regmap[0], 0x008e, 0x3f, tmp1);
if (ret)
goto error;
memcpy(priv->gpio, gpio, sizeof(priv->gpio));
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int cxd2820r_set_frontend(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
switch (c->delivery_system) {
case SYS_DVBT:
ret = cxd2820r_init_t(fe);
if (ret < 0)
goto err;
ret = cxd2820r_set_frontend_t(fe);
if (ret < 0)
goto err;
break;
case SYS_DVBT2:
ret = cxd2820r_init_t(fe);
if (ret < 0)
goto err;
ret = cxd2820r_set_frontend_t2(fe);
if (ret < 0)
goto err;
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2820r_init_c(fe);
if (ret < 0)
goto err;
ret = cxd2820r_set_frontend_c(fe);
if (ret < 0)
goto err;
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
break;
}
err:
return ret;
}
static int cxd2820r_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
switch (c->delivery_system) {
case SYS_DVBT:
ret = cxd2820r_read_status_t(fe, status);
break;
case SYS_DVBT2:
ret = cxd2820r_read_status_t2(fe, status);
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2820r_read_status_c(fe, status);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int cxd2820r_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
if (priv->delivery_system == SYS_UNDEFINED)
return 0;
switch (c->delivery_system) {
case SYS_DVBT:
ret = cxd2820r_get_frontend_t(fe, p);
break;
case SYS_DVBT2:
ret = cxd2820r_get_frontend_t2(fe, p);
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2820r_get_frontend_c(fe, p);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
*ber = (priv->post_bit_error - priv->post_bit_error_prev_dvbv3);
priv->post_bit_error_prev_dvbv3 = priv->post_bit_error;
return 0;
}
static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
if (c->strength.stat[0].scale == FE_SCALE_RELATIVE)
*strength = c->strength.stat[0].uvalue;
else
*strength = 0;
return 0;
}
static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
*ucblocks = 0;
return 0;
}
static int cxd2820r_init(struct dvb_frontend *fe)
{
return 0;
}
static int cxd2820r_sleep(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
switch (c->delivery_system) {
case SYS_DVBT:
ret = cxd2820r_sleep_t(fe);
break;
case SYS_DVBT2:
ret = cxd2820r_sleep_t2(fe);
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2820r_sleep_c(fe);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
switch (c->delivery_system) {
case SYS_DVBT:
ret = cxd2820r_get_tune_settings_t(fe, s);
break;
case SYS_DVBT2:
ret = cxd2820r_get_tune_settings_t2(fe, s);
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2820r_get_tune_settings_c(fe, s);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
enum fe_status status = 0;
dev_dbg(&client->dev, "delivery_system=%d\n", c->delivery_system);
/* switch between DVB-T and DVB-T2 when tune fails */
if (priv->last_tune_failed) {
if (priv->delivery_system == SYS_DVBT) {
ret = cxd2820r_sleep_t(fe);
if (ret)
goto error;
c->delivery_system = SYS_DVBT2;
} else if (priv->delivery_system == SYS_DVBT2) {
ret = cxd2820r_sleep_t2(fe);
if (ret)
goto error;
c->delivery_system = SYS_DVBT;
}
}
/* set frontend */
ret = cxd2820r_set_frontend(fe);
if (ret)
goto error;
/* frontend lock wait loop count */
switch (priv->delivery_system) {
case SYS_DVBT:
case SYS_DVBC_ANNEX_A:
i = 20;
break;
case SYS_DVBT2:
i = 40;
break;
case SYS_UNDEFINED:
default:
i = 0;
break;
}
/* wait frontend lock */
for (; i > 0; i--) {
dev_dbg(&client->dev, "loop=%d\n", i);
msleep(50);
ret = cxd2820r_read_status(fe, &status);
if (ret)
goto error;
if (status & FE_HAS_LOCK)
break;
}
/* check if we have a valid signal */
if (status & FE_HAS_LOCK) {
priv->last_tune_failed = false;
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
priv->last_tune_failed = true;
return DVBFE_ALGO_SEARCH_AGAIN;
}
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return DVBFE_ALGO_SEARCH_ERROR;
}
static enum dvbfe_algo cxd2820r_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static void cxd2820r_release(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
dev_dbg(&client->dev, "\n");
i2c_unregister_device(client);
return;
}
static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
dev_dbg_ratelimited(&client->dev, "enable=%d\n", enable);
return regmap_update_bits(priv->regmap[0], 0x00db, 0x01, enable ? 1 : 0);
}
#ifdef CONFIG_GPIOLIB
static int cxd2820r_gpio_direction_output(struct gpio_chip *chip, unsigned nr,
int val)
{
struct cxd2820r_priv *priv = gpiochip_get_data(chip);
struct i2c_client *client = priv->client[0];
u8 gpio[GPIO_COUNT];
dev_dbg(&client->dev, "nr=%u val=%d\n", nr, val);
memcpy(gpio, priv->gpio, sizeof(gpio));
gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2);
return cxd2820r_gpio(&priv->fe, gpio);
}
static void cxd2820r_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
struct cxd2820r_priv *priv = gpiochip_get_data(chip);
struct i2c_client *client = priv->client[0];
u8 gpio[GPIO_COUNT];
dev_dbg(&client->dev, "nr=%u val=%d\n", nr, val);
memcpy(gpio, priv->gpio, sizeof(gpio));
gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2);
(void) cxd2820r_gpio(&priv->fe, gpio);
return;
}
static int cxd2820r_gpio_get(struct gpio_chip *chip, unsigned nr)
{
struct cxd2820r_priv *priv = gpiochip_get_data(chip);
struct i2c_client *client = priv->client[0];
dev_dbg(&client->dev, "nr=%u\n", nr);
return (priv->gpio[nr] >> 2) & 0x01;
}
#endif
static const struct dvb_frontend_ops cxd2820r_ops = {
.delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
/* default: DVB-T/T2 */
.info = {
.name = "Sony CXD2820R",
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_2G_MODULATION |
FE_CAN_MULTISTREAM
},
.release = cxd2820r_release,
.init = cxd2820r_init,
.sleep = cxd2820r_sleep,
.get_tune_settings = cxd2820r_get_tune_settings,
.i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
.get_frontend = cxd2820r_get_frontend,
.get_frontend_algo = cxd2820r_get_frontend_algo,
.search = cxd2820r_search,
.read_status = cxd2820r_read_status,
.read_snr = cxd2820r_read_snr,
.read_ber = cxd2820r_read_ber,
.read_ucblocks = cxd2820r_read_ucblocks,
.read_signal_strength = cxd2820r_read_signal_strength,
};
/*
* XXX: That is wrapper to cxd2820r_probe() via driver core in order to provide
* proper I2C client for legacy media attach binding.
* New users must use I2C client binding directly!
*/
struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *config,
struct i2c_adapter *adapter,
int *gpio_chip_base)
{
struct i2c_client *client;
struct i2c_board_info board_info;
struct cxd2820r_platform_data pdata;
pdata.ts_mode = config->ts_mode;
pdata.ts_clk_inv = config->ts_clock_inv;
pdata.if_agc_polarity = config->if_agc_polarity;
pdata.spec_inv = config->spec_inv;
pdata.gpio_chip_base = &gpio_chip_base;
pdata.attach_in_use = true;
memset(&board_info, 0, sizeof(board_info));
strscpy(board_info.type, "cxd2820r", I2C_NAME_SIZE);
board_info.addr = config->i2c_address;
board_info.platform_data = &pdata;
client = i2c_new_client_device(adapter, &board_info);
if (!i2c_client_has_driver(client))
return NULL;
return pdata.get_dvb_frontend(client);
}
EXPORT_SYMBOL_GPL(cxd2820r_attach);
static struct dvb_frontend *cxd2820r_get_dvb_frontend(struct i2c_client *client)
{
struct cxd2820r_priv *priv = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &priv->fe;
}
static int cxd2820r_probe(struct i2c_client *client)
{
struct cxd2820r_platform_data *pdata = client->dev.platform_data;
struct cxd2820r_priv *priv;
int ret, *gpio_chip_base;
unsigned int utmp;
static const struct regmap_range_cfg regmap_range_cfg0[] = {
{
.range_min = 0x0000,
.range_max = 0x3fff,
.selector_reg = 0x00,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0x00,
.window_len = 0x100,
},
};
static const struct regmap_range_cfg regmap_range_cfg1[] = {
{
.range_min = 0x0000,
.range_max = 0x01ff,
.selector_reg = 0x00,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0x00,
.window_len = 0x100,
},
};
static const struct regmap_config regmap_config0 = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x3fff,
.ranges = regmap_range_cfg0,
.num_ranges = ARRAY_SIZE(regmap_range_cfg0),
.cache_type = REGCACHE_NONE,
};
static const struct regmap_config regmap_config1 = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x01ff,
.ranges = regmap_range_cfg1,
.num_ranges = ARRAY_SIZE(regmap_range_cfg1),
.cache_type = REGCACHE_NONE,
};
dev_dbg(&client->dev, "\n");
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err;
}
priv->client[0] = client;
priv->fe.demodulator_priv = priv;
priv->i2c = client->adapter;
priv->ts_mode = pdata->ts_mode;
priv->ts_clk_inv = pdata->ts_clk_inv;
priv->if_agc_polarity = pdata->if_agc_polarity;
priv->spec_inv = pdata->spec_inv;
gpio_chip_base = *pdata->gpio_chip_base;
priv->regmap[0] = regmap_init_i2c(priv->client[0], ®map_config0);
if (IS_ERR(priv->regmap[0])) {
ret = PTR_ERR(priv->regmap[0]);
goto err_kfree;
}
/* Check demod answers with correct chip id */
ret = regmap_read(priv->regmap[0], 0x00fd, &utmp);
if (ret)
goto err_regmap_0_regmap_exit;
dev_dbg(&client->dev, "chip_id=%02x\n", utmp);
if (utmp != 0xe1) {
ret = -ENODEV;
goto err_regmap_0_regmap_exit;
}
/*
* Chip has two I2C addresses for different register banks. We register
* one dummy I2C client in order to get own I2C client for each
* register bank.
*/
priv->client[1] = i2c_new_dummy_device(client->adapter, client->addr | (1 << 1));
if (IS_ERR(priv->client[1])) {
ret = PTR_ERR(priv->client[1]);
dev_err(&client->dev, "I2C registration failed\n");
goto err_regmap_0_regmap_exit;
}
priv->regmap[1] = regmap_init_i2c(priv->client[1], ®map_config1);
if (IS_ERR(priv->regmap[1])) {
ret = PTR_ERR(priv->regmap[1]);
goto err_client_1_i2c_unregister_device;
}
if (gpio_chip_base) {
#ifdef CONFIG_GPIOLIB
/* Add GPIOs */
priv->gpio_chip.label = KBUILD_MODNAME;
priv->gpio_chip.parent = &client->dev;
priv->gpio_chip.owner = THIS_MODULE;
priv->gpio_chip.direction_output = cxd2820r_gpio_direction_output;
priv->gpio_chip.set = cxd2820r_gpio_set;
priv->gpio_chip.get = cxd2820r_gpio_get;
priv->gpio_chip.base = -1; /* Dynamic allocation */
priv->gpio_chip.ngpio = GPIO_COUNT;
priv->gpio_chip.can_sleep = 1;
ret = gpiochip_add_data(&priv->gpio_chip, priv);
if (ret)
goto err_regmap_1_regmap_exit;
dev_dbg(&client->dev, "gpio_chip.base=%d\n",
priv->gpio_chip.base);
*gpio_chip_base = priv->gpio_chip.base;
#else
/*
* Use static GPIO configuration if GPIOLIB is undefined.
* This is fallback condition.
*/
u8 gpio[GPIO_COUNT];
gpio[0] = (*gpio_chip_base >> 0) & 0x07;
gpio[1] = (*gpio_chip_base >> 3) & 0x07;
gpio[2] = 0;
ret = cxd2820r_gpio(&priv->fe, gpio);
if (ret)
goto err_regmap_1_regmap_exit;
#endif
}
/* Create dvb frontend */
memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof(priv->fe.ops));
if (!pdata->attach_in_use)
priv->fe.ops.release = NULL;
i2c_set_clientdata(client, priv);
/* Setup callbacks */
pdata->get_dvb_frontend = cxd2820r_get_dvb_frontend;
dev_info(&client->dev, "Sony CXD2820R successfully identified\n");
return 0;
err_regmap_1_regmap_exit:
regmap_exit(priv->regmap[1]);
err_client_1_i2c_unregister_device:
i2c_unregister_device(priv->client[1]);
err_regmap_0_regmap_exit:
regmap_exit(priv->regmap[0]);
err_kfree:
kfree(priv);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void cxd2820r_remove(struct i2c_client *client)
{
struct cxd2820r_priv *priv = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
#ifdef CONFIG_GPIOLIB
if (priv->gpio_chip.label)
gpiochip_remove(&priv->gpio_chip);
#endif
regmap_exit(priv->regmap[1]);
i2c_unregister_device(priv->client[1]);
regmap_exit(priv->regmap[0]);
kfree(priv);
}
static const struct i2c_device_id cxd2820r_id_table[] = {
{"cxd2820r", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cxd2820r_id_table);
static struct i2c_driver cxd2820r_driver = {
.driver = {
.name = "cxd2820r",
.suppress_bind_attrs = true,
},
.probe = cxd2820r_probe,
.remove = cxd2820r_remove,
.id_table = cxd2820r_id_table,
};
module_i2c_driver(cxd2820r_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cxd2820r_core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for STV0297 demodulator
Copyright (C) 2004 Andrew de Quincey <[email protected]>
Copyright (C) 2003-2004 Dennis Noermann <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "stv0297.h"
struct stv0297_state {
struct i2c_adapter *i2c;
const struct stv0297_config *config;
struct dvb_frontend frontend;
unsigned long last_ber;
unsigned long base_freq;
};
#if 1
#define dprintk(x...) printk(x)
#else
#define dprintk(x...)
#endif
#define STV0297_CLOCK_KHZ 28900
static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static int stv0297_readreg(struct stv0297_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
};
// this device needs a STOP between the register and data
if (state->config->stop_during_read) {
if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
return -1;
}
if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
return -1;
}
} else {
if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
return -1;
}
}
return b1[0];
}
static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
{
int val;
val = stv0297_readreg(state, reg);
val &= ~mask;
val |= (data & mask);
stv0297_writereg(state, reg, val);
return 0;
}
static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
{
int ret;
struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
®1,.len = 1},
{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
};
// this device needs a STOP between the register and data
if (state->config->stop_during_read) {
if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
return -1;
}
if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
return -1;
}
} else {
if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
return -1;
}
}
return 0;
}
static u32 stv0297_get_symbolrate(struct stv0297_state *state)
{
u64 tmp;
tmp = (u64)(stv0297_readreg(state, 0x55)
| (stv0297_readreg(state, 0x56) << 8)
| (stv0297_readreg(state, 0x57) << 16)
| (stv0297_readreg(state, 0x58) << 24));
tmp *= STV0297_CLOCK_KHZ;
tmp >>= 32;
return (u32) tmp;
}
static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
{
long tmp;
tmp = 131072L * srate; /* 131072 = 2^17 */
tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
tmp = tmp * 8192L; /* 8192 = 2^13 */
stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
}
static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
{
long tmp;
tmp = (long) fshift *262144L; /* 262144 = 2*18 */
tmp /= symrate;
tmp *= 1024; /* 1024 = 2*10 */
// adjust
if (tmp >= 0) {
tmp += 500000;
} else {
tmp -= 500000;
}
tmp /= 1000000;
stv0297_writereg(state, 0x60, tmp & 0xFF);
stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
}
static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
{
long tmp;
/* symrate is hardcoded to 10000 */
tmp = offset * 26844L; /* (2**28)/10000 */
if (tmp < 0)
tmp += 0x10000000;
tmp &= 0x0FFFFFFF;
stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
}
/*
static long stv0297_get_carrieroffset(struct stv0297_state *state)
{
s64 tmp;
stv0297_writereg(state, 0x6B, 0x00);
tmp = stv0297_readreg(state, 0x66);
tmp |= (stv0297_readreg(state, 0x67) << 8);
tmp |= (stv0297_readreg(state, 0x68) << 16);
tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
tmp *= stv0297_get_symbolrate(state);
tmp >>= 28;
return (s32) tmp;
}
*/
static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
{
s32 tmp;
if (freq > 10000)
freq -= STV0297_CLOCK_KHZ;
tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
tmp = (freq * 1000) / tmp;
if (tmp > 0xffff)
tmp = 0xffff;
stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
stv0297_writereg(state, 0x21, tmp >> 8);
stv0297_writereg(state, 0x20, tmp);
}
static int stv0297_set_qam(struct stv0297_state *state,
enum fe_modulation modulation)
{
int val = 0;
switch (modulation) {
case QAM_16:
val = 0;
break;
case QAM_32:
val = 1;
break;
case QAM_64:
val = 4;
break;
case QAM_128:
val = 2;
break;
case QAM_256:
val = 3;
break;
default:
return -EINVAL;
}
stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
return 0;
}
static int stv0297_set_inversion(struct stv0297_state *state,
enum fe_spectral_inversion inversion)
{
int val = 0;
switch (inversion) {
case INVERSION_OFF:
val = 0;
break;
case INVERSION_ON:
val = 1;
break;
default:
return -EINVAL;
}
stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
return 0;
}
static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0297_state *state = fe->demodulator_priv;
if (enable) {
stv0297_writereg(state, 0x87, 0x78);
stv0297_writereg(state, 0x86, 0xc8);
}
return 0;
}
static int stv0297_init(struct dvb_frontend *fe)
{
struct stv0297_state *state = fe->demodulator_priv;
int i;
/* load init table */
for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
msleep(200);
state->last_ber = 0;
return 0;
}
static int stv0297_sleep(struct dvb_frontend *fe)
{
struct stv0297_state *state = fe->demodulator_priv;
stv0297_writereg_mask(state, 0x80, 1, 1);
return 0;
}
static int stv0297_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct stv0297_state *state = fe->demodulator_priv;
u8 sync = stv0297_readreg(state, 0xDF);
*status = 0;
if (sync & 0x80)
*status |=
FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
return 0;
}
static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct stv0297_state *state = fe->demodulator_priv;
u8 BER[3];
stv0297_readregs(state, 0xA0, BER, 3);
if (!(BER[0] & 0x80)) {
state->last_ber = BER[2] << 8 | BER[1];
stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
}
*ber = state->last_ber;
return 0;
}
static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct stv0297_state *state = fe->demodulator_priv;
u8 STRENGTH[3];
u16 tmp;
stv0297_readregs(state, 0x41, STRENGTH, 3);
tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
if (STRENGTH[2] & 0x20) {
if (tmp < 0x200)
tmp = 0;
else
tmp = tmp - 0x200;
} else {
if (tmp > 0x1ff)
tmp = 0;
else
tmp = 0x1ff - tmp;
}
*strength = (tmp << 7) | (tmp >> 2);
return 0;
}
static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct stv0297_state *state = fe->demodulator_priv;
u8 SNR[2];
stv0297_readregs(state, 0x07, SNR, 2);
*snr = SNR[1] << 8 | SNR[0];
return 0;
}
static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct stv0297_state *state = fe->demodulator_priv;
stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
| stv0297_readreg(state, 0xD4);
stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
return 0;
}
static int stv0297_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stv0297_state *state = fe->demodulator_priv;
int u_threshold;
int initial_u;
int blind_u;
int delay;
int sweeprate;
int carrieroffset;
unsigned long timeout;
enum fe_spectral_inversion inversion;
switch (p->modulation) {
case QAM_16:
case QAM_32:
case QAM_64:
delay = 100;
sweeprate = 1000;
break;
case QAM_128:
case QAM_256:
delay = 200;
sweeprate = 500;
break;
default:
return -EINVAL;
}
// determine inversion dependent parameters
inversion = p->inversion;
if (state->config->invert)
inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
carrieroffset = -330;
switch (inversion) {
case INVERSION_OFF:
break;
case INVERSION_ON:
sweeprate = -sweeprate;
carrieroffset = -carrieroffset;
break;
default:
return -EINVAL;
}
stv0297_init(fe);
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
/* clear software interrupts */
stv0297_writereg(state, 0x82, 0x0);
/* set initial demodulation frequency */
stv0297_set_initialdemodfreq(state, 7250);
/* setup AGC */
stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
stv0297_writereg(state, 0x41, 0x00);
stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
stv0297_writereg(state, 0x72, 0x00);
stv0297_writereg(state, 0x73, 0x00);
stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
/* setup STL */
stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
/* disable frequency sweep */
stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
/* reset deinterleaver */
stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
/* ??? */
stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
/* reset equaliser */
u_threshold = stv0297_readreg(state, 0x00) & 0xf;
initial_u = stv0297_readreg(state, 0x01) >> 4;
blind_u = stv0297_readreg(state, 0x01) & 0xf;
stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
/* data comes from internal A/D */
stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
/* clear phase registers */
stv0297_writereg(state, 0x63, 0x00);
stv0297_writereg(state, 0x64, 0x00);
stv0297_writereg(state, 0x65, 0x00);
stv0297_writereg(state, 0x66, 0x00);
stv0297_writereg(state, 0x67, 0x00);
stv0297_writereg(state, 0x68, 0x00);
stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
/* set parameters */
stv0297_set_qam(state, p->modulation);
stv0297_set_symbolrate(state, p->symbol_rate / 1000);
stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
stv0297_set_carrieroffset(state, carrieroffset);
stv0297_set_inversion(state, inversion);
/* kick off lock */
/* Disable corner detection for higher QAMs */
if (p->modulation == QAM_128 ||
p->modulation == QAM_256)
stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
else
stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
/* wait for WGAGC lock */
timeout = jiffies + msecs_to_jiffies(2000);
while (time_before(jiffies, timeout)) {
msleep(10);
if (stv0297_readreg(state, 0x43) & 0x08)
break;
}
if (time_after(jiffies, timeout)) {
goto timeout;
}
msleep(20);
/* wait for equaliser partial convergence */
timeout = jiffies + msecs_to_jiffies(500);
while (time_before(jiffies, timeout)) {
msleep(10);
if (stv0297_readreg(state, 0x82) & 0x04) {
break;
}
}
if (time_after(jiffies, timeout)) {
goto timeout;
}
/* wait for equaliser full convergence */
timeout = jiffies + msecs_to_jiffies(delay);
while (time_before(jiffies, timeout)) {
msleep(10);
if (stv0297_readreg(state, 0x82) & 0x08) {
break;
}
}
if (time_after(jiffies, timeout)) {
goto timeout;
}
/* disable sweep */
stv0297_writereg_mask(state, 0x6a, 1, 0);
stv0297_writereg_mask(state, 0x88, 8, 0);
/* wait for main lock */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
msleep(10);
if (stv0297_readreg(state, 0xDF) & 0x80) {
break;
}
}
if (time_after(jiffies, timeout)) {
goto timeout;
}
msleep(100);
/* is it still locked after that delay? */
if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
goto timeout;
}
/* success!! */
stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
state->base_freq = p->frequency;
return 0;
timeout:
stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
return 0;
}
static int stv0297_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0297_state *state = fe->demodulator_priv;
int reg_00, reg_83;
reg_00 = stv0297_readreg(state, 0x00);
reg_83 = stv0297_readreg(state, 0x83);
p->frequency = state->base_freq;
p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
if (state->config->invert)
p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
p->fec_inner = FEC_NONE;
switch ((reg_00 >> 4) & 0x7) {
case 0:
p->modulation = QAM_16;
break;
case 1:
p->modulation = QAM_32;
break;
case 2:
p->modulation = QAM_128;
break;
case 3:
p->modulation = QAM_256;
break;
case 4:
p->modulation = QAM_64;
break;
}
return 0;
}
static void stv0297_release(struct dvb_frontend *fe)
{
struct stv0297_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops stv0297_ops;
struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
struct i2c_adapter *i2c)
{
struct stv0297_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->last_ber = 0;
state->base_freq = 0;
/* check if the demod is there */
if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops stv0297_ops = {
.delsys = { SYS_DVBC_ANNEX_A },
.info = {
.name = "ST STV0297 DVB-C",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 870000,
.symbol_rate_max = 11700000,
.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
.release = stv0297_release,
.init = stv0297_init,
.sleep = stv0297_sleep,
.i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
.set_frontend = stv0297_set_frontend,
.get_frontend = stv0297_get_frontend,
.read_status = stv0297_read_status,
.read_ber = stv0297_read_ber,
.read_signal_strength = stv0297_read_signal_strength,
.read_snr = stv0297_read_snr,
.read_ucblocks = stv0297_read_ucblocks,
};
MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(stv0297_attach);
| linux-master | drivers/media/dvb-frontends/stv0297.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for NXT2002 and NXT2004 - VSB/QAM
*
* Copyright (C) 2005 Kirk Lapray <[email protected]>
* Copyright (C) 2006-2014 Michael Krufky <[email protected]>
* based on nxt2002 by Taylor Jacob <[email protected]>
* and nxt2004 by Jean-Francois Thibert <[email protected]>
*/
/*
* NOTES ABOUT THIS DRIVER
*
* This Linux driver supports:
* B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
* AverTVHD MCE A180 (NXT2004)
* ATI HDTV Wonder (NXT2004)
*
* This driver needs external firmware. Please use the command
* "<kerneldir>/scripts/get_dvb_firmware nxt2002" or
* "<kerneldir>/scripts/get_dvb_firmware nxt2004" to
* download/extract the appropriate firmware, and then copy it to
* /usr/lib/hotplug/firmware/ or /lib/firmware/
* (depending on configuration of firmware hotplug).
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 256
#define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
#define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
#define CRC_CCIT_MASK 0x1021
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <media/dvb_frontend.h>
#include "nxt200x.h"
struct nxt200x_state {
struct i2c_adapter* i2c;
const struct nxt200x_config* config;
struct dvb_frontend frontend;
/* demodulator private data */
nxt_chip_type demod_chip;
u8 initialised:1;
};
static int debug;
#define dprintk(args...) do { if (debug) pr_debug(args); } while (0)
static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len)
{
int err;
struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len };
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
__func__, addr, err);
return -EREMOTEIO;
}
return 0;
}
static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len)
{
int err;
struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len };
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
__func__, addr, err);
return -EREMOTEIO;
}
return 0;
}
static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg,
const u8 *buf, u8 len)
{
u8 buf2[MAX_XFER_SIZE];
int err;
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
if (1 + len > sizeof(buf2)) {
pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
__func__, reg, len);
return -EINVAL;
}
buf2[0] = reg;
memcpy(&buf2[1], buf, len);
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
__func__, state->config->demod_address, err);
return -EREMOTEIO;
}
return 0;
}
static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len)
{
u8 reg2 [] = { reg };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
int err;
if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
__func__, state->config->demod_address, err);
return -EREMOTEIO;
}
return 0;
}
static u16 nxt200x_crc(u16 crc, u8 c)
{
u8 i;
u16 input = (u16) c & 0xFF;
input<<=8;
for(i=0; i<8; i++) {
if((crc^input) & 0x8000)
crc=(crc<<1)^CRC_CCIT_MASK;
else
crc<<=1;
input<<=1;
}
return crc;
}
static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
{
u8 attr, len2, buf;
dprintk("%s\n", __func__);
/* set multi register register */
nxt200x_writebytes(state, 0x35, ®, 1);
/* send the actual data */
nxt200x_writebytes(state, 0x36, data, len);
switch (state->demod_chip) {
case NXT2002:
len2 = len;
buf = 0x02;
break;
case NXT2004:
/* probably not right, but gives correct values */
attr = 0x02;
if (reg & 0x80) {
attr = attr << 1;
if (reg & 0x04)
attr = attr >> 1;
}
/* set write bit */
len2 = ((attr << 4) | 0x10) | len;
buf = 0x80;
break;
default:
return -EINVAL;
}
/* set multi register length */
nxt200x_writebytes(state, 0x34, &len2, 1);
/* toggle the multireg write bit */
nxt200x_writebytes(state, 0x21, &buf, 1);
nxt200x_readbytes(state, 0x21, &buf, 1);
switch (state->demod_chip) {
case NXT2002:
if ((buf & 0x02) == 0)
return 0;
break;
case NXT2004:
if (buf == 0)
return 0;
break;
default:
return -EINVAL;
}
pr_warn("Error writing multireg register 0x%02X\n", reg);
return 0;
}
static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
{
int i;
u8 buf, len2, attr;
dprintk("%s\n", __func__);
/* set multi register register */
nxt200x_writebytes(state, 0x35, ®, 1);
switch (state->demod_chip) {
case NXT2002:
/* set multi register length */
len2 = len & 0x80;
nxt200x_writebytes(state, 0x34, &len2, 1);
/* read the actual data */
nxt200x_readbytes(state, reg, data, len);
return 0;
case NXT2004:
/* probably not right, but gives correct values */
attr = 0x02;
if (reg & 0x80) {
attr = attr << 1;
if (reg & 0x04)
attr = attr >> 1;
}
/* set multi register length */
len2 = (attr << 4) | len;
nxt200x_writebytes(state, 0x34, &len2, 1);
/* toggle the multireg bit*/
buf = 0x80;
nxt200x_writebytes(state, 0x21, &buf, 1);
/* read the actual data */
for(i = 0; i < len; i++) {
nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
}
return 0;
default:
return -EINVAL;
}
}
static void nxt200x_microcontroller_stop (struct nxt200x_state* state)
{
u8 buf, stopval, counter = 0;
dprintk("%s\n", __func__);
/* set correct stop value */
switch (state->demod_chip) {
case NXT2002:
stopval = 0x40;
break;
case NXT2004:
stopval = 0x10;
break;
default:
stopval = 0;
break;
}
buf = 0x80;
nxt200x_writebytes(state, 0x22, &buf, 1);
while (counter < 20) {
nxt200x_readbytes(state, 0x31, &buf, 1);
if (buf & stopval)
return;
msleep(10);
counter++;
}
pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n");
return;
}
static void nxt200x_microcontroller_start (struct nxt200x_state* state)
{
u8 buf;
dprintk("%s\n", __func__);
buf = 0x00;
nxt200x_writebytes(state, 0x22, &buf, 1);
}
static void nxt2004_microcontroller_init (struct nxt200x_state* state)
{
u8 buf[9];
u8 counter = 0;
dprintk("%s\n", __func__);
buf[0] = 0x00;
nxt200x_writebytes(state, 0x2b, buf, 1);
buf[0] = 0x70;
nxt200x_writebytes(state, 0x34, buf, 1);
buf[0] = 0x04;
nxt200x_writebytes(state, 0x35, buf, 1);
buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89;
buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0;
nxt200x_writebytes(state, 0x36, buf, 9);
buf[0] = 0x80;
nxt200x_writebytes(state, 0x21, buf, 1);
while (counter < 20) {
nxt200x_readbytes(state, 0x21, buf, 1);
if (buf[0] == 0)
return;
msleep(10);
counter++;
}
pr_warn("Timeout waiting for nxt2004 to init.\n");
return;
}
static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
{
u8 buf, count = 0;
dprintk("%s\n", __func__);
dprintk("Tuner Bytes: %*ph\n", 4, data + 1);
/* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.
* direct write is required for Philips TUV1236D and ALPS TDHU2 */
switch (state->demod_chip) {
case NXT2004:
if (i2c_writebytes(state, data[0], data+1, 4))
pr_warn("error writing to tuner\n");
/* wait until we have a lock */
while (count < 20) {
i2c_readbytes(state, data[0], &buf, 1);
if (buf & 0x40)
return 0;
msleep(100);
count++;
}
pr_warn("timeout waiting for tuner lock\n");
break;
case NXT2002:
/* set the i2c transfer speed to the tuner */
buf = 0x03;
nxt200x_writebytes(state, 0x20, &buf, 1);
/* setup to transfer 4 bytes via i2c */
buf = 0x04;
nxt200x_writebytes(state, 0x34, &buf, 1);
/* write actual tuner bytes */
nxt200x_writebytes(state, 0x36, data+1, 4);
/* set tuner i2c address */
buf = data[0] << 1;
nxt200x_writebytes(state, 0x35, &buf, 1);
/* write UC Opmode to begin transfer */
buf = 0x80;
nxt200x_writebytes(state, 0x21, &buf, 1);
while (count < 20) {
nxt200x_readbytes(state, 0x21, &buf, 1);
if ((buf & 0x80)== 0x00)
return 0;
msleep(100);
count++;
}
pr_warn("timeout error writing to tuner\n");
break;
default:
return -EINVAL;
}
return 0;
}
static void nxt200x_agc_reset(struct nxt200x_state* state)
{
u8 buf;
dprintk("%s\n", __func__);
switch (state->demod_chip) {
case NXT2002:
buf = 0x08;
nxt200x_writebytes(state, 0x08, &buf, 1);
buf = 0x00;
nxt200x_writebytes(state, 0x08, &buf, 1);
break;
case NXT2004:
nxt200x_readreg_multibyte(state, 0x08, &buf, 1);
buf = 0x08;
nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
buf = 0x00;
nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
break;
default:
break;
}
return;
}
static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 buf[3], written = 0, chunkpos = 0;
u16 rambase, position, crc = 0;
dprintk("%s\n", __func__);
dprintk("Firmware is %zu bytes\n", fw->size);
/* Get the RAM base for this nxt2002 */
nxt200x_readbytes(state, 0x10, buf, 1);
if (buf[0] & 0x10)
rambase = 0x1000;
else
rambase = 0x0000;
dprintk("rambase on this nxt2002 is %04X\n", rambase);
/* Hold the micro in reset while loading firmware */
buf[0] = 0x80;
nxt200x_writebytes(state, 0x2B, buf, 1);
for (position = 0; position < fw->size; position++) {
if (written == 0) {
crc = 0;
chunkpos = 0x28;
buf[0] = ((rambase + position) >> 8);
buf[1] = (rambase + position) & 0xFF;
buf[2] = 0x81;
/* write starting address */
nxt200x_writebytes(state, 0x29, buf, 3);
}
written++;
chunkpos++;
if ((written % 4) == 0)
nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4);
crc = nxt200x_crc(crc, fw->data[position]);
if ((written == 255) || (position+1 == fw->size)) {
/* write remaining bytes of firmware */
nxt200x_writebytes(state, chunkpos+4-(written %4),
&fw->data[position-(written %4) + 1],
written %4);
buf[0] = crc << 8;
buf[1] = crc & 0xFF;
/* write crc */
nxt200x_writebytes(state, 0x2C, buf, 2);
/* do a read to stop things */
nxt200x_readbytes(state, 0x2A, buf, 1);
/* set transfer mode to complete */
buf[0] = 0x80;
nxt200x_writebytes(state, 0x2B, buf, 1);
written = 0;
}
}
return 0;
};
static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 buf[3];
u16 rambase, position, crc=0;
dprintk("%s\n", __func__);
dprintk("Firmware is %zu bytes\n", fw->size);
/* set rambase */
rambase = 0x1000;
/* hold the micro in reset while loading firmware */
buf[0] = 0x80;
nxt200x_writebytes(state, 0x2B, buf,1);
/* calculate firmware CRC */
for (position = 0; position < fw->size; position++) {
crc = nxt200x_crc(crc, fw->data[position]);
}
buf[0] = rambase >> 8;
buf[1] = rambase & 0xFF;
buf[2] = 0x81;
/* write starting address */
nxt200x_writebytes(state,0x29,buf,3);
for (position = 0; position < fw->size;) {
nxt200x_writebytes(state, 0x2C, &fw->data[position],
fw->size-position > 255 ? 255 : fw->size-position);
position += (fw->size-position > 255 ? 255 : fw->size-position);
}
buf[0] = crc >> 8;
buf[1] = crc & 0xFF;
dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]);
/* write crc */
nxt200x_writebytes(state, 0x2C, buf,2);
/* do a read to stop things */
nxt200x_readbytes(state, 0x2C, buf, 1);
/* set transfer mode to complete */
buf[0] = 0x80;
nxt200x_writebytes(state, 0x2B, buf,1);
return 0;
};
static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct nxt200x_state* state = fe->demodulator_priv;
u8 buf[5];
/* stop the micro first */
nxt200x_microcontroller_stop(state);
if (state->demod_chip == NXT2004) {
/* make sure demod is set to digital */
buf[0] = 0x04;
nxt200x_writebytes(state, 0x14, buf, 1);
buf[0] = 0x00;
nxt200x_writebytes(state, 0x17, buf, 1);
}
/* set additional params */
switch (p->modulation) {
case QAM_64:
case QAM_256:
/* Set punctured clock for QAM */
/* This is just a guess since I am unable to test it */
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 1);
break;
case VSB_8:
/* Set non-punctured clock for VSB */
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
break;
default:
return -EINVAL;
}
if (fe->ops.tuner_ops.calc_regs) {
/* get tuning information */
fe->ops.tuner_ops.calc_regs(fe, buf, 5);
/* write frequency information */
nxt200x_writetuner(state, buf);
}
/* reset the agc now that tuning has been completed */
nxt200x_agc_reset(state);
/* set target power level */
switch (p->modulation) {
case QAM_64:
case QAM_256:
buf[0] = 0x74;
break;
case VSB_8:
buf[0] = 0x70;
break;
default:
return -EINVAL;
}
nxt200x_writebytes(state, 0x42, buf, 1);
/* configure sdm */
switch (state->demod_chip) {
case NXT2002:
buf[0] = 0x87;
break;
case NXT2004:
buf[0] = 0x07;
break;
default:
return -EINVAL;
}
nxt200x_writebytes(state, 0x57, buf, 1);
/* write sdm1 input */
buf[0] = 0x10;
buf[1] = 0x00;
switch (state->demod_chip) {
case NXT2002:
nxt200x_writereg_multibyte(state, 0x58, buf, 2);
break;
case NXT2004:
nxt200x_writebytes(state, 0x58, buf, 2);
break;
default:
return -EINVAL;
}
/* write sdmx input */
switch (p->modulation) {
case QAM_64:
buf[0] = 0x68;
break;
case QAM_256:
buf[0] = 0x64;
break;
case VSB_8:
buf[0] = 0x60;
break;
default:
return -EINVAL;
}
buf[1] = 0x00;
switch (state->demod_chip) {
case NXT2002:
nxt200x_writereg_multibyte(state, 0x5C, buf, 2);
break;
case NXT2004:
nxt200x_writebytes(state, 0x5C, buf, 2);
break;
default:
return -EINVAL;
}
/* write adc power lpf fc */
buf[0] = 0x05;
nxt200x_writebytes(state, 0x43, buf, 1);
if (state->demod_chip == NXT2004) {
/* write ??? */
buf[0] = 0x00;
buf[1] = 0x00;
nxt200x_writebytes(state, 0x46, buf, 2);
}
/* write accumulator2 input */
buf[0] = 0x80;
buf[1] = 0x00;
switch (state->demod_chip) {
case NXT2002:
nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
break;
case NXT2004:
nxt200x_writebytes(state, 0x4B, buf, 2);
break;
default:
return -EINVAL;
}
/* write kg1 */
buf[0] = 0x00;
nxt200x_writebytes(state, 0x4D, buf, 1);
/* write sdm12 lpf fc */
buf[0] = 0x44;
nxt200x_writebytes(state, 0x55, buf, 1);
/* write agc control reg */
buf[0] = 0x04;
nxt200x_writebytes(state, 0x41, buf, 1);
if (state->demod_chip == NXT2004) {
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x24;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
/* soft reset? */
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x10;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x04;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x81, buf, 1);
buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
nxt200x_writereg_multibyte(state, 0x82, buf, 3);
nxt200x_readreg_multibyte(state, 0x88, buf, 1);
buf[0] = 0x11;
nxt200x_writereg_multibyte(state, 0x88, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x44;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
}
/* write agc ucgp0 */
switch (p->modulation) {
case QAM_64:
buf[0] = 0x02;
break;
case QAM_256:
buf[0] = 0x03;
break;
case VSB_8:
buf[0] = 0x00;
break;
default:
return -EINVAL;
}
nxt200x_writebytes(state, 0x30, buf, 1);
/* write agc control reg */
buf[0] = 0x00;
nxt200x_writebytes(state, 0x41, buf, 1);
/* write accumulator2 input */
buf[0] = 0x80;
buf[1] = 0x00;
switch (state->demod_chip) {
case NXT2002:
nxt200x_writereg_multibyte(state, 0x49, buf, 2);
nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
break;
case NXT2004:
nxt200x_writebytes(state, 0x49, buf, 2);
nxt200x_writebytes(state, 0x4B, buf, 2);
break;
default:
return -EINVAL;
}
/* write agc control reg */
buf[0] = 0x04;
nxt200x_writebytes(state, 0x41, buf, 1);
nxt200x_microcontroller_start(state);
if (state->demod_chip == NXT2004) {
nxt2004_microcontroller_init(state);
/* ???? */
buf[0] = 0xF0;
buf[1] = 0x00;
nxt200x_writebytes(state, 0x5C, buf, 2);
}
/* adjacent channel detection should be done here, but I don't
have any stations with this need so I cannot test it */
return 0;
}
static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 lock;
nxt200x_readbytes(state, 0x31, &lock, 1);
*status = 0;
if (lock & 0x20) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
}
return 0;
}
static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 b[3];
nxt200x_readreg_multibyte(state, 0xE6, b, 3);
*ber = ((b[0] << 8) + b[1]) * 8;
return 0;
}
static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 b[2];
u16 temp = 0;
/* setup to read cluster variance */
b[0] = 0x00;
nxt200x_writebytes(state, 0xA1, b, 1);
/* get multreg val */
nxt200x_readreg_multibyte(state, 0xA6, b, 2);
temp = (b[0] << 8) | b[1];
*strength = ((0x7FFF - temp) & 0x0FFF) * 16;
return 0;
}
static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 b[2];
u16 temp = 0, temp2;
u32 snrdb = 0;
/* setup to read cluster variance */
b[0] = 0x00;
nxt200x_writebytes(state, 0xA1, b, 1);
/* get multreg val from 0xA6 */
nxt200x_readreg_multibyte(state, 0xA6, b, 2);
temp = (b[0] << 8) | b[1];
temp2 = 0x7FFF - temp;
/* snr will be in db */
if (temp2 > 0x7F00)
snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
else if (temp2 > 0x7EC0)
snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
else if (temp2 > 0x7C00)
snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
else
snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
/* the value reported back from the frontend will be FFFF=32db 0000=0db */
*snr = snrdb * (0xFFFF/32000);
return 0;
}
static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct nxt200x_state* state = fe->demodulator_priv;
u8 b[3];
nxt200x_readreg_multibyte(state, 0xE6, b, 3);
*ucblocks = b[2];
return 0;
}
static int nxt200x_sleep(struct dvb_frontend* fe)
{
return 0;
}
static int nxt2002_init(struct dvb_frontend* fe)
{
struct nxt200x_state* state = fe->demodulator_priv;
const struct firmware *fw;
int ret;
u8 buf[2];
/* request the firmware, this will block until someone uploads it */
pr_debug("%s: Waiting for firmware upload (%s)...\n",
__func__, NXT2002_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE,
state->i2c->dev.parent);
pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
if (ret) {
pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
__func__);
return ret;
}
ret = nxt2002_load_firmware(fe, fw);
release_firmware(fw);
if (ret) {
pr_err("%s: Writing firmware to device failed\n", __func__);
return ret;
}
pr_info("%s: Firmware upload complete\n", __func__);
/* Put the micro into reset */
nxt200x_microcontroller_stop(state);
/* ensure transfer is complete */
buf[0]=0x00;
nxt200x_writebytes(state, 0x2B, buf, 1);
/* Put the micro into reset for real this time */
nxt200x_microcontroller_stop(state);
/* soft reset everything (agc,frontend,eq,fec)*/
buf[0] = 0x0F;
nxt200x_writebytes(state, 0x08, buf, 1);
buf[0] = 0x00;
nxt200x_writebytes(state, 0x08, buf, 1);
/* write agc sdm configure */
buf[0] = 0xF1;
nxt200x_writebytes(state, 0x57, buf, 1);
/* write mod output format */
buf[0] = 0x20;
nxt200x_writebytes(state, 0x09, buf, 1);
/* write fec mpeg mode */
buf[0] = 0x7E;
buf[1] = 0x00;
nxt200x_writebytes(state, 0xE9, buf, 2);
/* write mux selection */
buf[0] = 0x00;
nxt200x_writebytes(state, 0xCC, buf, 1);
return 0;
}
static int nxt2004_init(struct dvb_frontend* fe)
{
struct nxt200x_state* state = fe->demodulator_priv;
const struct firmware *fw;
int ret;
u8 buf[3];
/* ??? */
buf[0]=0x00;
nxt200x_writebytes(state, 0x1E, buf, 1);
/* request the firmware, this will block until someone uploads it */
pr_debug("%s: Waiting for firmware upload (%s)...\n",
__func__, NXT2004_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE,
state->i2c->dev.parent);
pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
if (ret) {
pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
__func__);
return ret;
}
ret = nxt2004_load_firmware(fe, fw);
release_firmware(fw);
if (ret) {
pr_err("%s: Writing firmware to device failed\n", __func__);
return ret;
}
pr_info("%s: Firmware upload complete\n", __func__);
/* ensure transfer is complete */
buf[0] = 0x01;
nxt200x_writebytes(state, 0x19, buf, 1);
nxt2004_microcontroller_init(state);
nxt200x_microcontroller_stop(state);
nxt200x_microcontroller_stop(state);
nxt2004_microcontroller_init(state);
nxt200x_microcontroller_stop(state);
/* soft reset everything (agc,frontend,eq,fec)*/
buf[0] = 0xFF;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
/* write agc sdm configure */
buf[0] = 0xD7;
nxt200x_writebytes(state, 0x57, buf, 1);
/* ???*/
buf[0] = 0x07;
buf[1] = 0xfe;
nxt200x_writebytes(state, 0x35, buf, 2);
buf[0] = 0x12;
nxt200x_writebytes(state, 0x34, buf, 1);
buf[0] = 0x80;
nxt200x_writebytes(state, 0x21, buf, 1);
/* ???*/
buf[0] = 0x21;
nxt200x_writebytes(state, 0x0A, buf, 1);
/* ???*/
buf[0] = 0x01;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
/* write fec mpeg mode */
buf[0] = 0x7E;
buf[1] = 0x00;
nxt200x_writebytes(state, 0xE9, buf, 2);
/* write mux selection */
buf[0] = 0x00;
nxt200x_writebytes(state, 0xCC, buf, 1);
/* ???*/
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
/* soft reset? */
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x10;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
/* ???*/
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x01;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x70;
nxt200x_writereg_multibyte(state, 0x81, buf, 1);
buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66;
nxt200x_writereg_multibyte(state, 0x82, buf, 3);
nxt200x_readreg_multibyte(state, 0x88, buf, 1);
buf[0] = 0x11;
nxt200x_writereg_multibyte(state, 0x88, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x40;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
nxt200x_readbytes(state, 0x10, buf, 1);
buf[0] = 0x10;
nxt200x_writebytes(state, 0x10, buf, 1);
nxt200x_readbytes(state, 0x0A, buf, 1);
buf[0] = 0x21;
nxt200x_writebytes(state, 0x0A, buf, 1);
nxt2004_microcontroller_init(state);
buf[0] = 0x21;
nxt200x_writebytes(state, 0x0A, buf, 1);
buf[0] = 0x7E;
nxt200x_writebytes(state, 0xE9, buf, 1);
buf[0] = 0x00;
nxt200x_writebytes(state, 0xEA, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
/* soft reset? */
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x10;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
nxt200x_readreg_multibyte(state, 0x08, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x08, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x04;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x00;
nxt200x_writereg_multibyte(state, 0x81, buf, 1);
buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
nxt200x_writereg_multibyte(state, 0x82, buf, 3);
nxt200x_readreg_multibyte(state, 0x88, buf, 1);
buf[0] = 0x11;
nxt200x_writereg_multibyte(state, 0x88, buf, 1);
nxt200x_readreg_multibyte(state, 0x80, buf, 1);
buf[0] = 0x44;
nxt200x_writereg_multibyte(state, 0x80, buf, 1);
/* initialize tuner */
nxt200x_readbytes(state, 0x10, buf, 1);
buf[0] = 0x12;
nxt200x_writebytes(state, 0x10, buf, 1);
buf[0] = 0x04;
nxt200x_writebytes(state, 0x13, buf, 1);
buf[0] = 0x00;
nxt200x_writebytes(state, 0x16, buf, 1);
buf[0] = 0x04;
nxt200x_writebytes(state, 0x14, buf, 1);
buf[0] = 0x00;
nxt200x_writebytes(state, 0x14, buf, 1);
nxt200x_writebytes(state, 0x17, buf, 1);
nxt200x_writebytes(state, 0x14, buf, 1);
nxt200x_writebytes(state, 0x17, buf, 1);
return 0;
}
static int nxt200x_init(struct dvb_frontend* fe)
{
struct nxt200x_state* state = fe->demodulator_priv;
int ret = 0;
if (!state->initialised) {
switch (state->demod_chip) {
case NXT2002:
ret = nxt2002_init(fe);
break;
case NXT2004:
ret = nxt2004_init(fe);
break;
default:
return -EINVAL;
}
state->initialised = 1;
}
return ret;
}
static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 500;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void nxt200x_release(struct dvb_frontend* fe)
{
struct nxt200x_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops nxt200x_ops;
struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config,
struct i2c_adapter* i2c)
{
struct nxt200x_state* state = NULL;
u8 buf [] = {0,0,0,0,0};
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->initialised = 0;
/* read card id */
nxt200x_readbytes(state, 0x00, buf, 5);
dprintk("NXT info: %*ph\n", 5, buf);
/* set demod chip */
switch (buf[0]) {
case 0x04:
state->demod_chip = NXT2002;
pr_info("NXT2002 Detected\n");
break;
case 0x05:
state->demod_chip = NXT2004;
pr_info("NXT2004 Detected\n");
break;
default:
goto error;
}
/* make sure demod chip is supported */
switch (state->demod_chip) {
case NXT2002:
if (buf[0] != 0x04) goto error; /* device id */
if (buf[1] != 0x02) goto error; /* fab id */
if (buf[2] != 0x11) goto error; /* month */
if (buf[3] != 0x20) goto error; /* year msb */
if (buf[4] != 0x00) goto error; /* year lsb */
break;
case NXT2004:
if (buf[0] != 0x05) goto error; /* device id */
break;
default:
goto error;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf);
return NULL;
}
static const struct dvb_frontend_ops nxt200x_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Nextwave NXT200X VSB/QAM frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 860 * MHz,
.frequency_stepsize_hz = 166666, /* stepsize is just a guess */
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
},
.release = nxt200x_release,
.init = nxt200x_init,
.sleep = nxt200x_sleep,
.set_frontend = nxt200x_setup_frontend_parameters,
.get_tune_settings = nxt200x_get_tune_settings,
.read_status = nxt200x_read_status,
.read_ber = nxt200x_read_ber,
.read_signal_strength = nxt200x_read_signal_strength,
.read_snr = nxt200x_read_snr,
.read_ucblocks = nxt200x_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(nxt200x_attach);
| linux-master | drivers/media/dvb-frontends/nxt200x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for ST STB6000 DVBS Silicon tuner
Copyright (C) 2008 Igor M. Liplianin ([email protected])
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <asm/types.h>
#include "stb6000.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "stb6000: " args); \
} while (0)
struct stb6000_priv {
/* i2c details */
int i2c_address;
struct i2c_adapter *i2c;
u32 frequency;
};
static void stb6000_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int stb6000_sleep(struct dvb_frontend *fe)
{
struct stb6000_priv *priv = fe->tuner_priv;
int ret;
u8 buf[] = { 10, 0 };
struct i2c_msg msg = {
.addr = priv->i2c_address,
.flags = 0,
.buf = buf,
.len = 2
};
dprintk("%s:\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: i2c error\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return (ret == 1) ? 0 : ret;
}
static int stb6000_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stb6000_priv *priv = fe->tuner_priv;
unsigned int n, m;
int ret;
u32 freq_mhz;
int bandwidth;
u8 buf[12];
struct i2c_msg msg = {
.addr = priv->i2c_address,
.flags = 0,
.buf = buf,
.len = 12
};
dprintk("%s:\n", __func__);
freq_mhz = p->frequency / 1000;
bandwidth = p->symbol_rate / 1000000;
if (bandwidth > 31)
bandwidth = 31;
if ((freq_mhz > 949) && (freq_mhz < 2151)) {
buf[0] = 0x01;
buf[1] = 0xac;
if (freq_mhz < 1950)
buf[1] = 0xaa;
if (freq_mhz < 1800)
buf[1] = 0xa8;
if (freq_mhz < 1650)
buf[1] = 0xa6;
if (freq_mhz < 1530)
buf[1] = 0xa5;
if (freq_mhz < 1470)
buf[1] = 0xa4;
if (freq_mhz < 1370)
buf[1] = 0xa2;
if (freq_mhz < 1300)
buf[1] = 0xa1;
if (freq_mhz < 1200)
buf[1] = 0xa0;
if (freq_mhz < 1075)
buf[1] = 0xbc;
if (freq_mhz < 1000)
buf[1] = 0xba;
if (freq_mhz < 1075) {
n = freq_mhz / 8; /* vco=lo*4 */
m = 2;
} else {
n = freq_mhz / 16; /* vco=lo*2 */
m = 1;
}
buf[2] = n >> 1;
buf[3] = (unsigned char)(((n & 1) << 7) |
(m * freq_mhz - n * 16) | 0x60);
buf[4] = 0x04;
buf[5] = 0x0e;
buf[6] = (unsigned char)(bandwidth);
buf[7] = 0xd8;
buf[8] = 0xd0;
buf[9] = 0x50;
buf[10] = 0xeb;
buf[11] = 0x4f;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: i2c error\n", __func__);
udelay(10);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
buf[0] = 0x07;
buf[1] = 0xdf;
buf[2] = 0xd0;
buf[3] = 0x50;
buf[4] = 0xfb;
msg.len = 5;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: i2c error\n", __func__);
udelay(10);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
priv->frequency = freq_mhz * 1000;
return (ret == 1) ? 0 : ret;
}
return -1;
}
static int stb6000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct stb6000_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static const struct dvb_tuner_ops stb6000_tuner_ops = {
.info = {
.name = "ST STB6000",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz
},
.release = stb6000_release,
.sleep = stb6000_sleep,
.set_params = stb6000_set_params,
.get_frequency = stb6000_get_frequency,
};
struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr,
struct i2c_adapter *i2c)
{
struct stb6000_priv *priv = NULL;
u8 b0[] = { 0 };
u8 b1[] = { 0, 0 };
struct i2c_msg msg[2] = {
{
.addr = addr,
.flags = 0,
.buf = b0,
.len = 0
}, {
.addr = addr,
.flags = I2C_M_RD,
.buf = b1,
.len = 2
}
};
int ret;
dprintk("%s:\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* is some i2c device here ? */
ret = i2c_transfer(i2c, msg, 2);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret != 2)
return NULL;
priv = kzalloc(sizeof(struct stb6000_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = addr;
priv->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &stb6000_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
}
EXPORT_SYMBOL_GPL(stb6000_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("DVB STB6000 driver");
MODULE_AUTHOR("Igor M. Liplianin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stb6000.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux-DVB Driver for DiBcom's DiB7000M and
* first generation DiB7000P-demodulator-family.
*
* Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <media/dvb_frontend.h>
#include "dib7000m.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
struct dib7000m_state {
struct dvb_frontend demod;
struct dib7000m_config cfg;
u8 i2c_addr;
struct i2c_adapter *i2c_adap;
struct dibx000_i2c_master i2c_master;
/* offset is 1 in case of the 7000MC */
u8 reg_offs;
u16 wbd_ref;
u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;
u32 timf_default;
u32 internal_clk;
u8 div_force_off : 1;
u8 div_state : 1;
u16 div_sync_wait;
u16 revision;
u8 agc_state;
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[4];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
};
enum dib7000m_power_mode {
DIB7000M_POWER_ALL = 0,
DIB7000M_POWER_NO,
DIB7000M_POWER_INTERF_ANALOG_AGC,
DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD,
DIB7000M_POWER_INTERFACE_ONLY,
};
static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
state->i2c_write_buffer[0] = (reg >> 8) | 0x80;
state->i2c_write_buffer[1] = reg & 0xff;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 2;
state->msg[1].addr = state->i2c_addr >> 1;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
dprintk("i2c read error on %d\n", reg);
ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
state->i2c_write_buffer[1] = reg & 0xff;
state->i2c_write_buffer[2] = (val >> 8) & 0xff;
state->i2c_write_buffer[3] = val & 0xff;
memset(&state->msg[0], 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 4;
ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
-EREMOTEIO : 0);
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
{
u16 l = 0, r, *n;
n = buf;
l = *n++;
while (l) {
r = *n++;
if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC
r++;
do {
dib7000m_write_word(state, r, *n++);
r++;
} while (--l);
l = *n++;
}
}
static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
{
int ret = 0;
u16 outreg, fifo_threshold, smo_mode,
sram = 0x0005; /* by default SRAM output is disabled */
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
outreg = (1 << 10); /* 0x0400 */
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
outreg = (1 << 10) | (1 << 6); /* 0x0440 */
break;
case OUTMODE_MPEG2_SERIAL: // STBs with serial input
outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
break;
case OUTMODE_DIVERSITY:
if (state->cfg.hostbus_diversity)
outreg = (1 << 10) | (4 << 6); /* 0x0500 */
else
sram |= 0x0c00;
break;
case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
smo_mode |= (3 << 1);
fifo_threshold = 512;
outreg = (1 << 10) | (5 << 6);
break;
case OUTMODE_HIGH_Z: // disable
outreg = 0;
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
break;
}
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5) ;
ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode);
ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */
ret |= dib7000m_write_word(state, 1795, outreg);
ret |= dib7000m_write_word(state, 1805, sram);
if (state->revision == 0x4003) {
u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
if (mode == OUTMODE_DIVERSITY)
clk_cfg1 |= (1 << 1); // P_O_CLK_en
dib7000m_write_word(state, 909, clk_cfg1);
}
return ret;
}
static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode)
{
/* by default everything is going to be powered off */
u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff;
u8 offset = 0;
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
case DIB7000M_POWER_ALL:
reg_903 = 0x0000; reg_904 = 0x0000; reg_905 = 0x0000; reg_906 = 0x0000;
break;
/* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
case DIB7000M_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
break;
case DIB7000M_POWER_INTERF_ANALOG_AGC:
reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
reg_906 &= ~((1 << 0));
break;
case DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
reg_903 = 0x0000; reg_904 = 0x801f; reg_905 = 0x0000; reg_906 = 0x0000;
break;
case DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD:
reg_903 = 0x0000; reg_904 = 0x8000; reg_905 = 0x010b; reg_906 = 0x0000;
break;
case DIB7000M_POWER_NO:
break;
}
/* always power down unused parts */
if (!state->cfg.mobile_mode)
reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
/* P_sdio_select_clk = 0 on MC and after*/
if (state->revision != 0x4000)
reg_906 <<= 1;
if (state->revision == 0x4003)
offset = 1;
dib7000m_write_word(state, 903 + offset, reg_903);
dib7000m_write_word(state, 904 + offset, reg_904);
dib7000m_write_word(state, 905 + offset, reg_905);
dib7000m_write_word(state, 906 + offset, reg_906);
}
static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no)
{
int ret = 0;
u16 reg_913 = dib7000m_read_word(state, 913),
reg_914 = dib7000m_read_word(state, 914);
switch (no) {
case DIBX000_SLOW_ADC_ON:
reg_914 |= (1 << 1) | (1 << 0);
ret |= dib7000m_write_word(state, 914, reg_914);
reg_914 &= ~(1 << 1);
break;
case DIBX000_SLOW_ADC_OFF:
reg_914 |= (1 << 1) | (1 << 0);
break;
case DIBX000_ADC_ON:
if (state->revision == 0x4000) { // workaround for PA/MA
// power-up ADC
dib7000m_write_word(state, 913, 0);
dib7000m_write_word(state, 914, reg_914 & 0x3);
// power-down bandgag
dib7000m_write_word(state, 913, (1 << 15));
dib7000m_write_word(state, 914, reg_914 & 0x3);
}
reg_913 &= 0x0fff;
reg_914 &= 0x0003;
break;
case DIBX000_ADC_OFF: // leave the VBG voltage on
reg_913 |= (1 << 14) | (1 << 13) | (1 << 12);
reg_914 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
break;
case DIBX000_VBG_ENABLE:
reg_913 &= ~(1 << 15);
break;
case DIBX000_VBG_DISABLE:
reg_913 |= (1 << 15);
break;
default:
break;
}
// dprintk("913: %x, 914: %x\n", reg_913, reg_914);
ret |= dib7000m_write_word(state, 913, reg_913);
ret |= dib7000m_write_word(state, 914, reg_914);
return ret;
}
static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
{
u32 timf;
if (!bw)
bw = 8000;
// store the current bandwidth for later use
state->current_bandwidth = bw;
if (state->timf == 0) {
dprintk("using default timf\n");
timf = state->timf_default;
} else {
dprintk("using updated timf\n");
timf = state->timf;
}
timf = timf * (bw / 50) / 160;
dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
return 0;
}
static int dib7000m_set_diversity_in(struct dvb_frontend *demod, int onoff)
{
struct dib7000m_state *state = demod->demodulator_priv;
if (state->div_force_off) {
dprintk("diversity combination deactivated - forced by COFDM parameters\n");
onoff = 0;
}
state->div_state = (u8)onoff;
if (onoff) {
dib7000m_write_word(state, 263 + state->reg_offs, 6);
dib7000m_write_word(state, 264 + state->reg_offs, 6);
dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
} else {
dib7000m_write_word(state, 263 + state->reg_offs, 1);
dib7000m_write_word(state, 264 + state->reg_offs, 0);
dib7000m_write_word(state, 266 + state->reg_offs, 0);
}
return 0;
}
static int dib7000m_sad_calib(struct dib7000m_state *state)
{
/* internal */
// dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writing in set_bandwidth
dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
/* do the calibration */
dib7000m_write_word(state, 929, (1 << 0));
dib7000m_write_word(state, 929, (0 << 0));
msleep(1);
return 0;
}
static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
{
dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
dib7000m_write_word(state, 928, bw->sad_cfg);
}
static void dib7000m_reset_pll(struct dib7000m_state *state)
{
const struct dibx000_bandwidth_config *bw = state->cfg.bw;
u16 reg_907,reg_910;
/* default */
reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |
(bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |
(bw->enable_refdiv << 1) | (0 << 0);
reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
// for this oscillator frequency should be 30 MHz for the Master (default values in the board_parameters give that value)
// this is only working only for 30 MHz crystals
if (!state->cfg.quartz_direct) {
reg_910 |= (1 << 5); // forcing the predivider to 1
// if the previous front-end is baseband, its output frequency is 15 MHz (prev freq divided by 2)
if(state->cfg.input_clk_is_div_2)
reg_907 |= (16 << 9);
else // otherwise the previous front-end puts out its input (default 30MHz) - no extra division necessary
reg_907 |= (8 << 9);
} else {
reg_907 |= (bw->pll_ratio & 0x3f) << 9;
reg_910 |= (bw->pll_prediv << 5);
}
dib7000m_write_word(state, 910, reg_910); // pll cfg
dib7000m_write_word(state, 907, reg_907); // clk cfg0
dib7000m_write_word(state, 908, 0x0006); // clk_cfg1
dib7000m_reset_pll_common(state, bw);
}
static void dib7000mc_reset_pll(struct dib7000m_state *state)
{
const struct dibx000_bandwidth_config *bw = state->cfg.bw;
u16 clk_cfg1;
// clk_cfg0
dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
// clk_cfg1
//dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
clk_cfg1 = (0 << 14) | (3 << 12) |(0 << 11) |
(bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
(1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);
dib7000m_write_word(state, 908, clk_cfg1);
clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);
dib7000m_write_word(state, 908, clk_cfg1);
// smpl_cfg
dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
dib7000m_reset_pll_common(state, bw);
}
static int dib7000m_reset_gpio(struct dib7000m_state *st)
{
/* reset the GPIOs */
dib7000m_write_word(st, 773, st->cfg.gpio_dir);
dib7000m_write_word(st, 774, st->cfg.gpio_val);
/* TODO 782 is P_gpio_od */
dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos);
dib7000m_write_word(st, 780, st->cfg.pwm_freq_div);
return 0;
}
static u16 dib7000m_defaults_common[] =
{
// auto search configuration
3, 2,
0x0004,
0x1000,
0x0814,
12, 6,
0x001b,
0x7740,
0x005b,
0x8d80,
0x01c9,
0xc380,
0x0000,
0x0080,
0x0000,
0x0090,
0x0001,
0xd4c0,
1, 26,
0x6680, // P_corm_thres Lock algorithms configuration
1, 170,
0x0410, // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
8, 173,
0,
0,
0,
0,
0,
0,
0,
0,
1, 182,
8192, // P_fft_nb_to_cut
2, 195,
0x0ccd, // P_pha3_thres
0, // P_cti_use_cpe, P_cti_use_prog
1, 205,
0x200f, // P_cspu_regul, P_cspu_win_cut
5, 214,
0x023d, // P_adp_regul_cnt
0x00a4, // P_adp_noise_cnt
0x00a4, // P_adp_regul_ext
0x7ff0, // P_adp_noise_ext
0x3ccc, // P_adp_fil
1, 226,
0, // P_2d_byp_ti_num
1, 255,
0x800, // P_equal_thres_wgn
1, 263,
0x0001,
1, 281,
0x0010, // P_fec_*
1, 294,
0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
0
};
static u16 dib7000m_defaults[] =
{
/* set ADC level to -16 */
11, 76,
(1 << 13) - 825 - 117,
(1 << 13) - 837 - 117,
(1 << 13) - 811 - 117,
(1 << 13) - 766 - 117,
(1 << 13) - 737 - 117,
(1 << 13) - 693 - 117,
(1 << 13) - 648 - 117,
(1 << 13) - 619 - 117,
(1 << 13) - 575 - 117,
(1 << 13) - 531 - 117,
(1 << 13) - 501 - 117,
// Tuner IO bank: max drive (14mA)
1, 912,
0x2c8a,
1, 1817,
1,
0,
};
static int dib7000m_demod_reset(struct dib7000m_state *state)
{
dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
/* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE);
/* restart all parts */
dib7000m_write_word(state, 898, 0xffff);
dib7000m_write_word(state, 899, 0xffff);
dib7000m_write_word(state, 900, 0xff0f);
dib7000m_write_word(state, 901, 0xfffc);
dib7000m_write_word(state, 898, 0);
dib7000m_write_word(state, 899, 0);
dib7000m_write_word(state, 900, 0);
dib7000m_write_word(state, 901, 0);
if (state->revision == 0x4000)
dib7000m_reset_pll(state);
else
dib7000mc_reset_pll(state);
if (dib7000m_reset_gpio(state) != 0)
dprintk("GPIO reset was not successful.\n");
if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
dprintk("OUTPUT_MODE could not be reset.\n");
/* unforce divstr regardless whether i2c enumeration was done or not */
dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
dib7000m_set_bandwidth(state, 8000);
dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON);
dib7000m_sad_calib(state);
dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
if (state->cfg.dvbt_mode)
dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
if (state->cfg.mobile_mode)
dib7000m_write_word(state, 261 + state->reg_offs, 2);
else
dib7000m_write_word(state, 224 + state->reg_offs, 1);
// P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
if(state->cfg.tuner_is_baseband)
dib7000m_write_word(state, 36, 0x0755);
else
dib7000m_write_word(state, 36, 0x1f55);
// P_divclksel=3 P_divbitsel=1
if (state->revision == 0x4000)
dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
else
dib7000m_write_word(state, 909, (3 << 4) | 1);
dib7000m_write_tab(state, dib7000m_defaults_common);
dib7000m_write_tab(state, dib7000m_defaults);
dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY);
state->internal_clk = state->cfg.bw->internal;
return 0;
}
static void dib7000m_restart_agc(struct dib7000m_state *state)
{
// P_restart_iqc & P_restart_agc
dib7000m_write_word(state, 898, 0x0c00);
dib7000m_write_word(state, 898, 0x0000);
}
static int dib7000m_agc_soft_split(struct dib7000m_state *state)
{
u16 agc,split_offset;
if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
return 0;
// n_agc_global
agc = dib7000m_read_word(state, 390);
if (agc > state->current_agc->split.min_thres)
split_offset = state->current_agc->split.min;
else if (agc < state->current_agc->split.max_thres)
split_offset = state->current_agc->split.max;
else
split_offset = state->current_agc->split.max *
(agc - state->current_agc->split.min_thres) /
(state->current_agc->split.max_thres - state->current_agc->split.min_thres);
dprintk("AGC split_offset: %d\n", split_offset);
// P_agc_force_split and P_agc_split_offset
return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
}
static int dib7000m_update_lna(struct dib7000m_state *state)
{
u16 dyn_gain;
if (state->cfg.update_lna) {
// read dyn_gain here (because it is demod-dependent and not fe)
dyn_gain = dib7000m_read_word(state, 390);
if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
dib7000m_restart_agc(state);
return 1;
}
}
return 0;
}
static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
{
struct dibx000_agc_config *agc = NULL;
int i;
if (state->current_band == band && state->current_agc != NULL)
return 0;
state->current_band = band;
for (i = 0; i < state->cfg.agc_config_count; i++)
if (state->cfg.agc[i].band_caps & band) {
agc = &state->cfg.agc[i];
break;
}
if (agc == NULL) {
dprintk("no valid AGC configuration found for band 0x%02x\n", band);
return -EINVAL;
}
state->current_agc = agc;
/* AGC */
dib7000m_write_word(state, 72 , agc->setup);
dib7000m_write_word(state, 73 , agc->inv_gain);
dib7000m_write_word(state, 74 , agc->time_stabiliz);
dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock);
// Demod AGC loop configuration
dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
/* AGC continued */
if (state->wbd_ref != 0)
dib7000m_write_word(state, 102, state->wbd_ref);
else // use default
dib7000m_write_word(state, 102, agc->wbd_ref);
dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
dib7000m_write_word(state, 104, agc->agc1_max);
dib7000m_write_word(state, 105, agc->agc1_min);
dib7000m_write_word(state, 106, agc->agc2_max);
dib7000m_write_word(state, 107, agc->agc2_min);
dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
if (state->revision > 0x4000) { // settings for the MC
dib7000m_write_word(state, 71, agc->agc1_pt3);
// dprintk("929: %x %d %d\n",
// (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
} else {
// wrong default values
u16 b[9] = { 676, 696, 717, 737, 758, 778, 799, 819, 840 };
for (i = 0; i < 9; i++)
dib7000m_write_word(state, 88 + i, b[i]);
}
return 0;
}
static void dib7000m_update_timf(struct dib7000m_state *state)
{
u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
state->timf = timf * 160 / (state->current_bandwidth / 50);
dib7000m_write_word(state, 23, (u16) (timf >> 16));
dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->timf_default);
}
static int dib7000m_agc_startup(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000m_state *state = demod->demodulator_priv;
u16 cfg_72 = dib7000m_read_word(state, 72);
int ret = -1;
u8 *agc_state = &state->agc_state;
u8 agc_split;
switch (state->agc_state) {
case 0:
// set power-up level: interf+analog+AGC
dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
dib7000m_set_adc_state(state, DIBX000_ADC_ON);
if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
return -1;
ret = 7; /* ADC power up */
(*agc_state)++;
break;
case 1:
/* AGC initialization */
if (state->cfg.agc_control)
state->cfg.agc_control(&state->demod, 1);
dib7000m_write_word(state, 75, 32768);
if (!state->current_agc->perform_agc_softsplit) {
/* we are using the wbd - so slow AGC startup */
dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
(*agc_state)++;
ret = 5;
} else {
/* default AGC startup */
(*agc_state) = 4;
/* wait AGC rough lock time */
ret = 7;
}
dib7000m_restart_agc(state);
break;
case 2: /* fast split search path after 5sec */
dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
(*agc_state)++;
ret = 14;
break;
case 3: /* split search ended */
agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
dib7000m_restart_agc(state);
dprintk("SPLIT %p: %u\n", demod, agc_split);
(*agc_state)++;
ret = 5;
break;
case 4: /* LNA startup */
/* wait AGC accurate lock time */
ret = 7;
if (dib7000m_update_lna(state))
// wait only AGC rough lock time
ret = 5;
else
(*agc_state)++;
break;
case 5:
dib7000m_agc_soft_split(state);
if (state->cfg.agc_control)
state->cfg.agc_control(&state->demod, 0);
(*agc_state)++;
break;
default:
break;
}
return ret;
}
static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch,
u8 seq)
{
u16 value, est[4];
dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
/* nfft, guard, qam, alpha */
value = 0;
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
case TRANSMISSION_MODE_4K: value |= (2 << 7); break;
default:
case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
default:
case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
}
switch (ch->modulation) {
case QPSK: value |= (0 << 3); break;
case QAM_16: value |= (1 << 3); break;
default:
case QAM_64: value |= (2 << 3); break;
}
switch (HIERARCHY_1) {
case HIERARCHY_2: value |= 2; break;
case HIERARCHY_4: value |= 4; break;
default:
case HIERARCHY_1: value |= 1; break;
}
dib7000m_write_word(state, 0, value);
dib7000m_write_word(state, 5, (seq << 4));
/* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
value = 0;
if (1 != 0)
value |= (1 << 6);
if (ch->hierarchy == 1)
value |= (1 << 4);
if (1 == 1)
value |= 1;
switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
case FEC_2_3: value |= (2 << 1); break;
case FEC_3_4: value |= (3 << 1); break;
case FEC_5_6: value |= (5 << 1); break;
case FEC_7_8: value |= (7 << 1); break;
default:
case FEC_1_2: value |= (1 << 1); break;
}
dib7000m_write_word(state, 267 + state->reg_offs, value);
/* offset loop parameters */
/* P_timf_alpha = 6, P_corm_alpha=6, P_corm_thres=0x80 */
dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80);
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=1, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3));
/* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max=3 */
dib7000m_write_word(state, 32, (0 << 4) | 0x3);
/* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step=5 */
dib7000m_write_word(state, 33, (0 << 4) | 0x5);
/* P_dvsy_sync_wait */
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_8K: value = 256; break;
case TRANSMISSION_MODE_4K: value = 128; break;
case TRANSMISSION_MODE_2K:
default: value = 64; break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_16: value *= 2; break;
case GUARD_INTERVAL_1_8: value *= 4; break;
case GUARD_INTERVAL_1_4: value *= 8; break;
default:
case GUARD_INTERVAL_1_32: value *= 1; break;
}
state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
/* deactivate the possibility of diversity reception if extended interleave - not for 7000MC */
/* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
if (1 == 1 || state->revision > 0x4000)
state->div_force_off = 0;
else
state->div_force_off = 1;
dib7000m_set_diversity_in(&state->demod, state->div_state);
/* channel estimation fine configuration */
switch (ch->modulation) {
case QAM_64:
est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
break;
case QAM_16:
est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
break;
default:
est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
break;
}
for (value = 0; value < 4; value++)
dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
// set power-up level: autosearch
dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
}
static int dib7000m_autosearch_start(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000m_state *state = demod->demodulator_priv;
struct dtv_frontend_properties schan;
int ret = 0;
u32 value, factor;
schan = *ch;
schan.modulation = QAM_64;
schan.guard_interval = GUARD_INTERVAL_1_32;
schan.transmission_mode = TRANSMISSION_MODE_8K;
schan.code_rate_HP = FEC_2_3;
schan.code_rate_LP = FEC_3_4;
schan.hierarchy = 0;
dib7000m_set_channel(state, &schan, 7);
factor = BANDWIDTH_TO_KHZ(schan.bandwidth_hz);
if (factor >= 5000)
factor = 1;
else
factor = 6;
// always use the setting for 8MHz here lock_time for 7,6 MHz are longer
value = 30 * state->internal_clk * factor;
ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
value = 100 * state->internal_clk * factor;
ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
value = 500 * state->internal_clk * factor;
ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
// start search
value = dib7000m_read_word(state, 0);
ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
/* clear n_irq_pending */
if (state->revision == 0x4000)
dib7000m_write_word(state, 1793, 0);
else
dib7000m_read_word(state, 537);
ret |= dib7000m_write_word(state, 0, (u16) value);
return ret;
}
static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg)
{
u16 irq_pending = dib7000m_read_word(state, reg);
if (irq_pending & 0x1) { // failed
dprintk("autosearch failed\n");
return 1;
}
if (irq_pending & 0x2) { // succeeded
dprintk("autosearch succeeded\n");
return 2;
}
return 0; // still pending
}
static int dib7000m_autosearch_is_irq(struct dvb_frontend *demod)
{
struct dib7000m_state *state = demod->demodulator_priv;
if (state->revision == 0x4000)
return dib7000m_autosearch_irq(state, 1793);
else
return dib7000m_autosearch_irq(state, 537);
}
static int dib7000m_tune(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000m_state *state = demod->demodulator_priv;
int ret = 0;
u16 value;
// we are already tuned - just resuming from suspend
dib7000m_set_channel(state, ch, 0);
// restart demod
ret |= dib7000m_write_word(state, 898, 0x4000);
ret |= dib7000m_write_word(state, 898, 0x0000);
msleep(45);
dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD);
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
// never achieved a lock before - wait for timfreq to update
if (state->timf == 0)
msleep(200);
//dump_reg(state);
/* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
value = (6 << 8) | 0x80;
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K: value |= (7 << 12); break;
case TRANSMISSION_MODE_4K: value |= (8 << 12); break;
default:
case TRANSMISSION_MODE_8K: value |= (9 << 12); break;
}
ret |= dib7000m_write_word(state, 26, value);
/* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
value = (0 << 4);
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K: value |= 0x6; break;
case TRANSMISSION_MODE_4K: value |= 0x7; break;
default:
case TRANSMISSION_MODE_8K: value |= 0x8; break;
}
ret |= dib7000m_write_word(state, 32, value);
/* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
value = (0 << 4);
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K: value |= 0x6; break;
case TRANSMISSION_MODE_4K: value |= 0x7; break;
default:
case TRANSMISSION_MODE_8K: value |= 0x8; break;
}
ret |= dib7000m_write_word(state, 33, value);
// we achieved a lock - it's time to update the timf freq
if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
dib7000m_update_timf(state);
dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
return ret;
}
static int dib7000m_wakeup(struct dvb_frontend *demod)
{
struct dib7000m_state *state = demod->demodulator_priv;
dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
dprintk("could not start Slow ADC\n");
return 0;
}
static int dib7000m_sleep(struct dvb_frontend *demod)
{
struct dib7000m_state *st = demod->demodulator_priv;
dib7000m_set_output_mode(st, OUTMODE_HIGH_Z);
dib7000m_set_power_mode(st, DIB7000M_POWER_INTERFACE_ONLY);
return dib7000m_set_adc_state(st, DIBX000_SLOW_ADC_OFF) |
dib7000m_set_adc_state(st, DIBX000_ADC_OFF);
}
static int dib7000m_identify(struct dib7000m_state *state)
{
u16 value;
if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
dprintk("wrong Vendor ID (0x%x)\n", value);
return -EREMOTEIO;
}
state->revision = dib7000m_read_word(state, 897);
if (state->revision != 0x4000 &&
state->revision != 0x4001 &&
state->revision != 0x4002 &&
state->revision != 0x4003) {
dprintk("wrong Device ID (0x%x)\n", value);
return -EREMOTEIO;
}
/* protect this driver to be used with 7000PC */
if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
dprintk("this driver does not work with DiB7000PC\n");
return -EREMOTEIO;
}
switch (state->revision) {
case 0x4000: dprintk("found DiB7000MA/PA/MB/PB\n"); break;
case 0x4001: state->reg_offs = 1; dprintk("found DiB7000HC\n"); break;
case 0x4002: state->reg_offs = 1; dprintk("found DiB7000MC\n"); break;
case 0x4003: state->reg_offs = 1; dprintk("found DiB9000\n"); break;
}
return 0;
}
static int dib7000m_get_frontend(struct dvb_frontend* fe,
struct dtv_frontend_properties *fep)
{
struct dib7000m_state *state = fe->demodulator_priv;
u16 tps = dib7000m_read_word(state,480);
fep->inversion = INVERSION_AUTO;
fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
switch ((tps >> 8) & 0x3) {
case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
/* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
}
switch (tps & 0x3) {
case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
}
switch ((tps >> 14) & 0x3) {
case 0: fep->modulation = QPSK; break;
case 1: fep->modulation = QAM_16; break;
case 2:
default: fep->modulation = QAM_64; break;
}
/* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
/* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
fep->hierarchy = HIERARCHY_NONE;
switch ((tps >> 5) & 0x7) {
case 1: fep->code_rate_HP = FEC_1_2; break;
case 2: fep->code_rate_HP = FEC_2_3; break;
case 3: fep->code_rate_HP = FEC_3_4; break;
case 5: fep->code_rate_HP = FEC_5_6; break;
case 7:
default: fep->code_rate_HP = FEC_7_8; break;
}
switch ((tps >> 2) & 0x7) {
case 1: fep->code_rate_LP = FEC_1_2; break;
case 2: fep->code_rate_LP = FEC_2_3; break;
case 3: fep->code_rate_LP = FEC_3_4; break;
case 5: fep->code_rate_LP = FEC_5_6; break;
case 7:
default: fep->code_rate_LP = FEC_7_8; break;
}
/* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
return 0;
}
static int dib7000m_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
struct dib7000m_state *state = fe->demodulator_priv;
int time, ret;
dib7000m_set_output_mode(state, OUTMODE_HIGH_Z);
dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* start up the AGC */
state->agc_state = 0;
do {
time = dib7000m_agc_startup(fe);
if (time != -1)
msleep(time);
} while (time != -1);
if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
fep->guard_interval == GUARD_INTERVAL_AUTO ||
fep->modulation == QAM_AUTO ||
fep->code_rate_HP == FEC_AUTO) {
int i = 800, found;
dib7000m_autosearch_start(fe);
do {
msleep(1);
found = dib7000m_autosearch_is_irq(fe);
} while (found == 0 && i--);
dprintk("autosearch returns: %d\n", found);
if (found == 0 || found == 1)
return 0; // no channel found
dib7000m_get_frontend(fe, fep);
}
ret = dib7000m_tune(fe);
/* make this a config parameter */
dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
return ret;
}
static int dib7000m_read_status(struct dvb_frontend *fe, enum fe_status *stat)
{
struct dib7000m_state *state = fe->demodulator_priv;
u16 lock = dib7000m_read_word(state, 535);
*stat = 0;
if (lock & 0x8000)
*stat |= FE_HAS_SIGNAL;
if (lock & 0x3000)
*stat |= FE_HAS_CARRIER;
if (lock & 0x0100)
*stat |= FE_HAS_VITERBI;
if (lock & 0x0010)
*stat |= FE_HAS_SYNC;
if (lock & 0x0008)
*stat |= FE_HAS_LOCK;
return 0;
}
static int dib7000m_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct dib7000m_state *state = fe->demodulator_priv;
*ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
return 0;
}
static int dib7000m_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
{
struct dib7000m_state *state = fe->demodulator_priv;
*unc = dib7000m_read_word(state, 534);
return 0;
}
static int dib7000m_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct dib7000m_state *state = fe->demodulator_priv;
u16 val = dib7000m_read_word(state, 390);
*strength = 65535 - val;
return 0;
}
static int dib7000m_read_snr(struct dvb_frontend* fe, u16 *snr)
{
*snr = 0x0000;
return 0;
}
static int dib7000m_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void dib7000m_release(struct dvb_frontend *demod)
{
struct dib7000m_state *st = demod->demodulator_priv;
dibx000_exit_i2c_master(&st->i2c_master);
kfree(st);
}
struct i2c_adapter * dib7000m_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
{
struct dib7000m_state *st = demod->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
}
EXPORT_SYMBOL(dib7000m_get_i2c_master);
int dib7000m_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib7000m_state *state = fe->demodulator_priv;
u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef;
val |= (onoff & 0x1) << 4;
dprintk("PID filter enabled %d\n", onoff);
return dib7000m_write_word(state, 294 + state->reg_offs, val);
}
EXPORT_SYMBOL(dib7000m_pid_filter_ctrl);
int dib7000m_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib7000m_state *state = fe->demodulator_priv;
dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff);
return dib7000m_write_word(state, 300 + state->reg_offs + id,
onoff ? (1 << 13) | pid : 0);
}
EXPORT_SYMBOL(dib7000m_pid_filter);
#if 0
/* used with some prototype boards */
int dib7000m_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods,
u8 default_addr, struct dib7000m_config cfg[])
{
struct dib7000m_state st = { .i2c_adap = i2c };
int k = 0;
u8 new_addr = 0;
for (k = no_of_demods-1; k >= 0; k--) {
st.cfg = cfg[k];
/* designated i2c address */
new_addr = (0x40 + k) << 1;
st.i2c_addr = new_addr;
if (dib7000m_identify(&st) != 0) {
st.i2c_addr = default_addr;
if (dib7000m_identify(&st) != 0) {
dprintk("DiB7000M #%d: not identified\n", k);
return -EIO;
}
}
/* start diversity to pull_down div_str - just for i2c-enumeration */
dib7000m_set_output_mode(&st, OUTMODE_DIVERSITY);
dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
/* set new i2c address and force divstart */
dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
}
for (k = 0; k < no_of_demods; k++) {
st.cfg = cfg[k];
st.i2c_addr = (0x40 + k) << 1;
// unforce divstr
dib7000m_write_word(&st,1794, st.i2c_addr << 2);
/* deactivate div - it was just for i2c-enumeration */
dib7000m_set_output_mode(&st, OUTMODE_HIGH_Z);
}
return 0;
}
EXPORT_SYMBOL(dib7000m_i2c_enumeration);
#endif
static const struct dvb_frontend_ops dib7000m_ops;
struct dvb_frontend * dib7000m_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000m_config *cfg)
{
struct dvb_frontend *demod;
struct dib7000m_state *st;
st = kzalloc(sizeof(struct dib7000m_state), GFP_KERNEL);
if (st == NULL)
return NULL;
memcpy(&st->cfg, cfg, sizeof(struct dib7000m_config));
st->i2c_adap = i2c_adap;
st->i2c_addr = i2c_addr;
demod = &st->demod;
demod->demodulator_priv = st;
memcpy(&st->demod.ops, &dib7000m_ops, sizeof(struct dvb_frontend_ops));
mutex_init(&st->i2c_buffer_lock);
st->timf_default = cfg->bw->timf;
if (dib7000m_identify(st) != 0)
goto error;
if (st->revision == 0x4000)
dibx000_init_i2c_master(&st->i2c_master, DIB7000, st->i2c_adap, st->i2c_addr);
else
dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c_adap, st->i2c_addr);
dib7000m_demod_reset(st);
return demod;
error:
kfree(st);
return NULL;
}
EXPORT_SYMBOL_GPL(dib7000m_attach);
static const struct dvb_frontend_ops dib7000m_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 7000MA/MB/PA/PB/MC",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = dib7000m_release,
.init = dib7000m_wakeup,
.sleep = dib7000m_sleep,
.set_frontend = dib7000m_set_frontend,
.get_tune_settings = dib7000m_fe_get_tune_settings,
.get_frontend = dib7000m_get_frontend,
.read_status = dib7000m_read_status,
.read_ber = dib7000m_read_ber,
.read_signal_strength = dib7000m_read_signal_strength,
.read_snr = dib7000m_read_snr,
.read_ucblocks = dib7000m_read_unc_blocks,
};
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 7000MA/MB/PA/PB/MC COFDM demodulator");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib7000m.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lnbp22.h - driver for lnb supply and control ic lnbp22
*
* Copyright (C) 2006 Dominik Kuhlen
* Based on lnbp21 driver
*
* the project's page is at https://linuxtv.org
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "lnbp22.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(lvl, arg...) if (debug >= (lvl)) printk(arg)
struct lnbp22 {
u8 config[4];
struct i2c_adapter *i2c;
};
static int lnbp22_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct lnbp22 *lnbp22 = (struct lnbp22 *)fe->sec_priv;
struct i2c_msg msg = {
.addr = 0x08,
.flags = 0,
.buf = (char *)&lnbp22->config,
.len = sizeof(lnbp22->config),
};
dprintk(1, "%s: %d (18V=%d 13V=%d)\n", __func__, voltage,
SEC_VOLTAGE_18, SEC_VOLTAGE_13);
lnbp22->config[3] = 0x60; /* Power down */
switch (voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
lnbp22->config[3] |= LNBP22_EN;
break;
case SEC_VOLTAGE_18:
lnbp22->config[3] |= (LNBP22_EN | LNBP22_VSEL);
break;
default:
return -EINVAL;
}
dprintk(1, "%s: 0x%02x)\n", __func__, lnbp22->config[3]);
return (i2c_transfer(lnbp22->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int lnbp22_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct lnbp22 *lnbp22 = (struct lnbp22 *) fe->sec_priv;
struct i2c_msg msg = {
.addr = 0x08,
.flags = 0,
.buf = (char *)&lnbp22->config,
.len = sizeof(lnbp22->config),
};
dprintk(1, "%s: %d\n", __func__, (int)arg);
if (arg)
lnbp22->config[3] |= LNBP22_LLC;
else
lnbp22->config[3] &= ~LNBP22_LLC;
return (i2c_transfer(lnbp22->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static void lnbp22_release(struct dvb_frontend *fe)
{
dprintk(1, "%s\n", __func__);
/* LNBP power off */
lnbp22_set_voltage(fe, SEC_VOLTAGE_OFF);
/* free data */
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *lnbp22_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c)
{
struct lnbp22 *lnbp22 = kmalloc(sizeof(struct lnbp22), GFP_KERNEL);
if (!lnbp22)
return NULL;
/* default configuration */
lnbp22->config[0] = 0x00; /* ? */
lnbp22->config[1] = 0x28; /* ? */
lnbp22->config[2] = 0x48; /* ? */
lnbp22->config[3] = 0x60; /* Power down */
lnbp22->i2c = i2c;
fe->sec_priv = lnbp22;
/* detect if it is present or not */
if (lnbp22_set_voltage(fe, SEC_VOLTAGE_OFF)) {
dprintk(0, "%s LNBP22 not found\n", __func__);
kfree(lnbp22);
fe->sec_priv = NULL;
return NULL;
}
/* install release callback */
fe->ops.release_sec = lnbp22_release;
/* override frontend ops */
fe->ops.set_voltage = lnbp22_set_voltage;
fe->ops.enable_high_lnb_voltage = lnbp22_enable_high_lnb_voltage;
return fe;
}
EXPORT_SYMBOL_GPL(lnbp22_attach);
MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp22");
MODULE_AUTHOR("Dominik Kuhlen");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/lnbp22.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Toshiba TC90522 Demodulator
*
* Copyright (C) 2014 Akihiro Tsukada <[email protected]>
*/
/*
* NOTICE:
* This driver is incomplete and lacks init/config of the chips,
* as the necessary info is not disclosed.
* It assumes that users of this driver (such as a PCI bridge of
* DTV receiver cards) properly init and configure the chip
* via I2C *before* calling this driver's init() function.
*
* Currently, PT3 driver is the only one that uses this driver,
* and contains init/config code in its firmware.
* Thus some part of the code might be dependent on PT3 specific config.
*/
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/dvb/frontend.h>
#include <linux/int_log.h>
#include "tc90522.h"
#define TC90522_I2C_THRU_REG 0xfe
#define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
struct tc90522_state {
struct tc90522_config cfg;
struct dvb_frontend fe;
struct i2c_client *i2c_client;
struct i2c_adapter tuner_i2c;
bool lna;
};
struct reg_val {
u8 reg;
u8 val;
};
static int
reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
{
int i, ret;
struct i2c_msg msg;
ret = 0;
msg.addr = state->i2c_client->addr;
msg.flags = 0;
msg.len = 2;
for (i = 0; i < num; i++) {
msg.buf = (u8 *)®s[i];
ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
if (ret == 0)
ret = -EIO;
if (ret < 0)
return ret;
}
return 0;
}
static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
{
struct i2c_msg msgs[2] = {
{
.addr = state->i2c_client->addr,
.flags = 0,
.buf = ®,
.len = 1,
},
{
.addr = state->i2c_client->addr,
.flags = I2C_M_RD,
.buf = val,
.len = len,
},
};
int ret;
ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret == ARRAY_SIZE(msgs))
ret = 0;
else if (ret >= 0)
ret = -EIO;
return ret;
}
static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
{
return container_of(c, struct tc90522_state, cfg);
}
static int tc90522s_set_tsid(struct dvb_frontend *fe)
{
struct reg_val set_tsid[] = {
{ 0x8f, 00 },
{ 0x90, 00 }
};
set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
}
static int tc90522t_set_layers(struct dvb_frontend *fe)
{
struct reg_val rv;
u8 laysel;
laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
rv.reg = 0x71;
rv.val = laysel;
return reg_write(fe->demodulator_priv, &rv, 1);
}
/* frontend ops */
static int tc90522s_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct tc90522_state *state;
int ret;
u8 reg;
state = fe->demodulator_priv;
ret = reg_read(state, 0xc3, ®, 1);
if (ret < 0)
return ret;
*status = 0;
if (reg & 0x80) /* input level under min ? */
return 0;
*status |= FE_HAS_SIGNAL;
if (reg & 0x60) /* carrier? */
return 0;
*status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
if (reg & 0x10)
return 0;
if (reg_read(state, 0xc5, ®, 1) < 0 || !(reg & 0x03))
return 0;
*status |= FE_HAS_LOCK;
return 0;
}
static int tc90522t_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct tc90522_state *state;
int ret;
u8 reg;
state = fe->demodulator_priv;
ret = reg_read(state, 0x96, ®, 1);
if (ret < 0)
return ret;
*status = 0;
if (reg & 0xe0) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
| FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
ret = reg_read(state, 0x80, ®, 1);
if (ret < 0)
return ret;
if (reg & 0xf0)
return 0;
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
if (reg & 0x0c)
return 0;
*status |= FE_HAS_SYNC | FE_HAS_VITERBI;
if (reg & 0x02)
return 0;
*status |= FE_HAS_LOCK;
return 0;
}
static const enum fe_code_rate fec_conv_sat[] = {
FEC_NONE, /* unused */
FEC_1_2, /* for BPSK */
FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
FEC_2_3, /* for 8PSK. (trellis code) */
};
static int tc90522s_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct tc90522_state *state;
struct dtv_fe_stats *stats;
int ret, i;
int layers;
u8 val[10];
u32 cndat;
state = fe->demodulator_priv;
c->delivery_system = SYS_ISDBS;
c->symbol_rate = 28860000;
layers = 0;
ret = reg_read(state, 0xe6, val, 5);
if (ret == 0) {
u8 v;
c->stream_id = val[0] << 8 | val[1];
/* high/single layer */
v = (val[2] & 0x70) >> 4;
c->modulation = (v == 7) ? PSK_8 : QPSK;
c->fec_inner = fec_conv_sat[v];
c->layer[0].fec = c->fec_inner;
c->layer[0].modulation = c->modulation;
c->layer[0].segment_count = val[3] & 0x3f; /* slots */
/* low layer */
v = (val[2] & 0x07);
c->layer[1].fec = fec_conv_sat[v];
if (v == 0) /* no low layer */
c->layer[1].segment_count = 0;
else
c->layer[1].segment_count = val[4] & 0x3f; /* slots */
/*
* actually, BPSK if v==1, but not defined in
* enum fe_modulation
*/
c->layer[1].modulation = QPSK;
layers = (v > 0) ? 2 : 1;
}
/* statistics */
stats = &c->strength;
stats->len = 0;
/* let the connected tuner set RSSI property cache */
if (fe->ops.tuner_ops.get_rf_strength) {
u16 dummy;
fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
}
stats = &c->cnr;
stats->len = 1;
stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
cndat = 0;
ret = reg_read(state, 0xbc, val, 2);
if (ret == 0)
cndat = val[0] << 8 | val[1];
if (cndat >= 3000) {
u32 p, p4;
s64 cn;
cndat -= 3000; /* cndat: 4.12 fixed point float */
/*
* cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
* + 88977 * P^2 - 89565 * P + 58857
* (P = sqrt(cndat) / 64)
*/
/* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */
/* cn = cnr << 3 */
p = int_sqrt(cndat << 16);
p4 = cndat * cndat;
cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
cn += (14341LL * p4) >> 21;
cn -= (50259LL * cndat * p) >> 23;
cn += (88977LL * cndat) >> 9;
cn -= (89565LL * p) >> 11;
cn += 58857 << 3;
stats->stat[0].svalue = cn >> 3;
stats->stat[0].scale = FE_SCALE_DECIBEL;
}
/* per-layer post viterbi BER (or PER? config dependent?) */
stats = &c->post_bit_error;
memset(stats, 0, sizeof(*stats));
stats->len = layers;
ret = reg_read(state, 0xeb, val, 10);
if (ret < 0)
for (i = 0; i < layers; i++)
stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
else {
for (i = 0; i < layers; i++) {
stats->stat[i].scale = FE_SCALE_COUNTER;
stats->stat[i].uvalue = val[i * 5] << 16
| val[i * 5 + 1] << 8 | val[i * 5 + 2];
}
}
stats = &c->post_bit_count;
memset(stats, 0, sizeof(*stats));
stats->len = layers;
if (ret < 0)
for (i = 0; i < layers; i++)
stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
else {
for (i = 0; i < layers; i++) {
stats->stat[i].scale = FE_SCALE_COUNTER;
stats->stat[i].uvalue =
val[i * 5 + 3] << 8 | val[i * 5 + 4];
stats->stat[i].uvalue *= 204 * 8;
}
}
return 0;
}
static const enum fe_transmit_mode tm_conv[] = {
TRANSMISSION_MODE_2K,
TRANSMISSION_MODE_4K,
TRANSMISSION_MODE_8K,
0
};
static const enum fe_code_rate fec_conv_ter[] = {
FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
};
static const enum fe_modulation mod_conv[] = {
DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
};
static int tc90522t_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct tc90522_state *state;
struct dtv_fe_stats *stats;
int ret, i;
int layers;
u8 val[15], mode;
u32 cndat;
state = fe->demodulator_priv;
c->delivery_system = SYS_ISDBT;
c->bandwidth_hz = 6000000;
mode = 1;
ret = reg_read(state, 0xb0, val, 1);
if (ret == 0) {
mode = (val[0] & 0xc0) >> 6;
c->transmission_mode = tm_conv[mode];
c->guard_interval = (val[0] & 0x30) >> 4;
}
ret = reg_read(state, 0xb2, val, 6);
layers = 0;
if (ret == 0) {
u8 v;
c->isdbt_partial_reception = val[0] & 0x01;
c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40;
/* layer A */
v = (val[2] & 0x78) >> 3;
if (v == 0x0f)
c->layer[0].segment_count = 0;
else {
layers++;
c->layer[0].segment_count = v;
c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
c->layer[0].interleaving = v;
}
/* layer B */
v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6;
if (v == 0x0f)
c->layer[1].segment_count = 0;
else {
layers++;
c->layer[1].segment_count = v;
c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
}
/* layer C */
v = (val[5] & 0x1e) >> 1;
if (v == 0x0f)
c->layer[2].segment_count = 0;
else {
layers++;
c->layer[2].segment_count = v;
c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
}
}
/* statistics */
stats = &c->strength;
stats->len = 0;
/* let the connected tuner set RSSI property cache */
if (fe->ops.tuner_ops.get_rf_strength) {
u16 dummy;
fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
}
stats = &c->cnr;
stats->len = 1;
stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
cndat = 0;
ret = reg_read(state, 0x8b, val, 3);
if (ret == 0)
cndat = val[0] << 16 | val[1] << 8 | val[2];
if (cndat != 0) {
u32 p, tmp;
s64 cn;
/*
* cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
* (P = 10log10(5505024/cndat))
*/
/* cn = cnr << 3 (61.3 fixed point float */
/* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/
p = intlog10(5505024) - intlog10(cndat);
p *= 10;
cn = 24772;
cn += div64_s64(43827LL * p, 10) >> 24;
tmp = p >> 8;
cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
tmp = p >> 13;
cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
tmp = p >> 18;
cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
stats->stat[0].svalue = cn >> 3;
stats->stat[0].scale = FE_SCALE_DECIBEL;
}
/* per-layer post viterbi BER (or PER? config dependent?) */
stats = &c->post_bit_error;
memset(stats, 0, sizeof(*stats));
stats->len = layers;
ret = reg_read(state, 0x9d, val, 15);
if (ret < 0)
for (i = 0; i < layers; i++)
stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
else {
for (i = 0; i < layers; i++) {
stats->stat[i].scale = FE_SCALE_COUNTER;
stats->stat[i].uvalue = val[i * 3] << 16
| val[i * 3 + 1] << 8 | val[i * 3 + 2];
}
}
stats = &c->post_bit_count;
memset(stats, 0, sizeof(*stats));
stats->len = layers;
if (ret < 0)
for (i = 0; i < layers; i++)
stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
else {
for (i = 0; i < layers; i++) {
stats->stat[i].scale = FE_SCALE_COUNTER;
stats->stat[i].uvalue =
val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
stats->stat[i].uvalue *= 204 * 8;
}
}
return 0;
}
static const struct reg_val reset_sat = { 0x03, 0x01 };
static const struct reg_val reset_ter = { 0x01, 0x40 };
static int tc90522_set_frontend(struct dvb_frontend *fe)
{
struct tc90522_state *state;
int ret;
state = fe->demodulator_priv;
if (fe->ops.tuner_ops.set_params)
ret = fe->ops.tuner_ops.set_params(fe);
else
ret = -ENODEV;
if (ret < 0)
goto failed;
if (fe->ops.delsys[0] == SYS_ISDBS) {
ret = tc90522s_set_tsid(fe);
if (ret < 0)
goto failed;
ret = reg_write(state, &reset_sat, 1);
} else {
ret = tc90522t_set_layers(fe);
if (ret < 0)
goto failed;
ret = reg_write(state, &reset_ter, 1);
}
if (ret < 0)
goto failed;
return 0;
failed:
dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
static int tc90522_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *settings)
{
if (fe->ops.delsys[0] == SYS_ISDBS) {
settings->min_delay_ms = 250;
settings->step_size = 1000;
settings->max_drift = settings->step_size * 2;
} else {
settings->min_delay_ms = 400;
settings->step_size = 142857;
settings->max_drift = settings->step_size;
}
return 0;
}
static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
{
struct reg_val agc_sat[] = {
{ 0x0a, 0x00 },
{ 0x10, 0x30 },
{ 0x11, 0x00 },
{ 0x03, 0x01 },
};
struct reg_val agc_ter[] = {
{ 0x25, 0x00 },
{ 0x23, 0x4c },
{ 0x01, 0x40 },
};
struct tc90522_state *state;
struct reg_val *rv;
int num;
state = fe->demodulator_priv;
if (fe->ops.delsys[0] == SYS_ISDBS) {
agc_sat[0].val = on ? 0xff : 0x00;
agc_sat[1].val |= 0x80;
agc_sat[1].val |= on ? 0x01 : 0x00;
agc_sat[2].val |= on ? 0x40 : 0x00;
rv = agc_sat;
num = ARRAY_SIZE(agc_sat);
} else {
agc_ter[0].val = on ? 0x40 : 0x00;
agc_ter[1].val |= on ? 0x00 : 0x01;
rv = agc_ter;
num = ARRAY_SIZE(agc_ter);
}
return reg_write(state, rv, num);
}
static const struct reg_val sleep_sat = { 0x17, 0x01 };
static const struct reg_val sleep_ter = { 0x03, 0x90 };
static int tc90522_sleep(struct dvb_frontend *fe)
{
struct tc90522_state *state;
int ret;
state = fe->demodulator_priv;
if (fe->ops.delsys[0] == SYS_ISDBS)
ret = reg_write(state, &sleep_sat, 1);
else {
ret = reg_write(state, &sleep_ter, 1);
if (ret == 0 && fe->ops.set_lna &&
fe->dtv_property_cache.lna == LNA_AUTO) {
fe->dtv_property_cache.lna = 0;
ret = fe->ops.set_lna(fe);
fe->dtv_property_cache.lna = LNA_AUTO;
}
}
if (ret < 0)
dev_warn(&state->tuner_i2c.dev,
"(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
static const struct reg_val wakeup_sat = { 0x17, 0x00 };
static const struct reg_val wakeup_ter = { 0x03, 0x80 };
static int tc90522_init(struct dvb_frontend *fe)
{
struct tc90522_state *state;
int ret;
/*
* Because the init sequence is not public,
* the parent device/driver should have init'ed the device before.
* just wake up the device here.
*/
state = fe->demodulator_priv;
if (fe->ops.delsys[0] == SYS_ISDBS)
ret = reg_write(state, &wakeup_sat, 1);
else {
ret = reg_write(state, &wakeup_ter, 1);
if (ret == 0 && fe->ops.set_lna &&
fe->dtv_property_cache.lna == LNA_AUTO) {
fe->dtv_property_cache.lna = 1;
ret = fe->ops.set_lna(fe);
fe->dtv_property_cache.lna = LNA_AUTO;
}
}
if (ret < 0) {
dev_warn(&state->tuner_i2c.dev,
"(%s) failed. [adap%d-fe%d]\n",
__func__, fe->dvb->num, fe->id);
return ret;
}
/* prefer 'all-layers' to 'none' as a default */
if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
fe->dtv_property_cache.isdbt_layer_enabled = 7;
return tc90522_set_if_agc(fe, true);
}
/*
* tuner I2C adapter functions
*/
static int
tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct tc90522_state *state;
struct i2c_msg *new_msgs;
int i, j;
int ret, rd_num;
u8 wbuf[256];
u8 *p, *bufend;
if (num <= 0)
return -EINVAL;
rd_num = 0;
for (i = 0; i < num; i++)
if (msgs[i].flags & I2C_M_RD)
rd_num++;
new_msgs = kmalloc_array(num + rd_num, sizeof(*new_msgs), GFP_KERNEL);
if (!new_msgs)
return -ENOMEM;
state = i2c_get_adapdata(adap);
p = wbuf;
bufend = wbuf + sizeof(wbuf);
for (i = 0, j = 0; i < num; i++, j++) {
new_msgs[j].addr = state->i2c_client->addr;
new_msgs[j].flags = msgs[i].flags;
if (msgs[i].flags & I2C_M_RD) {
new_msgs[j].flags &= ~I2C_M_RD;
if (p + 2 > bufend)
break;
p[0] = TC90522_I2C_THRU_REG;
p[1] = msgs[i].addr << 1 | 0x01;
new_msgs[j].buf = p;
new_msgs[j].len = 2;
p += 2;
j++;
new_msgs[j].addr = state->i2c_client->addr;
new_msgs[j].flags = msgs[i].flags;
new_msgs[j].buf = msgs[i].buf;
new_msgs[j].len = msgs[i].len;
continue;
}
if (p + msgs[i].len + 2 > bufend)
break;
p[0] = TC90522_I2C_THRU_REG;
p[1] = msgs[i].addr << 1;
memcpy(p + 2, msgs[i].buf, msgs[i].len);
new_msgs[j].buf = p;
new_msgs[j].len = msgs[i].len + 2;
p += new_msgs[j].len;
}
if (i < num) {
ret = -ENOMEM;
} else if (!state->cfg.split_tuner_read_i2c || rd_num == 0) {
ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
} else {
/*
* Split transactions at each I2C_M_RD message.
* Some of the parent device require this,
* such as Friio (see. dvb-usb-gl861).
*/
int from, to;
ret = 0;
from = 0;
do {
int r;
to = from + 1;
while (to < j && !(new_msgs[to].flags & I2C_M_RD))
to++;
r = i2c_transfer(state->i2c_client->adapter,
&new_msgs[from], to - from);
ret = (r <= 0) ? r : ret + r;
from = to;
} while (from < j && ret > 0);
}
if (ret >= 0 && ret < j)
ret = -EIO;
kfree(new_msgs);
return (ret == j) ? num : ret;
}
static u32 tc90522_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
.master_xfer = &tc90522_master_xfer,
.functionality = &tc90522_functionality,
};
/*
* I2C driver functions
*/
static const struct dvb_frontend_ops tc90522_ops_sat = {
.delsys = { SYS_ISDBS },
.info = {
.name = "Toshiba TC90522 ISDB-S module",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
},
.init = tc90522_init,
.sleep = tc90522_sleep,
.set_frontend = tc90522_set_frontend,
.get_tune_settings = tc90522_get_tune_settings,
.get_frontend = tc90522s_get_frontend,
.read_status = tc90522s_read_status,
};
static const struct dvb_frontend_ops tc90522_ops_ter = {
.delsys = { SYS_ISDBT },
.info = {
.name = "Toshiba TC90522 ISDB-T module",
.frequency_min_hz = 470 * MHz,
.frequency_max_hz = 770 * MHz,
.frequency_stepsize_hz = 142857,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.init = tc90522_init,
.sleep = tc90522_sleep,
.set_frontend = tc90522_set_frontend,
.get_tune_settings = tc90522_get_tune_settings,
.get_frontend = tc90522t_get_frontend,
.read_status = tc90522t_read_status,
};
static int tc90522_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct tc90522_state *state;
struct tc90522_config *cfg;
const struct dvb_frontend_ops *ops;
struct i2c_adapter *adap;
int ret;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
state->i2c_client = client;
cfg = client->dev.platform_data;
memcpy(&state->cfg, cfg, sizeof(state->cfg));
cfg->fe = state->cfg.fe = &state->fe;
ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
memcpy(&state->fe.ops, ops, sizeof(*ops));
state->fe.demodulator_priv = state;
adap = &state->tuner_i2c;
adap->owner = THIS_MODULE;
adap->algo = &tc90522_tuner_i2c_algo;
adap->dev.parent = &client->dev;
strscpy(adap->name, "tc90522_sub", sizeof(adap->name));
i2c_set_adapdata(adap, state);
ret = i2c_add_adapter(adap);
if (ret < 0)
goto free_state;
cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
i2c_set_clientdata(client, &state->cfg);
dev_info(&client->dev, "Toshiba TC90522 attached.\n");
return 0;
free_state:
kfree(state);
return ret;
}
static void tc90522_remove(struct i2c_client *client)
{
struct tc90522_state *state;
state = cfg_to_state(i2c_get_clientdata(client));
i2c_del_adapter(&state->tuner_i2c);
kfree(state);
}
static const struct i2c_device_id tc90522_id[] = {
{ TC90522_I2C_DEV_SAT, 0 },
{ TC90522_I2C_DEV_TER, 1 },
{}
};
MODULE_DEVICE_TABLE(i2c, tc90522_id);
static struct i2c_driver tc90522_driver = {
.driver = {
.name = "tc90522",
},
.probe = tc90522_probe,
.remove = tc90522_remove,
.id_table = tc90522_id,
};
module_i2c_driver(tc90522_driver);
MODULE_DESCRIPTION("Toshiba TC90522 frontend");
MODULE_AUTHOR("Akihiro TSUKADA");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tc90522.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
*
* Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
*
* This code is more or less generated from another driver, please
* excuse some codingstyle oddities.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <media/dvb_frontend.h>
#include "dib0070.h"
#include "dibx000_common.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
#define DIB0070_P1D 0x00
#define DIB0070_P1F 0x01
#define DIB0070_P1G 0x03
#define DIB0070S_P1A 0x02
struct dib0070_state {
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
const struct dib0070_config *cfg;
u16 wbd_ff_offset;
u8 revision;
enum frontend_tune_state tune_state;
u32 current_rf;
/* for the captrim binary search */
s8 step;
u16 adc_diff;
s8 captrim;
s8 fcaptrim;
u16 lo4;
const struct dib0070_tuning *current_tune_table_index;
const struct dib0070_lna_match *lna_match;
u8 wbd_gain_current;
u16 wbd_offset_3_3[2];
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[3];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
};
static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
state->i2c_write_buffer[0] = reg;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->cfg->i2c_address;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 1;
state->msg[1].addr = state->cfg->i2c_address;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
pr_warn("DiB0070 I2C read failed\n");
ret = 0;
} else
ret = (state->i2c_read_buffer[0] << 8)
| state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = reg;
state->i2c_write_buffer[1] = val >> 8;
state->i2c_write_buffer[2] = val & 0xff;
memset(state->msg, 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->cfg->i2c_address;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 3;
if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
pr_warn("DiB0070 I2C write failed\n");
ret = -EREMOTEIO;
} else
ret = 0;
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
#define HARD_RESET(state) do { \
state->cfg->sleep(state->fe, 0); \
if (state->cfg->reset) { \
state->cfg->reset(state->fe,1); msleep(10); \
state->cfg->reset(state->fe,0); msleep(10); \
} \
} while (0)
static int dib0070_set_bandwidth(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
tmp |= (0 << 14);
else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
tmp |= (1 << 14);
else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
tmp |= (2 << 14);
else
tmp |= (3 << 14);
dib0070_write_reg(state, 0x02, tmp);
/* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
u16 value = dib0070_read_reg(state, 0x17);
dib0070_write_reg(state, 0x17, value & 0xfffc);
tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
dib0070_write_reg(state, 0x01, tmp | (60 << 9));
dib0070_write_reg(state, 0x17, value);
}
return 0;
}
static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
{
int8_t step_sign;
u16 adc;
int ret = 0;
if (*tune_state == CT_TUNER_STEP_0) {
dib0070_write_reg(state, 0x0f, 0xed10);
dib0070_write_reg(state, 0x17, 0x0034);
dib0070_write_reg(state, 0x18, 0x0032);
state->step = state->captrim = state->fcaptrim = 64;
state->adc_diff = 3000;
ret = 20;
*tune_state = CT_TUNER_STEP_1;
} else if (*tune_state == CT_TUNER_STEP_1) {
state->step /= 2;
dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
ret = 15;
*tune_state = CT_TUNER_STEP_2;
} else if (*tune_state == CT_TUNER_STEP_2) {
adc = dib0070_read_reg(state, 0x19);
dprintk("CAPTRIM=%d; ADC = %hd (ADC) & %dmV\n", state->captrim,
adc, (u32)adc * (u32)1800 / (u32)1024);
if (adc >= 400) {
adc -= 400;
step_sign = -1;
} else {
adc = 400 - adc;
step_sign = 1;
}
if (adc < state->adc_diff) {
dprintk("CAPTRIM=%d is closer to target (%hd/%hd)\n",
state->captrim, adc, state->adc_diff);
state->adc_diff = adc;
state->fcaptrim = state->captrim;
}
state->captrim += (step_sign * state->step);
if (state->step >= 1)
*tune_state = CT_TUNER_STEP_1;
else
*tune_state = CT_TUNER_STEP_3;
} else if (*tune_state == CT_TUNER_STEP_3) {
dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
dib0070_write_reg(state, 0x18, 0x07ff);
*tune_state = CT_TUNER_STEP_4;
}
return ret;
}
static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
{
struct dib0070_state *state = fe->tuner_priv;
u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
dprintk("CTRL_LO5: 0x%x\n", lo5);
return dib0070_write_reg(state, 0x15, lo5);
}
void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
{
struct dib0070_state *state = fe->tuner_priv;
if (open) {
dib0070_write_reg(state, 0x1b, 0xff00);
dib0070_write_reg(state, 0x1a, 0x0000);
} else {
dib0070_write_reg(state, 0x1b, 0x4112);
if (state->cfg->vga_filter != 0) {
dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
dprintk("vga filter register is set to %x\n", state->cfg->vga_filter);
} else
dib0070_write_reg(state, 0x1a, 0x0009);
}
}
EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
struct dib0070_tuning {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 switch_trim;
u8 vco_band;
u8 hfdiv;
u8 vco_multi;
u8 presc;
u8 wbdmux;
u16 tuner_enable;
};
struct dib0070_lna_match {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 lna_band;
};
static const struct dib0070_tuning dib0070s_tuning_table[] = {
{ 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
{ 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
{ 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
{ 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
{ 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
{ 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
{ 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
};
static const struct dib0070_tuning dib0070_tuning_table[] = {
{ 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
{ 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
{ 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
{ 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
{ 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
{ 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
{ 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
{ 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
};
static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
{ 180000, 0 }, /* VHF */
{ 188000, 1 },
{ 196400, 2 },
{ 250000, 3 },
{ 550000, 0 }, /* UHF */
{ 590000, 1 },
{ 666000, 3 },
{ 864000, 5 },
{ 1500000, 0 }, /* LBAND or everything higher than UHF */
{ 1600000, 1 },
{ 2000000, 3 },
{ 0xffffffff, 7 },
};
static const struct dib0070_lna_match dib0070_lna[] = {
{ 180000, 0 }, /* VHF */
{ 188000, 1 },
{ 196400, 2 },
{ 250000, 3 },
{ 550000, 2 }, /* UHF */
{ 650000, 3 },
{ 750000, 5 },
{ 850000, 6 },
{ 864000, 7 },
{ 1500000, 0 }, /* LBAND or everything higher than UHF */
{ 1600000, 1 },
{ 2000000, 3 },
{ 0xffffffff, 7 },
};
#define LPF 100
static int dib0070_tune_digital(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
const struct dib0070_tuning *tune;
const struct dib0070_lna_match *lna_match;
enum frontend_tune_state *tune_state = &state->tune_state;
int ret = 10; /* 1ms is the default delay most of the time */
u8 band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
#ifdef CONFIG_SYS_ISDBT
if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
freq += 850;
#endif
if (state->current_rf != freq) {
switch (state->revision) {
case DIB0070S_P1A:
tune = dib0070s_tuning_table;
lna_match = dib0070_lna;
break;
default:
tune = dib0070_tuning_table;
if (state->cfg->flip_chip)
lna_match = dib0070_lna_flip_chip;
else
lna_match = dib0070_lna;
break;
}
while (freq > tune->max_freq) /* find the right one */
tune++;
while (freq > lna_match->max_freq) /* find the right one */
lna_match++;
state->current_tune_table_index = tune;
state->lna_match = lna_match;
}
if (*tune_state == CT_TUNER_START) {
dprintk("Tuning for Band: %d (%d kHz)\n", band, freq);
if (state->current_rf != freq) {
u8 REFDIV;
u32 FBDiv, Rest, FREF, VCOF_kHz;
u8 Den;
state->current_rf = freq;
state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
dib0070_write_reg(state, 0x17, 0x30);
VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
switch (band) {
case BAND_VHF:
REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
break;
case BAND_FM:
REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
break;
default:
REFDIV = (u8) (state->cfg->clock_khz / 10000);
break;
}
FREF = state->cfg->clock_khz / REFDIV;
switch (state->revision) {
case DIB0070S_P1A:
FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
break;
case DIB0070_P1G:
case DIB0070_P1F:
default:
FBDiv = (freq / (FREF / 2));
Rest = 2 * freq - FBDiv * FREF;
break;
}
if (Rest < LPF)
Rest = 0;
else if (Rest < 2 * LPF)
Rest = 2 * LPF;
else if (Rest > (FREF - LPF)) {
Rest = 0;
FBDiv += 1;
} else if (Rest > (FREF - 2 * LPF))
Rest = FREF - 2 * LPF;
Rest = (Rest * 6528) / (FREF / 10);
Den = 1;
if (Rest > 0) {
state->lo4 |= (1 << 14) | (1 << 12);
Den = 255;
}
dib0070_write_reg(state, 0x11, (u16)FBDiv);
dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
dib0070_write_reg(state, 0x13, (u16) Rest);
if (state->revision == DIB0070S_P1A) {
if (band == BAND_SBAND) {
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
dib0070_write_reg(state, 0x1d, 0xFFFF);
} else
dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
}
dib0070_write_reg(state, 0x20,
0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
dprintk("REFDIV: %u, FREF: %d\n", REFDIV, FREF);
dprintk("FBDIV: %d, Rest: %d\n", FBDiv, Rest);
dprintk("Num: %u, Den: %u, SD: %d\n", (u16)Rest, Den,
(state->lo4 >> 12) & 0x1);
dprintk("HFDIV code: %u\n",
state->current_tune_table_index->hfdiv);
dprintk("VCO = %u\n",
state->current_tune_table_index->vco_band);
dprintk("VCOF: ((%u*%d) << 1))\n",
state->current_tune_table_index->vco_multi,
freq);
*tune_state = CT_TUNER_STEP_0;
} else { /* we are already tuned to this frequency - the configuration is correct */
ret = 50; /* wakeup time */
*tune_state = CT_TUNER_STEP_5;
}
} else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
ret = dib0070_captrim(state, tune_state);
} else if (*tune_state == CT_TUNER_STEP_4) {
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
if (tmp != NULL) {
while (freq/1000 > tmp->freq) /* find the right one */
tmp++;
dib0070_write_reg(state, 0x0f,
(0 << 15) | (1 << 14) | (3 << 12)
| (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
| (state->current_tune_table_index->wbdmux << 0));
state->wbd_gain_current = tmp->wbd_gain_val;
} else {
dib0070_write_reg(state, 0x0f,
(0 << 15) | (1 << 14) | (3 << 12)
| (6 << 9) | (0 << 8) | (1 << 7)
| (state->current_tune_table_index->wbdmux << 0));
state->wbd_gain_current = 6;
}
dib0070_write_reg(state, 0x06, 0x3fff);
dib0070_write_reg(state, 0x07,
(state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
dib0070_write_reg(state, 0x0d, 0x0d80);
dib0070_write_reg(state, 0x18, 0x07ff);
dib0070_write_reg(state, 0x17, 0x0033);
*tune_state = CT_TUNER_STEP_5;
} else if (*tune_state == CT_TUNER_STEP_5) {
dib0070_set_bandwidth(fe);
*tune_state = CT_TUNER_STOP;
} else {
ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
}
return ret;
}
static int dib0070_tune(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
uint32_t ret;
state->tune_state = CT_TUNER_START;
do {
ret = dib0070_tune_digital(fe);
if (ret != FE_CALLBACK_TIME_NEVER)
msleep(ret/10);
else
break;
} while (state->tune_state != CT_TUNER_STOP);
return 0;
}
static int dib0070_wakeup(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
if (state->cfg->sleep)
state->cfg->sleep(fe, 0);
return 0;
}
static int dib0070_sleep(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
if (state->cfg->sleep)
state->cfg->sleep(fe, 1);
return 0;
}
u8 dib0070_get_rf_output(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
}
EXPORT_SYMBOL(dib0070_get_rf_output);
int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
{
struct dib0070_state *state = fe->tuner_priv;
u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
if (no > 3)
no = 3;
if (no < 1)
no = 1;
return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
}
EXPORT_SYMBOL(dib0070_set_rf_output);
static const u16 dib0070_p1f_defaults[] =
{
7, 0x02,
0x0008,
0x0000,
0x0000,
0x0000,
0x0000,
0x0002,
0x0100,
3, 0x0d,
0x0d80,
0x0001,
0x0000,
4, 0x11,
0x0000,
0x0103,
0x0000,
0x0000,
3, 0x16,
0x0004 | 0x0040,
0x0030,
0x07ff,
6, 0x1b,
0x4112,
0xff00,
0xc07f,
0x0000,
0x0180,
0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
0,
};
static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
{
u16 tuner_en = dib0070_read_reg(state, 0x20);
u16 offset;
dib0070_write_reg(state, 0x18, 0x07ff);
dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
msleep(9);
offset = dib0070_read_reg(state, 0x19);
dib0070_write_reg(state, 0x20, tuner_en);
return offset;
}
static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
{
u8 gain;
for (gain = 6; gain < 8; gain++) {
state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
dprintk("Gain: %d, WBDOffset (3.3V) = %hd\n", gain, state->wbd_offset_3_3[gain-6]);
}
}
u16 dib0070_wbd_offset(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
u32 freq = fe->dtv_property_cache.frequency/1000;
if (tmp != NULL) {
while (freq/1000 > tmp->freq) /* find the right one */
tmp++;
state->wbd_gain_current = tmp->wbd_gain_val;
} else
state->wbd_gain_current = 6;
return state->wbd_offset_3_3[state->wbd_gain_current - 6];
}
EXPORT_SYMBOL(dib0070_wbd_offset);
#define pgm_read_word(w) (*w)
static int dib0070_reset(struct dvb_frontend *fe)
{
struct dib0070_state *state = fe->tuner_priv;
u16 l, r, *n;
HARD_RESET(state);
#ifndef FORCE_SBAND_TUNER
if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
else
#else
#warning forcing SBAND
#endif
state->revision = DIB0070S_P1A;
/* P1F or not */
dprintk("Revision: %x\n", state->revision);
if (state->revision == DIB0070_P1D) {
dprintk("Error: this driver is not to be used meant for P1D or earlier\n");
return -EINVAL;
}
n = (u16 *) dib0070_p1f_defaults;
l = pgm_read_word(n++);
while (l) {
r = pgm_read_word(n++);
do {
dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
r++;
} while (--l);
l = pgm_read_word(n++);
}
if (state->cfg->force_crystal_mode != 0)
r = state->cfg->force_crystal_mode;
else if (state->cfg->clock_khz >= 24000)
r = 1;
else
r = 2;
r |= state->cfg->osc_buffer_state << 3;
dib0070_write_reg(state, 0x10, r);
dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
if (state->cfg->invert_iq) {
r = dib0070_read_reg(state, 0x02) & 0xffdf;
dib0070_write_reg(state, 0x02, r | (1 << 5));
}
if (state->revision == DIB0070S_P1A)
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
else
dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump,
state->cfg->enable_third_order_filter);
dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
dib0070_wbd_offset_calibration(state);
return 0;
}
static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct dib0070_state *state = fe->tuner_priv;
*frequency = 1000 * state->current_rf;
return 0;
}
static void dib0070_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static const struct dvb_tuner_ops dib0070_ops = {
.info = {
.name = "DiBcom DiB0070",
.frequency_min_hz = 45 * MHz,
.frequency_max_hz = 860 * MHz,
.frequency_step_hz = 1 * kHz,
},
.release = dib0070_release,
.init = dib0070_wakeup,
.sleep = dib0070_sleep,
.set_params = dib0070_tune,
.get_frequency = dib0070_get_frequency,
// .get_bandwidth = dib0070_get_bandwidth
};
struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
{
struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
if (state == NULL)
return NULL;
state->cfg = cfg;
state->i2c = i2c;
state->fe = fe;
mutex_init(&state->i2c_buffer_lock);
fe->tuner_priv = state;
if (dib0070_reset(fe) != 0)
goto free_mem;
pr_info("DiB0070: successfully identified\n");
memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = state;
return fe;
free_mem:
kfree(state);
fe->tuner_priv = NULL;
return NULL;
}
EXPORT_SYMBOL_GPL(dib0070_attach);
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib0070.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Intersil ISL6423 SEC and LNB Power supply controller
Copyright (C) Manu Abraham <[email protected]>
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "isl6423.h"
static unsigned int verbose;
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
#define FE_ERROR 0
#define FE_NOTICE 1
#define FE_INFO 2
#define FE_DEBUG 3
#define FE_DEBUGREG 4
#define dprintk(__y, __z, format, arg...) do { \
if (__z) { \
if ((verbose > FE_ERROR) && (verbose > __y)) \
printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_NOTICE) && (verbose > __y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_INFO) && (verbose > __y)) \
printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_DEBUG) && (verbose > __y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
} else { \
if (verbose > __y) \
printk(format, ##arg); \
} \
} while (0)
struct isl6423_dev {
const struct isl6423_config *config;
struct i2c_adapter *i2c;
u8 reg_3;
u8 reg_4;
unsigned int verbose;
};
static int isl6423_write(struct isl6423_dev *isl6423, u8 reg)
{
struct i2c_adapter *i2c = isl6423->i2c;
u8 addr = isl6423->config->addr;
int err = 0;
struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = ®, .len = 1 };
dprintk(FE_DEBUG, 1, "write reg %02X", reg);
err = i2c_transfer(i2c, &msg, 1);
if (err < 0)
goto exit;
return 0;
exit:
dprintk(FE_ERROR, 1, "I/O error <%d>", err);
return err;
}
static int isl6423_set_modulation(struct dvb_frontend *fe)
{
struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
const struct isl6423_config *config = isl6423->config;
int err = 0;
u8 reg_2 = 0;
reg_2 = 0x01 << 5;
if (config->mod_extern)
reg_2 |= (1 << 3);
else
reg_2 |= (1 << 4);
err = isl6423_write(isl6423, reg_2);
if (err < 0)
goto exit;
return 0;
exit:
dprintk(FE_ERROR, 1, "I/O error <%d>", err);
return err;
}
static int isl6423_voltage_boost(struct dvb_frontend *fe, long arg)
{
struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
u8 reg_3 = isl6423->reg_3;
u8 reg_4 = isl6423->reg_4;
int err = 0;
if (arg) {
/* EN = 1, VSPEN = 1, VBOT = 1 */
reg_4 |= (1 << 4);
reg_4 |= 0x1;
reg_3 |= (1 << 3);
} else {
/* EN = 1, VSPEN = 1, VBOT = 0 */
reg_4 |= (1 << 4);
reg_4 &= ~0x1;
reg_3 |= (1 << 3);
}
err = isl6423_write(isl6423, reg_3);
if (err < 0)
goto exit;
err = isl6423_write(isl6423, reg_4);
if (err < 0)
goto exit;
isl6423->reg_3 = reg_3;
isl6423->reg_4 = reg_4;
return 0;
exit:
dprintk(FE_ERROR, 1, "I/O error <%d>", err);
return err;
}
static int isl6423_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
u8 reg_3 = isl6423->reg_3;
u8 reg_4 = isl6423->reg_4;
int err = 0;
switch (voltage) {
case SEC_VOLTAGE_OFF:
/* EN = 0 */
reg_4 &= ~(1 << 4);
break;
case SEC_VOLTAGE_13:
/* EN = 1, VSPEN = 1, VTOP = 0, VBOT = 0 */
reg_4 |= (1 << 4);
reg_4 &= ~0x3;
reg_3 |= (1 << 3);
break;
case SEC_VOLTAGE_18:
/* EN = 1, VSPEN = 1, VTOP = 1, VBOT = 0 */
reg_4 |= (1 << 4);
reg_4 |= 0x2;
reg_4 &= ~0x1;
reg_3 |= (1 << 3);
break;
default:
break;
}
err = isl6423_write(isl6423, reg_3);
if (err < 0)
goto exit;
err = isl6423_write(isl6423, reg_4);
if (err < 0)
goto exit;
isl6423->reg_3 = reg_3;
isl6423->reg_4 = reg_4;
return 0;
exit:
dprintk(FE_ERROR, 1, "I/O error <%d>", err);
return err;
}
static int isl6423_set_current(struct dvb_frontend *fe)
{
struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
u8 reg_3 = isl6423->reg_3;
const struct isl6423_config *config = isl6423->config;
int err = 0;
switch (config->current_max) {
case SEC_CURRENT_275m:
/* 275mA */
/* ISELH = 0, ISELL = 0 */
reg_3 &= ~0x3;
break;
case SEC_CURRENT_515m:
/* 515mA */
/* ISELH = 0, ISELL = 1 */
reg_3 &= ~0x2;
reg_3 |= 0x1;
break;
case SEC_CURRENT_635m:
/* 635mA */
/* ISELH = 1, ISELL = 0 */
reg_3 &= ~0x1;
reg_3 |= 0x2;
break;
case SEC_CURRENT_800m:
/* 800mA */
/* ISELH = 1, ISELL = 1 */
reg_3 |= 0x3;
break;
}
err = isl6423_write(isl6423, reg_3);
if (err < 0)
goto exit;
switch (config->curlim) {
case SEC_CURRENT_LIM_ON:
/* DCL = 0 */
reg_3 &= ~0x10;
break;
case SEC_CURRENT_LIM_OFF:
/* DCL = 1 */
reg_3 |= 0x10;
break;
}
err = isl6423_write(isl6423, reg_3);
if (err < 0)
goto exit;
isl6423->reg_3 = reg_3;
return 0;
exit:
dprintk(FE_ERROR, 1, "I/O error <%d>", err);
return err;
}
static void isl6423_release(struct dvb_frontend *fe)
{
isl6423_set_voltage(fe, SEC_VOLTAGE_OFF);
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
const struct isl6423_config *config)
{
struct isl6423_dev *isl6423;
isl6423 = kzalloc(sizeof(struct isl6423_dev), GFP_KERNEL);
if (!isl6423)
return NULL;
isl6423->config = config;
isl6423->i2c = i2c;
fe->sec_priv = isl6423;
/* SR3H = 0, SR3M = 1, SR3L = 0 */
isl6423->reg_3 = 0x02 << 5;
/* SR4H = 0, SR4M = 1, SR4L = 1 */
isl6423->reg_4 = 0x03 << 5;
if (isl6423_set_current(fe))
goto exit;
if (isl6423_set_modulation(fe))
goto exit;
fe->ops.release_sec = isl6423_release;
fe->ops.set_voltage = isl6423_set_voltage;
fe->ops.enable_high_lnb_voltage = isl6423_voltage_boost;
isl6423->verbose = verbose;
return fe;
exit:
kfree(isl6423);
fe->sec_priv = NULL;
return NULL;
}
EXPORT_SYMBOL_GPL(isl6423_attach);
MODULE_DESCRIPTION("ISL6423 SEC");
MODULE_AUTHOR("Manu Abraham");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/isl6423.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Zarlink DVB-T MT352 demodulator
*
* Written by Holger Waechtler <[email protected]>
* and Daniel Mack <[email protected]>
*
* AVerMedia AVerTV DVB-T 771 support by
* Wolfram Joost <[email protected]>
*
* Support for Samsung TDTC9251DH01C(M) tuner
* Copyright (C) 2004 Antonio Mancuso <[email protected]>
* Amauri Celani <[email protected]>
*
* DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
* Christopher Pascoe <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "mt352_priv.h"
#include "mt352.h"
struct mt352_state {
struct i2c_adapter* i2c;
struct dvb_frontend frontend;
/* configuration settings */
struct mt352_config config;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "mt352: " args); \
} while (0)
static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
struct mt352_state* state = fe->demodulator_priv;
u8 buf[2] = { reg, val };
struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
.buf = buf, .len = 2 };
int err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
return err;
}
return 0;
}
static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
{
int err,i;
for (i=0; i < ilen-1; i++)
if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
return err;
return 0;
}
static int mt352_read_register(struct mt352_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config.demod_address,
.flags = 0,
.buf = b0, .len = 1 },
{ .addr = state->config.demod_address,
.flags = I2C_M_RD,
.buf = b1, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk("%s: readreg error (reg=%d, ret==%i)\n",
__func__, reg, ret);
return ret;
}
return b1[0];
}
static int mt352_sleep(struct dvb_frontend* fe)
{
static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
_mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
return 0;
}
static void mt352_calc_nominal_rate(struct mt352_state* state,
u32 bandwidth,
unsigned char *buf)
{
u32 adc_clock = 20480; /* 20.340 MHz */
u32 bw,value;
switch (bandwidth) {
case 6000000:
bw = 6;
break;
case 7000000:
bw = 7;
break;
case 8000000:
default:
bw = 8;
break;
}
if (state->config.adc_clock)
adc_clock = state->config.adc_clock;
value = 64 * bw * (1<<16) / (7 * 8);
value = value * 1000 / adc_clock;
dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
__func__, bw, adc_clock, value);
buf[0] = msb(value);
buf[1] = lsb(value);
}
static void mt352_calc_input_freq(struct mt352_state* state,
unsigned char *buf)
{
int adc_clock = 20480; /* 20.480000 MHz */
int if2 = 36167; /* 36.166667 MHz */
int ife,value;
if (state->config.adc_clock)
adc_clock = state->config.adc_clock;
if (state->config.if2)
if2 = state->config.if2;
if (adc_clock >= if2 * 2)
ife = if2;
else {
ife = adc_clock - (if2 % adc_clock);
if (ife > adc_clock / 2)
ife = adc_clock - ife;
}
value = -16374 * ife / adc_clock;
dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
__func__, if2, ife, adc_clock, value, value & 0x3fff);
buf[0] = msb(value);
buf[1] = lsb(value);
}
static int mt352_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *op = &fe->dtv_property_cache;
struct mt352_state* state = fe->demodulator_priv;
unsigned char buf[13];
static unsigned char tuner_go[] = { 0x5d, 0x01 };
static unsigned char fsm_go[] = { 0x5e, 0x01 };
unsigned int tps = 0;
switch (op->code_rate_HP) {
case FEC_2_3:
tps |= (1 << 7);
break;
case FEC_3_4:
tps |= (2 << 7);
break;
case FEC_5_6:
tps |= (3 << 7);
break;
case FEC_7_8:
tps |= (4 << 7);
break;
case FEC_1_2:
case FEC_AUTO:
break;
default:
return -EINVAL;
}
switch (op->code_rate_LP) {
case FEC_2_3:
tps |= (1 << 4);
break;
case FEC_3_4:
tps |= (2 << 4);
break;
case FEC_5_6:
tps |= (3 << 4);
break;
case FEC_7_8:
tps |= (4 << 4);
break;
case FEC_1_2:
case FEC_AUTO:
break;
case FEC_NONE:
if (op->hierarchy == HIERARCHY_AUTO ||
op->hierarchy == HIERARCHY_NONE)
break;
fallthrough;
default:
return -EINVAL;
}
switch (op->modulation) {
case QPSK:
break;
case QAM_AUTO:
case QAM_16:
tps |= (1 << 13);
break;
case QAM_64:
tps |= (2 << 13);
break;
default:
return -EINVAL;
}
switch (op->transmission_mode) {
case TRANSMISSION_MODE_2K:
case TRANSMISSION_MODE_AUTO:
break;
case TRANSMISSION_MODE_8K:
tps |= (1 << 0);
break;
default:
return -EINVAL;
}
switch (op->guard_interval) {
case GUARD_INTERVAL_1_32:
case GUARD_INTERVAL_AUTO:
break;
case GUARD_INTERVAL_1_16:
tps |= (1 << 2);
break;
case GUARD_INTERVAL_1_8:
tps |= (2 << 2);
break;
case GUARD_INTERVAL_1_4:
tps |= (3 << 2);
break;
default:
return -EINVAL;
}
switch (op->hierarchy) {
case HIERARCHY_AUTO:
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
tps |= (1 << 10);
break;
case HIERARCHY_2:
tps |= (2 << 10);
break;
case HIERARCHY_4:
tps |= (3 << 10);
break;
default:
return -EINVAL;
}
buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
buf[2] = lsb(tps);
buf[3] = 0x50; // old
// buf[3] = 0xf4; // pinnacle
mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
mt352_calc_input_freq(state, buf+6);
if (state->config.no_tuner) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
_mt352_write(fe, buf, 8);
_mt352_write(fe, fsm_go, 2);
} else {
if (fe->ops.tuner_ops.calc_regs) {
fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
buf[8] <<= 1;
_mt352_write(fe, buf, sizeof(buf));
_mt352_write(fe, tuner_go, 2);
}
}
return 0;
}
static int mt352_get_parameters(struct dvb_frontend* fe,
struct dtv_frontend_properties *op)
{
struct mt352_state* state = fe->demodulator_priv;
u16 tps;
u16 div;
u8 trl;
static const u8 tps_fec_to_api[8] =
{
FEC_1_2,
FEC_2_3,
FEC_3_4,
FEC_5_6,
FEC_7_8,
FEC_AUTO,
FEC_AUTO,
FEC_AUTO
};
if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
return -EINVAL;
/* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
* the mt352 sometimes works with the wrong parameters
*/
tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
switch ( (tps >> 13) & 3)
{
case 0:
op->modulation = QPSK;
break;
case 1:
op->modulation = QAM_16;
break;
case 2:
op->modulation = QAM_64;
break;
default:
op->modulation = QAM_AUTO;
break;
}
op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
switch ( (tps >> 2) & 3)
{
case 0:
op->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
op->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
op->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
op->guard_interval = GUARD_INTERVAL_1_4;
break;
default:
op->guard_interval = GUARD_INTERVAL_AUTO;
break;
}
switch ( (tps >> 10) & 7)
{
case 0:
op->hierarchy = HIERARCHY_NONE;
break;
case 1:
op->hierarchy = HIERARCHY_1;
break;
case 2:
op->hierarchy = HIERARCHY_2;
break;
case 3:
op->hierarchy = HIERARCHY_4;
break;
default:
op->hierarchy = HIERARCHY_AUTO;
break;
}
op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
if (trl == 0x72)
op->bandwidth_hz = 8000000;
else if (trl == 0x64)
op->bandwidth_hz = 7000000;
else
op->bandwidth_hz = 6000000;
if (mt352_read_register(state, STATUS_2) & 0x02)
op->inversion = INVERSION_OFF;
else
op->inversion = INVERSION_ON;
return 0;
}
static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct mt352_state* state = fe->demodulator_priv;
int s0, s1, s3;
/* FIXME:
*
* The MT352 design manual from Zarlink states (page 46-47):
*
* Notes about the TUNER_GO register:
*
* If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
* byte is copied from the tuner to the STATUS_3 register and
* completion of the read operation is indicated by bit-5 of the
* INTERRUPT_3 register.
*/
if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
return -EREMOTEIO;
if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
return -EREMOTEIO;
if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
return -EREMOTEIO;
*status = 0;
if (s0 & (1 << 4))
*status |= FE_HAS_CARRIER;
if (s0 & (1 << 1))
*status |= FE_HAS_VITERBI;
if (s0 & (1 << 5))
*status |= FE_HAS_LOCK;
if (s1 & (1 << 1))
*status |= FE_HAS_SYNC;
if (s3 & (1 << 6))
*status |= FE_HAS_SIGNAL;
if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
(FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
*status &= ~FE_HAS_LOCK;
return 0;
}
static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct mt352_state* state = fe->demodulator_priv;
*ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
(mt352_read_register (state, RS_ERR_CNT_1) << 8) |
(mt352_read_register (state, RS_ERR_CNT_0));
return 0;
}
static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct mt352_state* state = fe->demodulator_priv;
/* align the 12 bit AGC gain with the most significant bits */
u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
(mt352_read_register(state, AGC_GAIN_0) << 4);
/* inverse of gain is signal strength */
*strength = ~signal;
return 0;
}
static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct mt352_state* state = fe->demodulator_priv;
u8 _snr = mt352_read_register (state, SNR);
*snr = (_snr << 8) | _snr;
return 0;
}
static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct mt352_state* state = fe->demodulator_priv;
*ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
(mt352_read_register (state, RS_UBC_0));
return 0;
}
static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 800;
fe_tune_settings->step_size = 0;
fe_tune_settings->max_drift = 0;
return 0;
}
static int mt352_init(struct dvb_frontend* fe)
{
struct mt352_state* state = fe->demodulator_priv;
static u8 mt352_reset_attach [] = { RESET, 0xC0 };
dprintk("%s: hello\n",__func__);
if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
(mt352_read_register(state, CONFIG) & 0x20) == 0) {
/* Do a "hard" reset */
_mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
return state->config.demod_init(fe);
}
return 0;
}
static void mt352_release(struct dvb_frontend* fe)
{
struct mt352_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops mt352_ops;
struct dvb_frontend* mt352_attach(const struct mt352_config* config,
struct i2c_adapter* i2c)
{
struct mt352_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->i2c = i2c;
memcpy(&state->config,config,sizeof(struct mt352_config));
/* check if the demod is there */
if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops mt352_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Zarlink MT352 DVB-T",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.release = mt352_release,
.init = mt352_init,
.sleep = mt352_sleep,
.write = _mt352_write,
.set_frontend = mt352_set_parameters,
.get_frontend = mt352_get_parameters,
.get_tune_settings = mt352_get_tune_settings,
.read_status = mt352_read_status,
.read_ber = mt352_read_ber,
.read_signal_strength = mt352_read_signal_strength,
.read_snr = mt352_read_snr,
.read_ucblocks = mt352_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(mt352_attach);
| linux-master | drivers/media/dvb-frontends/mt352.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Samsung s5h1432 DVB-T demodulator driver
*
* Copyright (C) 2009 Bill Liu <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "s5h1432.h"
struct s5h1432_state {
struct i2c_adapter *i2c;
/* configuration settings */
const struct s5h1432_config *config;
struct dvb_frontend frontend;
enum fe_modulation current_modulation;
unsigned int first_tune:1;
u32 current_frequency;
int if_freq;
u8 inversion;
};
static int debug;
#define dprintk(arg...) do { \
if (debug) \
printk(arg); \
} while (0)
static int s5h1432_writereg(struct s5h1432_state *state,
u8 addr, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
__func__, addr, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{.addr = addr, .flags = 0, .buf = b0, .len = 1},
{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk(KERN_ERR "%s: readreg error (ret == %i)\n",
__func__, ret);
return b1[0];
}
static int s5h1432_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
u32 bandwidth)
{
struct s5h1432_state *state = fe->demodulator_priv;
u8 reg = 0;
/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
reg &= ~(0x0C);
switch (bandwidth) {
case 6:
reg |= 0x08;
break;
case 7:
reg |= 0x04;
break;
case 8:
reg |= 0x00;
break;
default:
return 0;
}
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
return 1;
}
static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
{
struct s5h1432_state *state = fe->demodulator_priv;
switch (ifFreqHz) {
case TAIWAN_HI_IF_FREQ_44_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
break;
case EUROPE_HI_IF_FREQ_36_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
break;
case IF_FREQ_6_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
break;
case IF_FREQ_3point3_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
break;
case IF_FREQ_3point5_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
break;
case IF_FREQ_4_MHZ:
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
break;
default:
{
u32 value = 0;
value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
(u32) 32768) / (48 * 1000));
printk(KERN_INFO
"Default IFFreq %d :reg value = 0x%x\n",
ifFreqHz, value);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
(u8) value & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
(u8) (value >> 8) & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
(u8) (value >> 16) & 0xFF);
break;
}
}
return 1;
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int s5h1432_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 dvb_bandwidth = 8;
struct s5h1432_state *state = fe->demodulator_priv;
if (p->frequency == state->current_frequency) {
/*current_frequency = p->frequency; */
/*state->current_frequency = p->frequency; */
} else {
fe->ops.tuner_ops.set_params(fe);
msleep(300);
s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
switch (p->bandwidth_hz) {
case 6000000:
dvb_bandwidth = 6;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
case 7000000:
dvb_bandwidth = 7;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
case 8000000:
dvb_bandwidth = 8;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
default:
return 0;
}
/*fe->ops.tuner_ops.set_params(fe); */
/*Soft Reset chip*/
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
switch (p->bandwidth_hz) {
case 6000000:
dvb_bandwidth = 6;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
case 7000000:
dvb_bandwidth = 7;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
case 8000000:
dvb_bandwidth = 8;
s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
break;
default:
return 0;
}
/*fe->ops.tuner_ops.set_params(fe); */
/*Soft Reset chip*/
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
}
state->current_frequency = p->frequency;
return 0;
}
static int s5h1432_init(struct dvb_frontend *fe)
{
struct s5h1432_state *state = fe->demodulator_priv;
u8 reg = 0;
state->current_frequency = 0;
printk(KERN_INFO " s5h1432_init().\n");
/*Set VSB mode as default, this also does a soft reset */
/*Initialize registers */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
/*For NXP tuner*/
/*Set 3.3MHz as default IF frequency */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
/* Set reg 0x1E to get the full dynamic range */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
/* Mode setting in demod */
reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
reg |= 0x80;
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
/* Serial mode */
/* Soft Reset chip */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
return 0;
}
static int s5h1432_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
return 0;
}
static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
return 0;
}
static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
{
return 0;
}
static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
return 0;
}
static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
{
return 0;
}
static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
return 0;
}
static void s5h1432_release(struct dvb_frontend *fe)
{
struct s5h1432_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops s5h1432_ops;
struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
struct i2c_adapter *i2c)
{
struct s5h1432_state *state = NULL;
printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
/* allocate memory for the internal state */
state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
if (!state)
return NULL;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->current_modulation = QAM_16;
state->inversion = state->config->inversion;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1432_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL_GPL(s5h1432_attach);
static const struct dvb_frontend_ops s5h1432_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Samsung s5h1432 DVB-T Frontend",
.frequency_min_hz = 177 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
.init = s5h1432_init,
.sleep = s5h1432_sleep,
.set_frontend = s5h1432_set_frontend,
.get_tune_settings = s5h1432_get_tune_settings,
.read_status = s5h1432_read_status,
.read_ber = s5h1432_read_ber,
.read_signal_strength = s5h1432_read_signal_strength,
.read_snr = s5h1432_read_snr,
.read_ucblocks = s5h1432_read_ucblocks,
.release = s5h1432_release,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
MODULE_AUTHOR("Bill Liu");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/s5h1432.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
STV0900/0903 Multistandard Broadcast Frontend driver
Copyright (C) Manu Abraham <[email protected]>
Copyright (C) ST Microelectronics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/dvb/frontend.h>
#include <media/dvb_frontend.h>
#include "stv6110x.h" /* for demodulator internal modes */
#include "stv090x_reg.h"
#include "stv090x.h"
#include "stv090x_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static unsigned int verbose;
module_param(verbose, int, 0644);
/* internal params node */
struct stv090x_dev {
/* pointer for internal params, one for each pair of demods */
struct stv090x_internal *internal;
struct stv090x_dev *next_dev;
};
/* first internal params */
static struct stv090x_dev *stv090x_first_dev;
/* find chip by i2c adapter and i2c address */
static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
u8 i2c_addr)
{
struct stv090x_dev *temp_dev = stv090x_first_dev;
/*
Search of the last stv0900 chip or
find it by i2c adapter and i2c address */
while ((temp_dev != NULL) &&
((temp_dev->internal->i2c_adap != i2c_adap) ||
(temp_dev->internal->i2c_addr != i2c_addr))) {
temp_dev = temp_dev->next_dev;
}
return temp_dev;
}
/* deallocating chip */
static void remove_dev(struct stv090x_internal *internal)
{
struct stv090x_dev *prev_dev = stv090x_first_dev;
struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
internal->i2c_addr);
if (del_dev != NULL) {
if (del_dev == stv090x_first_dev) {
stv090x_first_dev = del_dev->next_dev;
} else {
while (prev_dev->next_dev != del_dev)
prev_dev = prev_dev->next_dev;
prev_dev->next_dev = del_dev->next_dev;
}
kfree(del_dev);
}
}
/* allocating new chip */
static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
{
struct stv090x_dev *new_dev;
struct stv090x_dev *temp_dev;
new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
if (new_dev != NULL) {
new_dev->internal = internal;
new_dev->next_dev = NULL;
/* append to list */
if (stv090x_first_dev == NULL) {
stv090x_first_dev = new_dev;
} else {
temp_dev = stv090x_first_dev;
while (temp_dev->next_dev != NULL)
temp_dev = temp_dev->next_dev;
temp_dev->next_dev = new_dev;
}
}
return new_dev;
}
/* DVBS1 and DSS C/N Lookup table */
static const struct stv090x_tab stv090x_s1cn_tab[] = {
{ 0, 8917 }, /* 0.0dB */
{ 5, 8801 }, /* 0.5dB */
{ 10, 8667 }, /* 1.0dB */
{ 15, 8522 }, /* 1.5dB */
{ 20, 8355 }, /* 2.0dB */
{ 25, 8175 }, /* 2.5dB */
{ 30, 7979 }, /* 3.0dB */
{ 35, 7763 }, /* 3.5dB */
{ 40, 7530 }, /* 4.0dB */
{ 45, 7282 }, /* 4.5dB */
{ 50, 7026 }, /* 5.0dB */
{ 55, 6781 }, /* 5.5dB */
{ 60, 6514 }, /* 6.0dB */
{ 65, 6241 }, /* 6.5dB */
{ 70, 5965 }, /* 7.0dB */
{ 75, 5690 }, /* 7.5dB */
{ 80, 5424 }, /* 8.0dB */
{ 85, 5161 }, /* 8.5dB */
{ 90, 4902 }, /* 9.0dB */
{ 95, 4654 }, /* 9.5dB */
{ 100, 4417 }, /* 10.0dB */
{ 105, 4186 }, /* 10.5dB */
{ 110, 3968 }, /* 11.0dB */
{ 115, 3757 }, /* 11.5dB */
{ 120, 3558 }, /* 12.0dB */
{ 125, 3366 }, /* 12.5dB */
{ 130, 3185 }, /* 13.0dB */
{ 135, 3012 }, /* 13.5dB */
{ 140, 2850 }, /* 14.0dB */
{ 145, 2698 }, /* 14.5dB */
{ 150, 2550 }, /* 15.0dB */
{ 160, 2283 }, /* 16.0dB */
{ 170, 2042 }, /* 17.0dB */
{ 180, 1827 }, /* 18.0dB */
{ 190, 1636 }, /* 19.0dB */
{ 200, 1466 }, /* 20.0dB */
{ 210, 1315 }, /* 21.0dB */
{ 220, 1181 }, /* 22.0dB */
{ 230, 1064 }, /* 23.0dB */
{ 240, 960 }, /* 24.0dB */
{ 250, 869 }, /* 25.0dB */
{ 260, 792 }, /* 26.0dB */
{ 270, 724 }, /* 27.0dB */
{ 280, 665 }, /* 28.0dB */
{ 290, 616 }, /* 29.0dB */
{ 300, 573 }, /* 30.0dB */
{ 310, 537 }, /* 31.0dB */
{ 320, 507 }, /* 32.0dB */
{ 330, 483 }, /* 33.0dB */
{ 400, 398 }, /* 40.0dB */
{ 450, 381 }, /* 45.0dB */
{ 500, 377 } /* 50.0dB */
};
/* DVBS2 C/N Lookup table */
static const struct stv090x_tab stv090x_s2cn_tab[] = {
{ -30, 13348 }, /* -3.0dB */
{ -20, 12640 }, /* -2d.0B */
{ -10, 11883 }, /* -1.0dB */
{ 0, 11101 }, /* -0.0dB */
{ 5, 10718 }, /* 0.5dB */
{ 10, 10339 }, /* 1.0dB */
{ 15, 9947 }, /* 1.5dB */
{ 20, 9552 }, /* 2.0dB */
{ 25, 9183 }, /* 2.5dB */
{ 30, 8799 }, /* 3.0dB */
{ 35, 8422 }, /* 3.5dB */
{ 40, 8062 }, /* 4.0dB */
{ 45, 7707 }, /* 4.5dB */
{ 50, 7353 }, /* 5.0dB */
{ 55, 7025 }, /* 5.5dB */
{ 60, 6684 }, /* 6.0dB */
{ 65, 6331 }, /* 6.5dB */
{ 70, 6036 }, /* 7.0dB */
{ 75, 5727 }, /* 7.5dB */
{ 80, 5437 }, /* 8.0dB */
{ 85, 5164 }, /* 8.5dB */
{ 90, 4902 }, /* 9.0dB */
{ 95, 4653 }, /* 9.5dB */
{ 100, 4408 }, /* 10.0dB */
{ 105, 4187 }, /* 10.5dB */
{ 110, 3961 }, /* 11.0dB */
{ 115, 3751 }, /* 11.5dB */
{ 120, 3558 }, /* 12.0dB */
{ 125, 3368 }, /* 12.5dB */
{ 130, 3191 }, /* 13.0dB */
{ 135, 3017 }, /* 13.5dB */
{ 140, 2862 }, /* 14.0dB */
{ 145, 2710 }, /* 14.5dB */
{ 150, 2565 }, /* 15.0dB */
{ 160, 2300 }, /* 16.0dB */
{ 170, 2058 }, /* 17.0dB */
{ 180, 1849 }, /* 18.0dB */
{ 190, 1663 }, /* 19.0dB */
{ 200, 1495 }, /* 20.0dB */
{ 210, 1349 }, /* 21.0dB */
{ 220, 1222 }, /* 22.0dB */
{ 230, 1110 }, /* 23.0dB */
{ 240, 1011 }, /* 24.0dB */
{ 250, 925 }, /* 25.0dB */
{ 260, 853 }, /* 26.0dB */
{ 270, 789 }, /* 27.0dB */
{ 280, 734 }, /* 28.0dB */
{ 290, 690 }, /* 29.0dB */
{ 300, 650 }, /* 30.0dB */
{ 310, 619 }, /* 31.0dB */
{ 320, 593 }, /* 32.0dB */
{ 330, 571 }, /* 33.0dB */
{ 400, 498 }, /* 40.0dB */
{ 450, 484 }, /* 45.0dB */
{ 500, 481 } /* 50.0dB */
};
/* RF level C/N lookup table */
static const struct stv090x_tab stv090x_rf_tab[] = {
{ -5, 0xcaa1 }, /* -5dBm */
{ -10, 0xc229 }, /* -10dBm */
{ -15, 0xbb08 }, /* -15dBm */
{ -20, 0xb4bc }, /* -20dBm */
{ -25, 0xad5a }, /* -25dBm */
{ -30, 0xa298 }, /* -30dBm */
{ -35, 0x98a8 }, /* -35dBm */
{ -40, 0x8389 }, /* -40dBm */
{ -45, 0x59be }, /* -45dBm */
{ -50, 0x3a14 }, /* -50dBm */
{ -55, 0x2d11 }, /* -55dBm */
{ -60, 0x210d }, /* -60dBm */
{ -65, 0xa14f }, /* -65dBm */
{ -70, 0x07aa } /* -70dBm */
};
static struct stv090x_reg stv0900_initval[] = {
{ STV090x_OUTCFG, 0x00 },
{ STV090x_MODECFG, 0xff },
{ STV090x_AGCRF1CFG, 0x11 },
{ STV090x_AGCRF2CFG, 0x13 },
{ STV090x_TSGENERAL1X, 0x14 },
{ STV090x_TSTTNR2, 0x21 },
{ STV090x_TSTTNR4, 0x21 },
{ STV090x_P2_DISTXCTL, 0x22 },
{ STV090x_P2_F22TX, 0xc0 },
{ STV090x_P2_F22RX, 0xc0 },
{ STV090x_P2_DISRXCTL, 0x00 },
{ STV090x_P2_DMDCFGMD, 0xF9 },
{ STV090x_P2_DEMOD, 0x08 },
{ STV090x_P2_DMDCFG3, 0xc4 },
{ STV090x_P2_CARFREQ, 0xed },
{ STV090x_P2_LDT, 0xd0 },
{ STV090x_P2_LDT2, 0xb8 },
{ STV090x_P2_TMGCFG, 0xd2 },
{ STV090x_P2_TMGTHRISE, 0x20 },
{ STV090x_P1_TMGCFG, 0xd2 },
{ STV090x_P2_TMGTHFALL, 0x00 },
{ STV090x_P2_FECSPY, 0x88 },
{ STV090x_P2_FSPYDATA, 0x3a },
{ STV090x_P2_FBERCPT4, 0x00 },
{ STV090x_P2_FSPYBER, 0x10 },
{ STV090x_P2_ERRCTRL1, 0x35 },
{ STV090x_P2_ERRCTRL2, 0xc1 },
{ STV090x_P2_CFRICFG, 0xf8 },
{ STV090x_P2_NOSCFG, 0x1c },
{ STV090x_P2_DMDTOM, 0x20 },
{ STV090x_P2_CORRELMANT, 0x70 },
{ STV090x_P2_CORRELABS, 0x88 },
{ STV090x_P2_AGC2O, 0x5b },
{ STV090x_P2_AGC2REF, 0x38 },
{ STV090x_P2_CARCFG, 0xe4 },
{ STV090x_P2_ACLC, 0x1A },
{ STV090x_P2_BCLC, 0x09 },
{ STV090x_P2_CARHDR, 0x08 },
{ STV090x_P2_KREFTMG, 0xc1 },
{ STV090x_P2_SFRUPRATIO, 0xf0 },
{ STV090x_P2_SFRLOWRATIO, 0x70 },
{ STV090x_P2_SFRSTEP, 0x58 },
{ STV090x_P2_TMGCFG2, 0x01 },
{ STV090x_P2_CAR2CFG, 0x26 },
{ STV090x_P2_BCLC2S2Q, 0x86 },
{ STV090x_P2_BCLC2S28, 0x86 },
{ STV090x_P2_SMAPCOEF7, 0x77 },
{ STV090x_P2_SMAPCOEF6, 0x85 },
{ STV090x_P2_SMAPCOEF5, 0x77 },
{ STV090x_P2_TSCFGL, 0x20 },
{ STV090x_P2_DMDCFG2, 0x3b },
{ STV090x_P2_MODCODLST0, 0xff },
{ STV090x_P2_MODCODLST1, 0xff },
{ STV090x_P2_MODCODLST2, 0xff },
{ STV090x_P2_MODCODLST3, 0xff },
{ STV090x_P2_MODCODLST4, 0xff },
{ STV090x_P2_MODCODLST5, 0xff },
{ STV090x_P2_MODCODLST6, 0xff },
{ STV090x_P2_MODCODLST7, 0xcc },
{ STV090x_P2_MODCODLST8, 0xcc },
{ STV090x_P2_MODCODLST9, 0xcc },
{ STV090x_P2_MODCODLSTA, 0xcc },
{ STV090x_P2_MODCODLSTB, 0xcc },
{ STV090x_P2_MODCODLSTC, 0xcc },
{ STV090x_P2_MODCODLSTD, 0xcc },
{ STV090x_P2_MODCODLSTE, 0xcc },
{ STV090x_P2_MODCODLSTF, 0xcf },
{ STV090x_P1_DISTXCTL, 0x22 },
{ STV090x_P1_F22TX, 0xc0 },
{ STV090x_P1_F22RX, 0xc0 },
{ STV090x_P1_DISRXCTL, 0x00 },
{ STV090x_P1_DMDCFGMD, 0xf9 },
{ STV090x_P1_DEMOD, 0x08 },
{ STV090x_P1_DMDCFG3, 0xc4 },
{ STV090x_P1_DMDTOM, 0x20 },
{ STV090x_P1_CARFREQ, 0xed },
{ STV090x_P1_LDT, 0xd0 },
{ STV090x_P1_LDT2, 0xb8 },
{ STV090x_P1_TMGCFG, 0xd2 },
{ STV090x_P1_TMGTHRISE, 0x20 },
{ STV090x_P1_TMGTHFALL, 0x00 },
{ STV090x_P1_SFRUPRATIO, 0xf0 },
{ STV090x_P1_SFRLOWRATIO, 0x70 },
{ STV090x_P1_TSCFGL, 0x20 },
{ STV090x_P1_FECSPY, 0x88 },
{ STV090x_P1_FSPYDATA, 0x3a },
{ STV090x_P1_FBERCPT4, 0x00 },
{ STV090x_P1_FSPYBER, 0x10 },
{ STV090x_P1_ERRCTRL1, 0x35 },
{ STV090x_P1_ERRCTRL2, 0xc1 },
{ STV090x_P1_CFRICFG, 0xf8 },
{ STV090x_P1_NOSCFG, 0x1c },
{ STV090x_P1_CORRELMANT, 0x70 },
{ STV090x_P1_CORRELABS, 0x88 },
{ STV090x_P1_AGC2O, 0x5b },
{ STV090x_P1_AGC2REF, 0x38 },
{ STV090x_P1_CARCFG, 0xe4 },
{ STV090x_P1_ACLC, 0x1A },
{ STV090x_P1_BCLC, 0x09 },
{ STV090x_P1_CARHDR, 0x08 },
{ STV090x_P1_KREFTMG, 0xc1 },
{ STV090x_P1_SFRSTEP, 0x58 },
{ STV090x_P1_TMGCFG2, 0x01 },
{ STV090x_P1_CAR2CFG, 0x26 },
{ STV090x_P1_BCLC2S2Q, 0x86 },
{ STV090x_P1_BCLC2S28, 0x86 },
{ STV090x_P1_SMAPCOEF7, 0x77 },
{ STV090x_P1_SMAPCOEF6, 0x85 },
{ STV090x_P1_SMAPCOEF5, 0x77 },
{ STV090x_P1_DMDCFG2, 0x3b },
{ STV090x_P1_MODCODLST0, 0xff },
{ STV090x_P1_MODCODLST1, 0xff },
{ STV090x_P1_MODCODLST2, 0xff },
{ STV090x_P1_MODCODLST3, 0xff },
{ STV090x_P1_MODCODLST4, 0xff },
{ STV090x_P1_MODCODLST5, 0xff },
{ STV090x_P1_MODCODLST6, 0xff },
{ STV090x_P1_MODCODLST7, 0xcc },
{ STV090x_P1_MODCODLST8, 0xcc },
{ STV090x_P1_MODCODLST9, 0xcc },
{ STV090x_P1_MODCODLSTA, 0xcc },
{ STV090x_P1_MODCODLSTB, 0xcc },
{ STV090x_P1_MODCODLSTC, 0xcc },
{ STV090x_P1_MODCODLSTD, 0xcc },
{ STV090x_P1_MODCODLSTE, 0xcc },
{ STV090x_P1_MODCODLSTF, 0xcf },
{ STV090x_GENCFG, 0x1d },
{ STV090x_NBITER_NF4, 0x37 },
{ STV090x_NBITER_NF5, 0x29 },
{ STV090x_NBITER_NF6, 0x37 },
{ STV090x_NBITER_NF7, 0x33 },
{ STV090x_NBITER_NF8, 0x31 },
{ STV090x_NBITER_NF9, 0x2f },
{ STV090x_NBITER_NF10, 0x39 },
{ STV090x_NBITER_NF11, 0x3a },
{ STV090x_NBITER_NF12, 0x29 },
{ STV090x_NBITER_NF13, 0x37 },
{ STV090x_NBITER_NF14, 0x33 },
{ STV090x_NBITER_NF15, 0x2f },
{ STV090x_NBITER_NF16, 0x39 },
{ STV090x_NBITER_NF17, 0x3a },
{ STV090x_NBITERNOERR, 0x04 },
{ STV090x_GAINLLR_NF4, 0x0C },
{ STV090x_GAINLLR_NF5, 0x0F },
{ STV090x_GAINLLR_NF6, 0x11 },
{ STV090x_GAINLLR_NF7, 0x14 },
{ STV090x_GAINLLR_NF8, 0x17 },
{ STV090x_GAINLLR_NF9, 0x19 },
{ STV090x_GAINLLR_NF10, 0x20 },
{ STV090x_GAINLLR_NF11, 0x21 },
{ STV090x_GAINLLR_NF12, 0x0D },
{ STV090x_GAINLLR_NF13, 0x0F },
{ STV090x_GAINLLR_NF14, 0x13 },
{ STV090x_GAINLLR_NF15, 0x1A },
{ STV090x_GAINLLR_NF16, 0x1F },
{ STV090x_GAINLLR_NF17, 0x21 },
{ STV090x_RCCFGH, 0x20 },
{ STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
{ STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
{ STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
{ STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
};
static struct stv090x_reg stv0903_initval[] = {
{ STV090x_OUTCFG, 0x00 },
{ STV090x_AGCRF1CFG, 0x11 },
{ STV090x_STOPCLK1, 0x48 },
{ STV090x_STOPCLK2, 0x14 },
{ STV090x_TSTTNR1, 0x27 },
{ STV090x_TSTTNR2, 0x21 },
{ STV090x_P1_DISTXCTL, 0x22 },
{ STV090x_P1_F22TX, 0xc0 },
{ STV090x_P1_F22RX, 0xc0 },
{ STV090x_P1_DISRXCTL, 0x00 },
{ STV090x_P1_DMDCFGMD, 0xF9 },
{ STV090x_P1_DEMOD, 0x08 },
{ STV090x_P1_DMDCFG3, 0xc4 },
{ STV090x_P1_CARFREQ, 0xed },
{ STV090x_P1_TNRCFG2, 0x82 },
{ STV090x_P1_LDT, 0xd0 },
{ STV090x_P1_LDT2, 0xb8 },
{ STV090x_P1_TMGCFG, 0xd2 },
{ STV090x_P1_TMGTHRISE, 0x20 },
{ STV090x_P1_TMGTHFALL, 0x00 },
{ STV090x_P1_SFRUPRATIO, 0xf0 },
{ STV090x_P1_SFRLOWRATIO, 0x70 },
{ STV090x_P1_TSCFGL, 0x20 },
{ STV090x_P1_FECSPY, 0x88 },
{ STV090x_P1_FSPYDATA, 0x3a },
{ STV090x_P1_FBERCPT4, 0x00 },
{ STV090x_P1_FSPYBER, 0x10 },
{ STV090x_P1_ERRCTRL1, 0x35 },
{ STV090x_P1_ERRCTRL2, 0xc1 },
{ STV090x_P1_CFRICFG, 0xf8 },
{ STV090x_P1_NOSCFG, 0x1c },
{ STV090x_P1_DMDTOM, 0x20 },
{ STV090x_P1_CORRELMANT, 0x70 },
{ STV090x_P1_CORRELABS, 0x88 },
{ STV090x_P1_AGC2O, 0x5b },
{ STV090x_P1_AGC2REF, 0x38 },
{ STV090x_P1_CARCFG, 0xe4 },
{ STV090x_P1_ACLC, 0x1A },
{ STV090x_P1_BCLC, 0x09 },
{ STV090x_P1_CARHDR, 0x08 },
{ STV090x_P1_KREFTMG, 0xc1 },
{ STV090x_P1_SFRSTEP, 0x58 },
{ STV090x_P1_TMGCFG2, 0x01 },
{ STV090x_P1_CAR2CFG, 0x26 },
{ STV090x_P1_BCLC2S2Q, 0x86 },
{ STV090x_P1_BCLC2S28, 0x86 },
{ STV090x_P1_SMAPCOEF7, 0x77 },
{ STV090x_P1_SMAPCOEF6, 0x85 },
{ STV090x_P1_SMAPCOEF5, 0x77 },
{ STV090x_P1_DMDCFG2, 0x3b },
{ STV090x_P1_MODCODLST0, 0xff },
{ STV090x_P1_MODCODLST1, 0xff },
{ STV090x_P1_MODCODLST2, 0xff },
{ STV090x_P1_MODCODLST3, 0xff },
{ STV090x_P1_MODCODLST4, 0xff },
{ STV090x_P1_MODCODLST5, 0xff },
{ STV090x_P1_MODCODLST6, 0xff },
{ STV090x_P1_MODCODLST7, 0xcc },
{ STV090x_P1_MODCODLST8, 0xcc },
{ STV090x_P1_MODCODLST9, 0xcc },
{ STV090x_P1_MODCODLSTA, 0xcc },
{ STV090x_P1_MODCODLSTB, 0xcc },
{ STV090x_P1_MODCODLSTC, 0xcc },
{ STV090x_P1_MODCODLSTD, 0xcc },
{ STV090x_P1_MODCODLSTE, 0xcc },
{ STV090x_P1_MODCODLSTF, 0xcf },
{ STV090x_GENCFG, 0x1c },
{ STV090x_NBITER_NF4, 0x37 },
{ STV090x_NBITER_NF5, 0x29 },
{ STV090x_NBITER_NF6, 0x37 },
{ STV090x_NBITER_NF7, 0x33 },
{ STV090x_NBITER_NF8, 0x31 },
{ STV090x_NBITER_NF9, 0x2f },
{ STV090x_NBITER_NF10, 0x39 },
{ STV090x_NBITER_NF11, 0x3a },
{ STV090x_NBITER_NF12, 0x29 },
{ STV090x_NBITER_NF13, 0x37 },
{ STV090x_NBITER_NF14, 0x33 },
{ STV090x_NBITER_NF15, 0x2f },
{ STV090x_NBITER_NF16, 0x39 },
{ STV090x_NBITER_NF17, 0x3a },
{ STV090x_NBITERNOERR, 0x04 },
{ STV090x_GAINLLR_NF4, 0x0C },
{ STV090x_GAINLLR_NF5, 0x0F },
{ STV090x_GAINLLR_NF6, 0x11 },
{ STV090x_GAINLLR_NF7, 0x14 },
{ STV090x_GAINLLR_NF8, 0x17 },
{ STV090x_GAINLLR_NF9, 0x19 },
{ STV090x_GAINLLR_NF10, 0x20 },
{ STV090x_GAINLLR_NF11, 0x21 },
{ STV090x_GAINLLR_NF12, 0x0D },
{ STV090x_GAINLLR_NF13, 0x0F },
{ STV090x_GAINLLR_NF14, 0x13 },
{ STV090x_GAINLLR_NF15, 0x1A },
{ STV090x_GAINLLR_NF16, 0x1F },
{ STV090x_GAINLLR_NF17, 0x21 },
{ STV090x_RCCFGH, 0x20 },
{ STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
{ STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
};
static struct stv090x_reg stv0900_cut20_val[] = {
{ STV090x_P2_DMDCFG3, 0xe8 },
{ STV090x_P2_DMDCFG4, 0x10 },
{ STV090x_P2_CARFREQ, 0x38 },
{ STV090x_P2_CARHDR, 0x20 },
{ STV090x_P2_KREFTMG, 0x5a },
{ STV090x_P2_SMAPCOEF7, 0x06 },
{ STV090x_P2_SMAPCOEF6, 0x00 },
{ STV090x_P2_SMAPCOEF5, 0x04 },
{ STV090x_P2_NOSCFG, 0x0c },
{ STV090x_P1_DMDCFG3, 0xe8 },
{ STV090x_P1_DMDCFG4, 0x10 },
{ STV090x_P1_CARFREQ, 0x38 },
{ STV090x_P1_CARHDR, 0x20 },
{ STV090x_P1_KREFTMG, 0x5a },
{ STV090x_P1_SMAPCOEF7, 0x06 },
{ STV090x_P1_SMAPCOEF6, 0x00 },
{ STV090x_P1_SMAPCOEF5, 0x04 },
{ STV090x_P1_NOSCFG, 0x0c },
{ STV090x_GAINLLR_NF4, 0x21 },
{ STV090x_GAINLLR_NF5, 0x21 },
{ STV090x_GAINLLR_NF6, 0x20 },
{ STV090x_GAINLLR_NF7, 0x1F },
{ STV090x_GAINLLR_NF8, 0x1E },
{ STV090x_GAINLLR_NF9, 0x1E },
{ STV090x_GAINLLR_NF10, 0x1D },
{ STV090x_GAINLLR_NF11, 0x1B },
{ STV090x_GAINLLR_NF12, 0x20 },
{ STV090x_GAINLLR_NF13, 0x20 },
{ STV090x_GAINLLR_NF14, 0x20 },
{ STV090x_GAINLLR_NF15, 0x20 },
{ STV090x_GAINLLR_NF16, 0x20 },
{ STV090x_GAINLLR_NF17, 0x21 },
};
static struct stv090x_reg stv0903_cut20_val[] = {
{ STV090x_P1_DMDCFG3, 0xe8 },
{ STV090x_P1_DMDCFG4, 0x10 },
{ STV090x_P1_CARFREQ, 0x38 },
{ STV090x_P1_CARHDR, 0x20 },
{ STV090x_P1_KREFTMG, 0x5a },
{ STV090x_P1_SMAPCOEF7, 0x06 },
{ STV090x_P1_SMAPCOEF6, 0x00 },
{ STV090x_P1_SMAPCOEF5, 0x04 },
{ STV090x_P1_NOSCFG, 0x0c },
{ STV090x_GAINLLR_NF4, 0x21 },
{ STV090x_GAINLLR_NF5, 0x21 },
{ STV090x_GAINLLR_NF6, 0x20 },
{ STV090x_GAINLLR_NF7, 0x1F },
{ STV090x_GAINLLR_NF8, 0x1E },
{ STV090x_GAINLLR_NF9, 0x1E },
{ STV090x_GAINLLR_NF10, 0x1D },
{ STV090x_GAINLLR_NF11, 0x1B },
{ STV090x_GAINLLR_NF12, 0x20 },
{ STV090x_GAINLLR_NF13, 0x20 },
{ STV090x_GAINLLR_NF14, 0x20 },
{ STV090x_GAINLLR_NF15, 0x20 },
{ STV090x_GAINLLR_NF16, 0x20 },
{ STV090x_GAINLLR_NF17, 0x21 }
};
/* Cut 2.0 Long Frame Tracking CR loop */
static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
{ STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
{ STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
{ STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
{ STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
{ STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
{ STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
{ STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
{ STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
};
/* Cut 3.0 Long Frame Tracking CR loop */
static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
{ STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
{ STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
{ STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
{ STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
{ STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
{ STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
{ STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
{ STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
{ STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
{ STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
{ STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
{ STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
{ STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
};
/* Cut 2.0 Long Frame Tracking CR Loop */
static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
{ STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
{ STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
{ STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
{ STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
{ STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
{ STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
{ STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
{ STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
{ STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
{ STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
};
/* Cut 3.0 Long Frame Tracking CR Loop */
static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
{ STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
{ STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
{ STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
{ STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
{ STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
{ STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
{ STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
{ STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
{ STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
{ STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
};
static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
{ STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
{ STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
};
static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
/* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
{ STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
{ STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
{ STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
};
/* Cut 2.0 Short Frame Tracking CR Loop */
static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
/* MODCOD 2M 5M 10M 20M 30M */
{ STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
{ STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
{ STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
{ STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
};
/* Cut 3.0 Short Frame Tracking CR Loop */
static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
/* MODCOD 2M 5M 10M 20M 30M */
{ STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
{ STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
{ STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
{ STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
};
static inline s32 comp2(s32 __x, s32 __width)
{
if (__width == 32)
return __x;
else
return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
}
static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
{
const struct stv090x_config *config = state->config;
int ret;
u8 b0[] = { reg >> 8, reg & 0xff };
u8 buf;
struct i2c_msg msg[] = {
{ .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
{ .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
if (ret != -ERESTARTSYS)
dprintk(FE_ERROR, 1,
"Read error, Reg=[0x%02x], Status=%d",
reg, ret);
return ret < 0 ? ret : -EREMOTEIO;
}
if (unlikely(*state->verbose >= FE_DEBUGREG))
dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
reg, buf);
return (unsigned int) buf;
}
static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
{
const struct stv090x_config *config = state->config;
int ret;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
if (2 + count > sizeof(buf)) {
printk(KERN_WARNING
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, count);
return -EINVAL;
}
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
memcpy(&buf[2], data, count);
dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph",
__func__, reg, count, data);
ret = i2c_transfer(state->i2c, &i2c_msg, 1);
if (ret != 1) {
if (ret != -ERESTARTSYS)
dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
reg, data[0], count, ret);
return ret < 0 ? ret : -EREMOTEIO;
}
return 0;
}
static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
{
u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return stv090x_write_regs(state, reg, &tmp, 1);
}
static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
{
u32 reg;
/*
* NOTE! A lock is used as a FSM to control the state in which
* access is serialized between two tuners on the same demod.
* This has nothing to do with a lock to protect a critical section
* which may in some other cases be confused with protecting I/O
* access to the demodulator gate.
* In case of any error, the lock is unlocked and exit within the
* relevant operations themselves.
*/
if (enable) {
if (state->config->tuner_i2c_lock)
state->config->tuner_i2c_lock(&state->frontend, 1);
else
mutex_lock(&state->internal->tuner_lock);
}
reg = STV090x_READ_DEMOD(state, I2CRPT);
if (enable) {
dprintk(FE_DEBUG, 1, "Enable Gate");
STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
goto err;
} else {
dprintk(FE_DEBUG, 1, "Disable Gate");
STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
goto err;
}
if (!enable) {
if (state->config->tuner_i2c_lock)
state->config->tuner_i2c_lock(&state->frontend, 0);
else
mutex_unlock(&state->internal->tuner_lock);
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
if (state->config->tuner_i2c_lock)
state->config->tuner_i2c_lock(&state->frontend, 0);
else
mutex_unlock(&state->internal->tuner_lock);
return -1;
}
static void stv090x_get_lock_tmg(struct stv090x_state *state)
{
switch (state->algo) {
case STV090x_BLIND_SEARCH:
dprintk(FE_DEBUG, 1, "Blind Search");
if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
state->DemodTimeout = 1500;
state->FecTimeout = 400;
} else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
state->DemodTimeout = 1000;
state->FecTimeout = 300;
} else { /*SR >20Msps*/
state->DemodTimeout = 700;
state->FecTimeout = 100;
}
break;
case STV090x_COLD_SEARCH:
case STV090x_WARM_SEARCH:
default:
dprintk(FE_DEBUG, 1, "Normal Search");
if (state->srate <= 1000000) { /*SR <=1Msps*/
state->DemodTimeout = 4500;
state->FecTimeout = 1700;
} else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
state->DemodTimeout = 2500;
state->FecTimeout = 1100;
} else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
state->DemodTimeout = 1000;
state->FecTimeout = 550;
} else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
state->DemodTimeout = 700;
state->FecTimeout = 250;
} else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
state->DemodTimeout = 400;
state->FecTimeout = 130;
} else { /*SR >20Msps*/
state->DemodTimeout = 300;
state->FecTimeout = 100;
}
break;
}
if (state->algo == STV090x_WARM_SEARCH)
state->DemodTimeout /= 2;
}
static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
{
u32 sym;
if (srate > 60000000) {
sym = (srate << 4); /* SR * 2^16 / master_clk */
sym /= (state->internal->mclk >> 12);
} else if (srate > 6000000) {
sym = (srate << 6);
sym /= (state->internal->mclk >> 10);
} else {
sym = (srate << 9);
sym /= (state->internal->mclk >> 7);
}
if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
{
u32 sym;
srate = 105 * (srate / 100);
if (srate > 60000000) {
sym = (srate << 4); /* SR * 2^16 / master_clk */
sym /= (state->internal->mclk >> 12);
} else if (srate > 6000000) {
sym = (srate << 6);
sym /= (state->internal->mclk >> 10);
} else {
sym = (srate << 9);
sym /= (state->internal->mclk >> 7);
}
if (sym < 0x7fff) {
if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
goto err;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
{
u32 sym;
srate = 95 * (srate / 100);
if (srate > 60000000) {
sym = (srate << 4); /* SR * 2^16 / master_clk */
sym /= (state->internal->mclk >> 12);
} else if (srate > 6000000) {
sym = (srate << 6);
sym /= (state->internal->mclk >> 10);
} else {
sym = (srate << 9);
sym /= (state->internal->mclk >> 7);
}
if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
{
u32 ro;
switch (rolloff) {
case STV090x_RO_20:
ro = 20;
break;
case STV090x_RO_25:
ro = 25;
break;
case STV090x_RO_35:
default:
ro = 35;
break;
}
return srate + (srate * ro) / 100;
}
static int stv090x_set_vit_thacq(struct stv090x_state *state)
{
if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_vit_thtracq(struct stv090x_state *state)
{
if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_viterbi(struct stv090x_state *state)
{
switch (state->search_mode) {
case STV090x_SEARCH_AUTO:
if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
goto err;
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
goto err;
break;
case STV090x_SEARCH_DVBS1:
if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
goto err;
switch (state->fec) {
case STV090x_PR12:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
goto err;
break;
case STV090x_PR23:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
goto err;
break;
case STV090x_PR34:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
goto err;
break;
case STV090x_PR56:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
goto err;
break;
case STV090x_PR78:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
goto err;
break;
default:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
goto err;
break;
}
break;
case STV090x_SEARCH_DSS:
if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
goto err;
switch (state->fec) {
case STV090x_PR12:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
goto err;
break;
case STV090x_PR23:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
goto err;
break;
case STV090x_PR67:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
goto err;
break;
default:
if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
goto err;
break;
}
break;
default:
break;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_stop_modcod(struct stv090x_state *state)
{
if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_activate_modcod(struct stv090x_state *state)
{
if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_activate_modcod_single(struct stv090x_state *state)
{
if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
{
u32 reg;
switch (state->demod) {
case STV090x_DEMODULATOR_0:
mutex_lock(&state->internal->demod_lock);
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err;
mutex_unlock(&state->internal->demod_lock);
break;
case STV090x_DEMODULATOR_1:
mutex_lock(&state->internal->demod_lock);
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err;
mutex_unlock(&state->internal->demod_lock);
break;
default:
dprintk(FE_ERROR, 1, "Wrong demodulator!");
break;
}
return 0;
err:
mutex_unlock(&state->internal->demod_lock);
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_dvbs_track_crl(struct stv090x_state *state)
{
if (state->internal->dev_ver >= 0x30) {
/* Set ACLC BCLC optimised value vs SR */
if (state->srate >= 15000000) {
if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
goto err;
} else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
goto err;
} else if (state->srate < 7000000) {
if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
goto err;
}
} else {
/* Cut 2.0 */
if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
goto err;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_delivery_search(struct stv090x_state *state)
{
u32 reg;
switch (state->search_mode) {
case STV090x_SEARCH_DVBS1:
case STV090x_SEARCH_DSS:
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
/* Activate Viterbi decoder in legacy search,
* do not use FRESVIT1, might impact VITERBI2
*/
if (stv090x_vitclk_ctl(state, 0) < 0)
goto err;
if (stv090x_dvbs_track_crl(state) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
goto err;
if (stv090x_set_vit_thacq(state) < 0)
goto err;
if (stv090x_set_viterbi(state) < 0)
goto err;
break;
case STV090x_SEARCH_DVBS2:
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (stv090x_vitclk_ctl(state, 1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
goto err;
if (state->internal->dev_ver <= 0x20) {
/* enable S2 carrier loop */
if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
goto err;
} else {
/* > Cut 3: Stop carrier 3 */
if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
goto err;
}
if (state->demod_mode != STV090x_SINGLE) {
/* Cut 2: enable link during search */
if (stv090x_activate_modcod(state) < 0)
goto err;
} else {
/* Single demodulator
* Authorize SHORT and LONG frames,
* QPSK, 8PSK, 16APSK and 32APSK
*/
if (stv090x_activate_modcod_single(state) < 0)
goto err;
}
if (stv090x_set_vit_thtracq(state) < 0)
goto err;
break;
case STV090x_SEARCH_AUTO:
default:
/* enable DVB-S2 and DVB-S2 in Auto MODE */
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (stv090x_vitclk_ctl(state, 0) < 0)
goto err;
if (stv090x_dvbs_track_crl(state) < 0)
goto err;
if (state->internal->dev_ver <= 0x20) {
/* enable S2 carrier loop */
if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
goto err;
} else {
/* > Cut 3: Stop carrier 3 */
if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
goto err;
}
if (state->demod_mode != STV090x_SINGLE) {
/* Cut 2: enable link during search */
if (stv090x_activate_modcod(state) < 0)
goto err;
} else {
/* Single demodulator
* Authorize SHORT and LONG frames,
* QPSK, 8PSK, 16APSK and 32APSK
*/
if (stv090x_activate_modcod_single(state) < 0)
goto err;
}
if (stv090x_set_vit_thacq(state) < 0)
goto err;
if (stv090x_set_viterbi(state) < 0)
goto err;
break;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_start_search(struct stv090x_state *state)
{
u32 reg, freq_abs;
s16 freq;
/* Reset demodulator */
reg = STV090x_READ_DEMOD(state, DMDISTATE);
STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
goto err;
if (state->internal->dev_ver <= 0x20) {
if (state->srate <= 5000000) {
if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
goto err;
/*enlarge the timing bandwidth for Low SR*/
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
goto err;
} else {
/* If the symbol rate is >5 Msps
Set The carrier search up and low to auto mode */
if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
goto err;
/*reduce the timing bandwidth for high SR*/
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
goto err;
}
} else {
/* >= Cut 3 */
if (state->srate <= 5000000) {
/* enlarge the timing bandwidth for Low SR */
STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
} else {
/* reduce timing bandwidth for high SR */
STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
}
/* Set CFR min and max to manual mode */
STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
if (state->algo == STV090x_WARM_SEARCH) {
/* WARM Start
* CFR min = -1MHz,
* CFR max = +1MHz
*/
freq_abs = 1000 << 16;
freq_abs /= (state->internal->mclk / 1000);
freq = (s16) freq_abs;
} else {
/* COLD Start
* CFR min =- (SearchRange / 2 + 600KHz)
* CFR max = +(SearchRange / 2 + 600KHz)
* (600KHz for the tuner step size)
*/
freq_abs = (state->search_range / 2000) + 600;
freq_abs = freq_abs << 16;
freq_abs /= (state->internal->mclk / 1000);
freq = (s16) freq_abs;
}
if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
goto err;
freq *= -1;
if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
goto err;
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
goto err;
if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
(state->search_mode == STV090x_SEARCH_DSS) ||
(state->search_mode == STV090x_SEARCH_AUTO)) {
if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
goto err;
}
}
if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFG2);
STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
goto err;
if (state->internal->dev_ver >= 0x20) {
/*Frequency offset detector setting*/
if (state->srate < 2000000) {
if (state->internal->dev_ver <= 0x20) {
/* Cut 2 */
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
goto err;
} else {
/* Cut 3 */
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
goto err;
} else if (state->srate < 10000000) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
goto err;
}
} else {
if (state->srate < 10000000) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
goto err;
}
}
switch (state->algo) {
case STV090x_WARM_SEARCH:
/* The symbol rate and the exact
* carrier Frequency are known
*/
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
goto err;
break;
case STV090x_COLD_SEARCH:
/* The symbol rate is known */
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
goto err;
break;
default:
break;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_get_agc2_min_level(struct stv090x_state *state)
{
u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
s32 i, j, steps, dir;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
goto err;
if (stv090x_set_srate(state, 1000000) < 0)
goto err;
steps = state->search_range / 1000000;
if (steps <= 0)
steps = 1;
dir = 1;
freq_step = (1000000 * 256) / (state->internal->mclk / 256);
freq_init = 0;
for (i = 0; i < steps; i++) {
if (dir > 0)
freq_init = freq_init + (freq_step * i);
else
freq_init = freq_init - (freq_step * i);
dir *= -1;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
goto err;
msleep(10);
agc2 = 0;
for (j = 0; j < 10; j++) {
agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
STV090x_READ_DEMOD(state, AGC2I0);
}
agc2 /= 10;
if (agc2 < agc2_min)
agc2_min = agc2;
}
return agc2_min;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
{
u8 r3, r2, r1, r0;
s32 srate, int_1, int_2, tmp_1, tmp_2;
r3 = STV090x_READ_DEMOD(state, SFR3);
r2 = STV090x_READ_DEMOD(state, SFR2);
r1 = STV090x_READ_DEMOD(state, SFR1);
r0 = STV090x_READ_DEMOD(state, SFR0);
srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
int_1 = clk >> 16;
int_2 = srate >> 16;
tmp_1 = clk % 0x10000;
tmp_2 = srate % 0x10000;
srate = (int_1 * int_2) +
((int_1 * tmp_2) >> 16) +
((int_2 * tmp_1) >> 16);
return srate;
}
static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
{
struct dvb_frontend *fe = &state->frontend;
int tmg_lock = 0, i;
s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
u32 agc2th;
if (state->internal->dev_ver >= 0x30)
agc2th = 0x2e00;
else
agc2th = 0x1f00;
reg = STV090x_READ_DEMOD(state, DMDISTATE);
STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
goto err;
if (state->internal->dev_ver >= 0x30) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
goto err;
} else if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
goto err;
}
if (state->srate <= 2000000)
car_step = 1000;
else if (state->srate <= 5000000)
car_step = 2000;
else if (state->srate <= 12000000)
car_step = 3000;
else
car_step = 5000;
steps = -1 + ((state->search_range / 1000) / car_step);
steps /= 2;
steps = (2 * steps) + 1;
if (steps < 0)
steps = 1;
else if (steps > 10) {
steps = 11;
car_step = (state->search_range / 1000) / 10;
}
cur_step = 0;
dir = 1;
freq = state->frequency;
while ((!tmg_lock) && (cur_step < steps)) {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
goto err;
/* trigger acquisition */
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
goto err;
msleep(50);
for (i = 0; i < 10; i++) {
reg = STV090x_READ_DEMOD(state, DSTATUS);
if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
tmg_cpt++;
agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
STV090x_READ_DEMOD(state, AGC2I0);
}
agc2 /= 10;
srate_coarse = stv090x_get_srate(state, state->internal->mclk);
cur_step++;
dir *= -1;
if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
(srate_coarse < 50000000) && (srate_coarse > 850000))
tmg_lock = 1;
else if (cur_step < steps) {
if (dir > 0)
freq += cur_step * car_step;
else
freq -= cur_step * car_step;
/* Setup tuner */
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_set_frequency) {
if (state->config->tuner_set_frequency(fe, freq) < 0)
goto err_gateoff;
}
if (state->config->tuner_set_bandwidth) {
if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
msleep(50);
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_get_status) {
if (state->config->tuner_get_status(fe, ®) < 0)
goto err_gateoff;
}
if (reg)
dprintk(FE_DEBUG, 1, "Tuner phase locked");
else
dprintk(FE_DEBUG, 1, "Tuner unlocked");
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
}
}
if (!tmg_lock)
srate_coarse = 0;
else
srate_coarse = stv090x_get_srate(state, state->internal->mclk);
return srate_coarse;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
{
u32 srate_coarse, freq_coarse, sym, reg;
srate_coarse = stv090x_get_srate(state, state->internal->mclk);
freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
if (sym < state->srate)
srate_coarse = 0;
else {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
if (state->internal->dev_ver >= 0x30) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
goto err;
} else if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
goto err;
}
if (srate_coarse > 3000000) {
sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
sym = (sym / 1000) * 65536;
sym /= (state->internal->mclk / 1000);
if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
goto err;
sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
sym = (sym / 1000) * 65536;
sym /= (state->internal->mclk / 1000);
if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
goto err;
sym = (srate_coarse / 1000) * 65536;
sym /= (state->internal->mclk / 1000);
if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
goto err;
} else {
sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
sym = (sym / 100) * 65536;
sym /= (state->internal->mclk / 100);
if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
goto err;
sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
sym = (sym / 100) * 65536;
sym /= (state->internal->mclk / 100);
if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
goto err;
sym = (srate_coarse / 100) * 65536;
sym /= (state->internal->mclk / 100);
if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
goto err;
}
return srate_coarse;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
{
s32 timer = 0, lock = 0;
u32 reg;
u8 stat;
while ((timer < timeout) && (!lock)) {
reg = STV090x_READ_DEMOD(state, DMDSTATE);
stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
switch (stat) {
case 0: /* searching */
case 1: /* first PLH detected */
default:
dprintk(FE_DEBUG, 1, "Demodulator searching ..");
lock = 0;
break;
case 2: /* DVB-S2 mode */
case 3: /* DVB-S1/legacy mode */
reg = STV090x_READ_DEMOD(state, DSTATUS);
lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
break;
}
if (!lock)
msleep(10);
else
dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
timer += 10;
}
return lock;
}
static int stv090x_blind_search(struct stv090x_state *state)
{
u32 agc2, reg, srate_coarse;
s32 cpt_fail, agc2_ovflw, i;
u8 k_ref, k_max, k_min;
int coarse_fail = 0;
int lock;
k_max = 110;
k_min = 10;
agc2 = stv090x_get_agc2_min_level(state);
if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
lock = 0;
} else {
if (state->internal->dev_ver <= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
goto err;
} else {
/* > Cut 3 */
if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
goto err;
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
goto err;
}
k_ref = k_max;
do {
if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
goto err;
if (stv090x_srate_srch_coarse(state) != 0) {
srate_coarse = stv090x_srate_srch_fine(state);
if (srate_coarse != 0) {
stv090x_get_lock_tmg(state);
lock = stv090x_get_dmdlock(state,
state->DemodTimeout);
} else {
lock = 0;
}
} else {
cpt_fail = 0;
agc2_ovflw = 0;
for (i = 0; i < 10; i++) {
agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
STV090x_READ_DEMOD(state, AGC2I0);
if (agc2 >= 0xff00)
agc2_ovflw++;
reg = STV090x_READ_DEMOD(state, DSTATUS2);
if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
(STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
cpt_fail++;
}
if ((cpt_fail > 7) || (agc2_ovflw > 7))
coarse_fail = 1;
lock = 0;
}
k_ref -= 20;
} while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
}
return lock;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_chk_tmg(struct stv090x_state *state)
{
u32 reg;
s32 tmg_cpt = 0, i;
u8 freq, tmg_thh, tmg_thl;
int tmg_lock = 0;
freq = STV090x_READ_DEMOD(state, CARFREQ);
tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
goto err;
msleep(10);
for (i = 0; i < 10; i++) {
reg = STV090x_READ_DEMOD(state, DSTATUS);
if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
tmg_cpt++;
msleep(1);
}
if (tmg_cpt >= 3)
tmg_lock = 1;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
goto err;
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
goto err;
if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
goto err;
return tmg_lock;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
{
struct dvb_frontend *fe = &state->frontend;
u32 reg;
s32 car_step, steps, cur_step, dir, freq, timeout_lock;
int lock;
if (state->srate >= 10000000)
timeout_lock = timeout_dmd / 3;
else
timeout_lock = timeout_dmd / 2;
lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
if (lock)
return lock;
if (state->srate >= 10000000) {
if (stv090x_chk_tmg(state)) {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
goto err;
return stv090x_get_dmdlock(state, timeout_dmd);
}
return 0;
}
if (state->srate <= 4000000)
car_step = 1000;
else if (state->srate <= 7000000)
car_step = 2000;
else if (state->srate <= 10000000)
car_step = 3000;
else
car_step = 5000;
steps = (state->search_range / 1000) / car_step;
steps /= 2;
steps = 2 * (steps + 1);
if (steps < 0)
steps = 2;
else if (steps > 12)
steps = 12;
cur_step = 1;
dir = 1;
freq = state->frequency;
state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
while ((cur_step <= steps) && (!lock)) {
if (dir > 0)
freq += cur_step * car_step;
else
freq -= cur_step * car_step;
/* Setup tuner */
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_set_frequency) {
if (state->config->tuner_set_frequency(fe, freq) < 0)
goto err_gateoff;
}
if (state->config->tuner_set_bandwidth) {
if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
msleep(50);
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_get_status) {
if (state->config->tuner_get_status(fe, ®) < 0)
goto err_gateoff;
if (reg)
dprintk(FE_DEBUG, 1, "Tuner phase locked");
else
dprintk(FE_DEBUG, 1, "Tuner unlocked");
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
goto err;
lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
dir *= -1;
cur_step++;
}
return lock;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
{
s32 timeout, inc, steps_max, srate, car_max;
srate = state->srate;
car_max = state->search_range / 1000;
car_max += car_max / 10;
car_max = 65536 * (car_max / 2);
car_max /= (state->internal->mclk / 1000);
if (car_max > 0x4000)
car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
inc = srate;
inc /= state->internal->mclk / 1000;
inc *= 256;
inc *= 256;
inc /= 1000;
switch (state->search_mode) {
case STV090x_SEARCH_DVBS1:
case STV090x_SEARCH_DSS:
inc *= 3; /* freq step = 3% of srate */
timeout = 20;
break;
case STV090x_SEARCH_DVBS2:
inc *= 4;
timeout = 25;
break;
case STV090x_SEARCH_AUTO:
default:
inc *= 3;
timeout = 25;
break;
}
inc /= 100;
if ((inc > car_max) || (inc < 0))
inc = car_max / 2; /* increment <= 1/8 Mclk */
timeout *= 27500; /* 27.5 Msps reference */
if (srate > 0)
timeout /= (srate / 1000);
if ((timeout > 100) || (timeout < 0))
timeout = 100;
steps_max = (car_max / inc) + 1; /* min steps = 3 */
if ((steps_max > 100) || (steps_max < 0)) {
steps_max = 100; /* max steps <= 100 */
inc = car_max / steps_max;
}
*freq_inc = inc;
*timeout_sw = timeout;
*steps = steps_max;
return 0;
}
static int stv090x_chk_signal(struct stv090x_state *state)
{
s32 offst_car, agc2, car_max;
int no_signal;
offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
offst_car |= STV090x_READ_DEMOD(state, CFR1);
offst_car = comp2(offst_car, 16);
agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
car_max = state->search_range / 1000;
car_max += (car_max / 10); /* 10% margin */
car_max = (65536 * car_max / 2);
car_max /= state->internal->mclk / 1000;
if (car_max > 0x4000)
car_max = 0x4000;
if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
no_signal = 1;
dprintk(FE_DEBUG, 1, "No Signal");
} else {
no_signal = 0;
dprintk(FE_DEBUG, 1, "Found Signal");
}
return no_signal;
}
static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
{
int no_signal, lock = 0;
s32 cpt_step = 0, offst_freq, car_max;
u32 reg;
car_max = state->search_range / 1000;
car_max += (car_max / 10);
car_max = (65536 * car_max / 2);
car_max /= (state->internal->mclk / 1000);
if (car_max > 0x4000)
car_max = 0x4000;
if (zigzag)
offst_freq = 0;
else
offst_freq = -car_max + inc;
do {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, PDELCTRL1);
STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
if (zigzag) {
if (offst_freq >= 0)
offst_freq = -offst_freq - 2 * inc;
else
offst_freq = -offst_freq;
} else {
offst_freq += 2 * inc;
}
cpt_step++;
lock = stv090x_get_dmdlock(state, timeout);
no_signal = stv090x_chk_signal(state);
} while ((!lock) &&
(!no_signal) &&
((offst_freq - inc) < car_max) &&
((offst_freq + inc) > -car_max) &&
(cpt_step < steps_max));
reg = STV090x_READ_DEMOD(state, PDELCTRL1);
STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
return lock;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_sw_algo(struct stv090x_state *state)
{
int no_signal, zigzag, lock = 0;
u32 reg;
s32 dvbs2_fly_wheel;
s32 inc, timeout_step, trials, steps_max;
/* get params */
stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
switch (state->search_mode) {
case STV090x_SEARCH_DVBS1:
case STV090x_SEARCH_DSS:
/* accelerate the frequency detector */
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
goto err;
zigzag = 0;
break;
case STV090x_SEARCH_DVBS2:
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
goto err;
zigzag = 1;
break;
case STV090x_SEARCH_AUTO:
default:
/* accelerate the frequency detector */
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
goto err;
zigzag = 0;
break;
}
trials = 0;
do {
lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
no_signal = stv090x_chk_signal(state);
trials++;
/*run the SW search 2 times maximum*/
if (lock || no_signal || (trials == 2)) {
/*Check if the demod is not losing lock in DVBS2*/
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
goto err;
}
reg = STV090x_READ_DEMOD(state, DMDSTATE);
if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
/*Check if the demod is not losing lock in DVBS2*/
msleep(timeout_step);
reg = STV090x_READ_DEMOD(state, DMDFLYW);
dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
msleep(timeout_step);
reg = STV090x_READ_DEMOD(state, DMDFLYW);
dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
}
if (dvbs2_fly_wheel < 0xd) {
/*FALSE lock, The demod is losing lock */
lock = 0;
if (trials < 2) {
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
goto err;
}
}
}
}
} while ((!lock) && (trials < 2) && (!no_signal));
return lock;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
{
u32 reg;
enum stv090x_delsys delsys;
reg = STV090x_READ_DEMOD(state, DMDSTATE);
if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
delsys = STV090x_DVBS2;
else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
reg = STV090x_READ_DEMOD(state, FECM);
if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
delsys = STV090x_DSS;
else
delsys = STV090x_DVBS1;
} else {
delsys = STV090x_ERROR;
}
return delsys;
}
/* in Hz */
static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
{
s32 derot, int_1, int_2, tmp_1, tmp_2;
derot = STV090x_READ_DEMOD(state, CFR2) << 16;
derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
derot |= STV090x_READ_DEMOD(state, CFR0);
derot = comp2(derot, 24);
int_1 = mclk >> 12;
int_2 = derot >> 12;
/* carrier_frequency = MasterClock * Reg / 2^24 */
tmp_1 = mclk % 0x1000;
tmp_2 = derot % 0x1000;
derot = (int_1 * int_2) +
((int_1 * tmp_2) >> 12) +
((int_2 * tmp_1) >> 12);
return derot;
}
static int stv090x_get_viterbi(struct stv090x_state *state)
{
u32 reg, rate;
reg = STV090x_READ_DEMOD(state, VITCURPUN);
rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
switch (rate) {
case 13:
state->fec = STV090x_PR12;
break;
case 18:
state->fec = STV090x_PR23;
break;
case 21:
state->fec = STV090x_PR34;
break;
case 24:
state->fec = STV090x_PR56;
break;
case 25:
state->fec = STV090x_PR67;
break;
case 26:
state->fec = STV090x_PR78;
break;
default:
state->fec = STV090x_PRERR;
break;
}
return 0;
}
static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
{
struct dvb_frontend *fe = &state->frontend;
u8 tmg;
u32 reg;
s32 i = 0, offst_freq;
msleep(5);
if (state->algo == STV090x_BLIND_SEARCH) {
tmg = STV090x_READ_DEMOD(state, TMGREG2);
STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
tmg = STV090x_READ_DEMOD(state, TMGREG2);
msleep(5);
i += 5;
}
}
state->delsys = stv090x_get_std(state);
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_get_frequency) {
if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
state->frequency += offst_freq;
if (stv090x_get_viterbi(state) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDMODCOD);
state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
reg = STV090x_READ_DEMOD(state, TMGOBS);
state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
reg = STV090x_READ_DEMOD(state, FECM);
state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_get_frequency) {
if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
return STV090x_RANGEOK;
else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
return STV090x_RANGEOK;
} else {
if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
return STV090x_RANGEOK;
}
return STV090x_OUTOFRANGE;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
{
s32 offst_tmg;
offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
if (!offst_tmg)
offst_tmg = 1;
offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
offst_tmg /= 320;
return offst_tmg;
}
static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
{
u8 aclc = 0x29;
s32 i;
struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
if (state->internal->dev_ver == 0x20) {
car_loop = stv090x_s2_crl_cut20;
car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
} else {
/* >= Cut 3 */
car_loop = stv090x_s2_crl_cut30;
car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
}
if (modcod < STV090x_QPSK_12) {
i = 0;
while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
i++;
if (i >= 3)
i = 2;
} else {
i = 0;
while ((i < 14) && (modcod != car_loop[i].modcod))
i++;
if (i >= 14) {
i = 0;
while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
i++;
if (i >= 11)
i = 10;
}
}
if (modcod <= STV090x_QPSK_25) {
if (pilots) {
if (state->srate <= 3000000)
aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
else if (state->srate <= 7000000)
aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
else if (state->srate <= 15000000)
aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
else if (state->srate <= 25000000)
aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
else
aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
} else {
if (state->srate <= 3000000)
aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
else if (state->srate <= 7000000)
aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
else if (state->srate <= 15000000)
aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
else if (state->srate <= 25000000)
aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
else
aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
}
} else if (modcod <= STV090x_8PSK_910) {
if (pilots) {
if (state->srate <= 3000000)
aclc = car_loop[i].crl_pilots_on_2;
else if (state->srate <= 7000000)
aclc = car_loop[i].crl_pilots_on_5;
else if (state->srate <= 15000000)
aclc = car_loop[i].crl_pilots_on_10;
else if (state->srate <= 25000000)
aclc = car_loop[i].crl_pilots_on_20;
else
aclc = car_loop[i].crl_pilots_on_30;
} else {
if (state->srate <= 3000000)
aclc = car_loop[i].crl_pilots_off_2;
else if (state->srate <= 7000000)
aclc = car_loop[i].crl_pilots_off_5;
else if (state->srate <= 15000000)
aclc = car_loop[i].crl_pilots_off_10;
else if (state->srate <= 25000000)
aclc = car_loop[i].crl_pilots_off_20;
else
aclc = car_loop[i].crl_pilots_off_30;
}
} else { /* 16APSK and 32APSK */
/*
* This should never happen in practice, except if
* something is really wrong at the car_loop table.
*/
if (i >= 11)
i = 10;
if (state->srate <= 3000000)
aclc = car_loop_apsk_low[i].crl_pilots_on_2;
else if (state->srate <= 7000000)
aclc = car_loop_apsk_low[i].crl_pilots_on_5;
else if (state->srate <= 15000000)
aclc = car_loop_apsk_low[i].crl_pilots_on_10;
else if (state->srate <= 25000000)
aclc = car_loop_apsk_low[i].crl_pilots_on_20;
else
aclc = car_loop_apsk_low[i].crl_pilots_on_30;
}
return aclc;
}
static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
{
struct stv090x_short_frame_crloop *short_crl = NULL;
s32 index = 0;
u8 aclc = 0x0b;
switch (state->modulation) {
case STV090x_QPSK:
default:
index = 0;
break;
case STV090x_8PSK:
index = 1;
break;
case STV090x_16APSK:
index = 2;
break;
case STV090x_32APSK:
index = 3;
break;
}
if (state->internal->dev_ver >= 0x30) {
/* Cut 3.0 and up */
short_crl = stv090x_s2_short_crl_cut30;
} else {
/* Cut 2.0 and up: we don't support cuts older than 2.0 */
short_crl = stv090x_s2_short_crl_cut20;
}
if (state->srate <= 3000000)
aclc = short_crl[index].crl_2;
else if (state->srate <= 7000000)
aclc = short_crl[index].crl_5;
else if (state->srate <= 15000000)
aclc = short_crl[index].crl_10;
else if (state->srate <= 25000000)
aclc = short_crl[index].crl_20;
else
aclc = short_crl[index].crl_30;
return aclc;
}
static int stv090x_optimize_track(struct stv090x_state *state)
{
struct dvb_frontend *fe = &state->frontend;
enum stv090x_modcod modcod;
s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
u32 reg;
srate = stv090x_get_srate(state, state->internal->mclk);
srate += stv090x_get_tmgoffst(state, srate);
switch (state->delsys) {
case STV090x_DVBS1:
case STV090x_DSS:
if (state->search_mode == STV090x_SEARCH_AUTO) {
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
}
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
goto err;
if (state->internal->dev_ver >= 0x30) {
if (stv090x_get_viterbi(state) < 0)
goto err;
if (state->fec == STV090x_PR12) {
if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
goto err;
}
}
if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
goto err;
break;
case STV090x_DVBS2:
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (state->internal->dev_ver >= 0x30) {
if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
goto err;
}
if (state->frame_len == STV090x_LONG_FRAME) {
reg = STV090x_READ_DEMOD(state, DMDMODCOD);
modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
aclc = stv090x_optimize_carloop(state, modcod, pilots);
if (modcod <= STV090x_QPSK_910) {
STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
} else if (modcod <= STV090x_8PSK_910) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
goto err;
}
if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
if (modcod <= STV090x_16APSK_910) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
goto err;
}
}
} else {
/*Carrier loop setting for short frame*/
aclc = stv090x_optimize_carloop_short(state);
if (state->modulation == STV090x_QPSK) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
goto err;
} else if (state->modulation == STV090x_8PSK) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
goto err;
} else if (state->modulation == STV090x_16APSK) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
goto err;
} else if (state->modulation == STV090x_32APSK) {
if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
goto err;
}
}
STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
break;
case STV090x_ERROR:
default:
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
break;
}
f_1 = STV090x_READ_DEMOD(state, CFR2);
f_0 = STV090x_READ_DEMOD(state, CFR1);
reg = STV090x_READ_DEMOD(state, TMGOBS);
if (state->algo == STV090x_BLIND_SEARCH) {
STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
goto err;
if (stv090x_set_srate(state, srate) < 0)
goto err;
blind_tune = 1;
if (stv090x_dvbs_track_crl(state) < 0)
goto err;
}
if (state->internal->dev_ver >= 0x20) {
if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
(state->search_mode == STV090x_SEARCH_DSS) ||
(state->search_mode == STV090x_SEARCH_AUTO)) {
if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
goto err;
}
}
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
/* AUTO tracking MODE */
if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
goto err;
/* AUTO tracking MODE */
if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
goto err;
if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
(state->srate < 10000000)) {
/* update initial carrier freq with the found freq offset */
if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
goto err;
state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
if (state->algo != STV090x_WARM_SEARCH) {
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_set_bandwidth) {
if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
}
}
if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
msleep(50); /* blind search: wait 50ms for SR stabilization */
else
msleep(5);
stv090x_get_lock_tmg(state);
if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
goto err;
i = 0;
while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
goto err;
i++;
}
}
}
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
goto err;
}
if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
stv090x_set_vit_thtracq(state);
return 0;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
{
s32 timer = 0, lock = 0, stat;
u32 reg;
while ((timer < timeout) && (!lock)) {
reg = STV090x_READ_DEMOD(state, DMDSTATE);
stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
switch (stat) {
case 0: /* searching */
case 1: /* first PLH detected */
default:
lock = 0;
break;
case 2: /* DVB-S2 mode */
reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
break;
case 3: /* DVB-S1/legacy mode */
reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
break;
}
if (!lock) {
msleep(10);
timer += 10;
}
}
return lock;
}
static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
{
u32 reg;
s32 timer = 0;
int lock;
lock = stv090x_get_dmdlock(state, timeout_dmd);
if (lock)
lock = stv090x_get_feclock(state, timeout_fec);
if (lock) {
lock = 0;
while ((timer < timeout_fec) && (!lock)) {
reg = STV090x_READ_DEMOD(state, TSSTATUS);
lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
msleep(1);
timer++;
}
}
return lock;
}
static int stv090x_set_s2rolloff(struct stv090x_state *state)
{
u32 reg;
if (state->internal->dev_ver <= 0x20) {
/* rolloff to auto mode if DVBS2 */
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
goto err;
} else {
/* DVB-S2 rolloff to auto mode if DVBS2 */
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
goto err;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
{
struct dvb_frontend *fe = &state->frontend;
enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
u32 reg;
s32 agc1_power, power_iq = 0, i;
int lock = 0, low_sr = 0;
reg = STV090x_READ_DEMOD(state, TSCFGH);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
goto err;
if (state->internal->dev_ver >= 0x20) {
if (state->srate > 5000000) {
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
goto err;
}
}
stv090x_get_lock_tmg(state);
if (state->algo == STV090x_BLIND_SEARCH) {
state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
goto err;
if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
goto err;
if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
goto err;
} else {
/* known srate */
if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
goto err;
if (state->srate < 2000000) {
/* SR < 2MSPS */
if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
goto err;
} else {
/* SR >= 2Msps */
if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
if (state->internal->dev_ver >= 0x20) {
if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
goto err;
if (state->algo == STV090x_COLD_SEARCH)
state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
else if (state->algo == STV090x_WARM_SEARCH)
state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
}
/* if cold start or warm (Symbolrate is known)
* use a Narrow symbol rate scan range
*/
if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
goto err;
if (stv090x_set_srate(state, state->srate) < 0)
goto err;
if (stv090x_set_max_srate(state, state->internal->mclk,
state->srate) < 0)
goto err;
if (stv090x_set_min_srate(state, state->internal->mclk,
state->srate) < 0)
goto err;
if (state->srate >= 10000000)
low_sr = 0;
else
low_sr = 1;
}
/* Setup tuner */
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_set_bbgain) {
reg = state->config->tuner_bbgain;
if (reg == 0)
reg = 10; /* default: 10dB */
if (state->config->tuner_set_bbgain(fe, reg) < 0)
goto err_gateoff;
}
if (state->config->tuner_set_frequency) {
if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
goto err_gateoff;
}
if (state->config->tuner_set_bandwidth) {
if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
msleep(50);
if (state->config->tuner_get_status) {
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_get_status(fe, ®) < 0)
goto err_gateoff;
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
if (reg)
dprintk(FE_DEBUG, 1, "Tuner phase locked");
else {
dprintk(FE_DEBUG, 1, "Tuner unlocked");
return STV090x_NOCARRIER;
}
}
msleep(10);
agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
STV090x_READ_DEMOD(state, AGCIQIN0));
if (agc1_power == 0) {
/* If AGC1 integrator value is 0
* then read POWERI, POWERQ
*/
for (i = 0; i < 5; i++) {
power_iq += (STV090x_READ_DEMOD(state, POWERI) +
STV090x_READ_DEMOD(state, POWERQ)) >> 1;
}
power_iq /= 5;
}
if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
lock = 0;
signal_state = STV090x_NOAGC1;
} else {
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
if (state->internal->dev_ver <= 0x20) {
/* rolloff to auto mode if DVBS2 */
STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
} else {
/* DVB-S2 rolloff to auto mode if DVBS2 */
STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
}
if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
goto err;
if (stv090x_delivery_search(state) < 0)
goto err;
if (state->algo != STV090x_BLIND_SEARCH) {
if (stv090x_start_search(state) < 0)
goto err;
}
}
if (signal_state == STV090x_NOAGC1)
return signal_state;
if (state->algo == STV090x_BLIND_SEARCH)
lock = stv090x_blind_search(state);
else if (state->algo == STV090x_COLD_SEARCH)
lock = stv090x_get_coldlock(state, state->DemodTimeout);
else if (state->algo == STV090x_WARM_SEARCH)
lock = stv090x_get_dmdlock(state, state->DemodTimeout);
if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
if (!low_sr) {
if (stv090x_chk_tmg(state))
lock = stv090x_sw_algo(state);
}
}
if (lock)
signal_state = stv090x_get_sig_params(state);
if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
stv090x_optimize_track(state);
if (state->internal->dev_ver >= 0x20) {
/* >= Cut 2.0 :release TS reset after
* demod lock and optimized Tracking
*/
reg = STV090x_READ_DEMOD(state, TSCFGH);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
goto err;
msleep(3);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
goto err;
}
lock = stv090x_get_lock(state, state->FecTimeout,
state->FecTimeout);
if (lock) {
if (state->delsys == STV090x_DVBS2) {
stv090x_set_s2rolloff(state);
reg = STV090x_READ_DEMOD(state, PDELCTRL2);
STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
goto err;
/* Reset DVBS2 packet delinator error counter */
reg = STV090x_READ_DEMOD(state, PDELCTRL2);
STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
goto err;
} else {
if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
goto err;
}
/* Reset the Total packet counter */
if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
goto err;
/* Reset the packet Error counter2 */
if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
goto err;
} else {
signal_state = STV090x_NODATA;
stv090x_chk_signal(state);
}
}
return signal_state;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code)
{
dprintk(FE_DEBUG, 1, "Set Gold PLS code %d", pls_code);
if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_mis(struct stv090x_state *state, int mis)
{
u32 reg;
if (mis < 0 || mis > 255) {
dprintk(FE_DEBUG, 1, "Disable MIS filtering");
reg = STV090x_READ_DEMOD(state, PDELCTRL1);
STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
} else {
dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
reg = STV090x_READ_DEMOD(state, PDELCTRL1);
STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
goto err;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *props = &fe->dtv_property_cache;
if (props->frequency == 0)
return DVBFE_ALGO_SEARCH_INVALID;
switch (props->delivery_system) {
case SYS_DSS:
state->delsys = STV090x_DSS;
break;
case SYS_DVBS:
state->delsys = STV090x_DVBS1;
break;
case SYS_DVBS2:
state->delsys = STV090x_DVBS2;
break;
default:
return DVBFE_ALGO_SEARCH_INVALID;
}
state->frequency = props->frequency;
state->srate = props->symbol_rate;
state->search_mode = STV090x_SEARCH_AUTO;
state->algo = STV090x_COLD_SEARCH;
state->fec = STV090x_PRERR;
if (state->srate > 10000000) {
dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
state->search_range = 10000000;
} else {
dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
state->search_range = 5000000;
}
stv090x_set_pls(state, props->scrambling_sequence_index);
stv090x_set_mis(state, props->stream_id);
if (stv090x_algo(state) == STV090x_RANGEOK) {
dprintk(FE_DEBUG, 1, "Search success!");
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
dprintk(FE_DEBUG, 1, "Search failed!");
return DVBFE_ALGO_SEARCH_FAILED;
}
return DVBFE_ALGO_SEARCH_ERROR;
}
static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg, dstatus;
u8 search_state;
*status = 0;
dstatus = STV090x_READ_DEMOD(state, DSTATUS);
if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
reg = STV090x_READ_DEMOD(state, DMDSTATE);
search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
switch (search_state) {
case 0: /* searching */
case 1: /* first PLH detected */
default:
dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
break;
case 2: /* DVB-S2 mode */
dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
*status |= FE_HAS_VITERBI;
reg = STV090x_READ_DEMOD(state, TSSTATUS);
if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
}
}
break;
case 3: /* DVB-S1/legacy mode */
dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
*status |= FE_HAS_VITERBI;
reg = STV090x_READ_DEMOD(state, TSSTATUS);
if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
}
}
break;
}
return 0;
}
static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
{
struct stv090x_state *state = fe->demodulator_priv;
s32 count_4, count_3, count_2, count_1, count_0, count;
u32 reg, h, m, l;
enum fe_status status;
stv090x_read_status(fe, &status);
if (!(status & FE_HAS_LOCK)) {
*per = 1 << 23; /* Max PER */
} else {
/* Counter 2 */
reg = STV090x_READ_DEMOD(state, ERRCNT22);
h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
reg = STV090x_READ_DEMOD(state, ERRCNT21);
m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
reg = STV090x_READ_DEMOD(state, ERRCNT20);
l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
*per = ((h << 16) | (m << 8) | l);
count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
if ((!count_4) && (!count_3)) {
count = (count_2 & 0xff) << 16;
count |= (count_1 & 0xff) << 8;
count |= count_0 & 0xff;
} else {
count = 1 << 24;
}
if (count == 0)
*per = 1;
}
if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
{
int res = 0;
int min = 0, med;
if ((val >= tab[min].read && val < tab[max].read) ||
(val >= tab[max].read && val < tab[min].read)) {
while ((max - min) > 1) {
med = (max + min) / 2;
if ((val >= tab[min].read && val < tab[med].read) ||
(val >= tab[med].read && val < tab[min].read))
max = med;
else
min = med;
}
res = ((val - tab[min].read) *
(tab[max].real - tab[min].real) /
(tab[max].read - tab[min].read)) +
tab[min].real;
} else {
if (tab[min].read < tab[max].read) {
if (val < tab[min].read)
res = tab[min].real;
else if (val >= tab[max].read)
res = tab[max].real;
} else {
if (val >= tab[min].read)
res = tab[min].real;
else if (val < tab[max].read)
res = tab[max].real;
}
}
return res;
}
static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
s32 agc_0, agc_1, agc;
s32 str;
reg = STV090x_READ_DEMOD(state, AGCIQIN1);
agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
reg = STV090x_READ_DEMOD(state, AGCIQIN0);
agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
agc = MAKEWORD16(agc_1, agc_0);
str = stv090x_table_lookup(stv090x_rf_tab,
ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
if (agc > stv090x_rf_tab[0].read)
str = 0;
else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
str = -100;
*strength = (str + 100) * 0xFFFF / 100;
return 0;
}
static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg_0, reg_1, reg, i;
s32 val_0, val_1, val = 0;
u8 lock_f;
s32 div;
u32 last;
switch (state->delsys) {
case STV090x_DVBS2:
reg = STV090x_READ_DEMOD(state, DSTATUS);
lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
if (lock_f) {
msleep(5);
for (i = 0; i < 16; i++) {
reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
val += MAKEWORD16(val_1, val_0);
msleep(1);
}
val /= 16;
last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
div = stv090x_s2cn_tab[last].real -
stv090x_s2cn_tab[3].real;
val = stv090x_table_lookup(stv090x_s2cn_tab, last, val);
if (val < 0)
val = 0;
*cnr = val * 0xFFFF / div;
}
break;
case STV090x_DVBS1:
case STV090x_DSS:
reg = STV090x_READ_DEMOD(state, DSTATUS);
lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
if (lock_f) {
msleep(5);
for (i = 0; i < 16; i++) {
reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
val += MAKEWORD16(val_1, val_0);
msleep(1);
}
val /= 16;
last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
div = stv090x_s1cn_tab[last].real -
stv090x_s1cn_tab[0].real;
val = stv090x_table_lookup(stv090x_s1cn_tab, last, val);
*cnr = val * 0xFFFF / div;
}
break;
default:
break;
}
return 0;
}
static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
reg = STV090x_READ_DEMOD(state, DISTXCTL);
switch (tone) {
case SEC_TONE_ON:
STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
break;
case SEC_TONE_OFF:
STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
break;
default:
return -EINVAL;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg, idle = 0, fifo_full = 1;
int i;
reg = STV090x_READ_DEMOD(state, DISTXCTL);
STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
(state->config->diseqc_envelope_mode) ? 4 : 2);
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
for (i = 0; i < cmd->msg_len; i++) {
while (fifo_full) {
reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
}
if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
goto err;
}
reg = STV090x_READ_DEMOD(state, DISTXCTL);
STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
i = 0;
while ((!idle) && (i < 10)) {
reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
msleep(10);
i++;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg, idle = 0, fifo_full = 1;
u8 mode, value;
int i;
reg = STV090x_READ_DEMOD(state, DISTXCTL);
if (burst == SEC_MINI_A) {
mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
value = 0x00;
} else {
mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
value = 0xFF;
}
STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
while (fifo_full) {
reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
}
if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DISTXCTL);
STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
goto err;
i = 0;
while ((!idle) && (i < 10)) {
reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
msleep(10);
i++;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg = 0, i = 0, rx_end = 0;
while ((rx_end != 1) && (i < 10)) {
msleep(10);
i++;
reg = STV090x_READ_DEMOD(state, DISRX_ST0);
rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
}
if (rx_end) {
reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
for (i = 0; i < reply->msg_len; i++)
reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
}
return 0;
}
static int stv090x_sleep(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
u8 full_standby = 0;
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (state->config->tuner_sleep) {
if (state->config->tuner_sleep(fe) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
state->device == STV0900 ? "STV0900" : "STV0903",
state->demod);
mutex_lock(&state->internal->demod_lock);
switch (state->demod) {
case STV090x_DEMODULATOR_0:
/* power off ADC 1 */
reg = stv090x_read_reg(state, STV090x_TSTTNR1);
STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
goto err_unlock;
/* power off DiSEqC 1 */
reg = stv090x_read_reg(state, STV090x_TSTTNR2);
STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
goto err_unlock;
/* check whether path 2 is already sleeping, that is when
ADC2 is off */
reg = stv090x_read_reg(state, STV090x_TSTTNR3);
if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
full_standby = 1;
/* stop clocks */
reg = stv090x_read_reg(state, STV090x_STOPCLK1);
/* packet delineator 1 clock */
STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
/* ADC 1 clock */
STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
/* FEC clock is shared between the two paths, only stop it
when full standby is possible */
if (full_standby)
STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
goto err_unlock;
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
/* sampling 1 clock */
STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
/* viterbi 1 clock */
STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
/* TS clock is shared between the two paths, only stop it
when full standby is possible */
if (full_standby)
STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err_unlock;
break;
case STV090x_DEMODULATOR_1:
/* power off ADC 2 */
reg = stv090x_read_reg(state, STV090x_TSTTNR3);
STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
goto err_unlock;
/* power off DiSEqC 2 */
reg = stv090x_read_reg(state, STV090x_TSTTNR4);
STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
goto err_unlock;
/* check whether path 1 is already sleeping, that is when
ADC1 is off */
reg = stv090x_read_reg(state, STV090x_TSTTNR1);
if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
full_standby = 1;
/* stop clocks */
reg = stv090x_read_reg(state, STV090x_STOPCLK1);
/* packet delineator 2 clock */
STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
/* ADC 2 clock */
STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
/* FEC clock is shared between the two paths, only stop it
when full standby is possible */
if (full_standby)
STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
goto err_unlock;
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
/* sampling 2 clock */
STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
/* viterbi 2 clock */
STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
/* TS clock is shared between the two paths, only stop it
when full standby is possible */
if (full_standby)
STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err_unlock;
break;
default:
dprintk(FE_ERROR, 1, "Wrong demodulator!");
break;
}
if (full_standby) {
/* general power off */
reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
goto err_unlock;
}
mutex_unlock(&state->internal->demod_lock);
return 0;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
goto err;
err_unlock:
mutex_unlock(&state->internal->demod_lock);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_wakeup(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
state->device == STV0900 ? "STV0900" : "STV0903",
state->demod);
mutex_lock(&state->internal->demod_lock);
/* general power on */
reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
goto err;
switch (state->demod) {
case STV090x_DEMODULATOR_0:
/* power on ADC 1 */
reg = stv090x_read_reg(state, STV090x_TSTTNR1);
STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
goto err;
/* power on DiSEqC 1 */
reg = stv090x_read_reg(state, STV090x_TSTTNR2);
STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
goto err;
/* activate clocks */
reg = stv090x_read_reg(state, STV090x_STOPCLK1);
/* packet delineator 1 clock */
STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
/* ADC 1 clock */
STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
/* FEC clock */
STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
goto err;
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
/* sampling 1 clock */
STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
/* viterbi 1 clock */
STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
/* TS clock */
STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err;
break;
case STV090x_DEMODULATOR_1:
/* power on ADC 2 */
reg = stv090x_read_reg(state, STV090x_TSTTNR3);
STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
goto err;
/* power on DiSEqC 2 */
reg = stv090x_read_reg(state, STV090x_TSTTNR4);
STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
goto err;
/* activate clocks */
reg = stv090x_read_reg(state, STV090x_STOPCLK1);
/* packet delineator 2 clock */
STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
/* ADC 2 clock */
STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
/* FEC clock */
STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
goto err;
reg = stv090x_read_reg(state, STV090x_STOPCLK2);
/* sampling 2 clock */
STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
/* viterbi 2 clock */
STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
/* TS clock */
STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
goto err;
break;
default:
dprintk(FE_ERROR, 1, "Wrong demodulator!");
break;
}
mutex_unlock(&state->internal->demod_lock);
return 0;
err:
mutex_unlock(&state->internal->demod_lock);
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static void stv090x_release(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
state->internal->num_used--;
if (state->internal->num_used <= 0) {
dprintk(FE_ERROR, 1, "Actually removing");
remove_dev(state->internal);
kfree(state->internal);
}
kfree(state);
}
static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
{
u32 reg = 0;
reg = stv090x_read_reg(state, STV090x_GENCFG);
switch (ldpc_mode) {
case STV090x_DUAL:
default:
if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
/* set LDPC to dual mode */
if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
goto err;
state->demod_mode = STV090x_DUAL;
reg = stv090x_read_reg(state, STV090x_TSTRES0);
STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
goto err;
STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
goto err;
}
break;
case STV090x_SINGLE:
if (stv090x_stop_modcod(state) < 0)
goto err;
if (stv090x_activate_modcod_single(state) < 0)
goto err;
if (state->demod == STV090x_DEMODULATOR_1) {
if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
goto err;
} else {
if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
goto err;
}
reg = stv090x_read_reg(state, STV090x_TSTRES0);
STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
goto err;
STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, PDELCTRL1);
STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
goto err;
break;
}
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
/* return (Hz), clk in Hz*/
static u32 stv090x_get_mclk(struct stv090x_state *state)
{
const struct stv090x_config *config = state->config;
u32 div, reg;
u8 ratio;
div = stv090x_read_reg(state, STV090x_NCOARSE);
reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
return (div + 1) * config->xtal / ratio; /* kHz */
}
static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
{
const struct stv090x_config *config = state->config;
u32 reg, div, clk_sel;
reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
div = ((clk_sel * mclk) / config->xtal) - 1;
reg = stv090x_read_reg(state, STV090x_NCOARSE);
STV090x_SETFIELD(reg, M_DIV_FIELD, div);
if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
goto err;
state->internal->mclk = stv090x_get_mclk(state);
/*Set the DiseqC frequency to 22KHz */
div = state->internal->mclk / 704000;
if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv0900_set_tspath(struct stv090x_state *state)
{
u32 reg;
if (state->internal->dev_ver >= 0x20) {
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
switch (state->config->ts2_mode) {
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
break;
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
goto err;
reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
goto err;
reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
goto err;
break;
}
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
switch (state->config->ts2_mode) {
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
goto err;
break;
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
goto err;
break;
}
break;
}
} else {
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
switch (state->config->ts2_mode) {
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
break;
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
goto err;
reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
goto err;
break;
}
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
switch (state->config->ts2_mode) {
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
break;
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
break;
}
break;
}
}
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_DVBCI:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_CONTINUOUS:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
default:
break;
}
switch (state->config->ts2_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_DVBCI:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_CONTINUOUS:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
break;
default:
break;
}
if (state->config->ts1_clk > 0) {
u32 speed;
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
default:
speed = state->internal->mclk /
(state->config->ts1_clk / 4);
if (speed < 0x08)
speed = 0x08;
if (speed > 0xFF)
speed = 0xFF;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
speed = state->internal->mclk /
(state->config->ts1_clk / 32);
if (speed < 0x20)
speed = 0x20;
if (speed > 0xFF)
speed = 0xFF;
break;
}
reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
goto err;
}
if (state->config->ts2_clk > 0) {
u32 speed;
switch (state->config->ts2_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
default:
speed = state->internal->mclk /
(state->config->ts2_clk / 4);
if (speed < 0x08)
speed = 0x08;
if (speed > 0xFF)
speed = 0xFF;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
speed = state->internal->mclk /
(state->config->ts2_clk / 32);
if (speed < 0x20)
speed = 0x20;
if (speed > 0xFF)
speed = 0xFF;
break;
}
reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
goto err;
}
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
goto err;
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv0903_set_tspath(struct stv090x_state *state)
{
u32 reg;
if (state->internal->dev_ver >= 0x20) {
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
break;
}
} else {
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
default:
stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
break;
}
}
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_DVBCI:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
case STV090x_TSMODE_SERIAL_CONTINUOUS:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
break;
default:
break;
}
if (state->config->ts1_clk > 0) {
u32 speed;
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
case STV090x_TSMODE_DVBCI:
default:
speed = state->internal->mclk /
(state->config->ts1_clk / 4);
if (speed < 0x08)
speed = 0x08;
if (speed > 0xFF)
speed = 0xFF;
break;
case STV090x_TSMODE_SERIAL_PUNCTURED:
case STV090x_TSMODE_SERIAL_CONTINUOUS:
speed = state->internal->mclk /
(state->config->ts1_clk / 32);
if (speed < 0x20)
speed = 0x20;
if (speed > 0xFF)
speed = 0xFF;
break;
}
reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
goto err;
}
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_init(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
const struct stv090x_config *config = state->config;
u32 reg;
if (state->internal->mclk == 0) {
/* call tuner init to configure the tuner's clock output
divider directly before setting up the master clock of
the stv090x. */
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (config->tuner_init) {
if (config->tuner_init(fe) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
msleep(5);
if (stv090x_write_reg(state, STV090x_SYNTCTRL,
0x20 | config->clk_mode) < 0)
goto err;
stv090x_get_mclk(state);
}
if (stv090x_wakeup(fe) < 0) {
dprintk(FE_ERROR, 1, "Error waking device");
goto err;
}
if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, TNRCFG2);
STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
goto err;
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
if (config->tuner_set_mode) {
if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
goto err_gateoff;
}
if (config->tuner_init) {
if (config->tuner_init(fe) < 0)
goto err_gateoff;
}
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
if (state->device == STV0900) {
if (stv0900_set_tspath(state) < 0)
goto err;
} else {
if (stv0903_set_tspath(state) < 0)
goto err;
}
return 0;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_setup(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
const struct stv090x_config *config = state->config;
const struct stv090x_reg *stv090x_initval = NULL;
const struct stv090x_reg *stv090x_cut20_val = NULL;
unsigned long t1_size = 0, t2_size = 0;
u32 reg = 0;
int i;
if (state->device == STV0900) {
dprintk(FE_DEBUG, 1, "Initializing STV0900");
stv090x_initval = stv0900_initval;
t1_size = ARRAY_SIZE(stv0900_initval);
stv090x_cut20_val = stv0900_cut20_val;
t2_size = ARRAY_SIZE(stv0900_cut20_val);
} else if (state->device == STV0903) {
dprintk(FE_DEBUG, 1, "Initializing STV0903");
stv090x_initval = stv0903_initval;
t1_size = ARRAY_SIZE(stv0903_initval);
stv090x_cut20_val = stv0903_cut20_val;
t2_size = ARRAY_SIZE(stv0903_cut20_val);
}
/* STV090x init */
/* Stop Demod */
if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
goto err;
if (state->device == STV0900)
if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
goto err;
msleep(5);
/* Set No Tuner Mode */
if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
goto err;
if (state->device == STV0900)
if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
goto err;
/* I2C repeater OFF */
STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
goto err;
if (state->device == STV0900)
if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
goto err;
msleep(5);
if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
goto err;
if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
goto err;
msleep(5);
/* write initval */
dprintk(FE_DEBUG, 1, "Setting up initial values");
for (i = 0; i < t1_size; i++) {
if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
goto err;
}
state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
if (state->internal->dev_ver >= 0x20) {
if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
goto err;
/* write cut20_val*/
dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
for (i = 0; i < t2_size; i++) {
if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
goto err;
}
} else if (state->internal->dev_ver < 0x20) {
dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
state->internal->dev_ver);
goto err;
} else if (state->internal->dev_ver > 0x30) {
/* we shouldn't bail out from here */
dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
state->internal->dev_ver);
}
/* ADC1 range */
reg = stv090x_read_reg(state, STV090x_TSTTNR1);
STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
(config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
goto err;
/* ADC2 range */
reg = stv090x_read_reg(state, STV090x_TSTTNR3);
STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
(config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
goto err;
if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
goto err;
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
u8 value, u8 xor_value)
{
struct stv090x_state *state = fe->demodulator_priv;
u8 reg = 0;
STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
}
static int stv090x_setup_compound(struct stv090x_state *state)
{
struct stv090x_dev *temp_int;
temp_int = find_dev(state->i2c,
state->config->address);
if (temp_int && state->demod_mode == STV090x_DUAL) {
state->internal = temp_int->internal;
state->internal->num_used++;
dprintk(FE_INFO, 1, "Found Internal Structure!");
} else {
state->internal = kmalloc(sizeof(*state->internal), GFP_KERNEL);
if (!state->internal)
goto error;
temp_int = append_internal(state->internal);
if (!temp_int) {
kfree(state->internal);
goto error;
}
state->internal->num_used = 1;
state->internal->mclk = 0;
state->internal->dev_ver = 0;
state->internal->i2c_adap = state->i2c;
state->internal->i2c_addr = state->config->address;
dprintk(FE_INFO, 1, "Create New Internal Structure!");
mutex_init(&state->internal->demod_lock);
mutex_init(&state->internal->tuner_lock);
if (stv090x_setup(&state->frontend) < 0) {
dprintk(FE_ERROR, 1, "Error setting up device");
goto err_remove;
}
}
if (state->internal->dev_ver >= 0x30)
state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
/* workaround for stuck DiSEqC output */
if (state->config->diseqc_envelope_mode)
stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
state->config->set_gpio = stv090x_set_gpio;
dprintk(FE_ERROR, 1, "Probing %s demodulator(%d) Cut=0x%02x",
state->device == STV0900 ? "STV0900" : "STV0903",
state->config->demod,
state->internal->dev_ver);
return 0;
error:
return -ENOMEM;
err_remove:
remove_dev(state->internal);
kfree(state->internal);
return -ENODEV;
}
static const struct dvb_frontend_ops stv090x_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
.info = {
.name = "STV090x Multistandard",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_2G_MODULATION
},
.release = stv090x_release,
.init = stv090x_init,
.sleep = stv090x_sleep,
.get_frontend_algo = stv090x_frontend_algo,
.diseqc_send_master_cmd = stv090x_send_diseqc_msg,
.diseqc_send_burst = stv090x_send_diseqc_burst,
.diseqc_recv_slave_reply = stv090x_recv_slave_reply,
.set_tone = stv090x_set_tone,
.search = stv090x_search,
.read_status = stv090x_read_status,
.read_ber = stv090x_read_per,
.read_signal_strength = stv090x_read_signal_strength,
.read_snr = stv090x_read_cnr,
};
static struct dvb_frontend *stv090x_get_dvb_frontend(struct i2c_client *client)
{
struct stv090x_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &state->frontend;
}
static int stv090x_probe(struct i2c_client *client)
{
int ret = 0;
struct stv090x_config *config = client->dev.platform_data;
struct stv090x_state *state = NULL;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state) {
ret = -ENOMEM;
goto error;
}
state->verbose = &verbose;
state->config = config;
state->i2c = client->adapter;
state->frontend.ops = stv090x_ops;
state->frontend.demodulator_priv = state;
state->demod = config->demod;
/* Single or Dual mode */
state->demod_mode = config->demod_mode;
state->device = config->device;
/* default */
state->rolloff = STV090x_RO_35;
ret = stv090x_setup_compound(state);
if (ret)
goto error;
i2c_set_clientdata(client, state);
/* setup callbacks */
config->get_dvb_frontend = stv090x_get_dvb_frontend;
return 0;
error:
kfree(state);
return ret;
}
static void stv090x_remove(struct i2c_client *client)
{
struct stv090x_state *state = i2c_get_clientdata(client);
stv090x_release(&state->frontend);
}
struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
struct i2c_adapter *i2c,
enum stv090x_demodulator demod)
{
int ret = 0;
struct stv090x_state *state = NULL;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
goto error;
state->verbose = &verbose;
state->config = config;
state->i2c = i2c;
state->frontend.ops = stv090x_ops;
state->frontend.demodulator_priv = state;
state->demod = demod;
/* Single or Dual mode */
state->demod_mode = config->demod_mode;
state->device = config->device;
/* default */
state->rolloff = STV090x_RO_35;
ret = stv090x_setup_compound(state);
if (ret)
goto error;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv090x_attach);
static const struct i2c_device_id stv090x_id_table[] = {
{"stv090x", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, stv090x_id_table);
static struct i2c_driver stv090x_driver = {
.driver = {
.name = "stv090x",
.suppress_bind_attrs = true,
},
.probe = stv090x_probe,
.remove = stv090x_remove,
.id_table = stv090x_id_table,
};
module_i2c_driver(stv090x_driver);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv090x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
*
* Copyright (C) 2010-2013 Mauro Carvalho Chehab
* Copyright (C) 2009-2010 Douglas Landgraf <[email protected]>
*/
#include <linux/kernel.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "mb86a20s.h"
#define NUM_LAYERS 3
enum mb86a20s_bandwidth {
MB86A20S_13SEG = 0,
MB86A20S_13SEG_PARTIAL = 1,
MB86A20S_1SEG = 2,
MB86A20S_3SEG = 3,
};
static u8 mb86a20s_subchannel[] = {
0xb0, 0xc0, 0xd0, 0xe0,
0xf0, 0x00, 0x10, 0x20,
};
struct mb86a20s_state {
struct i2c_adapter *i2c;
const struct mb86a20s_config *config;
u32 last_frequency;
struct dvb_frontend frontend;
u32 if_freq;
enum mb86a20s_bandwidth bw;
bool inversion;
u32 subchannel;
u32 estimated_rate[NUM_LAYERS];
unsigned long get_strength_time;
bool need_init;
};
struct regdata {
u8 reg;
u8 data;
};
#define BER_SAMPLING_RATE 1 /* Seconds */
/*
* Initialization sequence: Use whatevere default values that PV SBTVD
* does on its initialisation, obtained via USB snoop
*/
static struct regdata mb86a20s_init1[] = {
{ 0x70, 0x0f },
{ 0x70, 0xff },
{ 0x08, 0x01 },
{ 0x50, 0xd1 }, { 0x51, 0x20 },
};
static struct regdata mb86a20s_init2[] = {
{ 0x50, 0xd1 }, { 0x51, 0x22 },
{ 0x39, 0x01 },
{ 0x71, 0x00 },
{ 0x3b, 0x21 },
{ 0x3c, 0x3a },
{ 0x01, 0x0d },
{ 0x04, 0x08 }, { 0x05, 0x05 },
{ 0x04, 0x0e }, { 0x05, 0x00 },
{ 0x04, 0x0f }, { 0x05, 0x14 },
{ 0x04, 0x0b }, { 0x05, 0x8c },
{ 0x04, 0x00 }, { 0x05, 0x00 },
{ 0x04, 0x01 }, { 0x05, 0x07 },
{ 0x04, 0x02 }, { 0x05, 0x0f },
{ 0x04, 0x03 }, { 0x05, 0xa0 },
{ 0x04, 0x09 }, { 0x05, 0x00 },
{ 0x04, 0x0a }, { 0x05, 0xff },
{ 0x04, 0x27 }, { 0x05, 0x64 },
{ 0x04, 0x28 }, { 0x05, 0x00 },
{ 0x04, 0x1e }, { 0x05, 0xff },
{ 0x04, 0x29 }, { 0x05, 0x0a },
{ 0x04, 0x32 }, { 0x05, 0x0a },
{ 0x04, 0x14 }, { 0x05, 0x02 },
{ 0x04, 0x04 }, { 0x05, 0x00 },
{ 0x04, 0x05 }, { 0x05, 0x22 },
{ 0x04, 0x06 }, { 0x05, 0x0e },
{ 0x04, 0x07 }, { 0x05, 0xd8 },
{ 0x04, 0x12 }, { 0x05, 0x00 },
{ 0x04, 0x13 }, { 0x05, 0xff },
/*
* On this demod, when the bit count reaches the count below,
* it collects the bit error count. The bit counters are initialized
* to 65535 here. This warrants that all of them will be quickly
* calculated when device gets locked. As TMCC is parsed, the values
* will be adjusted later in the driver's code.
*/
{ 0x52, 0x01 }, /* Turn on BER before Viterbi */
{ 0x50, 0xa7 }, { 0x51, 0x00 },
{ 0x50, 0xa8 }, { 0x51, 0xff },
{ 0x50, 0xa9 }, { 0x51, 0xff },
{ 0x50, 0xaa }, { 0x51, 0x00 },
{ 0x50, 0xab }, { 0x51, 0xff },
{ 0x50, 0xac }, { 0x51, 0xff },
{ 0x50, 0xad }, { 0x51, 0x00 },
{ 0x50, 0xae }, { 0x51, 0xff },
{ 0x50, 0xaf }, { 0x51, 0xff },
/*
* On this demod, post BER counts blocks. When the count reaches the
* value below, it collects the block error count. The block counters
* are initialized to 127 here. This warrants that all of them will be
* quickly calculated when device gets locked. As TMCC is parsed, the
* values will be adjusted later in the driver's code.
*/
{ 0x5e, 0x07 }, /* Turn on BER after Viterbi */
{ 0x50, 0xdc }, { 0x51, 0x00 },
{ 0x50, 0xdd }, { 0x51, 0x7f },
{ 0x50, 0xde }, { 0x51, 0x00 },
{ 0x50, 0xdf }, { 0x51, 0x7f },
{ 0x50, 0xe0 }, { 0x51, 0x00 },
{ 0x50, 0xe1 }, { 0x51, 0x7f },
/*
* On this demod, when the block count reaches the count below,
* it collects the block error count. The block counters are initialized
* to 127 here. This warrants that all of them will be quickly
* calculated when device gets locked. As TMCC is parsed, the values
* will be adjusted later in the driver's code.
*/
{ 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
{ 0x50, 0xb2 }, { 0x51, 0x00 },
{ 0x50, 0xb3 }, { 0x51, 0x7f },
{ 0x50, 0xb4 }, { 0x51, 0x00 },
{ 0x50, 0xb5 }, { 0x51, 0x7f },
{ 0x50, 0xb6 }, { 0x51, 0x00 },
{ 0x50, 0xb7 }, { 0x51, 0x7f },
{ 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
{ 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
{ 0x45, 0x04 }, /* CN symbol 4 */
{ 0x48, 0x04 }, /* CN manual mode */
{ 0x50, 0xd5 }, { 0x51, 0x01 },
{ 0x50, 0xd6 }, { 0x51, 0x1f },
{ 0x50, 0xd2 }, { 0x51, 0x03 },
{ 0x50, 0xd7 }, { 0x51, 0x3f },
{ 0x1c, 0x01 },
{ 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
{ 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
{ 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
{ 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
{ 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
{ 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
{ 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
{ 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
{ 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
{ 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
{ 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
{ 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
{ 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
{ 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
{ 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
{ 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
{ 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
{ 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
{ 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
{ 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
{ 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
{ 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
{ 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
{ 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
{ 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
{ 0x50, 0x1e }, { 0x51, 0x5d },
{ 0x50, 0x22 }, { 0x51, 0x00 },
{ 0x50, 0x23 }, { 0x51, 0xc8 },
{ 0x50, 0x24 }, { 0x51, 0x00 },
{ 0x50, 0x25 }, { 0x51, 0xf0 },
{ 0x50, 0x26 }, { 0x51, 0x00 },
{ 0x50, 0x27 }, { 0x51, 0xc3 },
{ 0x50, 0x39 }, { 0x51, 0x02 },
{ 0x50, 0xd5 }, { 0x51, 0x01 },
{ 0xd0, 0x00 },
};
static struct regdata mb86a20s_reset_reception[] = {
{ 0x70, 0xf0 },
{ 0x70, 0xff },
{ 0x08, 0x01 },
{ 0x08, 0x00 },
};
static struct regdata mb86a20s_per_ber_reset[] = {
{ 0x53, 0x00 }, /* pre BER Counter reset */
{ 0x53, 0x07 },
{ 0x5f, 0x00 }, /* post BER Counter reset */
{ 0x5f, 0x07 },
{ 0x50, 0xb1 }, /* PER Counter reset */
{ 0x51, 0x07 },
{ 0x51, 0x00 },
};
/*
* I2C read/write functions and macros
*/
static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
u8 i2c_addr, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
};
int rc;
rc = i2c_transfer(state->i2c, &msg, 1);
if (rc != 1) {
dev_err(&state->i2c->dev,
"%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
__func__, rc, reg, data);
return rc;
}
return 0;
}
static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
u8 i2c_addr, struct regdata *rd, int size)
{
int i, rc;
for (i = 0; i < size; i++) {
rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
rd[i].data);
if (rc < 0)
return rc;
}
return 0;
}
static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
u8 i2c_addr, u8 reg)
{
u8 val;
int rc;
struct i2c_msg msg[] = {
{ .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
};
rc = i2c_transfer(state->i2c, msg, 2);
if (rc != 2) {
dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
__func__, reg, rc);
return (rc < 0) ? rc : -EIO;
}
return val;
}
#define mb86a20s_readreg(state, reg) \
mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
#define mb86a20s_writereg(state, reg, val) \
mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
#define mb86a20s_writeregdata(state, regdata) \
mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
regdata, ARRAY_SIZE(regdata))
/*
* Ancillary internal routines (likely compiled inlined)
*
* The functions below assume that gateway lock has already obtained
*/
static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct mb86a20s_state *state = fe->demodulator_priv;
int val;
*status = 0;
val = mb86a20s_readreg(state, 0x0a);
if (val < 0)
return val;
val &= 0xf;
if (val >= 2)
*status |= FE_HAS_SIGNAL;
if (val >= 4)
*status |= FE_HAS_CARRIER;
if (val >= 5)
*status |= FE_HAS_VITERBI;
if (val >= 7)
*status |= FE_HAS_SYNC;
/*
* Actually, on state S8, it starts receiving TS, but the TS
* output is only on normal state after the transition to S9.
*/
if (val >= 9)
*status |= FE_HAS_LOCK;
dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
__func__, *status, val);
return val;
}
static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int rc;
unsigned rf_max, rf_min, rf;
if (state->get_strength_time &&
(!time_after(jiffies, state->get_strength_time)))
return c->strength.stat[0].uvalue;
/* Reset its value if an error happen */
c->strength.stat[0].uvalue = 0;
/* Does a binary search to get RF strength */
rf_max = 0xfff;
rf_min = 0;
do {
rf = (rf_max + rf_min) / 2;
rc = mb86a20s_writereg(state, 0x04, 0x1f);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x05, rf >> 8);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x04, 0x20);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x05, rf);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x02);
if (rc < 0)
return rc;
if (rc & 0x08)
rf_min = (rf_max + rf_min) / 2;
else
rf_max = (rf_max + rf_min) / 2;
if (rf_max - rf_min < 4) {
rf = (rf_max + rf_min) / 2;
/* Rescale it from 2^12 (4096) to 2^16 */
rf = rf << (16 - 12);
if (rf)
rf |= (1 << 12) - 1;
dev_dbg(&state->i2c->dev,
"%s: signal strength = %d (%d < RF=%d < %d)\n",
__func__, rf, rf_min, rf >> 4, rf_max);
c->strength.stat[0].uvalue = rf;
state->get_strength_time = jiffies +
msecs_to_jiffies(1000);
return 0;
}
} while (1);
}
static int mb86a20s_get_modulation(struct mb86a20s_state *state,
unsigned layer)
{
int rc;
static unsigned char reg[] = {
[0] = 0x86, /* Layer A */
[1] = 0x8a, /* Layer B */
[2] = 0x8e, /* Layer C */
};
if (layer >= ARRAY_SIZE(reg))
return -EINVAL;
rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x6e);
if (rc < 0)
return rc;
switch ((rc >> 4) & 0x07) {
case 0:
return DQPSK;
case 1:
return QPSK;
case 2:
return QAM_16;
case 3:
return QAM_64;
default:
return QAM_AUTO;
}
}
static int mb86a20s_get_fec(struct mb86a20s_state *state,
unsigned layer)
{
int rc;
static unsigned char reg[] = {
[0] = 0x87, /* Layer A */
[1] = 0x8b, /* Layer B */
[2] = 0x8f, /* Layer C */
};
if (layer >= ARRAY_SIZE(reg))
return -EINVAL;
rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x6e);
if (rc < 0)
return rc;
switch ((rc >> 4) & 0x07) {
case 0:
return FEC_1_2;
case 1:
return FEC_2_3;
case 2:
return FEC_3_4;
case 3:
return FEC_5_6;
case 4:
return FEC_7_8;
default:
return FEC_AUTO;
}
}
static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
unsigned layer)
{
int rc;
static const int interleaving[] = {
0, 1, 2, 4, 8
};
static const unsigned char reg[] = {
[0] = 0x88, /* Layer A */
[1] = 0x8c, /* Layer B */
[2] = 0x90, /* Layer C */
};
if (layer >= ARRAY_SIZE(reg))
return -EINVAL;
rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x6e);
if (rc < 0)
return rc;
return interleaving[(rc >> 4) & 0x07];
}
static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
unsigned layer)
{
int rc, count;
static unsigned char reg[] = {
[0] = 0x89, /* Layer A */
[1] = 0x8d, /* Layer B */
[2] = 0x91, /* Layer C */
};
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (layer >= ARRAY_SIZE(reg))
return -EINVAL;
rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x6e);
if (rc < 0)
return rc;
count = (rc >> 4) & 0x0f;
dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
return count;
}
static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
/* Fixed parameters */
c->delivery_system = SYS_ISDBT;
c->bandwidth_hz = 6000000;
/* Initialize values that will be later autodetected */
c->isdbt_layer_enabled = 0;
c->transmission_mode = TRANSMISSION_MODE_AUTO;
c->guard_interval = GUARD_INTERVAL_AUTO;
c->isdbt_sb_mode = 0;
c->isdbt_sb_segment_count = 0;
}
/*
* Estimates the bit rate using the per-segment bit rate given by
* ABNT/NBR 15601 spec (table 4).
*/
static const u32 isdbt_rate[3][5][4] = {
{ /* DQPSK/QPSK */
{ 280850, 312060, 330420, 340430 }, /* 1/2 */
{ 374470, 416080, 440560, 453910 }, /* 2/3 */
{ 421280, 468090, 495630, 510650 }, /* 3/4 */
{ 468090, 520100, 550700, 567390 }, /* 5/6 */
{ 491500, 546110, 578230, 595760 }, /* 7/8 */
}, { /* QAM16 */
{ 561710, 624130, 660840, 680870 }, /* 1/2 */
{ 748950, 832170, 881120, 907820 }, /* 2/3 */
{ 842570, 936190, 991260, 1021300 }, /* 3/4 */
{ 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
{ 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
}, { /* QAM64 */
{ 842570, 936190, 991260, 1021300 }, /* 1/2 */
{ 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
{ 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
{ 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
{ 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
}
};
static u32 isdbt_layer_min_bitrate(struct dtv_frontend_properties *c,
u32 layer)
{
int mod, fec, guard;
/*
* If modulation/fec/guard is not detected, the default is
* to consider the lowest bit rate, to avoid taking too long time
* to get BER.
*/
switch (c->layer[layer].modulation) {
case DQPSK:
case QPSK:
default:
mod = 0;
break;
case QAM_16:
mod = 1;
break;
case QAM_64:
mod = 2;
break;
}
switch (c->layer[layer].fec) {
default:
case FEC_1_2:
case FEC_AUTO:
fec = 0;
break;
case FEC_2_3:
fec = 1;
break;
case FEC_3_4:
fec = 2;
break;
case FEC_5_6:
fec = 3;
break;
case FEC_7_8:
fec = 4;
break;
}
switch (c->guard_interval) {
default:
case GUARD_INTERVAL_1_4:
guard = 0;
break;
case GUARD_INTERVAL_1_8:
guard = 1;
break;
case GUARD_INTERVAL_1_16:
guard = 2;
break;
case GUARD_INTERVAL_1_32:
guard = 3;
break;
}
return isdbt_rate[mod][fec][guard] * c->layer[layer].segment_count;
}
static int mb86a20s_get_frontend(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int layer, rc, rate, counter;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
/* Reset frontend cache to default values */
mb86a20s_reset_frontend_cache(fe);
/* Check for partial reception */
rc = mb86a20s_writereg(state, 0x6d, 0x85);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x6e);
if (rc < 0)
return rc;
c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
/* Get per-layer data */
for (layer = 0; layer < NUM_LAYERS; layer++) {
dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
__func__, 'A' + layer);
rc = mb86a20s_get_segment_count(state, layer);
if (rc < 0)
goto noperlayer_error;
if (rc >= 0 && rc < 14) {
c->layer[layer].segment_count = rc;
} else {
c->layer[layer].segment_count = 0;
state->estimated_rate[layer] = 0;
continue;
}
c->isdbt_layer_enabled |= 1 << layer;
rc = mb86a20s_get_modulation(state, layer);
if (rc < 0)
goto noperlayer_error;
dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
__func__, rc);
c->layer[layer].modulation = rc;
rc = mb86a20s_get_fec(state, layer);
if (rc < 0)
goto noperlayer_error;
dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
__func__, rc);
c->layer[layer].fec = rc;
rc = mb86a20s_get_interleaving(state, layer);
if (rc < 0)
goto noperlayer_error;
dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
__func__, rc);
c->layer[layer].interleaving = rc;
rate = isdbt_layer_min_bitrate(c, layer);
counter = rate * BER_SAMPLING_RATE;
/* Avoids sampling too quickly or to overflow the register */
if (counter < 256)
counter = 256;
else if (counter > (1 << 24) - 1)
counter = (1 << 24) - 1;
dev_dbg(&state->i2c->dev,
"%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
__func__, 'A' + layer, rate / 1000, counter, counter);
state->estimated_rate[layer] = counter;
}
rc = mb86a20s_writereg(state, 0x6d, 0x84);
if (rc < 0)
return rc;
if ((rc & 0x60) == 0x20) {
c->isdbt_sb_mode = 1;
/* At least, one segment should exist */
if (!c->isdbt_sb_segment_count)
c->isdbt_sb_segment_count = 1;
}
/* Get transmission mode and guard interval */
rc = mb86a20s_readreg(state, 0x07);
if (rc < 0)
return rc;
c->transmission_mode = TRANSMISSION_MODE_AUTO;
if ((rc & 0x60) == 0x20) {
/* Only modes 2 and 3 are supported */
switch ((rc >> 2) & 0x03) {
case 1:
c->transmission_mode = TRANSMISSION_MODE_4K;
break;
case 2:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
}
c->guard_interval = GUARD_INTERVAL_AUTO;
if (!(rc & 0x10)) {
/* Guard interval 1/32 is not supported */
switch (rc & 0x3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
}
}
return 0;
noperlayer_error:
/* per-layer info is incomplete; discard all per-layer */
c->isdbt_layer_enabled = 0;
return rc;
}
static int mb86a20s_reset_counters(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int rc, val;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
/* Reset the counters, if the channel changed */
if (state->last_frequency != c->frequency) {
memset(&c->cnr, 0, sizeof(c->cnr));
memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
memset(&c->block_error, 0, sizeof(c->block_error));
memset(&c->block_count, 0, sizeof(c->block_count));
state->last_frequency = c->frequency;
}
/* Clear status for most stats */
/* BER/PER counter reset */
rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
if (rc < 0)
goto err;
/* CNR counter reset */
rc = mb86a20s_readreg(state, 0x45);
if (rc < 0)
goto err;
val = rc;
rc = mb86a20s_writereg(state, 0x45, val | 0x10);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
if (rc < 0)
goto err;
/* MER counter reset */
rc = mb86a20s_writereg(state, 0x50, 0x50);
if (rc < 0)
goto err;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
goto err;
val = rc;
rc = mb86a20s_writereg(state, 0x51, val | 0x01);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x51, val & 0x06);
if (rc < 0)
goto err;
goto ok;
err:
dev_err(&state->i2c->dev,
"%s: Can't reset FE statistics (error %d).\n",
__func__, rc);
ok:
return rc;
}
static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
unsigned layer,
u32 *error, u32 *count)
{
struct mb86a20s_state *state = fe->demodulator_priv;
int rc, val;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (layer >= NUM_LAYERS)
return -EINVAL;
/* Check if the BER measures are already available */
rc = mb86a20s_readreg(state, 0x54);
if (rc < 0)
return rc;
/* Check if data is available for that layer */
if (!(rc & (1 << layer))) {
dev_dbg(&state->i2c->dev,
"%s: preBER for layer %c is not available yet.\n",
__func__, 'A' + layer);
return -EBUSY;
}
/* Read Bit Error Count */
rc = mb86a20s_readreg(state, 0x55 + layer * 3);
if (rc < 0)
return rc;
*error = rc << 16;
rc = mb86a20s_readreg(state, 0x56 + layer * 3);
if (rc < 0)
return rc;
*error |= rc << 8;
rc = mb86a20s_readreg(state, 0x57 + layer * 3);
if (rc < 0)
return rc;
*error |= rc;
dev_dbg(&state->i2c->dev,
"%s: bit error before Viterbi for layer %c: %d.\n",
__func__, 'A' + layer, *error);
/* Read Bit Count */
rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*count = rc << 16;
rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*count |= rc << 8;
rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*count |= rc;
dev_dbg(&state->i2c->dev,
"%s: bit count before Viterbi for layer %c: %d.\n",
__func__, 'A' + layer, *count);
/*
* As we get TMCC data from the frontend, we can better estimate the
* BER bit counters, in order to do the BER measure during a longer
* time. Use those data, if available, to update the bit count
* measure.
*/
if (state->estimated_rate[layer]
&& state->estimated_rate[layer] != *count) {
dev_dbg(&state->i2c->dev,
"%s: updating layer %c preBER counter to %d.\n",
__func__, 'A' + layer, state->estimated_rate[layer]);
/* Turn off BER before Viterbi */
rc = mb86a20s_writereg(state, 0x52, 0x00);
/* Update counter for this layer */
rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51,
state->estimated_rate[layer] >> 16);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51,
state->estimated_rate[layer] >> 8);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51,
state->estimated_rate[layer]);
if (rc < 0)
return rc;
/* Turn on BER before Viterbi */
rc = mb86a20s_writereg(state, 0x52, 0x01);
/* Reset all preBER counters */
rc = mb86a20s_writereg(state, 0x53, 0x00);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x53, 0x07);
} else {
/* Reset counter to collect new data */
rc = mb86a20s_readreg(state, 0x53);
if (rc < 0)
return rc;
val = rc;
rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
}
return rc;
}
static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
unsigned layer,
u32 *error, u32 *count)
{
struct mb86a20s_state *state = fe->demodulator_priv;
u32 counter, collect_rate;
int rc, val;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (layer >= NUM_LAYERS)
return -EINVAL;
/* Check if the BER measures are already available */
rc = mb86a20s_readreg(state, 0x60);
if (rc < 0)
return rc;
/* Check if data is available for that layer */
if (!(rc & (1 << layer))) {
dev_dbg(&state->i2c->dev,
"%s: post BER for layer %c is not available yet.\n",
__func__, 'A' + layer);
return -EBUSY;
}
/* Read Bit Error Count */
rc = mb86a20s_readreg(state, 0x64 + layer * 3);
if (rc < 0)
return rc;
*error = rc << 16;
rc = mb86a20s_readreg(state, 0x65 + layer * 3);
if (rc < 0)
return rc;
*error |= rc << 8;
rc = mb86a20s_readreg(state, 0x66 + layer * 3);
if (rc < 0)
return rc;
*error |= rc;
dev_dbg(&state->i2c->dev,
"%s: post bit error for layer %c: %d.\n",
__func__, 'A' + layer, *error);
/* Read Bit Count */
rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
counter = rc << 8;
rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
counter |= rc;
*count = counter * 204 * 8;
dev_dbg(&state->i2c->dev,
"%s: post bit count for layer %c: %d.\n",
__func__, 'A' + layer, *count);
/*
* As we get TMCC data from the frontend, we can better estimate the
* BER bit counters, in order to do the BER measure during a longer
* time. Use those data, if available, to update the bit count
* measure.
*/
if (!state->estimated_rate[layer])
goto reset_measurement;
collect_rate = state->estimated_rate[layer] / 204 / 8;
if (collect_rate < 32)
collect_rate = 32;
if (collect_rate > 65535)
collect_rate = 65535;
if (collect_rate != counter) {
dev_dbg(&state->i2c->dev,
"%s: updating postBER counter on layer %c to %d.\n",
__func__, 'A' + layer, collect_rate);
/* Turn off BER after Viterbi */
rc = mb86a20s_writereg(state, 0x5e, 0x00);
/* Update counter for this layer */
rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
if (rc < 0)
return rc;
/* Turn on BER after Viterbi */
rc = mb86a20s_writereg(state, 0x5e, 0x07);
/* Reset all preBER counters */
rc = mb86a20s_writereg(state, 0x5f, 0x00);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x5f, 0x07);
return rc;
}
reset_measurement:
/* Reset counter to collect new data */
rc = mb86a20s_readreg(state, 0x5f);
if (rc < 0)
return rc;
val = rc;
rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
return rc;
}
static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
unsigned layer,
u32 *error, u32 *count)
{
struct mb86a20s_state *state = fe->demodulator_priv;
int rc, val;
u32 collect_rate;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (layer >= NUM_LAYERS)
return -EINVAL;
/* Check if the PER measures are already available */
rc = mb86a20s_writereg(state, 0x50, 0xb8);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
/* Check if data is available for that layer */
if (!(rc & (1 << layer))) {
dev_dbg(&state->i2c->dev,
"%s: block counts for layer %c aren't available yet.\n",
__func__, 'A' + layer);
return -EBUSY;
}
/* Read Packet error Count */
rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*error = rc << 8;
rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*error |= rc;
dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
__func__, 'A' + layer, *error);
/* Read Bit Count */
rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*count = rc << 8;
rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
*count |= rc;
dev_dbg(&state->i2c->dev,
"%s: block count for layer %c: %d.\n",
__func__, 'A' + layer, *count);
/*
* As we get TMCC data from the frontend, we can better estimate the
* BER bit counters, in order to do the BER measure during a longer
* time. Use those data, if available, to update the bit count
* measure.
*/
if (!state->estimated_rate[layer])
goto reset_measurement;
collect_rate = state->estimated_rate[layer] / 204 / 8;
if (collect_rate < 32)
collect_rate = 32;
if (collect_rate > 65535)
collect_rate = 65535;
if (collect_rate != *count) {
dev_dbg(&state->i2c->dev,
"%s: updating PER counter on layer %c to %d.\n",
__func__, 'A' + layer, collect_rate);
/* Stop PER measurement */
rc = mb86a20s_writereg(state, 0x50, 0xb0);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, 0x00);
if (rc < 0)
return rc;
/* Update this layer's counter */
rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
if (rc < 0)
return rc;
/* start PER measurement */
rc = mb86a20s_writereg(state, 0x50, 0xb0);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, 0x07);
if (rc < 0)
return rc;
/* Reset all counters to collect new data */
rc = mb86a20s_writereg(state, 0x50, 0xb1);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, 0x07);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, 0x00);
return rc;
}
reset_measurement:
/* Reset counter to collect new data */
rc = mb86a20s_writereg(state, 0x50, 0xb1);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
val = rc;
rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
return rc;
}
struct linear_segments {
unsigned x, y;
};
/*
* All tables below return a dB/1000 measurement
*/
static const struct linear_segments cnr_to_db_table[] = {
{ 19648, 0},
{ 18187, 1000},
{ 16534, 2000},
{ 14823, 3000},
{ 13161, 4000},
{ 11622, 5000},
{ 10279, 6000},
{ 9089, 7000},
{ 8042, 8000},
{ 7137, 9000},
{ 6342, 10000},
{ 5641, 11000},
{ 5030, 12000},
{ 4474, 13000},
{ 3988, 14000},
{ 3556, 15000},
{ 3180, 16000},
{ 2841, 17000},
{ 2541, 18000},
{ 2276, 19000},
{ 2038, 20000},
{ 1800, 21000},
{ 1625, 22000},
{ 1462, 23000},
{ 1324, 24000},
{ 1175, 25000},
{ 1063, 26000},
{ 980, 27000},
{ 907, 28000},
{ 840, 29000},
{ 788, 30000},
};
static const struct linear_segments cnr_64qam_table[] = {
{ 3922688, 0},
{ 3920384, 1000},
{ 3902720, 2000},
{ 3894784, 3000},
{ 3882496, 4000},
{ 3872768, 5000},
{ 3858944, 6000},
{ 3851520, 7000},
{ 3838976, 8000},
{ 3829248, 9000},
{ 3818240, 10000},
{ 3806976, 11000},
{ 3791872, 12000},
{ 3767040, 13000},
{ 3720960, 14000},
{ 3637504, 15000},
{ 3498496, 16000},
{ 3296000, 17000},
{ 3031040, 18000},
{ 2715392, 19000},
{ 2362624, 20000},
{ 1963264, 21000},
{ 1649664, 22000},
{ 1366784, 23000},
{ 1120768, 24000},
{ 890880, 25000},
{ 723456, 26000},
{ 612096, 27000},
{ 518912, 28000},
{ 448256, 29000},
{ 388864, 30000},
};
static const struct linear_segments cnr_16qam_table[] = {
{ 5314816, 0},
{ 5219072, 1000},
{ 5118720, 2000},
{ 4998912, 3000},
{ 4875520, 4000},
{ 4736000, 5000},
{ 4604160, 6000},
{ 4458752, 7000},
{ 4300288, 8000},
{ 4092928, 9000},
{ 3836160, 10000},
{ 3521024, 11000},
{ 3155968, 12000},
{ 2756864, 13000},
{ 2347008, 14000},
{ 1955072, 15000},
{ 1593600, 16000},
{ 1297920, 17000},
{ 1043968, 18000},
{ 839680, 19000},
{ 672256, 20000},
{ 523008, 21000},
{ 424704, 22000},
{ 345088, 23000},
{ 280064, 24000},
{ 221440, 25000},
{ 179712, 26000},
{ 151040, 27000},
{ 128512, 28000},
{ 110080, 29000},
{ 95744, 30000},
};
static const struct linear_segments cnr_qpsk_table[] = {
{ 2834176, 0},
{ 2683648, 1000},
{ 2536960, 2000},
{ 2391808, 3000},
{ 2133248, 4000},
{ 1906176, 5000},
{ 1666560, 6000},
{ 1422080, 7000},
{ 1189632, 8000},
{ 976384, 9000},
{ 790272, 10000},
{ 633344, 11000},
{ 505600, 12000},
{ 402944, 13000},
{ 320768, 14000},
{ 255488, 15000},
{ 204032, 16000},
{ 163072, 17000},
{ 130304, 18000},
{ 105216, 19000},
{ 83456, 20000},
{ 65024, 21000},
{ 52480, 22000},
{ 42752, 23000},
{ 34560, 24000},
{ 27136, 25000},
{ 22016, 26000},
{ 18432, 27000},
{ 15616, 28000},
{ 13312, 29000},
{ 11520, 30000},
};
static u32 interpolate_value(u32 value, const struct linear_segments *segments,
unsigned len)
{
u64 tmp64;
u32 dx, dy;
int i, ret;
if (value >= segments[0].x)
return segments[0].y;
if (value < segments[len-1].x)
return segments[len-1].y;
for (i = 1; i < len - 1; i++) {
/* If value is identical, no need to interpolate */
if (value == segments[i].x)
return segments[i].y;
if (value > segments[i].x)
break;
}
/* Linear interpolation between the two (x,y) points */
dy = segments[i].y - segments[i - 1].y;
dx = segments[i - 1].x - segments[i].x;
tmp64 = value - segments[i].x;
tmp64 *= dy;
do_div(tmp64, dx);
ret = segments[i].y - tmp64;
return ret;
}
static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 cnr_linear, cnr;
int rc, val;
/* Check if CNR is available */
rc = mb86a20s_readreg(state, 0x45);
if (rc < 0)
return rc;
if (!(rc & 0x40)) {
dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
__func__);
return -EBUSY;
}
val = rc;
rc = mb86a20s_readreg(state, 0x46);
if (rc < 0)
return rc;
cnr_linear = rc << 8;
rc = mb86a20s_readreg(state, 0x46);
if (rc < 0)
return rc;
cnr_linear |= rc;
cnr = interpolate_value(cnr_linear,
cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
__func__, cnr / 1000, cnr % 1000, cnr_linear);
/* CNR counter reset */
rc = mb86a20s_writereg(state, 0x45, val | 0x10);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
return rc;
}
static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 mer, cnr;
int rc, val, layer;
const struct linear_segments *segs;
unsigned segs_len;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
/* Check if the measures are already available */
rc = mb86a20s_writereg(state, 0x50, 0x5b);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
/* Check if data is available */
if (!(rc & 0x01)) {
dev_dbg(&state->i2c->dev,
"%s: MER measures aren't available yet.\n", __func__);
return -EBUSY;
}
/* Read all layers */
for (layer = 0; layer < NUM_LAYERS; layer++) {
if (!(c->isdbt_layer_enabled & (1 << layer))) {
c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
continue;
}
rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
mer = rc << 16;
rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
mer |= rc << 8;
rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
mer |= rc;
switch (c->layer[layer].modulation) {
case DQPSK:
case QPSK:
segs = cnr_qpsk_table;
segs_len = ARRAY_SIZE(cnr_qpsk_table);
break;
case QAM_16:
segs = cnr_16qam_table;
segs_len = ARRAY_SIZE(cnr_16qam_table);
break;
default:
case QAM_64:
segs = cnr_64qam_table;
segs_len = ARRAY_SIZE(cnr_64qam_table);
break;
}
cnr = interpolate_value(mer, segs, segs_len);
c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
c->cnr.stat[1 + layer].svalue = cnr;
dev_dbg(&state->i2c->dev,
"%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
__func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
}
/* Start a new MER measurement */
/* MER counter reset */
rc = mb86a20s_writereg(state, 0x50, 0x50);
if (rc < 0)
return rc;
rc = mb86a20s_readreg(state, 0x51);
if (rc < 0)
return rc;
val = rc;
rc = mb86a20s_writereg(state, 0x51, val | 0x01);
if (rc < 0)
return rc;
rc = mb86a20s_writereg(state, 0x51, val & 0x06);
if (rc < 0)
return rc;
return 0;
}
static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int layer;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
/* Fill the length of each status counter */
/* Only global stats */
c->strength.len = 1;
/* Per-layer stats - 3 layers + global */
c->cnr.len = NUM_LAYERS + 1;
c->pre_bit_error.len = NUM_LAYERS + 1;
c->pre_bit_count.len = NUM_LAYERS + 1;
c->post_bit_error.len = NUM_LAYERS + 1;
c->post_bit_count.len = NUM_LAYERS + 1;
c->block_error.len = NUM_LAYERS + 1;
c->block_count.len = NUM_LAYERS + 1;
/* Signal is always available */
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = 0;
/* Put all of them at FE_SCALE_NOT_AVAILABLE */
for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
}
}
static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int rc = 0, layer;
u32 bit_error = 0, bit_count = 0;
u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
u32 t_post_bit_error = 0, t_post_bit_count = 0;
u32 block_error = 0, block_count = 0;
u32 t_block_error = 0, t_block_count = 0;
int pre_ber_layers = 0, post_ber_layers = 0;
int per_layers = 0;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
mb86a20s_get_main_CNR(fe);
/* Get per-layer stats */
mb86a20s_get_blk_error_layer_CNR(fe);
/*
* At state 7, only CNR is available
* For BER measures, state=9 is required
* FIXME: we may get MER measures with state=8
*/
if (status_nr < 9)
return 0;
for (layer = 0; layer < NUM_LAYERS; layer++) {
if (c->isdbt_layer_enabled & (1 << layer)) {
/* Handle BER before vterbi */
rc = mb86a20s_get_pre_ber(fe, layer,
&bit_error, &bit_count);
if (rc >= 0) {
c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
} else if (rc != -EBUSY) {
/*
* If an I/O error happened,
* measures are now unavailable
*/
c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
dev_err(&state->i2c->dev,
"%s: Can't get BER for layer %c (error %d).\n",
__func__, 'A' + layer, rc);
}
if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
pre_ber_layers++;
/* Handle BER post vterbi */
rc = mb86a20s_get_post_ber(fe, layer,
&bit_error, &bit_count);
if (rc >= 0) {
c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[1 + layer].uvalue += bit_error;
c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[1 + layer].uvalue += bit_count;
} else if (rc != -EBUSY) {
/*
* If an I/O error happened,
* measures are now unavailable
*/
c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
dev_err(&state->i2c->dev,
"%s: Can't get BER for layer %c (error %d).\n",
__func__, 'A' + layer, rc);
}
if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
post_ber_layers++;
/* Handle Block errors for PER/UCB reports */
rc = mb86a20s_get_blk_error(fe, layer,
&block_error,
&block_count);
if (rc >= 0) {
c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->block_error.stat[1 + layer].uvalue += block_error;
c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
c->block_count.stat[1 + layer].uvalue += block_count;
} else if (rc != -EBUSY) {
/*
* If an I/O error happened,
* measures are now unavailable
*/
c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
dev_err(&state->i2c->dev,
"%s: Can't get PER for layer %c (error %d).\n",
__func__, 'A' + layer, rc);
}
if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
per_layers++;
/* Update total preBER */
t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
/* Update total postBER */
t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
/* Update total PER */
t_block_error += c->block_error.stat[1 + layer].uvalue;
t_block_count += c->block_count.stat[1 + layer].uvalue;
}
}
/*
* Start showing global count if at least one error count is
* available.
*/
if (pre_ber_layers) {
/*
* At least one per-layer BER measure was read. We can now
* calculate the total BER
*
* Total Bit Error/Count is calculated as the sum of the
* bit errors on all active layers.
*/
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
} else {
c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
}
/*
* Start showing global count if at least one error count is
* available.
*/
if (post_ber_layers) {
/*
* At least one per-layer BER measure was read. We can now
* calculate the total BER
*
* Total Bit Error/Count is calculated as the sum of the
* bit errors on all active layers.
*/
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = t_post_bit_error;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = t_post_bit_count;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
}
if (per_layers) {
/*
* At least one per-layer UCB measure was read. We can now
* calculate the total UCB
*
* Total block Error/Count is calculated as the sum of the
* block errors on all active layers.
*/
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = t_block_error;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue = t_block_count;
} else {
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
}
return rc;
}
/*
* The functions below are called via DVB callbacks, so they need to
* properly use the I2C gate control
*/
static int mb86a20s_initfe(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
u64 pll;
u32 fclk;
int rc;
u8 regD5 = 1, reg71, reg09 = 0x3a;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
/* Initialize the frontend */
rc = mb86a20s_writeregdata(state, mb86a20s_init1);
if (rc < 0)
goto err;
if (!state->inversion)
reg09 |= 0x04;
rc = mb86a20s_writereg(state, 0x09, reg09);
if (rc < 0)
goto err;
if (!state->bw)
reg71 = 1;
else
reg71 = 0;
rc = mb86a20s_writereg(state, 0x39, reg71);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x71, state->bw);
if (rc < 0)
goto err;
if (state->subchannel) {
rc = mb86a20s_writereg(state, 0x44, state->subchannel);
if (rc < 0)
goto err;
}
fclk = state->config->fclk;
if (!fclk)
fclk = 32571428;
/* Adjust IF frequency to match tuner */
if (fe->ops.tuner_ops.get_if_frequency)
fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
if (!state->if_freq)
state->if_freq = 3300000;
pll = (((u64)1) << 34) * state->if_freq;
do_div(pll, 63 * fclk);
pll = (1 << 25) - pll;
rc = mb86a20s_writereg(state, 0x28, 0x2a);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
if (rc < 0)
goto err;
dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
__func__, fclk, state->if_freq, (long long)pll);
/* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
pll = state->if_freq * 1677721600L;
do_div(pll, 1628571429L);
rc = mb86a20s_writereg(state, 0x28, 0x20);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
if (rc < 0)
goto err;
dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
__func__, state->if_freq, (long long)pll);
if (!state->config->is_serial)
regD5 &= ~1;
rc = mb86a20s_writereg(state, 0x50, 0xd5);
if (rc < 0)
goto err;
rc = mb86a20s_writereg(state, 0x51, regD5);
if (rc < 0)
goto err;
rc = mb86a20s_writeregdata(state, mb86a20s_init2);
if (rc < 0)
goto err;
err:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (rc < 0) {
state->need_init = true;
dev_info(&state->i2c->dev,
"mb86a20s: Init failed. Will try again later\n");
} else {
state->need_init = false;
dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
}
return rc;
}
static int mb86a20s_set_frontend(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int rc, if_freq;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (!c->isdbt_layer_enabled)
c->isdbt_layer_enabled = 7;
if (c->isdbt_layer_enabled == 1)
state->bw = MB86A20S_1SEG;
else if (c->isdbt_partial_reception)
state->bw = MB86A20S_13SEG_PARTIAL;
else
state->bw = MB86A20S_13SEG;
if (c->inversion == INVERSION_ON)
state->inversion = true;
else
state->inversion = false;
if (!c->isdbt_sb_mode) {
state->subchannel = 0;
} else {
if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
c->isdbt_sb_subchannel = 0;
state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
}
/*
* Gate should already be opened, but it doesn't hurt to
* double-check
*/
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.tuner_ops.get_if_frequency)
fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
/*
* Make it more reliable: if, for some reason, the initial
* device initialization doesn't happen, initialize it when
* a SBTVD parameters are adjusted.
*
* Unfortunately, due to a hard to track bug at tda829x/tda18271,
* the agc callback logic is not called during DVB attach time,
* causing mb86a20s to not be initialized with Kworld SBTVD.
* So, this hack is needed, in order to make Kworld SBTVD to work.
*
* It is also needed to change the IF after the initial init.
*
* HACK: Always init the frontend when set_frontend is called:
* it was noticed that, on some devices, it fails to lock on a
* different channel. So, it is better to reset everything, even
* wasting some time, than to loose channel lock.
*/
mb86a20s_initfe(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
mb86a20s_reset_counters(fe);
mb86a20s_stats_not_ready(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
return rc;
}
static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
enum fe_status *status)
{
struct mb86a20s_state *state = fe->demodulator_priv;
int rc, status_nr;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
/* Get lock */
status_nr = mb86a20s_read_status(fe, status);
if (status_nr < 7) {
mb86a20s_stats_not_ready(fe);
mb86a20s_reset_frontend_cache(fe);
}
if (status_nr < 0) {
dev_err(&state->i2c->dev,
"%s: Can't read frontend lock status\n", __func__);
rc = status_nr;
goto error;
}
/* Get signal strength */
rc = mb86a20s_read_signal_strength(fe);
if (rc < 0) {
dev_err(&state->i2c->dev,
"%s: Can't reset VBER registers.\n", __func__);
mb86a20s_stats_not_ready(fe);
mb86a20s_reset_frontend_cache(fe);
rc = 0; /* Status is OK */
goto error;
}
if (status_nr >= 7) {
/* Get TMCC info*/
rc = mb86a20s_get_frontend(fe);
if (rc < 0) {
dev_err(&state->i2c->dev,
"%s: Can't get FE TMCC data.\n", __func__);
rc = 0; /* Status is OK */
goto error;
}
/* Get statistics */
rc = mb86a20s_get_stats(fe, status_nr);
if (rc < 0 && rc != -EBUSY) {
dev_err(&state->i2c->dev,
"%s: Can't get FE statistics.\n", __func__);
rc = 0;
goto error;
}
rc = 0; /* Don't return EBUSY to userspace */
}
goto ok;
error:
mb86a20s_stats_not_ready(fe);
ok:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
return rc;
}
static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
u16 *strength)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
*strength = c->strength.stat[0].uvalue;
return 0;
}
static int mb86a20s_tune(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
struct mb86a20s_state *state = fe->demodulator_priv;
int rc = 0;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
if (re_tune)
rc = mb86a20s_set_frontend(fe);
if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
mb86a20s_read_status_and_stats(fe, status);
return rc;
}
static void mb86a20s_release(struct dvb_frontend *fe)
{
struct mb86a20s_state *state = fe->demodulator_priv;
dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
kfree(state);
}
static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static const struct dvb_frontend_ops mb86a20s_ops;
struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
struct i2c_adapter *i2c)
{
struct mb86a20s_state *state;
u8 rev;
dev_dbg(&i2c->dev, "%s called.\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &mb86a20s_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* Check if it is a mb86a20s frontend */
rev = mb86a20s_readreg(state, 0);
if (rev != 0x13) {
kfree(state);
dev_dbg(&i2c->dev,
"Frontend revision %d is unknown - aborting.\n",
rev);
return NULL;
}
dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
return &state->frontend;
}
EXPORT_SYMBOL_GPL(mb86a20s_attach);
static const struct dvb_frontend_ops mb86a20s_ops = {
.delsys = { SYS_ISDBT },
/* Use dib8000 values per default */
.info = {
.name = "Fujitsu mb86A20s",
.caps = FE_CAN_RECOVER |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
/* Actually, those values depend on the used tuner */
.frequency_min_hz = 45 * MHz,
.frequency_max_hz = 864 * MHz,
.frequency_stepsize_hz = 62500,
},
.release = mb86a20s_release,
.init = mb86a20s_initfe,
.set_frontend = mb86a20s_set_frontend,
.read_status = mb86a20s_read_status_and_stats,
.read_signal_strength = mb86a20s_read_signal_strength_from_cache,
.tune = mb86a20s_tune,
.get_frontend_algo = mb86a20s_get_frontend_algo,
};
MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
MODULE_AUTHOR("Mauro Carvalho Chehab");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/mb86a20s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
Copyright (C) 2006-2008 Steven Toth <[email protected]>
Copyright (C) 2006-2007 Georg Acher
Copyright (C) 2007-2008 Darron Broad
March 2007
Fixed some bugs.
Added diseqc support.
Added corrected signal strength support.
August 2007
Sync with legacy version.
Some clean ups.
Copyright (C) 2008 Igor Liplianin
September, 9th 2008
Fixed locking on high symbol rates (>30000).
Implement MPEG initialization parameter.
January, 17th 2009
Fill set_voltage with actually control voltage code.
Correct set tone to not affect voltage.
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include <media/dvb_frontend.h>
#include "cx24116.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_INFO "cx24116: " args); \
} while (0)
#define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
#define CX24116_SEARCH_RANGE_KHZ 5000
/* known registers */
#define CX24116_REG_COMMAND (0x00) /* command args 0x00..0x1e */
#define CX24116_REG_EXECUTE (0x1f) /* execute command */
#define CX24116_REG_MAILBOX (0x96) /* FW or multipurpose mailbox? */
#define CX24116_REG_RESET (0x20) /* reset status > 0 */
#define CX24116_REG_SIGNAL (0x9e) /* signal low */
#define CX24116_REG_SSTATUS (0x9d) /* signal high / status */
#define CX24116_REG_QUALITY8 (0xa3)
#define CX24116_REG_QSTATUS (0xbc)
#define CX24116_REG_QUALITY0 (0xd5)
#define CX24116_REG_BER0 (0xc9)
#define CX24116_REG_BER8 (0xc8)
#define CX24116_REG_BER16 (0xc7)
#define CX24116_REG_BER24 (0xc6)
#define CX24116_REG_UCB0 (0xcb)
#define CX24116_REG_UCB8 (0xca)
#define CX24116_REG_CLKDIV (0xf3)
#define CX24116_REG_RATEDIV (0xf9)
/* configured fec (not tuned) or actual FEC (tuned) 1=1/2 2=2/3 etc */
#define CX24116_REG_FECSTATUS (0x9c)
/* FECSTATUS bits */
/* mask to determine configured fec (not tuned) or actual fec (tuned) */
#define CX24116_FEC_FECMASK (0x1f)
/* Select DVB-S demodulator, else DVB-S2 */
#define CX24116_FEC_DVBS (0x20)
#define CX24116_FEC_UNKNOWN (0x40) /* Unknown/unused */
/* Pilot mode requested when tuning else always reset when tuned */
#define CX24116_FEC_PILOT (0x80)
/* arg buffer size */
#define CX24116_ARGLEN (0x1e)
/* rolloff */
#define CX24116_ROLLOFF_020 (0x00)
#define CX24116_ROLLOFF_025 (0x01)
#define CX24116_ROLLOFF_035 (0x02)
/* pilot bit */
#define CX24116_PILOT_OFF (0x00)
#define CX24116_PILOT_ON (0x40)
/* signal status */
#define CX24116_HAS_SIGNAL (0x01)
#define CX24116_HAS_CARRIER (0x02)
#define CX24116_HAS_VITERBI (0x04)
#define CX24116_HAS_SYNCLOCK (0x08)
#define CX24116_HAS_UNKNOWN1 (0x10)
#define CX24116_HAS_UNKNOWN2 (0x20)
#define CX24116_STATUS_MASK (0x0f)
#define CX24116_SIGNAL_MASK (0xc0)
#define CX24116_DISEQC_TONEOFF (0) /* toneburst never sent */
#define CX24116_DISEQC_TONECACHE (1) /* toneburst cached */
#define CX24116_DISEQC_MESGCACHE (2) /* message cached */
/* arg offset for DiSEqC */
#define CX24116_DISEQC_BURST (1)
#define CX24116_DISEQC_ARG2_2 (2) /* unknown value=2 */
#define CX24116_DISEQC_ARG3_0 (3) /* unknown value=0 */
#define CX24116_DISEQC_ARG4_0 (4) /* unknown value=0 */
#define CX24116_DISEQC_MSGLEN (5)
#define CX24116_DISEQC_MSGOFS (6)
/* DiSEqC burst */
#define CX24116_DISEQC_MINI_A (0)
#define CX24116_DISEQC_MINI_B (1)
/* DiSEqC tone burst */
static int toneburst = 1;
module_param(toneburst, int, 0644);
MODULE_PARM_DESC(toneburst, "DiSEqC toneburst 0=OFF, 1=TONE CACHE, "\
"2=MESSAGE CACHE (default:1)");
/* SNR measurements */
static int esno_snr;
module_param(esno_snr, int, 0644);
MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
"1=ESNO(db * 10) (default:0)");
enum cmds {
CMD_SET_VCO = 0x10,
CMD_TUNEREQUEST = 0x11,
CMD_MPEGCONFIG = 0x13,
CMD_TUNERINIT = 0x14,
CMD_BANDWIDTH = 0x15,
CMD_GETAGC = 0x19,
CMD_LNBCONFIG = 0x20,
CMD_LNBSEND = 0x21, /* Formerly CMD_SEND_DISEQC */
CMD_LNBDCLEVEL = 0x22,
CMD_SET_TONE = 0x23,
CMD_UPDFWVERS = 0x35,
CMD_TUNERSLEEP = 0x36,
CMD_AGCCONTROL = 0x3b, /* Unknown */
};
/* The Demod/Tuner can't easily provide these, we cache them */
struct cx24116_tuning {
u32 frequency;
u32 symbol_rate;
enum fe_spectral_inversion inversion;
enum fe_code_rate fec;
enum fe_delivery_system delsys;
enum fe_modulation modulation;
enum fe_pilot pilot;
enum fe_rolloff rolloff;
/* Demod values */
u8 fec_val;
u8 fec_mask;
u8 inversion_val;
u8 pilot_val;
u8 rolloff_val;
};
/* Basic commands that are sent to the firmware */
struct cx24116_cmd {
u8 len;
u8 args[CX24116_ARGLEN];
};
struct cx24116_state {
struct i2c_adapter *i2c;
const struct cx24116_config *config;
struct dvb_frontend frontend;
struct cx24116_tuning dcur;
struct cx24116_tuning dnxt;
u8 skip_fw_load;
u8 burst;
struct cx24116_cmd dsec_cmd;
};
static int cx24116_writereg(struct cx24116_state *state, int reg, int data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address,
.flags = 0, .buf = buf, .len = 2 };
int err;
if (debug > 1)
printk("cx24116: %s: write reg 0x%02x, value 0x%02x\n",
__func__, reg, data);
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
__func__, err, reg, data);
return -EREMOTEIO;
}
return 0;
}
/* Bulk byte writes to a single I2C address, for 32k firmware load */
static int cx24116_writeregN(struct cx24116_state *state, int reg,
const u8 *data, u16 len)
{
int ret;
struct i2c_msg msg;
u8 *buf;
buf = kmalloc(len + 1, GFP_KERNEL);
if (!buf)
return -ENOMEM;
*(buf) = reg;
memcpy(buf + 1, data, len);
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.buf = buf;
msg.len = len + 1;
if (debug > 1)
printk(KERN_INFO "cx24116: %s: write regN 0x%02x, len = %d\n",
__func__, reg, len);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x\n",
__func__, ret, reg);
ret = -EREMOTEIO;
}
kfree(buf);
return ret;
}
static int cx24116_readreg(struct cx24116_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0,
.buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD,
.buf = b1, .len = 1 }
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk(KERN_ERR "%s: reg=0x%x (error=%d)\n",
__func__, reg, ret);
return ret;
}
if (debug > 1)
printk(KERN_INFO "cx24116: read reg 0x%02x, value 0x%02x\n",
reg, b1[0]);
return b1[0];
}
static int cx24116_set_inversion(struct cx24116_state *state,
enum fe_spectral_inversion inversion)
{
dprintk("%s(%d)\n", __func__, inversion);
switch (inversion) {
case INVERSION_OFF:
state->dnxt.inversion_val = 0x00;
break;
case INVERSION_ON:
state->dnxt.inversion_val = 0x04;
break;
case INVERSION_AUTO:
state->dnxt.inversion_val = 0x0C;
break;
default:
return -EINVAL;
}
state->dnxt.inversion = inversion;
return 0;
}
/*
* modfec (modulation and FEC)
* ===========================
*
* MOD FEC mask/val standard
* ---- -------- ----------- --------
* QPSK FEC_1_2 0x02 0x02+X DVB-S
* QPSK FEC_2_3 0x04 0x02+X DVB-S
* QPSK FEC_3_4 0x08 0x02+X DVB-S
* QPSK FEC_4_5 0x10 0x02+X DVB-S (?)
* QPSK FEC_5_6 0x20 0x02+X DVB-S
* QPSK FEC_6_7 0x40 0x02+X DVB-S
* QPSK FEC_7_8 0x80 0x02+X DVB-S
* QPSK FEC_8_9 0x01 0x02+X DVB-S (?) (NOT SUPPORTED?)
* QPSK AUTO 0xff 0x02+X DVB-S
*
* For DVB-S high byte probably represents FEC
* and low byte selects the modulator. The high
* byte is search range mask. Bit 5 may turn
* on DVB-S and remaining bits represent some
* kind of calibration (how/what i do not know).
*
* Eg.(2/3) szap "Zone Horror"
*
* mask/val = 0x04, 0x20
* status 1f | signal c3c0 | snr a333 | ber 00000098 | unc 0 | FE_HAS_LOCK
*
* mask/val = 0x04, 0x30
* status 1f | signal c3c0 | snr a333 | ber 00000000 | unc 0 | FE_HAS_LOCK
*
* After tuning FECSTATUS contains actual FEC
* in use numbered 1 through to 8 for 1/2 .. 2/3 etc
*
* NBC=NOT/NON BACKWARD COMPATIBLE WITH DVB-S (DVB-S2 only)
*
* NBC-QPSK FEC_1_2 0x00, 0x04 DVB-S2
* NBC-QPSK FEC_3_5 0x00, 0x05 DVB-S2
* NBC-QPSK FEC_2_3 0x00, 0x06 DVB-S2
* NBC-QPSK FEC_3_4 0x00, 0x07 DVB-S2
* NBC-QPSK FEC_4_5 0x00, 0x08 DVB-S2
* NBC-QPSK FEC_5_6 0x00, 0x09 DVB-S2
* NBC-QPSK FEC_8_9 0x00, 0x0a DVB-S2
* NBC-QPSK FEC_9_10 0x00, 0x0b DVB-S2
*
* NBC-8PSK FEC_3_5 0x00, 0x0c DVB-S2
* NBC-8PSK FEC_2_3 0x00, 0x0d DVB-S2
* NBC-8PSK FEC_3_4 0x00, 0x0e DVB-S2
* NBC-8PSK FEC_5_6 0x00, 0x0f DVB-S2
* NBC-8PSK FEC_8_9 0x00, 0x10 DVB-S2
* NBC-8PSK FEC_9_10 0x00, 0x11 DVB-S2
*
* For DVB-S2 low bytes selects both modulator
* and FEC. High byte is meaningless here. To
* set pilot, bit 6 (0x40) is set. When inspecting
* FECSTATUS bit 7 (0x80) represents the pilot
* selection whilst not tuned. When tuned, actual FEC
* in use is found in FECSTATUS as per above. Pilot
* value is reset.
*/
/* A table of modulation, fec and configuration bytes for the demod.
* Not all S2 mmodulation schemes are support and not all rates with
* a scheme are support. Especially, no auto detect when in S2 mode.
*/
static struct cx24116_modfec {
enum fe_delivery_system delivery_system;
enum fe_modulation modulation;
enum fe_code_rate fec;
u8 mask; /* In DVBS mode this is used to autodetect */
u8 val; /* Passed to the firmware to indicate mode selection */
} CX24116_MODFEC_MODES[] = {
/* QPSK. For unknown rates we set hardware to auto detect 0xfe 0x30 */
/*mod fec mask val */
{ SYS_DVBS, QPSK, FEC_NONE, 0xfe, 0x30 },
{ SYS_DVBS, QPSK, FEC_1_2, 0x02, 0x2e }, /* 00000010 00101110 */
{ SYS_DVBS, QPSK, FEC_2_3, 0x04, 0x2f }, /* 00000100 00101111 */
{ SYS_DVBS, QPSK, FEC_3_4, 0x08, 0x30 }, /* 00001000 00110000 */
{ SYS_DVBS, QPSK, FEC_4_5, 0xfe, 0x30 }, /* 000?0000 ? */
{ SYS_DVBS, QPSK, FEC_5_6, 0x20, 0x31 }, /* 00100000 00110001 */
{ SYS_DVBS, QPSK, FEC_6_7, 0xfe, 0x30 }, /* 0?000000 ? */
{ SYS_DVBS, QPSK, FEC_7_8, 0x80, 0x32 }, /* 10000000 00110010 */
{ SYS_DVBS, QPSK, FEC_8_9, 0xfe, 0x30 }, /* 0000000? ? */
{ SYS_DVBS, QPSK, FEC_AUTO, 0xfe, 0x30 },
/* NBC-QPSK */
{ SYS_DVBS2, QPSK, FEC_1_2, 0x00, 0x04 },
{ SYS_DVBS2, QPSK, FEC_3_5, 0x00, 0x05 },
{ SYS_DVBS2, QPSK, FEC_2_3, 0x00, 0x06 },
{ SYS_DVBS2, QPSK, FEC_3_4, 0x00, 0x07 },
{ SYS_DVBS2, QPSK, FEC_4_5, 0x00, 0x08 },
{ SYS_DVBS2, QPSK, FEC_5_6, 0x00, 0x09 },
{ SYS_DVBS2, QPSK, FEC_8_9, 0x00, 0x0a },
{ SYS_DVBS2, QPSK, FEC_9_10, 0x00, 0x0b },
/* 8PSK */
{ SYS_DVBS2, PSK_8, FEC_3_5, 0x00, 0x0c },
{ SYS_DVBS2, PSK_8, FEC_2_3, 0x00, 0x0d },
{ SYS_DVBS2, PSK_8, FEC_3_4, 0x00, 0x0e },
{ SYS_DVBS2, PSK_8, FEC_5_6, 0x00, 0x0f },
{ SYS_DVBS2, PSK_8, FEC_8_9, 0x00, 0x10 },
{ SYS_DVBS2, PSK_8, FEC_9_10, 0x00, 0x11 },
/*
* `val' can be found in the FECSTATUS register when tuning.
* FECSTATUS will give the actual FEC in use if tuning was successful.
*/
};
static int cx24116_lookup_fecmod(struct cx24116_state *state,
enum fe_delivery_system d, enum fe_modulation m, enum fe_code_rate f)
{
int i, ret = -EOPNOTSUPP;
dprintk("%s(0x%02x,0x%02x)\n", __func__, m, f);
for (i = 0; i < ARRAY_SIZE(CX24116_MODFEC_MODES); i++) {
if ((d == CX24116_MODFEC_MODES[i].delivery_system) &&
(m == CX24116_MODFEC_MODES[i].modulation) &&
(f == CX24116_MODFEC_MODES[i].fec)) {
ret = i;
break;
}
}
return ret;
}
static int cx24116_set_fec(struct cx24116_state *state,
enum fe_delivery_system delsys,
enum fe_modulation mod,
enum fe_code_rate fec)
{
int ret = 0;
dprintk("%s(0x%02x,0x%02x)\n", __func__, mod, fec);
ret = cx24116_lookup_fecmod(state, delsys, mod, fec);
if (ret < 0)
return ret;
state->dnxt.fec = fec;
state->dnxt.fec_val = CX24116_MODFEC_MODES[ret].val;
state->dnxt.fec_mask = CX24116_MODFEC_MODES[ret].mask;
dprintk("%s() mask/val = 0x%02x/0x%02x\n", __func__,
state->dnxt.fec_mask, state->dnxt.fec_val);
return 0;
}
static int cx24116_set_symbolrate(struct cx24116_state *state, u32 rate)
{
dprintk("%s(%d)\n", __func__, rate);
/* check if symbol rate is within limits */
if ((rate > state->frontend.ops.info.symbol_rate_max) ||
(rate < state->frontend.ops.info.symbol_rate_min)) {
dprintk("%s() unsupported symbol_rate = %d\n", __func__, rate);
return -EOPNOTSUPP;
}
state->dnxt.symbol_rate = rate;
dprintk("%s() symbol_rate = %d\n", __func__, rate);
return 0;
}
static int cx24116_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw);
static int cx24116_firmware_ondemand(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
const struct firmware *fw;
int ret = 0;
dprintk("%s()\n", __func__);
if (cx24116_readreg(state, 0x20) > 0) {
if (state->skip_fw_load)
return 0;
/* Load firmware */
/* request the firmware, this will block until loaded */
printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n",
__func__, CX24116_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, CX24116_DEFAULT_FIRMWARE,
state->i2c->dev.parent);
printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n",
__func__);
if (ret) {
printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
__func__);
return ret;
}
/* Make sure we don't recurse back through here
* during loading */
state->skip_fw_load = 1;
ret = cx24116_load_firmware(fe, fw);
if (ret)
printk(KERN_ERR "%s: Writing firmware to device failed\n",
__func__);
release_firmware(fw);
printk(KERN_INFO "%s: Firmware upload %s\n", __func__,
ret == 0 ? "complete" : "failed");
/* Ensure firmware is always loaded if required */
state->skip_fw_load = 0;
}
return ret;
}
/* Take a basic firmware command structure, format it
* and forward it for processing
*/
static int cx24116_cmd_execute(struct dvb_frontend *fe, struct cx24116_cmd *cmd)
{
struct cx24116_state *state = fe->demodulator_priv;
int i, ret;
dprintk("%s()\n", __func__);
/* Load the firmware if required */
ret = cx24116_firmware_ondemand(fe);
if (ret != 0) {
printk(KERN_ERR "%s(): Unable initialise the firmware\n",
__func__);
return ret;
}
/* Write the command */
for (i = 0; i < cmd->len ; i++) {
dprintk("%s: 0x%02x == 0x%02x\n", __func__, i, cmd->args[i]);
cx24116_writereg(state, i, cmd->args[i]);
}
/* Start execution and wait for cmd to terminate */
cx24116_writereg(state, CX24116_REG_EXECUTE, 0x01);
while (cx24116_readreg(state, CX24116_REG_EXECUTE)) {
msleep(10);
if (i++ > 64) {
/* Avoid looping forever if the firmware does
not respond */
printk(KERN_WARNING "%s() Firmware not responding\n",
__func__);
return -EREMOTEIO;
}
}
return 0;
}
static int cx24116_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw)
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
int i, ret, len, max, remaining;
unsigned char vers[4];
dprintk("%s\n", __func__);
dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
fw->size,
fw->data[0],
fw->data[1],
fw->data[fw->size-2],
fw->data[fw->size-1]);
/* Toggle 88x SRST pin to reset demod */
if (state->config->reset_device)
state->config->reset_device(fe);
/* Begin the firmware load process */
/* Prepare the demod, load the firmware, cleanup after load */
/* Init PLL */
cx24116_writereg(state, 0xE5, 0x00);
cx24116_writereg(state, 0xF1, 0x08);
cx24116_writereg(state, 0xF2, 0x13);
/* Start PLL */
cx24116_writereg(state, 0xe0, 0x03);
cx24116_writereg(state, 0xe0, 0x00);
/* Unknown */
cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
/* Unknown */
cx24116_writereg(state, 0xF0, 0x03);
cx24116_writereg(state, 0xF4, 0x81);
cx24116_writereg(state, 0xF5, 0x00);
cx24116_writereg(state, 0xF6, 0x00);
/* Split firmware to the max I2C write len and write.
* Writes whole firmware as one write when i2c_wr_max is set to 0. */
if (state->config->i2c_wr_max)
max = state->config->i2c_wr_max;
else
max = INT_MAX; /* enough for 32k firmware */
for (remaining = fw->size; remaining > 0; remaining -= max - 1) {
len = remaining;
if (len > max - 1)
len = max - 1;
cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining],
len);
}
cx24116_writereg(state, 0xF4, 0x10);
cx24116_writereg(state, 0xF0, 0x00);
cx24116_writereg(state, 0xF8, 0x06);
/* Firmware CMD 10: VCO config */
cmd.args[0x00] = CMD_SET_VCO;
cmd.args[0x01] = 0x05;
cmd.args[0x02] = 0xdc;
cmd.args[0x03] = 0xda;
cmd.args[0x04] = 0xae;
cmd.args[0x05] = 0xaa;
cmd.args[0x06] = 0x04;
cmd.args[0x07] = 0x9d;
cmd.args[0x08] = 0xfc;
cmd.args[0x09] = 0x06;
cmd.len = 0x0a;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
cx24116_writereg(state, CX24116_REG_SSTATUS, 0x00);
/* Firmware CMD 14: Tuner config */
cmd.args[0x00] = CMD_TUNERINIT;
cmd.args[0x01] = 0x00;
cmd.args[0x02] = 0x00;
cmd.len = 0x03;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
cx24116_writereg(state, 0xe5, 0x00);
/* Firmware CMD 13: MPEG config */
cmd.args[0x00] = CMD_MPEGCONFIG;
cmd.args[0x01] = 0x01;
cmd.args[0x02] = 0x75;
cmd.args[0x03] = 0x00;
if (state->config->mpg_clk_pos_pol)
cmd.args[0x04] = state->config->mpg_clk_pos_pol;
else
cmd.args[0x04] = 0x02;
cmd.args[0x05] = 0x00;
cmd.len = 0x06;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
/* Firmware CMD 35: Get firmware version */
cmd.args[0x00] = CMD_UPDFWVERS;
cmd.len = 0x02;
for (i = 0; i < 4; i++) {
cmd.args[0x01] = i;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
vers[i] = cx24116_readreg(state, CX24116_REG_MAILBOX);
}
printk(KERN_INFO "%s: FW version %i.%i.%i.%i\n", __func__,
vers[0], vers[1], vers[2], vers[3]);
return 0;
}
static int cx24116_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx24116_state *state = fe->demodulator_priv;
int lock = cx24116_readreg(state, CX24116_REG_SSTATUS) &
CX24116_STATUS_MASK;
dprintk("%s: status = 0x%02x\n", __func__, lock);
*status = 0;
if (lock & CX24116_HAS_SIGNAL)
*status |= FE_HAS_SIGNAL;
if (lock & CX24116_HAS_CARRIER)
*status |= FE_HAS_CARRIER;
if (lock & CX24116_HAS_VITERBI)
*status |= FE_HAS_VITERBI;
if (lock & CX24116_HAS_SYNCLOCK)
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
static int cx24116_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cx24116_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
*ber = (cx24116_readreg(state, CX24116_REG_BER24) << 24) |
(cx24116_readreg(state, CX24116_REG_BER16) << 16) |
(cx24116_readreg(state, CX24116_REG_BER8) << 8) |
cx24116_readreg(state, CX24116_REG_BER0);
return 0;
}
/* TODO Determine function and scale appropriately */
static int cx24116_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
int ret;
u16 sig_reading;
dprintk("%s()\n", __func__);
/* Firmware CMD 19: Get AGC */
cmd.args[0x00] = CMD_GETAGC;
cmd.len = 0x01;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
sig_reading =
(cx24116_readreg(state,
CX24116_REG_SSTATUS) & CX24116_SIGNAL_MASK) |
(cx24116_readreg(state, CX24116_REG_SIGNAL) << 6);
*signal_strength = 0 - sig_reading;
dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n",
__func__, sig_reading, *signal_strength);
return 0;
}
/* SNR (0..100)% = (sig & 0xf0) * 10 + (sig & 0x0f) * 10 / 16 */
static int cx24116_read_snr_pct(struct dvb_frontend *fe, u16 *snr)
{
struct cx24116_state *state = fe->demodulator_priv;
u8 snr_reading;
static const u32 snr_tab[] = { /* 10 x Table (rounded up) */
0x00000, 0x0199A, 0x03333, 0x04ccD, 0x06667,
0x08000, 0x0999A, 0x0b333, 0x0cccD, 0x0e667,
0x10000, 0x1199A, 0x13333, 0x14ccD, 0x16667,
0x18000 };
dprintk("%s()\n", __func__);
snr_reading = cx24116_readreg(state, CX24116_REG_QUALITY0);
if (snr_reading >= 0xa0 /* 100% */)
*snr = 0xffff;
else
*snr = snr_tab[(snr_reading & 0xf0) >> 4] +
(snr_tab[(snr_reading & 0x0f)] >> 4);
dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
snr_reading, *snr);
return 0;
}
/* The reelbox patches show the value in the registers represents
* ESNO, from 0->30db (values 0->300). We provide this value by
* default.
*/
static int cx24116_read_snr_esno(struct dvb_frontend *fe, u16 *snr)
{
struct cx24116_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
*snr = cx24116_readreg(state, CX24116_REG_QUALITY8) << 8 |
cx24116_readreg(state, CX24116_REG_QUALITY0);
dprintk("%s: raw 0x%04x\n", __func__, *snr);
return 0;
}
static int cx24116_read_snr(struct dvb_frontend *fe, u16 *snr)
{
if (esno_snr == 1)
return cx24116_read_snr_esno(fe, snr);
else
return cx24116_read_snr_pct(fe, snr);
}
static int cx24116_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct cx24116_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
*ucblocks = (cx24116_readreg(state, CX24116_REG_UCB8) << 8) |
cx24116_readreg(state, CX24116_REG_UCB0);
return 0;
}
/* Overwrite the current tuning params, we are about to tune */
static void cx24116_clone_params(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
state->dcur = state->dnxt;
}
/* Wait for LNB */
static int cx24116_wait_for_lnb(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
int i;
dprintk("%s() qstatus = 0x%02x\n", __func__,
cx24116_readreg(state, CX24116_REG_QSTATUS));
/* Wait for up to 300 ms */
for (i = 0; i < 30 ; i++) {
if (cx24116_readreg(state, CX24116_REG_QSTATUS) & 0x20)
return 0;
msleep(10);
}
dprintk("%s(): LNB not ready\n", __func__);
return -ETIMEDOUT; /* -EBUSY ? */
}
static int cx24116_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx24116_cmd cmd;
int ret;
dprintk("%s: %s\n", __func__,
voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
/* Wait for LNB ready */
ret = cx24116_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Wait for voltage/min repeat delay */
msleep(100);
cmd.args[0x00] = CMD_LNBDCLEVEL;
cmd.args[0x01] = (voltage == SEC_VOLTAGE_18 ? 0x01 : 0x00);
cmd.len = 0x02;
/* Min delay time before DiSEqC send */
msleep(15);
return cx24116_cmd_execute(fe, &cmd);
}
static int cx24116_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct cx24116_cmd cmd;
int ret;
dprintk("%s(%d)\n", __func__, tone);
if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
return -EINVAL;
}
/* Wait for LNB ready */
ret = cx24116_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Min delay time after DiSEqC send */
msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
/* Now we set the tone */
cmd.args[0x00] = CMD_SET_TONE;
cmd.args[0x01] = 0x00;
cmd.args[0x02] = 0x00;
switch (tone) {
case SEC_TONE_ON:
dprintk("%s: setting tone on\n", __func__);
cmd.args[0x03] = 0x01;
break;
case SEC_TONE_OFF:
dprintk("%s: setting tone off\n", __func__);
cmd.args[0x03] = 0x00;
break;
}
cmd.len = 0x04;
/* Min delay time before DiSEqC send */
msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
return cx24116_cmd_execute(fe, &cmd);
}
/* Initialise DiSEqC */
static int cx24116_diseqc_init(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
int ret;
/* Firmware CMD 20: LNB/DiSEqC config */
cmd.args[0x00] = CMD_LNBCONFIG;
cmd.args[0x01] = 0x00;
cmd.args[0x02] = 0x10;
cmd.args[0x03] = 0x00;
cmd.args[0x04] = 0x8f;
cmd.args[0x05] = 0x28;
cmd.args[0x06] = (toneburst == CX24116_DISEQC_TONEOFF) ? 0x00 : 0x01;
cmd.args[0x07] = 0x01;
cmd.len = 0x08;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
/* Prepare a DiSEqC command */
state->dsec_cmd.args[0x00] = CMD_LNBSEND;
/* DiSEqC burst */
state->dsec_cmd.args[CX24116_DISEQC_BURST] = CX24116_DISEQC_MINI_A;
/* Unknown */
state->dsec_cmd.args[CX24116_DISEQC_ARG2_2] = 0x02;
state->dsec_cmd.args[CX24116_DISEQC_ARG3_0] = 0x00;
/* Continuation flag? */
state->dsec_cmd.args[CX24116_DISEQC_ARG4_0] = 0x00;
/* DiSEqC message length */
state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = 0x00;
/* Command length */
state->dsec_cmd.len = CX24116_DISEQC_MSGOFS;
return 0;
}
/* Send DiSEqC message with derived burst (hack) || previous burst */
static int cx24116_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *d)
{
struct cx24116_state *state = fe->demodulator_priv;
int i, ret;
/* Validate length */
if (d->msg_len > sizeof(d->msg))
return -EINVAL;
/* Dump DiSEqC message */
if (debug) {
printk(KERN_INFO "cx24116: %s(", __func__);
for (i = 0 ; i < d->msg_len ;) {
printk(KERN_INFO "0x%02x", d->msg[i]);
if (++i < d->msg_len)
printk(KERN_INFO ", ");
}
printk(") toneburst=%d\n", toneburst);
}
/* DiSEqC message */
for (i = 0; i < d->msg_len; i++)
state->dsec_cmd.args[CX24116_DISEQC_MSGOFS + i] = d->msg[i];
/* DiSEqC message length */
state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = d->msg_len;
/* Command length */
state->dsec_cmd.len = CX24116_DISEQC_MSGOFS +
state->dsec_cmd.args[CX24116_DISEQC_MSGLEN];
/* DiSEqC toneburst */
if (toneburst == CX24116_DISEQC_MESGCACHE)
/* Message is cached */
return 0;
else if (toneburst == CX24116_DISEQC_TONEOFF)
/* Message is sent without burst */
state->dsec_cmd.args[CX24116_DISEQC_BURST] = 0;
else if (toneburst == CX24116_DISEQC_TONECACHE) {
/*
* Message is sent with derived else cached burst
*
* WRITE PORT GROUP COMMAND 38
*
* 0/A/A: E0 10 38 F0..F3
* 1/B/B: E0 10 38 F4..F7
* 2/C/A: E0 10 38 F8..FB
* 3/D/B: E0 10 38 FC..FF
*
* databyte[3]= 8421:8421
* ABCD:WXYZ
* CLR :SET
*
* WX= PORT SELECT 0..3 (X=TONEBURST)
* Y = VOLTAGE (0=13V, 1=18V)
* Z = BAND (0=LOW, 1=HIGH(22K))
*/
if (d->msg_len >= 4 && d->msg[2] == 0x38)
state->dsec_cmd.args[CX24116_DISEQC_BURST] =
((d->msg[3] & 4) >> 2);
if (debug)
dprintk("%s burst=%d\n", __func__,
state->dsec_cmd.args[CX24116_DISEQC_BURST]);
}
/* Wait for LNB ready */
ret = cx24116_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Wait for voltage/min repeat delay */
msleep(100);
/* Command */
ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
if (ret != 0)
return ret;
/*
* Wait for send
*
* Eutelsat spec:
* >15ms delay + (XXX determine if FW does this, see set_tone)
* 13.5ms per byte +
* >15ms delay +
* 12.5ms burst +
* >15ms delay (XXX determine if FW does this, see set_tone)
*/
msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) +
((toneburst == CX24116_DISEQC_TONEOFF) ? 30 : 60));
return 0;
}
/* Send DiSEqC burst */
static int cx24116_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct cx24116_state *state = fe->demodulator_priv;
int ret;
dprintk("%s(%d) toneburst=%d\n", __func__, burst, toneburst);
/* DiSEqC burst */
if (burst == SEC_MINI_A)
state->dsec_cmd.args[CX24116_DISEQC_BURST] =
CX24116_DISEQC_MINI_A;
else if (burst == SEC_MINI_B)
state->dsec_cmd.args[CX24116_DISEQC_BURST] =
CX24116_DISEQC_MINI_B;
else
return -EINVAL;
/* DiSEqC toneburst */
if (toneburst != CX24116_DISEQC_MESGCACHE)
/* Burst is cached */
return 0;
/* Burst is to be sent with cached message */
/* Wait for LNB ready */
ret = cx24116_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Wait for voltage/min repeat delay */
msleep(100);
/* Command */
ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
if (ret != 0)
return ret;
/*
* Wait for send
*
* Eutelsat spec:
* >15ms delay + (XXX determine if FW does this, see set_tone)
* 13.5ms per byte +
* >15ms delay +
* 12.5ms burst +
* >15ms delay (XXX determine if FW does this, see set_tone)
*/
msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) + 60);
return 0;
}
static void cx24116_release(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
kfree(state);
}
static const struct dvb_frontend_ops cx24116_ops;
struct dvb_frontend *cx24116_attach(const struct cx24116_config *config,
struct i2c_adapter *i2c)
{
struct cx24116_state *state;
int ret;
dprintk("%s\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (state == NULL)
return NULL;
state->config = config;
state->i2c = i2c;
/* check if the demod is present */
ret = (cx24116_readreg(state, 0xFF) << 8) |
cx24116_readreg(state, 0xFE);
if (ret != 0x0501) {
kfree(state);
printk(KERN_INFO "Invalid probe, probably not a CX24116 device\n");
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx24116_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL_GPL(cx24116_attach);
/*
* Initialise or wake up device
*
* Power config will reset and load initial firmware if required
*/
static int cx24116_initfe(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
int ret;
dprintk("%s()\n", __func__);
/* Power on */
cx24116_writereg(state, 0xe0, 0);
cx24116_writereg(state, 0xe1, 0);
cx24116_writereg(state, 0xea, 0);
/* Firmware CMD 36: Power config */
cmd.args[0x00] = CMD_TUNERSLEEP;
cmd.args[0x01] = 0;
cmd.len = 0x02;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
ret = cx24116_diseqc_init(fe);
if (ret != 0)
return ret;
/* HVR-4000 needs this */
return cx24116_set_voltage(fe, SEC_VOLTAGE_13);
}
/*
* Put device to sleep
*/
static int cx24116_sleep(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
int ret;
dprintk("%s()\n", __func__);
/* Firmware CMD 36: Power config */
cmd.args[0x00] = CMD_TUNERSLEEP;
cmd.args[0x01] = 1;
cmd.len = 0x02;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
/* Power off (Shutdown clocks) */
cx24116_writereg(state, 0xea, 0xff);
cx24116_writereg(state, 0xe1, 1);
cx24116_writereg(state, 0xe0, 1);
return 0;
}
/* dvb-core told us to tune, the tv property cache will be complete,
* it's safe for is to pull values and use them for tuning purposes.
*/
static int cx24116_set_frontend(struct dvb_frontend *fe)
{
struct cx24116_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24116_cmd cmd;
enum fe_status tunerstat;
int i, status, ret, retune = 1;
dprintk("%s()\n", __func__);
switch (c->delivery_system) {
case SYS_DVBS:
dprintk("%s: DVB-S delivery system selected\n", __func__);
/* Only QPSK is supported for DVB-S */
if (c->modulation != QPSK) {
dprintk("%s: unsupported modulation selected (%d)\n",
__func__, c->modulation);
return -EOPNOTSUPP;
}
/* Pilot doesn't exist in DVB-S, turn bit off */
state->dnxt.pilot_val = CX24116_PILOT_OFF;
/* DVB-S only supports 0.35 */
if (c->rolloff != ROLLOFF_35) {
dprintk("%s: unsupported rolloff selected (%d)\n",
__func__, c->rolloff);
return -EOPNOTSUPP;
}
state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
break;
case SYS_DVBS2:
dprintk("%s: DVB-S2 delivery system selected\n", __func__);
/*
* NBC 8PSK/QPSK with DVB-S is supported for DVB-S2,
* but not hardware auto detection
*/
if (c->modulation != PSK_8 && c->modulation != QPSK) {
dprintk("%s: unsupported modulation selected (%d)\n",
__func__, c->modulation);
return -EOPNOTSUPP;
}
switch (c->pilot) {
case PILOT_AUTO: /* Not supported but emulated */
state->dnxt.pilot_val = (c->modulation == QPSK)
? CX24116_PILOT_OFF : CX24116_PILOT_ON;
retune++;
break;
case PILOT_OFF:
state->dnxt.pilot_val = CX24116_PILOT_OFF;
break;
case PILOT_ON:
state->dnxt.pilot_val = CX24116_PILOT_ON;
break;
default:
dprintk("%s: unsupported pilot mode selected (%d)\n",
__func__, c->pilot);
return -EOPNOTSUPP;
}
switch (c->rolloff) {
case ROLLOFF_20:
state->dnxt.rolloff_val = CX24116_ROLLOFF_020;
break;
case ROLLOFF_25:
state->dnxt.rolloff_val = CX24116_ROLLOFF_025;
break;
case ROLLOFF_35:
state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
break;
case ROLLOFF_AUTO: /* Rolloff must be explicit */
default:
dprintk("%s: unsupported rolloff selected (%d)\n",
__func__, c->rolloff);
return -EOPNOTSUPP;
}
break;
default:
dprintk("%s: unsupported delivery system selected (%d)\n",
__func__, c->delivery_system);
return -EOPNOTSUPP;
}
state->dnxt.delsys = c->delivery_system;
state->dnxt.modulation = c->modulation;
state->dnxt.frequency = c->frequency;
state->dnxt.pilot = c->pilot;
state->dnxt.rolloff = c->rolloff;
ret = cx24116_set_inversion(state, c->inversion);
if (ret != 0)
return ret;
/* FEC_NONE/AUTO for DVB-S2 is not supported and detected here */
ret = cx24116_set_fec(state, c->delivery_system, c->modulation, c->fec_inner);
if (ret != 0)
return ret;
ret = cx24116_set_symbolrate(state, c->symbol_rate);
if (ret != 0)
return ret;
/* discard the 'current' tuning parameters and prepare to tune */
cx24116_clone_params(fe);
dprintk("%s: delsys = %d\n", __func__, state->dcur.delsys);
dprintk("%s: modulation = %d\n", __func__, state->dcur.modulation);
dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
dprintk("%s: pilot = %d (val = 0x%02x)\n", __func__,
state->dcur.pilot, state->dcur.pilot_val);
dprintk("%s: retune = %d\n", __func__, retune);
dprintk("%s: rolloff = %d (val = 0x%02x)\n", __func__,
state->dcur.rolloff, state->dcur.rolloff_val);
dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
dprintk("%s: FEC = %d (mask/val = 0x%02x/0x%02x)\n", __func__,
state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
dprintk("%s: Inversion = %d (val = 0x%02x)\n", __func__,
state->dcur.inversion, state->dcur.inversion_val);
/* This is also done in advise/acquire on HVR4000 but not on LITE */
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
/* Set/Reset B/W */
cmd.args[0x00] = CMD_BANDWIDTH;
cmd.args[0x01] = 0x01;
cmd.len = 0x02;
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
/* Prepare a tune request */
cmd.args[0x00] = CMD_TUNEREQUEST;
/* Frequency */
cmd.args[0x01] = (state->dcur.frequency & 0xff0000) >> 16;
cmd.args[0x02] = (state->dcur.frequency & 0x00ff00) >> 8;
cmd.args[0x03] = (state->dcur.frequency & 0x0000ff);
/* Symbol Rate */
cmd.args[0x04] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
cmd.args[0x05] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
/* Automatic Inversion */
cmd.args[0x06] = state->dcur.inversion_val;
/* Modulation / FEC / Pilot */
cmd.args[0x07] = state->dcur.fec_val | state->dcur.pilot_val;
cmd.args[0x08] = CX24116_SEARCH_RANGE_KHZ >> 8;
cmd.args[0x09] = CX24116_SEARCH_RANGE_KHZ & 0xff;
cmd.args[0x0a] = 0x00;
cmd.args[0x0b] = 0x00;
cmd.args[0x0c] = state->dcur.rolloff_val;
cmd.args[0x0d] = state->dcur.fec_mask;
if (state->dcur.symbol_rate > 30000000) {
cmd.args[0x0e] = 0x04;
cmd.args[0x0f] = 0x00;
cmd.args[0x10] = 0x01;
cmd.args[0x11] = 0x77;
cmd.args[0x12] = 0x36;
cx24116_writereg(state, CX24116_REG_CLKDIV, 0x44);
cx24116_writereg(state, CX24116_REG_RATEDIV, 0x01);
} else {
cmd.args[0x0e] = 0x06;
cmd.args[0x0f] = 0x00;
cmd.args[0x10] = 0x00;
cmd.args[0x11] = 0xFA;
cmd.args[0x12] = 0x24;
cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
}
cmd.len = 0x13;
/* We need to support pilot and non-pilot tuning in the
* driver automatically. This is a workaround for because
* the demod does not support autodetect.
*/
do {
/* Reset status register */
status = cx24116_readreg(state, CX24116_REG_SSTATUS)
& CX24116_SIGNAL_MASK;
cx24116_writereg(state, CX24116_REG_SSTATUS, status);
/* Tune */
ret = cx24116_cmd_execute(fe, &cmd);
if (ret != 0)
break;
/*
* Wait for up to 500 ms before retrying
*
* If we are able to tune then generally it occurs within 100ms.
* If it takes longer, try a different toneburst setting.
*/
for (i = 0; i < 50 ; i++) {
cx24116_read_status(fe, &tunerstat);
status = tunerstat & (FE_HAS_SIGNAL | FE_HAS_SYNC);
if (status == (FE_HAS_SIGNAL | FE_HAS_SYNC)) {
dprintk("%s: Tuned\n", __func__);
goto tuned;
}
msleep(10);
}
dprintk("%s: Not tuned\n", __func__);
/* Toggle pilot bit when in auto-pilot */
if (state->dcur.pilot == PILOT_AUTO)
cmd.args[0x07] ^= CX24116_PILOT_ON;
} while (--retune);
tuned: /* Set/Reset B/W */
cmd.args[0x00] = CMD_BANDWIDTH;
cmd.args[0x01] = 0x00;
cmd.len = 0x02;
return cx24116_cmd_execute(fe, &cmd);
}
static int cx24116_tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
{
/*
* It is safe to discard "params" here, as the DVB core will sync
* fe->dtv_property_cache with fepriv->parameters_in, where the
* DVBv3 params are stored. The only practical usage for it indicate
* that re-tuning is needed, e. g. (fepriv->state & FESTATE_RETUNE) is
* true.
*/
*delay = HZ / 5;
if (re_tune) {
int ret = cx24116_set_frontend(fe);
if (ret)
return ret;
}
return cx24116_read_status(fe, status);
}
static enum dvbfe_algo cx24116_get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static const struct dvb_frontend_ops cx24116_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "Conexant CX24116/CX24118",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = cx24116_release,
.init = cx24116_initfe,
.sleep = cx24116_sleep,
.read_status = cx24116_read_status,
.read_ber = cx24116_read_ber,
.read_signal_strength = cx24116_read_signal_strength,
.read_snr = cx24116_read_snr,
.read_ucblocks = cx24116_read_ucblocks,
.set_tone = cx24116_set_tone,
.set_voltage = cx24116_set_voltage,
.diseqc_send_master_cmd = cx24116_send_diseqc_msg,
.diseqc_send_burst = cx24116_diseqc_send_burst,
.get_frontend_algo = cx24116_get_algo,
.tune = cx24116_tune,
.set_frontend = cx24116_set_frontend,
};
MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24116/cx24118 hardware");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cx24116.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
Copyright (C) 2003 Andreas Oberritter <[email protected]>
Copyright (C) 2008 Matthias Schwarzott <[email protected]>
References:
http://products.zarlink.com/product_profiles/MT312.htm
http://products.zarlink.com/product_profiles/SL1935.htm
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "mt312_priv.h"
#include "mt312.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
struct mt312_state {
struct i2c_adapter *i2c;
/* configuration settings */
const struct mt312_config *config;
struct dvb_frontend frontend;
u8 id;
unsigned long xtal;
u8 freq_mult;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "mt312: " args); \
} while (0)
#define MT312_PLL_CLK 10000000UL /* 10 MHz */
#define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
u8 *buf, const size_t count)
{
int ret;
struct i2c_msg msg[2];
u8 regbuf[1] = { reg };
msg[0].addr = state->config->demod_address;
msg[0].flags = 0;
msg[0].buf = regbuf;
msg[0].len = 1;
msg[1].addr = state->config->demod_address;
msg[1].flags = I2C_M_RD;
msg[1].buf = buf;
msg[1].len = count;
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
return -EREMOTEIO;
}
if (debug) {
int i;
dprintk("R(%d):", reg & 0x7f);
for (i = 0; i < count; i++)
printk(KERN_CONT " %02x", buf[i]);
printk("\n");
}
return 0;
}
static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
const u8 *src, const size_t count)
{
int ret;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg;
if (1 + count > sizeof(buf)) {
printk(KERN_WARNING
"mt312: write: len=%zu is too big!\n", count);
return -EINVAL;
}
if (debug) {
int i;
dprintk("W(%d):", reg & 0x7f);
for (i = 0; i < count; i++)
printk(KERN_CONT " %02x", src[i]);
printk("\n");
}
buf[0] = reg;
memcpy(&buf[1], src, count);
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.buf = buf;
msg.len = count + 1;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
dprintk("%s: ret == %d\n", __func__, ret);
return -EREMOTEIO;
}
return 0;
}
static inline int mt312_readreg(struct mt312_state *state,
const enum mt312_reg_addr reg, u8 *val)
{
return mt312_read(state, reg, val, 1);
}
static inline int mt312_writereg(struct mt312_state *state,
const enum mt312_reg_addr reg, const u8 val)
{
u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return mt312_write(state, reg, &tmp, 1);
}
static int mt312_reset(struct mt312_state *state, const u8 full)
{
return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
}
static int mt312_get_inversion(struct mt312_state *state,
enum fe_spectral_inversion *i)
{
int ret;
u8 vit_mode;
ret = mt312_readreg(state, VIT_MODE, &vit_mode);
if (ret < 0)
return ret;
if (vit_mode & 0x80) /* auto inversion was used */
*i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
return 0;
}
static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
{
int ret;
u8 sym_rate_h;
u8 dec_ratio;
u16 sym_rat_op;
u16 monitor;
u8 buf[2];
ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
if (ret < 0)
return ret;
if (sym_rate_h & 0x80) {
/* symbol rate search was used */
ret = mt312_writereg(state, MON_CTRL, 0x03);
if (ret < 0)
return ret;
ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
if (ret < 0)
return ret;
monitor = (buf[0] << 8) | buf[1];
dprintk("sr(auto) = %u\n",
DIV_ROUND_CLOSEST(monitor * 15625, 4));
} else {
ret = mt312_writereg(state, MON_CTRL, 0x05);
if (ret < 0)
return ret;
ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
if (ret < 0)
return ret;
dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
if (ret < 0)
return ret;
sym_rat_op = (buf[0] << 8) | buf[1];
dprintk("sym_rat_op=%d dec_ratio=%d\n",
sym_rat_op, dec_ratio);
dprintk("*sr(manual) = %lu\n",
(((state->xtal * 8192) / (sym_rat_op + 8192)) *
2) - dec_ratio);
}
return 0;
}
static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
{
const enum fe_code_rate fec_tab[8] =
{ FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
FEC_AUTO, FEC_AUTO };
int ret;
u8 fec_status;
ret = mt312_readreg(state, FEC_STATUS, &fec_status);
if (ret < 0)
return ret;
*cr = fec_tab[(fec_status >> 4) & 0x07];
return 0;
}
static int mt312_initfe(struct dvb_frontend *fe)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[2];
/* wake up */
ret = mt312_writereg(state, CONFIG,
(state->freq_mult == 6 ? 0x88 : 0x8c));
if (ret < 0)
return ret;
/* wait at least 150 usec */
udelay(150);
/* full reset */
ret = mt312_reset(state, 1);
if (ret < 0)
return ret;
/* Per datasheet, write correct values. 09/28/03 ACCJr.
* If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
{
u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
0x01, 0x00, 0x00, 0x00 };
ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
if (ret < 0)
return ret;
}
switch (state->id) {
case ID_ZL10313:
/* enable ADC */
ret = mt312_writereg(state, GPP_CTRL, 0x80);
if (ret < 0)
return ret;
/* configure ZL10313 for optimal ADC performance */
buf[0] = 0x80;
buf[1] = 0xB0;
ret = mt312_write(state, HW_CTRL, buf, 2);
if (ret < 0)
return ret;
/* enable MPEG output and ADCs */
ret = mt312_writereg(state, HW_CTRL, 0x00);
if (ret < 0)
return ret;
ret = mt312_writereg(state, MPEG_CTRL, 0x00);
if (ret < 0)
return ret;
break;
}
/* SYS_CLK */
buf[0] = DIV_ROUND_CLOSEST(state->xtal * state->freq_mult * 2, 1000000);
/* DISEQC_RATIO */
buf[1] = DIV_ROUND_CLOSEST(state->xtal, 22000 * 4);
ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
if (ret < 0)
return ret;
ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
if (ret < 0)
return ret;
/* different MOCLK polarity */
switch (state->id) {
case ID_ZL10313:
buf[0] = 0x33;
break;
default:
buf[0] = 0x53;
break;
}
ret = mt312_writereg(state, OP_CTRL, buf[0]);
if (ret < 0)
return ret;
/* TS_SW_LIM */
buf[0] = 0x8c;
buf[1] = 0x98;
ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
if (ret < 0)
return ret;
ret = mt312_writereg(state, CS_SW_LIM, 0x69);
if (ret < 0)
return ret;
return 0;
}
static int mt312_send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *c)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 diseqc_mode;
if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
return -EINVAL;
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
if (ret < 0)
return ret;
ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
if (ret < 0)
return ret;
ret = mt312_writereg(state, DISEQC_MODE,
(diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
| 0x04);
if (ret < 0)
return ret;
/* is there a better way to wait for message to be transmitted */
msleep(100);
/* set DISEQC_MODE[2:0] to zero if a return message is expected */
if (c->msg[0] & 0x02) {
ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
if (ret < 0)
return ret;
}
return 0;
}
static int mt312_send_burst(struct dvb_frontend *fe,
const enum fe_sec_mini_cmd c)
{
struct mt312_state *state = fe->demodulator_priv;
const u8 mini_tab[2] = { 0x02, 0x03 };
int ret;
u8 diseqc_mode;
if (c > SEC_MINI_B)
return -EINVAL;
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
if (ret < 0)
return ret;
ret = mt312_writereg(state, DISEQC_MODE,
(diseqc_mode & 0x40) | mini_tab[c]);
if (ret < 0)
return ret;
return 0;
}
static int mt312_set_tone(struct dvb_frontend *fe,
const enum fe_sec_tone_mode t)
{
struct mt312_state *state = fe->demodulator_priv;
const u8 tone_tab[2] = { 0x01, 0x00 };
int ret;
u8 diseqc_mode;
if (t > SEC_TONE_OFF)
return -EINVAL;
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
if (ret < 0)
return ret;
ret = mt312_writereg(state, DISEQC_MODE,
(diseqc_mode & 0x40) | tone_tab[t]);
if (ret < 0)
return ret;
return 0;
}
static int mt312_set_voltage(struct dvb_frontend *fe,
const enum fe_sec_voltage v)
{
struct mt312_state *state = fe->demodulator_priv;
const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
u8 val;
if (v > SEC_VOLTAGE_OFF)
return -EINVAL;
val = volt_tab[v];
if (state->config->voltage_inverted)
val ^= 0x40;
return mt312_writereg(state, DISEQC_MODE, val);
}
static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 status[3];
*s = 0;
ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
if (ret < 0)
return ret;
dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
status[0], status[1], status[2]);
if (status[0] & 0xc0)
*s |= FE_HAS_SIGNAL; /* signal noise ratio */
if (status[0] & 0x04)
*s |= FE_HAS_CARRIER; /* qpsk carrier lock */
if (status[2] & 0x02)
*s |= FE_HAS_VITERBI; /* viterbi lock */
if (status[2] & 0x04)
*s |= FE_HAS_SYNC; /* byte align lock */
if (status[0] & 0x01)
*s |= FE_HAS_LOCK; /* qpsk lock */
return 0;
}
static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[3];
ret = mt312_read(state, RS_BERCNT_H, buf, 3);
if (ret < 0)
return ret;
*ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
return 0;
}
static int mt312_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[3];
u16 agc;
s16 err_db;
ret = mt312_read(state, AGC_H, buf, sizeof(buf));
if (ret < 0)
return ret;
agc = (buf[0] << 6) | (buf[1] >> 2);
err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
*signal_strength = agc;
dprintk("agc=%08x err_db=%hd\n", agc, err_db);
return 0;
}
static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[2];
ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
if (ret < 0)
return ret;
*snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
return 0;
}
static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[2];
ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
if (ret < 0)
return ret;
*ubc = (buf[0] << 8) | buf[1];
return 0;
}
static int mt312_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 buf[5], config_val;
u16 sr;
const u8 fec_tab[10] =
{ 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
dprintk("%s: Freq %d\n", __func__, p->frequency);
if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
|| (p->frequency > fe->ops.info.frequency_max_hz / kHz))
return -EINVAL;
if (((int)p->inversion < INVERSION_OFF)
|| (p->inversion > INVERSION_ON))
return -EINVAL;
if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
|| (p->symbol_rate > fe->ops.info.symbol_rate_max))
return -EINVAL;
if (((int)p->fec_inner < FEC_NONE)
|| (p->fec_inner > FEC_AUTO))
return -EINVAL;
if ((p->fec_inner == FEC_4_5)
|| (p->fec_inner == FEC_8_9))
return -EINVAL;
switch (state->id) {
case ID_VP310:
/* For now we will do this only for the VP310.
* It should be better for the mt312 as well,
* but tuning will be slower. ACCJr 09/29/03
*/
ret = mt312_readreg(state, CONFIG, &config_val);
if (ret < 0)
return ret;
if (p->symbol_rate >= 30000000) {
/* Note that 30MS/s should use 90MHz */
if (state->freq_mult == 6) {
/* We are running 60MHz */
state->freq_mult = 9;
ret = mt312_initfe(fe);
if (ret < 0)
return ret;
}
} else {
if (state->freq_mult == 9) {
/* We are running 90MHz */
state->freq_mult = 6;
ret = mt312_initfe(fe);
if (ret < 0)
return ret;
}
}
break;
case ID_MT312:
case ID_ZL10313:
break;
default:
return -EINVAL;
}
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* sr = (u16)(sr * 256.0 / 1000000.0) */
sr = DIV_ROUND_CLOSEST(p->symbol_rate * 4, 15625);
/* SYM_RATE */
buf[0] = (sr >> 8) & 0x3f;
buf[1] = (sr >> 0) & 0xff;
/* VIT_MODE */
buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
/* QPSK_CTRL */
buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
if (p->symbol_rate < 10000000)
buf[3] |= 0x04; /* use afc mode */
/* GO */
buf[4] = 0x01;
ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
if (ret < 0)
return ret;
ret = mt312_reset(state, 0);
if (ret < 0)
return ret;
return 0;
}
static int mt312_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
ret = mt312_get_inversion(state, &p->inversion);
if (ret < 0)
return ret;
ret = mt312_get_symbol_rate(state, &p->symbol_rate);
if (ret < 0)
return ret;
ret = mt312_get_code_rate(state, &p->fec_inner);
if (ret < 0)
return ret;
return 0;
}
static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct mt312_state *state = fe->demodulator_priv;
u8 val = 0x00;
int ret;
switch (state->id) {
case ID_ZL10313:
ret = mt312_readreg(state, GPP_CTRL, &val);
if (ret < 0)
goto error;
/* preserve this bit to not accidentally shutdown ADC */
val &= 0x80;
break;
}
if (enable)
val |= 0x40;
else
val &= ~0x40;
ret = mt312_writereg(state, GPP_CTRL, val);
error:
return ret;
}
static int mt312_sleep(struct dvb_frontend *fe)
{
struct mt312_state *state = fe->demodulator_priv;
int ret;
u8 config;
/* reset all registers to defaults */
ret = mt312_reset(state, 1);
if (ret < 0)
return ret;
if (state->id == ID_ZL10313) {
/* reset ADC */
ret = mt312_writereg(state, GPP_CTRL, 0x00);
if (ret < 0)
return ret;
/* full shutdown of ADCs, mpeg bus tristated */
ret = mt312_writereg(state, HW_CTRL, 0x0d);
if (ret < 0)
return ret;
}
ret = mt312_readreg(state, CONFIG, &config);
if (ret < 0)
return ret;
/* enter standby */
ret = mt312_writereg(state, CONFIG, config & 0x7f);
if (ret < 0)
return ret;
return 0;
}
static int mt312_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 50;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void mt312_release(struct dvb_frontend *fe)
{
struct mt312_state *state = fe->demodulator_priv;
kfree(state);
}
#define MT312_SYS_CLK 90000000UL /* 90 MHz */
static const struct dvb_frontend_ops mt312_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Zarlink ???? DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
/* FIXME: adjust freq to real used xtal */
.frequency_stepsize_hz = MT312_PLL_CLK / 128,
.symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
.symbol_rate_max = MT312_SYS_CLK / 2,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
FE_CAN_RECOVER
},
.release = mt312_release,
.init = mt312_initfe,
.sleep = mt312_sleep,
.i2c_gate_ctrl = mt312_i2c_gate_ctrl,
.set_frontend = mt312_set_frontend,
.get_frontend = mt312_get_frontend,
.get_tune_settings = mt312_get_tune_settings,
.read_status = mt312_read_status,
.read_ber = mt312_read_ber,
.read_signal_strength = mt312_read_signal_strength,
.read_snr = mt312_read_snr,
.read_ucblocks = mt312_read_ucblocks,
.diseqc_send_master_cmd = mt312_send_master_cmd,
.diseqc_send_burst = mt312_send_burst,
.set_tone = mt312_set_tone,
.set_voltage = mt312_set_voltage,
};
struct dvb_frontend *mt312_attach(const struct mt312_config *config,
struct i2c_adapter *i2c)
{
struct mt312_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if (mt312_readreg(state, ID, &state->id) < 0)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &mt312_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
switch (state->id) {
case ID_VP310:
strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
sizeof(state->frontend.ops.info.name));
state->xtal = MT312_PLL_CLK;
state->freq_mult = 9;
break;
case ID_MT312:
strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
sizeof(state->frontend.ops.info.name));
state->xtal = MT312_PLL_CLK;
state->freq_mult = 6;
break;
case ID_ZL10313:
strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
sizeof(state->frontend.ops.info.name));
state->xtal = MT312_PLL_CLK_10_111;
state->freq_mult = 9;
break;
default:
printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
goto error;
}
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(mt312_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
MODULE_AUTHOR("Andreas Oberritter <[email protected]>");
MODULE_AUTHOR("Matthias Schwarzott <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/mt312.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Legend Silicon LGS-8GL5 DMB-TH OFDM demodulator driver
Copyright (C) 2008 Sirius International (Hong Kong) Limited
Timothy Lee <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "lgs8gl5.h"
#define REG_RESET 0x02
#define REG_RESET_OFF 0x01
#define REG_03 0x03
#define REG_04 0x04
#define REG_07 0x07
#define REG_09 0x09
#define REG_0A 0x0a
#define REG_0B 0x0b
#define REG_0C 0x0c
#define REG_37 0x37
#define REG_STRENGTH 0x4b
#define REG_STRENGTH_MASK 0x7f
#define REG_STRENGTH_CARRIER 0x80
#define REG_INVERSION 0x7c
#define REG_INVERSION_ON 0x80
#define REG_7D 0x7d
#define REG_7E 0x7e
#define REG_A2 0xa2
#define REG_STATUS 0xa4
#define REG_STATUS_SYNC 0x04
#define REG_STATUS_LOCK 0x01
struct lgs8gl5_state {
struct i2c_adapter *i2c;
const struct lgs8gl5_config *config;
struct dvb_frontend frontend;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "lgs8gl5: " args); \
} while (0)
/* Writes into demod's register */
static int
lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
{
int ret;
u8 buf[] = {reg, data};
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
/* Reads from demod's register */
static int
lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
{
int ret;
u8 b0[] = {reg};
u8 b1[] = {0};
struct i2c_msg msg[2] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
},
{
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
return -EIO;
return b1[0];
}
static int
lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
{
lgs8gl5_read_reg(state, reg);
lgs8gl5_write_reg(state, reg, data);
return 0;
}
/* Writes into alternate device's register */
/* TODO: Find out what that device is for! */
static int
lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
{
int ret;
u8 b0[] = {reg};
u8 b1[] = {0};
u8 b2[] = {reg, data};
struct i2c_msg msg[3] = {
{
.addr = state->config->demod_address + 2,
.flags = 0,
.buf = b0,
.len = 1
},
{
.addr = state->config->demod_address + 2,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
},
{
.addr = state->config->demod_address + 2,
.flags = 0,
.buf = b2,
.len = 2
},
};
ret = i2c_transfer(state->i2c, msg, 3);
return (ret != 3) ? -1 : 0;
}
static void
lgs8gl5_soft_reset(struct lgs8gl5_state *state)
{
u8 val;
dprintk("%s\n", __func__);
val = lgs8gl5_read_reg(state, REG_RESET);
lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
msleep(5);
}
/* Starts demodulation */
static void
lgs8gl5_start_demod(struct lgs8gl5_state *state)
{
u8 val;
int n;
dprintk("%s\n", __func__);
lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
lgs8gl5_soft_reset(state);
lgs8gl5_update_reg(state, REG_07, 0x10);
lgs8gl5_update_reg(state, REG_07, 0x10);
lgs8gl5_write_reg(state, REG_09, 0x0e);
lgs8gl5_write_reg(state, REG_0A, 0xe5);
lgs8gl5_write_reg(state, REG_0B, 0x35);
lgs8gl5_write_reg(state, REG_0C, 0x30);
lgs8gl5_update_reg(state, REG_03, 0x00);
lgs8gl5_update_reg(state, REG_7E, 0x01);
lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
lgs8gl5_update_reg(state, REG_04, 0x02);
lgs8gl5_update_reg(state, REG_37, 0x01);
lgs8gl5_soft_reset(state);
/* Wait for carrier */
for (n = 0; n < 10; n++) {
val = lgs8gl5_read_reg(state, REG_STRENGTH);
dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
if (val & REG_STRENGTH_CARRIER)
break;
msleep(4);
}
if (!(val & REG_STRENGTH_CARRIER))
return;
/* Wait for lock */
for (n = 0; n < 20; n++) {
val = lgs8gl5_read_reg(state, REG_STATUS);
dprintk("Wait for lock[%d] 0x%02X\n", n, val);
if (val & REG_STATUS_LOCK)
break;
msleep(12);
}
if (!(val & REG_STATUS_LOCK))
return;
lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
lgs8gl5_soft_reset(state);
}
static int
lgs8gl5_init(struct dvb_frontend *fe)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
lgs8gl5_soft_reset(state);
lgs8gl5_update_reg(state, REG_07, 0x10);
lgs8gl5_update_reg(state, REG_07, 0x10);
lgs8gl5_write_reg(state, REG_09, 0x0e);
lgs8gl5_write_reg(state, REG_0A, 0xe5);
lgs8gl5_write_reg(state, REG_0B, 0x35);
lgs8gl5_write_reg(state, REG_0C, 0x30);
return 0;
}
static int
lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
*status = 0;
if ((level & REG_STRENGTH_MASK) > 0)
*status |= FE_HAS_SIGNAL;
if (level & REG_STRENGTH_CARRIER)
*status |= FE_HAS_CARRIER;
if (flags & REG_STATUS_SYNC)
*status |= FE_HAS_SYNC;
if (flags & REG_STATUS_LOCK)
*status |= FE_HAS_LOCK;
return 0;
}
static int
lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
{
*ber = 0;
return 0;
}
static int
lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
*signal_strength = (level & REG_STRENGTH_MASK) << 8;
return 0;
}
static int
lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
*snr = (level & REG_STRENGTH_MASK) << 8;
return 0;
}
static int
lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
*ucblocks = 0;
return 0;
}
static int
lgs8gl5_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct lgs8gl5_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (p->bandwidth_hz != 8000000)
return -EINVAL;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* lgs8gl5_set_inversion(state, p->inversion); */
lgs8gl5_start_demod(state);
return 0;
}
static int
lgs8gl5_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
p->code_rate_HP = FEC_1_2;
p->code_rate_LP = FEC_7_8;
p->guard_interval = GUARD_INTERVAL_1_32;
p->transmission_mode = TRANSMISSION_MODE_2K;
p->modulation = QAM_64;
p->hierarchy = HIERARCHY_NONE;
p->bandwidth_hz = 8000000;
return 0;
}
static int
lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 240;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void
lgs8gl5_release(struct dvb_frontend *fe)
{
struct lgs8gl5_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops lgs8gl5_ops;
struct dvb_frontend*
lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
{
struct lgs8gl5_state *state = NULL;
dprintk("%s\n", __func__);
/* Allocate memory for the internal state */
state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* Setup the state */
state->config = config;
state->i2c = i2c;
/* Check if the demod is there */
if (lgs8gl5_read_reg(state, REG_RESET) < 0)
goto error;
/* Create dvb_frontend */
memcpy(&state->frontend.ops, &lgs8gl5_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL(lgs8gl5_attach);
static const struct dvb_frontend_ops lgs8gl5_ops = {
.delsys = { SYS_DTMB },
.info = {
.name = "Legend Silicon LGS-8GL5 DMB-TH",
.frequency_min_hz = 474 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 10 * kHz,
.caps = FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_BANDWIDTH_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER
},
.release = lgs8gl5_release,
.init = lgs8gl5_init,
.set_frontend = lgs8gl5_set_frontend,
.get_frontend = lgs8gl5_get_frontend,
.get_tune_settings = lgs8gl5_get_tune_settings,
.read_status = lgs8gl5_read_status,
.read_ber = lgs8gl5_read_ber,
.read_signal_strength = lgs8gl5_read_signal_strength,
.read_snr = lgs8gl5_read_snr,
.read_ucblocks = lgs8gl5_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
MODULE_AUTHOR("Timothy Lee");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/lgs8gl5.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
STB0899 Multistandard Frontend driver
Copyright (C) Manu Abraham ([email protected])
Copyright (C) ST Microelectronics
*/
#include <linux/init.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/dvb/frontend.h>
#include <media/dvb_frontend.h>
#include "stb0899_drv.h"
#include "stb0899_priv.h"
#include "stb0899_reg.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static unsigned int verbose = 0;//1;
module_param(verbose, int, 0644);
/* C/N in dB/10, NIRM/NIRL */
static const struct stb0899_tab stb0899_cn_tab[] = {
{ 200, 2600 },
{ 190, 2700 },
{ 180, 2860 },
{ 170, 3020 },
{ 160, 3210 },
{ 150, 3440 },
{ 140, 3710 },
{ 130, 4010 },
{ 120, 4360 },
{ 110, 4740 },
{ 100, 5190 },
{ 90, 5670 },
{ 80, 6200 },
{ 70, 6770 },
{ 60, 7360 },
{ 50, 7970 },
{ 40, 8250 },
{ 30, 9000 },
{ 20, 9450 },
{ 15, 9600 },
};
/* DVB-S AGCIQ_VALUE vs. signal level in dBm/10.
* As measured, connected to a modulator.
* -8.0 to -50.0 dBm directly connected,
* -52.0 to -74.8 with extra attenuation.
* Cut-off to AGCIQ_VALUE = 0x80 below -74.8dBm.
* Crude linear extrapolation below -84.8dBm and above -8.0dBm.
*/
static const struct stb0899_tab stb0899_dvbsrf_tab[] = {
{ -750, -128 },
{ -748, -94 },
{ -745, -92 },
{ -735, -90 },
{ -720, -87 },
{ -670, -77 },
{ -640, -70 },
{ -610, -62 },
{ -600, -60 },
{ -590, -56 },
{ -560, -41 },
{ -540, -25 },
{ -530, -17 },
{ -520, -11 },
{ -500, 1 },
{ -490, 6 },
{ -480, 10 },
{ -440, 22 },
{ -420, 27 },
{ -400, 31 },
{ -380, 34 },
{ -340, 40 },
{ -320, 43 },
{ -280, 48 },
{ -250, 52 },
{ -230, 55 },
{ -180, 61 },
{ -140, 66 },
{ -90, 73 },
{ -80, 74 },
{ 500, 127 }
};
/* DVB-S2 IF_AGC_GAIN vs. signal level in dBm/10.
* As measured, connected to a modulator.
* -8.0 to -50.1 dBm directly connected,
* -53.0 to -76.6 with extra attenuation.
* Cut-off to IF_AGC_GAIN = 0x3fff below -76.6dBm.
* Crude linear extrapolation below -76.6dBm and above -8.0dBm.
*/
static const struct stb0899_tab stb0899_dvbs2rf_tab[] = {
{ 700, 0 },
{ -80, 3217 },
{ -150, 3893 },
{ -190, 4217 },
{ -240, 4621 },
{ -280, 4945 },
{ -320, 5273 },
{ -350, 5545 },
{ -370, 5741 },
{ -410, 6147 },
{ -450, 6671 },
{ -490, 7413 },
{ -501, 7665 },
{ -530, 8767 },
{ -560, 10219 },
{ -580, 10939 },
{ -590, 11518 },
{ -600, 11723 },
{ -650, 12659 },
{ -690, 13219 },
{ -730, 13645 },
{ -750, 13909 },
{ -766, 14153 },
{ -950, 16383 }
};
/* DVB-S2 Es/N0 quant in dB/100 vs read value * 100*/
static struct stb0899_tab stb0899_quant_tab[] = {
{ 0, 0 },
{ 0, 100 },
{ 600, 200 },
{ 950, 299 },
{ 1200, 398 },
{ 1400, 501 },
{ 1560, 603 },
{ 1690, 700 },
{ 1810, 804 },
{ 1910, 902 },
{ 2000, 1000 },
{ 2080, 1096 },
{ 2160, 1202 },
{ 2230, 1303 },
{ 2350, 1496 },
{ 2410, 1603 },
{ 2460, 1698 },
{ 2510, 1799 },
{ 2600, 1995 },
{ 2650, 2113 },
{ 2690, 2213 },
{ 2720, 2291 },
{ 2760, 2399 },
{ 2800, 2512 },
{ 2860, 2692 },
{ 2930, 2917 },
{ 2960, 3020 },
{ 3010, 3199 },
{ 3040, 3311 },
{ 3060, 3388 },
{ 3120, 3631 },
{ 3190, 3936 },
{ 3400, 5012 },
{ 3610, 6383 },
{ 3800, 7943 },
{ 4210, 12735 },
{ 4500, 17783 },
{ 4690, 22131 },
{ 4810, 25410 }
};
/* DVB-S2 Es/N0 estimate in dB/100 vs read value */
static struct stb0899_tab stb0899_est_tab[] = {
{ 0, 0 },
{ 0, 1 },
{ 301, 2 },
{ 1204, 16 },
{ 1806, 64 },
{ 2408, 256 },
{ 2709, 512 },
{ 3010, 1023 },
{ 3311, 2046 },
{ 3612, 4093 },
{ 3823, 6653 },
{ 3913, 8185 },
{ 4010, 10233 },
{ 4107, 12794 },
{ 4214, 16368 },
{ 4266, 18450 },
{ 4311, 20464 },
{ 4353, 22542 },
{ 4391, 24604 },
{ 4425, 26607 },
{ 4457, 28642 },
{ 4487, 30690 },
{ 4515, 32734 },
{ 4612, 40926 },
{ 4692, 49204 },
{ 4816, 65464 },
{ 4913, 81846 },
{ 4993, 98401 },
{ 5060, 114815 },
{ 5118, 131220 },
{ 5200, 158489 },
{ 5300, 199526 },
{ 5400, 251189 },
{ 5500, 316228 },
{ 5600, 398107 },
{ 5720, 524807 },
{ 5721, 526017 },
};
static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
{
int ret;
u8 b0[] = { reg >> 8, reg & 0xff };
u8 buf;
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 2
},{
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = &buf,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
if (ret != -ERESTARTSYS)
dprintk(state->verbose, FE_ERROR, 1,
"Read error, Reg=[0x%02x], Status=%d",
reg, ret);
return ret < 0 ? ret : -EREMOTEIO;
}
if (unlikely(*state->verbose >= FE_DEBUGREG))
dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
reg, buf);
return (unsigned int)buf;
}
int stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
{
int result;
result = _stb0899_read_reg(state, reg);
/*
* Bug ID 9:
* access to 0xf2xx/0xf6xx
* must be followed by read from 0xf2ff/0xf6ff.
*/
if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
(((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
_stb0899_read_reg(state, (reg | 0x00ff));
return result;
}
u32 _stb0899_read_s2reg(struct stb0899_state *state,
u32 stb0899_i2cdev,
u32 stb0899_base_addr,
u16 stb0899_reg_offset)
{
int status;
u32 data;
u8 buf[7] = { 0 };
u16 tmpaddr;
u8 buf_0[] = {
GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
};
u8 buf_1[] = {
0x00, /* 0xf3 Reg Offset */
0x00, /* 0x44 Reg Offset */
};
struct i2c_msg msg_0 = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf_0,
.len = 6
};
struct i2c_msg msg_1 = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf_1,
.len = 2
};
struct i2c_msg msg_r = {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = buf,
.len = 4
};
tmpaddr = stb0899_reg_offset & 0xff00;
if (!(stb0899_reg_offset & 0x8))
tmpaddr = stb0899_reg_offset | 0x20;
buf_1[0] = GETBYTE(tmpaddr, BYTE1);
buf_1[1] = GETBYTE(tmpaddr, BYTE0);
status = i2c_transfer(state->i2c, &msg_0, 1);
if (status < 1) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s ERR(1), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
goto err;
}
/* Dummy */
status = i2c_transfer(state->i2c, &msg_1, 1);
if (status < 1)
goto err;
status = i2c_transfer(state->i2c, &msg_r, 1);
if (status < 1)
goto err;
buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
/* Actual */
status = i2c_transfer(state->i2c, &msg_1, 1);
if (status < 1) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s ERR(2), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
goto err;
}
status = i2c_transfer(state->i2c, &msg_r, 1);
if (status < 1) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s ERR(3), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
return status < 0 ? status : -EREMOTEIO;
}
data = MAKEWORD32(buf[3], buf[2], buf[1], buf[0]);
if (unlikely(*state->verbose >= FE_DEBUGREG))
printk(KERN_DEBUG "%s Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, data);
return data;
err:
return status < 0 ? status : -EREMOTEIO;
}
int stb0899_write_s2reg(struct stb0899_state *state,
u32 stb0899_i2cdev,
u32 stb0899_base_addr,
u16 stb0899_reg_offset,
u32 stb0899_data)
{
int status;
/* Base Address Setup */
u8 buf_0[] = {
GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
};
u8 buf_1[] = {
0x00, /* 0xf3 Reg Offset */
0x00, /* 0x44 Reg Offset */
0x00, /* data */
0x00, /* data */
0x00, /* data */
0x00, /* data */
};
struct i2c_msg msg_0 = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf_0,
.len = 6
};
struct i2c_msg msg_1 = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf_1,
.len = 6
};
buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
buf_1[2] = GETBYTE(stb0899_data, BYTE0);
buf_1[3] = GETBYTE(stb0899_data, BYTE1);
buf_1[4] = GETBYTE(stb0899_data, BYTE2);
buf_1[5] = GETBYTE(stb0899_data, BYTE3);
if (unlikely(*state->verbose >= FE_DEBUGREG))
printk(KERN_DEBUG "%s Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data);
status = i2c_transfer(state->i2c, &msg_0, 1);
if (unlikely(status < 1)) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s ERR (1), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
goto err;
}
status = i2c_transfer(state->i2c, &msg_1, 1);
if (unlikely(status < 1)) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s ERR (2), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
__func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
return status < 0 ? status : -EREMOTEIO;
}
return 0;
err:
return status < 0 ? status : -EREMOTEIO;
}
int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count)
{
int status;
u8 b0[] = { reg >> 8, reg & 0xff };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 2
},{
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = buf,
.len = count
}
};
status = i2c_transfer(state->i2c, msg, 2);
if (status != 2) {
if (status != -ERESTARTSYS)
printk(KERN_ERR "%s Read error, Reg=[0x%04x], Count=%u, Status=%d\n",
__func__, reg, count, status);
goto err;
}
/*
* Bug ID 9:
* access to 0xf2xx/0xf6xx
* must be followed by read from 0xf2ff/0xf6ff.
*/
if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
(((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
_stb0899_read_reg(state, (reg | 0x00ff));
dprintk(state->verbose, FE_DEBUGREG, 1,
"%s [0x%04x]: %*ph", __func__, reg, count, buf);
return 0;
err:
return status < 0 ? status : -EREMOTEIO;
}
int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count)
{
int ret;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg i2c_msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2 + count
};
if (2 + count > sizeof(buf)) {
printk(KERN_WARNING
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, count);
return -EINVAL;
}
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
memcpy(&buf[2], data, count);
dprintk(state->verbose, FE_DEBUGREG, 1,
"%s [0x%04x]: %*ph", __func__, reg, count, data);
ret = i2c_transfer(state->i2c, &i2c_msg, 1);
/*
* Bug ID 9:
* access to 0xf2xx/0xf6xx
* must be followed by read from 0xf2ff/0xf6ff.
*/
if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
stb0899_read_reg(state, (reg | 0x00ff));
if (ret != 1) {
if (ret != -ERESTARTSYS)
dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
reg, data[0], count, ret);
return ret < 0 ? ret : -EREMOTEIO;
}
return 0;
}
int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data)
{
u8 tmp = data;
return stb0899_write_regs(state, reg, &tmp, 1);
}
/*
* stb0899_get_mclk
* Get STB0899 master clock frequency
* ExtClk: external clock frequency (Hz)
*/
static u32 stb0899_get_mclk(struct stb0899_state *state)
{
u32 mclk = 0, div = 0;
div = stb0899_read_reg(state, STB0899_NCOARSE);
mclk = (div + 1) * state->config->xtal_freq / 6;
dprintk(state->verbose, FE_DEBUG, 1, "div=%d, mclk=%d", div, mclk);
return mclk;
}
/*
* stb0899_set_mclk
* Set STB0899 master Clock frequency
* Mclk: demodulator master clock
* ExtClk: external clock frequency (Hz)
*/
static void stb0899_set_mclk(struct stb0899_state *state, u32 Mclk)
{
struct stb0899_internal *internal = &state->internal;
u8 mdiv = 0;
dprintk(state->verbose, FE_DEBUG, 1, "state->config=%p", state->config);
mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1;
dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv);
stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
internal->master_clk = stb0899_get_mclk(state);
dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk);
}
static int stb0899_postproc(struct stb0899_state *state, u8 ctl, int enable)
{
struct stb0899_config *config = state->config;
const struct stb0899_postproc *postproc = config->postproc;
/* post process event */
if (postproc) {
if (enable) {
if (postproc[ctl].level == STB0899_GPIOPULLUP)
stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
else
stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
} else {
if (postproc[ctl].level == STB0899_GPIOPULLUP)
stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
else
stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
}
}
return 0;
}
static void stb0899_detach(struct dvb_frontend *fe)
{
struct stb0899_state *state = fe->demodulator_priv;
/* post process event */
stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
}
static void stb0899_release(struct dvb_frontend *fe)
{
struct stb0899_state *state = fe->demodulator_priv;
dprintk(state->verbose, FE_DEBUG, 1, "Release Frontend");
kfree(state);
}
/*
* stb0899_get_alpha
* return: rolloff
*/
static int stb0899_get_alpha(struct stb0899_state *state)
{
u8 mode_coeff;
mode_coeff = stb0899_read_reg(state, STB0899_DEMOD);
if (STB0899_GETFIELD(MODECOEFF, mode_coeff) == 1)
return 20;
else
return 35;
}
/*
* stb0899_init_calc
*/
static void stb0899_init_calc(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
int master_clk;
u8 agc[2];
u32 reg;
/* Read registers (in burst mode) */
stb0899_read_regs(state, STB0899_AGC1REF, agc, 2); /* AGC1R and AGC2O */
/* Initial calculations */
master_clk = stb0899_get_mclk(state);
internal->t_agc1 = 0;
internal->t_agc2 = 0;
internal->master_clk = master_clk;
internal->mclk = master_clk / 65536L;
internal->rolloff = stb0899_get_alpha(state);
/* DVBS2 Initial calculations */
/* Set AGC value to the middle */
internal->agc_gain = 8154;
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA);
internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg);
internal->center_freq = 0;
internal->av_frame_coarse = 10;
internal->av_frame_fine = 20;
internal->step_size = 2;
/*
if ((pParams->SpectralInv == FE_IQ_NORMAL) || (pParams->SpectralInv == FE_IQ_AUTO))
pParams->IQLocked = 0;
else
pParams->IQLocked = 1;
*/
}
static int stb0899_wait_diseqc_fifo_empty(struct stb0899_state *state, int timeout)
{
u8 reg = 0;
unsigned long start = jiffies;
while (1) {
reg = stb0899_read_reg(state, STB0899_DISSTATUS);
if (!STB0899_GETFIELD(FIFOFULL, reg))
break;
if (time_after(jiffies, start + timeout)) {
dprintk(state->verbose, FE_ERROR, 1, "timed out !!");
return -ETIMEDOUT;
}
}
return 0;
}
static int stb0899_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
{
struct stb0899_state *state = fe->demodulator_priv;
u8 reg, i;
if (cmd->msg_len > sizeof(cmd->msg))
return -EINVAL;
/* enable FIFO precharge */
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
for (i = 0; i < cmd->msg_len; i++) {
/* wait for FIFO empty */
if (stb0899_wait_diseqc_fifo_empty(state, 100) < 0)
return -ETIMEDOUT;
stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
}
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
msleep(100);
return 0;
}
static int stb0899_wait_diseqc_rxidle(struct stb0899_state *state, int timeout)
{
u8 reg = 0;
unsigned long start = jiffies;
while (!STB0899_GETFIELD(RXEND, reg)) {
reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
if (time_after(jiffies, start + timeout)) {
dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
return -ETIMEDOUT;
}
msleep(10);
}
return 0;
}
static int stb0899_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
{
struct stb0899_state *state = fe->demodulator_priv;
u8 reg, length = 0, i;
int result;
if (stb0899_wait_diseqc_rxidle(state, 100) < 0)
return -ETIMEDOUT;
reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
if (STB0899_GETFIELD(RXEND, reg)) {
reg = stb0899_read_reg(state, STB0899_DISRX_ST1);
length = STB0899_GETFIELD(FIFOBYTENBR, reg);
if (length > sizeof (reply->msg)) {
result = -EOVERFLOW;
goto exit;
}
reply->msg_len = length;
/* extract data */
for (i = 0; i < length; i++)
reply->msg[i] = stb0899_read_reg(state, STB0899_DISFIFO);
}
return 0;
exit:
return result;
}
static int stb0899_wait_diseqc_txidle(struct stb0899_state *state, int timeout)
{
u8 reg = 0;
unsigned long start = jiffies;
while (!STB0899_GETFIELD(TXIDLE, reg)) {
reg = stb0899_read_reg(state, STB0899_DISSTATUS);
if (time_after(jiffies, start + timeout)) {
dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
return -ETIMEDOUT;
}
msleep(10);
}
return 0;
}
static int stb0899_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct stb0899_state *state = fe->demodulator_priv;
u8 reg, old_state;
/* wait for diseqc idle */
if (stb0899_wait_diseqc_txidle(state, 100) < 0)
return -ETIMEDOUT;
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
old_state = reg;
/* set to burst mode */
STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03);
STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
switch (burst) {
case SEC_MINI_A:
/* unmodulated */
stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
break;
case SEC_MINI_B:
/* modulated */
stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
break;
}
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
/* wait for diseqc idle */
if (stb0899_wait_diseqc_txidle(state, 100) < 0)
return -ETIMEDOUT;
/* restore state */
stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
return 0;
}
static int stb0899_diseqc_init(struct stb0899_state *state)
{
/*
struct dvb_diseqc_slave_reply rx_data;
*/
u8 f22_tx, reg;
u32 mclk, tx_freq = 22000;/* count = 0, i; */
reg = stb0899_read_reg(state, STB0899_DISCNTRL2);
STB0899_SETFIELD_VAL(ONECHIP_TRX, reg, 0);
stb0899_write_reg(state, STB0899_DISCNTRL2, reg);
/* disable Tx spy */
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
STB0899_SETFIELD_VAL(DISEQCRESET, reg, 1);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
STB0899_SETFIELD_VAL(DISEQCRESET, reg, 0);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
mclk = stb0899_get_mclk(state);
f22_tx = mclk / (tx_freq * 32);
stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */
state->rx_freq = 20000;
return 0;
}
static int stb0899_sleep(struct dvb_frontend *fe)
{
struct stb0899_state *state = fe->demodulator_priv;
/*
u8 reg;
*/
dprintk(state->verbose, FE_DEBUG, 1, "Going to Sleep .. (Really tired .. :-))");
/* post process event */
stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
return 0;
}
static int stb0899_wakeup(struct dvb_frontend *fe)
{
int rc;
struct stb0899_state *state = fe->demodulator_priv;
if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
return rc;
/* Activate all clocks; DVB-S2 registers are inaccessible otherwise. */
if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
return rc;
if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
return rc;
/* post process event */
stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 1);
return 0;
}
static int stb0899_init(struct dvb_frontend *fe)
{
int i;
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_config *config = state->config;
dprintk(state->verbose, FE_DEBUG, 1, "Initializing STB0899 ... ");
/* init device */
dprintk(state->verbose, FE_DEBUG, 1, "init device");
for (i = 0; config->init_dev[i].address != 0xffff; i++)
stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
dprintk(state->verbose, FE_DEBUG, 1, "init S2 demod");
/* init S2 demod */
for (i = 0; config->init_s2_demod[i].offset != 0xffff; i++)
stb0899_write_s2reg(state, STB0899_S2DEMOD,
config->init_s2_demod[i].base_address,
config->init_s2_demod[i].offset,
config->init_s2_demod[i].data);
dprintk(state->verbose, FE_DEBUG, 1, "init S1 demod");
/* init S1 demod */
for (i = 0; config->init_s1_demod[i].address != 0xffff; i++)
stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
dprintk(state->verbose, FE_DEBUG, 1, "init S2 FEC");
/* init S2 fec */
for (i = 0; config->init_s2_fec[i].offset != 0xffff; i++)
stb0899_write_s2reg(state, STB0899_S2FEC,
config->init_s2_fec[i].base_address,
config->init_s2_fec[i].offset,
config->init_s2_fec[i].data);
dprintk(state->verbose, FE_DEBUG, 1, "init TST");
/* init test */
for (i = 0; config->init_tst[i].address != 0xffff; i++)
stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
stb0899_init_calc(state);
stb0899_diseqc_init(state);
return 0;
}
static int stb0899_table_lookup(const struct stb0899_tab *tab, int max, int val)
{
int res = 0;
int min = 0, med;
if (val < tab[min].read)
res = tab[min].real;
else if (val >= tab[max].read)
res = tab[max].real;
else {
while ((max - min) > 1) {
med = (max + min) / 2;
if (val >= tab[min].read && val < tab[med].read)
max = med;
else
min = med;
}
res = ((val - tab[min].read) *
(tab[max].real - tab[min].real) /
(tab[max].read - tab[min].read)) +
tab[min].real;
}
return res;
}
static int stb0899_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
int val;
u32 reg;
*strength = 0;
switch (state->delsys) {
case SYS_DVBS:
case SYS_DSS:
if (internal->lock) {
reg = stb0899_read_reg(state, STB0899_VSTATUS);
if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
reg = stb0899_read_reg(state, STB0899_AGCIQIN);
val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg);
*strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val);
*strength += 750;
dprintk(state->verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm",
val & 0xff, *strength);
}
}
break;
case SYS_DVBS2:
if (internal->lock) {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_GAIN);
val = STB0899_GETFIELD(IF_AGC_GAIN, reg);
*strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val);
*strength += 950;
dprintk(state->verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm",
val & 0x3fff, *strength);
}
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
return -EINVAL;
}
return 0;
}
static int stb0899_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
unsigned int val, quant, quantn = -1, est, estn = -1;
u8 buf[2];
u32 reg;
*snr = 0;
reg = stb0899_read_reg(state, STB0899_VSTATUS);
switch (state->delsys) {
case SYS_DVBS:
case SYS_DSS:
if (internal->lock) {
if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
stb0899_read_regs(state, STB0899_NIRM, buf, 2);
val = MAKEWORD16(buf[0], buf[1]);
*snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val);
dprintk(state->verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n",
buf[0], buf[1], val, *snr);
}
}
break;
case SYS_DVBS2:
if (internal->lock) {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
est = STB0899_GETFIELD(ESN0_EST, reg);
if (est == 1)
val = 301; /* C/N = 30.1 dB */
else if (est == 2)
val = 270; /* C/N = 27.0 dB */
else {
/* quantn = 100 * log(quant^2) */
quantn = stb0899_table_lookup(stb0899_quant_tab, ARRAY_SIZE(stb0899_quant_tab) - 1, quant * 100);
/* estn = 100 * log(est) */
estn = stb0899_table_lookup(stb0899_est_tab, ARRAY_SIZE(stb0899_est_tab) - 1, est);
/* snr(dBm/10) = -10*(log(est)-log(quant^2)) => snr(dBm/10) = (100*log(quant^2)-100*log(est))/10 */
val = (quantn - estn) / 10;
}
*snr = val;
dprintk(state->verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm",
quant, quantn, est, estn, val);
}
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
return -EINVAL;
}
return 0;
}
static int stb0899_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
u8 reg;
*status = 0;
switch (state->delsys) {
case SYS_DVBS:
case SYS_DSS:
dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S/DSS");
if (internal->lock) {
reg = stb0899_read_reg(state, STB0899_VSTATUS);
if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_CARRIER | FE_HAS_LOCK");
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK;
reg = stb0899_read_reg(state, STB0899_PLPARM);
if (STB0899_GETFIELD(VITCURPUN, reg)) {
dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_VITERBI | FE_HAS_SYNC");
*status |= FE_HAS_VITERBI | FE_HAS_SYNC;
/* post process event */
stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
}
}
}
break;
case SYS_DVBS2:
dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S2");
if (internal->lock) {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) {
*status |= FE_HAS_CARRIER;
dprintk(state->verbose, FE_DEBUG, 1,
"UWP & CSM Lock ! ---> DVB-S2 FE_HAS_CARRIER");
reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) {
*status |= FE_HAS_LOCK;
dprintk(state->verbose, FE_DEBUG, 1,
"Packet Delineator Locked ! -----> DVB-S2 FE_HAS_LOCK");
}
if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) {
*status |= FE_HAS_VITERBI;
dprintk(state->verbose, FE_DEBUG, 1,
"Packet Delineator found VITERBI ! -----> DVB-S2 FE_HAS_VITERBI");
}
if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) {
*status |= FE_HAS_SYNC;
dprintk(state->verbose, FE_DEBUG, 1,
"Packet Delineator found SYNC ! -----> DVB-S2 FE_HAS_SYNC");
/* post process event */
stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
}
}
}
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
return -EINVAL;
}
return 0;
}
/*
* stb0899_get_error
* viterbi error for DVB-S/DSS
* packet error for DVB-S2
* Bit Error Rate or Packet Error Rate * 10 ^ 7
*/
static int stb0899_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
u8 lsb, msb;
*ber = 0;
switch (state->delsys) {
case SYS_DVBS:
case SYS_DSS:
if (internal->lock) {
lsb = stb0899_read_reg(state, STB0899_ECNT1L);
msb = stb0899_read_reg(state, STB0899_ECNT1M);
*ber = MAKEWORD16(msb, lsb);
/* Viterbi Check */
if (STB0899_GETFIELD(VSTATUS_PRFVIT, internal->v_status)) {
/* Error Rate */
*ber *= 9766;
/* ber = ber * 10 ^ 7 */
*ber /= (-1 + (1 << (2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
*ber /= 8;
}
}
break;
case SYS_DVBS2:
if (internal->lock) {
lsb = stb0899_read_reg(state, STB0899_ECNT1L);
msb = stb0899_read_reg(state, STB0899_ECNT1M);
*ber = MAKEWORD16(msb, lsb);
/* ber = ber * 10 ^ 7 */
*ber *= 10000000;
*ber /= (-1 + (1 << (4 + 2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
}
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
return -EINVAL;
}
return 0;
}
static int stb0899_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct stb0899_state *state = fe->demodulator_priv;
switch (voltage) {
case SEC_VOLTAGE_13:
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
break;
case SEC_VOLTAGE_18:
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
break;
case SEC_VOLTAGE_OFF:
stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
break;
default:
return -EINVAL;
}
return 0;
}
static int stb0899_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
u8 div, reg;
/* wait for diseqc idle */
if (stb0899_wait_diseqc_txidle(state, 100) < 0)
return -ETIMEDOUT;
switch (tone) {
case SEC_TONE_ON:
div = (internal->master_clk / 100) / 5632;
div = (div + 5) / 10;
stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
reg = stb0899_read_reg(state, STB0899_ACRPRESC);
STB0899_SETFIELD_VAL(ACRPRESC, reg, 0x03);
stb0899_write_reg(state, STB0899_ACRPRESC, reg);
stb0899_write_reg(state, STB0899_ACRDIV1, div);
break;
case SEC_TONE_OFF:
stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
break;
default:
return -EINVAL;
}
return 0;
}
int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
int i2c_stat;
struct stb0899_state *state = fe->demodulator_priv;
i2c_stat = stb0899_read_reg(state, STB0899_I2CRPT);
if (i2c_stat < 0)
goto err;
if (enable) {
dprintk(state->verbose, FE_DEBUG, 1, "Enabling I2C Repeater ...");
i2c_stat |= STB0899_I2CTON;
if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
goto err;
} else {
dprintk(state->verbose, FE_DEBUG, 1, "Disabling I2C Repeater ...");
i2c_stat &= ~STB0899_I2CTON;
if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
goto err;
}
return 0;
err:
dprintk(state->verbose, FE_ERROR, 1, "I2C Repeater control failed");
return -EREMOTEIO;
}
static inline void CONVERT32(u32 x, char *str)
{
*str++ = (x >> 24) & 0xff;
*str++ = (x >> 16) & 0xff;
*str++ = (x >> 8) & 0xff;
*str++ = (x >> 0) & 0xff;
*str = '\0';
}
static int stb0899_get_dev_id(struct stb0899_state *state)
{
u8 chip_id, release;
u16 id;
u32 demod_ver = 0, fec_ver = 0;
char demod_str[5] = { 0 };
char fec_str[5] = { 0 };
id = stb0899_read_reg(state, STB0899_DEV_ID);
dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id);
chip_id = STB0899_GETFIELD(CHIP_ID, id);
release = STB0899_GETFIELD(CHIP_REL, id);
dprintk(state->verbose, FE_ERROR, 1, "Device ID=[%d], Release=[%d]",
chip_id, release);
CONVERT32(STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CORE_ID), (char *)&demod_str);
demod_ver = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_VERSION_ID);
dprintk(state->verbose, FE_ERROR, 1, "Demodulator Core ID=[%s], Version=[%d]", (char *) &demod_str, demod_ver);
CONVERT32(STB0899_READ_S2REG(STB0899_S2FEC, FEC_CORE_ID_REG), (char *)&fec_str);
fec_ver = STB0899_READ_S2REG(STB0899_S2FEC, FEC_VER_ID_REG);
if (! (chip_id > 0)) {
dprintk(state->verbose, FE_ERROR, 1, "couldn't find a STB 0899");
return -ENODEV;
}
dprintk(state->verbose, FE_ERROR, 1, "FEC Core ID=[%s], Version=[%d]", (char*) &fec_str, fec_ver);
return 0;
}
static void stb0899_set_delivery(struct stb0899_state *state)
{
u8 reg;
u8 stop_clk[2];
stop_clk[0] = stb0899_read_reg(state, STB0899_STOPCLK1);
stop_clk[1] = stb0899_read_reg(state, STB0899_STOPCLK2);
switch (state->delsys) {
case SYS_DVBS:
dprintk(state->verbose, FE_DEBUG, 1, "Delivery System -- DVB-S");
/* FECM/Viterbi ON */
reg = stb0899_read_reg(state, STB0899_FECM);
STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xb1);
stb0899_write_reg(state, STB0899_TSULC, 0x40);
stb0899_write_reg(state, STB0899_RSLLC, 0x42);
stb0899_write_reg(state, STB0899_TSLPL, 0x12);
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
break;
case SYS_DVBS2:
/* FECM/Viterbi OFF */
reg = stb0899_read_reg(state, STB0899_FECM);
STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0);
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xb1);
stb0899_write_reg(state, STB0899_TSULC, 0x42);
stb0899_write_reg(state, STB0899_RSLLC, 0x40);
stb0899_write_reg(state, STB0899_TSLPL, 0x02);
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESLDPC, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 0);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 0);
STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 0);
break;
case SYS_DSS:
/* FECM/Viterbi ON */
reg = stb0899_read_reg(state, STB0899_FECM);
STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1);
STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
stb0899_write_reg(state, STB0899_FECM, reg);
stb0899_write_reg(state, STB0899_RSULC, 0xa1);
stb0899_write_reg(state, STB0899_TSULC, 0x61);
stb0899_write_reg(state, STB0899_RSLLC, 0x42);
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
break;
default:
dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
break;
}
STB0899_SETFIELD_VAL(STOP_CKADCI108, stop_clk[0], 0);
stb0899_write_regs(state, STB0899_STOPCLK1, stop_clk, 2);
}
/*
* stb0899_set_iterations
* set the LDPC iteration scale function
*/
static void stb0899_set_iterations(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
s32 iter_scale;
u32 reg;
iter_scale = 17 * (internal->master_clk / 1000);
iter_scale += 410000;
iter_scale /= (internal->srate / 1000000);
iter_scale /= 1000;
if (iter_scale > config->ldpc_max_iter)
iter_scale = config->ldpc_max_iter;
reg = STB0899_READ_S2REG(STB0899_S2FEC, MAX_ITER);
STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale);
stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg);
}
static enum dvbfe_search stb0899_search(struct dvb_frontend *fe)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_params *i_params = &state->params;
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
struct dtv_frontend_properties *props = &fe->dtv_property_cache;
u32 SearchRange, gain;
i_params->freq = props->frequency;
i_params->srate = props->symbol_rate;
state->delsys = props->delivery_system;
dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
SearchRange = 10000000;
dprintk(state->verbose, FE_DEBUG, 1, "Frequency=%d, Srate=%d", i_params->freq, i_params->srate);
/* checking Search Range is meaningless for a fixed 3 Mhz */
if (INRANGE(i_params->srate, 1000000, 45000000)) {
dprintk(state->verbose, FE_DEBUG, 1, "Parameters IN RANGE");
stb0899_set_delivery(state);
if (state->config->tuner_set_rfsiggain) {
if (internal->srate > 15000000)
gain = 8; /* 15Mb < srate < 45Mb, gain = 8dB */
else if (internal->srate > 5000000)
gain = 12; /* 5Mb < srate < 15Mb, gain = 12dB */
else
gain = 14; /* 1Mb < srate < 5Mb, gain = 14db */
state->config->tuner_set_rfsiggain(fe, gain);
}
if (i_params->srate <= 5000000)
stb0899_set_mclk(state, config->lo_clk);
else
stb0899_set_mclk(state, config->hi_clk);
switch (state->delsys) {
case SYS_DVBS:
case SYS_DSS:
dprintk(state->verbose, FE_DEBUG, 1, "DVB-S delivery system");
internal->freq = i_params->freq;
internal->srate = i_params->srate;
/*
* search = user search range +
* 500Khz +
* 2 * Tuner_step_size +
* 10% of the symbol rate
*/
internal->srch_range = SearchRange + 1500000 + (i_params->srate / 5);
internal->derot_percent = 30;
/* What to do for tuners having no bandwidth setup ? */
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
if (state->config->tuner_set_bandwidth)
state->config->tuner_set_bandwidth(fe, (13 * (stb0899_carr_width(state) + SearchRange)) / 10);
if (state->config->tuner_get_bandwidth)
state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
/* Set DVB-S1 AGC */
stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
/* Run the search algorithm */
dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S search algo ..");
if (stb0899_dvbs_algo(state) == RANGEOK) {
internal->lock = 1;
dprintk(state->verbose, FE_DEBUG, 1,
"-------------------------------------> DVB-S LOCK !");
// stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */
// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
// dprintk(state->verbose, FE_DEBUG, 1, "VSTATUS=0x%02x", internal->v_status);
// dprintk(state->verbose, FE_DEBUG, 1, "ERR_CTRL=0x%02x", internal->err_ctrl);
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
internal->lock = 0;
return DVBFE_ALGO_SEARCH_FAILED;
}
break;
case SYS_DVBS2:
internal->freq = i_params->freq;
internal->srate = i_params->srate;
internal->srch_range = SearchRange;
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
if (state->config->tuner_set_bandwidth)
state->config->tuner_set_bandwidth(fe, (stb0899_carr_width(state) + SearchRange));
if (state->config->tuner_get_bandwidth)
state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
// pParams->SpectralInv = pSearch->IQ_Inversion;
/* Set DVB-S2 AGC */
stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
/* Set IterScale =f(MCLK,SYMB) */
stb0899_set_iterations(state);
/* Run the search algorithm */
dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S2 search algo ..");
if (stb0899_dvbs2_algo(state) == DVBS2_FEC_LOCK) {
internal->lock = 1;
dprintk(state->verbose, FE_DEBUG, 1,
"-------------------------------------> DVB-S2 LOCK !");
// stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */
// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
internal->lock = 0;
return DVBFE_ALGO_SEARCH_FAILED;
}
break;
default:
dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
return DVBFE_ALGO_SEARCH_INVALID;
}
}
return DVBFE_ALGO_SEARCH_ERROR;
}
static int stb0899_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stb0899_state *state = fe->demodulator_priv;
struct stb0899_internal *internal = &state->internal;
dprintk(state->verbose, FE_DEBUG, 1, "Get params");
p->symbol_rate = internal->srate;
p->frequency = internal->freq;
return 0;
}
static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static const struct dvb_frontend_ops stb0899_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
.info = {
.name = "STB0899 Multistandard",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.symbol_rate_min = 5000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_QPSK
},
.detach = stb0899_detach,
.release = stb0899_release,
.init = stb0899_init,
.sleep = stb0899_sleep,
// .wakeup = stb0899_wakeup,
.i2c_gate_ctrl = stb0899_i2c_gate_ctrl,
.get_frontend_algo = stb0899_frontend_algo,
.search = stb0899_search,
.get_frontend = stb0899_get_frontend,
.read_status = stb0899_read_status,
.read_snr = stb0899_read_snr,
.read_signal_strength = stb0899_read_signal_strength,
.read_ber = stb0899_read_ber,
.set_voltage = stb0899_set_voltage,
.set_tone = stb0899_set_tone,
.diseqc_send_master_cmd = stb0899_send_diseqc_msg,
.diseqc_recv_slave_reply = stb0899_recv_slave_reply,
.diseqc_send_burst = stb0899_send_diseqc_burst,
};
struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_adapter *i2c)
{
struct stb0899_state *state = NULL;
state = kzalloc(sizeof (struct stb0899_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->verbose = &verbose;
state->config = config;
state->i2c = i2c;
state->frontend.ops = stb0899_ops;
state->frontend.demodulator_priv = state;
/* use configured inversion as default -- we'll later autodetect inversion */
state->internal.inversion = config->inversion;
stb0899_wakeup(&state->frontend);
if (stb0899_get_dev_id(state) == -ENODEV) {
printk("%s: Exiting .. !\n", __func__);
goto error;
}
printk("%s: Attaching STB0899 \n", __func__);
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stb0899_attach);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("STB0899 Multi-Std frontend");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stb0899_drv.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ZyDAS ZD1301 driver (demodulator)
*
* Copyright (C) 2015 Antti Palosaari <[email protected]>
*/
#include "zd1301_demod.h"
static u8 zd1301_demod_gain = 0x38;
module_param_named(gain, zd1301_demod_gain, byte, 0644);
MODULE_PARM_DESC(gain, "gain (value: 0x00 - 0x70, default: 0x38)");
struct zd1301_demod_dev {
struct platform_device *pdev;
struct dvb_frontend frontend;
struct i2c_adapter adapter;
u8 gain;
};
static int zd1301_demod_wreg(struct zd1301_demod_dev *dev, u16 reg, u8 val)
{
struct platform_device *pdev = dev->pdev;
struct zd1301_demod_platform_data *pdata = pdev->dev.platform_data;
return pdata->reg_write(pdata->reg_priv, reg, val);
}
static int zd1301_demod_rreg(struct zd1301_demod_dev *dev, u16 reg, u8 *val)
{
struct platform_device *pdev = dev->pdev;
struct zd1301_demod_platform_data *pdata = pdev->dev.platform_data;
return pdata->reg_read(pdata->reg_priv, reg, val);
}
static int zd1301_demod_set_frontend(struct dvb_frontend *fe)
{
struct zd1301_demod_dev *dev = fe->demodulator_priv;
struct platform_device *pdev = dev->pdev;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
u32 if_frequency;
u8 r6a50_val;
dev_dbg(&pdev->dev, "frequency=%u bandwidth_hz=%u\n",
c->frequency, c->bandwidth_hz);
/* Program tuner */
if (fe->ops.tuner_ops.set_params &&
fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto err;
} else {
ret = -EINVAL;
goto err;
}
dev_dbg(&pdev->dev, "if_frequency=%u\n", if_frequency);
if (if_frequency != 36150000) {
ret = -EINVAL;
goto err;
}
switch (c->bandwidth_hz) {
case 6000000:
r6a50_val = 0x78;
break;
case 7000000:
r6a50_val = 0x68;
break;
case 8000000:
r6a50_val = 0x58;
break;
default:
ret = -EINVAL;
goto err;
}
ret = zd1301_demod_wreg(dev, 0x6a60, 0x11);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a47, 0x46);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a48, 0x46);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a4a, 0x15);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a4b, 0x63);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a5b, 0x99);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a3b, 0x10);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6806, 0x01);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a41, 0x08);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a42, 0x46);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a44, 0x14);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a45, 0x67);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a38, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a4c, 0x52);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a49, 0x2a);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6840, 0x2e);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a50, r6a50_val);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a38, 0x07);
if (ret)
goto err;
return 0;
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static int zd1301_demod_sleep(struct dvb_frontend *fe)
{
struct zd1301_demod_dev *dev = fe->demodulator_priv;
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "\n");
ret = zd1301_demod_wreg(dev, 0x6a43, 0x70);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x684e, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6849, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x68e2, 0xd7);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x68e0, 0x39);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6840, 0x21);
if (ret)
goto err;
return 0;
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static int zd1301_demod_init(struct dvb_frontend *fe)
{
struct zd1301_demod_dev *dev = fe->demodulator_priv;
struct platform_device *pdev = dev->pdev;
int ret;
dev_dbg(&pdev->dev, "\n");
ret = zd1301_demod_wreg(dev, 0x6840, 0x26);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x68e0, 0xff);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x68e2, 0xd8);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6849, 0x4e);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x684e, 0x01);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6a43, zd1301_demod_gain);
if (ret)
goto err;
return 0;
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static int zd1301_demod_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *settings)
{
struct zd1301_demod_dev *dev = fe->demodulator_priv;
struct platform_device *pdev = dev->pdev;
dev_dbg(&pdev->dev, "\n");
/* ~180ms seems to be enough */
settings->min_delay_ms = 400;
return 0;
}
static int zd1301_demod_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct zd1301_demod_dev *dev = fe->demodulator_priv;
struct platform_device *pdev = dev->pdev;
int ret;
u8 u8tmp;
ret = zd1301_demod_rreg(dev, 0x6a24, &u8tmp);
if (ret)
goto err;
if (u8tmp > 0x00 && u8tmp < 0x20)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
FE_HAS_SYNC | FE_HAS_LOCK;
else
*status = 0;
dev_dbg(&pdev->dev, "lock byte=%02x\n", u8tmp);
/*
* Interesting registers here are:
* 0x6a05: get some gain value
* 0x6a06: get about same gain value than set to 0x6a43
* 0x6a07: get some gain value
* 0x6a43: set gain value by driver
* 0x6a24: get demod lock bits (FSM stage?)
*
* Driver should implement some kind of algorithm to calculate suitable
* value for register 0x6a43, based likely values from register 0x6a05
* and 0x6a07. Looks like gain register 0x6a43 value could be from
* range 0x00 - 0x70.
*/
if (dev->gain != zd1301_demod_gain) {
dev->gain = zd1301_demod_gain;
ret = zd1301_demod_wreg(dev, 0x6a43, dev->gain);
if (ret)
goto err;
}
return 0;
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_frontend_ops zd1301_demod_ops = {
.delsys = {SYS_DVBT},
.info = {
.name = "ZyDAS ZD1301",
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS
},
.sleep = zd1301_demod_sleep,
.init = zd1301_demod_init,
.set_frontend = zd1301_demod_set_frontend,
.get_tune_settings = zd1301_demod_get_tune_settings,
.read_status = zd1301_demod_read_status,
};
struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *pdev)
{
struct zd1301_demod_dev *dev = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "\n");
return &dev->frontend;
}
EXPORT_SYMBOL(zd1301_demod_get_dvb_frontend);
static int zd1301_demod_i2c_master_xfer(struct i2c_adapter *adapter,
struct i2c_msg msg[], int num)
{
struct zd1301_demod_dev *dev = i2c_get_adapdata(adapter);
struct platform_device *pdev = dev->pdev;
int ret, i;
unsigned long timeout;
u8 u8tmp;
#define I2C_XFER_TIMEOUT 5
#define ZD1301_IS_I2C_XFER_WRITE_READ(_msg, _num) \
(_num == 2 && !(_msg[0].flags & I2C_M_RD) && (_msg[1].flags & I2C_M_RD))
#define ZD1301_IS_I2C_XFER_WRITE(_msg, _num) \
(_num == 1 && !(_msg[0].flags & I2C_M_RD))
#define ZD1301_IS_I2C_XFER_READ(_msg, _num) \
(_num == 1 && (_msg[0].flags & I2C_M_RD))
if (ZD1301_IS_I2C_XFER_WRITE_READ(msg, num)) {
dev_dbg(&pdev->dev, "write&read msg[0].len=%u msg[1].len=%u\n",
msg[0].len, msg[1].len);
if (msg[0].len > 1 || msg[1].len > 8) {
ret = -EOPNOTSUPP;
goto err;
}
ret = zd1301_demod_wreg(dev, 0x6811, 0x80);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6812, 0x05);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6813, msg[1].addr << 1);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6801, msg[0].buf[0]);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6802, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6803, 0x06);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6805, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6804, msg[1].len);
if (ret)
goto err;
/* Poll xfer ready */
timeout = jiffies + msecs_to_jiffies(I2C_XFER_TIMEOUT);
for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
usleep_range(500, 800);
ret = zd1301_demod_rreg(dev, 0x6804, &u8tmp);
if (ret)
goto err;
}
for (i = 0; i < msg[1].len; i++) {
ret = zd1301_demod_rreg(dev, 0x0600 + i, &msg[1].buf[i]);
if (ret)
goto err;
}
} else if (ZD1301_IS_I2C_XFER_WRITE(msg, num)) {
dev_dbg(&pdev->dev, "write msg[0].len=%u\n", msg[0].len);
if (msg[0].len > 1 + 8) {
ret = -EOPNOTSUPP;
goto err;
}
ret = zd1301_demod_wreg(dev, 0x6811, 0x80);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6812, 0x01);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6813, msg[0].addr << 1);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6800, msg[0].buf[0]);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6802, 0x00);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6803, 0x06);
if (ret)
goto err;
for (i = 0; i < msg[0].len - 1; i++) {
ret = zd1301_demod_wreg(dev, 0x0600 + i, msg[0].buf[1 + i]);
if (ret)
goto err;
}
ret = zd1301_demod_wreg(dev, 0x6805, 0x80);
if (ret)
goto err;
ret = zd1301_demod_wreg(dev, 0x6804, msg[0].len - 1);
if (ret)
goto err;
/* Poll xfer ready */
timeout = jiffies + msecs_to_jiffies(I2C_XFER_TIMEOUT);
for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
usleep_range(500, 800);
ret = zd1301_demod_rreg(dev, 0x6804, &u8tmp);
if (ret)
goto err;
}
} else {
dev_dbg(&pdev->dev, "unknown msg[0].len=%u\n", msg[0].len);
ret = -EOPNOTSUPP;
goto err;
}
return num;
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static u32 zd1301_demod_i2c_functionality(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm zd1301_demod_i2c_algorithm = {
.master_xfer = zd1301_demod_i2c_master_xfer,
.functionality = zd1301_demod_i2c_functionality,
};
struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *pdev)
{
struct zd1301_demod_dev *dev = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "\n");
return &dev->adapter;
}
EXPORT_SYMBOL(zd1301_demod_get_i2c_adapter);
/* Platform driver interface */
static int zd1301_demod_probe(struct platform_device *pdev)
{
struct zd1301_demod_dev *dev;
struct zd1301_demod_platform_data *pdata = pdev->dev.platform_data;
int ret;
dev_dbg(&pdev->dev, "\n");
if (!pdata) {
ret = -EINVAL;
dev_err(&pdev->dev, "cannot proceed without platform data\n");
goto err;
}
if (!pdev->dev.parent->driver) {
ret = -EINVAL;
dev_dbg(&pdev->dev, "no parent device\n");
goto err;
}
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
/* Setup the state */
dev->pdev = pdev;
dev->gain = zd1301_demod_gain;
/* Sleep */
ret = zd1301_demod_wreg(dev, 0x6840, 0x21);
if (ret)
goto err_kfree;
ret = zd1301_demod_wreg(dev, 0x6a38, 0x07);
if (ret)
goto err_kfree;
/* Create I2C adapter */
strscpy(dev->adapter.name, "ZyDAS ZD1301 demod",
sizeof(dev->adapter.name));
dev->adapter.algo = &zd1301_demod_i2c_algorithm;
dev->adapter.algo_data = NULL;
dev->adapter.dev.parent = pdev->dev.parent;
i2c_set_adapdata(&dev->adapter, dev);
ret = i2c_add_adapter(&dev->adapter);
if (ret) {
dev_err(&pdev->dev, "I2C adapter add failed %d\n", ret);
goto err_kfree;
}
/* Create dvb frontend */
memcpy(&dev->frontend.ops, &zd1301_demod_ops, sizeof(dev->frontend.ops));
dev->frontend.demodulator_priv = dev;
platform_set_drvdata(pdev, dev);
dev_info(&pdev->dev, "ZyDAS ZD1301 demod attached\n");
return 0;
err_kfree:
kfree(dev);
err:
dev_dbg(&pdev->dev, "failed=%d\n", ret);
return ret;
}
static void zd1301_demod_remove(struct platform_device *pdev)
{
struct zd1301_demod_dev *dev = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "\n");
i2c_del_adapter(&dev->adapter);
kfree(dev);
}
static struct platform_driver zd1301_demod_driver = {
.driver = {
.name = "zd1301_demod",
.suppress_bind_attrs = true,
},
.probe = zd1301_demod_probe,
.remove_new = zd1301_demod_remove,
};
module_platform_driver(zd1301_demod_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("ZyDAS ZD1301 demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/zd1301_demod.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner driver
Copyright (C) 2008 Patrick Boettcher <[email protected]>
Copyright (C) 2009 Sergey Tyurin <forum.free-x.de>
Updated 2012 by Jannis Achstetter <[email protected]>
Copyright (C) 2015 Jemma Denson <[email protected]>
April 2015
Refactored & simplified driver
Updated to work with delivery system supplied by DVBv5
Add frequency, fec & pilot to get_frontend
Cards supported: Technisat Skystar S2
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include <media/dvb_frontend.h>
#include "cx24120.h"
#define CX24120_SEARCH_RANGE_KHZ 5000
#define CX24120_FIRMWARE "dvb-fe-cx24120-1.20.58.2.fw"
/* cx24120 i2c registers */
#define CX24120_REG_CMD_START 0x00 /* write cmd_id */
#define CX24120_REG_CMD_ARGS 0x01 /* write command arguments */
#define CX24120_REG_CMD_END 0x1f /* write 0x01 for end */
#define CX24120_REG_MAILBOX 0x33
#define CX24120_REG_FREQ3 0x34 /* frequency */
#define CX24120_REG_FREQ2 0x35
#define CX24120_REG_FREQ1 0x36
#define CX24120_REG_FECMODE 0x39 /* FEC status */
#define CX24120_REG_STATUS 0x3a /* Tuner status */
#define CX24120_REG_SIGSTR_H 0x3a /* Signal strength high */
#define CX24120_REG_SIGSTR_L 0x3b /* Signal strength low byte */
#define CX24120_REG_QUALITY_H 0x40 /* SNR high byte */
#define CX24120_REG_QUALITY_L 0x41 /* SNR low byte */
#define CX24120_REG_BER_HH 0x47 /* BER high byte of high word */
#define CX24120_REG_BER_HL 0x48 /* BER low byte of high word */
#define CX24120_REG_BER_LH 0x49 /* BER high byte of low word */
#define CX24120_REG_BER_LL 0x4a /* BER low byte of low word */
#define CX24120_REG_UCB_H 0x50 /* UCB high byte */
#define CX24120_REG_UCB_L 0x51 /* UCB low byte */
#define CX24120_REG_CLKDIV 0xe6
#define CX24120_REG_RATEDIV 0xf0
#define CX24120_REG_REVISION 0xff /* Chip revision (ro) */
/* Command messages */
enum command_message_id {
CMD_VCO_SET = 0x10, /* cmd.len = 12; */
CMD_TUNEREQUEST = 0x11, /* cmd.len = 15; */
CMD_MPEG_ONOFF = 0x13, /* cmd.len = 4; */
CMD_MPEG_INIT = 0x14, /* cmd.len = 7; */
CMD_BANDWIDTH = 0x15, /* cmd.len = 12; */
CMD_CLOCK_READ = 0x16, /* read clock */
CMD_CLOCK_SET = 0x17, /* cmd.len = 10; */
CMD_DISEQC_MSG1 = 0x20, /* cmd.len = 11; */
CMD_DISEQC_MSG2 = 0x21, /* cmd.len = d->msg_len + 6; */
CMD_SETVOLTAGE = 0x22, /* cmd.len = 2; */
CMD_SETTONE = 0x23, /* cmd.len = 4; */
CMD_DISEQC_BURST = 0x24, /* cmd.len not used !!! */
CMD_READ_SNR = 0x1a, /* Read signal strength */
CMD_START_TUNER = 0x1b, /* ??? */
CMD_FWVERSION = 0x35,
CMD_BER_CTRL = 0x3c, /* cmd.len = 0x03; */
};
#define CX24120_MAX_CMD_LEN 30
/* pilot mask */
#define CX24120_PILOT_OFF 0x00
#define CX24120_PILOT_ON 0x40
#define CX24120_PILOT_AUTO 0x80
/* signal status */
#define CX24120_HAS_SIGNAL 0x01
#define CX24120_HAS_CARRIER 0x02
#define CX24120_HAS_VITERBI 0x04
#define CX24120_HAS_LOCK 0x08
#define CX24120_HAS_UNK1 0x10
#define CX24120_HAS_UNK2 0x20
#define CX24120_STATUS_MASK 0x0f
#define CX24120_SIGNAL_MASK 0xc0
/* ber window */
#define CX24120_BER_WINDOW 16
#define CX24120_BER_WSIZE ((1 << CX24120_BER_WINDOW) * 208 * 8)
#define info(args...) pr_info("cx24120: " args)
#define err(args...) pr_err("cx24120: ### ERROR: " args)
/* The Demod/Tuner can't easily provide these, we cache them */
struct cx24120_tuning {
u32 frequency;
u32 symbol_rate;
enum fe_spectral_inversion inversion;
enum fe_code_rate fec;
enum fe_delivery_system delsys;
enum fe_modulation modulation;
enum fe_pilot pilot;
/* Demod values */
u8 fec_val;
u8 fec_mask;
u8 clkdiv;
u8 ratediv;
u8 inversion_val;
u8 pilot_val;
};
/* Private state */
struct cx24120_state {
struct i2c_adapter *i2c;
const struct cx24120_config *config;
struct dvb_frontend frontend;
u8 cold_init;
u8 mpeg_enabled;
u8 need_clock_set;
/* current and next tuning parameters */
struct cx24120_tuning dcur;
struct cx24120_tuning dnxt;
enum fe_status fe_status;
/* dvbv5 stats calculations */
u32 bitrate;
u32 berw_usecs;
u32 ber_prev;
u32 ucb_offset;
unsigned long ber_jiffies_stats;
unsigned long per_jiffies_stats;
};
/* Command message to firmware */
struct cx24120_cmd {
u8 id;
u8 len;
u8 arg[CX24120_MAX_CMD_LEN];
};
/* Read single register */
static int cx24120_readreg(struct cx24120_state *state, u8 reg)
{
int ret;
u8 buf = 0;
struct i2c_msg msg[] = {
{
.addr = state->config->i2c_addr,
.flags = 0,
.len = 1,
.buf = ®
}, {
.addr = state->config->i2c_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = &buf
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
err("Read error: reg=0x%02x, ret=%i)\n", reg, ret);
return ret;
}
dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, buf);
return buf;
}
/* Write single register */
static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = state->config->i2c_addr,
.flags = 0,
.buf = buf,
.len = 2
};
int ret;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
err("Write error: i2c_write error(err == %i, 0x%02x: 0x%02x)\n",
ret, reg, data);
return ret;
}
dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, data);
return 0;
}
/* Write multiple registers in chunks of i2c_wr_max-sized buffers */
static int cx24120_writeregs(struct cx24120_state *state,
u8 reg, const u8 *values, u16 len, u8 incr)
{
int ret;
u16 max = state->config->i2c_wr_max > 0 ?
state->config->i2c_wr_max :
len;
struct i2c_msg msg = {
.addr = state->config->i2c_addr,
.flags = 0,
};
msg.buf = kmalloc(max + 1, GFP_KERNEL);
if (!msg.buf)
return -ENOMEM;
while (len) {
msg.buf[0] = reg;
msg.len = len > max ? max : len;
memcpy(&msg.buf[1], values, msg.len);
len -= msg.len; /* data length revers counter */
values += msg.len; /* incr data pointer */
if (incr)
reg += msg.len;
msg.len++; /* don't forget the addr byte */
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
err("i2c_write error(err == %i, 0x%02x)\n", ret, reg);
goto out;
}
dev_dbg(&state->i2c->dev, "reg=0x%02x; data=%*ph\n",
reg, msg.len - 1, msg.buf + 1);
}
ret = 0;
out:
kfree(msg.buf);
return ret;
}
static const struct dvb_frontend_ops cx24120_ops;
struct dvb_frontend *cx24120_attach(const struct cx24120_config *config,
struct i2c_adapter *i2c)
{
struct cx24120_state *state;
int demod_rev;
info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner\n");
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state) {
err("Unable to allocate memory for cx24120_state\n");
goto error;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is present and has proper type */
demod_rev = cx24120_readreg(state, CX24120_REG_REVISION);
switch (demod_rev) {
case 0x07:
info("Demod cx24120 rev. 0x07 detected.\n");
break;
case 0x05:
info("Demod cx24120 rev. 0x05 detected.\n");
break;
default:
err("Unsupported demod revision: 0x%x detected.\n", demod_rev);
goto error;
}
/* create dvb_frontend */
state->cold_init = 0;
memcpy(&state->frontend.ops, &cx24120_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
info("Conexant cx24120/cx24118 attached.\n");
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(cx24120_attach);
static int cx24120_test_rom(struct cx24120_state *state)
{
int err, ret;
err = cx24120_readreg(state, 0xfd);
if (err & 4) {
ret = cx24120_readreg(state, 0xdf) & 0xfe;
err = cx24120_writereg(state, 0xdf, ret);
}
return err;
}
static int cx24120_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->cnr.stat[0].scale != FE_SCALE_DECIBEL)
*snr = 0;
else
*snr = div_s64(c->cnr.stat[0].svalue, 100);
return 0;
}
static int cx24120_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cx24120_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
*ber = 0;
return 0;
}
*ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
state->ber_prev = c->post_bit_error.stat[0].uvalue;
return 0;
}
static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
u8 flag);
/* Check if we're running a command that needs to disable mpeg out */
static void cx24120_check_cmd(struct cx24120_state *state, u8 id)
{
switch (id) {
case CMD_TUNEREQUEST:
case CMD_CLOCK_READ:
case CMD_DISEQC_MSG1:
case CMD_DISEQC_MSG2:
case CMD_SETVOLTAGE:
case CMD_SETTONE:
case CMD_DISEQC_BURST:
cx24120_msg_mpeg_output_global_config(state, 0);
/* Old driver would do a msleep(100) here */
return;
default:
return;
}
}
/* Send a message to the firmware */
static int cx24120_message_send(struct cx24120_state *state,
struct cx24120_cmd *cmd)
{
int ficus;
if (state->mpeg_enabled) {
/* Disable mpeg out on certain commands */
cx24120_check_cmd(state, cmd->id);
}
cx24120_writereg(state, CX24120_REG_CMD_START, cmd->id);
cx24120_writeregs(state, CX24120_REG_CMD_ARGS, &cmd->arg[0],
cmd->len, 1);
cx24120_writereg(state, CX24120_REG_CMD_END, 0x01);
ficus = 1000;
while (cx24120_readreg(state, CX24120_REG_CMD_END)) {
msleep(20);
ficus -= 20;
if (ficus == 0) {
err("Error sending message to firmware\n");
return -EREMOTEIO;
}
}
dev_dbg(&state->i2c->dev, "sent message 0x%02x\n", cmd->id);
return 0;
}
/* Send a message and fill arg[] with the results */
static int cx24120_message_sendrcv(struct cx24120_state *state,
struct cx24120_cmd *cmd, u8 numreg)
{
int ret, i;
if (numreg > CX24120_MAX_CMD_LEN) {
err("Too many registers to read. cmd->reg = %d", numreg);
return -EREMOTEIO;
}
ret = cx24120_message_send(state, cmd);
if (ret != 0)
return ret;
if (!numreg)
return 0;
/* Read numreg registers starting from register cmd->len */
for (i = 0; i < numreg; i++)
cmd->arg[i] = cx24120_readreg(state, (cmd->len + i + 1));
return 0;
}
static int cx24120_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->strength.stat[0].scale != FE_SCALE_RELATIVE)
*signal_strength = 0;
else
*signal_strength = c->strength.stat[0].uvalue;
return 0;
}
static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
u8 enable)
{
struct cx24120_cmd cmd;
int ret;
cmd.id = CMD_MPEG_ONOFF;
cmd.len = 4;
cmd.arg[0] = 0x01;
cmd.arg[1] = 0x00;
cmd.arg[2] = enable ? 0 : (u8)(-1);
cmd.arg[3] = 0x01;
ret = cx24120_message_send(state, &cmd);
if (ret != 0) {
dev_dbg(&state->i2c->dev, "failed to %s MPEG output\n",
enable ? "enable" : "disable");
return ret;
}
state->mpeg_enabled = enable;
dev_dbg(&state->i2c->dev, "MPEG output %s\n",
enable ? "enabled" : "disabled");
return 0;
}
static int cx24120_msg_mpeg_output_config(struct cx24120_state *state, u8 seq)
{
struct cx24120_cmd cmd;
struct cx24120_initial_mpeg_config i =
state->config->initial_mpeg_config;
cmd.id = CMD_MPEG_INIT;
cmd.len = 7;
cmd.arg[0] = seq; /* sequental number - can be 0,1,2 */
cmd.arg[1] = ((i.x1 & 0x01) << 1) | ((i.x1 >> 1) & 0x01);
cmd.arg[2] = 0x05;
cmd.arg[3] = 0x02;
cmd.arg[4] = ((i.x2 >> 1) & 0x01);
cmd.arg[5] = (i.x2 & 0xf0) | (i.x3 & 0x0f);
cmd.arg[6] = 0x10;
return cx24120_message_send(state, &cmd);
}
static int cx24120_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
dev_dbg(&state->i2c->dev, "\n");
/*
* Yes, cmd.len is set to zero. The old driver
* didn't specify any len, but also had a
* memset 0 before every use of the cmd struct
* which would have set it to zero.
* This quite probably needs looking into.
*/
cmd.id = CMD_DISEQC_BURST;
cmd.len = 0;
cmd.arg[0] = 0x00;
cmd.arg[1] = (burst == SEC_MINI_B) ? 0x01 : 0x00;
return cx24120_message_send(state, &cmd);
}
static int cx24120_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
dev_dbg(&state->i2c->dev, "(%d)\n", tone);
if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
err("Invalid tone=%d\n", tone);
return -EINVAL;
}
cmd.id = CMD_SETTONE;
cmd.len = 4;
cmd.arg[0] = 0x00;
cmd.arg[1] = 0x00;
cmd.arg[2] = 0x00;
cmd.arg[3] = (tone == SEC_TONE_ON) ? 0x01 : 0x00;
return cx24120_message_send(state, &cmd);
}
static int cx24120_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
dev_dbg(&state->i2c->dev, "(%d)\n", voltage);
cmd.id = CMD_SETVOLTAGE;
cmd.len = 2;
cmd.arg[0] = 0x00;
cmd.arg[1] = (voltage == SEC_VOLTAGE_18) ? 0x01 : 0x00;
return cx24120_message_send(state, &cmd);
}
static int cx24120_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *d)
{
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
int back_count;
dev_dbg(&state->i2c->dev, "\n");
cmd.id = CMD_DISEQC_MSG1;
cmd.len = 11;
cmd.arg[0] = 0x00;
cmd.arg[1] = 0x00;
cmd.arg[2] = 0x03;
cmd.arg[3] = 0x16;
cmd.arg[4] = 0x28;
cmd.arg[5] = 0x01;
cmd.arg[6] = 0x01;
cmd.arg[7] = 0x14;
cmd.arg[8] = 0x19;
cmd.arg[9] = 0x14;
cmd.arg[10] = 0x1e;
if (cx24120_message_send(state, &cmd)) {
err("send 1st message(0x%x) failed\n", cmd.id);
return -EREMOTEIO;
}
cmd.id = CMD_DISEQC_MSG2;
cmd.len = d->msg_len + 6;
cmd.arg[0] = 0x00;
cmd.arg[1] = 0x01;
cmd.arg[2] = 0x02;
cmd.arg[3] = 0x00;
cmd.arg[4] = 0x00;
cmd.arg[5] = d->msg_len;
memcpy(&cmd.arg[6], &d->msg, d->msg_len);
if (cx24120_message_send(state, &cmd)) {
err("send 2nd message(0x%x) failed\n", cmd.id);
return -EREMOTEIO;
}
back_count = 500;
do {
if (!(cx24120_readreg(state, 0x93) & 0x01)) {
dev_dbg(&state->i2c->dev, "diseqc sequence sent\n");
return 0;
}
msleep(20);
back_count -= 20;
} while (back_count);
err("Too long waiting for diseqc.\n");
return -ETIMEDOUT;
}
static void cx24120_get_stats(struct cx24120_state *state)
{
struct dvb_frontend *fe = &state->frontend;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24120_cmd cmd;
int ret, cnr, msecs;
u16 sig, ucb;
u32 ber;
dev_dbg(&state->i2c->dev, "\n");
/* signal strength */
if (state->fe_status & FE_HAS_SIGNAL) {
cmd.id = CMD_READ_SNR;
cmd.len = 1;
cmd.arg[0] = 0x00;
ret = cx24120_message_send(state, &cmd);
if (ret != 0) {
err("error reading signal strength\n");
return;
}
/* raw */
sig = cx24120_readreg(state, CX24120_REG_SIGSTR_H) >> 6;
sig = sig << 8;
sig |= cx24120_readreg(state, CX24120_REG_SIGSTR_L);
dev_dbg(&state->i2c->dev,
"signal strength from firmware = 0x%x\n", sig);
/* cooked */
sig = -100 * sig + 94324;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = sig;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (state->fe_status & FE_HAS_VITERBI) {
cnr = cx24120_readreg(state, CX24120_REG_QUALITY_H) << 8;
cnr |= cx24120_readreg(state, CX24120_REG_QUALITY_L);
dev_dbg(&state->i2c->dev, "read SNR index = %d\n", cnr);
/* guessed - seems about right */
cnr = cnr * 100;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER & UCB require lock */
if (!(state->fe_status & FE_HAS_LOCK)) {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
/* BER */
if (time_after(jiffies, state->ber_jiffies_stats)) {
msecs = (state->berw_usecs + 500) / 1000;
state->ber_jiffies_stats = jiffies + msecs_to_jiffies(msecs);
ber = cx24120_readreg(state, CX24120_REG_BER_HH) << 24;
ber |= cx24120_readreg(state, CX24120_REG_BER_HL) << 16;
ber |= cx24120_readreg(state, CX24120_REG_BER_LH) << 8;
ber |= cx24120_readreg(state, CX24120_REG_BER_LL);
dev_dbg(&state->i2c->dev, "read BER index = %d\n", ber);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += ber;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += CX24120_BER_WSIZE;
}
/* UCB */
if (time_after(jiffies, state->per_jiffies_stats)) {
state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
ucb = cx24120_readreg(state, CX24120_REG_UCB_H) << 8;
ucb |= cx24120_readreg(state, CX24120_REG_UCB_L);
dev_dbg(&state->i2c->dev, "ucblocks = %d\n", ucb);
/* handle reset */
if (ucb < state->ucb_offset)
state->ucb_offset = c->block_error.stat[0].uvalue;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = ucb + state->ucb_offset;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += state->bitrate / 8 / 208;
}
}
static void cx24120_set_clock_ratios(struct dvb_frontend *fe);
/* Read current tuning status */
static int cx24120_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx24120_state *state = fe->demodulator_priv;
int lock;
lock = cx24120_readreg(state, CX24120_REG_STATUS);
dev_dbg(&state->i2c->dev, "status = 0x%02x\n", lock);
*status = 0;
if (lock & CX24120_HAS_SIGNAL)
*status = FE_HAS_SIGNAL;
if (lock & CX24120_HAS_CARRIER)
*status |= FE_HAS_CARRIER;
if (lock & CX24120_HAS_VITERBI)
*status |= FE_HAS_VITERBI | FE_HAS_SYNC;
if (lock & CX24120_HAS_LOCK)
*status |= FE_HAS_LOCK;
/*
* TODO: is FE_HAS_SYNC in the right place?
* Other cx241xx drivers have this slightly
* different
*/
state->fe_status = *status;
cx24120_get_stats(state);
/* Set the clock once tuned in */
if (state->need_clock_set && *status & FE_HAS_LOCK) {
/* Set clock ratios */
cx24120_set_clock_ratios(fe);
/* Old driver would do a msleep(200) here */
/* Renable mpeg output */
if (!state->mpeg_enabled)
cx24120_msg_mpeg_output_global_config(state, 1);
state->need_clock_set = 0;
}
return 0;
}
/*
* FEC & modulation lookup table
* Used for decoding the REG_FECMODE register
* once tuned in.
*/
struct cx24120_modfec {
enum fe_delivery_system delsys;
enum fe_modulation mod;
enum fe_code_rate fec;
u8 val;
};
static const struct cx24120_modfec modfec_lookup_table[] = {
/*delsys mod fec val */
{ SYS_DVBS, QPSK, FEC_1_2, 0x01 },
{ SYS_DVBS, QPSK, FEC_2_3, 0x02 },
{ SYS_DVBS, QPSK, FEC_3_4, 0x03 },
{ SYS_DVBS, QPSK, FEC_4_5, 0x04 },
{ SYS_DVBS, QPSK, FEC_5_6, 0x05 },
{ SYS_DVBS, QPSK, FEC_6_7, 0x06 },
{ SYS_DVBS, QPSK, FEC_7_8, 0x07 },
{ SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
{ SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
{ SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
{ SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
{ SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
{ SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
{ SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
{ SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
{ SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
{ SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
{ SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
{ SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
{ SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
{ SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
};
/* Retrieve current fec, modulation & pilot values */
static int cx24120_get_fec(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24120_state *state = fe->demodulator_priv;
int idx;
int ret;
int fec;
ret = cx24120_readreg(state, CX24120_REG_FECMODE);
fec = ret & 0x3f; /* Lower 6 bits */
dev_dbg(&state->i2c->dev, "raw fec = %d\n", fec);
for (idx = 0; idx < ARRAY_SIZE(modfec_lookup_table); idx++) {
if (modfec_lookup_table[idx].delsys != state->dcur.delsys)
continue;
if (modfec_lookup_table[idx].val != fec)
continue;
break; /* found */
}
if (idx >= ARRAY_SIZE(modfec_lookup_table)) {
dev_dbg(&state->i2c->dev, "couldn't find fec!\n");
return -EINVAL;
}
/* save values back to cache */
c->modulation = modfec_lookup_table[idx].mod;
c->fec_inner = modfec_lookup_table[idx].fec;
c->pilot = (ret & 0x80) ? PILOT_ON : PILOT_OFF;
dev_dbg(&state->i2c->dev, "mod(%d), fec(%d), pilot(%d)\n",
c->modulation, c->fec_inner, c->pilot);
return 0;
}
/* Calculate ber window time */
static void cx24120_calculate_ber_window(struct cx24120_state *state, u32 rate)
{
struct dvb_frontend *fe = &state->frontend;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u64 tmp;
/*
* Calculate bitrate from rate in the clock ratios table.
* This isn't *exactly* right but close enough.
*/
tmp = (u64)c->symbol_rate * rate;
do_div(tmp, 256);
state->bitrate = tmp;
/* usecs per ber window */
tmp = 1000000ULL * CX24120_BER_WSIZE;
do_div(tmp, state->bitrate);
state->berw_usecs = tmp;
dev_dbg(&state->i2c->dev, "bitrate: %u, berw_usecs: %u\n",
state->bitrate, state->berw_usecs);
}
/*
* Clock ratios lookup table
*
* Values obtained from much larger table in old driver
* which had numerous entries which would never match.
*
* There's probably some way of calculating these but I
* can't determine the pattern
*/
struct cx24120_clock_ratios_table {
enum fe_delivery_system delsys;
enum fe_pilot pilot;
enum fe_modulation mod;
enum fe_code_rate fec;
u32 m_rat;
u32 n_rat;
u32 rate;
};
static const struct cx24120_clock_ratios_table clock_ratios_table[] = {
/*delsys pilot mod fec m_rat n_rat rate */
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_1_2, 273088, 254505, 274 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_5, 17272, 13395, 330 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_2_3, 24344, 16967, 367 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_4, 410788, 254505, 413 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_4_5, 438328, 254505, 440 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_5_6, 30464, 16967, 459 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_8_9, 487832, 254505, 490 },
{ SYS_DVBS2, PILOT_OFF, QPSK, FEC_9_10, 493952, 254505, 496 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_5, 328168, 169905, 494 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_2_3, 24344, 11327, 550 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_4, 410788, 169905, 618 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_5_6, 30464, 11327, 688 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_8_9, 487832, 169905, 735 },
{ SYS_DVBS2, PILOT_OFF, PSK_8, FEC_9_10, 493952, 169905, 744 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_1_2, 273088, 260709, 268 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_3_5, 328168, 260709, 322 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_2_3, 121720, 86903, 358 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_3_4, 410788, 260709, 403 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_4_5, 438328, 260709, 430 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_5_6, 152320, 86903, 448 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_8_9, 487832, 260709, 479 },
{ SYS_DVBS2, PILOT_ON, QPSK, FEC_9_10, 493952, 260709, 485 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_5, 328168, 173853, 483 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_2_3, 121720, 57951, 537 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_4, 410788, 173853, 604 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_5_6, 152320, 57951, 672 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_8_9, 487832, 173853, 718 },
{ SYS_DVBS2, PILOT_ON, PSK_8, FEC_9_10, 493952, 173853, 727 },
{ SYS_DVBS, PILOT_OFF, QPSK, FEC_1_2, 152592, 152592, 256 },
{ SYS_DVBS, PILOT_OFF, QPSK, FEC_2_3, 305184, 228888, 341 },
{ SYS_DVBS, PILOT_OFF, QPSK, FEC_3_4, 457776, 305184, 384 },
{ SYS_DVBS, PILOT_OFF, QPSK, FEC_5_6, 762960, 457776, 427 },
{ SYS_DVBS, PILOT_OFF, QPSK, FEC_7_8, 1068144, 610368, 448 },
};
/* Set clock ratio from lookup table */
static void cx24120_set_clock_ratios(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
int ret, idx;
/* Find fec, modulation, pilot */
ret = cx24120_get_fec(fe);
if (ret != 0)
return;
/* Find the clock ratios in the lookup table */
for (idx = 0; idx < ARRAY_SIZE(clock_ratios_table); idx++) {
if (clock_ratios_table[idx].delsys != state->dcur.delsys)
continue;
if (clock_ratios_table[idx].mod != c->modulation)
continue;
if (clock_ratios_table[idx].fec != c->fec_inner)
continue;
if (clock_ratios_table[idx].pilot != c->pilot)
continue;
break; /* found */
}
if (idx >= ARRAY_SIZE(clock_ratios_table)) {
info("Clock ratio not found - data reception in danger\n");
return;
}
/* Read current values? */
cmd.id = CMD_CLOCK_READ;
cmd.len = 1;
cmd.arg[0] = 0x00;
ret = cx24120_message_sendrcv(state, &cmd, 6);
if (ret != 0)
return;
/* in cmd[0]-[5] - result */
dev_dbg(&state->i2c->dev, "m=%d, n=%d; idx: %d m=%d, n=%d, rate=%d\n",
cmd.arg[2] | (cmd.arg[1] << 8) | (cmd.arg[0] << 16),
cmd.arg[5] | (cmd.arg[4] << 8) | (cmd.arg[3] << 16),
idx,
clock_ratios_table[idx].m_rat,
clock_ratios_table[idx].n_rat,
clock_ratios_table[idx].rate);
/* Set the clock */
cmd.id = CMD_CLOCK_SET;
cmd.len = 10;
cmd.arg[0] = 0;
cmd.arg[1] = 0x10;
cmd.arg[2] = (clock_ratios_table[idx].m_rat >> 16) & 0xff;
cmd.arg[3] = (clock_ratios_table[idx].m_rat >> 8) & 0xff;
cmd.arg[4] = (clock_ratios_table[idx].m_rat >> 0) & 0xff;
cmd.arg[5] = (clock_ratios_table[idx].n_rat >> 16) & 0xff;
cmd.arg[6] = (clock_ratios_table[idx].n_rat >> 8) & 0xff;
cmd.arg[7] = (clock_ratios_table[idx].n_rat >> 0) & 0xff;
cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff;
cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff;
ret = cx24120_message_send(state, &cmd);
if (ret != 0)
return;
/* Calculate ber window rates for stat work */
cx24120_calculate_ber_window(state, clock_ratios_table[idx].rate);
}
/* Set inversion value */
static int cx24120_set_inversion(struct cx24120_state *state,
enum fe_spectral_inversion inversion)
{
dev_dbg(&state->i2c->dev, "(%d)\n", inversion);
switch (inversion) {
case INVERSION_OFF:
state->dnxt.inversion_val = 0x00;
break;
case INVERSION_ON:
state->dnxt.inversion_val = 0x04;
break;
case INVERSION_AUTO:
state->dnxt.inversion_val = 0x0c;
break;
default:
return -EINVAL;
}
state->dnxt.inversion = inversion;
return 0;
}
/* FEC lookup table for tuning */
struct cx24120_modfec_table {
enum fe_delivery_system delsys;
enum fe_modulation mod;
enum fe_code_rate fec;
u8 val;
};
static const struct cx24120_modfec_table modfec_table[] = {
/*delsys mod fec val */
{ SYS_DVBS, QPSK, FEC_1_2, 0x2e },
{ SYS_DVBS, QPSK, FEC_2_3, 0x2f },
{ SYS_DVBS, QPSK, FEC_3_4, 0x30 },
{ SYS_DVBS, QPSK, FEC_5_6, 0x31 },
{ SYS_DVBS, QPSK, FEC_6_7, 0x32 },
{ SYS_DVBS, QPSK, FEC_7_8, 0x33 },
{ SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
{ SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
{ SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
{ SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
{ SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
{ SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
{ SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
{ SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
{ SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
{ SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
{ SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
{ SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
{ SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
{ SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
};
/* Set fec_val & fec_mask values from delsys, modulation & fec */
static int cx24120_set_fec(struct cx24120_state *state, enum fe_modulation mod,
enum fe_code_rate fec)
{
int idx;
dev_dbg(&state->i2c->dev, "(0x%02x,0x%02x)\n", mod, fec);
state->dnxt.fec = fec;
/* Lookup fec_val from modfec table */
for (idx = 0; idx < ARRAY_SIZE(modfec_table); idx++) {
if (modfec_table[idx].delsys != state->dnxt.delsys)
continue;
if (modfec_table[idx].mod != mod)
continue;
if (modfec_table[idx].fec != fec)
continue;
/* found */
state->dnxt.fec_mask = 0x00;
state->dnxt.fec_val = modfec_table[idx].val;
return 0;
}
if (state->dnxt.delsys == SYS_DVBS2) {
/* DVBS2 auto is 0x00/0x00 */
state->dnxt.fec_mask = 0x00;
state->dnxt.fec_val = 0x00;
} else {
/* Set DVB-S to auto */
state->dnxt.fec_val = 0x2e;
state->dnxt.fec_mask = 0xac;
}
return 0;
}
/* Set pilot */
static int cx24120_set_pilot(struct cx24120_state *state, enum fe_pilot pilot)
{
dev_dbg(&state->i2c->dev, "(%d)\n", pilot);
/* Pilot only valid in DVBS2 */
if (state->dnxt.delsys != SYS_DVBS2) {
state->dnxt.pilot_val = CX24120_PILOT_OFF;
return 0;
}
switch (pilot) {
case PILOT_OFF:
state->dnxt.pilot_val = CX24120_PILOT_OFF;
break;
case PILOT_ON:
state->dnxt.pilot_val = CX24120_PILOT_ON;
break;
case PILOT_AUTO:
default:
state->dnxt.pilot_val = CX24120_PILOT_AUTO;
}
return 0;
}
/* Set symbol rate */
static int cx24120_set_symbolrate(struct cx24120_state *state, u32 rate)
{
dev_dbg(&state->i2c->dev, "(%d)\n", rate);
state->dnxt.symbol_rate = rate;
/* Check symbol rate */
if (rate > 31000000) {
state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2;
state->dnxt.ratediv = (-(rate < 31000001) & 6) + 4;
} else {
state->dnxt.clkdiv = 3;
state->dnxt.ratediv = 6;
}
return 0;
}
/* Overwrite the current tuning params, we are about to tune */
static void cx24120_clone_params(struct dvb_frontend *fe)
{
struct cx24120_state *state = fe->demodulator_priv;
state->dcur = state->dnxt;
}
static int cx24120_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
int ret;
switch (c->delivery_system) {
case SYS_DVBS2:
dev_dbg(&state->i2c->dev, "DVB-S2\n");
break;
case SYS_DVBS:
dev_dbg(&state->i2c->dev, "DVB-S\n");
break;
default:
dev_dbg(&state->i2c->dev,
"delivery system(%d) not supported\n",
c->delivery_system);
return -EINVAL;
}
state->dnxt.delsys = c->delivery_system;
state->dnxt.modulation = c->modulation;
state->dnxt.frequency = c->frequency;
state->dnxt.pilot = c->pilot;
ret = cx24120_set_inversion(state, c->inversion);
if (ret != 0)
return ret;
ret = cx24120_set_fec(state, c->modulation, c->fec_inner);
if (ret != 0)
return ret;
ret = cx24120_set_pilot(state, c->pilot);
if (ret != 0)
return ret;
ret = cx24120_set_symbolrate(state, c->symbol_rate);
if (ret != 0)
return ret;
/* discard the 'current' tuning parameters and prepare to tune */
cx24120_clone_params(fe);
dev_dbg(&state->i2c->dev,
"delsys = %d\n", state->dcur.delsys);
dev_dbg(&state->i2c->dev,
"modulation = %d\n", state->dcur.modulation);
dev_dbg(&state->i2c->dev,
"frequency = %d\n", state->dcur.frequency);
dev_dbg(&state->i2c->dev,
"pilot = %d (val = 0x%02x)\n",
state->dcur.pilot, state->dcur.pilot_val);
dev_dbg(&state->i2c->dev,
"symbol_rate = %d (clkdiv/ratediv = 0x%02x/0x%02x)\n",
state->dcur.symbol_rate,
state->dcur.clkdiv, state->dcur.ratediv);
dev_dbg(&state->i2c->dev,
"FEC = %d (mask/val = 0x%02x/0x%02x)\n",
state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
dev_dbg(&state->i2c->dev,
"Inversion = %d (val = 0x%02x)\n",
state->dcur.inversion, state->dcur.inversion_val);
/* Flag that clock needs to be set after tune */
state->need_clock_set = 1;
/* Tune in */
cmd.id = CMD_TUNEREQUEST;
cmd.len = 15;
cmd.arg[0] = 0;
cmd.arg[1] = (state->dcur.frequency & 0xff0000) >> 16;
cmd.arg[2] = (state->dcur.frequency & 0x00ff00) >> 8;
cmd.arg[3] = (state->dcur.frequency & 0x0000ff);
cmd.arg[4] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
cmd.arg[5] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
cmd.arg[6] = state->dcur.inversion;
cmd.arg[7] = state->dcur.fec_val | state->dcur.pilot_val;
cmd.arg[8] = CX24120_SEARCH_RANGE_KHZ >> 8;
cmd.arg[9] = CX24120_SEARCH_RANGE_KHZ & 0xff;
cmd.arg[10] = 0; /* maybe rolloff? */
cmd.arg[11] = state->dcur.fec_mask;
cmd.arg[12] = state->dcur.ratediv;
cmd.arg[13] = state->dcur.clkdiv;
cmd.arg[14] = 0;
/* Send tune command */
ret = cx24120_message_send(state, &cmd);
if (ret != 0)
return ret;
/* Write symbol rate values */
ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv);
ret = cx24120_readreg(state, CX24120_REG_RATEDIV);
ret &= 0xfffffff0;
ret |= state->dcur.ratediv;
ret = cx24120_writereg(state, CX24120_REG_RATEDIV, ret);
return 0;
}
/* Set vco from config */
static int cx24120_set_vco(struct cx24120_state *state)
{
struct cx24120_cmd cmd;
u32 nxtal_khz, vco;
u64 inv_vco;
u32 xtal_khz = state->config->xtal_khz;
nxtal_khz = xtal_khz * 4;
vco = nxtal_khz * 10;
inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco);
dev_dbg(&state->i2c->dev, "xtal=%d, vco=%d, inv_vco=%lld\n",
xtal_khz, vco, inv_vco);
cmd.id = CMD_VCO_SET;
cmd.len = 12;
cmd.arg[0] = (vco >> 16) & 0xff;
cmd.arg[1] = (vco >> 8) & 0xff;
cmd.arg[2] = vco & 0xff;
cmd.arg[3] = (inv_vco >> 8) & 0xff;
cmd.arg[4] = (inv_vco) & 0xff;
cmd.arg[5] = 0x03;
cmd.arg[6] = (nxtal_khz >> 8) & 0xff;
cmd.arg[7] = nxtal_khz & 0xff;
cmd.arg[8] = 0x06;
cmd.arg[9] = 0x03;
cmd.arg[10] = (xtal_khz >> 16) & 0xff;
cmd.arg[11] = xtal_khz & 0xff;
return cx24120_message_send(state, &cmd);
}
static int cx24120_init(struct dvb_frontend *fe)
{
const struct firmware *fw;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24120_state *state = fe->demodulator_priv;
struct cx24120_cmd cmd;
u8 reg;
int ret, i;
unsigned char vers[4];
if (state->cold_init)
return 0;
/* ???? */
cx24120_writereg(state, 0xea, 0x00);
cx24120_test_rom(state);
reg = cx24120_readreg(state, 0xfb) & 0xfe;
cx24120_writereg(state, 0xfb, reg);
reg = cx24120_readreg(state, 0xfc) & 0xfe;
cx24120_writereg(state, 0xfc, reg);
cx24120_writereg(state, 0xc3, 0x04);
cx24120_writereg(state, 0xc4, 0x04);
cx24120_writereg(state, 0xce, 0x00);
cx24120_writereg(state, 0xcf, 0x00);
reg = cx24120_readreg(state, 0xea) & 0xfe;
cx24120_writereg(state, 0xea, reg);
cx24120_writereg(state, 0xeb, 0x0c);
cx24120_writereg(state, 0xec, 0x06);
cx24120_writereg(state, 0xed, 0x05);
cx24120_writereg(state, 0xee, 0x03);
cx24120_writereg(state, 0xef, 0x05);
cx24120_writereg(state, 0xf3, 0x03);
cx24120_writereg(state, 0xf4, 0x44);
for (i = 0; i < 3; i++) {
cx24120_writereg(state, 0xf0 + i, 0x04);
cx24120_writereg(state, 0xe6 + i, 0x02);
}
cx24120_writereg(state, 0xea, (reg | 0x01));
for (i = 0; i < 6; i += 2) {
cx24120_writereg(state, 0xc5 + i, 0x00);
cx24120_writereg(state, 0xc6 + i, 0x00);
}
cx24120_writereg(state, 0xe4, 0x03);
cx24120_writereg(state, 0xeb, 0x0a);
dev_dbg(&state->i2c->dev, "requesting firmware (%s) to download...\n",
CX24120_FIRMWARE);
ret = state->config->request_firmware(fe, &fw, CX24120_FIRMWARE);
if (ret) {
err("Could not load firmware (%s): %d\n", CX24120_FIRMWARE,
ret);
return ret;
}
dev_dbg(&state->i2c->dev,
"Firmware found, size %d bytes (%02x %02x .. %02x %02x)\n",
(int)fw->size, /* firmware_size in bytes */
fw->data[0], /* fw 1st byte */
fw->data[1], /* fw 2d byte */
fw->data[fw->size - 2], /* fw before last byte */
fw->data[fw->size - 1]); /* fw last byte */
cx24120_test_rom(state);
reg = cx24120_readreg(state, 0xfb) & 0xfe;
cx24120_writereg(state, 0xfb, reg);
cx24120_writereg(state, 0xe0, 0x76);
cx24120_writereg(state, 0xf7, 0x81);
cx24120_writereg(state, 0xf8, 0x00);
cx24120_writereg(state, 0xf9, 0x00);
cx24120_writeregs(state, 0xfa, fw->data, (fw->size - 1), 0x00);
cx24120_writereg(state, 0xf7, 0xc0);
cx24120_writereg(state, 0xe0, 0x00);
reg = (fw->size - 2) & 0x00ff;
cx24120_writereg(state, 0xf8, reg);
reg = ((fw->size - 2) >> 8) & 0x00ff;
cx24120_writereg(state, 0xf9, reg);
cx24120_writereg(state, 0xf7, 0x00);
cx24120_writereg(state, 0xdc, 0x00);
cx24120_writereg(state, 0xdc, 0x07);
msleep(500);
/* Check final byte matches final byte of firmware */
reg = cx24120_readreg(state, 0xe1);
if (reg == fw->data[fw->size - 1]) {
dev_dbg(&state->i2c->dev, "Firmware uploaded successfully\n");
ret = 0;
} else {
err("Firmware upload failed. Last byte returned=0x%x\n", ret);
ret = -EREMOTEIO;
}
cx24120_writereg(state, 0xdc, 0x00);
release_firmware(fw);
if (ret != 0)
return ret;
/* Start tuner */
cmd.id = CMD_START_TUNER;
cmd.len = 3;
cmd.arg[0] = 0x00;
cmd.arg[1] = 0x00;
cmd.arg[2] = 0x00;
if (cx24120_message_send(state, &cmd) != 0) {
err("Error tuner start! :(\n");
return -EREMOTEIO;
}
/* Set VCO */
ret = cx24120_set_vco(state);
if (ret != 0) {
err("Error set VCO! :(\n");
return ret;
}
/* set bandwidth */
cmd.id = CMD_BANDWIDTH;
cmd.len = 12;
cmd.arg[0] = 0x00;
cmd.arg[1] = 0x00;
cmd.arg[2] = 0x00;
cmd.arg[3] = 0x00;
cmd.arg[4] = 0x05;
cmd.arg[5] = 0x02;
cmd.arg[6] = 0x02;
cmd.arg[7] = 0x00;
cmd.arg[8] = 0x05;
cmd.arg[9] = 0x02;
cmd.arg[10] = 0x02;
cmd.arg[11] = 0x00;
if (cx24120_message_send(state, &cmd)) {
err("Error set bandwidth!\n");
return -EREMOTEIO;
}
reg = cx24120_readreg(state, 0xba);
if (reg > 3) {
dev_dbg(&state->i2c->dev, "Reset-readreg 0xba: %x\n", ret);
err("Error initialising tuner!\n");
return -EREMOTEIO;
}
dev_dbg(&state->i2c->dev, "Tuner initialised correctly.\n");
/* Initialise mpeg outputs */
cx24120_writereg(state, 0xeb, 0x0a);
if (cx24120_msg_mpeg_output_global_config(state, 0) ||
cx24120_msg_mpeg_output_config(state, 0) ||
cx24120_msg_mpeg_output_config(state, 1) ||
cx24120_msg_mpeg_output_config(state, 2)) {
err("Error initialising mpeg output. :(\n");
return -EREMOTEIO;
}
/* Set size of BER window */
cmd.id = CMD_BER_CTRL;
cmd.len = 3;
cmd.arg[0] = 0x00;
cmd.arg[1] = CX24120_BER_WINDOW;
cmd.arg[2] = CX24120_BER_WINDOW;
if (cx24120_message_send(state, &cmd)) {
err("Error setting ber window\n");
return -EREMOTEIO;
}
/* Firmware CMD 35: Get firmware version */
cmd.id = CMD_FWVERSION;
cmd.len = 1;
for (i = 0; i < 4; i++) {
cmd.arg[0] = i;
ret = cx24120_message_send(state, &cmd);
if (ret != 0)
return ret;
vers[i] = cx24120_readreg(state, CX24120_REG_MAILBOX);
}
info("FW version %i.%i.%i.%i\n", vers[0], vers[1], vers[2], vers[3]);
/* init stats here in order signal app which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
state->cold_init = 1;
return 0;
}
static int cx24120_tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags, unsigned int *delay,
enum fe_status *status)
{
struct cx24120_state *state = fe->demodulator_priv;
int ret;
dev_dbg(&state->i2c->dev, "(%d)\n", re_tune);
/* TODO: Do we need to set delay? */
if (re_tune) {
ret = cx24120_set_frontend(fe);
if (ret)
return ret;
}
return cx24120_read_status(fe, status);
}
static enum dvbfe_algo cx24120_get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static int cx24120_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int cx24120_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cx24120_state *state = fe->demodulator_priv;
u8 freq1, freq2, freq3;
int status;
dev_dbg(&state->i2c->dev, "\n");
/* don't return empty data if we're not tuned in */
status = cx24120_readreg(state, CX24120_REG_STATUS);
if (!(status & CX24120_HAS_LOCK))
return 0;
/* Get frequency */
freq1 = cx24120_readreg(state, CX24120_REG_FREQ1);
freq2 = cx24120_readreg(state, CX24120_REG_FREQ2);
freq3 = cx24120_readreg(state, CX24120_REG_FREQ3);
c->frequency = (freq3 << 16) | (freq2 << 8) | freq1;
dev_dbg(&state->i2c->dev, "frequency = %d\n", c->frequency);
/* Get modulation, fec, pilot */
cx24120_get_fec(fe);
return 0;
}
static void cx24120_release(struct dvb_frontend *fe)
{
struct cx24120_state *state = fe->demodulator_priv;
dev_dbg(&state->i2c->dev, "Clear state structure\n");
kfree(state);
}
static int cx24120_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct cx24120_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->block_error.stat[0].scale != FE_SCALE_COUNTER) {
*ucblocks = 0;
return 0;
}
*ucblocks = c->block_error.stat[0].uvalue - state->ucb_offset;
return 0;
}
static const struct dvb_frontend_ops cx24120_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "Conexant CX24120/CX24118",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = cx24120_release,
.init = cx24120_init,
.sleep = cx24120_sleep,
.tune = cx24120_tune,
.get_frontend_algo = cx24120_get_algo,
.set_frontend = cx24120_set_frontend,
.get_frontend = cx24120_get_frontend,
.read_status = cx24120_read_status,
.read_ber = cx24120_read_ber,
.read_signal_strength = cx24120_read_signal_strength,
.read_snr = cx24120_read_snr,
.read_ucblocks = cx24120_read_ucblocks,
.diseqc_send_master_cmd = cx24120_send_diseqc_msg,
.diseqc_send_burst = cx24120_diseqc_send_burst,
.set_tone = cx24120_set_tone,
.set_voltage = cx24120_set_voltage,
};
MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24120/CX24118 hardware");
MODULE_AUTHOR("Jemma Denson");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cx24120.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* descriptions + helper functions for simple dvb plls.
*
* (c) 2004 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/dvb/frontend.h>
#include <asm/types.h>
#include "dvb-pll.h"
#define dprintk(fmt, arg...) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), __func__, ##arg)
struct dvb_pll_priv {
/* pll number */
int nr;
/* i2c details */
int pll_i2c_address;
struct i2c_adapter *i2c;
/* the PLL descriptor */
const struct dvb_pll_desc *pll_desc;
/* cached frequency/bandwidth */
u32 frequency;
u32 bandwidth;
};
#define DVB_PLL_MAX 64
static DEFINE_IDA(pll_ida);
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable verbose debug messages");
static unsigned int id[DVB_PLL_MAX] =
{ [ 0 ... (DVB_PLL_MAX-1) ] = DVB_PLL_UNDEFINED };
module_param_array(id, int, NULL, 0644);
MODULE_PARM_DESC(id, "force pll id to use (DEBUG ONLY)");
/* ----------------------------------------------------------- */
struct dvb_pll_desc {
const char *name;
u32 min;
u32 max;
u32 iffreq;
void (*set)(struct dvb_frontend *fe, u8 *buf);
u8 *initdata;
u8 *initdata2;
u8 *sleepdata;
int count;
struct {
u32 limit;
u32 stepsize;
u8 config;
u8 cb;
} entries[];
};
/* ----------------------------------------------------------- */
/* descriptions */
static const struct dvb_pll_desc dvb_pll_thomson_dtt7579 = {
.name = "Thomson dtt7579",
.min = 177 * MHz,
.max = 858 * MHz,
.iffreq= 36166667,
.sleepdata = (u8[]){ 2, 0xb4, 0x03 },
.count = 4,
.entries = {
{ 443250000, 166667, 0xb4, 0x02 },
{ 542000000, 166667, 0xb4, 0x08 },
{ 771000000, 166667, 0xbc, 0x08 },
{ 999999999, 166667, 0xf4, 0x08 },
},
};
static void thomson_dtt759x_bw(struct dvb_frontend *fe, u8 *buf)
{
u32 bw = fe->dtv_property_cache.bandwidth_hz;
if (bw == 7000000)
buf[3] |= 0x10;
}
static const struct dvb_pll_desc dvb_pll_thomson_dtt759x = {
.name = "Thomson dtt759x",
.min = 177 * MHz,
.max = 896 * MHz,
.set = thomson_dtt759x_bw,
.iffreq= 36166667,
.sleepdata = (u8[]){ 2, 0x84, 0x03 },
.count = 5,
.entries = {
{ 264000000, 166667, 0xb4, 0x02 },
{ 470000000, 166667, 0xbc, 0x02 },
{ 735000000, 166667, 0xbc, 0x08 },
{ 835000000, 166667, 0xf4, 0x08 },
{ 999999999, 166667, 0xfc, 0x08 },
},
};
static void thomson_dtt7520x_bw(struct dvb_frontend *fe, u8 *buf)
{
u32 bw = fe->dtv_property_cache.bandwidth_hz;
if (bw == 8000000)
buf[3] ^= 0x10;
}
static const struct dvb_pll_desc dvb_pll_thomson_dtt7520x = {
.name = "Thomson dtt7520x",
.min = 185 * MHz,
.max = 900 * MHz,
.set = thomson_dtt7520x_bw,
.iffreq = 36166667,
.count = 7,
.entries = {
{ 305000000, 166667, 0xb4, 0x12 },
{ 405000000, 166667, 0xbc, 0x12 },
{ 445000000, 166667, 0xbc, 0x12 },
{ 465000000, 166667, 0xf4, 0x18 },
{ 735000000, 166667, 0xfc, 0x18 },
{ 835000000, 166667, 0xbc, 0x18 },
{ 999999999, 166667, 0xfc, 0x18 },
},
};
static const struct dvb_pll_desc dvb_pll_lg_z201 = {
.name = "LG z201",
.min = 174 * MHz,
.max = 862 * MHz,
.iffreq= 36166667,
.sleepdata = (u8[]){ 2, 0xbc, 0x03 },
.count = 5,
.entries = {
{ 157500000, 166667, 0xbc, 0x01 },
{ 443250000, 166667, 0xbc, 0x02 },
{ 542000000, 166667, 0xbc, 0x04 },
{ 830000000, 166667, 0xf4, 0x04 },
{ 999999999, 166667, 0xfc, 0x04 },
},
};
static const struct dvb_pll_desc dvb_pll_unknown_1 = {
.name = "unknown 1", /* used by dntv live dvb-t */
.min = 174 * MHz,
.max = 862 * MHz,
.iffreq= 36166667,
.count = 9,
.entries = {
{ 150000000, 166667, 0xb4, 0x01 },
{ 173000000, 166667, 0xbc, 0x01 },
{ 250000000, 166667, 0xb4, 0x02 },
{ 400000000, 166667, 0xbc, 0x02 },
{ 420000000, 166667, 0xf4, 0x02 },
{ 470000000, 166667, 0xfc, 0x02 },
{ 600000000, 166667, 0xbc, 0x08 },
{ 730000000, 166667, 0xf4, 0x08 },
{ 999999999, 166667, 0xfc, 0x08 },
},
};
/* Infineon TUA6010XS
* used in Thomson Cable Tuner
*/
static const struct dvb_pll_desc dvb_pll_tua6010xs = {
.name = "Infineon TUA6010XS",
.min = 44250 * kHz,
.max = 858 * MHz,
.iffreq= 36125000,
.count = 3,
.entries = {
{ 115750000, 62500, 0x8e, 0x03 },
{ 403250000, 62500, 0x8e, 0x06 },
{ 999999999, 62500, 0x8e, 0x85 },
},
};
/* Panasonic env57h1xd5 (some Philips PLL ?) */
static const struct dvb_pll_desc dvb_pll_env57h1xd5 = {
.name = "Panasonic ENV57H1XD5",
.min = 44250 * kHz,
.max = 858 * MHz,
.iffreq= 36125000,
.count = 4,
.entries = {
{ 153000000, 166667, 0xc2, 0x41 },
{ 470000000, 166667, 0xc2, 0x42 },
{ 526000000, 166667, 0xc2, 0x84 },
{ 999999999, 166667, 0xc2, 0xa4 },
},
};
/* Philips TDA6650/TDA6651
* used in Panasonic ENV77H11D5
*/
static void tda665x_bw(struct dvb_frontend *fe, u8 *buf)
{
u32 bw = fe->dtv_property_cache.bandwidth_hz;
if (bw == 8000000)
buf[3] |= 0x08;
}
static const struct dvb_pll_desc dvb_pll_tda665x = {
.name = "Philips TDA6650/TDA6651",
.min = 44250 * kHz,
.max = 858 * MHz,
.set = tda665x_bw,
.iffreq= 36166667,
.initdata = (u8[]){ 4, 0x0b, 0xf5, 0x85, 0xab },
.count = 12,
.entries = {
{ 93834000, 166667, 0xca, 0x61 /* 011 0 0 0 01 */ },
{ 123834000, 166667, 0xca, 0xa1 /* 101 0 0 0 01 */ },
{ 161000000, 166667, 0xca, 0xa1 /* 101 0 0 0 01 */ },
{ 163834000, 166667, 0xca, 0xc2 /* 110 0 0 0 10 */ },
{ 253834000, 166667, 0xca, 0x62 /* 011 0 0 0 10 */ },
{ 383834000, 166667, 0xca, 0xa2 /* 101 0 0 0 10 */ },
{ 443834000, 166667, 0xca, 0xc2 /* 110 0 0 0 10 */ },
{ 444000000, 166667, 0xca, 0xc4 /* 110 0 0 1 00 */ },
{ 583834000, 166667, 0xca, 0x64 /* 011 0 0 1 00 */ },
{ 793834000, 166667, 0xca, 0xa4 /* 101 0 0 1 00 */ },
{ 444834000, 166667, 0xca, 0xc4 /* 110 0 0 1 00 */ },
{ 861000000, 166667, 0xca, 0xe4 /* 111 0 0 1 00 */ },
}
};
/* Infineon TUA6034
* used in LG TDTP E102P
*/
static void tua6034_bw(struct dvb_frontend *fe, u8 *buf)
{
u32 bw = fe->dtv_property_cache.bandwidth_hz;
if (bw == 7000000)
buf[3] |= 0x08;
}
static const struct dvb_pll_desc dvb_pll_tua6034 = {
.name = "Infineon TUA6034",
.min = 44250 * kHz,
.max = 858 * MHz,
.iffreq= 36166667,
.count = 3,
.set = tua6034_bw,
.entries = {
{ 174500000, 62500, 0xce, 0x01 },
{ 230000000, 62500, 0xce, 0x02 },
{ 999999999, 62500, 0xce, 0x04 },
},
};
/* ALPS TDED4
* used in Nebula-Cards and USB boxes
*/
static void tded4_bw(struct dvb_frontend *fe, u8 *buf)
{
u32 bw = fe->dtv_property_cache.bandwidth_hz;
if (bw == 8000000)
buf[3] |= 0x04;
}
static const struct dvb_pll_desc dvb_pll_tded4 = {
.name = "ALPS TDED4",
.min = 47 * MHz,
.max = 863 * MHz,
.iffreq= 36166667,
.set = tded4_bw,
.count = 4,
.entries = {
{ 153000000, 166667, 0x85, 0x01 },
{ 470000000, 166667, 0x85, 0x02 },
{ 823000000, 166667, 0x85, 0x08 },
{ 999999999, 166667, 0x85, 0x88 },
}
};
/* ALPS TDHU2
* used in AverTVHD MCE A180
*/
static const struct dvb_pll_desc dvb_pll_tdhu2 = {
.name = "ALPS TDHU2",
.min = 54 * MHz,
.max = 864 * MHz,
.iffreq= 44000000,
.count = 4,
.entries = {
{ 162000000, 62500, 0x85, 0x01 },
{ 426000000, 62500, 0x85, 0x02 },
{ 782000000, 62500, 0x85, 0x08 },
{ 999999999, 62500, 0x85, 0x88 },
}
};
/* Samsung TBMV30111IN / TBMV30712IN1
* used in Air2PC ATSC - 2nd generation (nxt2002)
*/
static const struct dvb_pll_desc dvb_pll_samsung_tbmv = {
.name = "Samsung TBMV30111IN / TBMV30712IN1",
.min = 54 * MHz,
.max = 860 * MHz,
.iffreq= 44000000,
.count = 6,
.entries = {
{ 172000000, 166667, 0xb4, 0x01 },
{ 214000000, 166667, 0xb4, 0x02 },
{ 467000000, 166667, 0xbc, 0x02 },
{ 721000000, 166667, 0xbc, 0x08 },
{ 841000000, 166667, 0xf4, 0x08 },
{ 999999999, 166667, 0xfc, 0x02 },
}
};
/*
* Philips SD1878 Tuner.
*/
static const struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
.name = "Philips SD1878",
.min = 950 * MHz,
.max = 2150 * MHz,
.iffreq= 249, /* zero-IF, offset 249 is to round up */
.count = 4,
.entries = {
{ 1250000, 500, 0xc4, 0x00},
{ 1450000, 500, 0xc4, 0x40},
{ 2050000, 500, 0xc4, 0x80},
{ 2150000, 500, 0xc4, 0xc0},
},
};
static void opera1_bw(struct dvb_frontend *fe, u8 *buf)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_pll_priv *priv = fe->tuner_priv;
u32 b_w = (c->symbol_rate * 27) / 32000;
struct i2c_msg msg = {
.addr = priv->pll_i2c_address,
.flags = 0,
.buf = buf,
.len = 4
};
int result;
u8 lpf;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
result = i2c_transfer(priv->i2c, &msg, 1);
if (result != 1)
pr_err("%s: i2c_transfer failed:%d",
__func__, result);
if (b_w <= 10000)
lpf = 0xc;
else if (b_w <= 12000)
lpf = 0x2;
else if (b_w <= 14000)
lpf = 0xa;
else if (b_w <= 16000)
lpf = 0x6;
else if (b_w <= 18000)
lpf = 0xe;
else if (b_w <= 20000)
lpf = 0x1;
else if (b_w <= 22000)
lpf = 0x9;
else if (b_w <= 24000)
lpf = 0x5;
else if (b_w <= 26000)
lpf = 0xd;
else if (b_w <= 28000)
lpf = 0x3;
else
lpf = 0xb;
buf[2] ^= 0x1c; /* Flip bits 3-5 */
/* Set lpf */
buf[2] |= ((lpf >> 2) & 0x3) << 3;
buf[3] |= (lpf & 0x3) << 2;
return;
}
static const struct dvb_pll_desc dvb_pll_opera1 = {
.name = "Opera Tuner",
.min = 900 * MHz,
.max = 2250 * MHz,
.initdata = (u8[]){ 4, 0x08, 0xe5, 0xe1, 0x00 },
.initdata2 = (u8[]){ 4, 0x08, 0xe5, 0xe5, 0x00 },
.iffreq= 0,
.set = opera1_bw,
.count = 8,
.entries = {
{ 1064000, 500, 0xf9, 0xc2 },
{ 1169000, 500, 0xf9, 0xe2 },
{ 1299000, 500, 0xf9, 0x20 },
{ 1444000, 500, 0xf9, 0x40 },
{ 1606000, 500, 0xf9, 0x60 },
{ 1777000, 500, 0xf9, 0x80 },
{ 1941000, 500, 0xf9, 0xa0 },
{ 2250000, 500, 0xf9, 0xc0 },
}
};
static void samsung_dtos403ih102a_set(struct dvb_frontend *fe, u8 *buf)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
struct i2c_msg msg = {
.addr = priv->pll_i2c_address,
.flags = 0,
.buf = buf,
.len = 4
};
int result;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
result = i2c_transfer(priv->i2c, &msg, 1);
if (result != 1)
pr_err("%s: i2c_transfer failed:%d",
__func__, result);
buf[2] = 0x9e;
buf[3] = 0x90;
return;
}
/* unknown pll used in Samsung DTOS403IH102A DVB-C tuner */
static const struct dvb_pll_desc dvb_pll_samsung_dtos403ih102a = {
.name = "Samsung DTOS403IH102A",
.min = 44250 * kHz,
.max = 858 * MHz,
.iffreq = 36125000,
.count = 8,
.set = samsung_dtos403ih102a_set,
.entries = {
{ 135000000, 62500, 0xbe, 0x01 },
{ 177000000, 62500, 0xf6, 0x01 },
{ 370000000, 62500, 0xbe, 0x02 },
{ 450000000, 62500, 0xf6, 0x02 },
{ 466000000, 62500, 0xfe, 0x02 },
{ 538000000, 62500, 0xbe, 0x08 },
{ 826000000, 62500, 0xf6, 0x08 },
{ 999999999, 62500, 0xfe, 0x08 },
}
};
/* Samsung TDTC9251DH0 DVB-T NIM, as used on AirStar 2 */
static const struct dvb_pll_desc dvb_pll_samsung_tdtc9251dh0 = {
.name = "Samsung TDTC9251DH0",
.min = 48 * MHz,
.max = 863 * MHz,
.iffreq = 36166667,
.count = 3,
.entries = {
{ 157500000, 166667, 0xcc, 0x09 },
{ 443000000, 166667, 0xcc, 0x0a },
{ 863000000, 166667, 0xcc, 0x08 },
}
};
/* Samsung TBDU18132 DVB-S NIM with TSA5059 PLL, used in SkyStar2 DVB-S 2.3 */
static const struct dvb_pll_desc dvb_pll_samsung_tbdu18132 = {
.name = "Samsung TBDU18132",
.min = 950 * MHz,
.max = 2150 * MHz, /* guesses */
.iffreq = 0,
.count = 2,
.entries = {
{ 1550000, 125, 0x84, 0x82 },
{ 4095937, 125, 0x84, 0x80 },
}
/* TSA5059 PLL has a 17 bit divisor rather than the 15 bits supported
* by this driver. The two extra bits are 0x60 in the third byte. 15
* bits is enough for over 4 GHz, which is enough to cover the range
* of this tuner. We could use the additional divisor bits by adding
* more entries, e.g.
{ 0x0ffff * 125 + 125/2, 125, 0x84 | 0x20, },
{ 0x17fff * 125 + 125/2, 125, 0x84 | 0x40, },
{ 0x1ffff * 125 + 125/2, 125, 0x84 | 0x60, }, */
};
/* Samsung TBMU24112 DVB-S NIM with SL1935 zero-IF tuner */
static const struct dvb_pll_desc dvb_pll_samsung_tbmu24112 = {
.name = "Samsung TBMU24112",
.min = 950 * MHz,
.max = 2150 * MHz, /* guesses */
.iffreq = 0,
.count = 2,
.entries = {
{ 1500000, 125, 0x84, 0x18 },
{ 9999999, 125, 0x84, 0x08 },
}
};
/* Alps TDEE4 DVB-C NIM, used on Cablestar 2 */
/* byte 4 : 1 * * AGD R3 R2 R1 R0
* byte 5 : C1 * RE RTS BS4 BS3 BS2 BS1
* AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95
* Range(MHz) C1 * RE RTS BS4 BS3 BS2 BS1 Byte 5
* 47 - 153 0 * 0 0 0 0 0 1 0x01
* 153 - 430 0 * 0 0 0 0 1 0 0x02
* 430 - 822 0 * 0 0 1 0 0 0 0x08
* 822 - 862 1 * 0 0 1 0 0 0 0x88 */
static const struct dvb_pll_desc dvb_pll_alps_tdee4 = {
.name = "ALPS TDEE4",
.min = 47 * MHz,
.max = 862 * MHz,
.iffreq = 36125000,
.count = 4,
.entries = {
{ 153000000, 62500, 0x95, 0x01 },
{ 430000000, 62500, 0x95, 0x02 },
{ 822000000, 62500, 0x95, 0x08 },
{ 999999999, 62500, 0x95, 0x88 },
}
};
/* Infineon TUA6034 ISDB-T, used in Friio */
/* CP cur. 50uA, AGC takeover: 103dBuV, PORT3 on */
static const struct dvb_pll_desc dvb_pll_tua6034_friio = {
.name = "Infineon TUA6034 ISDB-T (Friio)",
.min = 90 * MHz,
.max = 770 * MHz,
.iffreq = 57000000,
.initdata = (u8[]){ 4, 0x9a, 0x50, 0xb2, 0x08 },
.sleepdata = (u8[]){ 4, 0x9a, 0x70, 0xb3, 0x0b },
.count = 3,
.entries = {
{ 170000000, 142857, 0xba, 0x09 },
{ 470000000, 142857, 0xba, 0x0a },
{ 770000000, 142857, 0xb2, 0x08 },
}
};
/* Philips TDA6651 ISDB-T, used in Earthsoft PT1 */
static const struct dvb_pll_desc dvb_pll_tda665x_earth_pt1 = {
.name = "Philips TDA6651 ISDB-T (EarthSoft PT1)",
.min = 90 * MHz,
.max = 770 * MHz,
.iffreq = 57000000,
.initdata = (u8[]){ 5, 0x0e, 0x7f, 0xc1, 0x80, 0x80 },
.count = 10,
.entries = {
{ 140000000, 142857, 0xc1, 0x81 },
{ 170000000, 142857, 0xc1, 0xa1 },
{ 220000000, 142857, 0xc1, 0x62 },
{ 330000000, 142857, 0xc1, 0xa2 },
{ 402000000, 142857, 0xc1, 0xe2 },
{ 450000000, 142857, 0xc1, 0x64 },
{ 550000000, 142857, 0xc1, 0x84 },
{ 600000000, 142857, 0xc1, 0xa4 },
{ 700000000, 142857, 0xc1, 0xc4 },
{ 770000000, 142857, 0xc1, 0xe4 },
}
};
/* ----------------------------------------------------------- */
static const struct dvb_pll_desc *pll_list[] = {
[DVB_PLL_UNDEFINED] = NULL,
[DVB_PLL_THOMSON_DTT7579] = &dvb_pll_thomson_dtt7579,
[DVB_PLL_THOMSON_DTT759X] = &dvb_pll_thomson_dtt759x,
[DVB_PLL_THOMSON_DTT7520X] = &dvb_pll_thomson_dtt7520x,
[DVB_PLL_LG_Z201] = &dvb_pll_lg_z201,
[DVB_PLL_UNKNOWN_1] = &dvb_pll_unknown_1,
[DVB_PLL_TUA6010XS] = &dvb_pll_tua6010xs,
[DVB_PLL_ENV57H1XD5] = &dvb_pll_env57h1xd5,
[DVB_PLL_TUA6034] = &dvb_pll_tua6034,
[DVB_PLL_TDA665X] = &dvb_pll_tda665x,
[DVB_PLL_TDED4] = &dvb_pll_tded4,
[DVB_PLL_TDEE4] = &dvb_pll_alps_tdee4,
[DVB_PLL_TDHU2] = &dvb_pll_tdhu2,
[DVB_PLL_SAMSUNG_TBMV] = &dvb_pll_samsung_tbmv,
[DVB_PLL_PHILIPS_SD1878_TDA8261] = &dvb_pll_philips_sd1878_tda8261,
[DVB_PLL_OPERA1] = &dvb_pll_opera1,
[DVB_PLL_SAMSUNG_DTOS403IH102A] = &dvb_pll_samsung_dtos403ih102a,
[DVB_PLL_SAMSUNG_TDTC9251DH0] = &dvb_pll_samsung_tdtc9251dh0,
[DVB_PLL_SAMSUNG_TBDU18132] = &dvb_pll_samsung_tbdu18132,
[DVB_PLL_SAMSUNG_TBMU24112] = &dvb_pll_samsung_tbmu24112,
[DVB_PLL_TUA6034_FRIIO] = &dvb_pll_tua6034_friio,
[DVB_PLL_TDA665X_EARTH_PT1] = &dvb_pll_tda665x_earth_pt1,
};
/* ----------------------------------------------------------- */
/* code */
static int dvb_pll_configure(struct dvb_frontend *fe, u8 *buf,
const u32 frequency)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
const struct dvb_pll_desc *desc = priv->pll_desc;
u32 div;
int i;
for (i = 0; i < desc->count; i++) {
if (frequency > desc->entries[i].limit)
continue;
break;
}
if (debug)
dprintk("pll: %s: freq=%d | i=%d/%d\n", desc->name,
frequency, i, desc->count);
if (i == desc->count)
return -EINVAL;
div = (frequency + desc->iffreq +
desc->entries[i].stepsize/2) / desc->entries[i].stepsize;
buf[0] = div >> 8;
buf[1] = div & 0xff;
buf[2] = desc->entries[i].config;
buf[3] = desc->entries[i].cb;
if (desc->set)
desc->set(fe, buf);
if (debug)
dprintk("pll: %s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n",
desc->name, div, buf[0], buf[1], buf[2], buf[3]);
// calculate the frequency we set it to
return (div * desc->entries[i].stepsize) - desc->iffreq;
}
static void dvb_pll_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int dvb_pll_sleep(struct dvb_frontend *fe)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
if (priv->i2c == NULL)
return -EINVAL;
if (priv->pll_desc->sleepdata) {
struct i2c_msg msg = { .flags = 0,
.addr = priv->pll_i2c_address,
.buf = priv->pll_desc->sleepdata + 1,
.len = priv->pll_desc->sleepdata[0] };
int result;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) {
return result;
}
return 0;
}
/* Shouldn't be called when initdata is NULL, maybe BUG()? */
return -EINVAL;
}
static int dvb_pll_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_pll_priv *priv = fe->tuner_priv;
u8 buf[4];
struct i2c_msg msg =
{ .addr = priv->pll_i2c_address, .flags = 0,
.buf = buf, .len = sizeof(buf) };
int result;
u32 frequency = 0;
if (priv->i2c == NULL)
return -EINVAL;
result = dvb_pll_configure(fe, buf, c->frequency);
if (result < 0)
return result;
else
frequency = result;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) {
return result;
}
priv->frequency = frequency;
priv->bandwidth = c->bandwidth_hz;
return 0;
}
static int dvb_pll_calc_regs(struct dvb_frontend *fe,
u8 *buf, int buf_len)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_pll_priv *priv = fe->tuner_priv;
int result;
u32 frequency = 0;
if (buf_len < 5)
return -EINVAL;
result = dvb_pll_configure(fe, buf + 1, c->frequency);
if (result < 0)
return result;
else
frequency = result;
buf[0] = priv->pll_i2c_address;
priv->frequency = frequency;
priv->bandwidth = c->bandwidth_hz;
return 5;
}
static int dvb_pll_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static int dvb_pll_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
*bandwidth = priv->bandwidth;
return 0;
}
static int dvb_pll_init(struct dvb_frontend *fe)
{
struct dvb_pll_priv *priv = fe->tuner_priv;
if (priv->i2c == NULL)
return -EINVAL;
if (priv->pll_desc->initdata) {
struct i2c_msg msg = { .flags = 0,
.addr = priv->pll_i2c_address,
.buf = priv->pll_desc->initdata + 1,
.len = priv->pll_desc->initdata[0] };
int result;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
result = i2c_transfer(priv->i2c, &msg, 1);
if (result != 1)
return result;
if (priv->pll_desc->initdata2) {
msg.buf = priv->pll_desc->initdata2 + 1;
msg.len = priv->pll_desc->initdata2[0];
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
result = i2c_transfer(priv->i2c, &msg, 1);
if (result != 1)
return result;
}
return 0;
}
/* Shouldn't be called when initdata is NULL, maybe BUG()? */
return -EINVAL;
}
static const struct dvb_tuner_ops dvb_pll_tuner_ops = {
.release = dvb_pll_release,
.sleep = dvb_pll_sleep,
.init = dvb_pll_init,
.set_params = dvb_pll_set_params,
.calc_regs = dvb_pll_calc_regs,
.get_frequency = dvb_pll_get_frequency,
.get_bandwidth = dvb_pll_get_bandwidth,
};
struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr,
struct i2c_adapter *i2c,
unsigned int pll_desc_id)
{
u8 *b1;
struct i2c_msg msg = { .addr = pll_addr, .flags = I2C_M_RD, .len = 1 };
struct dvb_pll_priv *priv = NULL;
int ret;
const struct dvb_pll_desc *desc;
int nr;
b1 = kmalloc(1, GFP_KERNEL);
if (!b1)
return NULL;
b1[0] = 0;
msg.buf = b1;
nr = ida_simple_get(&pll_ida, 0, DVB_PLL_MAX, GFP_KERNEL);
if (nr < 0) {
kfree(b1);
return NULL;
}
if (id[nr] > DVB_PLL_UNDEFINED && id[nr] < ARRAY_SIZE(pll_list))
pll_desc_id = id[nr];
BUG_ON(pll_desc_id < 1 || pll_desc_id >= ARRAY_SIZE(pll_list));
desc = pll_list[pll_desc_id];
if (i2c != NULL) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer (i2c, &msg, 1);
if (ret != 1)
goto out;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
priv = kzalloc(sizeof(struct dvb_pll_priv), GFP_KERNEL);
if (!priv)
goto out;
priv->pll_i2c_address = pll_addr;
priv->i2c = i2c;
priv->pll_desc = desc;
priv->nr = nr;
memcpy(&fe->ops.tuner_ops, &dvb_pll_tuner_ops,
sizeof(struct dvb_tuner_ops));
strscpy(fe->ops.tuner_ops.info.name, desc->name,
sizeof(fe->ops.tuner_ops.info.name));
fe->ops.tuner_ops.info.frequency_min_hz = desc->min;
fe->ops.tuner_ops.info.frequency_max_hz = desc->max;
dprintk("%s tuner, frequency range: %u...%u\n",
desc->name, desc->min, desc->max);
if (!desc->initdata)
fe->ops.tuner_ops.init = NULL;
if (!desc->sleepdata)
fe->ops.tuner_ops.sleep = NULL;
fe->tuner_priv = priv;
if ((debug) || (id[priv->nr] == pll_desc_id)) {
dprintk("dvb-pll[%d]", priv->nr);
if (i2c != NULL)
pr_cont(" %d-%04x", i2c_adapter_id(i2c), pll_addr);
pr_cont(": id# %d (%s) attached, %s\n", pll_desc_id, desc->name,
id[priv->nr] == pll_desc_id ?
"insmod option" : "autodetected");
}
kfree(b1);
return fe;
out:
kfree(b1);
ida_simple_remove(&pll_ida, nr);
return NULL;
}
EXPORT_SYMBOL_GPL(dvb_pll_attach);
static int
dvb_pll_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct dvb_pll_config *cfg;
struct dvb_frontend *fe;
unsigned int desc_id;
cfg = client->dev.platform_data;
fe = cfg->fe;
i2c_set_clientdata(client, fe);
desc_id = (unsigned int) id->driver_data;
if (!dvb_pll_attach(fe, client->addr, client->adapter, desc_id))
return -ENOMEM;
/*
* Unset tuner_ops.release (== dvb_pll_release)
* which has been just set in the above dvb_pll_attach(),
* because if tuner_ops.release was left defined,
* this module would be 'put' twice on exit:
* once by dvb_frontend_detach() and another by dvb_module_release().
*
* dvb_pll_release is instead executed in the i2c driver's .remove(),
* keeping dvb_pll_attach untouched for legacy (dvb_attach) drivers.
*/
fe->ops.tuner_ops.release = NULL;
dev_info(&client->dev, "DVB Simple Tuner attached.\n");
return 0;
}
static void dvb_pll_remove(struct i2c_client *client)
{
struct dvb_frontend *fe = i2c_get_clientdata(client);
struct dvb_pll_priv *priv = fe->tuner_priv;
ida_simple_remove(&pll_ida, priv->nr);
dvb_pll_release(fe);
}
static const struct i2c_device_id dvb_pll_id[] = {
{"dtt7579", DVB_PLL_THOMSON_DTT7579},
{"dtt759x", DVB_PLL_THOMSON_DTT759X},
{"z201", DVB_PLL_LG_Z201},
{"unknown_1", DVB_PLL_UNKNOWN_1},
{"tua6010xs", DVB_PLL_TUA6010XS},
{"env57h1xd5", DVB_PLL_ENV57H1XD5},
{"tua6034", DVB_PLL_TUA6034},
{"tda665x", DVB_PLL_TDA665X},
{"tded4", DVB_PLL_TDED4},
{"tdhu2", DVB_PLL_TDHU2},
{"tbmv", DVB_PLL_SAMSUNG_TBMV},
{"sd1878_tda8261", DVB_PLL_PHILIPS_SD1878_TDA8261},
{"opera1", DVB_PLL_OPERA1},
{"dtos403ih102a", DVB_PLL_SAMSUNG_DTOS403IH102A},
{"tdtc9251dh0", DVB_PLL_SAMSUNG_TDTC9251DH0},
{"tbdu18132", DVB_PLL_SAMSUNG_TBDU18132},
{"tbmu24112", DVB_PLL_SAMSUNG_TBMU24112},
{"tdee4", DVB_PLL_TDEE4},
{"dtt7520x", DVB_PLL_THOMSON_DTT7520X},
{"tua6034_friio", DVB_PLL_TUA6034_FRIIO},
{"tda665x_earthpt1", DVB_PLL_TDA665X_EARTH_PT1},
{}
};
MODULE_DEVICE_TABLE(i2c, dvb_pll_id);
static struct i2c_driver dvb_pll_driver = {
.driver = {
.name = "dvb_pll",
},
.probe = dvb_pll_probe,
.remove = dvb_pll_remove,
.id_table = dvb_pll_id,
};
module_i2c_driver(dvb_pll_driver);
MODULE_DESCRIPTION("dvb pll library");
MODULE_AUTHOR("Gerd Knorr");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dvb-pll.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Sony CXD2820R demodulator driver
*
* Copyright (C) 2010 Antti Palosaari <[email protected]>
*/
#include "cxd2820r_priv.h"
int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, bw_i;
unsigned int utmp;
u32 if_frequency;
u8 buf[3], bw_param;
u8 bw_params1[][5] = {
{ 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
};
struct reg_val_mask tab[] = {
{ 0x00080, 0x02, 0xff },
{ 0x00081, 0x20, 0xff },
{ 0x00085, 0x07, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x02069, 0x01, 0xff },
{ 0x0207f, 0x2a, 0xff },
{ 0x02082, 0x0a, 0xff },
{ 0x02083, 0x0a, 0xff },
{ 0x020cb, priv->if_agc_polarity << 6, 0x40 },
{ 0x02070, priv->ts_mode, 0xff },
{ 0x02071, !priv->ts_clk_inv << 6, 0x40 },
{ 0x020b5, priv->spec_inv << 4, 0x10 },
{ 0x02567, 0x07, 0x0f },
{ 0x02569, 0x03, 0x03 },
{ 0x02595, 0x1a, 0xff },
{ 0x02596, 0x50, 0xff },
{ 0x02a8c, 0x00, 0xff },
{ 0x02a8d, 0x34, 0xff },
{ 0x02a45, 0x06, 0x07 },
{ 0x03f10, 0x0d, 0xff },
{ 0x03f11, 0x02, 0xff },
{ 0x03f12, 0x01, 0xff },
{ 0x03f23, 0x2c, 0xff },
{ 0x03f51, 0x13, 0xff },
{ 0x03f52, 0x01, 0xff },
{ 0x03f53, 0x00, 0xff },
{ 0x027e6, 0x14, 0xff },
{ 0x02786, 0x02, 0x07 },
{ 0x02787, 0x40, 0xe0 },
{ 0x027ef, 0x10, 0x18 },
};
dev_dbg(&client->dev,
"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d stream_id=%u\n",
c->delivery_system, c->modulation, c->frequency,
c->bandwidth_hz, c->inversion, c->stream_id);
switch (c->bandwidth_hz) {
case 5000000:
bw_i = 0;
bw_param = 3;
break;
case 6000000:
bw_i = 1;
bw_param = 2;
break;
case 7000000:
bw_i = 2;
bw_param = 1;
break;
case 8000000:
bw_i = 3;
bw_param = 0;
break;
default:
return -EINVAL;
}
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
if (priv->delivery_system != SYS_DVBT2) {
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
}
priv->delivery_system = SYS_DVBT2;
/* program IF frequency */
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto error;
dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
} else {
ret = -EINVAL;
goto error;
}
utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
buf[0] = (utmp >> 16) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 0) & 0xff;
ret = regmap_bulk_write(priv->regmap[0], 0x20b6, buf, 3);
if (ret)
goto error;
/* PLP filtering */
if (c->stream_id > 255) {
dev_dbg(&client->dev, "disable PLP filtering\n");
ret = regmap_write(priv->regmap[0], 0x23ad, 0x00);
if (ret)
goto error;
} else {
dev_dbg(&client->dev, "enable PLP filtering\n");
ret = regmap_write(priv->regmap[0], 0x23af, c->stream_id & 0xff);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x23ad, 0x01);
if (ret)
goto error;
}
ret = regmap_bulk_write(priv->regmap[0], 0x209f, bw_params1[bw_i], 5);
if (ret)
goto error;
ret = regmap_update_bits(priv->regmap[0], 0x20d7, 0xc0, bw_param << 6);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
unsigned int utmp;
u8 buf[2];
dev_dbg(&client->dev, "\n");
ret = regmap_bulk_read(priv->regmap[0], 0x205c, buf, 2);
if (ret)
goto error;
switch ((buf[0] >> 0) & 0x07) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
case 2:
c->transmission_mode = TRANSMISSION_MODE_4K;
break;
case 3:
c->transmission_mode = TRANSMISSION_MODE_1K;
break;
case 4:
c->transmission_mode = TRANSMISSION_MODE_16K;
break;
case 5:
c->transmission_mode = TRANSMISSION_MODE_32K;
break;
}
switch ((buf[1] >> 4) & 0x07) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
case 4:
c->guard_interval = GUARD_INTERVAL_1_128;
break;
case 5:
c->guard_interval = GUARD_INTERVAL_19_128;
break;
case 6:
c->guard_interval = GUARD_INTERVAL_19_256;
break;
}
ret = regmap_bulk_read(priv->regmap[0], 0x225b, buf, 2);
if (ret)
goto error;
switch ((buf[0] >> 0) & 0x07) {
case 0:
c->fec_inner = FEC_1_2;
break;
case 1:
c->fec_inner = FEC_3_5;
break;
case 2:
c->fec_inner = FEC_2_3;
break;
case 3:
c->fec_inner = FEC_3_4;
break;
case 4:
c->fec_inner = FEC_4_5;
break;
case 5:
c->fec_inner = FEC_5_6;
break;
}
switch ((buf[1] >> 0) & 0x07) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
case 3:
c->modulation = QAM_256;
break;
}
ret = regmap_read(priv->regmap[0], 0x20b5, &utmp);
if (ret)
goto error;
switch ((utmp >> 4) & 0x01) {
case 0:
c->inversion = INVERSION_OFF;
break;
case 1:
c->inversion = INVERSION_ON;
break;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_read_status_t2(struct dvb_frontend *fe, enum fe_status *status)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct i2c_client *client = priv->client[0];
int ret;
unsigned int utmp, utmp1, utmp2;
u8 buf[4];
/* Lock detection */
ret = regmap_bulk_read(priv->regmap[0], 0x2010, &buf[0], 1);
if (ret)
goto error;
utmp1 = (buf[0] >> 0) & 0x07;
utmp2 = (buf[0] >> 5) & 0x01;
if (utmp1 == 6 && utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else if (utmp1 == 6 || utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC;
} else {
*status = 0;
}
dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
*status, 1, buf, utmp1, utmp2);
/* Signal strength */
if (*status & FE_HAS_SIGNAL) {
unsigned int strength;
ret = regmap_bulk_read(priv->regmap[0], 0x2026, buf, 2);
if (ret)
goto error;
utmp = buf[0] << 8 | buf[1] << 0;
utmp = ~utmp & 0x0fff;
/* Scale value to 0x0000-0xffff */
strength = utmp << 4 | utmp >> 8;
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = strength;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (*status & FE_HAS_VITERBI) {
unsigned int cnr;
ret = regmap_bulk_read(priv->regmap[0], 0x2028, buf, 2);
if (ret)
goto error;
utmp = buf[0] << 8 | buf[1] << 0;
utmp = utmp & 0x0fff;
#define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
if (utmp)
cnr = div_u64((u64)(intlog10(utmp)
- CXD2820R_LOG10_8_24) * 10000,
(1 << 24));
else
cnr = 0;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (*status & FE_HAS_SYNC) {
unsigned int post_bit_error;
ret = regmap_bulk_read(priv->regmap[0], 0x2039, buf, 4);
if (ret)
goto error;
if ((buf[0] >> 4) & 0x01) {
post_bit_error = buf[0] << 24 | buf[1] << 16 |
buf[2] << 8 | buf[3] << 0;
post_bit_error &= 0x0fffffff;
} else {
post_bit_error = 0;
}
priv->post_bit_error += post_bit_error;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
} else {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_sleep_t2(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
static const struct reg_val_mask tab[] = {
{ 0x000ff, 0x1f, 0xff },
{ 0x00085, 0x00, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x02069, 0x00, 0xff },
{ 0x00081, 0x00, 0xff },
{ 0x00080, 0x00, 0xff },
};
dev_dbg(&client->dev, "\n");
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
priv->delivery_system = SYS_UNDEFINED;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 1500;
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2820r_t2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
STB0899 Multistandard Frontend driver
Copyright (C) Manu Abraham ([email protected])
Copyright (C) ST Microelectronics
*/
#include <linux/bitops.h>
#include "stb0899_drv.h"
#include "stb0899_priv.h"
#include "stb0899_reg.h"
static inline u32 stb0899_do_div(u64 n, u32 d)
{
/* wrap do_div() for ease of use */
do_div(n, d);
return n;
}
#if 0
/* These functions are currently unused */
/*
* stb0899_calc_srate
* Compute symbol rate
*/
static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
{
u64 tmp;
/* srate = (SFR * master_clk) >> 20 */
/* sfr is of size 20 bit, stored with an offset of 4 bit */
tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
tmp &= ~0xf;
tmp *= master_clk;
tmp >>= 24;
return tmp;
}
/*
* stb0899_get_srate
* Get the current symbol rate
*/
static u32 stb0899_get_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u8 sfr[3];
stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
return stb0899_calc_srate(internal->master_clk, sfr);
}
#endif
/*
* stb0899_set_srate
* Set symbol frequency
* MasterClock: master clock frequency (hz)
* SymbolRate: symbol rate (bauds)
* return symbol frequency
*/
static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
{
u32 tmp;
u8 sfr[3];
dprintk(state->verbose, FE_DEBUG, 1, "-->");
/*
* in order to have the maximum precision, the symbol rate entered into
* the chip is computed as the closest value of the "true value".
* In this purpose, the symbol rate value is rounded (1 is added on the bit
* below the LSB )
*
* srate = (SFR * master_clk) >> 20
* <=>
* SFR = srate << 20 / master_clk
*
* rounded:
* SFR = (srate << 21 + master_clk) / (2 * master_clk)
*
* stored as 20 bit number with an offset of 4 bit:
* sfr = SFR << 4;
*/
tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
tmp <<= 4;
sfr[0] = tmp >> 16;
sfr[1] = tmp >> 8;
sfr[2] = tmp;
stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
return srate;
}
/*
* stb0899_calc_derot_time
* Compute the amount of time needed by the derotator to lock
* SymbolRate: Symbol rate
* return: derotator time constant (ms)
*/
static long stb0899_calc_derot_time(long srate)
{
if (srate > 0)
return (100000 / (srate / 1000));
else
return 0;
}
/*
* stb0899_carr_width
* Compute the width of the carrier
* return: width of carrier (kHz or Mhz)
*/
long stb0899_carr_width(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
return (internal->srate + (internal->srate * internal->rolloff) / 100);
}
/*
* stb0899_first_subrange
* Compute the first subrange of the search
*/
static void stb0899_first_subrange(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
struct stb0899_config *config = state->config;
int range = 0;
u32 bandwidth = 0;
if (config->tuner_get_bandwidth) {
stb0899_i2c_gate_ctrl(&state->frontend, 1);
config->tuner_get_bandwidth(&state->frontend, &bandwidth);
stb0899_i2c_gate_ctrl(&state->frontend, 0);
range = bandwidth - stb0899_carr_width(state) / 2;
}
if (range > 0)
internal->sub_range = min(internal->srch_range, range);
else
internal->sub_range = 0;
internal->freq = params->freq;
internal->tuner_offst = 0L;
internal->sub_dir = 1;
}
/*
* stb0899_check_tmg
* check for timing lock
* internal.Ttiming: time to wait for loop lock
*/
static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
int lock;
u8 reg;
s8 timing;
msleep(internal->t_derot);
stb0899_write_reg(state, STB0899_RTF, 0xf2);
reg = stb0899_read_reg(state, STB0899_TLIR);
lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
timing = stb0899_read_reg(state, STB0899_RTF);
if (lock >= 42) {
if ((lock > 48) && (abs(timing) >= 110)) {
internal->status = ANALOGCARRIER;
dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
} else {
internal->status = TIMINGOK;
dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
}
} else {
internal->status = NOTIMING;
dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
}
return internal->status;
}
/*
* stb0899_search_tmg
* perform a fs/2 zig-zag to find timing
*/
static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
int index = 0;
u8 cfr[2];
internal->status = NOTIMING;
/* timing loop computation & symbol rate optimisation */
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_step = (params->srate / 2L) / internal->mclk;
while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
index++;
derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
}
internal->direction = -internal->direction; /* Change zigzag direction */
}
if (internal->status == TIMINGOK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
}
return internal->status;
}
/*
* stb0899_check_carrier
* Check for carrier found
*/
static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u8 reg;
msleep(internal->t_derot); /* wait for derotator ok */
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
reg = stb0899_read_reg(state, STB0899_DSTATUS);
dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
internal->status = CARRIEROK;
dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
} else {
internal->status = NOCARRIER;
dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
}
return internal->status;
}
/*
* stb0899_search_carrier
* Search for a QPSK carrier with the derotator
*/
static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
int index = 0;
u8 cfr[2];
u8 reg;
internal->status = NOCARRIER;
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_freq = internal->derot_freq;
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
do {
dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
if (stb0899_check_carrier(state) == NOCARRIER) {
index++;
last_derot_freq = derot_freq;
derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
if(abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
}
}
internal->direction = -internal->direction; /* Change zigzag direction */
} while ((internal->status != CARRIEROK) && next_loop);
if (internal->status == CARRIEROK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
} else {
internal->derot_freq = last_derot_freq;
}
return internal->status;
}
/*
* stb0899_check_data
* Check for data found
*/
static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
int lock = 0, index = 0, dataTime = 500, loop;
u8 reg;
internal->status = NODATA;
/* RESET FEC */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESACS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
msleep(1);
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESACS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
if (params->srate <= 2000000)
dataTime = 2000;
else if (params->srate <= 5000000)
dataTime = 1500;
else if (params->srate <= 15000000)
dataTime = 1000;
else
dataTime = 500;
/* clear previous failed END_LOOPVIT */
stb0899_read_reg(state, STB0899_VSTATUS);
stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
while (1) {
/* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
reg = stb0899_read_reg(state, STB0899_VSTATUS);
lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
if (lock || loop || (index > dataTime))
break;
index++;
}
if (lock) { /* DATA LOCK indicator */
internal->status = DATAOK;
dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
}
return internal->status;
}
/*
* stb0899_search_data
* Search for a QPSK carrier with the derotator
*/
static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
{
short int derot_freq, derot_step, derot_limit, next_loop = 3;
u8 cfr[2];
u8 reg;
int index = 1;
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
derot_step = (params->srate / 4L) / internal->mclk;
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_freq = internal->derot_freq;
do {
if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
stb0899_check_carrier(state);
index++;
}
}
internal->direction = -internal->direction; /* change zig zag direction */
} while ((internal->status != DATAOK) && next_loop);
if (internal->status == DATAOK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
/* store autodetected IQ swapping as default for DVB-S2 tuning */
reg = stb0899_read_reg(state, STB0899_IQSWAP);
if (STB0899_GETFIELD(SYM, reg))
internal->inversion = IQ_SWAP_ON;
else
internal->inversion = IQ_SWAP_OFF;
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
}
return internal->status;
}
/*
* stb0899_check_range
* check if the found frequency is in the correct range
*/
static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
int range_offst, tp_freq;
range_offst = internal->srch_range / 2000;
tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
internal->status = RANGEOK;
dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
} else {
internal->status = OUTOFRANGE;
dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
}
return internal->status;
}
/*
* NextSubRange
* Compute the next subrange of the search
*/
static void next_sub_range(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
long old_sub_range;
if (internal->sub_dir > 0) {
old_sub_range = internal->sub_range;
internal->sub_range = min((internal->srch_range / 2) -
(internal->tuner_offst + internal->sub_range / 2),
internal->sub_range);
if (internal->sub_range < 0)
internal->sub_range = 0;
internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
}
internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
internal->sub_dir = -internal->sub_dir;
}
/*
* stb0899_dvbs_algo
* Search for a signal, timing, carrier and data for a
* given frequency in a given range
*/
enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
{
struct stb0899_params *params = &state->params;
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u8 bclc, reg;
u8 cfr[2];
u8 eq_const[10];
s32 clnI = 3;
u32 bandwidth = 0;
/* BETA values rated @ 99MHz */
s32 betaTab[5][4] = {
/* 5 10 20 30MBps */
{ 37, 34, 32, 31 }, /* QPSK 1/2 */
{ 37, 35, 33, 31 }, /* QPSK 2/3 */
{ 37, 35, 33, 31 }, /* QPSK 3/4 */
{ 37, 36, 33, 32 }, /* QPSK 5/6 */
{ 37, 36, 33, 32 } /* QPSK 7/8 */
};
internal->direction = 1;
stb0899_set_srate(state, internal->master_clk, params->srate);
/* Carrier loop optimization versus symbol rate for acquisition*/
if (params->srate <= 5000000) {
stb0899_write_reg(state, STB0899_ACLC, 0x89);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 0;
} else if (params->srate <= 15000000) {
stb0899_write_reg(state, STB0899_ACLC, 0xc9);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 1;
} else if(params->srate <= 25000000) {
stb0899_write_reg(state, STB0899_ACLC, 0x89);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 2;
} else {
stb0899_write_reg(state, STB0899_ACLC, 0xc8);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 3;
}
dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
/* Set the timing loop to acquisition */
stb0899_write_reg(state, STB0899_RTC, 0x46);
stb0899_write_reg(state, STB0899_CFD, 0xee);
/* !! WARNING !!
* Do not read any status variables while acquisition,
* If any needed, read before the acquisition starts
* querying status while acquiring causes the
* acquisition to go bad and hence no locks.
*/
dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
internal->derot_percent, params->srate, internal->mclk);
/* Initial calculations */
internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
internal->t_derot = stb0899_calc_derot_time(params->srate);
internal->t_data = 500;
dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
/* RESET Stream merger */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/*
* Set KDIVIDER to an intermediate value between
* 1/2 and 7/8 for acquisition
*/
reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
stb0899_first_subrange(state);
do {
/* Initialisations */
cfr[0] = cfr[1] = 0;
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
stb0899_write_reg(state, STB0899_RTF, 0);
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
internal->derot_freq = 0;
internal->status = NOAGC1;
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
/* Move tuner to frequency */
dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
if (state->config->tuner_set_frequency)
state->config->tuner_set_frequency(&state->frontend, internal->freq);
if (state->config->tuner_get_frequency)
state->config->tuner_get_frequency(&state->frontend, &internal->freq);
msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
internal->status = AGC1OK;
/* There is signal in the band */
if (config->tuner_get_bandwidth)
config->tuner_get_bandwidth(&state->frontend, &bandwidth);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
if (params->srate <= bandwidth / 2)
stb0899_search_tmg(state); /* For low rates (SCPC) */
else
stb0899_check_tmg(state); /* For high rates (MCPC) */
if (internal->status == TIMINGOK) {
dprintk(state->verbose, FE_DEBUG, 1,
"TIMING OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
dprintk(state->verbose, FE_DEBUG, 1,
"CARRIER OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_search_data(state) == DATAOK) { /* Check for data */
dprintk(state->verbose, FE_DEBUG, 1,
"DATA OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_check_range(state) == RANGEOK) {
dprintk(state->verbose, FE_DEBUG, 1,
"RANGE OK ! derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
reg = stb0899_read_reg(state, STB0899_PLPARM);
internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
dprintk(state->verbose, FE_DEBUG, 1,
"freq=%d, internal resultant freq=%d",
params->freq, internal->freq);
dprintk(state->verbose, FE_DEBUG, 1,
"internal puncture rate=%d",
internal->fecrate);
}
}
}
}
if (internal->status != RANGEOK)
next_sub_range(state);
} while (internal->sub_range && internal->status != RANGEOK);
/* Set the timing loop to tracking */
stb0899_write_reg(state, STB0899_RTC, 0x33);
stb0899_write_reg(state, STB0899_CFD, 0xf7);
/* if locked and range ok, set Kdiv */
if (internal->status == RANGEOK) {
dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
/*
* Carrier loop optimization versus
* symbol Rate/Puncture Rate for Tracking
*/
reg = stb0899_read_reg(state, STB0899_BCLC);
switch (internal->fecrate) {
case STB0899_FEC_1_2: /* 13 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_2_3: /* 18 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_3_4: /* 21 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_5_6: /* 24 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_6_7: /* 25 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
stb0899_write_reg(state, STB0899_ACLC, 0x88);
stb0899_write_reg(state, STB0899_BCLC, 0x9a);
break;
case STB0899_FEC_7_8: /* 26 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
break;
}
/* release stream merger RESET */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/* disable carrier detector */
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
}
return internal->status;
}
/*
* stb0899_dvbs2_config_uwp
* Configure UWP state machine
*/
static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 uwp1, uwp2, uwp3, reg;
uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
}
/*
* stb0899_dvbs2_config_csm_auto
* Set CSM to AUTO mode
*/
static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
{
u32 reg;
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
}
static long Log2Int(int number)
{
int i;
i = 0;
while ((1 << i) <= abs(number))
i++;
if (number == 0)
i = 1;
return i - 1;
}
/*
* stb0899_dvbs2_calc_srate
* compute BTR_NOM_FREQ for the symbol rate
*/
static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
u32 master_clk, srate;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
decim = 1 << dec_rate;
master_clk = internal->master_clk / 1000;
srate = internal->srate / 1000;
if (decim <= 4) {
intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
} else {
intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
}
btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
return btr_nom_freq;
}
/*
* stb0899_dvbs2_calc_dev
* compute the correction to be applied to symbol rate
*/
static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u32 dec_ratio, correction, master_clk, srate;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
master_clk = internal->master_clk / 1000; /* for integer Calculation*/
srate = internal->srate / 1000; /* for integer Calculation*/
correction = (512 * master_clk) / (2 * dec_ratio * srate);
return correction;
}
/*
* stb0899_dvbs2_set_srate
* Set DVBS2 symbol rate
*/
static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
u32 correction, freq_adj, band_lim, decim_cntrl, reg;
u8 anti_alias;
/*set decimation to 1*/
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
win_sel = 0;
if (dec_rate >= 5)
win_sel = dec_rate - 4;
decim = (1 << dec_rate);
/* (FSamp/Fsymbol *100) for integer Calculation */
f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
if (f_sym <= 2250) /* don't band limit signal going into btr block*/
band_lim = 1;
else
band_lim = 0; /* band limit signal going into btr block*/
decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
if (f_sym <= 3450)
anti_alias = 0;
else if (f_sym <= 4250)
anti_alias = 1;
else
anti_alias = 2;
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
btr_nom_freq = stb0899_dvbs2_calc_srate(state);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
correction = stb0899_dvbs2_calc_dev(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
/* scale UWP+CSM frequency to sample rate*/
freq_adj = internal->srate / (internal->master_clk / 4096);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
}
/*
* stb0899_dvbs2_set_btr_loopbw
* set bit timing loop bandwidth as a percentage of the symbol rate
*/
static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
u32 decim, K, wn, k_direct, k_indirect;
u32 reg;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
decim = (1 << dec_rate);
sym_peak *= 576000;
K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
if (K != 0) {
K = sym_peak / K;
wn = (4 * zeta * zeta) + 1000000;
wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
k_indirect = (wn * wn) / K; /*kindirect = kindirect 10^-6*/
k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
k_direct *= 100;
k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
k_btr1 = k_direct / (1 << k_direct_shift);
k_btr1 /= 10000;
k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
k_btr0 = k_indirect * (1 << (-k_indirect_shift));
k_btr0 /= 1000000;
k_btr2_rshft = 0;
if (k_btr0_rshft > 15) {
k_btr2_rshft = k_btr0_rshft - 15;
k_btr0_rshft = 15;
}
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
} else
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
}
/*
* stb0899_dvbs2_set_carr_freq
* set nominal frequency for carrier search
*/
static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
{
struct stb0899_config *config = state->config;
s32 crl_nom_freq;
u32 reg;
crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
crl_nom_freq *= carr_freq;
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
}
/*
* stb0899_dvbs2_init_calc
* Initialize DVBS2 UWP, CSM, carrier and timing loops
*/
static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
s32 steps, step_size;
u32 range, reg;
/* config uwp and csm */
stb0899_dvbs2_config_uwp(state);
stb0899_dvbs2_config_csm_auto(state);
/* initialize BTR */
stb0899_dvbs2_set_srate(state);
stb0899_dvbs2_set_btr_loopbw(state);
if (internal->srate / 1000000 >= 15)
step_size = (1 << 17) / 5;
else if (internal->srate / 1000000 >= 10)
step_size = (1 << 17) / 7;
else if (internal->srate / 1000000 >= 5)
step_size = (1 << 17) / 10;
else
step_size = (1 << 17) / 4;
range = internal->srch_range / 1000000;
steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
steps = (steps + 6) / 10;
steps = (steps == 0) ? 1 : steps;
if (steps % 2 == 0)
stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
(internal->step_size * (internal->srate / 20000000)),
(internal->master_clk) / 1000000);
else
stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
/*Set Carrier Search params (zigzag, num steps and freq step size*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
}
/*
* stb0899_dvbs2_btr_init
* initialize the timing loop
*/
static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
{
u32 reg;
/* set enable BTR loopback */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
/* fix btr freq accum at 0 */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
/* fix btr freq accum at 0 */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
}
/*
* stb0899_dvbs2_reacquire
* trigger a DVB-S2 acquisition
*/
static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
{
u32 reg = 0;
/* demod soft reset */
STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
/*Reset Timing Loop */
stb0899_dvbs2_btr_init(state);
/* reset Carrier loop */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
/*release demod soft reset */
reg = 0;
STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
/* start acquisition process */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
/* equalizer Init */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
/*Start equilizer */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
/* RESET Packet delineator */
stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
}
/*
* stb0899_dvbs2_get_dmd_status
* get DVB-S2 Demod LOCK status
*/
static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
{
int time = -10, lock = 0, uwp, csm;
u32 reg;
do {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
uwp = STB0899_GETFIELD(UWP_LOCK, reg);
csm = STB0899_GETFIELD(CSM_LOCK, reg);
if (uwp && csm)
lock = 1;
time += 10;
msleep(10);
} while ((!lock) && (time <= timeout));
if (lock) {
dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
return DVBS2_DEMOD_LOCK;
} else {
return DVBS2_DEMOD_NOLOCK;
}
}
/*
* stb0899_dvbs2_get_data_lock
* get FEC status
*/
static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
{
int time = 0, lock = 0;
u8 reg;
while ((!lock) && (time < timeout)) {
reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
time++;
}
return lock;
}
/*
* stb0899_dvbs2_get_fec_status
* get DVB-S2 FEC LOCK status
*/
static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
{
int time = 0, Locked;
do {
Locked = stb0899_dvbs2_get_data_lock(state, 1);
time++;
msleep(1);
} while ((!Locked) && (time < timeout));
if (Locked) {
dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
return DVBS2_FEC_LOCK;
} else {
return DVBS2_FEC_NOLOCK;
}
}
/*
* stb0899_dvbs2_init_csm
* set parameters for manual mode
*/
static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
{
struct stb0899_internal *internal = &state->internal;
s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
u32 csm1, csm2, csm3, csm4;
if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
switch (modcod) {
case STB0899_QPSK_12:
gamma_acq = 25;
gamma_rho_acq = 2700;
gamma_trk = 12;
gamma_rho_trk = 180;
lock_count_thr = 8;
break;
case STB0899_QPSK_35:
gamma_acq = 38;
gamma_rho_acq = 7182;
gamma_trk = 14;
gamma_rho_trk = 308;
lock_count_thr = 8;
break;
case STB0899_QPSK_23:
gamma_acq = 42;
gamma_rho_acq = 9408;
gamma_trk = 17;
gamma_rho_trk = 476;
lock_count_thr = 8;
break;
case STB0899_QPSK_34:
gamma_acq = 53;
gamma_rho_acq = 16642;
gamma_trk = 19;
gamma_rho_trk = 646;
lock_count_thr = 8;
break;
case STB0899_QPSK_45:
gamma_acq = 53;
gamma_rho_acq = 17119;
gamma_trk = 22;
gamma_rho_trk = 880;
lock_count_thr = 8;
break;
case STB0899_QPSK_56:
gamma_acq = 55;
gamma_rho_acq = 19250;
gamma_trk = 23;
gamma_rho_trk = 989;
lock_count_thr = 8;
break;
case STB0899_QPSK_89:
gamma_acq = 60;
gamma_rho_acq = 24240;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
case STB0899_QPSK_910:
gamma_acq = 66;
gamma_rho_acq = 29634;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
default:
gamma_acq = 66;
gamma_rho_acq = 29634;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
}
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
}
}
/*
* stb0899_dvbs2_get_srate
* get DVB-S2 Symbol Rate
*/
static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
int div1, div2, rem1, rem2;
div1 = config->btr_nco_bits / 2;
div2 = config->btr_nco_bits - div1 - 1;
bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
decimRate = (1 << decimRate);
intval1 = internal->master_clk / (1 << div1);
intval2 = bTrNomFreq / (1 << div2);
rem1 = internal->master_clk % (1 << div1);
rem2 = bTrNomFreq % (1 << div2);
/* only for integer calculation */
srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
return srate;
}
/*
* stb0899_dvbs2_algo
* Search for signal, timing, carrier and data for a given
* frequency in a given range
*/
enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
enum stb0899_modcod modcod;
s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
int i = 0;
u32 reg, csm1;
if (internal->srate <= 2000000) {
searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
} else if (internal->srate <= 5000000) {
searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
} else if (internal->srate <= 10000000) {
searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
} else if (internal->srate <= 15000000) {
searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
} else if (internal->srate <= 20000000) {
searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
} else if (internal->srate <= 25000000) {
searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
} else {
searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
}
/* Maintain Stream Merger in reset during acquisition */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
/* Move tuner to frequency */
if (state->config->tuner_set_frequency)
state->config->tuner_set_frequency(&state->frontend, internal->freq);
if (state->config->tuner_get_frequency)
state->config->tuner_get_frequency(&state->frontend, &internal->freq);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
/* Set IF AGC to acquisition */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
/* Initialisation */
stb0899_dvbs2_init_calc(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
switch (internal->inversion) {
case IQ_SWAP_OFF:
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
break;
case IQ_SWAP_ON:
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
break;
}
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
stb0899_dvbs2_reacquire(state);
/* Wait for demod lock (UWP and CSM) */
internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
if (internal->status == DVBS2_DEMOD_LOCK) {
dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
i = 0;
/* Demod Locked, check FEC status */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
/*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
/* Read the frequency offset*/
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
/* Set the Nominal frequency to the found frequency offset for the next reacquire*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
stb0899_dvbs2_reacquire(state);
internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
i++;
}
}
if (internal->status != DVBS2_FEC_LOCK) {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
/* IQ Spectrum Inversion */
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
/* start acquistion process */
stb0899_dvbs2_reacquire(state);
/* Wait for demod lock (UWP and CSM) */
internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
if (internal->status == DVBS2_DEMOD_LOCK) {
i = 0;
/* Demod Locked, check FEC */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
/*try thrice for false locks, (UWP and CSM Locked but no FEC) */
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
/* Read the frequency offset*/
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
/* Set the Nominal frequency to the found frequency offset for the next reacquire*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
stb0899_dvbs2_reacquire(state);
internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
i++;
}
}
/*
if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
pParams->IQLocked = !iqSpectrum;
*/
}
if (internal->status == DVBS2_FEC_LOCK) {
dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
(INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
(pilots == 1)) {
stb0899_dvbs2_init_csm(state, pilots, modcod);
/* Wait for UWP,CSM and data LOCK 20ms max */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
i = 0;
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
i++;
}
}
if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
(INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
(pilots == 1)) {
/* Equalizer Disable update */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
}
/* slow down the Equalizer once locked */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
/* Store signal parameters */
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
offsetfreq = sign_extend32(offsetfreq, 29);
offsetfreq = offsetfreq / ((1 << 30) / 1000);
offsetfreq *= (internal->master_clk / 1000000);
/* store current inversion for next run */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
internal->inversion = IQ_SWAP_ON;
else
internal->inversion = IQ_SWAP_OFF;
internal->freq = internal->freq + offsetfreq;
internal->srate = stb0899_dvbs2_get_srate(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
/* Set IF AGC to tracking */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
/* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
}
/* Release Stream Merger Reset */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
return internal->status;
}
| linux-master | drivers/media/dvb-frontends/stb0899_algo.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the MaxLinear MxL5xx family of tuners/demods
*
* Copyright (C) 2014-2015 Ralph Metzler <[email protected]>
* Marcus Metzler <[email protected]>
* developed for Digital Devices GmbH
*
* based on code:
* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
* which was released under GPL V2
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/vmalloc.h>
#include <asm/div64.h>
#include <asm/unaligned.h>
#include <media/dvb_frontend.h>
#include "mxl5xx.h"
#include "mxl5xx_regs.h"
#include "mxl5xx_defs.h"
#define BYTE0(v) ((v >> 0) & 0xff)
#define BYTE1(v) ((v >> 8) & 0xff)
#define BYTE2(v) ((v >> 16) & 0xff)
#define BYTE3(v) ((v >> 24) & 0xff)
static LIST_HEAD(mxllist);
struct mxl_base {
struct list_head mxllist;
struct list_head mxls;
u8 adr;
struct i2c_adapter *i2c;
u32 count;
u32 type;
u32 sku_type;
u32 chipversion;
u32 clock;
u32 fwversion;
u8 *ts_map;
u8 can_clkout;
u8 chan_bond;
u8 demod_num;
u8 tuner_num;
unsigned long next_tune;
struct mutex i2c_lock;
struct mutex status_lock;
struct mutex tune_lock;
u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
u32 cmd_size;
u8 cmd_data[MAX_CMD_DATA];
};
struct mxl {
struct list_head mxl;
struct mxl_base *base;
struct dvb_frontend fe;
struct device *i2cdev;
u32 demod;
u32 tuner;
u32 tuner_in_use;
u8 xbar[3];
unsigned long tune_time;
};
static void convert_endian(u8 flag, u32 size, u8 *d)
{
u32 i;
if (!flag)
return;
for (i = 0; i < (size & ~3); i += 4) {
d[i + 0] ^= d[i + 3];
d[i + 3] ^= d[i + 0];
d[i + 0] ^= d[i + 3];
d[i + 1] ^= d[i + 2];
d[i + 2] ^= d[i + 1];
d[i + 1] ^= d[i + 2];
}
switch (size & 3) {
case 0:
case 1:
/* do nothing */
break;
case 2:
d[i + 0] ^= d[i + 1];
d[i + 1] ^= d[i + 0];
d[i + 0] ^= d[i + 1];
break;
case 3:
d[i + 0] ^= d[i + 2];
d[i + 2] ^= d[i + 0];
d[i + 0] ^= d[i + 2];
break;
}
}
static int i2c_write(struct i2c_adapter *adap, u8 adr,
u8 *data, u32 len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
}
static int i2c_read(struct i2c_adapter *adap, u8 adr,
u8 *data, u32 len)
{
struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
.buf = data, .len = len};
return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
}
static int i2cread(struct mxl *state, u8 *data, int len)
{
return i2c_read(state->base->i2c, state->base->adr, data, len);
}
static int i2cwrite(struct mxl *state, u8 *data, int len)
{
return i2c_write(state->base->i2c, state->base->adr, data, len);
}
static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
{
int stat;
u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
MXL_HYDRA_PLID_REG_READ, 0x04,
GET_BYTE(reg, 0), GET_BYTE(reg, 1),
GET_BYTE(reg, 2), GET_BYTE(reg, 3),
};
stat = i2cwrite(state, data,
MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
if (stat)
dev_err(state->i2cdev, "i2c read error 1\n");
if (!stat)
stat = i2cread(state, (u8 *) val,
MXL_HYDRA_REG_SIZE_IN_BYTES);
le32_to_cpus(val);
if (stat)
dev_err(state->i2cdev, "i2c read error 2\n");
return stat;
}
#define DMA_I2C_INTERRUPT_ADDR 0x8000011C
#define DMA_INTR_PROT_WR_CMP 0x08
static int send_command(struct mxl *state, u32 size, u8 *buf)
{
int stat;
u32 val, count = 10;
mutex_lock(&state->base->i2c_lock);
if (state->base->fwversion > 0x02010109) {
read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
if (DMA_INTR_PROT_WR_CMP & val)
dev_info(state->i2cdev, "%s busy\n", __func__);
while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
mutex_unlock(&state->base->i2c_lock);
usleep_range(1000, 2000);
mutex_lock(&state->base->i2c_lock);
read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
&val);
}
if (!count) {
dev_info(state->i2cdev, "%s busy\n", __func__);
mutex_unlock(&state->base->i2c_lock);
return -EBUSY;
}
}
stat = i2cwrite(state, buf, size);
mutex_unlock(&state->base->i2c_lock);
return stat;
}
static int write_register(struct mxl *state, u32 reg, u32 val)
{
int stat;
u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
MXL_HYDRA_PLID_REG_WRITE, 0x08,
BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
};
mutex_lock(&state->base->i2c_lock);
stat = i2cwrite(state, data, sizeof(data));
mutex_unlock(&state->base->i2c_lock);
if (stat)
dev_err(state->i2cdev, "i2c write error\n");
return stat;
}
static int write_firmware_block(struct mxl *state,
u32 reg, u32 size, u8 *reg_data_ptr)
{
int stat;
u8 *buf = state->base->buf;
mutex_lock(&state->base->i2c_lock);
buf[0] = MXL_HYDRA_PLID_REG_WRITE;
buf[1] = size + 4;
buf[2] = GET_BYTE(reg, 0);
buf[3] = GET_BYTE(reg, 1);
buf[4] = GET_BYTE(reg, 2);
buf[5] = GET_BYTE(reg, 3);
memcpy(&buf[6], reg_data_ptr, size);
stat = i2cwrite(state, buf,
MXL_HYDRA_I2C_HDR_SIZE +
MXL_HYDRA_REG_SIZE_IN_BYTES + size);
mutex_unlock(&state->base->i2c_lock);
if (stat)
dev_err(state->i2cdev, "fw block write failed\n");
return stat;
}
static int read_register(struct mxl *state, u32 reg, u32 *val)
{
int stat;
u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
MXL_HYDRA_PLID_REG_READ, 0x04,
GET_BYTE(reg, 0), GET_BYTE(reg, 1),
GET_BYTE(reg, 2), GET_BYTE(reg, 3),
};
mutex_lock(&state->base->i2c_lock);
stat = i2cwrite(state, data,
MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
if (stat)
dev_err(state->i2cdev, "i2c read error 1\n");
if (!stat)
stat = i2cread(state, (u8 *) val,
MXL_HYDRA_REG_SIZE_IN_BYTES);
mutex_unlock(&state->base->i2c_lock);
le32_to_cpus(val);
if (stat)
dev_err(state->i2cdev, "i2c read error 2\n");
return stat;
}
static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
{
int stat;
u8 *buf = state->base->buf;
mutex_lock(&state->base->i2c_lock);
buf[0] = MXL_HYDRA_PLID_REG_READ;
buf[1] = size + 4;
buf[2] = GET_BYTE(reg, 0);
buf[3] = GET_BYTE(reg, 1);
buf[4] = GET_BYTE(reg, 2);
buf[5] = GET_BYTE(reg, 3);
stat = i2cwrite(state, buf,
MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
if (!stat) {
stat = i2cread(state, data, size);
convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
}
mutex_unlock(&state->base->i2c_lock);
return stat;
}
static int read_by_mnemonic(struct mxl *state,
u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
{
u32 data = 0, mask = 0;
int stat;
stat = read_register(state, reg, &data);
if (stat)
return stat;
mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
data &= mask;
data >>= lsbloc;
*val = data;
return 0;
}
static int update_by_mnemonic(struct mxl *state,
u32 reg, u8 lsbloc, u8 numofbits, u32 val)
{
u32 data, mask;
int stat;
stat = read_register(state, reg, &data);
if (stat)
return stat;
mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
data = (data & ~mask) | ((val << lsbloc) & mask);
stat = write_register(state, reg, data);
return stat;
}
static int firmware_is_alive(struct mxl *state)
{
u32 hb0, hb1;
if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
return 0;
msleep(20);
if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
return 0;
if (hb1 == hb0)
return 0;
return 1;
}
static int init(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
/* init fe stats */
p->strength.len = 1;
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.len = 1;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.len = 1;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.len = 1;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.len = 1;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.len = 1;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
static void release(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
list_del(&state->mxl);
/* Release one frontend, two more shall take its place! */
state->base->count--;
if (state->base->count == 0) {
list_del(&state->base->mxllist);
kfree(state->base);
}
kfree(state);
}
static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static u32 gold2root(u32 gold)
{
u32 x, g, tmp = gold;
if (tmp >= 0x3ffff)
tmp = 0;
for (g = 0, x = 1; g < tmp; g++)
x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1);
return x;
}
static int cfg_scrambler(struct mxl *state, u32 gold)
{
u32 root;
u8 buf[26] = {
MXL_HYDRA_PLID_CMD_WRITE, 24,
0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0,
state->demod, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 0, 0,
};
root = gold2root(gold);
buf[25] = (root >> 24) & 0xff;
buf[24] = (root >> 16) & 0xff;
buf[23] = (root >> 8) & 0xff;
buf[22] = root & 0xff;
return send_command(state, sizeof(buf), buf);
}
static int cfg_demod_abort_tune(struct mxl *state)
{
struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
u8 cmd_size = sizeof(abort_tune_cmd);
u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
abort_tune_cmd.demod_id = state->demod;
BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
cmd_size, &abort_tune_cmd, cmd_buff);
return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
&cmd_buff[0]);
}
static int send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
/*struct mxl *state = fe->demodulator_priv;*/
return 0; /*CfgDemodAbortTune(state);*/
}
static int set_parameters(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
u8 cmd_size = sizeof(demod_chan_cfg);
u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
u32 srange = 10;
int stat;
if (p->frequency < 950000 || p->frequency > 2150000)
return -EINVAL;
if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
return -EINVAL;
/* CfgDemodAbortTune(state); */
switch (p->delivery_system) {
case SYS_DSS:
demod_chan_cfg.standard = MXL_HYDRA_DSS;
demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
break;
case SYS_DVBS:
srange = p->symbol_rate / 1000000;
if (srange > 10)
srange = 10;
demod_chan_cfg.standard = MXL_HYDRA_DVBS;
demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
break;
case SYS_DVBS2:
demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
cfg_scrambler(state, p->scrambling_sequence_index);
break;
default:
return -EINVAL;
}
demod_chan_cfg.tuner_index = state->tuner;
demod_chan_cfg.demod_index = state->demod;
demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
demod_chan_cfg.max_carrier_offset_in_mhz = srange;
demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
mutex_lock(&state->base->tune_lock);
if (time_after(jiffies + msecs_to_jiffies(200),
state->base->next_tune))
while (time_before(jiffies, state->base->next_tune))
usleep_range(10000, 11000);
state->base->next_tune = jiffies + msecs_to_jiffies(100);
state->tuner_in_use = state->tuner;
BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
cmd_size, &demod_chan_cfg, cmd_buff);
stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
&cmd_buff[0]);
mutex_unlock(&state->base->tune_lock);
return stat;
}
static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
static int sleep(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
struct mxl *p;
cfg_demod_abort_tune(state);
if (state->tuner_in_use != 0xffffffff) {
mutex_lock(&state->base->tune_lock);
state->tuner_in_use = 0xffffffff;
list_for_each_entry(p, &state->base->mxls, mxl) {
if (p->tuner_in_use == state->tuner)
break;
}
if (&p->mxl == &state->base->mxls)
enable_tuner(state, state->tuner, 0);
mutex_unlock(&state->base->tune_lock);
}
return 0;
}
static int read_snr(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
int stat;
u32 reg_data = 0;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
®_data);
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
mutex_unlock(&state->base->status_lock);
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = (s16)reg_data * 10;
return stat;
}
static int read_ber(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 reg[8];
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
read_register_block(state,
(HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
(4 * sizeof(u32)),
(u8 *) ®[0]);
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
switch (p->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_error.stat[0].uvalue = reg[2];
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_count.stat[0].uvalue = reg[3];
break;
default:
break;
}
read_register_block(state,
(HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
(7 * sizeof(u32)),
(u8 *) ®[0]);
switch (p->delivery_system) {
case SYS_DSS:
case SYS_DVBS:
p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_error.stat[0].uvalue = reg[5];
p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_count.stat[0].uvalue = reg[6];
break;
case SYS_DVBS2:
p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_error.stat[0].uvalue = reg[1];
p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_count.stat[0].uvalue = reg[2];
break;
default:
break;
}
mutex_unlock(&state->base->status_lock);
return 0;
}
static int read_signal_strength(struct dvb_frontend *fe)
{
struct mxl *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int stat;
u32 reg_data = 0;
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
®_data);
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
mutex_unlock(&state->base->status_lock);
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
return stat;
}
static int read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct mxl *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 reg_data = 0;
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
®_data);
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
mutex_unlock(&state->base->status_lock);
*status = (reg_data == 1) ? 0x1f : 0;
/* signal statistics */
/* signal strength is always available */
read_signal_strength(fe);
if (*status & FE_HAS_CARRIER)
read_snr(fe);
else
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (*status & FE_HAS_SYNC)
read_ber(fe);
else {
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags,
unsigned int *delay, enum fe_status *status)
{
struct mxl *state = fe->demodulator_priv;
int r = 0;
*delay = HZ / 2;
if (re_tune) {
r = set_parameters(fe);
if (r)
return r;
state->tune_time = jiffies;
}
return read_status(fe, status);
}
static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
{
enum fe_code_rate fec2fec[11] = {
FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
FEC_7_8, FEC_8_9, FEC_9_10
};
if (fec > MXL_HYDRA_FEC_9_10)
return FEC_NONE;
return fec2fec[fec];
}
static int get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct mxl *state = fe->demodulator_priv;
u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
u32 freq;
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
read_register_block(state,
(HYDRA_DMD_STANDARD_ADDR_OFFSET +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
(MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
(u8 *) ®_data[0]);
/* read demod channel parameters */
read_register_block(state,
(HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
HYDRA_DMD_STATUS_OFFSET(state->demod)),
(4), /* 4 bytes */
(u8 *) &freq);
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
mutex_unlock(&state->base->status_lock);
dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
freq * 1000, reg_data[DMD_STANDARD_ADDR],
reg_data[DMD_SYMBOL_RATE_ADDR]);
p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
p->frequency = freq;
/*
* p->delivery_system =
* (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
* p->inversion =
* (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
* freqSearchRangeKHz =
* (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
*/
p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
switch (p->delivery_system) {
case SYS_DSS:
break;
case SYS_DVBS2:
switch ((enum MXL_HYDRA_PILOTS_E)
reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
case MXL_HYDRA_PILOTS_OFF:
p->pilot = PILOT_OFF;
break;
case MXL_HYDRA_PILOTS_ON:
p->pilot = PILOT_ON;
break;
default:
break;
}
fallthrough;
case SYS_DVBS:
switch ((enum MXL_HYDRA_MODULATION_E)
reg_data[DMD_MODULATION_SCHEME_ADDR]) {
case MXL_HYDRA_MOD_QPSK:
p->modulation = QPSK;
break;
case MXL_HYDRA_MOD_8PSK:
p->modulation = PSK_8;
break;
default:
break;
}
switch ((enum MXL_HYDRA_ROLLOFF_E)
reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
case MXL_HYDRA_ROLLOFF_0_20:
p->rolloff = ROLLOFF_20;
break;
case MXL_HYDRA_ROLLOFF_0_35:
p->rolloff = ROLLOFF_35;
break;
case MXL_HYDRA_ROLLOFF_0_25:
p->rolloff = ROLLOFF_25;
break;
default:
break;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int set_input(struct dvb_frontend *fe, int input)
{
struct mxl *state = fe->demodulator_priv;
state->tuner = input;
return 0;
}
static const struct dvb_frontend_ops mxl_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
.info = {
.name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
.frequency_min_hz = 300 * MHz,
.frequency_max_hz = 2350 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_2G_MODULATION
},
.init = init,
.release = release,
.get_frontend_algo = get_algo,
.tune = tune,
.read_status = read_status,
.sleep = sleep,
.get_frontend = get_frontend,
.diseqc_send_master_cmd = send_master_cmd,
};
static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr)
{
struct mxl_base *p;
list_for_each_entry(p, &mxllist, mxllist)
if (p->i2c == i2c && p->adr == adr)
return p;
return NULL;
}
static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
{
if (state->base->can_clkout || !enable)
update_by_mnemonic(state, 0x90200054, 23, 1, enable);
if (freq == 24000000)
write_register(state, HYDRA_CRYSTAL_SETTING, 0);
else
write_register(state, HYDRA_CRYSTAL_SETTING, 1);
write_register(state, HYDRA_CRYSTAL_CAP, cap);
}
static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
{
u32 ret_value = 0;
switch (num_of_bits) {
case 24:
ret_value = (((u32) buf[0]) << 16) |
(((u32) buf[1]) << 8) | buf[2];
break;
case 32:
ret_value = (((u32) buf[0]) << 24) |
(((u32) buf[1]) << 16) |
(((u32) buf[2]) << 8) | buf[3];
break;
default:
break;
}
return ret_value;
}
static int write_fw_segment(struct mxl *state,
u32 mem_addr, u32 total_size, u8 *data_ptr)
{
int status;
u32 data_count = 0;
u32 size = 0;
u32 orig_size = 0;
u8 *w_buf_ptr = NULL;
u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
(MXL_HYDRA_I2C_HDR_SIZE +
MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
(MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
do {
size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
(total_size - data_count) : block_size;
if (orig_size & 3)
size = (orig_size + 4) & ~3;
w_buf_ptr = &w_msg_buffer[0];
memset((void *) w_buf_ptr, 0, size);
memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
convert_endian(1, size, w_buf_ptr);
status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
if (status)
return status;
data_count += size;
mem_addr += size;
data_ptr += size;
} while (data_count < total_size);
return status;
}
static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
u32 mbin_buffer_size)
{
int status;
u32 index = 0;
u32 seg_length = 0;
u32 seg_address = 0;
struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr;
struct MBIN_SEGMENT_T *segment_ptr;
enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
__func__, mbin_ptr->header.id);
return -EINVAL;
}
status = write_register(state, FW_DL_SIGN_ADDR, 0);
if (status)
return status;
segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
for (index = 0; index < mbin_ptr->header.num_segments; index++) {
if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
__func__, segment_ptr->header.id);
return -EINVAL;
}
seg_length = get_big_endian(24,
&(segment_ptr->header.len24[0]));
seg_address = get_big_endian(32,
&(segment_ptr->header.address[0]));
if (state->base->type == MXL_HYDRA_DEVICE_568) {
if ((((seg_address & 0x90760000) == 0x90760000) ||
((seg_address & 0x90740000) == 0x90740000)) &&
(xcpu_fw_flag == MXL_FALSE)) {
update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
msleep(200);
write_register(state, 0x90720000, 0);
usleep_range(10000, 11000);
xcpu_fw_flag = MXL_TRUE;
}
status = write_fw_segment(state, seg_address,
seg_length,
(u8 *) segment_ptr->data);
} else {
if (((seg_address & 0x90760000) != 0x90760000) &&
((seg_address & 0x90740000) != 0x90740000))
status = write_fw_segment(state, seg_address,
seg_length, (u8 *) segment_ptr->data);
}
if (status)
return status;
segment_ptr = (struct MBIN_SEGMENT_T *)
&(segment_ptr->data[((seg_length + 3) / 4) * 4]);
}
return status;
}
static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
{
struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
u32 flen = (fh->image_size24[0] << 16) |
(fh->image_size24[1] << 8) | fh->image_size24[2];
u8 *fw, cs = 0;
u32 i;
if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
dev_info(state->i2cdev, "Invalid FW Header\n");
return -1;
}
fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
for (i = 0; i < flen; i += 1)
cs += fw[i];
if (cs != fh->image_checksum) {
dev_info(state->i2cdev, "Invalid FW Checksum\n");
return -1;
}
return 0;
}
static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
{
int status;
u32 reg_data = 0;
struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
if (check_fw(state, mbin, mbin_len))
return -1;
/* put CPU into reset */
status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
if (status)
return status;
usleep_range(1000, 2000);
/* Reset TX FIFO's, BBAND, XBAR */
status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
HYDRA_RESET_TRANSPORT_FIFO_DATA);
if (status)
return status;
status = write_register(state, HYDRA_RESET_BBAND_REG,
HYDRA_RESET_BBAND_DATA);
if (status)
return status;
status = write_register(state, HYDRA_RESET_XBAR_REG,
HYDRA_RESET_XBAR_DATA);
if (status)
return status;
/* Disable clock to Baseband, Wideband, SerDes,
* Alias ext & Transport modules
*/
status = write_register(state, HYDRA_MODULES_CLK_2_REG,
HYDRA_DISABLE_CLK_2);
if (status)
return status;
/* Clear Software & Host interrupt status - (Clear on read) */
status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data);
if (status)
return status;
status = do_firmware_download(state, mbin, mbin_len);
if (status)
return status;
if (state->base->type == MXL_HYDRA_DEVICE_568) {
usleep_range(10000, 11000);
/* bring XCPU out of reset */
status = write_register(state, 0x90720000, 1);
if (status)
return status;
msleep(500);
/* Enable XCPU UART message processing in MCPU */
status = write_register(state, 0x9076B510, 1);
if (status)
return status;
} else {
/* Bring CPU out of reset */
status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
if (status)
return status;
/* Wait until FW boots */
msleep(150);
}
/* Initialize XPT XBAR */
status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
if (status)
return status;
if (!firmware_is_alive(state))
return -1;
dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
/* sometimes register values are wrong shortly
* after first heart beats
*/
msleep(50);
dev_sku_cfg.sku_type = state->base->sku_type;
BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
cmd_size, &dev_sku_cfg, cmd_buff);
status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
&cmd_buff[0]);
return status;
}
static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
{
int status = 0;
u32 pad_mux_value = 0;
if (enable_serial_ts == MXL_TRUE) {
pad_mux_value = 0;
if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
(state->base->type == MXL_HYDRA_DEVICE_541S))
pad_mux_value = 2;
} else {
if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
(state->base->type == MXL_HYDRA_DEVICE_581S))
pad_mux_value = 2;
else
pad_mux_value = 3;
}
switch (state->base->type) {
case MXL_HYDRA_DEVICE_561:
case MXL_HYDRA_DEVICE_581:
case MXL_HYDRA_DEVICE_541:
case MXL_HYDRA_DEVICE_541S:
case MXL_HYDRA_DEVICE_561S:
case MXL_HYDRA_DEVICE_581S:
status |= update_by_mnemonic(state, 0x90000170, 24, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000170, 28, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 0, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 4, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 8, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 12, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 16, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 20, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 24, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000174, 28, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000178, 0, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000178, 4, 3,
pad_mux_value);
status |= update_by_mnemonic(state, 0x90000178, 8, 3,
pad_mux_value);
break;
case MXL_HYDRA_DEVICE_544:
case MXL_HYDRA_DEVICE_542:
status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
if (enable_serial_ts == MXL_ENABLE) {
status |= update_by_mnemonic(state,
0x90000170, 4, 3, 0);
status |= update_by_mnemonic(state,
0x90000170, 8, 3, 0);
status |= update_by_mnemonic(state,
0x90000170, 12, 3, 0);
status |= update_by_mnemonic(state,
0x90000170, 16, 3, 0);
status |= update_by_mnemonic(state,
0x90000170, 20, 3, 1);
status |= update_by_mnemonic(state,
0x90000170, 24, 3, 1);
status |= update_by_mnemonic(state,
0x90000170, 28, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 0, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 4, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 8, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 12, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 16, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 20, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 24, 3, 2);
status |= update_by_mnemonic(state,
0x90000174, 28, 3, 2);
status |= update_by_mnemonic(state,
0x90000178, 0, 3, 2);
status |= update_by_mnemonic(state,
0x90000178, 4, 3, 2);
status |= update_by_mnemonic(state,
0x90000178, 8, 3, 2);
} else {
status |= update_by_mnemonic(state,
0x90000170, 4, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 8, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 12, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 16, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 20, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 24, 3, 3);
status |= update_by_mnemonic(state,
0x90000170, 28, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 0, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 4, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 8, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 12, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 16, 3, 3);
status |= update_by_mnemonic(state,
0x90000174, 20, 3, 1);
status |= update_by_mnemonic(state,
0x90000174, 24, 3, 1);
status |= update_by_mnemonic(state,
0x90000174, 28, 3, 1);
status |= update_by_mnemonic(state,
0x90000178, 0, 3, 1);
status |= update_by_mnemonic(state,
0x90000178, 4, 3, 1);
status |= update_by_mnemonic(state,
0x90000178, 8, 3, 1);
}
break;
case MXL_HYDRA_DEVICE_568:
if (enable_serial_ts == MXL_FALSE) {
status |= update_by_mnemonic(state,
0x9000016C, 8, 3, 5);
status |= update_by_mnemonic(state,
0x9000016C, 12, 3, 5);
status |= update_by_mnemonic(state,
0x9000016C, 16, 3, 5);
status |= update_by_mnemonic(state,
0x9000016C, 20, 3, 5);
status |= update_by_mnemonic(state,
0x9000016C, 24, 3, 5);
status |= update_by_mnemonic(state,
0x9000016C, 28, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 0, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 4, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 8, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 12, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 16, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 20, 3, 5);
status |= update_by_mnemonic(state,
0x90000170, 24, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 0, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 8, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 12, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 16, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 20, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 24, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 28, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000178, 0, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000178, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000178, 8, 3, 5);
status |= update_by_mnemonic(state,
0x90000178, 12, 3, 5);
status |= update_by_mnemonic(state,
0x90000178, 16, 3, 5);
status |= update_by_mnemonic(state,
0x90000178, 20, 3, 5);
status |= update_by_mnemonic(state,
0x90000178, 24, 3, 5);
status |= update_by_mnemonic(state,
0x90000178, 28, 3, 5);
status |= update_by_mnemonic(state,
0x9000017C, 0, 3, 5);
status |= update_by_mnemonic(state,
0x9000017C, 4, 3, 5);
} else {
status |= update_by_mnemonic(state,
0x90000170, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 8, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 12, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 16, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 20, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 24, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 28, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 0, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 8, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 12, 3, pad_mux_value);
}
break;
case MXL_HYDRA_DEVICE_584:
default:
status |= update_by_mnemonic(state,
0x90000170, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 8, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 12, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 16, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 20, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 24, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000170, 28, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 0, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 4, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 8, 3, pad_mux_value);
status |= update_by_mnemonic(state,
0x90000174, 12, 3, pad_mux_value);
break;
}
return status;
}
static int set_drive_strength(struct mxl *state,
enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
{
int stat = 0;
u32 val;
read_register(state, 0x90000194, &val);
dev_info(state->i2cdev, "DIGIO = %08x\n", val);
dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
return stat;
}
static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
{
int stat = 0;
struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
u8 cmd_size = sizeof(ctrl_tuner_cmd);
u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
u32 val, count = 10;
ctrl_tuner_cmd.tuner_id = tuner;
ctrl_tuner_cmd.enable = enable;
BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
cmd_size, &ctrl_tuner_cmd, cmd_buff);
stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
&cmd_buff[0]);
if (stat)
return stat;
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
while (--count && ((val >> tuner) & 1) != enable) {
msleep(20);
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
}
if (!count)
return -1;
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
tuner, (val >> tuner) & 1);
return 0;
}
static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
{
int status = 0;
u32 nco_count_min = 0;
u32 clk_type = 0;
struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
{0x90700010, 8, 1}, {0x90700010, 9, 1},
{0x90700010, 10, 1}, {0x90700010, 11, 1},
{0x90700010, 12, 1}, {0x90700010, 13, 1},
{0x90700010, 14, 1}, {0x90700010, 15, 1} };
struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
{0x90700010, 16, 1}, {0x90700010, 17, 1},
{0x90700010, 18, 1}, {0x90700010, 19, 1},
{0x90700010, 20, 1}, {0x90700010, 21, 1},
{0x90700010, 22, 1}, {0x90700010, 23, 1} };
struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
{0x90700014, 0, 1}, {0x90700014, 1, 1},
{0x90700014, 2, 1}, {0x90700014, 3, 1},
{0x90700014, 4, 1}, {0x90700014, 5, 1},
{0x90700014, 6, 1}, {0x90700014, 7, 1} };
struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
{0x90700018, 0, 3}, {0x90700018, 4, 3},
{0x90700018, 8, 3}, {0x90700018, 12, 3},
{0x90700018, 16, 3}, {0x90700018, 20, 3},
{0x90700018, 24, 3}, {0x90700018, 28, 3} };
struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
{0x9070000C, 16, 1}, {0x9070000C, 17, 1},
{0x9070000C, 18, 1}, {0x9070000C, 19, 1},
{0x9070000C, 20, 1}, {0x9070000C, 21, 1},
{0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
{0x90700010, 0, 1}, {0x90700010, 1, 1},
{0x90700010, 2, 1}, {0x90700010, 3, 1},
{0x90700010, 4, 1}, {0x90700010, 5, 1},
{0x90700010, 6, 1}, {0x90700010, 7, 1} };
struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
{0x9070000C, 0, 1}, {0x9070000C, 1, 1},
{0x9070000C, 2, 1}, {0x9070000C, 3, 1},
{0x9070000C, 4, 1}, {0x9070000C, 5, 1},
{0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
{0x9070000C, 24, 1}, {0x9070000C, 25, 1},
{0x9070000C, 26, 1}, {0x9070000C, 27, 1},
{0x9070000C, 28, 1}, {0x9070000C, 29, 1},
{0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
{0x90700014, 8, 1}, {0x90700014, 9, 1},
{0x90700014, 10, 1}, {0x90700014, 11, 1},
{0x90700014, 12, 1}, {0x90700014, 13, 1},
{0x90700014, 14, 1}, {0x90700014, 15, 1} };
struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
{0x907001D4, 0, 1}, {0x907001D4, 1, 1},
{0x907001D4, 2, 1}, {0x907001D4, 3, 1},
{0x907001D4, 4, 1}, {0x907001D4, 5, 1},
{0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
{0x90700044, 16, 80}, {0x90700044, 16, 81},
{0x90700044, 16, 82}, {0x90700044, 16, 83},
{0x90700044, 16, 84}, {0x90700044, 16, 85},
{0x90700044, 16, 86}, {0x90700044, 16, 87} };
demod_id = state->base->ts_map[demod_id];
if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
if (mpeg_out_param_ptr->mpeg_mode ==
MXL_HYDRA_MPEG_MODE_PARALLEL) {
} else {
cfg_ts_pad_mux(state, MXL_TRUE);
update_by_mnemonic(state,
0x90700010, 27, 1, MXL_FALSE);
}
}
nco_count_min =
(u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
if (state->base->chipversion >= 2) {
status |= update_by_mnemonic(state,
xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
nco_count_min); /* Data */
} else
update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
clk_type = 1;
if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
status |= update_by_mnemonic(state,
xpt_continuous_clock[demod_id].reg_addr,
xpt_continuous_clock[demod_id].lsb_pos,
xpt_continuous_clock[demod_id].num_of_bits,
clk_type);
} else
update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
status |= update_by_mnemonic(state,
xpt_sync_polarity[demod_id].reg_addr,
xpt_sync_polarity[demod_id].lsb_pos,
xpt_sync_polarity[demod_id].num_of_bits,
mpeg_out_param_ptr->mpeg_sync_pol);
status |= update_by_mnemonic(state,
xpt_valid_polarity[demod_id].reg_addr,
xpt_valid_polarity[demod_id].lsb_pos,
xpt_valid_polarity[demod_id].num_of_bits,
mpeg_out_param_ptr->mpeg_valid_pol);
status |= update_by_mnemonic(state,
xpt_clock_polarity[demod_id].reg_addr,
xpt_clock_polarity[demod_id].lsb_pos,
xpt_clock_polarity[demod_id].num_of_bits,
mpeg_out_param_ptr->mpeg_clk_pol);
status |= update_by_mnemonic(state,
xpt_sync_byte[demod_id].reg_addr,
xpt_sync_byte[demod_id].lsb_pos,
xpt_sync_byte[demod_id].num_of_bits,
mpeg_out_param_ptr->mpeg_sync_pulse_width);
status |= update_by_mnemonic(state,
xpt_ts_clock_phase[demod_id].reg_addr,
xpt_ts_clock_phase[demod_id].lsb_pos,
xpt_ts_clock_phase[demod_id].num_of_bits,
mpeg_out_param_ptr->mpeg_clk_phase);
status |= update_by_mnemonic(state,
xpt_lsb_first[demod_id].reg_addr,
xpt_lsb_first[demod_id].lsb_pos,
xpt_lsb_first[demod_id].num_of_bits,
mpeg_out_param_ptr->lsb_or_msb_first);
switch (mpeg_out_param_ptr->mpeg_error_indication) {
case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
status |= update_by_mnemonic(state,
xpt_err_replace_sync[demod_id].reg_addr,
xpt_err_replace_sync[demod_id].lsb_pos,
xpt_err_replace_sync[demod_id].num_of_bits,
MXL_TRUE);
status |= update_by_mnemonic(state,
xpt_err_replace_valid[demod_id].reg_addr,
xpt_err_replace_valid[demod_id].lsb_pos,
xpt_err_replace_valid[demod_id].num_of_bits,
MXL_FALSE);
break;
case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
status |= update_by_mnemonic(state,
xpt_err_replace_sync[demod_id].reg_addr,
xpt_err_replace_sync[demod_id].lsb_pos,
xpt_err_replace_sync[demod_id].num_of_bits,
MXL_FALSE);
status |= update_by_mnemonic(state,
xpt_err_replace_valid[demod_id].reg_addr,
xpt_err_replace_valid[demod_id].lsb_pos,
xpt_err_replace_valid[demod_id].num_of_bits,
MXL_TRUE);
break;
case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
default:
status |= update_by_mnemonic(state,
xpt_err_replace_sync[demod_id].reg_addr,
xpt_err_replace_sync[demod_id].lsb_pos,
xpt_err_replace_sync[demod_id].num_of_bits,
MXL_FALSE);
status |= update_by_mnemonic(state,
xpt_err_replace_valid[demod_id].reg_addr,
xpt_err_replace_valid[demod_id].lsb_pos,
xpt_err_replace_valid[demod_id].num_of_bits,
MXL_FALSE);
break;
}
if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
status |= update_by_mnemonic(state,
xpt_enable_output[demod_id].reg_addr,
xpt_enable_output[demod_id].lsb_pos,
xpt_enable_output[demod_id].num_of_bits,
mpeg_out_param_ptr->enable);
}
return status;
}
static int config_mux(struct mxl *state)
{
update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
update_by_mnemonic(state, 0x90700008, 0, 2, 1);
update_by_mnemonic(state, 0x90700008, 2, 2, 1);
return 0;
}
static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
{
int stat = 0;
u8 *buf;
if (cfg->fw)
return firmware_download(state, cfg->fw, cfg->fw_len);
if (!cfg->fw_read)
return -1;
buf = vmalloc(0x40000);
if (!buf)
return -ENOMEM;
cfg->fw_read(cfg->fw_priv, buf, 0x40000);
stat = firmware_download(state, buf, 0x40000);
vfree(buf);
return stat;
}
static int validate_sku(struct mxl *state)
{
u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
int status;
u32 type = state->base->type;
status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
if (status)
return -1;
dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
pad_mux_bond, prcm_chip_id, prcm_so_cid);
if (prcm_chip_id != 0x560) {
switch (pad_mux_bond) {
case MXL_HYDRA_SKU_ID_581:
if (type == MXL_HYDRA_DEVICE_581)
return 0;
if (type == MXL_HYDRA_DEVICE_581S) {
state->base->type = MXL_HYDRA_DEVICE_581;
return 0;
}
break;
case MXL_HYDRA_SKU_ID_584:
if (type == MXL_HYDRA_DEVICE_584)
return 0;
break;
case MXL_HYDRA_SKU_ID_544:
if (type == MXL_HYDRA_DEVICE_544)
return 0;
if (type == MXL_HYDRA_DEVICE_542)
return 0;
break;
case MXL_HYDRA_SKU_ID_582:
if (type == MXL_HYDRA_DEVICE_582)
return 0;
break;
default:
return -1;
}
}
return -1;
}
static int get_fwinfo(struct mxl *state)
{
int status;
u32 val = 0;
status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
if (status)
return status;
dev_info(state->i2cdev, "chipID=%08x\n", val);
status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
if (status)
return status;
dev_info(state->i2cdev, "chipVer=%08x\n", val);
status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
if (status)
return status;
dev_info(state->i2cdev, "FWVer=%08x\n", val);
state->base->fwversion = val;
return status;
}
static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
MXL_HYDRA_DEMOD_ID_0,
MXL_HYDRA_DEMOD_ID_1,
MXL_HYDRA_DEMOD_ID_2,
MXL_HYDRA_DEMOD_ID_3,
MXL_HYDRA_DEMOD_ID_4,
MXL_HYDRA_DEMOD_ID_5,
MXL_HYDRA_DEMOD_ID_6,
MXL_HYDRA_DEMOD_ID_7,
};
static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
MXL_HYDRA_DEMOD_ID_2,
MXL_HYDRA_DEMOD_ID_3,
MXL_HYDRA_DEMOD_ID_4,
MXL_HYDRA_DEMOD_ID_5,
MXL_HYDRA_DEMOD_MAX,
MXL_HYDRA_DEMOD_MAX,
MXL_HYDRA_DEMOD_MAX,
MXL_HYDRA_DEMOD_MAX,
};
static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
{
u32 chipver;
int fw, status, j;
struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
state->base->ts_map = ts_map1_to_1;
switch (state->base->type) {
case MXL_HYDRA_DEVICE_581:
case MXL_HYDRA_DEVICE_581S:
state->base->can_clkout = 1;
state->base->demod_num = 8;
state->base->tuner_num = 1;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
break;
case MXL_HYDRA_DEVICE_582:
state->base->can_clkout = 1;
state->base->demod_num = 8;
state->base->tuner_num = 3;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
break;
case MXL_HYDRA_DEVICE_585:
state->base->can_clkout = 0;
state->base->demod_num = 8;
state->base->tuner_num = 4;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
break;
case MXL_HYDRA_DEVICE_544:
state->base->can_clkout = 0;
state->base->demod_num = 4;
state->base->tuner_num = 4;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
state->base->ts_map = ts_map54x;
break;
case MXL_HYDRA_DEVICE_541:
case MXL_HYDRA_DEVICE_541S:
state->base->can_clkout = 0;
state->base->demod_num = 4;
state->base->tuner_num = 1;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
state->base->ts_map = ts_map54x;
break;
case MXL_HYDRA_DEVICE_561:
case MXL_HYDRA_DEVICE_561S:
state->base->can_clkout = 0;
state->base->demod_num = 6;
state->base->tuner_num = 1;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
break;
case MXL_HYDRA_DEVICE_568:
state->base->can_clkout = 0;
state->base->demod_num = 8;
state->base->tuner_num = 1;
state->base->chan_bond = 1;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
break;
case MXL_HYDRA_DEVICE_542:
state->base->can_clkout = 1;
state->base->demod_num = 4;
state->base->tuner_num = 3;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
state->base->ts_map = ts_map54x;
break;
case MXL_HYDRA_DEVICE_TEST:
case MXL_HYDRA_DEVICE_584:
default:
state->base->can_clkout = 0;
state->base->demod_num = 8;
state->base->tuner_num = 4;
state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
break;
}
status = validate_sku(state);
if (status)
return status;
update_by_mnemonic(state, 0x80030014, 9, 1, 1);
update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
if (status)
state->base->chipversion = 0;
else
state->base->chipversion = (chipver == 2) ? 2 : 1;
dev_info(state->i2cdev, "Hydra chip version %u\n",
state->base->chipversion);
cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
fw = firmware_is_alive(state);
if (!fw) {
status = load_fw(state, cfg);
if (status)
return status;
}
get_fwinfo(state);
config_mux(state);
mpeg_interface_cfg.enable = MXL_ENABLE;
mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
/* supports only (0-104&139)MHz */
if (cfg->ts_clk)
mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
else
mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
/* MXL_HYDRA_MPEG_CLK_GAPPED; */
mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
mpeg_interface_cfg.mpeg_error_indication =
MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
for (j = 0; j < state->base->demod_num; j++) {
status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
&mpeg_interface_cfg);
if (status)
return status;
}
set_drive_strength(state, 1);
return 0;
}
struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
int (**fn_set_input)(struct dvb_frontend *, int))
{
struct mxl *state;
struct mxl_base *base;
state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
if (!state)
return NULL;
state->demod = demod;
state->tuner = tuner;
state->tuner_in_use = 0xffffffff;
state->i2cdev = &i2c->dev;
base = match_base(i2c, cfg->adr);
if (base) {
base->count++;
if (base->count > base->demod_num)
goto fail;
state->base = base;
} else {
base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
if (!base)
goto fail;
base->i2c = i2c;
base->adr = cfg->adr;
base->type = cfg->type;
base->count = 1;
mutex_init(&base->i2c_lock);
mutex_init(&base->status_lock);
mutex_init(&base->tune_lock);
INIT_LIST_HEAD(&base->mxls);
state->base = base;
if (probe(state, cfg) < 0) {
kfree(base);
goto fail;
}
list_add(&base->mxllist, &mxllist);
}
state->fe.ops = mxl_ops;
state->xbar[0] = 4;
state->xbar[1] = demod;
state->xbar[2] = 8;
state->fe.demodulator_priv = state;
*fn_set_input = set_input;
list_add(&state->mxl, &base->mxls);
return &state->fe;
fail:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(mxl5xx_attach);
MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/mxl5xx.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the ST STV6111 tuner
*
* Copyright (C) 2014 Digital Devices GmbH
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <asm/div64.h>
#include "stv6111.h"
#include <media/dvb_frontend.h>
struct stv {
struct i2c_adapter *i2c;
u8 adr;
u8 reg[11];
u32 ref_freq;
u32 frequency;
};
struct slookup {
s16 value;
u16 reg_value;
};
static const struct slookup lnagain_nf_lookup[] = {
/* Gain *100dB // Reg */
{ 2572, 0 },
{ 2575, 1 },
{ 2580, 2 },
{ 2588, 3 },
{ 2596, 4 },
{ 2611, 5 },
{ 2633, 6 },
{ 2664, 7 },
{ 2701, 8 },
{ 2753, 9 },
{ 2816, 10 },
{ 2902, 11 },
{ 2995, 12 },
{ 3104, 13 },
{ 3215, 14 },
{ 3337, 15 },
{ 3492, 16 },
{ 3614, 17 },
{ 3731, 18 },
{ 3861, 19 },
{ 3988, 20 },
{ 4124, 21 },
{ 4253, 22 },
{ 4386, 23 },
{ 4505, 24 },
{ 4623, 25 },
{ 4726, 26 },
{ 4821, 27 },
{ 4903, 28 },
{ 4979, 29 },
{ 5045, 30 },
{ 5102, 31 }
};
static const struct slookup lnagain_iip3_lookup[] = {
/* Gain *100dB // reg */
{ 1548, 0 },
{ 1552, 1 },
{ 1569, 2 },
{ 1565, 3 },
{ 1577, 4 },
{ 1594, 5 },
{ 1627, 6 },
{ 1656, 7 },
{ 1700, 8 },
{ 1748, 9 },
{ 1805, 10 },
{ 1896, 11 },
{ 1995, 12 },
{ 2113, 13 },
{ 2233, 14 },
{ 2366, 15 },
{ 2543, 16 },
{ 2687, 17 },
{ 2842, 18 },
{ 2999, 19 },
{ 3167, 20 },
{ 3342, 21 },
{ 3507, 22 },
{ 3679, 23 },
{ 3827, 24 },
{ 3970, 25 },
{ 4094, 26 },
{ 4210, 27 },
{ 4308, 28 },
{ 4396, 29 },
{ 4468, 30 },
{ 4535, 31 }
};
static const struct slookup gain_rfagc_lookup[] = {
/* Gain *100dB // reg */
{ 4870, 0x3000 },
{ 4850, 0x3C00 },
{ 4800, 0x4500 },
{ 4750, 0x4800 },
{ 4700, 0x4B00 },
{ 4650, 0x4D00 },
{ 4600, 0x4F00 },
{ 4550, 0x5100 },
{ 4500, 0x5200 },
{ 4420, 0x5500 },
{ 4316, 0x5800 },
{ 4200, 0x5B00 },
{ 4119, 0x5D00 },
{ 3999, 0x6000 },
{ 3950, 0x6100 },
{ 3876, 0x6300 },
{ 3755, 0x6600 },
{ 3641, 0x6900 },
{ 3567, 0x6B00 },
{ 3425, 0x6F00 },
{ 3350, 0x7100 },
{ 3236, 0x7400 },
{ 3118, 0x7700 },
{ 3004, 0x7A00 },
{ 2917, 0x7C00 },
{ 2776, 0x7F00 },
{ 2635, 0x8200 },
{ 2516, 0x8500 },
{ 2406, 0x8800 },
{ 2290, 0x8B00 },
{ 2170, 0x8E00 },
{ 2073, 0x9100 },
{ 1949, 0x9400 },
{ 1836, 0x9700 },
{ 1712, 0x9A00 },
{ 1631, 0x9C00 },
{ 1515, 0x9F00 },
{ 1400, 0xA200 },
{ 1323, 0xA400 },
{ 1203, 0xA700 },
{ 1091, 0xAA00 },
{ 1011, 0xAC00 },
{ 904, 0xAF00 },
{ 787, 0xB200 },
{ 685, 0xB500 },
{ 571, 0xB800 },
{ 464, 0xBB00 },
{ 374, 0xBE00 },
{ 275, 0xC200 },
{ 181, 0xC600 },
{ 102, 0xCC00 },
{ 49, 0xD900 }
};
/*
* This table is 6 dB too low comapred to the others (probably created with
* a different BB_MAG setting)
*/
static const struct slookup gain_channel_agc_nf_lookup[] = {
/* Gain *100dB // reg */
{ 7082, 0x3000 },
{ 7052, 0x4000 },
{ 7007, 0x4600 },
{ 6954, 0x4A00 },
{ 6909, 0x4D00 },
{ 6833, 0x5100 },
{ 6753, 0x5400 },
{ 6659, 0x5700 },
{ 6561, 0x5A00 },
{ 6472, 0x5C00 },
{ 6366, 0x5F00 },
{ 6259, 0x6100 },
{ 6151, 0x6400 },
{ 6026, 0x6700 },
{ 5920, 0x6900 },
{ 5835, 0x6B00 },
{ 5770, 0x6C00 },
{ 5681, 0x6E00 },
{ 5596, 0x7000 },
{ 5503, 0x7200 },
{ 5429, 0x7300 },
{ 5319, 0x7500 },
{ 5220, 0x7700 },
{ 5111, 0x7900 },
{ 4983, 0x7B00 },
{ 4876, 0x7D00 },
{ 4755, 0x7F00 },
{ 4635, 0x8100 },
{ 4499, 0x8300 },
{ 4405, 0x8500 },
{ 4323, 0x8600 },
{ 4233, 0x8800 },
{ 4156, 0x8A00 },
{ 4038, 0x8C00 },
{ 3935, 0x8E00 },
{ 3823, 0x9000 },
{ 3712, 0x9200 },
{ 3601, 0x9500 },
{ 3511, 0x9700 },
{ 3413, 0x9900 },
{ 3309, 0x9B00 },
{ 3213, 0x9D00 },
{ 3088, 0x9F00 },
{ 2992, 0xA100 },
{ 2878, 0xA400 },
{ 2769, 0xA700 },
{ 2645, 0xAA00 },
{ 2538, 0xAD00 },
{ 2441, 0xB000 },
{ 2350, 0xB600 },
{ 2237, 0xBA00 },
{ 2137, 0xBF00 },
{ 2039, 0xC500 },
{ 1938, 0xDF00 },
{ 1927, 0xFF00 }
};
static const struct slookup gain_channel_agc_iip3_lookup[] = {
/* Gain *100dB // reg */
{ 7070, 0x3000 },
{ 7028, 0x4000 },
{ 7019, 0x4600 },
{ 6900, 0x4A00 },
{ 6811, 0x4D00 },
{ 6763, 0x5100 },
{ 6690, 0x5400 },
{ 6644, 0x5700 },
{ 6617, 0x5A00 },
{ 6598, 0x5C00 },
{ 6462, 0x5F00 },
{ 6348, 0x6100 },
{ 6197, 0x6400 },
{ 6154, 0x6700 },
{ 6098, 0x6900 },
{ 5893, 0x6B00 },
{ 5812, 0x6C00 },
{ 5773, 0x6E00 },
{ 5723, 0x7000 },
{ 5661, 0x7200 },
{ 5579, 0x7300 },
{ 5460, 0x7500 },
{ 5308, 0x7700 },
{ 5099, 0x7900 },
{ 4910, 0x7B00 },
{ 4800, 0x7D00 },
{ 4785, 0x7F00 },
{ 4635, 0x8100 },
{ 4466, 0x8300 },
{ 4314, 0x8500 },
{ 4295, 0x8600 },
{ 4144, 0x8800 },
{ 3920, 0x8A00 },
{ 3889, 0x8C00 },
{ 3771, 0x8E00 },
{ 3655, 0x9000 },
{ 3446, 0x9200 },
{ 3298, 0x9500 },
{ 3083, 0x9700 },
{ 3015, 0x9900 },
{ 2833, 0x9B00 },
{ 2746, 0x9D00 },
{ 2632, 0x9F00 },
{ 2598, 0xA100 },
{ 2480, 0xA400 },
{ 2236, 0xA700 },
{ 2171, 0xAA00 },
{ 2060, 0xAD00 },
{ 1999, 0xB000 },
{ 1974, 0xB600 },
{ 1820, 0xBA00 },
{ 1741, 0xBF00 },
{ 1655, 0xC500 },
{ 1444, 0xDF00 },
{ 1325, 0xFF00 },
};
static inline u32 muldiv32(u32 a, u32 b, u32 c)
{
u64 tmp64;
tmp64 = (u64)a * (u64)b;
do_div(tmp64, c);
return (u32)tmp64;
}
static int i2c_read(struct i2c_adapter *adap,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
.buf = msg, .len = len},
{ .addr = adr, .flags = I2C_M_RD,
.buf = answ, .len = alen } };
if (i2c_transfer(adap, msgs, 2) != 2) {
dev_err(&adap->dev, "i2c read error\n");
return -EIO;
}
return 0;
}
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
dev_err(&adap->dev, "i2c write error\n");
return -EIO;
}
return 0;
}
static int write_regs(struct stv *state, int reg, int len)
{
u8 d[12];
memcpy(&d[1], &state->reg[reg], len);
d[0] = reg;
return i2c_write(state->i2c, state->adr, d, len + 1);
}
static int write_reg(struct stv *state, u8 reg, u8 val)
{
u8 d[2] = {reg, val};
return i2c_write(state->i2c, state->adr, d, 2);
}
static int read_reg(struct stv *state, u8 reg, u8 *val)
{
return i2c_read(state->i2c, state->adr, ®, 1, val, 1);
}
static int wait_for_call_done(struct stv *state, u8 mask)
{
int status = 0;
u32 lock_retry_count = 10;
while (lock_retry_count > 0) {
u8 regval;
status = read_reg(state, 9, ®val);
if (status < 0)
return status;
if ((regval & mask) == 0)
break;
usleep_range(4000, 6000);
lock_retry_count -= 1;
status = -EIO;
}
return status;
}
static void init_state(struct stv *state)
{
u32 clkdiv = 0;
u32 agcmode = 0;
u32 agcref = 2;
u32 agcset = 0xffffffff;
u32 bbmode = 0xffffffff;
state->reg[0] = 0x08;
state->reg[1] = 0x41;
state->reg[2] = 0x8f;
state->reg[3] = 0x00;
state->reg[4] = 0xce;
state->reg[5] = 0x54;
state->reg[6] = 0x55;
state->reg[7] = 0x45;
state->reg[8] = 0x46;
state->reg[9] = 0xbd;
state->reg[10] = 0x11;
state->ref_freq = 16000;
if (clkdiv <= 3)
state->reg[0x00] |= (clkdiv & 0x03);
if (agcmode <= 3) {
state->reg[0x03] |= (agcmode << 5);
if (agcmode == 0x01)
state->reg[0x01] |= 0x30;
}
if (bbmode <= 3)
state->reg[0x01] = (state->reg[0x01] & ~0x30) | (bbmode << 4);
if (agcref <= 7)
state->reg[0x03] |= agcref;
if (agcset <= 31)
state->reg[0x02] = (state->reg[0x02] & ~0x1F) | agcset | 0x40;
}
static int attach_init(struct stv *state)
{
if (write_regs(state, 0, 11))
return -ENODEV;
return 0;
}
static void release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int set_bandwidth(struct dvb_frontend *fe, u32 cutoff_frequency)
{
struct stv *state = fe->tuner_priv;
u32 index = (cutoff_frequency + 999999) / 1000000;
int stat = 0;
if (index < 6)
index = 6;
if (index > 50)
index = 50;
if ((state->reg[0x08] & ~0xFC) == ((index - 6) << 2))
return 0;
state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2);
state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08;
if (fe->ops.i2c_gate_ctrl)
stat = fe->ops.i2c_gate_ctrl(fe, 1);
if (!stat) {
write_regs(state, 0x08, 2);
wait_for_call_done(state, 0x08);
}
if (fe->ops.i2c_gate_ctrl && !stat)
fe->ops.i2c_gate_ctrl(fe, 0);
return stat;
}
static int set_lof(struct stv *state, u32 local_frequency, u32 cutoff_frequency)
{
u32 index = (cutoff_frequency + 999999) / 1000000;
u32 frequency = (local_frequency + 500) / 1000;
u32 p = 1, psel = 0, fvco, div, frac;
u8 icp, tmp;
if (index < 6)
index = 6;
if (index > 50)
index = 50;
if (frequency <= 1300000) {
p = 4;
psel = 1;
} else {
p = 2;
psel = 0;
}
fvco = frequency * p;
div = fvco / state->ref_freq;
frac = fvco % state->ref_freq;
frac = muldiv32(frac, 0x40000, state->ref_freq);
icp = 0;
if (fvco < 2700000)
icp = 0;
else if (fvco < 2950000)
icp = 1;
else if (fvco < 3300000)
icp = 2;
else if (fvco < 3700000)
icp = 3;
else if (fvco < 4200000)
icp = 5;
else if (fvco < 4800000)
icp = 6;
else
icp = 7;
state->reg[0x02] |= 0x80; /* LNA IIP3 Mode */
state->reg[0x03] = (state->reg[0x03] & ~0x80) | (psel << 7);
state->reg[0x04] = (div & 0xFF);
state->reg[0x05] = (((div >> 8) & 0x01) | ((frac & 0x7F) << 1)) & 0xff;
state->reg[0x06] = ((frac >> 7) & 0xFF);
state->reg[0x07] = (state->reg[0x07] & ~0x07) | ((frac >> 15) & 0x07);
state->reg[0x07] = (state->reg[0x07] & ~0xE0) | (icp << 5);
state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2);
/* Start cal vco,CF */
state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x0C;
write_regs(state, 2, 8);
wait_for_call_done(state, 0x0C);
usleep_range(10000, 12000);
read_reg(state, 0x03, &tmp);
if (tmp & 0x10) {
state->reg[0x02] &= ~0x80; /* LNA NF Mode */
write_regs(state, 2, 1);
}
read_reg(state, 0x08, &tmp);
state->frequency = frequency;
return 0;
}
static int set_params(struct dvb_frontend *fe)
{
struct stv *state = fe->tuner_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 freq, cutoff;
int stat = 0;
if (p->delivery_system != SYS_DVBS && p->delivery_system != SYS_DVBS2)
return -EINVAL;
freq = p->frequency * 1000;
cutoff = 5000000 + muldiv32(p->symbol_rate, 135, 200);
if (fe->ops.i2c_gate_ctrl)
stat = fe->ops.i2c_gate_ctrl(fe, 1);
if (!stat)
set_lof(state, freq, cutoff);
if (fe->ops.i2c_gate_ctrl && !stat)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static s32 table_lookup(const struct slookup *table,
int table_size, u16 reg_value)
{
s32 gain;
s32 reg_diff;
int imin = 0;
int imax = table_size - 1;
int i;
/* Assumes Table[0].RegValue < Table[imax].RegValue */
if (reg_value <= table[0].reg_value) {
gain = table[0].value;
} else if (reg_value >= table[imax].reg_value) {
gain = table[imax].value;
} else {
while ((imax - imin) > 1) {
i = (imax + imin) / 2;
if ((table[imin].reg_value <= reg_value) &&
(reg_value <= table[i].reg_value))
imax = i;
else
imin = i;
}
reg_diff = table[imax].reg_value - table[imin].reg_value;
gain = table[imin].value;
if (reg_diff != 0)
gain += ((s32)(reg_value - table[imin].reg_value) *
(s32)(table[imax].value
- table[imin].value)) / reg_diff;
}
return gain;
}
static int get_rf_strength(struct dvb_frontend *fe, u16 *st)
{
struct stv *state = fe->tuner_priv;
u16 rfagc = *st;
s32 gain;
if ((state->reg[0x03] & 0x60) == 0) {
/* RF Mode, Read AGC ADC */
u8 reg = 0;
int stat = 0;
if (fe->ops.i2c_gate_ctrl)
stat = fe->ops.i2c_gate_ctrl(fe, 1);
if (!stat) {
write_reg(state, 0x02, state->reg[0x02] | 0x20);
read_reg(state, 2, ®);
if (reg & 0x20)
read_reg(state, 2, ®);
}
if (fe->ops.i2c_gate_ctrl && !stat)
fe->ops.i2c_gate_ctrl(fe, 0);
if ((state->reg[0x02] & 0x80) == 0)
/* NF */
gain = table_lookup(lnagain_nf_lookup,
ARRAY_SIZE(lnagain_nf_lookup),
reg & 0x1F);
else
/* IIP3 */
gain = table_lookup(lnagain_iip3_lookup,
ARRAY_SIZE(lnagain_iip3_lookup),
reg & 0x1F);
gain += table_lookup(gain_rfagc_lookup,
ARRAY_SIZE(gain_rfagc_lookup), rfagc);
gain -= 2400;
} else {
/* Channel Mode */
if ((state->reg[0x02] & 0x80) == 0) {
/* NF */
gain = table_lookup(
gain_channel_agc_nf_lookup,
ARRAY_SIZE(gain_channel_agc_nf_lookup), rfagc);
gain += 600;
} else {
/* IIP3 */
gain = table_lookup(
gain_channel_agc_iip3_lookup,
ARRAY_SIZE(gain_channel_agc_iip3_lookup),
rfagc);
}
}
if (state->frequency > 0)
/* Tilt correction ( 0.00016 dB/MHz ) */
gain -= ((((s32)(state->frequency / 1000) - 1550) * 2) / 12);
/* + (BBGain * 10); */
gain += (s32)((state->reg[0x01] & 0xC0) >> 6) * 600 - 1300;
if (gain < 0)
gain = 0;
else if (gain > 10000)
gain = 10000;
*st = 10000 - gain;
return 0;
}
static const struct dvb_tuner_ops tuner_ops = {
.info = {
.name = "ST STV6111",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
},
.set_params = set_params,
.release = release,
.get_rf_strength = get_rf_strength,
.set_bandwidth = set_bandwidth,
};
struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr)
{
struct stv *state;
int stat = -ENODEV;
int gatestat = 0;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
state->adr = adr;
state->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
init_state(state);
if (fe->ops.i2c_gate_ctrl)
gatestat = fe->ops.i2c_gate_ctrl(fe, 1);
if (!gatestat)
stat = attach_init(state);
if (fe->ops.i2c_gate_ctrl && !gatestat)
fe->ops.i2c_gate_ctrl(fe, 0);
if (stat < 0) {
kfree(state);
return NULL;
}
fe->tuner_priv = state;
return fe;
}
EXPORT_SYMBOL_GPL(stv6111_attach);
MODULE_DESCRIPTION("ST STV6111 satellite tuner driver");
MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/stv6111.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Afatech AF9013 demodulator driver
*
* Copyright (C) 2007 Antti Palosaari <[email protected]>
* Copyright (C) 2011 Antti Palosaari <[email protected]>
*
* Thanks to Afatech who kindly provided information.
*/
#include "af9013_priv.h"
struct af9013_state {
struct i2c_client *client;
struct regmap *regmap;
struct i2c_mux_core *muxc;
struct dvb_frontend fe;
u32 clk;
u8 tuner;
u32 if_frequency;
u8 ts_mode;
u8 ts_output_pin;
bool spec_inv;
u8 api_version[4];
u8 gpio[4];
u32 bandwidth_hz;
enum fe_status fe_status;
/* RF and IF AGC limits used for signal strength calc */
u8 strength_en, rf_agc_50, rf_agc_80, if_agc_50, if_agc_80;
unsigned long set_frontend_jiffies;
unsigned long read_status_jiffies;
unsigned long strength_jiffies;
unsigned long cnr_jiffies;
unsigned long ber_ucb_jiffies;
u16 dvbv3_snr;
u16 dvbv3_strength;
u32 dvbv3_ber;
u32 dvbv3_ucblocks;
bool first_tune;
};
static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
{
struct i2c_client *client = state->client;
int ret;
u8 pos;
u16 addr;
dev_dbg(&client->dev, "gpio %u, gpioval %02x\n", gpio, gpioval);
/*
* GPIO0 & GPIO1 0xd735
* GPIO2 & GPIO3 0xd736
*/
switch (gpio) {
case 0:
case 1:
addr = 0xd735;
break;
case 2:
case 3:
addr = 0xd736;
break;
default:
ret = -EINVAL;
goto err;
}
switch (gpio) {
case 0:
case 2:
pos = 0;
break;
case 1:
case 3:
default:
pos = 4;
break;
}
ret = regmap_update_bits(state->regmap, addr, 0x0f << pos,
gpioval << pos);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 800;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int af9013_set_frontend(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, sampling_freq;
bool auto_mode, spec_inv;
u8 buf[6];
u32 if_frequency, freq_cw;
dev_dbg(&client->dev, "frequency %u, bandwidth_hz %u\n",
c->frequency, c->bandwidth_hz);
/* program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
/* program CFOE coefficients */
if (c->bandwidth_hz != state->bandwidth_hz) {
for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
if (coeff_lut[i].clock == state->clk &&
coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
break;
}
}
/* Return an error if can't find bandwidth or the right clock */
if (i == ARRAY_SIZE(coeff_lut)) {
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_write(state->regmap, 0xae00, coeff_lut[i].val,
sizeof(coeff_lut[i].val));
if (ret)
goto err;
}
/* program frequency control */
if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) {
/* get used IF frequency */
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe,
&if_frequency);
if (ret)
goto err;
} else {
if_frequency = state->if_frequency;
}
dev_dbg(&client->dev, "if_frequency %u\n", if_frequency);
sampling_freq = if_frequency;
while (sampling_freq > (state->clk / 2))
sampling_freq -= state->clk;
if (sampling_freq < 0) {
sampling_freq *= -1;
spec_inv = state->spec_inv;
} else {
spec_inv = !state->spec_inv;
}
freq_cw = DIV_ROUND_CLOSEST_ULL((u64)sampling_freq * 0x800000,
state->clk);
if (spec_inv)
freq_cw = 0x800000 - freq_cw;
buf[0] = (freq_cw >> 0) & 0xff;
buf[1] = (freq_cw >> 8) & 0xff;
buf[2] = (freq_cw >> 16) & 0x7f;
freq_cw = 0x800000 - freq_cw;
buf[3] = (freq_cw >> 0) & 0xff;
buf[4] = (freq_cw >> 8) & 0xff;
buf[5] = (freq_cw >> 16) & 0x7f;
ret = regmap_bulk_write(state->regmap, 0xd140, buf, 3);
if (ret)
goto err;
ret = regmap_bulk_write(state->regmap, 0x9be7, buf, 6);
if (ret)
goto err;
}
/* clear TPS lock flag */
ret = regmap_update_bits(state->regmap, 0xd330, 0x08, 0x08);
if (ret)
goto err;
/* clear MPEG2 lock flag */
ret = regmap_update_bits(state->regmap, 0xd507, 0x40, 0x00);
if (ret)
goto err;
/* empty channel function */
ret = regmap_update_bits(state->regmap, 0x9bfe, 0x01, 0x00);
if (ret)
goto err;
/* empty DVB-T channel function */
ret = regmap_update_bits(state->regmap, 0x9bc2, 0x01, 0x00);
if (ret)
goto err;
/* transmission parameters */
auto_mode = false;
memset(buf, 0, 3);
switch (c->transmission_mode) {
case TRANSMISSION_MODE_AUTO:
auto_mode = true;
break;
case TRANSMISSION_MODE_2K:
break;
case TRANSMISSION_MODE_8K:
buf[0] |= (1 << 0);
break;
default:
dev_dbg(&client->dev, "invalid transmission_mode\n");
auto_mode = true;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_AUTO:
auto_mode = true;
break;
case GUARD_INTERVAL_1_32:
break;
case GUARD_INTERVAL_1_16:
buf[0] |= (1 << 2);
break;
case GUARD_INTERVAL_1_8:
buf[0] |= (2 << 2);
break;
case GUARD_INTERVAL_1_4:
buf[0] |= (3 << 2);
break;
default:
dev_dbg(&client->dev, "invalid guard_interval\n");
auto_mode = true;
}
switch (c->hierarchy) {
case HIERARCHY_AUTO:
auto_mode = true;
break;
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
buf[0] |= (1 << 4);
break;
case HIERARCHY_2:
buf[0] |= (2 << 4);
break;
case HIERARCHY_4:
buf[0] |= (3 << 4);
break;
default:
dev_dbg(&client->dev, "invalid hierarchy\n");
auto_mode = true;
}
switch (c->modulation) {
case QAM_AUTO:
auto_mode = true;
break;
case QPSK:
break;
case QAM_16:
buf[1] |= (1 << 6);
break;
case QAM_64:
buf[1] |= (2 << 6);
break;
default:
dev_dbg(&client->dev, "invalid modulation\n");
auto_mode = true;
}
/* Use HP. How and which case we can switch to LP? */
buf[1] |= (1 << 4);
switch (c->code_rate_HP) {
case FEC_AUTO:
auto_mode = true;
break;
case FEC_1_2:
break;
case FEC_2_3:
buf[2] |= (1 << 0);
break;
case FEC_3_4:
buf[2] |= (2 << 0);
break;
case FEC_5_6:
buf[2] |= (3 << 0);
break;
case FEC_7_8:
buf[2] |= (4 << 0);
break;
default:
dev_dbg(&client->dev, "invalid code_rate_HP\n");
auto_mode = true;
}
switch (c->code_rate_LP) {
case FEC_AUTO:
auto_mode = true;
break;
case FEC_1_2:
break;
case FEC_2_3:
buf[2] |= (1 << 3);
break;
case FEC_3_4:
buf[2] |= (2 << 3);
break;
case FEC_5_6:
buf[2] |= (3 << 3);
break;
case FEC_7_8:
buf[2] |= (4 << 3);
break;
case FEC_NONE:
break;
default:
dev_dbg(&client->dev, "invalid code_rate_LP\n");
auto_mode = true;
}
switch (c->bandwidth_hz) {
case 6000000:
break;
case 7000000:
buf[1] |= (1 << 2);
break;
case 8000000:
buf[1] |= (2 << 2);
break;
default:
dev_dbg(&client->dev, "invalid bandwidth_hz\n");
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_write(state->regmap, 0xd3c0, buf, 3);
if (ret)
goto err;
if (auto_mode) {
/* clear easy mode flag */
ret = regmap_write(state->regmap, 0xaefd, 0x00);
if (ret)
goto err;
dev_dbg(&client->dev, "auto params\n");
} else {
/* set easy mode flag */
ret = regmap_write(state->regmap, 0xaefd, 0x01);
if (ret)
goto err;
ret = regmap_write(state->regmap, 0xaefe, 0x00);
if (ret)
goto err;
dev_dbg(&client->dev, "manual params\n");
}
/* Reset FSM */
ret = regmap_write(state->regmap, 0xffff, 0x00);
if (ret)
goto err;
state->bandwidth_hz = c->bandwidth_hz;
state->set_frontend_jiffies = jiffies;
state->first_tune = false;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
u8 buf[3];
dev_dbg(&client->dev, "\n");
ret = regmap_bulk_read(state->regmap, 0xd3c0, buf, 3);
if (ret)
goto err;
switch ((buf[1] >> 6) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[0] >> 0) & 3) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
}
switch ((buf[0] >> 2) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[0] >> 4) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[2] >> 0) & 7) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
}
switch ((buf[2] >> 3) & 7) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
}
switch ((buf[1] >> 2) & 3) {
case 0:
c->bandwidth_hz = 6000000;
break;
case 1:
c->bandwidth_hz = 7000000;
break;
case 2:
c->bandwidth_hz = 8000000;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, stmp1;
unsigned int utmp, utmp1, utmp2, utmp3, utmp4;
u8 buf[7];
dev_dbg(&client->dev, "\n");
/*
* Return status from the cache if it is younger than 2000ms with the
* exception of last tune is done during 4000ms.
*/
if (time_is_after_jiffies(state->read_status_jiffies + msecs_to_jiffies(2000)) &&
time_is_before_jiffies(state->set_frontend_jiffies + msecs_to_jiffies(4000))) {
*status = state->fe_status;
} else {
/* MPEG2 lock */
ret = regmap_read(state->regmap, 0xd507, &utmp);
if (ret)
goto err;
if ((utmp >> 6) & 0x01) {
utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else {
/* TPS lock */
ret = regmap_read(state->regmap, 0xd330, &utmp);
if (ret)
goto err;
if ((utmp >> 3) & 0x01)
utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
else
utmp1 = 0;
}
dev_dbg(&client->dev, "fe_status %02x\n", utmp1);
state->read_status_jiffies = jiffies;
state->fe_status = utmp1;
*status = utmp1;
}
/* Signal strength */
switch (state->strength_en) {
case 0:
/* Check if we support signal strength */
ret = regmap_read(state->regmap, 0x9bee, &utmp);
if (ret)
goto err;
if ((utmp >> 0) & 0x01) {
/* Read agc values for signal strength estimation */
ret = regmap_read(state->regmap, 0x9bbd, &utmp1);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9bd0, &utmp2);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9be2, &utmp3);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9be4, &utmp4);
if (ret)
goto err;
state->rf_agc_50 = utmp1;
state->rf_agc_80 = utmp2;
state->if_agc_50 = utmp3;
state->if_agc_80 = utmp4;
dev_dbg(&client->dev,
"rf_agc_50 %u, rf_agc_80 %u, if_agc_50 %u, if_agc_80 %u\n",
utmp1, utmp2, utmp3, utmp4);
state->strength_en = 1;
} else {
/* Signal strength is not supported */
state->strength_en = 2;
break;
}
fallthrough;
case 1:
if (time_is_after_jiffies(state->strength_jiffies + msecs_to_jiffies(2000)))
break;
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd07c, buf, 2);
if (ret)
goto err;
/*
* Construct line equation from tuner dependent -80/-50 dBm agc
* limits and use it to map current agc value to dBm estimate
*/
#define agc_gain (buf[0] + buf[1])
#define agc_gain_50dbm (state->rf_agc_50 + state->if_agc_50)
#define agc_gain_80dbm (state->rf_agc_80 + state->if_agc_80)
stmp1 = 30000 * (agc_gain - agc_gain_80dbm) /
(agc_gain_50dbm - agc_gain_80dbm) - 80000;
dev_dbg(&client->dev,
"strength %d, agc_gain %d, agc_gain_50dbm %d, agc_gain_80dbm %d\n",
stmp1, agc_gain, agc_gain_50dbm, agc_gain_80dbm);
state->strength_jiffies = jiffies;
/* Convert [-90, -30] dBm to [0x0000, 0xffff] for dvbv3 */
utmp1 = clamp(stmp1 + 90000, 0, 60000);
state->dvbv3_strength = div_u64((u64)utmp1 * 0xffff, 60000);
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = stmp1;
break;
default:
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
/* CNR */
switch (state->fe_status & FE_HAS_VITERBI) {
case FE_HAS_VITERBI:
if (time_is_after_jiffies(state->cnr_jiffies + msecs_to_jiffies(2000)))
break;
/* Check if cnr ready */
ret = regmap_read(state->regmap, 0xd2e1, &utmp);
if (ret)
goto err;
if (!((utmp >> 3) & 0x01)) {
dev_dbg(&client->dev, "cnr not ready\n");
break;
}
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd2e3, buf, 3);
if (ret)
goto err;
utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
/* Read current modulation */
ret = regmap_read(state->regmap, 0xd3c1, &utmp);
if (ret)
goto err;
switch ((utmp >> 6) & 3) {
case 0:
/*
* QPSK
* CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
* value [653799, 1689999], 2.6 / 13 = 3355443
*/
utmp1 = clamp(utmp1, 653799U, 1689999U);
utmp1 = ((u64)(intlog10(utmp1)
- intlog10(1690000 - utmp1)
+ 3355443) * 13 * 1000) >> 24;
break;
case 1:
/*
* QAM-16
* CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
* value [371105, 827999], 15.7 / 6 = 43900382
*/
utmp1 = clamp(utmp1, 371105U, 827999U);
utmp1 = ((u64)(intlog10(utmp1 - 370000)
- intlog10(828000 - utmp1)
+ 43900382) * 6 * 1000) >> 24;
break;
case 2:
/*
* QAM-64
* CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
* value [193246, 424999], 23.8 / 8 = 49912218
*/
utmp1 = clamp(utmp1, 193246U, 424999U);
utmp1 = ((u64)(intlog10(utmp1 - 193000)
- intlog10(425000 - utmp1)
+ 49912218) * 8 * 1000) >> 24;
break;
default:
dev_dbg(&client->dev, "invalid modulation %u\n",
(utmp >> 6) & 3);
utmp1 = 0;
break;
}
dev_dbg(&client->dev, "cnr %u\n", utmp1);
state->cnr_jiffies = jiffies;
state->dvbv3_snr = utmp1 / 100;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = utmp1;
break;
default:
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
/* BER / PER */
switch (state->fe_status & FE_HAS_SYNC) {
case FE_HAS_SYNC:
if (time_is_after_jiffies(state->ber_ucb_jiffies + msecs_to_jiffies(2000)))
break;
/* Check if ber / ucb is ready */
ret = regmap_read(state->regmap, 0xd391, &utmp);
if (ret)
goto err;
if (!((utmp >> 4) & 0x01)) {
dev_dbg(&client->dev, "ber not ready\n");
break;
}
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd385, buf, 7);
if (ret)
goto err;
utmp1 = buf[4] << 16 | buf[3] << 8 | buf[2] << 0;
utmp2 = (buf[1] << 8 | buf[0] << 0) * 204 * 8;
utmp3 = buf[6] << 8 | buf[5] << 0;
utmp4 = buf[1] << 8 | buf[0] << 0;
/* Use 10000 TS packets for measure */
if (utmp4 != 10000) {
buf[0] = (10000 >> 0) & 0xff;
buf[1] = (10000 >> 8) & 0xff;
ret = regmap_bulk_write(state->regmap, 0xd385, buf, 2);
if (ret)
goto err;
}
/* Reset ber / ucb counter */
ret = regmap_update_bits(state->regmap, 0xd391, 0x20, 0x20);
if (ret)
goto err;
dev_dbg(&client->dev, "post_bit_error %u, post_bit_count %u\n",
utmp1, utmp2);
dev_dbg(&client->dev, "block_error %u, block_count %u\n",
utmp3, utmp4);
state->ber_ucb_jiffies = jiffies;
state->dvbv3_ber = utmp1;
state->dvbv3_ucblocks += utmp3;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += utmp1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += utmp2;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += utmp3;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += utmp4;
break;
default:
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct af9013_state *state = fe->demodulator_priv;
*snr = state->dvbv3_snr;
return 0;
}
static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct af9013_state *state = fe->demodulator_priv;
*strength = state->dvbv3_strength;
return 0;
}
static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct af9013_state *state = fe->demodulator_priv;
*ber = state->dvbv3_ber;
return 0;
}
static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct af9013_state *state = fe->demodulator_priv;
*ucblocks = state->dvbv3_ucblocks;
return 0;
}
static int af9013_init(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret, i, len;
unsigned int utmp;
u8 buf[3];
const struct af9013_reg_mask_val *tab;
dev_dbg(&client->dev, "\n");
/* ADC on */
ret = regmap_update_bits(state->regmap, 0xd73a, 0x08, 0x00);
if (ret)
goto err;
/* Clear reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x02, 0x00);
if (ret)
goto err;
/* Disable reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x00);
if (ret)
goto err;
/* write API version to firmware */
ret = regmap_bulk_write(state->regmap, 0x9bf2, state->api_version, 4);
if (ret)
goto err;
/* program ADC control */
switch (state->clk) {
case 28800000: /* 28.800 MHz */
utmp = 0;
break;
case 20480000: /* 20.480 MHz */
utmp = 1;
break;
case 28000000: /* 28.000 MHz */
utmp = 2;
break;
case 25000000: /* 25.000 MHz */
utmp = 3;
break;
default:
ret = -EINVAL;
goto err;
}
ret = regmap_update_bits(state->regmap, 0x9bd2, 0x0f, utmp);
if (ret)
goto err;
utmp = div_u64((u64)state->clk * 0x80000, 1000000);
buf[0] = (utmp >> 0) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 16) & 0xff;
ret = regmap_bulk_write(state->regmap, 0xd180, buf, 3);
if (ret)
goto err;
/* Demod core settings */
dev_dbg(&client->dev, "load demod core settings\n");
len = ARRAY_SIZE(demod_init_tab);
tab = demod_init_tab;
for (i = 0; i < len; i++) {
ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
/* Demod tuner specific settings */
dev_dbg(&client->dev, "load tuner specific settings\n");
switch (state->tuner) {
case AF9013_TUNER_MXL5003D:
len = ARRAY_SIZE(tuner_init_tab_mxl5003d);
tab = tuner_init_tab_mxl5003d;
break;
case AF9013_TUNER_MXL5005D:
case AF9013_TUNER_MXL5005R:
case AF9013_TUNER_MXL5007T:
len = ARRAY_SIZE(tuner_init_tab_mxl5005);
tab = tuner_init_tab_mxl5005;
break;
case AF9013_TUNER_ENV77H11D5:
len = ARRAY_SIZE(tuner_init_tab_env77h11d5);
tab = tuner_init_tab_env77h11d5;
break;
case AF9013_TUNER_MT2060:
len = ARRAY_SIZE(tuner_init_tab_mt2060);
tab = tuner_init_tab_mt2060;
break;
case AF9013_TUNER_MC44S803:
len = ARRAY_SIZE(tuner_init_tab_mc44s803);
tab = tuner_init_tab_mc44s803;
break;
case AF9013_TUNER_QT1010:
case AF9013_TUNER_QT1010A:
len = ARRAY_SIZE(tuner_init_tab_qt1010);
tab = tuner_init_tab_qt1010;
break;
case AF9013_TUNER_MT2060_2:
len = ARRAY_SIZE(tuner_init_tab_mt2060_2);
tab = tuner_init_tab_mt2060_2;
break;
case AF9013_TUNER_TDA18271:
case AF9013_TUNER_TDA18218:
len = ARRAY_SIZE(tuner_init_tab_tda18271);
tab = tuner_init_tab_tda18271;
break;
case AF9013_TUNER_UNKNOWN:
default:
len = ARRAY_SIZE(tuner_init_tab_unknown);
tab = tuner_init_tab_unknown;
break;
}
for (i = 0; i < len; i++) {
ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
/* TS interface */
if (state->ts_output_pin == 7)
utmp = 1 << 3 | state->ts_mode << 1;
else
utmp = 0 << 3 | state->ts_mode << 1;
ret = regmap_update_bits(state->regmap, 0xd500, 0x0e, utmp);
if (ret)
goto err;
/* enable lock led */
ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x01);
if (ret)
goto err;
state->first_tune = true;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_sleep(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
unsigned int utmp;
dev_dbg(&client->dev, "\n");
/* disable lock led */
ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x00);
if (ret)
goto err;
/* Enable reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x10);
if (ret)
goto err;
/* Start reset execution */
ret = regmap_write(state->regmap, 0xaeff, 0x01);
if (ret)
goto err;
/* Wait reset performs */
ret = regmap_read_poll_timeout(state->regmap, 0xd417, utmp,
(utmp >> 1) & 0x01, 5000, 1000000);
if (ret)
goto err;
if (!((utmp >> 1) & 0x01)) {
ret = -ETIMEDOUT;
goto err;
}
/* ADC off */
ret = regmap_update_bits(state->regmap, 0xd73a, 0x08, 0x08);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static const struct dvb_frontend_ops af9013_ops;
static int af9013_download_firmware(struct af9013_state *state)
{
struct i2c_client *client = state->client;
int ret, i, len, rem;
unsigned int utmp;
u8 buf[4];
u16 checksum = 0;
const struct firmware *firmware;
const char *name = AF9013_FIRMWARE;
dev_dbg(&client->dev, "\n");
/* Check whether firmware is already running */
ret = regmap_read(state->regmap, 0x98be, &utmp);
if (ret)
goto err;
dev_dbg(&client->dev, "firmware status %02x\n", utmp);
if (utmp == 0x0c)
return 0;
dev_info(&client->dev, "found a '%s' in cold state, will try to load a firmware\n",
af9013_ops.info.name);
/* Request the firmware, will block and timeout */
ret = request_firmware(&firmware, name, &client->dev);
if (ret) {
dev_info(&client->dev, "firmware file '%s' not found %d\n",
name, ret);
goto err;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n",
name);
/* Write firmware checksum & size */
for (i = 0; i < firmware->size; i++)
checksum += firmware->data[i];
buf[0] = (checksum >> 8) & 0xff;
buf[1] = (checksum >> 0) & 0xff;
buf[2] = (firmware->size >> 8) & 0xff;
buf[3] = (firmware->size >> 0) & 0xff;
ret = regmap_bulk_write(state->regmap, 0x50fc, buf, 4);
if (ret)
goto err_release_firmware;
/* Download firmware */
#define LEN_MAX 16
for (rem = firmware->size; rem > 0; rem -= LEN_MAX) {
len = min(LEN_MAX, rem);
ret = regmap_bulk_write(state->regmap,
0x5100 + firmware->size - rem,
&firmware->data[firmware->size - rem],
len);
if (ret) {
dev_err(&client->dev, "firmware download failed %d\n",
ret);
goto err_release_firmware;
}
}
release_firmware(firmware);
/* Boot firmware */
ret = regmap_write(state->regmap, 0xe205, 0x01);
if (ret)
goto err;
/* Check firmware status. 0c=OK, 04=fail */
ret = regmap_read_poll_timeout(state->regmap, 0x98be, utmp,
(utmp == 0x0c || utmp == 0x04),
5000, 1000000);
if (ret)
goto err;
dev_dbg(&client->dev, "firmware status %02x\n", utmp);
if (utmp == 0x04) {
ret = -ENODEV;
dev_err(&client->dev, "firmware did not run\n");
goto err;
} else if (utmp != 0x0c) {
ret = -ENODEV;
dev_err(&client->dev, "firmware boot timeout\n");
goto err;
}
dev_info(&client->dev, "found a '%s' in warm state\n",
af9013_ops.info.name);
return 0;
err_release_firmware:
release_firmware(firmware);
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static const struct dvb_frontend_ops af9013_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Afatech AF9013",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 250 * kHz,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.init = af9013_init,
.sleep = af9013_sleep,
.get_tune_settings = af9013_get_tune_settings,
.set_frontend = af9013_set_frontend,
.get_frontend = af9013_get_frontend,
.read_status = af9013_read_status,
.read_snr = af9013_read_snr,
.read_signal_strength = af9013_read_signal_strength,
.read_ber = af9013_read_ber,
.read_ucblocks = af9013_read_ucblocks,
};
static int af9013_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
dev_dbg(&client->dev, "onoff %d\n", onoff);
ret = regmap_update_bits(state->regmap, 0xd503, 0x01, onoff);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
int onoff)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
u8 buf[2];
dev_dbg(&client->dev, "index %d, pid %04x, onoff %d\n",
index, pid, onoff);
if (pid > 0x1fff) {
/* 0x2000 is kernel virtual pid for whole ts (all pids) */
ret = 0;
goto err;
}
buf[0] = (pid >> 0) & 0xff;
buf[1] = (pid >> 8) & 0xff;
ret = regmap_bulk_write(state->regmap, 0xd505, buf, 2);
if (ret)
goto err;
ret = regmap_write(state->regmap, 0xd504, onoff << 5 | index << 0);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static struct dvb_frontend *af9013_get_dvb_frontend(struct i2c_client *client)
{
struct af9013_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &state->fe;
}
static struct i2c_adapter *af9013_get_i2c_adapter(struct i2c_client *client)
{
struct af9013_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return state->muxc->adapter[0];
}
/*
* XXX: Hackish solution. We use virtual register, reg bit 16, to carry info
* about i2c adapter locking. Own locking is needed because i2c mux call has
* already locked i2c adapter.
*/
static int af9013_select(struct i2c_mux_core *muxc, u32 chan)
{
struct af9013_state *state = i2c_mux_priv(muxc);
struct i2c_client *client = state->client;
int ret;
dev_dbg(&client->dev, "\n");
if (state->ts_mode == AF9013_TS_MODE_USB)
ret = regmap_update_bits(state->regmap, 0x1d417, 0x08, 0x08);
else
ret = regmap_update_bits(state->regmap, 0x1d607, 0x04, 0x04);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_deselect(struct i2c_mux_core *muxc, u32 chan)
{
struct af9013_state *state = i2c_mux_priv(muxc);
struct i2c_client *client = state->client;
int ret;
dev_dbg(&client->dev, "\n");
if (state->ts_mode == AF9013_TS_MODE_USB)
ret = regmap_update_bits(state->regmap, 0x1d417, 0x08, 0x00);
else
ret = regmap_update_bits(state->regmap, 0x1d607, 0x04, 0x00);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
/* Own I2C access routines needed for regmap as chip uses extra command byte */
static int af9013_wregs(struct i2c_client *client, u8 cmd, u16 reg,
const u8 *val, int len, u8 lock)
{
int ret;
u8 buf[21];
struct i2c_msg msg[1] = {
{
.addr = client->addr,
.flags = 0,
.len = 3 + len,
.buf = buf,
}
};
if (3 + len > sizeof(buf)) {
ret = -EINVAL;
goto err;
}
buf[0] = (reg >> 8) & 0xff;
buf[1] = (reg >> 0) & 0xff;
buf[2] = cmd;
memcpy(&buf[3], val, len);
if (lock)
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = __i2c_transfer(client->adapter, msg, 1);
if (lock)
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret < 0) {
goto err;
} else if (ret != 1) {
ret = -EREMOTEIO;
goto err;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_rregs(struct i2c_client *client, u8 cmd, u16 reg,
u8 *val, int len, u8 lock)
{
int ret;
u8 buf[3];
struct i2c_msg msg[2] = {
{
.addr = client->addr,
.flags = 0,
.len = 3,
.buf = buf,
}, {
.addr = client->addr,
.flags = I2C_M_RD,
.len = len,
.buf = val,
}
};
buf[0] = (reg >> 8) & 0xff;
buf[1] = (reg >> 0) & 0xff;
buf[2] = cmd;
if (lock)
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = __i2c_transfer(client->adapter, msg, 2);
if (lock)
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret < 0) {
goto err;
} else if (ret != 2) {
ret = -EREMOTEIO;
goto err;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_regmap_write(void *context, const void *data, size_t count)
{
struct i2c_client *client = context;
struct af9013_state *state = i2c_get_clientdata(client);
int ret, i;
u8 cmd;
u8 lock = !((u8 *)data)[0];
u16 reg = ((u8 *)data)[1] << 8 | ((u8 *)data)[2] << 0;
u8 *val = &((u8 *)data)[3];
const unsigned int len = count - 3;
if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) {
cmd = 0 << 7|0 << 6|(len - 1) << 2|1 << 1|1 << 0;
ret = af9013_wregs(client, cmd, reg, val, len, lock);
if (ret)
goto err;
} else if (reg >= 0x5100 && reg < 0x8fff) {
/* Firmware download */
cmd = 1 << 7|1 << 6|(len - 1) << 2|1 << 1|1 << 0;
ret = af9013_wregs(client, cmd, reg, val, len, lock);
if (ret)
goto err;
} else {
cmd = 0 << 7|0 << 6|(1 - 1) << 2|1 << 1|1 << 0;
for (i = 0; i < len; i++) {
ret = af9013_wregs(client, cmd, reg + i, val + i, 1,
lock);
if (ret)
goto err;
}
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_regmap_read(void *context, const void *reg_buf,
size_t reg_size, void *val_buf, size_t val_size)
{
struct i2c_client *client = context;
struct af9013_state *state = i2c_get_clientdata(client);
int ret, i;
u8 cmd;
u8 lock = !((u8 *)reg_buf)[0];
u16 reg = ((u8 *)reg_buf)[1] << 8 | ((u8 *)reg_buf)[2] << 0;
u8 *val = &((u8 *)val_buf)[0];
const unsigned int len = val_size;
if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) {
cmd = 0 << 7|0 << 6|(len - 1) << 2|1 << 1|0 << 0;
ret = af9013_rregs(client, cmd, reg, val_buf, len, lock);
if (ret)
goto err;
} else {
cmd = 0 << 7|0 << 6|(1 - 1) << 2|1 << 1|0 << 0;
for (i = 0; i < len; i++) {
ret = af9013_rregs(client, cmd, reg + i, val + i, 1,
lock);
if (ret)
goto err;
}
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_probe(struct i2c_client *client)
{
struct af9013_state *state;
struct af9013_platform_data *pdata = client->dev.platform_data;
struct dtv_frontend_properties *c;
int ret, i;
u8 firmware_version[4];
static const struct regmap_bus regmap_bus = {
.read = af9013_regmap_read,
.write = af9013_regmap_write,
};
static const struct regmap_config regmap_config = {
/* Actual reg is 16 bits, see i2c adapter lock */
.reg_bits = 24,
.val_bits = 8,
};
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state) {
ret = -ENOMEM;
goto err;
}
dev_dbg(&client->dev, "\n");
/* Setup the state */
state->client = client;
i2c_set_clientdata(client, state);
state->clk = pdata->clk;
state->tuner = pdata->tuner;
state->if_frequency = pdata->if_frequency;
state->ts_mode = pdata->ts_mode;
state->ts_output_pin = pdata->ts_output_pin;
state->spec_inv = pdata->spec_inv;
memcpy(&state->api_version, pdata->api_version, sizeof(state->api_version));
memcpy(&state->gpio, pdata->gpio, sizeof(state->gpio));
state->regmap = regmap_init(&client->dev, ®map_bus, client,
®map_config);
if (IS_ERR(state->regmap)) {
ret = PTR_ERR(state->regmap);
goto err_kfree;
}
/* Create mux i2c adapter */
state->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
af9013_select, af9013_deselect);
if (!state->muxc) {
ret = -ENOMEM;
goto err_regmap_exit;
}
state->muxc->priv = state;
ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
if (ret)
goto err_regmap_exit;
/* Download firmware */
if (state->ts_mode != AF9013_TS_MODE_USB) {
ret = af9013_download_firmware(state);
if (ret)
goto err_i2c_mux_del_adapters;
}
/* Firmware version */
ret = regmap_bulk_read(state->regmap, 0x5103, firmware_version,
sizeof(firmware_version));
if (ret)
goto err_i2c_mux_del_adapters;
/* Set GPIOs */
for (i = 0; i < sizeof(state->gpio); i++) {
ret = af9013_set_gpio(state, i, state->gpio[i]);
if (ret)
goto err_i2c_mux_del_adapters;
}
/* Create dvb frontend */
memcpy(&state->fe.ops, &af9013_ops, sizeof(state->fe.ops));
state->fe.demodulator_priv = state;
/* Setup callbacks */
pdata->get_dvb_frontend = af9013_get_dvb_frontend;
pdata->get_i2c_adapter = af9013_get_i2c_adapter;
pdata->pid_filter = af9013_pid_filter;
pdata->pid_filter_ctrl = af9013_pid_filter_ctrl;
/* Init stats to indicate which stats are supported */
c = &state->fe.dtv_property_cache;
c->strength.len = 1;
c->cnr.len = 1;
c->post_bit_error.len = 1;
c->post_bit_count.len = 1;
c->block_error.len = 1;
c->block_count.len = 1;
dev_info(&client->dev, "Afatech AF9013 successfully attached\n");
dev_info(&client->dev, "firmware version: %d.%d.%d.%d\n",
firmware_version[0], firmware_version[1],
firmware_version[2], firmware_version[3]);
return 0;
err_i2c_mux_del_adapters:
i2c_mux_del_adapters(state->muxc);
err_regmap_exit:
regmap_exit(state->regmap);
err_kfree:
kfree(state);
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static void af9013_remove(struct i2c_client *client)
{
struct af9013_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
i2c_mux_del_adapters(state->muxc);
regmap_exit(state->regmap);
kfree(state);
}
static const struct i2c_device_id af9013_id_table[] = {
{"af9013", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, af9013_id_table);
static struct i2c_driver af9013_driver = {
.driver = {
.name = "af9013",
.suppress_bind_attrs = true,
},
.probe = af9013_probe,
.remove = af9013_remove,
.id_table = af9013_id_table,
};
module_i2c_driver(af9013_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Afatech AF9013 DVB-T demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(AF9013_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/af9013.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for LG2160 - ATSC/MH
*
* Copyright (C) 2010 Michael Krufky <[email protected]>
*/
#include <linux/jiffies.h>
#include <linux/dvb/frontend.h>
#include "lg2160.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
#define DBG_INFO 1
#define DBG_REG 2
#define lg_printk(kern, fmt, arg...) \
printk(kern "%s: " fmt, __func__, ##arg)
#define lg_info(fmt, arg...) printk(KERN_INFO "lg2160: " fmt, ##arg)
#define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
#define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
#define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
lg_printk(KERN_DEBUG, fmt, ##arg)
#define lg_reg(fmt, arg...) if (debug & DBG_REG) \
lg_printk(KERN_DEBUG, fmt, ##arg)
#define lg_fail(ret) \
({ \
int __ret; \
__ret = (ret < 0); \
if (__ret) \
lg_err("error %d on line %d\n", ret, __LINE__); \
__ret; \
})
struct lg216x_state {
struct i2c_adapter *i2c_adap;
const struct lg2160_config *cfg;
struct dvb_frontend frontend;
u32 current_frequency;
u8 parade_id;
u8 fic_ver;
unsigned int last_reset;
};
/* ------------------------------------------------------------------------ */
static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val)
{
int ret;
u8 buf[] = { reg >> 8, reg & 0xff, val };
struct i2c_msg msg = {
.addr = state->cfg->i2c_addr, .flags = 0,
.buf = buf, .len = 3,
};
lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
if (ret != 1) {
lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
msg.buf[0], msg.buf[1], msg.buf[2], ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
return 0;
}
static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val)
{
int ret;
u8 reg_buf[] = { reg >> 8, reg & 0xff };
struct i2c_msg msg[] = {
{ .addr = state->cfg->i2c_addr,
.flags = 0, .buf = reg_buf, .len = 2 },
{ .addr = state->cfg->i2c_addr,
.flags = I2C_M_RD, .buf = val, .len = 1 },
};
lg_reg("reg: 0x%04x\n", reg);
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
lg_err("error (addr %02x reg %04x error (ret == %i)\n",
state->cfg->i2c_addr, reg, ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
return 0;
}
struct lg216x_reg {
u16 reg;
u8 val;
};
static int lg216x_write_regs(struct lg216x_state *state,
struct lg216x_reg *regs, int len)
{
int i, ret;
lg_reg("writing %d registers...\n", len);
for (i = 0; i < len; i++) {
ret = lg216x_write_reg(state, regs[i].reg, regs[i].val);
if (lg_fail(ret))
return ret;
}
return 0;
}
static int lg216x_set_reg_bit(struct lg216x_state *state,
u16 reg, int bit, int onoff)
{
u8 val;
int ret;
lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
ret = lg216x_read_reg(state, reg, &val);
if (lg_fail(ret))
goto fail;
val &= ~(1 << bit);
val |= (onoff & 1) << bit;
ret = lg216x_write_reg(state, reg, val);
lg_fail(ret);
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg216x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct lg216x_state *state = fe->demodulator_priv;
int ret;
if (state->cfg->deny_i2c_rptr)
return 0;
lg_dbg("(%d)\n", enable);
ret = lg216x_set_reg_bit(state, 0x0000, 0, enable ? 0 : 1);
msleep(1);
return ret;
}
static int lg216x_soft_reset(struct lg216x_state *state)
{
int ret;
lg_dbg("\n");
ret = lg216x_write_reg(state, 0x0002, 0x00);
if (lg_fail(ret))
goto fail;
msleep(20);
ret = lg216x_write_reg(state, 0x0002, 0x01);
if (lg_fail(ret))
goto fail;
state->last_reset = jiffies_to_msecs(jiffies);
fail:
return ret;
}
static int lg216x_initialize(struct lg216x_state *state)
{
int ret;
static struct lg216x_reg lg2160_init[] = {
#if 0
{ .reg = 0x0015, .val = 0xe6 },
#else
{ .reg = 0x0015, .val = 0xf7 },
{ .reg = 0x001b, .val = 0x52 },
{ .reg = 0x0208, .val = 0x00 },
{ .reg = 0x0209, .val = 0x82 },
{ .reg = 0x0210, .val = 0xf9 },
{ .reg = 0x020a, .val = 0x00 },
{ .reg = 0x020b, .val = 0x82 },
{ .reg = 0x020d, .val = 0x28 },
{ .reg = 0x020f, .val = 0x14 },
#endif
};
static struct lg216x_reg lg2161_init[] = {
{ .reg = 0x0000, .val = 0x41 },
{ .reg = 0x0001, .val = 0xfb },
{ .reg = 0x0216, .val = 0x00 },
{ .reg = 0x0219, .val = 0x00 },
{ .reg = 0x021b, .val = 0x55 },
{ .reg = 0x0606, .val = 0x0a },
};
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_write_regs(state,
lg2160_init, ARRAY_SIZE(lg2160_init));
break;
case LG2161:
ret = lg216x_write_regs(state,
lg2161_init, ARRAY_SIZE(lg2161_init));
break;
default:
ret = -EINVAL;
break;
}
if (lg_fail(ret))
goto fail;
ret = lg216x_soft_reset(state);
lg_fail(ret);
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg216x_set_if(struct lg216x_state *state)
{
u8 val;
int ret;
lg_dbg("%d KHz\n", state->cfg->if_khz);
ret = lg216x_read_reg(state, 0x0132, &val);
if (lg_fail(ret))
goto fail;
val &= 0xfb;
val |= (0 == state->cfg->if_khz) ? 0x04 : 0x00;
ret = lg216x_write_reg(state, 0x0132, val);
lg_fail(ret);
/* if NOT zero IF, 6 MHz is the default */
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg2160_agc_fix(struct lg216x_state *state,
int if_agc_fix, int rf_agc_fix)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0100, &val);
if (lg_fail(ret))
goto fail;
val &= 0xf3;
val |= (if_agc_fix) ? 0x08 : 0x00;
val |= (rf_agc_fix) ? 0x04 : 0x00;
ret = lg216x_write_reg(state, 0x0100, val);
lg_fail(ret);
fail:
return ret;
}
#if 0
static int lg2160_agc_freeze(struct lg216x_state *state,
int if_agc_freeze, int rf_agc_freeze)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0100, &val);
if (lg_fail(ret))
goto fail;
val &= 0xcf;
val |= (if_agc_freeze) ? 0x20 : 0x00;
val |= (rf_agc_freeze) ? 0x10 : 0x00;
ret = lg216x_write_reg(state, 0x0100, val);
lg_fail(ret);
fail:
return ret;
}
#endif
static int lg2160_agc_polarity(struct lg216x_state *state,
int if_agc_polarity, int rf_agc_polarity)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0100, &val);
if (lg_fail(ret))
goto fail;
val &= 0xfc;
val |= (if_agc_polarity) ? 0x02 : 0x00;
val |= (rf_agc_polarity) ? 0x01 : 0x00;
ret = lg216x_write_reg(state, 0x0100, val);
lg_fail(ret);
fail:
return ret;
}
static int lg2160_tuner_pwr_save_polarity(struct lg216x_state *state,
int polarity)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0008, &val);
if (lg_fail(ret))
goto fail;
val &= 0xfe;
val |= (polarity) ? 0x01 : 0x00;
ret = lg216x_write_reg(state, 0x0008, val);
lg_fail(ret);
fail:
return ret;
}
static int lg2160_spectrum_polarity(struct lg216x_state *state,
int inverted)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0132, &val);
if (lg_fail(ret))
goto fail;
val &= 0xfd;
val |= (inverted) ? 0x02 : 0x00;
ret = lg216x_write_reg(state, 0x0132, val);
lg_fail(ret);
fail:
return lg216x_soft_reset(state);
}
static int lg2160_tuner_pwr_save(struct lg216x_state *state, int onoff)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0007, &val);
if (lg_fail(ret))
goto fail;
val &= 0xbf;
val |= (onoff) ? 0x40 : 0x00;
ret = lg216x_write_reg(state, 0x0007, val);
lg_fail(ret);
fail:
return ret;
}
static int lg216x_set_parade(struct lg216x_state *state, int id)
{
int ret;
ret = lg216x_write_reg(state, 0x013e, id & 0x7f);
if (lg_fail(ret))
goto fail;
state->parade_id = id & 0x7f;
fail:
return ret;
}
static int lg216x_set_ensemble(struct lg216x_state *state, int id)
{
int ret;
u16 reg;
u8 val;
switch (state->cfg->lg_chip) {
case LG2160:
reg = 0x0400;
break;
case LG2161:
default:
reg = 0x0500;
break;
}
ret = lg216x_read_reg(state, reg, &val);
if (lg_fail(ret))
goto fail;
val &= 0xfe;
val |= (id) ? 0x01 : 0x00;
ret = lg216x_write_reg(state, reg, val);
lg_fail(ret);
fail:
return ret;
}
static int lg2160_set_spi_clock(struct lg216x_state *state)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0014, &val);
if (lg_fail(ret))
goto fail;
val &= 0xf3;
val |= (state->cfg->spi_clock << 2);
ret = lg216x_write_reg(state, 0x0014, val);
lg_fail(ret);
fail:
return ret;
}
static int lg2161_set_output_interface(struct lg216x_state *state)
{
u8 val;
int ret;
ret = lg216x_read_reg(state, 0x0014, &val);
if (lg_fail(ret))
goto fail;
val &= ~0x07;
val |= state->cfg->output_if; /* FIXME: needs sanity check */
ret = lg216x_write_reg(state, 0x0014, val);
lg_fail(ret);
fail:
return ret;
}
static int lg216x_enable_fic(struct lg216x_state *state, int onoff)
{
int ret;
ret = lg216x_write_reg(state, 0x0017, 0x23);
if (lg_fail(ret))
goto fail;
ret = lg216x_write_reg(state, 0x0016, 0xfc);
if (lg_fail(ret))
goto fail;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_write_reg(state, 0x0016,
0xfc | ((onoff) ? 0x02 : 0x00));
break;
case LG2161:
ret = lg216x_write_reg(state, 0x0016, (onoff) ? 0x10 : 0x00);
break;
}
if (lg_fail(ret))
goto fail;
ret = lg216x_initialize(state);
if (lg_fail(ret))
goto fail;
if (onoff) {
ret = lg216x_write_reg(state, 0x0017, 0x03);
lg_fail(ret);
}
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg216x_get_fic_version(struct lg216x_state *state, u8 *ficver)
{
u8 val;
int ret;
*ficver = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0128, &val);
if (lg_fail(ret))
goto fail;
*ficver = (val >> 3) & 0x1f;
fail:
return ret;
}
#if 0
static int lg2160_get_parade_id(struct lg216x_state *state, u8 *id)
{
u8 val;
int ret;
*id = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0123, &val);
if (lg_fail(ret))
goto fail;
*id = val & 0x7f;
fail:
return ret;
}
#endif
static int lg216x_get_nog(struct lg216x_state *state, u8 *nog)
{
u8 val;
int ret;
*nog = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0124, &val);
if (lg_fail(ret))
goto fail;
*nog = ((val >> 4) & 0x07) + 1;
fail:
return ret;
}
static int lg216x_get_tnog(struct lg216x_state *state, u8 *tnog)
{
u8 val;
int ret;
*tnog = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0125, &val);
if (lg_fail(ret))
goto fail;
*tnog = val & 0x1f;
fail:
return ret;
}
static int lg216x_get_sgn(struct lg216x_state *state, u8 *sgn)
{
u8 val;
int ret;
*sgn = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0124, &val);
if (lg_fail(ret))
goto fail;
*sgn = val & 0x0f;
fail:
return ret;
}
static int lg216x_get_prc(struct lg216x_state *state, u8 *prc)
{
u8 val;
int ret;
*prc = 0xff; /* invalid value */
ret = lg216x_read_reg(state, 0x0125, &val);
if (lg_fail(ret))
goto fail;
*prc = ((val >> 5) & 0x07) + 1;
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg216x_get_rs_frame_mode(struct lg216x_state *state,
enum atscmh_rs_frame_mode *rs_framemode)
{
u8 val;
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0410, &val);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x0513, &val);
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
switch ((val >> 4) & 0x03) {
#if 1
default:
#endif
case 0x00:
*rs_framemode = ATSCMH_RSFRAME_PRI_ONLY;
break;
case 0x01:
*rs_framemode = ATSCMH_RSFRAME_PRI_SEC;
break;
#if 0
default:
*rs_framemode = ATSCMH_RSFRAME_RES;
break;
#endif
}
fail:
return ret;
}
static
int lg216x_get_rs_frame_ensemble(struct lg216x_state *state,
enum atscmh_rs_frame_ensemble *rs_frame_ens)
{
u8 val;
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0400, &val);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x0500, &val);
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
val &= 0x01;
*rs_frame_ens = (enum atscmh_rs_frame_ensemble) val;
fail:
return ret;
}
static int lg216x_get_rs_code_mode(struct lg216x_state *state,
enum atscmh_rs_code_mode *rs_code_pri,
enum atscmh_rs_code_mode *rs_code_sec)
{
u8 val;
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0410, &val);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x0513, &val);
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
*rs_code_pri = (enum atscmh_rs_code_mode) ((val >> 2) & 0x03);
*rs_code_sec = (enum atscmh_rs_code_mode) (val & 0x03);
fail:
return ret;
}
static int lg216x_get_sccc_block_mode(struct lg216x_state *state,
enum atscmh_sccc_block_mode *sccc_block)
{
u8 val;
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0315, &val);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x0511, &val);
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
switch (val & 0x03) {
case 0x00:
*sccc_block = ATSCMH_SCCC_BLK_SEP;
break;
case 0x01:
*sccc_block = ATSCMH_SCCC_BLK_COMB;
break;
default:
*sccc_block = ATSCMH_SCCC_BLK_RES;
break;
}
fail:
return ret;
}
static int lg216x_get_sccc_code_mode(struct lg216x_state *state,
enum atscmh_sccc_code_mode *mode_a,
enum atscmh_sccc_code_mode *mode_b,
enum atscmh_sccc_code_mode *mode_c,
enum atscmh_sccc_code_mode *mode_d)
{
u8 val;
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0316, &val);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x0512, &val);
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
switch ((val >> 6) & 0x03) {
case 0x00:
*mode_a = ATSCMH_SCCC_CODE_HLF;
break;
case 0x01:
*mode_a = ATSCMH_SCCC_CODE_QTR;
break;
default:
*mode_a = ATSCMH_SCCC_CODE_RES;
break;
}
switch ((val >> 4) & 0x03) {
case 0x00:
*mode_b = ATSCMH_SCCC_CODE_HLF;
break;
case 0x01:
*mode_b = ATSCMH_SCCC_CODE_QTR;
break;
default:
*mode_b = ATSCMH_SCCC_CODE_RES;
break;
}
switch ((val >> 2) & 0x03) {
case 0x00:
*mode_c = ATSCMH_SCCC_CODE_HLF;
break;
case 0x01:
*mode_c = ATSCMH_SCCC_CODE_QTR;
break;
default:
*mode_c = ATSCMH_SCCC_CODE_RES;
break;
}
switch (val & 0x03) {
case 0x00:
*mode_d = ATSCMH_SCCC_CODE_HLF;
break;
case 0x01:
*mode_d = ATSCMH_SCCC_CODE_QTR;
break;
default:
*mode_d = ATSCMH_SCCC_CODE_RES;
break;
}
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
#if 0
static int lg216x_read_fic_err_count(struct lg216x_state *state, u8 *err)
{
u8 fic_err;
int ret;
*err = 0;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg216x_read_reg(state, 0x0012, &fic_err);
break;
case LG2161:
ret = lg216x_read_reg(state, 0x001e, &fic_err);
break;
}
if (lg_fail(ret))
goto fail;
*err = fic_err;
fail:
return ret;
}
static int lg2160_read_crc_err_count(struct lg216x_state *state, u16 *err)
{
u8 crc_err1, crc_err2;
int ret;
*err = 0;
ret = lg216x_read_reg(state, 0x0411, &crc_err1);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_reg(state, 0x0412, &crc_err2);
if (lg_fail(ret))
goto fail;
*err = (u16)(((crc_err2 & 0x0f) << 8) | crc_err1);
fail:
return ret;
}
static int lg2161_read_crc_err_count(struct lg216x_state *state, u16 *err)
{
u8 crc_err;
int ret;
*err = 0;
ret = lg216x_read_reg(state, 0x0612, &crc_err);
if (lg_fail(ret))
goto fail;
*err = (u16)crc_err;
fail:
return ret;
}
static int lg216x_read_crc_err_count(struct lg216x_state *state, u16 *err)
{
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg2160_read_crc_err_count(state, err);
break;
case LG2161:
ret = lg2161_read_crc_err_count(state, err);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int lg2160_read_rs_err_count(struct lg216x_state *state, u16 *err)
{
u8 rs_err1, rs_err2;
int ret;
*err = 0;
ret = lg216x_read_reg(state, 0x0413, &rs_err1);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_reg(state, 0x0414, &rs_err2);
if (lg_fail(ret))
goto fail;
*err = (u16)(((rs_err2 & 0x0f) << 8) | rs_err1);
fail:
return ret;
}
static int lg2161_read_rs_err_count(struct lg216x_state *state, u16 *err)
{
u8 rs_err1, rs_err2;
int ret;
*err = 0;
ret = lg216x_read_reg(state, 0x0613, &rs_err1);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_reg(state, 0x0614, &rs_err2);
if (lg_fail(ret))
goto fail;
*err = (u16)((rs_err1 << 8) | rs_err2);
fail:
return ret;
}
static int lg216x_read_rs_err_count(struct lg216x_state *state, u16 *err)
{
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg2160_read_rs_err_count(state, err);
break;
case LG2161:
ret = lg2161_read_rs_err_count(state, err);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
#endif
/* ------------------------------------------------------------------------ */
static int lg216x_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct lg216x_state *state = fe->demodulator_priv;
int ret;
lg_dbg("\n");
c->modulation = VSB_8;
c->frequency = state->current_frequency;
c->delivery_system = SYS_ATSCMH;
ret = lg216x_get_fic_version(state,
&c->atscmh_fic_ver);
if (lg_fail(ret))
goto fail;
if (state->fic_ver != c->atscmh_fic_ver) {
state->fic_ver = c->atscmh_fic_ver;
#if 0
ret = lg2160_get_parade_id(state,
&c->atscmh_parade_id);
if (lg_fail(ret))
goto fail;
/* #else */
c->atscmh_parade_id = state->parade_id;
#endif
ret = lg216x_get_nog(state,
&c->atscmh_nog);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_tnog(state,
&c->atscmh_tnog);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_sgn(state,
&c->atscmh_sgn);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_prc(state,
&c->atscmh_prc);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_rs_frame_mode(state,
(enum atscmh_rs_frame_mode *)
&c->atscmh_rs_frame_mode);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_rs_frame_ensemble(state,
(enum atscmh_rs_frame_ensemble *)
&c->atscmh_rs_frame_ensemble);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_rs_code_mode(state,
(enum atscmh_rs_code_mode *)
&c->atscmh_rs_code_mode_pri,
(enum atscmh_rs_code_mode *)
&c->atscmh_rs_code_mode_sec);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_sccc_block_mode(state,
(enum atscmh_sccc_block_mode *)
&c->atscmh_sccc_block_mode);
if (lg_fail(ret))
goto fail;
ret = lg216x_get_sccc_code_mode(state,
(enum atscmh_sccc_code_mode *)
&c->atscmh_sccc_code_mode_a,
(enum atscmh_sccc_code_mode *)
&c->atscmh_sccc_code_mode_b,
(enum atscmh_sccc_code_mode *)
&c->atscmh_sccc_code_mode_c,
(enum atscmh_sccc_code_mode *)
&c->atscmh_sccc_code_mode_d);
if (lg_fail(ret))
goto fail;
}
#if 0
ret = lg216x_read_fic_err_count(state,
(u8 *)&c->atscmh_fic_err);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_crc_err_count(state,
&c->atscmh_crc_err);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_rs_err_count(state,
&c->atscmh_rs_err);
if (lg_fail(ret))
goto fail;
switch (state->cfg->lg_chip) {
case LG2160:
if (((c->atscmh_rs_err >= 240) &&
(c->atscmh_crc_err >= 240)) &&
((jiffies_to_msecs(jiffies) - state->last_reset) > 6000))
ret = lg216x_soft_reset(state);
break;
case LG2161:
/* no fix needed here (as far as we know) */
ret = 0;
break;
}
lg_fail(ret);
#endif
fail:
return ret;
}
static int lg2160_set_frontend(struct dvb_frontend *fe)
{
struct lg216x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
lg_dbg("(%d)\n", fe->dtv_property_cache.frequency);
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (lg_fail(ret))
goto fail;
state->current_frequency = fe->dtv_property_cache.frequency;
}
ret = lg2160_agc_fix(state, 0, 0);
if (lg_fail(ret))
goto fail;
ret = lg2160_agc_polarity(state, 0, 0);
if (lg_fail(ret))
goto fail;
ret = lg2160_tuner_pwr_save_polarity(state, 1);
if (lg_fail(ret))
goto fail;
ret = lg216x_set_if(state);
if (lg_fail(ret))
goto fail;
ret = lg2160_spectrum_polarity(state, state->cfg->spectral_inversion);
if (lg_fail(ret))
goto fail;
/* be tuned before this point */
ret = lg216x_soft_reset(state);
if (lg_fail(ret))
goto fail;
ret = lg2160_tuner_pwr_save(state, 0);
if (lg_fail(ret))
goto fail;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg2160_set_spi_clock(state);
if (lg_fail(ret))
goto fail;
break;
case LG2161:
ret = lg2161_set_output_interface(state);
if (lg_fail(ret))
goto fail;
break;
}
ret = lg216x_set_parade(state, fe->dtv_property_cache.atscmh_parade_id);
if (lg_fail(ret))
goto fail;
ret = lg216x_set_ensemble(state,
fe->dtv_property_cache.atscmh_rs_frame_ensemble);
if (lg_fail(ret))
goto fail;
ret = lg216x_initialize(state);
if (lg_fail(ret))
goto fail;
ret = lg216x_enable_fic(state, 1);
lg_fail(ret);
lg216x_get_frontend(fe, c);
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg2160_read_lock_status(struct lg216x_state *state,
int *acq_lock, int *sync_lock)
{
u8 val;
int ret;
*acq_lock = 0;
*sync_lock = 0;
ret = lg216x_read_reg(state, 0x011b, &val);
if (lg_fail(ret))
goto fail;
*sync_lock = (val & 0x20) ? 0 : 1;
*acq_lock = (val & 0x40) ? 0 : 1;
fail:
return ret;
}
#ifdef USE_LG2161_LOCK_BITS
static int lg2161_read_lock_status(struct lg216x_state *state,
int *acq_lock, int *sync_lock)
{
u8 val;
int ret;
*acq_lock = 0;
*sync_lock = 0;
ret = lg216x_read_reg(state, 0x0304, &val);
if (lg_fail(ret))
goto fail;
*sync_lock = (val & 0x80) ? 0 : 1;
ret = lg216x_read_reg(state, 0x011b, &val);
if (lg_fail(ret))
goto fail;
*acq_lock = (val & 0x40) ? 0 : 1;
fail:
return ret;
}
#endif
static int lg216x_read_lock_status(struct lg216x_state *state,
int *acq_lock, int *sync_lock)
{
#ifdef USE_LG2161_LOCK_BITS
int ret;
switch (state->cfg->lg_chip) {
case LG2160:
ret = lg2160_read_lock_status(state, acq_lock, sync_lock);
break;
case LG2161:
ret = lg2161_read_lock_status(state, acq_lock, sync_lock);
break;
default:
ret = -EINVAL;
break;
}
return ret;
#else
return lg2160_read_lock_status(state, acq_lock, sync_lock);
#endif
}
static int lg216x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct lg216x_state *state = fe->demodulator_priv;
int ret, acq_lock, sync_lock;
*status = 0;
ret = lg216x_read_lock_status(state, &acq_lock, &sync_lock);
if (lg_fail(ret))
goto fail;
lg_dbg("%s%s\n",
acq_lock ? "SIGNALEXIST " : "",
sync_lock ? "SYNCLOCK" : "");
if (acq_lock)
*status |= FE_HAS_SIGNAL;
if (sync_lock)
*status |= FE_HAS_SYNC;
if (*status)
*status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lg2160_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lg216x_state *state = fe->demodulator_priv;
u8 snr1, snr2;
int ret;
*snr = 0;
ret = lg216x_read_reg(state, 0x0202, &snr1);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_reg(state, 0x0203, &snr2);
if (lg_fail(ret))
goto fail;
if ((snr1 == 0xba) || (snr2 == 0xdf))
*snr = 0;
else
#if 1
*snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 >> 4);
#else /* BCD */
*snr = (snr2 | (snr1 << 8));
#endif
fail:
return ret;
}
static int lg2161_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lg216x_state *state = fe->demodulator_priv;
u8 snr1, snr2;
int ret;
*snr = 0;
ret = lg216x_read_reg(state, 0x0302, &snr1);
if (lg_fail(ret))
goto fail;
ret = lg216x_read_reg(state, 0x0303, &snr2);
if (lg_fail(ret))
goto fail;
if ((snr1 == 0xba) || (snr2 == 0xfd))
*snr = 0;
else
*snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 & 0x0f);
fail:
return ret;
}
static int lg216x_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
#if 0
/* borrowed from lgdt330x.c
*
* Calculate strength from SNR up to 35dB
* Even though the SNR can go higher than 35dB,
* there is some comfort factor in having a range of
* strong signals that can show at 100%
*/
struct lg216x_state *state = fe->demodulator_priv;
u16 snr;
int ret;
#endif
*strength = 0;
#if 0
ret = fe->ops.read_snr(fe, &snr);
if (lg_fail(ret))
goto fail;
/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
/* scale the range 0 - 35*2^24 into 0 - 65535 */
if (state->snr >= 8960 * 0x10000)
*strength = 0xffff;
else
*strength = state->snr / 8960;
fail:
return ret;
#else
return 0;
#endif
}
/* ------------------------------------------------------------------------ */
static int lg216x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
#if 0
struct lg216x_state *state = fe->demodulator_priv;
int ret;
ret = lg216x_read_rs_err_count(state,
&fe->dtv_property_cache.atscmh_rs_err);
if (lg_fail(ret))
goto fail;
*ucblocks = fe->dtv_property_cache.atscmh_rs_err;
fail:
#else
*ucblocks = 0;
#endif
return 0;
}
static int lg216x_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings
*fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 500;
lg_dbg("\n");
return 0;
}
static void lg216x_release(struct dvb_frontend *fe)
{
struct lg216x_state *state = fe->demodulator_priv;
lg_dbg("\n");
kfree(state);
}
static const struct dvb_frontend_ops lg2160_ops = {
.delsys = { SYS_ATSCMH },
.info = {
.name = "LG Electronics LG2160 ATSC/MH Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
},
.i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
#if 0
.init = lg216x_init,
.sleep = lg216x_sleep,
#endif
.set_frontend = lg2160_set_frontend,
.get_frontend = lg216x_get_frontend,
.get_tune_settings = lg216x_get_tune_settings,
.read_status = lg216x_read_status,
#if 0
.read_ber = lg216x_read_ber,
#endif
.read_signal_strength = lg216x_read_signal_strength,
.read_snr = lg2160_read_snr,
.read_ucblocks = lg216x_read_ucblocks,
.release = lg216x_release,
};
static const struct dvb_frontend_ops lg2161_ops = {
.delsys = { SYS_ATSCMH },
.info = {
.name = "LG Electronics LG2161 ATSC/MH Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
},
.i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
#if 0
.init = lg216x_init,
.sleep = lg216x_sleep,
#endif
.set_frontend = lg2160_set_frontend,
.get_frontend = lg216x_get_frontend,
.get_tune_settings = lg216x_get_tune_settings,
.read_status = lg216x_read_status,
#if 0
.read_ber = lg216x_read_ber,
#endif
.read_signal_strength = lg216x_read_signal_strength,
.read_snr = lg2161_read_snr,
.read_ucblocks = lg216x_read_ucblocks,
.release = lg216x_release,
};
struct dvb_frontend *lg2160_attach(const struct lg2160_config *config,
struct i2c_adapter *i2c_adap)
{
struct lg216x_state *state = NULL;
lg_dbg("(%d-%04x)\n",
i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
config ? config->i2c_addr : 0);
state = kzalloc(sizeof(struct lg216x_state), GFP_KERNEL);
if (!state)
return NULL;
state->cfg = config;
state->i2c_adap = i2c_adap;
state->fic_ver = 0xff;
state->parade_id = 0xff;
switch (config->lg_chip) {
default:
lg_warn("invalid chip requested, defaulting to LG2160");
fallthrough;
case LG2160:
memcpy(&state->frontend.ops, &lg2160_ops,
sizeof(struct dvb_frontend_ops));
break;
case LG2161:
memcpy(&state->frontend.ops, &lg2161_ops,
sizeof(struct dvb_frontend_ops));
break;
}
state->frontend.demodulator_priv = state;
state->current_frequency = -1;
/* parade 1 by default */
state->frontend.dtv_property_cache.atscmh_parade_id = 1;
return &state->frontend;
}
EXPORT_SYMBOL_GPL(lg2160_attach);
MODULE_DESCRIPTION("LG Electronics LG216x ATSC/MH Demodulator Driver");
MODULE_AUTHOR("Michael Krufky <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.3");
| linux-master | drivers/media/dvb-frontends/lg2160.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
driver for LSI L64781 COFDM demodulator
Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
Marko Kohtala <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "l64781.h"
struct l64781_state {
struct i2c_adapter* i2c;
const struct l64781_config* config;
struct dvb_frontend frontend;
/* private demodulator data */
unsigned int first:1;
};
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "l64781: " args); \
} while (0)
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
{
int ret;
u8 buf [] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
__func__, reg, ret);
return (ret != 1) ? -1 : 0;
}
static int l64781_readreg (struct l64781_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) return ret;
return b1[0];
}
static void apply_tps (struct l64781_state* state)
{
l64781_writereg (state, 0x2a, 0x00);
l64781_writereg (state, 0x2a, 0x01);
/* This here is a little bit questionable because it enables
the automatic update of TPS registers. I think we'd need to
handle the IRQ from FE to update some other registers as
well, or at least implement some magic to tuning to correct
to the TPS received from transmission. */
l64781_writereg (state, 0x2a, 0x02);
}
static void reset_afc (struct l64781_state* state)
{
/* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
timing offset */
l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
l64781_writereg (state, 0x09, 0);
l64781_writereg (state, 0x0a, 0);
l64781_writereg (state, 0x07, 0x8e);
l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
l64781_writereg (state, 0x11, 0x80); /* stall TIM */
l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
l64781_writereg (state, 0x12, 0);
l64781_writereg (state, 0x13, 0);
l64781_writereg (state, 0x11, 0x00);
}
static int reset_and_configure (struct l64781_state* state)
{
u8 buf [] = { 0x06 };
struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
// NOTE: this is correct in writing to address 0x00
return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
}
static int apply_frontend_param(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct l64781_state* state = fe->demodulator_priv;
/* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
/* QPSK, QAM_16, QAM_64 */
static const u8 qam_tab [] = { 2, 4, 0, 6 };
static const u8 guard_tab [] = { 1, 2, 4, 8 };
/* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
static const u32 ppm = 8000;
u32 ddfs_offset_fixed;
/* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
/* bw_tab[p->bandWidth]<<10)/15625; */
u32 init_freq;
u32 spi_bias;
u8 val0x04;
u8 val0x05;
u8 val0x06;
int bw;
switch (p->bandwidth_hz) {
case 8000000:
bw = 8;
break;
case 7000000:
bw = 7;
break;
case 6000000:
bw = 6;
break;
default:
return -EINVAL;
}
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
if (p->inversion != INVERSION_ON &&
p->inversion != INVERSION_OFF)
return -EINVAL;
if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
p->code_rate_HP != FEC_7_8)
return -EINVAL;
if (p->hierarchy != HIERARCHY_NONE &&
(p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
p->code_rate_LP != FEC_7_8))
return -EINVAL;
if (p->modulation != QPSK && p->modulation != QAM_16 &&
p->modulation != QAM_64)
return -EINVAL;
if (p->transmission_mode != TRANSMISSION_MODE_2K &&
p->transmission_mode != TRANSMISSION_MODE_8K)
return -EINVAL;
if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
p->guard_interval > GUARD_INTERVAL_1_4)
return -EINVAL;
if ((int)p->hierarchy < HIERARCHY_NONE ||
p->hierarchy > HIERARCHY_4)
return -EINVAL;
ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
/* This works up to 20000 ppm, it overflows if too large ppm! */
init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
bw & 0xFFFFFF);
/* SPI bias calculation is slightly modified to fit in 32bit */
/* will work for high ppm only... */
spi_bias = 378 * (1 << 10);
spi_bias *= 16;
spi_bias *= bw;
spi_bias *= qam_tab[p->modulation];
spi_bias /= p->code_rate_HP + 1;
spi_bias /= (guard_tab[p->guard_interval] + 32);
spi_bias *= 1000;
spi_bias /= 1000 + ppm/1000;
spi_bias *= p->code_rate_HP;
val0x04 = (p->transmission_mode << 2) | p->guard_interval;
val0x05 = fec_tab[p->code_rate_HP];
if (p->hierarchy != HIERARCHY_NONE)
val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
val0x06 = (p->hierarchy << 2) | p->modulation;
l64781_writereg (state, 0x04, val0x04);
l64781_writereg (state, 0x05, val0x05);
l64781_writereg (state, 0x06, val0x06);
reset_afc (state);
/* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
l64781_writereg (state, 0x15,
p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
l64781_writereg (state, 0x16, init_freq & 0xff);
l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
l64781_writereg (state, 0x1b, spi_bias & 0xff);
l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
(p->inversion == INVERSION_ON ? 0x80 : 0x00));
l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
l64781_readreg (state, 0x00); /* clear interrupt registers... */
l64781_readreg (state, 0x01); /* dto. */
apply_tps (state);
return 0;
}
static int get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct l64781_state* state = fe->demodulator_priv;
int tmp;
tmp = l64781_readreg(state, 0x04);
switch(tmp & 3) {
case 0:
p->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
p->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
p->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
p->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch((tmp >> 2) & 3) {
case 0:
p->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
p->transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
printk(KERN_WARNING "Unexpected value for transmission_mode\n");
}
tmp = l64781_readreg(state, 0x05);
switch(tmp & 7) {
case 0:
p->code_rate_HP = FEC_1_2;
break;
case 1:
p->code_rate_HP = FEC_2_3;
break;
case 2:
p->code_rate_HP = FEC_3_4;
break;
case 3:
p->code_rate_HP = FEC_5_6;
break;
case 4:
p->code_rate_HP = FEC_7_8;
break;
default:
printk("Unexpected value for code_rate_HP\n");
}
switch((tmp >> 3) & 7) {
case 0:
p->code_rate_LP = FEC_1_2;
break;
case 1:
p->code_rate_LP = FEC_2_3;
break;
case 2:
p->code_rate_LP = FEC_3_4;
break;
case 3:
p->code_rate_LP = FEC_5_6;
break;
case 4:
p->code_rate_LP = FEC_7_8;
break;
default:
printk("Unexpected value for code_rate_LP\n");
}
tmp = l64781_readreg(state, 0x06);
switch(tmp & 3) {
case 0:
p->modulation = QPSK;
break;
case 1:
p->modulation = QAM_16;
break;
case 2:
p->modulation = QAM_64;
break;
default:
printk(KERN_WARNING "Unexpected value for modulation\n");
}
switch((tmp >> 2) & 7) {
case 0:
p->hierarchy = HIERARCHY_NONE;
break;
case 1:
p->hierarchy = HIERARCHY_1;
break;
case 2:
p->hierarchy = HIERARCHY_2;
break;
case 3:
p->hierarchy = HIERARCHY_4;
break;
default:
printk("Unexpected value for hierarchy\n");
}
tmp = l64781_readreg (state, 0x1d);
p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
tmp = (int) (l64781_readreg (state, 0x08) |
(l64781_readreg (state, 0x09) << 8) |
(l64781_readreg (state, 0x0a) << 16));
p->frequency += tmp;
return 0;
}
static int l64781_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct l64781_state* state = fe->demodulator_priv;
int sync = l64781_readreg (state, 0x32);
int gain = l64781_readreg (state, 0x0e);
l64781_readreg (state, 0x00); /* clear interrupt registers... */
l64781_readreg (state, 0x01); /* dto. */
*status = 0;
if (gain > 5)
*status |= FE_HAS_SIGNAL;
if (sync & 0x02) /* VCXO locked, this criteria should be ok */
*status |= FE_HAS_CARRIER;
if (sync & 0x20)
*status |= FE_HAS_VITERBI;
if (sync & 0x40)
*status |= FE_HAS_SYNC;
if (sync == 0x7f)
*status |= FE_HAS_LOCK;
return 0;
}
static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct l64781_state* state = fe->demodulator_priv;
/* XXX FIXME: set up counting period (reg 0x26...0x28)
*/
*ber = l64781_readreg (state, 0x39)
| (l64781_readreg (state, 0x3a) << 8);
return 0;
}
static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
struct l64781_state* state = fe->demodulator_priv;
u8 gain = l64781_readreg (state, 0x0e);
*signal_strength = (gain << 8) | gain;
return 0;
}
static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct l64781_state* state = fe->demodulator_priv;
u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
*snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
return 0;
}
static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct l64781_state* state = fe->demodulator_priv;
*ucblocks = l64781_readreg (state, 0x37)
| (l64781_readreg (state, 0x38) << 8);
return 0;
}
static int l64781_sleep(struct dvb_frontend* fe)
{
struct l64781_state* state = fe->demodulator_priv;
/* Power down */
return l64781_writereg (state, 0x3e, 0x5a);
}
static int l64781_init(struct dvb_frontend* fe)
{
struct l64781_state* state = fe->demodulator_priv;
reset_and_configure (state);
/* Power up */
l64781_writereg (state, 0x3e, 0xa5);
/* Reset hard */
l64781_writereg (state, 0x2a, 0x04);
l64781_writereg (state, 0x2a, 0x00);
/* Set tuner specific things */
/* AFC_POL, set also in reset_afc */
l64781_writereg (state, 0x07, 0x8e);
/* Use internal ADC */
l64781_writereg (state, 0x0b, 0x81);
/* AGC loop gain, and polarity is positive */
l64781_writereg (state, 0x0c, 0x84);
/* Internal ADC outputs two's complement */
l64781_writereg (state, 0x0d, 0x8c);
/* With ppm=8000, it seems the DTR_SENSITIVITY will result in
value of 2 with all possible bandwidths and guard
intervals, which is the initial value anyway. */
/*l64781_writereg (state, 0x19, 0x92);*/
/* Everything is two's complement, soft bit and CSI_OUT too */
l64781_writereg (state, 0x1e, 0x09);
/* delay a bit after first init attempt */
if (state->first) {
state->first = 0;
msleep(200);
}
return 0;
}
static int l64781_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 4000;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void l64781_release(struct dvb_frontend* fe)
{
struct l64781_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops l64781_ops;
struct dvb_frontend* l64781_attach(const struct l64781_config* config,
struct i2c_adapter* i2c)
{
struct l64781_state* state = NULL;
int reg0x3e = -1;
u8 b0 [] = { 0x1a };
u8 b1 [] = { 0x00 };
struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->first = 1;
/*
* the L64781 won't show up before we send the reset_and_configure()
* broadcast. If nothing responds there is no L64781 on the bus...
*/
if (reset_and_configure(state) < 0) {
dprintk("No response to reset and configure broadcast...\n");
goto error;
}
/* The chip always responds to reads */
if (i2c_transfer(state->i2c, msg, 2) != 2) {
dprintk("No response to read on I2C bus\n");
goto error;
}
/* Save current register contents for bailout */
reg0x3e = l64781_readreg(state, 0x3e);
/* Reading the POWER_DOWN register always returns 0 */
if (reg0x3e != 0) {
dprintk("Device doesn't look like L64781\n");
goto error;
}
/* Turn the chip off */
l64781_writereg (state, 0x3e, 0x5a);
/* Responds to all reads with 0 */
if (l64781_readreg(state, 0x1a) != 0) {
dprintk("Read 1 returned unexpected value\n");
goto error;
}
/* Turn the chip on */
l64781_writereg (state, 0x3e, 0xa5);
/* Responds with register default value */
if (l64781_readreg(state, 0x1a) != 0xa1) {
dprintk("Read 2 returned unexpected value\n");
goto error;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
if (reg0x3e >= 0)
l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops l64781_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "LSI L64781 DVB-T",
/* .frequency_min_hz = ???,*/
/* .frequency_max_hz = ???,*/
.frequency_stepsize_hz = 166666,
/* .symbol_rate_tolerance = ???,*/
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_MUTE_TS
},
.release = l64781_release,
.init = l64781_init,
.sleep = l64781_sleep,
.set_frontend = apply_frontend_param,
.get_frontend = get_frontend,
.get_tune_settings = l64781_get_tune_settings,
.read_status = l64781_read_status,
.read_ber = l64781_read_ber,
.read_signal_strength = l64781_read_signal_strength,
.read_snr = l64781_read_snr,
.read_ucblocks = l64781_read_ucblocks,
};
MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(l64781_attach);
| linux-master | drivers/media/dvb-frontends/l64781.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Allegro A8293 SEC driver
*
* Copyright (C) 2011 Antti Palosaari <[email protected]>
*/
#include "a8293.h"
#define A8293_FLAG_ODT 0x10
struct a8293_dev {
struct i2c_client *client;
u8 reg[2];
int volt_slew_nanos_per_mv;
};
/*
* When increasing voltage, do so in minimal steps over time, minimizing
* risk of vIN undervoltage.
*/
static int a8293_set_voltage_slew(struct a8293_dev *dev,
struct i2c_client *client,
enum fe_sec_voltage fe_sec_voltage,
int min_nanos_per_mv)
{
int ret;
u8 reg0, reg1;
int new_volt_idx;
const int idx_to_mv[] = {
0, 12709, 13042, 13375, 14042, 15042, 18042, 18709, 19042
};
const u8 idx_to_reg[] = {
0x00, 0x20, 0x21, 0x22, 0x24, 0x27, 0x28, 0x2A, 0x2B
};
int this_volt_idx;
u8 status;
int prev_volt_idx;
dev_dbg(&client->dev, "set_voltage_slew fe_sec_voltage=%d\n",
fe_sec_voltage);
/* Read status register to clear any stale faults. */
ret = i2c_master_recv(client, &status, 1);
if (ret < 0)
goto err;
/* Determine previous voltage */
switch (dev->reg[0] & 0x2F) {
case 0x00:
prev_volt_idx = 0;
break;
case 0x20:
prev_volt_idx = 1;
break;
case 0x21:
prev_volt_idx = 2;
break;
case 0x22:
prev_volt_idx = 3;
break;
case 0x24:
prev_volt_idx = 4;
break;
case 0x27:
prev_volt_idx = 5;
break;
case 0x28:
prev_volt_idx = 6;
break;
case 0x2A:
prev_volt_idx = 7;
break;
case 0x2B:
prev_volt_idx = 8;
break;
default:
prev_volt_idx = 0;
}
/* Determine new voltage */
switch (fe_sec_voltage) {
case SEC_VOLTAGE_OFF:
new_volt_idx = 0;
break;
case SEC_VOLTAGE_13:
new_volt_idx = 2;
break;
case SEC_VOLTAGE_18:
new_volt_idx = 6;
break;
default:
ret = -EINVAL;
goto err;
}
/* Slew to new voltage if new voltage is greater than current voltage */
this_volt_idx = prev_volt_idx;
if (this_volt_idx < new_volt_idx) {
while (this_volt_idx < new_volt_idx) {
int delta_mv = idx_to_mv[this_volt_idx+1] - idx_to_mv[this_volt_idx];
int min_wait_time = delta_mv * min_nanos_per_mv;
reg0 = idx_to_reg[this_volt_idx+1];
reg0 |= A8293_FLAG_ODT;
ret = i2c_master_send(client, ®0, 1);
if (ret < 0)
goto err;
dev->reg[0] = reg0;
this_volt_idx++;
usleep_range(min_wait_time, min_wait_time * 2);
}
} else { /* Else just set the voltage */
reg0 = idx_to_reg[new_volt_idx];
reg0 |= A8293_FLAG_ODT;
ret = i2c_master_send(client, ®0, 1);
if (ret < 0)
goto err;
dev->reg[0] = reg0;
}
/* TMODE=0, TGATE=1 */
reg1 = 0x82;
if (reg1 != dev->reg[1]) {
ret = i2c_master_send(client, ®1, 1);
if (ret < 0)
goto err;
dev->reg[1] = reg1;
}
usleep_range(1500, 5000);
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int a8293_set_voltage_noslew(struct dvb_frontend *fe,
enum fe_sec_voltage fe_sec_voltage)
{
struct a8293_dev *dev = fe->sec_priv;
struct i2c_client *client = dev->client;
int ret;
u8 reg0, reg1;
dev_dbg(&client->dev, "set_voltage_noslew fe_sec_voltage=%d\n",
fe_sec_voltage);
switch (fe_sec_voltage) {
case SEC_VOLTAGE_OFF:
/* ENB=0 */
reg0 = 0x10;
break;
case SEC_VOLTAGE_13:
/* VSEL0=1, VSEL1=0, VSEL2=0, VSEL3=0, ENB=1*/
reg0 = 0x31;
break;
case SEC_VOLTAGE_18:
/* VSEL0=0, VSEL1=0, VSEL2=0, VSEL3=1, ENB=1*/
reg0 = 0x38;
break;
default:
ret = -EINVAL;
goto err;
}
if (reg0 != dev->reg[0]) {
ret = i2c_master_send(client, ®0, 1);
if (ret < 0)
goto err;
dev->reg[0] = reg0;
}
/* TMODE=0, TGATE=1 */
reg1 = 0x82;
if (reg1 != dev->reg[1]) {
ret = i2c_master_send(client, ®1, 1);
if (ret < 0)
goto err;
dev->reg[1] = reg1;
}
usleep_range(1500, 50000);
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int a8293_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage fe_sec_voltage)
{
struct a8293_dev *dev = fe->sec_priv;
struct i2c_client *client = dev->client;
int volt_slew_nanos_per_mv = dev->volt_slew_nanos_per_mv;
dev_dbg(&client->dev, "set_voltage volt_slew_nanos_per_mv=%d\n",
volt_slew_nanos_per_mv);
/* Use slew version if slew rate is set to a sane value */
if (volt_slew_nanos_per_mv > 0 && volt_slew_nanos_per_mv < 1600)
a8293_set_voltage_slew(dev, client, fe_sec_voltage,
volt_slew_nanos_per_mv);
else
a8293_set_voltage_noslew(fe, fe_sec_voltage);
return 0;
}
static int a8293_probe(struct i2c_client *client)
{
struct a8293_dev *dev;
struct a8293_platform_data *pdata = client->dev.platform_data;
struct dvb_frontend *fe = pdata->dvb_frontend;
int ret;
u8 buf[2];
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
dev->client = client;
dev->volt_slew_nanos_per_mv = pdata->volt_slew_nanos_per_mv;
/* check if the SEC is there */
ret = i2c_master_recv(client, buf, 2);
if (ret < 0)
goto err_kfree;
/* override frontend ops */
fe->ops.set_voltage = a8293_set_voltage;
fe->sec_priv = dev;
i2c_set_clientdata(client, dev);
dev_info(&client->dev, "Allegro A8293 SEC successfully attached\n");
return 0;
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void a8293_remove(struct i2c_client *client)
{
struct a8293_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
kfree(dev);
}
static const struct i2c_device_id a8293_id_table[] = {
{"a8293", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, a8293_id_table);
static struct i2c_driver a8293_driver = {
.driver = {
.name = "a8293",
.suppress_bind_attrs = true,
},
.probe = a8293_probe,
.remove = a8293_remove,
.id_table = a8293_id_table,
};
module_i2c_driver(a8293_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Allegro A8293 SEC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/a8293.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
*
* Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <asm/div64.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "dib8000.h"
#define LAYER_ALL -1
#define LAYER_A 1
#define LAYER_B 2
#define LAYER_C 3
#define MAX_NUMBER_OF_FRONTENDS 6
/* #define DIB8000_AGC_FREEZE */
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
struct i2c_device {
struct i2c_adapter *adap;
u8 addr;
u8 *i2c_write_buffer;
u8 *i2c_read_buffer;
struct mutex *i2c_buffer_lock;
};
enum param_loop_step {
LOOP_TUNE_1,
LOOP_TUNE_2
};
enum dib8000_autosearch_step {
AS_START = 0,
AS_SEARCHING_FFT,
AS_SEARCHING_GUARD,
AS_DONE = 100,
};
enum timeout_mode {
SYMBOL_DEPENDENT_OFF = 0,
SYMBOL_DEPENDENT_ON,
};
struct dib8000_state {
struct dib8000_config cfg;
struct i2c_device i2c;
struct dibx000_i2c_master i2c_master;
u16 wbd_ref;
u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;
u32 timf_default;
u8 div_force_off:1;
u8 div_state:1;
u16 div_sync_wait;
u8 agc_state;
u8 differential_constellation;
u8 diversity_onoff;
s16 ber_monitored_layer;
u16 gpio_dir;
u16 gpio_val;
u16 revision;
u8 isdbt_cfg_loaded;
enum frontend_tune_state tune_state;
s32 status;
struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[4];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
u8 input_mode_mpeg;
u16 tuner_enable;
struct i2c_adapter dib8096p_tuner_adap;
u16 current_demod_bw;
u16 seg_mask;
u16 seg_diff_mask;
u16 mode;
u8 layer_b_nb_seg;
u8 layer_c_nb_seg;
u8 channel_parameters_set;
u16 autosearch_state;
u16 found_nfft;
u16 found_guard;
u8 subchannel;
u8 symbol_duration;
unsigned long timeout;
u8 longest_intlv_layer;
u16 output_mode;
/* for DVBv5 stats */
s64 init_ucb;
unsigned long per_jiffies_stats;
unsigned long ber_jiffies_stats;
unsigned long ber_jiffies_stats_layer[3];
#ifdef DIB8000_AGC_FREEZE
u16 agc1_max;
u16 agc1_min;
u16 agc2_max;
u16 agc2_min;
#endif
};
enum dib8000_power_mode {
DIB8000_POWER_ALL = 0,
DIB8000_POWER_INTERFACE_ONLY,
};
static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
{
u16 ret;
struct i2c_msg msg[2] = {
{.addr = i2c->addr >> 1, .flags = 0, .len = 2},
{.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
};
if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
msg[0].buf = i2c->i2c_write_buffer;
msg[0].buf[0] = reg >> 8;
msg[0].buf[1] = reg & 0xff;
msg[1].buf = i2c->i2c_read_buffer;
if (i2c_transfer(i2c->adap, msg, 2) != 2)
dprintk("i2c read error on %d\n", reg);
ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
mutex_unlock(i2c->i2c_buffer_lock);
return ret;
}
static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)
{
u16 ret;
state->i2c_write_buffer[0] = reg >> 8;
state->i2c_write_buffer[1] = reg & 0xff;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 2;
state->msg[1].addr = state->i2c.addr >> 1;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
dprintk("i2c read error on %d\n", reg);
ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
return ret;
}
static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
ret = __dib8000_read_word(state, reg);
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
{
u16 rw[2];
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
rw[0] = __dib8000_read_word(state, reg + 0);
rw[1] = __dib8000_read_word(state, reg + 1);
mutex_unlock(&state->i2c_buffer_lock);
return ((rw[0] << 16) | (rw[1]));
}
static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
{
struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
int ret = 0;
if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
msg.buf = i2c->i2c_write_buffer;
msg.buf[0] = (reg >> 8) & 0xff;
msg.buf[1] = reg & 0xff;
msg.buf[2] = (val >> 8) & 0xff;
msg.buf[3] = val & 0xff;
ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
mutex_unlock(i2c->i2c_buffer_lock);
return ret;
}
static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
state->i2c_write_buffer[1] = reg & 0xff;
state->i2c_write_buffer[2] = (val >> 8) & 0xff;
state->i2c_write_buffer[3] = val & 0xff;
memset(&state->msg[0], 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 4;
ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
-EREMOTEIO : 0);
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
(769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
(920 << 5) | 0x09
};
static const s16 coeff_2k_sb_1seg[8] = {
(692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
};
static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
(-931 << 5) | 0x0f
};
static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
(622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
(982 << 5) | 0x0c
};
static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
(-720 << 5) | 0x0d
};
static const s16 coeff_2k_sb_3seg[8] = {
(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
(-610 << 5) | 0x0a
};
static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
(-922 << 5) | 0x0d
};
static const s16 coeff_4k_sb_1seg[8] = {
(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
(-655 << 5) | 0x0a
};
static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
(-958 << 5) | 0x13
};
static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
(-568 << 5) | 0x0f
};
static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
(-848 << 5) | 0x13
};
static const s16 coeff_4k_sb_3seg[8] = {
(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
(-869 << 5) | 0x13
};
static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
(-598 << 5) | 0x10
};
static const s16 coeff_8k_sb_1seg[8] = {
(673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
(585 << 5) | 0x0f
};
static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
(863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
(0 << 5) | 0x14
};
static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
(-877 << 5) | 0x15
};
static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
(-921 << 5) | 0x14
};
static const s16 coeff_8k_sb_3seg[8] = {
(514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
(690 << 5) | 0x14
};
static const s16 ana_fe_coeff_3seg[24] = {
81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
};
static const s16 ana_fe_coeff_1seg[24] = {
249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
};
static const s16 ana_fe_coeff_13seg[24] = {
396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
};
static u16 fft_to_mode(struct dib8000_state *state)
{
u16 mode;
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
mode = 1;
break;
case TRANSMISSION_MODE_4K:
mode = 2;
break;
default:
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
mode = 3;
break;
}
return mode;
}
static void dib8000_set_acquisition_mode(struct dib8000_state *state)
{
u16 nud = dib8000_read_word(state, 298);
nud |= (1 << 3) | (1 << 0);
dprintk("acquisition mode activated\n");
dib8000_write_word(state, 298, nud);
}
static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
state->output_mode = mode;
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
dprintk("-I- Setting output mode for demod %p to %d\n",
&state->fe[0], mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
outreg = (1 << 10); /* 0x0400 */
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
outreg = (1 << 10) | (1 << 6); /* 0x0440 */
break;
case OUTMODE_MPEG2_SERIAL: // STBs with serial input
outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
break;
case OUTMODE_DIVERSITY:
if (state->cfg.hostbus_diversity) {
outreg = (1 << 10) | (4 << 6); /* 0x0500 */
sram &= 0xfdff;
} else
sram |= 0x0c00;
break;
case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
smo_mode |= (3 << 1);
fifo_threshold = 512;
outreg = (1 << 10) | (5 << 6);
break;
case OUTMODE_HIGH_Z: // disable
outreg = 0;
break;
case OUTMODE_ANALOG_ADC:
outreg = (1 << 10) | (3 << 6);
dib8000_set_acquisition_mode(state);
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p\n",
&state->fe[0]);
return -EINVAL;
}
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
dib8000_write_word(state, 299, smo_mode);
dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
dib8000_write_word(state, 1286, outreg);
dib8000_write_word(state, 1291, sram);
return 0;
}
static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
dprintk("set diversity input to %i\n", onoff);
if (!state->differential_constellation) {
dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
} else {
dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
}
state->diversity_onoff = onoff;
switch (onoff) {
case 0: /* only use the internal way - not the diversity input */
dib8000_write_word(state, 270, 1);
dib8000_write_word(state, 271, 0);
break;
case 1: /* both ways */
dib8000_write_word(state, 270, 6);
dib8000_write_word(state, 271, 6);
break;
case 2: /* only the diversity input */
dib8000_write_word(state, 270, 0);
dib8000_write_word(state, 271, 1);
break;
}
if (state->revision == 0x8002) {
tmp = dib8000_read_word(state, 903);
dib8000_write_word(state, 903, tmp & ~(1 << 3));
msleep(30);
dib8000_write_word(state, 903, tmp | (1 << 3));
}
return 0;
}
static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
{
/* by default everything is going to be powered off */
u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
reg_1280;
if (state->revision != 0x8090)
reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
else
reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
case DIB8000_POWER_ALL:
reg_774 = 0x0000;
reg_775 = 0x0000;
reg_776 = 0x0000;
reg_900 &= 0xfffc;
if (state->revision != 0x8090)
reg_1280 &= 0x00ff;
else
reg_1280 &= 0x707f;
break;
case DIB8000_POWER_INTERFACE_ONLY:
if (state->revision != 0x8090)
reg_1280 &= 0x00ff;
else
reg_1280 &= 0xfa7b;
break;
}
dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x\n", reg_774, reg_775, reg_776, reg_900, reg_1280);
dib8000_write_word(state, 774, reg_774);
dib8000_write_word(state, 775, reg_775);
dib8000_write_word(state, 776, reg_776);
dib8000_write_word(state, 900, reg_900);
dib8000_write_word(state, 1280, reg_1280);
}
static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
{
int ret = 0;
u16 reg, reg_907 = dib8000_read_word(state, 907);
u16 reg_908 = dib8000_read_word(state, 908);
switch (no) {
case DIBX000_SLOW_ADC_ON:
if (state->revision != 0x8090) {
reg_908 |= (1 << 1) | (1 << 0);
ret |= dib8000_write_word(state, 908, reg_908);
reg_908 &= ~(1 << 1);
} else {
reg = dib8000_read_word(state, 1925);
/* en_slowAdc = 1 & reset_sladc = 1 */
dib8000_write_word(state, 1925, reg |
(1<<4) | (1<<2));
/* read access to make it works... strange ... */
reg = dib8000_read_word(state, 1925);
msleep(20);
/* en_slowAdc = 1 & reset_sladc = 0 */
dib8000_write_word(state, 1925, reg & ~(1<<4));
reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
| (0x3 << 12));
/* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
(Vin2 = Vcm) */
dib8000_write_word(state, 921, reg | (1 << 14)
| (3 << 12));
}
break;
case DIBX000_SLOW_ADC_OFF:
if (state->revision == 0x8090) {
reg = dib8000_read_word(state, 1925);
/* reset_sladc = 1 en_slowAdc = 0 */
dib8000_write_word(state, 1925,
(reg & ~(1<<2)) | (1<<4));
}
reg_908 |= (1 << 1) | (1 << 0);
break;
case DIBX000_ADC_ON:
reg_907 &= 0x0fff;
reg_908 &= 0x0003;
break;
case DIBX000_ADC_OFF: // leave the VBG voltage on
reg_907 = (1 << 13) | (1 << 12);
reg_908 = (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1);
break;
case DIBX000_VBG_ENABLE:
reg_907 &= ~(1 << 15);
break;
case DIBX000_VBG_DISABLE:
reg_907 |= (1 << 15);
break;
default:
break;
}
ret |= dib8000_write_word(state, 907, reg_907);
ret |= dib8000_write_word(state, 908, reg_908);
return ret;
}
static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 timf;
if (bw == 0)
bw = 6000;
if (state->timf == 0) {
dprintk("using default timf\n");
timf = state->timf_default;
} else {
dprintk("using updated timf\n");
timf = state->timf;
}
dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
return 0;
}
static int dib8000_sad_calib(struct dib8000_state *state)
{
u8 sad_sel = 3;
if (state->revision == 0x8090) {
dib8000_write_word(state, 922, (sad_sel << 2));
dib8000_write_word(state, 923, 2048);
dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);
dib8000_write_word(state, 922, (sad_sel << 2));
} else {
/* internal */
dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
dib8000_write_word(state, 924, 776);
/* do the calibration */
dib8000_write_word(state, 923, (1 << 0));
dib8000_write_word(state, 923, (0 << 0));
}
msleep(1);
return 0;
}
static int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
{
struct dib8000_state *state = fe->demodulator_priv;
if (value > 4095)
value = 4095;
state->wbd_ref = value;
return dib8000_write_word(state, 106, value);
}
static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
{
dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
if (state->revision != 0x8090) {
dib8000_write_word(state, 23,
(u16) (((bw->internal * 1000) >> 16) & 0xffff));
dib8000_write_word(state, 24,
(u16) ((bw->internal * 1000) & 0xffff));
} else {
dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
dib8000_write_word(state, 24,
(u16) ((bw->internal / 2 * 1000) & 0xffff));
}
dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
if (state->revision != 0x8090)
dib8000_write_word(state, 922, bw->sad_cfg);
}
static void dib8000_reset_pll(struct dib8000_state *state)
{
const struct dibx000_bandwidth_config *pll = state->cfg.pll;
u16 clk_cfg1, reg;
if (state->revision != 0x8090) {
dib8000_write_word(state, 901,
(pll->pll_prediv << 8) | (pll->pll_ratio << 0));
clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
(1 << 3) | (pll->pll_range << 1) |
(pll->pll_reset << 0);
dib8000_write_word(state, 902, clk_cfg1);
clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
dib8000_write_word(state, 902, clk_cfg1);
dprintk("clk_cfg1: 0x%04x\n", clk_cfg1);
/* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
if (state->cfg.pll->ADClkSrc == 0)
dib8000_write_word(state, 904,
(0 << 15) | (0 << 12) | (0 << 10) |
(pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
else if (state->cfg.refclksel != 0)
dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
((state->cfg.refclksel & 0x3) << 10) |
(pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
else
dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
(3 << 10) | (pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
} else {
dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
(pll->pll_range<<12) | (pll->pll_ratio<<6) |
(pll->pll_prediv));
reg = dib8000_read_word(state, 1857);
dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
dib8000_write_word(state, 1858, reg | 1);
dib8000_write_word(state, 904, (pll->modulo << 8));
}
dib8000_reset_pll_common(state, pll);
}
static int dib8000_update_pll(struct dvb_frontend *fe,
struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
u32 internal, xtal;
/* get back old values */
prediv = reg_1856 & 0x3f;
loopdiv = (reg_1856 >> 6) & 0x3f;
if ((pll == NULL) || (pll->pll_prediv == prediv &&
pll->pll_ratio == loopdiv))
return -EINVAL;
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
if (state->revision == 0x8090) {
reg_1856 &= 0xf000;
reg_1857 = dib8000_read_word(state, 1857);
/* disable PLL */
dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
dib8000_write_word(state, 1856, reg_1856 |
((pll->pll_ratio & 0x3f) << 6) |
(pll->pll_prediv & 0x3f));
/* write new system clk into P_sec_len */
internal = dib8000_read32(state, 23) / 1000;
dprintk("Old Internal = %d\n", internal);
xtal = 2 * (internal / loopdiv) * prediv;
internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d\n", xtal, internal/1000, internal/2000, internal/8000);
dprintk("New Internal = %d\n", internal);
dib8000_write_word(state, 23,
(u16) (((internal / 2) >> 16) & 0xffff));
dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
/* enable PLL */
dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
dprintk("Waiting for PLL to lock\n");
/* verify */
reg_1856 = dib8000_read_word(state, 1856);
dprintk("PLL Updated with prediv = %d and loopdiv = %d\n",
reg_1856&0x3f, (reg_1856>>6)&0x3f);
} else {
if (bw != state->current_demod_bw) {
/** Bandwidth change => force PLL update **/
dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
if (state->cfg.pll->pll_prediv != oldprediv) {
/** Full PLL change only if prediv is changed **/
/** full update => bypass and reconfigure **/
dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
dib8000_reset_pll(state);
dib8000_write_word(state, 898, 0x0004); /* sad */
} else
ratio = state->cfg.pll->pll_ratio;
state->current_demod_bw = bw;
}
if (ratio != 0) {
/** ratio update => only change ratio **/
dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
}
}
return 0;
}
static int dib8000_reset_gpio(struct dib8000_state *st)
{
/* reset the GPIOs */
dib8000_write_word(st, 1029, st->cfg.gpio_dir);
dib8000_write_word(st, 1030, st->cfg.gpio_val);
/* TODO 782 is P_gpio_od */
dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
return 0;
}
static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
{
st->cfg.gpio_dir = dib8000_read_word(st, 1029);
st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
dib8000_write_word(st, 1029, st->cfg.gpio_dir);
st->cfg.gpio_val = dib8000_read_word(st, 1030);
st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
dib8000_write_word(st, 1030, st->cfg.gpio_val);
dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val);
return 0;
}
static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
{
struct dib8000_state *state = fe->demodulator_priv;
return dib8000_cfg_gpio(state, num, dir, val);
}
static const u16 dib8000_defaults[] = {
/* auto search configuration - lock0 by default waiting
* for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
3, 7,
0x0004,
0x0400,
0x0814,
12, 11,
0x001b,
0x7740,
0x005b,
0x8d80,
0x01c9,
0xc380,
0x0000,
0x0080,
0x0000,
0x0090,
0x0001,
0xd4c0,
/*1, 32,
0x6680 // P_corm_thres Lock algorithms configuration */
11, 80, /* set ADC level to -16 */
(1 << 13) - 825 - 117,
(1 << 13) - 837 - 117,
(1 << 13) - 811 - 117,
(1 << 13) - 766 - 117,
(1 << 13) - 737 - 117,
(1 << 13) - 693 - 117,
(1 << 13) - 648 - 117,
(1 << 13) - 619 - 117,
(1 << 13) - 575 - 117,
(1 << 13) - 531 - 117,
(1 << 13) - 501 - 117,
4, 108,
0,
0,
0,
0,
1, 175,
0x0410,
1, 179,
8192, // P_fft_nb_to_cut
6, 181,
0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
0x2800,
0x2800,
0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
0x2800,
0x2800,
2, 193,
0x0666, // P_pha3_thres
0x0000, // P_cti_use_cpe, P_cti_use_prog
2, 205,
0x200f, // P_cspu_regul, P_cspu_win_cut
0x000f, // P_des_shift_work
5, 215,
0x023d, // P_adp_regul_cnt
0x00a4, // P_adp_noise_cnt
0x00a4, // P_adp_regul_ext
0x7ff0, // P_adp_noise_ext
0x3ccc, // P_adp_fil
1, 230,
0x0000, // P_2d_byp_ti_num
1, 263,
0x800, //P_equal_thres_wgn
1, 268,
(2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
1, 270,
0x0001, // P_div_lock0_wait
1, 285,
0x0020, //p_fec_
1, 299,
0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
1, 338,
(1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
(1 << 10) |
(0 << 9) | /* P_ctrl_pre_freq_inh=0 */
(3 << 5) | /* P_ctrl_pre_freq_step=3 */
(1 << 0), /* P_pre_freq_win_len=1 */
0,
};
static u16 dib8000_identify(struct i2c_device *client)
{
u16 value;
//because of glitches sometimes
value = dib8000_i2c_read16(client, 896);
if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
dprintk("wrong Vendor ID (read=0x%x)\n", value);
return 0;
}
value = dib8000_i2c_read16(client, 897);
if (value != 0x8000 && value != 0x8001 &&
value != 0x8002 && value != 0x8090) {
dprintk("wrong Device ID (%x)\n", value);
return 0;
}
switch (value) {
case 0x8000:
dprintk("found DiB8000A\n");
break;
case 0x8001:
dprintk("found DiB8000B\n");
break;
case 0x8002:
dprintk("found DiB8000C\n");
break;
case 0x8090:
dprintk("found DiB8096P\n");
break;
}
return value;
}
static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 *unc);
static void dib8000_reset_stats(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
u32 ucb;
memset(&c->strength, 0, sizeof(c->strength));
memset(&c->cnr, 0, sizeof(c->cnr));
memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
memset(&c->block_error, 0, sizeof(c->block_error));
c->strength.len = 1;
c->cnr.len = 1;
c->block_error.len = 1;
c->block_count.len = 1;
c->post_bit_error.len = 1;
c->post_bit_count.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].uvalue = 0;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dib8000_read_unc_blocks(fe, &ucb);
state->init_ucb = -ucb;
state->ber_jiffies_stats = 0;
state->per_jiffies_stats = 0;
memset(&state->ber_jiffies_stats_layer, 0,
sizeof(state->ber_jiffies_stats_layer));
}
static int dib8000_reset(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
if ((state->revision = dib8000_identify(&state->i2c)) == 0)
return -EINVAL;
/* sram lead in, rdy */
if (state->revision != 0x8090)
dib8000_write_word(state, 1287, 0x0003);
if (state->revision == 0x8000)
dprintk("error : dib8000 MA not supported\n");
dibx000_reset_i2c_master(&state->i2c_master);
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
/* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
dib8000_set_adc_state(state, DIBX000_ADC_OFF);
/* restart all parts */
dib8000_write_word(state, 770, 0xffff);
dib8000_write_word(state, 771, 0xffff);
dib8000_write_word(state, 772, 0xfffc);
dib8000_write_word(state, 898, 0x000c); /* restart sad */
if (state->revision == 0x8090)
dib8000_write_word(state, 1280, 0x0045);
else
dib8000_write_word(state, 1280, 0x004d);
dib8000_write_word(state, 1281, 0x000c);
dib8000_write_word(state, 770, 0x0000);
dib8000_write_word(state, 771, 0x0000);
dib8000_write_word(state, 772, 0x0000);
dib8000_write_word(state, 898, 0x0004); // sad
dib8000_write_word(state, 1280, 0x0000);
dib8000_write_word(state, 1281, 0x0000);
/* drives */
if (state->revision != 0x8090) {
if (state->cfg.drives)
dib8000_write_word(state, 906, state->cfg.drives);
else {
dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.\n");
/* min drive SDRAM - not optimal - adjust */
dib8000_write_word(state, 906, 0x2d98);
}
}
dib8000_reset_pll(state);
if (state->revision != 0x8090)
dib8000_write_word(state, 898, 0x0004);
if (dib8000_reset_gpio(state) != 0)
dprintk("GPIO reset was not successful.\n");
if ((state->revision != 0x8090) &&
(dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
dprintk("OUTPUT_MODE could not be reset.\n");
state->current_agc = NULL;
// P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
/* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
if (state->cfg.pll->ifreq == 0)
dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
else
dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
{
u16 l = 0, r;
const u16 *n;
n = dib8000_defaults;
l = *n++;
while (l) {
r = *n++;
do {
dib8000_write_word(state, r, *n++);
r++;
} while (--l);
l = *n++;
}
}
state->isdbt_cfg_loaded = 0;
//div_cfg override for special configs
if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
dib8000_write_word(state, 903, state->cfg.div_cfg);
/* unforce divstr regardless whether i2c enumeration was done or not */
dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
dib8000_set_bandwidth(fe, 6000);
dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
dib8000_sad_calib(state);
if (state->revision != 0x8090)
dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
/* ber_rs_len = 3 */
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
dib8000_reset_stats(fe);
return 0;
}
static void dib8000_restart_agc(struct dib8000_state *state)
{
// P_restart_iqc & P_restart_agc
dib8000_write_word(state, 770, 0x0a00);
dib8000_write_word(state, 770, 0x0000);
}
static int dib8000_update_lna(struct dib8000_state *state)
{
u16 dyn_gain;
if (state->cfg.update_lna) {
// read dyn_gain here (because it is demod-dependent and not tuner)
dyn_gain = dib8000_read_word(state, 390);
if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
dib8000_restart_agc(state);
return 1;
}
}
return 0;
}
static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
{
struct dibx000_agc_config *agc = NULL;
int i;
u16 reg;
if (state->current_band == band && state->current_agc != NULL)
return 0;
state->current_band = band;
for (i = 0; i < state->cfg.agc_config_count; i++)
if (state->cfg.agc[i].band_caps & band) {
agc = &state->cfg.agc[i];
break;
}
if (agc == NULL) {
dprintk("no valid AGC configuration found for band 0x%02x\n", band);
return -EINVAL;
}
state->current_agc = agc;
/* AGC */
dib8000_write_word(state, 76, agc->setup);
dib8000_write_word(state, 77, agc->inv_gain);
dib8000_write_word(state, 78, agc->time_stabiliz);
dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
// Demod AGC loop configuration
dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
/* AGC continued */
if (state->wbd_ref != 0)
dib8000_write_word(state, 106, state->wbd_ref);
else // use default
dib8000_write_word(state, 106, agc->wbd_ref);
if (state->revision == 0x8090) {
reg = dib8000_read_word(state, 922) & (0x3 << 2);
dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
}
dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
dib8000_write_word(state, 108, agc->agc1_max);
dib8000_write_word(state, 109, agc->agc1_min);
dib8000_write_word(state, 110, agc->agc2_max);
dib8000_write_word(state, 111, agc->agc2_min);
dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
dib8000_write_word(state, 75, agc->agc1_pt3);
if (state->revision != 0x8090)
dib8000_write_word(state, 923,
(dib8000_read_word(state, 923) & 0xffe3) |
(agc->wbd_inv << 4) | (agc->wbd_sel << 2));
return 0;
}
static void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
dib8000_set_adc_state(state, DIBX000_ADC_ON);
dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
}
static int dib8000_agc_soft_split(struct dib8000_state *state)
{
u16 agc, split_offset;
if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
return 0;
// n_agc_global
agc = dib8000_read_word(state, 390);
if (agc > state->current_agc->split.min_thres)
split_offset = state->current_agc->split.min;
else if (agc < state->current_agc->split.max_thres)
split_offset = state->current_agc->split.max;
else
split_offset = state->current_agc->split.max *
(agc - state->current_agc->split.min_thres) /
(state->current_agc->split.max_thres - state->current_agc->split.min_thres);
dprintk("AGC split_offset: %d\n", split_offset);
// P_agc_force_split and P_agc_split_offset
dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
return 5000;
}
static int dib8000_agc_startup(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
enum frontend_tune_state *tune_state = &state->tune_state;
int ret = 0;
u16 reg;
u32 upd_demod_gain_period = 0x8000;
switch (*tune_state) {
case CT_AGC_START:
// set power-up level: interf+analog+AGC
if (state->revision != 0x8090)
dib8000_set_adc_state(state, DIBX000_ADC_ON);
else {
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
reg = dib8000_read_word(state, 1947)&0xff00;
dib8000_write_word(state, 1946,
upd_demod_gain_period & 0xFFFF);
/* bit 14 = enDemodGain */
dib8000_write_word(state, 1947, reg | (1<<14) |
((upd_demod_gain_period >> 16) & 0xFF));
/* enable adc i & q */
reg = dib8000_read_word(state, 1920);
dib8000_write_word(state, 1920, (reg | 0x3) &
(~(1 << 7)));
}
if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
*tune_state = CT_AGC_STOP;
state->status = FE_STATUS_TUNE_FAILED;
break;
}
ret = 70;
*tune_state = CT_AGC_STEP_0;
break;
case CT_AGC_STEP_0:
//AGC initialization
if (state->cfg.agc_control)
state->cfg.agc_control(fe, 1);
dib8000_restart_agc(state);
// wait AGC rough lock time
ret = 50;
*tune_state = CT_AGC_STEP_1;
break;
case CT_AGC_STEP_1:
// wait AGC accurate lock time
ret = 70;
if (dib8000_update_lna(state))
// wait only AGC rough lock time
ret = 50;
else
*tune_state = CT_AGC_STEP_2;
break;
case CT_AGC_STEP_2:
dib8000_agc_soft_split(state);
if (state->cfg.agc_control)
state->cfg.agc_control(fe, 0);
*tune_state = CT_AGC_STOP;
break;
default:
ret = dib8000_agc_soft_split(state);
break;
}
return ret;
}
static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
{
u16 reg;
drive &= 0x7;
/* drive host bus 2, 3, 4 */
reg = dib8000_read_word(state, 1798) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1798, reg);
/* drive host bus 5,6 */
reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive<<8) | (drive<<2);
dib8000_write_word(state, 1799, reg);
/* drive host bus 7, 8, 9 */
reg = dib8000_read_word(state, 1800) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1800, reg);
/* drive host bus 10, 11 */
reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive<<8) | (drive<<2);
dib8000_write_word(state, 1801, reg);
/* drive host bus 12, 13, 14 */
reg = dib8000_read_word(state, 1802) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1802, reg);
}
static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
u32 insertExtSynchro, u32 syncSize)
{
u32 quantif = 3;
u32 nom = (insertExtSynchro * P_Kin+syncSize);
u32 denom = P_Kout;
u32 syncFreq = ((nom << quantif) / denom);
if ((syncFreq & ((1 << quantif) - 1)) != 0)
syncFreq = (syncFreq >> quantif) + 1;
else
syncFreq = (syncFreq >> quantif);
if (syncFreq != 0)
syncFreq = syncFreq - 1;
return syncFreq;
}
static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
u32 syncWord, u32 syncSize)
{
dprintk("Configure DibStream Tx\n");
dib8000_write_word(state, 1615, 1);
dib8000_write_word(state, 1603, P_Kin);
dib8000_write_word(state, 1605, P_Kout);
dib8000_write_word(state, 1606, insertExtSynchro);
dib8000_write_word(state, 1608, synchroMode);
dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
dib8000_write_word(state, 1610, syncWord & 0xffff);
dib8000_write_word(state, 1612, syncSize);
dib8000_write_word(state, 1615, 0);
}
static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
u32 syncWord, u32 syncSize, u32 dataOutRate)
{
u32 syncFreq;
dprintk("Configure DibStream Rx synchroMode = %d\n", synchroMode);
if ((P_Kin != 0) && (P_Kout != 0)) {
syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
insertExtSynchro, syncSize);
dib8000_write_word(state, 1542, syncFreq);
}
dib8000_write_word(state, 1554, 1);
dib8000_write_word(state, 1536, P_Kin);
dib8000_write_word(state, 1537, P_Kout);
dib8000_write_word(state, 1539, synchroMode);
dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
dib8000_write_word(state, 1541, syncWord & 0xffff);
dib8000_write_word(state, 1543, syncSize);
dib8000_write_word(state, 1544, dataOutRate);
dib8000_write_word(state, 1554, 0);
}
static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
{
u16 reg_1287;
reg_1287 = dib8000_read_word(state, 1287);
switch (onoff) {
case 1:
reg_1287 &= ~(1 << 8);
break;
case 0:
reg_1287 |= (1 << 8);
break;
}
dib8000_write_word(state, 1287, reg_1287);
}
static void dib8096p_configMpegMux(struct dib8000_state *state,
u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
{
u16 reg_1287;
dprintk("Enable Mpeg mux\n");
dib8096p_enMpegMux(state, 0);
/* If the input mode is MPEG do not divide the serial clock */
if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
enSerialClkDiv2 = 0;
reg_1287 = ((pulseWidth & 0x1f) << 3) |
((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
dib8000_write_word(state, 1287, reg_1287);
dib8096p_enMpegMux(state, 1);
}
static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
{
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
switch (mode) {
case MPEG_ON_DIBTX:
dprintk("SET MPEG ON DIBSTREAM TX\n");
dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
reg_1288 |= (1 << 9); break;
case DIV_ON_DIBTX:
dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
reg_1288 |= (1 << 8); break;
case ADC_ON_DIBTX:
dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
reg_1288 |= (1 << 7); break;
default:
break;
}
dib8000_write_word(state, 1288, reg_1288);
}
static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
{
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
switch (mode) {
case DEMOUT_ON_HOSTBUS:
dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
dib8096p_enMpegMux(state, 0);
reg_1288 |= (1 << 6);
break;
case DIBTX_ON_HOSTBUS:
dprintk("SET DIBSTREAM TX ON HOST BUS\n");
dib8096p_enMpegMux(state, 0);
reg_1288 |= (1 << 5);
break;
case MPEG_ON_HOSTBUS:
dprintk("SET MPEG MUX ON HOST BUS\n");
reg_1288 |= (1 << 4);
break;
default:
break;
}
dib8000_write_word(state, 1288, reg_1288);
}
static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 reg_1287;
switch (onoff) {
case 0: /* only use the internal way - not the diversity input */
dprintk("%s mode OFF : by default Enable Mpeg INPUT\n",
__func__);
/* outputRate = 8 */
dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
/* Do not divide the serial clock of MPEG MUX in
SERIAL MODE in case input mode MPEG is used */
reg_1287 = dib8000_read_word(state, 1287);
/* enSerialClkDiv2 == 1 ? */
if ((reg_1287 & 0x1) == 1) {
/* force enSerialClkDiv2 = 0 */
reg_1287 &= ~0x1;
dib8000_write_word(state, 1287, reg_1287);
}
state->input_mode_mpeg = 1;
break;
case 1: /* both ways */
case 2: /* only the diversity input */
dprintk("%s ON : Enable diversity INPUT\n", __func__);
dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
state->input_mode_mpeg = 0;
break;
}
dib8000_set_diversity_in(state->fe[0], onoff);
return 0;
}
static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 outreg, smo_mode, fifo_threshold;
u8 prefer_mpeg_mux_use = 1;
int ret = 0;
state->output_mode = mode;
dib8096p_host_bus_drive(state, 1);
fifo_threshold = 1792;
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
outreg = dib8000_read_word(state, 1286) &
~((1 << 10) | (0x7 << 6) | (1 << 1));
switch (mode) {
case OUTMODE_HIGH_Z:
outreg = 0;
break;
case OUTMODE_MPEG2_SERIAL:
if (prefer_mpeg_mux_use) {
dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux\n");
dib8096p_configMpegMux(state, 3, 1, 1);
dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else {/* Use Smooth block */
dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc\n");
dib8096p_setHostBusMux(state,
DEMOUT_ON_HOSTBUS);
outreg |= (2 << 6) | (0 << 1);
}
break;
case OUTMODE_MPEG2_PAR_GATED_CLK:
if (prefer_mpeg_mux_use) {
dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
dib8096p_configMpegMux(state, 2, 0, 0);
dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else { /* Use Smooth block */
dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block\n");
dib8096p_setHostBusMux(state,
DEMOUT_ON_HOSTBUS);
outreg |= (0 << 6);
}
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block\n");
dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (1 << 6);
break;
case OUTMODE_MPEG2_FIFO:
/* Using Smooth block because not supported
by new Mpeg Mux bloc */
dprintk("dib8096P setting output mode TS_FIFO using Smooth block\n");
dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (5 << 6);
smo_mode |= (3 << 1);
fifo_threshold = 512;
break;
case OUTMODE_DIVERSITY:
dprintk("dib8096P setting output mode MODE_DIVERSITY\n");
dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
case OUTMODE_ANALOG_ADC:
dprintk("dib8096P setting output mode MODE_ANALOG_ADC\n");
dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
}
if (mode != OUTMODE_HIGH_Z)
outreg |= (1<<10);
dprintk("output_mpeg2_in_188_bytes = %d\n",
state->cfg.output_mpeg2_in_188_bytes);
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
ret |= dib8000_write_word(state, 299, smo_mode);
/* synchronous fread */
ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
ret |= dib8000_write_word(state, 1286, outreg);
return ret;
}
static int map_addr_to_serpar_number(struct i2c_msg *msg)
{
if (msg->buf[0] <= 15)
msg->buf[0] -= 1;
else if (msg->buf[0] == 17)
msg->buf[0] = 15;
else if (msg->buf[0] == 16)
msg->buf[0] = 17;
else if (msg->buf[0] == 19)
msg->buf[0] = 16;
else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
msg->buf[0] -= 3;
else if (msg->buf[0] == 28)
msg->buf[0] = 23;
else if (msg->buf[0] == 99)
msg->buf[0] = 99;
else
return -EINVAL;
return 0;
}
static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
while (n_overflow == 1 && i) {
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("Tuner ITF: write busy (overflow)\n");
}
dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
return num;
}
static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1, n_empty = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
u16 read_word;
while (n_overflow == 1 && i) {
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (overflow)\n");
}
dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
i = 1000;
while (n_empty == 1 && i) {
n_empty = dib8000_read_word(state, 1984)&0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (empty)\n");
}
read_word = dib8000_read_word(state, 1987);
msg[1].buf[0] = (read_word >> 8) & 0xff;
msg[1].buf[1] = (read_word) & 0xff;
return num;
}
static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
if (map_addr_to_serpar_number(&msg[0]) == 0) {
if (num == 1) /* write */
return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
else /* read */
return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
}
return num;
}
static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num, u16 apb_address)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u16 word;
if (num == 1) { /* write */
dib8000_write_word(state, apb_address,
((msg[0].buf[1] << 8) | (msg[0].buf[2])));
} else {
word = dib8000_read_word(state, apb_address);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
}
return num;
}
static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u16 apb_address = 0, word;
int i = 0;
switch (msg[0].buf[0]) {
case 0x12:
apb_address = 1920;
break;
case 0x14:
apb_address = 1921;
break;
case 0x24:
apb_address = 1922;
break;
case 0x1a:
apb_address = 1923;
break;
case 0x22:
apb_address = 1924;
break;
case 0x33:
apb_address = 1926;
break;
case 0x34:
apb_address = 1927;
break;
case 0x35:
apb_address = 1928;
break;
case 0x36:
apb_address = 1929;
break;
case 0x37:
apb_address = 1930;
break;
case 0x38:
apb_address = 1931;
break;
case 0x39:
apb_address = 1932;
break;
case 0x2a:
apb_address = 1935;
break;
case 0x2b:
apb_address = 1936;
break;
case 0x2c:
apb_address = 1937;
break;
case 0x2d:
apb_address = 1938;
break;
case 0x2e:
apb_address = 1939;
break;
case 0x2f:
apb_address = 1940;
break;
case 0x30:
apb_address = 1941;
break;
case 0x31:
apb_address = 1942;
break;
case 0x32:
apb_address = 1943;
break;
case 0x3e:
apb_address = 1944;
break;
case 0x3f:
apb_address = 1945;
break;
case 0x40:
apb_address = 1948;
break;
case 0x25:
apb_address = 936;
break;
case 0x26:
apb_address = 937;
break;
case 0x27:
apb_address = 938;
break;
case 0x28:
apb_address = 939;
break;
case 0x1d:
/* get sad sel request */
i = ((dib8000_read_word(state, 921) >> 12)&0x3);
word = dib8000_read_word(state, 924+i);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
return num;
case 0x1f:
if (num == 1) { /* write */
word = (u16) ((msg[0].buf[1] << 8) |
msg[0].buf[2]);
/* in the VGAMODE Sel are located on bit 0/1 */
word &= 0x3;
word = (dib8000_read_word(state, 921) &
~(3<<12)) | (word<<12);
/* Set the proper input */
dib8000_write_word(state, 921, word);
return num;
}
}
if (apb_address != 0) /* R/W access via APB */
return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
else /* R/W access via SERPAR */
return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
return 0;
}
static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm dib8096p_tuner_xfer_algo = {
.master_xfer = dib8096p_tuner_xfer,
.functionality = dib8096p_i2c_func,
};
static struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
{
struct dib8000_state *st = fe->demodulator_priv;
return &st->dib8096p_tuner_adap;
}
static int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 en_cur_state;
dprintk("sleep dib8096p: %d\n", onoff);
en_cur_state = dib8000_read_word(state, 1922);
/* LNAs and MIX are ON and therefore it is a valid configuration */
if (en_cur_state > 0xff)
state->tuner_enable = en_cur_state ;
if (onoff)
en_cur_state &= 0x00ff;
else {
if (state->tuner_enable != 0)
en_cur_state = state->tuner_enable;
}
dib8000_write_word(state, 1922, en_cur_state);
return 0;
}
static const s32 lut_1000ln_mant[] =
{
908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
};
static s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
s32 val;
val = dib8000_read32(state, 384);
if (mode) {
tmp_val = val;
while (tmp_val >>= 1)
exp++;
mant = (val * 1000 / (1<<exp));
ix = (u8)((mant-1000)/100); /* index of the LUT */
val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
val = (val*256)/1000;
}
return val;
}
static int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
{
struct dib8000_state *state = fe->demodulator_priv;
int val = 0;
switch (IQ) {
case 1:
val = dib8000_read_word(state, 403);
break;
case 0:
val = dib8000_read_word(state, 404);
break;
}
if (val & 0x200)
val -= 1024;
return val;
}
static void dib8000_update_timf(struct dib8000_state *state)
{
u32 timf = state->timf = dib8000_read32(state, 435);
dib8000_write_word(state, 29, (u16) (timf >> 16));
dib8000_write_word(state, 30, (u16) (timf & 0xffff));
dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);
}
static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
{
struct dib8000_state *state = fe->demodulator_priv;
switch (op) {
case DEMOD_TIMF_SET:
state->timf = timf;
break;
case DEMOD_TIMF_UPDATE:
dib8000_update_timf(state);
break;
case DEMOD_TIMF_GET:
break;
}
dib8000_set_bandwidth(state->fe[0], 6000);
return state->timf;
}
static const u16 adc_target_16dB[11] = {
7250, 7238, 7264, 7309, 7338, 7382, 7427, 7456, 7500, 7544, 7574
};
static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)
{
u8 cr, constellation, time_intlv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
switch (c->layer[layer_index].modulation) {
case DQPSK:
constellation = 0;
break;
case QPSK:
constellation = 1;
break;
case QAM_16:
constellation = 2;
break;
case QAM_64:
default:
constellation = 3;
break;
}
switch (c->layer[layer_index].fec) {
case FEC_1_2:
cr = 1;
break;
case FEC_2_3:
cr = 2;
break;
case FEC_3_4:
cr = 3;
break;
case FEC_5_6:
cr = 5;
break;
case FEC_7_8:
default:
cr = 7;
break;
}
time_intlv = fls(c->layer[layer_index].interleaving);
if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1))
time_intlv = 0;
dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
if (c->layer[layer_index].segment_count > 0) {
switch (max_constellation) {
case DQPSK:
case QPSK:
if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64)
max_constellation = c->layer[layer_index].modulation;
break;
case QAM_16:
if (c->layer[layer_index].modulation == QAM_64)
max_constellation = c->layer[layer_index].modulation;
break;
}
}
return max_constellation;
}
static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */
static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */
static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp_noise_cnt -0.01, P_adp_regul_ext 0.1, P_adp_noise_ext -0.002 */
static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)
{
u16 i, ana_gain = 0;
const u16 *adp;
/* channel estimation fine configuration */
switch (max_constellation) {
case QAM_64:
ana_gain = 0x7;
adp = &adp_Q64[0];
break;
case QAM_16:
ana_gain = 0x7;
adp = &adp_Q16[0];
break;
default:
ana_gain = 0;
adp = &adp_Qdefault[0];
break;
}
for (i = 0; i < 4; i++)
dib8000_write_word(state, 215 + i, adp[i]);
return ana_gain;
}
static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)
{
u16 i;
dib8000_write_word(state, 116, ana_gain);
/* update ADC target depending on ana_gain */
if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */
for (i = 0; i < 10; i++)
dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
} else { /* set -22dB ADC target for ana_gain=0 */
for (i = 0; i < 10; i++)
dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
}
}
static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)
{
u16 mode = 0;
if (state->isdbt_cfg_loaded == 0)
for (mode = 0; mode < 24; mode++)
dib8000_write_word(state, 117 + mode, ana_fe[mode]);
}
static const u16 lut_prbs_2k[13] = {
0x423, 0x009, 0x5C7,
0x7A6, 0x3D8, 0x527,
0x7FF, 0x79B, 0x3D6,
0x3A2, 0x53B, 0x2F4,
0x213
};
static const u16 lut_prbs_4k[13] = {
0x208, 0x0C3, 0x7B9,
0x423, 0x5C7, 0x3D8,
0x7FF, 0x3D6, 0x53B,
0x213, 0x029, 0x0D0,
0x48E
};
static const u16 lut_prbs_8k[13] = {
0x740, 0x069, 0x7DD,
0x208, 0x7B9, 0x5C7,
0x7FF, 0x53B, 0x029,
0x48E, 0x4C4, 0x367,
0x684
};
static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)
{
int sub_channel_prbs_group = 0;
int prbs_group;
sub_channel_prbs_group = subchannel / 3;
if (sub_channel_prbs_group >= ARRAY_SIZE(lut_prbs_2k))
return 0;
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
prbs_group = lut_prbs_2k[sub_channel_prbs_group];
break;
case TRANSMISSION_MODE_4K:
prbs_group = lut_prbs_4k[sub_channel_prbs_group];
break;
default:
case TRANSMISSION_MODE_8K:
prbs_group = lut_prbs_8k[sub_channel_prbs_group];
}
dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x\n",
sub_channel_prbs_group, subchannel, prbs_group);
return prbs_group;
}
static void dib8000_set_13seg_channel(struct dib8000_state *state)
{
u16 i;
u16 coff_pow = 0x2800;
state->seg_mask = 0x1fff; /* All 13 segments enabled */
/* ---- COFF ---- Carloff, the most robust --- */
if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */
dib8000_write_word(state, 180, (16 << 6) | 9);
dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
coff_pow = 0x2800;
for (i = 0; i < 6; i++)
dib8000_write_word(state, 181+i, coff_pow);
/* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */
/* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
/* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */
dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
/* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */
dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
dib8000_write_word(state, 228, 0); /* default value */
dib8000_write_word(state, 265, 31); /* default value */
dib8000_write_word(state, 205, 0x200f); /* init value */
}
/*
* make the cpil_coff_lock more robust but slower p_coff_winlen
* 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
*/
if (state->cfg.pll->ifreq == 0)
dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);
}
static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)
{
u16 reg_1;
reg_1 = dib8000_read_word(state, 1);
dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */
}
static void dib8000_small_fine_tune(struct dib8000_state *state)
{
u16 i;
const s16 *ncoeff;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
dib8000_write_word(state, 352, state->seg_diff_mask);
dib8000_write_word(state, 353, state->seg_mask);
/* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */
dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
if (c->isdbt_sb_mode) {
/* ---- SMALL ---- */
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
if (c->isdbt_partial_reception == 0) { /* 1-seg */
if (c->layer[0].modulation == DQPSK) /* DQPSK */
ncoeff = coeff_2k_sb_1seg_dqpsk;
else /* QPSK or QAM */
ncoeff = coeff_2k_sb_1seg;
} else { /* 3-segments */
if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_2k_sb_3seg_0dqpsk;
} else { /* QPSK or QAM on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_2k_sb_3seg_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_2k_sb_3seg;
}
}
break;
case TRANSMISSION_MODE_4K:
if (c->isdbt_partial_reception == 0) { /* 1-seg */
if (c->layer[0].modulation == DQPSK) /* DQPSK */
ncoeff = coeff_4k_sb_1seg_dqpsk;
else /* QPSK or QAM */
ncoeff = coeff_4k_sb_1seg;
} else { /* 3-segments */
if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_4k_sb_3seg_0dqpsk;
} else { /* QPSK or QAM on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_4k_sb_3seg_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_4k_sb_3seg;
}
}
break;
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
default:
if (c->isdbt_partial_reception == 0) { /* 1-seg */
if (c->layer[0].modulation == DQPSK) /* DQPSK */
ncoeff = coeff_8k_sb_1seg_dqpsk;
else /* QPSK or QAM */
ncoeff = coeff_8k_sb_1seg;
} else { /* 3-segments */
if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_8k_sb_3seg_0dqpsk;
} else { /* QPSK or QAM on central segment */
if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
ncoeff = coeff_8k_sb_3seg_1dqpsk;
else /* QPSK or QAM on external segments */
ncoeff = coeff_8k_sb_3seg;
}
}
break;
}
for (i = 0; i < 8; i++)
dib8000_write_word(state, 343 + i, ncoeff[i]);
}
}
static const u16 coff_thres_1seg[3] = {300, 150, 80};
static const u16 coff_thres_3seg[3] = {350, 300, 250};
static void dib8000_set_sb_channel(struct dib8000_state *state)
{
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
const u16 *coff;
u16 i;
if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) {
dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
} else {
dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
}
if (c->isdbt_partial_reception == 1) /* 3-segments */
state->seg_mask = 0x00E0;
else /* 1-segment */
state->seg_mask = 0x0040;
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
/* ---- COFF ---- Carloff, the most robust --- */
/* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 */
dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */
dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */
/* Sound Broadcasting mode 1 seg */
if (c->isdbt_partial_reception == 0) {
/* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */
if (state->mode == 3)
dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
else
dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
/* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 */
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
coff = &coff_thres_1seg[0];
} else { /* Sound Broadcasting mode 3 seg */
dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
/* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 */
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
coff = &coff_thres_3seg[0];
}
dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */
dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K)
dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */
/* Write COFF thres */
for (i = 0 ; i < 3; i++) {
dib8000_write_word(state, 181+i, coff[i]);
dib8000_write_word(state, 184+i, coff[i]);
}
/*
* make the cpil_coff_lock more robust but slower p_coff_winlen
* 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
*/
dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
if (c->isdbt_partial_reception == 0)
dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */
else
dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
}
static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
{
u16 p_cfr_left_edge = 0, p_cfr_right_edge = 0;
u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;
u16 max_constellation = DQPSK;
int init_prbs;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
if (autosearching)
c->isdbt_partial_reception = 1;
/* P_mode */
dib8000_write_word(state, 10, (seq << 4));
/* init mode */
state->mode = fft_to_mode(state);
/* set guard */
tmp = dib8000_read_word(state, 1);
dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
/* signal optimization parameter */
if (c->isdbt_partial_reception) {
state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
for (i = 1; i < 3; i++)
nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
state->seg_diff_mask |= 1 << permu_seg[i+1];
} else {
for (i = 0; i < 3; i++)
nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
state->seg_diff_mask |= 1 << permu_seg[i];
}
if (state->seg_diff_mask)
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
else
dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */
for (i = 0; i < 3; i++)
max_constellation = dib8000_set_layer(state, i, max_constellation);
if (autosearching == 0) {
state->layer_b_nb_seg = c->layer[1].segment_count;
state->layer_c_nb_seg = c->layer[2].segment_count;
}
/* WRITE: Mode & Diff mask */
dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
state->differential_constellation = (state->seg_diff_mask != 0);
/* channel estimation fine configuration */
ana_gain = dib8000_adp_fine_tune(state, max_constellation);
/* update ana_gain depending on max constellation */
dib8000_update_ana_gain(state, ana_gain);
/* ---- ANA_FE ---- */
if (c->isdbt_partial_reception) /* 3-segments */
dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);
else
dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
/* TSB or ISDBT ? apply it now */
if (c->isdbt_sb_mode) {
dib8000_set_sb_channel(state);
init_prbs = dib8000_get_init_prbs(state,
c->isdbt_sb_subchannel);
} else {
dib8000_set_13seg_channel(state);
init_prbs = 0xfff;
}
/* SMALL */
dib8000_small_fine_tune(state);
dib8000_set_subchannel_prbs(state, init_prbs);
/* ---- CHAN_BLK ---- */
for (i = 0; i < 13; i++) {
if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
}
}
dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */
dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */
/* "P_cspu_left_edge" & "P_cspu_right_edge" not used => do not care */
dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
if (!autosearching)
dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
else
dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */
dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
/* ---- TMCC ---- */
for (i = 0; i < 3; i++)
tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;
/* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */
/* Threshold is set at 1/4 of max power. */
tmcc_pow *= (1 << (9-2));
dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */
dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */
dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */
/*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */
/* ---- PHA3 ---- */
if (state->isdbt_cfg_loaded == 0)
dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */
state->isdbt_cfg_loaded = 0;
}
static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,
u32 wait0_ms, u32 wait1_ms, u32 wait2_ms)
{
u32 value = 0; /* P_search_end0 wait time */
u16 reg = 11; /* P_search_end0 start addr */
for (reg = 11; reg < 16; reg += 2) {
if (reg == 11) {
if (state->revision == 0x8090)
value = internal * wait1_ms;
else
value = internal * wait0_ms;
} else if (reg == 13)
value = internal * wait1_ms;
else if (reg == 15)
value = internal * wait2_ms;
dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));
dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));
}
return value;
}
static int dib8000_autosearch_start(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
u8 slist = 0;
u32 value, internal = state->cfg.pll->internal;
if (state->revision == 0x8090)
internal = dib8000_read32(state, 23) / 1000;
if ((state->revision >= 0x8002) &&
(state->autosearch_state == AS_SEARCHING_FFT)) {
dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */
dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */
dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */
dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */
dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
if (state->revision == 0x8090)
value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
else
value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
dib8000_write_word(state, 17, 0);
dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */
dib8000_write_word(state, 19, 0);
dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */
dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */
dib8000_write_word(state, 22, value & 0xffff);
if (state->revision == 0x8090)
dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
else
dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */
/* P_search_param_select = (1 | 1<<4 | 1 << 8) */
dib8000_write_word(state, 356, 0);
dib8000_write_word(state, 357, 0x111);
dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
} else if ((state->revision >= 0x8002) &&
(state->autosearch_state == AS_SEARCHING_GUARD)) {
c->transmission_mode = TRANSMISSION_MODE_8K;
c->guard_interval = GUARD_INTERVAL_1_8;
c->inversion = 0;
c->layer[0].modulation = QAM_64;
c->layer[0].fec = FEC_2_3;
c->layer[0].interleaving = 0;
c->layer[0].segment_count = 13;
slist = 16;
c->transmission_mode = state->found_nfft;
dib8000_set_isdbt_common_channel(state, slist, 1);
/* set lock_mask values */
dib8000_write_word(state, 6, 0x4);
if (state->revision == 0x8090)
dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */
else
dib8000_write_word(state, 7, 0x8);
dib8000_write_word(state, 8, 0x1000);
/* set lock_mask wait time values */
if (state->revision == 0x8090)
dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
else
dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */
/* P_search_param_select = 0xf; look for the 4 different guard intervals */
dib8000_write_word(state, 356, 0);
dib8000_write_word(state, 357, 0xf);
value = dib8000_read_word(state, 0);
dib8000_write_word(state, 0, (u16)((1 << 15) | value));
dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
dib8000_write_word(state, 0, (u16)value);
} else {
c->inversion = 0;
c->layer[0].modulation = QAM_64;
c->layer[0].fec = FEC_2_3;
c->layer[0].interleaving = 0;
c->layer[0].segment_count = 13;
if (!c->isdbt_sb_mode)
c->layer[0].segment_count = 13;
/* choose the right list, in sb, always do everything */
if (c->isdbt_sb_mode) {
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
} else {
if (c->guard_interval == GUARD_INTERVAL_AUTO) {
if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
c->transmission_mode = TRANSMISSION_MODE_8K;
c->guard_interval = GUARD_INTERVAL_1_8;
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */
} else {
c->guard_interval = GUARD_INTERVAL_1_8;
slist = 3;
}
} else {
if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
c->transmission_mode = TRANSMISSION_MODE_8K;
slist = 2;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */
} else
slist = 0;
}
}
dprintk("Using list for autosearch : %d\n", slist);
dib8000_set_isdbt_common_channel(state, slist, 1);
/* set lock_mask values */
dib8000_write_word(state, 6, 0x4);
if (state->revision == 0x8090)
dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));
else
dib8000_write_word(state, 7, 0x8);
dib8000_write_word(state, 8, 0x1000);
/* set lock_mask wait time values */
if (state->revision == 0x8090)
dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
else
dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
value = dib8000_read_word(state, 0);
dib8000_write_word(state, 0, (u16)((1 << 15) | value));
dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
dib8000_write_word(state, 0, (u16)value);
}
return 0;
}
static int dib8000_autosearch_irq(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 irq_pending = dib8000_read_word(state, 1284);
if ((state->revision >= 0x8002) &&
(state->autosearch_state == AS_SEARCHING_FFT)) {
if (irq_pending & 0x1) {
dprintk("dib8000_autosearch_irq: max correlation result available\n");
return 3;
}
} else {
if (irq_pending & 0x1) { /* failed */
dprintk("dib8000_autosearch_irq failed\n");
return 1;
}
if (irq_pending & 0x2) { /* succeeded */
dprintk("dib8000_autosearch_irq succeeded\n");
return 2;
}
}
return 0; // still pending
}
static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)
{
u16 tmp;
tmp = dib8000_read_word(state, 771);
if (onoff) /* start P_restart_chd : channel_decoder */
dib8000_write_word(state, 771, tmp & 0xfffd);
else /* stop P_restart_chd : channel_decoder */
dib8000_write_word(state, 771, tmp | (1<<1));
}
static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)
{
s16 unit_khz_dds_val;
u32 abs_offset_khz = abs(offset_khz);
u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
u8 ratio;
if (state->revision == 0x8090) {
ratio = 4;
unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);
if (offset_khz < 0)
dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val);
else
dds = (abs_offset_khz * unit_khz_dds_val);
if (invert)
dds = (1<<26) - dds;
} else {
ratio = 2;
unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
if (offset_khz < 0)
unit_khz_dds_val *= -1;
/* IF tuner */
if (invert)
dds -= abs_offset_khz * unit_khz_dds_val;
else
dds += abs_offset_khz * unit_khz_dds_val;
}
dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val);
if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
/* Max dds offset is the half of the demod freq */
dib8000_write_word(state, 26, invert);
dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);
dib8000_write_word(state, 28, (u16)(dds & 0xffff));
}
}
static void dib8000_set_frequency_offset(struct dib8000_state *state)
{
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
int i;
u32 current_rf;
int total_dds_offset_khz;
if (state->fe[0]->ops.tuner_ops.get_frequency)
state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf);
else
current_rf = c->frequency;
current_rf /= 1000;
total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000;
if (c->isdbt_sb_mode) {
state->subchannel = c->isdbt_sb_subchannel;
i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
dib8000_write_word(state, 26, c->inversion ^ i);
if (state->cfg.pll->ifreq == 0) { /* low if tuner */
if ((c->inversion ^ i) == 0)
dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
} else {
if ((c->inversion ^ i) == 0)
total_dds_offset_khz *= -1;
}
}
dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz);
/* apply dds offset now */
dib8000_set_dds(state, total_dds_offset_khz);
}
static u16 LUT_isdbt_symbol_duration[4] = { 26, 101, 63 };
static u32 dib8000_get_symbol_duration(struct dib8000_state *state)
{
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
u16 i;
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
i = 0;
break;
case TRANSMISSION_MODE_4K:
i = 2;
break;
default:
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
i = 1;
break;
}
return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1;
}
static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step)
{
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
u16 reg_32 = 0, reg_37 = 0;
switch (loop_step) {
case LOOP_TUNE_1:
if (c->isdbt_sb_mode) {
if (c->isdbt_partial_reception == 0) {
reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
} else { /* Sound Broadcasting mode 3 seg */
reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */
}
} else { /* 13-seg start conf offset loop parameters */
reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
}
break;
case LOOP_TUNE_2:
if (c->isdbt_sb_mode) {
if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */
reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
} else { /* Sound Broadcasting mode 3 seg */
reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
}
} else { /* 13 seg */
reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
}
break;
}
dib8000_write_word(state, 32, reg_32);
dib8000_write_word(state, 37, reg_37);
}
static void dib8000_demod_restart(struct dib8000_state *state)
{
dib8000_write_word(state, 770, 0x4000);
dib8000_write_word(state, 770, 0x0000);
return;
}
static void dib8000_set_sync_wait(struct dib8000_state *state)
{
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
u16 sync_wait = 64;
/* P_dvsy_sync_wait - reuse mode */
switch (c->transmission_mode) {
case TRANSMISSION_MODE_8K:
sync_wait = 256;
break;
case TRANSMISSION_MODE_4K:
sync_wait = 128;
break;
default:
case TRANSMISSION_MODE_2K:
sync_wait = 64;
break;
}
if (state->cfg.diversity_delay == 0)
sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */
else
sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
}
static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)
{
if (mode == SYMBOL_DEPENDENT_ON)
delay *= state->symbol_duration;
return jiffies + usecs_to_jiffies(delay * 100);
}
static s32 dib8000_get_status(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
return state->status;
}
static enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
return state->tune_state;
}
static int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{
struct dib8000_state *state = fe->demodulator_priv;
state->tune_state = tune_state;
return 0;
}
static int dib8000_tune_restart_from_demod(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
state->status = FE_STATUS_TUNE_PENDING;
state->tune_state = CT_DEMOD_START;
return 0;
}
static u16 dib8000_read_lock(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
if (state->revision == 0x8090)
return dib8000_read_word(state, 570);
return dib8000_read_word(state, 568);
}
static int dib8090p_init_sdram(struct dib8000_state *state)
{
u16 reg = 0;
dprintk("init sdram\n");
reg = dib8000_read_word(state, 274) & 0xfff0;
dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */
dib8000_write_word(state, 1803, (7 << 2));
reg = dib8000_read_word(state, 1280);
dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */
dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */
return 0;
}
/**
* is_manual_mode - Check if TMCC should be used for parameters settings
* @c: struct dvb_frontend_properties
*
* By default, TMCC table should be used for parameter settings on most
* usercases. However, sometimes it is desirable to lock the demod to
* use the manual parameters.
*
* On manual mode, the current dib8000_tune state machine is very restrict:
* It requires that both per-layer and per-transponder parameters to be
* properly specified, otherwise the device won't lock.
*
* Check if all those conditions are properly satisfied before allowing
* the device to use the manual frequency lock mode.
*/
static int is_manual_mode(struct dtv_frontend_properties *c)
{
int i, n_segs = 0;
/* Use auto mode on DVB-T compat mode */
if (c->delivery_system != SYS_ISDBT)
return 0;
/*
* Transmission mode is only detected on auto mode, currently
*/
if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
dprintk("transmission mode auto\n");
return 0;
}
/*
* Guard interval is only detected on auto mode, currently
*/
if (c->guard_interval == GUARD_INTERVAL_AUTO) {
dprintk("guard interval auto\n");
return 0;
}
/*
* If no layer is enabled, assume auto mode, as at least one
* layer should be enabled
*/
if (!c->isdbt_layer_enabled) {
dprintk("no layer modulation specified\n");
return 0;
}
/*
* Check if the per-layer parameters aren't auto and
* disable a layer if segment count is 0 or invalid.
*/
for (i = 0; i < 3; i++) {
if (!(c->isdbt_layer_enabled & 1 << i))
continue;
if ((c->layer[i].segment_count > 13) ||
(c->layer[i].segment_count == 0)) {
c->isdbt_layer_enabled &= ~(1 << i);
continue;
}
n_segs += c->layer[i].segment_count;
if ((c->layer[i].modulation == QAM_AUTO) ||
(c->layer[i].fec == FEC_AUTO)) {
dprintk("layer %c has either modulation or FEC auto\n",
'A' + i);
return 0;
}
}
/*
* Userspace specified a wrong number of segments.
* fallback to auto mode.
*/
if (n_segs == 0 || n_segs > 13) {
dprintk("number of segments is invalid\n");
return 0;
}
/* Everything looks ok for manual mode */
return 1;
}
static int dib8000_tune(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
enum frontend_tune_state *tune_state = &state->tune_state;
u16 locks, deeper_interleaver = 0, i;
int ret = 1; /* 1 symbol duration (in 100us unit) delay most of the time */
unsigned long *timeout = &state->timeout;
unsigned long now = jiffies;
u16 init_prbs;
#ifdef DIB8000_AGC_FREEZE
u16 agc1, agc2;
#endif
u32 corm[4] = {0, 0, 0, 0};
u8 find_index, max_value;
#if 0
if (*tune_state < CT_DEMOD_STOP)
dprintk("IN: context status = %d, TUNE_STATE %d autosearch step = %u jiffies = %lu\n",
state->channel_parameters_set, *tune_state, state->autosearch_state, now);
#endif
switch (*tune_state) {
case CT_DEMOD_START: /* 30 */
dib8000_reset_stats(fe);
if (state->revision == 0x8090)
dib8090p_init_sdram(state);
state->status = FE_STATUS_TUNE_PENDING;
state->channel_parameters_set = is_manual_mode(c);
dprintk("Tuning channel on %s search mode\n",
state->channel_parameters_set ? "manual" : "auto");
dib8000_viterbi_state(state, 0); /* force chan dec in restart */
/* Layer monitor */
dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
dib8000_set_frequency_offset(state);
dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000);
if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
#ifdef DIB8000_AGC_FREEZE
if (state->revision != 0x8090) {
state->agc1_max = dib8000_read_word(state, 108);
state->agc1_min = dib8000_read_word(state, 109);
state->agc2_max = dib8000_read_word(state, 110);
state->agc2_min = dib8000_read_word(state, 111);
agc1 = dib8000_read_word(state, 388);
agc2 = dib8000_read_word(state, 389);
dib8000_write_word(state, 108, agc1);
dib8000_write_word(state, 109, agc1);
dib8000_write_word(state, 110, agc2);
dib8000_write_word(state, 111, agc2);
}
#endif
state->autosearch_state = AS_SEARCHING_FFT;
state->found_nfft = TRANSMISSION_MODE_AUTO;
state->found_guard = GUARD_INTERVAL_AUTO;
*tune_state = CT_DEMOD_SEARCH_NEXT;
} else { /* we already know the channel struct so TUNE only ! */
state->autosearch_state = AS_DONE;
*tune_state = CT_DEMOD_STEP_3;
}
state->symbol_duration = dib8000_get_symbol_duration(state);
break;
case CT_DEMOD_SEARCH_NEXT: /* 51 */
dib8000_autosearch_start(fe);
if (state->revision == 0x8090)
ret = 50;
else
ret = 15;
*tune_state = CT_DEMOD_STEP_1;
break;
case CT_DEMOD_STEP_1: /* 31 */
switch (dib8000_autosearch_irq(fe)) {
case 1: /* fail */
state->status = FE_STATUS_TUNE_FAILED;
state->autosearch_state = AS_DONE;
*tune_state = CT_DEMOD_STOP; /* else we are done here */
break;
case 2: /* Success */
state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
*tune_state = CT_DEMOD_STEP_3;
if (state->autosearch_state == AS_SEARCHING_GUARD)
*tune_state = CT_DEMOD_STEP_2;
else
state->autosearch_state = AS_DONE;
break;
case 3: /* Autosearch FFT max correlation endded */
*tune_state = CT_DEMOD_STEP_2;
break;
}
break;
case CT_DEMOD_STEP_2:
switch (state->autosearch_state) {
case AS_SEARCHING_FFT:
/* searching for the correct FFT */
if (state->revision == 0x8090) {
corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
} else {
corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
}
/* dprintk("corm fft: %u %u %u\n", corm[0], corm[1], corm[2]); */
max_value = 0;
for (find_index = 1 ; find_index < 3 ; find_index++) {
if (corm[max_value] < corm[find_index])
max_value = find_index ;
}
switch (max_value) {
case 0:
state->found_nfft = TRANSMISSION_MODE_2K;
break;
case 1:
state->found_nfft = TRANSMISSION_MODE_4K;
break;
case 2:
default:
state->found_nfft = TRANSMISSION_MODE_8K;
break;
}
/* dprintk("Autosearch FFT has found Mode %d\n", max_value + 1); */
*tune_state = CT_DEMOD_SEARCH_NEXT;
state->autosearch_state = AS_SEARCHING_GUARD;
if (state->revision == 0x8090)
ret = 50;
else
ret = 10;
break;
case AS_SEARCHING_GUARD:
/* searching for the correct guard interval */
if (state->revision == 0x8090)
state->found_guard = dib8000_read_word(state, 572) & 0x3;
else
state->found_guard = dib8000_read_word(state, 570) & 0x3;
/* dprintk("guard interval found=%i\n", state->found_guard); */
*tune_state = CT_DEMOD_STEP_3;
break;
default:
/* the demod should never be in this state */
state->status = FE_STATUS_TUNE_FAILED;
state->autosearch_state = AS_DONE;
*tune_state = CT_DEMOD_STOP; /* else we are done here */
break;
}
break;
case CT_DEMOD_STEP_3: /* 33 */
dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);
dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */
*tune_state = CT_DEMOD_STEP_4;
break;
case CT_DEMOD_STEP_4: /* (34) */
dib8000_demod_restart(state);
dib8000_set_sync_wait(state);
dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
/* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */
*timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
*tune_state = CT_DEMOD_STEP_5;
break;
case CT_DEMOD_STEP_5: /* (35) */
locks = dib8000_read_lock(fe);
if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */
dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
if (!state->differential_constellation) {
/* 2 times lmod4_win_len + 10 symbols (pipe delay after coff + nb to compute a 1st correlation) */
*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
*tune_state = CT_DEMOD_STEP_7;
} else {
*tune_state = CT_DEMOD_STEP_8;
}
} else if (time_after(now, *timeout)) {
*tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
}
break;
case CT_DEMOD_STEP_6: /* (36) if there is an input (diversity) */
if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
/* if there is a diversity fe in input and this fe is has not already failed : wait here until this fe has succeeded or failed */
if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
*tune_state = CT_DEMOD_STEP_8; /* go for mpeg */
else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failed also, break the current one */
*tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
dib8000_viterbi_state(state, 1); /* start viterbi chandec */
dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
state->status = FE_STATUS_TUNE_FAILED;
}
} else {
dib8000_viterbi_state(state, 1); /* start viterbi chandec */
dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
*tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
state->status = FE_STATUS_TUNE_FAILED;
}
break;
case CT_DEMOD_STEP_7: /* 37 */
locks = dib8000_read_lock(fe);
if (locks & (1<<10)) { /* lmod4_lock */
ret = 14; /* wait for 14 symbols */
*tune_state = CT_DEMOD_STEP_8;
} else if (time_after(now, *timeout))
*tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
break;
case CT_DEMOD_STEP_8: /* 38 */
dib8000_viterbi_state(state, 1); /* start viterbi chandec */
dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
/* mpeg will never lock on this condition because init_prbs is not set : search for it !*/
if (c->isdbt_sb_mode
&& c->isdbt_sb_subchannel < 14
&& !state->differential_constellation) {
state->subchannel = 0;
*tune_state = CT_DEMOD_STEP_11;
} else {
*tune_state = CT_DEMOD_STEP_9;
state->status = FE_STATUS_LOCKED;
}
break;
case CT_DEMOD_STEP_9: /* 39 */
if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
/* defines timeout for mpeg lock depending on interleaver length of longest layer */
for (i = 0; i < 3; i++) {
if (c->layer[i].interleaving >= deeper_interleaver) {
dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving);
if (c->layer[i].segment_count > 0) { /* valid layer */
deeper_interleaver = c->layer[0].interleaving;
state->longest_intlv_layer = i;
}
}
}
if (deeper_interleaver == 0)
locks = 2; /* locks is the tmp local variable name */
else if (deeper_interleaver == 3)
locks = 8;
else
locks = 2 * deeper_interleaver;
if (state->diversity_onoff != 0) /* because of diversity sync */
locks *= 2;
*timeout = now + msecs_to_jiffies(200 * locks); /* give the mpeg lock 800ms if sram is present */
dprintk("Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %ld\n",
deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
*tune_state = CT_DEMOD_STEP_10;
} else
*tune_state = CT_DEMOD_STOP;
break;
case CT_DEMOD_STEP_10: /* 40 */
locks = dib8000_read_lock(fe);
if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n",
c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
if (c->isdbt_sb_mode
&& c->isdbt_sb_subchannel < 14
&& !state->differential_constellation)
/* signal to the upper layer, that there was a channel found and the parameters can be read */
state->status = FE_STATUS_DEMOD_SUCCESS;
else
state->status = FE_STATUS_DATA_LOCKED;
*tune_state = CT_DEMOD_STOP;
} else if (time_after(now, *timeout)) {
if (c->isdbt_sb_mode
&& c->isdbt_sb_subchannel < 14
&& !state->differential_constellation) { /* continue to try init prbs autosearch */
state->subchannel += 3;
*tune_state = CT_DEMOD_STEP_11;
} else { /* we are done mpeg of the longest interleaver xas not locking but let's try if an other layer has locked in the same time */
if (locks & (0x7 << 5)) {
dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n",
jiffies_to_msecs(now - *timeout),
c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
state->status = FE_STATUS_DATA_LOCKED;
} else
state->status = FE_STATUS_TUNE_FAILED;
*tune_state = CT_DEMOD_STOP;
}
}
break;
case CT_DEMOD_STEP_11: /* 41 : init prbs autosearch */
init_prbs = dib8000_get_init_prbs(state, state->subchannel);
if (init_prbs) {
dib8000_set_subchannel_prbs(state, init_prbs);
*tune_state = CT_DEMOD_STEP_9;
} else {
*tune_state = CT_DEMOD_STOP;
state->status = FE_STATUS_TUNE_FAILED;
}
break;
default:
break;
}
/* tuning is finished - cleanup the demod */
switch (*tune_state) {
case CT_DEMOD_STOP: /* (42) */
#ifdef DIB8000_AGC_FREEZE
if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
dib8000_write_word(state, 108, state->agc1_max);
dib8000_write_word(state, 109, state->agc1_min);
dib8000_write_word(state, 110, state->agc2_max);
dib8000_write_word(state, 111, state->agc2_min);
state->agc1_max = 0;
state->agc1_min = 0;
state->agc2_max = 0;
state->agc2_min = 0;
}
#endif
ret = 0;
break;
default:
break;
}
if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3))
return ret * state->symbol_duration;
if ((ret > 0) && (ret < state->symbol_duration))
return state->symbol_duration; /* at least one symbol */
return ret;
}
static int dib8000_wakeup(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
int ret;
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
dib8000_set_adc_state(state, DIBX000_ADC_ON);
if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
dprintk("could not start Slow ADC\n");
if (state->revision == 0x8090)
dib8000_sad_calib(state);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
if (ret < 0)
return ret;
}
return 0;
}
static int dib8000_sleep(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
int ret;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
if (ret < 0)
return ret;
}
if (state->revision != 0x8090)
dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
}
static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat);
static int dib8000_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 i, val = 0;
enum fe_status stat = 0;
u8 index_frontend, sub_index_frontend;
c->bandwidth_hz = 6000000;
/*
* If called to early, get_frontend makes dib8000_tune to either
* not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail.
* So, let's just return if frontend 0 has not locked.
*/
dib8000_read_status(fe, &stat);
if (!(stat & FE_HAS_SYNC))
return 0;
dprintk("dib8000_get_frontend: TMCC lock\n");
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
if (stat&FE_HAS_SYNC) {
dprintk("TMCC lock on the slave%i\n", index_frontend);
/* synchronize the cache with the other frontends */
state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
if (sub_index_frontend != index_frontend) {
state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
for (i = 0; i < 3; i++) {
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
}
}
}
return 0;
}
}
c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
if (state->revision == 0x8090)
val = dib8000_read_word(state, 572);
else
val = dib8000_read_word(state, 570);
c->inversion = (val & 0x40) >> 6;
switch ((val & 0x30) >> 4) {
case 1:
c->transmission_mode = TRANSMISSION_MODE_2K;
dprintk("dib8000_get_frontend: transmission mode 2K\n");
break;
case 2:
c->transmission_mode = TRANSMISSION_MODE_4K;
dprintk("dib8000_get_frontend: transmission mode 4K\n");
break;
case 3:
default:
c->transmission_mode = TRANSMISSION_MODE_8K;
dprintk("dib8000_get_frontend: transmission mode 8K\n");
break;
}
switch (val & 0x3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
dprintk("dib8000_get_frontend: Guard Interval = 1/32\n");
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
dprintk("dib8000_get_frontend: Guard Interval = 1/16\n");
break;
case 2:
dprintk("dib8000_get_frontend: Guard Interval = 1/8\n");
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
dprintk("dib8000_get_frontend: Guard Interval = 1/4\n");
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
val = dib8000_read_word(state, 505);
c->isdbt_partial_reception = val & 1;
dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception);
for (i = 0; i < 3; i++) {
int show;
val = dib8000_read_word(state, 493 + i) & 0x0f;
c->layer[i].segment_count = val;
if (val == 0 || val > 13)
show = 0;
else
show = 1;
if (show)
dprintk("dib8000_get_frontend: Layer %d segments = %d\n",
i, c->layer[i].segment_count);
val = dib8000_read_word(state, 499 + i) & 0x3;
/* Interleaving can be 0, 1, 2 or 4 */
if (val == 3)
val = 4;
c->layer[i].interleaving = val;
if (show)
dprintk("dib8000_get_frontend: Layer %d time_intlv = %d\n",
i, c->layer[i].interleaving);
val = dib8000_read_word(state, 481 + i);
switch (val & 0x7) {
case 1:
c->layer[i].fec = FEC_1_2;
if (show)
dprintk("dib8000_get_frontend: Layer %d Code Rate = 1/2\n", i);
break;
case 2:
c->layer[i].fec = FEC_2_3;
if (show)
dprintk("dib8000_get_frontend: Layer %d Code Rate = 2/3\n", i);
break;
case 3:
c->layer[i].fec = FEC_3_4;
if (show)
dprintk("dib8000_get_frontend: Layer %d Code Rate = 3/4\n", i);
break;
case 5:
c->layer[i].fec = FEC_5_6;
if (show)
dprintk("dib8000_get_frontend: Layer %d Code Rate = 5/6\n", i);
break;
default:
c->layer[i].fec = FEC_7_8;
if (show)
dprintk("dib8000_get_frontend: Layer %d Code Rate = 7/8\n", i);
break;
}
val = dib8000_read_word(state, 487 + i);
switch (val & 0x3) {
case 0:
c->layer[i].modulation = DQPSK;
if (show)
dprintk("dib8000_get_frontend: Layer %d DQPSK\n", i);
break;
case 1:
c->layer[i].modulation = QPSK;
if (show)
dprintk("dib8000_get_frontend: Layer %d QPSK\n", i);
break;
case 2:
c->layer[i].modulation = QAM_16;
if (show)
dprintk("dib8000_get_frontend: Layer %d QAM16\n", i);
break;
case 3:
default:
c->layer[i].modulation = QAM_64;
if (show)
dprintk("dib8000_get_frontend: Layer %d QAM64\n", i);
break;
}
}
/* synchronize the cache with the other frontends */
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;
state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;
for (i = 0; i < 3; i++) {
state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;
state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;
state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;
state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;
}
}
return 0;
}
static int dib8000_set_frontend(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
int l, i, active, time, time_slave = 0;
u8 exit_condition, index_frontend;
unsigned long delay, callback_time;
if (c->frequency == 0) {
dprintk("dib8000: must at least specify frequency\n");
return 0;
}
if (c->bandwidth_hz == 0) {
dprintk("dib8000: no bandwidth specified, set to default\n");
c->bandwidth_hz = 6000000;
}
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
/* synchronization of the cache */
state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
/* set output mode and diversity input */
if (state->revision != 0x8090) {
dib8000_set_diversity_in(state->fe[index_frontend], 1);
if (index_frontend != 0)
dib8000_set_output_mode(state->fe[index_frontend],
OUTMODE_DIVERSITY);
else
dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
} else {
dib8096p_set_diversity_in(state->fe[index_frontend], 1);
if (index_frontend != 0)
dib8096p_set_output_mode(state->fe[index_frontend],
OUTMODE_DIVERSITY);
else
dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
}
/* tune the tuner */
if (state->fe[index_frontend]->ops.tuner_ops.set_params)
state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
}
/* turn off the diversity of the last chip */
if (state->revision != 0x8090)
dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
else
dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
/* start up the AGC */
do {
time = dib8000_agc_startup(state->fe[0]);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
time_slave = dib8000_agc_startup(state->fe[index_frontend]);
if (time == 0)
time = time_slave;
else if ((time_slave != 0) && (time_slave > time))
time = time_slave;
}
if (time == 0)
break;
/*
* Despite dib8000_agc_startup returns time at a 0.1 ms range,
* the actual sleep time depends on CONFIG_HZ. The worse case
* is when CONFIG_HZ=100. In such case, the minimum granularity
* is 10ms. On some real field tests, the tuner sometimes don't
* lock when this timer is lower than 10ms. So, enforce a 10ms
* granularity.
*/
time = 10 * (time + 99)/100;
usleep_range(time * 1000, (time + 1) * 1000);
exit_condition = 1;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
exit_condition = 0;
break;
}
}
} while (exit_condition == 0);
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
active = 1;
do {
callback_time = 0;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
delay = dib8000_tune(state->fe[index_frontend]);
if (delay != 0) {
delay = jiffies + usecs_to_jiffies(100 * delay);
if (!callback_time || delay < callback_time)
callback_time = delay;
}
/* we are in autosearch */
if (state->channel_parameters_set == 0) { /* searching */
if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
dprintk("autosearch succeeded on fe%i\n", index_frontend);
dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */
state->channel_parameters_set = 1;
for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
if (l != index_frontend) { /* and for all frontend except the successful one */
dprintk("Restarting frontend %d\n", l);
dib8000_tune_restart_from_demod(state->fe[l]);
state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
for (i = 0; i < 3; i++) {
state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
}
}
}
}
}
}
/* tuning is done when the master frontend is done (failed or success) */
if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
active = 0;
/* we need to wait for all frontends to be finished */
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
active = 1;
}
if (active == 0)
dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));
}
if ((active == 1) && (callback_time == 0)) {
dprintk("strange callback time something went wrong\n");
active = 0;
}
while ((active == 1) && (time_before(jiffies, callback_time)))
msleep(100);
} while (active);
/* set output mode */
if (state->revision != 0x8090)
dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
else {
dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
if (state->cfg.enMpegOutput == 0) {
dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
}
}
return 0;
}
static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat);
static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 lock_slave = 0, lock;
u8 index_frontend;
lock = dib8000_read_lock(fe);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
*stat = 0;
if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
*stat |= FE_HAS_SIGNAL;
if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
*stat |= FE_HAS_CARRIER;
if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
*stat |= FE_HAS_SYNC;
if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
*stat |= FE_HAS_LOCK;
if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
}
dib8000_get_stats(fe, *stat);
return 0;
}
static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib8000_state *state = fe->demodulator_priv;
/* 13 segments */
if (state->revision == 0x8090)
*ber = (dib8000_read_word(state, 562) << 16) |
dib8000_read_word(state, 563);
else
*ber = (dib8000_read_word(state, 560) << 16) |
dib8000_read_word(state, 561);
return 0;
}
static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib8000_state *state = fe->demodulator_priv;
/* packet error on 13 seg */
if (state->revision == 0x8090)
*unc = dib8000_read_word(state, 567);
else
*unc = dib8000_read_word(state, 565);
return 0;
}
static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
u16 val;
*strength = 0;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
}
val = 65535 - dib8000_read_word(state, 390);
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
return 0;
}
static u32 dib8000_get_snr(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 n, s, exp;
u16 val;
if (state->revision != 0x8090)
val = dib8000_read_word(state, 542);
else
val = dib8000_read_word(state, 544);
n = (val >> 6) & 0xff;
exp = (val & 0x3f);
if ((exp & 0x20) != 0)
exp -= 0x40;
n <<= exp+16;
if (state->revision != 0x8090)
val = dib8000_read_word(state, 543);
else
val = dib8000_read_word(state, 545);
s = (val >> 6) & 0xff;
exp = (val & 0x3f);
if ((exp & 0x20) != 0)
exp -= 0x40;
s <<= exp+16;
if (n > 0) {
u32 t = (s/n) << 16;
return t + ((s << 16) - n*t) / n;
}
return 0xffffffff;
}
static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
u32 snr_master;
snr_master = dib8000_get_snr(fe);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
snr_master += dib8000_get_snr(state->fe[index_frontend]);
if ((snr_master >> 16) != 0) {
snr_master = 10*intlog10(snr_master>>16);
*snr = snr_master / ((1 << 24) / 10);
}
else
*snr = 0;
return 0;
}
struct per_layer_regs {
u16 lock, ber, per;
};
static const struct per_layer_regs per_layer_regs[] = {
{ 554, 560, 562 },
{ 555, 576, 578 },
{ 556, 581, 583 },
};
struct linear_segments {
unsigned x;
signed y;
};
/*
* Table to estimate signal strength in dBm.
* This table was empirically determinated by measuring the signal
* strength generated by a DTA-2111 RF generator directly connected into
* a dib8076 device (a PixelView PV-D231U stick), using a good quality
* 3 meters RC6 cable and good RC6 connectors.
* The real value can actually be different on other devices, depending
* on several factors, like if LNA is enabled or not, if diversity is
* enabled, type of connectors, etc.
* Yet, it is better to use this measure in dB than a random non-linear
* percentage value, especially for antenna adjustments.
* On my tests, the precision of the measure using this table is about
* 0.5 dB, with sounds reasonable enough.
*/
static struct linear_segments strength_to_db_table[] = {
{ 55953, 108500 }, /* -22.5 dBm */
{ 55394, 108000 },
{ 53834, 107000 },
{ 52863, 106000 },
{ 52239, 105000 },
{ 52012, 104000 },
{ 51803, 103000 },
{ 51566, 102000 },
{ 51356, 101000 },
{ 51112, 100000 },
{ 50869, 99000 },
{ 50600, 98000 },
{ 50363, 97000 },
{ 50117, 96000 }, /* -35 dBm */
{ 49889, 95000 },
{ 49680, 94000 },
{ 49493, 93000 },
{ 49302, 92000 },
{ 48929, 91000 },
{ 48416, 90000 },
{ 48035, 89000 },
{ 47593, 88000 },
{ 47282, 87000 },
{ 46953, 86000 },
{ 46698, 85000 },
{ 45617, 84000 },
{ 44773, 83000 },
{ 43845, 82000 },
{ 43020, 81000 },
{ 42010, 80000 }, /* -51 dBm */
{ 0, 0 },
};
static u32 interpolate_value(u32 value, struct linear_segments *segments,
unsigned len)
{
u64 tmp64;
u32 dx;
s32 dy;
int i, ret;
if (value >= segments[0].x)
return segments[0].y;
if (value < segments[len-1].x)
return segments[len-1].y;
for (i = 1; i < len - 1; i++) {
/* If value is identical, no need to interpolate */
if (value == segments[i].x)
return segments[i].y;
if (value > segments[i].x)
break;
}
/* Linear interpolation between the two (x,y) points */
dy = segments[i - 1].y - segments[i].y;
dx = segments[i - 1].x - segments[i].x;
tmp64 = value - segments[i].x;
tmp64 *= dy;
do_div(tmp64, dx);
ret = segments[i].y + tmp64;
return ret;
}
static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
int ini_layer, end_layer, i;
u64 time_us, tmp64;
u32 tmp, denom;
int guard, rate_num, rate_denum = 1, bits_per_symbol, nsegs;
int interleaving = 0, fft_div;
if (layer >= 0) {
ini_layer = layer;
end_layer = layer + 1;
} else {
ini_layer = 0;
end_layer = 3;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_1_4:
guard = 4;
break;
case GUARD_INTERVAL_1_8:
guard = 8;
break;
case GUARD_INTERVAL_1_16:
guard = 16;
break;
default:
case GUARD_INTERVAL_1_32:
guard = 32;
break;
}
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
fft_div = 4;
break;
case TRANSMISSION_MODE_4K:
fft_div = 2;
break;
default:
case TRANSMISSION_MODE_8K:
fft_div = 1;
break;
}
denom = 0;
for (i = ini_layer; i < end_layer; i++) {
nsegs = c->layer[i].segment_count;
if (nsegs == 0 || nsegs > 13)
continue;
switch (c->layer[i].modulation) {
case DQPSK:
case QPSK:
bits_per_symbol = 2;
break;
case QAM_16:
bits_per_symbol = 4;
break;
default:
case QAM_64:
bits_per_symbol = 6;
break;
}
switch (c->layer[i].fec) {
case FEC_1_2:
rate_num = 1;
rate_denum = 2;
break;
case FEC_2_3:
rate_num = 2;
rate_denum = 3;
break;
case FEC_3_4:
rate_num = 3;
rate_denum = 4;
break;
case FEC_5_6:
rate_num = 5;
rate_denum = 6;
break;
default:
case FEC_7_8:
rate_num = 7;
rate_denum = 8;
break;
}
interleaving = c->layer[i].interleaving;
denom += bits_per_symbol * rate_num * fft_div * nsegs * 384;
}
/* If all goes wrong, wait for 1s for the next stats */
if (!denom)
return 0;
/* Estimate the period for the total bit rate */
time_us = rate_denum * (1008 * 1562500L);
tmp64 = time_us;
do_div(tmp64, guard);
time_us = time_us + tmp64;
time_us += denom / 2;
do_div(time_us, denom);
tmp = 1008 * 96 * interleaving;
time_us += tmp + tmp / guard;
return time_us;
}
static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat)
{
struct dib8000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
int i;
int show_per_stats = 0;
u32 time_us = 0, snr, val;
u64 blocks;
s32 db;
u16 strength;
/* Get Signal strength */
dib8000_read_signal_strength(fe, &strength);
val = strength;
db = interpolate_value(val,
strength_to_db_table,
ARRAY_SIZE(strength_to_db_table)) - 131000;
c->strength.stat[0].svalue = db;
/* UCB/BER/CNR measures require lock */
if (!(stat & FE_HAS_LOCK)) {
c->cnr.len = 1;
c->block_count.len = 1;
c->block_error.len = 1;
c->post_bit_error.len = 1;
c->post_bit_count.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
/* Check if time for stats was elapsed */
if (time_after(jiffies, state->per_jiffies_stats)) {
state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
/* Get SNR */
snr = dib8000_get_snr(fe);
for (i = 1; i < MAX_NUMBER_OF_FRONTENDS; i++) {
if (state->fe[i])
snr += dib8000_get_snr(state->fe[i]);
}
snr = snr >> 16;
if (snr) {
snr = 10 * intlog10(snr);
snr = (1000L * snr) >> 24;
} else {
snr = 0;
}
c->cnr.stat[0].svalue = snr;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
/* Get UCB measures */
dib8000_read_unc_blocks(fe, &val);
if (val < state->init_ucb)
state->init_ucb += 0x100000000LL;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = val + state->init_ucb;
/* Estimate the number of packets based on bitrate */
if (!time_us)
time_us = dib8000_get_time_us(fe, -1);
if (time_us) {
blocks = 1250000ULL * 1000000ULL;
do_div(blocks, time_us * 8 * 204);
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += blocks;
}
show_per_stats = 1;
}
/* Get post-BER measures */
if (time_after(jiffies, state->ber_jiffies_stats)) {
time_us = dib8000_get_time_us(fe, -1);
state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
dprintk("Next all layers stats available in %u us.\n", time_us);
dib8000_read_ber(fe, &val);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += val;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += 100000000;
}
if (state->revision < 0x8002)
return 0;
c->block_error.len = 4;
c->post_bit_error.len = 4;
c->post_bit_count.len = 4;
for (i = 0; i < 3; i++) {
unsigned nsegs = c->layer[i].segment_count;
if (nsegs == 0 || nsegs > 13)
continue;
time_us = 0;
if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
time_us = dib8000_get_time_us(fe, i);
state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
dprintk("Next layer %c stats will be available in %u us\n",
'A' + i, time_us);
val = dib8000_read_word(state, per_layer_regs[i].ber);
c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[1 + i].uvalue += val;
c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[1 + i].uvalue += 100000000;
}
if (show_per_stats) {
val = dib8000_read_word(state, per_layer_regs[i].per);
c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
c->block_error.stat[1 + i].uvalue += val;
if (!time_us)
time_us = dib8000_get_time_us(fe, i);
if (time_us) {
blocks = 1250000ULL * 1000000ULL;
do_div(blocks, time_us * 8 * 204);
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += blocks;
}
}
}
return 0;
}
static int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend = 1;
while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
index_frontend++;
if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
dprintk("set slave fe %p to index %i\n", fe_slave, index_frontend);
state->fe[index_frontend] = fe_slave;
return 0;
}
dprintk("too many slave frontend\n");
return -ENOMEM;
}
static struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
{
struct dib8000_state *state = fe->demodulator_priv;
if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
return NULL;
return state->fe[slave_index];
}
static int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
u8 default_addr, u8 first_addr, u8 is_dib8096p)
{
int k = 0, ret = 0;
u8 new_addr = 0;
struct i2c_device client = {.adap = host };
client.i2c_write_buffer = kzalloc(4, GFP_KERNEL);
if (!client.i2c_write_buffer) {
dprintk("%s: not enough memory\n", __func__);
return -ENOMEM;
}
client.i2c_read_buffer = kzalloc(4, GFP_KERNEL);
if (!client.i2c_read_buffer) {
dprintk("%s: not enough memory\n", __func__);
ret = -ENOMEM;
goto error_memory_read;
}
client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
if (!client.i2c_buffer_lock) {
dprintk("%s: not enough memory\n", __func__);
ret = -ENOMEM;
goto error_memory_lock;
}
mutex_init(client.i2c_buffer_lock);
for (k = no_of_demods - 1; k >= 0; k--) {
/* designated i2c address */
new_addr = first_addr + (k << 1);
client.addr = new_addr;
if (!is_dib8096p)
dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
if (dib8000_identify(&client) == 0) {
/* sram lead in, rdy */
if (!is_dib8096p)
dib8000_i2c_write16(&client, 1287, 0x0003);
client.addr = default_addr;
if (dib8000_identify(&client) == 0) {
dprintk("#%d: not identified\n", k);
ret = -EINVAL;
goto error;
}
}
/* start diversity to pull_down div_str - just for i2c-enumeration */
dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
/* set new i2c address and force divstart */
dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
client.addr = new_addr;
dib8000_identify(&client);
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
}
for (k = 0; k < no_of_demods; k++) {
new_addr = first_addr | (k << 1);
client.addr = new_addr;
// unforce divstr
dib8000_i2c_write16(&client, 1285, new_addr << 2);
/* deactivate div - it was just for i2c-enumeration */
dib8000_i2c_write16(&client, 1286, 0);
}
error:
kfree(client.i2c_buffer_lock);
error_memory_lock:
kfree(client.i2c_read_buffer);
error_memory_read:
kfree(client.i2c_write_buffer);
return ret;
}
static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
tune->step_size = 0;
tune->max_drift = 0;
return 0;
}
static void dib8000_release(struct dvb_frontend *fe)
{
struct dib8000_state *st = fe->demodulator_priv;
u8 index_frontend;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
dvb_frontend_detach(st->fe[index_frontend]);
dibx000_exit_i2c_master(&st->i2c_master);
i2c_del_adapter(&st->dib8096p_tuner_adap);
kfree(st->fe[0]);
kfree(st);
}
static struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
{
struct dib8000_state *st = fe->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
}
static int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
u16 val = dib8000_read_word(st, 299) & 0xffef;
val |= (onoff & 0x1) << 4;
dprintk("pid filter enabled %d\n", onoff);
return dib8000_write_word(st, 299, val);
}
static int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
dprintk("Index %x, PID %d, OnOff %d\n", id, pid, onoff);
return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
}
static const struct dvb_frontend_ops dib8000_ops = {
.delsys = { SYS_ISDBT },
.info = {
.name = "DiBcom 8000 ISDB-T",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
},
.release = dib8000_release,
.init = dib8000_wakeup,
.sleep = dib8000_sleep,
.set_frontend = dib8000_set_frontend,
.get_tune_settings = dib8000_fe_get_tune_settings,
.get_frontend = dib8000_get_frontend,
.read_status = dib8000_read_status,
.read_ber = dib8000_read_ber,
.read_signal_strength = dib8000_read_signal_strength,
.read_snr = dib8000_read_snr,
.read_ucblocks = dib8000_read_unc_blocks,
};
static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
{
struct dvb_frontend *fe;
struct dib8000_state *state;
dprintk("dib8000_init\n");
state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
if (state == NULL)
return NULL;
fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
if (fe == NULL)
goto error;
memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
state->i2c.adap = i2c_adap;
state->i2c.addr = i2c_addr;
state->i2c.i2c_write_buffer = state->i2c_write_buffer;
state->i2c.i2c_read_buffer = state->i2c_read_buffer;
mutex_init(&state->i2c_buffer_lock);
state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
state->gpio_val = cfg->gpio_val;
state->gpio_dir = cfg->gpio_dir;
/* Ensure the output mode remains at the previous default if it's
* not specifically set by the caller.
*/
if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
state->fe[0] = fe;
fe->demodulator_priv = state;
memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
state->timf_default = cfg->pll->timf;
if (dib8000_identify(&state->i2c) == 0) {
kfree(fe);
goto error;
}
dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
/* init 8096p tuner adapter */
strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
sizeof(state->dib8096p_tuner_adap.name));
state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
state->dib8096p_tuner_adap.algo_data = NULL;
state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
i2c_add_adapter(&state->dib8096p_tuner_adap);
dib8000_reset(fe);
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
state->current_demod_bw = 6000;
return fe;
error:
kfree(state);
return NULL;
}
void *dib8000_attach(struct dib8000_ops *ops)
{
if (!ops)
return NULL;
ops->pwm_agc_reset = dib8000_pwm_agc_reset;
ops->get_dc_power = dib8090p_get_dc_power;
ops->set_gpio = dib8000_set_gpio;
ops->get_slave_frontend = dib8000_get_slave_frontend;
ops->set_tune_state = dib8000_set_tune_state;
ops->pid_filter_ctrl = dib8000_pid_filter_ctrl;
ops->get_adc_power = dib8000_get_adc_power;
ops->update_pll = dib8000_update_pll;
ops->tuner_sleep = dib8096p_tuner_sleep;
ops->get_tune_state = dib8000_get_tune_state;
ops->get_i2c_tuner = dib8096p_get_i2c_tuner;
ops->set_slave_frontend = dib8000_set_slave_frontend;
ops->pid_filter = dib8000_pid_filter;
ops->ctrl_timf = dib8000_ctrl_timf;
ops->init = dib8000_init;
ops->get_i2c_master = dib8000_get_i2c_master;
ops->i2c_enumeration = dib8000_i2c_enumeration;
ops->set_wbd_ref = dib8000_set_wbd_ref;
return ops;
}
EXPORT_SYMBOL_GPL(dib8000_attach);
MODULE_AUTHOR("Olivier Grenie <[email protected], Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib8000.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drxk_hard: DRX-K DVB-C/T demodulator driver
*
* Copyright (C) 2010-2011 Digital Devices GmbH
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/hardirq.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "drxk.h"
#include "drxk_hard.h"
#include <linux/int_log.h>
static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
static int power_down_qam(struct drxk_state *state);
static int set_dvbt_standard(struct drxk_state *state,
enum operation_mode o_mode);
static int set_qam_standard(struct drxk_state *state,
enum operation_mode o_mode);
static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
s32 tuner_freq_offset);
static int set_dvbt_standard(struct drxk_state *state,
enum operation_mode o_mode);
static int dvbt_start(struct drxk_state *state);
static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
s32 tuner_freq_offset);
static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
static int switch_antenna_to_qam(struct drxk_state *state);
static int switch_antenna_to_dvbt(struct drxk_state *state);
static bool is_dvbt(struct drxk_state *state)
{
return state->m_operation_mode == OM_DVBT;
}
static bool is_qam(struct drxk_state *state)
{
return state->m_operation_mode == OM_QAM_ITU_A ||
state->m_operation_mode == OM_QAM_ITU_B ||
state->m_operation_mode == OM_QAM_ITU_C;
}
#define NOA1ROM 0
#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
#define DEFAULT_MER_83 165
#define DEFAULT_MER_93 250
#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
#endif
#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
#endif
#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
#ifndef DRXK_KI_RAGC_ATV
#define DRXK_KI_RAGC_ATV 4
#endif
#ifndef DRXK_KI_IAGC_ATV
#define DRXK_KI_IAGC_ATV 6
#endif
#ifndef DRXK_KI_DAGC_ATV
#define DRXK_KI_DAGC_ATV 7
#endif
#ifndef DRXK_KI_RAGC_QAM
#define DRXK_KI_RAGC_QAM 3
#endif
#ifndef DRXK_KI_IAGC_QAM
#define DRXK_KI_IAGC_QAM 4
#endif
#ifndef DRXK_KI_DAGC_QAM
#define DRXK_KI_DAGC_QAM 7
#endif
#ifndef DRXK_KI_RAGC_DVBT
#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
#endif
#ifndef DRXK_KI_IAGC_DVBT
#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
#endif
#ifndef DRXK_KI_DAGC_DVBT
#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
#endif
#ifndef DRXK_AGC_DAC_OFFSET
#define DRXK_AGC_DAC_OFFSET (0x800)
#endif
#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
#endif
#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
#endif
#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
#endif
#ifndef DRXK_QAM_SYMBOLRATE_MAX
#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
#endif
#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
#define DRXK_BL_ROM_OFFSET_UCODE 0
#define DRXK_BLC_TIMEOUT 100
#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
#endif
#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages");
#define dprintk(level, fmt, arg...) do { \
if (debug >= level) \
printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
} while (0)
static inline u32 Frac28a(u32 a, u32 c)
{
int i = 0;
u32 Q1 = 0;
u32 R0 = 0;
R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
Q1 = a / c; /*
* integer part, only the 4 least significant
* bits will be visible in the result
*/
/* division using radix 16, 7 nibbles in the result */
for (i = 0; i < 7; i++) {
Q1 = (Q1 << 4) | (R0 / c);
R0 = (R0 % c) << 4;
}
/* rounding */
if ((R0 >> 3) >= c)
Q1++;
return Q1;
}
static inline u32 log10times100(u32 value)
{
return (100L * intlog10(value)) >> 24;
}
/***************************************************************************/
/* I2C **********************************************************************/
/***************************************************************************/
static int drxk_i2c_lock(struct drxk_state *state)
{
i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
state->drxk_i2c_exclusive_lock = true;
return 0;
}
static void drxk_i2c_unlock(struct drxk_state *state)
{
if (!state->drxk_i2c_exclusive_lock)
return;
i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
state->drxk_i2c_exclusive_lock = false;
}
static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
unsigned len)
{
if (state->drxk_i2c_exclusive_lock)
return __i2c_transfer(state->i2c, msgs, len);
else
return i2c_transfer(state->i2c, msgs, len);
}
static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
{
struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
.buf = val, .len = 1}
};
return drxk_i2c_transfer(state, msgs, 1);
}
static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
{
int status;
struct i2c_msg msg = {
.addr = adr, .flags = 0, .buf = data, .len = len };
dprintk(3, ": %*ph\n", len, data);
status = drxk_i2c_transfer(state, &msg, 1);
if (status >= 0 && status != 1)
status = -EIO;
if (status < 0)
pr_err("i2c write error at addr 0x%02x\n", adr);
return status;
}
static int i2c_read(struct drxk_state *state,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
int status;
struct i2c_msg msgs[2] = {
{.addr = adr, .flags = 0,
.buf = msg, .len = len},
{.addr = adr, .flags = I2C_M_RD,
.buf = answ, .len = alen}
};
status = drxk_i2c_transfer(state, msgs, 2);
if (status != 2) {
if (debug > 2)
pr_cont(": ERROR!\n");
if (status >= 0)
status = -EIO;
pr_err("i2c read error at addr 0x%02x\n", adr);
return status;
}
dprintk(3, ": read from %*ph, value = %*ph\n", len, msg, alen, answ);
return 0;
}
static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
{
int status;
u8 adr = state->demod_address, mm1[4], mm2[2], len;
if (state->single_master)
flags |= 0xC0;
if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
mm1[0] = (((reg << 1) & 0xFF) | 0x01);
mm1[1] = ((reg >> 16) & 0xFF);
mm1[2] = ((reg >> 24) & 0xFF) | flags;
mm1[3] = ((reg >> 7) & 0xFF);
len = 4;
} else {
mm1[0] = ((reg << 1) & 0xFF);
mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
len = 2;
}
dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
status = i2c_read(state, adr, mm1, len, mm2, 2);
if (status < 0)
return status;
if (data)
*data = mm2[0] | (mm2[1] << 8);
return 0;
}
static int read16(struct drxk_state *state, u32 reg, u16 *data)
{
return read16_flags(state, reg, data, 0);
}
static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
{
int status;
u8 adr = state->demod_address, mm1[4], mm2[4], len;
if (state->single_master)
flags |= 0xC0;
if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
mm1[0] = (((reg << 1) & 0xFF) | 0x01);
mm1[1] = ((reg >> 16) & 0xFF);
mm1[2] = ((reg >> 24) & 0xFF) | flags;
mm1[3] = ((reg >> 7) & 0xFF);
len = 4;
} else {
mm1[0] = ((reg << 1) & 0xFF);
mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
len = 2;
}
dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
status = i2c_read(state, adr, mm1, len, mm2, 4);
if (status < 0)
return status;
if (data)
*data = mm2[0] | (mm2[1] << 8) |
(mm2[2] << 16) | (mm2[3] << 24);
return 0;
}
static int read32(struct drxk_state *state, u32 reg, u32 *data)
{
return read32_flags(state, reg, data, 0);
}
static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
{
u8 adr = state->demod_address, mm[6], len;
if (state->single_master)
flags |= 0xC0;
if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
mm[0] = (((reg << 1) & 0xFF) | 0x01);
mm[1] = ((reg >> 16) & 0xFF);
mm[2] = ((reg >> 24) & 0xFF) | flags;
mm[3] = ((reg >> 7) & 0xFF);
len = 4;
} else {
mm[0] = ((reg << 1) & 0xFF);
mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
len = 2;
}
mm[len] = data & 0xff;
mm[len + 1] = (data >> 8) & 0xff;
dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
return i2c_write(state, adr, mm, len + 2);
}
static int write16(struct drxk_state *state, u32 reg, u16 data)
{
return write16_flags(state, reg, data, 0);
}
static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
{
u8 adr = state->demod_address, mm[8], len;
if (state->single_master)
flags |= 0xC0;
if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
mm[0] = (((reg << 1) & 0xFF) | 0x01);
mm[1] = ((reg >> 16) & 0xFF);
mm[2] = ((reg >> 24) & 0xFF) | flags;
mm[3] = ((reg >> 7) & 0xFF);
len = 4;
} else {
mm[0] = ((reg << 1) & 0xFF);
mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
len = 2;
}
mm[len] = data & 0xff;
mm[len + 1] = (data >> 8) & 0xff;
mm[len + 2] = (data >> 16) & 0xff;
mm[len + 3] = (data >> 24) & 0xff;
dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
return i2c_write(state, adr, mm, len + 4);
}
static int write32(struct drxk_state *state, u32 reg, u32 data)
{
return write32_flags(state, reg, data, 0);
}
static int write_block(struct drxk_state *state, u32 address,
const int block_size, const u8 p_block[])
{
int status = 0, blk_size = block_size;
u8 flags = 0;
if (state->single_master)
flags |= 0xC0;
while (blk_size > 0) {
int chunk = blk_size > state->m_chunk_size ?
state->m_chunk_size : blk_size;
u8 *adr_buf = &state->chunk[0];
u32 adr_length = 0;
if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
adr_buf[1] = ((address >> 16) & 0xFF);
adr_buf[2] = ((address >> 24) & 0xFF);
adr_buf[3] = ((address >> 7) & 0xFF);
adr_buf[2] |= flags;
adr_length = 4;
if (chunk == state->m_chunk_size)
chunk -= 2;
} else {
adr_buf[0] = ((address << 1) & 0xFF);
adr_buf[1] = (((address >> 16) & 0x0F) |
((address >> 18) & 0xF0));
adr_length = 2;
}
memcpy(&state->chunk[adr_length], p_block, chunk);
dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
if (p_block)
dprintk(2, "%*ph\n", chunk, p_block);
status = i2c_write(state, state->demod_address,
&state->chunk[0], chunk + adr_length);
if (status < 0) {
pr_err("%s: i2c write error at addr 0x%02x\n",
__func__, address);
break;
}
p_block += chunk;
address += (chunk >> 1);
blk_size -= chunk;
}
return status;
}
#ifndef DRXK_MAX_RETRIES_POWERUP
#define DRXK_MAX_RETRIES_POWERUP 20
#endif
static int power_up_device(struct drxk_state *state)
{
int status;
u8 data = 0;
u16 retry_count = 0;
dprintk(1, "\n");
status = i2c_read1(state, state->demod_address, &data);
if (status < 0) {
do {
data = 0;
status = i2c_write(state, state->demod_address,
&data, 1);
usleep_range(10000, 11000);
retry_count++;
if (status < 0)
continue;
status = i2c_read1(state, state->demod_address,
&data);
} while (status < 0 &&
(retry_count < DRXK_MAX_RETRIES_POWERUP));
if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
goto error;
}
/* Make sure all clk domains are active */
status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
/* Enable pll lock tests */
status = write16(state, SIO_CC_PLL_LOCK__A, 1);
if (status < 0)
goto error;
state->m_current_power_mode = DRX_POWER_UP;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int init_state(struct drxk_state *state)
{
/*
* FIXME: most (all?) of the values below should be moved into
* struct drxk_config, as they are probably board-specific
*/
u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
u32 ul_vsb_if_agc_output_level = 0;
u32 ul_vsb_if_agc_min_level = 0;
u32 ul_vsb_if_agc_max_level = 0x7FFF;
u32 ul_vsb_if_agc_speed = 3;
u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
u32 ul_vsb_rf_agc_output_level = 0;
u32 ul_vsb_rf_agc_min_level = 0;
u32 ul_vsb_rf_agc_max_level = 0x7FFF;
u32 ul_vsb_rf_agc_speed = 3;
u32 ul_vsb_rf_agc_top = 9500;
u32 ul_vsb_rf_agc_cut_off_current = 4000;
u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
u32 ul_atv_if_agc_output_level = 0;
u32 ul_atv_if_agc_min_level = 0;
u32 ul_atv_if_agc_max_level = 0;
u32 ul_atv_if_agc_speed = 3;
u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
u32 ul_atv_rf_agc_output_level = 0;
u32 ul_atv_rf_agc_min_level = 0;
u32 ul_atv_rf_agc_max_level = 0;
u32 ul_atv_rf_agc_top = 9500;
u32 ul_atv_rf_agc_cut_off_current = 4000;
u32 ul_atv_rf_agc_speed = 3;
u32 ulQual83 = DEFAULT_MER_83;
u32 ulQual93 = DEFAULT_MER_93;
u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
u32 ul_gpio_cfg = 0x0113;
u32 ul_invert_ts_clock = 0;
u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
u32 ul_dvbt_bitrate = 50000000;
u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
u32 ul_insert_rs_byte = 0;
u32 ul_rf_mirror = 1;
u32 ul_power_down = 0;
dprintk(1, "\n");
state->m_has_lna = false;
state->m_has_dvbt = false;
state->m_has_dvbc = false;
state->m_has_atv = false;
state->m_has_oob = false;
state->m_has_audio = false;
if (!state->m_chunk_size)
state->m_chunk_size = 124;
state->m_osc_clock_freq = 0;
state->m_smart_ant_inverted = false;
state->m_b_p_down_open_bridge = false;
/* real system clock frequency in kHz */
state->m_sys_clock_freq = 151875;
/* Timing div, 250ns/Psys */
/* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
HI_I2C_DELAY) / 1000;
/* Clipping */
if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
/* port/bridge/power down ctrl */
state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
state->m_b_power_down = (ul_power_down != 0);
state->m_drxk_a3_patch_code = false;
/* Init AGC and PGA parameters */
/* VSB IF */
state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
state->m_vsb_pga_cfg = 140;
/* VSB RF */
state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
state->m_vsb_pre_saw_cfg.reference = 0x07;
state->m_vsb_pre_saw_cfg.use_pre_saw = true;
state->m_Quality83percent = DEFAULT_MER_83;
state->m_Quality93percent = DEFAULT_MER_93;
if (ulQual93 <= 500 && ulQual83 < ulQual93) {
state->m_Quality83percent = ulQual83;
state->m_Quality93percent = ulQual93;
}
/* ATV IF */
state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
/* ATV RF */
state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
state->m_atv_pre_saw_cfg.reference = 0x04;
state->m_atv_pre_saw_cfg.use_pre_saw = true;
/* DVBT RF */
state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
state->m_dvbt_rf_agc_cfg.output_level = 0;
state->m_dvbt_rf_agc_cfg.min_output_level = 0;
state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
state->m_dvbt_rf_agc_cfg.top = 0x2100;
state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
state->m_dvbt_rf_agc_cfg.speed = 1;
/* DVBT IF */
state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
state->m_dvbt_if_agc_cfg.output_level = 0;
state->m_dvbt_if_agc_cfg.min_output_level = 0;
state->m_dvbt_if_agc_cfg.max_output_level = 9000;
state->m_dvbt_if_agc_cfg.top = 13424;
state->m_dvbt_if_agc_cfg.cut_off_current = 0;
state->m_dvbt_if_agc_cfg.speed = 3;
state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
/* state->m_dvbtPgaCfg = 140; */
state->m_dvbt_pre_saw_cfg.reference = 4;
state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
/* QAM RF */
state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
state->m_qam_rf_agc_cfg.output_level = 0;
state->m_qam_rf_agc_cfg.min_output_level = 6023;
state->m_qam_rf_agc_cfg.max_output_level = 27000;
state->m_qam_rf_agc_cfg.top = 0x2380;
state->m_qam_rf_agc_cfg.cut_off_current = 4000;
state->m_qam_rf_agc_cfg.speed = 3;
/* QAM IF */
state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
state->m_qam_if_agc_cfg.output_level = 0;
state->m_qam_if_agc_cfg.min_output_level = 0;
state->m_qam_if_agc_cfg.max_output_level = 9000;
state->m_qam_if_agc_cfg.top = 0x0511;
state->m_qam_if_agc_cfg.cut_off_current = 0;
state->m_qam_if_agc_cfg.speed = 3;
state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
state->m_qam_pga_cfg = 140;
state->m_qam_pre_saw_cfg.reference = 4;
state->m_qam_pre_saw_cfg.use_pre_saw = false;
state->m_operation_mode = OM_NONE;
state->m_drxk_state = DRXK_UNINITIALIZED;
/* MPEG output configuration */
state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
state->m_invert_data = false; /* If TRUE; invert DATA signals */
state->m_invert_err = false; /* If TRUE; invert ERR signal */
state->m_invert_str = false; /* If TRUE; invert STR signals */
state->m_invert_val = false; /* If TRUE; invert VAL signals */
state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
/* If TRUE; static MPEG clockrate will be used;
otherwise clockrate will adapt to the bitrate of the TS */
state->m_dvbt_bitrate = ul_dvbt_bitrate;
state->m_dvbc_bitrate = ul_dvbc_bitrate;
state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
/* Maximum bitrate in b/s in case static clockrate is selected */
state->m_mpeg_ts_static_bitrate = 19392658;
state->m_disable_te_ihandling = false;
if (ul_insert_rs_byte)
state->m_insert_rs_byte = true;
state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
if (ul_mpeg_lock_time_out < 10000)
state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
if (ul_demod_lock_time_out < 10000)
state->m_demod_lock_time_out = ul_demod_lock_time_out;
/* QAM defaults */
state->m_constellation = DRX_CONSTELLATION_AUTO;
state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
state->m_fec_rs_prescale = 1;
state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
state->m_agcfast_clip_ctrl_delay = 0;
state->m_gpio_cfg = ul_gpio_cfg;
state->m_b_power_down = false;
state->m_current_power_mode = DRX_POWER_DOWN;
state->m_rfmirror = (ul_rf_mirror == 0);
state->m_if_agc_pol = false;
return 0;
}
static int drxx_open(struct drxk_state *state)
{
int status = 0;
u32 jtag = 0;
u16 bid = 0;
u16 key = 0;
dprintk(1, "\n");
/* stop lock indicator process */
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
/* Check device id */
status = read16(state, SIO_TOP_COMM_KEY__A, &key);
if (status < 0)
goto error;
status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
if (status < 0)
goto error;
status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
if (status < 0)
goto error;
status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
if (status < 0)
goto error;
status = write16(state, SIO_TOP_COMM_KEY__A, key);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int get_device_capabilities(struct drxk_state *state)
{
u16 sio_pdr_ohw_cfg = 0;
u32 sio_top_jtagid_lo = 0;
int status;
const char *spin = "";
dprintk(1, "\n");
/* driver 0.9.0 */
/* stop lock indicator process */
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
if (status < 0)
goto error;
status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
if (status < 0)
goto error;
switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
case 0:
/* ignore (bypass ?) */
break;
case 1:
/* 27 MHz */
state->m_osc_clock_freq = 27000;
break;
case 2:
/* 20.25 MHz */
state->m_osc_clock_freq = 20250;
break;
case 3:
/* 4 MHz */
state->m_osc_clock_freq = 20250;
break;
default:
pr_err("Clock Frequency is unknown\n");
return -EINVAL;
}
/*
Determine device capabilities
Based on pinning v14
*/
status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
if (status < 0)
goto error;
pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
/* driver 0.9.0 */
switch ((sio_top_jtagid_lo >> 29) & 0xF) {
case 0:
state->m_device_spin = DRXK_SPIN_A1;
spin = "A1";
break;
case 2:
state->m_device_spin = DRXK_SPIN_A2;
spin = "A2";
break;
case 3:
state->m_device_spin = DRXK_SPIN_A3;
spin = "A3";
break;
default:
state->m_device_spin = DRXK_SPIN_UNKNOWN;
status = -EINVAL;
pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
goto error2;
}
switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
case 0x13:
/* typeId = DRX3913K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = false;
state->m_has_audio = false;
state->m_has_dvbt = true;
state->m_has_dvbc = true;
state->m_has_sawsw = true;
state->m_has_gpio2 = false;
state->m_has_gpio1 = false;
state->m_has_irqn = false;
break;
case 0x15:
/* typeId = DRX3915K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = false;
state->m_has_dvbt = true;
state->m_has_dvbc = false;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x16:
/* typeId = DRX3916K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = false;
state->m_has_dvbt = true;
state->m_has_dvbc = false;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x18:
/* typeId = DRX3918K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = true;
state->m_has_dvbt = true;
state->m_has_dvbc = false;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x21:
/* typeId = DRX3921K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = true;
state->m_has_dvbt = true;
state->m_has_dvbc = true;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x23:
/* typeId = DRX3923K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = true;
state->m_has_dvbt = true;
state->m_has_dvbc = true;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x25:
/* typeId = DRX3925K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = true;
state->m_has_dvbt = true;
state->m_has_dvbc = true;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
case 0x26:
/* typeId = DRX3926K_TYPE_ID */
state->m_has_lna = false;
state->m_has_oob = false;
state->m_has_atv = true;
state->m_has_audio = false;
state->m_has_dvbt = true;
state->m_has_dvbc = true;
state->m_has_sawsw = true;
state->m_has_gpio2 = true;
state->m_has_gpio1 = true;
state->m_has_irqn = false;
break;
default:
pr_err("DeviceID 0x%02x not supported\n",
((sio_top_jtagid_lo >> 12) & 0xFF));
status = -EINVAL;
goto error2;
}
pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
((sio_top_jtagid_lo >> 12) & 0xFF), spin,
state->m_osc_clock_freq / 1000,
state->m_osc_clock_freq % 1000);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
error2:
return status;
}
static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
{
int status;
bool powerdown_cmd;
dprintk(1, "\n");
/* Write command */
status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
if (status < 0)
goto error;
if (cmd == SIO_HI_RA_RAM_CMD_RESET)
usleep_range(1000, 2000);
powerdown_cmd =
(bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
((state->m_hi_cfg_ctrl) &
SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
if (!powerdown_cmd) {
/* Wait until command rdy */
u32 retry_count = 0;
u16 wait_cmd;
do {
usleep_range(1000, 2000);
retry_count += 1;
status = read16(state, SIO_HI_RA_RAM_CMD__A,
&wait_cmd);
} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
if (status < 0)
goto error;
status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int hi_cfg_command(struct drxk_state *state)
{
int status;
dprintk(1, "\n");
mutex_lock(&state->mutex);
status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
state->m_hi_cfg_timeout);
if (status < 0)
goto error;
status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
state->m_hi_cfg_ctrl);
if (status < 0)
goto error;
status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
state->m_hi_cfg_wake_up_key);
if (status < 0)
goto error;
status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
state->m_hi_cfg_bridge_delay);
if (status < 0)
goto error;
status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
state->m_hi_cfg_timing_div);
if (status < 0)
goto error;
status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
if (status < 0)
goto error;
status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
if (status < 0)
goto error;
state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
error:
mutex_unlock(&state->mutex);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int init_hi(struct drxk_state *state)
{
dprintk(1, "\n");
state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
state->m_hi_cfg_timeout = 0x96FF;
/* port/bridge/power down ctrl */
state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
return hi_cfg_command(state);
}
static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
{
int status;
u16 sio_pdr_mclk_cfg = 0;
u16 sio_pdr_mdx_cfg = 0;
u16 err_cfg = 0;
dprintk(1, ": mpeg %s, %s mode\n",
mpeg_enable ? "enable" : "disable",
state->m_enable_parallel ? "parallel" : "serial");
/* stop lock indicator process */
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
/* MPEG TS pad configuration */
status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
if (status < 0)
goto error;
if (!mpeg_enable) {
/* Set MPEG TS pads to inputmode */
status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
if (status < 0)
goto error;
} else {
/* Enable MPEG output */
sio_pdr_mdx_cfg =
((state->m_ts_data_strength <<
SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
SIO_PDR_MCLK_CFG_DRIVE__B) |
0x0003);
status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
if (status < 0)
goto error;
if (state->enable_merr_cfg)
err_cfg = sio_pdr_mdx_cfg;
status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
if (status < 0)
goto error;
if (state->m_enable_parallel) {
/* parallel -> enable MD1 to MD7 */
status = write16(state, SIO_PDR_MD1_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD2_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD3_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD4_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD5_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD6_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD7_CFG__A,
sio_pdr_mdx_cfg);
if (status < 0)
goto error;
} else {
sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
SIO_PDR_MD0_CFG_DRIVE__B)
| 0x0003);
/* serial -> disable MD1 to MD7 */
status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
if (status < 0)
goto error;
}
status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
if (status < 0)
goto error;
status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
if (status < 0)
goto error;
}
/* Enable MB output over MPEG pads and ctl input */
status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
if (status < 0)
goto error;
/* Write nomagic word to enable pdr reg write */
status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int mpegts_disable(struct drxk_state *state)
{
dprintk(1, "\n");
return mpegts_configure_pins(state, false);
}
static int bl_chain_cmd(struct drxk_state *state,
u16 rom_offset, u16 nr_of_elements, u32 time_out)
{
u16 bl_status = 0;
int status;
unsigned long end;
dprintk(1, "\n");
mutex_lock(&state->mutex);
status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
if (status < 0)
goto error;
status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
if (status < 0)
goto error;
status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
if (status < 0)
goto error;
status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
if (status < 0)
goto error;
end = jiffies + msecs_to_jiffies(time_out);
do {
usleep_range(1000, 2000);
status = read16(state, SIO_BL_STATUS__A, &bl_status);
if (status < 0)
goto error;
} while ((bl_status == 0x1) &&
((time_is_after_jiffies(end))));
if (bl_status == 0x1) {
pr_err("SIO not ready\n");
status = -EINVAL;
goto error2;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
error2:
mutex_unlock(&state->mutex);
return status;
}
static int download_microcode(struct drxk_state *state,
const u8 p_mc_image[], u32 length)
{
const u8 *p_src = p_mc_image;
u32 address;
u16 n_blocks;
u16 block_size;
u32 offset = 0;
u32 i;
int status = 0;
dprintk(1, "\n");
/* down the drain (we don't care about MAGIC_WORD) */
#if 0
/* For future reference */
drain = (p_src[0] << 8) | p_src[1];
#endif
p_src += sizeof(u16);
offset += sizeof(u16);
n_blocks = (p_src[0] << 8) | p_src[1];
p_src += sizeof(u16);
offset += sizeof(u16);
for (i = 0; i < n_blocks; i += 1) {
address = (p_src[0] << 24) | (p_src[1] << 16) |
(p_src[2] << 8) | p_src[3];
p_src += sizeof(u32);
offset += sizeof(u32);
block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
p_src += sizeof(u16);
offset += sizeof(u16);
#if 0
/* For future reference */
flags = (p_src[0] << 8) | p_src[1];
#endif
p_src += sizeof(u16);
offset += sizeof(u16);
#if 0
/* For future reference */
block_crc = (p_src[0] << 8) | p_src[1];
#endif
p_src += sizeof(u16);
offset += sizeof(u16);
if (offset + block_size > length) {
pr_err("Firmware is corrupted.\n");
return -EINVAL;
}
status = write_block(state, address, block_size, p_src);
if (status < 0) {
pr_err("Error %d while loading firmware\n", status);
break;
}
p_src += block_size;
offset += block_size;
}
return status;
}
static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
{
int status;
u16 data = 0;
u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
unsigned long end;
dprintk(1, "\n");
if (!enable) {
desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
}
status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
if (status >= 0 && data == desired_status) {
/* tokenring already has correct status */
return status;
}
/* Disable/enable dvbt tokenring bridge */
status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
do {
status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
if ((status >= 0 && data == desired_status)
|| time_is_after_jiffies(end))
break;
usleep_range(1000, 2000);
} while (1);
if (data != desired_status) {
pr_err("SIO not ready\n");
return -EINVAL;
}
return status;
}
static int mpegts_stop(struct drxk_state *state)
{
int status = 0;
u16 fec_oc_snc_mode = 0;
u16 fec_oc_ipr_mode = 0;
dprintk(1, "\n");
/* Graceful shutdown (byte boundaries) */
status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
if (status < 0)
goto error;
fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
if (status < 0)
goto error;
/* Suppress MCLK during absence of data */
status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
if (status < 0)
goto error;
fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int scu_command(struct drxk_state *state,
u16 cmd, u8 parameter_len,
u16 *parameter, u8 result_len, u16 *result)
{
#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
#error DRXK register mapping no longer compatible with this routine!
#endif
u16 cur_cmd = 0;
int status = -EINVAL;
unsigned long end;
u8 buffer[34];
int cnt = 0, ii;
const char *p;
char errname[30];
dprintk(1, "\n");
if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
((result_len > 0) && (result == NULL))) {
pr_err("Error %d on %s\n", status, __func__);
return status;
}
mutex_lock(&state->mutex);
/* assume that the command register is ready
since it is checked afterwards */
if (parameter) {
for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
buffer[cnt++] = (parameter[ii] & 0xFF);
buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
}
}
buffer[cnt++] = (cmd & 0xFF);
buffer[cnt++] = ((cmd >> 8) & 0xFF);
write_block(state, SCU_RAM_PARAM_0__A -
(parameter_len - 1), cnt, buffer);
/* Wait until SCU has processed command */
end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
do {
usleep_range(1000, 2000);
status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
if (status < 0)
goto error;
} while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
if (cur_cmd != DRX_SCU_READY) {
pr_err("SCU not ready\n");
status = -EIO;
goto error2;
}
/* read results */
if ((result_len > 0) && (result != NULL)) {
s16 err;
int ii;
for (ii = result_len - 1; ii >= 0; ii -= 1) {
status = read16(state, SCU_RAM_PARAM_0__A - ii,
&result[ii]);
if (status < 0)
goto error;
}
/* Check if an error was reported by SCU */
err = (s16)result[0];
if (err >= 0)
goto error;
/* check for the known error codes */
switch (err) {
case SCU_RESULT_UNKCMD:
p = "SCU_RESULT_UNKCMD";
break;
case SCU_RESULT_UNKSTD:
p = "SCU_RESULT_UNKSTD";
break;
case SCU_RESULT_SIZE:
p = "SCU_RESULT_SIZE";
break;
case SCU_RESULT_INVPAR:
p = "SCU_RESULT_INVPAR";
break;
default: /* Other negative values are errors */
sprintf(errname, "ERROR: %d\n", err);
p = errname;
}
pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
status = -EINVAL;
goto error2;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
error2:
mutex_unlock(&state->mutex);
return status;
}
static int set_iqm_af(struct drxk_state *state, bool active)
{
u16 data = 0;
int status;
dprintk(1, "\n");
/* Configure IQM */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
if (!active) {
data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
| IQM_AF_STDBY_STDBY_AMP_STANDBY
| IQM_AF_STDBY_STDBY_PD_STANDBY
| IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
| IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
} else {
data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
& (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
& (~IQM_AF_STDBY_STDBY_PD_STANDBY)
& (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
& (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
);
}
status = write16(state, IQM_AF_STDBY__A, data);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
{
int status = 0;
u16 sio_cc_pwd_mode = 0;
dprintk(1, "\n");
/* Check arguments */
if (mode == NULL)
return -EINVAL;
switch (*mode) {
case DRX_POWER_UP:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
break;
case DRXK_POWER_DOWN_OFDM:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
break;
case DRXK_POWER_DOWN_CORE:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
break;
case DRXK_POWER_DOWN_PLL:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
break;
case DRX_POWER_DOWN:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
break;
default:
/* Unknown sleep mode */
return -EINVAL;
}
/* If already in requested power mode, do nothing */
if (state->m_current_power_mode == *mode)
return 0;
/* For next steps make sure to start from DRX_POWER_UP mode */
if (state->m_current_power_mode != DRX_POWER_UP) {
status = power_up_device(state);
if (status < 0)
goto error;
status = dvbt_enable_ofdm_token_ring(state, true);
if (status < 0)
goto error;
}
if (*mode == DRX_POWER_UP) {
/* Restore analog & pin configuration */
} else {
/* Power down to requested mode */
/* Backup some register settings */
/* Set pins with possible pull-ups connected
to them in input mode */
/* Analog power down */
/* ADC power down */
/* Power down device */
/* stop all comm_exec */
/* Stop and power down previous standard */
switch (state->m_operation_mode) {
case OM_DVBT:
status = mpegts_stop(state);
if (status < 0)
goto error;
status = power_down_dvbt(state, false);
if (status < 0)
goto error;
break;
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
status = mpegts_stop(state);
if (status < 0)
goto error;
status = power_down_qam(state);
if (status < 0)
goto error;
break;
default:
break;
}
status = dvbt_enable_ofdm_token_ring(state, false);
if (status < 0)
goto error;
status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
if (*mode != DRXK_POWER_DOWN_OFDM) {
state->m_hi_cfg_ctrl |=
SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
status = hi_cfg_command(state);
if (status < 0)
goto error;
}
}
state->m_current_power_mode = *mode;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
{
enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
u16 cmd_result = 0;
u16 data = 0;
int status;
dprintk(1, "\n");
status = read16(state, SCU_COMM_EXEC__A, &data);
if (status < 0)
goto error;
if (data == SCU_COMM_EXEC_ACTIVE) {
/* Send OFDM stop command */
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* Send OFDM reset command */
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
}
/* Reset datapath for OFDM, processors first */
status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
if (status < 0)
goto error;
/* powerdown AFE */
status = set_iqm_af(state, false);
if (status < 0)
goto error;
/* powerdown to OFDM mode */
if (set_power_mode) {
status = ctrl_power_mode(state, &power_mode);
if (status < 0)
goto error;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int setoperation_mode(struct drxk_state *state,
enum operation_mode o_mode)
{
int status = 0;
dprintk(1, "\n");
/*
Stop and power down previous standard
TODO investigate total power down instead of partial
power down depending on "previous" standard.
*/
/* disable HW lock indicator */
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
/* Device is already at the required mode */
if (state->m_operation_mode == o_mode)
return 0;
switch (state->m_operation_mode) {
/* OM_NONE was added for start up */
case OM_NONE:
break;
case OM_DVBT:
status = mpegts_stop(state);
if (status < 0)
goto error;
status = power_down_dvbt(state, true);
if (status < 0)
goto error;
state->m_operation_mode = OM_NONE;
break;
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
status = mpegts_stop(state);
if (status < 0)
goto error;
status = power_down_qam(state);
if (status < 0)
goto error;
state->m_operation_mode = OM_NONE;
break;
case OM_QAM_ITU_B:
default:
status = -EINVAL;
goto error;
}
/*
Power up new standard
*/
switch (o_mode) {
case OM_DVBT:
dprintk(1, ": DVB-T\n");
state->m_operation_mode = o_mode;
status = set_dvbt_standard(state, o_mode);
if (status < 0)
goto error;
break;
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
dprintk(1, ": DVB-C Annex %c\n",
(state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
state->m_operation_mode = o_mode;
status = set_qam_standard(state, o_mode);
if (status < 0)
goto error;
break;
case OM_QAM_ITU_B:
default:
status = -EINVAL;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int start(struct drxk_state *state, s32 offset_freq,
s32 intermediate_frequency)
{
int status = -EINVAL;
u16 i_freqk_hz;
s32 offsetk_hz = offset_freq / 1000;
dprintk(1, "\n");
if (state->m_drxk_state != DRXK_STOPPED &&
state->m_drxk_state != DRXK_DTV_STARTED)
goto error;
state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
if (intermediate_frequency < 0) {
state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
intermediate_frequency = -intermediate_frequency;
}
switch (state->m_operation_mode) {
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
i_freqk_hz = (intermediate_frequency / 1000);
status = set_qam(state, i_freqk_hz, offsetk_hz);
if (status < 0)
goto error;
state->m_drxk_state = DRXK_DTV_STARTED;
break;
case OM_DVBT:
i_freqk_hz = (intermediate_frequency / 1000);
status = mpegts_stop(state);
if (status < 0)
goto error;
status = set_dvbt(state, i_freqk_hz, offsetk_hz);
if (status < 0)
goto error;
status = dvbt_start(state);
if (status < 0)
goto error;
state->m_drxk_state = DRXK_DTV_STARTED;
break;
default:
break;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int shut_down(struct drxk_state *state)
{
dprintk(1, "\n");
mpegts_stop(state);
return 0;
}
static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
{
int status = -EINVAL;
dprintk(1, "\n");
if (p_lock_status == NULL)
goto error;
*p_lock_status = NOT_LOCKED;
/* define the SCU command code */
switch (state->m_operation_mode) {
case OM_QAM_ITU_A:
case OM_QAM_ITU_B:
case OM_QAM_ITU_C:
status = get_qam_lock_status(state, p_lock_status);
break;
case OM_DVBT:
status = get_dvbt_lock_status(state, p_lock_status);
break;
default:
pr_debug("Unsupported operation mode %d in %s\n",
state->m_operation_mode, __func__);
return 0;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int mpegts_start(struct drxk_state *state)
{
int status;
u16 fec_oc_snc_mode = 0;
/* Allow OC to sync again */
status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
if (status < 0)
goto error;
fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
if (status < 0)
goto error;
status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int mpegts_dto_init(struct drxk_state *state)
{
int status;
dprintk(1, "\n");
/* Rate integration settings */
status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
if (status < 0)
goto error;
status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
if (status < 0)
goto error;
status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
if (status < 0)
goto error;
status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
if (status < 0)
goto error;
status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
if (status < 0)
goto error;
/* Additional configuration */
status = write16(state, FEC_OC_OCR_INVERT__A, 0);
if (status < 0)
goto error;
status = write16(state, FEC_OC_SNC_LWM__A, 2);
if (status < 0)
goto error;
status = write16(state, FEC_OC_SNC_HWM__A, 12);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int mpegts_dto_setup(struct drxk_state *state,
enum operation_mode o_mode)
{
int status;
u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */
u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */
u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */
u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */
u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */
u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */
u16 fec_oc_tmd_mode = 0;
u16 fec_oc_tmd_int_upd_rate = 0;
u32 max_bit_rate = 0;
bool static_clk = false;
dprintk(1, "\n");
/* Check insertion of the Reed-Solomon parity bytes */
status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
if (status < 0)
goto error;
status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
if (status < 0)
goto error;
fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
if (state->m_insert_rs_byte) {
/* enable parity symbol forward */
fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
/* MVAL disable during parity bytes */
fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
/* TS burst length to 204 */
fec_oc_dto_burst_len = 204;
}
/* Check serial or parallel output */
fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
if (!state->m_enable_parallel) {
/* MPEG data output is serial -> set ipr_mode[0] */
fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
}
switch (o_mode) {
case OM_DVBT:
max_bit_rate = state->m_dvbt_bitrate;
fec_oc_tmd_mode = 3;
fec_oc_rcn_ctl_rate = 0xC00000;
static_clk = state->m_dvbt_static_clk;
break;
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
fec_oc_tmd_mode = 0x0004;
fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
max_bit_rate = state->m_dvbc_bitrate;
static_clk = state->m_dvbc_static_clk;
break;
default:
status = -EINVAL;
} /* switch (standard) */
if (status < 0)
goto error;
/* Configure DTO's */
if (static_clk) {
u32 bit_rate = 0;
/* Rational DTO for MCLK source (static MCLK rate),
Dynamic DTO for optimal grouping
(avoid intra-packet gaps),
DTO offset enable to sync TS burst with MSTRT */
fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
FEC_OC_FCT_MODE_VIRT_ENA__M);
/* Check user defined bitrate */
bit_rate = max_bit_rate;
if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */
bit_rate = 75900000UL;
}
/* Rational DTO period:
dto_period = (Fsys / bitrate) - 2
result should be floored,
to make sure >= requested bitrate
*/
fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
* 1000) / bit_rate);
if (fec_oc_dto_period <= 2)
fec_oc_dto_period = 0;
else
fec_oc_dto_period -= 2;
fec_oc_tmd_int_upd_rate = 8;
} else {
/* (commonAttr->static_clk == false) => dynamic mode */
fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
fec_oc_tmd_int_upd_rate = 5;
}
/* Write appropriate registers with requested configuration */
status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
if (status < 0)
goto error;
status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
if (status < 0)
goto error;
status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
if (status < 0)
goto error;
status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
if (status < 0)
goto error;
status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
if (status < 0)
goto error;
status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
if (status < 0)
goto error;
/* Rate integration settings */
status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
fec_oc_tmd_int_upd_rate);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int mpegts_configure_polarity(struct drxk_state *state)
{
u16 fec_oc_reg_ipr_invert = 0;
/* Data mask for the output data byte */
u16 invert_data_mask =
FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
dprintk(1, "\n");
/* Control selective inversion of output bits */
fec_oc_reg_ipr_invert &= (~(invert_data_mask));
if (state->m_invert_data)
fec_oc_reg_ipr_invert |= invert_data_mask;
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
if (state->m_invert_err)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
if (state->m_invert_str)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
if (state->m_invert_val)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
if (state->m_invert_clk)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
}
#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
static int set_agc_rf(struct drxk_state *state,
struct s_cfg_agc *p_agc_cfg, bool is_dtv)
{
int status = -EINVAL;
u16 data = 0;
struct s_cfg_agc *p_if_agc_settings;
dprintk(1, "\n");
if (p_agc_cfg == NULL)
goto error;
switch (p_agc_cfg->ctrl_mode) {
case DRXK_AGC_CTRL_AUTO:
/* Enable RF AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
/* Enable SCU RF AGC loop */
data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
/* Polarity */
if (state->m_rf_agc_pol)
data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
else
data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
/* Set speed (using complementary reduction value) */
status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
if (status < 0)
goto error;
data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
data |= (~(p_agc_cfg->speed <<
SCU_RAM_AGC_KI_RED_RAGC_RED__B)
& SCU_RAM_AGC_KI_RED_RAGC_RED__M);
status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
if (status < 0)
goto error;
if (is_dvbt(state))
p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
else if (is_qam(state))
p_if_agc_settings = &state->m_qam_if_agc_cfg;
else
p_if_agc_settings = &state->m_atv_if_agc_cfg;
if (p_if_agc_settings == NULL) {
status = -EINVAL;
goto error;
}
/* Set TOP, only if IF-AGC is in AUTO mode */
if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
status = write16(state,
SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
p_agc_cfg->top);
if (status < 0)
goto error;
}
/* Cut-Off current */
status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
p_agc_cfg->cut_off_current);
if (status < 0)
goto error;
/* Max. output level */
status = write16(state, SCU_RAM_AGC_RF_MAX__A,
p_agc_cfg->max_output_level);
if (status < 0)
goto error;
break;
case DRXK_AGC_CTRL_USER:
/* Enable RF AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
/* Disable SCU RF AGC loop */
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
if (state->m_rf_agc_pol)
data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
else
data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
/* SCU c.o.c. to 0, enabling full control range */
status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
if (status < 0)
goto error;
/* Write value to output pin */
status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
p_agc_cfg->output_level);
if (status < 0)
goto error;
break;
case DRXK_AGC_CTRL_OFF:
/* Disable RF AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
/* Disable SCU RF AGC loop */
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
break;
default:
status = -EINVAL;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
static int set_agc_if(struct drxk_state *state,
struct s_cfg_agc *p_agc_cfg, bool is_dtv)
{
u16 data = 0;
int status = 0;
struct s_cfg_agc *p_rf_agc_settings;
dprintk(1, "\n");
switch (p_agc_cfg->ctrl_mode) {
case DRXK_AGC_CTRL_AUTO:
/* Enable IF AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
/* Enable SCU IF AGC loop */
data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
/* Polarity */
if (state->m_if_agc_pol)
data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
else
data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
/* Set speed (using complementary reduction value) */
status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
if (status < 0)
goto error;
data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
data |= (~(p_agc_cfg->speed <<
SCU_RAM_AGC_KI_RED_IAGC_RED__B)
& SCU_RAM_AGC_KI_RED_IAGC_RED__M);
status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
if (status < 0)
goto error;
if (is_qam(state))
p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
else
p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
if (p_rf_agc_settings == NULL)
return -1;
/* Restore TOP */
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
p_rf_agc_settings->top);
if (status < 0)
goto error;
break;
case DRXK_AGC_CTRL_USER:
/* Enable IF AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
/* Disable SCU IF AGC loop */
data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
/* Polarity */
if (state->m_if_agc_pol)
data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
else
data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
/* Write value to output pin */
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
p_agc_cfg->output_level);
if (status < 0)
goto error;
break;
case DRXK_AGC_CTRL_OFF:
/* Disable If AGC DAC */
status = read16(state, IQM_AF_STDBY__A, &data);
if (status < 0)
goto error;
data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
status = write16(state, IQM_AF_STDBY__A, data);
if (status < 0)
goto error;
/* Disable SCU IF AGC loop */
status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
if (status < 0)
goto error;
data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
if (status < 0)
goto error;
break;
} /* switch (agcSettingsIf->ctrl_mode) */
/* always set the top to support
configurations without if-loop */
status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int get_qam_signal_to_noise(struct drxk_state *state,
s32 *p_signal_to_noise)
{
int status = 0;
u16 qam_sl_err_power = 0; /* accum. error between
raw and sliced symbols */
u32 qam_sl_sig_power = 0; /* used for MER, depends of
QAM modulation */
u32 qam_sl_mer = 0; /* QAM MER */
dprintk(1, "\n");
/* MER calculation */
/* get the register value needed for MER */
status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
if (status < 0) {
pr_err("Error %d on %s\n", status, __func__);
return -EINVAL;
}
switch (state->props.modulation) {
case QAM_16:
qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
break;
case QAM_32:
qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
break;
case QAM_64:
qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
break;
case QAM_128:
qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
break;
default:
case QAM_256:
qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
break;
}
if (qam_sl_err_power > 0) {
qam_sl_mer = log10times100(qam_sl_sig_power) -
log10times100((u32) qam_sl_err_power);
}
*p_signal_to_noise = qam_sl_mer;
return status;
}
static int get_dvbt_signal_to_noise(struct drxk_state *state,
s32 *p_signal_to_noise)
{
int status;
u16 reg_data = 0;
u32 eq_reg_td_sqr_err_i = 0;
u32 eq_reg_td_sqr_err_q = 0;
u16 eq_reg_td_sqr_err_exp = 0;
u16 eq_reg_td_tps_pwr_ofs = 0;
u16 eq_reg_td_req_smb_cnt = 0;
u32 tps_cnt = 0;
u32 sqr_err_iq = 0;
u32 a = 0;
u32 b = 0;
u32 c = 0;
u32 i_mer = 0;
u16 transmission_params = 0;
dprintk(1, "\n");
status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
&eq_reg_td_tps_pwr_ofs);
if (status < 0)
goto error;
status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
&eq_reg_td_req_smb_cnt);
if (status < 0)
goto error;
status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
&eq_reg_td_sqr_err_exp);
if (status < 0)
goto error;
status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
®_data);
if (status < 0)
goto error;
/* Extend SQR_ERR_I operational range */
eq_reg_td_sqr_err_i = (u32) reg_data;
if ((eq_reg_td_sqr_err_exp > 11) &&
(eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
eq_reg_td_sqr_err_i += 0x00010000UL;
}
status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
if (status < 0)
goto error;
/* Extend SQR_ERR_Q operational range */
eq_reg_td_sqr_err_q = (u32) reg_data;
if ((eq_reg_td_sqr_err_exp > 11) &&
(eq_reg_td_sqr_err_q < 0x00000FFFUL))
eq_reg_td_sqr_err_q += 0x00010000UL;
status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
&transmission_params);
if (status < 0)
goto error;
/* Check input data for MER */
/* MER calculation (in 0.1 dB) without math.h */
if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
i_mer = 0;
else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
/* No error at all, this must be the HW reset value
* Apparently no first measurement yet
* Set MER to 0.0 */
i_mer = 0;
} else {
sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
eq_reg_td_sqr_err_exp;
if ((transmission_params &
OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
== OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
tps_cnt = 17;
else
tps_cnt = 68;
/* IMER = 100 * log10 (x)
where x = (eq_reg_td_tps_pwr_ofs^2 *
eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
=> IMER = a + b -c
where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
c = 100 * log10 (sqr_err_iq)
*/
/* log(x) x = 9bits * 9bits->18 bits */
a = log10times100(eq_reg_td_tps_pwr_ofs *
eq_reg_td_tps_pwr_ofs);
/* log(x) x = 16bits * 7bits->23 bits */
b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
/* log(x) x = (16bits + 16bits) << 15 ->32 bits */
c = log10times100(sqr_err_iq);
i_mer = a + b - c;
}
*p_signal_to_noise = i_mer;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
{
dprintk(1, "\n");
*p_signal_to_noise = 0;
switch (state->m_operation_mode) {
case OM_DVBT:
return get_dvbt_signal_to_noise(state, p_signal_to_noise);
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
return get_qam_signal_to_noise(state, p_signal_to_noise);
default:
break;
}
return 0;
}
#if 0
static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
{
/* SNR Values for quasi errorfree reception rom Nordig 2.2 */
int status = 0;
dprintk(1, "\n");
static s32 QE_SN[] = {
51, /* QPSK 1/2 */
69, /* QPSK 2/3 */
79, /* QPSK 3/4 */
89, /* QPSK 5/6 */
97, /* QPSK 7/8 */
108, /* 16-QAM 1/2 */
131, /* 16-QAM 2/3 */
146, /* 16-QAM 3/4 */
156, /* 16-QAM 5/6 */
160, /* 16-QAM 7/8 */
165, /* 64-QAM 1/2 */
187, /* 64-QAM 2/3 */
202, /* 64-QAM 3/4 */
216, /* 64-QAM 5/6 */
225, /* 64-QAM 7/8 */
};
*p_quality = 0;
do {
s32 signal_to_noise = 0;
u16 constellation = 0;
u16 code_rate = 0;
u32 signal_to_noise_rel;
u32 ber_quality;
status = get_dvbt_signal_to_noise(state, &signal_to_noise);
if (status < 0)
break;
status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
&constellation);
if (status < 0)
break;
constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
&code_rate);
if (status < 0)
break;
code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
break;
signal_to_noise_rel = signal_to_noise -
QE_SN[constellation * 5 + code_rate];
ber_quality = 100;
if (signal_to_noise_rel < -70)
*p_quality = 0;
else if (signal_to_noise_rel < 30)
*p_quality = ((signal_to_noise_rel + 70) *
ber_quality) / 100;
else
*p_quality = ber_quality;
} while (0);
return 0;
};
static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
{
int status = 0;
*p_quality = 0;
dprintk(1, "\n");
do {
u32 signal_to_noise = 0;
u32 ber_quality = 100;
u32 signal_to_noise_rel = 0;
status = get_qam_signal_to_noise(state, &signal_to_noise);
if (status < 0)
break;
switch (state->props.modulation) {
case QAM_16:
signal_to_noise_rel = signal_to_noise - 200;
break;
case QAM_32:
signal_to_noise_rel = signal_to_noise - 230;
break; /* Not in NorDig */
case QAM_64:
signal_to_noise_rel = signal_to_noise - 260;
break;
case QAM_128:
signal_to_noise_rel = signal_to_noise - 290;
break;
default:
case QAM_256:
signal_to_noise_rel = signal_to_noise - 320;
break;
}
if (signal_to_noise_rel < -70)
*p_quality = 0;
else if (signal_to_noise_rel < 30)
*p_quality = ((signal_to_noise_rel + 70) *
ber_quality) / 100;
else
*p_quality = ber_quality;
} while (0);
return status;
}
static int get_quality(struct drxk_state *state, s32 *p_quality)
{
dprintk(1, "\n");
switch (state->m_operation_mode) {
case OM_DVBT:
return get_dvbt_quality(state, p_quality);
case OM_QAM_ITU_A:
return get_dvbc_quality(state, p_quality);
default:
break;
}
return 0;
}
#endif
/* Free data ram in SIO HI */
#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
#define SIO_HI_RA_RAM_USR_END__A 0x420060
#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
{
int status = -EINVAL;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return 0;
if (state->m_drxk_state == DRXK_POWERED_DOWN)
goto error;
if (state->no_i2c_bridge)
return 0;
status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
if (status < 0)
goto error;
if (b_enable_bridge) {
status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
if (status < 0)
goto error;
} else {
status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
if (status < 0)
goto error;
}
status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int set_pre_saw(struct drxk_state *state,
struct s_cfg_pre_saw *p_pre_saw_cfg)
{
int status = -EINVAL;
dprintk(1, "\n");
if ((p_pre_saw_cfg == NULL)
|| (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
goto error;
status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
u16 rom_offset, u16 nr_of_elements, u32 time_out)
{
u16 bl_status = 0;
u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
int status;
unsigned long end;
dprintk(1, "\n");
mutex_lock(&state->mutex);
status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
if (status < 0)
goto error;
status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
if (status < 0)
goto error;
status = write16(state, SIO_BL_TGT_ADDR__A, offset);
if (status < 0)
goto error;
status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
if (status < 0)
goto error;
status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
if (status < 0)
goto error;
status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
if (status < 0)
goto error;
end = jiffies + msecs_to_jiffies(time_out);
do {
status = read16(state, SIO_BL_STATUS__A, &bl_status);
if (status < 0)
goto error;
} while ((bl_status == 0x1) && time_is_after_jiffies(end));
if (bl_status == 0x1) {
pr_err("SIO not ready\n");
status = -EINVAL;
goto error2;
}
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
error2:
mutex_unlock(&state->mutex);
return status;
}
static int adc_sync_measurement(struct drxk_state *state, u16 *count)
{
u16 data = 0;
int status;
dprintk(1, "\n");
/* start measurement */
status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = write16(state, IQM_AF_START_LOCK__A, 1);
if (status < 0)
goto error;
*count = 0;
status = read16(state, IQM_AF_PHASE0__A, &data);
if (status < 0)
goto error;
if (data == 127)
*count = *count + 1;
status = read16(state, IQM_AF_PHASE1__A, &data);
if (status < 0)
goto error;
if (data == 127)
*count = *count + 1;
status = read16(state, IQM_AF_PHASE2__A, &data);
if (status < 0)
goto error;
if (data == 127)
*count = *count + 1;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int adc_synchronization(struct drxk_state *state)
{
u16 count = 0;
int status;
dprintk(1, "\n");
status = adc_sync_measurement(state, &count);
if (status < 0)
goto error;
if (count == 1) {
/* Try sampling on a different edge */
u16 clk_neg = 0;
status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
if (status < 0)
goto error;
if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
clk_neg |=
IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
} else {
clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
clk_neg |=
IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
}
status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
if (status < 0)
goto error;
status = adc_sync_measurement(state, &count);
if (status < 0)
goto error;
}
if (count < 2)
status = -EINVAL;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int set_frequency_shifter(struct drxk_state *state,
u16 intermediate_freqk_hz,
s32 tuner_freq_offset, bool is_dtv)
{
bool select_pos_image = false;
u32 rf_freq_residual = tuner_freq_offset;
u32 fm_frequency_shift = 0;
bool tuner_mirror = !state->m_b_mirror_freq_spect;
u32 adc_freq;
bool adc_flip;
int status;
u32 if_freq_actual;
u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
u32 frequency_shift;
bool image_to_select;
dprintk(1, "\n");
/*
Program frequency shifter
No need to account for mirroring on RF
*/
if (is_dtv) {
if ((state->m_operation_mode == OM_QAM_ITU_A) ||
(state->m_operation_mode == OM_QAM_ITU_C) ||
(state->m_operation_mode == OM_DVBT))
select_pos_image = true;
else
select_pos_image = false;
}
if (tuner_mirror)
/* tuner doesn't mirror */
if_freq_actual = intermediate_freqk_hz +
rf_freq_residual + fm_frequency_shift;
else
/* tuner mirrors */
if_freq_actual = intermediate_freqk_hz -
rf_freq_residual - fm_frequency_shift;
if (if_freq_actual > sampling_frequency / 2) {
/* adc mirrors */
adc_freq = sampling_frequency - if_freq_actual;
adc_flip = true;
} else {
/* adc doesn't mirror */
adc_freq = if_freq_actual;
adc_flip = false;
}
frequency_shift = adc_freq;
image_to_select = state->m_rfmirror ^ tuner_mirror ^
adc_flip ^ select_pos_image;
state->m_iqm_fs_rate_ofs =
Frac28a((frequency_shift), sampling_frequency);
if (image_to_select)
state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
/* Program frequency shifter with tuner offset compensation */
/* frequency_shift += tuner_freq_offset; TODO */
status = write32(state, IQM_FS_RATE_OFS_LO__A,
state->m_iqm_fs_rate_ofs);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int init_agc(struct drxk_state *state, bool is_dtv)
{
u16 ingain_tgt = 0;
u16 ingain_tgt_min = 0;
u16 ingain_tgt_max = 0;
u16 clp_cyclen = 0;
u16 clp_sum_min = 0;
u16 clp_dir_to = 0;
u16 sns_sum_min = 0;
u16 sns_sum_max = 0;
u16 clp_sum_max = 0;
u16 sns_dir_to = 0;
u16 ki_innergain_min = 0;
u16 if_iaccu_hi_tgt = 0;
u16 if_iaccu_hi_tgt_min = 0;
u16 if_iaccu_hi_tgt_max = 0;
u16 data = 0;
u16 fast_clp_ctrl_delay = 0;
u16 clp_ctrl_mode = 0;
int status = 0;
dprintk(1, "\n");
/* Common settings */
sns_sum_max = 1023;
if_iaccu_hi_tgt_min = 2047;
clp_cyclen = 500;
clp_sum_max = 1023;
/* AGCInit() not available for DVBT; init done in microcode */
if (!is_qam(state)) {
pr_err("%s: mode %d is not DVB-C\n",
__func__, state->m_operation_mode);
return -EINVAL;
}
/* FIXME: Analog TV AGC require different settings */
/* Standard specific settings */
clp_sum_min = 8;
clp_dir_to = (u16) -9;
clp_ctrl_mode = 0;
sns_sum_min = 8;
sns_dir_to = (u16) -9;
ki_innergain_min = (u16) -1030;
if_iaccu_hi_tgt_max = 0x2380;
if_iaccu_hi_tgt = 0x2380;
ingain_tgt_min = 0x0511;
ingain_tgt = 0x0511;
ingain_tgt_max = 5119;
fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
fast_clp_ctrl_delay);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
if_iaccu_hi_tgt_min);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
if_iaccu_hi_tgt_max);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
ki_innergain_min);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
if_iaccu_hi_tgt);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
if (status < 0)
goto error;
/* Initialize inner-loop KI gain factors */
status = read16(state, SCU_RAM_AGC_KI__A, &data);
if (status < 0)
goto error;
data = 0x0657;
data &= ~SCU_RAM_AGC_KI_RF__M;
data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
data &= ~SCU_RAM_AGC_KI_IF__M;
data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
status = write16(state, SCU_RAM_AGC_KI__A, data);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
{
int status;
dprintk(1, "\n");
if (packet_err == NULL)
status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
else
status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
packet_err);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int dvbt_sc_command(struct drxk_state *state,
u16 cmd, u16 subcmd,
u16 param0, u16 param1, u16 param2,
u16 param3, u16 param4)
{
u16 cur_cmd = 0;
u16 err_code = 0;
u16 retry_cnt = 0;
u16 sc_exec = 0;
int status;
dprintk(1, "\n");
status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
if (sc_exec != 1) {
/* SC is not running */
status = -EINVAL;
}
if (status < 0)
goto error;
/* Wait until sc is ready to receive command */
retry_cnt = 0;
do {
usleep_range(1000, 2000);
status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
retry_cnt++;
} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
goto error;
/* Write sub-command */
switch (cmd) {
/* All commands using sub-cmd */
case OFDM_SC_RA_RAM_CMD_PROC_START:
case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
if (status < 0)
goto error;
break;
default:
/* Do nothing */
break;
}
/* Write needed parameters and the command */
status = 0;
switch (cmd) {
/* All commands using 5 parameters */
/* All commands using 4 parameters */
/* All commands using 3 parameters */
/* All commands using 2 parameters */
case OFDM_SC_RA_RAM_CMD_PROC_START:
case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
fallthrough; /* All commands using 1 parameters */
case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
case OFDM_SC_RA_RAM_CMD_USER_IO:
status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
fallthrough; /* All commands using 0 parameters */
case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
case OFDM_SC_RA_RAM_CMD_NULL:
/* Write command */
status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
break;
default:
/* Unknown command */
status = -EINVAL;
}
if (status < 0)
goto error;
/* Wait until sc is ready processing command */
retry_cnt = 0;
do {
usleep_range(1000, 2000);
status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
retry_cnt++;
} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
goto error;
/* Check for illegal cmd */
status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
if (err_code == 0xFFFF) {
/* illegal command */
status = -EINVAL;
}
if (status < 0)
goto error;
/* Retrieve results parameters from SC */
switch (cmd) {
/* All commands yielding 5 results */
/* All commands yielding 4 results */
/* All commands yielding 3 results */
/* All commands yielding 2 results */
/* All commands yielding 1 result */
case OFDM_SC_RA_RAM_CMD_USER_IO:
case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
break;
/* All commands yielding 0 results */
case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
case OFDM_SC_RA_RAM_CMD_SET_TIMER:
case OFDM_SC_RA_RAM_CMD_PROC_START:
case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
case OFDM_SC_RA_RAM_CMD_NULL:
break;
default:
/* Unknown command */
status = -EINVAL;
break;
} /* switch (cmd->cmd) */
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int power_up_dvbt(struct drxk_state *state)
{
enum drx_power_mode power_mode = DRX_POWER_UP;
int status;
dprintk(1, "\n");
status = ctrl_power_mode(state, &power_mode);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
{
int status;
dprintk(1, "\n");
if (*enabled)
status = write16(state, IQM_CF_BYPASSDET__A, 0);
else
status = write16(state, IQM_CF_BYPASSDET__A, 1);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
#define DEFAULT_FR_THRES_8K 4000
static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
{
int status;
dprintk(1, "\n");
if (*enabled) {
/* write mask to 1 */
status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
DEFAULT_FR_THRES_8K);
} else {
/* write mask to 0 */
status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
}
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
{
u16 data = 0;
int status;
dprintk(1, "\n");
status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
if (status < 0)
goto error;
switch (echo_thres->fft_mode) {
case DRX_FFTMODE_2K:
data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
data |= ((echo_thres->threshold <<
OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
& (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
break;
case DRX_FFTMODE_8K:
data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
data |= ((echo_thres->threshold <<
OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
& (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
break;
default:
return -EINVAL;
}
status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
enum drxk_cfg_dvbt_sqi_speed *speed)
{
int status = -EINVAL;
dprintk(1, "\n");
switch (*speed) {
case DRXK_DVBT_SQI_SPEED_FAST:
case DRXK_DVBT_SQI_SPEED_MEDIUM:
case DRXK_DVBT_SQI_SPEED_SLOW:
break;
default:
goto error;
}
status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
(u16) *speed);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Activate DVBT specific presets
* \param demod instance of demodulator.
* \return DRXStatus_t.
*
* Called in DVBTSetStandard
*
*/
static int dvbt_activate_presets(struct drxk_state *state)
{
int status;
bool setincenable = false;
bool setfrenable = true;
struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
dprintk(1, "\n");
status = dvbt_ctrl_set_inc_enable(state, &setincenable);
if (status < 0)
goto error;
status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
if (status < 0)
goto error;
status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
if (status < 0)
goto error;
status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
state->m_dvbt_if_agc_cfg.ingain_tgt_max);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Initialize channelswitch-independent settings for DVBT.
* \param demod instance of demodulator.
* \return DRXStatus_t.
*
* For ROM code channel filter taps are loaded from the bootloader. For microcode
* the DVB-T taps from the drxk_filters.h are used.
*/
static int set_dvbt_standard(struct drxk_state *state,
enum operation_mode o_mode)
{
u16 cmd_result = 0;
u16 data = 0;
int status;
dprintk(1, "\n");
power_up_dvbt(state);
/* added antenna switch */
switch_antenna_to_dvbt(state);
/* send OFDM reset command */
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* send OFDM setenv command */
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* reset datapath for OFDM, processors first */
status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
if (status < 0)
goto error;
/* IQM setup */
/* synchronize on ofdstate->m_festart */
status = write16(state, IQM_AF_UPD_SEL__A, 1);
if (status < 0)
goto error;
/* window size for clipping ADC detection */
status = write16(state, IQM_AF_CLP_LEN__A, 0);
if (status < 0)
goto error;
/* window size for sense pre-SAW detection */
status = write16(state, IQM_AF_SNS_LEN__A, 0);
if (status < 0)
goto error;
/* sense threshold for sense pre-SAW detection */
status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
if (status < 0)
goto error;
status = set_iqm_af(state, true);
if (status < 0)
goto error;
status = write16(state, IQM_AF_AGC_RF__A, 0);
if (status < 0)
goto error;
/* Impulse noise cruncher setup */
status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
if (status < 0)
goto error;
status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
if (status < 0)
goto error;
status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
if (status < 0)
goto error;
status = write16(state, IQM_RC_STRETCH__A, 16);
if (status < 0)
goto error;
status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
if (status < 0)
goto error;
status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
if (status < 0)
goto error;
status = write16(state, IQM_CF_SCALE__A, 1600);
if (status < 0)
goto error;
status = write16(state, IQM_CF_SCALE_SH__A, 0);
if (status < 0)
goto error;
/* virtual clipping threshold for clipping ADC detection */
status = write16(state, IQM_AF_CLP_TH__A, 448);
if (status < 0)
goto error;
status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
if (status < 0)
goto error;
status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
if (status < 0)
goto error;
status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
if (status < 0)
goto error;
status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
if (status < 0)
goto error;
/* enable power measurement interrupt */
status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
if (status < 0)
goto error;
/* IQM will not be reset from here, sync ADC and update/init AGC */
status = adc_synchronization(state);
if (status < 0)
goto error;
status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
if (status < 0)
goto error;
/* Halt SCU to enable safe non-atomic accesses */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
if (status < 0)
goto error;
status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
if (status < 0)
goto error;
status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
if (status < 0)
goto error;
/* Set Noise Estimation notch width and enable DC fix */
status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
if (status < 0)
goto error;
data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
if (status < 0)
goto error;
/* Activate SCU to enable SCU commands */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
if (!state->m_drxk_a3_rom_code) {
/* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
if (status < 0)
goto error;
}
/* OFDM_SC setup */
#ifdef COMPILE_FOR_NONRT
status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
if (status < 0)
goto error;
#endif
/* FEC setup */
status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
if (status < 0)
goto error;
#ifdef COMPILE_FOR_NONRT
status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
if (status < 0)
goto error;
#else
status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
if (status < 0)
goto error;
#endif
status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
if (status < 0)
goto error;
/* Setup MPEG bus */
status = mpegts_dto_setup(state, OM_DVBT);
if (status < 0)
goto error;
/* Set DVBT Presets */
status = dvbt_activate_presets(state);
if (status < 0)
goto error;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief start dvbt demodulating for channel.
* \param demod instance of demodulator.
* \return DRXStatus_t.
*/
static int dvbt_start(struct drxk_state *state)
{
u16 param1;
int status;
/* drxk_ofdm_sc_cmd_t scCmd; */
dprintk(1, "\n");
/* start correct processes to get in lock */
/* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
0, 0, 0);
if (status < 0)
goto error;
/* start FEC OC */
status = mpegts_start(state);
if (status < 0)
goto error;
status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Set up dvbt demodulator for channel.
* \param demod instance of demodulator.
* \return DRXStatus_t.
* // original DVBTSetChannel()
*/
static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
s32 tuner_freq_offset)
{
u16 cmd_result = 0;
u16 transmission_params = 0;
u32 iqm_rc_rate_ofs = 0;
u32 bandwidth = 0;
u16 param1;
int status;
dprintk(1, "IF =%d, TFO = %d\n",
intermediate_freqk_hz, tuner_freq_offset);
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* Halt SCU to enable safe non-atomic accesses */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
if (status < 0)
goto error;
/* Stop processors */
status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
if (status < 0)
goto error;
/* Mandatory fix, always stop CP, required to set spl offset back to
hardware default (is set to 0 by ucode during pilot detection */
status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
if (status < 0)
goto error;
/*== Write channel settings to device ================================*/
/* mode */
switch (state->props.transmission_mode) {
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
default:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
break;
case TRANSMISSION_MODE_2K:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
break;
}
/* guard */
switch (state->props.guard_interval) {
default:
case GUARD_INTERVAL_AUTO: /* try first guess DRX_GUARD_1DIV4 */
case GUARD_INTERVAL_1_4:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
break;
case GUARD_INTERVAL_1_32:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
break;
case GUARD_INTERVAL_1_16:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
break;
case GUARD_INTERVAL_1_8:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
break;
}
/* hierarchy */
switch (state->props.hierarchy) {
case HIERARCHY_AUTO:
case HIERARCHY_NONE:
default: /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
case HIERARCHY_1:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
break;
case HIERARCHY_2:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
break;
case HIERARCHY_4:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
break;
}
/* modulation */
switch (state->props.modulation) {
case QAM_AUTO:
default: /* try first guess DRX_CONSTELLATION_QAM64 */
case QAM_64:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
break;
case QPSK:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
break;
case QAM_16:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
break;
}
#if 0
/* No hierarchical channels support in BDA */
/* Priority (only for hierarchical channels) */
switch (channel->priority) {
case DRX_PRIORITY_LOW:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
OFDM_EC_SB_PRIOR_LO);
break;
case DRX_PRIORITY_HIGH:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
OFDM_EC_SB_PRIOR_HI));
break;
case DRX_PRIORITY_UNKNOWN:
default:
status = -EINVAL;
goto error;
}
#else
/* Set Priority high */
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
if (status < 0)
goto error;
#endif
/* coderate */
switch (state->props.code_rate_HP) {
case FEC_AUTO:
default: /* try first guess DRX_CODERATE_2DIV3 */
case FEC_2_3:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
break;
case FEC_1_2:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
break;
case FEC_3_4:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
break;
case FEC_5_6:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
break;
case FEC_7_8:
transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
break;
}
/*
* SAW filter selection: normally not necessary, but if wanted
* the application can select a SAW filter via the driver by
* using UIOs
*/
/* First determine real bandwidth (Hz) */
/* Also set delay for impulse noise cruncher */
/*
* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
* changed by SC for fix for some 8K,1/8 guard but is restored by
* InitEC and ResetEC functions
*/
switch (state->props.bandwidth_hz) {
case 0:
state->props.bandwidth_hz = 8000000;
fallthrough;
case 8000000:
bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3052);
if (status < 0)
goto error;
/* cochannel protection for PAL 8 MHz */
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
7);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
7);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
7);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
1);
if (status < 0)
goto error;
break;
case 7000000:
bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3491);
if (status < 0)
goto error;
/* cochannel protection for PAL 7 MHz */
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
8);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
8);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
4);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
1);
if (status < 0)
goto error;
break;
case 6000000:
bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
4073);
if (status < 0)
goto error;
/* cochannel protection for NTSC 6 MHz */
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
19);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
19);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
14);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
1);
if (status < 0)
goto error;
break;
default:
status = -EINVAL;
goto error;
}
if (iqm_rc_rate_ofs == 0) {
/* Now compute IQM_RC_RATE_OFS
(((SysFreq/BandWidth)/2)/2) -1) * 2^23)
=>
((SysFreq / BandWidth) * (2^21)) - (2^23)
*/
/* (SysFreq / BandWidth) * (2^28) */
/*
* assert (MAX(sysClk)/MIN(bandwidth) < 16)
* => assert(MAX(sysClk) < 16*MIN(bandwidth))
* => assert(109714272 > 48000000) = true
* so Frac 28 can be used
*/
iqm_rc_rate_ofs = Frac28a((u32)
((state->m_sys_clock_freq *
1000) / 3), bandwidth);
/* (SysFreq / BandWidth) * (2^21), rounding before truncating */
if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
iqm_rc_rate_ofs += 0x80L;
iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
/* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
}
iqm_rc_rate_ofs &=
((((u32) IQM_RC_RATE_OFS_HI__M) <<
IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
if (status < 0)
goto error;
/* Bandwidth setting done */
#if 0
status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
if (status < 0)
goto error;
#endif
status = set_frequency_shifter(state, intermediate_freqk_hz,
tuner_freq_offset, true);
if (status < 0)
goto error;
/*== start SC, write channel settings to SC ==========================*/
/* Activate SCU to enable SCU commands */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
/* Enable SC after setting all other parameters */
status = write16(state, OFDM_SC_COMM_STATE__A, 0);
if (status < 0)
goto error;
status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
if (status < 0)
goto error;
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_START,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* Write SC parameter registers, set all AUTO flags in operation mode */
param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
0, transmission_params, param1, 0, 0, 0);
if (status < 0)
goto error;
if (!state->m_drxk_a3_rom_code)
status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Retrieve lock status .
* \param demod Pointer to demodulator instance.
* \param lockStat Pointer to lock status structure.
* \return DRXStatus_t.
*
*/
static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
{
int status;
const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
OFDM_SC_RA_RAM_LOCK_FEC__M);
const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
u16 sc_ra_ram_lock = 0;
u16 sc_comm_exec = 0;
dprintk(1, "\n");
*p_lock_status = NOT_LOCKED;
/* driver 0.9.0 */
/* Check if SC is running */
status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
if (status < 0)
goto end;
if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
goto end;
status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
if (status < 0)
goto end;
if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
*p_lock_status = MPEG_LOCK;
else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
*p_lock_status = FEC_LOCK;
else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
*p_lock_status = DEMOD_LOCK;
else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
*p_lock_status = NEVER_LOCK;
end:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int power_up_qam(struct drxk_state *state)
{
enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
int status;
dprintk(1, "\n");
status = ctrl_power_mode(state, &power_mode);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/* Power Down QAM */
static int power_down_qam(struct drxk_state *state)
{
u16 data = 0;
u16 cmd_result;
int status = 0;
dprintk(1, "\n");
status = read16(state, SCU_COMM_EXEC__A, &data);
if (status < 0)
goto error;
if (data == SCU_COMM_EXEC_ACTIVE) {
/*
STOP demodulator
QAM and HW blocks
*/
/* stop all comstate->m_exec */
status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
}
/* powerdown AFE */
status = set_iqm_af(state, false);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Setup of the QAM Measurement intervals for signal quality
* \param demod instance of demod.
* \param modulation current modulation.
* \return DRXStatus_t.
*
* NOTE:
* Take into account that for certain settings the errorcounters can overflow.
* The implementation does not check this.
*
*/
static int set_qam_measurement(struct drxk_state *state,
enum e_drxk_constellation modulation,
u32 symbol_rate)
{
u32 fec_bits_desired = 0; /* BER accounting period */
u32 fec_rs_period_total = 0; /* Total period */
u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
u16 fec_rs_period = 0; /* Value for corresponding I2C register */
int status = 0;
dprintk(1, "\n");
fec_rs_prescale = 1;
/* fec_bits_desired = symbol_rate [kHz] *
FrameLenght [ms] *
(modulation + 1) *
SyncLoss (== 1) *
ViterbiLoss (==1)
*/
switch (modulation) {
case DRX_CONSTELLATION_QAM16:
fec_bits_desired = 4 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM32:
fec_bits_desired = 5 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM64:
fec_bits_desired = 6 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM128:
fec_bits_desired = 7 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM256:
fec_bits_desired = 8 * symbol_rate;
break;
default:
status = -EINVAL;
}
if (status < 0)
goto error;
fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
fec_bits_desired *= 500; /* meas. period [ms] */
/* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
/* fec_rs_period_total = fec_bits_desired / 1632 */
fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */
/* fec_rs_period_total = fec_rs_prescale * fec_rs_period */
fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
if (fec_rs_prescale == 0) {
/* Divide by zero (though impossible) */
status = -EINVAL;
if (status < 0)
goto error;
}
fec_rs_period =
((u16) fec_rs_period_total +
(fec_rs_prescale >> 1)) / fec_rs_prescale;
/* write corresponding registers */
status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
if (status < 0)
goto error;
status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
fec_rs_prescale);
if (status < 0)
goto error;
status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int set_qam16(struct drxk_state *state)
{
int status = 0;
dprintk(1, "\n");
/* QAM Equalizer Setup */
/* Equalizer */
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
if (status < 0)
goto error;
/* Decision Feedback Equalizer */
status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_HWM__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_AWM__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_LWM__A, 3);
if (status < 0)
goto error;
/* QAM Slicer Settings */
status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
DRXK_QAM_SL_SIG_POWER_QAM16);
if (status < 0)
goto error;
/* QAM Loop Controller Coeficients */
status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
if (status < 0)
goto error;
/* QAM State Machine (FSM) Thresholds */
status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
if (status < 0)
goto error;
/* QAM FSM Tracking Parameters */
status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
if (status < 0)
goto error;
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief QAM32 specific setup
* \param demod instance of demod.
* \return DRXStatus_t.
*/
static int set_qam32(struct drxk_state *state)
{
int status = 0;
dprintk(1, "\n");
/* QAM Equalizer Setup */
/* Equalizer */
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
if (status < 0)
goto error;
/* Decision Feedback Equalizer */
status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_HWM__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_AWM__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_LWM__A, 3);
if (status < 0)
goto error;
/* QAM Slicer Settings */
status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
DRXK_QAM_SL_SIG_POWER_QAM32);
if (status < 0)
goto error;
/* QAM Loop Controller Coeficients */
status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
if (status < 0)
goto error;
/* QAM State Machine (FSM) Thresholds */
status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
if (status < 0)
goto error;
/* QAM FSM Tracking Parameters */
status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief QAM64 specific setup
* \param demod instance of demod.
* \return DRXStatus_t.
*/
static int set_qam64(struct drxk_state *state)
{
int status = 0;
dprintk(1, "\n");
/* QAM Equalizer Setup */
/* Equalizer */
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
if (status < 0)
goto error;
/* Decision Feedback Equalizer */
status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_HWM__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_AWM__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_LWM__A, 3);
if (status < 0)
goto error;
/* QAM Slicer Settings */
status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
DRXK_QAM_SL_SIG_POWER_QAM64);
if (status < 0)
goto error;
/* QAM Loop Controller Coeficients */
status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
if (status < 0)
goto error;
/* QAM State Machine (FSM) Thresholds */
status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
if (status < 0)
goto error;
/* QAM FSM Tracking Parameters */
status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief QAM128 specific setup
* \param demod: instance of demod.
* \return DRXStatus_t.
*/
static int set_qam128(struct drxk_state *state)
{
int status = 0;
dprintk(1, "\n");
/* QAM Equalizer Setup */
/* Equalizer */
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
if (status < 0)
goto error;
/* Decision Feedback Equalizer */
status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_HWM__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_AWM__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_LWM__A, 3);
if (status < 0)
goto error;
/* QAM Slicer Settings */
status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
DRXK_QAM_SL_SIG_POWER_QAM128);
if (status < 0)
goto error;
/* QAM Loop Controller Coeficients */
status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
if (status < 0)
goto error;
/* QAM State Machine (FSM) Thresholds */
status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
if (status < 0)
goto error;
/* QAM FSM Tracking Parameters */
status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief QAM256 specific setup
* \param demod: instance of demod.
* \return DRXStatus_t.
*/
static int set_qam256(struct drxk_state *state)
{
int status = 0;
dprintk(1, "\n");
/* QAM Equalizer Setup */
/* Equalizer */
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
if (status < 0)
goto error;
/* Decision Feedback Equalizer */
status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
if (status < 0)
goto error;
status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_HWM__A, 5);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_AWM__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_SY_SYNC_LWM__A, 3);
if (status < 0)
goto error;
/* QAM Slicer Settings */
status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
DRXK_QAM_SL_SIG_POWER_QAM256);
if (status < 0)
goto error;
/* QAM Loop Controller Coeficients */
status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
if (status < 0)
goto error;
/* QAM State Machine (FSM) Thresholds */
status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
if (status < 0)
goto error;
/* QAM FSM Tracking Parameters */
status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Reset QAM block.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \return DRXStatus_t.
*/
static int qam_reset_qam(struct drxk_state *state)
{
int status;
u16 cmd_result;
dprintk(1, "\n");
/* Stop QAM comstate->m_exec */
status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
0, NULL, 1, &cmd_result);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Set QAM symbolrate.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \return DRXStatus_t.
*/
static int qam_set_symbolrate(struct drxk_state *state)
{
u32 adc_frequency = 0;
u32 symb_freq = 0;
u32 iqm_rc_rate = 0;
u16 ratesel = 0;
u32 lc_symb_rate = 0;
int status;
dprintk(1, "\n");
/* Select & calculate correct IQM rate */
adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
ratesel = 0;
if (state->props.symbol_rate <= 1188750)
ratesel = 3;
else if (state->props.symbol_rate <= 2377500)
ratesel = 2;
else if (state->props.symbol_rate <= 4755000)
ratesel = 1;
status = write16(state, IQM_FD_RATESEL__A, ratesel);
if (status < 0)
goto error;
/*
IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
*/
symb_freq = state->props.symbol_rate * (1 << ratesel);
if (symb_freq == 0) {
/* Divide by zero */
status = -EINVAL;
goto error;
}
iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
(Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
(1 << 23);
status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
if (status < 0)
goto error;
state->m_iqm_rc_rate = iqm_rc_rate;
/*
LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15))
*/
symb_freq = state->props.symbol_rate;
if (adc_frequency == 0) {
/* Divide by zero */
status = -EINVAL;
goto error;
}
lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
(Frac28a((symb_freq % adc_frequency), adc_frequency) >>
16);
if (lc_symb_rate > 511)
lc_symb_rate = 511;
status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
/*============================================================================*/
/*
* \brief Get QAM lock status.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \return DRXStatus_t.
*/
static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
{
int status;
u16 result[2] = { 0, 0 };
dprintk(1, "\n");
*p_lock_status = NOT_LOCKED;
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
result);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
/* 0x0000 NOT LOCKED */
} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
/* 0x4000 DEMOD LOCKED */
*p_lock_status = DEMOD_LOCK;
} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
/* 0x8000 DEMOD + FEC LOCKED (system lock) */
*p_lock_status = MPEG_LOCK;
} else {
/* 0xC000 NEVER LOCKED */
/* (system will never be able to lock to the signal) */
/*
* TODO: check this, intermediate & standard specific lock
* states are not taken into account here
*/
*p_lock_status = NEVER_LOCK;
}
return status;
}
#define QAM_MIRROR__M 0x03
#define QAM_MIRROR_NORMAL 0x00
#define QAM_MIRRORED 0x01
#define QAM_MIRROR_AUTO_ON 0x02
#define QAM_LOCKRANGE__M 0x10
#define QAM_LOCKRANGE_NORMAL 0x10
static int qam_demodulator_command(struct drxk_state *state,
int number_of_parameters)
{
int status;
u16 cmd_result;
u16 set_param_parameters[4] = { 0, 0, 0, 0 };
set_param_parameters[0] = state->m_constellation; /* modulation */
set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
if (number_of_parameters == 2) {
u16 set_env_parameters[1] = { 0 };
if (state->m_operation_mode == OM_QAM_ITU_C)
set_env_parameters[0] = QAM_TOP_ANNEX_C;
else
set_env_parameters[0] = QAM_TOP_ANNEX_A;
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
1, set_env_parameters, 1, &cmd_result);
if (status < 0)
goto error;
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
number_of_parameters, set_param_parameters,
1, &cmd_result);
} else if (number_of_parameters == 4) {
if (state->m_operation_mode == OM_QAM_ITU_C)
set_param_parameters[2] = QAM_TOP_ANNEX_C;
else
set_param_parameters[2] = QAM_TOP_ANNEX_A;
set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
/* Env parameters */
/* check for LOCKRANGE Extended */
/* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
status = scu_command(state,
SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
number_of_parameters, set_param_parameters,
1, &cmd_result);
} else {
pr_warn("Unknown QAM demodulator parameter count %d\n",
number_of_parameters);
status = -EINVAL;
}
error:
if (status < 0)
pr_warn("Warning %d on %s\n", status, __func__);
return status;
}
static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
s32 tuner_freq_offset)
{
int status;
u16 cmd_result;
int qam_demod_param_count = state->qam_demod_parameter_count;
dprintk(1, "\n");
/*
* STEP 1: reset demodulator
* resets FEC DI and FEC RS
* resets QAM block
* resets SCU variables
*/
status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = qam_reset_qam(state);
if (status < 0)
goto error;
/*
* STEP 2: configure demodulator
* -set params; resets IQM,QAM,FEC HW; initializes some
* SCU variables
*/
status = qam_set_symbolrate(state);
if (status < 0)
goto error;
/* Set params */
switch (state->props.modulation) {
case QAM_256:
state->m_constellation = DRX_CONSTELLATION_QAM256;
break;
case QAM_AUTO:
case QAM_64:
state->m_constellation = DRX_CONSTELLATION_QAM64;
break;
case QAM_16:
state->m_constellation = DRX_CONSTELLATION_QAM16;
break;
case QAM_32:
state->m_constellation = DRX_CONSTELLATION_QAM32;
break;
case QAM_128:
state->m_constellation = DRX_CONSTELLATION_QAM128;
break;
default:
status = -EINVAL;
break;
}
if (status < 0)
goto error;
/* Use the 4-parameter if it's requested or we're probing for
* the correct command. */
if (state->qam_demod_parameter_count == 4
|| !state->qam_demod_parameter_count) {
qam_demod_param_count = 4;
status = qam_demodulator_command(state, qam_demod_param_count);
}
/* Use the 2-parameter command if it was requested or if we're
* probing for the correct command and the 4-parameter command
* failed. */
if (state->qam_demod_parameter_count == 2
|| (!state->qam_demod_parameter_count && status < 0)) {
qam_demod_param_count = 2;
status = qam_demodulator_command(state, qam_demod_param_count);
}
if (status < 0) {
dprintk(1, "Could not set demodulator parameters.\n");
dprintk(1,
"Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
state->qam_demod_parameter_count,
state->microcode_name);
goto error;
} else if (!state->qam_demod_parameter_count) {
dprintk(1,
"Auto-probing the QAM command parameters was successful - using %d parameters.\n",
qam_demod_param_count);
/*
* One of our commands was successful. We don't need to
* auto-probe anymore, now that we got the correct command.
*/
state->qam_demod_parameter_count = qam_demod_param_count;
}
/*
* STEP 3: enable the system in a mode where the ADC provides valid
* signal setup modulation independent registers
*/
#if 0
status = set_frequency(channel, tuner_freq_offset));
if (status < 0)
goto error;
#endif
status = set_frequency_shifter(state, intermediate_freqk_hz,
tuner_freq_offset, true);
if (status < 0)
goto error;
/* Setup BER measurement */
status = set_qam_measurement(state, state->m_constellation,
state->props.symbol_rate);
if (status < 0)
goto error;
/* Reset default values */
status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
if (status < 0)
goto error;
status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
if (status < 0)
goto error;
/* Reset default LC values */
status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_LC_MODE__A, 7);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
if (status < 0)
goto error;
status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
if (status < 0)
goto error;
/* Mirroring, QAM-block starting point not inverted */
status = write16(state, QAM_SY_SP_INV__A,
QAM_SY_SP_INV_SPECTRUM_INV_DIS);
if (status < 0)
goto error;
/* Halt SCU to enable safe non-atomic accesses */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
if (status < 0)
goto error;
/* STEP 4: modulation specific setup */
switch (state->props.modulation) {
case QAM_16:
status = set_qam16(state);
break;
case QAM_32:
status = set_qam32(state);
break;
case QAM_AUTO:
case QAM_64:
status = set_qam64(state);
break;
case QAM_128:
status = set_qam128(state);
break;
case QAM_256:
status = set_qam256(state);
break;
default:
status = -EINVAL;
break;
}
if (status < 0)
goto error;
/* Activate SCU to enable SCU commands */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
/* Re-configure MPEG output, requires knowledge of channel bitrate */
/* extAttr->currentChannel.modulation = channel->modulation; */
/* extAttr->currentChannel.symbolrate = channel->symbolrate; */
status = mpegts_dto_setup(state, state->m_operation_mode);
if (status < 0)
goto error;
/* start processes */
status = mpegts_start(state);
if (status < 0)
goto error;
status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
if (status < 0)
goto error;
/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_START,
0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* update global DRXK data container */
/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int set_qam_standard(struct drxk_state *state,
enum operation_mode o_mode)
{
int status;
#ifdef DRXK_QAM_TAPS
#define DRXK_QAMA_TAPS_SELECT
#include "drxk_filters.h"
#undef DRXK_QAMA_TAPS_SELECT
#endif
dprintk(1, "\n");
/* added antenna switch */
switch_antenna_to_qam(state);
/* Ensure correct power-up mode */
status = power_up_qam(state);
if (status < 0)
goto error;
/* Reset QAM block */
status = qam_reset_qam(state);
if (status < 0)
goto error;
/* Setup IQM */
status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
if (status < 0)
goto error;
status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
if (status < 0)
goto error;
/* Upload IQM Channel Filter settings by
boot loader from ROM table */
switch (o_mode) {
case OM_QAM_ITU_A:
status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
DRXK_BLCC_NR_ELEMENTS_TAPS,
DRXK_BLC_TIMEOUT);
break;
case OM_QAM_ITU_C:
status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
DRXK_BLDC_NR_ELEMENTS_TAPS,
DRXK_BLC_TIMEOUT);
if (status < 0)
goto error;
status = bl_direct_cmd(state,
IQM_CF_TAP_IM0__A,
DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
DRXK_BLDC_NR_ELEMENTS_TAPS,
DRXK_BLC_TIMEOUT);
break;
default:
status = -EINVAL;
}
if (status < 0)
goto error;
status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
if (status < 0)
goto error;
status = write16(state, IQM_CF_SYMMETRIC__A, 0);
if (status < 0)
goto error;
status = write16(state, IQM_CF_MIDTAP__A,
((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
if (status < 0)
goto error;
status = write16(state, IQM_RC_STRETCH__A, 21);
if (status < 0)
goto error;
status = write16(state, IQM_AF_CLP_LEN__A, 0);
if (status < 0)
goto error;
status = write16(state, IQM_AF_CLP_TH__A, 448);
if (status < 0)
goto error;
status = write16(state, IQM_AF_SNS_LEN__A, 0);
if (status < 0)
goto error;
status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
if (status < 0)
goto error;
status = write16(state, IQM_FS_ADJ_SEL__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_RC_ADJ_SEL__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_CF_ADJ_SEL__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_AF_UPD_SEL__A, 0);
if (status < 0)
goto error;
/* IQM Impulse Noise Processing Unit */
status = write16(state, IQM_CF_CLP_VAL__A, 500);
if (status < 0)
goto error;
status = write16(state, IQM_CF_DATATH__A, 1000);
if (status < 0)
goto error;
status = write16(state, IQM_CF_BYPASSDET__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_CF_DET_LCT__A, 0);
if (status < 0)
goto error;
status = write16(state, IQM_CF_WND_LEN__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_CF_PKDTH__A, 1);
if (status < 0)
goto error;
status = write16(state, IQM_AF_INC_BYPASS__A, 1);
if (status < 0)
goto error;
/* turn on IQMAF. Must be done before setAgc**() */
status = set_iqm_af(state, true);
if (status < 0)
goto error;
status = write16(state, IQM_AF_START_LOCK__A, 0x01);
if (status < 0)
goto error;
/* IQM will not be reset from here, sync ADC and update/init AGC */
status = adc_synchronization(state);
if (status < 0)
goto error;
/* Set the FSM step period */
status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
if (status < 0)
goto error;
/* Halt SCU to enable safe non-atomic accesses */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
if (status < 0)
goto error;
/* No more resets of the IQM, current standard correctly set =>
now AGCs can be configured. */
status = init_agc(state, true);
if (status < 0)
goto error;
status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
if (status < 0)
goto error;
/* Configure AGC's */
status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
if (status < 0)
goto error;
status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
if (status < 0)
goto error;
/* Activate SCU to enable SCU commands */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int write_gpio(struct drxk_state *state)
{
int status;
u16 value = 0;
dprintk(1, "\n");
/* stop lock indicator process */
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
/* Write magic word to enable pdr reg write */
status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
if (status < 0)
goto error;
if (state->m_has_sawsw) {
if (state->uio_mask & 0x0001) { /* UIO-1 */
/* write to io pad configuration register - output mode */
status = write16(state, SIO_PDR_SMA_TX_CFG__A,
state->m_gpio_cfg);
if (status < 0)
goto error;
/* use corresponding bit in io data output registar */
status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
if (status < 0)
goto error;
if ((state->m_gpio & 0x0001) == 0)
value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
else
value |= 0x8000; /* write one to 15th bit - 1st UIO */
/* write back to io data output register */
status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
if (status < 0)
goto error;
}
if (state->uio_mask & 0x0002) { /* UIO-2 */
/* write to io pad configuration register - output mode */
status = write16(state, SIO_PDR_SMA_RX_CFG__A,
state->m_gpio_cfg);
if (status < 0)
goto error;
/* use corresponding bit in io data output registar */
status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
if (status < 0)
goto error;
if ((state->m_gpio & 0x0002) == 0)
value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
else
value |= 0x4000; /* write one to 14th bit - 2st UIO */
/* write back to io data output register */
status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
if (status < 0)
goto error;
}
if (state->uio_mask & 0x0004) { /* UIO-3 */
/* write to io pad configuration register - output mode */
status = write16(state, SIO_PDR_GPIO_CFG__A,
state->m_gpio_cfg);
if (status < 0)
goto error;
/* use corresponding bit in io data output registar */
status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
if (status < 0)
goto error;
if ((state->m_gpio & 0x0004) == 0)
value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
else
value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
/* write back to io data output register */
status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
if (status < 0)
goto error;
}
}
/* Write magic word to disable pdr reg write */
status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int switch_antenna_to_qam(struct drxk_state *state)
{
int status = 0;
bool gpio_state;
dprintk(1, "\n");
if (!state->antenna_gpio)
return 0;
gpio_state = state->m_gpio & state->antenna_gpio;
if (state->antenna_dvbt ^ gpio_state) {
/* Antenna is on DVB-T mode. Switch */
if (state->antenna_dvbt)
state->m_gpio &= ~state->antenna_gpio;
else
state->m_gpio |= state->antenna_gpio;
status = write_gpio(state);
}
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int switch_antenna_to_dvbt(struct drxk_state *state)
{
int status = 0;
bool gpio_state;
dprintk(1, "\n");
if (!state->antenna_gpio)
return 0;
gpio_state = state->m_gpio & state->antenna_gpio;
if (!(state->antenna_dvbt ^ gpio_state)) {
/* Antenna is on DVB-C mode. Switch */
if (state->antenna_dvbt)
state->m_gpio |= state->antenna_gpio;
else
state->m_gpio &= ~state->antenna_gpio;
status = write_gpio(state);
}
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int power_down_device(struct drxk_state *state)
{
/* Power down to requested mode */
/* Backup some register settings */
/* Set pins with possible pull-ups connected to them in input mode */
/* Analog power down */
/* ADC power down */
/* Power down device */
int status;
dprintk(1, "\n");
if (state->m_b_p_down_open_bridge) {
/* Open I2C bridge before power down of DRXK */
status = ConfigureI2CBridge(state, true);
if (status < 0)
goto error;
}
/* driver 0.9.0 */
status = dvbt_enable_ofdm_token_ring(state, false);
if (status < 0)
goto error;
status = write16(state, SIO_CC_PWD_MODE__A,
SIO_CC_PWD_MODE_LEVEL_CLOCK);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
status = hi_cfg_command(state);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
}
static int init_drxk(struct drxk_state *state)
{
int status = 0, n = 0;
enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
u16 driver_version;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_UNINITIALIZED) {
drxk_i2c_lock(state);
status = power_up_device(state);
if (status < 0)
goto error;
status = drxx_open(state);
if (status < 0)
goto error;
/* Soft reset of OFDM-, sys- and osc-clockdomain */
status = write16(state, SIO_CC_SOFT_RST__A,
SIO_CC_SOFT_RST_OFDM__M
| SIO_CC_SOFT_RST_SYS__M
| SIO_CC_SOFT_RST_OSC__M);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
/*
* TODO is this needed? If yes, how much delay in
* worst case scenario
*/
usleep_range(1000, 2000);
state->m_drxk_a3_patch_code = true;
status = get_device_capabilities(state);
if (status < 0)
goto error;
/* Bridge delay, uses oscilator clock */
/* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
/* SDA brdige delay */
state->m_hi_cfg_bridge_delay =
(u16) ((state->m_osc_clock_freq / 1000) *
HI_I2C_BRIDGE_DELAY) / 1000;
/* Clipping */
if (state->m_hi_cfg_bridge_delay >
SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
state->m_hi_cfg_bridge_delay =
SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
}
/* SCL bridge delay, same as SDA for now */
state->m_hi_cfg_bridge_delay +=
state->m_hi_cfg_bridge_delay <<
SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
status = init_hi(state);
if (status < 0)
goto error;
/* disable various processes */
#if NOA1ROM
if (!(state->m_DRXK_A1_ROM_CODE)
&& !(state->m_DRXK_A2_ROM_CODE))
#endif
{
status = write16(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
}
/* disable MPEG port */
status = mpegts_disable(state);
if (status < 0)
goto error;
/* Stop AUD and SCU */
status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
if (status < 0)
goto error;
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
if (status < 0)
goto error;
/* enable token-ring bus through OFDM block for possible ucode upload */
status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
if (status < 0)
goto error;
/* include boot loader section */
status = write16(state, SIO_BL_COMM_EXEC__A,
SIO_BL_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = bl_chain_cmd(state, 0, 6, 100);
if (status < 0)
goto error;
if (state->fw) {
status = download_microcode(state, state->fw->data,
state->fw->size);
if (status < 0)
goto error;
}
/* disable token-ring bus through OFDM block for possible ucode upload */
status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
if (status < 0)
goto error;
/* Run SCU for a little while to initialize microcode version numbers */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = drxx_open(state);
if (status < 0)
goto error;
/* added for test */
msleep(30);
power_mode = DRXK_POWER_DOWN_OFDM;
status = ctrl_power_mode(state, &power_mode);
if (status < 0)
goto error;
/* Stamp driver version number in SCU data RAM in BCD code
Done to enable field application engineers to retrieve drxdriver version
via I2C from SCU RAM.
Not using SCU command interface for SCU register access since no
microcode may be present.
*/
driver_version =
(((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
(((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
((DRXK_VERSION_MAJOR % 10) << 4) +
(DRXK_VERSION_MINOR % 10);
status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
driver_version);
if (status < 0)
goto error;
driver_version =
(((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
(((DRXK_VERSION_PATCH / 100) % 10) << 8) +
(((DRXK_VERSION_PATCH / 10) % 10) << 4) +
(DRXK_VERSION_PATCH % 10);
status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
driver_version);
if (status < 0)
goto error;
pr_info("DRXK driver version %d.%d.%d\n",
DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
DRXK_VERSION_PATCH);
/*
* Dirty fix of default values for ROM/PATCH microcode
* Dirty because this fix makes it impossible to setup
* suitable values before calling DRX_Open. This solution
* requires changes to RF AGC speed to be done via the CTRL
* function after calling DRX_Open
*/
/* m_dvbt_rf_agc_cfg.speed = 3; */
/* Reset driver debug flags to 0 */
status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
if (status < 0)
goto error;
/* driver 0.9.0 */
/* Setup FEC OC:
NOTE: No more full FEC resets allowed afterwards!! */
status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
if (status < 0)
goto error;
/* MPEGTS functions are still the same */
status = mpegts_dto_init(state);
if (status < 0)
goto error;
status = mpegts_stop(state);
if (status < 0)
goto error;
status = mpegts_configure_polarity(state);
if (status < 0)
goto error;
status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
if (status < 0)
goto error;
/* added: configure GPIO */
status = write_gpio(state);
if (status < 0)
goto error;
state->m_drxk_state = DRXK_STOPPED;
if (state->m_b_power_down) {
status = power_down_device(state);
if (status < 0)
goto error;
state->m_drxk_state = DRXK_POWERED_DOWN;
} else
state->m_drxk_state = DRXK_STOPPED;
/* Initialize the supported delivery systems */
n = 0;
if (state->m_has_dvbc) {
state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
strlcat(state->frontend.ops.info.name, " DVB-C",
sizeof(state->frontend.ops.info.name));
}
if (state->m_has_dvbt) {
state->frontend.ops.delsys[n++] = SYS_DVBT;
strlcat(state->frontend.ops.info.name, " DVB-T",
sizeof(state->frontend.ops.info.name));
}
drxk_i2c_unlock(state);
}
error:
if (status < 0) {
state->m_drxk_state = DRXK_NO_DEV;
drxk_i2c_unlock(state);
pr_err("Error %d on %s\n", status, __func__);
}
return status;
}
static void load_firmware_cb(const struct firmware *fw,
void *context)
{
struct drxk_state *state = context;
dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
if (!fw) {
pr_err("Could not load firmware file %s.\n",
state->microcode_name);
pr_info("Copy %s to your hotplug directory!\n",
state->microcode_name);
state->microcode_name = NULL;
/*
* As firmware is now load asynchronous, it is not possible
* anymore to fail at frontend attach. We might silently
* return here, and hope that the driver won't crash.
* We might also change all DVB callbacks to return -ENODEV
* if the device is not initialized.
* As the DRX-K devices have their own internal firmware,
* let's just hope that it will match a firmware revision
* compatible with this driver and proceed.
*/
}
state->fw = fw;
init_drxk(state);
}
static void drxk_release(struct dvb_frontend *fe)
{
struct drxk_state *state = fe->demodulator_priv;
dprintk(1, "\n");
release_firmware(state->fw);
kfree(state);
}
static int drxk_sleep(struct dvb_frontend *fe)
{
struct drxk_state *state = fe->demodulator_priv;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return 0;
shut_down(state);
return 0;
}
static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct drxk_state *state = fe->demodulator_priv;
dprintk(1, ": %s\n", enable ? "enable" : "disable");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
return ConfigureI2CBridge(state, enable ? true : false);
}
static int drxk_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 delsys = p->delivery_system, old_delsys;
struct drxk_state *state = fe->demodulator_priv;
u32 IF;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
if (!fe->ops.tuner_ops.get_if_frequency) {
pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
return -EINVAL;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
old_delsys = state->props.delivery_system;
state->props = *p;
if (old_delsys != delsys) {
shut_down(state);
switch (delsys) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
if (!state->m_has_dvbc)
return -EINVAL;
state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
true : false;
if (state->m_itut_annex_c)
setoperation_mode(state, OM_QAM_ITU_C);
else
setoperation_mode(state, OM_QAM_ITU_A);
break;
case SYS_DVBT:
if (!state->m_has_dvbt)
return -EINVAL;
setoperation_mode(state, OM_DVBT);
break;
default:
return -EINVAL;
}
}
fe->ops.tuner_ops.get_if_frequency(fe, &IF);
start(state, 0, IF);
/* After set_frontend, stats aren't available */
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
return 0;
}
static int get_strength(struct drxk_state *state, u64 *strength)
{
int status;
struct s_cfg_agc rf_agc, if_agc;
u32 total_gain = 0;
u32 atten = 0;
u32 agc_range = 0;
u16 scu_lvl = 0;
u16 scu_coc = 0;
/* FIXME: those are part of the tuner presets */
u16 tuner_rf_gain = 50; /* Default value on az6007 driver */
u16 tuner_if_gain = 40; /* Default value on az6007 driver */
*strength = 0;
if (is_dvbt(state)) {
rf_agc = state->m_dvbt_rf_agc_cfg;
if_agc = state->m_dvbt_if_agc_cfg;
} else if (is_qam(state)) {
rf_agc = state->m_qam_rf_agc_cfg;
if_agc = state->m_qam_if_agc_cfg;
} else {
rf_agc = state->m_atv_rf_agc_cfg;
if_agc = state->m_atv_if_agc_cfg;
}
if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
/* SCU output_level */
status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
if (status < 0)
return status;
/* SCU c.o.c. */
status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
if (status < 0)
return status;
if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
rf_agc.output_level = scu_lvl + scu_coc;
else
rf_agc.output_level = 0xffff;
/* Take RF gain into account */
total_gain += tuner_rf_gain;
/* clip output value */
if (rf_agc.output_level < rf_agc.min_output_level)
rf_agc.output_level = rf_agc.min_output_level;
if (rf_agc.output_level > rf_agc.max_output_level)
rf_agc.output_level = rf_agc.max_output_level;
agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
if (agc_range > 0) {
atten += 100UL *
((u32)(tuner_rf_gain)) *
((u32)(rf_agc.output_level - rf_agc.min_output_level))
/ agc_range;
}
}
if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
&if_agc.output_level);
if (status < 0)
return status;
status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
&if_agc.top);
if (status < 0)
return status;
/* Take IF gain into account */
total_gain += (u32) tuner_if_gain;
/* clip output value */
if (if_agc.output_level < if_agc.min_output_level)
if_agc.output_level = if_agc.min_output_level;
if (if_agc.output_level > if_agc.max_output_level)
if_agc.output_level = if_agc.max_output_level;
agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
if (agc_range > 0) {
atten += 100UL *
((u32)(tuner_if_gain)) *
((u32)(if_agc.output_level - if_agc.min_output_level))
/ agc_range;
}
}
/*
* Convert to 0..65535 scale.
* If it can't be measured (AGC is disabled), just show 100%.
*/
if (total_gain > 0)
*strength = (65535UL * atten / total_gain / 100);
else
*strength = 65535;
return 0;
}
static int drxk_get_stats(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct drxk_state *state = fe->demodulator_priv;
int status;
u32 stat;
u16 reg16;
u32 post_bit_count;
u32 post_bit_err_count;
u32 post_bit_error_scale;
u32 pre_bit_err_count;
u32 pre_bit_count;
u32 pkt_count;
u32 pkt_error_count;
s32 cnr;
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
/* get status */
state->fe_status = 0;
get_lock_status(state, &stat);
if (stat == MPEG_LOCK)
state->fe_status |= 0x1f;
if (stat == FEC_LOCK)
state->fe_status |= 0x0f;
if (stat == DEMOD_LOCK)
state->fe_status |= 0x07;
/*
* Estimate signal strength from AGC
*/
get_strength(state, &c->strength.stat[0].uvalue);
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
if (stat >= DEMOD_LOCK) {
get_signal_to_noise(state, &cnr);
c->cnr.stat[0].svalue = cnr * 100;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
if (stat < FEC_LOCK) {
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
/* Get post BER */
/* BER measurement is valid if at least FEC lock is achieved */
/*
* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
* written to set nr of symbols or bits over which to measure
* EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
*/
/* Read registers for post/preViterbi BER calculation */
status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
if (status < 0)
goto error;
pre_bit_err_count = reg16;
status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
if (status < 0)
goto error;
pre_bit_count = reg16;
/* Number of bit-errors */
status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
if (status < 0)
goto error;
post_bit_err_count = reg16;
status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
if (status < 0)
goto error;
post_bit_error_scale = reg16;
status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
if (status < 0)
goto error;
pkt_count = reg16;
status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
if (status < 0)
goto error;
pkt_error_count = reg16;
write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
post_bit_err_count *= post_bit_error_scale;
post_bit_count = pkt_count * 204 * 8;
/* Store the results */
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += pkt_error_count;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += pkt_count;
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_count.stat[0].uvalue += pre_bit_count;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += post_bit_err_count;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += post_bit_count;
error:
return status;
}
static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct drxk_state *state = fe->demodulator_priv;
int rc;
dprintk(1, "\n");
rc = drxk_get_stats(fe);
if (rc < 0)
return rc;
*status = state->fe_status;
return 0;
}
static int drxk_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
struct drxk_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
*strength = c->strength.stat[0].uvalue;
return 0;
}
static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct drxk_state *state = fe->demodulator_priv;
s32 snr2;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
get_signal_to_noise(state, &snr2);
/* No negative SNR, clip to zero */
if (snr2 < 0)
snr2 = 0;
*snr = snr2 & 0xffff;
return 0;
}
static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct drxk_state *state = fe->demodulator_priv;
u16 err = 0;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
dvbtqam_get_acc_pkt_err(state, &err);
*ucblocks = (u32) err;
return 0;
}
static int drxk_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *sets)
{
struct drxk_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dprintk(1, "\n");
if (state->m_drxk_state == DRXK_NO_DEV)
return -ENODEV;
if (state->m_drxk_state == DRXK_UNINITIALIZED)
return -EAGAIN;
switch (p->delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_C:
case SYS_DVBT:
sets->min_delay_ms = 3000;
sets->max_drift = 0;
sets->step_size = 0;
return 0;
default:
return -EINVAL;
}
}
static const struct dvb_frontend_ops drxk_ops = {
/* .delsys will be filled dynamically */
.info = {
.name = "DRXK",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 865 * MHz,
/* For DVB-C */
.symbol_rate_min = 870000,
.symbol_rate_max = 11700000,
/* For DVB-T */
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
},
.release = drxk_release,
.sleep = drxk_sleep,
.i2c_gate_ctrl = drxk_gate_ctrl,
.set_frontend = drxk_set_parameters,
.get_tune_settings = drxk_get_tune_settings,
.read_status = drxk_read_status,
.read_signal_strength = drxk_read_signal_strength,
.read_snr = drxk_read_snr,
.read_ucblocks = drxk_read_ucblocks,
};
struct dvb_frontend *drxk_attach(const struct drxk_config *config,
struct i2c_adapter *i2c)
{
struct dtv_frontend_properties *p;
struct drxk_state *state = NULL;
u8 adr = config->adr;
int status;
dprintk(1, "\n");
state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
if (!state)
return NULL;
state->i2c = i2c;
state->demod_address = adr;
state->single_master = config->single_master;
state->microcode_name = config->microcode_name;
state->qam_demod_parameter_count = config->qam_demod_parameter_count;
state->no_i2c_bridge = config->no_i2c_bridge;
state->antenna_gpio = config->antenna_gpio;
state->antenna_dvbt = config->antenna_dvbt;
state->m_chunk_size = config->chunk_size;
state->enable_merr_cfg = config->enable_merr_cfg;
if (config->dynamic_clk) {
state->m_dvbt_static_clk = false;
state->m_dvbc_static_clk = false;
} else {
state->m_dvbt_static_clk = true;
state->m_dvbc_static_clk = true;
}
if (config->mpeg_out_clk_strength)
state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
else
state->m_ts_clockk_strength = 0x06;
if (config->parallel_ts)
state->m_enable_parallel = true;
else
state->m_enable_parallel = false;
/* NOTE: as more UIO bits will be used, add them to the mask */
state->uio_mask = config->antenna_gpio;
/* Default gpio to DVB-C */
if (!state->antenna_dvbt && state->antenna_gpio)
state->m_gpio |= state->antenna_gpio;
else
state->m_gpio &= ~state->antenna_gpio;
mutex_init(&state->mutex);
memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
state->frontend.demodulator_priv = state;
init_state(state);
/* Load firmware and initialize DRX-K */
if (state->microcode_name) {
const struct firmware *fw = NULL;
status = request_firmware(&fw, state->microcode_name,
state->i2c->dev.parent);
if (status < 0)
fw = NULL;
load_firmware_cb(fw, state);
} else if (init_drxk(state) < 0)
goto error;
/* Initialize stats */
p = &state->frontend.dtv_property_cache;
p->strength.len = 1;
p->cnr.len = 1;
p->block_error.len = 1;
p->block_count.len = 1;
p->pre_bit_error.len = 1;
p->pre_bit_count.len = 1;
p->post_bit_error.len = 1;
p->post_bit_count.len = 1;
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_info("frontend initialized.\n");
return &state->frontend;
error:
pr_err("not found\n");
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(drxk_attach);
MODULE_DESCRIPTION("DRX-K driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/drxk_hard.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* DVB compliant Linux driver for the DVB-S si2109/2110 demodulator
*
* Copyright (C) 2008 Igor M. Liplianin ([email protected])
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "si21xx.h"
#define REVISION_REG 0x00
#define SYSTEM_MODE_REG 0x01
#define TS_CTRL_REG_1 0x02
#define TS_CTRL_REG_2 0x03
#define PIN_CTRL_REG_1 0x04
#define PIN_CTRL_REG_2 0x05
#define LOCK_STATUS_REG_1 0x0f
#define LOCK_STATUS_REG_2 0x10
#define ACQ_STATUS_REG 0x11
#define ACQ_CTRL_REG_1 0x13
#define ACQ_CTRL_REG_2 0x14
#define PLL_DIVISOR_REG 0x15
#define COARSE_TUNE_REG 0x16
#define FINE_TUNE_REG_L 0x17
#define FINE_TUNE_REG_H 0x18
#define ANALOG_AGC_POWER_LEVEL_REG 0x28
#define CFO_ESTIMATOR_CTRL_REG_1 0x29
#define CFO_ESTIMATOR_CTRL_REG_2 0x2a
#define CFO_ESTIMATOR_CTRL_REG_3 0x2b
#define SYM_RATE_ESTIMATE_REG_L 0x31
#define SYM_RATE_ESTIMATE_REG_M 0x32
#define SYM_RATE_ESTIMATE_REG_H 0x33
#define CFO_ESTIMATOR_OFFSET_REG_L 0x36
#define CFO_ESTIMATOR_OFFSET_REG_H 0x37
#define CFO_ERROR_REG_L 0x38
#define CFO_ERROR_REG_H 0x39
#define SYM_RATE_ESTIMATOR_CTRL_REG 0x3a
#define SYM_RATE_REG_L 0x3f
#define SYM_RATE_REG_M 0x40
#define SYM_RATE_REG_H 0x41
#define SYM_RATE_ESTIMATOR_MAXIMUM_REG 0x42
#define SYM_RATE_ESTIMATOR_MINIMUM_REG 0x43
#define C_N_ESTIMATOR_CTRL_REG 0x7c
#define C_N_ESTIMATOR_THRSHLD_REG 0x7d
#define C_N_ESTIMATOR_LEVEL_REG_L 0x7e
#define C_N_ESTIMATOR_LEVEL_REG_H 0x7f
#define BLIND_SCAN_CTRL_REG 0x80
#define LSA_CTRL_REG_1 0x8D
#define SPCTRM_TILT_CORR_THRSHLD_REG 0x8f
#define ONE_DB_BNDWDTH_THRSHLD_REG 0x90
#define TWO_DB_BNDWDTH_THRSHLD_REG 0x91
#define THREE_DB_BNDWDTH_THRSHLD_REG 0x92
#define INBAND_POWER_THRSHLD_REG 0x93
#define REF_NOISE_LVL_MRGN_THRSHLD_REG 0x94
#define VIT_SRCH_CTRL_REG_1 0xa0
#define VIT_SRCH_CTRL_REG_2 0xa1
#define VIT_SRCH_CTRL_REG_3 0xa2
#define VIT_SRCH_STATUS_REG 0xa3
#define VITERBI_BER_COUNT_REG_L 0xab
#define REED_SOLOMON_CTRL_REG 0xb0
#define REED_SOLOMON_ERROR_COUNT_REG_L 0xb1
#define PRBS_CTRL_REG 0xb5
#define LNB_CTRL_REG_1 0xc0
#define LNB_CTRL_REG_2 0xc1
#define LNB_CTRL_REG_3 0xc2
#define LNB_CTRL_REG_4 0xc3
#define LNB_CTRL_STATUS_REG 0xc4
#define LNB_FIFO_REGS_0 0xc5
#define LNB_FIFO_REGS_1 0xc6
#define LNB_FIFO_REGS_2 0xc7
#define LNB_FIFO_REGS_3 0xc8
#define LNB_FIFO_REGS_4 0xc9
#define LNB_FIFO_REGS_5 0xca
#define LNB_SUPPLY_CTRL_REG_1 0xcb
#define LNB_SUPPLY_CTRL_REG_2 0xcc
#define LNB_SUPPLY_CTRL_REG_3 0xcd
#define LNB_SUPPLY_CTRL_REG_4 0xce
#define LNB_SUPPLY_STATUS_REG 0xcf
#define FAIL -1
#define PASS 0
#define ALLOWABLE_FS_COUNT 10
#define STATUS_BER 0
#define STATUS_UCBLOCKS 1
static int debug;
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "si21xx: " args); \
} while (0)
enum {
ACTIVE_HIGH,
ACTIVE_LOW
};
enum {
BYTE_WIDE,
BIT_WIDE
};
enum {
CLK_GAPPED_MODE,
CLK_CONTINUOUS_MODE
};
enum {
RISING_EDGE,
FALLING_EDGE
};
enum {
MSB_FIRST,
LSB_FIRST
};
enum {
SERIAL,
PARALLEL
};
struct si21xx_state {
struct i2c_adapter *i2c;
const struct si21xx_config *config;
struct dvb_frontend frontend;
u8 initialised:1;
int errmode;
int fs; /*Sampling rate of the ADC in MHz*/
};
/* register default initialization */
static u8 serit_sp1511lhb_inittab[] = {
0x01, 0x28, /* set i2c_inc_disable */
0x20, 0x03,
0x27, 0x20,
0xe0, 0x45,
0xe1, 0x08,
0xfe, 0x01,
0x01, 0x28,
0x89, 0x09,
0x04, 0x80,
0x05, 0x01,
0x06, 0x00,
0x20, 0x03,
0x24, 0x88,
0x29, 0x09,
0x2a, 0x0f,
0x2c, 0x10,
0x2d, 0x19,
0x2e, 0x08,
0x2f, 0x10,
0x30, 0x19,
0x34, 0x20,
0x35, 0x03,
0x45, 0x02,
0x46, 0x45,
0x47, 0xd0,
0x48, 0x00,
0x49, 0x40,
0x4a, 0x03,
0x4c, 0xfd,
0x4f, 0x2e,
0x50, 0x2e,
0x51, 0x10,
0x52, 0x10,
0x56, 0x92,
0x59, 0x00,
0x5a, 0x2d,
0x5b, 0x33,
0x5c, 0x1f,
0x5f, 0x76,
0x62, 0xc0,
0x63, 0xc0,
0x64, 0xf3,
0x65, 0xf3,
0x79, 0x40,
0x6a, 0x40,
0x6b, 0x0a,
0x6c, 0x80,
0x6d, 0x27,
0x71, 0x06,
0x75, 0x60,
0x78, 0x00,
0x79, 0xb5,
0x7c, 0x05,
0x7d, 0x1a,
0x87, 0x55,
0x88, 0x72,
0x8f, 0x08,
0x90, 0xe0,
0x94, 0x40,
0xa0, 0x3f,
0xa1, 0xc0,
0xa4, 0xcc,
0xa5, 0x66,
0xa6, 0x66,
0xa7, 0x7b,
0xa8, 0x7b,
0xa9, 0x7b,
0xaa, 0x9a,
0xed, 0x04,
0xad, 0x00,
0xae, 0x03,
0xcc, 0xab,
0x01, 0x08,
0xff, 0xff
};
/* low level read/writes */
static int si21_writeregs(struct si21xx_state *state, u8 reg1,
u8 *data, int len)
{
int ret;
u8 buf[60];/* = { reg1, data };*/
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = len + 1
};
if (len > sizeof(buf) - 1)
return -EINVAL;
msg.buf[0] = reg1;
memcpy(msg.buf + 1, data, len);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: writereg error (reg1 == 0x%02x, data == 0x%02x, ret == %i)\n",
__func__, reg1, data[0], ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int si21_writereg(struct si21xx_state *state, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: writereg error (reg == 0x%02x, data == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int si21_write(struct dvb_frontend *fe, const u8 buf[], int len)
{
struct si21xx_state *state = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return si21_writereg(state, buf[0], buf[1]);
}
static u8 si21_readreg(struct si21xx_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return b1[0];
}
static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len)
{
int ret;
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = ®1,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b,
.len = len
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
dprintk("%s: readreg error (ret == %i)\n", __func__, ret);
return ret == 2 ? 0 : -1;
}
static int si21xx_wait_diseqc_idle(struct si21xx_state *state, int timeout)
{
unsigned long start = jiffies;
dprintk("%s\n", __func__);
while ((si21_readreg(state, LNB_CTRL_REG_1) & 0x8) == 8) {
if (time_is_before_jiffies(start + timeout)) {
dprintk("%s: timeout!!\n", __func__);
return -ETIMEDOUT;
}
msleep(10);
}
return 0;
}
static int si21xx_set_symbolrate(struct dvb_frontend *fe, u32 srate)
{
struct si21xx_state *state = fe->demodulator_priv;
u32 sym_rate, data_rate;
int i;
u8 sym_rate_bytes[3];
dprintk("%s : srate = %i\n", __func__ , srate);
if ((srate < 1000000) || (srate > 45000000))
return -EINVAL;
data_rate = srate;
sym_rate = 0;
for (i = 0; i < 4; ++i) {
sym_rate /= 100;
sym_rate = sym_rate + ((data_rate % 100) * 0x800000) /
state->fs;
data_rate /= 100;
}
for (i = 0; i < 3; ++i)
sym_rate_bytes[i] = (u8)((sym_rate >> (i * 8)) & 0xff);
si21_writeregs(state, SYM_RATE_REG_L, sym_rate_bytes, 0x03);
return 0;
}
static int si21xx_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *m)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 lnb_status;
u8 LNB_CTRL_1;
int status;
dprintk("%s\n", __func__);
status = PASS;
LNB_CTRL_1 = 0;
status |= si21_readregs(state, LNB_CTRL_STATUS_REG, &lnb_status, 0x01);
status |= si21_readregs(state, LNB_CTRL_REG_1, &lnb_status, 0x01);
/*fill the FIFO*/
status |= si21_writeregs(state, LNB_FIFO_REGS_0, m->msg, m->msg_len);
LNB_CTRL_1 = (lnb_status & 0x70);
LNB_CTRL_1 |= m->msg_len;
LNB_CTRL_1 |= 0x80; /* begin LNB signaling */
status |= si21_writeregs(state, LNB_CTRL_REG_1, &LNB_CTRL_1, 0x01);
return status;
}
static int si21xx_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 val;
dprintk("%s\n", __func__);
if (si21xx_wait_diseqc_idle(state, 100) < 0)
return -ETIMEDOUT;
val = (0x80 | si21_readreg(state, 0xc1));
if (si21_writereg(state, LNB_CTRL_REG_1,
burst == SEC_MINI_A ? (val & ~0x10) : (val | 0x10)))
return -EREMOTEIO;
if (si21xx_wait_diseqc_idle(state, 100) < 0)
return -ETIMEDOUT;
if (si21_writereg(state, LNB_CTRL_REG_1, val))
return -EREMOTEIO;
return 0;
}
/* 30.06.2008 */
static int si21xx_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 val;
dprintk("%s\n", __func__);
val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1));
switch (tone) {
case SEC_TONE_ON:
return si21_writereg(state, LNB_CTRL_REG_1, val | 0x20);
case SEC_TONE_OFF:
return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x20));
default:
return -EINVAL;
}
}
static int si21xx_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage volt)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 val;
dprintk("%s: %s\n", __func__,
volt == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
volt == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1));
switch (volt) {
case SEC_VOLTAGE_18:
return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40);
case SEC_VOLTAGE_13:
return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40));
default:
return -EINVAL;
}
}
static int si21xx_init(struct dvb_frontend *fe)
{
struct si21xx_state *state = fe->demodulator_priv;
int i;
int status = 0;
u8 reg1;
u8 val;
u8 reg2[2];
dprintk("%s\n", __func__);
for (i = 0; ; i += 2) {
reg1 = serit_sp1511lhb_inittab[i];
val = serit_sp1511lhb_inittab[i+1];
if (reg1 == 0xff && val == 0xff)
break;
si21_writeregs(state, reg1, &val, 1);
}
/*DVB QPSK SYSTEM MODE REG*/
reg1 = 0x08;
si21_writeregs(state, SYSTEM_MODE_REG, ®1, 0x01);
/*transport stream config*/
/*
mode = PARALLEL;
sdata_form = LSB_FIRST;
clk_edge = FALLING_EDGE;
clk_mode = CLK_GAPPED_MODE;
strt_len = BYTE_WIDE;
sync_pol = ACTIVE_HIGH;
val_pol = ACTIVE_HIGH;
err_pol = ACTIVE_HIGH;
sclk_rate = 0x00;
parity = 0x00 ;
data_delay = 0x00;
clk_delay = 0x00;
pclk_smooth = 0x00;
*/
reg2[0] =
PARALLEL + (LSB_FIRST << 1)
+ (FALLING_EDGE << 2) + (CLK_GAPPED_MODE << 3)
+ (BYTE_WIDE << 4) + (ACTIVE_HIGH << 5)
+ (ACTIVE_HIGH << 6) + (ACTIVE_HIGH << 7);
reg2[1] = 0;
/* sclk_rate + (parity << 2)
+ (data_delay << 3) + (clk_delay << 4)
+ (pclk_smooth << 5);
*/
status |= si21_writeregs(state, TS_CTRL_REG_1, reg2, 0x02);
if (status != 0)
dprintk(" %s : TS Set Error\n", __func__);
return 0;
}
static int si21_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 regs_read[2];
u8 reg_read;
u8 i;
u8 lock;
u8 signal = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG);
si21_readregs(state, LOCK_STATUS_REG_1, regs_read, 0x02);
reg_read = 0;
for (i = 0; i < 7; ++i)
reg_read |= ((regs_read[0] >> i) & 0x01) << (6 - i);
lock = ((reg_read & 0x7f) | (regs_read[1] & 0x80));
dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, lock);
*status = 0;
if (signal > 10)
*status |= FE_HAS_SIGNAL;
if (lock & 0x2)
*status |= FE_HAS_CARRIER;
if (lock & 0x20)
*status |= FE_HAS_VITERBI;
if (lock & 0x40)
*status |= FE_HAS_SYNC;
if ((lock & 0x7b) == 0x7b)
*status |= FE_HAS_LOCK;
return 0;
}
static int si21_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct si21xx_state *state = fe->demodulator_priv;
/*status = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG,
(u8*)agclevel, 0x01);*/
u16 signal = (3 * si21_readreg(state, 0x27) *
si21_readreg(state, 0x28));
dprintk("%s : AGCPWR: 0x%02x%02x, signal=0x%04x\n", __func__,
si21_readreg(state, 0x27),
si21_readreg(state, 0x28), (int) signal);
signal <<= 4;
*strength = signal;
return 0;
}
static int si21_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct si21xx_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (state->errmode != STATUS_BER)
return 0;
*ber = (si21_readreg(state, 0x1d) << 8) |
si21_readreg(state, 0x1e);
return 0;
}
static int si21_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct si21xx_state *state = fe->demodulator_priv;
s32 xsnr = 0xffff - ((si21_readreg(state, 0x24) << 8) |
si21_readreg(state, 0x25));
xsnr = 3 * (xsnr - 0xa100);
*snr = (xsnr > 0xffff) ? 0xffff : (xsnr < 0) ? 0 : xsnr;
dprintk("%s\n", __func__);
return 0;
}
static int si21_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct si21xx_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (state->errmode != STATUS_UCBLOCKS)
*ucblocks = 0;
else
*ucblocks = (si21_readreg(state, 0x1d) << 8) |
si21_readreg(state, 0x1e);
return 0;
}
/* initiates a channel acquisition sequence
using the specified symbol rate and code rate */
static int si21xx_setacquire(struct dvb_frontend *fe, int symbrate,
enum fe_code_rate crate)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 coderates[] = {
0x0, 0x01, 0x02, 0x04, 0x00,
0x8, 0x10, 0x20, 0x00, 0x3f
};
u8 coderate_ptr;
int status;
u8 start_acq = 0x80;
u8 reg, regs[3];
dprintk("%s\n", __func__);
status = PASS;
coderate_ptr = coderates[crate];
si21xx_set_symbolrate(fe, symbrate);
/* write code rates to use in the Viterbi search */
status |= si21_writeregs(state,
VIT_SRCH_CTRL_REG_1,
&coderate_ptr, 0x01);
/* clear acq_start bit */
status |= si21_readregs(state, ACQ_CTRL_REG_2, ®, 0x01);
reg &= ~start_acq;
status |= si21_writeregs(state, ACQ_CTRL_REG_2, ®, 0x01);
/* use new Carrier Frequency Offset Estimator (QuickLock) */
regs[0] = 0xCB;
regs[1] = 0x40;
regs[2] = 0xCB;
status |= si21_writeregs(state,
TWO_DB_BNDWDTH_THRSHLD_REG,
®s[0], 0x03);
reg = 0x56;
status |= si21_writeregs(state,
LSA_CTRL_REG_1, ®, 1);
reg = 0x05;
status |= si21_writeregs(state,
BLIND_SCAN_CTRL_REG, ®, 1);
/* start automatic acq */
status |= si21_writeregs(state,
ACQ_CTRL_REG_2, &start_acq, 0x01);
return status;
}
static int si21xx_set_frontend(struct dvb_frontend *fe)
{
struct si21xx_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
/* freq Channel carrier frequency in KHz (i.e. 1550000 KHz)
datarate Channel symbol rate in Sps (i.e. 22500000 Sps)*/
/* in MHz */
unsigned char coarse_tune_freq;
int fine_tune_freq;
unsigned char sample_rate = 0;
/* boolean */
bool inband_interferer_ind;
/* INTERMEDIATE VALUES */
int icoarse_tune_freq; /* MHz */
int ifine_tune_freq; /* MHz */
unsigned int band_high;
unsigned int band_low;
unsigned int x1;
unsigned int x2;
int i;
bool inband_interferer_div2[ALLOWABLE_FS_COUNT];
bool inband_interferer_div4[ALLOWABLE_FS_COUNT];
int status = 0;
/* allowable sample rates for ADC in MHz */
int afs[ALLOWABLE_FS_COUNT] = { 200, 192, 193, 194, 195,
196, 204, 205, 206, 207
};
/* in MHz */
int if_limit_high;
int if_limit_low;
int lnb_lo;
int lnb_uncertanity;
int rf_freq;
int data_rate;
unsigned char regs[4];
dprintk("%s : FE_SET_FRONTEND\n", __func__);
if (c->delivery_system != SYS_DVBS) {
dprintk("%s: unsupported delivery system selected (%d)\n",
__func__, c->delivery_system);
return -EOPNOTSUPP;
}
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i)
inband_interferer_div2[i] = inband_interferer_div4[i] = false;
if_limit_high = -700000;
if_limit_low = -100000;
/* in MHz */
lnb_lo = 0;
lnb_uncertanity = 0;
rf_freq = 10 * c->frequency ;
data_rate = c->symbol_rate / 100;
band_low = (rf_freq - lnb_lo) - ((lnb_uncertanity * 200)
+ (data_rate * 135)) / 200;
band_high = (rf_freq - lnb_lo) + ((lnb_uncertanity * 200)
+ (data_rate * 135)) / 200;
icoarse_tune_freq = 100000 *
(((rf_freq - lnb_lo) -
(if_limit_low + if_limit_high) / 2)
/ 100000);
ifine_tune_freq = (rf_freq - lnb_lo) - icoarse_tune_freq ;
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
x1 = ((rf_freq - lnb_lo) / (afs[i] * 2500)) *
(afs[i] * 2500) + afs[i] * 2500;
x2 = ((rf_freq - lnb_lo) / (afs[i] * 2500)) *
(afs[i] * 2500);
if (((band_low < x1) && (x1 < band_high)) ||
((band_low < x2) && (x2 < band_high)))
inband_interferer_div4[i] = true;
}
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
x1 = ((rf_freq - lnb_lo) / (afs[i] * 5000)) *
(afs[i] * 5000) + afs[i] * 5000;
x2 = ((rf_freq - lnb_lo) / (afs[i] * 5000)) *
(afs[i] * 5000);
if (((band_low < x1) && (x1 < band_high)) ||
((band_low < x2) && (x2 < band_high)))
inband_interferer_div2[i] = true;
}
inband_interferer_ind = true;
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
if (inband_interferer_div2[i] || inband_interferer_div4[i]) {
inband_interferer_ind = false;
break;
}
}
if (inband_interferer_ind) {
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
if (!inband_interferer_div2[i]) {
sample_rate = (u8) afs[i];
break;
}
}
} else {
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
if ((inband_interferer_div2[i] ||
!inband_interferer_div4[i])) {
sample_rate = (u8) afs[i];
break;
}
}
}
if (sample_rate > 207 || sample_rate < 192)
sample_rate = 200;
fine_tune_freq = ((0x4000 * (ifine_tune_freq / 10)) /
((sample_rate) * 1000));
coarse_tune_freq = (u8)(icoarse_tune_freq / 100000);
regs[0] = sample_rate;
regs[1] = coarse_tune_freq;
regs[2] = fine_tune_freq & 0xFF;
regs[3] = fine_tune_freq >> 8 & 0xFF;
status |= si21_writeregs(state, PLL_DIVISOR_REG, ®s[0], 0x04);
state->fs = sample_rate;/*ADC MHz*/
si21xx_setacquire(fe, c->symbol_rate, c->fec_inner);
if (status)
return -EREMOTEIO;
return 0;
}
static int si21xx_sleep(struct dvb_frontend *fe)
{
struct si21xx_state *state = fe->demodulator_priv;
u8 regdata;
dprintk("%s\n", __func__);
si21_readregs(state, SYSTEM_MODE_REG, ®data, 0x01);
regdata |= 1 << 6;
si21_writeregs(state, SYSTEM_MODE_REG, ®data, 0x01);
state->initialised = 0;
return 0;
}
static void si21xx_release(struct dvb_frontend *fe)
{
struct si21xx_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
kfree(state);
}
static const struct dvb_frontend_ops si21xx_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "SL SI21XX DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500, /* ppm */
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = si21xx_release,
.init = si21xx_init,
.sleep = si21xx_sleep,
.write = si21_write,
.read_status = si21_read_status,
.read_ber = si21_read_ber,
.read_signal_strength = si21_read_signal_strength,
.read_snr = si21_read_snr,
.read_ucblocks = si21_read_ucblocks,
.diseqc_send_master_cmd = si21xx_send_diseqc_msg,
.diseqc_send_burst = si21xx_send_diseqc_burst,
.set_tone = si21xx_set_tone,
.set_voltage = si21xx_set_voltage,
.set_frontend = si21xx_set_frontend,
};
struct dvb_frontend *si21xx_attach(const struct si21xx_config *config,
struct i2c_adapter *i2c)
{
struct si21xx_state *state = NULL;
int id;
dprintk("%s\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct si21xx_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->initialised = 0;
state->errmode = STATUS_BER;
/* check if the demod is there */
id = si21_readreg(state, SYSTEM_MODE_REG);
si21_writereg(state, SYSTEM_MODE_REG, id | 0x40); /* standby off */
msleep(200);
id = si21_readreg(state, 0x00);
/* register 0x00 contains:
0x34 for SI2107
0x24 for SI2108
0x14 for SI2109
0x04 for SI2110
*/
if (id != 0x04 && id != 0x14)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &si21xx_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(si21xx_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("SL SI21XX DVB Demodulator driver");
MODULE_AUTHOR("Igor M. Liplianin");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/si21xx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Infineon tua6100 pll.
*
* (c) 2006 Andrew de Quincey
*
* Based on code found in budget-av.c, which has the following:
* Compiled from various sources by Michael Hunold <[email protected]>
*
* CI interface support (c) 2004 Olivier Gournet <[email protected]> &
* Andrew de Quincey <[email protected]>
*
* Copyright (C) 2002 Ralph Metzler <[email protected]>
*
* Copyright (C) 1999-2002 Ralph Metzler
* & Marcus Metzler for convergence integrated media GmbH
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <asm/types.h>
#include "tua6100.h"
struct tua6100_priv {
/* i2c details */
int i2c_address;
struct i2c_adapter *i2c;
u32 frequency;
};
static void tua6100_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int tua6100_sleep(struct dvb_frontend *fe)
{
struct tua6100_priv *priv = fe->tuner_priv;
int ret;
u8 reg0[] = { 0x00, 0x00 };
struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if ((ret = i2c_transfer (priv->i2c, &msg, 1)) != 1) {
printk("%s: i2c error\n", __func__);
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return (ret == 1) ? 0 : ret;
}
static int tua6100_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tua6100_priv *priv = fe->tuner_priv;
u32 div;
u32 prediv;
u8 reg0[] = { 0x00, 0x00 };
u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 };
u8 reg2[] = { 0x02, 0x00, 0x00 };
struct i2c_msg msg0 = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 };
struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 };
#define _R_VAL 4
#define _P_VAL 32
#define _ri 4000000
// setup register 0
if (c->frequency < 2000000)
reg0[1] = 0x03;
else
reg0[1] = 0x07;
// setup register 1
if (c->frequency < 1630000)
reg1[1] = 0x2c;
else
reg1[1] = 0x0c;
if (_P_VAL == 64)
reg1[1] |= 0x40;
if (c->frequency >= 1525000)
reg1[1] |= 0x80;
// register 2
reg2[1] = (_R_VAL >> 8) & 0x03;
reg2[2] = _R_VAL;
if (c->frequency < 1455000)
reg2[1] |= 0x1c;
else if (c->frequency < 1630000)
reg2[1] |= 0x0c;
else
reg2[1] |= 0x1c;
/*
* The N divisor ratio (note: c->frequency is in kHz, but we
* need it in Hz)
*/
prediv = (c->frequency * _R_VAL) / (_ri / 1000);
div = prediv / _P_VAL;
reg1[1] |= (div >> 9) & 0x03;
reg1[2] = div >> 1;
reg1[3] = (div << 7);
priv->frequency = ((div * _P_VAL) * (_ri / 1000)) / _R_VAL;
// Finally, calculate and store the value for A
reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f;
#undef _R_VAL
#undef _P_VAL
#undef _ri
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(priv->i2c, &msg0, 1) != 1)
return -EIO;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(priv->i2c, &msg2, 1) != 1)
return -EIO;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(priv->i2c, &msg1, 1) != 1)
return -EIO;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int tua6100_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tua6100_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static const struct dvb_tuner_ops tua6100_tuner_ops = {
.info = {
.name = "Infineon TUA6100",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_step_hz = 1 * MHz,
},
.release = tua6100_release,
.sleep = tua6100_sleep,
.set_params = tua6100_set_params,
.get_frequency = tua6100_get_frequency,
};
struct dvb_frontend *tua6100_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c)
{
struct tua6100_priv *priv = NULL;
u8 b1 [] = { 0x80 };
u8 b2 [] = { 0x00 };
struct i2c_msg msg [] = { { .addr = addr, .flags = 0, .buf = b1, .len = 1 },
{ .addr = addr, .flags = I2C_M_RD, .buf = b2, .len = 1 } };
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer (i2c, msg, 2);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret != 2)
return NULL;
priv = kzalloc(sizeof(struct tua6100_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = addr;
priv->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &tua6100_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
}
EXPORT_SYMBOL_GPL(tua6100_attach);
MODULE_DESCRIPTION("DVB tua6100 driver");
MODULE_AUTHOR("Andrew de Quincey");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tua6100.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* stv0900_sw.c
*
* Driver for ST STV0900 satellite demodulator IC.
*
* Copyright (C) ST Microelectronics.
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
*/
#include "stv0900.h"
#include "stv0900_reg.h"
#include "stv0900_priv.h"
s32 shiftx(s32 x, int demod, s32 shift)
{
if (demod == 1)
return x - shift;
return x;
}
int stv0900_check_signal_presence(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 carr_offset,
agc2_integr,
max_carrier;
int no_signal = FALSE;
carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
| stv0900_read_reg(intp, CFR1);
carr_offset = ge2comp(carr_offset, 16);
agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
max_carrier = intp->srch_range[demod] / 1000;
max_carrier += (max_carrier / 10);
max_carrier = 65536 * (max_carrier / 2);
max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
if ((agc2_integr > 0x2000)
|| (carr_offset > (2 * max_carrier))
|| (carr_offset < (-2 * max_carrier)))
no_signal = TRUE;
return no_signal;
}
static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
s32 *frequency_inc, s32 *sw_timeout,
s32 *steps,
enum fe_stv0900_demod_num demod)
{
s32 timeout, freq_inc, max_steps, srate, max_carrier;
enum fe_stv0900_search_standard standard;
srate = intp->symbol_rate[demod];
max_carrier = intp->srch_range[demod] / 1000;
max_carrier += max_carrier / 10;
standard = intp->srch_standard[demod];
max_carrier = 65536 * (max_carrier / 2);
max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
freq_inc = srate;
freq_inc /= intp->mclk >> 10;
freq_inc = freq_inc << 6;
switch (standard) {
case STV0900_SEARCH_DVBS1:
case STV0900_SEARCH_DSS:
freq_inc *= 3;
timeout = 20;
break;
case STV0900_SEARCH_DVBS2:
freq_inc *= 4;
timeout = 25;
break;
case STV0900_AUTO_SEARCH:
default:
freq_inc *= 3;
timeout = 25;
break;
}
freq_inc /= 100;
if ((freq_inc > max_carrier) || (freq_inc < 0))
freq_inc = max_carrier / 2;
timeout *= 27500;
if (srate > 0)
timeout /= srate / 1000;
if ((timeout > 100) || (timeout < 0))
timeout = 100;
max_steps = (max_carrier / freq_inc) + 1;
if ((max_steps > 100) || (max_steps < 0)) {
max_steps = 100;
freq_inc = max_carrier / max_steps;
}
*frequency_inc = freq_inc;
*sw_timeout = timeout;
*steps = max_steps;
}
static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
s32 FreqIncr, s32 Timeout, int zigzag,
s32 MaxStep, enum fe_stv0900_demod_num demod)
{
int no_signal,
lock = FALSE;
s32 stepCpt,
freqOffset,
max_carrier;
max_carrier = intp->srch_range[demod] / 1000;
max_carrier += (max_carrier / 10);
max_carrier = 65536 * (max_carrier / 2);
max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
if (zigzag == TRUE)
freqOffset = 0;
else
freqOffset = -max_carrier + FreqIncr;
stepCpt = 0;
do {
stv0900_write_reg(intp, DMDISTATE, 0x1c);
stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
stv0900_write_reg(intp, DMDISTATE, 0x18);
stv0900_write_bits(intp, ALGOSWRST, 1);
if (intp->chip_id == 0x12) {
stv0900_write_bits(intp, RST_HWARE, 1);
stv0900_write_bits(intp, RST_HWARE, 0);
}
if (zigzag == TRUE) {
if (freqOffset >= 0)
freqOffset = -freqOffset - 2 * FreqIncr;
else
freqOffset = -freqOffset;
} else
freqOffset += + 2 * FreqIncr;
stepCpt++;
lock = stv0900_get_demod_lock(intp, demod, Timeout);
no_signal = stv0900_check_signal_presence(intp, demod);
} while ((lock == FALSE)
&& (no_signal == FALSE)
&& ((freqOffset - FreqIncr) < max_carrier)
&& ((freqOffset + FreqIncr) > -max_carrier)
&& (stepCpt < MaxStep));
stv0900_write_bits(intp, ALGOSWRST, 0);
return lock;
}
static int stv0900_sw_algo(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
int lock = FALSE,
no_signal,
zigzag;
s32 s2fw,
fqc_inc,
sft_stp_tout,
trial_cntr,
max_steps;
stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
&max_steps, demod);
switch (intp->srch_standard[demod]) {
case STV0900_SEARCH_DVBS1:
case STV0900_SEARCH_DSS:
if (intp->chip_id >= 0x20)
stv0900_write_reg(intp, CARFREQ, 0x3b);
else
stv0900_write_reg(intp, CARFREQ, 0xef);
stv0900_write_reg(intp, DMDCFGMD, 0x49);
zigzag = FALSE;
break;
case STV0900_SEARCH_DVBS2:
if (intp->chip_id >= 0x20)
stv0900_write_reg(intp, CORRELABS, 0x79);
else
stv0900_write_reg(intp, CORRELABS, 0x68);
stv0900_write_reg(intp, DMDCFGMD, 0x89);
zigzag = TRUE;
break;
case STV0900_AUTO_SEARCH:
default:
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, CARFREQ, 0x3b);
stv0900_write_reg(intp, CORRELABS, 0x79);
} else {
stv0900_write_reg(intp, CARFREQ, 0xef);
stv0900_write_reg(intp, CORRELABS, 0x68);
}
stv0900_write_reg(intp, DMDCFGMD, 0xc9);
zigzag = FALSE;
break;
}
trial_cntr = 0;
do {
lock = stv0900_search_carr_sw_loop(intp,
fqc_inc,
sft_stp_tout,
zigzag,
max_steps,
demod);
no_signal = stv0900_check_signal_presence(intp, demod);
trial_cntr++;
if ((lock == TRUE)
|| (no_signal == TRUE)
|| (trial_cntr == 2)) {
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, CARFREQ, 0x49);
stv0900_write_reg(intp, CORRELABS, 0x9e);
} else {
stv0900_write_reg(intp, CARFREQ, 0xed);
stv0900_write_reg(intp, CORRELABS, 0x88);
}
if ((stv0900_get_bits(intp, HEADER_MODE) ==
STV0900_DVBS2_FOUND) &&
(lock == TRUE)) {
msleep(sft_stp_tout);
s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
if (s2fw < 0xd) {
msleep(sft_stp_tout);
s2fw = stv0900_get_bits(intp,
FLYWHEEL_CPT);
}
if (s2fw < 0xd) {
lock = FALSE;
if (trial_cntr < 2) {
if (intp->chip_id >= 0x20)
stv0900_write_reg(intp,
CORRELABS,
0x79);
else
stv0900_write_reg(intp,
CORRELABS,
0x68);
stv0900_write_reg(intp,
DMDCFGMD,
0x89);
}
}
}
}
} while ((lock == FALSE)
&& (trial_cntr < 2)
&& (no_signal == FALSE));
return lock;
}
static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
u32 mclk,
enum fe_stv0900_demod_num demod)
{
s32 rem1, rem2, intval1, intval2, srate;
srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
(stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
(stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
(stv0900_get_bits(intp, SYMB_FREQ0));
dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
srate, stv0900_get_bits(intp, SYMB_FREQ0),
stv0900_get_bits(intp, SYMB_FREQ1),
stv0900_get_bits(intp, SYMB_FREQ2),
stv0900_get_bits(intp, SYMB_FREQ3));
intval1 = (mclk) >> 16;
intval2 = (srate) >> 16;
rem1 = (mclk) % 0x10000;
rem2 = (srate) % 0x10000;
srate = (intval1 * intval2) +
((intval1 * rem2) >> 16) +
((intval2 * rem1) >> 16);
return srate;
}
static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
u32 symb;
dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
srate, demod);
if (srate > 60000000) {
symb = srate << 4;
symb /= (mclk >> 12);
} else if (srate > 6000000) {
symb = srate << 6;
symb /= (mclk >> 10);
} else {
symb = srate << 9;
symb /= (mclk >> 7);
}
stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
}
static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
u32 symb;
srate = 105 * (srate / 100);
if (srate > 60000000) {
symb = srate << 4;
symb /= (mclk >> 12);
} else if (srate > 6000000) {
symb = srate << 6;
symb /= (mclk >> 10);
} else {
symb = srate << 9;
symb /= (mclk >> 7);
}
if (symb < 0x7fff) {
stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
} else {
stv0900_write_reg(intp, SFRUP1, 0x7f);
stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
}
}
static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
u32 symb;
srate = 95 * (srate / 100);
if (srate > 60000000) {
symb = srate << 4;
symb /= (mclk >> 12);
} else if (srate > 6000000) {
symb = srate << 6;
symb /= (mclk >> 10);
} else {
symb = srate << 9;
symb /= (mclk >> 7);
}
stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
}
static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
u32 srate,
enum fe_stv0900_demod_num demod)
{
s32 timingoffset;
timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
(stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
(stv0900_read_reg(intp, TMGREG2 + 2));
timingoffset = ge2comp(timingoffset, 24);
if (timingoffset == 0)
timingoffset = 1;
timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
timingoffset /= 320;
return timingoffset;
}
static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 rolloff;
if (intp->chip_id == 0x10) {
stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
} else if (intp->chip_id <= 0x20)
stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
else /* cut 3.0 */
stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
}
static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
{
u32 rolloff;
switch (ro) {
case STV0900_20:
rolloff = 20;
break;
case STV0900_25:
rolloff = 25;
break;
case STV0900_35:
default:
rolloff = 35;
break;
}
return srate + (srate * rolloff) / 100;
}
static int stv0900_check_timing_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
int timingLock = FALSE;
s32 i,
timingcpt = 0;
u8 car_freq,
tmg_th_high,
tmg_th_low;
car_freq = stv0900_read_reg(intp, CARFREQ);
tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
stv0900_write_reg(intp, TMGTHRISE, 0x20);
stv0900_write_reg(intp, TMGTHFALL, 0x0);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_reg(intp, RTC, 0x80);
stv0900_write_reg(intp, RTCS2, 0x40);
stv0900_write_reg(intp, CARFREQ, 0x0);
stv0900_write_reg(intp, CFRINIT1, 0x0);
stv0900_write_reg(intp, CFRINIT0, 0x0);
stv0900_write_reg(intp, AGC2REF, 0x65);
stv0900_write_reg(intp, DMDISTATE, 0x18);
msleep(7);
for (i = 0; i < 10; i++) {
if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
timingcpt++;
msleep(1);
}
if (timingcpt >= 3)
timingLock = TRUE;
stv0900_write_reg(intp, AGC2REF, 0x38);
stv0900_write_reg(intp, RTC, 0x88);
stv0900_write_reg(intp, RTCS2, 0x68);
stv0900_write_reg(intp, CARFREQ, car_freq);
stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
return timingLock;
}
static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
s32 demod_timeout)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
int lock = FALSE,
d = demod;
s32 srate,
search_range,
locktimeout,
currier_step,
nb_steps,
current_step,
direction,
tuner_freq,
timeout,
freq;
srate = intp->symbol_rate[d];
search_range = intp->srch_range[d];
if (srate >= 10000000)
locktimeout = demod_timeout / 3;
else
locktimeout = demod_timeout / 2;
lock = stv0900_get_demod_lock(intp, d, locktimeout);
if (lock != FALSE)
return lock;
if (srate >= 10000000) {
if (stv0900_check_timing_lock(intp, d) == TRUE) {
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x15);
lock = stv0900_get_demod_lock(intp, d, demod_timeout);
} else
lock = FALSE;
return lock;
}
if (intp->chip_id <= 0x20) {
if (srate <= 1000000)
currier_step = 500;
else if (srate <= 4000000)
currier_step = 1000;
else if (srate <= 7000000)
currier_step = 2000;
else if (srate <= 10000000)
currier_step = 3000;
else
currier_step = 5000;
if (srate >= 2000000) {
timeout = (demod_timeout / 3);
if (timeout > 1000)
timeout = 1000;
} else
timeout = (demod_timeout / 2);
} else {
/*cut 3.0 */
currier_step = srate / 4000;
timeout = (demod_timeout * 3) / 4;
}
nb_steps = ((search_range / 1000) / currier_step);
if ((nb_steps % 2) != 0)
nb_steps += 1;
if (nb_steps <= 0)
nb_steps = 2;
else if (nb_steps > 12)
nb_steps = 12;
current_step = 1;
direction = 1;
if (intp->chip_id <= 0x20) {
tuner_freq = intp->freq[d];
intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
intp->rolloff) + intp->symbol_rate[d];
} else
tuner_freq = 0;
while ((current_step <= nb_steps) && (lock == FALSE)) {
if (direction > 0)
tuner_freq += (current_step * currier_step);
else
tuner_freq -= (current_step * currier_step);
if (intp->chip_id <= 0x20) {
if (intp->tuner_type[d] == 3)
stv0900_set_tuner_auto(intp, tuner_freq,
intp->bw[d], demod);
else
stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
stv0900_write_reg(intp, DMDISTATE, 0x1c);
stv0900_write_reg(intp, CFRINIT1, 0);
stv0900_write_reg(intp, CFRINIT0, 0);
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x15);
} else {
stv0900_write_reg(intp, DMDISTATE, 0x1c);
freq = (tuner_freq * 65536) / (intp->mclk / 1000);
stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x05);
}
lock = stv0900_get_demod_lock(intp, d, timeout);
direction *= -1;
current_step++;
}
return lock;
}
static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
s32 srate,
enum fe_stv0900_search_algo algo)
{
switch (algo) {
case STV0900_BLIND_SEARCH:
if (srate <= 1500000) {
(*demod_timeout) = 1500;
(*fec_timeout) = 400;
} else if (srate <= 5000000) {
(*demod_timeout) = 1000;
(*fec_timeout) = 300;
} else {
(*demod_timeout) = 700;
(*fec_timeout) = 100;
}
break;
case STV0900_COLD_START:
case STV0900_WARM_START:
default:
if (srate <= 1000000) {
(*demod_timeout) = 3000;
(*fec_timeout) = 1700;
} else if (srate <= 2000000) {
(*demod_timeout) = 2500;
(*fec_timeout) = 1100;
} else if (srate <= 5000000) {
(*demod_timeout) = 1000;
(*fec_timeout) = 550;
} else if (srate <= 10000000) {
(*demod_timeout) = 700;
(*fec_timeout) = 250;
} else if (srate <= 20000000) {
(*demod_timeout) = 400;
(*fec_timeout) = 130;
} else {
(*demod_timeout) = 300;
(*fec_timeout) = 100;
}
break;
}
if (algo == STV0900_WARM_START)
(*demod_timeout) /= 2;
}
static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 vth_reg = VTH12;
dprintk("%s\n", __func__);
stv0900_write_reg(intp, vth_reg++, 0xd0);
stv0900_write_reg(intp, vth_reg++, 0x7d);
stv0900_write_reg(intp, vth_reg++, 0x53);
stv0900_write_reg(intp, vth_reg++, 0x2f);
stv0900_write_reg(intp, vth_reg++, 0x24);
stv0900_write_reg(intp, vth_reg++, 0x1f);
}
static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
enum fe_stv0900_search_standard standard,
enum fe_stv0900_fec fec,
enum fe_stv0900_demod_num demod)
{
dprintk("%s: ViterbiStandard = ", __func__);
switch (standard) {
case STV0900_AUTO_SEARCH:
dprintk("Auto\n");
stv0900_write_reg(intp, FECM, 0x10);
stv0900_write_reg(intp, PRVIT, 0x3f);
break;
case STV0900_SEARCH_DVBS1:
dprintk("DVBS1\n");
stv0900_write_reg(intp, FECM, 0x00);
switch (fec) {
case STV0900_FEC_UNKNOWN:
default:
stv0900_write_reg(intp, PRVIT, 0x2f);
break;
case STV0900_FEC_1_2:
stv0900_write_reg(intp, PRVIT, 0x01);
break;
case STV0900_FEC_2_3:
stv0900_write_reg(intp, PRVIT, 0x02);
break;
case STV0900_FEC_3_4:
stv0900_write_reg(intp, PRVIT, 0x04);
break;
case STV0900_FEC_5_6:
stv0900_write_reg(intp, PRVIT, 0x08);
break;
case STV0900_FEC_7_8:
stv0900_write_reg(intp, PRVIT, 0x20);
break;
}
break;
case STV0900_SEARCH_DSS:
dprintk("DSS\n");
stv0900_write_reg(intp, FECM, 0x80);
switch (fec) {
case STV0900_FEC_UNKNOWN:
default:
stv0900_write_reg(intp, PRVIT, 0x13);
break;
case STV0900_FEC_1_2:
stv0900_write_reg(intp, PRVIT, 0x01);
break;
case STV0900_FEC_2_3:
stv0900_write_reg(intp, PRVIT, 0x02);
break;
case STV0900_FEC_6_7:
stv0900_write_reg(intp, PRVIT, 0x10);
break;
}
break;
default:
break;
}
}
static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_fec prate;
s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
switch (rate_fld) {
case 13:
prate = STV0900_FEC_1_2;
break;
case 18:
prate = STV0900_FEC_2_3;
break;
case 21:
prate = STV0900_FEC_3_4;
break;
case 24:
prate = STV0900_FEC_5_6;
break;
case 25:
prate = STV0900_FEC_6_7;
break;
case 26:
prate = STV0900_FEC_7_8;
break;
default:
prate = STV0900_FEC_UNKNOWN;
break;
}
return prate;
}
static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod,
u32 srate)
{
if (intp->chip_id >= 0x30) {
if (srate >= 15000000) {
stv0900_write_reg(intp, ACLC, 0x2b);
stv0900_write_reg(intp, BCLC, 0x1a);
} else if ((srate >= 7000000) && (15000000 > srate)) {
stv0900_write_reg(intp, ACLC, 0x0c);
stv0900_write_reg(intp, BCLC, 0x1b);
} else if (srate < 7000000) {
stv0900_write_reg(intp, ACLC, 0x2c);
stv0900_write_reg(intp, BCLC, 0x1c);
}
} else { /*cut 2.0 and 1.x*/
stv0900_write_reg(intp, ACLC, 0x1a);
stv0900_write_reg(intp, BCLC, 0x09);
}
}
static void stv0900_track_optimization(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 srate,
pilots,
aclc,
freq1,
freq0,
i = 0,
timed,
timef,
blind_tun_sw = 0,
modulation;
enum fe_stv0900_modcode foundModcod;
dprintk("%s\n", __func__);
srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
srate += stv0900_get_timing_offst(intp, srate, demod);
switch (intp->result[demod].standard) {
case STV0900_DVBS1_STANDARD:
case STV0900_DSS_STANDARD:
dprintk("%s: found DVB-S or DSS\n", __func__);
if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
stv0900_write_bits(intp, DVBS1_ENABLE, 1);
stv0900_write_bits(intp, DVBS2_ENABLE, 0);
}
stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
if (intp->chip_id < 0x30) {
stv0900_write_reg(intp, ERRCTRL1, 0x75);
break;
}
if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
stv0900_write_reg(intp, GAUSSR0, 0x98);
stv0900_write_reg(intp, CCIR0, 0x18);
} else {
stv0900_write_reg(intp, GAUSSR0, 0x18);
stv0900_write_reg(intp, CCIR0, 0x18);
}
stv0900_write_reg(intp, ERRCTRL1, 0x75);
break;
case STV0900_DVBS2_STANDARD:
dprintk("%s: found DVB-S2\n", __func__);
stv0900_write_bits(intp, DVBS1_ENABLE, 0);
stv0900_write_bits(intp, DVBS2_ENABLE, 1);
stv0900_write_reg(intp, ACLC, 0);
stv0900_write_reg(intp, BCLC, 0);
if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
aclc = stv0900_get_optim_carr_loop(srate,
foundModcod,
pilots,
intp->chip_id);
if (foundModcod <= STV0900_QPSK_910)
stv0900_write_reg(intp, ACLC2S2Q, aclc);
else if (foundModcod <= STV0900_8PSK_910) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S28, aclc);
}
if ((intp->demod_mode == STV0900_SINGLE) &&
(foundModcod > STV0900_8PSK_910)) {
if (foundModcod <= STV0900_16APSK_910) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S216A,
aclc);
} else if (foundModcod <= STV0900_32APSK_910) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S232A,
aclc);
}
}
} else {
modulation = intp->result[demod].modulation;
aclc = stv0900_get_optim_short_carr_loop(srate,
modulation, intp->chip_id);
if (modulation == STV0900_QPSK)
stv0900_write_reg(intp, ACLC2S2Q, aclc);
else if (modulation == STV0900_8PSK) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S28, aclc);
} else if (modulation == STV0900_16APSK) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S216A, aclc);
} else if (modulation == STV0900_32APSK) {
stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
stv0900_write_reg(intp, ACLC2S232A, aclc);
}
}
if (intp->chip_id <= 0x11) {
if (intp->demod_mode != STV0900_SINGLE)
stv0900_activate_s2_modcod(intp, demod);
}
stv0900_write_reg(intp, ERRCTRL1, 0x67);
break;
case STV0900_UNKNOWN_STANDARD:
default:
dprintk("%s: found unknown standard\n", __func__);
stv0900_write_bits(intp, DVBS1_ENABLE, 1);
stv0900_write_bits(intp, DVBS2_ENABLE, 1);
break;
}
freq1 = stv0900_read_reg(intp, CFR2);
freq0 = stv0900_read_reg(intp, CFR1);
if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
stv0900_write_reg(intp, SFRSTEP, 0x00);
stv0900_write_bits(intp, SCAN_ENABLE, 0);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_reg(intp, TMGCFG2, 0xc1);
stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
blind_tun_sw = 1;
if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
}
if (intp->chip_id >= 0x20) {
if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
(intp->srch_standard[demod] ==
STV0900_SEARCH_DSS) ||
(intp->srch_standard[demod] ==
STV0900_AUTO_SEARCH)) {
stv0900_write_reg(intp, VAVSRVIT, 0x0a);
stv0900_write_reg(intp, VITSCALE, 0x0);
}
}
if (intp->chip_id < 0x20)
stv0900_write_reg(intp, CARHDR, 0x08);
if (intp->chip_id == 0x10)
stv0900_write_reg(intp, CORRELEXP, 0x0a);
stv0900_write_reg(intp, AGC2REF, 0x38);
if ((intp->chip_id >= 0x20) ||
(blind_tun_sw == 1) ||
(intp->symbol_rate[demod] < 10000000)) {
stv0900_write_reg(intp, CFRINIT1, freq1);
stv0900_write_reg(intp, CFRINIT0, freq0);
intp->bw[demod] = stv0900_carrier_width(srate,
intp->rolloff) + 10000000;
if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
if (intp->srch_algo[demod] != STV0900_WARM_START) {
if (intp->tuner_type[demod] == 3)
stv0900_set_tuner_auto(intp,
intp->freq[demod],
intp->bw[demod],
demod);
else
stv0900_set_bandwidth(fe,
intp->bw[demod]);
}
}
if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
(intp->symbol_rate[demod] < 10000000))
msleep(50);
else
msleep(5);
stv0900_get_lock_timeout(&timed, &timef, srate,
STV0900_WARM_START);
if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, CFRINIT1, freq1);
stv0900_write_reg(intp, CFRINIT0, freq0);
stv0900_write_reg(intp, DMDISTATE, 0x18);
i = 0;
while ((stv0900_get_demod_lock(intp,
demod,
timed / 2) == FALSE) &&
(i <= 2)) {
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, CFRINIT1, freq1);
stv0900_write_reg(intp, CFRINIT0, freq0);
stv0900_write_reg(intp, DMDISTATE, 0x18);
i++;
}
}
}
if (intp->chip_id >= 0x20)
stv0900_write_reg(intp, CARFREQ, 0x49);
if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
(intp->result[demod].standard == STV0900_DSS_STANDARD))
stv0900_set_viterbi_tracq(intp, demod);
}
static int stv0900_get_fec_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod, s32 time_out)
{
s32 timer = 0, lock = 0;
enum fe_stv0900_search_state dmd_state;
dprintk("%s\n", __func__);
dmd_state = stv0900_get_bits(intp, HEADER_MODE);
while ((timer < time_out) && (lock == 0)) {
switch (dmd_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
default:
lock = 0;
break;
case STV0900_DVBS2_FOUND:
lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
break;
case STV0900_DVBS_FOUND:
lock = stv0900_get_bits(intp, LOCKEDVIT);
break;
}
if (lock == 0) {
msleep(10);
timer += 10;
}
}
if (lock)
dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
else
dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
return lock;
}
static int stv0900_wait_for_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod,
s32 dmd_timeout, s32 fec_timeout)
{
s32 timer = 0, lock = 0;
dprintk("%s\n", __func__);
lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
if (lock)
lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
if (lock) {
lock = 0;
dprintk("%s: Timer = %d, time_out = %d\n",
__func__, timer, fec_timeout);
while ((timer < fec_timeout) && (lock == 0)) {
lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
msleep(1);
timer++;
}
}
if (lock)
dprintk("%s: DEMOD LOCK OK\n", __func__);
else
dprintk("%s: DEMOD LOCK FAIL\n", __func__);
if (lock)
return TRUE;
else
return FALSE;
}
enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
enum fe_stv0900_demod_num demod)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_tracking_standard fnd_standard;
int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
switch (hdr_mode) {
case 2:
fnd_standard = STV0900_DVBS2_STANDARD;
break;
case 3:
if (stv0900_get_bits(intp, DSS_DVB) == 1)
fnd_standard = STV0900_DSS_STANDARD;
else
fnd_standard = STV0900_DVBS1_STANDARD;
break;
default:
fnd_standard = STV0900_UNKNOWN_STANDARD;
}
dprintk("%s: standard %d\n", __func__, fnd_standard);
return fnd_standard;
}
static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
enum fe_stv0900_demod_num demod)
{
s32 derot,
rem1,
rem2,
intval1,
intval2;
derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
(stv0900_get_bits(intp, CAR_FREQ1) << 8) +
(stv0900_get_bits(intp, CAR_FREQ0));
derot = ge2comp(derot, 24);
intval1 = mclk >> 12;
intval2 = derot >> 12;
rem1 = mclk % 0x1000;
rem2 = derot % 0x1000;
derot = (intval1 * intval2) +
((intval1 * rem2) >> 12) +
((intval2 * rem1) >> 12);
return derot;
}
static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
{
struct dvb_frontend_ops *frontend_ops = NULL;
struct dvb_tuner_ops *tuner_ops = NULL;
u32 freq = 0;
frontend_ops = &fe->ops;
tuner_ops = &frontend_ops->tuner_ops;
if (tuner_ops->get_frequency) {
if ((tuner_ops->get_frequency(fe, &freq)) < 0)
dprintk("%s: Invalid parameter\n", __func__);
else
dprintk("%s: Frequency=%d\n", __func__, freq);
}
return freq;
}
static enum
fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
struct stv0900_signal_info *result = &intp->result[demod];
s32 offsetFreq,
srate_offset;
int i = 0,
d = demod;
u8 timing;
msleep(5);
if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
timing = stv0900_read_reg(intp, TMGREG2);
i = 0;
stv0900_write_reg(intp, SFRSTEP, 0x5c);
while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
timing = stv0900_read_reg(intp, TMGREG2);
msleep(5);
i += 5;
}
}
result->standard = stv0900_get_standard(fe, d);
if (intp->tuner_type[demod] == 3)
result->frequency = stv0900_get_freq_auto(intp, d);
else
result->frequency = stv0900_get_tuner_freq(fe);
offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
result->frequency += offsetFreq;
result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
result->symbol_rate += srate_offset;
result->fec = stv0900_get_vit_fec(intp, d);
result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
switch (result->standard) {
case STV0900_DVBS2_STANDARD:
result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
if (result->modcode <= STV0900_QPSK_910)
result->modulation = STV0900_QPSK;
else if (result->modcode <= STV0900_8PSK_910)
result->modulation = STV0900_8PSK;
else if (result->modcode <= STV0900_16APSK_910)
result->modulation = STV0900_16APSK;
else if (result->modcode <= STV0900_32APSK_910)
result->modulation = STV0900_32APSK;
else
result->modulation = STV0900_UNKNOWN;
break;
case STV0900_DVBS1_STANDARD:
case STV0900_DSS_STANDARD:
result->spectrum = stv0900_get_bits(intp, IQINV);
result->modulation = STV0900_QPSK;
break;
default:
break;
}
if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
(intp->symbol_rate[d] < 10000000)) {
offsetFreq = result->frequency - intp->freq[d];
if (intp->tuner_type[demod] == 3)
intp->freq[d] = stv0900_get_freq_auto(intp, d);
else
intp->freq[d] = stv0900_get_tuner_freq(fe);
if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
range = STV0900_RANGEOK;
else if (abs(offsetFreq) <=
(stv0900_carrier_width(result->symbol_rate,
result->rolloff) / 2000))
range = STV0900_RANGEOK;
} else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
range = STV0900_RANGEOK;
dprintk("%s: range %d\n", __func__, range);
return range;
}
static enum
fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
s32 srate,
demod_timeout,
fec_timeout,
freq1,
freq0;
intp->result[demod].locked = FALSE;
if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
srate += stv0900_get_timing_offst(intp, srate, demod);
if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
srate, STV0900_WARM_START);
freq1 = stv0900_read_reg(intp, CFR2);
freq0 = stv0900_read_reg(intp, CFR1);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_bits(intp, SPECINV_CONTROL,
STV0900_IQ_FORCE_SWAPPED);
stv0900_write_reg(intp, DMDISTATE, 0x1c);
stv0900_write_reg(intp, CFRINIT1, freq1);
stv0900_write_reg(intp, CFRINIT0, freq0);
stv0900_write_reg(intp, DMDISTATE, 0x18);
if (stv0900_wait_for_lock(intp, demod,
demod_timeout, fec_timeout) == TRUE) {
intp->result[demod].locked = TRUE;
signal_type = stv0900_get_signal_params(fe);
stv0900_track_optimization(fe);
} else {
stv0900_write_bits(intp, SPECINV_CONTROL,
STV0900_IQ_FORCE_NORMAL);
stv0900_write_reg(intp, DMDISTATE, 0x1c);
stv0900_write_reg(intp, CFRINIT1, freq1);
stv0900_write_reg(intp, CFRINIT0, freq0);
stv0900_write_reg(intp, DMDISTATE, 0x18);
if (stv0900_wait_for_lock(intp, demod,
demod_timeout, fec_timeout) == TRUE) {
intp->result[demod].locked = TRUE;
signal_type = stv0900_get_signal_params(fe);
stv0900_track_optimization(fe);
}
}
} else
intp->result[demod].locked = FALSE;
return signal_type;
}
static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 minagc2level = 0xffff,
agc2level,
init_freq, freq_step;
s32 i, j, nb_steps, direction;
dprintk("%s\n", __func__);
stv0900_write_reg(intp, AGC2REF, 0x38);
stv0900_write_bits(intp, SCAN_ENABLE, 0);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_bits(intp, AUTO_GUP, 1);
stv0900_write_bits(intp, AUTO_GLOW, 1);
stv0900_write_reg(intp, DMDT0M, 0x0);
stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
nb_steps = -1 + (intp->srch_range[demod] / 1000000);
nb_steps /= 2;
nb_steps = (2 * nb_steps) + 1;
if (nb_steps < 0)
nb_steps = 1;
direction = 1;
freq_step = (1000000 << 8) / (intp->mclk >> 8);
init_freq = 0;
for (i = 0; i < nb_steps; i++) {
if (direction > 0)
init_freq = init_freq + (freq_step * i);
else
init_freq = init_freq - (freq_step * i);
direction *= -1;
stv0900_write_reg(intp, DMDISTATE, 0x5C);
stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
stv0900_write_reg(intp, DMDISTATE, 0x58);
msleep(10);
agc2level = 0;
for (j = 0; j < 10; j++)
agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
agc2level /= 10;
if (agc2level < minagc2level)
minagc2level = agc2level;
}
return (u16)minagc2level;
}
static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
int timing_lck = FALSE;
s32 i, timingcpt = 0,
direction = 1,
nb_steps,
current_step = 0,
tuner_freq;
u32 agc2_th,
coarse_srate = 0,
agc2_integr = 0,
currier_step = 1200;
if (intp->chip_id >= 0x30)
agc2_th = 0x2e00;
else
agc2_th = 0x1f00;
stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
stv0900_write_reg(intp, TMGCFG, 0x12);
stv0900_write_reg(intp, TMGTHRISE, 0xf0);
stv0900_write_reg(intp, TMGTHFALL, 0xe0);
stv0900_write_bits(intp, SCAN_ENABLE, 1);
stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
stv0900_write_reg(intp, SFRUP1, 0x83);
stv0900_write_reg(intp, SFRUP0, 0xc0);
stv0900_write_reg(intp, SFRLOW1, 0x82);
stv0900_write_reg(intp, SFRLOW0, 0xa0);
stv0900_write_reg(intp, DMDT0M, 0x0);
stv0900_write_reg(intp, AGC2REF, 0x50);
if (intp->chip_id >= 0x30) {
stv0900_write_reg(intp, CARFREQ, 0x99);
stv0900_write_reg(intp, SFRSTEP, 0x98);
} else if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, CARFREQ, 0x6a);
stv0900_write_reg(intp, SFRSTEP, 0x95);
} else {
stv0900_write_reg(intp, CARFREQ, 0xed);
stv0900_write_reg(intp, SFRSTEP, 0x73);
}
if (intp->symbol_rate[demod] <= 2000000)
currier_step = 1000;
else if (intp->symbol_rate[demod] <= 5000000)
currier_step = 2000;
else if (intp->symbol_rate[demod] <= 12000000)
currier_step = 3000;
else
currier_step = 5000;
nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
nb_steps /= 2;
nb_steps = (2 * nb_steps) + 1;
if (nb_steps < 0)
nb_steps = 1;
else if (nb_steps > 10) {
nb_steps = 11;
currier_step = (intp->srch_range[demod] / 1000) / 10;
}
current_step = 0;
direction = 1;
tuner_freq = intp->freq[demod];
while ((timing_lck == FALSE) && (current_step < nb_steps)) {
stv0900_write_reg(intp, DMDISTATE, 0x5f);
stv0900_write_bits(intp, DEMOD_MODE, 0);
msleep(50);
for (i = 0; i < 10; i++) {
if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
timingcpt++;
agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
stv0900_read_reg(intp, AGC2I0);
}
agc2_integr /= 10;
coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
current_step++;
direction *= -1;
dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
tuner_freq, agc2_integr, coarse_srate, timingcpt);
if ((timingcpt >= 5) &&
(agc2_integr < agc2_th) &&
(coarse_srate < 55000000) &&
(coarse_srate > 850000))
timing_lck = TRUE;
else if (current_step < nb_steps) {
if (direction > 0)
tuner_freq += (current_step * currier_step);
else
tuner_freq -= (current_step * currier_step);
if (intp->tuner_type[demod] == 3)
stv0900_set_tuner_auto(intp, tuner_freq,
intp->bw[demod], demod);
else
stv0900_set_tuner(fe, tuner_freq,
intp->bw[demod]);
}
}
if (timing_lck == FALSE)
coarse_srate = 0;
else
coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
return coarse_srate;
}
static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u32 coarse_srate,
coarse_freq,
symb,
symbmax,
symbmin,
symbcomp;
coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
if (coarse_srate > 3000000) {
symbmax = 13 * (coarse_srate / 10);
symbmax = (symbmax / 1000) * 65536;
symbmax /= (intp->mclk / 1000);
symbmin = 10 * (coarse_srate / 13);
symbmin = (symbmin / 1000)*65536;
symbmin /= (intp->mclk / 1000);
symb = (coarse_srate / 1000) * 65536;
symb /= (intp->mclk / 1000);
} else {
symbmax = 13 * (coarse_srate / 10);
symbmax = (symbmax / 100) * 65536;
symbmax /= (intp->mclk / 100);
symbmin = 10 * (coarse_srate / 14);
symbmin = (symbmin / 100) * 65536;
symbmin /= (intp->mclk / 100);
symb = (coarse_srate / 100) * 65536;
symb /= (intp->mclk / 100);
}
symbcomp = 13 * (coarse_srate / 10);
coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
| stv0900_read_reg(intp, CFR1);
if (symbcomp < intp->symbol_rate[demod])
coarse_srate = 0;
else {
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, TMGCFG2, 0xc1);
stv0900_write_reg(intp, TMGTHRISE, 0x20);
stv0900_write_reg(intp, TMGTHFALL, 0x00);
stv0900_write_reg(intp, TMGCFG, 0xd2);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_reg(intp, AGC2REF, 0x38);
if (intp->chip_id >= 0x30)
stv0900_write_reg(intp, CARFREQ, 0x79);
else if (intp->chip_id >= 0x20)
stv0900_write_reg(intp, CARFREQ, 0x49);
else
stv0900_write_reg(intp, CARFREQ, 0xed);
stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
stv0900_write_reg(intp, DMDT0M, 0x20);
stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
stv0900_write_reg(intp, DMDISTATE, 0x15);
}
return coarse_srate;
}
static int stv0900_blind_search_algo(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u8 k_ref_tmg,
k_ref_tmg_max,
k_ref_tmg_min;
u32 coarse_srate,
agc2_th;
int lock = FALSE,
coarse_fail = FALSE;
s32 demod_timeout = 500,
fec_timeout = 50,
fail_cpt,
i,
agc2_overflow;
u16 agc2_int;
u8 dstatus2;
dprintk("%s\n", __func__);
if (intp->chip_id < 0x20) {
k_ref_tmg_max = 233;
k_ref_tmg_min = 143;
} else {
k_ref_tmg_max = 110;
k_ref_tmg_min = 10;
}
if (intp->chip_id <= 0x20)
agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
else
agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
if (agc2_int > agc2_th)
return FALSE;
if (intp->chip_id == 0x10)
stv0900_write_reg(intp, CORRELEXP, 0xaa);
if (intp->chip_id < 0x20)
stv0900_write_reg(intp, CARHDR, 0x55);
else
stv0900_write_reg(intp, CARHDR, 0x20);
if (intp->chip_id <= 0x20)
stv0900_write_reg(intp, CARCFG, 0xc4);
else
stv0900_write_reg(intp, CARCFG, 0x6);
stv0900_write_reg(intp, RTCS2, 0x44);
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, EQUALCFG, 0x41);
stv0900_write_reg(intp, FFECFG, 0x41);
stv0900_write_reg(intp, VITSCALE, 0x82);
stv0900_write_reg(intp, VAVSRVIT, 0x0);
}
k_ref_tmg = k_ref_tmg_max;
do {
stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
if (stv0900_search_srate_coarse(fe) != 0) {
coarse_srate = stv0900_search_srate_fine(fe);
if (coarse_srate != 0) {
stv0900_get_lock_timeout(&demod_timeout,
&fec_timeout,
coarse_srate,
STV0900_BLIND_SEARCH);
lock = stv0900_get_demod_lock(intp,
demod,
demod_timeout);
} else
lock = FALSE;
} else {
fail_cpt = 0;
agc2_overflow = 0;
for (i = 0; i < 10; i++) {
agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
| stv0900_read_reg(intp, AGC2I0);
if (agc2_int >= 0xff00)
agc2_overflow++;
dstatus2 = stv0900_read_reg(intp, DSTATUS2);
if (((dstatus2 & 0x1) == 0x1) &&
((dstatus2 >> 7) == 1))
fail_cpt++;
}
if ((fail_cpt > 7) || (agc2_overflow > 7))
coarse_fail = TRUE;
lock = FALSE;
}
k_ref_tmg -= 30;
} while ((k_ref_tmg >= k_ref_tmg_min) &&
(lock == FALSE) &&
(coarse_fail == FALSE));
return lock;
}
static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 vth_reg = VTH12;
dprintk("%s\n", __func__);
stv0900_write_reg(intp, vth_reg++, 0x96);
stv0900_write_reg(intp, vth_reg++, 0x64);
stv0900_write_reg(intp, vth_reg++, 0x36);
stv0900_write_reg(intp, vth_reg++, 0x23);
stv0900_write_reg(intp, vth_reg++, 0x1e);
stv0900_write_reg(intp, vth_reg++, 0x19);
}
static void stv0900_set_search_standard(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
dprintk("%s\n", __func__);
switch (intp->srch_standard[demod]) {
case STV0900_SEARCH_DVBS1:
dprintk("Search Standard = DVBS1\n");
break;
case STV0900_SEARCH_DSS:
dprintk("Search Standard = DSS\n");
break;
case STV0900_SEARCH_DVBS2:
dprintk("Search Standard = DVBS2\n");
break;
case STV0900_AUTO_SEARCH:
default:
dprintk("Search Standard = AUTO\n");
break;
}
switch (intp->srch_standard[demod]) {
case STV0900_SEARCH_DVBS1:
case STV0900_SEARCH_DSS:
stv0900_write_bits(intp, DVBS1_ENABLE, 1);
stv0900_write_bits(intp, DVBS2_ENABLE, 0);
stv0900_write_bits(intp, STOP_CLKVIT, 0);
stv0900_set_dvbs1_track_car_loop(intp,
demod,
intp->symbol_rate[demod]);
stv0900_write_reg(intp, CAR2CFG, 0x22);
stv0900_set_viterbi_acq(intp, demod);
stv0900_set_viterbi_standard(intp,
intp->srch_standard[demod],
intp->fec[demod], demod);
break;
case STV0900_SEARCH_DVBS2:
stv0900_write_bits(intp, DVBS1_ENABLE, 0);
stv0900_write_bits(intp, DVBS2_ENABLE, 1);
stv0900_write_bits(intp, STOP_CLKVIT, 1);
stv0900_write_reg(intp, ACLC, 0x1a);
stv0900_write_reg(intp, BCLC, 0x09);
if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
stv0900_write_reg(intp, CAR2CFG, 0x26);
else
stv0900_write_reg(intp, CAR2CFG, 0x66);
if (intp->demod_mode != STV0900_SINGLE) {
if (intp->chip_id <= 0x11)
stv0900_stop_all_s2_modcod(intp, demod);
else
stv0900_activate_s2_modcod(intp, demod);
} else
stv0900_activate_s2_modcod_single(intp, demod);
stv0900_set_viterbi_tracq(intp, demod);
break;
case STV0900_AUTO_SEARCH:
default:
stv0900_write_bits(intp, DVBS1_ENABLE, 1);
stv0900_write_bits(intp, DVBS2_ENABLE, 1);
stv0900_write_bits(intp, STOP_CLKVIT, 0);
stv0900_write_reg(intp, ACLC, 0x1a);
stv0900_write_reg(intp, BCLC, 0x09);
stv0900_set_dvbs1_track_car_loop(intp,
demod,
intp->symbol_rate[demod]);
if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
stv0900_write_reg(intp, CAR2CFG, 0x26);
else
stv0900_write_reg(intp, CAR2CFG, 0x66);
if (intp->demod_mode != STV0900_SINGLE) {
if (intp->chip_id <= 0x11)
stv0900_stop_all_s2_modcod(intp, demod);
else
stv0900_activate_s2_modcod(intp, demod);
} else
stv0900_activate_s2_modcod_single(intp, demod);
stv0900_set_viterbi_tracq(intp, demod);
stv0900_set_viterbi_standard(intp,
intp->srch_standard[demod],
intp->fec[demod], demod);
break;
}
}
enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 demod_timeout = 500, fec_timeout = 50;
s32 aq_power, agc1_power, i;
int lock = FALSE, low_sr = FALSE;
enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
enum fe_stv0900_search_algo algo;
int no_signal = FALSE;
dprintk("%s\n", __func__);
algo = intp->srch_algo[demod];
stv0900_write_bits(intp, RST_HWARE, 1);
stv0900_write_reg(intp, DMDISTATE, 0x5c);
if (intp->chip_id >= 0x20) {
if (intp->symbol_rate[demod] > 5000000)
stv0900_write_reg(intp, CORRELABS, 0x9e);
else
stv0900_write_reg(intp, CORRELABS, 0x82);
} else
stv0900_write_reg(intp, CORRELABS, 0x88);
stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
intp->symbol_rate[demod],
intp->srch_algo[demod]);
if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
intp->bw[demod] = 2 * 36000000;
stv0900_write_reg(intp, TMGCFG2, 0xc0);
stv0900_write_reg(intp, CORRELMANT, 0x70);
stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
} else {
stv0900_write_reg(intp, DMDT0M, 0x20);
stv0900_write_reg(intp, TMGCFG, 0xd2);
if (intp->symbol_rate[demod] < 2000000)
stv0900_write_reg(intp, CORRELMANT, 0x63);
else
stv0900_write_reg(intp, CORRELMANT, 0x70);
stv0900_write_reg(intp, AGC2REF, 0x38);
intp->bw[demod] =
stv0900_carrier_width(intp->symbol_rate[demod],
intp->rolloff);
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, KREFTMG, 0x5a);
if (intp->srch_algo[demod] == STV0900_COLD_START) {
intp->bw[demod] += 10000000;
intp->bw[demod] *= 15;
intp->bw[demod] /= 10;
} else if (intp->srch_algo[demod] == STV0900_WARM_START)
intp->bw[demod] += 10000000;
} else {
stv0900_write_reg(intp, KREFTMG, 0xc1);
intp->bw[demod] += 10000000;
intp->bw[demod] *= 15;
intp->bw[demod] /= 10;
}
stv0900_write_reg(intp, TMGCFG2, 0xc1);
stv0900_set_symbol_rate(intp, intp->mclk,
intp->symbol_rate[demod], demod);
stv0900_set_max_symbol_rate(intp, intp->mclk,
intp->symbol_rate[demod], demod);
stv0900_set_min_symbol_rate(intp, intp->mclk,
intp->symbol_rate[demod], demod);
if (intp->symbol_rate[demod] >= 10000000)
low_sr = FALSE;
else
low_sr = TRUE;
}
if (intp->tuner_type[demod] == 3)
stv0900_set_tuner_auto(intp, intp->freq[demod],
intp->bw[demod], demod);
else
stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
stv0900_get_bits(intp, AGCIQ_VALUE0));
aq_power = 0;
if (agc1_power == 0) {
for (i = 0; i < 5; i++)
aq_power += (stv0900_get_bits(intp, POWER_I) +
stv0900_get_bits(intp, POWER_Q)) / 2;
aq_power /= 5;
}
if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
intp->result[demod].locked = FALSE;
signal_type = STV0900_NOAGC1;
dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
} else {
stv0900_write_bits(intp, SPECINV_CONTROL,
intp->srch_iq_inv[demod]);
if (intp->chip_id <= 0x20) /*cut 2.0*/
stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
else /*cut 3.0*/
stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
stv0900_set_search_standard(intp, demod);
if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
stv0900_start_search(intp, demod);
}
if (signal_type == STV0900_NOAGC1)
return signal_type;
if (intp->chip_id == 0x12) {
stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
stv0900_write_bits(intp, RST_HWARE, 1);
stv0900_write_bits(intp, RST_HWARE, 0);
}
if (algo == STV0900_BLIND_SEARCH)
lock = stv0900_blind_search_algo(fe);
else if (algo == STV0900_COLD_START)
lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
else if (algo == STV0900_WARM_START)
lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
if (low_sr == FALSE) {
if (stv0900_check_timing_lock(intp, demod) == TRUE)
lock = stv0900_sw_algo(intp, demod);
}
}
if (lock == TRUE)
signal_type = stv0900_get_signal_params(fe);
if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
stv0900_track_optimization(fe);
if (intp->chip_id <= 0x11) {
if ((stv0900_get_standard(fe, 0) ==
STV0900_DVBS1_STANDARD) &&
(stv0900_get_standard(fe, 1) ==
STV0900_DVBS1_STANDARD)) {
msleep(20);
stv0900_write_bits(intp, RST_HWARE, 0);
} else {
stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
stv0900_write_bits(intp, RST_HWARE, 1);
stv0900_write_bits(intp, RST_HWARE, 0);
}
} else if (intp->chip_id >= 0x20) {
stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
stv0900_write_bits(intp, RST_HWARE, 1);
stv0900_write_bits(intp, RST_HWARE, 0);
}
if (stv0900_wait_for_lock(intp, demod,
fec_timeout, fec_timeout) == TRUE) {
lock = TRUE;
intp->result[demod].locked = TRUE;
if (intp->result[demod].standard ==
STV0900_DVBS2_STANDARD) {
stv0900_set_dvbs2_rolloff(intp, demod);
stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
stv0900_write_reg(intp, ERRCTRL1, 0x67);
} else {
stv0900_write_reg(intp, ERRCTRL1, 0x75);
}
stv0900_write_reg(intp, FBERCPT4, 0);
stv0900_write_reg(intp, ERRCTRL2, 0xc1);
} else {
lock = FALSE;
signal_type = STV0900_NODATA;
no_signal = stv0900_check_signal_presence(intp, demod);
intp->result[demod].locked = FALSE;
}
}
if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
return signal_type;
if (intp->chip_id > 0x11) {
intp->result[demod].locked = FALSE;
return signal_type;
}
if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
(intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
signal_type = stv0900_dvbs1_acq_workaround(fe);
return signal_type;
}
| linux-master | drivers/media/dvb-frontends/stv0900_sw.c |
/*
* Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
*
* Copyright (C) 2001-5, B2C2 inc.
*
* GPL/Linux driver written by Patrick Boettcher <[email protected]>
*
* This driver is "hard-coded" to be used with the 1st generation of
* Technisat/B2C2's Air2PC ATSC PCI/USB cards/boxes. The pll-programming
* (Panasonic CT10S) is located here, which is actually wrong. Unless there is
* another device with a BCM3510, this is no problem.
*
* The driver works also with QAM64 DVB-C, but had an unreasonable high
* UNC. (Tested with the Air2PC ATSC 1st generation)
*
* You'll need a firmware for this driver in order to get it running. It is
* called "dvb-fe-bcm3510-01.fw".
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 675 Mass
* Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <media/dvb_frontend.h>
#include "bcm3510.h"
#include "bcm3510_priv.h"
/* Max transfer size done by bcm3510_do_hab_cmd() function */
#define MAX_XFER_SIZE 128
struct bcm3510_state {
struct i2c_adapter* i2c;
const struct bcm3510_config* config;
struct dvb_frontend frontend;
/* demodulator private data */
struct mutex hab_mutex;
u8 firmware_loaded:1;
unsigned long next_status_check;
unsigned long status_check_interval;
struct bcm3510_hab_cmd_status1 status1;
struct bcm3510_hab_cmd_status2 status2;
};
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debugging level (1=info,2=i2c (|-able)).");
#define dprintk(level,x...) if (level & debug) printk(x)
#define dbufout(b,l,m) {\
int i; \
for (i = 0; i < l; i++) \
m("%02x ",b[i]); \
}
#define deb_info(args...) dprintk(0x01,args)
#define deb_i2c(args...) dprintk(0x02,args)
#define deb_hab(args...) dprintk(0x04,args)
/* transfer functions */
static int bcm3510_writebytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len)
{
u8 b[256];
int err;
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = len + 1 };
b[0] = reg;
memcpy(&b[1],buf,len);
deb_i2c("i2c wr %02x: ",reg);
dbufout(buf,len,deb_i2c);
deb_i2c("\n");
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
deb_info("%s: i2c write error (addr %02x, reg %02x, err == %i)\n",
__func__, state->config->demod_address, reg, err);
return -EREMOTEIO;
}
return 0;
}
static int bcm3510_readbytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len)
{
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len }
};
int err;
memset(buf,0,len);
if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
deb_info("%s: i2c read error (addr %02x, reg %02x, err == %i)\n",
__func__, state->config->demod_address, reg, err);
return -EREMOTEIO;
}
deb_i2c("i2c rd %02x: ",reg);
dbufout(buf,len,deb_i2c);
deb_i2c("\n");
return 0;
}
static int bcm3510_writeB(struct bcm3510_state *state, u8 reg, bcm3510_register_value v)
{
return bcm3510_writebytes(state,reg,&v.raw,1);
}
static int bcm3510_readB(struct bcm3510_state *state, u8 reg, bcm3510_register_value *v)
{
return bcm3510_readbytes(state,reg,&v->raw,1);
}
/* Host Access Buffer transfers */
static int bcm3510_hab_get_response(struct bcm3510_state *st, u8 *buf, int len)
{
bcm3510_register_value v;
int ret,i;
v.HABADR_a6.HABADR = 0;
if ((ret = bcm3510_writeB(st,0xa6,v)) < 0)
return ret;
for (i = 0; i < len; i++) {
if ((ret = bcm3510_readB(st,0xa7,&v)) < 0)
return ret;
buf[i] = v.HABDATA_a7;
}
return 0;
}
static int bcm3510_hab_send_request(struct bcm3510_state *st, u8 *buf, int len)
{
bcm3510_register_value v,hab;
int ret,i;
unsigned long t;
/* Check if any previous HAB request still needs to be serviced by the
* Acquisition Processor before sending new request */
if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
return ret;
if (v.HABSTAT_a8.HABR) {
deb_info("HAB is running already - clearing it.\n");
v.HABSTAT_a8.HABR = 0;
bcm3510_writeB(st,0xa8,v);
// return -EBUSY;
}
/* Send the start HAB Address (automatically incremented after write of
* HABDATA) and write the HAB Data */
hab.HABADR_a6.HABADR = 0;
if ((ret = bcm3510_writeB(st,0xa6,hab)) < 0)
return ret;
for (i = 0; i < len; i++) {
hab.HABDATA_a7 = buf[i];
if ((ret = bcm3510_writeB(st,0xa7,hab)) < 0)
return ret;
}
/* Set the HABR bit to indicate AP request in progress (LBHABR allows HABR to
* be written) */
v.raw = 0; v.HABSTAT_a8.HABR = 1; v.HABSTAT_a8.LDHABR = 1;
if ((ret = bcm3510_writeB(st,0xa8,v)) < 0)
return ret;
/* Polling method: Wait until the AP finishes processing the HAB request */
t = jiffies + 1*HZ;
while (time_before(jiffies, t)) {
deb_info("waiting for HAB to complete\n");
msleep(10);
if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
return ret;
if (!v.HABSTAT_a8.HABR)
return 0;
}
deb_info("send_request execution timed out.\n");
return -ETIMEDOUT;
}
static int bcm3510_do_hab_cmd(struct bcm3510_state *st, u8 cmd, u8 msgid, u8 *obuf, u8 olen, u8 *ibuf, u8 ilen)
{
u8 ob[MAX_XFER_SIZE], ib[MAX_XFER_SIZE];
int ret = 0;
if (ilen + 2 > sizeof(ib)) {
deb_hab("do_hab_cmd: ilen=%d is too big!\n", ilen);
return -EINVAL;
}
if (olen + 2 > sizeof(ob)) {
deb_hab("do_hab_cmd: olen=%d is too big!\n", olen);
return -EINVAL;
}
ob[0] = cmd;
ob[1] = msgid;
memcpy(&ob[2],obuf,olen);
deb_hab("hab snd: ");
dbufout(ob,olen+2,deb_hab);
deb_hab("\n");
if (mutex_lock_interruptible(&st->hab_mutex) < 0)
return -EAGAIN;
if ((ret = bcm3510_hab_send_request(st, ob, olen+2)) < 0 ||
(ret = bcm3510_hab_get_response(st, ib, ilen+2)) < 0)
goto error;
deb_hab("hab get: ");
dbufout(ib,ilen+2,deb_hab);
deb_hab("\n");
memcpy(ibuf,&ib[2],ilen);
error:
mutex_unlock(&st->hab_mutex);
return ret;
}
#if 0
/* not needed, we use a semaphore to prevent HAB races */
static int bcm3510_is_ap_ready(struct bcm3510_state *st)
{
bcm3510_register_value ap,hab;
int ret;
if ((ret = bcm3510_readB(st,0xa8,&hab)) < 0 ||
(ret = bcm3510_readB(st,0xa2,&ap) < 0))
return ret;
if (ap.APSTAT1_a2.RESET || ap.APSTAT1_a2.IDLE || ap.APSTAT1_a2.STOP || hab.HABSTAT_a8.HABR) {
deb_info("AP is busy\n");
return -EBUSY;
}
return 0;
}
#endif
static int bcm3510_bert_reset(struct bcm3510_state *st)
{
bcm3510_register_value b;
int ret;
if ((ret = bcm3510_readB(st,0xfa,&b)) < 0)
return ret;
b.BERCTL_fa.RESYNC = 0; bcm3510_writeB(st,0xfa,b);
b.BERCTL_fa.RESYNC = 1; bcm3510_writeB(st,0xfa,b);
b.BERCTL_fa.RESYNC = 0; bcm3510_writeB(st,0xfa,b);
b.BERCTL_fa.CNTCTL = 1; b.BERCTL_fa.BITCNT = 1; bcm3510_writeB(st,0xfa,b);
/* clear residual bit counter TODO */
return 0;
}
static int bcm3510_refresh_state(struct bcm3510_state *st)
{
if (time_after(jiffies,st->next_status_check)) {
bcm3510_do_hab_cmd(st, CMD_STATUS, MSGID_STATUS1, NULL,0, (u8 *)&st->status1, sizeof(st->status1));
bcm3510_do_hab_cmd(st, CMD_STATUS, MSGID_STATUS2, NULL,0, (u8 *)&st->status2, sizeof(st->status2));
st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000;
}
return 0;
}
static int bcm3510_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct bcm3510_state* st = fe->demodulator_priv;
bcm3510_refresh_state(st);
*status = 0;
if (st->status1.STATUS1.RECEIVER_LOCK)
*status |= FE_HAS_LOCK | FE_HAS_SYNC;
if (st->status1.STATUS1.FEC_LOCK)
*status |= FE_HAS_VITERBI;
if (st->status1.STATUS1.OUT_PLL_LOCK)
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
if (*status & FE_HAS_LOCK)
st->status_check_interval = 1500;
else /* more frequently checks if no lock has been achieved yet */
st->status_check_interval = 500;
deb_info("real_status: %02x\n",*status);
return 0;
}
static int bcm3510_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct bcm3510_state* st = fe->demodulator_priv;
bcm3510_refresh_state(st);
*ber = (st->status2.LDBER0 << 16) | (st->status2.LDBER1 << 8) | st->status2.LDBER2;
return 0;
}
static int bcm3510_read_unc(struct dvb_frontend* fe, u32* unc)
{
struct bcm3510_state* st = fe->demodulator_priv;
bcm3510_refresh_state(st);
*unc = (st->status2.LDUERC0 << 8) | st->status2.LDUERC1;
return 0;
}
static int bcm3510_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct bcm3510_state* st = fe->demodulator_priv;
s32 t;
bcm3510_refresh_state(st);
t = st->status2.SIGNAL;
if (t > 190)
t = 190;
if (t < 90)
t = 90;
t -= 90;
t = t * 0xff / 100;
/* normalize if necessary */
*strength = (t << 8) | t;
return 0;
}
static int bcm3510_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct bcm3510_state* st = fe->demodulator_priv;
bcm3510_refresh_state(st);
*snr = st->status1.SNR_EST0*1000 + ((st->status1.SNR_EST1*1000) >> 8);
return 0;
}
/* tuner frontend programming */
static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)
{
struct bcm3510_hab_cmd_tune c;
memset(&c,0,sizeof(struct bcm3510_hab_cmd_tune));
/* I2C Mode disabled, set 16 control / Data pairs */
c.length = 0x10;
c.clock_width = 0;
/* CS1, CS0, DATA, CLK bits control the tuner RF_AGC_SEL pin is set to
* logic high (as Configuration) */
c.misc = 0x10;
/* Set duration of the initial state of TUNCTL = 3.34 micro Sec */
c.TUNCTL_state = 0x40;
/* PRESCALER DIVIDE RATIO | BC1_2_3_4; (band switch), 1stosc REFERENCE COUNTER REF_S12 and REF_S11 */
c.ctl_dat[0].ctrl.size = BITS_8;
c.ctl_dat[0].data = 0x80 | bc;
/* Control DATA pin, 1stosc REFERENCE COUNTER REF_S10 to REF_S3 */
c.ctl_dat[1].ctrl.size = BITS_8;
c.ctl_dat[1].data = 4;
/* set CONTROL BIT 1 to 1, 1stosc REFERENCE COUNTER REF_S2 to REF_S1 */
c.ctl_dat[2].ctrl.size = BITS_3;
c.ctl_dat[2].data = 0x20;
/* control CS0 pin, pulse byte ? */
c.ctl_dat[3].ctrl.size = BITS_3;
c.ctl_dat[3].ctrl.clk_off = 1;
c.ctl_dat[3].ctrl.cs0 = 1;
c.ctl_dat[3].data = 0x40;
/* PGM_S18 to PGM_S11 */
c.ctl_dat[4].ctrl.size = BITS_8;
c.ctl_dat[4].data = n >> 3;
/* PGM_S10 to PGM_S8, SWL_S7 to SWL_S3 */
c.ctl_dat[5].ctrl.size = BITS_8;
c.ctl_dat[5].data = ((n & 0x7) << 5) | (a >> 2);
/* SWL_S2 and SWL_S1, set CONTROL BIT 2 to 0 */
c.ctl_dat[6].ctrl.size = BITS_3;
c.ctl_dat[6].data = (a << 6) & 0xdf;
/* control CS0 pin, pulse byte ? */
c.ctl_dat[7].ctrl.size = BITS_3;
c.ctl_dat[7].ctrl.clk_off = 1;
c.ctl_dat[7].ctrl.cs0 = 1;
c.ctl_dat[7].data = 0x40;
/* PRESCALER DIVIDE RATIO, 2ndosc REFERENCE COUNTER REF_S12 and REF_S11 */
c.ctl_dat[8].ctrl.size = BITS_8;
c.ctl_dat[8].data = 0x80;
/* 2ndosc REFERENCE COUNTER REF_S10 to REF_S3 */
c.ctl_dat[9].ctrl.size = BITS_8;
c.ctl_dat[9].data = 0x10;
/* set CONTROL BIT 1 to 1, 2ndosc REFERENCE COUNTER REF_S2 to REF_S1 */
c.ctl_dat[10].ctrl.size = BITS_3;
c.ctl_dat[10].data = 0x20;
/* pulse byte */
c.ctl_dat[11].ctrl.size = BITS_3;
c.ctl_dat[11].ctrl.clk_off = 1;
c.ctl_dat[11].ctrl.cs1 = 1;
c.ctl_dat[11].data = 0x40;
/* PGM_S18 to PGM_S11 */
c.ctl_dat[12].ctrl.size = BITS_8;
c.ctl_dat[12].data = 0x2a;
/* PGM_S10 to PGM_S8 and SWL_S7 to SWL_S3 */
c.ctl_dat[13].ctrl.size = BITS_8;
c.ctl_dat[13].data = 0x8e;
/* SWL_S2 and SWL_S1 and set CONTROL BIT 2 to 0 */
c.ctl_dat[14].ctrl.size = BITS_3;
c.ctl_dat[14].data = 0;
/* Pulse Byte */
c.ctl_dat[15].ctrl.size = BITS_3;
c.ctl_dat[15].ctrl.clk_off = 1;
c.ctl_dat[15].ctrl.cs1 = 1;
c.ctl_dat[15].data = 0x40;
return bcm3510_do_hab_cmd(st,CMD_TUNE, MSGID_TUNE,(u8 *) &c,sizeof(c), NULL, 0);
}
static int bcm3510_set_freq(struct bcm3510_state* st,u32 freq)
{
u8 bc,a;
u16 n;
s32 YIntercept,Tfvco1;
freq /= 1000;
deb_info("%dkHz:",freq);
/* set Band Switch */
if (freq <= 168000)
bc = 0x1c;
else if (freq <= 378000)
bc = 0x2c;
else
bc = 0x30;
if (freq >= 470000) {
freq -= 470001;
YIntercept = 18805;
} else if (freq >= 90000) {
freq -= 90001;
YIntercept = 15005;
} else if (freq >= 76000){
freq -= 76001;
YIntercept = 14865;
} else {
freq -= 54001;
YIntercept = 14645;
}
Tfvco1 = (((freq/6000)*60 + YIntercept)*4)/10;
n = Tfvco1 >> 6;
a = Tfvco1 & 0x3f;
deb_info(" BC1_2_3_4: %x, N: %x A: %x\n", bc, n, a);
if (n >= 16 && n <= 2047)
return bcm3510_tuner_cmd(st,bc,n,a);
return -EINVAL;
}
static int bcm3510_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct bcm3510_state* st = fe->demodulator_priv;
struct bcm3510_hab_cmd_ext_acquire cmd;
struct bcm3510_hab_cmd_bert_control bert;
int ret;
memset(&cmd,0,sizeof(cmd));
switch (c->modulation) {
case QAM_256:
cmd.ACQUIRE0.MODE = 0x1;
cmd.ACQUIRE1.SYM_RATE = 0x1;
cmd.ACQUIRE1.IF_FREQ = 0x1;
break;
case QAM_64:
cmd.ACQUIRE0.MODE = 0x2;
cmd.ACQUIRE1.SYM_RATE = 0x2;
cmd.ACQUIRE1.IF_FREQ = 0x1;
break;
#if 0
case QAM_256:
cmd.ACQUIRE0.MODE = 0x3;
break;
case QAM_128:
cmd.ACQUIRE0.MODE = 0x4;
break;
case QAM_64:
cmd.ACQUIRE0.MODE = 0x5;
break;
case QAM_32:
cmd.ACQUIRE0.MODE = 0x6;
break;
case QAM_16:
cmd.ACQUIRE0.MODE = 0x7;
break;
#endif
case VSB_8:
cmd.ACQUIRE0.MODE = 0x8;
cmd.ACQUIRE1.SYM_RATE = 0x0;
cmd.ACQUIRE1.IF_FREQ = 0x0;
break;
case VSB_16:
cmd.ACQUIRE0.MODE = 0x9;
cmd.ACQUIRE1.SYM_RATE = 0x0;
cmd.ACQUIRE1.IF_FREQ = 0x0;
break;
default:
return -EINVAL;
}
cmd.ACQUIRE0.OFFSET = 0;
cmd.ACQUIRE0.NTSCSWEEP = 1;
cmd.ACQUIRE0.FA = 1;
cmd.ACQUIRE0.BW = 0;
/* if (enableOffset) {
cmd.IF_OFFSET0 = xx;
cmd.IF_OFFSET1 = xx;
cmd.SYM_OFFSET0 = xx;
cmd.SYM_OFFSET1 = xx;
if (enableNtscSweep) {
cmd.NTSC_OFFSET0;
cmd.NTSC_OFFSET1;
}
} */
bcm3510_do_hab_cmd(st, CMD_ACQUIRE, MSGID_EXT_TUNER_ACQUIRE, (u8 *) &cmd, sizeof(cmd), NULL, 0);
/* doing it with different MSGIDs, data book and source differs */
bert.BE = 0;
bert.unused = 0;
bcm3510_do_hab_cmd(st, CMD_STATE_CONTROL, MSGID_BERT_CONTROL, (u8 *) &bert, sizeof(bert), NULL, 0);
bcm3510_do_hab_cmd(st, CMD_STATE_CONTROL, MSGID_BERT_SET, (u8 *) &bert, sizeof(bert), NULL, 0);
bcm3510_bert_reset(st);
ret = bcm3510_set_freq(st, c->frequency);
if (ret < 0)
return ret;
memset(&st->status1,0,sizeof(st->status1));
memset(&st->status2,0,sizeof(st->status2));
st->status_check_interval = 500;
/* Give the AP some time */
msleep(200);
return 0;
}
static int bcm3510_sleep(struct dvb_frontend* fe)
{
return 0;
}
static int bcm3510_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 1000;
s->step_size = 0;
s->max_drift = 0;
return 0;
}
static void bcm3510_release(struct dvb_frontend* fe)
{
struct bcm3510_state* state = fe->demodulator_priv;
kfree(state);
}
/* firmware download:
* firmware file is build up like this:
* 16bit addr, 16bit length, 8byte of length
*/
#define BCM3510_DEFAULT_FIRMWARE "dvb-fe-bcm3510-01.fw"
static int bcm3510_write_ram(struct bcm3510_state *st, u16 addr, const u8 *b,
u16 len)
{
int ret = 0,i;
bcm3510_register_value vH, vL,vD;
vH.MADRH_a9 = addr >> 8;
vL.MADRL_aa = addr;
if ((ret = bcm3510_writeB(st,0xa9,vH)) < 0) return ret;
if ((ret = bcm3510_writeB(st,0xaa,vL)) < 0) return ret;
for (i = 0; i < len; i++) {
vD.MDATA_ab = b[i];
if ((ret = bcm3510_writeB(st,0xab,vD)) < 0)
return ret;
}
return 0;
}
static int bcm3510_download_firmware(struct dvb_frontend* fe)
{
struct bcm3510_state* st = fe->demodulator_priv;
const struct firmware *fw;
u16 addr,len;
const u8 *b;
int ret,i;
deb_info("requesting firmware\n");
if ((ret = st->config->request_firmware(fe, &fw, BCM3510_DEFAULT_FIRMWARE)) < 0) {
err("could not load firmware (%s): %d",BCM3510_DEFAULT_FIRMWARE,ret);
return ret;
}
deb_info("got firmware: %zu\n", fw->size);
b = fw->data;
for (i = 0; i < fw->size;) {
addr = le16_to_cpu(*((__le16 *)&b[i]));
len = le16_to_cpu(*((__le16 *)&b[i+2]));
deb_info("firmware chunk, addr: 0x%04x, len: 0x%04x, total length: 0x%04zx\n",addr,len,fw->size);
if ((ret = bcm3510_write_ram(st,addr,&b[i+4],len)) < 0) {
err("firmware download failed: %d\n",ret);
release_firmware(fw);
return ret;
}
i += 4 + len;
}
release_firmware(fw);
deb_info("firmware download successfully completed\n");
return 0;
}
static int bcm3510_check_firmware_version(struct bcm3510_state *st)
{
struct bcm3510_hab_cmd_get_version_info ver;
bcm3510_do_hab_cmd(st,CMD_GET_VERSION_INFO,MSGID_GET_VERSION_INFO,NULL,0,(u8*)&ver,sizeof(ver));
deb_info("Version information: 0x%02x 0x%02x 0x%02x 0x%02x\n",
ver.microcode_version, ver.script_version, ver.config_version, ver.demod_version);
if (ver.script_version == BCM3510_DEF_SCRIPT_VERSION &&
ver.config_version == BCM3510_DEF_CONFIG_VERSION &&
ver.demod_version == BCM3510_DEF_DEMOD_VERSION)
return 0;
deb_info("version check failed\n");
return -ENODEV;
}
/* (un)resetting the AP */
static int bcm3510_reset(struct bcm3510_state *st)
{
int ret;
unsigned long t;
bcm3510_register_value v;
bcm3510_readB(st,0xa0,&v); v.HCTL1_a0.RESET = 1;
if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
return ret;
t = jiffies + 3*HZ;
while (time_before(jiffies, t)) {
msleep(10);
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
return ret;
if (v.APSTAT1_a2.RESET)
return 0;
}
deb_info("reset timed out\n");
return -ETIMEDOUT;
}
static int bcm3510_clear_reset(struct bcm3510_state *st)
{
bcm3510_register_value v;
int ret;
unsigned long t;
v.raw = 0;
if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
return ret;
t = jiffies + 3*HZ;
while (time_before(jiffies, t)) {
msleep(10);
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
return ret;
/* verify that reset is cleared */
if (!v.APSTAT1_a2.RESET)
return 0;
}
deb_info("reset clear timed out\n");
return -ETIMEDOUT;
}
static int bcm3510_init_cold(struct bcm3510_state *st)
{
int ret;
bcm3510_register_value v;
/* read Acquisation Processor status register and check it is not in RUN mode */
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
return ret;
if (v.APSTAT1_a2.RUN) {
deb_info("AP is already running - firmware already loaded.\n");
return 0;
}
deb_info("reset?\n");
if ((ret = bcm3510_reset(st)) < 0)
return ret;
deb_info("tristate?\n");
/* tri-state */
v.TSTCTL_2e.CTL = 0;
if ((ret = bcm3510_writeB(st,0x2e,v)) < 0)
return ret;
deb_info("firmware?\n");
if ((ret = bcm3510_download_firmware(&st->frontend)) < 0 ||
(ret = bcm3510_clear_reset(st)) < 0)
return ret;
/* anything left here to Let the acquisition processor begin execution at program counter 0000 ??? */
return 0;
}
static int bcm3510_init(struct dvb_frontend* fe)
{
struct bcm3510_state* st = fe->demodulator_priv;
bcm3510_register_value j;
struct bcm3510_hab_cmd_set_agc c;
int ret;
if ((ret = bcm3510_readB(st,0xca,&j)) < 0)
return ret;
deb_info("JDEC: %02x\n",j.raw);
switch (j.JDEC_ca.JDEC) {
case JDEC_WAIT_AT_RAM:
deb_info("attempting to download firmware\n");
if ((ret = bcm3510_init_cold(st)) < 0)
return ret;
fallthrough;
case JDEC_EEPROM_LOAD_WAIT:
deb_info("firmware is loaded\n");
bcm3510_check_firmware_version(st);
break;
default:
return -ENODEV;
}
memset(&c,0,1);
c.SEL = 1;
bcm3510_do_hab_cmd(st,CMD_AUTO_PARAM,MSGID_SET_RF_AGC_SEL,(u8 *)&c,sizeof(c),NULL,0);
return 0;
}
static const struct dvb_frontend_ops bcm3510_ops;
struct dvb_frontend* bcm3510_attach(const struct bcm3510_config *config,
struct i2c_adapter *i2c)
{
struct bcm3510_state* state = NULL;
int ret;
bcm3510_register_value v;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct bcm3510_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &bcm3510_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
mutex_init(&state->hab_mutex);
if ((ret = bcm3510_readB(state,0xe0,&v)) < 0)
goto error;
deb_info("Revision: 0x%1x, Layer: 0x%1x.\n",v.REVID_e0.REV,v.REVID_e0.LAYER);
if ((v.REVID_e0.REV != 0x1 && v.REVID_e0.LAYER != 0xb) && /* cold */
(v.REVID_e0.REV != 0x8 && v.REVID_e0.LAYER != 0x0)) /* warm */
goto error;
info("Revision: 0x%1x, Layer: 0x%1x.",v.REVID_e0.REV,v.REVID_e0.LAYER);
bcm3510_reset(state);
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(bcm3510_attach);
static const struct dvb_frontend_ops bcm3510_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Broadcom BCM3510 VSB/QAM frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 803 * MHz,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_8VSB | FE_CAN_16VSB |
FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256
},
.release = bcm3510_release,
.init = bcm3510_init,
.sleep = bcm3510_sleep,
.set_frontend = bcm3510_set_frontend,
.get_tune_settings = bcm3510_get_tune_settings,
.read_status = bcm3510_read_status,
.read_ber = bcm3510_read_ber,
.read_signal_strength = bcm3510_read_signal_strength,
.read_snr = bcm3510_read_snr,
.read_ucblocks = bcm3510_read_unc,
};
MODULE_DESCRIPTION("Broadcom BCM3510 ATSC (8VSB/16VSB & ITU J83 AnnexB FEC QAM64/256) demodulator driver");
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/bcm3510.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Panasonic MN88473 DVB-T/T2/C demodulator driver
*
* Copyright (C) 2014 Antti Palosaari <[email protected]>
*/
#include "mn88473_priv.h"
static int mn88473_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 1000;
return 0;
}
static int mn88473_set_frontend(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88473_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
unsigned int uitmp;
u32 if_frequency;
u8 delivery_system_val, if_val[3], *conf_val_ptr;
u8 reg_bank2_2d_val, reg_bank0_d2_val;
dev_dbg(&client->dev,
"delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
c->delivery_system, c->modulation, c->frequency,
c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
delivery_system_val = 0x02;
reg_bank2_2d_val = 0x23;
reg_bank0_d2_val = 0x2a;
break;
case SYS_DVBT2:
delivery_system_val = 0x03;
reg_bank2_2d_val = 0x3b;
reg_bank0_d2_val = 0x29;
break;
case SYS_DVBC_ANNEX_A:
delivery_system_val = 0x04;
reg_bank2_2d_val = 0x3b;
reg_bank0_d2_val = 0x29;
break;
default:
ret = -EINVAL;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
case SYS_DVBT2:
switch (c->bandwidth_hz) {
case 6000000:
conf_val_ptr = "\xe9\x55\x55\x1c\x29\x1c\x29";
break;
case 7000000:
conf_val_ptr = "\xc8\x00\x00\x17\x0a\x17\x0a";
break;
case 8000000:
conf_val_ptr = "\xaf\x00\x00\x11\xec\x11\xec";
break;
default:
ret = -EINVAL;
goto err;
}
break;
case SYS_DVBC_ANNEX_A:
conf_val_ptr = "\x10\xab\x0d\xae\x1d\x9d";
break;
default:
break;
}
/* Program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto err;
dev_dbg(&client->dev, "get_if_frequency=%u\n", if_frequency);
} else {
ret = -EINVAL;
goto err;
}
/* Calculate IF registers */
uitmp = DIV_ROUND_CLOSEST_ULL((u64) if_frequency * 0x1000000, dev->clk);
if_val[0] = (uitmp >> 16) & 0xff;
if_val[1] = (uitmp >> 8) & 0xff;
if_val[2] = (uitmp >> 0) & 0xff;
ret = regmap_write(dev->regmap[2], 0x05, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0xfb, 0x13);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0xef, 0x13);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0xf9, 0x13);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x00, 0x18);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x01, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x02, 0x21);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
if (ret)
goto err;
for (i = 0; i < sizeof(if_val); i++) {
ret = regmap_write(dev->regmap[2], 0x10 + i, if_val[i]);
if (ret)
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
case SYS_DVBT2:
for (i = 0; i < 7; i++) {
ret = regmap_write(dev->regmap[2], 0x13 + i,
conf_val_ptr[i]);
if (ret)
goto err;
}
break;
case SYS_DVBC_ANNEX_A:
ret = regmap_bulk_write(dev->regmap[1], 0x10, conf_val_ptr, 6);
if (ret)
goto err;
break;
default:
break;
}
ret = regmap_write(dev->regmap[2], 0x2d, reg_bank2_2d_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x2e, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x56, 0x0d);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap[0], 0x01,
"\xba\x13\x80\xba\x91\xdd\xe7\x28", 8);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x0a, 0x1a);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x13, 0x1f);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x19, 0x03);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x1d, 0xb0);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x2a, 0x72);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x2d, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x3c, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x3f, 0xf8);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap[0], 0x40, "\xf4\x08", 2);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xd2, reg_bank0_d2_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xd4, 0x55);
if (ret)
goto err;
ret = regmap_write(dev->regmap[1], 0xbe, 0x08);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xb2, 0x37);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xd7, 0x04);
if (ret)
goto err;
/* PLP */
if (c->delivery_system == SYS_DVBT2) {
ret = regmap_write(dev->regmap[2], 0x36,
(c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
c->stream_id );
if (ret)
goto err;
}
/* Reset FSM */
ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88473_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88473_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, stmp;
unsigned int utmp, utmp1, utmp2;
u8 buf[5];
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
/* Lock detection */
switch (c->delivery_system) {
case SYS_DVBT:
ret = regmap_read(dev->regmap[0], 0x62, &utmp);
if (ret)
goto err;
if (!(utmp & 0xa0)) {
if ((utmp & 0x0f) >= 0x09)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
else if ((utmp & 0x0f) >= 0x03)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
} else {
*status = 0;
}
break;
case SYS_DVBT2:
ret = regmap_read(dev->regmap[2], 0x8b, &utmp);
if (ret)
goto err;
if (!(utmp & 0x40)) {
if ((utmp & 0x0f) >= 0x0d)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
else if ((utmp & 0x0f) >= 0x0a)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
else if ((utmp & 0x0f) >= 0x07)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
} else {
*status = 0;
}
break;
case SYS_DVBC_ANNEX_A:
ret = regmap_read(dev->regmap[1], 0x85, &utmp);
if (ret)
goto err;
if (!(utmp & 0x40)) {
ret = regmap_read(dev->regmap[1], 0x89, &utmp);
if (ret)
goto err;
if (utmp & 0x01)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
} else {
*status = 0;
}
break;
default:
ret = -EINVAL;
goto err;
}
/* Signal strength */
if (*status & FE_HAS_SIGNAL) {
for (i = 0; i < 2; i++) {
ret = regmap_bulk_read(dev->regmap[2], 0x86 + i,
&buf[i], 1);
if (ret)
goto err;
}
/* AGCRD[15:6] gives us a 10bit value ([5:0] are always 0) */
utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
dev_dbg(&client->dev, "strength=%u\n", utmp1);
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = utmp1;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
/* DVB-T CNR */
ret = regmap_bulk_read(dev->regmap[0], 0x8f, buf, 2);
if (ret)
goto err;
utmp = buf[0] << 8 | buf[1] << 0;
if (utmp) {
/* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
/* log10(65536) = 80807124, 0.2 = 3355443 */
stmp = div_u64(((u64)80807124 - intlog10(utmp)
+ 3355443) * 10000, 1 << 24);
dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else if (*status & FE_HAS_VITERBI &&
c->delivery_system == SYS_DVBT2) {
/* DVB-T2 CNR */
for (i = 0; i < 3; i++) {
ret = regmap_bulk_read(dev->regmap[2], 0xb7 + i,
&buf[i], 1);
if (ret)
goto err;
}
utmp = buf[1] << 8 | buf[2] << 0;
utmp1 = (buf[0] >> 2) & 0x01; /* 0=SISO, 1=MISO */
if (utmp) {
if (utmp1) {
/* CNR[dB]: 10 * (log10(16384 / value) - 0.6) */
/* log10(16384) = 70706234, 0.6 = 10066330 */
stmp = div_u64(((u64)70706234 - intlog10(utmp)
- 10066330) * 10000, 1 << 24);
dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
stmp, utmp);
} else {
/* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
/* log10(65536) = 80807124, 0.2 = 3355443 */
stmp = div_u64(((u64)80807124 - intlog10(utmp)
+ 3355443) * 10000, 1 << 24);
dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
stmp, utmp);
}
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else if (*status & FE_HAS_VITERBI &&
c->delivery_system == SYS_DVBC_ANNEX_A) {
/* DVB-C CNR */
ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
if (ret)
goto err;
utmp1 = buf[0] << 8 | buf[1] << 0; /* signal */
utmp2 = buf[2] << 8 | buf[3] << 0; /* noise */
if (utmp1 && utmp2) {
/* CNR[dB]: 10 * log10(8 * (signal / noise)) */
/* log10(8) = 15151336 */
stmp = div_u64(((u64)15151336 + intlog10(utmp1)
- intlog10(utmp2)) * 10000, 1 << 24);
dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
stmp, utmp1, utmp2);
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (*status & FE_HAS_LOCK && (c->delivery_system == SYS_DVBT ||
c->delivery_system == SYS_DVBC_ANNEX_A)) {
/* DVB-T & DVB-C BER */
ret = regmap_bulk_read(dev->regmap[0], 0x92, buf, 5);
if (ret)
goto err;
utmp1 = buf[0] << 16 | buf[1] << 8 | buf[2] << 0;
utmp2 = buf[3] << 8 | buf[4] << 0;
utmp2 = utmp2 * 8 * 204;
dev_dbg(&client->dev, "post_bit_error=%u post_bit_count=%u\n",
utmp1, utmp2);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += utmp1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += utmp2;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* PER */
if (*status & FE_HAS_LOCK) {
ret = regmap_bulk_read(dev->regmap[0], 0xdd, buf, 4);
if (ret)
goto err;
utmp1 = buf[0] << 8 | buf[1] << 0;
utmp2 = buf[2] << 8 | buf[3] << 0;
dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
utmp1, utmp2);
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += utmp1;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += utmp2;
} else {
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88473_init(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88473_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, len, remain;
unsigned int uitmp;
const struct firmware *fw;
const char *name = MN88473_FIRMWARE;
dev_dbg(&client->dev, "\n");
/* Check if firmware is already running */
ret = regmap_read(dev->regmap[0], 0xf5, &uitmp);
if (ret)
goto err;
if (!(uitmp & 0x01))
goto warm;
/* Request the firmware, this will block and timeout */
ret = request_firmware(&fw, name, &client->dev);
if (ret) {
dev_err(&client->dev, "firmware file '%s' not found\n", name);
goto err;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
if (ret)
goto err_release_firmware;
for (remain = fw->size; remain > 0; remain -= (dev->i2c_wr_max - 1)) {
len = min(dev->i2c_wr_max - 1, remain);
ret = regmap_bulk_write(dev->regmap[0], 0xf6,
&fw->data[fw->size - remain], len);
if (ret) {
dev_err(&client->dev, "firmware download failed %d\n",
ret);
goto err_release_firmware;
}
}
release_firmware(fw);
/* Parity check of firmware */
ret = regmap_read(dev->regmap[0], 0xf8, &uitmp);
if (ret)
goto err;
if (uitmp & 0x10) {
dev_err(&client->dev, "firmware parity check failed\n");
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
if (ret)
goto err;
warm:
/* TS config */
ret = regmap_write(dev->regmap[2], 0x09, 0x08);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x08, 0x1d);
if (ret)
goto err;
dev->active = true;
/* init stats here to indicate which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
err_release_firmware:
release_firmware(fw);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88473_sleep(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88473_dev *dev = i2c_get_clientdata(client);
int ret;
dev_dbg(&client->dev, "\n");
dev->active = false;
ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_frontend_ops mn88473_ops = {
.delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
.info = {
.name = "Panasonic MN88473",
.symbol_rate_min = 1000000,
.symbol_rate_max = 7200000,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_2G_MODULATION |
FE_CAN_MULTISTREAM
},
.get_tune_settings = mn88473_get_tune_settings,
.init = mn88473_init,
.sleep = mn88473_sleep,
.set_frontend = mn88473_set_frontend,
.read_status = mn88473_read_status,
};
static int mn88473_probe(struct i2c_client *client)
{
struct mn88473_config *config = client->dev.platform_data;
struct mn88473_dev *dev;
int ret;
unsigned int uitmp;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
dev_dbg(&client->dev, "\n");
/* Caller really need to provide pointer for frontend we create */
if (config->fe == NULL) {
dev_err(&client->dev, "frontend pointer not defined\n");
ret = -EINVAL;
goto err;
}
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
goto err;
}
if (config->i2c_wr_max)
dev->i2c_wr_max = config->i2c_wr_max;
else
dev->i2c_wr_max = ~0;
if (config->xtal)
dev->clk = config->xtal;
else
dev->clk = 25000000;
dev->client[0] = client;
dev->regmap[0] = regmap_init_i2c(dev->client[0], ®map_config);
if (IS_ERR(dev->regmap[0])) {
ret = PTR_ERR(dev->regmap[0]);
goto err_kfree;
}
/*
* Chip has three I2C addresses for different register banks. Used
* addresses are 0x18, 0x1a and 0x1c. We register two dummy clients,
* 0x1a and 0x1c, in order to get own I2C client for each register bank.
*
* Also, register bank 2 do not support sequential I/O. Only single
* register write or read is allowed to that bank.
*/
dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a);
if (IS_ERR(dev->client[1])) {
ret = PTR_ERR(dev->client[1]);
dev_err(&client->dev, "I2C registration failed\n");
goto err_regmap_0_regmap_exit;
}
dev->regmap[1] = regmap_init_i2c(dev->client[1], ®map_config);
if (IS_ERR(dev->regmap[1])) {
ret = PTR_ERR(dev->regmap[1]);
goto err_client_1_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[1], dev);
dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c);
if (IS_ERR(dev->client[2])) {
ret = PTR_ERR(dev->client[2]);
dev_err(&client->dev, "2nd I2C registration failed\n");
goto err_regmap_1_regmap_exit;
}
dev->regmap[2] = regmap_init_i2c(dev->client[2], ®map_config);
if (IS_ERR(dev->regmap[2])) {
ret = PTR_ERR(dev->regmap[2]);
goto err_client_2_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[2], dev);
/* Check demod answers with correct chip id */
ret = regmap_read(dev->regmap[2], 0xff, &uitmp);
if (ret)
goto err_regmap_2_regmap_exit;
dev_dbg(&client->dev, "chip id=%02x\n", uitmp);
if (uitmp != 0x03) {
ret = -ENODEV;
goto err_regmap_2_regmap_exit;
}
/* Sleep because chip is active by default */
ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
if (ret)
goto err_regmap_2_regmap_exit;
/* Create dvb frontend */
memcpy(&dev->frontend.ops, &mn88473_ops, sizeof(dev->frontend.ops));
dev->frontend.demodulator_priv = client;
*config->fe = &dev->frontend;
i2c_set_clientdata(client, dev);
dev_info(&client->dev, "Panasonic MN88473 successfully identified\n");
return 0;
err_regmap_2_regmap_exit:
regmap_exit(dev->regmap[2]);
err_client_2_i2c_unregister_device:
i2c_unregister_device(dev->client[2]);
err_regmap_1_regmap_exit:
regmap_exit(dev->regmap[1]);
err_client_1_i2c_unregister_device:
i2c_unregister_device(dev->client[1]);
err_regmap_0_regmap_exit:
regmap_exit(dev->regmap[0]);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void mn88473_remove(struct i2c_client *client)
{
struct mn88473_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
regmap_exit(dev->regmap[2]);
i2c_unregister_device(dev->client[2]);
regmap_exit(dev->regmap[1]);
i2c_unregister_device(dev->client[1]);
regmap_exit(dev->regmap[0]);
kfree(dev);
}
static const struct i2c_device_id mn88473_id_table[] = {
{"mn88473", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, mn88473_id_table);
static struct i2c_driver mn88473_driver = {
.driver = {
.name = "mn88473",
.suppress_bind_attrs = true,
},
.probe = mn88473_probe,
.remove = mn88473_remove,
.id_table = mn88473_id_table,
};
module_i2c_driver(mn88473_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Panasonic MN88473 DVB-T/T2/C demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(MN88473_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/mn88473.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
*
* Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "dib9000.h"
#include "dibx000_common.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
#define MAX_NUMBER_OF_FRONTENDS 6
struct i2c_device {
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
u8 *i2c_read_buffer;
u8 *i2c_write_buffer;
};
struct dib9000_pid_ctrl {
#define DIB9000_PID_FILTER_CTRL 0
#define DIB9000_PID_FILTER 1
u8 cmd;
u8 id;
u16 pid;
u8 onoff;
};
struct dib9000_state {
struct i2c_device i2c;
struct dibx000_i2c_master i2c_master;
struct i2c_adapter tuner_adap;
struct i2c_adapter component_bus;
u16 revision;
u8 reg_offs;
enum frontend_tune_state tune_state;
u32 status;
struct dvb_frontend_parametersContext channel_status;
u8 fe_id;
#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
u16 gpio_dir;
#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
u16 gpio_val;
#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
u16 gpio_pwm_pos;
union { /* common for all chips */
struct {
u8 mobile_mode:1;
} host;
struct {
struct dib9000_fe_memory_map {
u16 addr;
u16 size;
} fe_mm[18];
u8 memcmd;
struct mutex mbx_if_lock; /* to protect read/write operations */
struct mutex mbx_lock; /* to protect the whole mailbox handling */
struct mutex mem_lock; /* to protect the memory accesses */
struct mutex mem_mbx_lock; /* to protect the memory-based mailbox */
#define MBX_MAX_WORDS (256 - 200 - 2)
#define DIB9000_MSG_CACHE_SIZE 2
u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
u8 fw_is_running;
} risc;
} platform;
union { /* common for all platforms */
struct {
struct dib9000_config cfg;
} d9;
} chip;
struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
u16 component_bus_speed;
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[255];
u8 i2c_read_buffer[255];
struct mutex demod_lock;
u8 get_frontend_internal;
struct dib9000_pid_ctrl pid_ctrl[10];
s8 pid_ctrl_index; /* -1: empty list; -2: do not use the list */
};
static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
};
enum dib9000_power_mode {
DIB9000_POWER_ALL = 0,
DIB9000_POWER_NO,
DIB9000_POWER_INTERF_ANALOG_AGC,
DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
DIB9000_POWER_INTERFACE_ONLY,
};
enum dib9000_out_messages {
OUT_MSG_HBM_ACK,
OUT_MSG_HOST_BUF_FAIL,
OUT_MSG_REQ_VERSION,
OUT_MSG_BRIDGE_I2C_W,
OUT_MSG_BRIDGE_I2C_R,
OUT_MSG_BRIDGE_APB_W,
OUT_MSG_BRIDGE_APB_R,
OUT_MSG_SCAN_CHANNEL,
OUT_MSG_MONIT_DEMOD,
OUT_MSG_CONF_GPIO,
OUT_MSG_DEBUG_HELP,
OUT_MSG_SUBBAND_SEL,
OUT_MSG_ENABLE_TIME_SLICE,
OUT_MSG_FE_FW_DL,
OUT_MSG_FE_CHANNEL_SEARCH,
OUT_MSG_FE_CHANNEL_TUNE,
OUT_MSG_FE_SLEEP,
OUT_MSG_FE_SYNC,
OUT_MSG_CTL_MONIT,
OUT_MSG_CONF_SVC,
OUT_MSG_SET_HBM,
OUT_MSG_INIT_DEMOD,
OUT_MSG_ENABLE_DIVERSITY,
OUT_MSG_SET_OUTPUT_MODE,
OUT_MSG_SET_PRIORITARY_CHANNEL,
OUT_MSG_ACK_FRG,
OUT_MSG_INIT_PMU,
};
enum dib9000_in_messages {
IN_MSG_DATA,
IN_MSG_FRAME_INFO,
IN_MSG_CTL_MONIT,
IN_MSG_ACK_FREE_ITEM,
IN_MSG_DEBUG_BUF,
IN_MSG_MPE_MONITOR,
IN_MSG_RAWTS_MONITOR,
IN_MSG_END_BRIDGE_I2C_RW,
IN_MSG_END_BRIDGE_APB_RW,
IN_MSG_VERSION,
IN_MSG_END_OF_SCAN,
IN_MSG_MONIT_DEMOD,
IN_MSG_ERROR,
IN_MSG_FE_FW_DL_DONE,
IN_MSG_EVENT,
IN_MSG_ACK_CHANGE_SVC,
IN_MSG_HBM_PROF,
};
/* memory_access requests */
#define FE_MM_W_CHANNEL 0
#define FE_MM_W_FE_INFO 1
#define FE_MM_RW_SYNC 2
#define FE_SYNC_CHANNEL 1
#define FE_SYNC_W_GENERIC_MONIT 2
#define FE_SYNC_COMPONENT_ACCESS 3
#define FE_MM_R_CHANNEL_SEARCH_STATE 3
#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
#define FE_MM_R_FE_INFO 5
#define FE_MM_R_FE_MONITOR 6
#define FE_MM_W_CHANNEL_HEAD 7
#define FE_MM_W_CHANNEL_UNION 8
#define FE_MM_W_CHANNEL_CONTEXT 9
#define FE_MM_R_CHANNEL_UNION 10
#define FE_MM_R_CHANNEL_CONTEXT 11
#define FE_MM_R_CHANNEL_TUNE_STATE 12
#define FE_MM_R_GENERIC_MONITORING_SIZE 13
#define FE_MM_W_GENERIC_MONITORING 14
#define FE_MM_R_GENERIC_MONITORING 15
#define FE_MM_W_COMPONENT_ACCESS 16
#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
static u16 to_fw_output_mode(u16 mode)
{
switch (mode) {
case OUTMODE_HIGH_Z:
return 0;
case OUTMODE_MPEG2_PAR_GATED_CLK:
return 4;
case OUTMODE_MPEG2_PAR_CONT_CLK:
return 8;
case OUTMODE_MPEG2_SERIAL:
return 16;
case OUTMODE_DIVERSITY:
return 128;
case OUTMODE_MPEG2_FIFO:
return 2;
case OUTMODE_ANALOG_ADC:
return 1;
default:
return 0;
}
}
static int dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 *b, u32 len, u16 attribute)
{
u32 chunk_size = 126;
u32 l;
int ret;
if (state->platform.risc.fw_is_running && (reg < 1024))
return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 2;
state->msg[1].addr = state->i2c.i2c_addr >> 1;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = b;
state->msg[1].len = len;
state->i2c_write_buffer[0] = reg >> 8;
state->i2c_write_buffer[1] = reg & 0xff;
if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
state->i2c_write_buffer[0] |= (1 << 5);
if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
state->i2c_write_buffer[0] |= (1 << 4);
do {
l = min(len, chunk_size);
state->msg[1].len = l;
state->msg[1].buf = b;
ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0;
if (ret != 0) {
dprintk("i2c read error on %d\n", reg);
return -EREMOTEIO;
}
b += l;
len -= l;
if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
reg += l / 2;
} while ((ret == 0) && len);
return 0;
}
static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
{
struct i2c_msg msg[2] = {
{.addr = i2c->i2c_addr >> 1, .flags = 0,
.buf = i2c->i2c_write_buffer, .len = 2},
{.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD,
.buf = i2c->i2c_read_buffer, .len = 2},
};
i2c->i2c_write_buffer[0] = reg >> 8;
i2c->i2c_write_buffer[1] = reg & 0xff;
if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
dprintk("read register %x error\n", reg);
return 0;
}
return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1];
}
static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
{
if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0)
return 0;
return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
{
if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2,
attribute) != 0)
return 0;
return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
static int dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 *buf, u32 len, u16 attribute)
{
u32 chunk_size = 126;
u32 l;
int ret;
if (state->platform.risc.fw_is_running && (reg < 1024)) {
if (dib9000_risc_apb_access_write
(state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
return -EINVAL;
return 0;
}
memset(&state->msg[0], 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = len + 2;
state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
state->i2c_write_buffer[1] = (reg) & 0xff;
if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
state->i2c_write_buffer[0] |= (1 << 5);
if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
state->i2c_write_buffer[0] |= (1 << 4);
do {
l = min(len, chunk_size);
state->msg[0].len = l + 2;
memcpy(&state->i2c_write_buffer[2], buf, l);
ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
buf += l;
len -= l;
if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
reg += l / 2;
} while ((ret == 0) && len);
return ret;
}
static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
{
struct i2c_msg msg = {
.addr = i2c->i2c_addr >> 1, .flags = 0,
.buf = i2c->i2c_write_buffer, .len = 4
};
i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff;
i2c->i2c_write_buffer[1] = reg & 0xff;
i2c->i2c_write_buffer[2] = (val >> 8) & 0xff;
i2c->i2c_write_buffer[3] = val & 0xff;
return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
}
static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
{
u8 b[2] = { val >> 8, val & 0xff };
return dib9000_write16_attr(state, reg, b, 2, 0);
}
static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
{
u8 b[2] = { val >> 8, val & 0xff };
return dib9000_write16_attr(state, reg, b, 2, attribute);
}
#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
#define MAC_IRQ (1 << 1)
#define IRQ_POL_MSK (1 << 4)
#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
{
u8 b[14] = { 0 };
/* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
/* b[0] = 0 << 7; */
b[1] = 1;
/* b[2] = 0; */
/* b[3] = 0; */
b[4] = (u8) (addr >> 8);
b[5] = (u8) (addr & 0xff);
/* b[10] = 0; */
/* b[11] = 0; */
b[12] = (u8) (addr >> 8);
b[13] = (u8) (addr & 0xff);
addr += len;
/* b[6] = 0; */
/* b[7] = 0; */
b[8] = (u8) (addr >> 8);
b[9] = (u8) (addr & 0xff);
dib9000_write(state, 1056, b, 14);
if (reading)
dib9000_write_word(state, 1056, (1 << 15) | 1);
state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
}
static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
{
struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
/* decide whether we need to "refresh" the memory controller */
if (state->platform.risc.memcmd == cmd && /* same command */
!(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
return;
dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
state->platform.risc.memcmd = cmd;
}
static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
{
if (!state->platform.risc.fw_is_running)
return -EIO;
if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
dib9000_risc_mem_setup(state, cmd | 0x80);
dib9000_risc_mem_read_chunks(state, b, len);
mutex_unlock(&state->platform.risc.mem_lock);
return 0;
}
static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
{
struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
if (!state->platform.risc.fw_is_running)
return -EIO;
if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
dib9000_risc_mem_setup(state, cmd);
dib9000_risc_mem_write_chunks(state, b, m->size);
mutex_unlock(&state->platform.risc.mem_lock);
return 0;
}
static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
{
u16 offs;
if (risc_id == 1)
offs = 16;
else
offs = 0;
/* config crtl reg */
dib9000_write_word(state, 1024 + offs, 0x000f);
dib9000_write_word(state, 1025 + offs, 0);
dib9000_write_word(state, 1031 + offs, key);
dprintk("going to download %dB of microcode\n", len);
if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
dprintk("error while downloading microcode for RISC %c\n", 'A' + risc_id);
return -EIO;
}
dprintk("Microcode for RISC %c loaded\n", 'A' + risc_id);
return 0;
}
static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
{
u16 mbox_offs;
u16 reset_reg;
u16 tries = 1000;
if (risc_id == 1)
mbox_offs = 16;
else
mbox_offs = 0;
/* Reset mailbox */
dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
/* Read reset status */
do {
reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
msleep(100);
} while ((reset_reg & 0x8000) && --tries);
if (reset_reg & 0x8000) {
dprintk("MBX: init ERROR, no response from RISC %c\n", 'A' + risc_id);
return -EIO;
}
dprintk("MBX: initialized\n");
return 0;
}
#define MAX_MAILBOX_TRY 100
static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
{
u8 *d, b[2];
u16 tmp;
u16 size;
u32 i;
int ret = 0;
if (!state->platform.risc.fw_is_running)
return -EINVAL;
if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
tmp = MAX_MAILBOX_TRY;
do {
size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
dprintk("MBX: RISC mbx full, retrying\n");
msleep(100);
} else
break;
} while (1);
/*dprintk( "MBX: size: %d\n", size); */
if (tmp == 0) {
ret = -EINVAL;
goto out;
}
#ifdef DUMP_MSG
dprintk("--> %02x %d %*ph\n", id, len + 1, len, data);
#endif
/* byte-order conversion - works on big (where it is not necessary) or little endian */
d = (u8 *) data;
for (i = 0; i < len; i++) {
tmp = data[i];
*d++ = tmp >> 8;
*d++ = tmp & 0xff;
}
/* write msg */
b[0] = id;
b[1] = len + 1;
if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
ret = -EIO;
goto out;
}
/* update register nb_mes_in_RX */
ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
out:
mutex_unlock(&state->platform.risc.mbx_if_lock);
return ret;
}
static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
{
#ifdef DUMP_MSG
u16 *d = data;
#endif
u16 tmp, i;
u8 size;
u8 mc_base;
if (!state->platform.risc.fw_is_running)
return 0;
if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
dprintk("could not get the lock\n");
return 0;
}
if (risc_id == 1)
mc_base = 16;
else
mc_base = 0;
/* Length and type in the first word */
*data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
size = *data & 0xff;
if (size <= MBX_MAX_WORDS) {
data++;
size--; /* Initial word already read */
dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
/* to word conversion */
for (i = 0; i < size; i++) {
tmp = *data;
*data = (tmp >> 8) | (tmp << 8);
data++;
}
#ifdef DUMP_MSG
dprintk("<--\n");
for (i = 0; i < size + 1; i++)
dprintk("%04x\n", d[i]);
dprintk("\n");
#endif
} else {
dprintk("MBX: message is too big for message cache (%d), flushing message\n", size);
size--; /* Initial word already read */
while (size--)
dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
}
/* Update register nb_mes_in_TX */
dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
mutex_unlock(&state->platform.risc.mbx_if_lock);
return size + 1;
}
static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
{
u32 ts = data[1] << 16 | data[0];
char *b = (char *)&data[2];
b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
if (*b == '~') {
b++;
dprintk("%s\n", b);
} else
dprintk("RISC%d: %d.%04d %s\n",
state->fe_id,
ts / 10000, ts % 10000, *b ? b : "<empty>");
return 1;
}
static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
{
int i;
u8 size;
u16 *block;
/* find a free slot */
for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
block = state->platform.risc.message_cache[i];
if (*block == 0) {
size = dib9000_mbx_read(state, block, 1, attr);
/* dprintk( "MBX: fetched %04x message to cache\n", *block); */
switch (*block >> 8) {
case IN_MSG_DEBUG_BUF:
dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
*block = 0; /* free the block */
break;
#if 0
case IN_MSG_DATA: /* FE-TRACE */
dib9000_risc_data_process(state, block + 1, size);
*block = 0;
break;
#endif
default:
break;
}
return 1;
}
}
dprintk("MBX: no free cache-slot found for new message...\n");
return -1;
}
static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
{
if (risc_id == 0)
return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
else
return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
}
static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
{
int ret = 0;
if (!state->platform.risc.fw_is_running)
return -1;
if (mutex_lock_interruptible(&state->platform.risc.mbx_lock) < 0) {
dprintk("could not get the lock\n");
return -1;
}
if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
ret = dib9000_mbx_fetch_to_cache(state, attr);
dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
/* if (tmp) */
/* dprintk( "cleared IRQ: %x\n", tmp); */
mutex_unlock(&state->platform.risc.mbx_lock);
return ret;
}
static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
{
u8 i;
u16 *block;
u16 timeout = 30;
*msg = 0;
do {
/* dib9000_mbx_get_from_cache(); */
for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
block = state->platform.risc.message_cache[i];
if ((*block >> 8) == id) {
*size = (*block & 0xff) - 1;
memcpy(msg, block + 1, (*size) * 2);
*block = 0; /* free the block */
i = 0; /* signal that we found a message */
break;
}
}
if (i == 0)
break;
if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
return -1;
} while (--timeout);
if (timeout == 0) {
dprintk("waiting for message %d timed out\n", id);
return -1;
}
return i == 0;
}
static int dib9000_risc_check_version(struct dib9000_state *state)
{
u8 r[4];
u8 size;
u16 fw_version = 0;
if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
return -EIO;
if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
return -EIO;
fw_version = (r[0] << 8) | r[1];
dprintk("RISC: ver: %d.%02d (IC: %d)\n", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
if ((fw_version >> 10) != 7)
return -EINVAL;
switch (fw_version & 0x3ff) {
case 11:
case 12:
case 14:
case 15:
case 16:
case 17:
break;
default:
dprintk("RISC: invalid firmware version");
return -EINVAL;
}
dprintk("RISC: valid firmware version");
return 0;
}
static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
{
/* Reconfig pool mac ram */
dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
dib9000_write_word(state, 1226, 0x05);
/* Toggles IP crypto to Host APB interface. */
dib9000_write_word(state, 1542, 1);
/* Set jump and no jump in the dma box */
dib9000_write_word(state, 1074, 0);
dib9000_write_word(state, 1075, 0);
/* Set MAC as APB Master. */
dib9000_write_word(state, 1237, 0);
/* Reset the RISCs */
if (codeA != NULL)
dib9000_write_word(state, 1024, 2);
else
dib9000_write_word(state, 1024, 15);
if (codeB != NULL)
dib9000_write_word(state, 1040, 2);
if (codeA != NULL)
dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
if (codeB != NULL)
dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
/* Run the RISCs */
if (codeA != NULL)
dib9000_write_word(state, 1024, 0);
if (codeB != NULL)
dib9000_write_word(state, 1040, 0);
if (codeA != NULL)
if (dib9000_mbx_host_init(state, 0) != 0)
return -EIO;
if (codeB != NULL)
if (dib9000_mbx_host_init(state, 1) != 0)
return -EIO;
msleep(100);
state->platform.risc.fw_is_running = 1;
if (dib9000_risc_check_version(state) != 0)
return -EINVAL;
state->platform.risc.memcmd = 0xff;
return 0;
}
static u16 dib9000_identify(struct i2c_device *client)
{
u16 value;
value = dib9000_i2c_read16(client, 896);
if (value != 0x01b3) {
dprintk("wrong Vendor ID (0x%x)\n", value);
return 0;
}
value = dib9000_i2c_read16(client, 897);
if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
dprintk("wrong Device ID (0x%x)\n", value);
return 0;
}
/* protect this driver to be used with 7000PC */
if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
dprintk("this driver does not work with DiB7000PC\n");
return 0;
}
switch (value) {
case 0x4000:
dprintk("found DiB7000MA/PA/MB/PB\n");
break;
case 0x4001:
dprintk("found DiB7000HC\n");
break;
case 0x4002:
dprintk("found DiB7000MC\n");
break;
case 0x4003:
dprintk("found DiB9000A\n");
break;
case 0x4004:
dprintk("found DiB9000H\n");
break;
case 0x4005:
dprintk("found DiB9000M\n");
break;
}
return value;
}
static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
{
/* by default everything is going to be powered off */
u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
u8 offset;
if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
offset = 1;
else
offset = 0;
reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
case DIB9000_POWER_ALL:
reg_903 = 0x0000;
reg_904 = 0x0000;
reg_905 = 0x0000;
reg_906 = 0x0000;
break;
/* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
break;
case DIB9000_POWER_INTERF_ANALOG_AGC:
reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
reg_906 &= ~((1 << 0));
break;
case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
reg_903 = 0x0000;
reg_904 = 0x801f;
reg_905 = 0x0000;
reg_906 &= ~((1 << 0));
break;
case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
reg_903 = 0x0000;
reg_904 = 0x8000;
reg_905 = 0x010b;
reg_906 &= ~((1 << 0));
break;
default:
case DIB9000_POWER_NO:
break;
}
/* always power down unused parts */
if (!state->platform.host.mobile_mode)
reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
/* P_sdio_select_clk = 0 on MC and after */
if (state->revision != 0x4000)
reg_906 <<= 1;
dib9000_write_word(state, 903 + offset, reg_903);
dib9000_write_word(state, 904 + offset, reg_904);
dib9000_write_word(state, 905 + offset, reg_905);
dib9000_write_word(state, 906 + offset, reg_906);
}
static int dib9000_fw_reset(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
dib9000_write_word(state, 1817, 0x0003);
dib9000_write_word(state, 1227, 1);
dib9000_write_word(state, 1227, 0);
switch ((state->revision = dib9000_identify(&state->i2c))) {
case 0x4003:
case 0x4004:
case 0x4005:
state->reg_offs = 1;
break;
default:
return -EINVAL;
}
/* reset the i2c-master to use the host interface */
dibx000_reset_i2c_master(&state->i2c_master);
dib9000_set_power_mode(state, DIB9000_POWER_ALL);
/* unforce divstr regardless whether i2c enumeration was done or not */
dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
dib9000_write_word(state, 1796, 0);
dib9000_write_word(state, 1805, 0x805);
/* restart all parts */
dib9000_write_word(state, 898, 0xffff);
dib9000_write_word(state, 899, 0xffff);
dib9000_write_word(state, 900, 0x0001);
dib9000_write_word(state, 901, 0xff19);
dib9000_write_word(state, 902, 0x003c);
dib9000_write_word(state, 898, 0);
dib9000_write_word(state, 899, 0);
dib9000_write_word(state, 900, 0);
dib9000_write_word(state, 901, 0);
dib9000_write_word(state, 902, 0);
dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
return 0;
}
static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
{
u16 mb[10];
u8 i, s;
if (address >= 1024 || !state->platform.risc.fw_is_running)
return -EINVAL;
/* dprintk( "APB access through rd fw %d %x\n", address, attribute); */
mb[0] = (u16) address;
mb[1] = len / 2;
dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
case 1:
s--;
for (i = 0; i < s; i++) {
b[i * 2] = (mb[i + 1] >> 8) & 0xff;
b[i * 2 + 1] = (mb[i + 1]) & 0xff;
}
return 0;
default:
return -EIO;
}
return -EIO;
}
static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
{
u16 mb[10];
u8 s, i;
if (address >= 1024 || !state->platform.risc.fw_is_running)
return -EINVAL;
if (len > 18)
return -EINVAL;
/* dprintk( "APB access through wr fw %d %x\n", address, attribute); */
mb[0] = (u16)address;
for (i = 0; i + 1 < len; i += 2)
mb[1 + i / 2] = b[i] << 8 | b[i + 1];
if (len & 1)
mb[1 + len / 2] = b[len - 1] << 8;
dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, (3 + len) / 2, attribute);
return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
}
static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
{
u8 index_loop = 10;
if (!state->platform.risc.fw_is_running)
return 0;
dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
do {
dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1);
} while (state->i2c_read_buffer[0] && index_loop--);
if (index_loop > 0)
return 0;
return -EIO;
}
static int dib9000_fw_init(struct dib9000_state *state)
{
struct dibGPIOFunction *f;
u16 b[40] = { 0 };
u8 i;
u8 size;
if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
return -EIO;
/* initialize the firmware */
for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
f = &state->chip.d9.cfg.gpio_function[i];
if (f->mask) {
switch (f->function) {
case BOARD_GPIO_FUNCTION_COMPONENT_ON:
b[0] = (u16) f->mask;
b[1] = (u16) f->direction;
b[2] = (u16) f->value;
break;
case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
b[3] = (u16) f->mask;
b[4] = (u16) f->direction;
b[5] = (u16) f->value;
break;
}
}
}
if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
return -EIO;
/* subband */
b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
}
b[1 + i * 4] = 0; /* fe_id */
if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
return -EIO;
/* 0 - id, 1 - no_of_frontends */
b[0] = (0 << 8) | 1;
/* 0 = i2c-address demod, 0 = tuner */
b[1] = (0 << 8) | (0);
b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
b[29] = state->chip.d9.cfg.if_drives;
if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
return -EIO;
if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
return -EIO;
if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
return -EIO;
if (size > ARRAY_SIZE(b)) {
dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
(int)ARRAY_SIZE(b));
return -EINVAL;
}
for (i = 0; i < size; i += 2) {
state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
state->platform.risc.fe_mm[i / 2].size = b[i + 1];
}
return 0;
}
static void dib9000_fw_set_channel_head(struct dib9000_state *state)
{
u8 b[9];
u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
if (state->fe_id % 2)
freq += 101;
b[0] = (u8) ((freq >> 0) & 0xff);
b[1] = (u8) ((freq >> 8) & 0xff);
b[2] = (u8) ((freq >> 16) & 0xff);
b[3] = (u8) ((freq >> 24) & 0xff);
b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
b[8] |= 1;
dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
}
static int dib9000_fw_get_channel(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
struct dibDVBTChannel {
s8 spectrum_inversion;
s8 nfft;
s8 guard;
s8 constellation;
s8 hrch;
s8 alpha;
s8 code_rate_hp;
s8 code_rate_lp;
s8 select_hp;
s8 intlv_native;
};
struct dibDVBTChannel *ch;
int ret = 0;
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
ret = -EIO;
goto error;
}
dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION,
state->i2c_read_buffer, sizeof(struct dibDVBTChannel));
ch = (struct dibDVBTChannel *)state->i2c_read_buffer;
switch (ch->spectrum_inversion & 0x7) {
case 1:
state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
break;
case 0:
state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
break;
}
switch (ch->nfft) {
case 0:
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
break;
case 2:
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
break;
case 1:
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
break;
}
switch (ch->guard) {
case 0:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
break;
}
switch (ch->constellation) {
case 2:
state->fe[0]->dtv_property_cache.modulation = QAM_64;
break;
case 1:
state->fe[0]->dtv_property_cache.modulation = QAM_16;
break;
case 0:
state->fe[0]->dtv_property_cache.modulation = QPSK;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
break;
}
switch (ch->hrch) {
case 0:
state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
break;
case 1:
state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
break;
}
switch (ch->code_rate_hp) {
case 1:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
break;
case 2:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
break;
case 3:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
break;
case 5:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
break;
case 7:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
break;
}
switch (ch->code_rate_lp) {
case 1:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
break;
case 2:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
break;
case 3:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
break;
case 5:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
break;
case 7:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
break;
default:
case -1:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
break;
}
error:
mutex_unlock(&state->platform.risc.mem_mbx_lock);
return ret;
}
static int dib9000_fw_set_channel_union(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
struct dibDVBTChannel {
s8 spectrum_inversion;
s8 nfft;
s8 guard;
s8 constellation;
s8 hrch;
s8 alpha;
s8 code_rate_hp;
s8 code_rate_lp;
s8 select_hp;
s8 intlv_native;
};
struct dibDVBTChannel ch;
switch (state->fe[0]->dtv_property_cache.inversion) {
case INVERSION_ON:
ch.spectrum_inversion = 1;
break;
case INVERSION_OFF:
ch.spectrum_inversion = 0;
break;
default:
case INVERSION_AUTO:
ch.spectrum_inversion = -1;
break;
}
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
ch.nfft = 0;
break;
case TRANSMISSION_MODE_4K:
ch.nfft = 2;
break;
case TRANSMISSION_MODE_8K:
ch.nfft = 1;
break;
default:
case TRANSMISSION_MODE_AUTO:
ch.nfft = 1;
break;
}
switch (state->fe[0]->dtv_property_cache.guard_interval) {
case GUARD_INTERVAL_1_32:
ch.guard = 0;
break;
case GUARD_INTERVAL_1_16:
ch.guard = 1;
break;
case GUARD_INTERVAL_1_8:
ch.guard = 2;
break;
case GUARD_INTERVAL_1_4:
ch.guard = 3;
break;
default:
case GUARD_INTERVAL_AUTO:
ch.guard = -1;
break;
}
switch (state->fe[0]->dtv_property_cache.modulation) {
case QAM_64:
ch.constellation = 2;
break;
case QAM_16:
ch.constellation = 1;
break;
case QPSK:
ch.constellation = 0;
break;
default:
case QAM_AUTO:
ch.constellation = -1;
break;
}
switch (state->fe[0]->dtv_property_cache.hierarchy) {
case HIERARCHY_NONE:
ch.hrch = 0;
break;
case HIERARCHY_1:
case HIERARCHY_2:
case HIERARCHY_4:
ch.hrch = 1;
break;
default:
case HIERARCHY_AUTO:
ch.hrch = -1;
break;
}
ch.alpha = 1;
switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
case FEC_1_2:
ch.code_rate_hp = 1;
break;
case FEC_2_3:
ch.code_rate_hp = 2;
break;
case FEC_3_4:
ch.code_rate_hp = 3;
break;
case FEC_5_6:
ch.code_rate_hp = 5;
break;
case FEC_7_8:
ch.code_rate_hp = 7;
break;
default:
case FEC_AUTO:
ch.code_rate_hp = -1;
break;
}
switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
case FEC_1_2:
ch.code_rate_lp = 1;
break;
case FEC_2_3:
ch.code_rate_lp = 2;
break;
case FEC_3_4:
ch.code_rate_lp = 3;
break;
case FEC_5_6:
ch.code_rate_lp = 5;
break;
case FEC_7_8:
ch.code_rate_lp = 7;
break;
default:
case FEC_AUTO:
ch.code_rate_lp = -1;
break;
}
ch.select_hp = 1;
ch.intlv_native = 1;
dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
return 0;
}
static int dib9000_fw_tune(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
s8 i;
switch (state->tune_state) {
case CT_DEMOD_START:
dib9000_fw_set_channel_head(state);
/* write the channel context - a channel is initialized to 0, so it is OK */
dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
if (search)
dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
else {
dib9000_fw_set_channel_union(fe);
dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
}
state->tune_state = CT_DEMOD_STEP_1;
break;
case CT_DEMOD_STEP_1:
if (search)
dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1);
else
dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1);
i = (s8)state->i2c_read_buffer[0];
switch (i) { /* something happened */
case 0:
break;
case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
if (search)
state->status = FE_STATUS_DEMOD_SUCCESS;
else {
state->tune_state = CT_DEMOD_STOP;
state->status = FE_STATUS_LOCKED;
}
break;
default:
state->status = FE_STATUS_TUNE_FAILED;
state->tune_state = CT_DEMOD_STOP;
break;
}
break;
default:
ret = FE_CALLBACK_TIME_NEVER;
break;
}
return ret;
}
static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 mode = (u16) onoff;
return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
}
static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 outreg, smo_mode;
dprintk("setting output mode for demod %p to %d\n", fe, mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK:
outreg = (1 << 10); /* 0x0400 */
break;
case OUTMODE_MPEG2_PAR_CONT_CLK:
outreg = (1 << 10) | (1 << 6); /* 0x0440 */
break;
case OUTMODE_MPEG2_SERIAL:
outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
break;
case OUTMODE_DIVERSITY:
outreg = (1 << 10) | (4 << 6); /* 0x0500 */
break;
case OUTMODE_MPEG2_FIFO:
outreg = (1 << 10) | (5 << 6);
break;
case OUTMODE_HIGH_Z:
outreg = 0;
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->fe[0]);
return -EINVAL;
}
dib9000_write_word(state, 1795, outreg);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK:
case OUTMODE_MPEG2_PAR_CONT_CLK:
case OUTMODE_MPEG2_SERIAL:
case OUTMODE_MPEG2_FIFO:
smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
dib9000_write_word(state, 295, smo_mode);
break;
}
outreg = to_fw_output_mode(mode);
return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
}
static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
u16 i, len, t, index_msg;
for (index_msg = 0; index_msg < num; index_msg++) {
if (msg[index_msg].flags & I2C_M_RD) { /* read */
len = msg[index_msg].len;
if (len > 16)
len = 16;
if (dib9000_read_word(state, 790) != 0)
dprintk("TunerITF: read busy\n");
dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
dib9000_write_word(state, 787, (len / 2) - 1);
dib9000_write_word(state, 786, 1); /* start read */
i = 1000;
while (dib9000_read_word(state, 790) != (len / 2) && i)
i--;
if (i == 0)
dprintk("TunerITF: read failed\n");
for (i = 0; i < len; i += 2) {
t = dib9000_read_word(state, 785);
msg[index_msg].buf[i] = (t >> 8) & 0xff;
msg[index_msg].buf[i + 1] = (t) & 0xff;
}
if (dib9000_read_word(state, 790) != 0)
dprintk("TunerITF: read more data than expected\n");
} else {
i = 1000;
while (dib9000_read_word(state, 789) && i)
i--;
if (i == 0)
dprintk("TunerITF: write busy\n");
len = msg[index_msg].len;
if (len > 16)
len = 16;
for (i = 0; i < len; i += 2)
dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
dib9000_write_word(state, 787, (len / 2) - 1);
dib9000_write_word(state, 786, 0); /* start write */
i = 1000;
while (dib9000_read_word(state, 791) > 0 && i)
i--;
if (i == 0)
dprintk("TunerITF: write failed\n");
}
}
return num;
}
int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
{
struct dib9000_state *state = fe->demodulator_priv;
state->component_bus_speed = speed;
return 0;
}
EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
u8 type = 0; /* I2C */
u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
u16 scl = state->component_bus_speed; /* SCL frequency */
struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
u8 p[13] = { 0 };
p[0] = type;
p[1] = port;
p[2] = msg[0].addr << 1;
p[3] = (u8) scl & 0xff; /* scl */
p[4] = (u8) (scl >> 8);
p[7] = 0;
p[8] = 0;
p[9] = (u8) (msg[0].len);
p[10] = (u8) (msg[0].len >> 8);
if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
p[11] = (u8) (msg[1].len);
p[12] = (u8) (msg[1].len >> 8);
} else {
p[11] = 0;
p[12] = 0;
}
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
return 0;
}
dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
{ /* write-part */
dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
}
/* do the transaction */
if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
mutex_unlock(&state->platform.risc.mem_mbx_lock);
return 0;
}
/* read back any possible result */
if ((num > 1) && (msg[1].flags & I2C_M_RD))
dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
mutex_unlock(&state->platform.risc.mem_mbx_lock);
return num;
}
static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm dib9000_tuner_algo = {
.master_xfer = dib9000_tuner_xfer,
.functionality = dib9000_i2c_func,
};
static const struct i2c_algorithm dib9000_component_bus_algo = {
.master_xfer = dib9000_fw_component_bus_xfer,
.functionality = dib9000_i2c_func,
};
struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
{
struct dib9000_state *st = fe->demodulator_priv;
return &st->tuner_adap;
}
EXPORT_SYMBOL(dib9000_get_tuner_interface);
struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
{
struct dib9000_state *st = fe->demodulator_priv;
return &st->component_bus;
}
EXPORT_SYMBOL(dib9000_get_component_bus_interface);
struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
{
struct dib9000_state *st = fe->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
}
EXPORT_SYMBOL(dib9000_get_i2c_master);
int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
{
struct dib9000_state *st = fe->demodulator_priv;
st->i2c.i2c_adap = i2c;
return 0;
}
EXPORT_SYMBOL(dib9000_set_i2c_adapter);
static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
{
st->gpio_dir = dib9000_read_word(st, 773);
st->gpio_dir &= ~(1 << num); /* reset the direction bit */
st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
dib9000_write_word(st, 773, st->gpio_dir);
st->gpio_val = dib9000_read_word(st, 774);
st->gpio_val &= ~(1 << num); /* reset the direction bit */
st->gpio_val |= (val & 0x01) << num; /* set the new value */
dib9000_write_word(st, 774, st->gpio_val);
dprintk("gpio dir: %04x: gpio val: %04x\n", st->gpio_dir, st->gpio_val);
return 0;
}
int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
{
struct dib9000_state *state = fe->demodulator_priv;
return dib9000_cfg_gpio(state, num, dir, val);
}
EXPORT_SYMBOL(dib9000_set_gpio);
int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 val;
int ret;
if ((state->pid_ctrl_index != -2) && (state->pid_ctrl_index < 9)) {
/* postpone the pid filtering cmd */
dprintk("pid filter cmd postpone\n");
state->pid_ctrl_index++;
state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER_CTRL;
state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
return 0;
}
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
val = dib9000_read_word(state, 294 + 1) & 0xffef;
val |= (onoff & 0x1) << 4;
dprintk("PID filter enabled %d\n", onoff);
ret = dib9000_write_word(state, 294 + 1, val);
mutex_unlock(&state->demod_lock);
return ret;
}
EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib9000_state *state = fe->demodulator_priv;
int ret;
if (state->pid_ctrl_index != -2) {
/* postpone the pid filtering cmd */
dprintk("pid filter postpone\n");
if (state->pid_ctrl_index < 9) {
state->pid_ctrl_index++;
state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER;
state->pid_ctrl[state->pid_ctrl_index].id = id;
state->pid_ctrl[state->pid_ctrl_index].pid = pid;
state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
} else
dprintk("can not add any more pid ctrl cmd\n");
return 0;
}
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
dprintk("Index %x, PID %d, OnOff %d\n", id, pid, onoff);
ret = dib9000_write_word(state, 300 + 1 + id,
onoff ? (1 << 13) | pid : 0);
mutex_unlock(&state->demod_lock);
return ret;
}
EXPORT_SYMBOL(dib9000_fw_pid_filter);
int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
return dib9000_fw_init(state);
}
EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
static void dib9000_release(struct dvb_frontend *demod)
{
struct dib9000_state *st = demod->demodulator_priv;
u8 index_frontend;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
dvb_frontend_detach(st->fe[index_frontend]);
dibx000_exit_i2c_master(&st->i2c_master);
i2c_del_adapter(&st->tuner_adap);
i2c_del_adapter(&st->component_bus);
kfree(st->fe[0]);
kfree(st);
}
static int dib9000_wakeup(struct dvb_frontend *fe)
{
return 0;
}
static int dib9000_sleep(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend;
int ret = 0;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
if (ret < 0)
goto error;
}
ret = dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
error:
mutex_unlock(&state->demod_lock);
return ret;
}
static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static int dib9000_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend, sub_index_frontend;
enum fe_status stat;
int ret = 0;
if (state->get_frontend_internal == 0) {
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
}
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
if (stat & FE_HAS_SYNC) {
dprintk("TPS lock on the slave%i\n", index_frontend);
/* synchronize the cache with the other frontends */
state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
sub_index_frontend++) {
if (sub_index_frontend != index_frontend) {
state->fe[sub_index_frontend]->dtv_property_cache.modulation =
state->fe[index_frontend]->dtv_property_cache.modulation;
state->fe[sub_index_frontend]->dtv_property_cache.inversion =
state->fe[index_frontend]->dtv_property_cache.inversion;
state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
state->fe[index_frontend]->dtv_property_cache.transmission_mode;
state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
state->fe[index_frontend]->dtv_property_cache.guard_interval;
state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
state->fe[index_frontend]->dtv_property_cache.hierarchy;
state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
state->fe[index_frontend]->dtv_property_cache.rolloff;
}
}
ret = 0;
goto return_value;
}
}
/* get the channel from master chip */
ret = dib9000_fw_get_channel(fe);
if (ret != 0)
goto return_value;
/* synchronize the cache with the other frontends */
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
state->fe[index_frontend]->dtv_property_cache.modulation = c->modulation;
state->fe[index_frontend]->dtv_property_cache.hierarchy = c->hierarchy;
state->fe[index_frontend]->dtv_property_cache.code_rate_HP = c->code_rate_HP;
state->fe[index_frontend]->dtv_property_cache.code_rate_LP = c->code_rate_LP;
state->fe[index_frontend]->dtv_property_cache.rolloff = c->rolloff;
}
ret = 0;
return_value:
if (state->get_frontend_internal == 0)
mutex_unlock(&state->demod_lock);
return ret;
}
static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{
struct dib9000_state *state = fe->demodulator_priv;
state->tune_state = tune_state;
if (tune_state == CT_DEMOD_START)
state->status = FE_STATUS_TUNE_PENDING;
return 0;
}
static u32 dib9000_get_status(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
return state->status;
}
static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
{
struct dib9000_state *state = fe->demodulator_priv;
memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
return 0;
}
static int dib9000_set_frontend(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
int sleep_time, sleep_time_slave;
u32 frontend_status;
u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
struct dvb_frontend_parametersContext channel_status;
/* check that the correct parameters are set */
if (state->fe[0]->dtv_property_cache.frequency == 0) {
dprintk("dib9000: must specify frequency\n");
return 0;
}
if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
dprintk("dib9000: must specify bandwidth\n");
return 0;
}
state->pid_ctrl_index = -1; /* postpone the pid filtering cmd */
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return 0;
}
fe->dtv_property_cache.delivery_system = SYS_DVBT;
/* set the master status */
if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO ||
state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO ||
state->fe[0]->dtv_property_cache.modulation == QAM_AUTO ||
state->fe[0]->dtv_property_cache.code_rate_HP == FEC_AUTO) {
/* no channel specified, autosearch the channel */
state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
} else
state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
/* set mode and status for the different frontends */
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
/* synchronization of the cache */
memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
}
/* actual tune */
exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
index_frontend_success = 0;
do {
sleep_time = dib9000_fw_tune(state->fe[0]);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
if (sleep_time == FE_CALLBACK_TIME_NEVER)
sleep_time = sleep_time_slave;
else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
sleep_time = sleep_time_slave;
}
if (sleep_time != FE_CALLBACK_TIME_NEVER)
msleep(sleep_time / 10);
else
break;
nbr_pending = 0;
exit_condition = 0;
index_frontend_success = 0;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
frontend_status = -dib9000_get_status(state->fe[index_frontend]);
if (frontend_status > -FE_STATUS_TUNE_PENDING) {
exit_condition = 2; /* tune success */
index_frontend_success = index_frontend;
break;
}
if (frontend_status == -FE_STATUS_TUNE_PENDING)
nbr_pending++; /* some frontends are still tuning */
}
if ((exit_condition != 2) && (nbr_pending == 0))
exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
} while (exit_condition == 0);
/* check the tune result */
if (exit_condition == 1) { /* tune failed */
dprintk("tune failed\n");
mutex_unlock(&state->demod_lock);
/* tune failed; put all the pid filtering cmd to junk */
state->pid_ctrl_index = -1;
return 0;
}
dprintk("tune success on frontend%i\n", index_frontend_success);
/* synchronize all the channel cache */
state->get_frontend_internal = 1;
dib9000_get_frontend(state->fe[0], &state->fe[0]->dtv_property_cache);
state->get_frontend_internal = 0;
/* retune the other frontends with the found channel */
channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
/* only retune the frontends which was not tuned success */
if (index_frontend != index_frontend_success) {
dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
}
}
do {
sleep_time = FE_CALLBACK_TIME_NEVER;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (index_frontend != index_frontend_success) {
sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
if (sleep_time == FE_CALLBACK_TIME_NEVER)
sleep_time = sleep_time_slave;
else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
sleep_time = sleep_time_slave;
}
}
if (sleep_time != FE_CALLBACK_TIME_NEVER)
msleep(sleep_time / 10);
else
break;
nbr_pending = 0;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (index_frontend != index_frontend_success) {
frontend_status = -dib9000_get_status(state->fe[index_frontend]);
if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
nbr_pending++; /* some frontends are still tuning */
}
}
} while (nbr_pending != 0);
/* set the output mode */
dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
/* turn off the diversity for the last frontend */
dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
mutex_unlock(&state->demod_lock);
if (state->pid_ctrl_index >= 0) {
u8 index_pid_filter_cmd;
u8 pid_ctrl_index = state->pid_ctrl_index;
state->pid_ctrl_index = -2;
for (index_pid_filter_cmd = 0;
index_pid_filter_cmd <= pid_ctrl_index;
index_pid_filter_cmd++) {
if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER_CTRL)
dib9000_fw_pid_filter_ctrl(state->fe[0],
state->pid_ctrl[index_pid_filter_cmd].onoff);
else if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER)
dib9000_fw_pid_filter(state->fe[0],
state->pid_ctrl[index_pid_filter_cmd].id,
state->pid_ctrl[index_pid_filter_cmd].pid,
state->pid_ctrl[index_pid_filter_cmd].onoff);
}
}
/* do not postpone any more the pid filtering */
state->pid_ctrl_index = -2;
return 0;
}
static u16 dib9000_read_lock(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
return dib9000_read_word(state, 535);
}
static int dib9000_read_status(struct dvb_frontend *fe, enum fe_status *stat)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend;
u16 lock = 0, lock_slave = 0;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
lock = dib9000_read_word(state, 535);
*stat = 0;
if ((lock & 0x8000) || (lock_slave & 0x8000))
*stat |= FE_HAS_SIGNAL;
if ((lock & 0x3000) || (lock_slave & 0x3000))
*stat |= FE_HAS_CARRIER;
if ((lock & 0x0100) || (lock_slave & 0x0100))
*stat |= FE_HAS_VITERBI;
if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
*stat |= FE_HAS_SYNC;
if ((lock & 0x0008) || (lock_slave & 0x0008))
*stat |= FE_HAS_LOCK;
mutex_unlock(&state->demod_lock);
return 0;
}
static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 *c;
int ret = 0;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
ret = -EINTR;
goto error;
}
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
mutex_unlock(&state->platform.risc.mem_mbx_lock);
ret = -EIO;
goto error;
}
dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR,
state->i2c_read_buffer, 16 * 2);
mutex_unlock(&state->platform.risc.mem_mbx_lock);
c = (u16 *)state->i2c_read_buffer;
*ber = c[10] << 16 | c[11];
error:
mutex_unlock(&state->demod_lock);
return ret;
}
static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend;
u16 *c = (u16 *)state->i2c_read_buffer;
u16 val;
int ret = 0;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
*strength = 0;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
}
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
ret = -EINTR;
goto error;
}
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
mutex_unlock(&state->platform.risc.mem_mbx_lock);
ret = -EIO;
goto error;
}
dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
mutex_unlock(&state->platform.risc.mem_mbx_lock);
val = 65535 - c[4];
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
error:
mutex_unlock(&state->demod_lock);
return ret;
}
static u32 dib9000_get_snr(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 *c = (u16 *)state->i2c_read_buffer;
u32 n, s, exp;
u16 val;
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
return 0;
}
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
mutex_unlock(&state->platform.risc.mem_mbx_lock);
return 0;
}
dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
mutex_unlock(&state->platform.risc.mem_mbx_lock);
val = c[7];
n = (val >> 4) & 0xff;
exp = ((val & 0xf) << 2);
val = c[8];
exp += ((val >> 14) & 0x3);
if ((exp & 0x20) != 0)
exp -= 0x40;
n <<= exp + 16;
s = (val >> 6) & 0xFF;
exp = (val & 0x3F);
if ((exp & 0x20) != 0)
exp -= 0x40;
s <<= exp + 16;
if (n > 0) {
u32 t = (s / n) << 16;
return t + ((s << 16) - n * t) / n;
}
return 0xffffffff;
}
static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend;
u32 snr_master;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
snr_master = dib9000_get_snr(fe);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
snr_master += dib9000_get_snr(state->fe[index_frontend]);
if ((snr_master >> 16) != 0) {
snr_master = 10 * intlog10(snr_master >> 16);
*snr = snr_master / ((1 << 24) / 10);
} else
*snr = 0;
mutex_unlock(&state->demod_lock);
return 0;
}
static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib9000_state *state = fe->demodulator_priv;
u16 *c = (u16 *)state->i2c_read_buffer;
int ret = 0;
if (mutex_lock_interruptible(&state->demod_lock) < 0) {
dprintk("could not get the lock\n");
return -EINTR;
}
if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
dprintk("could not get the lock\n");
ret = -EINTR;
goto error;
}
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
mutex_unlock(&state->platform.risc.mem_mbx_lock);
ret = -EIO;
goto error;
}
dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
mutex_unlock(&state->platform.risc.mem_mbx_lock);
*unc = c[12];
error:
mutex_unlock(&state->demod_lock);
return ret;
}
int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
{
int k = 0, ret = 0;
u8 new_addr = 0;
struct i2c_device client = {.i2c_adap = i2c };
client.i2c_write_buffer = kzalloc(4, GFP_KERNEL);
if (!client.i2c_write_buffer) {
dprintk("%s: not enough memory\n", __func__);
return -ENOMEM;
}
client.i2c_read_buffer = kzalloc(4, GFP_KERNEL);
if (!client.i2c_read_buffer) {
dprintk("%s: not enough memory\n", __func__);
ret = -ENOMEM;
goto error_memory;
}
client.i2c_addr = default_addr + 16;
dib9000_i2c_write16(&client, 1796, 0x0);
for (k = no_of_demods - 1; k >= 0; k--) {
/* designated i2c address */
new_addr = first_addr + (k << 1);
client.i2c_addr = default_addr;
dib9000_i2c_write16(&client, 1817, 3);
dib9000_i2c_write16(&client, 1796, 0);
dib9000_i2c_write16(&client, 1227, 1);
dib9000_i2c_write16(&client, 1227, 0);
client.i2c_addr = new_addr;
dib9000_i2c_write16(&client, 1817, 3);
dib9000_i2c_write16(&client, 1796, 0);
dib9000_i2c_write16(&client, 1227, 1);
dib9000_i2c_write16(&client, 1227, 0);
if (dib9000_identify(&client) == 0) {
client.i2c_addr = default_addr;
if (dib9000_identify(&client) == 0) {
dprintk("DiB9000 #%d: not identified\n", k);
ret = -EIO;
goto error;
}
}
dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
}
for (k = 0; k < no_of_demods; k++) {
new_addr = first_addr | (k << 1);
client.i2c_addr = new_addr;
dib9000_i2c_write16(&client, 1794, (new_addr << 2));
dib9000_i2c_write16(&client, 1795, 0);
}
error:
kfree(client.i2c_read_buffer);
error_memory:
kfree(client.i2c_write_buffer);
return ret;
}
EXPORT_SYMBOL(dib9000_i2c_enumeration);
int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend = 1;
while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
index_frontend++;
if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
dprintk("set slave fe %p to index %i\n", fe_slave, index_frontend);
state->fe[index_frontend] = fe_slave;
return 0;
}
dprintk("too many slave frontend\n");
return -ENOMEM;
}
EXPORT_SYMBOL(dib9000_set_slave_frontend);
struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
{
struct dib9000_state *state = fe->demodulator_priv;
if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
return NULL;
return state->fe[slave_index];
}
EXPORT_SYMBOL(dib9000_get_slave_frontend);
static const struct dvb_frontend_ops dib9000_ops;
struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
{
struct dvb_frontend *fe;
struct dib9000_state *st;
st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
if (st == NULL)
return NULL;
fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
if (fe == NULL) {
kfree(st);
return NULL;
}
memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
st->i2c.i2c_adap = i2c_adap;
st->i2c.i2c_addr = i2c_addr;
st->i2c.i2c_write_buffer = st->i2c_write_buffer;
st->i2c.i2c_read_buffer = st->i2c_read_buffer;
st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
mutex_init(&st->platform.risc.mbx_if_lock);
mutex_init(&st->platform.risc.mbx_lock);
mutex_init(&st->platform.risc.mem_lock);
mutex_init(&st->platform.risc.mem_mbx_lock);
mutex_init(&st->demod_lock);
st->get_frontend_internal = 0;
st->pid_ctrl_index = -2;
st->fe[0] = fe;
fe->demodulator_priv = st;
memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
/* Ensure the output mode remains at the previous default if it's
* not specifically set by the caller.
*/
if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
if (dib9000_identify(&st->i2c) == 0)
goto error;
dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
st->tuner_adap.dev.parent = i2c_adap->dev.parent;
strscpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS",
sizeof(st->tuner_adap.name));
st->tuner_adap.algo = &dib9000_tuner_algo;
st->tuner_adap.algo_data = NULL;
i2c_set_adapdata(&st->tuner_adap, st);
if (i2c_add_adapter(&st->tuner_adap) < 0)
goto error;
st->component_bus.dev.parent = i2c_adap->dev.parent;
strscpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS",
sizeof(st->component_bus.name));
st->component_bus.algo = &dib9000_component_bus_algo;
st->component_bus.algo_data = NULL;
st->component_bus_speed = 340;
i2c_set_adapdata(&st->component_bus, st);
if (i2c_add_adapter(&st->component_bus) < 0)
goto component_bus_add_error;
dib9000_fw_reset(fe);
return fe;
component_bus_add_error:
i2c_del_adapter(&st->tuner_adap);
error:
kfree(st);
return NULL;
}
EXPORT_SYMBOL_GPL(dib9000_attach);
static const struct dvb_frontend_ops dib9000_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 9000",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
},
.release = dib9000_release,
.init = dib9000_wakeup,
.sleep = dib9000_sleep,
.set_frontend = dib9000_set_frontend,
.get_tune_settings = dib9000_fe_get_tune_settings,
.get_frontend = dib9000_get_frontend,
.read_status = dib9000_read_status,
.read_ber = dib9000_read_ber,
.read_signal_strength = dib9000_read_signal_strength,
.read_snr = dib9000_read_snr,
.read_ucblocks = dib9000_read_unc_blocks,
};
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_AUTHOR("Olivier Grenie <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib9000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* isl6405.c - driver for dual lnb supply and control ic ISL6405
*
* Copyright (C) 2008 Hartmut Hackmann
* Copyright (C) 2006 Oliver Endriss
*
* the project's page is at https://linuxtv.org
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "isl6405.h"
struct isl6405 {
u8 config;
u8 override_or;
u8 override_and;
struct i2c_adapter *i2c;
u8 i2c_addr;
};
static int isl6405_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct isl6405 *isl6405 = (struct isl6405 *) fe->sec_priv;
struct i2c_msg msg = { .addr = isl6405->i2c_addr, .flags = 0,
.buf = &isl6405->config,
.len = sizeof(isl6405->config) };
if (isl6405->override_or & 0x80) {
isl6405->config &= ~(ISL6405_VSEL2 | ISL6405_EN2);
switch (voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
isl6405->config |= ISL6405_EN2;
break;
case SEC_VOLTAGE_18:
isl6405->config |= (ISL6405_EN2 | ISL6405_VSEL2);
break;
default:
return -EINVAL;
}
} else {
isl6405->config &= ~(ISL6405_VSEL1 | ISL6405_EN1);
switch (voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
isl6405->config |= ISL6405_EN1;
break;
case SEC_VOLTAGE_18:
isl6405->config |= (ISL6405_EN1 | ISL6405_VSEL1);
break;
default:
return -EINVAL;
}
}
isl6405->config |= isl6405->override_or;
isl6405->config &= isl6405->override_and;
return (i2c_transfer(isl6405->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int isl6405_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct isl6405 *isl6405 = (struct isl6405 *) fe->sec_priv;
struct i2c_msg msg = { .addr = isl6405->i2c_addr, .flags = 0,
.buf = &isl6405->config,
.len = sizeof(isl6405->config) };
if (isl6405->override_or & 0x80) {
if (arg)
isl6405->config |= ISL6405_LLC2;
else
isl6405->config &= ~ISL6405_LLC2;
} else {
if (arg)
isl6405->config |= ISL6405_LLC1;
else
isl6405->config &= ~ISL6405_LLC1;
}
isl6405->config |= isl6405->override_or;
isl6405->config &= isl6405->override_and;
return (i2c_transfer(isl6405->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static void isl6405_release(struct dvb_frontend *fe)
{
/* power off */
isl6405_set_voltage(fe, SEC_VOLTAGE_OFF);
/* free */
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c,
u8 i2c_addr, u8 override_set, u8 override_clear)
{
struct isl6405 *isl6405 = kmalloc(sizeof(struct isl6405), GFP_KERNEL);
if (!isl6405)
return NULL;
/* default configuration */
if (override_set & 0x80)
isl6405->config = ISL6405_ISEL2;
else
isl6405->config = ISL6405_ISEL1;
isl6405->i2c = i2c;
isl6405->i2c_addr = i2c_addr;
fe->sec_priv = isl6405;
/* bits which should be forced to '1' */
isl6405->override_or = override_set;
/* bits which should be forced to '0' */
isl6405->override_and = ~override_clear;
/* detect if it is present or not */
if (isl6405_set_voltage(fe, SEC_VOLTAGE_OFF)) {
kfree(isl6405);
fe->sec_priv = NULL;
return NULL;
}
/* install release callback */
fe->ops.release_sec = isl6405_release;
/* override frontend ops */
fe->ops.set_voltage = isl6405_set_voltage;
fe->ops.enable_high_lnb_voltage = isl6405_enable_high_lnb_voltage;
return fe;
}
EXPORT_SYMBOL_GPL(isl6405_attach);
MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6405");
MODULE_AUTHOR("Hartmut Hackmann & Oliver Endriss");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/isl6405.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lnbp21.c - driver for lnb supply and control ic lnbp21
*
* Copyright (C) 2006, 2009 Oliver Endriss <[email protected]>
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
*
* the project's page is at https://linuxtv.org
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "lnbp21.h"
#include "lnbh24.h"
struct lnbp21 {
u8 config;
u8 override_or;
u8 override_and;
struct i2c_adapter *i2c;
u8 i2c_addr;
};
static int lnbp21_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
lnbp21->config &= ~(LNBP21_VSEL | LNBP21_EN);
switch(voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
lnbp21->config |= LNBP21_EN;
break;
case SEC_VOLTAGE_18:
lnbp21->config |= (LNBP21_EN | LNBP21_VSEL);
break;
default:
return -EINVAL;
}
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int lnbp21_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
if (arg)
lnbp21->config |= LNBP21_LLC;
else
lnbp21->config &= ~LNBP21_LLC;
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int lnbp21_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
switch (tone) {
case SEC_TONE_OFF:
lnbp21->config &= ~LNBP21_TEN;
break;
case SEC_TONE_ON:
lnbp21->config |= LNBP21_TEN;
break;
default:
return -EINVAL;
}
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static void lnbp21_release(struct dvb_frontend *fe)
{
/* LNBP power off */
lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF);
/* free data */
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr, u8 config)
{
struct lnbp21 *lnbp21 = kmalloc(sizeof(struct lnbp21), GFP_KERNEL);
if (!lnbp21)
return NULL;
/* default configuration */
lnbp21->config = config;
lnbp21->i2c = i2c;
lnbp21->i2c_addr = i2c_addr;
fe->sec_priv = lnbp21;
/* bits which should be forced to '1' */
lnbp21->override_or = override_set;
/* bits which should be forced to '0' */
lnbp21->override_and = ~override_clear;
/* detect if it is present or not */
if (lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF)) {
kfree(lnbp21);
return NULL;
}
/* install release callback */
fe->ops.release_sec = lnbp21_release;
/* override frontend ops */
fe->ops.set_voltage = lnbp21_set_voltage;
fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage;
if (!(override_clear & LNBH24_TEN)) /*22kHz logic controlled by demod*/
fe->ops.set_tone = lnbp21_set_tone;
printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr);
return fe;
}
struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr)
{
return lnbx2x_attach(fe, i2c, override_set, override_clear,
i2c_addr, LNBH24_TTX);
}
EXPORT_SYMBOL_GPL(lnbh24_attach);
struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear)
{
return lnbx2x_attach(fe, i2c, override_set, override_clear,
0x08, LNBP21_ISEL);
}
EXPORT_SYMBOL_GPL(lnbp21_attach);
MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24");
MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/lnbp21.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
TDA8261 8PSK/QPSK tuner driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "tda8261.h"
struct tda8261_state {
struct dvb_frontend *fe;
struct i2c_adapter *i2c;
const struct tda8261_config *config;
/* state cache */
u32 frequency;
u32 bandwidth;
};
static int tda8261_read(struct tda8261_state *state, u8 *buf)
{
const struct tda8261_config *config = state->config;
int err = 0;
struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 };
if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
pr_err("%s: read error, err=%d\n", __func__, err);
return err;
}
static int tda8261_write(struct tda8261_state *state, u8 *buf)
{
const struct tda8261_config *config = state->config;
int err = 0;
struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 };
if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
pr_err("%s: write error, err=%d\n", __func__, err);
return err;
}
static int tda8261_get_status(struct dvb_frontend *fe, u32 *status)
{
struct tda8261_state *state = fe->tuner_priv;
u8 result = 0;
int err = 0;
*status = 0;
if ((err = tda8261_read(state, &result)) < 0) {
pr_err("%s: I/O Error\n", __func__);
return err;
}
if ((result >> 6) & 0x01) {
pr_debug("%s: Tuner Phase Locked\n", __func__);
*status = 1;
}
return err;
}
static const u32 div_tab[] = { 2000, 1000, 500, 250, 125 }; /* kHz */
static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 };
static int tda8261_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda8261_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static int tda8261_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tda8261_state *state = fe->tuner_priv;
const struct tda8261_config *config = state->config;
u32 frequency, N, status = 0;
u8 buf[4];
int err = 0;
/*
* N = Max VCO Frequency / Channel Spacing
* Max VCO Frequency = VCO frequency + (channel spacing - 1)
* (to account for half channel spacing on either side)
*/
frequency = c->frequency;
if ((frequency < 950000) || (frequency > 2150000)) {
pr_warn("%s: Frequency beyond limits, frequency=%d\n",
__func__, frequency);
return -EINVAL;
}
N = (frequency + (div_tab[config->step_size] - 1)) / div_tab[config->step_size];
pr_debug("%s: Step size=%d, Divider=%d, PG=0x%02x (%d)\n",
__func__, config->step_size, div_tab[config->step_size], N, N);
buf[0] = (N >> 8) & 0xff;
buf[1] = N & 0xff;
buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1);
if (frequency < 1450000)
buf[3] = 0x00;
else if (frequency < 2000000)
buf[3] = 0x40;
else if (frequency < 2150000)
buf[3] = 0x80;
/* Set params */
err = tda8261_write(state, buf);
if (err < 0) {
pr_err("%s: I/O Error\n", __func__);
return err;
}
/* sleep for some time */
pr_debug("%s: Waiting to Phase LOCK\n", __func__);
msleep(20);
/* check status */
if ((err = tda8261_get_status(fe, &status)) < 0) {
pr_err("%s: I/O Error\n", __func__);
return err;
}
if (status == 1) {
pr_debug("%s: Tuner Phase locked: status=%d\n", __func__,
status);
state->frequency = frequency; /* cache successful state */
} else {
pr_debug("%s: No Phase lock: status=%d\n", __func__, status);
}
return 0;
}
static void tda8261_release(struct dvb_frontend *fe)
{
struct tda8261_state *state = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(state);
}
static const struct dvb_tuner_ops tda8261_ops = {
.info = {
.name = "TDA8261",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
},
.set_params = tda8261_set_params,
.get_frequency = tda8261_get_frequency,
.get_status = tda8261_get_status,
.release = tda8261_release
};
struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
const struct tda8261_config *config,
struct i2c_adapter *i2c)
{
struct tda8261_state *state = NULL;
if ((state = kzalloc(sizeof (struct tda8261_state), GFP_KERNEL)) == NULL)
goto exit;
state->config = config;
state->i2c = i2c;
state->fe = fe;
fe->tuner_priv = state;
fe->ops.tuner_ops = tda8261_ops;
fe->ops.tuner_ops.info.frequency_step_hz = div_tab[config->step_size] * kHz;
pr_info("%s: Attaching TDA8261 8PSK/QPSK tuner\n", __func__);
return fe;
exit:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(tda8261_attach);
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("TDA8261 8PSK/QPSK Tuner");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tda8261.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Conexant 22702 DVB OFDM demodulator driver
based on:
Alps TDMB7 DVB OFDM demodulator driver
Copyright (C) 2001-2002 Convergence Integrated Media GmbH
Holger Waechtler <[email protected]>
Copyright (C) 2004 Steven Toth <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "cx22702.h"
struct cx22702_state {
struct i2c_adapter *i2c;
/* configuration settings */
const struct cx22702_config *config;
struct dvb_frontend frontend;
/* previous uncorrected block counter */
u8 prevUCBlocks;
};
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
#define dprintk if (debug) printk
/* Register values to initialise the demod */
static const u8 init_tab[] = {
0x00, 0x00, /* Stop acquisition */
0x0B, 0x06,
0x09, 0x01,
0x0D, 0x41,
0x16, 0x32,
0x20, 0x0A,
0x21, 0x17,
0x24, 0x3e,
0x26, 0xff,
0x27, 0x10,
0x28, 0x00,
0x29, 0x00,
0x2a, 0x10,
0x2b, 0x00,
0x2c, 0x10,
0x2d, 0x00,
0x48, 0xd4,
0x49, 0x56,
0x6b, 0x1e,
0xc8, 0x02,
0xf9, 0x00,
0xfa, 0x00,
0xfb, 0x00,
0xfc, 0x00,
0xfd, 0x00,
};
static int cx22702_writereg(struct cx22702_state *state, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = state->config->demod_address, .flags = 0,
.buf = buf, .len = 2 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (unlikely(ret != 1)) {
printk(KERN_ERR
"%s: error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return -1;
}
return 0;
}
static u8 cx22702_readreg(struct cx22702_state *state, u8 reg)
{
int ret;
u8 data;
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0,
.buf = ®, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD,
.buf = &data, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (unlikely(ret != 2)) {
printk(KERN_ERR "%s: error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return 0;
}
return data;
}
static int cx22702_set_inversion(struct cx22702_state *state, int inversion)
{
u8 val;
val = cx22702_readreg(state, 0x0C);
switch (inversion) {
case INVERSION_AUTO:
return -EOPNOTSUPP;
case INVERSION_ON:
val |= 0x01;
break;
case INVERSION_OFF:
val &= 0xfe;
break;
default:
return -EINVAL;
}
return cx22702_writereg(state, 0x0C, val);
}
/* Retrieve the demod settings */
static int cx22702_get_tps(struct cx22702_state *state,
struct dtv_frontend_properties *p)
{
u8 val;
/* Make sure the TPS regs are valid */
if (!(cx22702_readreg(state, 0x0A) & 0x20))
return -EAGAIN;
val = cx22702_readreg(state, 0x01);
switch ((val & 0x18) >> 3) {
case 0:
p->modulation = QPSK;
break;
case 1:
p->modulation = QAM_16;
break;
case 2:
p->modulation = QAM_64;
break;
}
switch (val & 0x07) {
case 0:
p->hierarchy = HIERARCHY_NONE;
break;
case 1:
p->hierarchy = HIERARCHY_1;
break;
case 2:
p->hierarchy = HIERARCHY_2;
break;
case 3:
p->hierarchy = HIERARCHY_4;
break;
}
val = cx22702_readreg(state, 0x02);
switch ((val & 0x38) >> 3) {
case 0:
p->code_rate_HP = FEC_1_2;
break;
case 1:
p->code_rate_HP = FEC_2_3;
break;
case 2:
p->code_rate_HP = FEC_3_4;
break;
case 3:
p->code_rate_HP = FEC_5_6;
break;
case 4:
p->code_rate_HP = FEC_7_8;
break;
}
switch (val & 0x07) {
case 0:
p->code_rate_LP = FEC_1_2;
break;
case 1:
p->code_rate_LP = FEC_2_3;
break;
case 2:
p->code_rate_LP = FEC_3_4;
break;
case 3:
p->code_rate_LP = FEC_5_6;
break;
case 4:
p->code_rate_LP = FEC_7_8;
break;
}
val = cx22702_readreg(state, 0x03);
switch ((val & 0x0c) >> 2) {
case 0:
p->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
p->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
p->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
p->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch (val & 0x03) {
case 0:
p->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
p->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
return 0;
}
static int cx22702_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct cx22702_state *state = fe->demodulator_priv;
u8 val;
dprintk("%s(%d)\n", __func__, enable);
val = cx22702_readreg(state, 0x0D);
if (enable)
val &= 0xfe;
else
val |= 0x01;
return cx22702_writereg(state, 0x0D, val);
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int cx22702_set_tps(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u8 val;
struct cx22702_state *state = fe->demodulator_priv;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* set inversion */
cx22702_set_inversion(state, p->inversion);
/* set bandwidth */
val = cx22702_readreg(state, 0x0C) & 0xcf;
switch (p->bandwidth_hz) {
case 6000000:
val |= 0x20;
break;
case 7000000:
val |= 0x10;
break;
case 8000000:
break;
default:
dprintk("%s: invalid bandwidth\n", __func__);
return -EINVAL;
}
cx22702_writereg(state, 0x0C, val);
p->code_rate_LP = FEC_AUTO; /* temp hack as manual not working */
/* use auto configuration? */
if ((p->hierarchy == HIERARCHY_AUTO) ||
(p->modulation == QAM_AUTO) ||
(p->code_rate_HP == FEC_AUTO) ||
(p->code_rate_LP == FEC_AUTO) ||
(p->guard_interval == GUARD_INTERVAL_AUTO) ||
(p->transmission_mode == TRANSMISSION_MODE_AUTO)) {
/* TPS Source - use hardware driven values */
cx22702_writereg(state, 0x06, 0x10);
cx22702_writereg(state, 0x07, 0x9);
cx22702_writereg(state, 0x08, 0xC1);
cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B)
& 0xfc);
cx22702_writereg(state, 0x0C,
(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
cx22702_writereg(state, 0x00, 0x01); /* Begin acquisition */
dprintk("%s: Autodetecting\n", __func__);
return 0;
}
/* manually programmed values */
switch (p->modulation) { /* mask 0x18 */
case QPSK:
val = 0x00;
break;
case QAM_16:
val = 0x08;
break;
case QAM_64:
val = 0x10;
break;
default:
dprintk("%s: invalid modulation\n", __func__);
return -EINVAL;
}
switch (p->hierarchy) { /* mask 0x07 */
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
val |= 0x01;
break;
case HIERARCHY_2:
val |= 0x02;
break;
case HIERARCHY_4:
val |= 0x03;
break;
default:
dprintk("%s: invalid hierarchy\n", __func__);
return -EINVAL;
}
cx22702_writereg(state, 0x06, val);
switch (p->code_rate_HP) { /* mask 0x38 */
case FEC_NONE:
case FEC_1_2:
val = 0x00;
break;
case FEC_2_3:
val = 0x08;
break;
case FEC_3_4:
val = 0x10;
break;
case FEC_5_6:
val = 0x18;
break;
case FEC_7_8:
val = 0x20;
break;
default:
dprintk("%s: invalid code_rate_HP\n", __func__);
return -EINVAL;
}
switch (p->code_rate_LP) { /* mask 0x07 */
case FEC_NONE:
case FEC_1_2:
break;
case FEC_2_3:
val |= 0x01;
break;
case FEC_3_4:
val |= 0x02;
break;
case FEC_5_6:
val |= 0x03;
break;
case FEC_7_8:
val |= 0x04;
break;
default:
dprintk("%s: invalid code_rate_LP\n", __func__);
return -EINVAL;
}
cx22702_writereg(state, 0x07, val);
switch (p->guard_interval) { /* mask 0x0c */
case GUARD_INTERVAL_1_32:
val = 0x00;
break;
case GUARD_INTERVAL_1_16:
val = 0x04;
break;
case GUARD_INTERVAL_1_8:
val = 0x08;
break;
case GUARD_INTERVAL_1_4:
val = 0x0c;
break;
default:
dprintk("%s: invalid guard_interval\n", __func__);
return -EINVAL;
}
switch (p->transmission_mode) { /* mask 0x03 */
case TRANSMISSION_MODE_2K:
break;
case TRANSMISSION_MODE_8K:
val |= 0x1;
break;
default:
dprintk("%s: invalid transmission_mode\n", __func__);
return -EINVAL;
}
cx22702_writereg(state, 0x08, val);
cx22702_writereg(state, 0x0B,
(cx22702_readreg(state, 0x0B) & 0xfc) | 0x02);
cx22702_writereg(state, 0x0C,
(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
/* Begin channel acquisition */
cx22702_writereg(state, 0x00, 0x01);
return 0;
}
/* Reset the demod hardware and reset all of the configuration registers
to a default state. */
static int cx22702_init(struct dvb_frontend *fe)
{
int i;
struct cx22702_state *state = fe->demodulator_priv;
cx22702_writereg(state, 0x00, 0x02);
msleep(10);
for (i = 0; i < ARRAY_SIZE(init_tab); i += 2)
cx22702_writereg(state, init_tab[i], init_tab[i + 1]);
cx22702_writereg(state, 0xf8, (state->config->output_mode << 1)
& 0x02);
cx22702_i2c_gate_ctrl(fe, 0);
return 0;
}
static int cx22702_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx22702_state *state = fe->demodulator_priv;
u8 reg0A;
u8 reg23;
*status = 0;
reg0A = cx22702_readreg(state, 0x0A);
reg23 = cx22702_readreg(state, 0x23);
dprintk("%s: status demod=0x%02x agc=0x%02x\n"
, __func__, reg0A, reg23);
if (reg0A & 0x10) {
*status |= FE_HAS_LOCK;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
}
if (reg0A & 0x20)
*status |= FE_HAS_CARRIER;
if (reg23 < 0xf0)
*status |= FE_HAS_SIGNAL;
return 0;
}
static int cx22702_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cx22702_state *state = fe->demodulator_priv;
if (cx22702_readreg(state, 0xE4) & 0x02) {
/* Realtime statistics */
*ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
| (cx22702_readreg(state, 0xDF) & 0x7F);
} else {
/* Averagtine statistics */
*ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
| cx22702_readreg(state, 0xDF);
}
return 0;
}
static int cx22702_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct cx22702_state *state = fe->demodulator_priv;
u8 reg23;
/*
* Experience suggests that the strength signal register works as
* follows:
* - In the absence of signal, value is 0xff.
* - In the presence of a weak signal, bit 7 is set, not sure what
* the lower 7 bits mean.
* - In the presence of a strong signal, the register holds a 7-bit
* value (bit 7 is cleared), with greater values standing for
* weaker signals.
*/
reg23 = cx22702_readreg(state, 0x23);
if (reg23 & 0x80) {
*signal_strength = 0;
} else {
reg23 = ~reg23 & 0x7f;
/* Scale to 16 bit */
*signal_strength = (reg23 << 9) | (reg23 << 2) | (reg23 >> 5);
}
return 0;
}
static int cx22702_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct cx22702_state *state = fe->demodulator_priv;
u16 rs_ber;
if (cx22702_readreg(state, 0xE4) & 0x02) {
/* Realtime statistics */
rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
| (cx22702_readreg(state, 0xDF) & 0x7F);
} else {
/* Averagine statistics */
rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 8
| cx22702_readreg(state, 0xDF);
}
*snr = ~rs_ber;
return 0;
}
static int cx22702_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct cx22702_state *state = fe->demodulator_priv;
u8 _ucblocks;
/* RS Uncorrectable Packet Count then reset */
_ucblocks = cx22702_readreg(state, 0xE3);
if (state->prevUCBlocks < _ucblocks)
*ucblocks = (_ucblocks - state->prevUCBlocks);
else
*ucblocks = state->prevUCBlocks - _ucblocks;
state->prevUCBlocks = _ucblocks;
return 0;
}
static int cx22702_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cx22702_state *state = fe->demodulator_priv;
u8 reg0C = cx22702_readreg(state, 0x0C);
c->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
return cx22702_get_tps(state, c);
}
static int cx22702_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void cx22702_release(struct dvb_frontend *fe)
{
struct cx22702_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops cx22702_ops;
struct dvb_frontend *cx22702_attach(const struct cx22702_config *config,
struct i2c_adapter *i2c)
{
struct cx22702_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct cx22702_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if (cx22702_readreg(state, 0x1f) != 0x3)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx22702_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(cx22702_attach);
static const struct dvb_frontend_ops cx22702_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Conexant CX22702 DVB-T",
.frequency_min_hz = 177 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
},
.release = cx22702_release,
.init = cx22702_init,
.i2c_gate_ctrl = cx22702_i2c_gate_ctrl,
.set_frontend = cx22702_set_tps,
.get_frontend = cx22702_get_frontend,
.get_tune_settings = cx22702_get_tune_settings,
.read_status = cx22702_read_status,
.read_ber = cx22702_read_ber,
.read_signal_strength = cx22702_read_signal_strength,
.read_snr = cx22702_read_snr,
.read_ucblocks = cx22702_read_ucblocks,
};
MODULE_DESCRIPTION("Conexant CX22702 DVB-T Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cx22702.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Auvitek AU8522 QAM/8VSB demodulator driver
Copyright (C) 2008 Steven Toth <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "au8522.h"
#include "au8522_priv.h"
static int debug;
static int zv_mode = 1; /* default to on */
#define dprintk(arg...)\
do { if (debug)\
printk(arg);\
} while (0)
struct mse2snr_tab {
u16 val;
u16 data;
};
/* VSB SNR lookup table */
static struct mse2snr_tab vsb_mse2snr_tab[] = {
{ 0, 270 },
{ 2, 250 },
{ 3, 240 },
{ 5, 230 },
{ 7, 220 },
{ 9, 210 },
{ 12, 200 },
{ 13, 195 },
{ 15, 190 },
{ 17, 185 },
{ 19, 180 },
{ 21, 175 },
{ 24, 170 },
{ 27, 165 },
{ 31, 160 },
{ 32, 158 },
{ 33, 156 },
{ 36, 152 },
{ 37, 150 },
{ 39, 148 },
{ 40, 146 },
{ 41, 144 },
{ 43, 142 },
{ 44, 140 },
{ 48, 135 },
{ 50, 130 },
{ 43, 142 },
{ 53, 125 },
{ 56, 120 },
{ 256, 115 },
};
/* QAM64 SNR lookup table */
static struct mse2snr_tab qam64_mse2snr_tab[] = {
{ 15, 0 },
{ 16, 290 },
{ 17, 288 },
{ 18, 286 },
{ 19, 284 },
{ 20, 282 },
{ 21, 281 },
{ 22, 279 },
{ 23, 277 },
{ 24, 275 },
{ 25, 273 },
{ 26, 271 },
{ 27, 269 },
{ 28, 268 },
{ 29, 266 },
{ 30, 264 },
{ 31, 262 },
{ 32, 260 },
{ 33, 259 },
{ 34, 258 },
{ 35, 256 },
{ 36, 255 },
{ 37, 254 },
{ 38, 252 },
{ 39, 251 },
{ 40, 250 },
{ 41, 249 },
{ 42, 248 },
{ 43, 246 },
{ 44, 245 },
{ 45, 244 },
{ 46, 242 },
{ 47, 241 },
{ 48, 240 },
{ 50, 239 },
{ 51, 238 },
{ 53, 237 },
{ 54, 236 },
{ 56, 235 },
{ 57, 234 },
{ 59, 233 },
{ 60, 232 },
{ 62, 231 },
{ 63, 230 },
{ 65, 229 },
{ 67, 228 },
{ 68, 227 },
{ 70, 226 },
{ 71, 225 },
{ 73, 224 },
{ 74, 223 },
{ 76, 222 },
{ 78, 221 },
{ 80, 220 },
{ 82, 219 },
{ 85, 218 },
{ 88, 217 },
{ 90, 216 },
{ 92, 215 },
{ 93, 214 },
{ 94, 212 },
{ 95, 211 },
{ 97, 210 },
{ 99, 209 },
{ 101, 208 },
{ 102, 207 },
{ 104, 206 },
{ 107, 205 },
{ 111, 204 },
{ 114, 203 },
{ 118, 202 },
{ 122, 201 },
{ 125, 200 },
{ 128, 199 },
{ 130, 198 },
{ 132, 197 },
{ 256, 190 },
};
/* QAM256 SNR lookup table */
static struct mse2snr_tab qam256_mse2snr_tab[] = {
{ 15, 0 },
{ 16, 400 },
{ 17, 398 },
{ 18, 396 },
{ 19, 394 },
{ 20, 392 },
{ 21, 390 },
{ 22, 388 },
{ 23, 386 },
{ 24, 384 },
{ 25, 382 },
{ 26, 380 },
{ 27, 379 },
{ 28, 378 },
{ 29, 377 },
{ 30, 376 },
{ 31, 375 },
{ 32, 374 },
{ 33, 373 },
{ 34, 372 },
{ 35, 371 },
{ 36, 370 },
{ 37, 362 },
{ 38, 354 },
{ 39, 346 },
{ 40, 338 },
{ 41, 330 },
{ 42, 328 },
{ 43, 326 },
{ 44, 324 },
{ 45, 322 },
{ 46, 320 },
{ 47, 319 },
{ 48, 318 },
{ 49, 317 },
{ 50, 316 },
{ 51, 315 },
{ 52, 314 },
{ 53, 313 },
{ 54, 312 },
{ 55, 311 },
{ 56, 310 },
{ 57, 308 },
{ 58, 306 },
{ 59, 304 },
{ 60, 302 },
{ 61, 300 },
{ 62, 298 },
{ 65, 295 },
{ 68, 294 },
{ 70, 293 },
{ 73, 292 },
{ 76, 291 },
{ 78, 290 },
{ 79, 289 },
{ 81, 288 },
{ 82, 287 },
{ 83, 286 },
{ 84, 285 },
{ 85, 284 },
{ 86, 283 },
{ 88, 282 },
{ 89, 281 },
{ 256, 280 },
};
static int au8522_mse2snr_lookup(struct mse2snr_tab *tab, int sz, int mse,
u16 *snr)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < sz; i++) {
if (mse < tab[i].val) {
*snr = tab[i].data;
ret = 0;
break;
}
}
dprintk("%s() snr=%d\n", __func__, *snr);
return ret;
}
static int au8522_set_if(struct dvb_frontend *fe, enum au8522_if_freq if_freq)
{
struct au8522_state *state = fe->demodulator_priv;
u8 r0b5, r0b6, r0b7;
char *ifmhz;
switch (if_freq) {
case AU8522_IF_3_25MHZ:
ifmhz = "3.25";
r0b5 = 0x00;
r0b6 = 0x3d;
r0b7 = 0xa0;
break;
case AU8522_IF_4MHZ:
ifmhz = "4.00";
r0b5 = 0x00;
r0b6 = 0x4b;
r0b7 = 0xd9;
break;
case AU8522_IF_6MHZ:
ifmhz = "6.00";
r0b5 = 0xfb;
r0b6 = 0x8e;
r0b7 = 0x39;
break;
default:
dprintk("%s() IF Frequency not supported\n", __func__);
return -EINVAL;
}
dprintk("%s() %s MHz\n", __func__, ifmhz);
au8522_writereg(state, 0x00b5, r0b5);
au8522_writereg(state, 0x00b6, r0b6);
au8522_writereg(state, 0x00b7, r0b7);
return 0;
}
/* VSB Modulation table */
static struct {
u16 reg;
u16 data;
} VSB_mod_tab[] = {
{ 0x0090, 0x84 },
{ 0x2005, 0x00 },
{ 0x0091, 0x80 },
{ 0x00a3, 0x0c },
{ 0x00a4, 0xe8 },
{ 0x0081, 0xc4 },
{ 0x00a5, 0x40 },
{ 0x00a7, 0x40 },
{ 0x00a6, 0x67 },
{ 0x0262, 0x20 },
{ 0x021c, 0x30 },
{ 0x00d8, 0x1a },
{ 0x0227, 0xa0 },
{ 0x0121, 0xff },
{ 0x00a8, 0xf0 },
{ 0x00a9, 0x05 },
{ 0x00aa, 0x77 },
{ 0x00ab, 0xf0 },
{ 0x00ac, 0x05 },
{ 0x00ad, 0x77 },
{ 0x00ae, 0x41 },
{ 0x00af, 0x66 },
{ 0x021b, 0xcc },
{ 0x021d, 0x80 },
{ 0x00a4, 0xe8 },
{ 0x0231, 0x13 },
};
/* QAM64 Modulation table */
static struct {
u16 reg;
u16 data;
} QAM64_mod_tab[] = {
{ 0x00a3, 0x09 },
{ 0x00a4, 0x00 },
{ 0x0081, 0xc4 },
{ 0x00a5, 0x40 },
{ 0x00aa, 0x77 },
{ 0x00ad, 0x77 },
{ 0x00a6, 0x67 },
{ 0x0262, 0x20 },
{ 0x021c, 0x30 },
{ 0x00b8, 0x3e },
{ 0x00b9, 0xf0 },
{ 0x00ba, 0x01 },
{ 0x00bb, 0x18 },
{ 0x00bc, 0x50 },
{ 0x00bd, 0x00 },
{ 0x00be, 0xea },
{ 0x00bf, 0xef },
{ 0x00c0, 0xfc },
{ 0x00c1, 0xbd },
{ 0x00c2, 0x1f },
{ 0x00c3, 0xfc },
{ 0x00c4, 0xdd },
{ 0x00c5, 0xaf },
{ 0x00c6, 0x00 },
{ 0x00c7, 0x38 },
{ 0x00c8, 0x30 },
{ 0x00c9, 0x05 },
{ 0x00ca, 0x4a },
{ 0x00cb, 0xd0 },
{ 0x00cc, 0x01 },
{ 0x00cd, 0xd9 },
{ 0x00ce, 0x6f },
{ 0x00cf, 0xf9 },
{ 0x00d0, 0x70 },
{ 0x00d1, 0xdf },
{ 0x00d2, 0xf7 },
{ 0x00d3, 0xc2 },
{ 0x00d4, 0xdf },
{ 0x00d5, 0x02 },
{ 0x00d6, 0x9a },
{ 0x00d7, 0xd0 },
{ 0x0250, 0x0d },
{ 0x0251, 0xcd },
{ 0x0252, 0xe0 },
{ 0x0253, 0x05 },
{ 0x0254, 0xa7 },
{ 0x0255, 0xff },
{ 0x0256, 0xed },
{ 0x0257, 0x5b },
{ 0x0258, 0xae },
{ 0x0259, 0xe6 },
{ 0x025a, 0x3d },
{ 0x025b, 0x0f },
{ 0x025c, 0x0d },
{ 0x025d, 0xea },
{ 0x025e, 0xf2 },
{ 0x025f, 0x51 },
{ 0x0260, 0xf5 },
{ 0x0261, 0x06 },
{ 0x021a, 0x00 },
{ 0x0546, 0x40 },
{ 0x0210, 0xc7 },
{ 0x0211, 0xaa },
{ 0x0212, 0xab },
{ 0x0213, 0x02 },
{ 0x0502, 0x00 },
{ 0x0121, 0x04 },
{ 0x0122, 0x04 },
{ 0x052e, 0x10 },
{ 0x00a4, 0xca },
{ 0x00a7, 0x40 },
{ 0x0526, 0x01 },
};
/* QAM256 Modulation table */
static struct {
u16 reg;
u16 data;
} QAM256_mod_tab[] = {
{ 0x00a3, 0x09 },
{ 0x00a4, 0x00 },
{ 0x0081, 0xc4 },
{ 0x00a5, 0x40 },
{ 0x00aa, 0x77 },
{ 0x00ad, 0x77 },
{ 0x00a6, 0x67 },
{ 0x0262, 0x20 },
{ 0x021c, 0x30 },
{ 0x00b8, 0x3e },
{ 0x00b9, 0xf0 },
{ 0x00ba, 0x01 },
{ 0x00bb, 0x18 },
{ 0x00bc, 0x50 },
{ 0x00bd, 0x00 },
{ 0x00be, 0xea },
{ 0x00bf, 0xef },
{ 0x00c0, 0xfc },
{ 0x00c1, 0xbd },
{ 0x00c2, 0x1f },
{ 0x00c3, 0xfc },
{ 0x00c4, 0xdd },
{ 0x00c5, 0xaf },
{ 0x00c6, 0x00 },
{ 0x00c7, 0x38 },
{ 0x00c8, 0x30 },
{ 0x00c9, 0x05 },
{ 0x00ca, 0x4a },
{ 0x00cb, 0xd0 },
{ 0x00cc, 0x01 },
{ 0x00cd, 0xd9 },
{ 0x00ce, 0x6f },
{ 0x00cf, 0xf9 },
{ 0x00d0, 0x70 },
{ 0x00d1, 0xdf },
{ 0x00d2, 0xf7 },
{ 0x00d3, 0xc2 },
{ 0x00d4, 0xdf },
{ 0x00d5, 0x02 },
{ 0x00d6, 0x9a },
{ 0x00d7, 0xd0 },
{ 0x0250, 0x0d },
{ 0x0251, 0xcd },
{ 0x0252, 0xe0 },
{ 0x0253, 0x05 },
{ 0x0254, 0xa7 },
{ 0x0255, 0xff },
{ 0x0256, 0xed },
{ 0x0257, 0x5b },
{ 0x0258, 0xae },
{ 0x0259, 0xe6 },
{ 0x025a, 0x3d },
{ 0x025b, 0x0f },
{ 0x025c, 0x0d },
{ 0x025d, 0xea },
{ 0x025e, 0xf2 },
{ 0x025f, 0x51 },
{ 0x0260, 0xf5 },
{ 0x0261, 0x06 },
{ 0x021a, 0x00 },
{ 0x0546, 0x40 },
{ 0x0210, 0x26 },
{ 0x0211, 0xf6 },
{ 0x0212, 0x84 },
{ 0x0213, 0x02 },
{ 0x0502, 0x01 },
{ 0x0121, 0x04 },
{ 0x0122, 0x04 },
{ 0x052e, 0x10 },
{ 0x00a4, 0xca },
{ 0x00a7, 0x40 },
{ 0x0526, 0x01 },
};
static struct {
u16 reg;
u16 data;
} QAM256_mod_tab_zv_mode[] = {
{ 0x80a3, 0x09 },
{ 0x80a4, 0x00 },
{ 0x8081, 0xc4 },
{ 0x80a5, 0x40 },
{ 0x80b5, 0xfb },
{ 0x80b6, 0x8e },
{ 0x80b7, 0x39 },
{ 0x80aa, 0x77 },
{ 0x80ad, 0x77 },
{ 0x80a6, 0x67 },
{ 0x8262, 0x20 },
{ 0x821c, 0x30 },
{ 0x80b8, 0x3e },
{ 0x80b9, 0xf0 },
{ 0x80ba, 0x01 },
{ 0x80bb, 0x18 },
{ 0x80bc, 0x50 },
{ 0x80bd, 0x00 },
{ 0x80be, 0xea },
{ 0x80bf, 0xef },
{ 0x80c0, 0xfc },
{ 0x80c1, 0xbd },
{ 0x80c2, 0x1f },
{ 0x80c3, 0xfc },
{ 0x80c4, 0xdd },
{ 0x80c5, 0xaf },
{ 0x80c6, 0x00 },
{ 0x80c7, 0x38 },
{ 0x80c8, 0x30 },
{ 0x80c9, 0x05 },
{ 0x80ca, 0x4a },
{ 0x80cb, 0xd0 },
{ 0x80cc, 0x01 },
{ 0x80cd, 0xd9 },
{ 0x80ce, 0x6f },
{ 0x80cf, 0xf9 },
{ 0x80d0, 0x70 },
{ 0x80d1, 0xdf },
{ 0x80d2, 0xf7 },
{ 0x80d3, 0xc2 },
{ 0x80d4, 0xdf },
{ 0x80d5, 0x02 },
{ 0x80d6, 0x9a },
{ 0x80d7, 0xd0 },
{ 0x8250, 0x0d },
{ 0x8251, 0xcd },
{ 0x8252, 0xe0 },
{ 0x8253, 0x05 },
{ 0x8254, 0xa7 },
{ 0x8255, 0xff },
{ 0x8256, 0xed },
{ 0x8257, 0x5b },
{ 0x8258, 0xae },
{ 0x8259, 0xe6 },
{ 0x825a, 0x3d },
{ 0x825b, 0x0f },
{ 0x825c, 0x0d },
{ 0x825d, 0xea },
{ 0x825e, 0xf2 },
{ 0x825f, 0x51 },
{ 0x8260, 0xf5 },
{ 0x8261, 0x06 },
{ 0x821a, 0x01 },
{ 0x8546, 0x40 },
{ 0x8210, 0x26 },
{ 0x8211, 0xf6 },
{ 0x8212, 0x84 },
{ 0x8213, 0x02 },
{ 0x8502, 0x01 },
{ 0x8121, 0x04 },
{ 0x8122, 0x04 },
{ 0x852e, 0x10 },
{ 0x80a4, 0xca },
{ 0x80a7, 0x40 },
{ 0x8526, 0x01 },
};
static int au8522_enable_modulation(struct dvb_frontend *fe,
enum fe_modulation m)
{
struct au8522_state *state = fe->demodulator_priv;
int i;
dprintk("%s(0x%08x)\n", __func__, m);
switch (m) {
case VSB_8:
dprintk("%s() VSB_8\n", __func__);
for (i = 0; i < ARRAY_SIZE(VSB_mod_tab); i++)
au8522_writereg(state,
VSB_mod_tab[i].reg,
VSB_mod_tab[i].data);
au8522_set_if(fe, state->config.vsb_if);
break;
case QAM_64:
dprintk("%s() QAM 64\n", __func__);
for (i = 0; i < ARRAY_SIZE(QAM64_mod_tab); i++)
au8522_writereg(state,
QAM64_mod_tab[i].reg,
QAM64_mod_tab[i].data);
au8522_set_if(fe, state->config.qam_if);
break;
case QAM_256:
if (zv_mode) {
dprintk("%s() QAM 256 (zv_mode)\n", __func__);
for (i = 0; i < ARRAY_SIZE(QAM256_mod_tab_zv_mode); i++)
au8522_writereg(state,
QAM256_mod_tab_zv_mode[i].reg,
QAM256_mod_tab_zv_mode[i].data);
au8522_set_if(fe, state->config.qam_if);
msleep(100);
au8522_writereg(state, 0x821a, 0x00);
} else {
dprintk("%s() QAM 256\n", __func__);
for (i = 0; i < ARRAY_SIZE(QAM256_mod_tab); i++)
au8522_writereg(state,
QAM256_mod_tab[i].reg,
QAM256_mod_tab[i].data);
au8522_set_if(fe, state->config.qam_if);
}
break;
default:
dprintk("%s() Invalid modulation\n", __func__);
return -EINVAL;
}
state->current_modulation = m;
return 0;
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int au8522_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct au8522_state *state = fe->demodulator_priv;
int ret = -EINVAL;
dprintk("%s(frequency=%d)\n", __func__, c->frequency);
if ((state->current_frequency == c->frequency) &&
(state->current_modulation == c->modulation))
return 0;
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (ret < 0)
return ret;
/* Allow the tuner to settle */
if (zv_mode) {
dprintk("%s() increase tuner settling time for zv_mode\n",
__func__);
msleep(250);
} else
msleep(100);
au8522_enable_modulation(fe, c->modulation);
state->current_frequency = c->frequency;
return 0;
}
static int au8522_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct au8522_state *state = fe->demodulator_priv;
u8 reg;
u32 tuner_status = 0;
*status = 0;
if (state->current_modulation == VSB_8) {
dprintk("%s() Checking VSB_8\n", __func__);
reg = au8522_readreg(state, 0x0088);
if ((reg & 0x03) == 0x03)
*status |= FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
} else {
dprintk("%s() Checking QAM\n", __func__);
reg = au8522_readreg(state, 0x0541);
if (reg & 0x80)
*status |= FE_HAS_VITERBI;
if (reg & 0x20)
*status |= FE_HAS_LOCK | FE_HAS_SYNC;
}
switch (state->config.status_mode) {
case AU8522_DEMODLOCKING:
dprintk("%s() DEMODLOCKING\n", __func__);
if (*status & FE_HAS_VITERBI)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
case AU8522_TUNERLOCKING:
/* Get the tuner status */
dprintk("%s() TUNERLOCKING\n", __func__);
if (fe->ops.tuner_ops.get_status) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.get_status(fe, &tuner_status);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (tuner_status)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
}
state->fe_status = *status;
if (*status & FE_HAS_LOCK)
/* turn on LED, if it isn't on already */
au8522_led_ctrl(state, -1);
else
/* turn off LED */
au8522_led_ctrl(state, 0);
dprintk("%s() status 0x%08x\n", __func__, *status);
return 0;
}
static int au8522_led_status(struct au8522_state *state, const u16 *snr)
{
struct au8522_led_config *led_config = state->config.led_cfg;
int led;
u16 strong;
/* bail out if we can't control an LED */
if (!led_config)
return 0;
if (0 == (state->fe_status & FE_HAS_LOCK))
return au8522_led_ctrl(state, 0);
else if (state->current_modulation == QAM_256)
strong = led_config->qam256_strong;
else if (state->current_modulation == QAM_64)
strong = led_config->qam64_strong;
else /* (state->current_modulation == VSB_8) */
strong = led_config->vsb8_strong;
if (*snr >= strong)
led = 2;
else
led = 1;
if ((state->led_state) &&
(((strong < *snr) ? (*snr - strong) : (strong - *snr)) <= 10))
/* snr didn't change enough to bother
* changing the color of the led */
return 0;
return au8522_led_ctrl(state, led);
}
static int au8522_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct au8522_state *state = fe->demodulator_priv;
int ret = -EINVAL;
dprintk("%s()\n", __func__);
if (state->current_modulation == QAM_256)
ret = au8522_mse2snr_lookup(qam256_mse2snr_tab,
ARRAY_SIZE(qam256_mse2snr_tab),
au8522_readreg(state, 0x0522),
snr);
else if (state->current_modulation == QAM_64)
ret = au8522_mse2snr_lookup(qam64_mse2snr_tab,
ARRAY_SIZE(qam64_mse2snr_tab),
au8522_readreg(state, 0x0522),
snr);
else /* VSB_8 */
ret = au8522_mse2snr_lookup(vsb_mse2snr_tab,
ARRAY_SIZE(vsb_mse2snr_tab),
au8522_readreg(state, 0x0311),
snr);
if (state->config.led_cfg)
au8522_led_status(state, snr);
return ret;
}
static int au8522_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
/* borrowed from lgdt330x.c
*
* Calculate strength from SNR up to 35dB
* Even though the SNR can go higher than 35dB,
* there is some comfort factor in having a range of
* strong signals that can show at 100%
*/
u16 snr;
u32 tmp;
int ret = au8522_read_snr(fe, &snr);
*signal_strength = 0;
if (0 == ret) {
/* The following calculation method was chosen
* purely for the sake of code re-use from the
* other demod drivers that use this method */
/* Convert from SNR in dB * 10 to 8.24 fixed-point */
tmp = (snr * ((1 << 24) / 10));
/* Convert from 8.24 fixed-point to
* scale the range 0 - 35*2^24 into 0 - 65535*/
if (tmp >= 8960 * 0x10000)
*signal_strength = 0xffff;
else
*signal_strength = tmp / 8960;
}
return ret;
}
static int au8522_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct au8522_state *state = fe->demodulator_priv;
if (state->current_modulation == VSB_8)
*ucblocks = au8522_readreg(state, 0x0087);
else
*ucblocks = au8522_readreg(state, 0x0543);
return 0;
}
static int au8522_read_ber(struct dvb_frontend *fe, u32 *ber)
{
return au8522_read_ucblocks(fe, ber);
}
static int au8522_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct au8522_state *state = fe->demodulator_priv;
c->frequency = state->current_frequency;
c->modulation = state->current_modulation;
return 0;
}
static int au8522_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static const struct dvb_frontend_ops au8522_ops;
static void au8522_release(struct dvb_frontend *fe)
{
struct au8522_state *state = fe->demodulator_priv;
au8522_release_state(state);
}
struct dvb_frontend *au8522_attach(const struct au8522_config *config,
struct i2c_adapter *i2c)
{
struct au8522_state *state = NULL;
int instance;
/* allocate memory for the internal state */
instance = au8522_get_state(&state, i2c, config->demod_address);
switch (instance) {
case 0:
dprintk("%s state allocation failed\n", __func__);
break;
case 1:
/* new demod instance */
dprintk("%s using new instance\n", __func__);
break;
default:
/* existing demod instance */
dprintk("%s using existing instance\n", __func__);
break;
}
/* setup the state */
state->config = *config;
state->i2c = i2c;
state->operational_mode = AU8522_DIGITAL_MODE;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &au8522_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
state->frontend.ops.analog_ops.i2c_gate_ctrl = au8522_analog_i2c_gate_ctrl;
if (au8522_init(&state->frontend) != 0) {
printk(KERN_ERR "%s: Failed to initialize correctly\n",
__func__);
goto error;
}
/* Note: Leaving the I2C gate open here. */
au8522_i2c_gate_ctrl(&state->frontend, 1);
return &state->frontend;
error:
au8522_release_state(state);
return NULL;
}
EXPORT_SYMBOL_GPL(au8522_attach);
static const struct dvb_frontend_ops au8522_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Auvitek AU8522 QAM/8VSB Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = au8522_init,
.sleep = au8522_sleep,
.i2c_gate_ctrl = au8522_i2c_gate_ctrl,
.set_frontend = au8522_set_frontend,
.get_frontend = au8522_get_frontend,
.get_tune_settings = au8522_get_tune_settings,
.read_status = au8522_read_status,
.read_ber = au8522_read_ber,
.read_signal_strength = au8522_read_signal_strength,
.read_snr = au8522_read_snr,
.read_ucblocks = au8522_read_ucblocks,
.release = au8522_release,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
module_param(zv_mode, int, 0644);
MODULE_PARM_DESC(zv_mode, "Turn on/off ZeeVee modulator compatibility mode (default:on).\n"
"\t\ton - modified AU8522 QAM256 initialization.\n"
"\t\tProvides faster lock when using ZeeVee modulator based sources");
MODULE_DESCRIPTION("Auvitek AU8522 QAM-B/ATSC Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/au8522_dig.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
* DiBcom (http://www.dibcom.fr/)
*
* Copyright (C) 2004-5 Patrick Boettcher ([email protected])
*
* based on GPL code from DibCom, which has
*
* Copyright (C) 2004 Amaury Demol for DiBcom
*
* Acknowledgements
*
* Amaury Demol from DiBcom for providing specs and driver
* sources, on which this driver (and the dvb-dibusb) are based.
*
* see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "dib3000.h"
#include "dib3000mb_priv.h"
/* Version information */
#define DRIVER_VERSION "0.1"
#define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
#define DRIVER_AUTHOR "Patrick Boettcher, [email protected]"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
#define deb_info(args...) dprintk(0x01, args)
#define deb_i2c(args...) dprintk(0x02, args)
#define deb_srch(args...) dprintk(0x04, args)
#define deb_info(args...) dprintk(0x01, args)
#define deb_xfer(args...) dprintk(0x02, args)
#define deb_setf(args...) dprintk(0x04, args)
#define deb_getf(args...) dprintk(0x08, args)
static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
{
u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
u8 rb[2];
struct i2c_msg msg[] = {
{ .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 },
{ .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
};
if (i2c_transfer(state->i2c, msg, 2) != 2)
deb_i2c("i2c read error\n");
deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
(rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
return (rb[0] << 8) | rb[1];
}
static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
{
u8 b[] = {
(reg >> 8) & 0xff, reg & 0xff,
(val >> 8) & 0xff, val & 0xff,
};
struct i2c_msg msg[] = {
{ .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
};
deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
}
static int dib3000_search_status(u16 irq,u16 lock)
{
if (irq & 0x02) {
if (lock & 0x01) {
deb_srch("auto search succeeded\n");
return 1; // auto search succeeded
} else {
deb_srch("auto search not successful\n");
return 0; // auto search failed
}
} else if (irq & 0x01) {
deb_srch("auto search failed\n");
return 0; // auto search failed
}
return -1; // try again
}
/* for auto search */
static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */
{ /* fft */
{ /* gua */
{ 0, 1 }, /* 0 0 { 0,1 } */
{ 3, 9 }, /* 0 1 { 0,1 } */
},
{
{ 2, 5 }, /* 1 0 { 0,1 } */
{ 6, 11 }, /* 1 1 { 0,1 } */
}
};
static int dib3000mb_get_frontend(struct dvb_frontend* fe,
struct dtv_frontend_properties *c);
static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
{
struct dib3000_state* state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
enum fe_code_rate fe_cr = FEC_NONE;
int search_state, seq;
if (tuner && fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
switch (c->bandwidth_hz) {
case 8000000:
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
break;
case 7000000:
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
break;
case 6000000:
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
break;
case 0:
return -EOPNOTSUPP;
default:
pr_err("unknown bandwidth value.\n");
return -EINVAL;
}
deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000);
}
wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
deb_setf("transmission mode: 2k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
break;
case TRANSMISSION_MODE_8K:
deb_setf("transmission mode: 8k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
break;
case TRANSMISSION_MODE_AUTO:
deb_setf("transmission mode: auto\n");
break;
default:
return -EINVAL;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_1_32:
deb_setf("guard 1_32\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
break;
case GUARD_INTERVAL_1_16:
deb_setf("guard 1_16\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
break;
case GUARD_INTERVAL_1_8:
deb_setf("guard 1_8\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
break;
case GUARD_INTERVAL_1_4:
deb_setf("guard 1_4\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
break;
case GUARD_INTERVAL_AUTO:
deb_setf("guard auto\n");
break;
default:
return -EINVAL;
}
switch (c->inversion) {
case INVERSION_OFF:
deb_setf("inversion off\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
break;
case INVERSION_AUTO:
deb_setf("inversion auto\n");
break;
case INVERSION_ON:
deb_setf("inversion on\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
break;
default:
return -EINVAL;
}
switch (c->modulation) {
case QPSK:
deb_setf("modulation: qpsk\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
break;
case QAM_16:
deb_setf("modulation: qam16\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
break;
case QAM_64:
deb_setf("modulation: qam64\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
break;
case QAM_AUTO:
break;
default:
return -EINVAL;
}
switch (c->hierarchy) {
case HIERARCHY_NONE:
deb_setf("hierarchy: none\n");
fallthrough;
case HIERARCHY_1:
deb_setf("hierarchy: alpha=1\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
break;
case HIERARCHY_2:
deb_setf("hierarchy: alpha=2\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
break;
case HIERARCHY_4:
deb_setf("hierarchy: alpha=4\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
break;
case HIERARCHY_AUTO:
deb_setf("hierarchy: alpha=auto\n");
break;
default:
return -EINVAL;
}
if (c->hierarchy == HIERARCHY_NONE) {
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
fe_cr = c->code_rate_HP;
} else if (c->hierarchy != HIERARCHY_AUTO) {
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
fe_cr = c->code_rate_LP;
}
switch (fe_cr) {
case FEC_1_2:
deb_setf("fec: 1_2\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
break;
case FEC_2_3:
deb_setf("fec: 2_3\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
break;
case FEC_3_4:
deb_setf("fec: 3_4\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
break;
case FEC_5_6:
deb_setf("fec: 5_6\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
break;
case FEC_7_8:
deb_setf("fec: 7_8\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
break;
case FEC_NONE:
deb_setf("fec: none\n");
break;
case FEC_AUTO:
deb_setf("fec: auto\n");
break;
default:
return -EINVAL;
}
seq = dib3000_seq
[c->transmission_mode == TRANSMISSION_MODE_AUTO]
[c->guard_interval == GUARD_INTERVAL_AUTO]
[c->inversion == INVERSION_AUTO];
deb_setf("seq? %d\n", seq);
wr(DIB3000MB_REG_SEQ, seq);
wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
if (c->transmission_mode == TRANSMISSION_MODE_2K) {
if (c->guard_interval == GUARD_INTERVAL_1_8) {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
} else {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
}
wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
} else {
wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
}
wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
/* wait for AGC lock */
msleep(70);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
/* something has to be auto searched */
if (c->modulation == QAM_AUTO ||
c->hierarchy == HIERARCHY_AUTO ||
fe_cr == FEC_AUTO ||
c->inversion == INVERSION_AUTO) {
int as_count=0;
deb_setf("autosearch enabled.\n");
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
while ((search_state =
dib3000_search_status(
rd(DIB3000MB_REG_AS_IRQ_PENDING),
rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
msleep(1);
deb_setf("search_state after autosearch %d after %d checks\n",
search_state, as_count);
if (search_state == 1) {
if (dib3000mb_get_frontend(fe, c) == 0) {
deb_setf("reading tuning data from frontend succeeded.\n");
return dib3000mb_set_frontend(fe, 0);
}
}
} else {
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
}
return 0;
}
static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
{
struct dib3000_state* state = fe->demodulator_priv;
deb_info("dib3000mb is getting up.\n");
wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_impulse_noise,
dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
return 0;
}
static int dib3000mb_get_frontend(struct dvb_frontend* fe,
struct dtv_frontend_properties *c)
{
struct dib3000_state* state = fe->demodulator_priv;
enum fe_code_rate *cr;
u16 tps_val;
int inv_test1,inv_test2;
u32 dds_val, threshold = 0x800000;
if (!rd(DIB3000MB_REG_TPS_LOCK))
return 0;
dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
if (dds_val < threshold)
inv_test1 = 0;
else if (dds_val == threshold)
inv_test1 = 1;
else
inv_test1 = 2;
dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
if (dds_val < threshold)
inv_test2 = 0;
else if (dds_val == threshold)
inv_test2 = 1;
else
inv_test2 = 2;
c->inversion =
((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
INVERSION_ON : INVERSION_OFF;
deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
case DIB3000_CONSTELLATION_QPSK:
deb_getf("QPSK\n");
c->modulation = QPSK;
break;
case DIB3000_CONSTELLATION_16QAM:
deb_getf("QAM16\n");
c->modulation = QAM_16;
break;
case DIB3000_CONSTELLATION_64QAM:
deb_getf("QAM64\n");
c->modulation = QAM_64;
break;
default:
pr_err("Unexpected constellation returned by TPS (%d)\n", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
if (rd(DIB3000MB_REG_TPS_HRCH)) {
deb_getf("HRCH ON\n");
cr = &c->code_rate_LP;
c->code_rate_HP = FEC_NONE;
switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
case DIB3000_ALPHA_0:
deb_getf("HIERARCHY_NONE\n");
c->hierarchy = HIERARCHY_NONE;
break;
case DIB3000_ALPHA_1:
deb_getf("HIERARCHY_1\n");
c->hierarchy = HIERARCHY_1;
break;
case DIB3000_ALPHA_2:
deb_getf("HIERARCHY_2\n");
c->hierarchy = HIERARCHY_2;
break;
case DIB3000_ALPHA_4:
deb_getf("HIERARCHY_4\n");
c->hierarchy = HIERARCHY_4;
break;
default:
pr_err("Unexpected ALPHA value returned by TPS (%d)\n", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
} else {
deb_getf("HRCH OFF\n");
cr = &c->code_rate_HP;
c->code_rate_LP = FEC_NONE;
c->hierarchy = HIERARCHY_NONE;
tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
}
switch (tps_val) {
case DIB3000_FEC_1_2:
deb_getf("FEC_1_2\n");
*cr = FEC_1_2;
break;
case DIB3000_FEC_2_3:
deb_getf("FEC_2_3\n");
*cr = FEC_2_3;
break;
case DIB3000_FEC_3_4:
deb_getf("FEC_3_4\n");
*cr = FEC_3_4;
break;
case DIB3000_FEC_5_6:
deb_getf("FEC_5_6\n");
*cr = FEC_4_5;
break;
case DIB3000_FEC_7_8:
deb_getf("FEC_7_8\n");
*cr = FEC_7_8;
break;
default:
pr_err("Unexpected FEC returned by TPS (%d)\n", tps_val);
break;
}
deb_getf("TPS: %d\n",tps_val);
switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
case DIB3000_GUARD_TIME_1_32:
deb_getf("GUARD_INTERVAL_1_32\n");
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case DIB3000_GUARD_TIME_1_16:
deb_getf("GUARD_INTERVAL_1_16\n");
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case DIB3000_GUARD_TIME_1_8:
deb_getf("GUARD_INTERVAL_1_8\n");
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case DIB3000_GUARD_TIME_1_4:
deb_getf("GUARD_INTERVAL_1_4\n");
c->guard_interval = GUARD_INTERVAL_1_4;
break;
default:
pr_err("Unexpected Guard Time returned by TPS (%d)\n", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
case DIB3000_TRANSMISSION_MODE_2K:
deb_getf("TRANSMISSION_MODE_2K\n");
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case DIB3000_TRANSMISSION_MODE_8K:
deb_getf("TRANSMISSION_MODE_8K\n");
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
pr_err("unexpected transmission mode return by TPS (%d)\n", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
return 0;
}
static int dib3000mb_read_status(struct dvb_frontend *fe,
enum fe_status *stat)
{
struct dib3000_state* state = fe->demodulator_priv;
*stat = 0;
if (rd(DIB3000MB_REG_AGC_LOCK))
*stat |= FE_HAS_SIGNAL;
if (rd(DIB3000MB_REG_CARRIER_LOCK))
*stat |= FE_HAS_CARRIER;
if (rd(DIB3000MB_REG_VIT_LCK))
*stat |= FE_HAS_VITERBI;
if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
*stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
deb_getf("actual status is %2x\n",*stat);
deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
rd(DIB3000MB_REG_TPS_LOCK),
rd(DIB3000MB_REG_TPS_QAM),
rd(DIB3000MB_REG_TPS_HRCH),
rd(DIB3000MB_REG_TPS_VIT_ALPHA),
rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
rd(DIB3000MB_REG_TPS_GUARD_TIME),
rd(DIB3000MB_REG_TPS_FFT),
rd(DIB3000MB_REG_TPS_CELL_ID));
//*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
{
struct dib3000_state* state = fe->demodulator_priv;
*ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
return 0;
}
/* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
{
struct dib3000_state* state = fe->demodulator_priv;
*strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
return 0;
}
static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
{
struct dib3000_state* state = fe->demodulator_priv;
short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
rd(DIB3000MB_REG_NOISE_POWER_LSB);
*snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
return 0;
}
static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
{
struct dib3000_state* state = fe->demodulator_priv;
*unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
return 0;
}
static int dib3000mb_sleep(struct dvb_frontend* fe)
{
struct dib3000_state* state = fe->demodulator_priv;
deb_info("dib3000mb is going to bed.\n");
wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
return 0;
}
static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 800;
return 0;
}
static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
{
return dib3000mb_fe_init(fe, 0);
}
static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
{
return dib3000mb_set_frontend(fe, 1);
}
static void dib3000mb_release(struct dvb_frontend* fe)
{
struct dib3000_state *state = fe->demodulator_priv;
kfree(state);
}
/* pid filter and transfer stuff */
static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
wr(index+DIB3000MB_REG_FIRST_PID,pid);
return 0;
}
static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
if (onoff) {
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
} else {
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
}
return 0;
}
static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
wr(DIB3000MB_REG_PID_PARSE,onoff);
return 0;
}
static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
{
struct dib3000_state *state = fe->demodulator_priv;
if (onoff) {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
} else {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
}
return 0;
}
static const struct dvb_frontend_ops dib3000mb_ops;
struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
{
struct dib3000_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
memcpy(&state->config,config,sizeof(struct dib3000_config));
/* check for the correct demod */
if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
goto error;
if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* set the xfer operations */
xfer_ops->pid_parse = dib3000mb_pid_parse;
xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
xfer_ops->pid_ctrl = dib3000mb_pid_control;
xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops dib3000mb_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 3000M-B DVB-T",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = dib3000mb_release,
.init = dib3000mb_fe_init_nonmobile,
.sleep = dib3000mb_sleep,
.set_frontend = dib3000mb_set_frontend_and_tuner,
.get_frontend = dib3000mb_get_frontend,
.get_tune_settings = dib3000mb_fe_get_tune_settings,
.read_status = dib3000mb_read_status,
.read_ber = dib3000mb_read_ber,
.read_signal_strength = dib3000mb_read_signal_strength,
.read_snr = dib3000mb_read_snr,
.read_ucblocks = dib3000mb_read_unc_blocks,
};
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(dib3000mb_attach);
| linux-master | drivers/media/dvb-frontends/dib3000mb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Sharp VA3A5JZ921 One Seg Broadcast Module driver
* This device is labeled as just S. 921 at the top of the frontend can
*
* Copyright (C) 2009-2010 Mauro Carvalho Chehab
* Copyright (C) 2009-2010 Douglas Landgraf <[email protected]>
*
* Developed for Leadership SBTVD 1seg device sold in Brazil
*
* Frontend module based on cx24123 driver, getting some info from
* the old s921 driver.
*
* FIXME: Need to port to DVB v5.2 API
*/
#include <linux/kernel.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "s921.h"
static int debug = 1;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
#define rc(args...) do { \
printk(KERN_ERR "s921: " args); \
} while (0)
#define dprintk(args...) \
do { \
if (debug) { \
printk(KERN_DEBUG "s921: %s: ", __func__); \
printk(args); \
} \
} while (0)
struct s921_state {
struct i2c_adapter *i2c;
const struct s921_config *config;
struct dvb_frontend frontend;
/* The Demod can't easily provide these, we cache them */
u32 currentfreq;
};
/*
* Various tuner defaults need to be established for a given frequency kHz.
* fixme: The bounds on the bands do not match the doc in real life.
* fixme: Some of them have been moved, other might need adjustment.
*/
static struct s921_bandselect_val {
u32 freq_low;
u8 band_reg;
} s921_bandselect[] = {
{ 0, 0x7b },
{ 485140000, 0x5b },
{ 515140000, 0x3b },
{ 545140000, 0x1b },
{ 599140000, 0xfb },
{ 623140000, 0xdb },
{ 659140000, 0xbb },
{ 713140000, 0x9b },
};
struct regdata {
u8 reg;
u8 data;
};
static struct regdata s921_init[] = {
{ 0x01, 0x80 }, /* Probably, a reset sequence */
{ 0x01, 0x40 },
{ 0x01, 0x80 },
{ 0x01, 0x40 },
{ 0x02, 0x00 },
{ 0x03, 0x40 },
{ 0x04, 0x01 },
{ 0x05, 0x00 },
{ 0x06, 0x00 },
{ 0x07, 0x00 },
{ 0x08, 0x00 },
{ 0x09, 0x00 },
{ 0x0a, 0x00 },
{ 0x0b, 0x5a },
{ 0x0c, 0x00 },
{ 0x0d, 0x00 },
{ 0x0f, 0x00 },
{ 0x13, 0x1b },
{ 0x14, 0x80 },
{ 0x15, 0x40 },
{ 0x17, 0x70 },
{ 0x18, 0x01 },
{ 0x19, 0x12 },
{ 0x1a, 0x01 },
{ 0x1b, 0x12 },
{ 0x1c, 0xa0 },
{ 0x1d, 0x00 },
{ 0x1e, 0x0a },
{ 0x1f, 0x08 },
{ 0x20, 0x40 },
{ 0x21, 0xff },
{ 0x22, 0x4c },
{ 0x23, 0x4e },
{ 0x24, 0x4c },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0xf4 },
{ 0x28, 0x60 },
{ 0x29, 0x88 },
{ 0x2a, 0x40 },
{ 0x2b, 0x40 },
{ 0x2c, 0xff },
{ 0x2d, 0x00 },
{ 0x2e, 0xff },
{ 0x2f, 0x00 },
{ 0x30, 0x20 },
{ 0x31, 0x06 },
{ 0x32, 0x0c },
{ 0x34, 0x0f },
{ 0x37, 0xfe },
{ 0x38, 0x00 },
{ 0x39, 0x63 },
{ 0x3a, 0x10 },
{ 0x3b, 0x10 },
{ 0x47, 0x00 },
{ 0x49, 0xe5 },
{ 0x4b, 0x00 },
{ 0x50, 0xc0 },
{ 0x52, 0x20 },
{ 0x54, 0x5a },
{ 0x55, 0x5b },
{ 0x56, 0x40 },
{ 0x57, 0x70 },
{ 0x5c, 0x50 },
{ 0x5d, 0x00 },
{ 0x62, 0x17 },
{ 0x63, 0x2f },
{ 0x64, 0x6f },
{ 0x68, 0x00 },
{ 0x69, 0x89 },
{ 0x6a, 0x00 },
{ 0x6b, 0x00 },
{ 0x6c, 0x00 },
{ 0x6d, 0x00 },
{ 0x6e, 0x00 },
{ 0x70, 0x10 },
{ 0x71, 0x00 },
{ 0x75, 0x00 },
{ 0x76, 0x30 },
{ 0x77, 0x01 },
{ 0xaf, 0x00 },
{ 0xb0, 0xa0 },
{ 0xb2, 0x3d },
{ 0xb3, 0x25 },
{ 0xb4, 0x8b },
{ 0xb5, 0x4b },
{ 0xb6, 0x3f },
{ 0xb7, 0xff },
{ 0xb8, 0xff },
{ 0xb9, 0xfc },
{ 0xba, 0x00 },
{ 0xbb, 0x00 },
{ 0xbc, 0x00 },
{ 0xd0, 0x30 },
{ 0xe4, 0x84 },
{ 0xf0, 0x48 },
{ 0xf1, 0x19 },
{ 0xf2, 0x5a },
{ 0xf3, 0x8e },
{ 0xf4, 0x2d },
{ 0xf5, 0x07 },
{ 0xf6, 0x5a },
{ 0xf7, 0xba },
{ 0xf8, 0xd7 },
};
static struct regdata s921_prefreq[] = {
{ 0x47, 0x60 },
{ 0x68, 0x00 },
{ 0x69, 0x89 },
{ 0xf0, 0x48 },
{ 0xf1, 0x19 },
};
static struct regdata s921_postfreq[] = {
{ 0xf5, 0xae },
{ 0xf6, 0xb7 },
{ 0xf7, 0xba },
{ 0xf8, 0xd7 },
{ 0x68, 0x0a },
{ 0x69, 0x09 },
};
static int s921_i2c_writereg(struct s921_state *state,
u8 i2c_addr, int reg, int data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
};
int rc;
rc = i2c_transfer(state->i2c, &msg, 1);
if (rc != 1) {
printk("%s: writereg rcor(rc == %i, reg == 0x%02x, data == 0x%02x)\n",
__func__, rc, reg, data);
return rc;
}
return 0;
}
static int s921_i2c_writeregdata(struct s921_state *state, u8 i2c_addr,
struct regdata *rd, int size)
{
int i, rc;
for (i = 0; i < size; i++) {
rc = s921_i2c_writereg(state, i2c_addr, rd[i].reg, rd[i].data);
if (rc < 0)
return rc;
}
return 0;
}
static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg)
{
u8 val;
int rc;
struct i2c_msg msg[] = {
{ .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
};
rc = i2c_transfer(state->i2c, msg, 2);
if (rc != 2) {
rc("%s: reg=0x%x (rcor=%d)\n", __func__, reg, rc);
return rc;
}
return val;
}
#define s921_readreg(state, reg) \
s921_i2c_readreg(state, state->config->demod_address, reg)
#define s921_writereg(state, reg, val) \
s921_i2c_writereg(state, state->config->demod_address, reg, val)
#define s921_writeregdata(state, regdata) \
s921_i2c_writeregdata(state, state->config->demod_address, \
regdata, ARRAY_SIZE(regdata))
static int s921_pll_tune(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s921_state *state = fe->demodulator_priv;
int band, rc, i;
unsigned long f_offset;
u8 f_switch;
u64 offset;
dprintk("frequency=%i\n", p->frequency);
for (band = 0; band < ARRAY_SIZE(s921_bandselect); band++)
if (p->frequency < s921_bandselect[band].freq_low)
break;
band--;
if (band < 0) {
rc("%s: frequency out of range\n", __func__);
return -EINVAL;
}
f_switch = s921_bandselect[band].band_reg;
offset = ((u64)p->frequency) * 258;
do_div(offset, 6000000);
f_offset = ((unsigned long)offset) + 2321;
rc = s921_writeregdata(state, s921_prefreq);
if (rc < 0)
return rc;
rc = s921_writereg(state, 0xf2, (f_offset >> 8) & 0xff);
if (rc < 0)
return rc;
rc = s921_writereg(state, 0xf3, f_offset & 0xff);
if (rc < 0)
return rc;
rc = s921_writereg(state, 0xf4, f_switch);
if (rc < 0)
return rc;
rc = s921_writeregdata(state, s921_postfreq);
if (rc < 0)
return rc;
for (i = 0 ; i < 6; i++) {
rc = s921_readreg(state, 0x80);
dprintk("status 0x80: %02x\n", rc);
}
rc = s921_writereg(state, 0x01, 0x40);
if (rc < 0)
return rc;
rc = s921_readreg(state, 0x01);
dprintk("status 0x01: %02x\n", rc);
rc = s921_readreg(state, 0x80);
dprintk("status 0x80: %02x\n", rc);
rc = s921_readreg(state, 0x80);
dprintk("status 0x80: %02x\n", rc);
rc = s921_readreg(state, 0x32);
dprintk("status 0x32: %02x\n", rc);
dprintk("pll tune band=%d, pll=%d\n", f_switch, (int)f_offset);
return 0;
}
static int s921_initfe(struct dvb_frontend *fe)
{
struct s921_state *state = fe->demodulator_priv;
int rc;
dprintk("\n");
rc = s921_writeregdata(state, s921_init);
if (rc < 0)
return rc;
return 0;
}
static int s921_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct s921_state *state = fe->demodulator_priv;
int regstatus, rc;
*status = 0;
rc = s921_readreg(state, 0x81);
if (rc < 0)
return rc;
regstatus = rc << 8;
rc = s921_readreg(state, 0x82);
if (rc < 0)
return rc;
regstatus |= rc;
dprintk("status = %04x\n", regstatus);
/* Full Sync - We don't know what each bit means on regs 0x81/0x82 */
if ((regstatus & 0xff) == 0x40) {
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER |
FE_HAS_VITERBI |
FE_HAS_SYNC |
FE_HAS_LOCK;
} else if (regstatus & 0x40) {
/* This is close to Full Sync, but not enough to get useful info */
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER |
FE_HAS_VITERBI |
FE_HAS_SYNC;
}
return 0;
}
static int s921_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
enum fe_status status;
struct s921_state *state = fe->demodulator_priv;
int rc;
/* FIXME: Use the proper register for it... 0x80? */
rc = s921_read_status(fe, &status);
if (rc < 0)
return rc;
*strength = (status & FE_HAS_LOCK) ? 0xffff : 0;
dprintk("strength = 0x%04x\n", *strength);
rc = s921_readreg(state, 0x01);
dprintk("status 0x01: %02x\n", rc);
rc = s921_readreg(state, 0x80);
dprintk("status 0x80: %02x\n", rc);
rc = s921_readreg(state, 0x32);
dprintk("status 0x32: %02x\n", rc);
return 0;
}
static int s921_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s921_state *state = fe->demodulator_priv;
int rc;
dprintk("\n");
/* FIXME: We don't know how to use non-auto mode */
rc = s921_pll_tune(fe);
if (rc < 0)
return rc;
state->currentfreq = p->frequency;
return 0;
}
static int s921_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct s921_state *state = fe->demodulator_priv;
/* FIXME: Probably it is possible to get it from regs f1 and f2 */
p->frequency = state->currentfreq;
p->delivery_system = SYS_ISDBT;
return 0;
}
static int s921_tune(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
int rc = 0;
dprintk("\n");
if (re_tune)
rc = s921_set_frontend(fe);
if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
s921_read_status(fe, status);
return rc;
}
static enum dvbfe_algo s921_get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static void s921_release(struct dvb_frontend *fe)
{
struct s921_state *state = fe->demodulator_priv;
dprintk("\n");
kfree(state);
}
static const struct dvb_frontend_ops s921_ops;
struct dvb_frontend *s921_attach(const struct s921_config *config,
struct i2c_adapter *i2c)
{
/* allocate memory for the internal state */
struct s921_state *state =
kzalloc(sizeof(struct s921_state), GFP_KERNEL);
dprintk("\n");
if (!state) {
rc("Unable to kzalloc\n");
return NULL;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s921_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL_GPL(s921_attach);
static const struct dvb_frontend_ops s921_ops = {
.delsys = { SYS_ISDBT },
/* Use dib8000 values per default */
.info = {
.name = "Sharp S921",
.frequency_min_hz = 470 * MHz,
/*
* Max should be 770MHz instead, according with Sharp docs,
* but Leadership doc says it works up to 806 MHz. This is
* required to get channel 69, used in Brazil
*/
.frequency_max_hz = 806 * MHz,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = s921_release,
.init = s921_initfe,
.set_frontend = s921_set_frontend,
.get_frontend = s921_get_frontend,
.read_status = s921_read_status,
.read_signal_strength = s921_read_signal_strength,
.tune = s921_tune,
.get_frontend_algo = s921_get_algo,
};
MODULE_DESCRIPTION("DVB Frontend module for Sharp S921 hardware");
MODULE_AUTHOR("Mauro Carvalho Chehab");
MODULE_AUTHOR("Douglas Landgraf <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/s921.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
*
* Copyright (C) 2008, 2009, 2010 Michael Krufky <[email protected]>
*
* LGDT3304 support by Jarod Wilson <[email protected]>
*/
#include <asm/div64.h>
#include <linux/dvb/frontend.h>
#include <linux/slab.h>
#include <linux/int_log.h>
#include "lgdt3305.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
#define DBG_INFO 1
#define DBG_REG 2
#define lg_printk(kern, fmt, arg...) \
printk(kern "%s: " fmt, __func__, ##arg)
#define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
#define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
#define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
#define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
lg_printk(KERN_DEBUG, fmt, ##arg)
#define lg_reg(fmt, arg...) if (debug & DBG_REG) \
lg_printk(KERN_DEBUG, fmt, ##arg)
#define lg_fail(ret) \
({ \
int __ret; \
__ret = (ret < 0); \
if (__ret) \
lg_err("error %d on line %d\n", ret, __LINE__); \
__ret; \
})
struct lgdt3305_state {
struct i2c_adapter *i2c_adap;
const struct lgdt3305_config *cfg;
struct dvb_frontend frontend;
enum fe_modulation current_modulation;
u32 current_frequency;
u32 snr;
};
/* ------------------------------------------------------------------------ */
/* FIXME: verify & document the LGDT3304 registers */
#define LGDT3305_GEN_CTRL_1 0x0000
#define LGDT3305_GEN_CTRL_2 0x0001
#define LGDT3305_GEN_CTRL_3 0x0002
#define LGDT3305_GEN_STATUS 0x0003
#define LGDT3305_GEN_CONTROL 0x0007
#define LGDT3305_GEN_CTRL_4 0x000a
#define LGDT3305_DGTL_AGC_REF_1 0x0012
#define LGDT3305_DGTL_AGC_REF_2 0x0013
#define LGDT3305_CR_CTR_FREQ_1 0x0106
#define LGDT3305_CR_CTR_FREQ_2 0x0107
#define LGDT3305_CR_CTR_FREQ_3 0x0108
#define LGDT3305_CR_CTR_FREQ_4 0x0109
#define LGDT3305_CR_MSE_1 0x011b
#define LGDT3305_CR_MSE_2 0x011c
#define LGDT3305_CR_LOCK_STATUS 0x011d
#define LGDT3305_CR_CTRL_7 0x0126
#define LGDT3305_AGC_POWER_REF_1 0x0300
#define LGDT3305_AGC_POWER_REF_2 0x0301
#define LGDT3305_AGC_DELAY_PT_1 0x0302
#define LGDT3305_AGC_DELAY_PT_2 0x0303
#define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
#define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
#define LGDT3305_IFBW_1 0x0308
#define LGDT3305_IFBW_2 0x0309
#define LGDT3305_AGC_CTRL_1 0x030c
#define LGDT3305_AGC_CTRL_4 0x0314
#define LGDT3305_EQ_MSE_1 0x0413
#define LGDT3305_EQ_MSE_2 0x0414
#define LGDT3305_EQ_MSE_3 0x0415
#define LGDT3305_PT_MSE_1 0x0417
#define LGDT3305_PT_MSE_2 0x0418
#define LGDT3305_PT_MSE_3 0x0419
#define LGDT3305_FEC_BLOCK_CTRL 0x0504
#define LGDT3305_FEC_LOCK_STATUS 0x050a
#define LGDT3305_FEC_PKT_ERR_1 0x050c
#define LGDT3305_FEC_PKT_ERR_2 0x050d
#define LGDT3305_TP_CTRL_1 0x050e
#define LGDT3305_BERT_PERIOD 0x0801
#define LGDT3305_BERT_ERROR_COUNT_1 0x080a
#define LGDT3305_BERT_ERROR_COUNT_2 0x080b
#define LGDT3305_BERT_ERROR_COUNT_3 0x080c
#define LGDT3305_BERT_ERROR_COUNT_4 0x080d
static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
{
int ret;
u8 buf[] = { reg >> 8, reg & 0xff, val };
struct i2c_msg msg = {
.addr = state->cfg->i2c_addr, .flags = 0,
.buf = buf, .len = 3,
};
lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
if (ret != 1) {
lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
msg.buf[0], msg.buf[1], msg.buf[2], ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
return 0;
}
static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
{
int ret;
u8 reg_buf[] = { reg >> 8, reg & 0xff };
struct i2c_msg msg[] = {
{ .addr = state->cfg->i2c_addr,
.flags = 0, .buf = reg_buf, .len = 2 },
{ .addr = state->cfg->i2c_addr,
.flags = I2C_M_RD, .buf = val, .len = 1 },
};
lg_reg("reg: 0x%04x\n", reg);
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
lg_err("error (addr %02x reg %04x error (ret == %i)\n",
state->cfg->i2c_addr, reg, ret);
if (ret < 0)
return ret;
else
return -EREMOTEIO;
}
return 0;
}
#define read_reg(state, reg) \
({ \
u8 __val; \
int ret = lgdt3305_read_reg(state, reg, &__val); \
if (lg_fail(ret)) \
__val = 0; \
__val; \
})
static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
u16 reg, int bit, int onoff)
{
u8 val;
int ret;
lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
ret = lgdt3305_read_reg(state, reg, &val);
if (lg_fail(ret))
goto fail;
val &= ~(1 << bit);
val |= (onoff & 1) << bit;
ret = lgdt3305_write_reg(state, reg, val);
fail:
return ret;
}
struct lgdt3305_reg {
u16 reg;
u8 val;
};
static int lgdt3305_write_regs(struct lgdt3305_state *state,
struct lgdt3305_reg *regs, int len)
{
int i, ret;
lg_reg("writing %d registers...\n", len);
for (i = 0; i < len - 1; i++) {
ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
if (lg_fail(ret))
return ret;
}
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_soft_reset(struct lgdt3305_state *state)
{
int ret;
lg_dbg("\n");
ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
if (lg_fail(ret))
goto fail;
msleep(20);
ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
fail:
return ret;
}
static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
enum lgdt3305_mpeg_mode mode)
{
lg_dbg("(%d)\n", mode);
return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
}
static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
{
u8 val;
int ret;
enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
lg_dbg("edge = %d, valid = %d\n", edge, valid);
ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
if (lg_fail(ret))
goto fail;
val &= ~0x09;
if (edge)
val |= 0x08;
if (mode)
val |= 0x40;
if (valid)
val |= 0x01;
ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_soft_reset(state);
fail:
return ret;
}
static int lgdt3305_set_modulation(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
u8 opermode;
int ret;
lg_dbg("\n");
ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
if (lg_fail(ret))
goto fail;
opermode &= ~0x03;
switch (p->modulation) {
case VSB_8:
opermode |= 0x03;
break;
case QAM_64:
opermode |= 0x00;
break;
case QAM_256:
opermode |= 0x01;
break;
default:
return -EINVAL;
}
ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
fail:
return ret;
}
static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
int val;
switch (p->modulation) {
case VSB_8:
val = 0;
break;
case QAM_64:
case QAM_256:
val = 1;
break;
default:
return -EINVAL;
}
lg_dbg("val = %d\n", val);
return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
u16 agc_ref;
switch (p->modulation) {
case VSB_8:
agc_ref = 0x32c4;
break;
case QAM_64:
agc_ref = 0x2a00;
break;
case QAM_256:
agc_ref = 0x2a80;
break;
default:
return -EINVAL;
}
lg_dbg("agc ref: 0x%04x\n", agc_ref);
lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
return 0;
}
static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
u16 ifbw, rfbw, agcdelay;
switch (p->modulation) {
case VSB_8:
agcdelay = 0x04c0;
rfbw = 0x8000;
ifbw = 0x8000;
break;
case QAM_64:
case QAM_256:
agcdelay = 0x046b;
rfbw = 0x8889;
/* FIXME: investigate optimal ifbw & rfbw values for the
* DT3304 and re-write this switch..case block */
if (state->cfg->demod_chip == LGDT3304)
ifbw = 0x6666;
else /* (state->cfg->demod_chip == LGDT3305) */
ifbw = 0x8888;
break;
default:
return -EINVAL;
}
if (state->cfg->rf_agc_loop) {
lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
/* rf agc loop filter bandwidth */
lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
agcdelay >> 8);
lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
agcdelay & 0xff);
lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
rfbw >> 8);
lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
rfbw & 0xff);
} else {
lg_dbg("ifbw: 0x%04x\n", ifbw);
/* if agc loop filter bandwidth */
lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
}
return 0;
}
static int lgdt3305_agc_setup(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
int lockdten, acqen;
switch (p->modulation) {
case VSB_8:
lockdten = 0;
acqen = 0;
break;
case QAM_64:
case QAM_256:
lockdten = 1;
acqen = 1;
break;
default:
return -EINVAL;
}
lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
/* control agc function */
switch (state->cfg->demod_chip) {
case LGDT3304:
lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
break;
case LGDT3305:
lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
break;
default:
return -EINVAL;
}
return lgdt3305_rfagc_loop(state, p);
}
static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
u16 usref = 0;
switch (p->modulation) {
case VSB_8:
if (state->cfg->usref_8vsb)
usref = state->cfg->usref_8vsb;
break;
case QAM_64:
if (state->cfg->usref_qam64)
usref = state->cfg->usref_qam64;
break;
case QAM_256:
if (state->cfg->usref_qam256)
usref = state->cfg->usref_qam256;
break;
default:
return -EINVAL;
}
if (usref) {
lg_dbg("set manual mode: 0x%04x\n", usref);
lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
0xff & (usref >> 8));
lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
0xff & (usref >> 0));
}
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
struct dtv_frontend_properties *p,
int inversion)
{
int ret;
lg_dbg("(%d)\n", inversion);
switch (p->modulation) {
case VSB_8:
ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
inversion ? 0xf9 : 0x79);
break;
case QAM_64:
case QAM_256:
ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
inversion ? 0xfd : 0xff);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int lgdt3305_set_if(struct lgdt3305_state *state,
struct dtv_frontend_properties *p)
{
u16 if_freq_khz;
u8 nco1, nco2, nco3, nco4;
u64 nco;
switch (p->modulation) {
case VSB_8:
if_freq_khz = state->cfg->vsb_if_khz;
break;
case QAM_64:
case QAM_256:
if_freq_khz = state->cfg->qam_if_khz;
break;
default:
return -EINVAL;
}
nco = if_freq_khz / 10;
switch (p->modulation) {
case VSB_8:
nco <<= 24;
do_div(nco, 625);
break;
case QAM_64:
case QAM_256:
nco <<= 28;
do_div(nco, 625);
break;
default:
return -EINVAL;
}
nco1 = (nco >> 24) & 0x3f;
nco1 |= 0x40;
nco2 = (nco >> 16) & 0xff;
nco3 = (nco >> 8) & 0xff;
nco4 = nco & 0xff;
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
if_freq_khz, nco1, nco2, nco3, nco4);
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct lgdt3305_state *state = fe->demodulator_priv;
if (state->cfg->deny_i2c_rptr)
return 0;
lg_dbg("(%d)\n", enable);
return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
enable ? 0 : 1);
}
static int lgdt3305_sleep(struct dvb_frontend *fe)
{
struct lgdt3305_state *state = fe->demodulator_priv;
u8 gen_ctrl_3, gen_ctrl_4;
lg_dbg("\n");
gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
/* hold in software reset while sleeping */
gen_ctrl_3 &= ~0x01;
/* tristate the IF-AGC pin */
gen_ctrl_3 |= 0x02;
/* tristate the RF-AGC pin */
gen_ctrl_3 |= 0x04;
/* disable vsb/qam module */
gen_ctrl_4 &= ~0x01;
/* disable adc module */
gen_ctrl_4 &= ~0x02;
lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
return 0;
}
static int lgdt3305_init(struct dvb_frontend *fe)
{
struct lgdt3305_state *state = fe->demodulator_priv;
int ret;
static struct lgdt3305_reg lgdt3304_init_data[] = {
{ .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
{ .reg = 0x000d, .val = 0x02, },
{ .reg = 0x000e, .val = 0x02, },
{ .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
{ .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
{ .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
{ .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, },
{ .reg = 0x0112, .val = 0x17, },
{ .reg = 0x0113, .val = 0x15, },
{ .reg = 0x0114, .val = 0x18, },
{ .reg = 0x0115, .val = 0xff, },
{ .reg = 0x0116, .val = 0x3c, },
{ .reg = 0x0214, .val = 0x67, },
{ .reg = 0x0424, .val = 0x8d, },
{ .reg = 0x0427, .val = 0x12, },
{ .reg = 0x0428, .val = 0x4f, },
{ .reg = LGDT3305_IFBW_1, .val = 0x80, },
{ .reg = LGDT3305_IFBW_2, .val = 0x00, },
{ .reg = 0x030a, .val = 0x08, },
{ .reg = 0x030b, .val = 0x9b, },
{ .reg = 0x030d, .val = 0x00, },
{ .reg = 0x030e, .val = 0x1c, },
{ .reg = 0x0314, .val = 0xe1, },
{ .reg = 0x000d, .val = 0x82, },
{ .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
{ .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
};
static struct lgdt3305_reg lgdt3305_init_data[] = {
{ .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
{ .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
{ .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
{ .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
{ .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
{ .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
{ .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
{ .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
{ .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
{ .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
{ .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
{ .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
{ .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
{ .reg = LGDT3305_IFBW_1, .val = 0x80, },
{ .reg = LGDT3305_IFBW_2, .val = 0x00, },
{ .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
{ .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
{ .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
{ .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
};
lg_dbg("\n");
switch (state->cfg->demod_chip) {
case LGDT3304:
ret = lgdt3305_write_regs(state, lgdt3304_init_data,
ARRAY_SIZE(lgdt3304_init_data));
break;
case LGDT3305:
ret = lgdt3305_write_regs(state, lgdt3305_init_data,
ARRAY_SIZE(lgdt3305_init_data));
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
ret = lgdt3305_soft_reset(state);
fail:
return ret;
}
static int lgdt3304_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct lgdt3305_state *state = fe->demodulator_priv;
int ret;
lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (lg_fail(ret))
goto fail;
state->current_frequency = p->frequency;
}
ret = lgdt3305_set_modulation(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_passband_digital_agc(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_agc_setup(state, p);
if (lg_fail(ret))
goto fail;
/* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
switch (p->modulation) {
case VSB_8:
lgdt3305_write_reg(state, 0x030d, 0x00);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
break;
case QAM_64:
case QAM_256:
lgdt3305_write_reg(state, 0x030d, 0x14);
ret = lgdt3305_set_if(state, p);
if (lg_fail(ret))
goto fail;
break;
default:
return -EINVAL;
}
ret = lgdt3305_spectral_inversion(state, p,
state->cfg->spectral_inversion
? 1 : 0);
if (lg_fail(ret))
goto fail;
state->current_modulation = p->modulation;
ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
if (lg_fail(ret))
goto fail;
/* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
ret = lgdt3305_mpeg_mode_polarity(state);
fail:
return ret;
}
static int lgdt3305_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct lgdt3305_state *state = fe->demodulator_priv;
int ret;
lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (lg_fail(ret))
goto fail;
state->current_frequency = p->frequency;
}
ret = lgdt3305_set_modulation(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_passband_digital_agc(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_set_agc_power_ref(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_agc_setup(state, p);
if (lg_fail(ret))
goto fail;
/* low if */
ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_set_if(state, p);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_spectral_inversion(state, p,
state->cfg->spectral_inversion
? 1 : 0);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_set_filter_extension(state, p);
if (lg_fail(ret))
goto fail;
state->current_modulation = p->modulation;
ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
if (lg_fail(ret))
goto fail;
/* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
ret = lgdt3305_mpeg_mode_polarity(state);
fail:
return ret;
}
static int lgdt3305_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct lgdt3305_state *state = fe->demodulator_priv;
lg_dbg("\n");
p->modulation = state->current_modulation;
p->frequency = state->current_frequency;
return 0;
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
int *locked)
{
u8 val;
int ret;
char *cr_lock_state = "";
*locked = 0;
ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
if (lg_fail(ret))
goto fail;
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
if (val & (1 << 1))
*locked = 1;
switch (val & 0x07) {
case 0:
cr_lock_state = "QAM UNLOCK";
break;
case 4:
cr_lock_state = "QAM 1stLock";
break;
case 6:
cr_lock_state = "QAM 2ndLock";
break;
case 7:
cr_lock_state = "QAM FinalLock";
break;
default:
cr_lock_state = "CLOCKQAM-INVALID!";
break;
}
break;
case VSB_8:
if (val & (1 << 7)) {
*locked = 1;
cr_lock_state = "CLOCKVSB";
}
break;
default:
ret = -EINVAL;
}
lg_dbg("(%d) %s\n", *locked, cr_lock_state);
fail:
return ret;
}
static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
int *locked)
{
u8 val;
int ret, mpeg_lock, fec_lock, viterbi_lock;
*locked = 0;
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
ret = lgdt3305_read_reg(state,
LGDT3305_FEC_LOCK_STATUS, &val);
if (lg_fail(ret))
goto fail;
mpeg_lock = (val & (1 << 0)) ? 1 : 0;
fec_lock = (val & (1 << 2)) ? 1 : 0;
viterbi_lock = (val & (1 << 3)) ? 1 : 0;
*locked = mpeg_lock && fec_lock && viterbi_lock;
lg_dbg("(%d) %s%s%s\n", *locked,
mpeg_lock ? "mpeg lock " : "",
fec_lock ? "fec lock " : "",
viterbi_lock ? "viterbi lock" : "");
break;
case VSB_8:
default:
ret = -EINVAL;
}
fail:
return ret;
}
static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct lgdt3305_state *state = fe->demodulator_priv;
u8 val;
int ret, signal, inlock, nofecerr, snrgood,
cr_lock, fec_lock, sync_lock;
*status = 0;
ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
if (lg_fail(ret))
goto fail;
signal = (val & (1 << 4)) ? 1 : 0;
inlock = (val & (1 << 3)) ? 0 : 1;
sync_lock = (val & (1 << 2)) ? 1 : 0;
nofecerr = (val & (1 << 1)) ? 1 : 0;
snrgood = (val & (1 << 0)) ? 1 : 0;
lg_dbg("%s%s%s%s%s\n",
signal ? "SIGNALEXIST " : "",
inlock ? "INLOCK " : "",
sync_lock ? "SYNCLOCK " : "",
nofecerr ? "NOFECERR " : "",
snrgood ? "SNRGOOD " : "");
ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
if (lg_fail(ret))
goto fail;
if (signal)
*status |= FE_HAS_SIGNAL;
if (cr_lock)
*status |= FE_HAS_CARRIER;
if (nofecerr)
*status |= FE_HAS_VITERBI;
if (sync_lock)
*status |= FE_HAS_SYNC;
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
/* signal bit is unreliable on the DT3304 in QAM mode */
if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
*status |= FE_HAS_SIGNAL;
ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
if (lg_fail(ret))
goto fail;
if (fec_lock)
*status |= FE_HAS_LOCK;
break;
case VSB_8:
if (inlock)
*status |= FE_HAS_LOCK;
break;
default:
ret = -EINVAL;
}
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
/* borrowed from lgdt330x.c */
static u32 calculate_snr(u32 mse, u32 c)
{
if (mse == 0) /* no signal */
return 0;
mse = intlog10(mse);
if (mse > c) {
/* Negative SNR, which is possible, but realisticly the
demod will lose lock before the signal gets this bad. The
API only allows for unsigned values, so just return 0 */
return 0;
}
return 10*(c - mse);
}
static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lgdt3305_state *state = fe->demodulator_priv;
u32 noise; /* noise value */
u32 c; /* per-modulation SNR calculation constant */
switch (state->current_modulation) {
case VSB_8:
#ifdef USE_PTMSE
/* Use Phase Tracker Mean-Square Error Register */
/* SNR for ranges from -13.11 to +44.08 */
noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
(read_reg(state, LGDT3305_PT_MSE_2) << 8) |
(read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
c = 73957994; /* log10(25*32^2)*2^24 */
#else
/* Use Equalizer Mean-Square Error Register */
/* SNR for ranges from -16.12 to +44.08 */
noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
(read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
(read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
c = 73957994; /* log10(25*32^2)*2^24 */
#endif
break;
case QAM_64:
case QAM_256:
noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
(read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
c = (state->current_modulation == QAM_64) ?
97939837 : 98026066;
/* log10(688128)*2^24 and log10(696320)*2^24 */
break;
default:
return -EINVAL;
}
state->snr = calculate_snr(noise, c);
/* report SNR in dB * 10 */
*snr = (state->snr / ((1 << 24) / 10));
lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
return 0;
}
static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
/* borrowed from lgdt330x.c
*
* Calculate strength from SNR up to 35dB
* Even though the SNR can go higher than 35dB,
* there is some comfort factor in having a range of
* strong signals that can show at 100%
*/
struct lgdt3305_state *state = fe->demodulator_priv;
u16 snr;
int ret;
*strength = 0;
ret = fe->ops.read_snr(fe, &snr);
if (lg_fail(ret))
goto fail;
/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
/* scale the range 0 - 35*2^24 into 0 - 65535 */
if (state->snr >= 8960 * 0x10000)
*strength = 0xffff;
else
*strength = state->snr / 8960;
fail:
return ret;
}
/* ------------------------------------------------------------------------ */
static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
{
*ber = 0;
return 0;
}
static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct lgdt3305_state *state = fe->demodulator_priv;
*ucblocks =
(read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
(read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
return 0;
}
static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings
*fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 500;
lg_dbg("\n");
return 0;
}
static void lgdt3305_release(struct dvb_frontend *fe)
{
struct lgdt3305_state *state = fe->demodulator_priv;
lg_dbg("\n");
kfree(state);
}
static const struct dvb_frontend_ops lgdt3304_ops;
static const struct dvb_frontend_ops lgdt3305_ops;
struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
struct i2c_adapter *i2c_adap)
{
struct lgdt3305_state *state = NULL;
int ret;
u8 val;
lg_dbg("(%d-%04x)\n",
i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
config ? config->i2c_addr : 0);
state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
if (state == NULL)
goto fail;
state->cfg = config;
state->i2c_adap = i2c_adap;
switch (config->demod_chip) {
case LGDT3304:
memcpy(&state->frontend.ops, &lgdt3304_ops,
sizeof(struct dvb_frontend_ops));
break;
case LGDT3305:
memcpy(&state->frontend.ops, &lgdt3305_ops,
sizeof(struct dvb_frontend_ops));
break;
default:
goto fail;
}
state->frontend.demodulator_priv = state;
/* verify that we're talking to a lg dt3304/5 */
ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
if ((lg_fail(ret)) | (val == 0))
goto fail;
ret = lgdt3305_write_reg(state, 0x0808, 0x80);
if (lg_fail(ret))
goto fail;
ret = lgdt3305_read_reg(state, 0x0808, &val);
if ((lg_fail(ret)) | (val != 0x80))
goto fail;
ret = lgdt3305_write_reg(state, 0x0808, 0x00);
if (lg_fail(ret))
goto fail;
state->current_frequency = -1;
state->current_modulation = -1;
return &state->frontend;
fail:
lg_warn("unable to detect %s hardware\n",
config->demod_chip ? "LGDT3304" : "LGDT3305");
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(lgdt3305_attach);
static const struct dvb_frontend_ops lgdt3304_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "LG Electronics LGDT3304 VSB/QAM Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
.init = lgdt3305_init,
.sleep = lgdt3305_sleep,
.set_frontend = lgdt3304_set_parameters,
.get_frontend = lgdt3305_get_frontend,
.get_tune_settings = lgdt3305_get_tune_settings,
.read_status = lgdt3305_read_status,
.read_ber = lgdt3305_read_ber,
.read_signal_strength = lgdt3305_read_signal_strength,
.read_snr = lgdt3305_read_snr,
.read_ucblocks = lgdt3305_read_ucblocks,
.release = lgdt3305_release,
};
static const struct dvb_frontend_ops lgdt3305_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "LG Electronics LGDT3305 VSB/QAM Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
.init = lgdt3305_init,
.sleep = lgdt3305_sleep,
.set_frontend = lgdt3305_set_parameters,
.get_frontend = lgdt3305_get_frontend,
.get_tune_settings = lgdt3305_get_tune_settings,
.read_status = lgdt3305_read_status,
.read_ber = lgdt3305_read_ber,
.read_signal_strength = lgdt3305_read_signal_strength,
.read_snr = lgdt3305_read_snr,
.read_ucblocks = lgdt3305_read_ucblocks,
.release = lgdt3305_release,
};
MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
MODULE_AUTHOR("Michael Krufky <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.2");
| linux-master | drivers/media/dvb-frontends/lgdt3305.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Abilis Systems Single DVB-T Receiver
* Copyright (C) 2008 Pierrick Hascoet <[email protected]>
* Copyright (C) 2010 Devin Heitmueller <[email protected]>
*/
#include <media/dvb_frontend.h>
#include "as102_fe.h"
struct as102_state {
struct dvb_frontend frontend;
struct as10x_demod_stats demod_stats;
const struct as102_fe_ops *ops;
void *priv;
uint8_t elna_cfg;
/* signal strength */
uint16_t signal_strength;
/* bit error rate */
uint32_t ber;
};
static uint8_t as102_fe_get_code_rate(enum fe_code_rate arg)
{
uint8_t c;
switch (arg) {
case FEC_1_2:
c = CODE_RATE_1_2;
break;
case FEC_2_3:
c = CODE_RATE_2_3;
break;
case FEC_3_4:
c = CODE_RATE_3_4;
break;
case FEC_5_6:
c = CODE_RATE_5_6;
break;
case FEC_7_8:
c = CODE_RATE_7_8;
break;
default:
c = CODE_RATE_UNKNOWN;
break;
}
return c;
}
static int as102_fe_set_frontend(struct dvb_frontend *fe)
{
struct as102_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct as10x_tune_args tune_args = { 0 };
/* set frequency */
tune_args.freq = c->frequency / 1000;
/* fix interleaving_mode */
tune_args.interleaving_mode = INTLV_NATIVE;
switch (c->bandwidth_hz) {
case 8000000:
tune_args.bandwidth = BW_8_MHZ;
break;
case 7000000:
tune_args.bandwidth = BW_7_MHZ;
break;
case 6000000:
tune_args.bandwidth = BW_6_MHZ;
break;
default:
tune_args.bandwidth = BW_8_MHZ;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_1_32:
tune_args.guard_interval = GUARD_INT_1_32;
break;
case GUARD_INTERVAL_1_16:
tune_args.guard_interval = GUARD_INT_1_16;
break;
case GUARD_INTERVAL_1_8:
tune_args.guard_interval = GUARD_INT_1_8;
break;
case GUARD_INTERVAL_1_4:
tune_args.guard_interval = GUARD_INT_1_4;
break;
case GUARD_INTERVAL_AUTO:
default:
tune_args.guard_interval = GUARD_UNKNOWN;
break;
}
switch (c->modulation) {
case QPSK:
tune_args.modulation = CONST_QPSK;
break;
case QAM_16:
tune_args.modulation = CONST_QAM16;
break;
case QAM_64:
tune_args.modulation = CONST_QAM64;
break;
default:
tune_args.modulation = CONST_UNKNOWN;
break;
}
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
tune_args.transmission_mode = TRANS_MODE_2K;
break;
case TRANSMISSION_MODE_8K:
tune_args.transmission_mode = TRANS_MODE_8K;
break;
default:
tune_args.transmission_mode = TRANS_MODE_UNKNOWN;
}
switch (c->hierarchy) {
case HIERARCHY_NONE:
tune_args.hierarchy = HIER_NONE;
break;
case HIERARCHY_1:
tune_args.hierarchy = HIER_ALPHA_1;
break;
case HIERARCHY_2:
tune_args.hierarchy = HIER_ALPHA_2;
break;
case HIERARCHY_4:
tune_args.hierarchy = HIER_ALPHA_4;
break;
case HIERARCHY_AUTO:
tune_args.hierarchy = HIER_UNKNOWN;
break;
}
pr_debug("as102: tuner parameters: freq: %d bw: 0x%02x gi: 0x%02x\n",
c->frequency,
tune_args.bandwidth,
tune_args.guard_interval);
/*
* Detect a hierarchy selection
* if HP/LP are both set to FEC_NONE, HP will be selected.
*/
if ((tune_args.hierarchy != HIER_NONE) &&
((c->code_rate_LP == FEC_NONE) ||
(c->code_rate_HP == FEC_NONE))) {
if (c->code_rate_LP == FEC_NONE) {
tune_args.hier_select = HIER_HIGH_PRIORITY;
tune_args.code_rate =
as102_fe_get_code_rate(c->code_rate_HP);
}
if (c->code_rate_HP == FEC_NONE) {
tune_args.hier_select = HIER_LOW_PRIORITY;
tune_args.code_rate =
as102_fe_get_code_rate(c->code_rate_LP);
}
pr_debug("as102: \thierarchy: 0x%02x selected: %s code_rate_%s: 0x%02x\n",
tune_args.hierarchy,
tune_args.hier_select == HIER_HIGH_PRIORITY ?
"HP" : "LP",
tune_args.hier_select == HIER_HIGH_PRIORITY ?
"HP" : "LP",
tune_args.code_rate);
} else {
tune_args.code_rate =
as102_fe_get_code_rate(c->code_rate_HP);
}
/* Set frontend arguments */
return state->ops->set_tune(state->priv, &tune_args);
}
static int as102_fe_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct as102_state *state = fe->demodulator_priv;
int ret = 0;
struct as10x_tps tps = { 0 };
/* send abilis command: GET_TPS */
ret = state->ops->get_tps(state->priv, &tps);
if (ret < 0)
return ret;
/* extract constellation */
switch (tps.modulation) {
case CONST_QPSK:
c->modulation = QPSK;
break;
case CONST_QAM16:
c->modulation = QAM_16;
break;
case CONST_QAM64:
c->modulation = QAM_64;
break;
}
/* extract hierarchy */
switch (tps.hierarchy) {
case HIER_NONE:
c->hierarchy = HIERARCHY_NONE;
break;
case HIER_ALPHA_1:
c->hierarchy = HIERARCHY_1;
break;
case HIER_ALPHA_2:
c->hierarchy = HIERARCHY_2;
break;
case HIER_ALPHA_4:
c->hierarchy = HIERARCHY_4;
break;
}
/* extract code rate HP */
switch (tps.code_rate_HP) {
case CODE_RATE_1_2:
c->code_rate_HP = FEC_1_2;
break;
case CODE_RATE_2_3:
c->code_rate_HP = FEC_2_3;
break;
case CODE_RATE_3_4:
c->code_rate_HP = FEC_3_4;
break;
case CODE_RATE_5_6:
c->code_rate_HP = FEC_5_6;
break;
case CODE_RATE_7_8:
c->code_rate_HP = FEC_7_8;
break;
}
/* extract code rate LP */
switch (tps.code_rate_LP) {
case CODE_RATE_1_2:
c->code_rate_LP = FEC_1_2;
break;
case CODE_RATE_2_3:
c->code_rate_LP = FEC_2_3;
break;
case CODE_RATE_3_4:
c->code_rate_LP = FEC_3_4;
break;
case CODE_RATE_5_6:
c->code_rate_LP = FEC_5_6;
break;
case CODE_RATE_7_8:
c->code_rate_LP = FEC_7_8;
break;
}
/* extract guard interval */
switch (tps.guard_interval) {
case GUARD_INT_1_32:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case GUARD_INT_1_16:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case GUARD_INT_1_8:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case GUARD_INT_1_4:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
/* extract transmission mode */
switch (tps.transmission_mode) {
case TRANS_MODE_2K:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case TRANS_MODE_8K:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
return 0;
}
static int as102_fe_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *settings)
{
settings->min_delay_ms = 1000;
return 0;
}
static int as102_fe_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
int ret = 0;
struct as102_state *state = fe->demodulator_priv;
struct as10x_tune_status tstate = { 0 };
/* send abilis command: GET_TUNE_STATUS */
ret = state->ops->get_status(state->priv, &tstate);
if (ret < 0)
return ret;
state->signal_strength = tstate.signal_strength;
state->ber = tstate.BER;
switch (tstate.tune_state) {
case TUNE_STATUS_SIGNAL_DVB_OK:
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
break;
case TUNE_STATUS_STREAM_DETECTED:
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_SYNC |
FE_HAS_VITERBI;
break;
case TUNE_STATUS_STREAM_TUNED:
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_SYNC |
FE_HAS_LOCK | FE_HAS_VITERBI;
break;
default:
*status = TUNE_STATUS_NOT_TUNED;
}
pr_debug("as102: tuner status: 0x%02x, strength %d, per: %d, ber: %d\n",
tstate.tune_state, tstate.signal_strength,
tstate.PER, tstate.BER);
if (!(*status & FE_HAS_LOCK)) {
memset(&state->demod_stats, 0, sizeof(state->demod_stats));
return 0;
}
ret = state->ops->get_stats(state->priv, &state->demod_stats);
if (ret < 0)
memset(&state->demod_stats, 0, sizeof(state->demod_stats));
return ret;
}
/*
* Note:
* - in AS102 SNR=MER
* - the SNR will be returned in linear terms, i.e. not in dB
* - the accuracy equals ±2dB for a SNR range from 4dB to 30dB
* - the accuracy is >2dB for SNR values outside this range
*/
static int as102_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct as102_state *state = fe->demodulator_priv;
*snr = state->demod_stats.mer;
return 0;
}
static int as102_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct as102_state *state = fe->demodulator_priv;
*ber = state->ber;
return 0;
}
static int as102_fe_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
struct as102_state *state = fe->demodulator_priv;
*strength = (((0xffff * 400) * state->signal_strength + 41000) * 2);
return 0;
}
static int as102_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct as102_state *state = fe->demodulator_priv;
if (state->demod_stats.has_started)
*ucblocks = state->demod_stats.bad_frame_count;
else
*ucblocks = 0;
return 0;
}
static int as102_fe_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
{
struct as102_state *state = fe->demodulator_priv;
return state->ops->stream_ctrl(state->priv, acquire,
state->elna_cfg);
}
static void as102_fe_release(struct dvb_frontend *fe)
{
struct as102_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops as102_fe_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Abilis AS102 DVB-T",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_INVERSION_AUTO
| FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO
| FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QPSK
| FE_CAN_QAM_AUTO
| FE_CAN_TRANSMISSION_MODE_AUTO
| FE_CAN_GUARD_INTERVAL_AUTO
| FE_CAN_HIERARCHY_AUTO
| FE_CAN_RECOVER
| FE_CAN_MUTE_TS
},
.set_frontend = as102_fe_set_frontend,
.get_frontend = as102_fe_get_frontend,
.get_tune_settings = as102_fe_get_tune_settings,
.read_status = as102_fe_read_status,
.read_snr = as102_fe_read_snr,
.read_ber = as102_fe_read_ber,
.read_signal_strength = as102_fe_read_signal_strength,
.read_ucblocks = as102_fe_read_ucblocks,
.ts_bus_ctrl = as102_fe_ts_bus_ctrl,
.release = as102_fe_release,
};
struct dvb_frontend *as102_attach(const char *name,
const struct as102_fe_ops *ops,
void *priv,
uint8_t elna_cfg)
{
struct as102_state *state;
struct dvb_frontend *fe;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
fe = &state->frontend;
fe->demodulator_priv = state;
state->ops = ops;
state->priv = priv;
state->elna_cfg = elna_cfg;
/* init frontend callback ops */
memcpy(&fe->ops, &as102_fe_ops, sizeof(struct dvb_frontend_ops));
strscpy(fe->ops.info.name, name, sizeof(fe->ops.info.name));
return fe;
}
EXPORT_SYMBOL_GPL(as102_attach);
MODULE_DESCRIPTION("as102-fe");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Pierrick Hascoet <[email protected]>");
| linux-master | drivers/media/dvb-frontends/as102_fe.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
* ATBM8830, ATBM8831
*
* Copyright (C) 2009 David T.L. Wong <[email protected]>
*/
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "atbm8830.h"
#include "atbm8830_priv.h"
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "atbm8830: " args); \
} while (0)
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
{
int ret = 0;
u8 dev_addr;
u8 buf1[] = { reg >> 8, reg & 0xFF };
u8 buf2[] = { data };
struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
dev_addr = priv->config->demod_address;
msg1.addr = dev_addr;
msg2.addr = dev_addr;
if (debug >= 2)
dprintk("%s: reg=0x%04X, data=0x%02X\n", __func__, reg, data);
ret = i2c_transfer(priv->i2c, &msg1, 1);
if (ret != 1)
return -EIO;
ret = i2c_transfer(priv->i2c, &msg2, 1);
return (ret != 1) ? -EIO : 0;
}
static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
{
int ret;
u8 dev_addr;
u8 buf1[] = { reg >> 8, reg & 0xFF };
u8 buf2[] = { 0 };
struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
dev_addr = priv->config->demod_address;
msg1.addr = dev_addr;
msg2.addr = dev_addr;
ret = i2c_transfer(priv->i2c, &msg1, 1);
if (ret != 1) {
dprintk("%s: error reg=0x%04x, ret=%i\n", __func__, reg, ret);
return -EIO;
}
ret = i2c_transfer(priv->i2c, &msg2, 1);
if (ret != 1)
return -EIO;
*p_data = buf2[0];
if (debug >= 2)
dprintk("%s: reg=0x%04X, data=0x%02X\n",
__func__, reg, buf2[0]);
return 0;
}
/* Lock register latch so that multi-register read is atomic */
static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
{
return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
}
static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
{
u32 val;
u64 t;
/* 0x100000 * freq / 30.4MHz */
t = (u64)0x100000 * freq;
do_div(t, 30400);
val = t;
atbm8830_write_reg(priv, REG_OSC_CLK, val);
atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
return 0;
}
static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
{
u32 fs = priv->config->osc_clk_freq;
u64 t;
u32 val;
u8 dat;
if (freq != 0) {
/* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
t = (u64) 2 * 31416 * (freq - fs);
t <<= 22;
do_div(t, fs);
do_div(t, 1000);
val = t;
atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
atbm8830_write_reg(priv, REG_IF_FREQ, val);
atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
dat &= 0xFC;
atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
} else {
/* Zero IF */
atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
dat &= 0xFC;
dat |= 0x02;
atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
if (priv->config->zif_swap_iq)
atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
else
atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
}
return 0;
}
static int is_locked(struct atbm_state *priv, u8 *locked)
{
u8 status;
atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
if (locked != NULL)
*locked = (status == 1);
return 0;
}
static int set_agc_config(struct atbm_state *priv,
u8 min, u8 max, u8 hold_loop)
{
/* no effect if both min and max are zero */
if (!min && !max)
return 0;
atbm8830_write_reg(priv, REG_AGC_MIN, min);
atbm8830_write_reg(priv, REG_AGC_MAX, max);
atbm8830_write_reg(priv, REG_AGC_HOLD_LOOP, hold_loop);
return 0;
}
static int set_static_channel_mode(struct atbm_state *priv)
{
int i;
for (i = 0; i < 5; i++)
atbm8830_write_reg(priv, 0x099B + i, 0x08);
atbm8830_write_reg(priv, 0x095B, 0x7F);
atbm8830_write_reg(priv, 0x09CB, 0x01);
atbm8830_write_reg(priv, 0x09CC, 0x7F);
atbm8830_write_reg(priv, 0x09CD, 0x7F);
atbm8830_write_reg(priv, 0x0E01, 0x20);
/* For single carrier */
atbm8830_write_reg(priv, 0x0B03, 0x0A);
atbm8830_write_reg(priv, 0x0935, 0x10);
atbm8830_write_reg(priv, 0x0936, 0x08);
atbm8830_write_reg(priv, 0x093E, 0x08);
atbm8830_write_reg(priv, 0x096E, 0x06);
/* frame_count_max0 */
atbm8830_write_reg(priv, 0x0B09, 0x00);
/* frame_count_max1 */
atbm8830_write_reg(priv, 0x0B0A, 0x08);
return 0;
}
static int set_ts_config(struct atbm_state *priv)
{
const struct atbm8830_config *cfg = priv->config;
/*Set parallel/serial ts mode*/
atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
/*Set ts sampling edge*/
atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
cfg->ts_sampling_edge ? 1 : 0);
/*Set ts clock freerun*/
atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
cfg->ts_clk_gated ? 0 : 1);
return 0;
}
static int atbm8830_init(struct dvb_frontend *fe)
{
struct atbm_state *priv = fe->demodulator_priv;
const struct atbm8830_config *cfg = priv->config;
/*Set oscillator frequency*/
set_osc_freq(priv, cfg->osc_clk_freq);
/*Set IF frequency*/
set_if_freq(priv, cfg->if_freq);
/*Set AGC Config*/
set_agc_config(priv, cfg->agc_min, cfg->agc_max,
cfg->agc_hold_loop);
/*Set static channel mode*/
set_static_channel_mode(priv);
set_ts_config(priv);
/*Turn off DSP reset*/
atbm8830_write_reg(priv, 0x000A, 0);
/*SW version test*/
atbm8830_write_reg(priv, 0x020C, 11);
/* Run */
atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
return 0;
}
static void atbm8830_release(struct dvb_frontend *fe)
{
struct atbm_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
kfree(state);
}
static int atbm8830_set_fe(struct dvb_frontend *fe)
{
struct atbm_state *priv = fe->demodulator_priv;
int i;
u8 locked = 0;
dprintk("%s\n", __func__);
/* set frequency */
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* start auto lock */
for (i = 0; i < 10; i++) {
mdelay(100);
dprintk("Try %d\n", i);
is_locked(priv, &locked);
if (locked != 0) {
dprintk("ATBM8830 locked!\n");
break;
}
}
return 0;
}
static int atbm8830_get_fe(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
dprintk("%s\n", __func__);
/* TODO: get real readings from device */
/* inversion status */
c->inversion = INVERSION_OFF;
/* bandwidth */
c->bandwidth_hz = 8000000;
c->code_rate_HP = FEC_AUTO;
c->code_rate_LP = FEC_AUTO;
c->modulation = QAM_AUTO;
/* transmission mode */
c->transmission_mode = TRANSMISSION_MODE_AUTO;
/* guard interval */
c->guard_interval = GUARD_INTERVAL_AUTO;
/* hierarchy */
c->hierarchy = HIERARCHY_NONE;
return 0;
}
static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 0;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int atbm8830_read_status(struct dvb_frontend *fe,
enum fe_status *fe_status)
{
struct atbm_state *priv = fe->demodulator_priv;
u8 locked = 0;
u8 agc_locked = 0;
dprintk("%s\n", __func__);
*fe_status = 0;
is_locked(priv, &locked);
if (locked) {
*fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
}
dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
dprintk("AGC Lock: %d\n", agc_locked);
return 0;
}
static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct atbm_state *priv = fe->demodulator_priv;
u32 frame_err;
u8 t;
dprintk("%s\n", __func__);
atbm8830_reglatch_lock(priv, 1);
atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
frame_err = t & 0x7F;
frame_err <<= 8;
atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
frame_err |= t;
atbm8830_reglatch_lock(priv, 0);
*ber = frame_err * 100 / 32767;
dprintk("%s: ber=0x%x\n", __func__, *ber);
return 0;
}
static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
{
struct atbm_state *priv = fe->demodulator_priv;
u32 pwm;
u8 t;
dprintk("%s\n", __func__);
atbm8830_reglatch_lock(priv, 1);
atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
pwm = t & 0x03;
pwm <<= 8;
atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
pwm |= t;
atbm8830_reglatch_lock(priv, 0);
dprintk("AGC PWM = 0x%02X\n", pwm);
pwm = 0x400 - pwm;
*signal = pwm * 0x10000 / 0x400;
return 0;
}
static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
{
dprintk("%s\n", __func__);
*snr = 0;
return 0;
}
static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
dprintk("%s\n", __func__);
*ucblocks = 0;
return 0;
}
static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct atbm_state *priv = fe->demodulator_priv;
return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
}
static const struct dvb_frontend_ops atbm8830_ops = {
.delsys = { SYS_DTMB },
.info = {
.name = "AltoBeam ATBM8830/8831 DMB-TH",
.frequency_min_hz = 474 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 10 * kHz,
.caps =
FE_CAN_FEC_AUTO |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO
},
.release = atbm8830_release,
.init = atbm8830_init,
.sleep = NULL,
.write = NULL,
.i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
.set_frontend = atbm8830_set_fe,
.get_frontend = atbm8830_get_fe,
.get_tune_settings = atbm8830_get_tune_settings,
.read_status = atbm8830_read_status,
.read_ber = atbm8830_read_ber,
.read_signal_strength = atbm8830_read_signal_strength,
.read_snr = atbm8830_read_snr,
.read_ucblocks = atbm8830_read_ucblocks,
};
struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
struct i2c_adapter *i2c)
{
struct atbm_state *priv = NULL;
u8 data = 0;
dprintk("%s()\n", __func__);
if (config == NULL || i2c == NULL)
return NULL;
priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
if (priv == NULL)
goto error_out;
priv->config = config;
priv->i2c = i2c;
/* check if the demod is there */
if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
__func__, priv->config->demod_address);
goto error_out;
}
dprintk("atbm8830 chip id: 0x%02X\n", data);
memcpy(&priv->frontend.ops, &atbm8830_ops,
sizeof(struct dvb_frontend_ops));
priv->frontend.demodulator_priv = priv;
atbm8830_init(&priv->frontend);
atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
return &priv->frontend;
error_out:
dprintk("%s() error_out\n", __func__);
kfree(priv);
return NULL;
}
EXPORT_SYMBOL_GPL(atbm8830_attach);
MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
MODULE_AUTHOR("David T. L. Wong <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/atbm8830.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
*
* Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
*
* This code is more or less generated from another driver, please
* excuse some codingstyle oddities.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <media/dvb_frontend.h>
#include "dib0090.h"
#include "dibx000_common.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
#define CONFIG_SYS_DVBT
#define CONFIG_SYS_ISDBT
#define CONFIG_BAND_CBAND
#define CONFIG_BAND_VHF
#define CONFIG_BAND_UHF
#define CONFIG_DIB0090_USE_PWM_AGC
#define EN_LNA0 0x8000
#define EN_LNA1 0x4000
#define EN_LNA2 0x2000
#define EN_LNA3 0x1000
#define EN_MIX0 0x0800
#define EN_MIX1 0x0400
#define EN_MIX2 0x0200
#define EN_MIX3 0x0100
#define EN_IQADC 0x0040
#define EN_PLL 0x0020
#define EN_TX 0x0010
#define EN_BB 0x0008
#define EN_LO 0x0004
#define EN_BIAS 0x0001
#define EN_IQANA 0x0002
#define EN_DIGCLK 0x0080 /* not in the 0x24 reg, only in 0x1b */
#define EN_CRYSTAL 0x0002
#define EN_UHF 0x22E9
#define EN_VHF 0x44E9
#define EN_LBD 0x11E9
#define EN_SBD 0x44E9
#define EN_CAB 0x88E9
/* Calibration defines */
#define DC_CAL 0x1
#define WBD_CAL 0x2
#define TEMP_CAL 0x4
#define CAPTRIM_CAL 0x8
#define KROSUS_PLL_LOCKED 0x800
#define KROSUS 0x2
/* Use those defines to identify SOC version */
#define SOC 0x02
#define SOC_7090_P1G_11R1 0x82
#define SOC_7090_P1G_21R1 0x8a
#define SOC_8090_P1G_11R1 0x86
#define SOC_8090_P1G_21R1 0x8e
/* else use thos ones to check */
#define P1A_B 0x0
#define P1C 0x1
#define P1D_E_F 0x3
#define P1G 0x7
#define P1G_21R2 0xf
#define MP001 0x1 /* Single 9090/8096 */
#define MP005 0x4 /* Single Sband */
#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
#define pgm_read_word(w) (*w)
struct dc_calibration;
struct dib0090_tuning {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 switch_trim;
u8 lna_tune;
u16 lna_bias;
u16 v2i;
u16 mix;
u16 load;
u16 tuner_enable;
};
struct dib0090_pll {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 vco_band;
u8 hfdiv_code;
u8 hfdiv;
u8 topresc;
};
struct dib0090_identity {
u8 version;
u8 product;
u8 p1g;
u8 in_soc;
};
struct dib0090_state {
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
const struct dib0090_config *config;
u8 current_band;
enum frontend_tune_state tune_state;
u32 current_rf;
u16 wbd_offset;
s16 wbd_target; /* in dB */
s16 rf_gain_limit; /* take-over-point: where to split between bb and rf gain */
s16 current_gain; /* keeps the currently programmed gain */
u8 agc_step; /* new binary search */
u16 gain[2]; /* for channel monitoring */
const u16 *rf_ramp;
const u16 *bb_ramp;
/* for the software AGC ramps */
u16 bb_1_def;
u16 rf_lt_def;
u16 gain_reg[4];
/* for the captrim/dc-offset search */
s8 step;
s16 adc_diff;
s16 min_adc_diff;
s8 captrim;
s8 fcaptrim;
const struct dc_calibration *dc;
u16 bb6, bb7;
const struct dib0090_tuning *current_tune_table_index;
const struct dib0090_pll *current_pll_table_index;
u8 tuner_is_tuned;
u8 agc_freeze;
struct dib0090_identity identity;
u32 rf_request;
u8 current_standard;
u8 calibrate;
u32 rest;
u16 bias;
s16 temperature;
u8 wbd_calibration_gain;
const struct dib0090_wbd_slope *current_wbd_table;
u16 wbdmux;
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[3];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
};
struct dib0090_fw_state {
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
struct dib0090_identity identity;
const struct dib0090_config *config;
/* for the I2C transfer */
struct i2c_msg msg;
u8 i2c_write_buffer[2];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
};
static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
state->i2c_write_buffer[0] = reg;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->config->i2c_address;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 1;
state->msg[1].addr = state->config->i2c_address;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
pr_warn("DiB0090 I2C read failed\n");
ret = 0;
} else
ret = (state->i2c_read_buffer[0] << 8)
| state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = reg & 0xff;
state->i2c_write_buffer[1] = val >> 8;
state->i2c_write_buffer[2] = val & 0xff;
memset(state->msg, 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->config->i2c_address;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 3;
if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
pr_warn("DiB0090 I2C write failed\n");
ret = -EREMOTEIO;
} else
ret = 0;
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
state->i2c_write_buffer[0] = reg;
memset(&state->msg, 0, sizeof(struct i2c_msg));
state->msg.addr = reg;
state->msg.flags = I2C_M_RD;
state->msg.buf = state->i2c_read_buffer;
state->msg.len = 2;
if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
pr_warn("DiB0090 I2C read failed\n");
ret = 0;
} else
ret = (state->i2c_read_buffer[0] << 8)
| state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = val >> 8;
state->i2c_write_buffer[1] = val & 0xff;
memset(&state->msg, 0, sizeof(struct i2c_msg));
state->msg.addr = reg;
state->msg.flags = 0;
state->msg.buf = state->i2c_write_buffer;
state->msg.len = 2;
if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
pr_warn("DiB0090 I2C write failed\n");
ret = -EREMOTEIO;
} else
ret = 0;
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
#define ADC_TARGET -220
#define GAIN_ALPHA 5
#define WBD_ALPHA 6
#define LPF 100
static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)
{
do {
dib0090_write_reg(state, r++, *b++);
} while (--c);
}
static int dib0090_identify(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
u16 v;
struct dib0090_identity *identity = &state->identity;
v = dib0090_read_reg(state, 0x1a);
identity->p1g = 0;
identity->in_soc = 0;
dprintk("Tuner identification (Version = 0x%04x)\n", v);
/* without PLL lock info */
v &= ~KROSUS_PLL_LOCKED;
identity->version = v & 0xff;
identity->product = (v >> 8) & 0xf;
if (identity->product != KROSUS)
goto identification_error;
if ((identity->version & 0x3) == SOC) {
identity->in_soc = 1;
switch (identity->version) {
case SOC_8090_P1G_11R1:
dprintk("SOC 8090 P1-G11R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_8090_P1G_21R1:
dprintk("SOC 8090 P1-G21R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_7090_P1G_11R1:
dprintk("SOC 7090 P1-G11R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_7090_P1G_21R1:
dprintk("SOC 7090 P1-G21R1 Has been detected\n");
identity->p1g = 1;
break;
default:
goto identification_error;
}
} else {
switch ((identity->version >> 5) & 0x7) {
case MP001:
dprintk("MP001 : 9090/8096\n");
break;
case MP005:
dprintk("MP005 : Single Sband\n");
break;
case MP008:
dprintk("MP008 : diversity VHF-UHF-LBAND\n");
break;
case MP009:
dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND\n");
break;
default:
goto identification_error;
}
switch (identity->version & 0x1f) {
case P1G_21R2:
dprintk("P1G_21R2 detected\n");
identity->p1g = 1;
break;
case P1G:
dprintk("P1G detected\n");
identity->p1g = 1;
break;
case P1D_E_F:
dprintk("P1D/E/F detected\n");
break;
case P1C:
dprintk("P1C detected\n");
break;
case P1A_B:
dprintk("P1-A/B detected: driver is deactivated - not available\n");
goto identification_error;
break;
default:
goto identification_error;
}
}
return 0;
identification_error:
return -EIO;
}
static int dib0090_fw_identify(struct dvb_frontend *fe)
{
struct dib0090_fw_state *state = fe->tuner_priv;
struct dib0090_identity *identity = &state->identity;
u16 v = dib0090_fw_read_reg(state, 0x1a);
identity->p1g = 0;
identity->in_soc = 0;
dprintk("FE: Tuner identification (Version = 0x%04x)\n", v);
/* without PLL lock info */
v &= ~KROSUS_PLL_LOCKED;
identity->version = v & 0xff;
identity->product = (v >> 8) & 0xf;
if (identity->product != KROSUS)
goto identification_error;
if ((identity->version & 0x3) == SOC) {
identity->in_soc = 1;
switch (identity->version) {
case SOC_8090_P1G_11R1:
dprintk("SOC 8090 P1-G11R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_8090_P1G_21R1:
dprintk("SOC 8090 P1-G21R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_7090_P1G_11R1:
dprintk("SOC 7090 P1-G11R1 Has been detected\n");
identity->p1g = 1;
break;
case SOC_7090_P1G_21R1:
dprintk("SOC 7090 P1-G21R1 Has been detected\n");
identity->p1g = 1;
break;
default:
goto identification_error;
}
} else {
switch ((identity->version >> 5) & 0x7) {
case MP001:
dprintk("MP001 : 9090/8096\n");
break;
case MP005:
dprintk("MP005 : Single Sband\n");
break;
case MP008:
dprintk("MP008 : diversity VHF-UHF-LBAND\n");
break;
case MP009:
dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND\n");
break;
default:
goto identification_error;
}
switch (identity->version & 0x1f) {
case P1G_21R2:
dprintk("P1G_21R2 detected\n");
identity->p1g = 1;
break;
case P1G:
dprintk("P1G detected\n");
identity->p1g = 1;
break;
case P1D_E_F:
dprintk("P1D/E/F detected\n");
break;
case P1C:
dprintk("P1C detected\n");
break;
case P1A_B:
dprintk("P1-A/B detected: driver is deactivated - not available\n");
goto identification_error;
break;
default:
goto identification_error;
}
}
return 0;
identification_error:
return -EIO;
}
static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
{
struct dib0090_state *state = fe->tuner_priv;
u16 PllCfg, i, v;
HARD_RESET(state);
dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
if (cfg->in_soc)
return;
dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
/* adcClkOutRatio=8->7, release reset */
dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
if (cfg->clkoutdrive != 0)
dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
| (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
else
dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
| (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
/* Read Pll current config * */
PllCfg = dib0090_read_reg(state, 0x21);
/** Reconfigure PLL if current setting is different from default setting **/
if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
&& !cfg->io.pll_bypass) {
/* Set Bypass mode */
PllCfg |= (1 << 15);
dib0090_write_reg(state, 0x21, PllCfg);
/* Set Reset Pll */
PllCfg &= ~(1 << 13);
dib0090_write_reg(state, 0x21, PllCfg);
/*** Set new Pll configuration in bypass and reset state ***/
PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
dib0090_write_reg(state, 0x21, PllCfg);
/* Remove Reset Pll */
PllCfg |= (1 << 13);
dib0090_write_reg(state, 0x21, PllCfg);
/*** Wait for PLL lock ***/
i = 100;
do {
v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
if (v)
break;
} while (--i);
if (i == 0) {
dprintk("Pll: Unable to lock Pll\n");
return;
}
/* Finally Remove Bypass mode */
PllCfg &= ~(1 << 15);
dib0090_write_reg(state, 0x21, PllCfg);
}
if (cfg->io.pll_bypass) {
PllCfg |= (cfg->io.pll_bypass << 15);
dib0090_write_reg(state, 0x21, PllCfg);
}
}
static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
{
struct dib0090_fw_state *state = fe->tuner_priv;
u16 PllCfg;
u16 v;
int i;
dprintk("fw reset digital\n");
HARD_RESET(state);
dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
dib0090_fw_write_reg(state, 0x20,
((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
if (cfg->clkoutdrive != 0)
v |= cfg->clkoutdrive << 5;
else
v |= 7 << 5;
v |= 2 << 10;
dib0090_fw_write_reg(state, 0x23, v);
/* Read Pll current config * */
PllCfg = dib0090_fw_read_reg(state, 0x21);
/** Reconfigure PLL if current setting is different from default setting **/
if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
/* Set Bypass mode */
PllCfg |= (1 << 15);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/* Set Reset Pll */
PllCfg &= ~(1 << 13);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/*** Set new Pll configuration in bypass and reset state ***/
PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/* Remove Reset Pll */
PllCfg |= (1 << 13);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/*** Wait for PLL lock ***/
i = 100;
do {
v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
if (v)
break;
} while (--i);
if (i == 0) {
dprintk("Pll: Unable to lock Pll\n");
return -EIO;
}
/* Finally Remove Bypass mode */
PllCfg &= ~(1 << 15);
dib0090_fw_write_reg(state, 0x21, PllCfg);
}
if (cfg->io.pll_bypass) {
PllCfg |= (cfg->io.pll_bypass << 15);
dib0090_fw_write_reg(state, 0x21, PllCfg);
}
return dib0090_fw_identify(fe);
}
static int dib0090_wakeup(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
if (state->config->sleep)
state->config->sleep(fe, 0);
/* enable dataTX in case we have been restarted in the wrong moment */
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
return 0;
}
static int dib0090_sleep(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
if (state->config->sleep)
state->config->sleep(fe, 1);
return 0;
}
void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
{
struct dib0090_state *state = fe->tuner_priv;
if (fast)
dib0090_write_reg(state, 0x04, 0);
else
dib0090_write_reg(state, 0x04, 1);
}
EXPORT_SYMBOL(dib0090_dcc_freq);
static const u16 bb_ramp_pwm_normal_socs[] = {
550, /* max BB gain in 10th of dB */
(1<<9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
440,
(4 << 9) | 0, /* BB_RAMP3 = 26dB */
(0 << 9) | 208, /* BB_RAMP4 */
(4 << 9) | 208, /* BB_RAMP5 = 29dB */
(0 << 9) | 440, /* BB_RAMP6 */
};
static const u16 rf_ramp_pwm_cband_7090p[] = {
280, /* max RF gain in 10th of dB */
18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
504, /* ramp_max = maximum X used on the ramp */
(29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
(0 << 10) | 504, /* RF_RAMP6, LNA 1 */
(60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
(0 << 10) | 364, /* RF_RAMP8, LNA 2 */
(34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
(0 << 10) | 228, /* GAIN_4_2, LNA 3 */
(37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
(0 << 10) | 109, /* RF_RAMP4, LNA 4 */
};
static const u16 rf_ramp_pwm_cband_7090e_sensitivity[] = {
186, /* max RF gain in 10th of dB */
40, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
746, /* ramp_max = maximum X used on the ramp */
(10 << 10) | 345, /* RF_RAMP5, LNA 1 = 10dB */
(0 << 10) | 746, /* RF_RAMP6, LNA 1 */
(0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
(0 << 10) | 0, /* RF_RAMP8, LNA 2 */
(28 << 10) | 200, /* GAIN_4_1, LNA 3 = 6.8dB */ /* 3.61 dB */
(0 << 10) | 345, /* GAIN_4_2, LNA 3 */
(20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
(0 << 10) | 200, /* RF_RAMP4, LNA 4 */
};
static const u16 rf_ramp_pwm_cband_7090e_aci[] = {
86, /* max RF gain in 10th of dB */
40, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
345, /* ramp_max = maximum X used on the ramp */
(0 << 10) | 0, /* RF_RAMP5, LNA 1 = 8dB */ /* 7.47 dB */
(0 << 10) | 0, /* RF_RAMP6, LNA 1 */
(0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
(0 << 10) | 0, /* RF_RAMP8, LNA 2 */
(28 << 10) | 200, /* GAIN_4_1, LNA 3 = 6.8dB */ /* 3.61 dB */
(0 << 10) | 345, /* GAIN_4_2, LNA 3 */
(20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
(0 << 10) | 200, /* RF_RAMP4, LNA 4 */
};
static const u16 rf_ramp_pwm_cband_8090[] = {
345, /* max RF gain in 10th of dB */
29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
1000, /* ramp_max = maximum X used on the ramp */
(35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
(0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
(58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
(0 << 10) | 772, /* RF_RAMP6, LNA 2 */
(27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
(0 << 10) | 496, /* RF_RAMP8, LNA 3 */
(40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
(0 << 10) | 200, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_uhf_7090[] = {
407, /* max RF gain in 10th of dB */
13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
529, /* ramp_max = maximum X used on the ramp */
(23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
(0 << 10) | 176, /* RF_RAMP4, LNA 1 */
(63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
(0 << 10) | 529, /* RF_RAMP6, LNA 2 */
(48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
(0 << 10) | 400, /* RF_RAMP8, LNA 3 */
(29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
(0 << 10) | 316, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_uhf_8090[] = {
388, /* max RF gain in 10th of dB */
26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
1008, /* ramp_max = maximum X used on the ramp */
(11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
(0 << 10) | 369, /* RF_RAMP4, LNA 1 */
(41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
(0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
(27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
(0 << 10) | 809, /* RF_RAMP8, LNA 3 */
(14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
(0 << 10) | 659, /* GAIN_4_2, LNA 4 */
};
/* GENERAL PWM ramp definition for all other Krosus */
static const u16 bb_ramp_pwm_normal[] = {
500, /* max BB gain in 10th of dB */
8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
400,
(2 << 9) | 0, /* BB_RAMP3 = 21dB */
(0 << 9) | 168, /* BB_RAMP4 */
(2 << 9) | 168, /* BB_RAMP5 = 29dB */
(0 << 9) | 400, /* BB_RAMP6 */
};
#if 0
/* Currently unused */
static const u16 bb_ramp_pwm_boost[] = {
550, /* max BB gain in 10th of dB */
8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
440,
(2 << 9) | 0, /* BB_RAMP3 = 26dB */
(0 << 9) | 208, /* BB_RAMP4 */
(2 << 9) | 208, /* BB_RAMP5 = 29dB */
(0 << 9) | 440, /* BB_RAMP6 */
};
#endif
static const u16 rf_ramp_pwm_cband[] = {
314, /* max RF gain in 10th of dB */
33, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
1023, /* ramp_max = maximum X used on the ramp */
(8 << 10) | 743, /* RF_RAMP3, LNA 1 = 0dB */
(0 << 10) | 1023, /* RF_RAMP4, LNA 1 */
(15 << 10) | 469, /* RF_RAMP5, LNA 2 = 0dB */
(0 << 10) | 742, /* RF_RAMP6, LNA 2 */
(9 << 10) | 234, /* RF_RAMP7, LNA 3 = 0dB */
(0 << 10) | 468, /* RF_RAMP8, LNA 3 */
(9 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
(0 << 10) | 233, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_vhf[] = {
398, /* max RF gain in 10th of dB */
24, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
954, /* ramp_max = maximum X used on the ramp */
(7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
(0 << 10) | 290, /* RF_RAMP4, LNA 1 */
(16 << 10) | 699, /* RF_RAMP5, LNA 2 = 10.5dB */
(0 << 10) | 954, /* RF_RAMP6, LNA 2 */
(17 << 10) | 580, /* RF_RAMP7, LNA 3 = 5dB */
(0 << 10) | 699, /* RF_RAMP8, LNA 3 */
(7 << 10) | 290, /* GAIN_4_1, LNA 4 = 12.5dB */
(0 << 10) | 580, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_uhf[] = {
398, /* max RF gain in 10th of dB */
24, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
954, /* ramp_max = maximum X used on the ramp */
(7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
(0 << 10) | 290, /* RF_RAMP4, LNA 1 */
(16 << 10) | 699, /* RF_RAMP5, LNA 2 = 10.5dB */
(0 << 10) | 954, /* RF_RAMP6, LNA 2 */
(17 << 10) | 580, /* RF_RAMP7, LNA 3 = 5dB */
(0 << 10) | 699, /* RF_RAMP8, LNA 3 */
(7 << 10) | 290, /* GAIN_4_1, LNA 4 = 12.5dB */
(0 << 10) | 580, /* GAIN_4_2, LNA 4 */
};
#if 0
/* Currently unused */
static const u16 rf_ramp_pwm_sband[] = {
253, /* max RF gain in 10th of dB */
38, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
961,
(4 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.1dB */
(0 << 10) | 508, /* RF_RAMP4, LNA 1 */
(9 << 10) | 508, /* RF_RAMP5, LNA 2 = 11.2dB */
(0 << 10) | 961, /* RF_RAMP6, LNA 2 */
(0 << 10) | 0, /* RF_RAMP7, LNA 3 = 0dB */
(0 << 10) | 0, /* RF_RAMP8, LNA 3 */
(0 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
(0 << 10) | 0, /* GAIN_4_2, LNA 4 */
};
#endif
struct slope {
s16 range;
s16 slope;
};
static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
{
u8 i;
u16 rest;
u16 ret = 0;
for (i = 0; i < num; i++) {
if (val > slopes[i].range)
rest = slopes[i].range;
else
rest = val;
ret += (rest * slopes[i].slope) / slopes[i].range;
val -= rest;
}
return ret;
}
static const struct slope dib0090_wbd_slopes[3] = {
{66, 120}, /* -64,-52: offset - 65 */
{600, 170}, /* -52,-35: 65 - 665 */
{170, 250}, /* -45,-10: 665 - 835 */
};
static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)
{
wbd &= 0x3ff;
if (wbd < state->wbd_offset)
wbd = 0;
else
wbd -= state->wbd_offset;
/* -64dB is the floor */
return -640 + (s16) slopes_to_scale(dib0090_wbd_slopes, ARRAY_SIZE(dib0090_wbd_slopes), wbd);
}
static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)
{
u16 offset = 250;
/* TODO : DAB digital N+/-1 interferer perfs : offset = 10 */
if (state->current_band == BAND_VHF)
offset = 650;
#ifndef FIRMWARE_FIREFLY
if (state->current_band == BAND_VHF)
offset = state->config->wbd_vhf_offset;
if (state->current_band == BAND_CBAND)
offset = state->config->wbd_cband_offset;
#endif
state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);
dprintk("wbd-target: %d dB\n", (u32) state->wbd_target);
}
static const int gain_reg_addr[4] = {
0x08, 0x0a, 0x0f, 0x01
};
static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)
{
u16 rf, bb, ref;
u16 i, v, gain_reg[4] = { 0 }, gain;
const u16 *g;
if (top_delta < -511)
top_delta = -511;
if (top_delta > 511)
top_delta = 511;
if (force) {
top_delta *= (1 << WBD_ALPHA);
gain_delta *= (1 << GAIN_ALPHA);
}
if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */
state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
else
state->rf_gain_limit += top_delta;
if (state->rf_gain_limit < 0) /*underflow */
state->rf_gain_limit = 0;
/* use gain as a temporary variable and correct current_gain */
gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;
if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */
state->current_gain = gain;
else
state->current_gain += gain_delta;
/* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */
if (state->current_gain < 0)
state->current_gain = 0;
/* now split total gain to rf and bb gain */
gain = state->current_gain >> GAIN_ALPHA;
/* requested gain is bigger than rf gain limit - ACI/WBD adjustment */
if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {
rf = state->rf_gain_limit >> WBD_ALPHA;
bb = gain - rf;
if (bb > state->bb_ramp[0])
bb = state->bb_ramp[0];
} else { /* high signal level -> all gains put on RF */
rf = gain;
bb = 0;
}
state->gain[0] = rf;
state->gain[1] = bb;
/* software ramp */
/* Start with RF gains */
g = state->rf_ramp + 1; /* point on RF LNA1 max gain */
ref = rf;
for (i = 0; i < 7; i++) { /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */
if (g[0] == 0 || ref < (g[1] - g[0])) /* if total gain of the current amp is null or this amp is not concerned because it starts to work from an higher gain value */
v = 0; /* force the gain to write for the current amp to be null */
else if (ref >= g[1]) /* Gain to set is higher than the high working point of this amp */
v = g[2]; /* force this amp to be full gain */
else /* compute the value to set to this amp because we are somewhere in his range */
v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
if (i == 0) /* LNA 1 reg mapping */
gain_reg[0] = v;
else if (i == 1) /* LNA 2 reg mapping */
gain_reg[0] |= v << 7;
else if (i == 2) /* LNA 3 reg mapping */
gain_reg[1] = v;
else if (i == 3) /* LNA 4 reg mapping */
gain_reg[1] |= v << 7;
else if (i == 4) /* CBAND LNA reg mapping */
gain_reg[2] = v | state->rf_lt_def;
else if (i == 5) /* BB gain 1 reg mapping */
gain_reg[3] = v << 3;
else if (i == 6) /* BB gain 2 reg mapping */
gain_reg[3] |= v << 8;
g += 3; /* go to next gain bloc */
/* When RF is finished, start with BB */
if (i == 4) {
g = state->bb_ramp + 1; /* point on BB gain 1 max gain */
ref = bb;
}
}
gain_reg[3] |= state->bb_1_def;
gain_reg[3] |= ((bb % 10) * 100) / 125;
#ifdef DEBUG_AGC
dprintk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_reg[0]=%04x\n", rf, bb, rf + bb,
gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]);
#endif
/* Write the amplifier regs */
for (i = 0; i < 4; i++) {
v = gain_reg[i];
if (force || state->gain_reg[i] != v) {
state->gain_reg[i] = v;
dib0090_write_reg(state, gain_reg_addr[i], v);
}
}
}
static void dib0090_set_boost(struct dib0090_state *state, int onoff)
{
state->bb_1_def &= 0xdfff;
state->bb_1_def |= onoff << 13;
}
static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)
{
state->rf_ramp = cfg;
}
static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)
{
state->rf_ramp = cfg;
dib0090_write_reg(state, 0x2a, 0xffff);
dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
dib0090_write_regs(state, 0x2c, cfg + 3, 6);
dib0090_write_regs(state, 0x3e, cfg + 9, 2);
}
static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)
{
state->bb_ramp = cfg;
dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
}
static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)
{
state->bb_ramp = cfg;
dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
dib0090_write_reg(state, 0x33, 0xffff);
dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33));
dib0090_write_regs(state, 0x35, cfg + 3, 4);
}
void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
const u16 *bb_ramp = bb_ramp_pwm_normal; /* default baseband config */
const u16 *rf_ramp = NULL;
u8 en_pwm_rf_mux = 1;
/* reset the AGC */
if (state->config->use_pwm_agc) {
if (state->current_band == BAND_CBAND) {
if (state->identity.in_soc) {
bb_ramp = bb_ramp_pwm_normal_socs;
if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
rf_ramp = rf_ramp_pwm_cband_8090;
else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) {
if (state->config->is_dib7090e) {
if (state->rf_ramp == NULL)
rf_ramp = rf_ramp_pwm_cband_7090e_sensitivity;
else
rf_ramp = state->rf_ramp;
} else
rf_ramp = rf_ramp_pwm_cband_7090p;
}
} else
rf_ramp = rf_ramp_pwm_cband;
} else
if (state->current_band == BAND_VHF) {
if (state->identity.in_soc) {
bb_ramp = bb_ramp_pwm_normal_socs;
/* rf_ramp = &rf_ramp_pwm_vhf_socs; */ /* TODO */
} else
rf_ramp = rf_ramp_pwm_vhf;
} else if (state->current_band == BAND_UHF) {
if (state->identity.in_soc) {
bb_ramp = bb_ramp_pwm_normal_socs;
if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
rf_ramp = rf_ramp_pwm_uhf_8090;
else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
rf_ramp = rf_ramp_pwm_uhf_7090;
} else
rf_ramp = rf_ramp_pwm_uhf;
}
if (rf_ramp)
dib0090_set_rframp_pwm(state, rf_ramp);
dib0090_set_bbramp_pwm(state, bb_ramp);
/* activate the ramp generator using PWM control */
if (state->rf_ramp)
dprintk("ramp RF gain = %d BAND = %s version = %d\n",
state->rf_ramp[0],
(state->current_band == BAND_CBAND) ? "CBAND" : "NOT CBAND",
state->identity.version & 0x1f);
if (rf_ramp && ((state->rf_ramp && state->rf_ramp[0] == 0) ||
(state->current_band == BAND_CBAND &&
(state->identity.version & 0x1f) <= P1D_E_F))) {
dprintk("DE-Engage mux for direct gain reg control\n");
en_pwm_rf_mux = 0;
} else
dprintk("Engage mux for PWM control\n");
dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11));
/* Set fast servo cutoff to start AGC; 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast*/
if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
dib0090_write_reg(state, 0x04, 3);
else
dib0090_write_reg(state, 0x04, 1);
dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */
}
}
EXPORT_SYMBOL(dib0090_pwm_gain_reset);
void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
{
struct dib0090_state *state = fe->tuner_priv;
if (DC_servo_cutoff < 4)
dib0090_write_reg(state, 0x04, DC_servo_cutoff);
}
EXPORT_SYMBOL(dib0090_set_dc_servo);
static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
{
u16 adc_val = dib0090_read_reg(state, 0x1d);
if (state->identity.in_soc)
adc_val >>= 2;
return adc_val;
}
int dib0090_gain_control(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
enum frontend_tune_state *tune_state = &state->tune_state;
int ret = 10;
u16 wbd_val = 0;
u8 apply_gain_immediatly = 1;
s16 wbd_error = 0, adc_error = 0;
if (*tune_state == CT_AGC_START) {
state->agc_freeze = 0;
dib0090_write_reg(state, 0x04, 0x0);
#ifdef CONFIG_BAND_SBAND
if (state->current_band == BAND_SBAND) {
dib0090_set_rframp(state, rf_ramp_sband);
dib0090_set_bbramp(state, bb_ramp_boost);
} else
#endif
#ifdef CONFIG_BAND_VHF
if (state->current_band == BAND_VHF && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_pwm_vhf);
dib0090_set_bbramp(state, bb_ramp_pwm_normal);
} else
#endif
#ifdef CONFIG_BAND_CBAND
if (state->current_band == BAND_CBAND && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_pwm_cband);
dib0090_set_bbramp(state, bb_ramp_pwm_normal);
} else
#endif
if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_pwm_cband_7090p);
dib0090_set_bbramp(state, bb_ramp_pwm_normal_socs);
} else {
dib0090_set_rframp(state, rf_ramp_pwm_uhf);
dib0090_set_bbramp(state, bb_ramp_pwm_normal);
}
dib0090_write_reg(state, 0x32, 0);
dib0090_write_reg(state, 0x39, 0);
dib0090_wbd_target(state, state->current_rf);
state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;
*tune_state = CT_AGC_STEP_0;
} else if (!state->agc_freeze) {
s16 wbd = 0, i, cnt;
int adc;
wbd_val = dib0090_get_slow_adc_val(state);
if (*tune_state == CT_AGC_STEP_0)
cnt = 5;
else
cnt = 1;
for (i = 0; i < cnt; i++) {
wbd_val = dib0090_get_slow_adc_val(state);
wbd += dib0090_wbd_to_db(state, wbd_val);
}
wbd /= cnt;
wbd_error = state->wbd_target - wbd;
if (*tune_state == CT_AGC_STEP_0) {
if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
#ifdef CONFIG_BAND_CBAND
/* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
if (state->current_band == BAND_CBAND && ltg2) {
ltg2 >>= 1;
state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */
}
#endif
} else {
state->agc_step = 0;
*tune_state = CT_AGC_STEP_1;
}
} else {
/* calc the adc power */
adc = state->config->get_adc_power(fe);
adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */
adc_error = (s16) (((s32) ADC_TARGET) - adc);
#ifdef CONFIG_STANDARD_DAB
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
adc_error -= 10;
#endif
#ifdef CONFIG_STANDARD_DVBT
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
(state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
adc_error += 60;
#endif
#ifdef CONFIG_SYS_ISDBT
if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
0)
&&
((state->fe->dtv_property_cache.layer[0].modulation ==
QAM_64)
|| (state->fe->dtv_property_cache.
layer[0].modulation == QAM_16)))
||
((state->fe->dtv_property_cache.layer[1].segment_count >
0)
&&
((state->fe->dtv_property_cache.layer[1].modulation ==
QAM_64)
|| (state->fe->dtv_property_cache.
layer[1].modulation == QAM_16)))
||
((state->fe->dtv_property_cache.layer[2].segment_count >
0)
&&
((state->fe->dtv_property_cache.layer[2].modulation ==
QAM_64)
|| (state->fe->dtv_property_cache.
layer[2].modulation == QAM_16)))
)
)
adc_error += 60;
#endif
if (*tune_state == CT_AGC_STEP_1) { /* quickly go to the correct range of the ADC power */
if (abs(adc_error) < 50 || state->agc_step++ > 5) {
#ifdef CONFIG_STANDARD_DAB
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {
dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
dib0090_write_reg(state, 0x04, 0x0);
} else
#endif
{
dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
}
*tune_state = CT_AGC_STOP;
}
} else {
/* everything higher than or equal to CT_AGC_STOP means tracking */
ret = 100; /* 10ms interval */
apply_gain_immediatly = 0;
}
}
#ifdef DEBUG_AGC
dprintk
("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
(u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
(u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
#endif
}
/* apply gain */
if (!state->agc_freeze)
dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
return ret;
}
EXPORT_SYMBOL(dib0090_gain_control);
void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
{
struct dib0090_state *state = fe->tuner_priv;
if (rf)
*rf = state->gain[0];
if (bb)
*bb = state->gain[1];
if (rf_gain_limit)
*rf_gain_limit = state->rf_gain_limit;
if (rflt)
*rflt = (state->rf_lt_def >> 10) & 0x7;
}
EXPORT_SYMBOL(dib0090_get_current_gain);
u16 dib0090_get_wbd_target(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
s32 current_temp = state->temperature;
s32 wbd_thot, wbd_tcold;
const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
while (f_MHz > wbd->max_freq)
wbd++;
dprintk("using wbd-table-entry with max freq %d\n", wbd->max_freq);
if (current_temp < 0)
current_temp = 0;
if (current_temp > 128)
current_temp = 128;
state->wbdmux &= ~(7 << 13);
if (wbd->wbd_gain != 0)
state->wbdmux |= (wbd->wbd_gain << 13);
else
state->wbdmux |= (4 << 13);
dib0090_write_reg(state, 0x10, state->wbdmux);
wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
dprintk("wbd-target: %d dB\n", (u32) state->wbd_target);
dprintk("wbd offset applied is %d\n", wbd_tcold);
return state->wbd_offset + wbd_tcold;
}
EXPORT_SYMBOL(dib0090_get_wbd_target);
u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
return state->wbd_offset;
}
EXPORT_SYMBOL(dib0090_get_wbd_offset);
int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3)
{
struct dib0090_state *state = fe->tuner_priv;
dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
| ((sw3 & 1) << 2) | ((sw2 & 1) << 1) | (sw1 & 1));
return 0;
}
EXPORT_SYMBOL(dib0090_set_switch);
int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
{
struct dib0090_state *state = fe->tuner_priv;
dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
| ((onoff & 1) << 15));
return 0;
}
EXPORT_SYMBOL(dib0090_set_vga);
int dib0090_update_rframp_7090(struct dvb_frontend *fe, u8 cfg_sensitivity)
{
struct dib0090_state *state = fe->tuner_priv;
if ((!state->identity.p1g) || (!state->identity.in_soc)
|| ((state->identity.version != SOC_7090_P1G_21R1)
&& (state->identity.version != SOC_7090_P1G_11R1))) {
dprintk("%s() function can only be used for dib7090P\n", __func__);
return -ENODEV;
}
if (cfg_sensitivity)
state->rf_ramp = rf_ramp_pwm_cband_7090e_sensitivity;
else
state->rf_ramp = rf_ramp_pwm_cband_7090e_aci;
dib0090_pwm_gain_reset(fe);
return 0;
}
EXPORT_SYMBOL(dib0090_update_rframp_7090);
static const u16 dib0090_defaults[] = {
25, 0x01,
0x0000,
0x99a0,
0x6008,
0x0000,
0x8bcb,
0x0000,
0x0405,
0x0000,
0x0000,
0x0000,
0xb802,
0x0300,
0x2d12,
0xbac0,
0x7c00,
0xdbb9,
0x0954,
0x0743,
0x8000,
0x0001,
0x0040,
0x0100,
0x0000,
0xe910,
0x149e,
1, 0x1c,
0xff2d,
1, 0x39,
0x0000,
2, 0x1e,
0x07FF,
0x0007,
1, 0x24,
EN_UHF | EN_CRYSTAL,
2, 0x3c,
0x3ff,
0x111,
0
};
static const u16 dib0090_p1g_additionnal_defaults[] = {
1, 0x05,
0xabcd,
1, 0x11,
0x00b4,
1, 0x1c,
0xfffd,
1, 0x40,
0x108,
0
};
static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
{
u16 l, r;
l = pgm_read_word(n++);
while (l) {
r = pgm_read_word(n++);
do {
dib0090_write_reg(state, r, pgm_read_word(n++));
r++;
} while (--l);
l = pgm_read_word(n++);
}
}
#define CAP_VALUE_MIN (u8) 9
#define CAP_VALUE_MAX (u8) 40
#define HR_MIN (u8) 25
#define HR_MAX (u8) 40
#define POLY_MIN (u8) 0
#define POLY_MAX (u8) 8
static void dib0090_set_EFUSE(struct dib0090_state *state)
{
u8 c, h, n;
u16 e2, e4;
u16 cal;
e2 = dib0090_read_reg(state, 0x26);
e4 = dib0090_read_reg(state, 0x28);
if ((state->identity.version == P1D_E_F) ||
(state->identity.version == P1G) || (e2 == 0xffff)) {
dib0090_write_reg(state, 0x22, 0x10);
cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
if ((cal < 670) || (cal == 1023))
cal = 850;
n = 165 - ((cal * 10)>>6) ;
e2 = e4 = (3<<12) | (34<<6) | (n);
}
if (e2 != e4)
e2 &= e4; /* Remove the redundancy */
if (e2 != 0xffff) {
c = e2 & 0x3f;
n = (e2 >> 12) & 0xf;
h = (e2 >> 6) & 0x3f;
if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
c = 32;
else
c += 14;
if ((h >= HR_MAX) || (h <= HR_MIN))
h = 34;
if ((n >= POLY_MAX) || (n <= POLY_MIN))
n = 3;
dib0090_write_reg(state, 0x13, (h << 10));
e2 = (n << 11) | ((h >> 2)<<6) | c;
dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */
}
}
static int dib0090_reset(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
dib0090_reset_digital(fe, state->config);
if (dib0090_identify(fe) < 0)
return -EIO;
#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
return 0;
#endif
if (!state->identity.in_soc) {
if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
else
dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
}
dib0090_set_default_config(state, dib0090_defaults);
if (state->identity.in_soc)
dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
if (state->identity.p1g)
dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
/* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
dib0090_set_EFUSE(state);
/* Congigure in function of the crystal */
if (state->config->force_crystal_mode != 0)
dib0090_write_reg(state, 0x14,
state->config->force_crystal_mode & 3);
else if (state->config->io.clock_khz >= 24000)
dib0090_write_reg(state, 0x14, 1);
else
dib0090_write_reg(state, 0x14, 2);
dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
return 0;
}
#define steps(u) (((u) > 15) ? ((u)-16) : (u))
#define INTERN_WAIT 10
static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = INTERN_WAIT * 10;
switch (*tune_state) {
case CT_TUNER_STEP_2:
/* Turns to positive */
dib0090_write_reg(state, 0x1f, 0x7);
*tune_state = CT_TUNER_STEP_3;
break;
case CT_TUNER_STEP_3:
state->adc_diff = dib0090_read_reg(state, 0x1d);
/* Turns to negative */
dib0090_write_reg(state, 0x1f, 0x4);
*tune_state = CT_TUNER_STEP_4;
break;
case CT_TUNER_STEP_4:
state->adc_diff -= dib0090_read_reg(state, 0x1d);
*tune_state = CT_TUNER_STEP_5;
ret = 0;
break;
default:
break;
}
return ret;
}
struct dc_calibration {
u8 addr;
u8 offset;
u8 pga:1;
u16 bb1;
u8 i:1;
};
static const struct dc_calibration dc_table[] = {
/* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
{0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
{0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
/* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
{0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
{0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
{0},
};
static const struct dc_calibration dc_p1g_table[] = {
/* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
/* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
{0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
{0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
/* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
{0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
{0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
{0},
};
static void dib0090_set_trim(struct dib0090_state *state)
{
u16 *val;
if (state->dc->addr == 0x07)
val = &state->bb7;
else
val = &state->bb6;
*val &= ~(0x1f << state->dc->offset);
*val |= state->step << state->dc->offset;
dib0090_write_reg(state, state->dc->addr, *val);
}
static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 0;
u16 reg;
switch (*tune_state) {
case CT_TUNER_START:
dprintk("Start DC offset calibration");
/* force vcm2 = 0.8V */
state->bb6 = 0;
state->bb7 = 0x040d;
/* the LNA AND LO are off */
reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
dib0090_write_reg(state, 0x24, reg);
state->wbdmux = dib0090_read_reg(state, 0x10);
dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
state->dc = dc_table;
if (state->identity.p1g)
state->dc = dc_p1g_table;
fallthrough;
case CT_TUNER_STEP_0:
dprintk("Start/continue DC calibration for %s path\n",
(state->dc->i == 1) ? "I" : "Q");
dib0090_write_reg(state, 0x01, state->dc->bb1);
dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
state->step = 0;
state->min_adc_diff = 1023;
*tune_state = CT_TUNER_STEP_1;
ret = 50;
break;
case CT_TUNER_STEP_1:
dib0090_set_trim(state);
*tune_state = CT_TUNER_STEP_2;
break;
case CT_TUNER_STEP_2:
case CT_TUNER_STEP_3:
case CT_TUNER_STEP_4:
ret = dib0090_get_offset(state, tune_state);
break;
case CT_TUNER_STEP_5: /* found an offset */
dprintk("adc_diff = %d, current step= %d\n", (u32) state->adc_diff, state->step);
if (state->step == 0 && state->adc_diff < 0) {
state->min_adc_diff = -1023;
dprintk("Change of sign of the minimum adc diff\n");
}
dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d\n", state->adc_diff, state->min_adc_diff, state->step);
/* first turn for this frequency */
if (state->step == 0) {
if (state->dc->pga && state->adc_diff < 0)
state->step = 0x10;
if (state->dc->pga == 0 && state->adc_diff > 0)
state->step = 0x10;
}
/* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
/* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
state->step++;
state->min_adc_diff = state->adc_diff;
*tune_state = CT_TUNER_STEP_1;
} else {
/* the minimum was what we have seen in the step before */
if (abs(state->adc_diff) > abs(state->min_adc_diff)) {
dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step\n", state->adc_diff, state->min_adc_diff);
state->step--;
}
dib0090_set_trim(state);
dprintk("BB Offset Cal, BBreg=%u,Offset=%d,Value Set=%d\n",
state->dc->addr, state->adc_diff, state->step);
state->dc++;
if (state->dc->addr == 0) /* done */
*tune_state = CT_TUNER_STEP_6;
else
*tune_state = CT_TUNER_STEP_0;
}
break;
case CT_TUNER_STEP_6:
dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
dib0090_write_reg(state, 0x1f, 0x7);
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
state->calibrate &= ~DC_CAL;
break;
default:
break;
}
return ret;
}
static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
u8 wbd_gain;
const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
switch (*tune_state) {
case CT_TUNER_START:
while (state->current_rf / 1000 > wbd->max_freq)
wbd++;
if (wbd->wbd_gain != 0)
wbd_gain = wbd->wbd_gain;
else {
wbd_gain = 4;
#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
wbd_gain = 2;
#endif
}
if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
*tune_state = CT_TUNER_START;
state->calibrate &= ~WBD_CAL;
return 0;
}
dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
*tune_state = CT_TUNER_STEP_0;
state->wbd_calibration_gain = wbd_gain;
return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
case CT_TUNER_STEP_0:
state->wbd_offset = dib0090_get_slow_adc_val(state);
dprintk("WBD calibration offset = %d\n", state->wbd_offset);
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
state->calibrate &= ~WBD_CAL;
break;
default:
break;
}
return 0;
}
static void dib0090_set_bandwidth(struct dib0090_state *state)
{
u16 tmp;
if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)
tmp = (3 << 14);
else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)
tmp = (2 << 14);
else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)
tmp = (1 << 14);
else
tmp = (0 << 14);
state->bb_1_def &= 0x3fff;
state->bb_1_def |= tmp;
dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
if (state->identity.in_soc) {
dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
} else {
dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
}
}
static const struct dib0090_pll dib0090_pll_table[] = {
#ifdef CONFIG_BAND_CBAND
{56000, 0, 9, 48, 6},
{70000, 1, 9, 48, 6},
{87000, 0, 8, 32, 4},
{105000, 1, 8, 32, 4},
{115000, 0, 7, 24, 6},
{140000, 1, 7, 24, 6},
{170000, 0, 6, 16, 4},
#endif
#ifdef CONFIG_BAND_VHF
{200000, 1, 6, 16, 4},
{230000, 0, 5, 12, 6},
{280000, 1, 5, 12, 6},
{340000, 0, 4, 8, 4},
{380000, 1, 4, 8, 4},
{450000, 0, 3, 6, 6},
#endif
#ifdef CONFIG_BAND_UHF
{580000, 1, 3, 6, 6},
{700000, 0, 2, 4, 4},
{860000, 1, 2, 4, 4},
#endif
#ifdef CONFIG_BAND_LBAND
{1800000, 1, 0, 2, 4},
#endif
#ifdef CONFIG_BAND_SBAND
{2900000, 0, 14, 1, 4},
#endif
};
static const struct dib0090_tuning dib0090_tuning_table_fm_vhf_on_cband[] = {
#ifdef CONFIG_BAND_CBAND
{184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
{227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
{380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
#endif
#ifdef CONFIG_BAND_UHF
{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
#endif
};
static const struct dib0090_tuning dib0090_tuning_table[] = {
#ifdef CONFIG_BAND_CBAND
{170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
#endif
#ifdef CONFIG_BAND_VHF
{184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
{227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
{380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
#endif
#ifdef CONFIG_BAND_UHF
{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
#endif
};
static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
#ifdef CONFIG_BAND_CBAND
{170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
#endif
#ifdef CONFIG_BAND_VHF
{184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
{227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
{380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
#endif
#ifdef CONFIG_BAND_UHF
{510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
#endif
};
static const struct dib0090_pll dib0090_p1g_pll_table[] = {
#ifdef CONFIG_BAND_CBAND
{57000, 0, 11, 48, 6},
{70000, 1, 11, 48, 6},
{86000, 0, 10, 32, 4},
{105000, 1, 10, 32, 4},
{115000, 0, 9, 24, 6},
{140000, 1, 9, 24, 6},
{170000, 0, 8, 16, 4},
#endif
#ifdef CONFIG_BAND_VHF
{200000, 1, 8, 16, 4},
{230000, 0, 7, 12, 6},
{280000, 1, 7, 12, 6},
{340000, 0, 6, 8, 4},
{380000, 1, 6, 8, 4},
{455000, 0, 5, 6, 6},
#endif
#ifdef CONFIG_BAND_UHF
{580000, 1, 5, 6, 6},
{680000, 0, 4, 4, 4},
{860000, 1, 4, 4, 4},
#endif
#ifdef CONFIG_BAND_LBAND
{1800000, 1, 2, 2, 4},
#endif
#ifdef CONFIG_BAND_SBAND
{2900000, 0, 1, 1, 6},
#endif
};
static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
#ifdef CONFIG_BAND_CBAND
{184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
{227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
{380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
#endif
#ifdef CONFIG_BAND_UHF
{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
#endif
};
static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
#ifdef CONFIG_BAND_CBAND
{300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
{380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
{570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
{858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
#endif
};
static const struct dib0090_tuning dib0090_tuning_table_cband_7090e_sensitivity[] = {
#ifdef CONFIG_BAND_CBAND
{ 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
{ 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
{ 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
{ 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
{ 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
{ 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
#endif
};
int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
u8 cfg_sensitivity)
{
struct dib0090_state *state = fe->tuner_priv;
const struct dib0090_tuning *tune =
dib0090_tuning_table_cband_7090e_sensitivity;
static const struct dib0090_tuning dib0090_tuning_table_cband_7090e_aci[] = {
{ 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
{ 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB },
{ 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB },
};
if ((!state->identity.p1g) || (!state->identity.in_soc)
|| ((state->identity.version != SOC_7090_P1G_21R1)
&& (state->identity.version != SOC_7090_P1G_11R1))) {
dprintk("%s() function can only be used for dib7090\n", __func__);
return -ENODEV;
}
if (cfg_sensitivity)
tune = dib0090_tuning_table_cband_7090e_sensitivity;
else
tune = dib0090_tuning_table_cband_7090e_aci;
while (state->rf_request > tune->max_freq)
tune++;
dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
| (tune->lna_bias & 0x7fff));
dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
| ((tune->lna_tune << 6) & 0x07c0));
return 0;
}
EXPORT_SYMBOL(dib0090_update_tuning_table_7090);
static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 0;
u16 lo4 = 0xe900;
s16 adc_target;
u16 adc;
s8 step_sign;
u8 force_soft_search = 0;
if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
force_soft_search = 1;
if (*tune_state == CT_TUNER_START) {
dprintk("Start Captrim search : %s\n",
(force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
dib0090_write_reg(state, 0x10, 0x2B1);
dib0090_write_reg(state, 0x1e, 0x0032);
if (!state->tuner_is_tuned) {
/* prepare a complete captrim */
if (!state->identity.p1g || force_soft_search)
state->step = state->captrim = state->fcaptrim = 64;
state->current_rf = state->rf_request;
} else { /* we are already tuned to this frequency - the configuration is correct */
if (!state->identity.p1g || force_soft_search) {
/* do a minimal captrim even if the frequency has not changed */
state->step = 4;
state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
}
}
state->adc_diff = 3000;
*tune_state = CT_TUNER_STEP_0;
} else if (*tune_state == CT_TUNER_STEP_0) {
if (state->identity.p1g && !force_soft_search) {
u8 ratio = 31;
dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
dib0090_read_reg(state, 0x40);
ret = 50;
} else {
state->step /= 2;
dib0090_write_reg(state, 0x18, lo4 | state->captrim);
if (state->identity.in_soc)
ret = 25;
}
*tune_state = CT_TUNER_STEP_1;
} else if (*tune_state == CT_TUNER_STEP_1) {
if (state->identity.p1g && !force_soft_search) {
dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
dib0090_read_reg(state, 0x40);
state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
dprintk("***Final Captrim= 0x%x\n", state->fcaptrim);
*tune_state = CT_TUNER_STEP_3;
} else {
/* MERGE for all krosus before P1G */
adc = dib0090_get_slow_adc_val(state);
dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV\n", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
adc_target = 200;
} else
adc_target = 400;
if (adc >= adc_target) {
adc -= adc_target;
step_sign = -1;
} else {
adc = adc_target - adc;
step_sign = 1;
}
if (adc < state->adc_diff) {
dprintk("CAPTRIM=%d is closer to target (%d/%d)\n", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
state->adc_diff = adc;
state->fcaptrim = state->captrim;
}
state->captrim += step_sign * state->step;
if (state->step >= 1)
*tune_state = CT_TUNER_STEP_0;
else
*tune_state = CT_TUNER_STEP_2;
ret = 25;
}
} else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
/*write the final cptrim config */
dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
*tune_state = CT_TUNER_STEP_3;
} else if (*tune_state == CT_TUNER_STEP_3) {
state->calibrate &= ~CAPTRIM_CAL;
*tune_state = CT_TUNER_STEP_0;
}
return ret;
}
static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 15;
s16 val;
switch (*tune_state) {
case CT_TUNER_START:
state->wbdmux = dib0090_read_reg(state, 0x10);
dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
state->bias = dib0090_read_reg(state, 0x13);
dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
*tune_state = CT_TUNER_STEP_0;
/* wait for the WBDMUX to switch and for the ADC to sample */
break;
case CT_TUNER_STEP_0:
state->adc_diff = dib0090_get_slow_adc_val(state);
dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
*tune_state = CT_TUNER_STEP_1;
break;
case CT_TUNER_STEP_1:
val = dib0090_get_slow_adc_val(state);
state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
dprintk("temperature: %d C\n", state->temperature - 30);
*tune_state = CT_TUNER_STEP_2;
break;
case CT_TUNER_STEP_2:
dib0090_write_reg(state, 0x13, state->bias);
dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
*tune_state = CT_TUNER_START;
state->calibrate &= ~TEMP_CAL;
if (state->config->analog_output == 0)
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
break;
default:
ret = 0;
break;
}
return ret;
}
#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
static int dib0090_tune(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
const struct dib0090_tuning *tune = state->current_tune_table_index;
const struct dib0090_pll *pll = state->current_pll_table_index;
enum frontend_tune_state *tune_state = &state->tune_state;
u16 lo5, lo6, Den, tmp;
u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
int ret = 10; /* 1ms is the default delay most of the time */
u8 c, i;
/************************* VCO ***************************/
/* Default values for FG */
/* from these are needed : */
/* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
/* in any case we first need to do a calibration if needed */
if (*tune_state == CT_TUNER_START) {
/* deactivate DataTX before some calibrations */
if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
else
/* Activate DataTX in case a calibration has been done before */
if (state->config->analog_output == 0)
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
}
if (state->calibrate & DC_CAL)
return dib0090_dc_offset_calibration(state, tune_state);
else if (state->calibrate & WBD_CAL) {
if (state->current_rf == 0)
state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
return dib0090_wbd_calibration(state, tune_state);
} else if (state->calibrate & TEMP_CAL)
return dib0090_get_temperature(state, tune_state);
else if (state->calibrate & CAPTRIM_CAL)
return dib0090_captrim_search(state, tune_state);
if (*tune_state == CT_TUNER_START) {
/* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
if (state->config->use_pwm_agc && state->identity.in_soc) {
tmp = dib0090_read_reg(state, 0x39);
if ((tmp >> 10) & 0x1)
dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
}
state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
state->rf_request =
state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
freq_offset_khz_vhf);
/* in ISDB-T 1seg we shift tuning frequency */
if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
&& state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
u8 found_offset = 0;
u32 margin_khz = 100;
if (LUT_offset != NULL) {
while (LUT_offset->RF_freq != 0xffff) {
if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
&& (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
&& LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
state->rf_request += LUT_offset->offset_khz;
found_offset = 1;
break;
}
LUT_offset++;
}
}
if (found_offset == 0)
state->rf_request += 400;
}
if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
state->tuner_is_tuned = 0;
state->current_rf = 0;
state->current_standard = 0;
tune = dib0090_tuning_table;
if (state->identity.p1g)
tune = dib0090_p1g_tuning_table;
tmp = (state->identity.version >> 5) & 0x7;
if (state->identity.in_soc) {
if (state->config->force_cband_input) { /* Use the CBAND input for all band */
if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
|| state->current_band & BAND_UHF) {
state->current_band = BAND_CBAND;
if (state->config->is_dib7090e)
tune = dib0090_tuning_table_cband_7090e_sensitivity;
else
tune = dib0090_tuning_table_cband_7090;
}
} else { /* Use the CBAND input for all band under UHF */
if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
state->current_band = BAND_CBAND;
if (state->config->is_dib7090e)
tune = dib0090_tuning_table_cband_7090e_sensitivity;
else
tune = dib0090_tuning_table_cband_7090;
}
}
} else
if (tmp == 0x4 || tmp == 0x7) {
/* CBAND tuner version for VHF */
if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
state->current_band = BAND_CBAND; /* Force CBAND */
tune = dib0090_tuning_table_fm_vhf_on_cband;
if (state->identity.p1g)
tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
}
}
pll = dib0090_pll_table;
if (state->identity.p1g)
pll = dib0090_p1g_pll_table;
/* Look for the interval */
while (state->rf_request > tune->max_freq)
tune++;
while (state->rf_request > pll->max_freq)
pll++;
state->current_tune_table_index = tune;
state->current_pll_table_index = pll;
dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
FREF = state->config->io.clock_khz;
if (state->config->fref_clock_ratio != 0)
FREF /= state->config->fref_clock_ratio;
FBDiv = (VCOF_kHz / pll->topresc / FREF);
Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
if (Rest < LPF)
Rest = 0;
else if (Rest < 2 * LPF)
Rest = 2 * LPF;
else if (Rest > (FREF - LPF)) {
Rest = 0;
FBDiv += 1;
} else if (Rest > (FREF - 2 * LPF))
Rest = FREF - 2 * LPF;
Rest = (Rest * 6528) / (FREF / 10);
state->rest = Rest;
/* external loop filter, otherwise:
* lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
* lo6 = 0x0e34 */
if (Rest == 0) {
if (pll->vco_band)
lo5 = 0x049f;
else
lo5 = 0x041f;
} else {
if (pll->vco_band)
lo5 = 0x049e;
else if (state->config->analog_output)
lo5 = 0x041d;
else
lo5 = 0x041c;
}
if (state->identity.p1g) { /* Bias is done automatically in P1G */
if (state->identity.in_soc) {
if (state->identity.version == SOC_8090_P1G_11R1)
lo5 = 0x46f;
else
lo5 = 0x42f;
} else
lo5 = 0x42c;
}
lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
if (!state->config->io.pll_int_loop_filt) {
if (state->identity.in_soc)
lo6 = 0xff98;
else if (state->identity.p1g || (Rest == 0))
lo6 = 0xfff8;
else
lo6 = 0xff28;
} else
lo6 = (state->config->io.pll_int_loop_filt << 3);
Den = 1;
if (Rest > 0) {
lo6 |= (1 << 2) | 2;
Den = 255;
}
dib0090_write_reg(state, 0x15, (u16) FBDiv);
if (state->config->fref_clock_ratio != 0)
dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
else
dib0090_write_reg(state, 0x16, (Den << 8) | 1);
dib0090_write_reg(state, 0x17, (u16) Rest);
dib0090_write_reg(state, 0x19, lo5);
dib0090_write_reg(state, 0x1c, lo6);
lo6 = tune->tuner_enable;
if (state->config->analog_output)
lo6 = (lo6 & 0xff9f) | 0x2;
dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
}
state->current_rf = state->rf_request;
state->current_standard = state->fe->dtv_property_cache.delivery_system;
ret = 20;
state->calibrate = CAPTRIM_CAL; /* captrim search now */
}
else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
while (state->current_rf / 1000 > wbd->max_freq)
wbd++;
dib0090_write_reg(state, 0x1e, 0x07ff);
dprintk("Final Captrim: %d\n", (u32) state->fcaptrim);
dprintk("HFDIV code: %d\n", (u32) pll->hfdiv_code);
dprintk("VCO = %d\n", (u32) pll->vco_band);
dprintk("VCOF in kHz: %d ((%d*%d) << 1))\n", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
dprintk("REFDIV: %d, FREF: %d\n", (u32) 1, (u32) state->config->io.clock_khz);
dprintk("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
dprintk("Num: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
(u32) dib0090_read_reg(state, 0x1c) & 0x3);
#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
c = 4;
i = 3;
if (wbd->wbd_gain != 0)
c = wbd->wbd_gain;
state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
dib0090_write_reg(state, 0x10, state->wbdmux);
if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
dprintk("P1G : The cable band is selected and lna_tune = %d\n", tune->lna_tune);
dib0090_write_reg(state, 0x09, tune->lna_bias);
dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
} else
dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
dib0090_write_reg(state, 0x0c, tune->v2i);
dib0090_write_reg(state, 0x0d, tune->mix);
dib0090_write_reg(state, 0x0e, tune->load);
*tune_state = CT_TUNER_STEP_1;
} else if (*tune_state == CT_TUNER_STEP_1) {
/* initialize the lt gain register */
state->rf_lt_def = 0x7c00;
dib0090_set_bandwidth(state);
state->tuner_is_tuned = 1;
state->calibrate |= WBD_CAL;
state->calibrate |= TEMP_CAL;
*tune_state = CT_TUNER_STOP;
} else
ret = FE_CALLBACK_TIME_NEVER;
return ret;
}
static void dib0090_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
return state->tune_state;
}
EXPORT_SYMBOL(dib0090_get_tune_state);
int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{
struct dib0090_state *state = fe->tuner_priv;
state->tune_state = tune_state;
return 0;
}
EXPORT_SYMBOL(dib0090_set_tune_state);
static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
{
struct dib0090_state *state = fe->tuner_priv;
*frequency = 1000 * state->current_rf;
return 0;
}
static int dib0090_set_params(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
u32 ret;
state->tune_state = CT_TUNER_START;
do {
ret = dib0090_tune(fe);
if (ret == FE_CALLBACK_TIME_NEVER)
break;
/*
* Despite dib0090_tune returns time at a 0.1 ms range,
* the actual sleep time depends on CONFIG_HZ. The worse case
* is when CONFIG_HZ=100. In such case, the minimum granularity
* is 10ms. On some real field tests, the tuner sometimes don't
* lock when this timer is lower than 10ms. So, enforce a 10ms
* granularity and use usleep_range() instead of msleep().
*/
ret = 10 * (ret + 99)/100;
usleep_range(ret * 1000, (ret + 1) * 1000);
} while (state->tune_state != CT_TUNER_STOP);
return 0;
}
static const struct dvb_tuner_ops dib0090_ops = {
.info = {
.name = "DiBcom DiB0090",
.frequency_min_hz = 45 * MHz,
.frequency_max_hz = 860 * MHz,
.frequency_step_hz = 1 * kHz,
},
.release = dib0090_release,
.init = dib0090_wakeup,
.sleep = dib0090_sleep,
.set_params = dib0090_set_params,
.get_frequency = dib0090_get_frequency,
};
static const struct dvb_tuner_ops dib0090_fw_ops = {
.info = {
.name = "DiBcom DiB0090",
.frequency_min_hz = 45 * MHz,
.frequency_max_hz = 860 * MHz,
.frequency_step_hz = 1 * kHz,
},
.release = dib0090_release,
.init = NULL,
.sleep = NULL,
.set_params = NULL,
.get_frequency = NULL,
};
static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
{470, 0, 250, 0, 100, 4},
{860, 51, 866, 21, 375, 4},
{1700, 0, 800, 0, 850, 4},
{2900, 0, 250, 0, 100, 6},
{0xFFFF, 0, 0, 0, 0, 0},
};
struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
{
struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
if (st == NULL)
return NULL;
st->config = config;
st->i2c = i2c;
st->fe = fe;
mutex_init(&st->i2c_buffer_lock);
fe->tuner_priv = st;
if (config->wbd == NULL)
st->current_wbd_table = dib0090_wbd_table_default;
else
st->current_wbd_table = config->wbd;
if (dib0090_reset(fe) != 0)
goto free_mem;
pr_info("DiB0090: successfully identified\n");
memcpy(&fe->ops.tuner_ops, &dib0090_ops, sizeof(struct dvb_tuner_ops));
return fe;
free_mem:
kfree(st);
fe->tuner_priv = NULL;
return NULL;
}
EXPORT_SYMBOL_GPL(dib0090_register);
struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
{
struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
if (st == NULL)
return NULL;
st->config = config;
st->i2c = i2c;
st->fe = fe;
mutex_init(&st->i2c_buffer_lock);
fe->tuner_priv = st;
if (dib0090_fw_reset_digital(fe, st->config) != 0)
goto free_mem;
dprintk("DiB0090 FW: successfully identified\n");
memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
return fe;
free_mem:
kfree(st);
fe->tuner_priv = NULL;
return NULL;
}
EXPORT_SYMBOL_GPL(dib0090_fw_register);
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_AUTHOR("Olivier Grenie <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib0090.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator
* LGS8913, LGS8GL5, LGS8G75
* experimental support LGS8G42, LGS8G52
*
* Copyright (C) 2007-2009 David T.L. Wong <[email protected]>
* Copyright (C) 2008 Sirius International (Hong Kong) Limited
* Timothy Lee <[email protected]> (for initial work on LGS8GL5)
*/
#include <asm/div64.h>
#include <linux/firmware.h>
#include <media/dvb_frontend.h>
#include "lgs8gxx.h"
#include "lgs8gxx_priv.h"
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "lgs8gxx: " args); \
} while (0)
static int debug;
static int fake_signal_str = 1;
#define LGS8GXX_FIRMWARE "lgs8g75.fw"
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
module_param(fake_signal_str, int, 0644);
MODULE_PARM_DESC(fake_signal_str, "fake signal strength for LGS8913."
"Signal strength calculation is slow.(default:on).");
/* LGS8GXX internal helper functions */
static int lgs8gxx_write_reg(struct lgs8gxx_state *priv, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
msg.addr = priv->config->demod_address;
if (priv->config->prod != LGS8GXX_PROD_LGS8G75 && reg >= 0xC0)
msg.addr += 0x02;
if (debug >= 2)
dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static int lgs8gxx_read_reg(struct lgs8gxx_state *priv, u8 reg, u8 *p_data)
{
int ret;
u8 dev_addr;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .flags = 0, .buf = b0, .len = 1 },
{ .flags = I2C_M_RD, .buf = b1, .len = 1 },
};
dev_addr = priv->config->demod_address;
if (priv->config->prod != LGS8GXX_PROD_LGS8G75 && reg >= 0xC0)
dev_addr += 0x02;
msg[1].addr = msg[0].addr = dev_addr;
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret != 2) {
dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret);
return -1;
}
*p_data = b1[0];
if (debug >= 2)
dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, b1[0]);
return 0;
}
static int lgs8gxx_soft_reset(struct lgs8gxx_state *priv)
{
lgs8gxx_write_reg(priv, 0x02, 0x00);
msleep(1);
lgs8gxx_write_reg(priv, 0x02, 0x01);
msleep(100);
return 0;
}
static int wait_reg_mask(struct lgs8gxx_state *priv, u8 reg, u8 mask,
u8 val, u8 delay, u8 tries)
{
u8 t;
int i;
for (i = 0; i < tries; i++) {
lgs8gxx_read_reg(priv, reg, &t);
if ((t & mask) == val)
return 0;
msleep(delay);
}
return 1;
}
static int lgs8gxx_set_ad_mode(struct lgs8gxx_state *priv)
{
const struct lgs8gxx_config *config = priv->config;
u8 if_conf;
if_conf = 0x10; /* AGC output on, RF_AGC output off; */
if_conf |=
((config->ext_adc) ? 0x80 : 0x00) |
((config->if_neg_center) ? 0x04 : 0x00) |
((config->if_freq == 0) ? 0x08 : 0x00) | /* Baseband */
((config->adc_signed) ? 0x02 : 0x00) |
((config->if_neg_edge) ? 0x01 : 0x00);
if (config->ext_adc &&
(config->prod == LGS8GXX_PROD_LGS8G52)) {
lgs8gxx_write_reg(priv, 0xBA, 0x40);
}
lgs8gxx_write_reg(priv, 0x07, if_conf);
return 0;
}
static int lgs8gxx_set_if_freq(struct lgs8gxx_state *priv, u32 freq /*in kHz*/)
{
u64 val;
u32 v32;
u32 if_clk;
if_clk = priv->config->if_clk_freq;
val = freq;
if (freq != 0) {
val <<= 32;
if (if_clk != 0)
do_div(val, if_clk);
v32 = val & 0xFFFFFFFF;
dprintk("Set IF Freq to %dkHz\n", freq);
} else {
v32 = 0;
dprintk("Set IF Freq to baseband\n");
}
dprintk("AFC_INIT_FREQ = 0x%08X\n", v32);
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_write_reg(priv, 0x08, 0xFF & (v32));
lgs8gxx_write_reg(priv, 0x09, 0xFF & (v32 >> 8));
lgs8gxx_write_reg(priv, 0x0A, 0xFF & (v32 >> 16));
lgs8gxx_write_reg(priv, 0x0B, 0xFF & (v32 >> 24));
} else {
lgs8gxx_write_reg(priv, 0x09, 0xFF & (v32));
lgs8gxx_write_reg(priv, 0x0A, 0xFF & (v32 >> 8));
lgs8gxx_write_reg(priv, 0x0B, 0xFF & (v32 >> 16));
lgs8gxx_write_reg(priv, 0x0C, 0xFF & (v32 >> 24));
}
return 0;
}
static int lgs8gxx_get_afc_phase(struct lgs8gxx_state *priv)
{
u64 val;
u32 v32 = 0;
u8 reg_addr, t;
int i;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75)
reg_addr = 0x23;
else
reg_addr = 0x48;
for (i = 0; i < 4; i++) {
lgs8gxx_read_reg(priv, reg_addr, &t);
v32 <<= 8;
v32 |= t;
reg_addr--;
}
val = v32;
val *= priv->config->if_clk_freq;
val >>= 32;
dprintk("AFC = %u kHz\n", (u32)val);
return 0;
}
static int lgs8gxx_set_mode_auto(struct lgs8gxx_state *priv)
{
u8 t;
u8 prod = priv->config->prod;
if (prod == LGS8GXX_PROD_LGS8913)
lgs8gxx_write_reg(priv, 0xC6, 0x01);
if (prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_read_reg(priv, 0x0C, &t);
t &= (~0x04);
lgs8gxx_write_reg(priv, 0x0C, t | 0x80);
lgs8gxx_write_reg(priv, 0x39, 0x00);
lgs8gxx_write_reg(priv, 0x3D, 0x04);
} else if (prod == LGS8GXX_PROD_LGS8913 ||
prod == LGS8GXX_PROD_LGS8GL5 ||
prod == LGS8GXX_PROD_LGS8G42 ||
prod == LGS8GXX_PROD_LGS8G52 ||
prod == LGS8GXX_PROD_LGS8G54) {
lgs8gxx_read_reg(priv, 0x7E, &t);
lgs8gxx_write_reg(priv, 0x7E, t | 0x01);
/* clear FEC self reset */
lgs8gxx_read_reg(priv, 0xC5, &t);
lgs8gxx_write_reg(priv, 0xC5, t & 0xE0);
}
if (prod == LGS8GXX_PROD_LGS8913) {
/* FEC auto detect */
lgs8gxx_write_reg(priv, 0xC1, 0x03);
lgs8gxx_read_reg(priv, 0x7C, &t);
t = (t & 0x8C) | 0x03;
lgs8gxx_write_reg(priv, 0x7C, t);
/* BER test mode */
lgs8gxx_read_reg(priv, 0xC3, &t);
t = (t & 0xEF) | 0x10;
lgs8gxx_write_reg(priv, 0xC3, t);
}
if (priv->config->prod == LGS8GXX_PROD_LGS8G52)
lgs8gxx_write_reg(priv, 0xD9, 0x40);
return 0;
}
static int lgs8gxx_set_mode_manual(struct lgs8gxx_state *priv)
{
u8 t;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
u8 t2;
lgs8gxx_read_reg(priv, 0x0C, &t);
t &= (~0x80);
lgs8gxx_write_reg(priv, 0x0C, t);
lgs8gxx_read_reg(priv, 0x0C, &t);
lgs8gxx_read_reg(priv, 0x19, &t2);
if (((t&0x03) == 0x01) && (t2&0x01)) {
lgs8gxx_write_reg(priv, 0x6E, 0x05);
lgs8gxx_write_reg(priv, 0x39, 0x02);
lgs8gxx_write_reg(priv, 0x39, 0x03);
lgs8gxx_write_reg(priv, 0x3D, 0x05);
lgs8gxx_write_reg(priv, 0x3E, 0x28);
lgs8gxx_write_reg(priv, 0x53, 0x80);
} else {
lgs8gxx_write_reg(priv, 0x6E, 0x3F);
lgs8gxx_write_reg(priv, 0x39, 0x00);
lgs8gxx_write_reg(priv, 0x3D, 0x04);
}
lgs8gxx_soft_reset(priv);
return 0;
}
/* turn off auto-detect; manual settings */
lgs8gxx_write_reg(priv, 0x7E, 0);
if (priv->config->prod == LGS8GXX_PROD_LGS8913)
lgs8gxx_write_reg(priv, 0xC1, 0);
lgs8gxx_read_reg(priv, 0xC5, &t);
t = (t & 0xE0) | 0x06;
lgs8gxx_write_reg(priv, 0xC5, t);
lgs8gxx_soft_reset(priv);
return 0;
}
static int lgs8gxx_is_locked(struct lgs8gxx_state *priv, u8 *locked)
{
int ret = 0;
u8 t;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75)
ret = lgs8gxx_read_reg(priv, 0x13, &t);
else
ret = lgs8gxx_read_reg(priv, 0x4B, &t);
if (ret != 0)
return ret;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75)
*locked = ((t & 0x80) == 0x80) ? 1 : 0;
else
*locked = ((t & 0xC0) == 0xC0) ? 1 : 0;
return 0;
}
/* Wait for Code Acquisition Lock */
static int lgs8gxx_wait_ca_lock(struct lgs8gxx_state *priv, u8 *locked)
{
int ret = 0;
u8 reg, mask, val;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
reg = 0x13;
mask = 0x80;
val = 0x80;
} else {
reg = 0x4B;
mask = 0xC0;
val = 0xC0;
}
ret = wait_reg_mask(priv, reg, mask, val, 50, 40);
*locked = (ret == 0) ? 1 : 0;
return 0;
}
static int lgs8gxx_is_autodetect_finished(struct lgs8gxx_state *priv,
u8 *finished)
{
int ret = 0;
u8 reg, mask, val;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
reg = 0x1f;
mask = 0xC0;
val = 0x80;
} else {
reg = 0xA4;
mask = 0x03;
val = 0x01;
}
ret = wait_reg_mask(priv, reg, mask, val, 10, 20);
*finished = (ret == 0) ? 1 : 0;
return 0;
}
static int lgs8gxx_autolock_gi(struct lgs8gxx_state *priv, u8 gi, u8 cpn,
u8 *locked)
{
int err = 0;
u8 ad_fini = 0;
u8 t1, t2;
if (gi == GI_945)
dprintk("try GI 945\n");
else if (gi == GI_595)
dprintk("try GI 595\n");
else if (gi == GI_420)
dprintk("try GI 420\n");
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_read_reg(priv, 0x0C, &t1);
lgs8gxx_read_reg(priv, 0x18, &t2);
t1 &= ~(GI_MASK);
t1 |= gi;
t2 &= 0xFE;
t2 |= cpn ? 0x01 : 0x00;
lgs8gxx_write_reg(priv, 0x0C, t1);
lgs8gxx_write_reg(priv, 0x18, t2);
} else {
lgs8gxx_write_reg(priv, 0x04, gi);
}
lgs8gxx_soft_reset(priv);
err = lgs8gxx_wait_ca_lock(priv, locked);
if (err || !(*locked))
return err;
err = lgs8gxx_is_autodetect_finished(priv, &ad_fini);
if (err != 0)
return err;
if (ad_fini) {
dprintk("auto detect finished\n");
} else
*locked = 0;
return 0;
}
static int lgs8gxx_auto_detect(struct lgs8gxx_state *priv,
u8 *detected_param, u8 *gi)
{
int i, j;
int err = 0;
u8 locked = 0, tmp_gi;
dprintk("%s\n", __func__);
lgs8gxx_set_mode_auto(priv);
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_write_reg(priv, 0x67, 0xAA);
lgs8gxx_write_reg(priv, 0x6E, 0x3F);
} else {
/* Guard Interval */
lgs8gxx_write_reg(priv, 0x03, 00);
}
for (i = 0; i < 2; i++) {
for (j = 0; j < 2; j++) {
tmp_gi = GI_945;
err = lgs8gxx_autolock_gi(priv, GI_945, j, &locked);
if (err)
goto out;
if (locked)
goto locked;
}
for (j = 0; j < 2; j++) {
tmp_gi = GI_420;
err = lgs8gxx_autolock_gi(priv, GI_420, j, &locked);
if (err)
goto out;
if (locked)
goto locked;
}
tmp_gi = GI_595;
err = lgs8gxx_autolock_gi(priv, GI_595, 1, &locked);
if (err)
goto out;
if (locked)
goto locked;
}
locked:
if ((err == 0) && (locked == 1)) {
u8 t;
if (priv->config->prod != LGS8GXX_PROD_LGS8G75) {
lgs8gxx_read_reg(priv, 0xA2, &t);
*detected_param = t;
} else {
lgs8gxx_read_reg(priv, 0x1F, &t);
*detected_param = t & 0x3F;
}
if (tmp_gi == GI_945)
dprintk("GI 945 locked\n");
else if (tmp_gi == GI_595)
dprintk("GI 595 locked\n");
else if (tmp_gi == GI_420)
dprintk("GI 420 locked\n");
*gi = tmp_gi;
}
if (!locked)
err = -1;
out:
return err;
}
static void lgs8gxx_auto_lock(struct lgs8gxx_state *priv)
{
s8 err;
u8 gi = 0x2;
u8 detected_param = 0;
err = lgs8gxx_auto_detect(priv, &detected_param, &gi);
if (err != 0) {
dprintk("lgs8gxx_auto_detect failed\n");
} else
dprintk("detected param = 0x%02X\n", detected_param);
/* Apply detected parameters */
if (priv->config->prod == LGS8GXX_PROD_LGS8913) {
u8 inter_leave_len = detected_param & TIM_MASK ;
/* Fix 8913 time interleaver detection bug */
inter_leave_len = (inter_leave_len == TIM_MIDDLE) ? 0x60 : 0x40;
detected_param &= CF_MASK | SC_MASK | LGS_FEC_MASK;
detected_param |= inter_leave_len;
}
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
u8 t;
lgs8gxx_read_reg(priv, 0x19, &t);
t &= 0x81;
t |= detected_param << 1;
lgs8gxx_write_reg(priv, 0x19, t);
} else {
lgs8gxx_write_reg(priv, 0x7D, detected_param);
if (priv->config->prod == LGS8GXX_PROD_LGS8913)
lgs8gxx_write_reg(priv, 0xC0, detected_param);
}
/* lgs8gxx_soft_reset(priv); */
/* Enter manual mode */
lgs8gxx_set_mode_manual(priv);
switch (gi) {
case GI_945:
priv->curr_gi = 945; break;
case GI_595:
priv->curr_gi = 595; break;
case GI_420:
priv->curr_gi = 420; break;
default:
priv->curr_gi = 945; break;
}
}
static int lgs8gxx_set_mpeg_mode(struct lgs8gxx_state *priv,
u8 serial, u8 clk_pol, u8 clk_gated)
{
int ret = 0;
u8 t, reg_addr;
reg_addr = (priv->config->prod == LGS8GXX_PROD_LGS8G75) ? 0x30 : 0xC2;
ret = lgs8gxx_read_reg(priv, reg_addr, &t);
if (ret != 0)
return ret;
t &= 0xF8;
t |= serial ? TS_SERIAL : TS_PARALLEL;
t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL;
t |= clk_gated ? TS_CLK_GATED : TS_CLK_FREERUN;
ret = lgs8gxx_write_reg(priv, reg_addr, t);
if (ret != 0)
return ret;
return 0;
}
/* A/D input peak-to-peak voltage range */
static int lgs8g75_set_adc_vpp(struct lgs8gxx_state *priv,
u8 sel)
{
u8 r26 = 0x73, r27 = 0x90;
if (priv->config->prod != LGS8GXX_PROD_LGS8G75)
return 0;
r26 |= (sel & 0x01) << 7;
r27 |= (sel & 0x02) >> 1;
lgs8gxx_write_reg(priv, 0x26, r26);
lgs8gxx_write_reg(priv, 0x27, r27);
return 0;
}
/* LGS8913 demod frontend functions */
static int lgs8913_init(struct lgs8gxx_state *priv)
{
u8 t;
/* LGS8913 specific */
lgs8gxx_write_reg(priv, 0xc1, 0x3);
lgs8gxx_read_reg(priv, 0x7c, &t);
lgs8gxx_write_reg(priv, 0x7c, (t&0x8c) | 0x3);
/* LGS8913 specific */
lgs8gxx_read_reg(priv, 0xc3, &t);
lgs8gxx_write_reg(priv, 0xc3, t&0x10);
return 0;
}
static int lgs8g75_init_data(struct lgs8gxx_state *priv)
{
const struct firmware *fw;
int rc;
int i;
rc = request_firmware(&fw, LGS8GXX_FIRMWARE, &priv->i2c->dev);
if (rc)
return rc;
lgs8gxx_write_reg(priv, 0xC6, 0x40);
lgs8gxx_write_reg(priv, 0x3D, 0x04);
lgs8gxx_write_reg(priv, 0x39, 0x00);
lgs8gxx_write_reg(priv, 0x3A, 0x00);
lgs8gxx_write_reg(priv, 0x38, 0x00);
lgs8gxx_write_reg(priv, 0x3B, 0x00);
lgs8gxx_write_reg(priv, 0x38, 0x00);
for (i = 0; i < fw->size; i++) {
lgs8gxx_write_reg(priv, 0x38, 0x00);
lgs8gxx_write_reg(priv, 0x3A, (u8)(i&0xff));
lgs8gxx_write_reg(priv, 0x3B, (u8)(i>>8));
lgs8gxx_write_reg(priv, 0x3C, fw->data[i]);
}
lgs8gxx_write_reg(priv, 0x38, 0x00);
release_firmware(fw);
return 0;
}
static int lgs8gxx_init(struct dvb_frontend *fe)
{
struct lgs8gxx_state *priv =
(struct lgs8gxx_state *)fe->demodulator_priv;
const struct lgs8gxx_config *config = priv->config;
u8 data = 0;
s8 err;
dprintk("%s\n", __func__);
lgs8gxx_read_reg(priv, 0, &data);
dprintk("reg 0 = 0x%02X\n", data);
if (config->prod == LGS8GXX_PROD_LGS8G75)
lgs8g75_set_adc_vpp(priv, config->adc_vpp);
/* Setup MPEG output format */
err = lgs8gxx_set_mpeg_mode(priv, config->serial_ts,
config->ts_clk_pol,
config->ts_clk_gated);
if (err != 0)
return -EIO;
if (config->prod == LGS8GXX_PROD_LGS8913)
lgs8913_init(priv);
lgs8gxx_set_if_freq(priv, priv->config->if_freq);
lgs8gxx_set_ad_mode(priv);
return 0;
}
static void lgs8gxx_release(struct dvb_frontend *fe)
{
struct lgs8gxx_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
kfree(state);
}
static int lgs8gxx_write(struct dvb_frontend *fe, const u8 buf[], int len)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return lgs8gxx_write_reg(priv, buf[0], buf[1]);
}
static int lgs8gxx_set_fe(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
struct lgs8gxx_state *priv = fe->demodulator_priv;
dprintk("%s\n", __func__);
/* set frequency */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* start auto lock */
lgs8gxx_auto_lock(priv);
msleep(10);
/* TODO: get real readings from device */
/* bandwidth */
fe_params->bandwidth_hz = 8000000;
fe_params->code_rate_HP = FEC_AUTO;
fe_params->code_rate_LP = FEC_AUTO;
fe_params->modulation = QAM_AUTO;
/* transmission mode */
fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
/* guard interval */
fe_params->guard_interval = GUARD_INTERVAL_AUTO;
/* hierarchy */
fe_params->hierarchy = HIERARCHY_NONE;
return 0;
}
static
int lgs8gxx_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
/* FIXME: copy from tda1004x.c */
fesettings->min_delay_ms = 800;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int lgs8gxx_read_status(struct dvb_frontend *fe,
enum fe_status *fe_status)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
s8 ret;
u8 t, locked = 0;
dprintk("%s\n", __func__);
*fe_status = 0;
lgs8gxx_get_afc_phase(priv);
lgs8gxx_is_locked(priv, &locked);
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
if (locked)
*fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
ret = lgs8gxx_read_reg(priv, 0x4B, &t);
if (ret != 0)
return -EIO;
dprintk("Reg 0x4B: 0x%02X\n", t);
*fe_status = 0;
if (priv->config->prod == LGS8GXX_PROD_LGS8913) {
if ((t & 0x40) == 0x40)
*fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
if ((t & 0x80) == 0x80)
*fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
} else {
if ((t & 0x80) == 0x80)
*fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
}
/* success */
dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
return 0;
}
static int lgs8gxx_read_signal_agc(struct lgs8gxx_state *priv, u16 *signal)
{
u16 v;
u8 agc_lvl[2], cat;
dprintk("%s()\n", __func__);
lgs8gxx_read_reg(priv, 0x3F, &agc_lvl[0]);
lgs8gxx_read_reg(priv, 0x3E, &agc_lvl[1]);
v = agc_lvl[0];
v <<= 8;
v |= agc_lvl[1];
dprintk("agc_lvl: 0x%04X\n", v);
if (v < 0x100)
cat = 0;
else if (v < 0x190)
cat = 5;
else if (v < 0x2A8)
cat = 4;
else if (v < 0x381)
cat = 3;
else if (v < 0x400)
cat = 2;
else if (v == 0x400)
cat = 1;
else
cat = 0;
*signal = cat * 65535 / 5;
return 0;
}
static int lgs8913_read_signal_strength(struct lgs8gxx_state *priv, u16 *signal)
{
u8 t; s8 ret;
s16 max_strength = 0;
u8 str;
u16 i, gi = priv->curr_gi;
dprintk("%s\n", __func__);
ret = lgs8gxx_read_reg(priv, 0x4B, &t);
if (ret != 0)
return -EIO;
if (fake_signal_str) {
if ((t & 0xC0) == 0xC0) {
dprintk("Fake signal strength\n");
*signal = 0x7FFF;
} else
*signal = 0;
return 0;
}
dprintk("gi = %d\n", gi);
for (i = 0; i < gi; i++) {
if ((i & 0xFF) == 0)
lgs8gxx_write_reg(priv, 0x84, 0x03 & (i >> 8));
lgs8gxx_write_reg(priv, 0x83, i & 0xFF);
lgs8gxx_read_reg(priv, 0x94, &str);
if (max_strength < str)
max_strength = str;
}
*signal = max_strength;
dprintk("%s: signal=0x%02X\n", __func__, *signal);
lgs8gxx_read_reg(priv, 0x95, &t);
dprintk("%s: AVG Noise=0x%02X\n", __func__, t);
return 0;
}
static int lgs8g75_read_signal_strength(struct lgs8gxx_state *priv, u16 *signal)
{
u8 t;
s16 v = 0;
dprintk("%s\n", __func__);
lgs8gxx_read_reg(priv, 0xB1, &t);
v |= t;
v <<= 8;
lgs8gxx_read_reg(priv, 0xB0, &t);
v |= t;
*signal = v;
dprintk("%s: signal=0x%02X\n", __func__, *signal);
return 0;
}
static int lgs8gxx_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
if (priv->config->prod == LGS8GXX_PROD_LGS8913)
return lgs8913_read_signal_strength(priv, signal);
else if (priv->config->prod == LGS8GXX_PROD_LGS8G75)
return lgs8g75_read_signal_strength(priv, signal);
else
return lgs8gxx_read_signal_agc(priv, signal);
}
static int lgs8gxx_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
u8 t;
*snr = 0;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75)
lgs8gxx_read_reg(priv, 0x34, &t);
else
lgs8gxx_read_reg(priv, 0x95, &t);
dprintk("AVG Noise=0x%02X\n", t);
*snr = 256 - t;
*snr <<= 8;
dprintk("snr=0x%x\n", *snr);
return 0;
}
static int lgs8gxx_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
*ucblocks = 0;
dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
return 0;
}
static void packet_counter_start(struct lgs8gxx_state *priv)
{
u8 orig, t;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_read_reg(priv, 0x30, &orig);
orig &= 0xE7;
t = orig | 0x10;
lgs8gxx_write_reg(priv, 0x30, t);
t = orig | 0x18;
lgs8gxx_write_reg(priv, 0x30, t);
t = orig | 0x10;
lgs8gxx_write_reg(priv, 0x30, t);
} else {
lgs8gxx_write_reg(priv, 0xC6, 0x01);
lgs8gxx_write_reg(priv, 0xC6, 0x41);
lgs8gxx_write_reg(priv, 0xC6, 0x01);
}
}
static void packet_counter_stop(struct lgs8gxx_state *priv)
{
u8 t;
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
lgs8gxx_read_reg(priv, 0x30, &t);
t &= 0xE7;
lgs8gxx_write_reg(priv, 0x30, t);
} else {
lgs8gxx_write_reg(priv, 0xC6, 0x81);
}
}
static int lgs8gxx_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
u8 reg_err, reg_total, t;
u32 total_cnt = 0, err_cnt = 0;
int i;
dprintk("%s\n", __func__);
packet_counter_start(priv);
msleep(200);
packet_counter_stop(priv);
if (priv->config->prod == LGS8GXX_PROD_LGS8G75) {
reg_total = 0x28; reg_err = 0x2C;
} else {
reg_total = 0xD0; reg_err = 0xD4;
}
for (i = 0; i < 4; i++) {
total_cnt <<= 8;
lgs8gxx_read_reg(priv, reg_total+3-i, &t);
total_cnt |= t;
}
for (i = 0; i < 4; i++) {
err_cnt <<= 8;
lgs8gxx_read_reg(priv, reg_err+3-i, &t);
err_cnt |= t;
}
dprintk("error=%d total=%d\n", err_cnt, total_cnt);
if (total_cnt == 0)
*ber = 0;
else
*ber = err_cnt * 100 / total_cnt;
dprintk("%s: ber=0x%x\n", __func__, *ber);
return 0;
}
static int lgs8gxx_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct lgs8gxx_state *priv = fe->demodulator_priv;
if (priv->config->tuner_address == 0)
return 0;
if (enable) {
u8 v = 0x80 | priv->config->tuner_address;
return lgs8gxx_write_reg(priv, 0x01, v);
}
return lgs8gxx_write_reg(priv, 0x01, 0);
}
static const struct dvb_frontend_ops lgs8gxx_ops = {
.delsys = { SYS_DTMB },
.info = {
.name = "Legend Silicon LGS8913/LGS8GXX DMB-TH",
.frequency_min_hz = 474 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 10 * kHz,
.caps =
FE_CAN_FEC_AUTO |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO
},
.release = lgs8gxx_release,
.init = lgs8gxx_init,
.write = lgs8gxx_write,
.i2c_gate_ctrl = lgs8gxx_i2c_gate_ctrl,
.set_frontend = lgs8gxx_set_fe,
.get_tune_settings = lgs8gxx_get_tune_settings,
.read_status = lgs8gxx_read_status,
.read_ber = lgs8gxx_read_ber,
.read_signal_strength = lgs8gxx_read_signal_strength,
.read_snr = lgs8gxx_read_snr,
.read_ucblocks = lgs8gxx_read_ucblocks,
};
struct dvb_frontend *lgs8gxx_attach(const struct lgs8gxx_config *config,
struct i2c_adapter *i2c)
{
struct lgs8gxx_state *priv = NULL;
u8 data = 0;
dprintk("%s()\n", __func__);
if (config == NULL || i2c == NULL)
return NULL;
priv = kzalloc(sizeof(struct lgs8gxx_state), GFP_KERNEL);
if (priv == NULL)
goto error_out;
priv->config = config;
priv->i2c = i2c;
/* check if the demod is there */
if (lgs8gxx_read_reg(priv, 0, &data) != 0) {
dprintk("%s lgs8gxx not found at i2c addr 0x%02X\n",
__func__, priv->config->demod_address);
goto error_out;
}
lgs8gxx_read_reg(priv, 1, &data);
memcpy(&priv->frontend.ops, &lgs8gxx_ops,
sizeof(struct dvb_frontend_ops));
priv->frontend.demodulator_priv = priv;
if (config->prod == LGS8GXX_PROD_LGS8G75)
lgs8g75_init_data(priv);
return &priv->frontend;
error_out:
dprintk("%s() error_out\n", __func__);
kfree(priv);
return NULL;
}
EXPORT_SYMBOL_GPL(lgs8gxx_attach);
MODULE_DESCRIPTION("Legend Silicon LGS8913/LGS8GXX DMB-TH demodulator driver");
MODULE_AUTHOR("David T. L. Wong <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(LGS8GXX_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/lgs8gxx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
NXP TDA10048HN DVB OFDM demodulator driver
Copyright (C) 2009 Steven Toth <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/math64.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include <linux/int_log.h>
#include "tda10048.h"
#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
/* Register name definitions */
#define TDA10048_IDENTITY 0x00
#define TDA10048_VERSION 0x01
#define TDA10048_DSP_CODE_CPT 0x0C
#define TDA10048_DSP_CODE_IN 0x0E
#define TDA10048_IN_CONF1 0x10
#define TDA10048_IN_CONF2 0x11
#define TDA10048_IN_CONF3 0x12
#define TDA10048_OUT_CONF1 0x14
#define TDA10048_OUT_CONF2 0x15
#define TDA10048_OUT_CONF3 0x16
#define TDA10048_AUTO 0x18
#define TDA10048_SYNC_STATUS 0x1A
#define TDA10048_CONF_C4_1 0x1E
#define TDA10048_CONF_C4_2 0x1F
#define TDA10048_CODE_IN_RAM 0x20
#define TDA10048_CHANNEL_INFO1_R 0x22
#define TDA10048_CHANNEL_INFO2_R 0x23
#define TDA10048_CHANNEL_INFO1 0x24
#define TDA10048_CHANNEL_INFO2 0x25
#define TDA10048_TIME_ERROR_R 0x26
#define TDA10048_TIME_ERROR 0x27
#define TDA10048_FREQ_ERROR_LSB_R 0x28
#define TDA10048_FREQ_ERROR_MSB_R 0x29
#define TDA10048_FREQ_ERROR_LSB 0x2A
#define TDA10048_FREQ_ERROR_MSB 0x2B
#define TDA10048_IT_SEL 0x30
#define TDA10048_IT_STAT 0x32
#define TDA10048_DSP_AD_LSB 0x3C
#define TDA10048_DSP_AD_MSB 0x3D
#define TDA10048_DSP_REG_LSB 0x3E
#define TDA10048_DSP_REG_MSB 0x3F
#define TDA10048_CONF_TRISTATE1 0x44
#define TDA10048_CONF_TRISTATE2 0x45
#define TDA10048_CONF_POLARITY 0x46
#define TDA10048_GPIO_SP_DS0 0x48
#define TDA10048_GPIO_SP_DS1 0x49
#define TDA10048_GPIO_SP_DS2 0x4A
#define TDA10048_GPIO_SP_DS3 0x4B
#define TDA10048_GPIO_OUT_SEL 0x4C
#define TDA10048_GPIO_SELECT 0x4D
#define TDA10048_IC_MODE 0x4E
#define TDA10048_CONF_XO 0x50
#define TDA10048_CONF_PLL1 0x51
#define TDA10048_CONF_PLL2 0x52
#define TDA10048_CONF_PLL3 0x53
#define TDA10048_CONF_ADC 0x54
#define TDA10048_CONF_ADC_2 0x55
#define TDA10048_CONF_C1_1 0x60
#define TDA10048_CONF_C1_3 0x62
#define TDA10048_AGC_CONF 0x70
#define TDA10048_AGC_THRESHOLD_LSB 0x72
#define TDA10048_AGC_THRESHOLD_MSB 0x73
#define TDA10048_AGC_RENORM 0x74
#define TDA10048_AGC_GAINS 0x76
#define TDA10048_AGC_TUN_MIN 0x78
#define TDA10048_AGC_TUN_MAX 0x79
#define TDA10048_AGC_IF_MIN 0x7A
#define TDA10048_AGC_IF_MAX 0x7B
#define TDA10048_AGC_TUN_LEVEL 0x7E
#define TDA10048_AGC_IF_LEVEL 0x7F
#define TDA10048_DIG_AGC_LEVEL 0x81
#define TDA10048_FREQ_PHY2_LSB 0x86
#define TDA10048_FREQ_PHY2_MSB 0x87
#define TDA10048_TIME_INVWREF_LSB 0x88
#define TDA10048_TIME_INVWREF_MSB 0x89
#define TDA10048_TIME_WREF_LSB 0x8A
#define TDA10048_TIME_WREF_MID1 0x8B
#define TDA10048_TIME_WREF_MID2 0x8C
#define TDA10048_TIME_WREF_MSB 0x8D
#define TDA10048_NP_OUT 0xA2
#define TDA10048_CELL_ID_LSB 0xA4
#define TDA10048_CELL_ID_MSB 0xA5
#define TDA10048_EXTTPS_ODD 0xAA
#define TDA10048_EXTTPS_EVEN 0xAB
#define TDA10048_TPS_LENGTH 0xAC
#define TDA10048_FREE_REG_1 0xB2
#define TDA10048_FREE_REG_2 0xB3
#define TDA10048_CONF_C3_1 0xC0
#define TDA10048_CVBER_CTRL 0xC2
#define TDA10048_CBER_NMAX_LSB 0xC4
#define TDA10048_CBER_NMAX_MSB 0xC5
#define TDA10048_CBER_LSB 0xC6
#define TDA10048_CBER_MSB 0xC7
#define TDA10048_VBER_LSB 0xC8
#define TDA10048_VBER_MID 0xC9
#define TDA10048_VBER_MSB 0xCA
#define TDA10048_CVBER_LUT 0xCC
#define TDA10048_UNCOR_CTRL 0xCD
#define TDA10048_UNCOR_CPT_LSB 0xCE
#define TDA10048_UNCOR_CPT_MSB 0xCF
#define TDA10048_SOFT_IT_C3 0xD6
#define TDA10048_CONF_TS2 0xE0
#define TDA10048_CONF_TS1 0xE1
static unsigned int debug;
#define dprintk(level, fmt, arg...)\
do { if (debug >= level)\
printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
} while (0)
struct tda10048_state {
struct i2c_adapter *i2c;
/* We'll cache and update the attach config settings */
struct tda10048_config config;
struct dvb_frontend frontend;
int fwloaded;
u32 freq_if_hz;
u32 xtal_hz;
u32 pll_mfactor;
u32 pll_nfactor;
u32 pll_pfactor;
u32 sample_freq;
u32 bandwidth;
};
static struct init_tab {
u8 reg;
u16 data;
} init_tab[] = {
{ TDA10048_CONF_PLL1, 0x08 },
{ TDA10048_CONF_ADC_2, 0x00 },
{ TDA10048_CONF_C4_1, 0x00 },
{ TDA10048_CONF_PLL1, 0x0f },
{ TDA10048_CONF_PLL2, 0x0a },
{ TDA10048_CONF_PLL3, 0x43 },
{ TDA10048_FREQ_PHY2_LSB, 0x02 },
{ TDA10048_FREQ_PHY2_MSB, 0x0a },
{ TDA10048_TIME_WREF_LSB, 0xbd },
{ TDA10048_TIME_WREF_MID1, 0xe4 },
{ TDA10048_TIME_WREF_MID2, 0xa8 },
{ TDA10048_TIME_WREF_MSB, 0x02 },
{ TDA10048_TIME_INVWREF_LSB, 0x04 },
{ TDA10048_TIME_INVWREF_MSB, 0x06 },
{ TDA10048_CONF_C4_1, 0x00 },
{ TDA10048_CONF_C1_1, 0xa8 },
{ TDA10048_AGC_CONF, 0x16 },
{ TDA10048_CONF_C1_3, 0x0b },
{ TDA10048_AGC_TUN_MIN, 0x00 },
{ TDA10048_AGC_TUN_MAX, 0xff },
{ TDA10048_AGC_IF_MIN, 0x00 },
{ TDA10048_AGC_IF_MAX, 0xff },
{ TDA10048_AGC_THRESHOLD_MSB, 0x00 },
{ TDA10048_AGC_THRESHOLD_LSB, 0x70 },
{ TDA10048_CVBER_CTRL, 0x38 },
{ TDA10048_AGC_GAINS, 0x12 },
{ TDA10048_CONF_XO, 0x00 },
{ TDA10048_CONF_TS1, 0x07 },
{ TDA10048_IC_MODE, 0x00 },
{ TDA10048_CONF_TS2, 0xc0 },
{ TDA10048_CONF_TRISTATE1, 0x21 },
{ TDA10048_CONF_TRISTATE2, 0x00 },
{ TDA10048_CONF_POLARITY, 0x00 },
{ TDA10048_CONF_C4_2, 0x04 },
{ TDA10048_CONF_ADC, 0x60 },
{ TDA10048_CONF_ADC_2, 0x10 },
{ TDA10048_CONF_ADC, 0x60 },
{ TDA10048_CONF_ADC_2, 0x00 },
{ TDA10048_CONF_C1_1, 0xa8 },
{ TDA10048_UNCOR_CTRL, 0x00 },
{ TDA10048_CONF_C4_2, 0x04 },
};
static struct pll_tab {
u32 clk_freq_khz;
u32 if_freq_khz;
} pll_tab[] = {
{ TDA10048_CLK_4000, TDA10048_IF_36130 },
{ TDA10048_CLK_16000, TDA10048_IF_3300 },
{ TDA10048_CLK_16000, TDA10048_IF_3500 },
{ TDA10048_CLK_16000, TDA10048_IF_3800 },
{ TDA10048_CLK_16000, TDA10048_IF_4000 },
{ TDA10048_CLK_16000, TDA10048_IF_4300 },
{ TDA10048_CLK_16000, TDA10048_IF_4500 },
{ TDA10048_CLK_16000, TDA10048_IF_5000 },
{ TDA10048_CLK_16000, TDA10048_IF_36130 },
};
static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
{
struct tda10048_config *config = &state->config;
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = config->demod_address,
.flags = 0, .buf = buf, .len = 2 };
dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk("%s: writereg error (ret == %i)\n", __func__, ret);
return (ret != 1) ? -1 : 0;
}
static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
{
struct tda10048_config *config = &state->config;
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = config->demod_address,
.flags = 0, .buf = b0, .len = 1 },
{ .addr = config->demod_address,
.flags = I2C_M_RD, .buf = b1, .len = 1 } };
dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk(KERN_ERR "%s: readreg error (ret == %i)\n",
__func__, ret);
return b1[0];
}
static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
const u8 *data, u16 len)
{
struct tda10048_config *config = &state->config;
int ret = -EREMOTEIO;
struct i2c_msg msg;
u8 *buf;
dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
buf = kmalloc(len + 1, GFP_KERNEL);
if (buf == NULL) {
ret = -ENOMEM;
goto error;
}
*buf = reg;
memcpy(buf + 1, data, len);
msg.addr = config->demod_address;
msg.flags = 0;
msg.buf = buf;
msg.len = len + 1;
dprintk(2, "%s(): write len = %d\n",
__func__, msg.len);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
printk(KERN_ERR "%s(): writereg error err %i\n",
__func__, ret);
ret = -EREMOTEIO;
}
error:
kfree(buf);
return ret;
}
static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
u32 if_hz)
{
struct tda10048_state *state = fe->demodulator_priv;
u64 t;
dprintk(1, "%s()\n", __func__);
if (sample_freq_hz == 0)
return -EINVAL;
if (if_hz < (sample_freq_hz / 2)) {
/* PHY2 = (if2/fs) * 2^15 */
t = if_hz;
t *= 10;
t *= 32768;
do_div(t, sample_freq_hz);
t += 5;
do_div(t, 10);
} else {
/* PHY2 = ((IF1-fs)/fs) * 2^15 */
t = sample_freq_hz - if_hz;
t *= 10;
t *= 32768;
do_div(t, sample_freq_hz);
t += 5;
do_div(t, 10);
t = ~t + 1;
}
tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
return 0;
}
static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
u32 bw)
{
struct tda10048_state *state = fe->demodulator_priv;
u64 t, z;
dprintk(1, "%s()\n", __func__);
if (sample_freq_hz == 0)
return -EINVAL;
/* WREF = (B / (7 * fs)) * 2^31 */
t = bw * 10;
/* avoid warning: this decimal constant is unsigned only in ISO C90 */
/* t *= 2147483648 on 32bit platforms */
t *= (2048 * 1024);
t *= 1024;
z = 7 * sample_freq_hz;
do_div(t, z);
t += 5;
do_div(t, 10);
tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
return 0;
}
static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
u32 bw)
{
struct tda10048_state *state = fe->demodulator_priv;
u64 t;
dprintk(1, "%s()\n", __func__);
if (sample_freq_hz == 0)
return -EINVAL;
/* INVWREF = ((7 * fs) / B) * 2^5 */
t = sample_freq_hz;
t *= 7;
t *= 32;
t *= 10;
do_div(t, bw);
t += 5;
do_div(t, 10);
tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
return 0;
}
static int tda10048_set_bandwidth(struct dvb_frontend *fe,
u32 bw)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s(bw=%d)\n", __func__, bw);
/* Bandwidth setting may need to be adjusted */
switch (bw) {
case 6000000:
case 7000000:
case 8000000:
tda10048_set_wref(fe, state->sample_freq, bw);
tda10048_set_invwref(fe, state->sample_freq, bw);
break;
default:
printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
return -EINVAL;
}
state->bandwidth = bw;
return 0;
}
static int tda10048_set_if(struct dvb_frontend *fe, u32 bw)
{
struct tda10048_state *state = fe->demodulator_priv;
struct tda10048_config *config = &state->config;
int i;
u32 if_freq_khz;
dprintk(1, "%s(bw = %d)\n", __func__, bw);
/* based on target bandwidth and clk we calculate pll factors */
switch (bw) {
case 6000000:
if_freq_khz = config->dtv6_if_freq_khz;
break;
case 7000000:
if_freq_khz = config->dtv7_if_freq_khz;
break;
case 8000000:
if_freq_khz = config->dtv8_if_freq_khz;
break;
default:
printk(KERN_ERR "%s() no default\n", __func__);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
(pll_tab[i].if_freq_khz == if_freq_khz)) {
state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
break;
}
}
if (i == ARRAY_SIZE(pll_tab)) {
printk(KERN_ERR "%s() Incorrect attach settings\n",
__func__);
return -EINVAL;
}
dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
/* Calculate the sample frequency */
state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
state->sample_freq /= (state->pll_nfactor + 1);
state->sample_freq /= (state->pll_pfactor + 4);
dprintk(1, "- sample_freq = %d\n", state->sample_freq);
/* Update the I/F */
tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
return 0;
}
static int tda10048_firmware_upload(struct dvb_frontend *fe)
{
struct tda10048_state *state = fe->demodulator_priv;
struct tda10048_config *config = &state->config;
const struct firmware *fw;
int ret;
int pos = 0;
int cnt;
u8 wlen = config->fwbulkwritelen;
if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
wlen = TDA10048_BULKWRITE_200;
/* request the firmware, this will block and timeout */
printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
__func__,
TDA10048_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
state->i2c->dev.parent);
if (ret) {
printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
__func__);
return -EIO;
} else {
printk(KERN_INFO "%s: firmware read %zu bytes.\n",
__func__,
fw->size);
ret = 0;
}
if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
ret = -EIO;
} else {
printk(KERN_INFO "%s: firmware uploading\n", __func__);
/* Soft reset */
tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
& 0xfe);
tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
| 0x01);
/* Put the demod into host download mode */
tda10048_writereg(state, TDA10048_CONF_C4_1,
tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
/* Boot the DSP */
tda10048_writereg(state, TDA10048_CONF_C4_1,
tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
/* Prepare for download */
tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
/* Download the firmware payload */
while (pos < fw->size) {
if ((fw->size - pos) > wlen)
cnt = wlen;
else
cnt = fw->size - pos;
tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
&fw->data[pos], cnt);
pos += cnt;
}
ret = -EIO;
/* Wait up to 250ms for the DSP to boot */
for (cnt = 0; cnt < 250 ; cnt += 10) {
msleep(10);
if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
& 0x40) {
ret = 0;
break;
}
}
}
release_firmware(fw);
if (ret == 0) {
printk(KERN_INFO "%s: firmware uploaded\n", __func__);
state->fwloaded = 1;
} else
printk(KERN_ERR "%s: firmware upload failed\n", __func__);
return ret;
}
static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s(%d)\n", __func__, inversion);
if (inversion == TDA10048_INVERSION_ON)
tda10048_writereg(state, TDA10048_CONF_C1_1,
tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
else
tda10048_writereg(state, TDA10048_CONF_C1_1,
tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
return 0;
}
/* Retrieve the demod settings */
static int tda10048_get_tps(struct tda10048_state *state,
struct dtv_frontend_properties *p)
{
u8 val;
/* Make sure the TPS regs are valid */
if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
return -EAGAIN;
val = tda10048_readreg(state, TDA10048_OUT_CONF2);
switch ((val & 0x60) >> 5) {
case 0:
p->modulation = QPSK;
break;
case 1:
p->modulation = QAM_16;
break;
case 2:
p->modulation = QAM_64;
break;
}
switch ((val & 0x18) >> 3) {
case 0:
p->hierarchy = HIERARCHY_NONE;
break;
case 1:
p->hierarchy = HIERARCHY_1;
break;
case 2:
p->hierarchy = HIERARCHY_2;
break;
case 3:
p->hierarchy = HIERARCHY_4;
break;
}
switch (val & 0x07) {
case 0:
p->code_rate_HP = FEC_1_2;
break;
case 1:
p->code_rate_HP = FEC_2_3;
break;
case 2:
p->code_rate_HP = FEC_3_4;
break;
case 3:
p->code_rate_HP = FEC_5_6;
break;
case 4:
p->code_rate_HP = FEC_7_8;
break;
}
val = tda10048_readreg(state, TDA10048_OUT_CONF3);
switch (val & 0x07) {
case 0:
p->code_rate_LP = FEC_1_2;
break;
case 1:
p->code_rate_LP = FEC_2_3;
break;
case 2:
p->code_rate_LP = FEC_3_4;
break;
case 3:
p->code_rate_LP = FEC_5_6;
break;
case 4:
p->code_rate_LP = FEC_7_8;
break;
}
val = tda10048_readreg(state, TDA10048_OUT_CONF1);
switch ((val & 0x0c) >> 2) {
case 0:
p->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
p->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
p->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
p->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch (val & 0x03) {
case 0:
p->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
p->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
return 0;
}
static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct tda10048_state *state = fe->demodulator_priv;
struct tda10048_config *config = &state->config;
dprintk(1, "%s(%d)\n", __func__, enable);
if (config->disable_gate_access)
return 0;
if (enable)
return tda10048_writereg(state, TDA10048_CONF_C4_1,
tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
else
return tda10048_writereg(state, TDA10048_CONF_C4_1,
tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
}
static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s(%d)\n", __func__, serial);
/* Ensure pins are out of tri-state */
tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
if (serial) {
tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
} else {
tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
}
return 0;
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
/* TODO: Support manual tuning with specific params */
static int tda10048_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
/* Update the I/F pll's if the bandwidth changes */
if (p->bandwidth_hz != state->bandwidth) {
tda10048_set_if(fe, p->bandwidth_hz);
tda10048_set_bandwidth(fe, p->bandwidth_hz);
}
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Enable demod TPS auto detection and begin acquisition */
tda10048_writereg(state, TDA10048_AUTO, 0x57);
/* trigger cber and vber acquisition */
tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B);
return 0;
}
/* Establish sane defaults and load firmware. */
static int tda10048_init(struct dvb_frontend *fe)
{
struct tda10048_state *state = fe->demodulator_priv;
struct tda10048_config *config = &state->config;
int ret = 0, i;
dprintk(1, "%s()\n", __func__);
/* PLL */
init_tab[4].data = (u8)(state->pll_mfactor);
init_tab[5].data = (u8)(state->pll_nfactor) | 0x40;
/* Apply register defaults */
for (i = 0; i < ARRAY_SIZE(init_tab); i++)
tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
if (state->fwloaded == 0)
ret = tda10048_firmware_upload(fe);
/* Set either serial or parallel */
tda10048_output_mode(fe, config->output_mode);
/* Set inversion */
tda10048_set_inversion(fe, config->inversion);
/* Establish default RF values */
tda10048_set_if(fe, 8000000);
tda10048_set_bandwidth(fe, 8000000);
/* Ensure we leave the gate closed */
tda10048_i2c_gate_ctrl(fe, 0);
return ret;
}
static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct tda10048_state *state = fe->demodulator_priv;
u8 reg;
*status = 0;
reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
dprintk(1, "%s() status =0x%02x\n", __func__, reg);
if (reg & 0x02)
*status |= FE_HAS_CARRIER;
if (reg & 0x04)
*status |= FE_HAS_SIGNAL;
if (reg & 0x08) {
*status |= FE_HAS_LOCK;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
}
return 0;
}
static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct tda10048_state *state = fe->demodulator_priv;
static u32 cber_current;
u32 cber_nmax;
u64 cber_tmp;
dprintk(1, "%s()\n", __func__);
/* update cber on interrupt */
if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) {
cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
tda10048_readreg(state, TDA10048_CBER_LSB);
cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 |
tda10048_readreg(state, TDA10048_CBER_NMAX_LSB);
cber_tmp *= 100000000;
cber_tmp *= 2;
cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1);
cber_current = (u32)cber_tmp;
/* retrigger cber acquisition */
tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39);
}
/* actual cber is (*ber)/1e8 */
*ber = cber_current;
return 0;
}
static int tda10048_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct tda10048_state *state = fe->demodulator_priv;
u8 v;
dprintk(1, "%s()\n", __func__);
*signal_strength = 65535;
v = tda10048_readreg(state, TDA10048_NP_OUT);
if (v > 0)
*signal_strength -= (v << 8) | v;
return 0;
}
/* SNR lookup table */
static struct snr_tab {
u8 val;
u8 data;
} snr_tab[] = {
{ 0, 0 },
{ 1, 246 },
{ 2, 215 },
{ 3, 198 },
{ 4, 185 },
{ 5, 176 },
{ 6, 168 },
{ 7, 161 },
{ 8, 155 },
{ 9, 150 },
{ 10, 146 },
{ 11, 141 },
{ 12, 138 },
{ 13, 134 },
{ 14, 131 },
{ 15, 128 },
{ 16, 125 },
{ 17, 122 },
{ 18, 120 },
{ 19, 118 },
{ 20, 115 },
{ 21, 113 },
{ 22, 111 },
{ 23, 109 },
{ 24, 107 },
{ 25, 106 },
{ 26, 104 },
{ 27, 102 },
{ 28, 101 },
{ 29, 99 },
{ 30, 98 },
{ 31, 96 },
{ 32, 95 },
{ 33, 94 },
{ 34, 92 },
{ 35, 91 },
{ 36, 90 },
{ 37, 89 },
{ 38, 88 },
{ 39, 86 },
{ 40, 85 },
{ 41, 84 },
{ 42, 83 },
{ 43, 82 },
{ 44, 81 },
{ 45, 80 },
{ 46, 79 },
{ 47, 78 },
{ 48, 77 },
{ 49, 76 },
{ 50, 76 },
{ 51, 75 },
{ 52, 74 },
{ 53, 73 },
{ 54, 72 },
{ 56, 71 },
{ 57, 70 },
{ 58, 69 },
{ 60, 68 },
{ 61, 67 },
{ 63, 66 },
{ 64, 65 },
{ 66, 64 },
{ 67, 63 },
{ 68, 62 },
{ 69, 62 },
{ 70, 61 },
{ 72, 60 },
{ 74, 59 },
{ 75, 58 },
{ 77, 57 },
{ 79, 56 },
{ 81, 55 },
{ 83, 54 },
{ 85, 53 },
{ 87, 52 },
{ 89, 51 },
{ 91, 50 },
{ 93, 49 },
{ 95, 48 },
{ 97, 47 },
{ 100, 46 },
{ 102, 45 },
{ 104, 44 },
{ 107, 43 },
{ 109, 42 },
{ 112, 41 },
{ 114, 40 },
{ 117, 39 },
{ 120, 38 },
{ 123, 37 },
{ 125, 36 },
{ 128, 35 },
{ 131, 34 },
{ 134, 33 },
{ 138, 32 },
{ 141, 31 },
{ 144, 30 },
{ 147, 29 },
{ 151, 28 },
{ 154, 27 },
{ 158, 26 },
{ 162, 25 },
{ 165, 24 },
{ 169, 23 },
{ 173, 22 },
{ 177, 21 },
{ 181, 20 },
{ 186, 19 },
{ 190, 18 },
{ 194, 17 },
{ 199, 16 },
{ 204, 15 },
{ 208, 14 },
{ 213, 13 },
{ 218, 12 },
{ 223, 11 },
{ 229, 10 },
{ 234, 9 },
{ 239, 8 },
{ 245, 7 },
{ 251, 6 },
{ 255, 5 },
};
static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct tda10048_state *state = fe->demodulator_priv;
u8 v;
int i, ret = -EINVAL;
dprintk(1, "%s()\n", __func__);
v = tda10048_readreg(state, TDA10048_NP_OUT);
for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
if (v <= snr_tab[i].val) {
*snr = snr_tab[i].data;
ret = 0;
break;
}
}
return ret;
}
static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s()\n", __func__);
*ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
/* clear the uncorrected TS packets counter when saturated */
if (*ucblocks == 0xFFFF)
tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
return 0;
}
static int tda10048_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s()\n", __func__);
p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
& 0x20 ? INVERSION_ON : INVERSION_OFF;
return tda10048_get_tps(state, p);
}
static int tda10048_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void tda10048_release(struct dvb_frontend *fe)
{
struct tda10048_state *state = fe->demodulator_priv;
dprintk(1, "%s()\n", __func__);
kfree(state);
}
static void tda10048_establish_defaults(struct dvb_frontend *fe)
{
struct tda10048_state *state = fe->demodulator_priv;
struct tda10048_config *config = &state->config;
/* Validate/default the config */
if (config->dtv6_if_freq_khz == 0) {
config->dtv6_if_freq_khz = TDA10048_IF_4300;
printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n",
__func__,
config->dtv6_if_freq_khz);
}
if (config->dtv7_if_freq_khz == 0) {
config->dtv7_if_freq_khz = TDA10048_IF_4300;
printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n",
__func__,
config->dtv7_if_freq_khz);
}
if (config->dtv8_if_freq_khz == 0) {
config->dtv8_if_freq_khz = TDA10048_IF_4300;
printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n",
__func__,
config->dtv8_if_freq_khz);
}
if (config->clk_freq_khz == 0) {
config->clk_freq_khz = TDA10048_CLK_16000;
printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n",
__func__,
config->clk_freq_khz);
}
}
static const struct dvb_frontend_ops tda10048_ops;
struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
struct i2c_adapter *i2c)
{
struct tda10048_state *state = NULL;
dprintk(1, "%s()\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state and clone the config */
memcpy(&state->config, config, sizeof(*config));
state->i2c = i2c;
state->fwloaded = config->no_firmware;
state->bandwidth = 8000000;
/* check if the demod is present */
if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10048_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* set pll */
if (config->set_pll) {
state->pll_mfactor = config->pll_m;
state->pll_nfactor = config->pll_n;
state->pll_pfactor = config->pll_p;
} else {
state->pll_mfactor = 10;
state->pll_nfactor = 3;
state->pll_pfactor = 0;
}
/* Establish any defaults the user didn't pass */
tda10048_establish_defaults(&state->frontend);
/* Set the xtal and freq defaults */
if (tda10048_set_if(&state->frontend, 8000000) != 0)
goto error;
/* Default bandwidth */
if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0)
goto error;
/* Leave the gate closed */
tda10048_i2c_gate_ctrl(&state->frontend, 0);
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(tda10048_attach);
static const struct dvb_frontend_ops tda10048_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "NXP TDA10048HN DVB-T",
.frequency_min_hz = 177 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
},
.release = tda10048_release,
.init = tda10048_init,
.i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
.set_frontend = tda10048_set_frontend,
.get_frontend = tda10048_get_frontend,
.get_tune_settings = tda10048_get_tune_settings,
.read_status = tda10048_read_status,
.read_ber = tda10048_read_ber,
.read_signal_strength = tda10048_read_signal_strength,
.read_snr = tda10048_read_snr,
.read_ucblocks = tda10048_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tda10048.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
TDA10023 - DVB-C decoder
(as used in Philips CU1216-3 NIM and the Reelbox DVB-C tuner card)
Copyright (C) 2005 Georg Acher, BayCom GmbH (acher at baycom dot de)
Copyright (c) 2006 Hartmut Birr (e9hack at gmail dot com)
Remotely based on tda10021.c
Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]>
Copyright (C) 2004 Markus Schulz <[email protected]>
Support for TDA10021
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "tda1002x.h"
#define REG0_INIT_VAL 0x23
struct tda10023_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct tda10023_config *config;
struct dvb_frontend frontend;
u8 pwm;
u8 reg0;
/* clock settings */
u32 xtal;
u8 pll_m;
u8 pll_p;
u8 pll_n;
u32 sysclk;
};
#define dprintk(x...)
static int verbose;
static u8 tda10023_readreg (struct tda10023_state* state, u8 reg)
{
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
int ret;
ret = i2c_transfer (state->i2c, msg, 2);
if (ret != 2) {
int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
printk(KERN_ERR "DVB: TDA10023(%d): %s: readreg error (reg == 0x%02x, ret == %i)\n",
num, __func__, reg, ret);
}
return b1[0];
}
static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int ret;
ret = i2c_transfer (state->i2c, &msg, 1);
if (ret != 1) {
int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
printk(KERN_ERR "DVB: TDA10023(%d): %s, writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
num, __func__, reg, data, ret);
}
return (ret != 1) ? -EREMOTEIO : 0;
}
static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data)
{
if (mask==0xff)
return tda10023_writereg(state, reg, data);
else {
u8 val;
val=tda10023_readreg(state,reg);
val&=~mask;
val|=(data&mask);
return tda10023_writereg(state, reg, val);
}
}
static void tda10023_writetab(struct tda10023_state* state, u8* tab)
{
u8 r,m,v;
while (1) {
r=*tab++;
m=*tab++;
v=*tab++;
if (r==0xff) {
if (m==0xff)
break;
else
msleep(m);
}
else
tda10023_writebit(state,r,m,v);
}
}
//get access to tuner
static int lock_tuner(struct tda10023_state* state)
{
u8 buf[2] = { 0x0f, 0xc0 };
struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
if(i2c_transfer(state->i2c, &msg, 1) != 1)
{
printk("tda10023: lock tuner fails\n");
return -EREMOTEIO;
}
return 0;
}
//release access from tuner
static int unlock_tuner(struct tda10023_state* state)
{
u8 buf[2] = { 0x0f, 0x40 };
struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
{
printk("tda10023: unlock tuner fails\n");
return -EREMOTEIO;
}
return 0;
}
static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0)
{
reg0 |= state->reg0 & 0x63;
tda10023_writereg (state, 0x00, reg0 & 0xfe);
tda10023_writereg (state, 0x00, reg0 | 0x01);
state->reg0 = reg0;
return 0;
}
static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
{
s32 BDR;
s32 BDRI;
s16 SFIL=0;
u16 NDEC = 0;
/* avoid floating point operations multiplying syscloc and divider
by 10 */
u32 sysclk_x_10 = state->sysclk * 10;
if (sr < (u32)(sysclk_x_10/984)) {
NDEC=3;
SFIL=1;
} else if (sr < (u32)(sysclk_x_10/640)) {
NDEC=3;
SFIL=0;
} else if (sr < (u32)(sysclk_x_10/492)) {
NDEC=2;
SFIL=1;
} else if (sr < (u32)(sysclk_x_10/320)) {
NDEC=2;
SFIL=0;
} else if (sr < (u32)(sysclk_x_10/246)) {
NDEC=1;
SFIL=1;
} else if (sr < (u32)(sysclk_x_10/160)) {
NDEC=1;
SFIL=0;
} else if (sr < (u32)(sysclk_x_10/123)) {
NDEC=0;
SFIL=1;
}
BDRI = (state->sysclk)*16;
BDRI>>=NDEC;
BDRI +=sr/2;
BDRI /=sr;
if (BDRI>255)
BDRI=255;
{
u64 BDRX;
BDRX=1<<(24+NDEC);
BDRX*=sr;
do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */
BDR=(s32)BDRX;
}
dprintk("Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",
sr, BDR, BDRI, NDEC);
tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
tda10023_writereg (state, 0x0a, BDR&255);
tda10023_writereg (state, 0x0b, (BDR>>8)&255);
tda10023_writereg (state, 0x0c, (BDR>>16)&31);
tda10023_writereg (state, 0x0d, BDRI);
tda10023_writereg (state, 0x3d, (SFIL<<7));
return 0;
}
static int tda10023_init (struct dvb_frontend *fe)
{
struct tda10023_state* state = fe->demodulator_priv;
u8 tda10023_inittab[] = {
/* reg mask val */
/* 000 */ 0x2a, 0xff, 0x02, /* PLL3, Bypass, Power Down */
/* 003 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
/* 006 */ 0x2a, 0xff, 0x03, /* PLL3, Bypass, Power Down */
/* 009 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
/* PLL1 */
/* 012 */ 0x28, 0xff, (state->pll_m-1),
/* PLL2 */
/* 015 */ 0x29, 0xff, ((state->pll_p-1)<<6)|(state->pll_n-1),
/* GPR FSAMPLING=1 */
/* 018 */ 0x00, 0xff, REG0_INIT_VAL,
/* 021 */ 0x2a, 0xff, 0x08, /* PLL3 PSACLK=1 */
/* 024 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
/* 027 */ 0x1f, 0xff, 0x00, /* RESET */
/* 030 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
/* 033 */ 0xe6, 0x0c, 0x04, /* RSCFG_IND */
/* 036 */ 0x10, 0xc0, 0x80, /* DECDVBCFG1 PBER=1 */
/* 039 */ 0x0e, 0xff, 0x82, /* GAIN1 */
/* 042 */ 0x03, 0x08, 0x08, /* CLKCONF DYN=1 */
/* 045 */ 0x2e, 0xbf, 0x30, /* AGCCONF2 TRIAGC=0,POSAGC=ENAGCIF=1
PPWMTUN=0 PPWMIF=0 */
/* 048 */ 0x01, 0xff, 0x30, /* AGCREF */
/* 051 */ 0x1e, 0x84, 0x84, /* CONTROL SACLK_ON=1 */
/* 054 */ 0x1b, 0xff, 0xc8, /* ADC TWOS=1 */
/* 057 */ 0x3b, 0xff, 0xff, /* IFMAX */
/* 060 */ 0x3c, 0xff, 0x00, /* IFMIN */
/* 063 */ 0x34, 0xff, 0x00, /* PWMREF */
/* 066 */ 0x35, 0xff, 0xff, /* TUNMAX */
/* 069 */ 0x36, 0xff, 0x00, /* TUNMIN */
/* 072 */ 0x06, 0xff, 0x7f, /* EQCONF1 POSI=7 ENADAPT=ENEQUAL=DFE=1 */
/* 075 */ 0x1c, 0x30, 0x30, /* EQCONF2 STEPALGO=SGNALGO=1 */
/* 078 */ 0x37, 0xff, 0xf6, /* DELTAF_LSB */
/* 081 */ 0x38, 0xff, 0xff, /* DELTAF_MSB */
/* 084 */ 0x02, 0xff, 0x93, /* AGCCONF1 IFS=1 KAGCIF=2 KAGCTUN=3 */
/* 087 */ 0x2d, 0xff, 0xf6, /* SWEEP SWPOS=1 SWDYN=7 SWSTEP=1 SWLEN=2 */
/* 090 */ 0x04, 0x10, 0x00, /* SWRAMP=1 */
/* 093 */ 0x12, 0xff, TDA10023_OUTPUT_MODE_PARALLEL_B, /*
INTP1 POCLKP=1 FEL=1 MFS=0 */
/* 096 */ 0x2b, 0x01, 0xa1, /* INTS1 */
/* 099 */ 0x20, 0xff, 0x04, /* INTP2 SWAPP=? MSBFIRSTP=? INTPSEL=? */
/* 102 */ 0x2c, 0xff, 0x0d, /* INTP/S TRIP=0 TRIS=0 */
/* 105 */ 0xc4, 0xff, 0x00,
/* 108 */ 0xc3, 0x30, 0x00,
/* 111 */ 0xb5, 0xff, 0x19, /* ERAGC_THD */
/* 114 */ 0x00, 0x03, 0x01, /* GPR, CLBS soft reset */
/* 117 */ 0x00, 0x03, 0x03, /* GPR, CLBS soft reset */
/* 120 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
/* 123 */ 0xff, 0xff, 0xff
};
dprintk("DVB: TDA10023(%d): init chip\n", fe->dvb->num);
/* override default values if set in config */
if (state->config->deltaf) {
tda10023_inittab[80] = (state->config->deltaf & 0xff);
tda10023_inittab[83] = (state->config->deltaf >> 8);
}
if (state->config->output_mode)
tda10023_inittab[95] = state->config->output_mode;
tda10023_writetab(state, tda10023_inittab);
return 0;
}
struct qam_params {
u8 qam, lockthr, mseth, aref, agcrefnyq, eragnyq_thd;
};
static int tda10023_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 delsys = c->delivery_system;
unsigned qam = c->modulation;
bool is_annex_c;
struct tda10023_state* state = fe->demodulator_priv;
static const struct qam_params qam_params[] = {
/* Modulation QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD */
[QPSK] = { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c },
[QAM_16] = { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 },
[QAM_32] = { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 },
[QAM_64] = { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 },
[QAM_128] = { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c },
[QAM_256] = { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c },
};
switch (delsys) {
case SYS_DVBC_ANNEX_A:
is_annex_c = false;
break;
case SYS_DVBC_ANNEX_C:
is_annex_c = true;
break;
default:
return -EINVAL;
}
/*
* gcc optimizes the code below the same way as it would code:
* "if (qam > 5) return -EINVAL;"
* Yet, the code is clearer, as it shows what QAM standards are
* supported by the driver, and avoids the usage of magic numbers on
* it.
*/
switch (qam) {
case QPSK:
case QAM_16:
case QAM_32:
case QAM_64:
case QAM_128:
case QAM_256:
break;
default:
return -EINVAL;
}
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
tda10023_set_symbolrate(state, c->symbol_rate);
tda10023_writereg(state, 0x05, qam_params[qam].lockthr);
tda10023_writereg(state, 0x08, qam_params[qam].mseth);
tda10023_writereg(state, 0x09, qam_params[qam].aref);
tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq);
tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd);
#if 0
tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32));
tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20));
#endif
tda10023_writebit(state, 0x04, 0x40, 0x40);
if (is_annex_c)
tda10023_writebit(state, 0x3d, 0xfc, 0x03);
else
tda10023_writebit(state, 0x3d, 0xfc, 0x02);
tda10023_setup_reg0(state, qam_params[qam].qam);
return 0;
}
static int tda10023_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct tda10023_state* state = fe->demodulator_priv;
int sync;
*status = 0;
//0x11[1] == CARLOCK -> Carrier locked
//0x11[2] == FSYNC -> Frame synchronisation
//0x11[3] == FEL -> Front End locked
//0x11[6] == NODVB -> DVB Mode Information
sync = tda10023_readreg (state, 0x11);
if (sync & 2)
*status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;
if (sync & 4)
*status |= FE_HAS_SYNC|FE_HAS_VITERBI;
if (sync & 8)
*status |= FE_HAS_LOCK;
return 0;
}
static int tda10023_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda10023_state* state = fe->demodulator_priv;
u8 a,b,c;
a=tda10023_readreg(state, 0x14);
b=tda10023_readreg(state, 0x15);
c=tda10023_readreg(state, 0x16)&0xf;
tda10023_writebit (state, 0x10, 0xc0, 0x00);
*ber = a | (b<<8)| (c<<16);
return 0;
}
static int tda10023_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct tda10023_state* state = fe->demodulator_priv;
u8 ifgain=tda10023_readreg(state, 0x2f);
u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
// Max raw value is about 0xb0 -> Normalize to >0xf0 after 0x90
if (gain>0x90)
gain=gain+2*(gain-0x90);
if (gain>255)
gain=255;
*strength = (gain<<8)|gain;
return 0;
}
static int tda10023_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct tda10023_state* state = fe->demodulator_priv;
u8 quality = ~tda10023_readreg(state, 0x18);
*snr = (quality << 8) | quality;
return 0;
}
static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda10023_state* state = fe->demodulator_priv;
u8 a,b,c,d;
a= tda10023_readreg (state, 0x74);
b= tda10023_readreg (state, 0x75);
c= tda10023_readreg (state, 0x76);
d= tda10023_readreg (state, 0x77);
*ucblocks = a | (b<<8)|(c<<16)|(d<<24);
tda10023_writebit (state, 0x10, 0x20,0x00);
tda10023_writebit (state, 0x10, 0x20,0x20);
tda10023_writebit (state, 0x13, 0x01, 0x00);
return 0;
}
static int tda10023_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct tda10023_state* state = fe->demodulator_priv;
int sync,inv;
s8 afc = 0;
sync = tda10023_readreg(state, 0x11);
afc = tda10023_readreg(state, 0x19);
inv = tda10023_readreg(state, 0x04);
if (verbose) {
/* AFC only valid when carrier has been recovered */
printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
"DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
state->frontend.dvb->num, afc,
-((s32)p->symbol_rate * afc) >> 10);
}
p->inversion = (inv&0x20?0:1);
p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
p->fec_inner = FEC_NONE;
p->frequency = ((p->frequency + 31250) / 62500) * 62500;
if (sync & 2)
p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
return 0;
}
static int tda10023_sleep(struct dvb_frontend* fe)
{
struct tda10023_state* state = fe->demodulator_priv;
tda10023_writereg (state, 0x1b, 0x02); /* pdown ADC */
tda10023_writereg (state, 0x00, 0x80); /* standby */
return 0;
}
static int tda10023_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct tda10023_state* state = fe->demodulator_priv;
if (enable) {
lock_tuner(state);
} else {
unlock_tuner(state);
}
return 0;
}
static void tda10023_release(struct dvb_frontend* fe)
{
struct tda10023_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops tda10023_ops;
struct dvb_frontend *tda10023_attach(const struct tda10023_config *config,
struct i2c_adapter *i2c,
u8 pwm)
{
struct tda10023_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* wakeup if in standby */
tda10023_writereg (state, 0x00, 0x33);
/* check if the demod is there */
if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
state->pwm = pwm;
state->reg0 = REG0_INIT_VAL;
if (state->config->xtal) {
state->xtal = state->config->xtal;
state->pll_m = state->config->pll_m;
state->pll_p = state->config->pll_p;
state->pll_n = state->config->pll_n;
} else {
/* set default values if not defined in config */
state->xtal = 28920000;
state->pll_m = 8;
state->pll_p = 4;
state->pll_n = 1;
}
/* calc sysclk */
state->sysclk = (state->xtal * state->pll_m / \
(state->pll_n * state->pll_p));
state->frontend.ops.info.symbol_rate_min = (state->sysclk/2)/64;
state->frontend.ops.info.symbol_rate_max = (state->sysclk/2)/4;
dprintk("DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
__func__, state->xtal, state->pll_m, state->pll_p,
state->pll_n);
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops tda10023_ops = {
.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
.info = {
.name = "Philips TDA10023 DVB-C",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 0, /* set in tda10023_attach */
.symbol_rate_max = 0, /* set in tda10023_attach */
.caps = 0x400 | //FE_CAN_QAM_4
FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
FE_CAN_QAM_128 | FE_CAN_QAM_256 |
FE_CAN_FEC_AUTO
},
.release = tda10023_release,
.init = tda10023_init,
.sleep = tda10023_sleep,
.i2c_gate_ctrl = tda10023_i2c_gate_ctrl,
.set_frontend = tda10023_set_parameters,
.get_frontend = tda10023_get_frontend,
.read_status = tda10023_read_status,
.read_ber = tda10023_read_ber,
.read_signal_strength = tda10023_read_signal_strength,
.read_snr = tda10023_read_snr,
.read_ucblocks = tda10023_read_ucblocks,
};
MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver");
MODULE_AUTHOR("Georg Acher, Hartmut Birr");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(tda10023_attach);
| linux-master | drivers/media/dvb-frontends/tda10023.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Realtek RTL2830 DVB-T demodulator driver
*
* Copyright (C) 2011 Antti Palosaari <[email protected]>
*/
#include "rtl2830_priv.h"
/* Our regmap is bypassing I2C adapter lock, thus we do it! */
static int rtl2830_bulk_write(struct i2c_client *client, unsigned int reg,
const void *val, size_t val_count)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
return ret;
}
static int rtl2830_update_bits(struct i2c_client *client, unsigned int reg,
unsigned int mask, unsigned int val)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_update_bits(dev->regmap, reg, mask, val);
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
return ret;
}
static int rtl2830_bulk_read(struct i2c_client *client, unsigned int reg,
void *val, size_t val_count)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
return ret;
}
static int rtl2830_init(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
int ret, i;
struct rtl2830_reg_val_mask tab[] = {
{0x00d, 0x01, 0x03},
{0x00d, 0x10, 0x10},
{0x104, 0x00, 0x1e},
{0x105, 0x80, 0x80},
{0x110, 0x02, 0x03},
{0x110, 0x08, 0x0c},
{0x17b, 0x00, 0x40},
{0x17d, 0x05, 0x0f},
{0x17d, 0x50, 0xf0},
{0x18c, 0x08, 0x0f},
{0x18d, 0x00, 0xc0},
{0x188, 0x05, 0x0f},
{0x189, 0x00, 0xfc},
{0x2d5, 0x02, 0x02},
{0x2f1, 0x02, 0x06},
{0x2f1, 0x20, 0xf8},
{0x16d, 0x00, 0x01},
{0x1a6, 0x00, 0x80},
{0x106, dev->pdata->vtop, 0x3f},
{0x107, dev->pdata->krf, 0x3f},
{0x112, 0x28, 0xff},
{0x103, dev->pdata->agc_targ_val, 0xff},
{0x00a, 0x02, 0x07},
{0x140, 0x0c, 0x3c},
{0x140, 0x40, 0xc0},
{0x15b, 0x05, 0x07},
{0x15b, 0x28, 0x38},
{0x15c, 0x05, 0x07},
{0x15c, 0x28, 0x38},
{0x115, dev->pdata->spec_inv, 0x01},
{0x16f, 0x01, 0x07},
{0x170, 0x18, 0x38},
{0x172, 0x0f, 0x0f},
{0x173, 0x08, 0x38},
{0x175, 0x01, 0x07},
{0x176, 0x00, 0xc0},
};
for (i = 0; i < ARRAY_SIZE(tab); i++) {
ret = rtl2830_update_bits(client, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
ret = rtl2830_bulk_write(client, 0x18f, "\x28\x00", 2);
if (ret)
goto err;
ret = rtl2830_bulk_write(client, 0x195,
"\x04\x06\x0a\x12\x0a\x12\x1e\x28", 8);
if (ret)
goto err;
/* TODO: spec init */
/* soft reset */
ret = rtl2830_update_bits(client, 0x101, 0x04, 0x04);
if (ret)
goto err;
ret = rtl2830_update_bits(client, 0x101, 0x04, 0x00);
if (ret)
goto err;
/* init stats here in order signal app which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dev->sleeping = false;
return ret;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2830_sleep(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
dev->sleeping = true;
dev->fe_status = 0;
return 0;
}
static int rtl2830_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 500;
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
return 0;
}
static int rtl2830_set_frontend(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
u64 num;
u8 buf[3], u8tmp;
u32 if_ctl, if_frequency;
static const u8 bw_params1[3][34] = {
{
0x1f, 0xf0, 0x1f, 0xf0, 0x1f, 0xfa, 0x00, 0x17, 0x00, 0x41,
0x00, 0x64, 0x00, 0x67, 0x00, 0x38, 0x1f, 0xde, 0x1f, 0x7a,
0x1f, 0x47, 0x1f, 0x7c, 0x00, 0x30, 0x01, 0x4b, 0x02, 0x82,
0x03, 0x73, 0x03, 0xcf, /* 6 MHz */
}, {
0x1f, 0xfa, 0x1f, 0xda, 0x1f, 0xc1, 0x1f, 0xb3, 0x1f, 0xca,
0x00, 0x07, 0x00, 0x4d, 0x00, 0x6d, 0x00, 0x40, 0x1f, 0xca,
0x1f, 0x4d, 0x1f, 0x2a, 0x1f, 0xb2, 0x00, 0xec, 0x02, 0x7e,
0x03, 0xd0, 0x04, 0x53, /* 7 MHz */
}, {
0x00, 0x10, 0x00, 0x0e, 0x1f, 0xf7, 0x1f, 0xc9, 0x1f, 0xa0,
0x1f, 0xa6, 0x1f, 0xec, 0x00, 0x4e, 0x00, 0x7d, 0x00, 0x3a,
0x1f, 0x98, 0x1f, 0x10, 0x1f, 0x40, 0x00, 0x75, 0x02, 0x5f,
0x04, 0x24, 0x04, 0xdb, /* 8 MHz */
},
};
static const u8 bw_params2[3][6] = {
{0xc3, 0x0c, 0x44, 0x33, 0x33, 0x30}, /* 6 MHz */
{0xb8, 0xe3, 0x93, 0x99, 0x99, 0x98}, /* 7 MHz */
{0xae, 0xba, 0xf3, 0x26, 0x66, 0x64}, /* 8 MHz */
};
dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
c->frequency, c->bandwidth_hz, c->inversion);
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
switch (c->bandwidth_hz) {
case 6000000:
i = 0;
break;
case 7000000:
i = 1;
break;
case 8000000:
i = 2;
break;
default:
dev_err(&client->dev, "invalid bandwidth_hz %u\n",
c->bandwidth_hz);
return -EINVAL;
}
ret = rtl2830_update_bits(client, 0x008, 0x06, i << 1);
if (ret)
goto err;
/* program if frequency */
if (fe->ops.tuner_ops.get_if_frequency)
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
else
ret = -EINVAL;
if (ret)
goto err;
num = if_frequency % dev->pdata->clk;
num *= 0x400000;
num = div_u64(num, dev->pdata->clk);
num = -num;
if_ctl = num & 0x3fffff;
dev_dbg(&client->dev, "if_frequency=%d if_ctl=%08x\n",
if_frequency, if_ctl);
buf[0] = (if_ctl >> 16) & 0x3f;
buf[1] = (if_ctl >> 8) & 0xff;
buf[2] = (if_ctl >> 0) & 0xff;
ret = rtl2830_bulk_read(client, 0x119, &u8tmp, 1);
if (ret)
goto err;
buf[0] |= u8tmp & 0xc0; /* [7:6] */
ret = rtl2830_bulk_write(client, 0x119, buf, 3);
if (ret)
goto err;
/* 1/2 split I2C write */
ret = rtl2830_bulk_write(client, 0x11c, &bw_params1[i][0], 17);
if (ret)
goto err;
/* 2/2 split I2C write */
ret = rtl2830_bulk_write(client, 0x12d, &bw_params1[i][17], 17);
if (ret)
goto err;
ret = rtl2830_bulk_write(client, 0x19d, bw_params2[i], 6);
if (ret)
goto err;
return ret;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2830_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
u8 buf[3];
if (dev->sleeping)
return 0;
ret = rtl2830_bulk_read(client, 0x33c, buf, 2);
if (ret)
goto err;
ret = rtl2830_bulk_read(client, 0x351, &buf[2], 1);
if (ret)
goto err;
dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
switch ((buf[0] >> 2) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[2] >> 2) & 1) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
}
switch ((buf[2] >> 0) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[0] >> 4) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[1] >> 3) & 7) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
}
switch ((buf[1] >> 0) & 7) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2830_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
int ret, stmp;
unsigned int utmp;
u8 u8tmp, buf[2];
*status = 0;
if (dev->sleeping)
return 0;
ret = rtl2830_bulk_read(client, 0x351, &u8tmp, 1);
if (ret)
goto err;
u8tmp = (u8tmp >> 3) & 0x0f; /* [6:3] */
if (u8tmp == 11) {
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else if (u8tmp == 10) {
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
}
dev->fe_status = *status;
/* Signal strength */
if (dev->fe_status & FE_HAS_SIGNAL) {
/* Read IF AGC */
ret = rtl2830_bulk_read(client, 0x359, buf, 2);
if (ret)
goto err;
stmp = buf[0] << 8 | buf[1] << 0;
stmp = sign_extend32(stmp, 13);
utmp = clamp_val(-4 * stmp + 32767, 0x0000, 0xffff);
dev_dbg(&client->dev, "IF AGC=%d\n", stmp);
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = utmp;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (dev->fe_status & FE_HAS_VITERBI) {
unsigned int hierarchy, constellation;
#define CONSTELLATION_NUM 3
#define HIERARCHY_NUM 4
static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
{70705899, 70705899, 70705899, 70705899},
{82433173, 82433173, 87483115, 94445660},
{92888734, 92888734, 95487525, 99770748},
};
ret = rtl2830_bulk_read(client, 0x33c, &u8tmp, 1);
if (ret)
goto err;
constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
if (constellation > CONSTELLATION_NUM - 1)
goto err;
hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
if (hierarchy > HIERARCHY_NUM - 1)
goto err;
ret = rtl2830_bulk_read(client, 0x40c, buf, 2);
if (ret)
goto err;
utmp = buf[0] << 8 | buf[1] << 0;
if (utmp)
stmp = (constant[constellation][hierarchy] -
intlog10(utmp)) / ((1 << 24) / 10000);
else
stmp = 0;
dev_dbg(&client->dev, "CNR raw=%u\n", utmp);
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = stmp;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (dev->fe_status & FE_HAS_LOCK) {
ret = rtl2830_bulk_read(client, 0x34e, buf, 2);
if (ret)
goto err;
utmp = buf[0] << 8 | buf[1] << 0;
dev->post_bit_error += utmp;
dev->post_bit_count += 1000000;
dev_dbg(&client->dev, "BER errors=%u total=1000000\n", utmp);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return ret;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2830_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int rtl2830_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
*ber = (dev->post_bit_error - dev->post_bit_error_prev);
dev->post_bit_error_prev = dev->post_bit_error;
return 0;
}
static int rtl2830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
*ucblocks = 0;
return 0;
}
static int rtl2830_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->strength.stat[0].scale == FE_SCALE_RELATIVE)
*strength = c->strength.stat[0].uvalue;
else
*strength = 0;
return 0;
}
static const struct dvb_frontend_ops rtl2830_ops = {
.delsys = {SYS_DVBT},
.info = {
.name = "Realtek RTL2830 (DVB-T)",
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.init = rtl2830_init,
.sleep = rtl2830_sleep,
.get_tune_settings = rtl2830_get_tune_settings,
.set_frontend = rtl2830_set_frontend,
.get_frontend = rtl2830_get_frontend,
.read_status = rtl2830_read_status,
.read_snr = rtl2830_read_snr,
.read_ber = rtl2830_read_ber,
.read_ucblocks = rtl2830_read_ucblocks,
.read_signal_strength = rtl2830_read_signal_strength,
};
static int rtl2830_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
{
struct i2c_client *client = fe->demodulator_priv;
int ret;
u8 u8tmp;
dev_dbg(&client->dev, "onoff=%d\n", onoff);
/* enable / disable PID filter */
if (onoff)
u8tmp = 0x80;
else
u8tmp = 0x00;
ret = rtl2830_update_bits(client, 0x061, 0x80, u8tmp);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2830_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid, int onoff)
{
struct i2c_client *client = fe->demodulator_priv;
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
u8 buf[4];
dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
index, pid, onoff);
/* skip invalid PIDs (0x2000) */
if (pid > 0x1fff || index > 32)
return 0;
if (onoff)
set_bit(index, &dev->filters);
else
clear_bit(index, &dev->filters);
/* enable / disable PIDs */
buf[0] = (dev->filters >> 0) & 0xff;
buf[1] = (dev->filters >> 8) & 0xff;
buf[2] = (dev->filters >> 16) & 0xff;
buf[3] = (dev->filters >> 24) & 0xff;
ret = rtl2830_bulk_write(client, 0x062, buf, 4);
if (ret)
goto err;
/* add PID */
buf[0] = (pid >> 8) & 0xff;
buf[1] = (pid >> 0) & 0xff;
ret = rtl2830_bulk_write(client, 0x066 + 2 * index, buf, 2);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
/*
* I2C gate/mux/repeater logic
* We must use unlocked __i2c_transfer() here (through regmap) because of I2C
* adapter lock is already taken by tuner driver.
* Gate is closed automatically after single I2C transfer.
*/
static int rtl2830_select(struct i2c_mux_core *muxc, u32 chan_id)
{
struct i2c_client *client = i2c_mux_priv(muxc);
struct rtl2830_dev *dev = i2c_get_clientdata(client);
int ret;
dev_dbg(&client->dev, "\n");
/* open I2C repeater for 1 transfer, closes automatically */
/* XXX: regmap_update_bits() does not lock I2C adapter */
ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static struct dvb_frontend *rtl2830_get_dvb_frontend(struct i2c_client *client)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &dev->fe;
}
static struct i2c_adapter *rtl2830_get_i2c_adapter(struct i2c_client *client)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return dev->muxc->adapter[0];
}
/*
* We implement own I2C access routines for regmap in order to get manual access
* to I2C adapter lock, which is needed for I2C mux adapter.
*/
static int rtl2830_regmap_read(void *context, const void *reg_buf,
size_t reg_size, void *val_buf, size_t val_size)
{
struct i2c_client *client = context;
int ret;
struct i2c_msg msg[2] = {
{
.addr = client->addr,
.flags = 0,
.len = reg_size,
.buf = (u8 *)reg_buf,
}, {
.addr = client->addr,
.flags = I2C_M_RD,
.len = val_size,
.buf = val_buf,
}
};
ret = __i2c_transfer(client->adapter, msg, 2);
if (ret != 2) {
dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
if (ret >= 0)
ret = -EREMOTEIO;
return ret;
}
return 0;
}
static int rtl2830_regmap_write(void *context, const void *data, size_t count)
{
struct i2c_client *client = context;
int ret;
struct i2c_msg msg[1] = {
{
.addr = client->addr,
.flags = 0,
.len = count,
.buf = (u8 *)data,
}
};
ret = __i2c_transfer(client->adapter, msg, 1);
if (ret != 1) {
dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
if (ret >= 0)
ret = -EREMOTEIO;
return ret;
}
return 0;
}
static int rtl2830_regmap_gather_write(void *context, const void *reg,
size_t reg_len, const void *val,
size_t val_len)
{
struct i2c_client *client = context;
int ret;
u8 buf[256];
struct i2c_msg msg[1] = {
{
.addr = client->addr,
.flags = 0,
.len = 1 + val_len,
.buf = buf,
}
};
buf[0] = *(u8 const *)reg;
memcpy(&buf[1], val, val_len);
ret = __i2c_transfer(client->adapter, msg, 1);
if (ret != 1) {
dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
if (ret >= 0)
ret = -EREMOTEIO;
return ret;
}
return 0;
}
static int rtl2830_probe(struct i2c_client *client)
{
struct rtl2830_platform_data *pdata = client->dev.platform_data;
struct rtl2830_dev *dev;
int ret;
u8 u8tmp;
static const struct regmap_bus regmap_bus = {
.read = rtl2830_regmap_read,
.write = rtl2830_regmap_write,
.gather_write = rtl2830_regmap_gather_write,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
static const struct regmap_range_cfg regmap_range_cfg[] = {
{
.selector_reg = 0x00,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 0x100,
.range_min = 0 * 0x100,
.range_max = 5 * 0x100,
},
};
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 5 * 0x100,
.ranges = regmap_range_cfg,
.num_ranges = ARRAY_SIZE(regmap_range_cfg),
};
dev_dbg(&client->dev, "\n");
if (pdata == NULL) {
ret = -EINVAL;
goto err;
}
/* allocate memory for the internal state */
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
goto err;
}
/* setup the state */
i2c_set_clientdata(client, dev);
dev->client = client;
dev->pdata = client->dev.platform_data;
dev->sleeping = true;
dev->regmap = regmap_init(&client->dev, ®map_bus, client,
®map_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
/* check if the demod is there */
ret = rtl2830_bulk_read(client, 0x000, &u8tmp, 1);
if (ret)
goto err_regmap_exit;
/* create muxed i2c adapter for tuner */
dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
rtl2830_select, NULL);
if (!dev->muxc) {
ret = -ENOMEM;
goto err_regmap_exit;
}
dev->muxc->priv = client;
ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
if (ret)
goto err_regmap_exit;
/* create dvb frontend */
memcpy(&dev->fe.ops, &rtl2830_ops, sizeof(dev->fe.ops));
dev->fe.demodulator_priv = client;
/* setup callbacks */
pdata->get_dvb_frontend = rtl2830_get_dvb_frontend;
pdata->get_i2c_adapter = rtl2830_get_i2c_adapter;
pdata->pid_filter = rtl2830_pid_filter;
pdata->pid_filter_ctrl = rtl2830_pid_filter_ctrl;
dev_info(&client->dev, "Realtek RTL2830 successfully attached\n");
return 0;
err_regmap_exit:
regmap_exit(dev->regmap);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void rtl2830_remove(struct i2c_client *client)
{
struct rtl2830_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
i2c_mux_del_adapters(dev->muxc);
regmap_exit(dev->regmap);
kfree(dev);
}
static const struct i2c_device_id rtl2830_id_table[] = {
{"rtl2830", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rtl2830_id_table);
static struct i2c_driver rtl2830_driver = {
.driver = {
.name = "rtl2830",
.suppress_bind_attrs = true,
},
.probe = rtl2830_probe,
.remove = rtl2830_remove,
.id_table = rtl2830_id_table,
};
module_i2c_driver(rtl2830_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Realtek RTL2830 DVB-T demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/rtl2830.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Montage Technology DS3000 - DVBS/S2 Demodulator driver
Copyright (C) 2009-2012 Konstantin Dimitrov <[email protected]>
Copyright (C) 2009-2012 TurboSight.com
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include <media/dvb_frontend.h>
#include "ts2020.h"
#include "ds3000.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) \
printk(args); \
} while (0)
/* as of March 2009 current DS3000 firmware version is 1.78 */
/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
#define DS3000_SAMPLE_RATE 96000 /* in kHz */
/* Register values to initialise the demod in DVB-S mode */
static u8 ds3000_dvbs_init_tab[] = {
0x23, 0x05,
0x08, 0x03,
0x0c, 0x00,
0x21, 0x54,
0x25, 0x82,
0x27, 0x31,
0x30, 0x08,
0x31, 0x40,
0x32, 0x32,
0x33, 0x35,
0x35, 0xff,
0x3a, 0x00,
0x37, 0x10,
0x38, 0x10,
0x39, 0x02,
0x42, 0x60,
0x4a, 0x40,
0x4b, 0x04,
0x4d, 0x91,
0x5d, 0xc8,
0x50, 0x77,
0x51, 0x77,
0x52, 0x36,
0x53, 0x36,
0x56, 0x01,
0x63, 0x43,
0x64, 0x30,
0x65, 0x40,
0x68, 0x26,
0x69, 0x4c,
0x70, 0x20,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x40,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x60,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x80,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0xa0,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x1f,
0x76, 0x00,
0x77, 0xd1,
0x78, 0x0c,
0x79, 0x80,
0x7f, 0x04,
0x7c, 0x00,
0x80, 0x86,
0x81, 0xa6,
0x85, 0x04,
0xcd, 0xf4,
0x90, 0x33,
0xa0, 0x44,
0xc0, 0x18,
0xc3, 0x10,
0xc4, 0x08,
0xc5, 0x80,
0xc6, 0x80,
0xc7, 0x0a,
0xc8, 0x1a,
0xc9, 0x80,
0xfe, 0x92,
0xe0, 0xf8,
0xe6, 0x8b,
0xd0, 0x40,
0xf8, 0x20,
0xfa, 0x0f,
0xfd, 0x20,
0xad, 0x20,
0xae, 0x07,
0xb8, 0x00,
};
/* Register values to initialise the demod in DVB-S2 mode */
static u8 ds3000_dvbs2_init_tab[] = {
0x23, 0x0f,
0x08, 0x07,
0x0c, 0x00,
0x21, 0x54,
0x25, 0x82,
0x27, 0x31,
0x30, 0x08,
0x31, 0x32,
0x32, 0x32,
0x33, 0x35,
0x35, 0xff,
0x3a, 0x00,
0x37, 0x10,
0x38, 0x10,
0x39, 0x02,
0x42, 0x60,
0x4a, 0x80,
0x4b, 0x04,
0x4d, 0x81,
0x5d, 0x88,
0x50, 0x36,
0x51, 0x36,
0x52, 0x36,
0x53, 0x36,
0x63, 0x60,
0x64, 0x10,
0x65, 0x10,
0x68, 0x04,
0x69, 0x29,
0x70, 0x20,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x40,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x60,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x80,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0xa0,
0x71, 0x70,
0x72, 0x04,
0x73, 0x00,
0x70, 0x1f,
0xa0, 0x44,
0xc0, 0x08,
0xc1, 0x10,
0xc2, 0x08,
0xc3, 0x10,
0xc4, 0x08,
0xc5, 0xf0,
0xc6, 0xf0,
0xc7, 0x0a,
0xc8, 0x1a,
0xc9, 0x80,
0xca, 0x23,
0xcb, 0x24,
0xce, 0x74,
0x90, 0x03,
0x76, 0x80,
0x77, 0x42,
0x78, 0x0a,
0x79, 0x80,
0xad, 0x40,
0xae, 0x07,
0x7f, 0xd4,
0x7c, 0x00,
0x80, 0xa8,
0x81, 0xda,
0x7c, 0x01,
0x80, 0xda,
0x81, 0xec,
0x7c, 0x02,
0x80, 0xca,
0x81, 0xeb,
0x7c, 0x03,
0x80, 0xba,
0x81, 0xdb,
0x85, 0x08,
0x86, 0x00,
0x87, 0x02,
0x89, 0x80,
0x8b, 0x44,
0x8c, 0xaa,
0x8a, 0x10,
0xba, 0x00,
0xf5, 0x04,
0xfe, 0x44,
0xd2, 0x32,
0xb8, 0x00,
};
struct ds3000_state {
struct i2c_adapter *i2c;
const struct ds3000_config *config;
struct dvb_frontend frontend;
/* previous uncorrected block counter for DVB-S2 */
u16 prevUCBS2;
};
static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address,
.flags = 0, .buf = buf, .len = 2 };
int err;
dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
__func__, err, reg, data);
return -EREMOTEIO;
}
return 0;
}
static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct ds3000_state *state = fe->demodulator_priv;
if (enable)
ds3000_writereg(state, 0x03, 0x12);
else
ds3000_writereg(state, 0x03, 0x02);
return 0;
}
/* I2C write for 8k firmware load */
static int ds3000_writeFW(struct ds3000_state *state, int reg,
const u8 *data, u16 len)
{
int i, ret = 0;
struct i2c_msg msg;
u8 *buf;
buf = kmalloc(33, GFP_KERNEL);
if (!buf)
return -ENOMEM;
*(buf) = reg;
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.buf = buf;
msg.len = 33;
for (i = 0; i < len; i += 32) {
memcpy(buf + 1, data + i, 32);
dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
__func__, ret, reg);
ret = -EREMOTEIO;
goto error;
}
}
ret = 0;
error:
kfree(buf);
return ret;
}
static int ds3000_readreg(struct ds3000_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
return ret;
}
dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
return b1[0];
}
static int ds3000_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw);
static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
{
struct ds3000_state *state = fe->demodulator_priv;
const struct firmware *fw;
int ret = 0;
dprintk("%s()\n", __func__);
ret = ds3000_readreg(state, 0xb2);
if (ret < 0)
return ret;
/* Load firmware */
/* request the firmware, this will block until someone uploads it */
printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
DS3000_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
state->i2c->dev.parent);
printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
if (ret) {
printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
__func__);
return ret;
}
ret = ds3000_load_firmware(fe, fw);
if (ret)
printk("%s: Writing firmware to device failed\n", __func__);
release_firmware(fw);
dprintk("%s: Firmware upload %s\n", __func__,
ret == 0 ? "complete" : "failed");
return ret;
}
static int ds3000_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw)
{
struct ds3000_state *state = fe->demodulator_priv;
int ret = 0;
dprintk("%s\n", __func__);
dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
fw->size,
fw->data[0],
fw->data[1],
fw->data[fw->size - 2],
fw->data[fw->size - 1]);
/* Begin the firmware load process */
ds3000_writereg(state, 0xb2, 0x01);
/* write the entire firmware */
ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
ds3000_writereg(state, 0xb2, 0x00);
return ret;
}
static int ds3000_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct ds3000_state *state = fe->demodulator_priv;
u8 data;
dprintk("%s(%d)\n", __func__, voltage);
data = ds3000_readreg(state, 0xa2);
data |= 0x03; /* bit0 V/H, bit1 off/on */
switch (voltage) {
case SEC_VOLTAGE_18:
data &= ~0x03;
break;
case SEC_VOLTAGE_13:
data &= ~0x03;
data |= 0x01;
break;
case SEC_VOLTAGE_OFF:
break;
}
ds3000_writereg(state, 0xa2, data);
return 0;
}
static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int lock;
*status = 0;
switch (c->delivery_system) {
case SYS_DVBS:
lock = ds3000_readreg(state, 0xd1);
if ((lock & 0x07) == 0x07)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
break;
case SYS_DVBS2:
lock = ds3000_readreg(state, 0x0d);
if ((lock & 0x8f) == 0x8f)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
break;
default:
return -EINVAL;
}
if (state->config->set_lock_led)
state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
dprintk("%s: status = 0x%02x\n", __func__, lock);
return 0;
}
/* read DS3000 BER value */
static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 data;
u32 ber_reading, lpdc_frames;
dprintk("%s()\n", __func__);
switch (c->delivery_system) {
case SYS_DVBS:
/* set the number of bytes checked during
BER estimation */
ds3000_writereg(state, 0xf9, 0x04);
/* read BER estimation status */
data = ds3000_readreg(state, 0xf8);
/* check if BER estimation is ready */
if ((data & 0x10) == 0) {
/* this is the number of error bits,
to calculate the bit error rate
divide to 8388608 */
*ber = (ds3000_readreg(state, 0xf7) << 8) |
ds3000_readreg(state, 0xf6);
/* start counting error bits */
/* need to be set twice
otherwise it fails sometimes */
data |= 0x10;
ds3000_writereg(state, 0xf8, data);
ds3000_writereg(state, 0xf8, data);
} else
/* used to indicate that BER estimation
is not ready, i.e. BER is unknown */
*ber = 0xffffffff;
break;
case SYS_DVBS2:
/* read the number of LPDC decoded frames */
lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
(ds3000_readreg(state, 0xd6) << 8) |
ds3000_readreg(state, 0xd5);
/* read the number of packets with bad CRC */
ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
ds3000_readreg(state, 0xf7);
if (lpdc_frames > 750) {
/* clear LPDC frame counters */
ds3000_writereg(state, 0xd1, 0x01);
/* clear bad packets counter */
ds3000_writereg(state, 0xf9, 0x01);
/* enable bad packets counter */
ds3000_writereg(state, 0xf9, 0x00);
/* enable LPDC frame counters */
ds3000_writereg(state, 0xd1, 0x00);
*ber = ber_reading;
} else
/* used to indicate that BER estimation is not ready,
i.e. BER is unknown */
*ber = 0xffffffff;
break;
default:
return -EINVAL;
}
return 0;
}
static int ds3000_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
if (fe->ops.tuner_ops.get_rf_strength)
fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
return 0;
}
/* calculate DS3000 snr value in dB */
static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 snr_reading, snr_value;
u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
};
static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
0x49e9, 0x4a20, 0x4a57
};
dprintk("%s()\n", __func__);
switch (c->delivery_system) {
case SYS_DVBS:
snr_reading = ds3000_readreg(state, 0xff);
snr_reading /= 8;
if (snr_reading == 0)
*snr = 0x0000;
else {
if (snr_reading > 20)
snr_reading = 20;
snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
/* cook the value to be suitable for szap-s2
human readable output */
*snr = snr_value * 8 * 655;
}
dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
snr_reading, *snr);
break;
case SYS_DVBS2:
dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
(ds3000_readreg(state, 0x8d) << 4);
dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
if (tmp == 0) {
*snr = 0x0000;
return 0;
}
if (dvbs2_noise_reading == 0) {
snr_value = 0x0013;
/* cook the value to be suitable for szap-s2
human readable output */
*snr = 0xffff;
return 0;
}
if (tmp > dvbs2_noise_reading) {
snr_reading = tmp / dvbs2_noise_reading;
if (snr_reading > 80)
snr_reading = 80;
snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
/* cook the value to be suitable for szap-s2
human readable output */
*snr = snr_value * 5 * 655;
} else {
snr_reading = dvbs2_noise_reading / tmp;
if (snr_reading > 80)
snr_reading = 80;
*snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
}
dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
snr_reading, *snr);
break;
default:
return -EINVAL;
}
return 0;
}
/* read DS3000 uncorrected blocks */
static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 data;
u16 _ucblocks;
dprintk("%s()\n", __func__);
switch (c->delivery_system) {
case SYS_DVBS:
*ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
ds3000_readreg(state, 0xf4);
data = ds3000_readreg(state, 0xf8);
/* clear packet counters */
data &= ~0x20;
ds3000_writereg(state, 0xf8, data);
/* enable packet counters */
data |= 0x20;
ds3000_writereg(state, 0xf8, data);
break;
case SYS_DVBS2:
_ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
ds3000_readreg(state, 0xe1);
if (_ucblocks > state->prevUCBS2)
*ucblocks = _ucblocks - state->prevUCBS2;
else
*ucblocks = state->prevUCBS2 - _ucblocks;
state->prevUCBS2 = _ucblocks;
break;
default:
return -EINVAL;
}
return 0;
}
static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct ds3000_state *state = fe->demodulator_priv;
u8 data;
dprintk("%s(%d)\n", __func__, tone);
if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
return -EINVAL;
}
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
ds3000_writereg(state, 0xa2, data);
switch (tone) {
case SEC_TONE_ON:
dprintk("%s: setting tone on\n", __func__);
data = ds3000_readreg(state, 0xa1);
data &= ~0x43;
data |= 0x04;
ds3000_writereg(state, 0xa1, data);
break;
case SEC_TONE_OFF:
dprintk("%s: setting tone off\n", __func__);
data = ds3000_readreg(state, 0xa2);
data |= 0x80;
ds3000_writereg(state, 0xa2, data);
break;
}
return 0;
}
static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *d)
{
struct ds3000_state *state = fe->demodulator_priv;
int i;
u8 data;
/* Dump DiSEqC message */
dprintk("%s(", __func__);
for (i = 0 ; i < d->msg_len;) {
dprintk("0x%02x", d->msg[i]);
if (++i < d->msg_len)
dprintk(", ");
}
/* enable DiSEqC message send pin */
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
ds3000_writereg(state, 0xa2, data);
/* DiSEqC message */
for (i = 0; i < d->msg_len; i++)
ds3000_writereg(state, 0xa3 + i, d->msg[i]);
data = ds3000_readreg(state, 0xa1);
/* clear DiSEqC message length and status,
enable DiSEqC message send */
data &= ~0xf8;
/* set DiSEqC mode, modulation active during 33 pulses,
set DiSEqC message length */
data |= ((d->msg_len - 1) << 3) | 0x07;
ds3000_writereg(state, 0xa1, data);
/* wait up to 150ms for DiSEqC transmission to complete */
for (i = 0; i < 15; i++) {
data = ds3000_readreg(state, 0xa1);
if ((data & 0x40) == 0)
break;
msleep(10);
}
/* DiSEqC timeout after 150ms */
if (i == 15) {
data = ds3000_readreg(state, 0xa1);
data &= ~0x80;
data |= 0x40;
ds3000_writereg(state, 0xa1, data);
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
data |= 0x80;
ds3000_writereg(state, 0xa2, data);
return -ETIMEDOUT;
}
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
data |= 0x80;
ds3000_writereg(state, 0xa2, data);
return 0;
}
/* Send DiSEqC burst */
static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct ds3000_state *state = fe->demodulator_priv;
int i;
u8 data;
dprintk("%s()\n", __func__);
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
ds3000_writereg(state, 0xa2, data);
/* DiSEqC burst */
if (burst == SEC_MINI_A)
/* Unmodulated tone burst */
ds3000_writereg(state, 0xa1, 0x02);
else if (burst == SEC_MINI_B)
/* Modulated tone burst */
ds3000_writereg(state, 0xa1, 0x01);
else
return -EINVAL;
msleep(13);
for (i = 0; i < 5; i++) {
data = ds3000_readreg(state, 0xa1);
if ((data & 0x40) == 0)
break;
msleep(1);
}
if (i == 5) {
data = ds3000_readreg(state, 0xa1);
data &= ~0x80;
data |= 0x40;
ds3000_writereg(state, 0xa1, data);
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
data |= 0x80;
ds3000_writereg(state, 0xa2, data);
return -ETIMEDOUT;
}
data = ds3000_readreg(state, 0xa2);
data &= ~0xc0;
data |= 0x80;
ds3000_writereg(state, 0xa2, data);
return 0;
}
static void ds3000_release(struct dvb_frontend *fe)
{
struct ds3000_state *state = fe->demodulator_priv;
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 0);
dprintk("%s\n", __func__);
kfree(state);
}
static const struct dvb_frontend_ops ds3000_ops;
struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
struct i2c_adapter *i2c)
{
struct ds3000_state *state;
int ret;
dprintk("%s\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
state->config = config;
state->i2c = i2c;
state->prevUCBS2 = 0;
/* check if the demod is present */
ret = ds3000_readreg(state, 0x00) & 0xfe;
if (ret != 0xe0) {
kfree(state);
printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
return NULL;
}
printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
ds3000_readreg(state, 0x02),
ds3000_readreg(state, 0x01));
memcpy(&state->frontend.ops, &ds3000_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/*
* Some devices like T480 starts with voltage on. Be sure
* to turn voltage off during init, as this can otherwise
* interfere with Unicable SCR systems.
*/
ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
return &state->frontend;
}
EXPORT_SYMBOL_GPL(ds3000_attach);
static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
s32 carrier_offset_khz)
{
struct ds3000_state *state = fe->demodulator_priv;
s32 tmp;
tmp = carrier_offset_khz;
tmp *= 65536;
tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
if (tmp < 0)
tmp += 65536;
ds3000_writereg(state, 0x5f, tmp >> 8);
ds3000_writereg(state, 0x5e, tmp & 0xff);
return 0;
}
static int ds3000_set_frontend(struct dvb_frontend *fe)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int i;
enum fe_status status;
s32 offset_khz;
u32 frequency;
u16 value;
dprintk("%s() ", __func__);
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
/* Tune */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* ds3000 global reset */
ds3000_writereg(state, 0x07, 0x80);
ds3000_writereg(state, 0x07, 0x00);
/* ds3000 built-in uC reset */
ds3000_writereg(state, 0xb2, 0x01);
/* ds3000 software reset */
ds3000_writereg(state, 0x00, 0x01);
switch (c->delivery_system) {
case SYS_DVBS:
/* initialise the demod in DVB-S mode */
for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
ds3000_writereg(state,
ds3000_dvbs_init_tab[i],
ds3000_dvbs_init_tab[i + 1]);
value = ds3000_readreg(state, 0xfe);
value &= 0xc0;
value |= 0x1b;
ds3000_writereg(state, 0xfe, value);
break;
case SYS_DVBS2:
/* initialise the demod in DVB-S2 mode */
for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
ds3000_writereg(state,
ds3000_dvbs2_init_tab[i],
ds3000_dvbs2_init_tab[i + 1]);
if (c->symbol_rate >= 30000000)
ds3000_writereg(state, 0xfe, 0x54);
else
ds3000_writereg(state, 0xfe, 0x98);
break;
default:
return -EINVAL;
}
/* enable 27MHz clock output */
ds3000_writereg(state, 0x29, 0x80);
/* enable ac coupling */
ds3000_writereg(state, 0x25, 0x8a);
if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
(c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
__func__, c->symbol_rate,
ds3000_ops.info.symbol_rate_min,
ds3000_ops.info.symbol_rate_max);
return -EINVAL;
}
/* enhance symbol rate performance */
if ((c->symbol_rate / 1000) <= 5000) {
value = 29777 / (c->symbol_rate / 1000) + 1;
if (value % 2 != 0)
value++;
ds3000_writereg(state, 0xc3, 0x0d);
ds3000_writereg(state, 0xc8, value);
ds3000_writereg(state, 0xc4, 0x10);
ds3000_writereg(state, 0xc7, 0x0e);
} else if ((c->symbol_rate / 1000) <= 10000) {
value = 92166 / (c->symbol_rate / 1000) + 1;
if (value % 2 != 0)
value++;
ds3000_writereg(state, 0xc3, 0x07);
ds3000_writereg(state, 0xc8, value);
ds3000_writereg(state, 0xc4, 0x09);
ds3000_writereg(state, 0xc7, 0x12);
} else if ((c->symbol_rate / 1000) <= 20000) {
value = 64516 / (c->symbol_rate / 1000) + 1;
ds3000_writereg(state, 0xc3, value);
ds3000_writereg(state, 0xc8, 0x0e);
ds3000_writereg(state, 0xc4, 0x07);
ds3000_writereg(state, 0xc7, 0x18);
} else {
value = 129032 / (c->symbol_rate / 1000) + 1;
ds3000_writereg(state, 0xc3, value);
ds3000_writereg(state, 0xc8, 0x0a);
ds3000_writereg(state, 0xc4, 0x05);
ds3000_writereg(state, 0xc7, 0x24);
}
/* normalized symbol rate rounded to the closest integer */
value = (((c->symbol_rate / 1000) << 16) +
(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
ds3000_writereg(state, 0x61, value & 0x00ff);
ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
/* co-channel interference cancellation disabled */
ds3000_writereg(state, 0x56, 0x00);
/* equalizer disabled */
ds3000_writereg(state, 0x76, 0x00);
/*ds3000_writereg(state, 0x08, 0x03);
ds3000_writereg(state, 0xfd, 0x22);
ds3000_writereg(state, 0x08, 0x07);
ds3000_writereg(state, 0xfd, 0x42);
ds3000_writereg(state, 0x08, 0x07);*/
if (state->config->ci_mode) {
switch (c->delivery_system) {
case SYS_DVBS:
default:
ds3000_writereg(state, 0xfd, 0x80);
break;
case SYS_DVBS2:
ds3000_writereg(state, 0xfd, 0x01);
break;
}
}
/* ds3000 out of software reset */
ds3000_writereg(state, 0x00, 0x00);
/* start ds3000 built-in uC */
ds3000_writereg(state, 0xb2, 0x00);
if (fe->ops.tuner_ops.get_frequency) {
fe->ops.tuner_ops.get_frequency(fe, &frequency);
offset_khz = frequency - c->frequency;
ds3000_set_carrier_offset(fe, offset_khz);
}
for (i = 0; i < 30 ; i++) {
ds3000_read_status(fe, &status);
if (status & FE_HAS_LOCK)
break;
msleep(10);
}
return 0;
}
static int ds3000_tune(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
if (re_tune) {
int ret = ds3000_set_frontend(fe);
if (ret)
return ret;
}
*delay = HZ / 5;
return ds3000_read_status(fe, status);
}
static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
{
struct ds3000_state *state = fe->demodulator_priv;
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 0);
dprintk("%s()\n", __func__);
return DVBFE_ALGO_HW;
}
/*
* Initialise or wake up device
*
* Power config will reset and load initial firmware if required
*/
static int ds3000_initfe(struct dvb_frontend *fe)
{
struct ds3000_state *state = fe->demodulator_priv;
int ret;
dprintk("%s()\n", __func__);
/* hard reset */
ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
msleep(1);
/* Load the firmware if required */
ret = ds3000_firmware_ondemand(fe);
if (ret != 0) {
printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
return ret;
}
return 0;
}
static const struct dvb_frontend_ops ds3000_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "Montage Technology DS3000",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = ds3000_release,
.init = ds3000_initfe,
.i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
.read_status = ds3000_read_status,
.read_ber = ds3000_read_ber,
.read_signal_strength = ds3000_read_signal_strength,
.read_snr = ds3000_read_snr,
.read_ucblocks = ds3000_read_ucblocks,
.set_voltage = ds3000_set_voltage,
.set_tone = ds3000_set_tone,
.diseqc_send_master_cmd = ds3000_send_diseqc_msg,
.diseqc_send_burst = ds3000_diseqc_send_burst,
.get_frontend_algo = ds3000_get_algo,
.set_frontend = ds3000_set_frontend,
.tune = ds3000_tune,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
MODULE_AUTHOR("Konstantin Dimitrov <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/ds3000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* stv0367.c
*
* Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
*
* Copyright (C) ST Microelectronics.
* Copyright (C) 2010,2011 NetUP Inc.
* Copyright (C) 2010,2011 Igor M. Liplianin <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/int_log.h>
#include "stv0367.h"
#include "stv0367_defs.h"
#include "stv0367_regs.h"
#include "stv0367_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static int stvdebug;
module_param_named(debug, stvdebug, int, 0644);
static int i2cdebug;
module_param_named(i2c_debug, i2cdebug, int, 0644);
#define dprintk(args...) \
do { \
if (stvdebug) \
printk(KERN_DEBUG args); \
} while (0)
/* DVB-C */
enum active_demod_state { demod_none, demod_ter, demod_cab };
struct stv0367cab_state {
enum stv0367_cab_signal_type state;
u32 mclk;
u32 adc_clk;
s32 search_range;
s32 derot_offset;
/* results */
int locked; /* channel found */
u32 freq_khz; /* found frequency (in kHz) */
u32 symbol_rate; /* found symbol rate (in Bds) */
enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
};
struct stv0367ter_state {
/* DVB-T */
enum stv0367_ter_signal_type state;
enum stv0367_ter_if_iq_mode if_iq_mode;
enum stv0367_ter_mode mode;/* mode 2K or 8K */
enum fe_guard_interval guard;
enum stv0367_ter_hierarchy hierarchy;
u32 frequency;
enum fe_spectral_inversion sense; /* current search spectrum */
u8 force; /* force mode/guard */
u8 bw; /* channel width 6, 7 or 8 in MHz */
u8 pBW; /* channel width used during previous lock */
u32 pBER;
u32 pPER;
u32 ucblocks;
s8 echo_pos; /* echo position */
u8 first_lock;
u8 unlock_counter;
u32 agc_val;
};
struct stv0367_state {
struct dvb_frontend fe;
struct i2c_adapter *i2c;
/* config settings */
const struct stv0367_config *config;
u8 chip_id;
/* DVB-C */
struct stv0367cab_state *cab_state;
/* DVB-T */
struct stv0367ter_state *ter_state;
/* flags for operation control */
u8 use_i2c_gatectrl;
u8 deftabs;
u8 reinit_on_setfrontend;
u8 auto_if_khz;
enum active_demod_state activedemod;
};
#define RF_LOOKUP_TABLE_SIZE 31
#define RF_LOOKUP_TABLE2_SIZE 16
/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
{/*AGC1*/
48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 80, 83, 85, 88,
}, {/*RF(dbm)*/
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
49, 50, 52, 53, 54, 55, 56,
}
};
/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
{/*AGC2*/
28, 29, 31, 32, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43, 44, 45,
}, {/*RF(dbm)*/
57, 58, 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72,
}
};
static
int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
{
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = len + 2
};
int ret;
if (2 + len > sizeof(buf)) {
printk(KERN_WARNING
"%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
buf[0] = MSB(reg);
buf[1] = LSB(reg);
memcpy(buf + 2, data, len);
if (i2cdebug)
printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
state->config->demod_address, reg, buf[2]);
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
__func__, state->config->demod_address, reg, buf[2]);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
{
u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return stv0367_writeregs(state, reg, &tmp, 1);
}
static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
{
u8 b0[] = { 0, 0 };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 2
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
int ret;
b0[0] = MSB(reg);
b0[1] = LSB(reg);
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
__func__, state->config->demod_address, reg, b1[0]);
if (i2cdebug)
printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
state->config->demod_address, reg, b1[0]);
return b1[0];
}
static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
{
u8 position = 0, i = 0;
(*mask) = label & 0xff;
while ((position == 0) && (i < 8)) {
position = ((*mask) >> i) & 0x01;
i++;
}
(*pos) = (i - 1);
}
static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
{
u8 reg, mask, pos;
reg = stv0367_readreg(state, (label >> 16) & 0xffff);
extract_mask_pos(label, &mask, &pos);
val = mask & (val << pos);
reg = (reg & (~mask)) | val;
stv0367_writereg(state, (label >> 16) & 0xffff, reg);
}
static void stv0367_setbits(u8 *reg, u32 label, u8 val)
{
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
val = mask & (val << pos);
(*reg) = ((*reg) & (~mask)) | val;
}
static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
{
u8 val = 0xff;
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
val = stv0367_readreg(state, label >> 16);
val = (val & mask) >> pos;
return val;
}
#if 0 /* Currently, unused */
static u8 stv0367_getbits(u8 reg, u32 label)
{
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
return (reg & mask) >> pos;
}
#endif
static void stv0367_write_table(struct stv0367_state *state,
const struct st_register *deftab)
{
int i = 0;
while (1) {
if (!deftab[i].addr)
break;
stv0367_writereg(state, deftab[i].addr, deftab[i].value);
i++;
}
}
static void stv0367_pll_setup(struct stv0367_state *state,
u32 icspeed, u32 xtal)
{
/* note on regs: R367TER_* and R367CAB_* defines each point to
* 0xf0d8, so just use R367TER_ for both cases
*/
switch (icspeed) {
case STV0367_ICSPEED_58000:
switch (xtal) {
default:
case 27000000:
dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
/* PLLMDIV: 27, PLLNDIV: 232 */
stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
break;
}
break;
default:
case STV0367_ICSPEED_53125:
switch (xtal) {
/* set internal freq to 53.125MHz */
case 16000000:
stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
break;
case 25000000:
stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
break;
default:
case 27000000:
dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
break;
case 30000000:
stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
break;
}
}
stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
}
static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
{
if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
*ifkhz = *ifkhz / 1000; /* hz -> khz */
} else
*ifkhz = state->config->if_khz;
return 0;
}
static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0367_state *state = fe->demodulator_priv;
u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
dprintk("%s:\n", __func__);
if (enable) {
stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
} else {
stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
}
stv0367_writereg(state, R367TER_I2CRPT, tmp);
return 0;
}
static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
{
struct dvb_frontend_ops *frontend_ops = &fe->ops;
struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
u32 freq = 0;
int err = 0;
dprintk("%s:\n", __func__);
if (tuner_ops->get_frequency) {
err = tuner_ops->get_frequency(fe, &freq);
if (err < 0) {
printk(KERN_ERR "%s: Invalid parameter\n", __func__);
return err;
}
dprintk("%s: frequency=%d\n", __func__, freq);
} else
return -1;
return freq;
}
static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
{
{0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
{0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
{0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
{0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
{0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
{0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
}, {
{0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
{0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
{0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
{0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
{0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
{0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
}, {
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
}
};
static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
{
{0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
{0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
{0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
{0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
{0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
{0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
}, {
{0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
{0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
{0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
{0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
{0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
{0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
}, {
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
}
};
static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
{
{0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
{0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
{0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
{0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
{0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
{0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
}, {
{0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
{0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
{0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
{0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
{0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
{0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
}, {
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
}
};
static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
{
u32 mclk_Hz = 0; /* master clock frequency (Hz) */
u32 m, n, p;
dprintk("%s:\n", __func__);
if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
if (n == 0)
n = n + 1;
m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
if (m == 0)
m = m + 1;
p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
if (p > 5)
p = 5;
mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
n, m, p, mclk_Hz, ExtClk_Hz);
} else
mclk_Hz = ExtClk_Hz;
dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
return mclk_Hz;
}
static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
u16 CellsCoeffs[3][6][5], u32 DemodXtal)
{
int i, j, k, freq;
dprintk("%s:\n", __func__);
freq = stv0367ter_get_mclk(state, DemodXtal);
if (freq == 53125000)
k = 1; /* equivalent to Xtal 25M on 362*/
else if (freq == 54000000)
k = 0; /* equivalent to Xtal 27M on 362*/
else if (freq == 52500000)
k = 2; /* equivalent to Xtal 30M on 362*/
else
return 0;
for (i = 1; i <= 6; i++) {
stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
for (j = 1; j <= 5; j++) {
stv0367_writereg(state,
(R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
MSB(CellsCoeffs[k][i-1][j-1]));
stv0367_writereg(state,
(R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
LSB(CellsCoeffs[k][i-1][j-1]));
}
}
return 1;
}
static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
{
dprintk("%s:\n", __func__);
stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
/* Lock detect 1 */
stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
/* Lock detect 2 */
stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
/* Lock detect 3 */
stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
/* Lock detect 4 */
stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
}
static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
u32 DemodXtalValue)
{
dprintk("%s:\n", __func__);
stv0367_writebits(state, F367TER_NRST_IIR, 0);
switch (Bandwidth) {
case 6:
if (!stv0367ter_filt_coeff_init(state,
CellsCoeffs_6MHz_367cofdm,
DemodXtalValue))
return 0;
break;
case 7:
if (!stv0367ter_filt_coeff_init(state,
CellsCoeffs_7MHz_367cofdm,
DemodXtalValue))
return 0;
break;
case 8:
if (!stv0367ter_filt_coeff_init(state,
CellsCoeffs_8MHz_367cofdm,
DemodXtalValue))
return 0;
break;
default:
return 0;
}
stv0367_writebits(state, F367TER_NRST_IIR, 1);
return 1;
}
static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
{
u8 com_n;
dprintk("%s:\n", __func__);
com_n = stv0367_readbits(state, F367TER_COM_N);
stv0367_writebits(state, F367TER_COM_N, 0x07);
stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
stv0367_writebits(state, F367TER_COM_N, com_n);
}
static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
{
int local_tempo = 0;
switch (mode) {
case 0:
local_tempo = tempo1;
break;
case 1:
local_tempo = tempo2;
break ;
case 2:
local_tempo = tempo3;
break;
default:
break;
}
/* msleep(local_tempo); */
return local_tempo;
}
static enum
stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
{
int wd = 100;
unsigned short int SYR_var;
s32 SYRStatus;
dprintk("%s:\n", __func__);
SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
while ((!SYR_var) && (wd > 0)) {
usleep_range(2000, 3000);
wd -= 2;
SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
}
if (!SYR_var)
SYRStatus = FE_TER_NOSYMBOL;
else
SYRStatus = FE_TER_SYMBOLOK;
dprintk("stv0367ter_check_syr SYRStatus %s\n",
SYR_var == 0 ? "No Symbol" : "OK");
return SYRStatus;
}
static enum
stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
s32 FFTmode)
{
s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
int wd = 0;
dprintk("%s:\n", __func__);
switch (FFTmode) {
case 0: /*2k mode*/
CPAMPMin = 20;
wd = 10;
break;
case 1: /*8k mode*/
CPAMPMin = 80;
wd = 55;
break;
case 2: /*4k mode*/
CPAMPMin = 40;
wd = 30;
break;
default:
CPAMPMin = 0xffff; /*drives to NOCPAMP */
break;
}
dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
usleep_range(1000, 2000);
wd -= 1;
CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
/*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
}
dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
if (CPAMPvalue < CPAMPMin) {
CPAMPStatus = FE_TER_NOCPAMP;
dprintk("%s: CPAMP failed\n", __func__);
} else {
dprintk("%s: CPAMP OK !\n", __func__);
CPAMPStatus = FE_TER_CPAMPOK;
}
return CPAMPStatus;
}
static enum stv0367_ter_signal_type
stv0367ter_lock_algo(struct stv0367_state *state)
{
enum stv0367_ter_signal_type ret_flag;
short int wd, tempo;
u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
u8 tmp, tmp2;
dprintk("%s:\n", __func__);
if (state == NULL)
return FE_TER_SWNOK;
try = 0;
do {
ret_flag = FE_TER_LOCKOK;
stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
if (state->config->if_iq_mode != 0)
stv0367_writebits(state, F367TER_COM_N, 0x07);
stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
stv0367_writebits(state, F367TER_MODE, 0);
stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
usleep_range(5000, 10000);
stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
return FE_TER_NOSYMBOL;
else { /*
if chip locked on wrong mode first try,
it must lock correctly second try */
mode = stv0367_readbits(state, F367TER_SYR_MODE);
if (stv0367ter_check_cpamp(state, mode) ==
FE_TER_NOCPAMP) {
if (try == 0)
ret_flag = FE_TER_NOCPAMP;
}
}
try++;
} while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
tmp = stv0367_readreg(state, R367TER_SYR_STAT);
tmp2 = stv0367_readreg(state, R367TER_STATUS);
dprintk("state=%p\n", state);
dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
mode, tmp, tmp2);
tmp = stv0367_readreg(state, R367TER_PRVIT);
tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
dprintk("GAIN_SRC1=0x%x\n", tmp);
if ((mode != 0) && (mode != 1) && (mode != 2))
return FE_TER_SWNOK;
/*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
/*suppress EPQ auto for SYR_GARD 1/16 or 1/32
and set channel predictor in automatic */
#if 0
switch (guard) {
case 0:
case 1:
stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
break;
case 2:
case 3:
stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
break;
default:
return FE_TER_SWNOK;
}
#endif
/*reset fec an reedsolo FOR 367 only*/
stv0367_writebits(state, F367TER_RST_SFEC, 1);
stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
usleep_range(1000, 2000);
stv0367_writebits(state, F367TER_RST_SFEC, 0);
stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
u_var1 = stv0367_readbits(state, F367TER_LK);
u_var2 = stv0367_readbits(state, F367TER_PRF);
u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
/* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
wd = stv0367ter_duration(mode, 125, 500, 250);
tempo = stv0367ter_duration(mode, 4, 16, 8);
/*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
usleep_range(1000 * tempo, 1000 * (tempo + 1));
wd -= tempo;
u_var1 = stv0367_readbits(state, F367TER_LK);
u_var2 = stv0367_readbits(state, F367TER_PRF);
u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
/*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
}
if (!u_var1)
return FE_TER_NOLOCK;
if (!u_var2)
return FE_TER_NOPRFOUND;
if (!u_var3)
return FE_TER_NOTPS;
guard = stv0367_readbits(state, F367TER_SYR_GUARD);
stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
switch (guard) {
case 0:
case 1:
stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
/*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
stv0367_writebits(state, F367TER_SYR_FILTER, 0);
break;
case 2:
case 3:
stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
/*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
stv0367_writebits(state, F367TER_SYR_FILTER, 1);
break;
default:
return FE_TER_SWNOK;
}
/* apply Sfec workaround if 8K 64QAM CR!=1/2*/
if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
(mode == 1) &&
(stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
} else
stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
wd = stv0367ter_duration(mode, 125, 500, 250);
u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
while ((!u_var4) && (wd >= 0)) {
usleep_range(1000 * tempo, 1000 * (tempo + 1));
wd -= tempo;
u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
}
if (!u_var4)
return FE_TER_NOLOCK;
/* for 367 leave COM_N at 0x7 for IQ_mode*/
/*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
tempo=0;
while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
(stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
ChipWaitOrAbort(state,1);
tempo+=1;
}
stv0367_writebits(state,F367TER_COM_N,0x17);
} */
stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
dprintk("FE_TER_LOCKOK !!!\n");
return FE_TER_LOCKOK;
}
static void stv0367ter_set_ts_mode(struct stv0367_state *state,
enum stv0367_ts_mode PathTS)
{
dprintk("%s:\n", __func__);
if (state == NULL)
return;
stv0367_writebits(state, F367TER_TS_DIS, 0);
switch (PathTS) {
default:
/*for removing warning :default we can assume in parallel mode*/
case STV0367_PARALLEL_PUNCT_CLOCK:
stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
break;
case STV0367_SERIAL_PUNCT_CLOCK:
stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
break;
}
}
static void stv0367ter_set_clk_pol(struct stv0367_state *state,
enum stv0367_clk_pol clock)
{
dprintk("%s:\n", __func__);
if (state == NULL)
return;
switch (clock) {
case STV0367_RISINGEDGE_CLOCK:
stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
break;
case STV0367_FALLINGEDGE_CLOCK:
stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
break;
/*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
default:
stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
break;
}
}
#if 0
static void stv0367ter_core_sw(struct stv0367_state *state)
{
dprintk("%s:\n", __func__);
stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
msleep(350);
}
#endif
static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
{
struct stv0367_state *state = fe->demodulator_priv;
dprintk("%s:\n", __func__);
if (standby_on) {
stv0367_writebits(state, F367TER_STDBY, 1);
stv0367_writebits(state, F367TER_STDBY_FEC, 1);
stv0367_writebits(state, F367TER_STDBY_CORE, 1);
} else {
stv0367_writebits(state, F367TER_STDBY, 0);
stv0367_writebits(state, F367TER_STDBY_FEC, 0);
stv0367_writebits(state, F367TER_STDBY_CORE, 0);
}
return 0;
}
static int stv0367ter_sleep(struct dvb_frontend *fe)
{
return stv0367ter_standby(fe, 1);
}
static int stv0367ter_init(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
dprintk("%s:\n", __func__);
ter_state->pBER = 0;
stv0367_write_table(state,
stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
/*Set TS1 and TS2 to serial or parallel mode */
stv0367ter_set_ts_mode(state, state->config->ts_mode);
stv0367ter_set_clk_pol(state, state->config->clk_pol);
state->chip_id = stv0367_readreg(state, R367TER_ID);
ter_state->first_lock = 0;
ter_state->unlock_counter = 2;
return 0;
}
static int stv0367ter_algo(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
int offset = 0, tempo = 0;
u8 u_var;
u8 /*constell,*/ counter;
s8 step;
s32 timing_offset = 0;
u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
dprintk("%s:\n", __func__);
stv0367_get_if_khz(state, &ifkhz);
ter_state->frequency = p->frequency;
ter_state->force = FE_TER_FORCENONE
+ stv0367_readbits(state, F367TER_FORCE) * 2;
ter_state->if_iq_mode = state->config->if_iq_mode;
switch (state->config->if_iq_mode) {
case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
stv0367_writebits(state, F367TER_TUNER_BB, 0);
stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
break;
case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
stv0367_writebits(state, F367TER_TUNER_BB, 0);
stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
break;
case FE_TER_IQ_TUNER: /* IQ mode */
dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
stv0367_writebits(state, F367TER_TUNER_BB, 1);
stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
break;
default:
printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
return -EINVAL;
}
usleep_range(5000, 7000);
switch (p->inversion) {
case INVERSION_AUTO:
default:
dprintk("%s: inversion AUTO\n", __func__);
if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
stv0367_writebits(state, F367TER_IQ_INVERT,
ter_state->sense);
else
stv0367_writebits(state, F367TER_INV_SPECTR,
ter_state->sense);
break;
case INVERSION_ON:
case INVERSION_OFF:
if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
stv0367_writebits(state, F367TER_IQ_INVERT,
p->inversion);
else
stv0367_writebits(state, F367TER_INV_SPECTR,
p->inversion);
break;
}
if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
(ter_state->pBW != ter_state->bw)) {
stv0367ter_agc_iir_lock_detect_set(state);
/*set fine agc target to 180 for LPIF or IQ mode*/
/* set Q_AGCTarget */
stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
/*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
/* set Q_AGCTarget */
stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
/*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
if (!stv0367_iir_filt_init(state, ter_state->bw,
state->config->xtal))
return -EINVAL;
/*set IIR filter once for 6,7 or 8MHz BW*/
ter_state->pBW = ter_state->bw;
stv0367ter_agc_iir_rst(state);
}
if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
else
stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
temp = (int)
((((ter_state->bw * 64 * (1 << 15) * 100)
/ (InternalFreq)) * 10) / 7);
stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
temp = temp / 2;
stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
stv0367_readbits(state, F367TER_GAIN_SRC_LO);
temp = (int)
((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
dprintk("DEROT temp=0x%x\n", temp);
stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
ter_state->echo_pos = 0;
ter_state->ucblocks = 0; /* liplianin */
ter_state->pBER = 0; /* liplianin */
stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
return 0;
ter_state->state = FE_TER_LOCKOK;
ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
ter_state->first_lock = 1; /* we know sense now :) */
ter_state->agc_val =
(stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
(stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
(stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
/* Carrier offset calculation */
stv0367_writebits(state, F367TER_FREEZE, 1);
offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
stv0367_writebits(state, F367TER_FREEZE, 0);
if (offset > 8388607)
offset -= 16777216;
offset = offset * 2 / 16384;
if (ter_state->mode == FE_TER_MODE_2K)
offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
else if (ter_state->mode == FE_TER_MODE_4K)
offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
else if (ter_state->mode == FE_TER_MODE_8K)
offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
(stv0367_readbits(state,
F367TER_STATUS_INV_SPECRUM) == 1)))
offset = offset * -1;
}
if (ter_state->bw == 6)
offset = (offset * 6) / 8;
else if (ter_state->bw == 7)
offset = (offset * 7) / 8;
ter_state->frequency += offset;
tempo = 10; /* exit even if timing_offset stays null */
while ((timing_offset == 0) && (tempo > 0)) {
usleep_range(10000, 20000); /*was 20ms */
/* fine tuning of timing offset if required */
timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
+ 256 * stv0367_readbits(state,
F367TER_TRL_TOFFSET_HI);
if (timing_offset >= 32768)
timing_offset -= 65536;
trl_nomrate = (512 * stv0367_readbits(state,
F367TER_TRL_NOMRATE_HI)
+ stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
+ stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
timing_offset = ((signed)(1000000 / trl_nomrate) *
timing_offset) / 2048;
tempo--;
}
if (timing_offset <= 0) {
timing_offset = (timing_offset - 11) / 22;
step = -1;
} else {
timing_offset = (timing_offset + 11) / 22;
step = 1;
}
for (counter = 0; counter < abs(timing_offset); counter++) {
trl_nomrate += step;
stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
trl_nomrate % 2);
stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
trl_nomrate / 2);
usleep_range(1000, 2000);
}
usleep_range(5000, 6000);
/* unlocks could happen in case of trl centring big step,
then a core off/on restarts demod */
u_var = stv0367_readbits(state, F367TER_LK);
if (!u_var) {
stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
msleep(20);
stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
}
return 0;
}
static int stv0367ter_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
/*u8 trials[2]; */
s8 num_trials, index;
u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
if (state->reinit_on_setfrontend)
stv0367ter_init(fe);
if (fe->ops.tuner_ops.set_params) {
if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
switch (p->transmission_mode) {
default:
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_2K:
ter_state->mode = FE_TER_MODE_2K;
break;
/* case TRANSMISSION_MODE_4K:
pLook.mode = FE_TER_MODE_4K;
break;*/
case TRANSMISSION_MODE_8K:
ter_state->mode = FE_TER_MODE_8K;
break;
}
switch (p->guard_interval) {
default:
case GUARD_INTERVAL_1_32:
case GUARD_INTERVAL_1_16:
case GUARD_INTERVAL_1_8:
case GUARD_INTERVAL_1_4:
ter_state->guard = p->guard_interval;
break;
case GUARD_INTERVAL_AUTO:
ter_state->guard = GUARD_INTERVAL_1_32;
break;
}
switch (p->bandwidth_hz) {
case 6000000:
ter_state->bw = FE_TER_CHAN_BW_6M;
break;
case 7000000:
ter_state->bw = FE_TER_CHAN_BW_7M;
break;
case 8000000:
default:
ter_state->bw = FE_TER_CHAN_BW_8M;
}
ter_state->hierarchy = FE_TER_HIER_NONE;
switch (p->inversion) {
case INVERSION_OFF:
case INVERSION_ON:
num_trials = 1;
break;
default:
num_trials = 2;
if (ter_state->first_lock)
num_trials = 1;
break;
}
ter_state->state = FE_TER_NOLOCK;
index = 0;
while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
if (!ter_state->first_lock) {
if (p->inversion == INVERSION_AUTO)
ter_state->sense = SenseTrials[index];
}
stv0367ter_algo(fe);
if ((ter_state->state == FE_TER_LOCKOK) &&
(p->inversion == INVERSION_AUTO) &&
(index == 1)) {
/* invert spectrum sense */
SenseTrials[index] = SenseTrials[0];
SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
}
index++;
}
return 0;
}
static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
u32 errs = 0;
/*wait for counting completion*/
if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
errs =
((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
* (1 << 16))
+ ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
* (1 << 8))
+ ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
ter_state->ucblocks = errs;
}
(*ucblocks) = ter_state->ucblocks;
return 0;
}
static int stv0367ter_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
enum stv0367_ter_mode mode;
int constell = 0,/* snr = 0,*/ Data = 0;
p->frequency = stv0367_get_tuner_freq(fe);
if ((int)p->frequency < 0)
p->frequency = -p->frequency;
constell = stv0367_readbits(state, F367TER_TPS_CONST);
if (constell == 0)
p->modulation = QPSK;
else if (constell == 1)
p->modulation = QAM_16;
else
p->modulation = QAM_64;
p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
/* Get the Hierarchical mode */
Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
switch (Data) {
case 0:
p->hierarchy = HIERARCHY_NONE;
break;
case 1:
p->hierarchy = HIERARCHY_1;
break;
case 2:
p->hierarchy = HIERARCHY_2;
break;
case 3:
p->hierarchy = HIERARCHY_4;
break;
default:
p->hierarchy = HIERARCHY_AUTO;
break; /* error */
}
/* Get the FEC Rate */
if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
else
Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
switch (Data) {
case 0:
p->code_rate_HP = FEC_1_2;
break;
case 1:
p->code_rate_HP = FEC_2_3;
break;
case 2:
p->code_rate_HP = FEC_3_4;
break;
case 3:
p->code_rate_HP = FEC_5_6;
break;
case 4:
p->code_rate_HP = FEC_7_8;
break;
default:
p->code_rate_HP = FEC_AUTO;
break; /* error */
}
mode = stv0367_readbits(state, F367TER_SYR_MODE);
switch (mode) {
case FE_TER_MODE_2K:
p->transmission_mode = TRANSMISSION_MODE_2K;
break;
/* case FE_TER_MODE_4K:
p->transmission_mode = TRANSMISSION_MODE_4K;
break;*/
case FE_TER_MODE_8K:
p->transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
p->transmission_mode = TRANSMISSION_MODE_AUTO;
}
p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
return 0;
}
static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
u32 snru32 = 0;
int cpt = 0;
u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
while (cpt < 10) {
usleep_range(2000, 3000);
if (cut == 0x50) /*cut 1.0 cut 1.1*/
snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
else /*cu2.0*/
snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
cpt++;
}
snru32 /= 10;/*average on 10 values*/
return snru32;
}
static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
{
u32 snrval = stv0367ter_snr_readreg(fe);
*snr = snrval / 1000;
return 0;
}
#if 0
static int stv0367ter_status(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
int locked = FALSE;
locked = (stv0367_readbits(state, F367TER_LK));
if (!locked)
ter_state->unlock_counter += 1;
else
ter_state->unlock_counter = 0;
if (ter_state->unlock_counter > 2) {
if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
(!stv0367_readbits(state, F367TER_LK))) {
stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
usleep_range(2000, 3000);
stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
msleep(350);
locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
(stv0367_readbits(state, F367TER_LK));
}
}
return locked;
}
#endif
static int stv0367ter_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct stv0367_state *state = fe->demodulator_priv;
dprintk("%s:\n", __func__);
*status = 0;
if (stv0367_readbits(state, F367TER_LK)) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
| FE_HAS_SYNC | FE_HAS_LOCK;
dprintk("%s: stv0367 has locked\n", __func__);
}
return 0;
}
static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367ter_state *ter_state = state->ter_state;
u32 Errors = 0, tber = 0, temporary = 0;
int abc = 0, def = 0;
/*wait for counting completion*/
if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
* (1 << 16))
+ ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
* (1 << 8))
+ ((u32)stv0367_readbits(state,
F367TER_SFEC_ERR_CNT_LO));
/*measurement not completed, load previous value*/
else {
tber = ter_state->pBER;
return 0;
}
abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
if (Errors == 0) {
tber = 0;
} else if (abc == 0x7) {
if (Errors <= 4) {
temporary = (Errors * 1000000000) / (8 * (1 << 14));
} else if (Errors <= 42) {
temporary = (Errors * 100000000) / (8 * (1 << 14));
temporary = temporary * 10;
} else if (Errors <= 429) {
temporary = (Errors * 10000000) / (8 * (1 << 14));
temporary = temporary * 100;
} else if (Errors <= 4294) {
temporary = (Errors * 1000000) / (8 * (1 << 14));
temporary = temporary * 1000;
} else if (Errors <= 42949) {
temporary = (Errors * 100000) / (8 * (1 << 14));
temporary = temporary * 10000;
} else if (Errors <= 429496) {
temporary = (Errors * 10000) / (8 * (1 << 14));
temporary = temporary * 100000;
} else { /*if (Errors<4294967) 2^22 max error*/
temporary = (Errors * 1000) / (8 * (1 << 14));
temporary = temporary * 100000; /* still to *10 */
}
/* Byte error*/
if (def == 2)
/*tber=Errors/(8*(1 <<14));*/
tber = temporary;
else if (def == 3)
/*tber=Errors/(8*(1 <<16));*/
tber = temporary / 4;
else if (def == 4)
/*tber=Errors/(8*(1 <<18));*/
tber = temporary / 16;
else if (def == 5)
/*tber=Errors/(8*(1 <<20));*/
tber = temporary / 64;
else if (def == 6)
/*tber=Errors/(8*(1 <<22));*/
tber = temporary / 256;
else
/* should not pass here*/
tber = 0;
if ((Errors < 4294967) && (Errors > 429496))
tber *= 10;
}
/* save actual value */
ter_state->pBER = tber;
(*ber) = tber;
return 0;
}
#if 0
static u32 stv0367ter_get_per(struct stv0367_state *state)
{
struct stv0367ter_state *ter_state = state->ter_state;
u32 Errors = 0, Per = 0, temporary = 0;
int abc = 0, def = 0, cpt = 0;
while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
(cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
usleep_range(1000, 2000);
Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
* (1 << 16))
+ ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
* (1 << 8))
+ ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
cpt++;
}
abc = stv0367_readbits(state, F367TER_ERR_SRC1);
def = stv0367_readbits(state, F367TER_NUM_EVT1);
if (Errors == 0)
Per = 0;
else if (abc == 0x9) {
if (Errors <= 4) {
temporary = (Errors * 1000000000) / (8 * (1 << 8));
} else if (Errors <= 42) {
temporary = (Errors * 100000000) / (8 * (1 << 8));
temporary = temporary * 10;
} else if (Errors <= 429) {
temporary = (Errors * 10000000) / (8 * (1 << 8));
temporary = temporary * 100;
} else if (Errors <= 4294) {
temporary = (Errors * 1000000) / (8 * (1 << 8));
temporary = temporary * 1000;
} else if (Errors <= 42949) {
temporary = (Errors * 100000) / (8 * (1 << 8));
temporary = temporary * 10000;
} else { /*if(Errors<=429496) 2^16 errors max*/
temporary = (Errors * 10000) / (8 * (1 << 8));
temporary = temporary * 100000;
}
/* pkt error*/
if (def == 2)
/*Per=Errors/(1 << 8);*/
Per = temporary;
else if (def == 3)
/*Per=Errors/(1 << 10);*/
Per = temporary / 4;
else if (def == 4)
/*Per=Errors/(1 << 12);*/
Per = temporary / 16;
else if (def == 5)
/*Per=Errors/(1 << 14);*/
Per = temporary / 64;
else if (def == 6)
/*Per=Errors/(1 << 16);*/
Per = temporary / 256;
else
Per = 0;
}
/* save actual value */
ter_state->pPER = Per;
return Per;
}
#endif
static int stv0367_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings
*fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 1000;
fe_tune_settings->step_size = 0;
fe_tune_settings->max_drift = 0;
return 0;
}
static void stv0367_release(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
kfree(state->ter_state);
kfree(state->cab_state);
kfree(state);
}
static const struct dvb_frontend_ops stv0367ter_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "ST STV0367 DVB-T",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 15625,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
FE_CAN_INVERSION_AUTO |
FE_CAN_MUTE_TS
},
.release = stv0367_release,
.init = stv0367ter_init,
.sleep = stv0367ter_sleep,
.i2c_gate_ctrl = stv0367ter_gate_ctrl,
.set_frontend = stv0367ter_set_frontend,
.get_frontend = stv0367ter_get_frontend,
.get_tune_settings = stv0367_get_tune_settings,
.read_status = stv0367ter_read_status,
.read_ber = stv0367ter_read_ber,/* too slow */
/* .read_signal_strength = stv0367_read_signal_strength,*/
.read_snr = stv0367ter_read_snr,
.read_ucblocks = stv0367ter_read_ucblocks,
};
struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c)
{
struct stv0367_state *state = NULL;
struct stv0367ter_state *ter_state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
if (state == NULL)
goto error;
ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
if (ter_state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
state->config = config;
state->ter_state = ter_state;
state->fe.ops = stv0367ter_ops;
state->fe.demodulator_priv = state;
state->chip_id = stv0367_readreg(state, 0xf000);
/* demod operation options */
state->use_i2c_gatectrl = 1;
state->deftabs = STV0367_DEFTAB_GENERIC;
state->reinit_on_setfrontend = 1;
state->auto_if_khz = 0;
dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
/* check if the demod is there */
if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
goto error;
return &state->fe;
error:
kfree(ter_state);
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0367ter_attach);
static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0367_state *state = fe->demodulator_priv;
dprintk("%s:\n", __func__);
stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
return 0;
}
static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
{
struct stv0367_state *state = fe->demodulator_priv;
u32 mclk_Hz = 0;/* master clock frequency (Hz) */
u32 M, N, P;
if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
if (N == 0)
N = N + 1;
M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
if (M == 0)
M = M + 1;
P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
if (P > 5)
P = 5;
mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
mclk_Hz);
} else
mclk_Hz = ExtClk_Hz;
dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
return mclk_Hz;
}
static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
{
return stv0367cab_get_mclk(fe, ExtClk_Hz);
}
static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
u32 SymbolRate,
enum stv0367cab_mod QAMSize)
{
/* Set QAM size */
stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
/* Set Registers settings specific to the QAM size */
switch (QAMSize) {
case FE_CAB_MOD_QAM4:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
break;
case FE_CAB_MOD_QAM16:
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
break;
case FE_CAB_MOD_QAM32:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
break;
case FE_CAB_MOD_QAM64:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
if (SymbolRate > 4500000) {
stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
} else if (SymbolRate > 2500000) {
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
} else {
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
}
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
break;
case FE_CAB_MOD_QAM128:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
if (SymbolRate > 4500000)
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
else if (SymbolRate > 2500000)
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
else
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
break;
case FE_CAB_MOD_QAM256:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
if (SymbolRate > 4500000)
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
else if (SymbolRate > 2500000)
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
else
stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
break;
case FE_CAB_MOD_QAM512:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
break;
case FE_CAB_MOD_QAM1024:
stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
break;
default:
break;
}
return QAMSize;
}
static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
u32 adc_hz, s32 derot_hz)
{
u32 sampled_if = 0;
u32 adc_khz;
adc_khz = adc_hz / 1000;
dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
if (adc_khz != 0) {
if (derot_hz < 1000000)
derot_hz = adc_hz / 4; /* ZIF operation */
if (derot_hz > adc_hz)
derot_hz = derot_hz - adc_hz;
sampled_if = (u32)derot_hz / 1000;
sampled_if *= 32768;
sampled_if /= adc_khz;
sampled_if *= 256;
}
if (sampled_if > 8388607)
sampled_if = 8388607;
dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
return derot_hz;
}
static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
{
u32 sampled_if;
sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
(stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
(stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
sampled_if /= 256;
sampled_if *= (adc_hz / 1000);
sampled_if += 1;
sampled_if /= 32768;
return sampled_if;
}
static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
u32 mclk_hz, u32 SymbolRate,
enum stv0367cab_mod QAMSize)
{
u32 QamSizeCorr = 0;
u32 u32_tmp = 0, u32_tmp1 = 0;
u32 adp_khz;
dprintk("%s:\n", __func__);
/* Set Correction factor of SRC gain */
switch (QAMSize) {
case FE_CAB_MOD_QAM4:
QamSizeCorr = 1110;
break;
case FE_CAB_MOD_QAM16:
QamSizeCorr = 1032;
break;
case FE_CAB_MOD_QAM32:
QamSizeCorr = 954;
break;
case FE_CAB_MOD_QAM64:
QamSizeCorr = 983;
break;
case FE_CAB_MOD_QAM128:
QamSizeCorr = 957;
break;
case FE_CAB_MOD_QAM256:
QamSizeCorr = 948;
break;
case FE_CAB_MOD_QAM512:
QamSizeCorr = 0;
break;
case FE_CAB_MOD_QAM1024:
QamSizeCorr = 944;
break;
default:
break;
}
/* Transfer ratio calculation */
if (adc_hz != 0) {
u32_tmp = 256 * SymbolRate;
u32_tmp = u32_tmp / adc_hz;
}
stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
/* Symbol rate and SRC gain calculation */
adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
if (adp_khz != 0) {
u32_tmp = SymbolRate;
u32_tmp1 = SymbolRate;
if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
/* Symbol rate calculation */
u32_tmp *= 2048; /* 2048 = 2^11 */
u32_tmp = u32_tmp / adp_khz;
u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
u32_tmp /= 125 ; /* 125 = 1000/2^3 */
u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
/* SRC Gain Calculation */
u32_tmp1 *= 2048; /* *2*2^10 */
u32_tmp1 /= 439; /* *2/878 */
u32_tmp1 *= 256; /* *2^8 */
u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
u32_tmp1 = u32_tmp1 / 10000000;
} else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
/* Symbol rate calculation */
u32_tmp *= 1024 ; /* 1024 = 2**10 */
u32_tmp = u32_tmp / adp_khz;
u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
u32_tmp /= 125 ; /* 125 = 1000/2**3 */
u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
/* SRC Gain Calculation */
u32_tmp1 *= 1024; /* *2*2^9 */
u32_tmp1 /= 439; /* *2/878 */
u32_tmp1 *= 256; /* *2^8 */
u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
u32_tmp1 = u32_tmp1 / 5000000;
} else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
/* Symbol rate calculation */
u32_tmp *= 512 ; /* 512 = 2**9 */
u32_tmp = u32_tmp / adp_khz;
u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
u32_tmp /= 125 ; /* 125 = 1000/2**3 */
u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
/* SRC Gain Calculation */
u32_tmp1 *= 512; /* *2*2^8 */
u32_tmp1 /= 439; /* *2/878 */
u32_tmp1 *= 256; /* *2^8 */
u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
u32_tmp1 = u32_tmp1 / 2500000;
} else {
/* Symbol rate calculation */
u32_tmp *= 256 ; /* 256 = 2**8 */
u32_tmp = u32_tmp / adp_khz;
u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
u32_tmp /= 125 ; /* 125 = 1000/2**3 */
u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
/* SRC Gain Calculation */
u32_tmp1 *= 256; /* 2*2^7 */
u32_tmp1 /= 439; /* *2/878 */
u32_tmp1 *= 256; /* *2^8 */
u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
u32_tmp1 = u32_tmp1 / 1250000;
}
}
#if 0
/* Filters' coefficients are calculated and written
into registers only if the filters are enabled */
if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
SymbolRate);
/* AllPass filter must be enabled
when the adjacents filter is used */
stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
} else
/* AllPass filter must be disabled
when the adjacents filter is not used */
#endif
stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
return SymbolRate ;
}
static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
{
u32 regsym;
u32 adp_khz;
regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
(stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
(stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
(stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
if (regsym < 134217728) { /* 134217728L = 2**27*/
regsym = regsym * 32; /* 32 = 2**5 */
regsym = regsym / 32768; /* 32768L = 2**15 */
regsym = adp_khz * regsym; /* AdpClk in kHz */
regsym = regsym / 128; /* 128 = 2**7 */
regsym *= 125 ; /* 125 = 1000/2**3 */
regsym /= 2048 ; /* 2048 = 2**11 */
} else if (regsym < 268435456) { /* 268435456L = 2**28 */
regsym = regsym * 16; /* 16 = 2**4 */
regsym = regsym / 32768; /* 32768L = 2**15 */
regsym = adp_khz * regsym; /* AdpClk in kHz */
regsym = regsym / 128; /* 128 = 2**7 */
regsym *= 125 ; /* 125 = 1000/2**3*/
regsym /= 1024 ; /* 256 = 2**10*/
} else if (regsym < 536870912) { /* 536870912L = 2**29*/
regsym = regsym * 8; /* 8 = 2**3 */
regsym = regsym / 32768; /* 32768L = 2**15 */
regsym = adp_khz * regsym; /* AdpClk in kHz */
regsym = regsym / 128; /* 128 = 2**7 */
regsym *= 125 ; /* 125 = 1000/2**3 */
regsym /= 512 ; /* 128 = 2**9 */
} else {
regsym = regsym * 4; /* 4 = 2**2 */
regsym = regsym / 32768; /* 32768L = 2**15 */
regsym = adp_khz * regsym; /* AdpClk in kHz */
regsym = regsym / 128; /* 128 = 2**7 */
regsym *= 125 ; /* 125 = 1000/2**3 */
regsym /= 256 ; /* 64 = 2**8 */
}
return regsym;
}
static u32 stv0367cab_fsm_status(struct stv0367_state *state)
{
return stv0367_readbits(state, F367CAB_FSM_STATUS);
}
static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
{
return stv0367_readbits(state,
(state->cab_state->qamfec_status_reg ?
state->cab_state->qamfec_status_reg :
F367CAB_QAMFEC_LOCK));
}
static
enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
{
enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
switch (qam_fsm_status) {
case 1:
signaltype = FE_CAB_NOAGC;
break;
case 2:
signaltype = FE_CAB_NOTIMING;
break;
case 3:
signaltype = FE_CAB_TIMINGOK;
break;
case 4:
signaltype = FE_CAB_NOCARRIER;
break;
case 5:
signaltype = FE_CAB_CARRIEROK;
break;
case 7:
signaltype = FE_CAB_NOBLIND;
break;
case 8:
signaltype = FE_CAB_BLINDOK;
break;
case 10:
signaltype = FE_CAB_NODEMOD;
break;
case 11:
signaltype = FE_CAB_DEMODOK;
break;
case 12:
signaltype = FE_CAB_DEMODOK;
break;
case 13:
signaltype = FE_CAB_NODEMOD;
break;
case 14:
signaltype = FE_CAB_NOBLIND;
break;
case 15:
signaltype = FE_CAB_NOSIGNAL;
break;
default:
break;
}
return signaltype;
}
static int stv0367cab_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct stv0367_state *state = fe->demodulator_priv;
dprintk("%s:\n", __func__);
*status = 0;
/* update cab_state->state from QAM_FSM_STATUS */
state->cab_state->state = stv0367cab_fsm_signaltype(
stv0367cab_fsm_status(state));
if (stv0367cab_qamfec_lock(state)) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
| FE_HAS_SYNC | FE_HAS_LOCK;
dprintk("%s: stv0367 has locked\n", __func__);
} else {
if (state->cab_state->state > FE_CAB_NOSIGNAL)
*status |= FE_HAS_SIGNAL;
if (state->cab_state->state > FE_CAB_NOCARRIER)
*status |= FE_HAS_CARRIER;
if (state->cab_state->state >= FE_CAB_DEMODOK)
*status |= FE_HAS_VITERBI;
if (state->cab_state->state >= FE_CAB_DATAOK)
*status |= FE_HAS_SYNC;
}
return 0;
}
static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
{
struct stv0367_state *state = fe->demodulator_priv;
dprintk("%s:\n", __func__);
if (standby_on) {
stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
stv0367_writebits(state, F367CAB_STDBY, 1);
stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
stv0367_writebits(state, F367CAB_POFFQ, 1);
stv0367_writebits(state, F367CAB_POFFI, 1);
} else {
stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
stv0367_writebits(state, F367CAB_STDBY, 0);
stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
stv0367_writebits(state, F367CAB_POFFQ, 0);
stv0367_writebits(state, F367CAB_POFFI, 0);
}
return 0;
}
static int stv0367cab_sleep(struct dvb_frontend *fe)
{
return stv0367cab_standby(fe, 1);
}
static int stv0367cab_init(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367cab_state *cab_state = state->cab_state;
dprintk("%s:\n", __func__);
stv0367_write_table(state,
stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
switch (state->config->ts_mode) {
case STV0367_DVBCI_CLOCK:
dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
break;
case STV0367_SERIAL_PUNCT_CLOCK:
case STV0367_SERIAL_CONT_CLOCK:
stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
break;
case STV0367_PARALLEL_PUNCT_CLOCK:
case STV0367_OUTPUTMODE_DEFAULT:
stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
break;
}
switch (state->config->clk_pol) {
case STV0367_RISINGEDGE_CLOCK:
stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
break;
case STV0367_FALLINGEDGE_CLOCK:
case STV0367_CLOCKPOLARITY_DEFAULT:
stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
break;
}
stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
return 0;
}
static
enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
struct dtv_frontend_properties *p)
{
struct stv0367cab_state *cab_state = state->cab_state;
enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
u8 TrackAGCAccum;
s32 tmp;
dprintk("%s:\n", __func__);
stv0367_get_if_khz(state, &ifkhz);
/* Timeouts calculation */
/* A max lock time of 25 ms is allowed for delayed AGC */
AGCTimeOut = 25;
/* 100000 symbols needed by the TRL as a maximum value */
TRLTimeOut = 100000000 / p->symbol_rate;
/* CRLSymbols is the needed number of symbols to achieve a lock
within [-4%, +4%] of the symbol rate.
CRL timeout is calculated
for a lock within [-search_range, +search_range].
EQL timeout can be changed depending on
the micro-reflections we want to handle.
A characterization must be performed
with these echoes to get new timeout values.
*/
switch (p->modulation) {
case QAM_16:
CRLSymbols = 150000;
EQLTimeOut = 100;
break;
case QAM_32:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
case QAM_64:
CRLSymbols = 200000;
EQLTimeOut = 100;
break;
case QAM_128:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
case QAM_256:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
default:
CRLSymbols = 200000;
EQLTimeOut = 100;
break;
}
#if 0
if (pIntParams->search_range < 0) {
CRLTimeOut = (25 * CRLSymbols *
(-pIntParams->search_range / 1000)) /
(pIntParams->symbol_rate / 1000);
} else
#endif
CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
(p->symbol_rate / 1000);
CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
/* Timeouts below 50ms are coerced */
if (CRLTimeOut < 50)
CRLTimeOut = 50;
/* A maximum of 100 TS packets is needed to get FEC lock even in case
the spectrum inversion needs to be changed.
This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
*/
FECTimeOut = 20;
DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
/* Reset the TRL to ensure nothing starts until the
AGC is stable which ensures a better lock time
*/
stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
/* Set AGC accumulation time to minimum and lock threshold to maximum
in order to speed up the AGC lock */
TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
/* Modulus Mapper is disabled */
stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
/* Disable the sweep function */
stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
/* The sweep function is never used, Sweep rate must be set to 0 */
/* Set the derotator frequency in Hz */
stv0367cab_set_derot_freq(state, cab_state->adc_clk,
(1000 * (s32)ifkhz + cab_state->derot_offset));
/* Disable the Allpass Filter when the symbol rate is out of range */
if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
stv0367_writebits(state, F367CAB_ADJ_EN, 0);
stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
}
#if 0
/* Check if the tuner is locked */
tuner_lock = stv0367cab_tuner_get_status(fe);
if (tuner_lock == 0)
return FE_367CAB_NOTUNER;
#endif
/* Release the TRL to start demodulator acquisition */
/* Wait for QAM lock */
LockTime = 0;
stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
do {
QAM_Lock = stv0367cab_fsm_status(state);
if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
(QAM_Lock == 0x04))
/*
* We don't wait longer, the frequency/phase offset
* must be too big
*/
LockTime = DemodTimeOut;
else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
(QAM_Lock == 0x02))
/*
* We don't wait longer, either there is no signal or
* it is not the right symbol rate or it is an analog
* carrier
*/
{
LockTime = DemodTimeOut;
u32_tmp = stv0367_readbits(state,
F367CAB_AGC_PWR_WORD_LO) +
(stv0367_readbits(state,
F367CAB_AGC_PWR_WORD_ME) << 8) +
(stv0367_readbits(state,
F367CAB_AGC_PWR_WORD_HI) << 16);
if (u32_tmp >= 131072)
u32_tmp = 262144 - u32_tmp;
u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
F367CAB_AGC_IF_BWSEL)));
if (u32_tmp < stv0367_readbits(state,
F367CAB_AGC_PWRREF_LO) +
256 * stv0367_readbits(state,
F367CAB_AGC_PWRREF_HI) - 10)
QAM_Lock = 0x0f;
} else {
usleep_range(10000, 20000);
LockTime += 10;
}
dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
} while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
(LockTime < DemodTimeOut));
dprintk("QAM_Lock=0x%x\n", QAM_Lock);
tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
/* Wait for FEC lock */
LockTime = 0;
do {
usleep_range(5000, 7000);
LockTime += 5;
QAMFEC_Lock = stv0367cab_qamfec_lock(state);
} while (!QAMFEC_Lock && (LockTime < FECTimeOut));
} else
QAMFEC_Lock = 0;
if (QAMFEC_Lock) {
signalType = FE_CAB_DATAOK;
cab_state->spect_inv = stv0367_readbits(state,
F367CAB_QUAD_INV);
#if 0
/* not clear for me */
if (ifkhz != 0) {
if (ifkhz > cab_state->adc_clk / 1000) {
cab_state->freq_khz =
FE_Cab_TunerGetFrequency(pIntParams->hTuner)
- stv0367cab_get_derot_freq(state, cab_state->adc_clk)
- cab_state->adc_clk / 1000 + ifkhz;
} else {
cab_state->freq_khz =
FE_Cab_TunerGetFrequency(pIntParams->hTuner)
- stv0367cab_get_derot_freq(state, cab_state->adc_clk)
+ ifkhz;
}
} else {
cab_state->freq_khz =
FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
stv0367cab_get_derot_freq(state,
cab_state->adc_clk) -
cab_state->adc_clk / 4000;
}
#endif
cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
cab_state->mclk);
cab_state->locked = 1;
/* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
} else
signalType = stv0367cab_fsm_signaltype(QAM_Lock);
/* Set the AGC control values to tracking values */
stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
return signalType;
}
static int stv0367cab_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367cab_state *cab_state = state->cab_state;
enum stv0367cab_mod QAMSize = 0;
dprintk("%s: freq = %d, srate = %d\n", __func__,
p->frequency, p->symbol_rate);
cab_state->derot_offset = 0;
switch (p->modulation) {
case QAM_16:
QAMSize = FE_CAB_MOD_QAM16;
break;
case QAM_32:
QAMSize = FE_CAB_MOD_QAM32;
break;
case QAM_64:
QAMSize = FE_CAB_MOD_QAM64;
break;
case QAM_128:
QAMSize = FE_CAB_MOD_QAM128;
break;
case QAM_256:
QAMSize = FE_CAB_MOD_QAM256;
break;
default:
break;
}
if (state->reinit_on_setfrontend)
stv0367cab_init(fe);
/* Tuner Frequency Setting */
if (fe->ops.tuner_ops.set_params) {
if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
stv0367cab_SetQamSize(
state,
p->symbol_rate,
QAMSize);
stv0367cab_set_srate(state,
cab_state->adc_clk,
cab_state->mclk,
p->symbol_rate,
QAMSize);
/* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
cab_state->state = stv0367cab_algo(state, p);
return 0;
}
static int stv0367cab_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0367_state *state = fe->demodulator_priv;
struct stv0367cab_state *cab_state = state->cab_state;
u32 ifkhz = 0;
enum stv0367cab_mod QAMSize;
dprintk("%s:\n", __func__);
stv0367_get_if_khz(state, &ifkhz);
p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
switch (QAMSize) {
case FE_CAB_MOD_QAM16:
p->modulation = QAM_16;
break;
case FE_CAB_MOD_QAM32:
p->modulation = QAM_32;
break;
case FE_CAB_MOD_QAM64:
p->modulation = QAM_64;
break;
case FE_CAB_MOD_QAM128:
p->modulation = QAM_128;
break;
case FE_CAB_MOD_QAM256:
p->modulation = QAM_256;
break;
default:
break;
}
p->frequency = stv0367_get_tuner_freq(fe);
dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
if (ifkhz == 0) {
p->frequency +=
(stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
cab_state->adc_clk / 4000);
return 0;
}
if (ifkhz > cab_state->adc_clk / 1000)
p->frequency += (ifkhz
- stv0367cab_get_derot_freq(state, cab_state->adc_clk)
- cab_state->adc_clk / 1000);
else
p->frequency += (ifkhz
- stv0367cab_get_derot_freq(state, cab_state->adc_clk));
return 0;
}
#if 0
void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
{
stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
stv0367cab_GetPacketsCount(state, Monitor_results);
return;
}
static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct stv0367_state *state = fe->demodulator_priv;
return 0;
}
#endif
static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
{
s32 rfLevel = 0;
s32 RfAgcPwm = 0, IfAgcPwm = 0;
u8 i;
stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
RfAgcPwm =
(stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
(stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
RfAgcPwm = 100 * RfAgcPwm / 1023;
IfAgcPwm =
stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
(stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
if (IfAgcPwm >= 2048)
IfAgcPwm -= 2048;
else
IfAgcPwm += 2048;
IfAgcPwm = 100 * IfAgcPwm / 4095;
/* For DTT75467 on NIM */
if (RfAgcPwm < 90 && IfAgcPwm < 28) {
for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
break;
}
}
if (i == RF_LOOKUP_TABLE_SIZE)
rfLevel = -56;
} else { /*if IF AGC>10*/
for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
break;
}
}
if (i == RF_LOOKUP_TABLE2_SIZE)
rfLevel = -72;
}
return rfLevel;
}
static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stv0367_state *state = fe->demodulator_priv;
s32 signal = stv0367cab_get_rf_lvl(state);
dprintk("%s: signal=%d dBm\n", __func__, signal);
if (signal <= -72)
*strength = 65535;
else
*strength = (22 + signal) * (-1311);
dprintk("%s: strength=%d\n", __func__, (*strength));
return 0;
}
static int stv0367cab_snr_power(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
enum stv0367cab_mod QAMSize;
QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
switch (QAMSize) {
case FE_CAB_MOD_QAM4:
return 21904;
case FE_CAB_MOD_QAM16:
return 20480;
case FE_CAB_MOD_QAM32:
return 23040;
case FE_CAB_MOD_QAM64:
return 21504;
case FE_CAB_MOD_QAM128:
return 23616;
case FE_CAB_MOD_QAM256:
return 21760;
case FE_CAB_MOD_QAM1024:
return 21280;
default:
break;
}
return 1;
}
static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
{
struct stv0367_state *state = fe->demodulator_priv;
u32 regval = 0;
int i;
for (i = 0; i < 10; i++) {
regval += (stv0367_readbits(state, F367CAB_SNR_LO)
+ 256 * stv0367_readbits(state, F367CAB_SNR_HI));
}
if (avgdiv)
regval /= 10;
return regval;
}
static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct stv0367_state *state = fe->demodulator_priv;
u32 noisepercentage;
u32 regval = 0, temp = 0;
int power;
power = stv0367cab_snr_power(fe);
regval = stv0367cab_snr_readreg(fe, 1);
if (regval != 0) {
temp = power
* (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
temp /= regval;
}
/* table values, not needed to calculate logarithms */
if (temp >= 5012)
noisepercentage = 100;
else if (temp >= 3981)
noisepercentage = 93;
else if (temp >= 3162)
noisepercentage = 86;
else if (temp >= 2512)
noisepercentage = 79;
else if (temp >= 1995)
noisepercentage = 72;
else if (temp >= 1585)
noisepercentage = 65;
else if (temp >= 1259)
noisepercentage = 58;
else if (temp >= 1000)
noisepercentage = 50;
else if (temp >= 794)
noisepercentage = 43;
else if (temp >= 501)
noisepercentage = 36;
else if (temp >= 316)
noisepercentage = 29;
else if (temp >= 200)
noisepercentage = 22;
else if (temp >= 158)
noisepercentage = 14;
else if (temp >= 126)
noisepercentage = 7;
else
noisepercentage = 0;
dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
*snr = (noisepercentage * 65535) / 100;
return 0;
}
static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct stv0367_state *state = fe->demodulator_priv;
int corrected, tscount;
*ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
| stv0367_readreg(state, R367CAB_RS_COUNTER_4);
corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
| stv0367_readreg(state, R367CAB_RS_COUNTER_2);
tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
| stv0367_readreg(state, R367CAB_RS_COUNTER_1);
dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
__func__, *ucblocks, corrected, tscount);
return 0;
};
static const struct dvb_frontend_ops stv0367cab_ops = {
.delsys = { SYS_DVBC_ANNEX_A },
.info = {
.name = "ST STV0367 DVB-C",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 870000,
.symbol_rate_max = 11700000,
.caps = 0x400 |/* FE_CAN_QAM_4 */
FE_CAN_QAM_16 | FE_CAN_QAM_32 |
FE_CAN_QAM_64 | FE_CAN_QAM_128 |
FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
},
.release = stv0367_release,
.init = stv0367cab_init,
.sleep = stv0367cab_sleep,
.i2c_gate_ctrl = stv0367cab_gate_ctrl,
.set_frontend = stv0367cab_set_frontend,
.get_frontend = stv0367cab_get_frontend,
.read_status = stv0367cab_read_status,
/* .read_ber = stv0367cab_read_ber, */
.read_signal_strength = stv0367cab_read_strength,
.read_snr = stv0367cab_read_snr,
.read_ucblocks = stv0367cab_read_ucblcks,
.get_tune_settings = stv0367_get_tune_settings,
};
struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c)
{
struct stv0367_state *state = NULL;
struct stv0367cab_state *cab_state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
if (state == NULL)
goto error;
cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
if (cab_state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
state->config = config;
cab_state->search_range = 280000;
cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
state->cab_state = cab_state;
state->fe.ops = stv0367cab_ops;
state->fe.demodulator_priv = state;
state->chip_id = stv0367_readreg(state, 0xf000);
/* demod operation options */
state->use_i2c_gatectrl = 1;
state->deftabs = STV0367_DEFTAB_GENERIC;
state->reinit_on_setfrontend = 1;
state->auto_if_khz = 0;
dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
/* check if the demod is there */
if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
goto error;
return &state->fe;
error:
kfree(cab_state);
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0367cab_attach);
/*
* Functions for operation on Digital Devices hardware
*/
static void stv0367ddb_setup_ter(struct stv0367_state *state)
{
stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
/* Tuner Setup */
/* Buffer Q disabled, I Enabled, unsigned ADC */
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
/* Clock setup */
/* PLL bypassed and disabled */
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
/* IC runs at 54 MHz with a 27 MHz crystal */
stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
msleep(50);
/* PLL enabled and used */
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
state->activedemod = demod_ter;
}
static void stv0367ddb_setup_cab(struct stv0367_state *state)
{
stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
/* Tuner Setup */
/* Buffer Q disabled, I Enabled, signed ADC */
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
/* ADCQ disabled */
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
/* Clock setup */
/* PLL bypassed and disabled */
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
/* Set QAM */
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
/* IC runs at 58 MHz with a 27 MHz crystal */
stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
msleep(50);
/* PLL enabled and used */
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
state->config->xtal);
state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
state->config->xtal);
state->activedemod = demod_cab;
}
static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
switch (fe->dtv_property_cache.delivery_system) {
case SYS_DVBT:
if (state->activedemod != demod_ter)
stv0367ddb_setup_ter(state);
return stv0367ter_set_frontend(fe);
case SYS_DVBC_ANNEX_A:
if (state->activedemod != demod_cab)
stv0367ddb_setup_cab(state);
/* protect against division error oopses */
if (fe->dtv_property_cache.symbol_rate == 0) {
printk(KERN_ERR "Invalid symbol rate\n");
return -EINVAL;
}
return stv0367cab_set_frontend(fe);
default:
break;
}
return -EINVAL;
}
static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
s32 signalstrength;
switch (state->activedemod) {
case demod_cab:
signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
break;
default:
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
p->strength.stat[0].uvalue = signalstrength;
}
static void stv0367ddb_read_snr(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int cab_pwr;
u32 regval, tmpval, snrval = 0;
switch (state->activedemod) {
case demod_ter:
snrval = stv0367ter_snr_readreg(fe);
break;
case demod_cab:
cab_pwr = stv0367cab_snr_power(fe);
regval = stv0367cab_snr_readreg(fe, 0);
/* prevent division by zero */
if (!regval) {
snrval = 0;
break;
}
tmpval = (cab_pwr * 320) / regval;
snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
break;
default:
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].uvalue = snrval;
}
static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 ucblocks = 0;
switch (state->activedemod) {
case demod_ter:
stv0367ter_read_ucblocks(fe, &ucblocks);
break;
case demod_cab:
stv0367cab_read_ucblcks(fe, &ucblocks);
break;
default:
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_error.stat[0].uvalue = ucblocks;
}
static int stv0367ddb_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct stv0367_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int ret = 0;
switch (state->activedemod) {
case demod_ter:
ret = stv0367ter_read_status(fe, status);
break;
case demod_cab:
ret = stv0367cab_read_status(fe, status);
break;
default:
break;
}
/* stop and report on *_read_status failure */
if (ret)
return ret;
stv0367ddb_read_signal_strength(fe);
/* read carrier/noise when a carrier is detected */
if (*status & FE_HAS_CARRIER)
stv0367ddb_read_snr(fe);
else
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* read uncorrected blocks on FE_HAS_LOCK */
if (*status & FE_HAS_LOCK)
stv0367ddb_read_ucblocks(fe);
else
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0367_state *state = fe->demodulator_priv;
switch (state->activedemod) {
case demod_ter:
return stv0367ter_get_frontend(fe, p);
case demod_cab:
return stv0367cab_get_frontend(fe, p);
default:
break;
}
return 0;
}
static int stv0367ddb_sleep(struct dvb_frontend *fe)
{
struct stv0367_state *state = fe->demodulator_priv;
switch (state->activedemod) {
case demod_ter:
state->activedemod = demod_none;
return stv0367ter_sleep(fe);
case demod_cab:
state->activedemod = demod_none;
return stv0367cab_sleep(fe);
default:
break;
}
return -EINVAL;
}
static int stv0367ddb_init(struct stv0367_state *state)
{
struct stv0367ter_state *ter_state = state->ter_state;
struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
stv0367_write_table(state,
stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
stv0367_write_table(state,
stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
stv0367_write_table(state,
stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
/* OFDM TS Setup */
stv0367_writereg(state, R367TER_TSCFGH, 0x70);
stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
stv0367_writereg(state, R367TER_TSCFGL, 0x20);
stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
stv0367_writereg(state, R367TER_TSCFGH, 0x71);
stv0367_writereg(state, R367TER_TSCFGH, 0x70);
stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
/* Also needed for QAM */
stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
/* QAM TS setup, note exact format also depends on descrambler */
/* settings */
/* Inverted Clock, Swap, serial */
stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
/* Clock setup (PLL bypassed and disabled) */
stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
/* IC runs at 58 MHz with a 27 MHz crystal */
stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
/* Tuner setup */
/* Buffer Q disabled, I Enabled, signed ADC */
stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
/* Improves the C/N lock limit */
stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
/* ZIF/IF Automatic mode */
stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
/* Improving burst noise performances */
stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
/* Improving ACI performances */
stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
/* PLL enabled and used */
stv0367_writereg(state, R367TER_ANACTRL, 0x00);
stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
ter_state->pBER = 0;
ter_state->first_lock = 0;
ter_state->unlock_counter = 2;
p->strength.len = 1;
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.len = 1;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.len = 1;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
static const struct dvb_frontend_ops stv0367ddb_ops = {
.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
.info = {
.name = "ST STV0367 DDB DVB-C/T",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 865 * MHz,
.frequency_stepsize_hz = 166667,
.symbol_rate_min = 870000,
.symbol_rate_max = 11700000,
.caps = /* DVB-C */
0x400 |/* FE_CAN_QAM_4 */
FE_CAN_QAM_16 | FE_CAN_QAM_32 |
FE_CAN_QAM_64 | FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
/* DVB-T */
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
FE_CAN_MUTE_TS
},
.release = stv0367_release,
.sleep = stv0367ddb_sleep,
.i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
.set_frontend = stv0367ddb_set_frontend,
.get_frontend = stv0367ddb_get_frontend,
.get_tune_settings = stv0367_get_tune_settings,
.read_status = stv0367ddb_read_status,
};
struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c)
{
struct stv0367_state *state = NULL;
struct stv0367ter_state *ter_state = NULL;
struct stv0367cab_state *cab_state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
if (state == NULL)
goto error;
ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
if (ter_state == NULL)
goto error;
cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
if (cab_state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
state->config = config;
state->ter_state = ter_state;
cab_state->search_range = 280000;
cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
state->cab_state = cab_state;
state->fe.ops = stv0367ddb_ops;
state->fe.demodulator_priv = state;
state->chip_id = stv0367_readreg(state, R367TER_ID);
/* demod operation options */
state->use_i2c_gatectrl = 0;
state->deftabs = STV0367_DEFTAB_DDB;
state->reinit_on_setfrontend = 0;
state->auto_if_khz = 1;
state->activedemod = demod_none;
dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
/* check if the demod is there */
if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
goto error;
dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
state->fe.ops.info.name, state->chip_id,
config->demod_address);
stv0367ddb_init(state);
return &state->fe;
error:
kfree(cab_state);
kfree(ter_state);
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0367ddb_attach);
MODULE_PARM_DESC(debug, "Set debug");
MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
MODULE_AUTHOR("Igor M. Liplianin");
MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv0367.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Afatech AF9033 demodulator driver
*
* Copyright (C) 2009 Antti Palosaari <[email protected]>
* Copyright (C) 2012 Antti Palosaari <[email protected]>
*/
#include "af9033_priv.h"
struct af9033_dev {
struct i2c_client *client;
struct regmap *regmap;
struct dvb_frontend fe;
struct af9033_config cfg;
bool is_af9035;
bool is_it9135;
u32 bandwidth_hz;
bool ts_mode_parallel;
bool ts_mode_serial;
enum fe_status fe_status;
u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
u64 post_bit_error;
u64 post_bit_count;
u64 error_block_count;
u64 total_block_count;
};
/* Write reg val table using reg addr auto increment */
static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
const struct reg_val *tab, int tab_len)
{
struct i2c_client *client = dev->client;
#define MAX_TAB_LEN 212
int ret, i, j;
u8 buf[1 + MAX_TAB_LEN];
dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
if (tab_len > sizeof(buf)) {
dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
return -EINVAL;
}
for (i = 0, j = 0; i < tab_len; i++) {
buf[j] = tab[i].val;
if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
buf, j + 1);
if (ret)
goto err;
j = 0;
} else {
j++;
}
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_init(struct dvb_frontend *fe)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, len;
unsigned int utmp;
const struct reg_val *init;
u8 buf[4];
struct reg_val_mask tab[] = {
{ 0x80fb24, 0x00, 0x08 },
{ 0x80004c, 0x00, 0xff },
{ 0x00f641, dev->cfg.tuner, 0xff },
{ 0x80f5ca, 0x01, 0x01 },
{ 0x80f715, 0x01, 0x01 },
{ 0x00f41f, 0x04, 0x04 },
{ 0x00f41a, 0x01, 0x01 },
{ 0x80f731, 0x00, 0x01 },
{ 0x00d91e, 0x00, 0x01 },
{ 0x00d919, 0x00, 0x01 },
{ 0x80f732, 0x00, 0x01 },
{ 0x00d91f, 0x00, 0x01 },
{ 0x00d91a, 0x00, 0x01 },
{ 0x80f730, 0x00, 0x01 },
{ 0x80f778, 0x00, 0xff },
{ 0x80f73c, 0x01, 0x01 },
{ 0x80f776, 0x00, 0x01 },
{ 0x00d8fd, 0x01, 0xff },
{ 0x00d830, 0x01, 0xff },
{ 0x00d831, 0x00, 0xff },
{ 0x00d832, 0x00, 0xff },
{ 0x80f985, dev->ts_mode_serial, 0x01 },
{ 0x80f986, dev->ts_mode_parallel, 0x01 },
{ 0x00d827, 0x00, 0xff },
{ 0x00d829, 0x00, 0xff },
{ 0x800045, dev->cfg.adc_multiplier, 0xff },
};
dev_dbg(&client->dev, "\n");
/* Main clk control */
utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
buf[0] = (utmp >> 0) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 16) & 0xff;
buf[3] = (utmp >> 24) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
if (ret)
goto err;
dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
/* ADC clk control */
for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
if (clock_adc_lut[i].clock == dev->cfg.clock)
break;
}
if (i == ARRAY_SIZE(clock_adc_lut)) {
dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
dev->cfg.clock);
ret = -ENODEV;
goto err;
}
utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
buf[0] = (utmp >> 0) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 16) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
if (ret)
goto err;
dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
clock_adc_lut[i].adc, utmp);
/* Config register table */
for (i = 0; i < ARRAY_SIZE(tab); i++) {
ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
/* Demod clk output */
if (dev->cfg.dyn0_clk) {
ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
if (ret)
goto err;
}
/* TS interface */
if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
if (ret)
goto err;
} else {
ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
if (ret)
goto err;
}
/* Demod core settings */
dev_dbg(&client->dev, "load ofsm settings\n");
switch (dev->cfg.tuner) {
case AF9033_TUNER_IT9135_38:
case AF9033_TUNER_IT9135_51:
case AF9033_TUNER_IT9135_52:
len = ARRAY_SIZE(ofsm_init_it9135_v1);
init = ofsm_init_it9135_v1;
break;
case AF9033_TUNER_IT9135_60:
case AF9033_TUNER_IT9135_61:
case AF9033_TUNER_IT9135_62:
len = ARRAY_SIZE(ofsm_init_it9135_v2);
init = ofsm_init_it9135_v2;
break;
default:
len = ARRAY_SIZE(ofsm_init);
init = ofsm_init;
break;
}
ret = af9033_wr_reg_val_tab(dev, init, len);
if (ret)
goto err;
/* Demod tuner specific settings */
dev_dbg(&client->dev, "load tuner specific settings\n");
switch (dev->cfg.tuner) {
case AF9033_TUNER_TUA9001:
len = ARRAY_SIZE(tuner_init_tua9001);
init = tuner_init_tua9001;
break;
case AF9033_TUNER_FC0011:
len = ARRAY_SIZE(tuner_init_fc0011);
init = tuner_init_fc0011;
break;
case AF9033_TUNER_MXL5007T:
len = ARRAY_SIZE(tuner_init_mxl5007t);
init = tuner_init_mxl5007t;
break;
case AF9033_TUNER_TDA18218:
len = ARRAY_SIZE(tuner_init_tda18218);
init = tuner_init_tda18218;
break;
case AF9033_TUNER_FC2580:
len = ARRAY_SIZE(tuner_init_fc2580);
init = tuner_init_fc2580;
break;
case AF9033_TUNER_FC0012:
len = ARRAY_SIZE(tuner_init_fc0012);
init = tuner_init_fc0012;
break;
case AF9033_TUNER_IT9135_38:
len = ARRAY_SIZE(tuner_init_it9135_38);
init = tuner_init_it9135_38;
break;
case AF9033_TUNER_IT9135_51:
len = ARRAY_SIZE(tuner_init_it9135_51);
init = tuner_init_it9135_51;
break;
case AF9033_TUNER_IT9135_52:
len = ARRAY_SIZE(tuner_init_it9135_52);
init = tuner_init_it9135_52;
break;
case AF9033_TUNER_IT9135_60:
len = ARRAY_SIZE(tuner_init_it9135_60);
init = tuner_init_it9135_60;
break;
case AF9033_TUNER_IT9135_61:
len = ARRAY_SIZE(tuner_init_it9135_61);
init = tuner_init_it9135_61;
break;
case AF9033_TUNER_IT9135_62:
len = ARRAY_SIZE(tuner_init_it9135_62);
init = tuner_init_it9135_62;
break;
default:
dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
dev->cfg.tuner);
ret = -ENODEV;
goto err;
}
ret = af9033_wr_reg_val_tab(dev, init, len);
if (ret)
goto err;
if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
if (ret)
goto err;
}
switch (dev->cfg.tuner) {
case AF9033_TUNER_IT9135_60:
case AF9033_TUNER_IT9135_61:
case AF9033_TUNER_IT9135_62:
ret = regmap_write(dev->regmap, 0x800000, 0x01);
if (ret)
goto err;
}
dev->bandwidth_hz = 0; /* Force to program all parameters */
/* Init stats here in order signal app which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_sleep(struct dvb_frontend *fe)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp;
dev_dbg(&client->dev, "\n");
ret = regmap_write(dev->regmap, 0x80004c, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x800000, 0x00);
if (ret)
goto err;
ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
5000, 1000000);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
if (ret)
goto err;
/* Prevent current leak by setting TS interface to parallel mode */
if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
/* Enable parallel TS */
ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
if (ret)
goto err;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
/* 800 => 2000 because IT9135 v2 is slow to gain lock */
fesettings->min_delay_ms = 2000;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int af9033_set_frontend(struct dvb_frontend *fe)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
unsigned int utmp, adc_freq;
u8 tmp, buf[3], bandwidth_reg_val;
u32 if_frequency;
dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
c->frequency, c->bandwidth_hz);
/* Check bandwidth */
switch (c->bandwidth_hz) {
case 6000000:
bandwidth_reg_val = 0x00;
break;
case 7000000:
bandwidth_reg_val = 0x01;
break;
case 8000000:
bandwidth_reg_val = 0x02;
break;
default:
dev_dbg(&client->dev, "invalid bandwidth_hz\n");
ret = -EINVAL;
goto err;
}
/* Program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* Coefficients */
if (c->bandwidth_hz != dev->bandwidth_hz) {
for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
if (coeff_lut[i].clock == dev->cfg.clock &&
coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
break;
}
}
if (i == ARRAY_SIZE(coeff_lut)) {
dev_err(&client->dev,
"Couldn't find config for clock %u\n",
dev->cfg.clock);
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
sizeof(coeff_lut[i].val));
if (ret)
goto err;
}
/* IF frequency control */
if (c->bandwidth_hz != dev->bandwidth_hz) {
for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
if (clock_adc_lut[i].clock == dev->cfg.clock)
break;
}
if (i == ARRAY_SIZE(clock_adc_lut)) {
dev_err(&client->dev,
"Couldn't find ADC clock for clock %u\n",
dev->cfg.clock);
ret = -EINVAL;
goto err;
}
adc_freq = clock_adc_lut[i].adc;
if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
adc_freq = 2 * adc_freq;
/* Get used IF frequency */
if (fe->ops.tuner_ops.get_if_frequency)
fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
else
if_frequency = 0;
utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
adc_freq);
if (!dev->cfg.spec_inv && if_frequency)
utmp = 0x800000 - utmp;
buf[0] = (utmp >> 0) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 16) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
if (ret)
goto err;
dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
dev->bandwidth_hz = c->bandwidth_hz;
}
ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
bandwidth_reg_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x800040, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x800047, 0x00);
if (ret)
goto err;
ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
if (ret)
goto err;
if (c->frequency <= 230000000)
tmp = 0x00; /* VHF */
else
tmp = 0x01; /* UHF */
ret = regmap_write(dev->regmap, 0x80004b, tmp);
if (ret)
goto err;
/* Reset FSM */
ret = regmap_write(dev->regmap, 0x800000, 0x00);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 buf[8];
dev_dbg(&client->dev, "\n");
/* Read all needed TPS registers */
ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
if (ret)
goto err;
switch ((buf[0] >> 0) & 3) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
}
switch ((buf[1] >> 0) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[2] >> 0) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[3] >> 0) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[4] >> 0) & 3) {
case 0:
c->bandwidth_hz = 6000000;
break;
case 1:
c->bandwidth_hz = 7000000;
break;
case 2:
c->bandwidth_hz = 8000000;
break;
}
switch ((buf[6] >> 0) & 7) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
case 5:
c->code_rate_HP = FEC_NONE;
break;
}
switch ((buf[7] >> 0) & 7) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
case 5:
c->code_rate_LP = FEC_NONE;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, tmp = 0;
u8 buf[7];
unsigned int utmp, utmp1;
dev_dbg(&client->dev, "\n");
*status = 0;
/* Radio channel status: 0=no result, 1=has signal, 2=no signal */
ret = regmap_read(dev->regmap, 0x800047, &utmp);
if (ret)
goto err;
/* Has signal */
if (utmp == 0x01)
*status |= FE_HAS_SIGNAL;
if (utmp != 0x02) {
/* TPS lock */
ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
if (ret)
goto err;
if ((utmp >> 0) & 0x01)
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
/* Full lock */
ret = regmap_read(dev->regmap, 0x80f999, &utmp);
if (ret)
goto err;
if ((utmp >> 0) & 0x01)
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
}
dev->fe_status = *status;
/* Signal strength */
if (dev->fe_status & FE_HAS_SIGNAL) {
if (dev->is_af9035) {
ret = regmap_read(dev->regmap, 0x80004a, &utmp);
if (ret)
goto err;
tmp = -utmp * 1000;
} else {
ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
if (ret)
goto err;
tmp = (utmp - 100) * 1000;
}
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = tmp;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (dev->fe_status & FE_HAS_VITERBI) {
/* Read raw SNR value */
ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
if (ret)
goto err;
utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
/* Read superframe number */
ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
if (ret)
goto err;
if (utmp)
utmp1 /= utmp;
/* Read current transmission mode */
ret = regmap_read(dev->regmap, 0x80f900, &utmp);
if (ret)
goto err;
switch ((utmp >> 0) & 3) {
case 0:
/* 2k */
utmp1 *= 4;
break;
case 1:
/* 8k */
utmp1 *= 1;
break;
case 2:
/* 4k */
utmp1 *= 2;
break;
default:
utmp1 *= 0;
break;
}
/* Read current modulation */
ret = regmap_read(dev->regmap, 0x80f903, &utmp);
if (ret)
goto err;
switch ((utmp >> 0) & 3) {
case 0:
/*
* QPSK
* CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
* value [653799, 1689999], 2.6 / 13 = 3355443
*/
utmp1 = clamp(utmp1, 653799U, 1689999U);
utmp1 = ((u64)(intlog10(utmp1)
- intlog10(1690000 - utmp1)
+ 3355443) * 13 * 1000) >> 24;
break;
case 1:
/*
* QAM-16
* CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
* value [371105, 827999], 15.7 / 6 = 43900382
*/
utmp1 = clamp(utmp1, 371105U, 827999U);
utmp1 = ((u64)(intlog10(utmp1 - 370000)
- intlog10(828000 - utmp1)
+ 43900382) * 6 * 1000) >> 24;
break;
case 2:
/*
* QAM-64
* CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
* value [193246, 424999], 23.8 / 8 = 49912218
*/
utmp1 = clamp(utmp1, 193246U, 424999U);
utmp1 = ((u64)(intlog10(utmp1 - 193000)
- intlog10(425000 - utmp1)
+ 49912218) * 8 * 1000) >> 24;
break;
default:
utmp1 = 0;
break;
}
dev_dbg(&client->dev, "cnr=%u\n", utmp1);
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = utmp1;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* UCB/PER/BER */
if (dev->fe_status & FE_HAS_LOCK) {
/* Outer FEC, 204 byte packets */
u16 abort_packet_count, rsd_packet_count;
/* Inner FEC, bits */
u32 rsd_bit_err_count;
/*
* Packet count used for measurement is 10000
* (rsd_packet_count). Maybe it should be increased?
*/
ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
if (ret)
goto err;
abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
dev->error_block_count += abort_packet_count;
dev->total_block_count += rsd_packet_count;
dev->post_bit_error += rsd_bit_err_count;
dev->post_bit_count += rsd_packet_count * 204 * 8;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue = dev->total_block_count;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = dev->error_block_count;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
int ret;
unsigned int utmp;
dev_dbg(&client->dev, "\n");
/* Use DVBv5 CNR */
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
/* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
if (dev->is_af9035) {
/* 1000x => 10x (0.1 dB) */
*snr = div_s64(c->cnr.stat[0].svalue, 100);
} else {
/* 1000x => 1x (1 dB) */
*snr = div_s64(c->cnr.stat[0].svalue, 1000);
/* Read current modulation */
ret = regmap_read(dev->regmap, 0x80f903, &utmp);
if (ret)
goto err;
/* scale value to 0x0000-0xffff */
switch ((utmp >> 0) & 3) {
case 0:
*snr = *snr * 0xffff / 23;
break;
case 1:
*snr = *snr * 0xffff / 26;
break;
case 2:
*snr = *snr * 0xffff / 32;
break;
default:
ret = -EINVAL;
goto err;
}
}
} else {
*snr = 0;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
int ret, tmp, power_real;
unsigned int utmp;
u8 gain_offset, buf[7];
dev_dbg(&client->dev, "\n");
if (dev->is_af9035) {
/* Read signal strength of 0-100 scale */
ret = regmap_read(dev->regmap, 0x800048, &utmp);
if (ret)
goto err;
/* Scale value to 0x0000-0xffff */
*strength = utmp * 0xffff / 100;
} else {
ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
if (ret)
goto err;
ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
if (ret)
goto err;
if (c->frequency <= 300000000)
gain_offset = 7; /* VHF */
else
gain_offset = 4; /* UHF */
power_real = (utmp - 100 - gain_offset) -
power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
if (power_real < -15)
tmp = 0;
else if ((power_real >= -15) && (power_real < 0))
tmp = (2 * (power_real + 15)) / 3;
else if ((power_real >= 0) && (power_real < 20))
tmp = 4 * power_real + 10;
else if ((power_real >= 20) && (power_real < 35))
tmp = (2 * (power_real - 20)) / 3 + 90;
else
tmp = 100;
/* Scale value to 0x0000-0xffff */
*strength = tmp * 0xffff / 100;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct af9033_dev *dev = fe->demodulator_priv;
*ber = (dev->post_bit_error - dev->post_bit_error_prev);
dev->post_bit_error_prev = dev->post_bit_error;
return 0;
}
static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct af9033_dev *dev = fe->demodulator_priv;
*ucblocks = dev->error_block_count;
return 0;
}
static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
dev_dbg(&client->dev, "enable=%d\n", enable);
ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
dev_dbg(&client->dev, "onoff=%d\n", onoff);
ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
int onoff)
{
struct af9033_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
index, pid, onoff);
if (pid > 0x1fff)
return 0;
ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80f994, onoff);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x80f995, index);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_frontend_ops af9033_ops = {
.delsys = {SYS_DVBT},
.info = {
.name = "Afatech AF9033 (DVB-T)",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 250 * kHz,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.init = af9033_init,
.sleep = af9033_sleep,
.get_tune_settings = af9033_get_tune_settings,
.set_frontend = af9033_set_frontend,
.get_frontend = af9033_get_frontend,
.read_status = af9033_read_status,
.read_snr = af9033_read_snr,
.read_signal_strength = af9033_read_signal_strength,
.read_ber = af9033_read_ber,
.read_ucblocks = af9033_read_ucblocks,
.i2c_gate_ctrl = af9033_i2c_gate_ctrl,
};
static int af9033_probe(struct i2c_client *client)
{
struct af9033_config *cfg = client->dev.platform_data;
struct af9033_dev *dev;
int ret;
u8 buf[8];
u32 reg;
static const struct regmap_config regmap_config = {
.reg_bits = 24,
.val_bits = 8,
};
/* Allocate memory for the internal state */
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
/* Setup the state */
dev->client = client;
memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
switch (dev->cfg.ts_mode) {
case AF9033_TS_MODE_PARALLEL:
dev->ts_mode_parallel = true;
break;
case AF9033_TS_MODE_SERIAL:
dev->ts_mode_serial = true;
break;
case AF9033_TS_MODE_USB:
/* USB mode for AF9035 */
default:
break;
}
if (dev->cfg.clock != 12000000) {
ret = -ENODEV;
dev_err(&client->dev,
"Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
dev->cfg.clock);
goto err_kfree;
}
/* Create regmap */
dev->regmap = regmap_init_i2c(client, ®map_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
/* Firmware version */
switch (dev->cfg.tuner) {
case AF9033_TUNER_IT9135_38:
case AF9033_TUNER_IT9135_51:
case AF9033_TUNER_IT9135_52:
case AF9033_TUNER_IT9135_60:
case AF9033_TUNER_IT9135_61:
case AF9033_TUNER_IT9135_62:
dev->is_it9135 = true;
reg = 0x004bfc;
break;
default:
dev->is_af9035 = true;
reg = 0x0083e9;
break;
}
ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
if (ret)
goto err_regmap_exit;
ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
if (ret)
goto err_regmap_exit;
dev_info(&client->dev,
"firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7]);
/* Sleep as chip seems to be partly active by default */
/* IT9135 did not like to sleep at that early */
if (dev->is_af9035) {
ret = regmap_write(dev->regmap, 0x80004c, 0x01);
if (ret)
goto err_regmap_exit;
ret = regmap_write(dev->regmap, 0x800000, 0x00);
if (ret)
goto err_regmap_exit;
}
/* Create dvb frontend */
memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
dev->fe.demodulator_priv = dev;
*cfg->fe = &dev->fe;
if (cfg->ops) {
cfg->ops->pid_filter = af9033_pid_filter;
cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
}
cfg->regmap = dev->regmap;
i2c_set_clientdata(client, dev);
dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
return 0;
err_regmap_exit:
regmap_exit(dev->regmap);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void af9033_remove(struct i2c_client *client)
{
struct af9033_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
regmap_exit(dev->regmap);
kfree(dev);
}
static const struct i2c_device_id af9033_id_table[] = {
{"af9033", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, af9033_id_table);
static struct i2c_driver af9033_driver = {
.driver = {
.name = "af9033",
.suppress_bind_attrs = true,
},
.probe = af9033_probe,
.remove = af9033_remove,
.id_table = af9033_id_table,
};
module_i2c_driver(af9033_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/af9033.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for VES1893 and VES1993 QPSK Demodulators
Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]>
Copyright (C) 2001 Ronny Strutz <[email protected]>
Copyright (C) 2002 Dennis Noermann <[email protected]>
Copyright (C) 2002-2003 Andreas Oberritter <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "ves1x93.h"
struct ves1x93_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct ves1x93_config* config;
struct dvb_frontend frontend;
/* previous uncorrected block counter */
enum fe_spectral_inversion inversion;
u8 *init_1x93_tab;
u8 *init_1x93_wtab;
u8 tab_size;
u8 demod_type;
u32 frequency;
};
static int debug;
#define dprintk if (debug) printk
#define DEMOD_VES1893 0
#define DEMOD_VES1993 1
static u8 init_1893_tab [] = {
0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
};
static u8 init_1993_tab [] = {
0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
0x00, 0x00, 0x0e, 0x80, 0x00
};
static u8 init_1893_wtab[] =
{
1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
1,1,1,0,1,1
};
static u8 init_1993_wtab[] =
{
1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
1,1,1,0,1,1,1,1, 1,1,1,1,1
};
static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
{
u8 buf [] = { 0x00, reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
int err;
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
return -EREMOTEIO;
}
return 0;
}
static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
{
int ret;
u8 b0 [] = { 0x00, reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
ret = i2c_transfer (state->i2c, msg, 2);
if (ret != 2) return ret;
return b1[0];
}
static int ves1x93_clr_bit (struct ves1x93_state* state)
{
msleep(10);
ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
msleep(50);
return 0;
}
static int ves1x93_set_inversion(struct ves1x93_state *state,
enum fe_spectral_inversion inversion)
{
u8 val;
/*
* inversion on/off are interchanged because i and q seem to
* be swapped on the hardware
*/
switch (inversion) {
case INVERSION_OFF:
val = 0xc0;
break;
case INVERSION_ON:
val = 0x80;
break;
case INVERSION_AUTO:
val = 0x00;
break;
default:
return -EINVAL;
}
return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
}
static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec)
{
if (fec == FEC_AUTO)
return ves1x93_writereg (state, 0x0d, 0x08);
else if (fec < FEC_1_2 || fec > FEC_8_9)
return -EINVAL;
else
return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
}
static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state)
{
return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
}
static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
{
u32 BDR;
u32 ratio;
u8 ADCONF, FCONF, FNR, AGCR;
u32 BDRI;
u32 tmp;
u32 FIN;
dprintk("%s: srate == %d\n", __func__, (unsigned int) srate);
if (srate > state->config->xin/2)
srate = state->config->xin/2;
if (srate < 500000)
srate = 500000;
#define MUL (1UL<<26)
FIN = (state->config->xin + 6000) >> 4;
tmp = srate << 6;
ratio = tmp / FIN;
tmp = (tmp % FIN) << 8;
ratio = (ratio << 8) + tmp / FIN;
tmp = (tmp % FIN) << 8;
ratio = (ratio << 8) + tmp / FIN;
FNR = 0xff;
if (ratio < MUL/3) FNR = 0;
if (ratio < (MUL*11)/50) FNR = 1;
if (ratio < MUL/6) FNR = 2;
if (ratio < MUL/9) FNR = 3;
if (ratio < MUL/12) FNR = 4;
if (ratio < (MUL*11)/200) FNR = 5;
if (ratio < MUL/24) FNR = 6;
if (ratio < (MUL*27)/1000) FNR = 7;
if (ratio < MUL/48) FNR = 8;
if (ratio < (MUL*137)/10000) FNR = 9;
if (FNR == 0xff) {
ADCONF = 0x89;
FCONF = 0x80;
FNR = 0;
} else {
ADCONF = 0x81;
FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
/*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/
}
BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
dprintk("FNR= %d\n", FNR);
dprintk("ratio= %08x\n", (unsigned int) ratio);
dprintk("BDR= %08x\n", (unsigned int) BDR);
dprintk("BDRI= %02x\n", (unsigned int) BDRI);
if (BDRI > 0xff)
BDRI = 0xff;
ves1x93_writereg (state, 0x06, 0xff & BDR);
ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
ves1x93_writereg (state, 0x09, BDRI);
ves1x93_writereg (state, 0x20, ADCONF);
ves1x93_writereg (state, 0x21, FCONF);
AGCR = state->init_1x93_tab[0x05];
if (state->config->invert_pwm)
AGCR |= 0x20;
if (srate < 6000000)
AGCR |= 0x80;
else
AGCR &= ~0x80;
ves1x93_writereg (state, 0x05, AGCR);
/* ves1993 hates this, will lose lock */
if (state->demod_type != DEMOD_VES1993)
ves1x93_clr_bit (state);
return 0;
}
static int ves1x93_init (struct dvb_frontend* fe)
{
struct ves1x93_state* state = fe->demodulator_priv;
int i;
int val;
dprintk("%s: init chip\n", __func__);
for (i = 0; i < state->tab_size; i++) {
if (state->init_1x93_wtab[i]) {
val = state->init_1x93_tab[i];
if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */
ves1x93_writereg (state, i, val);
}
}
return 0;
}
static int ves1x93_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct ves1x93_state* state = fe->demodulator_priv;
switch (voltage) {
case SEC_VOLTAGE_13:
return ves1x93_writereg (state, 0x1f, 0x20);
case SEC_VOLTAGE_18:
return ves1x93_writereg (state, 0x1f, 0x30);
case SEC_VOLTAGE_OFF:
return ves1x93_writereg (state, 0x1f, 0x00);
default:
return -EINVAL;
}
}
static int ves1x93_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct ves1x93_state* state = fe->demodulator_priv;
u8 sync = ves1x93_readreg (state, 0x0e);
/*
* The ves1893 sometimes returns sync values that make no sense,
* because, e.g., the SIGNAL bit is 0, while some of the higher
* bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
* Tests showed that the VITERBI and SYNC bits are returned
* reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
* If such a case occurs, we read the value again, until we get a
* valid value.
*/
int maxtry = 10; /* just for safety - let's not get stuck here */
while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
msleep(10);
sync = ves1x93_readreg (state, 0x0e);
}
*status = 0;
if (sync & 1)
*status |= FE_HAS_SIGNAL;
if (sync & 2)
*status |= FE_HAS_CARRIER;
if (sync & 4)
*status |= FE_HAS_VITERBI;
if (sync & 8)
*status |= FE_HAS_SYNC;
if ((sync & 0x1f) == 0x1f)
*status |= FE_HAS_LOCK;
return 0;
}
static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct ves1x93_state* state = fe->demodulator_priv;
*ber = ves1x93_readreg (state, 0x15);
*ber |= (ves1x93_readreg (state, 0x16) << 8);
*ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
*ber *= 10;
return 0;
}
static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct ves1x93_state* state = fe->demodulator_priv;
u8 signal = ~ves1x93_readreg (state, 0x0b);
*strength = (signal << 8) | signal;
return 0;
}
static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct ves1x93_state* state = fe->demodulator_priv;
u8 _snr = ~ves1x93_readreg (state, 0x1c);
*snr = (_snr << 8) | _snr;
return 0;
}
static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct ves1x93_state* state = fe->demodulator_priv;
*ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;
if (*ucblocks == 0x7f)
*ucblocks = 0xffffffff; /* counter overflow... */
ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
ves1x93_writereg (state, 0x18, 0x80); /* dto. */
return 0;
}
static int ves1x93_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct ves1x93_state* state = fe->demodulator_priv;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
ves1x93_set_inversion (state, p->inversion);
ves1x93_set_fec(state, p->fec_inner);
ves1x93_set_symbolrate(state, p->symbol_rate);
state->inversion = p->inversion;
state->frequency = p->frequency;
return 0;
}
static int ves1x93_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct ves1x93_state* state = fe->demodulator_priv;
int afc;
afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
afc = (afc * (int)(p->symbol_rate/1000/8))/16;
p->frequency = state->frequency - afc;
/*
* inversion indicator is only valid
* if auto inversion was used
*/
if (state->inversion == INVERSION_AUTO)
p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
INVERSION_OFF : INVERSION_ON;
p->fec_inner = ves1x93_get_fec(state);
/* XXX FIXME: timing offset !! */
return 0;
}
static int ves1x93_sleep(struct dvb_frontend* fe)
{
struct ves1x93_state* state = fe->demodulator_priv;
return ves1x93_writereg (state, 0x00, 0x08);
}
static void ves1x93_release(struct dvb_frontend* fe)
{
struct ves1x93_state* state = fe->demodulator_priv;
kfree(state);
}
static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct ves1x93_state* state = fe->demodulator_priv;
if (enable) {
return ves1x93_writereg(state, 0x00, 0x11);
} else {
return ves1x93_writereg(state, 0x00, 0x01);
}
}
static const struct dvb_frontend_ops ves1x93_ops;
struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
struct i2c_adapter* i2c)
{
struct ves1x93_state* state = NULL;
u8 identity;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->inversion = INVERSION_OFF;
/* check if the demod is there + identify it */
identity = ves1x93_readreg(state, 0x1e);
switch (identity) {
case 0xdc: /* VES1893A rev1 */
printk("ves1x93: Detected ves1893a rev1\n");
state->demod_type = DEMOD_VES1893;
state->init_1x93_tab = init_1893_tab;
state->init_1x93_wtab = init_1893_wtab;
state->tab_size = sizeof(init_1893_tab);
break;
case 0xdd: /* VES1893A rev2 */
printk("ves1x93: Detected ves1893a rev2\n");
state->demod_type = DEMOD_VES1893;
state->init_1x93_tab = init_1893_tab;
state->init_1x93_wtab = init_1893_wtab;
state->tab_size = sizeof(init_1893_tab);
break;
case 0xde: /* VES1993 */
printk("ves1x93: Detected ves1993\n");
state->demod_type = DEMOD_VES1993;
state->init_1x93_tab = init_1993_tab;
state->init_1x93_wtab = init_1993_wtab;
state->tab_size = sizeof(init_1993_tab);
break;
default:
goto error;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops ves1x93_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "VLSI VES1x93 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.frequency_tolerance_hz = 29500 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
/* .symbol_rate_tolerance = ???,*/
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK
},
.release = ves1x93_release,
.init = ves1x93_init,
.sleep = ves1x93_sleep,
.i2c_gate_ctrl = ves1x93_i2c_gate_ctrl,
.set_frontend = ves1x93_set_frontend,
.get_frontend = ves1x93_get_frontend,
.read_status = ves1x93_read_status,
.read_ber = ves1x93_read_ber,
.read_signal_strength = ves1x93_read_signal_strength,
.read_snr = ves1x93_read_snr,
.read_ucblocks = ves1x93_read_ucblocks,
.set_voltage = ves1x93_set_voltage,
};
module_param(debug, int, 0644);
MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(ves1x93_attach);
| linux-master | drivers/media/dvb-frontends/ves1x93.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
*
* Copyright (C) 2009 Devin Heitmueller <[email protected]>
* Copyright (C) 2005-2008 Auvitek International, Ltd.
*/
/* Developer notes:
*
* Enough is implemented here for CVBS and S-Video inputs, but the actual
* analog demodulator code isn't implemented (not needed for xc5000 since it
* has its own demodulator and outputs CVBS)
*
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include "au8522.h"
#include "au8522_priv.h"
MODULE_AUTHOR("Devin Heitmueller");
MODULE_LICENSE("GPL");
static int au8522_analog_debug;
module_param_named(analog_debug, au8522_analog_debug, int, 0644);
MODULE_PARM_DESC(analog_debug,
"Analog debugging messages [0=Off (default) 1=On]");
struct au8522_register_config {
u16 reg_name;
u8 reg_val[8];
};
/* Video Decoder Filter Coefficients
The values are as follows from left to right
0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
*/
static const struct au8522_register_config filter_coef[] = {
{AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
{AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
{AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
{AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
{AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
{AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
{AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
{AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
{AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
{AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
{AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
{AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
{AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
{AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
{AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
{AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
{AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
{AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
{AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
{AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
{AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
{AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
};
#define NUM_FILTER_COEF (sizeof(filter_coef)\
/ sizeof(struct au8522_register_config))
/* Registers 0x060b through 0x0652 are the LP Filter coefficients
The values are as follows from left to right
0="SIF" 1="ATVRF/ATVRF13"
Note: the "ATVRF/ATVRF13" mode has never been tested
*/
static const struct au8522_register_config lpfilter_coef[] = {
{0x060b, {0x21, 0x0b} },
{0x060c, {0xad, 0xad} },
{0x060d, {0x70, 0xf0} },
{0x060e, {0xea, 0xe9} },
{0x060f, {0xdd, 0xdd} },
{0x0610, {0x08, 0x64} },
{0x0611, {0x60, 0x60} },
{0x0612, {0xf8, 0xb2} },
{0x0613, {0x01, 0x02} },
{0x0614, {0xe4, 0xb4} },
{0x0615, {0x19, 0x02} },
{0x0616, {0xae, 0x2e} },
{0x0617, {0xee, 0xc5} },
{0x0618, {0x56, 0x56} },
{0x0619, {0x30, 0x58} },
{0x061a, {0xf9, 0xf8} },
{0x061b, {0x24, 0x64} },
{0x061c, {0x07, 0x07} },
{0x061d, {0x30, 0x30} },
{0x061e, {0xa9, 0xed} },
{0x061f, {0x09, 0x0b} },
{0x0620, {0x42, 0xc2} },
{0x0621, {0x1d, 0x2a} },
{0x0622, {0xd6, 0x56} },
{0x0623, {0x95, 0x8b} },
{0x0624, {0x2b, 0x2b} },
{0x0625, {0x30, 0x24} },
{0x0626, {0x3e, 0x3e} },
{0x0627, {0x62, 0xe2} },
{0x0628, {0xe9, 0xf5} },
{0x0629, {0x99, 0x19} },
{0x062a, {0xd4, 0x11} },
{0x062b, {0x03, 0x04} },
{0x062c, {0xb5, 0x85} },
{0x062d, {0x1e, 0x20} },
{0x062e, {0x2a, 0xea} },
{0x062f, {0xd7, 0xd2} },
{0x0630, {0x15, 0x15} },
{0x0631, {0xa3, 0xa9} },
{0x0632, {0x1f, 0x1f} },
{0x0633, {0xf9, 0xd1} },
{0x0634, {0xc0, 0xc3} },
{0x0635, {0x4d, 0x8d} },
{0x0636, {0x21, 0x31} },
{0x0637, {0x83, 0x83} },
{0x0638, {0x08, 0x8c} },
{0x0639, {0x19, 0x19} },
{0x063a, {0x45, 0xa5} },
{0x063b, {0xef, 0xec} },
{0x063c, {0x8a, 0x8a} },
{0x063d, {0xf4, 0xf6} },
{0x063e, {0x8f, 0x8f} },
{0x063f, {0x44, 0x0c} },
{0x0640, {0xef, 0xf0} },
{0x0641, {0x66, 0x66} },
{0x0642, {0xcc, 0xd2} },
{0x0643, {0x41, 0x41} },
{0x0644, {0x63, 0x93} },
{0x0645, {0x8e, 0x8e} },
{0x0646, {0xa2, 0x42} },
{0x0647, {0x7b, 0x7b} },
{0x0648, {0x04, 0x04} },
{0x0649, {0x00, 0x00} },
{0x064a, {0x40, 0x40} },
{0x064b, {0x8c, 0x98} },
{0x064c, {0x00, 0x00} },
{0x064d, {0x63, 0xc3} },
{0x064e, {0x04, 0x04} },
{0x064f, {0x20, 0x20} },
{0x0650, {0x00, 0x00} },
{0x0651, {0x40, 0x40} },
{0x0652, {0x01, 0x01} },
};
#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
/ sizeof(struct au8522_register_config))
static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct au8522_state, sd);
}
static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
{
int i;
int filter_coef_type;
/* Provide reasonable defaults for picture tuning values */
au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
/* Other decoder registers */
au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
if (is_svideo)
au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
else
au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
AU8522_TVDEC_PGA_REG012H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
AU8522_TVDED_DBG_MODE_REG060H_CVBS);
if (state->std == V4L2_STD_PAL_M) {
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
} else {
/* NTSC */
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
}
au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
if (is_svideo) {
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
} else {
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
}
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
AU8522_TOREGAAGC_REG0E5H_CVBS);
au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
/*
* Despite what the table says, for the HVR-950q we still need
* to be in CVBS mode for the S-Video input (reason unknown).
*/
/* filter_coef_type = 3; */
filter_coef_type = 5;
/* Load the Video Decoder Filter Coefficients */
for (i = 0; i < NUM_FILTER_COEF; i++) {
au8522_writereg(state, filter_coef[i].reg_name,
filter_coef[i].reg_val[filter_coef_type]);
}
/* It's not clear what these registers are for, but they are always
set to the same value regardless of what mode we're in */
au8522_writereg(state, AU8522_REG42EH, 0x87);
au8522_writereg(state, AU8522_REG42FH, 0xa2);
au8522_writereg(state, AU8522_REG430H, 0xbf);
au8522_writereg(state, AU8522_REG431H, 0xcb);
au8522_writereg(state, AU8522_REG432H, 0xa1);
au8522_writereg(state, AU8522_REG433H, 0x41);
au8522_writereg(state, AU8522_REG434H, 0x88);
au8522_writereg(state, AU8522_REG435H, 0xc2);
au8522_writereg(state, AU8522_REG436H, 0x3c);
}
static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
{
/* here we're going to try the pre-programmed route */
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
/* PGA in automatic mode */
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
/* Enable clamping control */
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
setup_decoder_defaults(state, false);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
}
static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
u8 input_mode)
{
/* here we're going to try the pre-programmed route */
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
/* It's not clear why we have to have the PGA in automatic mode while
enabling clamp control, but it's what Windows does */
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
/* Enable clamping control */
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
/* Disable automatic PGA (since the CVBS is coming from the tuner) */
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
/* Set input mode to CVBS on channel 4 with SIF audio input enabled */
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
setup_decoder_defaults(state, false);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
}
static void au8522_setup_svideo_mode(struct au8522_state *state,
u8 input_mode)
{
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
/* Set input to Y on Channe1, C on Channel 3 */
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
/* PGA in automatic mode */
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
/* Enable clamping control */
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
setup_decoder_defaults(state, true);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
}
/* ----------------------------------------------------------------------- */
static void disable_audio_input(struct au8522_state *state)
{
au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
}
/* 0=disable, 1=SIF */
static void set_audio_input(struct au8522_state *state)
{
int aud_input = state->aud_input;
int i;
/* Note that this function needs to be used in conjunction with setting
the input routing via register 0x81 */
if (aud_input == AU8522_AUDIO_NONE) {
disable_audio_input(state);
return;
}
if (aud_input != AU8522_AUDIO_SIF) {
/* The caller asked for a mode we don't currently support */
printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
aud_input);
return;
}
/* Load the Audio Decoder Filter Coefficients */
for (i = 0; i < NUM_LPFILTER_COEF; i++) {
au8522_writereg(state, lpfilter_coef[i].reg_name,
lpfilter_coef[i].reg_val[0]);
}
/* Set the volume */
au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
/* Not sure what this does */
au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
/* Setup the audio mode to stereo DBX */
au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
msleep(70);
/* Start the audio processing module */
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
/* Set the audio frequency to 48 KHz */
au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
/* Set the I2S parameters (WS, LSB, mode, sample rate */
au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
/* Enable the I2S output */
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
}
/* ----------------------------------------------------------------------- */
static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct au8522_state *state =
container_of(ctrl->handler, struct au8522_state, hdl);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
ctrl->val - 128);
break;
case V4L2_CID_CONTRAST:
au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
ctrl->val);
break;
case V4L2_CID_SATURATION:
au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
ctrl->val);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
ctrl->val);
break;
case V4L2_CID_HUE:
au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
ctrl->val >> 8);
au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
ctrl->val & 0xFF);
break;
default:
return -EINVAL;
}
return 0;
}
/* ----------------------------------------------------------------------- */
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int au8522_g_register(struct v4l2_subdev *sd,
struct v4l2_dbg_register *reg)
{
struct au8522_state *state = to_state(sd);
reg->val = au8522_readreg(state, reg->reg & 0xffff);
return 0;
}
static int au8522_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct au8522_state *state = to_state(sd);
au8522_writereg(state, reg->reg, reg->val & 0xff);
return 0;
}
#endif
static void au8522_video_set(struct au8522_state *state)
{
u8 input_mode;
au8522_writereg(state, 0xa4, 1 << 5);
switch (state->vid_input) {
case AU8522_COMPOSITE_CH1:
input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
au8522_setup_cvbs_mode(state, input_mode);
break;
case AU8522_COMPOSITE_CH2:
input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
au8522_setup_cvbs_mode(state, input_mode);
break;
case AU8522_COMPOSITE_CH3:
input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
au8522_setup_cvbs_mode(state, input_mode);
break;
case AU8522_COMPOSITE_CH4:
input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
au8522_setup_cvbs_mode(state, input_mode);
break;
case AU8522_SVIDEO_CH13:
input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
au8522_setup_svideo_mode(state, input_mode);
break;
case AU8522_SVIDEO_CH24:
input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
au8522_setup_svideo_mode(state, input_mode);
break;
default:
case AU8522_COMPOSITE_CH4_SIF:
input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
au8522_setup_cvbs_tuner_mode(state, input_mode);
break;
}
}
static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
{
struct au8522_state *state = to_state(sd);
if (enable) {
/*
* Clear out any state associated with the digital side of the
* chip, so that when it gets powered back up it won't think
* that it is already tuned
*/
state->current_frequency = 0;
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0x01);
msleep(10);
au8522_video_set(state);
set_audio_input(state);
state->operational_mode = AU8522_ANALOG_MODE;
} else {
/* This does not completely power down the device
(it only reduces it from around 140ma to 80ma) */
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
1 << 5);
state->operational_mode = AU8522_SUSPEND_MODE;
}
return 0;
}
static int au8522_s_video_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct au8522_state *state = to_state(sd);
switch (input) {
case AU8522_COMPOSITE_CH1:
case AU8522_SVIDEO_CH13:
case AU8522_COMPOSITE_CH4_SIF:
state->vid_input = input;
break;
default:
printk(KERN_ERR "au8522 mode not currently supported\n");
return -EINVAL;
}
if (state->operational_mode == AU8522_ANALOG_MODE)
au8522_video_set(state);
return 0;
}
static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
struct au8522_state *state = to_state(sd);
if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
return -EINVAL;
state->std = std;
if (state->operational_mode == AU8522_ANALOG_MODE)
au8522_video_set(state);
return 0;
}
static int au8522_s_audio_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct au8522_state *state = to_state(sd);
state->aud_input = input;
if (state->operational_mode == AU8522_ANALOG_MODE)
set_audio_input(state);
return 0;
}
static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
{
int val = 0;
struct au8522_state *state = to_state(sd);
u8 lock_status;
u8 pll_status;
/* Interrogate the decoder to see if we are getting a real signal */
lock_status = au8522_readreg(state, 0x00);
pll_status = au8522_readreg(state, 0x7e);
if ((lock_status == 0xa2) && (pll_status & 0x10))
vt->signal = 0xffff;
else
vt->signal = 0x00;
vt->capability |=
V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
val = V4L2_TUNER_SUB_MONO;
vt->rxsubchans = val;
vt->audmode = V4L2_TUNER_MODE_STEREO;
return 0;
}
/* ----------------------------------------------------------------------- */
static const struct v4l2_subdev_core_ops au8522_core_ops = {
.log_status = v4l2_ctrl_subdev_log_status,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = au8522_g_register,
.s_register = au8522_s_register,
#endif
};
static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
.g_tuner = au8522_g_tuner,
};
static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
.s_routing = au8522_s_audio_routing,
};
static const struct v4l2_subdev_video_ops au8522_video_ops = {
.s_routing = au8522_s_video_routing,
.s_stream = au8522_s_stream,
.s_std = au8522_s_std,
};
static const struct v4l2_subdev_ops au8522_ops = {
.core = &au8522_core_ops,
.tuner = &au8522_tuner_ops,
.audio = &au8522_audio_ops,
.video = &au8522_video_ops,
};
static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
.s_ctrl = au8522_s_ctrl,
};
/* ----------------------------------------------------------------------- */
static int au8522_probe(struct i2c_client *client)
{
struct au8522_state *state;
struct v4l2_ctrl_handler *hdl;
struct v4l2_subdev *sd;
int instance;
#ifdef CONFIG_MEDIA_CONTROLLER
int ret;
#endif
/* Check if the adapter supports the needed features */
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
return -EIO;
}
/* allocate memory for the internal state */
instance = au8522_get_state(&state, client->adapter, client->addr);
switch (instance) {
case 0:
printk(KERN_ERR "au8522_decoder allocation failed\n");
return -EIO;
case 1:
/* new demod instance */
printk(KERN_INFO "au8522_decoder creating new instance...\n");
break;
default:
/* existing demod instance */
printk(KERN_INFO "au8522_decoder attach existing instance.\n");
break;
}
state->config.demod_address = 0x8e >> 1;
state->i2c = client->adapter;
sd = &state->sd;
v4l2_i2c_subdev_init(sd, client, &au8522_ops);
#if defined(CONFIG_MEDIA_CONTROLLER)
state->pads[AU8522_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
state->pads[AU8522_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG;
state->pads[AU8522_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
state->pads[AU8522_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV;
state->pads[AU8522_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
state->pads[AU8522_PAD_AUDIO_OUT].sig_type = PAD_SIGNAL_AUDIO;
sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
state->pads);
if (ret < 0) {
v4l_info(client, "failed to initialize media entity!\n");
return ret;
}
#endif
hdl = &state->hdl;
v4l2_ctrl_handler_init(hdl, 4);
v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
V4L2_CID_CONTRAST, 0, 255, 1,
AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
V4L2_CID_SATURATION, 0, 255, 1, 128);
v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
V4L2_CID_HUE, -32768, 32767, 1, 0);
sd->ctrl_handler = hdl;
if (hdl->error) {
int err = hdl->error;
v4l2_ctrl_handler_free(hdl);
au8522_release_state(state);
return err;
}
state->c = client;
state->std = V4L2_STD_NTSC_M;
state->vid_input = AU8522_COMPOSITE_CH1;
state->aud_input = AU8522_AUDIO_NONE;
state->id = 8522;
state->rev = 0;
/* Jam open the i2c gate to the tuner */
au8522_writereg(state, 0x106, 1);
return 0;
}
static void au8522_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
v4l2_device_unregister_subdev(sd);
v4l2_ctrl_handler_free(sd->ctrl_handler);
au8522_release_state(to_state(sd));
}
static const struct i2c_device_id au8522_id[] = {
{"au8522", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, au8522_id);
static struct i2c_driver au8522_driver = {
.driver = {
.name = "au8522",
},
.probe = au8522_probe,
.remove = au8522_remove,
.id_table = au8522_id,
};
module_i2c_driver(au8522_driver);
| linux-master | drivers/media/dvb-frontends/au8522_decoder.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
STV6110(A) Silicon tuner driver
Copyright (C) Manu Abraham <[email protected]>
Copyright (C) ST Microelectronics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <media/dvb_frontend.h>
#include "stv6110x_reg.h"
#include "stv6110x.h"
#include "stv6110x_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static unsigned int verbose;
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
{
int ret;
const struct stv6110x_config *config = stv6110x->config;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = config->addr, .flags = 0, .buf = b0, .len = 1 },
{ .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 }
};
ret = i2c_transfer(stv6110x->i2c, msg, 2);
if (ret != 2) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EREMOTEIO;
}
*data = b1[0];
return 0;
}
static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 data[], int len)
{
int ret;
const struct stv6110x_config *config = stv6110x->config;
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = config->addr,
.flags = 0,
.buf = buf,
.len = len + 1
};
if (1 + len > sizeof(buf)) {
printk(KERN_WARNING
"%s: i2c wr: len=%d is too big!\n",
KBUILD_MODNAME, len);
return -EINVAL;
}
if (start + len > 8)
return -EINVAL;
buf[0] = start;
memcpy(&buf[1], data, len);
ret = i2c_transfer(stv6110x->i2c, &msg, 1);
if (ret != 1) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EREMOTEIO;
}
return 0;
}
static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
{
u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return stv6110x_write_regs(stv6110x, reg, &tmp, 1);
}
static int stv6110x_init(struct dvb_frontend *fe)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
int ret;
ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs,
ARRAY_SIZE(stv6110x->regs));
if (ret < 0) {
dprintk(FE_ERROR, 1, "Initialization failed");
return -1;
}
return 0;
}
static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
u32 rDiv, divider;
s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000;
u8 i;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
if (frequency <= 1023000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
pVal = 40;
} else if (frequency <= 1300000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
pVal = 40;
} else if (frequency <= 2046000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
pVal = 20;
} else {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
pVal = 20;
}
for (rDiv = 0; rDiv <= 3; rDiv++) {
pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal))))
rDivOpt = rDiv;
pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt);
}
divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
divider = (divider + 5) / 10;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
/* VCO Auto calibration */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x->regs[STV6110x_TNG1]);
stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x->regs[STV6110x_TNG0]);
stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
for (i = 0; i < TRIALS; i++) {
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x->regs[STV6110x_STAT1]))
break;
msleep(1);
}
return 0;
}
static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x->regs[STV6110x_TNG1]);
stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x->regs[STV6110x_TNG0]);
*frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x->regs[STV6110x_TNG1]),
STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x->regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
*frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x->regs[STV6110x_TNG1]) +
STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x->regs[STV6110x_TNG1])));
*frequency >>= 2;
return 0;
}
static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
u32 halfbw;
u8 i;
halfbw = bandwidth >> 1;
if (halfbw > 36000000)
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
else if (halfbw < 5000000)
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
else
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
for (i = 0; i < TRIALS; i++) {
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x->regs[STV6110x_STAT1]))
break;
msleep(1);
}
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
return 0;
}
static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x->regs[STV6110x_CTRL3]);
*bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x->regs[STV6110x_CTRL3]) + 5) * 2000000;
return 0;
}
static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
/* setup divider */
switch (refclock) {
default:
case 1:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
break;
case 2:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
break;
case 4:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
break;
case 8:
case 0:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
break;
}
stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x->regs[STV6110x_CTRL2]);
*gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
int ret;
switch (mode) {
case TUNER_SLEEP:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 0);
break;
case TUNER_WAKE:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 1);
break;
}
ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
if (ret < 0) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EIO;
}
return 0;
}
static int stv6110x_sleep(struct dvb_frontend *fe)
{
if (fe->tuner_priv)
return stv6110x_set_mode(fe, TUNER_SLEEP);
return 0;
}
static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x->regs[STV6110x_STAT1]))
*status = TUNER_PHASELOCKED;
else
*status = 0;
return 0;
}
static void stv6110x_release(struct dvb_frontend *fe)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(stv6110x);
}
static void st6110x_init_regs(struct stv6110x_state *stv6110x)
{
u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
memcpy(stv6110x->regs, default_regs, 8);
}
static void stv6110x_setup_divider(struct stv6110x_state *stv6110x)
{
switch (stv6110x->config->clk_div) {
default:
case 1:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2],
CTRL2_CO_DIV,
0);
break;
case 2:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2],
CTRL2_CO_DIV,
1);
break;
case 4:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2],
CTRL2_CO_DIV,
2);
break;
case 8:
case 0:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2],
CTRL2_CO_DIV,
3);
break;
}
}
static const struct dvb_tuner_ops stv6110x_ops = {
.info = {
.name = "STV6110(A) Silicon Tuner",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
},
.release = stv6110x_release
};
static struct stv6110x_devctl stv6110x_ctl = {
.tuner_init = stv6110x_init,
.tuner_sleep = stv6110x_sleep,
.tuner_set_mode = stv6110x_set_mode,
.tuner_set_frequency = stv6110x_set_frequency,
.tuner_get_frequency = stv6110x_get_frequency,
.tuner_set_bandwidth = stv6110x_set_bandwidth,
.tuner_get_bandwidth = stv6110x_get_bandwidth,
.tuner_set_bbgain = stv6110x_set_bbgain,
.tuner_get_bbgain = stv6110x_get_bbgain,
.tuner_set_refclk = stv6110x_set_refclock,
.tuner_get_status = stv6110x_get_status,
};
static void stv6110x_set_frontend_opts(struct stv6110x_state *stv6110x)
{
stv6110x->frontend->tuner_priv = stv6110x;
stv6110x->frontend->ops.tuner_ops = stv6110x_ops;
}
static struct stv6110x_devctl *stv6110x_get_devctl(struct i2c_client *client)
{
struct stv6110x_state *stv6110x = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return stv6110x->devctl;
}
static int stv6110x_probe(struct i2c_client *client)
{
struct stv6110x_config *config = client->dev.platform_data;
struct stv6110x_state *stv6110x;
stv6110x = kzalloc(sizeof(*stv6110x), GFP_KERNEL);
if (!stv6110x)
return -ENOMEM;
stv6110x->frontend = config->frontend;
stv6110x->i2c = client->adapter;
stv6110x->config = config;
stv6110x->devctl = &stv6110x_ctl;
st6110x_init_regs(stv6110x);
stv6110x_setup_divider(stv6110x);
stv6110x_set_frontend_opts(stv6110x);
dev_info(&stv6110x->i2c->dev, "Probed STV6110x\n");
i2c_set_clientdata(client, stv6110x);
/* setup callbacks */
config->get_devctl = stv6110x_get_devctl;
return 0;
}
static void stv6110x_remove(struct i2c_client *client)
{
struct stv6110x_state *stv6110x = i2c_get_clientdata(client);
stv6110x_release(stv6110x->frontend);
}
const struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
const struct stv6110x_config *config,
struct i2c_adapter *i2c)
{
struct stv6110x_state *stv6110x;
stv6110x = kzalloc(sizeof(*stv6110x), GFP_KERNEL);
if (!stv6110x)
return NULL;
stv6110x->frontend = fe;
stv6110x->i2c = i2c;
stv6110x->config = config;
stv6110x->devctl = &stv6110x_ctl;
st6110x_init_regs(stv6110x);
stv6110x_setup_divider(stv6110x);
stv6110x_set_frontend_opts(stv6110x);
fe->tuner_priv = stv6110x;
fe->ops.tuner_ops = stv6110x_ops;
dev_info(&stv6110x->i2c->dev, "Attaching STV6110x\n");
return stv6110x->devctl;
}
EXPORT_SYMBOL_GPL(stv6110x_attach);
static const struct i2c_device_id stv6110x_id_table[] = {
{"stv6110x", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, stv6110x_id_table);
static struct i2c_driver stv6110x_driver = {
.driver = {
.name = "stv6110x",
.suppress_bind_attrs = true,
},
.probe = stv6110x_probe,
.remove = stv6110x_remove,
.id_table = stv6110x_id_table,
};
module_i2c_driver(stv6110x_driver);
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("STV6110x Silicon tuner");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv6110x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
NxtWave Communications - NXT6000 demodulator driver
Copyright (C) 2002-2003 Florian Schirmer <[email protected]>
Copyright (C) 2003 Paul Andreassen <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "nxt6000_priv.h"
#include "nxt6000.h"
struct nxt6000_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct nxt6000_config* config;
struct dvb_frontend frontend;
};
static int debug;
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
static int nxt6000_writereg(struct nxt6000_state* state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
int ret;
if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
dprintk("nxt6000: nxt6000_write error (reg: 0x%02X, data: 0x%02X, ret: %d)\n", reg, data, ret);
return (ret != 1) ? -EIO : 0;
}
static u8 nxt6000_readreg(struct nxt6000_state* state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msgs[] = {
{.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
};
ret = i2c_transfer(state->i2c, msgs, 2);
if (ret != 2)
dprintk("nxt6000: nxt6000_read error (reg: 0x%02X, ret: %d)\n", reg, ret);
return b1[0];
}
static void nxt6000_reset(struct nxt6000_state* state)
{
u8 val;
val = nxt6000_readreg(state, OFDM_COR_CTL);
nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT);
nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT);
}
static int nxt6000_set_bandwidth(struct nxt6000_state *state, u32 bandwidth)
{
u16 nominal_rate;
int result;
switch (bandwidth) {
case 6000000:
nominal_rate = 0x55B7;
break;
case 7000000:
nominal_rate = 0x6400;
break;
case 8000000:
nominal_rate = 0x7249;
break;
default:
return -EINVAL;
}
if ((result = nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, nominal_rate & 0xFF)) < 0)
return result;
return nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, (nominal_rate >> 8) & 0xFF);
}
static int nxt6000_set_guard_interval(struct nxt6000_state *state,
enum fe_guard_interval guard_interval)
{
switch (guard_interval) {
case GUARD_INTERVAL_1_32:
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x00 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
case GUARD_INTERVAL_1_16:
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x01 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
case GUARD_INTERVAL_AUTO:
case GUARD_INTERVAL_1_8:
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x02 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
case GUARD_INTERVAL_1_4:
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x03 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
default:
return -EINVAL;
}
}
static int nxt6000_set_inversion(struct nxt6000_state *state,
enum fe_spectral_inversion inversion)
{
switch (inversion) {
case INVERSION_OFF:
return nxt6000_writereg(state, OFDM_ITB_CTL, 0x00);
case INVERSION_ON:
return nxt6000_writereg(state, OFDM_ITB_CTL, ITBINV);
default:
return -EINVAL;
}
}
static int
nxt6000_set_transmission_mode(struct nxt6000_state *state,
enum fe_transmit_mode transmission_mode)
{
int result;
switch (transmission_mode) {
case TRANSMISSION_MODE_2K:
if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x00 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
return result;
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x00 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
case TRANSMISSION_MODE_8K:
case TRANSMISSION_MODE_AUTO:
if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x02 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
return result;
return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x01 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
default:
return -EINVAL;
}
}
static void nxt6000_setup(struct dvb_frontend* fe)
{
struct nxt6000_state* state = fe->demodulator_priv;
nxt6000_writereg(state, RS_COR_SYNC_PARAM, SYNC_PARAM);
nxt6000_writereg(state, BER_CTRL, /*(1 << 2) | */ (0x01 << 1) | 0x01);
nxt6000_writereg(state, VIT_BERTIME_2, 0x00); // BER Timer = 0x000200 * 256 = 131072 bits
nxt6000_writereg(state, VIT_BERTIME_1, 0x02); //
nxt6000_writereg(state, VIT_BERTIME_0, 0x00); //
nxt6000_writereg(state, VIT_COR_INTEN, 0x98); // Enable BER interrupts
nxt6000_writereg(state, VIT_COR_CTL, 0x82); // Enable BER measurement
nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC | 0x02 );
nxt6000_writereg(state, OFDM_COR_CTL, (0x01 << 5) | (nxt6000_readreg(state, OFDM_COR_CTL) & 0x0F));
nxt6000_writereg(state, OFDM_COR_MODEGUARD, FORCEMODE8K | 0x02);
nxt6000_writereg(state, OFDM_AGC_CTL, AGCLAST | INITIAL_AGC_BW);
nxt6000_writereg(state, OFDM_ITB_FREQ_1, 0x06);
nxt6000_writereg(state, OFDM_ITB_FREQ_2, 0x31);
nxt6000_writereg(state, OFDM_CAS_CTL, (0x01 << 7) | (0x02 << 3) | 0x04);
nxt6000_writereg(state, CAS_FREQ, 0xBB); /* CHECKME */
nxt6000_writereg(state, OFDM_SYR_CTL, 1 << 2);
nxt6000_writereg(state, OFDM_PPM_CTL_1, PPM256);
nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, 0x49);
nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, 0x72);
nxt6000_writereg(state, ANALOG_CONTROL_0, 1 << 5);
nxt6000_writereg(state, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2);
nxt6000_writereg(state, DIAG_CONFIG, TB_SET);
if (state->config->clock_inversion)
nxt6000_writereg(state, SUB_DIAG_MODE_SEL, CLKINVERSION);
else
nxt6000_writereg(state, SUB_DIAG_MODE_SEL, 0);
nxt6000_writereg(state, TS_FORMAT, 0);
}
static void nxt6000_dump_status(struct nxt6000_state *state)
{
u8 val;
#if 0
pr_info("RS_COR_STAT: 0x%02X\n",
nxt6000_readreg(fe, RS_COR_STAT));
pr_info("VIT_SYNC_STATUS: 0x%02X\n",
nxt6000_readreg(fe, VIT_SYNC_STATUS));
pr_info("OFDM_COR_STAT: 0x%02X\n",
nxt6000_readreg(fe, OFDM_COR_STAT));
pr_info("OFDM_SYR_STAT: 0x%02X\n",
nxt6000_readreg(fe, OFDM_SYR_STAT));
pr_info("OFDM_TPS_RCVD_1: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RCVD_1));
pr_info("OFDM_TPS_RCVD_2: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RCVD_2));
pr_info("OFDM_TPS_RCVD_3: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RCVD_3));
pr_info("OFDM_TPS_RCVD_4: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RCVD_4));
pr_info("OFDM_TPS_RESERVED_1: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RESERVED_1));
pr_info("OFDM_TPS_RESERVED_2: 0x%02X\n",
nxt6000_readreg(fe, OFDM_TPS_RESERVED_2));
#endif
pr_info("NXT6000 status:");
val = nxt6000_readreg(state, RS_COR_STAT);
pr_cont(" DATA DESCR LOCK: %d,", val & 0x01);
pr_cont(" DATA SYNC LOCK: %d,", (val >> 1) & 0x01);
val = nxt6000_readreg(state, VIT_SYNC_STATUS);
pr_cont(" VITERBI LOCK: %d,", (val >> 7) & 0x01);
switch ((val >> 4) & 0x07) {
case 0x00:
pr_cont(" VITERBI CODERATE: 1/2,");
break;
case 0x01:
pr_cont(" VITERBI CODERATE: 2/3,");
break;
case 0x02:
pr_cont(" VITERBI CODERATE: 3/4,");
break;
case 0x03:
pr_cont(" VITERBI CODERATE: 5/6,");
break;
case 0x04:
pr_cont(" VITERBI CODERATE: 7/8,");
break;
default:
pr_cont(" VITERBI CODERATE: Reserved,");
}
val = nxt6000_readreg(state, OFDM_COR_STAT);
pr_cont(" CHCTrack: %d,", (val >> 7) & 0x01);
pr_cont(" TPSLock: %d,", (val >> 6) & 0x01);
pr_cont(" SYRLock: %d,", (val >> 5) & 0x01);
pr_cont(" AGCLock: %d,", (val >> 4) & 0x01);
switch (val & 0x0F) {
case 0x00:
pr_cont(" CoreState: IDLE,");
break;
case 0x02:
pr_cont(" CoreState: WAIT_AGC,");
break;
case 0x03:
pr_cont(" CoreState: WAIT_SYR,");
break;
case 0x04:
pr_cont(" CoreState: WAIT_PPM,");
break;
case 0x01:
pr_cont(" CoreState: WAIT_TRL,");
break;
case 0x05:
pr_cont(" CoreState: WAIT_TPS,");
break;
case 0x06:
pr_cont(" CoreState: MONITOR_TPS,");
break;
default:
pr_cont(" CoreState: Reserved,");
}
val = nxt6000_readreg(state, OFDM_SYR_STAT);
pr_cont(" SYRLock: %d,", (val >> 4) & 0x01);
pr_cont(" SYRMode: %s,", (val >> 2) & 0x01 ? "8K" : "2K");
switch ((val >> 4) & 0x03) {
case 0x00:
pr_cont(" SYRGuard: 1/32,");
break;
case 0x01:
pr_cont(" SYRGuard: 1/16,");
break;
case 0x02:
pr_cont(" SYRGuard: 1/8,");
break;
case 0x03:
pr_cont(" SYRGuard: 1/4,");
break;
}
val = nxt6000_readreg(state, OFDM_TPS_RCVD_3);
switch ((val >> 4) & 0x07) {
case 0x00:
pr_cont(" TPSLP: 1/2,");
break;
case 0x01:
pr_cont(" TPSLP: 2/3,");
break;
case 0x02:
pr_cont(" TPSLP: 3/4,");
break;
case 0x03:
pr_cont(" TPSLP: 5/6,");
break;
case 0x04:
pr_cont(" TPSLP: 7/8,");
break;
default:
pr_cont(" TPSLP: Reserved,");
}
switch (val & 0x07) {
case 0x00:
pr_cont(" TPSHP: 1/2,");
break;
case 0x01:
pr_cont(" TPSHP: 2/3,");
break;
case 0x02:
pr_cont(" TPSHP: 3/4,");
break;
case 0x03:
pr_cont(" TPSHP: 5/6,");
break;
case 0x04:
pr_cont(" TPSHP: 7/8,");
break;
default:
pr_cont(" TPSHP: Reserved,");
}
val = nxt6000_readreg(state, OFDM_TPS_RCVD_4);
pr_cont(" TPSMode: %s,", val & 0x01 ? "8K" : "2K");
switch ((val >> 4) & 0x03) {
case 0x00:
pr_cont(" TPSGuard: 1/32,");
break;
case 0x01:
pr_cont(" TPSGuard: 1/16,");
break;
case 0x02:
pr_cont(" TPSGuard: 1/8,");
break;
case 0x03:
pr_cont(" TPSGuard: 1/4,");
break;
}
/* Strange magic required to gain access to RF_AGC_STATUS */
nxt6000_readreg(state, RF_AGC_VAL_1);
val = nxt6000_readreg(state, RF_AGC_STATUS);
val = nxt6000_readreg(state, RF_AGC_STATUS);
pr_cont(" RF AGC LOCK: %d,", (val >> 4) & 0x01);
pr_cont("\n");
}
static int nxt6000_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
u8 core_status;
struct nxt6000_state* state = fe->demodulator_priv;
*status = 0;
core_status = nxt6000_readreg(state, OFDM_COR_STAT);
if (core_status & AGCLOCKED)
*status |= FE_HAS_SIGNAL;
if (nxt6000_readreg(state, OFDM_SYR_STAT) & GI14_SYR_LOCK)
*status |= FE_HAS_CARRIER;
if (nxt6000_readreg(state, VIT_SYNC_STATUS) & VITINSYNC)
*status |= FE_HAS_VITERBI;
if (nxt6000_readreg(state, RS_COR_STAT) & RSCORESTATUS)
*status |= FE_HAS_SYNC;
if ((core_status & TPSLOCKED) && (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)))
*status |= FE_HAS_LOCK;
if (debug)
nxt6000_dump_status(state);
return 0;
}
static int nxt6000_init(struct dvb_frontend* fe)
{
struct nxt6000_state* state = fe->demodulator_priv;
nxt6000_reset(state);
nxt6000_setup(fe);
return 0;
}
static int nxt6000_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct nxt6000_state* state = fe->demodulator_priv;
int result;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
result = nxt6000_set_bandwidth(state, p->bandwidth_hz);
if (result < 0)
return result;
result = nxt6000_set_guard_interval(state, p->guard_interval);
if (result < 0)
return result;
result = nxt6000_set_transmission_mode(state, p->transmission_mode);
if (result < 0)
return result;
result = nxt6000_set_inversion(state, p->inversion);
if (result < 0)
return result;
msleep(500);
return 0;
}
static void nxt6000_release(struct dvb_frontend* fe)
{
struct nxt6000_state* state = fe->demodulator_priv;
kfree(state);
}
static int nxt6000_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct nxt6000_state* state = fe->demodulator_priv;
*snr = nxt6000_readreg( state, OFDM_CHC_SNR) / 8;
return 0;
}
static int nxt6000_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct nxt6000_state* state = fe->demodulator_priv;
nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18 );
*ber = (nxt6000_readreg( state, VIT_BER_1 ) << 8 ) |
nxt6000_readreg( state, VIT_BER_0 );
nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18); // Clear BER Done interrupts
return 0;
}
static int nxt6000_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
struct nxt6000_state* state = fe->demodulator_priv;
*signal_strength = (short) (511 -
(nxt6000_readreg(state, AGC_GAIN_1) +
((nxt6000_readreg(state, AGC_GAIN_2) & 0x03) << 8)));
return 0;
}
static int nxt6000_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 500;
return 0;
}
static int nxt6000_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct nxt6000_state* state = fe->demodulator_priv;
if (enable) {
return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x01);
} else {
return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x00);
}
}
static const struct dvb_frontend_ops nxt6000_ops;
struct dvb_frontend* nxt6000_attach(const struct nxt6000_config* config,
struct i2c_adapter* i2c)
{
struct nxt6000_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct nxt6000_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if (nxt6000_readreg(state, OFDM_MSC_REV) != NXT6000ASICDEVICE) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &nxt6000_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops nxt6000_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "NxtWave NXT6000 DVB-T",
.frequency_min_hz = 0,
.frequency_max_hz = 863250 * kHz,
.frequency_stepsize_hz = 62500,
/*.frequency_tolerance = *//* FIXME: 12% of SR */
.symbol_rate_min = 0, /* FIXME */
.symbol_rate_max = 9360000, /* FIXME */
.symbol_rate_tolerance = 4000,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO,
},
.release = nxt6000_release,
.init = nxt6000_init,
.i2c_gate_ctrl = nxt6000_i2c_gate_ctrl,
.get_tune_settings = nxt6000_fe_get_tune_settings,
.set_frontend = nxt6000_set_frontend,
.read_status = nxt6000_read_status,
.read_ber = nxt6000_read_ber,
.read_signal_strength = nxt6000_read_signal_strength,
.read_snr = nxt6000_read_snr,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("NxtWave NXT6000 DVB-T demodulator driver");
MODULE_AUTHOR("Florian Schirmer");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(nxt6000_attach);
| linux-master | drivers/media/dvb-frontends/nxt6000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lnbh25.c
*
* Driver for LNB supply and control IC LNBH25
*
* Copyright (C) 2014 NetUP Inc.
* Copyright (C) 2014 Sergey Kozlov <[email protected]>
* Copyright (C) 2014 Abylay Ospan <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "lnbh25.h"
/**
* struct lnbh25_priv - LNBH25 driver private data
* @i2c: pointer to the I2C adapter structure
* @i2c_address: I2C address of LNBH25 SEC chip
* @config: Registers configuration:
* offset 0: 1st register address, always 0x02 (DATA1)
* offset 1: DATA1 register value
* offset 2: DATA2 register value
*/
struct lnbh25_priv {
struct i2c_adapter *i2c;
u8 i2c_address;
u8 config[3];
};
#define LNBH25_STATUS_OFL 0x1
#define LNBH25_STATUS_VMON 0x4
#define LNBH25_VSEL_13 0x03
#define LNBH25_VSEL_18 0x0a
static int lnbh25_read_vmon(struct lnbh25_priv *priv)
{
int i, ret;
u8 addr = 0x00;
u8 status[6];
struct i2c_msg msg[2] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = 1,
.buf = &addr
}, {
.addr = priv->i2c_address,
.flags = I2C_M_RD,
.len = sizeof(status),
.buf = status
}
};
for (i = 0; i < 2; i++) {
ret = i2c_transfer(priv->i2c, &msg[i], 1);
if (ret >= 0 && ret != 1)
ret = -EIO;
if (ret < 0) {
dev_dbg(&priv->i2c->dev,
"%s(): I2C transfer %d failed (%d)\n",
__func__, i, ret);
return ret;
}
}
dev_dbg(&priv->i2c->dev, "%s(): %*ph\n",
__func__, (int) sizeof(status), status);
if ((status[0] & (LNBH25_STATUS_OFL | LNBH25_STATUS_VMON)) != 0) {
dev_err(&priv->i2c->dev,
"%s(): voltage in failure state, status reg 0x%x\n",
__func__, status[0]);
return -EIO;
}
return 0;
}
static int lnbh25_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
int ret;
u8 data1_reg;
const char *vsel;
struct lnbh25_priv *priv = fe->sec_priv;
struct i2c_msg msg = {
.addr = priv->i2c_address,
.flags = 0,
.len = sizeof(priv->config),
.buf = priv->config
};
switch (voltage) {
case SEC_VOLTAGE_OFF:
data1_reg = 0x00;
vsel = "Off";
break;
case SEC_VOLTAGE_13:
data1_reg = LNBH25_VSEL_13;
vsel = "13V";
break;
case SEC_VOLTAGE_18:
data1_reg = LNBH25_VSEL_18;
vsel = "18V";
break;
default:
return -EINVAL;
}
priv->config[1] = data1_reg;
dev_dbg(&priv->i2c->dev,
"%s(): %s, I2C 0x%x write [ %02x %02x %02x ]\n",
__func__, vsel, priv->i2c_address,
priv->config[0], priv->config[1], priv->config[2]);
ret = i2c_transfer(priv->i2c, &msg, 1);
if (ret >= 0 && ret != 1)
ret = -EIO;
if (ret < 0) {
dev_err(&priv->i2c->dev, "%s(): I2C transfer error (%d)\n",
__func__, ret);
return ret;
}
if (voltage != SEC_VOLTAGE_OFF) {
msleep(120);
ret = lnbh25_read_vmon(priv);
} else {
msleep(20);
ret = 0;
}
return ret;
}
static void lnbh25_release(struct dvb_frontend *fe)
{
struct lnbh25_priv *priv = fe->sec_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
lnbh25_set_voltage(fe, SEC_VOLTAGE_OFF);
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe,
struct lnbh25_config *cfg,
struct i2c_adapter *i2c)
{
struct lnbh25_priv *priv;
dev_dbg(&i2c->dev, "%s()\n", __func__);
priv = kzalloc(sizeof(struct lnbh25_priv), GFP_KERNEL);
if (!priv)
return NULL;
priv->i2c_address = (cfg->i2c_address >> 1);
priv->i2c = i2c;
priv->config[0] = 0x02;
priv->config[1] = 0x00;
priv->config[2] = cfg->data2_config;
fe->sec_priv = priv;
if (lnbh25_set_voltage(fe, SEC_VOLTAGE_OFF)) {
dev_err(&i2c->dev,
"%s(): no LNBH25 found at I2C addr 0x%02x\n",
__func__, priv->i2c_address);
kfree(priv);
fe->sec_priv = NULL;
return NULL;
}
fe->ops.release_sec = lnbh25_release;
fe->ops.set_voltage = lnbh25_set_voltage;
dev_info(&i2c->dev, "%s(): attached at I2C addr 0x%02x\n",
__func__, priv->i2c_address);
return fe;
}
EXPORT_SYMBOL_GPL(lnbh25_attach);
MODULE_DESCRIPTION("ST LNBH25 driver");
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/lnbh25.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for
* Samsung S5H1420 and
* PnpNetwork PN1010 QPSK Demodulator
*
* Copyright (C) 2005 Andrew de Quincey <[email protected]>
* Copyright (C) 2005-8 Patrick Boettcher <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <asm/div64.h>
#include <linux/i2c.h>
#include <media/dvb_frontend.h>
#include "s5h1420.h"
#include "s5h1420_priv.h"
#define TONE_FREQ 22000
struct s5h1420_state {
struct i2c_adapter* i2c;
const struct s5h1420_config* config;
struct dvb_frontend frontend;
struct i2c_adapter tuner_i2c_adapter;
u8 CON_1_val;
u8 postlocked:1;
u32 fclk;
u32 tunedfreq;
enum fe_code_rate fec_inner;
u32 symbol_rate;
/* FIXME: ugly workaround for flexcop's incapable i2c-controller
* it does not support repeated-start, workaround: write addr-1
* and then read
*/
u8 shadow[256];
};
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings);
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debugging");
#define dprintk(x...) do { \
if (debug) \
printk(KERN_DEBUG "S5H1420: " x); \
} while (0)
static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
{
int ret;
u8 b[2];
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
{ .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
};
b[0] = (reg - 1) & 0xff;
b[1] = state->shadow[(reg - 1) & 0xff];
if (state->config->repeated_start_workaround) {
ret = i2c_transfer(state->i2c, msg, 3);
if (ret != 3)
return ret;
} else {
ret = i2c_transfer(state->i2c, &msg[1], 1);
if (ret != 1)
return ret;
ret = i2c_transfer(state->i2c, &msg[2], 1);
if (ret != 1)
return ret;
}
/* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
return b[0];
}
static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int err;
/* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
return -EREMOTEIO;
}
state->shadow[reg] = data;
return 0;
}
static int s5h1420_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct s5h1420_state* state = fe->demodulator_priv;
dprintk("enter %s\n", __func__);
switch(voltage) {
case SEC_VOLTAGE_13:
s5h1420_writereg(state, 0x3c,
(s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
break;
case SEC_VOLTAGE_18:
s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
break;
case SEC_VOLTAGE_OFF:
s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
break;
}
dprintk("leave %s\n", __func__);
return 0;
}
static int s5h1420_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct s5h1420_state* state = fe->demodulator_priv;
dprintk("enter %s\n", __func__);
switch(tone) {
case SEC_TONE_ON:
s5h1420_writereg(state, 0x3b,
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
break;
case SEC_TONE_OFF:
s5h1420_writereg(state, 0x3b,
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
break;
}
dprintk("leave %s\n", __func__);
return 0;
}
static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd* cmd)
{
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
int i;
unsigned long timeout;
int result = 0;
dprintk("enter %s\n", __func__);
if (cmd->msg_len > sizeof(cmd->msg))
return -EINVAL;
/* setup for DISEQC */
val = s5h1420_readreg(state, 0x3b);
s5h1420_writereg(state, 0x3b, 0x02);
msleep(15);
/* write the DISEQC command bytes */
for(i=0; i< cmd->msg_len; i++) {
s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
}
/* kick off transmission */
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
((cmd->msg_len-1) << 4) | 0x08);
/* wait for transmission to complete */
timeout = jiffies + ((100*HZ) / 1000);
while(time_before(jiffies, timeout)) {
if (!(s5h1420_readreg(state, 0x3b) & 0x08))
break;
msleep(5);
}
if (time_after(jiffies, timeout))
result = -ETIMEDOUT;
/* restore original settings */
s5h1420_writereg(state, 0x3b, val);
msleep(15);
dprintk("leave %s\n", __func__);
return result;
}
static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
struct dvb_diseqc_slave_reply* reply)
{
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
int i;
int length;
unsigned long timeout;
int result = 0;
/* setup for DISEQC receive */
val = s5h1420_readreg(state, 0x3b);
s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
msleep(15);
/* wait for reception to complete */
timeout = jiffies + ((reply->timeout*HZ) / 1000);
while(time_before(jiffies, timeout)) {
if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
break;
msleep(5);
}
if (time_after(jiffies, timeout)) {
result = -ETIMEDOUT;
goto exit;
}
/* check error flag - FIXME: not sure what this does - docs do not describe
* beyond "error flag for diseqc receive data :( */
if (s5h1420_readreg(state, 0x49)) {
result = -EIO;
goto exit;
}
/* check length */
length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
if (length > sizeof(reply->msg)) {
result = -EOVERFLOW;
goto exit;
}
reply->msg_len = length;
/* extract data */
for(i=0; i< length; i++) {
reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
}
exit:
/* restore original settings */
s5h1420_writereg(state, 0x3b, val);
msleep(15);
return result;
}
static int s5h1420_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd minicmd)
{
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
int result = 0;
unsigned long timeout;
/* setup for tone burst */
val = s5h1420_readreg(state, 0x3b);
s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
/* set value for B position if requested */
if (minicmd == SEC_MINI_B) {
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
}
msleep(15);
/* start transmission */
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
/* wait for transmission to complete */
timeout = jiffies + ((100*HZ) / 1000);
while(time_before(jiffies, timeout)) {
if (!(s5h1420_readreg(state, 0x3b) & 0x08))
break;
msleep(5);
}
if (time_after(jiffies, timeout))
result = -ETIMEDOUT;
/* restore original settings */
s5h1420_writereg(state, 0x3b, val);
msleep(15);
return result;
}
static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
{
u8 val;
enum fe_status status = 0;
val = s5h1420_readreg(state, 0x14);
if (val & 0x02)
status |= FE_HAS_SIGNAL;
if (val & 0x01)
status |= FE_HAS_CARRIER;
val = s5h1420_readreg(state, 0x36);
if (val & 0x01)
status |= FE_HAS_VITERBI;
if (val & 0x20)
status |= FE_HAS_SYNC;
if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
status |= FE_HAS_LOCK;
return status;
}
static int s5h1420_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
dprintk("enter %s\n", __func__);
if (status == NULL)
return -EINVAL;
/* determine lock state */
*status = s5h1420_get_status_bits(state);
/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
the inversion, wait a bit and check again */
if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
val = s5h1420_readreg(state, Vit10);
if ((val & 0x07) == 0x03) {
if (val & 0x08)
s5h1420_writereg(state, Vit09, 0x13);
else
s5h1420_writereg(state, Vit09, 0x1b);
/* wait a bit then update lock status */
mdelay(200);
*status = s5h1420_get_status_bits(state);
}
}
/* perform post lock setup */
if ((*status & FE_HAS_LOCK) && !state->postlocked) {
/* calculate the data rate */
u32 tmp = s5h1420_getsymbolrate(state);
switch (s5h1420_readreg(state, Vit10) & 0x07) {
case 0: tmp = (tmp * 2 * 1) / 2; break;
case 1: tmp = (tmp * 2 * 2) / 3; break;
case 2: tmp = (tmp * 2 * 3) / 4; break;
case 3: tmp = (tmp * 2 * 5) / 6; break;
case 4: tmp = (tmp * 2 * 6) / 7; break;
case 5: tmp = (tmp * 2 * 7) / 8; break;
}
if (tmp == 0) {
printk(KERN_ERR "s5h1420: avoided division by 0\n");
tmp = 1;
}
tmp = state->fclk / tmp;
/* set the MPEG_CLK_INTL for the calculated data rate */
if (tmp < 2)
val = 0x00;
else if (tmp < 5)
val = 0x01;
else if (tmp < 9)
val = 0x02;
else if (tmp < 13)
val = 0x03;
else if (tmp < 17)
val = 0x04;
else if (tmp < 25)
val = 0x05;
else if (tmp < 33)
val = 0x06;
else
val = 0x07;
dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
s5h1420_writereg(state, FEC01, 0x18);
s5h1420_writereg(state, FEC01, 0x10);
s5h1420_writereg(state, FEC01, val);
/* Enable "MPEG_Out" */
val = s5h1420_readreg(state, Mpeg02);
s5h1420_writereg(state, Mpeg02, val | (1 << 6));
/* kicker disable */
val = s5h1420_readreg(state, QPSK01) & 0x7f;
s5h1420_writereg(state, QPSK01, val);
/* DC freeze TODO it was never activated by default or it can stay activated */
if (s5h1420_getsymbolrate(state) >= 20000000) {
s5h1420_writereg(state, Loop04, 0x8a);
s5h1420_writereg(state, Loop05, 0x6a);
} else {
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x27);
}
/* post-lock processing has been done! */
state->postlocked = 1;
}
dprintk("leave %s\n", __func__);
return 0;
}
static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct s5h1420_state* state = fe->demodulator_priv;
s5h1420_writereg(state, 0x46, 0x1d);
mdelay(25);
*ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
return 0;
}
static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct s5h1420_state* state = fe->demodulator_priv;
u8 val = s5h1420_readreg(state, 0x15);
*strength = (u16) ((val << 8) | val);
return 0;
}
static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct s5h1420_state* state = fe->demodulator_priv;
s5h1420_writereg(state, 0x46, 0x1f);
mdelay(25);
*ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
return 0;
}
static void s5h1420_reset(struct s5h1420_state* state)
{
dprintk("%s\n", __func__);
s5h1420_writereg (state, 0x01, 0x08);
s5h1420_writereg (state, 0x01, 0x00);
udelay(10);
}
static void s5h1420_setsymbolrate(struct s5h1420_state* state,
struct dtv_frontend_properties *p)
{
u8 v;
u64 val;
dprintk("enter %s\n", __func__);
val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
if (p->symbol_rate < 29000000)
val *= 2;
do_div(val, (state->fclk / 1000));
dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
v = s5h1420_readreg(state, Loop01);
s5h1420_writereg(state, Loop01, v & 0x7f);
s5h1420_writereg(state, Tnco01, val >> 16);
s5h1420_writereg(state, Tnco02, val >> 8);
s5h1420_writereg(state, Tnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x80);
dprintk("leave %s\n", __func__);
}
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
{
return state->symbol_rate;
}
static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
{
int val;
u8 v;
dprintk("enter %s\n", __func__);
/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
* divide fclk by 1000000 to get the correct value. */
val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
v = s5h1420_readreg(state, Loop01);
s5h1420_writereg(state, Loop01, v & 0xbf);
s5h1420_writereg(state, Pnco01, val >> 16);
s5h1420_writereg(state, Pnco02, val >> 8);
s5h1420_writereg(state, Pnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x40);
dprintk("leave %s\n", __func__);
}
static int s5h1420_getfreqoffset(struct s5h1420_state* state)
{
int val;
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
val = s5h1420_readreg(state, 0x0e) << 16;
val |= s5h1420_readreg(state, 0x0f) << 8;
val |= s5h1420_readreg(state, 0x10);
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
if (val & 0x800000)
val |= 0xff000000;
/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
* divide fclk by 1000000 to get the correct value. */
val = (((-val) * (state->fclk/1000000)) / (1<<24));
return val;
}
static void s5h1420_setfec_inversion(struct s5h1420_state* state,
struct dtv_frontend_properties *p)
{
u8 inversion = 0;
u8 vit08, vit09;
dprintk("enter %s\n", __func__);
if (p->inversion == INVERSION_OFF)
inversion = state->config->invert ? 0x08 : 0;
else if (p->inversion == INVERSION_ON)
inversion = state->config->invert ? 0 : 0x08;
if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
vit08 = 0x3f;
vit09 = 0;
} else {
switch (p->fec_inner) {
case FEC_1_2:
vit08 = 0x01;
vit09 = 0x10;
break;
case FEC_2_3:
vit08 = 0x02;
vit09 = 0x11;
break;
case FEC_3_4:
vit08 = 0x04;
vit09 = 0x12;
break;
case FEC_5_6:
vit08 = 0x08;
vit09 = 0x13;
break;
case FEC_6_7:
vit08 = 0x10;
vit09 = 0x14;
break;
case FEC_7_8:
vit08 = 0x20;
vit09 = 0x15;
break;
default:
return;
}
}
vit09 |= inversion;
dprintk("fec: %02x %02x\n", vit08, vit09);
s5h1420_writereg(state, Vit08, vit08);
s5h1420_writereg(state, Vit09, vit09);
dprintk("leave %s\n", __func__);
}
static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
{
switch(s5h1420_readreg(state, 0x32) & 0x07) {
case 0:
return FEC_1_2;
case 1:
return FEC_2_3;
case 2:
return FEC_3_4;
case 3:
return FEC_5_6;
case 4:
return FEC_6_7;
case 5:
return FEC_7_8;
}
return FEC_NONE;
}
static enum fe_spectral_inversion
s5h1420_getinversion(struct s5h1420_state *state)
{
if (s5h1420_readreg(state, 0x32) & 0x08)
return INVERSION_ON;
return INVERSION_OFF;
}
static int s5h1420_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s5h1420_state* state = fe->demodulator_priv;
int frequency_delta;
struct dvb_frontend_tune_settings fesettings;
dprintk("enter %s\n", __func__);
/* check if we should do a fast-tune */
s5h1420_get_tune_settings(fe, &fesettings);
frequency_delta = p->frequency - state->tunedfreq;
if ((frequency_delta > -fesettings.max_drift) &&
(frequency_delta < fesettings.max_drift) &&
(frequency_delta != 0) &&
(state->fec_inner == p->fec_inner) &&
(state->symbol_rate == p->symbol_rate)) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
if (fe->ops.tuner_ops.get_frequency) {
u32 tmp;
fe->ops.tuner_ops.get_frequency(fe, &tmp);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
s5h1420_setfreqoffset(state, p->frequency - tmp);
} else {
s5h1420_setfreqoffset(state, 0);
}
dprintk("simple tune\n");
return 0;
}
dprintk("tuning demod\n");
/* first of all, software reset */
s5h1420_reset(state);
/* set s5h1420 fclk PLL according to desired symbol rate */
if (p->symbol_rate > 33000000)
state->fclk = 80000000;
else if (p->symbol_rate > 28500000)
state->fclk = 59000000;
else if (p->symbol_rate > 25000000)
state->fclk = 86000000;
else if (p->symbol_rate > 1900000)
state->fclk = 88000000;
else
state->fclk = 44000000;
dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
s5h1420_writereg(state, PLL02, 0x40);
s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
/* TODO DC offset removal, config parameter ? */
if (p->symbol_rate > 29000000)
s5h1420_writereg(state, QPSK01, 0xae | 0x10);
else
s5h1420_writereg(state, QPSK01, 0xac | 0x10);
/* set misc registers */
s5h1420_writereg(state, CON_1, 0x00);
s5h1420_writereg(state, QPSK02, 0x00);
s5h1420_writereg(state, Pre01, 0xb0);
s5h1420_writereg(state, Loop01, 0xF0);
s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
if (p->symbol_rate > 20000000)
s5h1420_writereg(state, Loop04, 0x79);
else
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x6b);
if (p->symbol_rate >= 8000000)
s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
else if (p->symbol_rate >= 4000000)
s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
else
s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
s5h1420_writereg(state, Sync01, 0x33);
s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
s5h1420_writereg(state, DiS03, 0x00);
s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
/* set tuner PLL */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
s5h1420_setfreqoffset(state, 0);
}
/* set the reset of the parameters */
s5h1420_setsymbolrate(state, p);
s5h1420_setfec_inversion(state, p);
/* start QPSK */
s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
state->fec_inner = p->fec_inner;
state->symbol_rate = p->symbol_rate;
state->postlocked = 0;
state->tunedfreq = p->frequency;
dprintk("leave %s\n", __func__);
return 0;
}
static int s5h1420_get_frontend(struct dvb_frontend* fe,
struct dtv_frontend_properties *p)
{
struct s5h1420_state* state = fe->demodulator_priv;
p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
p->inversion = s5h1420_getinversion(state);
p->symbol_rate = s5h1420_getsymbolrate(state);
p->fec_inner = s5h1420_getfec(state);
return 0;
}
static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->symbol_rate > 20000000) {
fesettings->min_delay_ms = 50;
fesettings->step_size = 2000;
fesettings->max_drift = 8000;
} else if (p->symbol_rate > 12000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 1500;
fesettings->max_drift = 9000;
} else if (p->symbol_rate > 8000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 1000;
fesettings->max_drift = 8000;
} else if (p->symbol_rate > 4000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 500;
fesettings->max_drift = 7000;
} else if (p->symbol_rate > 2000000) {
fesettings->min_delay_ms = 200;
fesettings->step_size = (p->symbol_rate / 8000);
fesettings->max_drift = 14 * fesettings->step_size;
} else {
fesettings->min_delay_ms = 200;
fesettings->step_size = (p->symbol_rate / 8000);
fesettings->max_drift = 18 * fesettings->step_size;
}
return 0;
}
static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct s5h1420_state* state = fe->demodulator_priv;
if (enable)
return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
else
return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
}
static int s5h1420_init (struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
/* disable power down and do reset */
state->CON_1_val = state->config->serial_mpeg << 4;
s5h1420_writereg(state, 0x02, state->CON_1_val);
msleep(10);
s5h1420_reset(state);
return 0;
}
static int s5h1420_sleep(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
state->CON_1_val = 0x12;
return s5h1420_writereg(state, 0x02, state->CON_1_val);
}
static void s5h1420_release(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
i2c_del_adapter(&state->tuner_i2c_adapter);
kfree(state);
}
static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
struct i2c_msg m[3];
u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
if (1 + num > ARRAY_SIZE(m)) {
printk(KERN_WARNING
"%s: i2c xfer: num=%d is too big!\n",
KBUILD_MODNAME, num);
return -EOPNOTSUPP;
}
memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
m[0].addr = state->config->demod_address;
m[0].buf = tx_open;
m[0].len = 2;
memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
}
static const struct i2c_algorithm s5h1420_tuner_i2c_algo = {
.master_xfer = s5h1420_tuner_i2c_tuner_xfer,
.functionality = s5h1420_tuner_i2c_func,
};
struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
struct s5h1420_state *state = fe->demodulator_priv;
return &state->tuner_i2c_adapter;
}
EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
static const struct dvb_frontend_ops s5h1420_ops;
struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
struct i2c_adapter *i2c)
{
/* allocate memory for the internal state */
struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
u8 i;
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->postlocked = 0;
state->fclk = 88000000;
state->tunedfreq = 0;
state->fec_inner = FEC_NONE;
state->symbol_rate = 0;
/* check if the demod is there + identify it */
i = s5h1420_readreg(state, ID01);
if (i != 0x03)
goto error;
memset(state->shadow, 0xff, sizeof(state->shadow));
for (i = 0; i < 0x50; i++)
state->shadow[i] = s5h1420_readreg(state, i);
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* create tuner i2c adapter */
strscpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
sizeof(state->tuner_i2c_adapter.name));
state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
state->tuner_i2c_adapter.algo_data = NULL;
i2c_set_adapdata(&state->tuner_i2c_adapter, state);
if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
goto error;
}
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(s5h1420_attach);
static const struct dvb_frontend_ops s5h1420_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.frequency_tolerance_hz = 29500 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
/* .symbol_rate_tolerance = ???,*/
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK
},
.release = s5h1420_release,
.init = s5h1420_init,
.sleep = s5h1420_sleep,
.i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
.set_frontend = s5h1420_set_frontend,
.get_frontend = s5h1420_get_frontend,
.get_tune_settings = s5h1420_get_tune_settings,
.read_status = s5h1420_read_status,
.read_ber = s5h1420_read_ber,
.read_signal_strength = s5h1420_read_signal_strength,
.read_ucblocks = s5h1420_read_ucblocks,
.diseqc_send_master_cmd = s5h1420_send_master_cmd,
.diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
.diseqc_send_burst = s5h1420_send_burst,
.set_tone = s5h1420_set_tone,
.set_voltage = s5h1420_set_voltage,
};
MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/s5h1420.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the MaxLinear MxL69x family of combo tuners/demods
*
* Copyright (C) 2020 Brad Love <[email protected]>
*
* based on code:
* Copyright (c) 2016 MaxLinear, Inc. All rights reserved
* which was released under GPL V2
*/
#include <linux/mutex.h>
#include <linux/i2c-mux.h>
#include <linux/string.h>
#include <linux/firmware.h>
#include "mxl692.h"
#include "mxl692_defs.h"
static const struct dvb_frontend_ops mxl692_ops;
struct mxl692_dev {
struct dvb_frontend fe;
struct i2c_client *i2c_client;
struct mutex i2c_lock; /* i2c command mutex */
enum MXL_EAGLE_DEMOD_TYPE_E demod_type;
enum MXL_EAGLE_POWER_MODE_E power_mode;
u32 current_frequency;
int device_type;
int seqnum;
int init_done;
};
static int mxl692_i2c_write(struct mxl692_dev *dev, u8 *buffer, u16 buf_len)
{
int ret = 0;
struct i2c_msg msg = {
.addr = dev->i2c_client->addr,
.flags = 0,
.buf = buffer,
.len = buf_len
};
ret = i2c_transfer(dev->i2c_client->adapter, &msg, 1);
if (ret != 1)
dev_dbg(&dev->i2c_client->dev, "i2c write error!\n");
return ret;
}
static int mxl692_i2c_read(struct mxl692_dev *dev, u8 *buffer, u16 buf_len)
{
int ret = 0;
struct i2c_msg msg = {
.addr = dev->i2c_client->addr,
.flags = I2C_M_RD,
.buf = buffer,
.len = buf_len
};
ret = i2c_transfer(dev->i2c_client->adapter, &msg, 1);
if (ret != 1)
dev_dbg(&dev->i2c_client->dev, "i2c read error!\n");
return ret;
}
static int convert_endian(u32 size, u8 *d)
{
u32 i;
for (i = 0; i < (size & ~3); i += 4) {
d[i + 0] ^= d[i + 3];
d[i + 3] ^= d[i + 0];
d[i + 0] ^= d[i + 3];
d[i + 1] ^= d[i + 2];
d[i + 2] ^= d[i + 1];
d[i + 1] ^= d[i + 2];
}
switch (size & 3) {
case 0:
case 1:
/* do nothing */
break;
case 2:
d[i + 0] ^= d[i + 1];
d[i + 1] ^= d[i + 0];
d[i + 0] ^= d[i + 1];
break;
case 3:
d[i + 0] ^= d[i + 2];
d[i + 2] ^= d[i + 0];
d[i + 0] ^= d[i + 2];
break;
}
return size;
}
static int convert_endian_n(int n, u32 size, u8 *d)
{
int i, count = 0;
for (i = 0; i < n; i += size)
count += convert_endian(size, d + i);
return count;
}
static void mxl692_tx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer)
{
#ifdef __BIG_ENDIAN
return;
#endif
buffer += MXL_EAGLE_HOST_MSG_HEADER_SIZE; /* skip API header */
switch (opcode) {
case MXL_EAGLE_OPCODE_DEVICE_INTR_MASK_SET:
case MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET:
case MXL_EAGLE_OPCODE_SMA_TRANSMIT_SET:
buffer += convert_endian(sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_PARAMS_SET:
buffer += 5;
buffer += convert_endian(2 * sizeof(u32), buffer);
break;
default:
/* no swapping - all get opcodes */
/* ATSC/OOB no swapping */
break;
}
}
static void mxl692_rx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer)
{
#ifdef __BIG_ENDIAN
return;
#endif
buffer += MXL_EAGLE_HOST_MSG_HEADER_SIZE; /* skip API header */
switch (opcode) {
case MXL_EAGLE_OPCODE_TUNER_AGC_STATUS_GET:
buffer++;
buffer += convert_endian(2 * sizeof(u16), buffer);
break;
case MXL_EAGLE_OPCODE_ATSC_STATUS_GET:
buffer += convert_endian_n(2, sizeof(u16), buffer);
buffer += convert_endian(sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET:
buffer += convert_endian(3 * sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_FFE_TAPS_GET:
buffer += convert_endian_n(24, sizeof(u16), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_STATUS_GET:
buffer += 8;
buffer += convert_endian_n(2, sizeof(u16), buffer);
buffer += convert_endian(sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_ERROR_COUNTERS_GET:
buffer += convert_endian(7 * sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_CONSTELLATION_VALUE_GET:
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_START_GET:
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET:
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_END_GET:
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_START_GET:
buffer += convert_endian_n(24, sizeof(u16), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_END_GET:
buffer += convert_endian_n(8, sizeof(u16), buffer);
break;
case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_FFE_GET:
buffer += convert_endian_n(17, sizeof(u16), buffer);
break;
case MXL_EAGLE_OPCODE_OOB_ERROR_COUNTERS_GET:
buffer += convert_endian(3 * sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_OOB_STATUS_GET:
buffer += convert_endian_n(2, sizeof(u16), buffer);
buffer += convert_endian(sizeof(u32), buffer);
break;
case MXL_EAGLE_OPCODE_SMA_RECEIVE_GET:
buffer += convert_endian(sizeof(u32), buffer);
break;
default:
/* no swapping - all set opcodes */
break;
}
}
static u32 mxl692_checksum(u8 *buffer, u32 size)
{
u32 ix, div_size;
u32 cur_cksum = 0;
__be32 *buf;
div_size = DIV_ROUND_UP(size, 4);
buf = (__be32 *)buffer;
for (ix = 0; ix < div_size; ix++)
cur_cksum += be32_to_cpu(buf[ix]);
cur_cksum ^= 0xDEADBEEF;
return cur_cksum;
}
static int mxl692_validate_fw_header(struct mxl692_dev *dev,
const u8 *buffer, u32 buf_len)
{
int status = 0;
u32 ix, temp;
__be32 *local_buf = NULL;
u8 temp_cksum = 0;
static const u8 fw_hdr[] = {
0x4D, 0x31, 0x10, 0x02, 0x40, 0x00, 0x00, 0x80
};
if (memcmp(buffer, fw_hdr, 8) != 0) {
status = -EINVAL;
goto err_finish;
}
local_buf = (__be32 *)(buffer + 8);
temp = be32_to_cpu(*local_buf);
if ((buf_len - 16) != temp >> 8) {
status = -EINVAL;
goto err_finish;
}
for (ix = 16; ix < buf_len; ix++)
temp_cksum += buffer[ix];
if (temp_cksum != buffer[11])
status = -EINVAL;
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "failed\n");
return status;
}
static int mxl692_write_fw_block(struct mxl692_dev *dev, const u8 *buffer,
u32 buf_len, u32 *index)
{
int status = 0;
u32 ix = 0, total_len = 0, addr = 0, chunk_len = 0, prevchunk_len = 0;
u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL;
int payload_max = MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_MHEADER_SIZE;
ix = *index;
if (buffer[ix] == 0x53) {
total_len = buffer[ix + 1] << 16 | buffer[ix + 2] << 8 | buffer[ix + 3];
total_len = (total_len + 3) & ~3;
addr = buffer[ix + 4] << 24 | buffer[ix + 5] << 16 |
buffer[ix + 6] << 8 | buffer[ix + 7];
ix += MXL_EAGLE_FW_SEGMENT_HEADER_SIZE;
while ((total_len > 0) && (status == 0)) {
plocal_buf = local_buf;
chunk_len = (total_len < payload_max) ? total_len : payload_max;
*plocal_buf++ = 0xFC;
*plocal_buf++ = chunk_len + sizeof(u32);
*(u32 *)plocal_buf = addr + prevchunk_len;
#ifdef __BIG_ENDIAN
convert_endian(sizeof(u32), plocal_buf);
#endif
plocal_buf += sizeof(u32);
memcpy(plocal_buf, &buffer[ix], chunk_len);
convert_endian(chunk_len, plocal_buf);
if (mxl692_i2c_write(dev, local_buf,
(chunk_len + MXL_EAGLE_I2C_MHEADER_SIZE)) < 0) {
status = -EREMOTEIO;
break;
}
prevchunk_len += chunk_len;
total_len -= chunk_len;
ix += chunk_len;
}
*index = ix;
} else {
status = -EINVAL;
}
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_memwrite(struct mxl692_dev *dev, u32 addr,
u8 *buffer, u32 size)
{
int status = 0, total_len = 0;
u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL;
total_len = size;
total_len = (total_len + 3) & ~3; /* 4 byte alignment */
if (total_len > (MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_MHEADER_SIZE))
dev_dbg(&dev->i2c_client->dev, "hrmph?\n");
plocal_buf = local_buf;
*plocal_buf++ = 0xFC;
*plocal_buf++ = total_len + sizeof(u32);
*(u32 *)plocal_buf = addr;
plocal_buf += sizeof(u32);
memcpy(plocal_buf, buffer, total_len);
#ifdef __BIG_ENDIAN
convert_endian(sizeof(u32) + total_len, local_buf + 2);
#endif
if (mxl692_i2c_write(dev, local_buf,
(total_len + MXL_EAGLE_I2C_MHEADER_SIZE)) < 0) {
status = -EREMOTEIO;
goto err_finish;
}
return status;
err_finish:
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_memread(struct mxl692_dev *dev, u32 addr,
u8 *buffer, u32 size)
{
int status = 0;
u8 local_buf[MXL_EAGLE_I2C_MHEADER_SIZE] = {}, *plocal_buf = NULL;
plocal_buf = local_buf;
*plocal_buf++ = 0xFB;
*plocal_buf++ = sizeof(u32);
*(u32 *)plocal_buf = addr;
#ifdef __BIG_ENDIAN
convert_endian(sizeof(u32), plocal_buf);
#endif
mutex_lock(&dev->i2c_lock);
if (mxl692_i2c_write(dev, local_buf, MXL_EAGLE_I2C_MHEADER_SIZE) > 0) {
size = (size + 3) & ~3; /* 4 byte alignment */
status = mxl692_i2c_read(dev, buffer, (u16)size) < 0 ? -EREMOTEIO : 0;
#ifdef __BIG_ENDIAN
if (status == 0)
convert_endian(size, buffer);
#endif
} else {
status = -EREMOTEIO;
}
mutex_unlock(&dev->i2c_lock);
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static const char *mxl692_opcode_string(u8 opcode)
{
if (opcode <= MXL_EAGLE_OPCODE_INTERNAL)
return MXL_EAGLE_OPCODE_STRING[opcode];
return "invalid opcode";
}
static int mxl692_opwrite(struct mxl692_dev *dev, u8 *buffer,
u32 size)
{
int status = 0, total_len = 0;
u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL;
struct MXL_EAGLE_HOST_MSG_HEADER_T *tx_hdr = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)buffer;
total_len = size;
total_len = (total_len + 3) & ~3; /* 4 byte alignment */
if (total_len > (MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_PHEADER_SIZE))
dev_dbg(&dev->i2c_client->dev, "hrmph?\n");
plocal_buf = local_buf;
*plocal_buf++ = 0xFE;
*plocal_buf++ = (u8)total_len;
memcpy(plocal_buf, buffer, total_len);
convert_endian(total_len, plocal_buf);
if (mxl692_i2c_write(dev, local_buf,
(total_len + MXL_EAGLE_I2C_PHEADER_SIZE)) < 0) {
status = -EREMOTEIO;
goto err_finish;
}
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "opcode %s err %d\n",
mxl692_opcode_string(tx_hdr->opcode), status);
return status;
}
static int mxl692_opread(struct mxl692_dev *dev, u8 *buffer,
u32 size)
{
int status = 0;
u32 ix = 0;
u8 local_buf[MXL_EAGLE_I2C_PHEADER_SIZE] = {};
local_buf[0] = 0xFD;
local_buf[1] = 0;
if (mxl692_i2c_write(dev, local_buf, MXL_EAGLE_I2C_PHEADER_SIZE) > 0) {
size = (size + 3) & ~3; /* 4 byte alignment */
/* Read in 4 byte chunks */
for (ix = 0; ix < size; ix += 4) {
if (mxl692_i2c_read(dev, buffer + ix, 4) < 0) {
dev_dbg(&dev->i2c_client->dev, "ix=%d size=%d\n", ix, size);
status = -EREMOTEIO;
goto err_finish;
}
}
convert_endian(size, buffer);
} else {
status = -EREMOTEIO;
}
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_i2c_writeread(struct mxl692_dev *dev,
u8 opcode,
u8 *tx_payload,
u8 tx_payload_size,
u8 *rx_payload,
u8 rx_payload_expected)
{
int status = 0, timeout = 40;
u8 tx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
u32 resp_checksum = 0, resp_checksum_tmp = 0;
struct MXL_EAGLE_HOST_MSG_HEADER_T *tx_header;
struct MXL_EAGLE_HOST_MSG_HEADER_T *rx_header;
mutex_lock(&dev->i2c_lock);
if ((tx_payload_size + MXL_EAGLE_HOST_MSG_HEADER_SIZE) >
(MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_PHEADER_SIZE)) {
status = -EINVAL;
goto err_finish;
}
tx_header = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)tx_buf;
tx_header->opcode = opcode;
tx_header->seqnum = dev->seqnum++;
tx_header->payload_size = tx_payload_size;
tx_header->checksum = 0;
if (dev->seqnum == 0)
dev->seqnum = 1;
if (tx_payload && tx_payload_size > 0)
memcpy(&tx_buf[MXL_EAGLE_HOST_MSG_HEADER_SIZE], tx_payload, tx_payload_size);
mxl692_tx_swap(opcode, tx_buf);
tx_header->checksum = 0;
tx_header->checksum = mxl692_checksum(tx_buf,
MXL_EAGLE_HOST_MSG_HEADER_SIZE + tx_payload_size);
#ifdef __LITTLE_ENDIAN
convert_endian(4, (u8 *)&tx_header->checksum); /* cksum is big endian */
#endif
/* send Tx message */
status = mxl692_opwrite(dev, tx_buf,
tx_payload_size + MXL_EAGLE_HOST_MSG_HEADER_SIZE);
if (status) {
status = -EREMOTEIO;
goto err_finish;
}
/* receive Rx message (polling) */
rx_header = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)rx_buf;
do {
status = mxl692_opread(dev, rx_buf,
rx_payload_expected + MXL_EAGLE_HOST_MSG_HEADER_SIZE);
usleep_range(1000, 2000);
timeout--;
} while ((timeout > 0) && (status == 0) &&
(rx_header->seqnum == 0) &&
(rx_header->checksum == 0));
if (timeout == 0 || status) {
dev_dbg(&dev->i2c_client->dev, "timeout=%d status=%d\n",
timeout, status);
status = -ETIMEDOUT;
goto err_finish;
}
if (rx_header->status) {
dev_dbg(&dev->i2c_client->dev, "rx header status code: %d\n", rx_header->status);
status = -EREMOTEIO;
goto err_finish;
}
if (rx_header->seqnum != tx_header->seqnum ||
rx_header->opcode != tx_header->opcode ||
rx_header->payload_size != rx_payload_expected) {
dev_dbg(&dev->i2c_client->dev, "Something failed seq=%s opcode=%s pSize=%s\n",
rx_header->seqnum != tx_header->seqnum ? "X" : "0",
rx_header->opcode != tx_header->opcode ? "X" : "0",
rx_header->payload_size != rx_payload_expected ? "X" : "0");
if (rx_header->payload_size != rx_payload_expected)
dev_dbg(&dev->i2c_client->dev,
"rx_header->payloadSize=%d rx_payload_expected=%d\n",
rx_header->payload_size, rx_payload_expected);
status = -EREMOTEIO;
goto err_finish;
}
resp_checksum = rx_header->checksum;
rx_header->checksum = 0;
resp_checksum_tmp = mxl692_checksum(rx_buf,
MXL_EAGLE_HOST_MSG_HEADER_SIZE + rx_header->payload_size);
#ifdef __LITTLE_ENDIAN
convert_endian(4, (u8 *)&resp_checksum_tmp); /* cksum is big endian */
#endif
if (resp_checksum != resp_checksum_tmp) {
dev_dbg(&dev->i2c_client->dev, "rx checksum failure\n");
status = -EREMOTEIO;
goto err_finish;
}
mxl692_rx_swap(rx_header->opcode, rx_buf);
if (rx_header->payload_size > 0) {
if (!rx_payload) {
dev_dbg(&dev->i2c_client->dev, "no rx payload?!?\n");
status = -EREMOTEIO;
goto err_finish;
}
memcpy(rx_payload, rx_buf + MXL_EAGLE_HOST_MSG_HEADER_SIZE,
rx_header->payload_size);
}
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
mutex_unlock(&dev->i2c_lock);
return status;
}
static int mxl692_fwdownload(struct mxl692_dev *dev,
const u8 *firmware_buf, u32 buf_len)
{
int status = 0;
u32 ix, reg_val = 0x1;
u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
struct MXL_EAGLE_DEV_STATUS_T *dev_status;
if (buf_len < MXL_EAGLE_FW_HEADER_SIZE ||
buf_len > MXL_EAGLE_FW_MAX_SIZE_IN_KB * 1000)
return -EINVAL;
mutex_lock(&dev->i2c_lock);
dev_dbg(&dev->i2c_client->dev, "\n");
status = mxl692_validate_fw_header(dev, firmware_buf, buf_len);
if (status)
goto err_finish;
ix = 16;
status = mxl692_write_fw_block(dev, firmware_buf, buf_len, &ix); /* DRAM */
if (status)
goto err_finish;
status = mxl692_write_fw_block(dev, firmware_buf, buf_len, &ix); /* IRAM */
if (status)
goto err_finish;
/* release CPU from reset */
status = mxl692_memwrite(dev, 0x70000018, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
mutex_unlock(&dev->i2c_lock);
if (status == 0) {
/* verify FW is alive */
usleep_range(MXL_EAGLE_FW_LOAD_TIME * 1000, (MXL_EAGLE_FW_LOAD_TIME + 5) * 1000);
dev_status = (struct MXL_EAGLE_DEV_STATUS_T *)&rx_buf;
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_DEVICE_STATUS_GET,
NULL,
0,
(u8 *)dev_status,
sizeof(struct MXL_EAGLE_DEV_STATUS_T));
}
return status;
err_finish:
mutex_unlock(&dev->i2c_lock);
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_get_versions(struct mxl692_dev *dev)
{
int status = 0;
struct MXL_EAGLE_DEV_VER_T dev_ver = {};
static const char * const chip_id[] = {"N/A", "691", "248", "692"};
status = mxl692_i2c_writeread(dev, MXL_EAGLE_OPCODE_DEVICE_VERSION_GET,
NULL,
0,
(u8 *)&dev_ver,
sizeof(struct MXL_EAGLE_DEV_VER_T));
if (status)
return status;
dev_info(&dev->i2c_client->dev, "MxL692_DEMOD Chip ID: %s\n",
chip_id[dev_ver.chip_id]);
dev_info(&dev->i2c_client->dev,
"MxL692_DEMOD FW Version: %d.%d.%d.%d_RC%d\n",
dev_ver.firmware_ver[0],
dev_ver.firmware_ver[1],
dev_ver.firmware_ver[2],
dev_ver.firmware_ver[3],
dev_ver.firmware_ver[4]);
return status;
}
static int mxl692_reset(struct mxl692_dev *dev)
{
int status = 0;
u32 dev_type = MXL_EAGLE_DEVICE_MAX, reg_val = 0x2;
dev_dbg(&dev->i2c_client->dev, "\n");
/* legacy i2c override */
status = mxl692_memwrite(dev, 0x80000100, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* verify sku */
status = mxl692_memread(dev, 0x70000188, (u8 *)&dev_type, sizeof(u32));
if (status)
goto err_finish;
if (dev_type != dev->device_type)
goto err_finish;
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_config_regulators(struct mxl692_dev *dev,
enum MXL_EAGLE_POWER_SUPPLY_SOURCE_E power_supply)
{
int status = 0;
u32 reg_val;
dev_dbg(&dev->i2c_client->dev, "\n");
/* configure main regulator according to the power supply source */
status = mxl692_memread(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val &= 0x00FFFFFF;
reg_val |= (power_supply == MXL_EAGLE_POWER_SUPPLY_SOURCE_SINGLE) ?
0x14000000 : 0x10000000;
status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* configure digital regulator to high current mode */
status = mxl692_memread(dev, 0x90000018, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val |= 0x800;
status = mxl692_memwrite(dev, 0x90000018, (u8 *)®_val, sizeof(u32));
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_config_xtal(struct mxl692_dev *dev,
struct MXL_EAGLE_DEV_XTAL_T *dev_xtal)
{
int status = 0;
u32 reg_val, reg_val1;
dev_dbg(&dev->i2c_client->dev, "\n");
status = mxl692_memread(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* set XTAL capacitance */
reg_val &= 0xFFFFFFE0;
reg_val |= dev_xtal->xtal_cap;
/* set CLK OUT */
reg_val = dev_xtal->clk_out_enable ? (reg_val | 0x0100) : (reg_val & 0xFFFFFEFF);
status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* set CLK OUT divider */
reg_val = dev_xtal->clk_out_div_enable ? (reg_val | 0x0200) : (reg_val & 0xFFFFFDFF);
status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* set XTAL sharing */
reg_val = dev_xtal->xtal_sharing_enable ? (reg_val | 0x010400) : (reg_val & 0xFFFEFBFF);
status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
/* enable/disable XTAL calibration, based on master/slave device */
status = mxl692_memread(dev, 0x90000030, (u8 *)®_val1, sizeof(u32));
if (status)
goto err_finish;
if (dev_xtal->xtal_calibration_enable) {
/* enable XTAL calibration and set XTAL amplitude to a higher value */
reg_val1 &= 0xFFFFFFFD;
reg_val1 |= 0x30;
status = mxl692_memwrite(dev, 0x90000030, (u8 *)®_val1, sizeof(u32));
if (status)
goto err_finish;
} else {
/* disable XTAL calibration */
reg_val1 |= 0x2;
status = mxl692_memwrite(dev, 0x90000030, (u8 *)®_val1, sizeof(u32));
if (status)
goto err_finish;
/* set XTAL bias value */
status = mxl692_memread(dev, 0x9000002c, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val &= 0xC0FFFFFF;
reg_val |= 0xA000000;
status = mxl692_memwrite(dev, 0x9000002c, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
}
/* start XTAL calibration */
status = mxl692_memread(dev, 0x70000010, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val |= 0x8;
status = mxl692_memwrite(dev, 0x70000010, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
status = mxl692_memread(dev, 0x70000018, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val |= 0x10;
status = mxl692_memwrite(dev, 0x70000018, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
status = mxl692_memread(dev, 0x9001014c, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val &= 0xFFFFEFFF;
status = mxl692_memwrite(dev, 0x9001014c, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
reg_val |= 0x1000;
status = mxl692_memwrite(dev, 0x9001014c, (u8 *)®_val, sizeof(u32));
if (status)
goto err_finish;
usleep_range(45000, 55000);
err_finish:
if (status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_powermode(struct mxl692_dev *dev,
enum MXL_EAGLE_POWER_MODE_E power_mode)
{
int status = 0;
u8 mode = power_mode;
dev_dbg(&dev->i2c_client->dev, "%s\n",
power_mode == MXL_EAGLE_POWER_MODE_SLEEP ? "sleep" : "active");
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_DEVICE_POWERMODE_SET,
&mode,
sizeof(u8),
NULL,
0);
if (status) {
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
dev->power_mode = power_mode;
return status;
}
static int mxl692_init(struct dvb_frontend *fe)
{
struct mxl692_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->i2c_client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int status = 0;
const struct firmware *firmware;
struct MXL_EAGLE_DEV_XTAL_T xtal_config = {};
dev_dbg(&dev->i2c_client->dev, "\n");
if (dev->init_done)
goto warm;
dev->seqnum = 1;
status = mxl692_reset(dev);
if (status)
goto err;
usleep_range(50 * 1000, 60 * 1000); /* was 1000! */
status = mxl692_config_regulators(dev, MXL_EAGLE_POWER_SUPPLY_SOURCE_DUAL);
if (status)
goto err;
xtal_config.xtal_cap = 26;
xtal_config.clk_out_div_enable = 0;
xtal_config.clk_out_enable = 0;
xtal_config.xtal_calibration_enable = 0;
xtal_config.xtal_sharing_enable = 1;
status = mxl692_config_xtal(dev, &xtal_config);
if (status)
goto err;
status = request_firmware(&firmware, MXL692_FIRMWARE, &client->dev);
if (status) {
dev_dbg(&dev->i2c_client->dev, "firmware missing? %s\n",
MXL692_FIRMWARE);
goto err;
}
status = mxl692_fwdownload(dev, firmware->data, firmware->size);
if (status)
goto err_release_firmware;
release_firmware(firmware);
status = mxl692_get_versions(dev);
if (status)
goto err;
dev->power_mode = MXL_EAGLE_POWER_MODE_SLEEP;
warm:
/* Config Device Power Mode */
if (dev->power_mode != MXL_EAGLE_POWER_MODE_ACTIVE) {
status = mxl692_powermode(dev, MXL_EAGLE_POWER_MODE_ACTIVE);
if (status)
goto err;
usleep_range(50 * 1000, 60 * 1000); /* was 500! */
}
/* Init stats here to indicate which stats are supported */
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dev->init_done = 1;
return 0;
err_release_firmware:
release_firmware(firmware);
err:
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_sleep(struct dvb_frontend *fe)
{
struct mxl692_dev *dev = fe->demodulator_priv;
if (dev->power_mode != MXL_EAGLE_POWER_MODE_SLEEP)
mxl692_powermode(dev, MXL_EAGLE_POWER_MODE_SLEEP);
return 0;
}
static int mxl692_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mxl692_dev *dev = fe->demodulator_priv;
int status = 0;
enum MXL_EAGLE_DEMOD_TYPE_E demod_type;
struct MXL_EAGLE_MPEGOUT_PARAMS_T mpeg_params = {};
enum MXL_EAGLE_QAM_DEMOD_ANNEX_TYPE_E qam_annex = MXL_EAGLE_QAM_DEMOD_ANNEX_B;
struct MXL_EAGLE_QAM_DEMOD_PARAMS_T qam_params = {};
struct MXL_EAGLE_TUNER_CHANNEL_PARAMS_T tuner_params = {};
u8 op_param = 0;
dev_dbg(&dev->i2c_client->dev, "\n");
switch (p->modulation) {
case VSB_8:
demod_type = MXL_EAGLE_DEMOD_TYPE_ATSC;
break;
case QAM_AUTO:
case QAM_64:
case QAM_128:
case QAM_256:
demod_type = MXL_EAGLE_DEMOD_TYPE_QAM;
break;
default:
return -EINVAL;
}
if (dev->current_frequency == p->frequency && dev->demod_type == demod_type) {
dev_dbg(&dev->i2c_client->dev, "already set up\n");
return 0;
}
dev->current_frequency = -1;
dev->demod_type = -1;
op_param = demod_type;
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_DEVICE_DEMODULATOR_TYPE_SET,
&op_param,
sizeof(u8),
NULL,
0);
if (status) {
dev_dbg(&dev->i2c_client->dev,
"DEVICE_DEMODULATOR_TYPE_SET...FAIL err 0x%x\n", status);
goto err;
}
usleep_range(20 * 1000, 30 * 1000); /* was 500! */
mpeg_params.mpeg_parallel = 0;
mpeg_params.msb_first = MXL_EAGLE_DATA_SERIAL_MSB_1ST;
mpeg_params.mpeg_sync_pulse_width = MXL_EAGLE_DATA_SYNC_WIDTH_BIT;
mpeg_params.mpeg_valid_pol = MXL_EAGLE_CLOCK_POSITIVE;
mpeg_params.mpeg_sync_pol = MXL_EAGLE_CLOCK_POSITIVE;
mpeg_params.mpeg_clk_pol = MXL_EAGLE_CLOCK_NEGATIVE;
mpeg_params.mpeg3wire_mode_enable = 0;
mpeg_params.mpeg_clk_freq = MXL_EAGLE_MPEG_CLOCK_27MHZ;
switch (demod_type) {
case MXL_EAGLE_DEMOD_TYPE_ATSC:
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET,
(u8 *)&mpeg_params,
sizeof(struct MXL_EAGLE_MPEGOUT_PARAMS_T),
NULL,
0);
if (status)
goto err;
break;
case MXL_EAGLE_DEMOD_TYPE_QAM:
if (qam_annex == MXL_EAGLE_QAM_DEMOD_ANNEX_A)
mpeg_params.msb_first = MXL_EAGLE_DATA_SERIAL_LSB_1ST;
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET,
(u8 *)&mpeg_params,
sizeof(struct MXL_EAGLE_MPEGOUT_PARAMS_T),
NULL,
0);
if (status)
goto err;
qam_params.annex_type = qam_annex;
qam_params.qam_type = MXL_EAGLE_QAM_DEMOD_AUTO;
qam_params.iq_flip = MXL_EAGLE_DEMOD_IQ_AUTO;
if (p->modulation == QAM_64)
qam_params.symbol_rate_hz = 5057000;
else
qam_params.symbol_rate_hz = 5361000;
qam_params.symbol_rate_256qam_hz = 5361000;
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_QAM_PARAMS_SET,
(u8 *)&qam_params,
sizeof(struct MXL_EAGLE_QAM_DEMOD_PARAMS_T),
NULL, 0);
if (status)
goto err;
break;
default:
break;
}
usleep_range(20 * 1000, 30 * 1000); /* was 500! */
tuner_params.freq_hz = p->frequency;
tuner_params.bandwidth = MXL_EAGLE_TUNER_BW_6MHZ;
tuner_params.tune_mode = MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_VIEW;
dev_dbg(&dev->i2c_client->dev, " Tuning Freq: %d %s\n", tuner_params.freq_hz,
demod_type == MXL_EAGLE_DEMOD_TYPE_ATSC ? "ATSC" : "QAM");
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET,
(u8 *)&tuner_params,
sizeof(struct MXL_EAGLE_TUNER_CHANNEL_PARAMS_T),
NULL,
0);
if (status)
goto err;
usleep_range(20 * 1000, 30 * 1000); /* was 500! */
switch (demod_type) {
case MXL_EAGLE_DEMOD_TYPE_ATSC:
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_ATSC_INIT_SET,
NULL, 0, NULL, 0);
if (status)
goto err;
break;
case MXL_EAGLE_DEMOD_TYPE_QAM:
status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_QAM_RESTART_SET,
NULL, 0, NULL, 0);
if (status)
goto err;
break;
default:
break;
}
dev->demod_type = demod_type;
dev->current_frequency = p->frequency;
return 0;
err:
dev_dbg(&dev->i2c_client->dev, "err %d\n", status);
return status;
}
static int mxl692_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
p->modulation = c->modulation;
p->frequency = c->frequency;
return 0;
}
static int mxl692_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct mxl692_dev *dev = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *atsc_status;
struct MXL_EAGLE_QAM_DEMOD_STATUS_T *qam_status;
enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type;
int mxl_status = 0;
*snr = 0;
dev_dbg(&dev->i2c_client->dev, "\n");
atsc_status = (struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *)&rx_buf;
qam_status = (struct MXL_EAGLE_QAM_DEMOD_STATUS_T *)&rx_buf;
switch (demod_type) {
case MXL_EAGLE_DEMOD_TYPE_ATSC:
mxl_status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_ATSC_STATUS_GET,
NULL,
0,
rx_buf,
sizeof(struct MXL_EAGLE_ATSC_DEMOD_STATUS_T));
if (!mxl_status) {
*snr = (u16)(atsc_status->snr_db_tenths / 10);
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = *snr;
}
break;
case MXL_EAGLE_DEMOD_TYPE_QAM:
mxl_status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_QAM_STATUS_GET,
NULL,
0,
rx_buf,
sizeof(struct MXL_EAGLE_QAM_DEMOD_STATUS_T));
if (!mxl_status)
*snr = (u16)(qam_status->snr_db_tenths / 10);
break;
case MXL_EAGLE_DEMOD_TYPE_OOB:
default:
break;
}
if (mxl_status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status);
return mxl_status;
}
static int mxl692_read_ber_ucb(struct dvb_frontend *fe)
{
struct mxl692_dev *dev = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *atsc_errors;
enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type;
int mxl_status = 0;
u32 utmp;
dev_dbg(&dev->i2c_client->dev, "\n");
atsc_errors = (struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *)&rx_buf;
switch (demod_type) {
case MXL_EAGLE_DEMOD_TYPE_ATSC:
mxl_status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET,
NULL,
0,
rx_buf,
sizeof(struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T));
if (!mxl_status) {
if (atsc_errors->error_packets == 0)
utmp = 0;
else
utmp = ((atsc_errors->error_bytes / atsc_errors->error_packets) *
atsc_errors->total_packets);
/* ber */
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += atsc_errors->error_bytes;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += utmp;
/* ucb */
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += atsc_errors->error_packets;
dev_dbg(&dev->i2c_client->dev, "%llu %llu\n",
c->post_bit_count.stat[0].uvalue, c->block_error.stat[0].uvalue);
}
break;
case MXL_EAGLE_DEMOD_TYPE_QAM:
case MXL_EAGLE_DEMOD_TYPE_OOB:
default:
break;
}
if (mxl_status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status);
return mxl_status;
}
static int mxl692_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct mxl692_dev *dev = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};
struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *atsc_status;
struct MXL_EAGLE_QAM_DEMOD_STATUS_T *qam_status;
enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type;
int mxl_status = 0;
*status = 0;
dev_dbg(&dev->i2c_client->dev, "\n");
atsc_status = (struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *)&rx_buf;
qam_status = (struct MXL_EAGLE_QAM_DEMOD_STATUS_T *)&rx_buf;
switch (demod_type) {
case MXL_EAGLE_DEMOD_TYPE_ATSC:
mxl_status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_ATSC_STATUS_GET,
NULL,
0,
rx_buf,
sizeof(struct MXL_EAGLE_ATSC_DEMOD_STATUS_T));
if (!mxl_status && atsc_status->atsc_lock) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = atsc_status->snr_db_tenths / 10;
}
break;
case MXL_EAGLE_DEMOD_TYPE_QAM:
mxl_status = mxl692_i2c_writeread(dev,
MXL_EAGLE_OPCODE_QAM_STATUS_GET,
NULL,
0,
rx_buf,
sizeof(struct MXL_EAGLE_QAM_DEMOD_STATUS_T));
if (!mxl_status && qam_status->qam_locked) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = qam_status->snr_db_tenths / 10;
}
break;
case MXL_EAGLE_DEMOD_TYPE_OOB:
default:
break;
}
if ((*status & FE_HAS_LOCK) == 0) {
/* No lock, reset all statistics */
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
if (mxl_status)
dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status);
else
mxl_status = mxl692_read_ber_ucb(fe);
return mxl_status;
}
static const struct dvb_frontend_ops mxl692_ops = {
.delsys = { SYS_ATSC },
.info = {
.name = "MaxLinear MxL692 VSB tuner-demodulator",
.frequency_min_hz = 54000000,
.frequency_max_hz = 858000000,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_8VSB
},
.init = mxl692_init,
.sleep = mxl692_sleep,
.set_frontend = mxl692_set_frontend,
.get_frontend = mxl692_get_frontend,
.read_status = mxl692_read_status,
.read_snr = mxl692_read_snr,
};
static int mxl692_probe(struct i2c_client *client)
{
struct mxl692_config *config = client->dev.platform_data;
struct mxl692_dev *dev;
int ret = 0;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
dev_dbg(&client->dev, "kzalloc() failed\n");
goto err;
}
memcpy(&dev->fe.ops, &mxl692_ops, sizeof(struct dvb_frontend_ops));
dev->fe.demodulator_priv = dev;
dev->i2c_client = client;
*config->fe = &dev->fe;
mutex_init(&dev->i2c_lock);
i2c_set_clientdata(client, dev);
dev_info(&client->dev, "MaxLinear mxl692 successfully attached\n");
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return -ENODEV;
}
static void mxl692_remove(struct i2c_client *client)
{
struct mxl692_dev *dev = i2c_get_clientdata(client);
dev->fe.demodulator_priv = NULL;
i2c_set_clientdata(client, NULL);
kfree(dev);
}
static const struct i2c_device_id mxl692_id_table[] = {
{"mxl692", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, mxl692_id_table);
static struct i2c_driver mxl692_driver = {
.driver = {
.name = "mxl692",
},
.probe = mxl692_probe,
.remove = mxl692_remove,
.id_table = mxl692_id_table,
};
module_i2c_driver(mxl692_driver);
MODULE_AUTHOR("Brad Love <[email protected]>");
MODULE_DESCRIPTION("MaxLinear MxL692 demodulator/tuner driver");
MODULE_FIRMWARE(MXL692_FIRMWARE);
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/mxl692.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* stv6110.c
*
* Driver for ST STV6110 satellite tuner IC.
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/types.h>
#include "stv6110.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static int debug;
struct stv6110_priv {
int i2c_address;
struct i2c_adapter *i2c;
u32 mclk;
u8 clk_div;
u8 gain;
u8 regs[8];
};
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG args); \
} while (0)
static s32 abssub(s32 a, s32 b)
{
if (a > b)
return a - b;
else
return b - a;
};
static void stv6110_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int stv6110_write_regs(struct dvb_frontend *fe, u8 buf[],
int start, int len)
{
struct stv6110_priv *priv = fe->tuner_priv;
int rc;
u8 cmdbuf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = priv->i2c_address,
.flags = 0,
.buf = cmdbuf,
.len = len + 1
};
dprintk("%s\n", __func__);
if (1 + len > sizeof(cmdbuf)) {
printk(KERN_WARNING
"%s: i2c wr: len=%d is too big!\n",
KBUILD_MODNAME, len);
return -EINVAL;
}
if (start + len > 8)
return -EINVAL;
memcpy(&cmdbuf[1], buf, len);
cmdbuf[0] = start;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
rc = i2c_transfer(priv->i2c, &msg, 1);
if (rc != 1)
dprintk("%s: i2c error\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int stv6110_read_regs(struct dvb_frontend *fe, u8 regs[],
int start, int len)
{
struct stv6110_priv *priv = fe->tuner_priv;
int rc;
u8 reg[] = { start };
struct i2c_msg msg[] = {
{
.addr = priv->i2c_address,
.flags = 0,
.buf = reg,
.len = 1,
}, {
.addr = priv->i2c_address,
.flags = I2C_M_RD,
.buf = regs,
.len = len,
},
};
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
rc = i2c_transfer(priv->i2c, msg, 2);
if (rc != 2)
dprintk("%s: i2c error\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&priv->regs[start], regs, len);
return 0;
}
static int stv6110_read_reg(struct dvb_frontend *fe, int start)
{
u8 buf[] = { 0 };
stv6110_read_regs(fe, buf, start, 1);
return buf[0];
}
static int stv6110_sleep(struct dvb_frontend *fe)
{
u8 reg[] = { 0 };
stv6110_write_regs(fe, reg, 0, 1);
return 0;
}
static u32 carrier_width(u32 symbol_rate, enum fe_rolloff rolloff)
{
u32 rlf;
switch (rolloff) {
case ROLLOFF_20:
rlf = 20;
break;
case ROLLOFF_25:
rlf = 25;
break;
default:
rlf = 35;
break;
}
return symbol_rate + ((symbol_rate * rlf) / 100);
}
static int stv6110_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
{
struct stv6110_priv *priv = fe->tuner_priv;
u8 r8, ret = 0x04;
int i;
if ((bandwidth / 2) > 36000000) /*BW/2 max=31+5=36 mhz for r8=31*/
r8 = 31;
else if ((bandwidth / 2) < 5000000) /* BW/2 min=5Mhz for F=0 */
r8 = 0;
else /*if 5 < BW/2 < 36*/
r8 = (bandwidth / 2) / 1000000 - 5;
/* ctrl3, RCCLKOFF = 0 Activate the calibration Clock */
/* ctrl3, CF = r8 Set the LPF value */
priv->regs[RSTV6110_CTRL3] &= ~((1 << 6) | 0x1f);
priv->regs[RSTV6110_CTRL3] |= (r8 & 0x1f);
stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
/* stat1, CALRCSTRT = 1 Start LPF auto calibration*/
priv->regs[RSTV6110_STAT1] |= 0x02;
stv6110_write_regs(fe, &priv->regs[RSTV6110_STAT1], RSTV6110_STAT1, 1);
i = 0;
/* Wait for CALRCSTRT == 0 */
while ((i < 10) && (ret != 0)) {
ret = ((stv6110_read_reg(fe, RSTV6110_STAT1)) & 0x02);
mdelay(1); /* wait for LPF auto calibration */
i++;
}
/* RCCLKOFF = 1 calibration done, deactivate the calibration Clock */
priv->regs[RSTV6110_CTRL3] |= (1 << 6);
stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
return 0;
}
static int stv6110_init(struct dvb_frontend *fe)
{
struct stv6110_priv *priv = fe->tuner_priv;
u8 buf0[] = { 0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e };
memcpy(priv->regs, buf0, 8);
/* K = (Reference / 1000000) - 16 */
priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
priv->regs[RSTV6110_CTRL1] |=
((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
/* divisor value for the output clock */
priv->regs[RSTV6110_CTRL2] &= ~0xc0;
priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6);
stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1], RSTV6110_CTRL1, 8);
msleep(1);
stv6110_set_bandwidth(fe, 72000000);
return 0;
}
static int stv6110_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct stv6110_priv *priv = fe->tuner_priv;
u32 nbsteps, divider, psd2, freq;
u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
stv6110_read_regs(fe, regs, 0, 8);
/*N*/
divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
divider += priv->regs[RSTV6110_TUNING1];
/*R*/
nbsteps = (priv->regs[RSTV6110_TUNING2] >> 6) & 3;
/*p*/
psd2 = (priv->regs[RSTV6110_TUNING2] >> 4) & 1;
freq = divider * (priv->mclk / 1000);
freq /= (1 << (nbsteps + psd2));
freq /= 4;
*frequency = freq;
return 0;
}
static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
{
struct stv6110_priv *priv = fe->tuner_priv;
u8 ret = 0x04;
u32 divider, ref, p, presc, i, result_freq, vco_freq;
s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val;
dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
frequency, priv->mclk);
/* K = (Reference / 1000000) - 16 */
priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
priv->regs[RSTV6110_CTRL1] |=
((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
/* BB_GAIN = db/2 */
priv->regs[RSTV6110_CTRL2] &= ~0x0f;
priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
if (frequency <= 1023000) {
p = 1;
presc = 0;
} else if (frequency <= 1300000) {
p = 1;
presc = 1;
} else if (frequency <= 2046000) {
p = 0;
presc = 0;
} else {
p = 0;
presc = 1;
}
/* DIV4SEL = p*/
priv->regs[RSTV6110_TUNING2] &= ~(1 << 4);
priv->regs[RSTV6110_TUNING2] |= (p << 4);
/* PRESC32ON = presc */
priv->regs[RSTV6110_TUNING2] &= ~(1 << 5);
priv->regs[RSTV6110_TUNING2] |= (presc << 5);
p_val = (int)(1 << (p + 1)) * 10;/* P = 2 or P = 4 */
for (r_div = 0; r_div <= 3; r_div++) {
p_calc = (priv->mclk / 100000);
p_calc /= (1 << (r_div + 1));
if ((abssub(p_calc, p_val)) < (abssub(p_calc_opt, p_val)))
r_div_opt = r_div;
p_calc_opt = (priv->mclk / 100000);
p_calc_opt /= (1 << (r_div_opt + 1));
}
ref = priv->mclk / ((1 << (r_div_opt + 1)) * (1 << (p + 1)));
divider = (((frequency * 1000) + (ref >> 1)) / ref);
/* RDIV = r_div_opt */
priv->regs[RSTV6110_TUNING2] &= ~(3 << 6);
priv->regs[RSTV6110_TUNING2] |= (((r_div_opt) & 3) << 6);
/* NDIV_MSB = MSB(divider) */
priv->regs[RSTV6110_TUNING2] &= ~0x0f;
priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
/* NDIV_LSB, LSB(divider) */
priv->regs[RSTV6110_TUNING1] = (divider & 0xff);
/* CALVCOSTRT = 1 VCO Auto Calibration */
priv->regs[RSTV6110_STAT1] |= 0x04;
stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1],
RSTV6110_CTRL1, 8);
i = 0;
/* Wait for CALVCOSTRT == 0 */
while ((i < 10) && (ret != 0)) {
ret = ((stv6110_read_reg(fe, RSTV6110_STAT1)) & 0x04);
msleep(1); /* wait for VCO auto calibration */
i++;
}
ret = stv6110_read_reg(fe, RSTV6110_STAT1);
stv6110_get_frequency(fe, &result_freq);
vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1))));
dprintk("%s, stat1=%x, lo_freq=%d kHz, vco_frec=%d kHz\n", __func__,
ret, result_freq, vco_freq);
return 0;
}
static int stv6110_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 bandwidth = carrier_width(c->symbol_rate, c->rolloff);
stv6110_set_frequency(fe, c->frequency);
stv6110_set_bandwidth(fe, bandwidth);
return 0;
}
static int stv6110_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct stv6110_priv *priv = fe->tuner_priv;
u8 r8 = 0;
u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
stv6110_read_regs(fe, regs, 0, 8);
/* CF */
r8 = priv->regs[RSTV6110_CTRL3] & 0x1f;
*bandwidth = (r8 + 5) * 2000000;/* x2 for ZIF tuner BW/2 = F+5 Mhz */
return 0;
}
static const struct dvb_tuner_ops stv6110_tuner_ops = {
.info = {
.name = "ST STV6110",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_step_hz = 1 * MHz,
},
.init = stv6110_init,
.release = stv6110_release,
.sleep = stv6110_sleep,
.set_params = stv6110_set_params,
.get_frequency = stv6110_get_frequency,
.set_frequency = stv6110_set_frequency,
.get_bandwidth = stv6110_get_bandwidth,
.set_bandwidth = stv6110_set_bandwidth,
};
struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe,
const struct stv6110_config *config,
struct i2c_adapter *i2c)
{
struct stv6110_priv *priv = NULL;
u8 reg0[] = { 0x00, 0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e };
struct i2c_msg msg[] = {
{
.addr = config->i2c_address,
.flags = 0,
.buf = reg0,
.len = 9
}
};
int ret;
/* divisor value for the output clock */
reg0[2] &= ~0xc0;
reg0[2] |= (config->clk_div << 6);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer(i2c, msg, 1);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret != 1)
return NULL;
priv = kzalloc(sizeof(struct stv6110_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = config->i2c_address;
priv->i2c = i2c;
priv->mclk = config->mclk;
priv->clk_div = config->clk_div;
priv->gain = config->gain;
memcpy(&priv->regs, ®0[1], 8);
memcpy(&fe->ops.tuner_ops, &stv6110_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
printk(KERN_INFO "STV6110 attached on addr=%x!\n", priv->i2c_address);
return fe;
}
EXPORT_SYMBOL_GPL(stv6110_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("ST STV6110 driver");
MODULE_AUTHOR("Igor M. Liplianin");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv6110.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for OR51132 (pcHDTV HD-3000) - VSB/QAM
*
* Copyright (C) 2007 Trent Piepho <[email protected]>
*
* Copyright (C) 2005 Kirk Lapray <[email protected]>
*
* Based on code from Jack Kelliher ([email protected])
* Copyright (C) 2002 & pcHDTV, inc.
*/
/*
* This driver needs two external firmware files. Please copy
* "dvb-fe-or51132-vsb.fw" and "dvb-fe-or51132-qam.fw" to
* /usr/lib/hotplug/firmware/ or /lib/firmware/
* (depending on configuration of firmware hotplug).
*/
#define OR51132_VSB_FIRMWARE "dvb-fe-or51132-vsb.fw"
#define OR51132_QAM_FIRMWARE "dvb-fe-or51132-qam.fw"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "or51132.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "or51132: " args); \
} while (0)
struct or51132_state
{
struct i2c_adapter* i2c;
/* Configuration settings */
const struct or51132_config* config;
struct dvb_frontend frontend;
/* Demodulator private data */
enum fe_modulation current_modulation;
u32 snr; /* Result of last SNR calculation */
/* Tuner private data */
u32 current_frequency;
};
/* Write buffer to demod */
static int or51132_writebuf(struct or51132_state *state, const u8 *buf, int len)
{
int err;
struct i2c_msg msg = { .addr = state->config->demod_address,
.flags = 0, .buf = (u8*)buf, .len = len };
/* msleep(20); */ /* doesn't appear to be necessary */
if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
printk(KERN_WARNING "or51132: I2C write (addr 0x%02x len %d) error: %d\n",
msg.addr, msg.len, err);
return -EREMOTEIO;
}
return 0;
}
/* Write constant bytes, e.g. or51132_writebytes(state, 0x04, 0x42, 0x00);
Less code and more efficient that loading a buffer on the stack with
the bytes to send and then calling or51132_writebuf() on that. */
#define or51132_writebytes(state, data...) \
({ static const u8 _data[] = {data}; \
or51132_writebuf(state, _data, sizeof(_data)); })
/* Read data from demod into buffer. Returns 0 on success. */
static int or51132_readbuf(struct or51132_state *state, u8 *buf, int len)
{
int err;
struct i2c_msg msg = { .addr = state->config->demod_address,
.flags = I2C_M_RD, .buf = buf, .len = len };
/* msleep(20); */ /* doesn't appear to be necessary */
if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
printk(KERN_WARNING "or51132: I2C read (addr 0x%02x len %d) error: %d\n",
msg.addr, msg.len, err);
return -EREMOTEIO;
}
return 0;
}
/* Reads a 16-bit demod register. Returns <0 on error. */
static int or51132_readreg(struct or51132_state *state, u8 reg)
{
u8 buf[2] = { 0x04, reg };
struct i2c_msg msg[2] = {
{.addr = state->config->demod_address, .flags = 0,
.buf = buf, .len = 2 },
{.addr = state->config->demod_address, .flags = I2C_M_RD,
.buf = buf, .len = 2 }};
int err;
if ((err = i2c_transfer(state->i2c, msg, 2)) != 2) {
printk(KERN_WARNING "or51132: I2C error reading register %d: %d\n",
reg, err);
return -EREMOTEIO;
}
return buf[0] | (buf[1] << 8);
}
static int or51132_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
{
struct or51132_state* state = fe->demodulator_priv;
static const u8 run_buf[] = {0x7F,0x01};
u8 rec_buf[8];
u32 firmwareAsize, firmwareBsize;
int i,ret;
dprintk("Firmware is %zd bytes\n",fw->size);
/* Get size of firmware A and B */
firmwareAsize = le32_to_cpu(*((__le32*)fw->data));
dprintk("FirmwareA is %i bytes\n",firmwareAsize);
firmwareBsize = le32_to_cpu(*((__le32*)(fw->data+4)));
dprintk("FirmwareB is %i bytes\n",firmwareBsize);
/* Upload firmware */
if ((ret = or51132_writebuf(state, &fw->data[8], firmwareAsize))) {
printk(KERN_WARNING "or51132: load_firmware error 1\n");
return ret;
}
if ((ret = or51132_writebuf(state, &fw->data[8+firmwareAsize],
firmwareBsize))) {
printk(KERN_WARNING "or51132: load_firmware error 2\n");
return ret;
}
if ((ret = or51132_writebuf(state, run_buf, 2))) {
printk(KERN_WARNING "or51132: load_firmware error 3\n");
return ret;
}
if ((ret = or51132_writebuf(state, run_buf, 2))) {
printk(KERN_WARNING "or51132: load_firmware error 4\n");
return ret;
}
/* 50ms for operation to begin */
msleep(50);
/* Read back ucode version to besure we loaded correctly and are really up and running */
/* Get uCode version */
if ((ret = or51132_writebytes(state, 0x10, 0x10, 0x00))) {
printk(KERN_WARNING "or51132: load_firmware error a\n");
return ret;
}
if ((ret = or51132_writebytes(state, 0x04, 0x17))) {
printk(KERN_WARNING "or51132: load_firmware error b\n");
return ret;
}
if ((ret = or51132_writebytes(state, 0x00, 0x00))) {
printk(KERN_WARNING "or51132: load_firmware error c\n");
return ret;
}
for (i=0;i<4;i++) {
/* Once upon a time, this command might have had something
to do with getting the firmware version, but it's
not used anymore:
{0x04,0x00,0x30,0x00,i+1} */
/* Read 8 bytes, two bytes at a time */
if ((ret = or51132_readbuf(state, &rec_buf[i*2], 2))) {
printk(KERN_WARNING
"or51132: load_firmware error d - %d\n",i);
return ret;
}
}
printk(KERN_WARNING
"or51132: Version: %02X%02X%02X%02X-%02X%02X%02X%02X (%02X%01X-%01X-%02X%01X-%01X)\n",
rec_buf[1],rec_buf[0],rec_buf[3],rec_buf[2],
rec_buf[5],rec_buf[4],rec_buf[7],rec_buf[6],
rec_buf[3],rec_buf[2]>>4,rec_buf[2]&0x0f,
rec_buf[5],rec_buf[4]>>4,rec_buf[4]&0x0f);
if ((ret = or51132_writebytes(state, 0x10, 0x00, 0x00))) {
printk(KERN_WARNING "or51132: load_firmware error e\n");
return ret;
}
return 0;
};
static int or51132_init(struct dvb_frontend* fe)
{
return 0;
}
static int or51132_read_ber(struct dvb_frontend* fe, u32* ber)
{
*ber = 0;
return 0;
}
static int or51132_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
*ucblocks = 0;
return 0;
}
static int or51132_sleep(struct dvb_frontend* fe)
{
return 0;
}
static int or51132_setmode(struct dvb_frontend* fe)
{
struct or51132_state* state = fe->demodulator_priv;
u8 cmd_buf1[3] = {0x04, 0x01, 0x5f};
u8 cmd_buf2[3] = {0x1c, 0x00, 0 };
dprintk("setmode %d\n",(int)state->current_modulation);
switch (state->current_modulation) {
case VSB_8:
/* Auto CH, Auto NTSC rej, MPEGser, MPEG2tr, phase noise-high */
cmd_buf1[2] = 0x50;
/* REC MODE inv IF spectrum, Normal */
cmd_buf2[1] = 0x03;
/* Channel MODE ATSC/VSB8 */
cmd_buf2[2] = 0x06;
break;
/* All QAM modes are:
Auto-deinterleave; MPEGser, MPEG2tr, phase noise-high
REC MODE Normal Carrier Lock */
case QAM_AUTO:
/* Channel MODE Auto QAM64/256 */
cmd_buf2[2] = 0x4f;
break;
case QAM_256:
/* Channel MODE QAM256 */
cmd_buf2[2] = 0x45;
break;
case QAM_64:
/* Channel MODE QAM64 */
cmd_buf2[2] = 0x43;
break;
default:
printk(KERN_WARNING
"or51132: setmode: Modulation set to unsupported value (%d)\n",
state->current_modulation);
return -EINVAL;
}
/* Set Receiver 1 register */
if (or51132_writebuf(state, cmd_buf1, 3)) {
printk(KERN_WARNING "or51132: set_mode error 1\n");
return -EREMOTEIO;
}
dprintk("set #1 to %02x\n", cmd_buf1[2]);
/* Set operation mode in Receiver 6 register */
if (or51132_writebuf(state, cmd_buf2, 3)) {
printk(KERN_WARNING "or51132: set_mode error 2\n");
return -EREMOTEIO;
}
dprintk("set #6 to 0x%02x%02x\n", cmd_buf2[1], cmd_buf2[2]);
return 0;
}
/* Some modulations use the same firmware. This classifies modulations
by the firmware they use. */
#define MOD_FWCLASS_UNKNOWN 0
#define MOD_FWCLASS_VSB 1
#define MOD_FWCLASS_QAM 2
static int modulation_fw_class(enum fe_modulation modulation)
{
switch(modulation) {
case VSB_8:
return MOD_FWCLASS_VSB;
case QAM_AUTO:
case QAM_64:
case QAM_256:
return MOD_FWCLASS_QAM;
default:
return MOD_FWCLASS_UNKNOWN;
}
}
static int or51132_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int ret;
struct or51132_state* state = fe->demodulator_priv;
const struct firmware *fw;
const char *fwname;
int clock_mode;
/* Upload new firmware only if we need a different one */
if (modulation_fw_class(state->current_modulation) !=
modulation_fw_class(p->modulation)) {
switch (modulation_fw_class(p->modulation)) {
case MOD_FWCLASS_VSB:
dprintk("set_parameters VSB MODE\n");
fwname = OR51132_VSB_FIRMWARE;
/* Set non-punctured clock for VSB */
clock_mode = 0;
break;
case MOD_FWCLASS_QAM:
dprintk("set_parameters QAM MODE\n");
fwname = OR51132_QAM_FIRMWARE;
/* Set punctured clock for QAM */
clock_mode = 1;
break;
default:
printk("or51132: Modulation type(%d) UNSUPPORTED\n",
p->modulation);
return -1;
}
printk("or51132: Waiting for firmware upload(%s)...\n",
fwname);
ret = request_firmware(&fw, fwname, state->i2c->dev.parent);
if (ret) {
printk(KERN_WARNING "or51132: No firmware uploaded(timeout or file not found?)\n");
return ret;
}
ret = or51132_load_firmware(fe, fw);
release_firmware(fw);
if (ret) {
printk(KERN_WARNING "or51132: Writing firmware to device failed!\n");
return ret;
}
printk("or51132: Firmware upload complete.\n");
state->config->set_ts_params(fe, clock_mode);
}
/* Change only if we are actually changing the modulation */
if (state->current_modulation != p->modulation) {
state->current_modulation = p->modulation;
or51132_setmode(fe);
}
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Set to current mode */
or51132_setmode(fe);
/* Update current frequency */
state->current_frequency = p->frequency;
return 0;
}
static int or51132_get_parameters(struct dvb_frontend* fe,
struct dtv_frontend_properties *p)
{
struct or51132_state* state = fe->demodulator_priv;
int status;
int retry = 1;
start:
/* Receiver Status */
if ((status = or51132_readreg(state, 0x00)) < 0) {
printk(KERN_WARNING "or51132: get_parameters: error reading receiver status\n");
return -EREMOTEIO;
}
switch(status&0xff) {
case 0x06:
p->modulation = VSB_8;
break;
case 0x43:
p->modulation = QAM_64;
break;
case 0x45:
p->modulation = QAM_256;
break;
default:
if (retry--)
goto start;
printk(KERN_WARNING "or51132: unknown status 0x%02x\n",
status&0xff);
return -EREMOTEIO;
}
/* FIXME: Read frequency from frontend, take AFC into account */
p->frequency = state->current_frequency;
/* FIXME: How to read inversion setting? Receiver 6 register? */
p->inversion = INVERSION_AUTO;
return 0;
}
static int or51132_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct or51132_state* state = fe->demodulator_priv;
int reg;
/* Receiver Status */
if ((reg = or51132_readreg(state, 0x00)) < 0) {
printk(KERN_WARNING "or51132: read_status: error reading receiver status: %d\n", reg);
*status = 0;
return -EREMOTEIO;
}
dprintk("%s: read_status %04x\n", __func__, reg);
if (reg & 0x0100) /* Receiver Lock */
*status = FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|
FE_HAS_SYNC|FE_HAS_LOCK;
else
*status = 0;
return 0;
}
/* Calculate SNR estimation (scaled by 2^24)
8-VSB SNR and QAM equations from Oren datasheets
For 8-VSB:
SNR[dB] = 10 * log10(897152044.8282 / MSE^2 ) - K
Where K = 0 if NTSC rejection filter is OFF; and
K = 3 if NTSC rejection filter is ON
For QAM64:
SNR[dB] = 10 * log10(897152044.8282 / MSE^2 )
For QAM256:
SNR[dB] = 10 * log10(907832426.314266 / MSE^2 )
We re-write the snr equation as:
SNR * 2^24 = 10*(c - 2*intlog10(MSE))
Where for QAM256, c = log10(907832426.314266) * 2^24
and for 8-VSB and QAM64, c = log10(897152044.8282) * 2^24 */
static u32 calculate_snr(u32 mse, u32 c)
{
if (mse == 0) /* No signal */
return 0;
mse = 2*intlog10(mse);
if (mse > c) {
/* Negative SNR, which is possible, but realisticly the
demod will lose lock before the signal gets this bad. The
API only allows for unsigned values, so just return 0 */
return 0;
}
return 10*(c - mse);
}
static int or51132_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct or51132_state* state = fe->demodulator_priv;
int noise, reg;
u32 c, usK = 0;
int retry = 1;
start:
/* SNR after Equalizer */
noise = or51132_readreg(state, 0x02);
if (noise < 0) {
printk(KERN_WARNING "or51132: read_snr: error reading equalizer\n");
return -EREMOTEIO;
}
dprintk("read_snr noise (%d)\n", noise);
/* Read status, contains modulation type for QAM_AUTO and
NTSC filter for VSB */
reg = or51132_readreg(state, 0x00);
if (reg < 0) {
printk(KERN_WARNING "or51132: read_snr: error reading receiver status\n");
return -EREMOTEIO;
}
switch (reg&0xff) {
case 0x06:
if (reg & 0x1000) usK = 3 << 24;
fallthrough;
case 0x43: /* QAM64 */
c = 150204167;
break;
case 0x45:
c = 150290396;
break;
default:
printk(KERN_WARNING "or51132: unknown status 0x%02x\n", reg&0xff);
if (retry--) goto start;
return -EREMOTEIO;
}
dprintk("%s: modulation %02x, NTSC rej O%s\n", __func__,
reg&0xff, reg&0x1000?"n":"ff");
/* Calculate SNR using noise, c, and NTSC rejection correction */
state->snr = calculate_snr(noise, c) - usK;
*snr = (state->snr) >> 16;
dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
return 0;
}
static int or51132_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
/* Calculate Strength from SNR up to 35dB */
/* Even though the SNR can go higher than 35dB, there is some comfort */
/* factor in having a range of strong signals that can show at 100% */
struct or51132_state* state = (struct or51132_state*) fe->demodulator_priv;
u16 snr;
int ret;
ret = fe->ops.read_snr(fe, &snr);
if (ret != 0)
return ret;
/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
/* scale the range 0 - 35*2^24 into 0 - 65535 */
if (state->snr >= 8960 * 0x10000)
*strength = 0xffff;
else
*strength = state->snr / 8960;
return 0;
}
static int or51132_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 500;
fe_tune_settings->step_size = 0;
fe_tune_settings->max_drift = 0;
return 0;
}
static void or51132_release(struct dvb_frontend* fe)
{
struct or51132_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops or51132_ops;
struct dvb_frontend* or51132_attach(const struct or51132_config* config,
struct i2c_adapter* i2c)
{
struct or51132_state* state = NULL;
/* Allocate memory for the internal state */
state = kzalloc(sizeof(struct or51132_state), GFP_KERNEL);
if (state == NULL)
return NULL;
/* Setup the state */
state->config = config;
state->i2c = i2c;
state->current_frequency = -1;
state->current_modulation = -1;
/* Create dvb_frontend */
memcpy(&state->frontend.ops, &or51132_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
static const struct dvb_frontend_ops or51132_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Oren OR51132 VSB/QAM Frontend",
.frequency_min_hz = 44 * MHz,
.frequency_max_hz = 958 * MHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
FE_CAN_8VSB
},
.release = or51132_release,
.init = or51132_init,
.sleep = or51132_sleep,
.set_frontend = or51132_set_parameters,
.get_frontend = or51132_get_parameters,
.get_tune_settings = or51132_get_tune_settings,
.read_status = or51132_read_status,
.read_ber = or51132_read_ber,
.read_signal_strength = or51132_read_signal_strength,
.read_snr = or51132_read_snr,
.read_ucblocks = or51132_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("OR51132 ATSC [pcHDTV HD-3000] (8VSB & ITU J83 AnnexB FEC QAM64/256) Demodulator Driver");
MODULE_AUTHOR("Kirk Lapray");
MODULE_AUTHOR("Trent Piepho");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(or51132_attach);
| linux-master | drivers/media/dvb-frontends/or51132.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* E3C EC100 demodulator driver
*
* Copyright (C) 2009 Antti Palosaari <[email protected]>
*/
#include <media/dvb_frontend.h>
#include "ec100.h"
struct ec100_state {
struct i2c_adapter *i2c;
struct dvb_frontend frontend;
struct ec100_config config;
u16 ber;
};
/* write single register */
static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
{
int ret;
u8 buf[2] = {reg, val};
struct i2c_msg msg[1] = {
{
.addr = state->config.demod_address,
.flags = 0,
.len = sizeof(buf),
.buf = buf,
}
};
ret = i2c_transfer(state->i2c, msg, 1);
if (ret == 1) {
ret = 0;
} else {
dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%02x\n",
KBUILD_MODNAME, ret, reg);
ret = -EREMOTEIO;
}
return ret;
}
/* read single register */
static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
{
int ret;
struct i2c_msg msg[2] = {
{
.addr = state->config.demod_address,
.flags = 0,
.len = 1,
.buf = ®
}, {
.addr = state->config.demod_address,
.flags = I2C_M_RD,
.len = 1,
.buf = val
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret == 2) {
ret = 0;
} else {
dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%02x\n",
KBUILD_MODNAME, ret, reg);
ret = -EREMOTEIO;
}
return ret;
}
static int ec100_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct ec100_state *state = fe->demodulator_priv;
int ret;
u8 tmp, tmp2;
dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
__func__, c->frequency, c->bandwidth_hz);
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
ret = ec100_write_reg(state, 0x04, 0x06);
if (ret)
goto error;
ret = ec100_write_reg(state, 0x67, 0x58);
if (ret)
goto error;
ret = ec100_write_reg(state, 0x05, 0x18);
if (ret)
goto error;
/* reg/bw | 6 | 7 | 8
-------+------+------+------
A 0x1b | 0xa1 | 0xe7 | 0x2c
A 0x1c | 0x55 | 0x63 | 0x72
-------+------+------+------
B 0x1b | 0xb7 | 0x00 | 0x49
B 0x1c | 0x55 | 0x64 | 0x72 */
switch (c->bandwidth_hz) {
case 6000000:
tmp = 0xb7;
tmp2 = 0x55;
break;
case 7000000:
tmp = 0x00;
tmp2 = 0x64;
break;
case 8000000:
default:
tmp = 0x49;
tmp2 = 0x72;
}
ret = ec100_write_reg(state, 0x1b, tmp);
if (ret)
goto error;
ret = ec100_write_reg(state, 0x1c, tmp2);
if (ret)
goto error;
ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
if (ret)
goto error;
ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
if (ret)
goto error;
ret = ec100_write_reg(state, 0x08, 0x24);
if (ret)
goto error;
ret = ec100_write_reg(state, 0x00, 0x00); /* go */
if (ret)
goto error;
ret = ec100_write_reg(state, 0x00, 0x20); /* go */
if (ret)
goto error;
return ret;
error:
dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int ec100_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 300;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int ec100_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct ec100_state *state = fe->demodulator_priv;
int ret;
u8 tmp;
*status = 0;
ret = ec100_read_reg(state, 0x42, &tmp);
if (ret)
goto error;
if (tmp & 0x80) {
/* bit7 set - have lock */
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
FE_HAS_SYNC | FE_HAS_LOCK;
} else {
ret = ec100_read_reg(state, 0x01, &tmp);
if (ret)
goto error;
if (tmp & 0x10) {
/* bit4 set - have signal */
*status |= FE_HAS_SIGNAL;
if (!(tmp & 0x01)) {
/* bit0 clear - have ~valid signal */
*status |= FE_HAS_CARRIER | FE_HAS_VITERBI;
}
}
}
return ret;
error:
dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct ec100_state *state = fe->demodulator_priv;
int ret;
u8 tmp, tmp2;
u16 ber2;
*ber = 0;
ret = ec100_read_reg(state, 0x65, &tmp);
if (ret)
goto error;
ret = ec100_read_reg(state, 0x66, &tmp2);
if (ret)
goto error;
ber2 = (tmp2 << 8) | tmp;
/* if counter overflow or clear */
if (ber2 < state->ber)
*ber = ber2;
else
*ber = ber2 - state->ber;
state->ber = ber2;
return ret;
error:
dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct ec100_state *state = fe->demodulator_priv;
int ret;
u8 tmp;
ret = ec100_read_reg(state, 0x24, &tmp);
if (ret) {
*strength = 0;
goto error;
}
*strength = ((tmp << 8) | tmp);
return ret;
error:
dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
return ret;
}
static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
{
*snr = 0;
return 0;
}
static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
*ucblocks = 0;
return 0;
}
static void ec100_release(struct dvb_frontend *fe)
{
struct ec100_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops ec100_ops;
struct dvb_frontend *ec100_attach(const struct ec100_config *config,
struct i2c_adapter *i2c)
{
int ret;
struct ec100_state *state = NULL;
u8 tmp;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
memcpy(&state->config, config, sizeof(struct ec100_config));
/* check if the demod is there */
ret = ec100_read_reg(state, 0x33, &tmp);
if (ret || tmp != 0x0b)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &ec100_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(ec100_attach);
static const struct dvb_frontend_ops ec100_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "E3C EC100 DVB-T",
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 |
FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS
},
.release = ec100_release,
.set_frontend = ec100_set_frontend,
.get_tune_settings = ec100_get_tune_settings,
.read_status = ec100_read_status,
.read_ber = ec100_read_ber,
.read_signal_strength = ec100_read_signal_strength,
.read_snr = ec100_read_snr,
.read_ucblocks = ec100_read_ucblocks,
};
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/ec100.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* horus3a.h
*
* Sony Horus3A DVB-S/S2 tuner driver
*
* Copyright 2012 Sony Corporation
* Copyright (C) 2014 NetUP Inc.
* Copyright (C) 2014 Sergey Kozlov <[email protected]>
* Copyright (C) 2014 Abylay Ospan <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/types.h>
#include "horus3a.h"
#include <media/dvb_frontend.h>
#define MAX_WRITE_REGSIZE 5
enum horus3a_state {
STATE_UNKNOWN,
STATE_SLEEP,
STATE_ACTIVE
};
struct horus3a_priv {
u32 frequency;
u8 i2c_address;
struct i2c_adapter *i2c;
enum horus3a_state state;
void *set_tuner_data;
int (*set_tuner)(void *, int);
};
static void horus3a_i2c_debug(struct horus3a_priv *priv,
u8 reg, u8 write, const u8 *data, u32 len)
{
dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
(write == 0 ? "read" : "write"), reg, len);
print_hex_dump_bytes("horus3a: I2C data: ",
DUMP_PREFIX_OFFSET, data, len);
}
static int horus3a_write_regs(struct horus3a_priv *priv,
u8 reg, const u8 *data, u32 len)
{
int ret;
u8 buf[MAX_WRITE_REGSIZE + 1];
struct i2c_msg msg[1] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = len + 1,
.buf = buf,
}
};
if (len + 1 > sizeof(buf)) {
dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
reg, len + 1);
return -E2BIG;
}
horus3a_i2c_debug(priv, reg, 1, data, len);
buf[0] = reg;
memcpy(&buf[1], data, len);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr failed=%d reg=%02x len=%d\n",
KBUILD_MODNAME, ret, reg, len);
return ret;
}
return 0;
}
static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
{
u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return horus3a_write_regs(priv, reg, &tmp, 1);
}
static int horus3a_enter_power_save(struct horus3a_priv *priv)
{
u8 data[2];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_SLEEP)
return 0;
/* IQ Generator disable */
horus3a_write_reg(priv, 0x2a, 0x79);
/* MDIV_EN = 0 */
horus3a_write_reg(priv, 0x29, 0x70);
/* VCO disable preparation */
horus3a_write_reg(priv, 0x28, 0x3e);
/* VCO buffer disable */
horus3a_write_reg(priv, 0x2a, 0x19);
/* VCO calibration disable */
horus3a_write_reg(priv, 0x1c, 0x00);
/* Power save setting (xtal is not stopped) */
data[0] = 0xC0;
/* LNA is Disabled */
data[1] = 0xA7;
/* 0x11 - 0x12 */
horus3a_write_regs(priv, 0x11, data, sizeof(data));
priv->state = STATE_SLEEP;
return 0;
}
static int horus3a_leave_power_save(struct horus3a_priv *priv)
{
u8 data[2];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_ACTIVE)
return 0;
/* Leave power save */
data[0] = 0x00;
/* LNA is Disabled */
data[1] = 0xa7;
/* 0x11 - 0x12 */
horus3a_write_regs(priv, 0x11, data, sizeof(data));
/* VCO buffer enable */
horus3a_write_reg(priv, 0x2a, 0x79);
/* VCO calibration enable */
horus3a_write_reg(priv, 0x1c, 0xc0);
/* MDIV_EN = 1 */
horus3a_write_reg(priv, 0x29, 0x71);
usleep_range(5000, 7000);
priv->state = STATE_ACTIVE;
return 0;
}
static int horus3a_init(struct dvb_frontend *fe)
{
struct horus3a_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
return 0;
}
static void horus3a_release(struct dvb_frontend *fe)
{
struct horus3a_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int horus3a_sleep(struct dvb_frontend *fe)
{
struct horus3a_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
horus3a_enter_power_save(priv);
return 0;
}
static int horus3a_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct horus3a_priv *priv = fe->tuner_priv;
u32 frequency = p->frequency;
u32 symbol_rate = p->symbol_rate/1000;
u8 mixdiv = 0;
u8 mdiv = 0;
u32 ms = 0;
u8 f_ctl = 0;
u8 g_ctl = 0;
u8 fc_lpf = 0;
u8 data[5];
dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
__func__, frequency, symbol_rate);
if (priv->set_tuner)
priv->set_tuner(priv->set_tuner_data, 0);
if (priv->state == STATE_SLEEP)
horus3a_leave_power_save(priv);
/* frequency should be X MHz (X : integer) */
frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
if (frequency <= 1155000) {
mixdiv = 4;
mdiv = 1;
} else {
mixdiv = 2;
mdiv = 0;
}
/* Assumed that fREF == 1MHz (1000kHz) */
ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
if (ms > 0x7FFF) { /* 15 bit */
dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
frequency);
return -EINVAL;
}
if (frequency < 975000) {
/* F_CTL=11100 G_CTL=001 */
f_ctl = 0x1C;
g_ctl = 0x01;
} else if (frequency < 1050000) {
/* F_CTL=11000 G_CTL=010 */
f_ctl = 0x18;
g_ctl = 0x02;
} else if (frequency < 1150000) {
/* F_CTL=10100 G_CTL=010 */
f_ctl = 0x14;
g_ctl = 0x02;
} else if (frequency < 1250000) {
/* F_CTL=10000 G_CTL=011 */
f_ctl = 0x10;
g_ctl = 0x03;
} else if (frequency < 1350000) {
/* F_CTL=01100 G_CTL=100 */
f_ctl = 0x0C;
g_ctl = 0x04;
} else if (frequency < 1450000) {
/* F_CTL=01010 G_CTL=100 */
f_ctl = 0x0A;
g_ctl = 0x04;
} else if (frequency < 1600000) {
/* F_CTL=00111 G_CTL=101 */
f_ctl = 0x07;
g_ctl = 0x05;
} else if (frequency < 1800000) {
/* F_CTL=00100 G_CTL=010 */
f_ctl = 0x04;
g_ctl = 0x02;
} else if (frequency < 2000000) {
/* F_CTL=00010 G_CTL=001 */
f_ctl = 0x02;
g_ctl = 0x01;
} else {
/* F_CTL=00000 G_CTL=000 */
f_ctl = 0x00;
g_ctl = 0x00;
}
/* LPF cutoff frequency setting */
if (p->delivery_system == SYS_DVBS) {
/*
* rolloff = 0.35
* SR <= 4.3
* fc_lpf = 5
* 4.3 < SR <= 10
* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
* SR * 1.175 = SR * (47/40)
* 10 < SR
* fc_lpf = SR * (1 + rolloff) / 2 + 5 =
* SR * 0.675 + 5 = SR * (27/40) + 5
* NOTE: The result should be round up.
*/
if (symbol_rate <= 4300)
fc_lpf = 5;
else if (symbol_rate <= 10000)
fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
else
fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
/* 5 <= fc_lpf <= 36 */
if (fc_lpf > 36)
fc_lpf = 36;
} else if (p->delivery_system == SYS_DVBS2) {
/*
* SR <= 4.5:
* fc_lpf = 5
* 4.5 < SR <= 10:
* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
* 10 < SR:
* fc_lpf = SR * (1 + rolloff) / 2 + 5
* NOTE: The result should be round up.
*/
if (symbol_rate <= 4500)
fc_lpf = 5;
else if (symbol_rate <= 10000)
fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
else
fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
/* 5 <= fc_lpf <= 36 is valid */
if (fc_lpf > 36)
fc_lpf = 36;
} else {
dev_err(&priv->i2c->dev,
"horus3a: invalid delivery system %d\n",
p->delivery_system);
return -EINVAL;
}
/* 0x00 - 0x04 */
data[0] = (u8)((ms >> 7) & 0xFF);
data[1] = (u8)((ms << 1) & 0xFF);
data[2] = 0x00;
data[3] = 0x00;
data[4] = (u8)(mdiv << 7);
horus3a_write_regs(priv, 0x00, data, sizeof(data));
/* Write G_CTL, F_CTL */
horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
/* Write LPF cutoff frequency */
horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
/* Start Calibration */
horus3a_write_reg(priv, 0x05, 0x80);
/* IQ Generator enable */
horus3a_write_reg(priv, 0x2a, 0x7b);
/* tuner stabilization time */
msleep(60);
/* Store tuned frequency to the struct */
priv->frequency = ms * 2 * 1000 / mixdiv;
return 0;
}
static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct horus3a_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static const struct dvb_tuner_ops horus3a_tuner_ops = {
.info = {
.name = "Sony Horus3a",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_step_hz = 1 * MHz,
},
.init = horus3a_init,
.release = horus3a_release,
.sleep = horus3a_sleep,
.set_params = horus3a_set_params,
.get_frequency = horus3a_get_frequency,
};
struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
const struct horus3a_config *config,
struct i2c_adapter *i2c)
{
u8 buf[3], val;
struct horus3a_priv *priv = NULL;
priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = (config->i2c_address >> 1);
priv->i2c = i2c;
priv->set_tuner_data = config->set_tuner_priv;
priv->set_tuner = config->set_tuner_callback;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* wait 4ms after power on */
usleep_range(4000, 6000);
/* IQ Generator disable */
horus3a_write_reg(priv, 0x2a, 0x79);
/* REF_R = Xtal Frequency */
buf[0] = config->xtal_freq_mhz;
buf[1] = config->xtal_freq_mhz;
buf[2] = 0;
/* 0x6 - 0x8 */
horus3a_write_regs(priv, 0x6, buf, 3);
/* IQ Out = Single Ended */
horus3a_write_reg(priv, 0x0a, 0x40);
switch (config->xtal_freq_mhz) {
case 27:
val = 0x1f;
break;
case 24:
val = 0x10;
break;
case 16:
val = 0xc;
break;
default:
val = 0;
dev_warn(&priv->i2c->dev,
"horus3a: invalid xtal frequency %dMHz\n",
config->xtal_freq_mhz);
break;
}
val <<= 2;
horus3a_write_reg(priv, 0x0e, val);
horus3a_enter_power_save(priv);
usleep_range(3000, 5000);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
dev_info(&priv->i2c->dev,
"Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
priv->i2c_address, priv->i2c);
return fe;
}
EXPORT_SYMBOL_GPL(horus3a_attach);
MODULE_DESCRIPTION("Sony HORUS3A satellite tuner driver");
MODULE_AUTHOR("Sergey Kozlov <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/horus3a.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Montage Technology M88DS3103/M88RS6000 demodulator driver
*
* Copyright (C) 2013 Antti Palosaari <[email protected]>
*/
#include "m88ds3103_priv.h"
static const struct dvb_frontend_ops m88ds3103_ops;
/* write single register with mask */
static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
u8 reg, u8 mask, u8 val)
{
int ret;
u8 tmp;
/* no need for read if whole reg is written */
if (mask != 0xff) {
ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
if (ret)
return ret;
val &= mask;
tmp &= ~mask;
val |= tmp;
}
return regmap_bulk_write(dev->regmap, reg, &val, 1);
}
/* write reg val table using reg addr auto increment */
static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
const struct m88ds3103_reg_val *tab, int tab_len)
{
struct i2c_client *client = dev->client;
int ret, i, j;
u8 buf[83];
dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
if (tab_len > 86) {
ret = -EINVAL;
goto err;
}
for (i = 0, j = 0; i < tab_len; i++, j++) {
buf[j] = tab[i].val;
if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
!((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
if (ret)
goto err;
j = -1;
}
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
/*
* m88ds3103b demod has an internal device related to clocking. First the i2c
* gate must be opened, for one transaction, then writes will be allowed.
*/
static int m88ds3103b_dt_write(struct m88ds3103_dev *dev, int reg, int data)
{
struct i2c_client *client = dev->client;
u8 buf[] = {reg, data};
u8 val;
int ret;
struct i2c_msg msg = {
.addr = dev->dt_addr, .flags = 0, .buf = buf, .len = 2
};
m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
val = 0x11;
ret = regmap_write(dev->regmap, 0x03, val);
if (ret)
dev_dbg(&client->dev, "fail=%d\n", ret);
ret = i2c_transfer(dev->dt_client->adapter, &msg, 1);
if (ret != 1) {
dev_err(&client->dev, "0x%02x (ret=%i, reg=0x%02x, value=0x%02x)\n",
dev->dt_addr, ret, reg, data);
m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
return -EREMOTEIO;
}
m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
dev->dt_addr, reg, data);
return 0;
}
/*
* m88ds3103b demod has an internal device related to clocking. First the i2c
* gate must be opened, for two transactions, then reads will be allowed.
*/
static int m88ds3103b_dt_read(struct m88ds3103_dev *dev, u8 reg)
{
struct i2c_client *client = dev->client;
int ret;
u8 val;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = dev->dt_addr,
.flags = 0,
.buf = b0,
.len = 1
},
{
.addr = dev->dt_addr,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
val = 0x12;
ret = regmap_write(dev->regmap, 0x03, val);
if (ret)
dev_dbg(&client->dev, "fail=%d\n", ret);
ret = i2c_transfer(dev->dt_client->adapter, msg, 2);
if (ret != 2) {
dev_err(&client->dev, "0x%02x (ret=%d, reg=0x%02x)\n",
dev->dt_addr, ret, reg);
m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
return -EREMOTEIO;
}
m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
dev->dt_addr, reg, b1[0]);
return b1[0];
}
/*
* Get the demodulator AGC PWM voltage setting supplied to the tuner.
*/
int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
unsigned tmp;
int ret;
ret = regmap_read(dev->regmap, 0x3f, &tmp);
if (ret == 0)
*_agc_pwm = tmp;
return ret;
}
EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
static int m88ds3103_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, itmp;
unsigned int utmp;
u8 buf[3];
*status = 0;
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBS:
ret = regmap_read(dev->regmap, 0xd1, &utmp);
if (ret)
goto err;
if ((utmp & 0x07) == 0x07)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
break;
case SYS_DVBS2:
ret = regmap_read(dev->regmap, 0x0d, &utmp);
if (ret)
goto err;
if ((utmp & 0x8f) == 0x8f)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_LOCK;
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto err;
}
dev->fe_status = *status;
dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
/* CNR */
if (dev->fe_status & FE_HAS_VITERBI) {
unsigned int cnr, noise, signal, noise_tot, signal_tot;
cnr = 0;
/* more iterations for more accurate estimation */
#define M88DS3103_SNR_ITERATIONS 3
switch (c->delivery_system) {
case SYS_DVBS:
itmp = 0;
for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
ret = regmap_read(dev->regmap, 0xff, &utmp);
if (ret)
goto err;
itmp += utmp;
}
/* use of single register limits max value to 15 dB */
/* SNR(X) dB = 10 * ln(X) / ln(10) dB */
itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
if (itmp)
cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
break;
case SYS_DVBS2:
noise_tot = 0;
signal_tot = 0;
for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
if (ret)
goto err;
noise = buf[1] << 6; /* [13:6] */
noise |= buf[0] & 0x3f; /* [5:0] */
noise >>= 2;
signal = buf[2] * buf[2];
signal >>= 1;
noise_tot += noise;
signal_tot += signal;
}
noise = noise_tot / M88DS3103_SNR_ITERATIONS;
signal = signal_tot / M88DS3103_SNR_ITERATIONS;
/* SNR(X) dB = 10 * log10(X) dB */
if (signal > noise) {
itmp = signal / noise;
cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
}
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto err;
}
if (cnr) {
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (dev->fe_status & FE_HAS_LOCK) {
unsigned int utmp, post_bit_error, post_bit_count;
switch (c->delivery_system) {
case SYS_DVBS:
ret = regmap_write(dev->regmap, 0xf9, 0x04);
if (ret)
goto err;
ret = regmap_read(dev->regmap, 0xf8, &utmp);
if (ret)
goto err;
/* measurement ready? */
if (!(utmp & 0x10)) {
ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
if (ret)
goto err;
post_bit_error = buf[1] << 8 | buf[0] << 0;
post_bit_count = 0x800000;
dev->post_bit_error += post_bit_error;
dev->post_bit_count += post_bit_count;
dev->dvbv3_ber = post_bit_error;
/* restart measurement */
utmp |= 0x10;
ret = regmap_write(dev->regmap, 0xf8, utmp);
if (ret)
goto err;
}
break;
case SYS_DVBS2:
ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
if (ret)
goto err;
utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
/* enough data? */
if (utmp > 4000) {
ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
if (ret)
goto err;
post_bit_error = buf[1] << 8 | buf[0] << 0;
post_bit_count = 32 * utmp; /* TODO: FEC */
dev->post_bit_error += post_bit_error;
dev->post_bit_count += post_bit_count;
dev->dvbv3_ber = post_bit_error;
/* restart measurement */
ret = regmap_write(dev->regmap, 0xd1, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xf9, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xf9, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xd1, 0x00);
if (ret)
goto err;
}
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto err;
}
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev)
{
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
u32 adc_Freq_MHz[3] = {96, 93, 99};
u8 reg16_list[3] = {96, 92, 100}, reg16, reg15;
u32 offset_MHz[3];
u32 max_offset = 0;
u32 old_setting = dev->mclk;
u32 tuner_freq_MHz = c->frequency / 1000;
u8 i;
char big_symbol = 0;
big_symbol = (c->symbol_rate > 45010000) ? 1 : 0;
if (big_symbol) {
reg16 = 115;
} else {
reg16 = 96;
/* TODO: IS THIS NECESSARY ? */
for (i = 0; i < 3; i++) {
offset_MHz[i] = tuner_freq_MHz % adc_Freq_MHz[i];
if (offset_MHz[i] > (adc_Freq_MHz[i] / 2))
offset_MHz[i] = adc_Freq_MHz[i] - offset_MHz[i];
if (offset_MHz[i] > max_offset) {
max_offset = offset_MHz[i];
reg16 = reg16_list[i];
dev->mclk = adc_Freq_MHz[i] * 1000 * 1000;
if (big_symbol)
dev->mclk /= 2;
dev_dbg(&client->dev, "modifying mclk %u -> %u\n",
old_setting, dev->mclk);
}
}
}
if (dev->mclk == 93000000)
regmap_write(dev->regmap, 0xA0, 0x42);
else if (dev->mclk == 96000000)
regmap_write(dev->regmap, 0xA0, 0x44);
else if (dev->mclk == 99000000)
regmap_write(dev->regmap, 0xA0, 0x46);
else if (dev->mclk == 110250000)
regmap_write(dev->regmap, 0xA0, 0x4E);
else
regmap_write(dev->regmap, 0xA0, 0x44);
reg15 = m88ds3103b_dt_read(dev, 0x15);
m88ds3103b_dt_write(dev, 0x05, 0x40);
m88ds3103b_dt_write(dev, 0x11, 0x08);
if (big_symbol)
reg15 |= 0x02;
else
reg15 &= ~0x02;
m88ds3103b_dt_write(dev, 0x15, reg15);
m88ds3103b_dt_write(dev, 0x16, reg16);
usleep_range(5000, 5500);
m88ds3103b_dt_write(dev, 0x05, 0x00);
m88ds3103b_dt_write(dev, 0x11, (u8)(big_symbol ? 0x0E : 0x0A));
usleep_range(5000, 5500);
return 0;
}
static int m88ds3103b_set_mclk(struct m88ds3103_dev *dev, u32 mclk_khz)
{
u8 reg15, reg16, reg1D, reg1E, reg1F, tmp;
u8 sm, f0 = 0, f1 = 0, f2 = 0, f3 = 0;
u16 pll_div_fb, N;
u32 div;
reg15 = m88ds3103b_dt_read(dev, 0x15);
reg16 = m88ds3103b_dt_read(dev, 0x16);
reg1D = m88ds3103b_dt_read(dev, 0x1D);
if (dev->cfg->ts_mode != M88DS3103_TS_SERIAL) {
if (reg16 == 92)
tmp = 93;
else if (reg16 == 100)
tmp = 99;
else
tmp = 96;
mclk_khz *= tmp;
mclk_khz /= 96;
}
pll_div_fb = (reg15 & 0x01) << 8;
pll_div_fb += reg16;
pll_div_fb += 32;
div = 9000 * pll_div_fb * 4;
div /= mclk_khz;
if (dev->cfg->ts_mode == M88DS3103_TS_SERIAL) {
if (div <= 32) {
N = 2;
f0 = 0;
f1 = div / N;
f2 = div - f1;
f3 = 0;
} else if (div <= 34) {
N = 3;
f0 = div / N;
f1 = (div - f0) / (N - 1);
f2 = div - f0 - f1;
f3 = 0;
} else if (div <= 64) {
N = 4;
f0 = div / N;
f1 = (div - f0) / (N - 1);
f2 = (div - f0 - f1) / (N - 2);
f3 = div - f0 - f1 - f2;
} else {
N = 4;
f0 = 16;
f1 = 16;
f2 = 16;
f3 = 16;
}
if (f0 == 16)
f0 = 0;
else if ((f0 < 8) && (f0 != 0))
f0 = 8;
if (f1 == 16)
f1 = 0;
else if ((f1 < 8) && (f1 != 0))
f1 = 8;
if (f2 == 16)
f2 = 0;
else if ((f2 < 8) && (f2 != 0))
f2 = 8;
if (f3 == 16)
f3 = 0;
else if ((f3 < 8) && (f3 != 0))
f3 = 8;
} else {
if (div <= 32) {
N = 2;
f0 = 0;
f1 = div / N;
f2 = div - f1;
f3 = 0;
} else if (div <= 48) {
N = 3;
f0 = div / N;
f1 = (div - f0) / (N - 1);
f2 = div - f0 - f1;
f3 = 0;
} else if (div <= 64) {
N = 4;
f0 = div / N;
f1 = (div - f0) / (N - 1);
f2 = (div - f0 - f1) / (N - 2);
f3 = div - f0 - f1 - f2;
} else {
N = 4;
f0 = 16;
f1 = 16;
f2 = 16;
f3 = 16;
}
if (f0 == 16)
f0 = 0;
else if ((f0 < 9) && (f0 != 0))
f0 = 9;
if (f1 == 16)
f1 = 0;
else if ((f1 < 9) && (f1 != 0))
f1 = 9;
if (f2 == 16)
f2 = 0;
else if ((f2 < 9) && (f2 != 0))
f2 = 9;
if (f3 == 16)
f3 = 0;
else if ((f3 < 9) && (f3 != 0))
f3 = 9;
}
sm = N - 1;
/* Write to registers */
//reg15 &= 0x01;
//reg15 |= (pll_div_fb >> 8) & 0x01;
//reg16 = pll_div_fb & 0xFF;
reg1D &= ~0x03;
reg1D |= sm;
reg1D |= 0x80;
reg1E = ((f3 << 4) + f2) & 0xFF;
reg1F = ((f1 << 4) + f0) & 0xFF;
m88ds3103b_dt_write(dev, 0x05, 0x40);
m88ds3103b_dt_write(dev, 0x11, 0x08);
m88ds3103b_dt_write(dev, 0x1D, reg1D);
m88ds3103b_dt_write(dev, 0x1E, reg1E);
m88ds3103b_dt_write(dev, 0x1F, reg1F);
m88ds3103b_dt_write(dev, 0x17, 0xc1);
m88ds3103b_dt_write(dev, 0x17, 0x81);
usleep_range(5000, 5500);
m88ds3103b_dt_write(dev, 0x05, 0x00);
m88ds3103b_dt_write(dev, 0x11, 0x0A);
usleep_range(5000, 5500);
return 0;
}
static int m88ds3103_set_frontend(struct dvb_frontend *fe)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, len;
const struct m88ds3103_reg_val *init;
u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
u8 buf[3];
u16 u16tmp;
u32 tuner_frequency_khz, target_mclk, u32tmp;
s32 s32tmp;
static const struct reg_sequence reset_buf[] = {
{0x07, 0x80}, {0x07, 0x00}
};
dev_dbg(&client->dev,
"delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
c->inversion, c->pilot, c->rolloff);
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
/* reset */
ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2);
if (ret)
goto err;
/* Disable demod clock path */
if (dev->chip_id == M88RS6000_CHIP_ID) {
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
ret = regmap_read(dev->regmap, 0xb2, &u32tmp);
if (ret)
goto err;
if (u32tmp == 0x01) {
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xb2, 0x00);
if (ret)
goto err;
}
}
ret = regmap_write(dev->regmap, 0x06, 0xe0);
if (ret)
goto err;
}
/* program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
if (fe->ops.tuner_ops.get_frequency) {
ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz);
if (ret)
goto err;
} else {
/*
* Use nominal target frequency as tuner driver does not provide
* actual frequency used. Carrier offset calculation is not
* valid.
*/
tuner_frequency_khz = c->frequency;
}
/* set M88RS6000/DS3103B demod main mclk and ts mclk from tuner die */
if (dev->chip_id == M88RS6000_CHIP_ID) {
if (c->symbol_rate > 45010000)
dev->mclk = 110250000;
else
dev->mclk = 96000000;
if (c->delivery_system == SYS_DVBS)
target_mclk = 96000000;
else
target_mclk = 144000000;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
m88ds3103b_select_mclk(dev);
m88ds3103b_set_mclk(dev, target_mclk / 1000);
}
/* Enable demod clock path */
ret = regmap_write(dev->regmap, 0x06, 0x00);
if (ret)
goto err;
usleep_range(10000, 20000);
} else {
/* set M88DS3103 mclk and ts mclk. */
dev->mclk = 96000000;
switch (dev->cfg->ts_mode) {
case M88DS3103_TS_SERIAL:
case M88DS3103_TS_SERIAL_D7:
target_mclk = dev->cfg->ts_clk;
break;
case M88DS3103_TS_PARALLEL:
case M88DS3103_TS_CI:
if (c->delivery_system == SYS_DVBS)
target_mclk = 96000000;
else {
if (c->symbol_rate < 18000000)
target_mclk = 96000000;
else if (c->symbol_rate < 28000000)
target_mclk = 144000000;
else
target_mclk = 192000000;
}
break;
default:
dev_dbg(&client->dev, "invalid ts_mode\n");
ret = -EINVAL;
goto err;
}
switch (target_mclk) {
case 96000000:
u8tmp1 = 0x02; /* 0b10 */
u8tmp2 = 0x01; /* 0b01 */
break;
case 144000000:
u8tmp1 = 0x00; /* 0b00 */
u8tmp2 = 0x01; /* 0b01 */
break;
case 192000000:
u8tmp1 = 0x03; /* 0b11 */
u8tmp2 = 0x00; /* 0b00 */
break;
}
ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
if (ret)
goto err;
}
ret = regmap_write(dev->regmap, 0xb2, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x00, 0x01);
if (ret)
goto err;
switch (c->delivery_system) {
case SYS_DVBS:
if (dev->chip_id == M88RS6000_CHIP_ID) {
len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
init = m88rs6000_dvbs_init_reg_vals;
} else {
len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
init = m88ds3103_dvbs_init_reg_vals;
}
break;
case SYS_DVBS2:
if (dev->chip_id == M88RS6000_CHIP_ID) {
len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
init = m88rs6000_dvbs2_init_reg_vals;
} else {
len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
init = m88ds3103_dvbs2_init_reg_vals;
}
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto err;
}
/* program init table */
if (c->delivery_system != dev->delivery_system) {
ret = m88ds3103_wr_reg_val_tab(dev, init, len);
if (ret)
goto err;
}
if (dev->chip_id == M88RS6000_CHIP_ID) {
if (c->delivery_system == SYS_DVBS2 &&
c->symbol_rate <= 5000000) {
ret = regmap_write(dev->regmap, 0xc0, 0x04);
if (ret)
goto err;
buf[0] = 0x09;
buf[1] = 0x22;
buf[2] = 0x88;
ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
if (ret)
goto err;
}
ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
if (ret)
goto err;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
buf[0] = m88ds3103b_dt_read(dev, 0x15);
buf[1] = m88ds3103b_dt_read(dev, 0x16);
if (c->symbol_rate > 45010000) {
buf[0] &= ~0x03;
buf[0] |= 0x02;
buf[0] |= ((147 - 32) >> 8) & 0x01;
buf[1] = (147 - 32) & 0xFF;
dev->mclk = 110250 * 1000;
} else {
buf[0] &= ~0x03;
buf[0] |= ((128 - 32) >> 8) & 0x01;
buf[1] = (128 - 32) & 0xFF;
dev->mclk = 96000 * 1000;
}
m88ds3103b_dt_write(dev, 0x15, buf[0]);
m88ds3103b_dt_write(dev, 0x16, buf[1]);
regmap_read(dev->regmap, 0x30, &u32tmp);
u32tmp &= ~0x80;
regmap_write(dev->regmap, 0x30, u32tmp & 0xff);
}
ret = regmap_write(dev->regmap, 0xf1, 0x01);
if (ret)
goto err;
if (dev->chiptype != M88DS3103_CHIPTYPE_3103B) {
ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
if (ret)
goto err;
}
}
switch (dev->cfg->ts_mode) {
case M88DS3103_TS_SERIAL:
u8tmp1 = 0x00;
u8tmp = 0x06;
break;
case M88DS3103_TS_SERIAL_D7:
u8tmp1 = 0x20;
u8tmp = 0x06;
break;
case M88DS3103_TS_PARALLEL:
u8tmp = 0x02;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
u8tmp = 0x01;
u8tmp1 = 0x01;
}
break;
case M88DS3103_TS_CI:
u8tmp = 0x03;
break;
default:
dev_dbg(&client->dev, "invalid ts_mode\n");
ret = -EINVAL;
goto err;
}
if (dev->cfg->ts_clk_pol)
u8tmp |= 0x40;
/* TS mode */
ret = regmap_write(dev->regmap, 0xfd, u8tmp);
if (ret)
goto err;
switch (dev->cfg->ts_mode) {
case M88DS3103_TS_SERIAL:
case M88DS3103_TS_SERIAL_D7:
ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
if (ret)
goto err;
u16tmp = 0;
u8tmp1 = 0x3f;
u8tmp2 = 0x3f;
break;
case M88DS3103_TS_PARALLEL:
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
ret = m88ds3103_update_bits(dev, 0x29, 0x01, u8tmp1);
if (ret)
goto err;
}
fallthrough;
default:
u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
u8tmp1 = u16tmp / 2 - 1;
u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
}
dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
target_mclk, dev->cfg->ts_clk, u16tmp);
/* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
/* u8tmp2[5:0] => ea[5:0] */
u8tmp = (u8tmp1 >> 2) & 0x0f;
ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
if (ret)
goto err;
u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
ret = regmap_write(dev->regmap, 0xea, u8tmp);
if (ret)
goto err;
if (c->symbol_rate <= 3000000)
u8tmp = 0x20;
else if (c->symbol_rate <= 10000000)
u8tmp = 0x10;
else
u8tmp = 0x06;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
m88ds3103b_set_mclk(dev, target_mclk / 1000);
ret = regmap_write(dev->regmap, 0xc3, 0x08);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xc8, u8tmp);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xc4, 0x08);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xc7, 0x00);
if (ret)
goto err;
u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk);
buf[0] = (u16tmp >> 0) & 0xff;
buf[1] = (u16tmp >> 8) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
if (ret)
goto err;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
/* enable/disable 192M LDPC clock */
ret = m88ds3103_update_bits(dev, 0x29, 0x10,
(c->delivery_system == SYS_DVBS) ? 0x10 : 0x0);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0xc9, 0x08, 0x08);
if (ret)
goto err;
}
dev_dbg(&client->dev, "carrier offset=%d\n",
(tuner_frequency_khz - c->frequency));
/* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */
s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency);
s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000);
buf[0] = (s32tmp >> 0) & 0xff;
buf[1] = (s32tmp >> 8) & 0xff;
ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xb2, 0x00);
if (ret)
goto err;
dev->delivery_system = c->delivery_system;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_init(struct dvb_frontend *fe)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, len, rem;
unsigned int utmp;
const struct firmware *firmware;
const char *name;
dev_dbg(&client->dev, "\n");
/* set cold state by default */
dev->warm = false;
/* wake up device from sleep */
ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
if (ret)
goto err;
/* firmware status */
ret = regmap_read(dev->regmap, 0xb9, &utmp);
if (ret)
goto err;
dev_dbg(&client->dev, "firmware=%02x\n", utmp);
if (utmp)
goto warm;
/* global reset, global diseqc reset, global fec reset */
ret = regmap_write(dev->regmap, 0x07, 0xe0);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x07, 0x00);
if (ret)
goto err;
/* cold state - try to download firmware */
dev_info(&client->dev, "found a '%s' in cold state\n",
dev->fe.ops.info.name);
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
name = M88DS3103B_FIRMWARE;
else if (dev->chip_id == M88RS6000_CHIP_ID)
name = M88RS6000_FIRMWARE;
else
name = M88DS3103_FIRMWARE;
/* request the firmware, this will block and timeout */
ret = request_firmware(&firmware, name, &client->dev);
if (ret) {
dev_err(&client->dev, "firmware file '%s' not found\n", name);
goto err;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
ret = regmap_write(dev->regmap, 0xb2, 0x01);
if (ret)
goto err_release_firmware;
for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) {
len = min(dev->cfg->i2c_wr_max - 1, rem);
ret = regmap_bulk_write(dev->regmap, 0xb0,
&firmware->data[firmware->size - rem],
len);
if (ret) {
dev_err(&client->dev, "firmware download failed %d\n",
ret);
goto err_release_firmware;
}
}
ret = regmap_write(dev->regmap, 0xb2, 0x00);
if (ret)
goto err_release_firmware;
release_firmware(firmware);
ret = regmap_read(dev->regmap, 0xb9, &utmp);
if (ret)
goto err;
if (!utmp) {
ret = -EINVAL;
dev_info(&client->dev, "firmware did not run\n");
goto err;
}
dev_info(&client->dev, "found a '%s' in warm state\n",
dev->fe.ops.info.name);
dev_info(&client->dev, "firmware version: %X.%X\n",
(utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
m88ds3103b_dt_write(dev, 0x21, 0x92);
m88ds3103b_dt_write(dev, 0x15, 0x6C);
m88ds3103b_dt_write(dev, 0x17, 0xC1);
m88ds3103b_dt_write(dev, 0x17, 0x81);
}
warm:
/* warm state */
dev->warm = true;
/* init stats here in order signal app which stats are supported */
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
err_release_firmware:
release_firmware(firmware);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_sleep(struct dvb_frontend *fe)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp;
dev_dbg(&client->dev, "\n");
dev->fe_status = 0;
dev->delivery_system = SYS_UNDEFINED;
/* TS Hi-Z */
if (dev->chip_id == M88RS6000_CHIP_ID)
utmp = 0x29;
else
utmp = 0x27;
ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
if (ret)
goto err;
/* sleep */
ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
if (ret)
goto err;
ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 buf[3];
dev_dbg(&client->dev, "\n");
if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
ret = 0;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBS:
ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
if (ret)
goto err;
ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
if (ret)
goto err;
switch ((buf[0] >> 2) & 0x01) {
case 0:
c->inversion = INVERSION_OFF;
break;
case 1:
c->inversion = INVERSION_ON;
break;
}
switch ((buf[1] >> 5) & 0x07) {
case 0:
c->fec_inner = FEC_7_8;
break;
case 1:
c->fec_inner = FEC_5_6;
break;
case 2:
c->fec_inner = FEC_3_4;
break;
case 3:
c->fec_inner = FEC_2_3;
break;
case 4:
c->fec_inner = FEC_1_2;
break;
default:
dev_dbg(&client->dev, "invalid fec_inner\n");
}
c->modulation = QPSK;
break;
case SYS_DVBS2:
ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
if (ret)
goto err;
ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
if (ret)
goto err;
ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
if (ret)
goto err;
switch ((buf[0] >> 0) & 0x0f) {
case 2:
c->fec_inner = FEC_2_5;
break;
case 3:
c->fec_inner = FEC_1_2;
break;
case 4:
c->fec_inner = FEC_3_5;
break;
case 5:
c->fec_inner = FEC_2_3;
break;
case 6:
c->fec_inner = FEC_3_4;
break;
case 7:
c->fec_inner = FEC_4_5;
break;
case 8:
c->fec_inner = FEC_5_6;
break;
case 9:
c->fec_inner = FEC_8_9;
break;
case 10:
c->fec_inner = FEC_9_10;
break;
default:
dev_dbg(&client->dev, "invalid fec_inner\n");
}
switch ((buf[0] >> 5) & 0x01) {
case 0:
c->pilot = PILOT_OFF;
break;
case 1:
c->pilot = PILOT_ON;
break;
}
switch ((buf[0] >> 6) & 0x07) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = PSK_8;
break;
case 2:
c->modulation = APSK_16;
break;
case 3:
c->modulation = APSK_32;
break;
default:
dev_dbg(&client->dev, "invalid modulation\n");
}
switch ((buf[1] >> 7) & 0x01) {
case 0:
c->inversion = INVERSION_OFF;
break;
case 1:
c->inversion = INVERSION_ON;
break;
}
switch ((buf[2] >> 0) & 0x03) {
case 0:
c->rolloff = ROLLOFF_35;
break;
case 1:
c->rolloff = ROLLOFF_25;
break;
case 2:
c->rolloff = ROLLOFF_20;
break;
default:
dev_dbg(&client->dev, "invalid rolloff\n");
}
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
if (ret)
goto err;
c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000);
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
*ber = dev->dvbv3_ber;
return 0;
}
static int m88ds3103_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode fe_sec_tone_mode)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp, tone, reg_a1_mask;
dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
switch (fe_sec_tone_mode) {
case SEC_TONE_ON:
tone = 0;
reg_a1_mask = 0x47;
break;
case SEC_TONE_OFF:
tone = 1;
reg_a1_mask = 0x00;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
ret = -EINVAL;
goto err;
}
utmp = tone << 7 | dev->cfg->envelope_mode << 5;
ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
if (ret)
goto err;
utmp = 1 << 2;
ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage fe_sec_voltage)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp;
bool voltage_sel, voltage_dis;
dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
switch (fe_sec_voltage) {
case SEC_VOLTAGE_18:
voltage_sel = true;
voltage_dis = false;
break;
case SEC_VOLTAGE_13:
voltage_sel = false;
voltage_dis = false;
break;
case SEC_VOLTAGE_OFF:
voltage_sel = false;
voltage_dis = true;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
ret = -EINVAL;
goto err;
}
/* output pin polarity */
voltage_sel ^= dev->cfg->lnb_hv_pol;
voltage_dis ^= dev->cfg->lnb_en_pol;
utmp = voltage_dis << 1 | voltage_sel << 0;
ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *diseqc_cmd)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp;
unsigned long timeout;
dev_dbg(&client->dev, "msg=%*ph\n",
diseqc_cmd->msg_len, diseqc_cmd->msg);
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
ret = -EINVAL;
goto err;
}
utmp = dev->cfg->envelope_mode << 5;
ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
diseqc_cmd->msg_len);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0xa1,
(diseqc_cmd->msg_len - 1) << 3 | 0x07);
if (ret)
goto err;
/* wait DiSEqC TX ready */
#define SEND_MASTER_CMD_TIMEOUT 120
timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
/* DiSEqC message period is 13.5 ms per byte */
utmp = diseqc_cmd->msg_len * 13500;
usleep_range(utmp - 4000, utmp);
for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
ret = regmap_read(dev->regmap, 0xa1, &utmp);
if (ret)
goto err;
utmp = (utmp >> 6) & 0x1;
}
if (utmp == 0) {
dev_dbg(&client->dev, "diseqc tx took %u ms\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
} else {
dev_dbg(&client->dev, "diseqc tx timeout\n");
ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
if (ret)
goto err;
}
ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
if (ret)
goto err;
if (utmp == 1) {
ret = -ETIMEDOUT;
goto err;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd fe_sec_mini_cmd)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
unsigned int utmp, burst;
unsigned long timeout;
dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
if (!dev->warm) {
ret = -EAGAIN;
goto err;
}
utmp = dev->cfg->envelope_mode << 5;
ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
if (ret)
goto err;
switch (fe_sec_mini_cmd) {
case SEC_MINI_A:
burst = 0x02;
break;
case SEC_MINI_B:
burst = 0x01;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap, 0xa1, burst);
if (ret)
goto err;
/* wait DiSEqC TX ready */
#define SEND_BURST_TIMEOUT 40
timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
/* DiSEqC ToneBurst period is 12.5 ms */
usleep_range(8500, 12500);
for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
ret = regmap_read(dev->regmap, 0xa1, &utmp);
if (ret)
goto err;
utmp = (utmp >> 6) & 0x1;
}
if (utmp == 0) {
dev_dbg(&client->dev, "diseqc tx took %u ms\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
} else {
dev_dbg(&client->dev, "diseqc tx timeout\n");
ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
if (ret)
goto err;
}
ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
if (ret)
goto err;
if (utmp == 1) {
ret = -ETIMEDOUT;
goto err;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 3000;
return 0;
}
static void m88ds3103_release(struct dvb_frontend *fe)
{
struct m88ds3103_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
i2c_unregister_device(client);
}
static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
{
struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
struct i2c_client *client = dev->client;
int ret;
struct i2c_msg msg = {
.addr = client->addr,
.flags = 0,
.len = 2,
.buf = "\x03\x11",
};
/* Open tuner I2C repeater for 1 xfer, closes automatically */
ret = __i2c_transfer(client->adapter, &msg, 1);
if (ret != 1) {
dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
if (ret >= 0)
ret = -EREMOTEIO;
return ret;
}
return 0;
}
/*
* XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
* proper I2C client for legacy media attach binding.
* New users must use I2C client binding directly!
*/
struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
struct i2c_adapter *i2c,
struct i2c_adapter **tuner_i2c_adapter)
{
struct i2c_client *client;
struct i2c_board_info board_info;
struct m88ds3103_platform_data pdata = {};
pdata.clk = cfg->clock;
pdata.i2c_wr_max = cfg->i2c_wr_max;
pdata.ts_mode = cfg->ts_mode;
pdata.ts_clk = cfg->ts_clk;
pdata.ts_clk_pol = cfg->ts_clk_pol;
pdata.spec_inv = cfg->spec_inv;
pdata.agc = cfg->agc;
pdata.agc_inv = cfg->agc_inv;
pdata.clk_out = cfg->clock_out;
pdata.envelope_mode = cfg->envelope_mode;
pdata.lnb_hv_pol = cfg->lnb_hv_pol;
pdata.lnb_en_pol = cfg->lnb_en_pol;
pdata.attach_in_use = true;
memset(&board_info, 0, sizeof(board_info));
strscpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
board_info.addr = cfg->i2c_addr;
board_info.platform_data = &pdata;
client = i2c_new_client_device(i2c, &board_info);
if (!i2c_client_has_driver(client))
return NULL;
*tuner_i2c_adapter = pdata.get_i2c_adapter(client);
return pdata.get_dvb_frontend(client);
}
EXPORT_SYMBOL_GPL(m88ds3103_attach);
static const struct dvb_frontend_ops m88ds3103_ops = {
.delsys = {SYS_DVBS, SYS_DVBS2},
.info = {
.name = "Montage Technology M88DS3103",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_8_9 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_RECOVER |
FE_CAN_2G_MODULATION
},
.release = m88ds3103_release,
.get_tune_settings = m88ds3103_get_tune_settings,
.init = m88ds3103_init,
.sleep = m88ds3103_sleep,
.set_frontend = m88ds3103_set_frontend,
.get_frontend = m88ds3103_get_frontend,
.read_status = m88ds3103_read_status,
.read_snr = m88ds3103_read_snr,
.read_ber = m88ds3103_read_ber,
.diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
.diseqc_send_burst = m88ds3103_diseqc_send_burst,
.set_tone = m88ds3103_set_tone,
.set_voltage = m88ds3103_set_voltage,
};
static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
{
struct m88ds3103_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &dev->fe;
}
static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
{
struct m88ds3103_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return dev->muxc->adapter[0];
}
static int m88ds3103_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct m88ds3103_dev *dev;
struct m88ds3103_platform_data *pdata = client->dev.platform_data;
int ret;
unsigned int utmp;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
dev->client = client;
dev->config.clock = pdata->clk;
dev->config.i2c_wr_max = pdata->i2c_wr_max;
dev->config.ts_mode = pdata->ts_mode;
dev->config.ts_clk = pdata->ts_clk * 1000;
dev->config.ts_clk_pol = pdata->ts_clk_pol;
dev->config.spec_inv = pdata->spec_inv;
dev->config.agc_inv = pdata->agc_inv;
dev->config.clock_out = pdata->clk_out;
dev->config.envelope_mode = pdata->envelope_mode;
dev->config.agc = pdata->agc;
dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
dev->config.lnb_en_pol = pdata->lnb_en_pol;
dev->cfg = &dev->config;
/* create regmap */
dev->regmap_config.reg_bits = 8;
dev->regmap_config.val_bits = 8;
dev->regmap_config.lock_arg = dev;
dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
/* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
ret = regmap_read(dev->regmap, 0x00, &utmp);
if (ret)
goto err_kfree;
dev->chip_id = utmp >> 1;
dev->chiptype = (u8)id->driver_data;
dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
switch (dev->chip_id) {
case M88RS6000_CHIP_ID:
case M88DS3103_CHIP_ID:
break;
default:
ret = -ENODEV;
dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id);
goto err_kfree;
}
switch (dev->cfg->clock_out) {
case M88DS3103_CLOCK_OUT_DISABLED:
utmp = 0x80;
break;
case M88DS3103_CLOCK_OUT_ENABLED:
utmp = 0x00;
break;
case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
utmp = 0x10;
break;
default:
ret = -EINVAL;
goto err_kfree;
}
if (!pdata->ts_clk) {
ret = -EINVAL;
goto err_kfree;
}
/* 0x29 register is defined differently for m88rs6000. */
/* set internal tuner address to 0x21 */
if (dev->chip_id == M88RS6000_CHIP_ID)
utmp = 0x00;
ret = regmap_write(dev->regmap, 0x29, utmp);
if (ret)
goto err_kfree;
/* sleep */
ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
if (ret)
goto err_kfree;
ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
if (ret)
goto err_kfree;
ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
if (ret)
goto err_kfree;
/* create mux i2c adapter for tuner */
dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
m88ds3103_select, NULL);
if (!dev->muxc) {
ret = -ENOMEM;
goto err_kfree;
}
dev->muxc->priv = dev;
ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
if (ret)
goto err_kfree;
/* create dvb_frontend */
memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
strscpy(dev->fe.ops.info.name, "Montage Technology M88DS3103B",
sizeof(dev->fe.ops.info.name));
else if (dev->chip_id == M88RS6000_CHIP_ID)
strscpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
sizeof(dev->fe.ops.info.name));
if (!pdata->attach_in_use)
dev->fe.ops.release = NULL;
dev->fe.demodulator_priv = dev;
i2c_set_clientdata(client, dev);
/* setup callbacks */
pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
/* enable i2c repeater for tuner */
m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
/* get frontend address */
ret = regmap_read(dev->regmap, 0x29, &utmp);
if (ret)
goto err_kfree;
dev->dt_addr = ((utmp & 0x80) == 0) ? 0x42 >> 1 : 0x40 >> 1;
dev_dbg(&client->dev, "dt addr is 0x%02x\n", dev->dt_addr);
dev->dt_client = i2c_new_dummy_device(client->adapter,
dev->dt_addr);
if (IS_ERR(dev->dt_client)) {
ret = PTR_ERR(dev->dt_client);
goto err_kfree;
}
}
return 0;
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void m88ds3103_remove(struct i2c_client *client)
{
struct m88ds3103_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
if (dev->dt_client)
i2c_unregister_device(dev->dt_client);
i2c_mux_del_adapters(dev->muxc);
kfree(dev);
}
static const struct i2c_device_id m88ds3103_id_table[] = {
{"m88ds3103", M88DS3103_CHIPTYPE_3103},
{"m88rs6000", M88DS3103_CHIPTYPE_RS6000},
{"m88ds3103b", M88DS3103_CHIPTYPE_3103B},
{}
};
MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
static struct i2c_driver m88ds3103_driver = {
.driver = {
.name = "m88ds3103",
.suppress_bind_attrs = true,
},
.probe = m88ds3103_probe,
.remove = m88ds3103_remove,
.id_table = m88ds3103_id_table,
};
module_i2c_driver(m88ds3103_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(M88DS3103_FIRMWARE);
MODULE_FIRMWARE(M88RS6000_FIRMWARE);
MODULE_FIRMWARE(M88DS3103B_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/m88ds3103.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Panasonic MN88472 DVB-T/T2/C demodulator driver
*
* Copyright (C) 2013 Antti Palosaari <[email protected]>
*/
#include "mn88472_priv.h"
static int mn88472_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 1000;
return 0;
}
static int mn88472_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88472_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, stmp;
unsigned int utmp, utmp1, utmp2;
u8 buf[5];
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
ret = regmap_read(dev->regmap[0], 0x7f, &utmp);
if (ret)
goto err;
if ((utmp & 0x0f) >= 0x09)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
else
*status = 0;
break;
case SYS_DVBT2:
ret = regmap_read(dev->regmap[2], 0x92, &utmp);
if (ret)
goto err;
if ((utmp & 0x0f) >= 0x0d)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
else if ((utmp & 0x0f) >= 0x0a)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
else if ((utmp & 0x0f) >= 0x07)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
else
*status = 0;
break;
case SYS_DVBC_ANNEX_A:
ret = regmap_read(dev->regmap[1], 0x84, &utmp);
if (ret)
goto err;
if ((utmp & 0x0f) >= 0x08)
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
else
*status = 0;
break;
default:
ret = -EINVAL;
goto err;
}
/* Signal strength */
if (*status & FE_HAS_SIGNAL) {
for (i = 0; i < 2; i++) {
ret = regmap_bulk_read(dev->regmap[2], 0x8e + i,
&buf[i], 1);
if (ret)
goto err;
}
utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
dev_dbg(&client->dev, "strength=%u\n", utmp1);
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = utmp1;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
/* DVB-T CNR */
ret = regmap_bulk_read(dev->regmap[0], 0x9c, buf, 2);
if (ret)
goto err;
utmp = buf[0] << 8 | buf[1] << 0;
if (utmp) {
/* CNR[dB]: 10 * log10(65536 / value) + 2 */
/* log10(65536) = 80807124, 0.2 = 3355443 */
stmp = ((u64)80807124 - intlog10(utmp) + 3355443)
* 10000 >> 24;
dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else if (*status & FE_HAS_VITERBI &&
c->delivery_system == SYS_DVBT2) {
/* DVB-T2 CNR */
for (i = 0; i < 3; i++) {
ret = regmap_bulk_read(dev->regmap[2], 0xbc + i,
&buf[i], 1);
if (ret)
goto err;
}
utmp = buf[1] << 8 | buf[2] << 0;
utmp1 = (buf[0] >> 2) & 0x01; /* 0=SISO, 1=MISO */
if (utmp) {
if (utmp1) {
/* CNR[dB]: 10 * log10(16384 / value) - 6 */
/* log10(16384) = 70706234, 0.6 = 10066330 */
stmp = ((u64)70706234 - intlog10(utmp)
- 10066330) * 10000 >> 24;
dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
stmp, utmp);
} else {
/* CNR[dB]: 10 * log10(65536 / value) + 2 */
/* log10(65536) = 80807124, 0.2 = 3355443 */
stmp = ((u64)80807124 - intlog10(utmp)
+ 3355443) * 10000 >> 24;
dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
stmp, utmp);
}
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else if (*status & FE_HAS_VITERBI &&
c->delivery_system == SYS_DVBC_ANNEX_A) {
/* DVB-C CNR */
ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
if (ret)
goto err;
utmp1 = buf[0] << 8 | buf[1] << 0; /* signal */
utmp2 = buf[2] << 8 | buf[3] << 0; /* noise */
if (utmp1 && utmp2) {
/* CNR[dB]: 10 * log10(8 * (signal / noise)) */
/* log10(8) = 15151336 */
stmp = ((u64)15151336 + intlog10(utmp1)
- intlog10(utmp2)) * 10000 >> 24;
dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
stmp, utmp1, utmp2);
} else {
stmp = 0;
}
c->cnr.stat[0].svalue = stmp;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* PER */
if (*status & FE_HAS_SYNC) {
ret = regmap_bulk_read(dev->regmap[0], 0xe1, buf, 4);
if (ret)
goto err;
utmp1 = buf[0] << 8 | buf[1] << 0;
utmp2 = buf[2] << 8 | buf[3] << 0;
dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
utmp1, utmp2);
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += utmp1;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += utmp2;
} else {
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88472_set_frontend(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88472_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
unsigned int utmp;
u32 if_frequency;
u8 buf[3], delivery_system_val, bandwidth_val, *bandwidth_vals_ptr;
u8 reg_bank0_b4_val, reg_bank0_cd_val, reg_bank0_d4_val;
u8 reg_bank0_d6_val;
dev_dbg(&client->dev,
"delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
c->delivery_system, c->modulation, c->frequency,
c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
delivery_system_val = 0x02;
reg_bank0_b4_val = 0x00;
reg_bank0_cd_val = 0x1f;
reg_bank0_d4_val = 0x0a;
reg_bank0_d6_val = 0x48;
break;
case SYS_DVBT2:
delivery_system_val = 0x03;
reg_bank0_b4_val = 0xf6;
reg_bank0_cd_val = 0x01;
reg_bank0_d4_val = 0x09;
reg_bank0_d6_val = 0x46;
break;
case SYS_DVBC_ANNEX_A:
delivery_system_val = 0x04;
reg_bank0_b4_val = 0x00;
reg_bank0_cd_val = 0x17;
reg_bank0_d4_val = 0x09;
reg_bank0_d6_val = 0x48;
break;
default:
ret = -EINVAL;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
case SYS_DVBT2:
switch (c->bandwidth_hz) {
case 5000000:
bandwidth_vals_ptr = "\xe5\x99\x9a\x1b\xa9\x1b\xa9";
bandwidth_val = 0x03;
break;
case 6000000:
bandwidth_vals_ptr = "\xbf\x55\x55\x15\x6b\x15\x6b";
bandwidth_val = 0x02;
break;
case 7000000:
bandwidth_vals_ptr = "\xa4\x00\x00\x0f\x2c\x0f\x2c";
bandwidth_val = 0x01;
break;
case 8000000:
bandwidth_vals_ptr = "\x8f\x80\x00\x08\xee\x08\xee";
bandwidth_val = 0x00;
break;
default:
ret = -EINVAL;
goto err;
}
break;
case SYS_DVBC_ANNEX_A:
bandwidth_vals_ptr = NULL;
bandwidth_val = 0x00;
break;
default:
break;
}
/* Program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto err;
dev_dbg(&client->dev, "get_if_frequency=%d\n", if_frequency);
} else {
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap[2], 0x00, 0x66);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x01, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x02, 0x01);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val);
if (ret)
goto err;
/* IF */
utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, dev->clk);
buf[0] = (utmp >> 16) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 0) & 0xff;
for (i = 0; i < 3; i++) {
ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]);
if (ret)
goto err;
}
/* Bandwidth */
if (bandwidth_vals_ptr) {
for (i = 0; i < 7; i++) {
ret = regmap_write(dev->regmap[2], 0x13 + i,
bandwidth_vals_ptr[i]);
if (ret)
goto err;
}
}
ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0xd6, reg_bank0_d6_val);
if (ret)
goto err;
switch (c->delivery_system) {
case SYS_DVBT:
ret = regmap_write(dev->regmap[0], 0x07, 0x26);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x00, 0xba);
if (ret)
goto err;
ret = regmap_write(dev->regmap[0], 0x01, 0x13);
if (ret)
goto err;
break;
case SYS_DVBT2:
ret = regmap_write(dev->regmap[2], 0x2b, 0x13);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x4f, 0x05);
if (ret)
goto err;
ret = regmap_write(dev->regmap[1], 0xf6, 0x05);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x32,
(c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
c->stream_id );
if (ret)
goto err;
break;
case SYS_DVBC_ANNEX_A:
break;
default:
break;
}
/* Reset FSM */
ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88472_init(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88472_dev *dev = i2c_get_clientdata(client);
int ret, len, rem;
unsigned int utmp;
const struct firmware *firmware;
const char *name = MN88472_FIRMWARE;
dev_dbg(&client->dev, "\n");
/* Power up */
ret = regmap_write(dev->regmap[2], 0x05, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x0c, 0x00);
if (ret)
goto err;
/* Check if firmware is already running */
ret = regmap_read(dev->regmap[0], 0xf5, &utmp);
if (ret)
goto err;
if (!(utmp & 0x01))
goto warm;
ret = request_firmware(&firmware, name, &client->dev);
if (ret) {
dev_err(&client->dev, "firmware file '%s' not found\n", name);
goto err;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
if (ret)
goto err_release_firmware;
for (rem = firmware->size; rem > 0; rem -= (dev->i2c_write_max - 1)) {
len = min(dev->i2c_write_max - 1, rem);
ret = regmap_bulk_write(dev->regmap[0], 0xf6,
&firmware->data[firmware->size - rem],
len);
if (ret) {
dev_err(&client->dev, "firmware download failed %d\n",
ret);
goto err_release_firmware;
}
}
/* Parity check of firmware */
ret = regmap_read(dev->regmap[0], 0xf8, &utmp);
if (ret)
goto err_release_firmware;
if (utmp & 0x10) {
ret = -EINVAL;
dev_err(&client->dev, "firmware did not run\n");
goto err_release_firmware;
}
ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
if (ret)
goto err_release_firmware;
release_firmware(firmware);
warm:
/* TS config */
switch (dev->ts_mode) {
case SERIAL_TS_MODE:
utmp = 0x1d;
break;
case PARALLEL_TS_MODE:
utmp = 0x00;
break;
default:
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap[2], 0x08, utmp);
if (ret)
goto err;
switch (dev->ts_clk) {
case VARIABLE_TS_CLOCK:
utmp = 0xe3;
break;
case FIXED_TS_CLOCK:
utmp = 0xe1;
break;
default:
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap[0], 0xd9, utmp);
if (ret)
goto err;
dev->active = true;
return 0;
err_release_firmware:
release_firmware(firmware);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int mn88472_sleep(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct mn88472_dev *dev = i2c_get_clientdata(client);
int ret;
dev_dbg(&client->dev, "\n");
/* Power down */
ret = regmap_write(dev->regmap[2], 0x0c, 0x30);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x0b, 0x30);
if (ret)
goto err;
ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_frontend_ops mn88472_ops = {
.delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
.info = {
.name = "Panasonic MN88472",
.symbol_rate_min = 1000000,
.symbol_rate_max = 7200000,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_2G_MODULATION |
FE_CAN_MULTISTREAM
},
.get_tune_settings = mn88472_get_tune_settings,
.init = mn88472_init,
.sleep = mn88472_sleep,
.set_frontend = mn88472_set_frontend,
.read_status = mn88472_read_status,
};
static struct dvb_frontend *mn88472_get_dvb_frontend(struct i2c_client *client)
{
struct mn88472_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &dev->fe;
}
static int mn88472_probe(struct i2c_client *client)
{
struct mn88472_config *pdata = client->dev.platform_data;
struct mn88472_dev *dev;
struct dtv_frontend_properties *c;
int ret;
unsigned int utmp;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
dev_dbg(&client->dev, "\n");
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
dev->i2c_write_max = pdata->i2c_wr_max ? pdata->i2c_wr_max : ~0;
dev->clk = pdata->xtal;
dev->ts_mode = pdata->ts_mode;
dev->ts_clk = pdata->ts_clock;
dev->client[0] = client;
dev->regmap[0] = regmap_init_i2c(dev->client[0], ®map_config);
if (IS_ERR(dev->regmap[0])) {
ret = PTR_ERR(dev->regmap[0]);
goto err_kfree;
}
/*
* Chip has three I2C addresses for different register banks. Used
* addresses are 0x18, 0x1a and 0x1c. We register two dummy clients,
* 0x1a and 0x1c, in order to get own I2C client for each register bank.
*
* Also, register bank 2 do not support sequential I/O. Only single
* register write or read is allowed to that bank.
*/
dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a);
if (IS_ERR(dev->client[1])) {
ret = PTR_ERR(dev->client[1]);
dev_err(&client->dev, "I2C registration failed\n");
goto err_regmap_0_regmap_exit;
}
dev->regmap[1] = regmap_init_i2c(dev->client[1], ®map_config);
if (IS_ERR(dev->regmap[1])) {
ret = PTR_ERR(dev->regmap[1]);
goto err_client_1_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[1], dev);
dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c);
if (IS_ERR(dev->client[2])) {
ret = PTR_ERR(dev->client[2]);
dev_err(&client->dev, "2nd I2C registration failed\n");
goto err_regmap_1_regmap_exit;
}
dev->regmap[2] = regmap_init_i2c(dev->client[2], ®map_config);
if (IS_ERR(dev->regmap[2])) {
ret = PTR_ERR(dev->regmap[2]);
goto err_client_2_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[2], dev);
/* Check demod answers with correct chip id */
ret = regmap_read(dev->regmap[2], 0xff, &utmp);
if (ret)
goto err_regmap_2_regmap_exit;
dev_dbg(&client->dev, "chip id=%02x\n", utmp);
if (utmp != 0x02) {
ret = -ENODEV;
goto err_regmap_2_regmap_exit;
}
/* Sleep because chip is active by default */
ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
if (ret)
goto err_regmap_2_regmap_exit;
/* Create dvb frontend */
memcpy(&dev->fe.ops, &mn88472_ops, sizeof(struct dvb_frontend_ops));
dev->fe.demodulator_priv = client;
*pdata->fe = &dev->fe;
i2c_set_clientdata(client, dev);
/* Init stats to indicate which stats are supported */
c = &dev->fe.dtv_property_cache;
c->strength.len = 1;
c->cnr.len = 1;
c->block_error.len = 1;
c->block_count.len = 1;
/* Setup callbacks */
pdata->get_dvb_frontend = mn88472_get_dvb_frontend;
dev_info(&client->dev, "Panasonic MN88472 successfully identified\n");
return 0;
err_regmap_2_regmap_exit:
regmap_exit(dev->regmap[2]);
err_client_2_i2c_unregister_device:
i2c_unregister_device(dev->client[2]);
err_regmap_1_regmap_exit:
regmap_exit(dev->regmap[1]);
err_client_1_i2c_unregister_device:
i2c_unregister_device(dev->client[1]);
err_regmap_0_regmap_exit:
regmap_exit(dev->regmap[0]);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void mn88472_remove(struct i2c_client *client)
{
struct mn88472_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
regmap_exit(dev->regmap[2]);
i2c_unregister_device(dev->client[2]);
regmap_exit(dev->regmap[1]);
i2c_unregister_device(dev->client[1]);
regmap_exit(dev->regmap[0]);
kfree(dev);
}
static const struct i2c_device_id mn88472_id_table[] = {
{"mn88472", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, mn88472_id_table);
static struct i2c_driver mn88472_driver = {
.driver = {
.name = "mn88472",
.suppress_bind_attrs = true,
},
.probe = mn88472_probe,
.remove = mn88472_remove,
.id_table = mn88472_id_table,
};
module_i2c_driver(mn88472_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Panasonic MN88472 DVB-T/T2/C demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(MN88472_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/mn88472.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator
*
* Copyright (C) 2013-2017 Matthias Schwarzott <[email protected]>
*
* References:
* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/firmware.h>
#include <linux/regmap.h>
#include <media/dvb_frontend.h>
#include <linux/int_log.h>
#include "si2165_priv.h"
#include "si2165.h"
/*
* Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx
* uses 16 MHz xtal
*
* Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx
* uses 24 MHz clock provided by tuner
*/
struct si2165_state {
struct i2c_client *client;
struct regmap *regmap;
struct dvb_frontend fe;
struct si2165_config config;
u8 chip_revcode;
u8 chip_type;
/* calculated by xtal and div settings */
u32 fvco_hz;
u32 sys_clk;
u32 adc_clk;
/* DVBv3 stats */
u64 ber_prev;
bool has_dvbc;
bool has_dvbt;
bool firmware_loaded;
};
static int si2165_write(struct si2165_state *state, const u16 reg,
const u8 *src, const int count)
{
int ret;
dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n",
reg, count, src);
ret = regmap_bulk_write(state->regmap, reg, src, count);
if (ret)
dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
return ret;
}
static int si2165_read(struct si2165_state *state,
const u16 reg, u8 *val, const int count)
{
int ret = regmap_bulk_read(state->regmap, reg, val, count);
if (ret) {
dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
__func__, state->config.i2c_addr, reg, ret);
return ret;
}
dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n",
reg, count, val);
return 0;
}
static int si2165_readreg8(struct si2165_state *state,
const u16 reg, u8 *val)
{
unsigned int val_tmp;
int ret = regmap_read(state->regmap, reg, &val_tmp);
*val = (u8)val_tmp;
dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val);
return ret;
}
static int si2165_readreg16(struct si2165_state *state,
const u16 reg, u16 *val)
{
u8 buf[2];
int ret = si2165_read(state, reg, buf, 2);
*val = buf[0] | buf[1] << 8;
dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val);
return ret;
}
static int si2165_readreg24(struct si2165_state *state,
const u16 reg, u32 *val)
{
u8 buf[3];
int ret = si2165_read(state, reg, buf, 3);
*val = buf[0] | buf[1] << 8 | buf[2] << 16;
dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val);
return ret;
}
static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)
{
return regmap_write(state->regmap, reg, val);
}
static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)
{
u8 buf[2] = { val & 0xff, (val >> 8) & 0xff };
return si2165_write(state, reg, buf, 2);
}
static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)
{
u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff };
return si2165_write(state, reg, buf, 3);
}
static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)
{
u8 buf[4] = {
val & 0xff,
(val >> 8) & 0xff,
(val >> 16) & 0xff,
(val >> 24) & 0xff
};
return si2165_write(state, reg, buf, 4);
}
static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,
u8 val, u8 mask)
{
if (mask != 0xff) {
u8 tmp;
int ret = si2165_readreg8(state, reg, &tmp);
if (ret < 0)
return ret;
val &= mask;
tmp &= ~mask;
val |= tmp;
}
return si2165_writereg8(state, reg, val);
}
#define REG16(reg, val) \
{ (reg), (val) & 0xff }, \
{ (reg) + 1, (val) >> 8 & 0xff }
struct si2165_reg_value_pair {
u16 reg;
u8 val;
};
static int si2165_write_reg_list(struct si2165_state *state,
const struct si2165_reg_value_pair *regs,
int count)
{
int i;
int ret;
for (i = 0; i < count; i++) {
ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
if (ret < 0)
return ret;
}
return 0;
}
static int si2165_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 1000;
return 0;
}
static int si2165_init_pll(struct si2165_state *state)
{
u32 ref_freq_hz = state->config.ref_freq_hz;
u8 divr = 1; /* 1..7 */
u8 divp = 1; /* only 1 or 4 */
u8 divn = 56; /* 1..63 */
u8 divm = 8;
u8 divl = 12;
u8 buf[4];
/*
* hardcoded values can be deleted if calculation is verified
* or it yields the same values as the windows driver
*/
switch (ref_freq_hz) {
case 16000000u:
divn = 56;
break;
case 24000000u:
divr = 2;
divp = 4;
divn = 19;
break;
default:
/* ref_freq / divr must be between 4 and 16 MHz */
if (ref_freq_hz > 16000000u)
divr = 2;
/*
* now select divn and divp such that
* fvco is in 1624..1824 MHz
*/
if (1624000000u * divr > ref_freq_hz * 2u * 63u)
divp = 4;
/* is this already correct regarding rounding? */
divn = 1624000000u * divr / (ref_freq_hz * 2u * divp);
break;
}
/* adc_clk and sys_clk depend on xtal and pll settings */
state->fvco_hz = ref_freq_hz / divr
* 2u * divn * divp;
state->adc_clk = state->fvco_hz / (divm * 4u);
state->sys_clk = state->fvco_hz / (divl * 2u);
/* write all 4 pll registers 0x00a0..0x00a3 at once */
buf[0] = divl;
buf[1] = divm;
buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80;
buf[3] = divr;
return si2165_write(state, REG_PLL_DIVL, buf, 4);
}
static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)
{
state->sys_clk = state->fvco_hz / (divl * 2u);
return si2165_writereg8(state, REG_PLL_DIVL, divl);
}
static u32 si2165_get_fe_clk(struct si2165_state *state)
{
/* assume Oversampling mode Ovr4 is used */
return state->adc_clk;
}
static int si2165_wait_init_done(struct si2165_state *state)
{
int ret;
u8 val = 0;
int i;
for (i = 0; i < 3; ++i) {
ret = si2165_readreg8(state, REG_INIT_DONE, &val);
if (ret < 0)
return ret;
if (val == 0x01)
return 0;
usleep_range(1000, 50000);
}
dev_err(&state->client->dev, "init_done was not set\n");
return -EINVAL;
}
static int si2165_upload_firmware_block(struct si2165_state *state,
const u8 *data, u32 len, u32 *poffset,
u32 block_count)
{
int ret;
u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 };
u8 wordcount;
u32 cur_block = 0;
u32 offset = poffset ? *poffset : 0;
if (len < 4)
return -EINVAL;
if (len % 4 != 0)
return -EINVAL;
dev_dbg(&state->client->dev,
"fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n",
__func__, len, offset, block_count);
while (offset + 12 <= len && cur_block < block_count) {
dev_dbg(&state->client->dev,
"fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
__func__, len, offset, cur_block, block_count);
wordcount = data[offset];
if (wordcount < 1 || data[offset + 1] ||
data[offset + 2] || data[offset + 3]) {
dev_warn(&state->client->dev,
"bad fw data[0..3] = %*ph\n",
4, data);
return -EINVAL;
}
if (offset + 8 + wordcount * 4 > len) {
dev_warn(&state->client->dev,
"len is too small for block len=%d, wordcount=%d\n",
len, wordcount);
return -EINVAL;
}
buf_ctrl[0] = wordcount - 1;
ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);
if (ret < 0)
goto error;
ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);
if (ret < 0)
goto error;
offset += 8;
while (wordcount > 0) {
ret = si2165_write(state, REG_DCOM_DATA,
data + offset, 4);
if (ret < 0)
goto error;
wordcount--;
offset += 4;
}
cur_block++;
}
dev_dbg(&state->client->dev,
"fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
__func__, len, offset, cur_block, block_count);
if (poffset)
*poffset = offset;
dev_dbg(&state->client->dev,
"fw load: %s: returned offset=0x%x\n",
__func__, offset);
return 0;
error:
return ret;
}
static int si2165_upload_firmware(struct si2165_state *state)
{
/* int ret; */
u8 val[3];
u16 val16;
int ret;
const struct firmware *fw = NULL;
u8 *fw_file;
const u8 *data;
u32 len;
u32 offset;
u8 patch_version;
u8 block_count;
u16 crc_expected;
switch (state->chip_revcode) {
case 0x03: /* revision D */
fw_file = SI2165_FIRMWARE_REV_D;
break;
default:
dev_info(&state->client->dev, "no firmware file for revision=%d\n",
state->chip_revcode);
return 0;
}
/* request the firmware, this will block and timeout */
ret = request_firmware(&fw, fw_file, &state->client->dev);
if (ret) {
dev_warn(&state->client->dev, "firmware file '%s' not found\n",
fw_file);
goto error;
}
data = fw->data;
len = fw->size;
dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n",
fw_file, len);
if (len % 4 != 0) {
dev_warn(&state->client->dev, "firmware size is not multiple of 4\n");
ret = -EINVAL;
goto error;
}
/* check header (8 bytes) */
if (len < 8) {
dev_warn(&state->client->dev, "firmware header is missing\n");
ret = -EINVAL;
goto error;
}
if (data[0] != 1 || data[1] != 0) {
dev_warn(&state->client->dev, "firmware file version is wrong\n");
ret = -EINVAL;
goto error;
}
patch_version = data[2];
block_count = data[4];
crc_expected = data[7] << 8 | data[6];
/* start uploading fw */
/* boot/wdog status */
ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
if (ret < 0)
goto error;
/* reset */
ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
if (ret < 0)
goto error;
/* boot/wdog status */
ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
if (ret < 0)
goto error;
/* enable reset on error */
ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
if (ret < 0)
goto error;
ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
if (ret < 0)
goto error;
/* start right after the header */
offset = 8;
dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",
__func__, patch_version, block_count, crc_expected);
ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
if (ret < 0)
goto error;
/* reset crc */
ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
if (ret)
goto error;
ret = si2165_upload_firmware_block(state, data, len,
&offset, block_count);
if (ret < 0) {
dev_err(&state->client->dev,
"firmware could not be uploaded\n");
goto error;
}
/* read crc */
ret = si2165_readreg16(state, REG_CRC, &val16);
if (ret)
goto error;
if (val16 != crc_expected) {
dev_err(&state->client->dev,
"firmware crc mismatch %04x != %04x\n",
val16, crc_expected);
ret = -EINVAL;
goto error;
}
ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
if (ret)
goto error;
if (len != offset) {
dev_err(&state->client->dev,
"firmware len mismatch %04x != %04x\n",
len, offset);
ret = -EINVAL;
goto error;
}
/* reset watchdog error register */
ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);
if (ret < 0)
goto error;
/* enable reset on error */
ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);
if (ret < 0)
goto error;
dev_info(&state->client->dev, "fw load finished\n");
ret = 0;
state->firmware_loaded = true;
error:
if (fw) {
release_firmware(fw);
fw = NULL;
}
return ret;
}
static int si2165_init(struct dvb_frontend *fe)
{
int ret = 0;
struct si2165_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 val;
u8 patch_version = 0x00;
dev_dbg(&state->client->dev, "%s: called\n", __func__);
/* powerup */
ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
if (ret < 0)
goto error;
/* dsp_clock_enable */
ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
if (ret < 0)
goto error;
/* verify chip_mode */
ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
if (ret < 0)
goto error;
if (val != state->config.chip_mode) {
dev_err(&state->client->dev, "could not set chip_mode\n");
return -EINVAL;
}
/* agc */
ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
if (ret < 0)
goto error;
/* rssi pad */
ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
if (ret < 0)
goto error;
ret = si2165_init_pll(state);
if (ret < 0)
goto error;
/* enable chip_init */
ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
if (ret < 0)
goto error;
/* set start_init */
ret = si2165_writereg8(state, REG_START_INIT, 0x01);
if (ret < 0)
goto error;
ret = si2165_wait_init_done(state);
if (ret < 0)
goto error;
/* disable chip_init */
ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
if (ret < 0)
goto error;
/* ber_pkt - default 65535 */
ret = si2165_writereg16(state, REG_BER_PKT,
STATISTICS_PERIOD_PKT_COUNT);
if (ret < 0)
goto error;
ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);
if (ret < 0)
goto error;
ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
if (ret < 0)
goto error;
/* dsp_addr_jump */
ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
if (ret < 0)
goto error;
/* boot/wdog status */
ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);
if (ret < 0)
goto error;
if (patch_version == 0x00) {
ret = si2165_upload_firmware(state);
if (ret < 0)
goto error;
}
/* ts output config */
ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
if (ret < 0)
return ret;
ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);
if (ret < 0)
return ret;
ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);
if (ret < 0)
return ret;
ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
if (ret < 0)
return ret;
ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
if (ret < 0)
return ret;
c = &state->fe.dtv_property_cache;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
error:
return ret;
}
static int si2165_sleep(struct dvb_frontend *fe)
{
int ret;
struct si2165_state *state = fe->demodulator_priv;
/* dsp clock disable */
ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
if (ret < 0)
return ret;
/* chip mode */
ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
if (ret < 0)
return ret;
return 0;
}
static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
int ret;
u8 u8tmp;
u32 u32tmp;
struct si2165_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 delsys = c->delivery_system;
*status = 0;
switch (delsys) {
case SYS_DVBT:
/* check fast signal type */
ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);
if (ret < 0)
return ret;
switch (u8tmp & 0x3) {
case 0: /* searching */
case 1: /* nothing */
break;
case 2: /* digital signal */
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
break;
}
break;
case SYS_DVBC_ANNEX_A:
/* check packet sync lock */
ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);
if (ret < 0)
return ret;
if (u8tmp & 0x01) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
}
break;
}
/* check fec_lock */
ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);
if (ret < 0)
return ret;
if (u8tmp & 0x01) {
*status |= FE_HAS_SIGNAL;
*status |= FE_HAS_CARRIER;
*status |= FE_HAS_VITERBI;
*status |= FE_HAS_SYNC;
*status |= FE_HAS_LOCK;
}
/* CNR */
if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) {
ret = si2165_readreg24(state, REG_C_N, &u32tmp);
if (ret < 0)
return ret;
/*
* svalue =
* 1000 * c_n/dB =
* 1000 * 10 * log10(2^24 / regval) =
* 1000 * 10 * (log10(2^24) - log10(regval)) =
* 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24
*
* intlog10(x) = log10(x) * 2^24
* intlog10(2^24) = log10(2^24) * 2^24 = 121210686
*/
u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp)))
>> 24;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = u32tmp;
} else
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* BER */
if (*status & FE_HAS_VITERBI) {
if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
/* start new sampling period to get rid of old data*/
ret = si2165_writereg8(state, REG_BER_RST, 0x01);
if (ret < 0)
return ret;
/* set scale to enter read code on next call */
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = 0;
c->post_bit_count.stat[0].uvalue = 0;
/*
* reset DVBv3 value to deliver a good result
* for the first call
*/
state->ber_prev = 0;
} else {
ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);
if (ret < 0)
return ret;
if (u8tmp & 1) {
u32 biterrcnt;
ret = si2165_readreg24(state, REG_BER_BIT,
&biterrcnt);
if (ret < 0)
return ret;
c->post_bit_error.stat[0].uvalue +=
biterrcnt;
c->post_bit_count.stat[0].uvalue +=
STATISTICS_PERIOD_BIT_COUNT;
/* start new sampling period */
ret = si2165_writereg8(state,
REG_BER_RST, 0x01);
if (ret < 0)
return ret;
dev_dbg(&state->client->dev,
"post_bit_error=%u post_bit_count=%u\n",
biterrcnt, STATISTICS_PERIOD_BIT_COUNT);
}
}
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct si2165_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
*ber = 0;
return 0;
}
*ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
state->ber_prev = c->post_bit_error.stat[0].uvalue;
return 0;
}
static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)
{
u64 oversamp;
u32 reg_value;
if (!dvb_rate)
return -EINVAL;
oversamp = si2165_get_fe_clk(state);
oversamp <<= 23;
do_div(oversamp, dvb_rate);
reg_value = oversamp & 0x3fffffff;
dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);
return si2165_writereg32(state, REG_OVERSAMP, reg_value);
}
static int si2165_set_if_freq_shift(struct si2165_state *state)
{
struct dvb_frontend *fe = &state->fe;
u64 if_freq_shift;
s32 reg_value = 0;
u32 fe_clk = si2165_get_fe_clk(state);
u32 IF = 0;
if (!fe->ops.tuner_ops.get_if_frequency) {
dev_err(&state->client->dev,
"Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
return -EINVAL;
}
if (!fe_clk)
return -EINVAL;
fe->ops.tuner_ops.get_if_frequency(fe, &IF);
if_freq_shift = IF;
if_freq_shift <<= 29;
do_div(if_freq_shift, fe_clk);
reg_value = (s32)if_freq_shift;
if (state->config.inversion)
reg_value = -reg_value;
reg_value = reg_value & 0x1fffffff;
/* if_freq_shift, usbdump contained 0x023ee08f; */
return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);
}
static const struct si2165_reg_value_pair dvbt_regs[] = {
/* standard = DVB-T */
{ REG_DVB_STANDARD, 0x01 },
/* impulsive_noise_remover */
{ REG_IMPULSIVE_NOISE_REM, 0x01 },
{ REG_AUTO_RESET, 0x00 },
/* agc2 */
{ REG_AGC2_MIN, 0x41 },
{ REG_AGC2_KACQ, 0x0e },
{ REG_AGC2_KLOC, 0x10 },
/* agc */
{ REG_AGC_UNFREEZE_THR, 0x03 },
{ REG_AGC_CRESTF_DBX8, 0x78 },
/* agc */
{ REG_AAF_CRESTF_DBX8, 0x78 },
{ REG_ACI_CRESTF_DBX8, 0x68 },
/* freq_sync_range */
REG16(REG_FREQ_SYNC_RANGE, 0x0064),
/* gp_reg0 */
{ REG_GP_REG0_MSB, 0x00 }
};
static int si2165_set_frontend_dvbt(struct dvb_frontend *fe)
{
int ret;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct si2165_state *state = fe->demodulator_priv;
u32 dvb_rate = 0;
u16 bw10k;
u32 bw_hz = p->bandwidth_hz;
dev_dbg(&state->client->dev, "%s: called\n", __func__);
if (!state->has_dvbt)
return -EINVAL;
/* no bandwidth auto-detection */
if (bw_hz == 0)
return -EINVAL;
dvb_rate = bw_hz * 8 / 7;
bw10k = bw_hz / 10000;
ret = si2165_adjust_pll_divl(state, 12);
if (ret < 0)
return ret;
/* bandwidth in 10KHz steps */
ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);
if (ret < 0)
return ret;
ret = si2165_set_oversamp(state, dvb_rate);
if (ret < 0)
return ret;
ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
if (ret < 0)
return ret;
return 0;
}
static const struct si2165_reg_value_pair dvbc_regs[] = {
/* standard = DVB-C */
{ REG_DVB_STANDARD, 0x05 },
/* agc2 */
{ REG_AGC2_MIN, 0x50 },
{ REG_AGC2_KACQ, 0x0e },
{ REG_AGC2_KLOC, 0x10 },
/* agc */
{ REG_AGC_UNFREEZE_THR, 0x03 },
{ REG_AGC_CRESTF_DBX8, 0x68 },
/* agc */
{ REG_AAF_CRESTF_DBX8, 0x68 },
{ REG_ACI_CRESTF_DBX8, 0x50 },
{ REG_EQ_AUTO_CONTROL, 0x0d },
{ REG_KP_LOCK, 0x05 },
{ REG_CENTRAL_TAP, 0x09 },
REG16(REG_UNKNOWN_350, 0x3e80),
{ REG_AUTO_RESET, 0x01 },
REG16(REG_UNKNOWN_24C, 0x0000),
REG16(REG_UNKNOWN_27C, 0x0000),
{ REG_SWEEP_STEP, 0x03 },
{ REG_AGC_IF_TRI, 0x00 },
};
static int si2165_set_frontend_dvbc(struct dvb_frontend *fe)
{
struct si2165_state *state = fe->demodulator_priv;
int ret;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
const u32 dvb_rate = p->symbol_rate;
u8 u8tmp;
if (!state->has_dvbc)
return -EINVAL;
if (dvb_rate == 0)
return -EINVAL;
ret = si2165_adjust_pll_divl(state, 14);
if (ret < 0)
return ret;
/* Oversampling */
ret = si2165_set_oversamp(state, dvb_rate);
if (ret < 0)
return ret;
switch (p->modulation) {
case QPSK:
u8tmp = 0x3;
break;
case QAM_16:
u8tmp = 0x7;
break;
case QAM_32:
u8tmp = 0x8;
break;
case QAM_64:
u8tmp = 0x9;
break;
case QAM_128:
u8tmp = 0xa;
break;
case QAM_256:
default:
u8tmp = 0xb;
break;
}
ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
if (ret < 0)
return ret;
ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);
if (ret < 0)
return ret;
ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
if (ret < 0)
return ret;
return 0;
}
static const struct si2165_reg_value_pair adc_rewrite[] = {
{ REG_ADC_RI1, 0x46 },
{ REG_ADC_RI3, 0x00 },
{ REG_ADC_RI5, 0x0a },
{ REG_ADC_RI6, 0xff },
{ REG_ADC_RI8, 0x70 }
};
static int si2165_set_frontend(struct dvb_frontend *fe)
{
struct si2165_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 delsys = p->delivery_system;
int ret;
u8 val[3];
/* initial setting of if freq shift */
ret = si2165_set_if_freq_shift(state);
if (ret < 0)
return ret;
switch (delsys) {
case SYS_DVBT:
ret = si2165_set_frontend_dvbt(fe);
if (ret < 0)
return ret;
break;
case SYS_DVBC_ANNEX_A:
ret = si2165_set_frontend_dvbc(fe);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
/* dsp_addr_jump */
ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
if (ret < 0)
return ret;
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* recalc if_freq_shift if IF might has changed */
ret = si2165_set_if_freq_shift(state);
if (ret < 0)
return ret;
/* boot/wdog status */
ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
if (ret < 0)
return ret;
ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
if (ret < 0)
return ret;
/* reset all */
ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
if (ret < 0)
return ret;
/* gp_reg0 */
ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);
if (ret < 0)
return ret;
/* write adc values after each reset*/
ret = si2165_write_reg_list(state, adc_rewrite,
ARRAY_SIZE(adc_rewrite));
if (ret < 0)
return ret;
/* start_synchro */
ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
if (ret < 0)
return ret;
/* boot/wdog status */
ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
if (ret < 0)
return ret;
return 0;
}
static const struct dvb_frontend_ops si2165_ops = {
.info = {
.name = "Silicon Labs ",
/* For DVB-C */
.symbol_rate_min = 1000000,
.symbol_rate_max = 7200000,
/* For DVB-T */
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_RECOVER
},
.get_tune_settings = si2165_get_tune_settings,
.init = si2165_init,
.sleep = si2165_sleep,
.set_frontend = si2165_set_frontend,
.read_status = si2165_read_status,
.read_snr = si2165_read_snr,
.read_ber = si2165_read_ber,
};
static int si2165_probe(struct i2c_client *client)
{
struct si2165_state *state = NULL;
struct si2165_platform_data *pdata = client->dev.platform_data;
int n;
int ret = 0;
u8 val;
char rev_char;
const char *chip_name;
static const struct regmap_config regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0x08ff,
};
/* allocate memory for the internal state */
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state) {
ret = -ENOMEM;
goto error;
}
/* create regmap */
state->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(state->regmap)) {
ret = PTR_ERR(state->regmap);
goto error;
}
/* setup the state */
state->client = client;
state->config.i2c_addr = client->addr;
state->config.chip_mode = pdata->chip_mode;
state->config.ref_freq_hz = pdata->ref_freq_hz;
state->config.inversion = pdata->inversion;
if (state->config.ref_freq_hz < 4000000 ||
state->config.ref_freq_hz > 27000000) {
dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n",
state->config.ref_freq_hz);
ret = -EINVAL;
goto error;
}
/* create dvb_frontend */
memcpy(&state->fe.ops, &si2165_ops,
sizeof(struct dvb_frontend_ops));
state->fe.ops.release = NULL;
state->fe.demodulator_priv = state;
i2c_set_clientdata(client, state);
/* powerup */
ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
if (ret < 0)
goto nodev_error;
ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
if (ret < 0)
goto nodev_error;
if (val != state->config.chip_mode)
goto nodev_error;
ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);
if (ret < 0)
goto nodev_error;
ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);
if (ret < 0)
goto nodev_error;
/* powerdown */
ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
if (ret < 0)
goto nodev_error;
if (state->chip_revcode < 26)
rev_char = 'A' + state->chip_revcode;
else
rev_char = '?';
switch (state->chip_type) {
case 0x06:
chip_name = "Si2161";
state->has_dvbt = true;
break;
case 0x07:
chip_name = "Si2165";
state->has_dvbt = true;
state->has_dvbc = true;
break;
default:
dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n",
state->chip_type, state->chip_revcode);
goto nodev_error;
}
dev_info(&state->client->dev,
"Detected Silicon Labs %s-%c (type %d, rev %d)\n",
chip_name, rev_char, state->chip_type,
state->chip_revcode);
strlcat(state->fe.ops.info.name, chip_name,
sizeof(state->fe.ops.info.name));
n = 0;
if (state->has_dvbt) {
state->fe.ops.delsys[n++] = SYS_DVBT;
strlcat(state->fe.ops.info.name, " DVB-T",
sizeof(state->fe.ops.info.name));
}
if (state->has_dvbc) {
state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
strlcat(state->fe.ops.info.name, " DVB-C",
sizeof(state->fe.ops.info.name));
}
/* return fe pointer */
*pdata->fe = &state->fe;
return 0;
nodev_error:
ret = -ENODEV;
error:
kfree(state);
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void si2165_remove(struct i2c_client *client)
{
struct si2165_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
kfree(state);
}
static const struct i2c_device_id si2165_id_table[] = {
{"si2165", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, si2165_id_table);
static struct i2c_driver si2165_driver = {
.driver = {
.name = "si2165",
},
.probe = si2165_probe,
.remove = si2165_remove,
.id_table = si2165_id_table,
};
module_i2c_driver(si2165_driver);
MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver");
MODULE_AUTHOR("Matthias Schwarzott <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D);
| linux-master | drivers/media/dvb-frontends/si2165.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
cx24110 - Single Chip Satellite Channel Receiver driver module
Copyright (C) 2002 Peter Hettkamp <[email protected]> based on
work
Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]>
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <media/dvb_frontend.h>
#include "cx24110.h"
struct cx24110_state {
struct i2c_adapter* i2c;
const struct cx24110_config* config;
struct dvb_frontend frontend;
u32 lastber;
u32 lastbler;
u32 lastesn0;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "cx24110: " args); \
} while (0)
static struct {u8 reg; u8 data;} cx24110_regdata[]=
/* Comments beginning with @ denote this value should
be the default */
{{0x09,0x01}, /* SoftResetAll */
{0x09,0x00}, /* release reset */
{0x01,0xe8}, /* MSB of code rate 27.5MS/s */
{0x02,0x17}, /* middle byte " */
{0x03,0x29}, /* LSB " */
{0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
{0x06,0xa5}, /* @ PLL 60MHz */
{0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
{0x0a,0x00}, /* @ partial chip disables, do not set */
{0x0b,0x01}, /* set output clock in gapped mode, start signal low
active for first byte */
{0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
{0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
{0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
to avoid starting the BER counter. Reset the
CRC test bit. Finite counting selected */
{0x15,0xff}, /* @ size of the limited time window for RS BER
estimation. It is <value>*256 RS blocks, this
gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
{0x16,0x00}, /* @ enable all RS output ports */
{0x17,0x04}, /* @ time window allowed for the RS to sync */
{0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
for automatically */
/* leave the current code rate and normalization
registers as they are after reset... */
{0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
only once */
{0x23,0x18}, /* @ size of the limited time window for Viterbi BER
estimation. It is <value>*65536 channel bits, i.e.
approx. 38ms at 27.5MS/s, rate 3/4 */
{0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
/* leave front-end AGC parameters at default values */
/* leave decimation AGC parameters at default values */
{0x35,0x40}, /* disable all interrupts. They are not connected anyway */
{0x36,0xff}, /* clear all interrupt pending flags */
{0x37,0x00}, /* @ fully enable AutoAcqq state machine */
{0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
/* leave the equalizer parameters on their default values */
/* leave the final AGC parameters on their default values */
{0x41,0x00}, /* @ MSB of front-end derotator frequency */
{0x42,0x00}, /* @ middle bytes " */
{0x43,0x00}, /* @ LSB " */
/* leave the carrier tracking loop parameters on default */
/* leave the bit timing loop parameters at default */
{0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
/* the cx24108 data sheet for symbol rates above 15MS/s */
{0x57,0x00}, /* @ Filter sigma delta enabled, positive */
{0x61,0x95}, /* GPIO pins 1-4 have special function */
{0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
{0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
{0x64,0x20}, /* GPIO 6 is input, all others are outputs */
{0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
{0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
{0x73,0x00}, /* @ disable several demod bypasses */
{0x74,0x00}, /* @ " */
{0x75,0x00} /* @ " */
/* the remaining registers are for SEC */
};
static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
{
u8 buf [] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int err;
if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n",
__func__, err, reg, data);
return -EREMOTEIO;
}
return 0;
}
static int cx24110_readreg (struct cx24110_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) return ret;
return b1[0];
}
static int cx24110_set_inversion(struct cx24110_state *state,
enum fe_spectral_inversion inversion)
{
/* fixme (low): error handling */
switch (inversion) {
case INVERSION_OFF:
cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
/* AcqSpectrInvDis on. No idea why someone should want this */
cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
/* Initial value 0 at start of acq */
cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
/* current value 0 */
/* The cx24110 manual tells us this reg is read-only.
But what the heck... set it ayways */
break;
case INVERSION_ON:
cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
/* AcqSpectrInvDis on. No idea why someone should want this */
cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
/* Initial value 1 at start of acq */
cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
/* current value 1 */
break;
case INVERSION_AUTO:
cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
/* AcqSpectrInvDis off. Leave initial & current states as is */
break;
default:
return -EINVAL;
}
return 0;
}
static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)
{
static const int rate[FEC_AUTO] = {-1, 1, 2, 3, 5, 7, -1};
static const int g1[FEC_AUTO] = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};
static const int g2[FEC_AUTO] = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};
/* Well, the AutoAcq engine of the cx24106 and 24110 automatically
searches all enabled viterbi rates, and can handle non-standard
rates as well. */
if (fec > FEC_AUTO)
fec = FEC_AUTO;
if (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);
/* clear AcqVitDis bit */
cx24110_writereg(state, 0x18, 0xae);
/* allow all DVB standard code rates */
cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);
/* set nominal Viterbi rate 3/4 */
cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);
/* set current Viterbi rate 3/4 */
cx24110_writereg(state, 0x1a, 0x05);
cx24110_writereg(state, 0x1b, 0x06);
/* set the puncture registers for code rate 3/4 */
return 0;
} else {
cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);
/* set AcqVitDis bit */
if (rate[fec] < 0)
return -EINVAL;
cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);
/* set nominal Viterbi rate */
cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);
/* set current Viterbi rate */
cx24110_writereg(state, 0x1a, g1[fec]);
cx24110_writereg(state, 0x1b, g2[fec]);
/* not sure if this is the right way: I always used AutoAcq mode */
}
return 0;
}
static enum fe_code_rate cx24110_get_fec(struct cx24110_state *state)
{
int i;
i=cx24110_readreg(state,0x22)&0x0f;
if(!(i&0x08)) {
return FEC_1_2 + i - 1;
} else {
/* fixme (low): a special code rate has been selected. In theory, we need to
return a denominator value, a numerator value, and a pair of puncture
maps to correctly describe this mode. But this should never happen in
practice, because it cannot be set by cx24110_get_fec. */
return FEC_NONE;
}
}
static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
{
/* fixme (low): add error handling */
u32 ratio;
u32 tmp, fclk, BDRI;
static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
int i;
dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
if (srate>90999000UL/2)
srate=90999000UL/2;
if (srate<500000)
srate=500000;
for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
;
/* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
R06[3:0] PLLphaseDetGain */
tmp=cx24110_readreg(state,0x07)&0xfc;
if(srate<90999000UL/4) { /* sample rate 45MHz*/
cx24110_writereg(state,0x07,tmp);
cx24110_writereg(state,0x06,0x78);
fclk=90999000UL/2;
} else if(srate<60666000UL/2) { /* sample rate 60MHz */
cx24110_writereg(state,0x07,tmp|0x1);
cx24110_writereg(state,0x06,0xa5);
fclk=60666000UL;
} else if(srate<80888000UL/2) { /* sample rate 80MHz */
cx24110_writereg(state,0x07,tmp|0x2);
cx24110_writereg(state,0x06,0x87);
fclk=80888000UL;
} else { /* sample rate 90MHz */
cx24110_writereg(state,0x07,tmp|0x3);
cx24110_writereg(state,0x06,0x78);
fclk=90999000UL;
}
dprintk("cx24110 debug: fclk %d Hz\n",fclk);
/* we need to divide two integers with approx. 27 bits in 32 bit
arithmetic giving a 25 bit result */
/* the maximum dividend is 90999000/2, 0x02b6446c, this number is
also the most complex divisor. Hence, the dividend has,
assuming 32bit unsigned arithmetic, 6 clear bits on top, the
divisor 2 unused bits at the bottom. Also, the quotient is
always less than 1/2. Borrowed from VES1893.c, of course */
tmp=srate<<6;
BDRI=fclk>>2;
ratio=(tmp/BDRI);
tmp=(tmp%BDRI)<<8;
ratio=(ratio<<8)+(tmp/BDRI);
tmp=(tmp%BDRI)<<8;
ratio=(ratio<<8)+(tmp/BDRI);
tmp=(tmp%BDRI)<<1;
ratio=(ratio<<1)+(tmp/BDRI);
dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
dprintk("fclk = %d\n", fclk);
dprintk("ratio= %08x\n", ratio);
cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
cx24110_writereg(state, 0x3, (ratio)&0xff);
return 0;
}
static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
{
struct cx24110_state *state = fe->demodulator_priv;
if (len != 3)
return -EINVAL;
/* tuner data is 21 bits long, must be left-aligned in data */
/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
/* FIXME (low): add error handling, avoid infinite loops if HW fails... */
cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
/* if the auto tuner writer is still busy, clear it out */
while (cx24110_readreg(state,0x6d)&0x80)
cx24110_writereg(state,0x72,0);
/* write the topmost 8 bits */
cx24110_writereg(state,0x72,buf[0]);
/* wait for the send to be completed */
while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
;
/* send another 8 bytes */
cx24110_writereg(state,0x72,buf[1]);
while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
;
/* and the topmost 5 bits of this byte */
cx24110_writereg(state,0x72,buf[2]);
while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
;
/* now strobe the enable line once */
cx24110_writereg(state,0x6d,0x32);
cx24110_writereg(state,0x6d,0x30);
return 0;
}
static int cx24110_initfe(struct dvb_frontend* fe)
{
struct cx24110_state *state = fe->demodulator_priv;
/* fixme (low): error handling */
int i;
dprintk("%s: init chip\n", __func__);
for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
}
return 0;
}
static int cx24110_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx24110_state *state = fe->demodulator_priv;
switch (voltage) {
case SEC_VOLTAGE_13:
return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
case SEC_VOLTAGE_18:
return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
default:
return -EINVAL;
}
}
static int cx24110_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
int rv, bit;
struct cx24110_state *state = fe->demodulator_priv;
unsigned long timeout;
if (burst == SEC_MINI_A)
bit = 0x00;
else if (burst == SEC_MINI_B)
bit = 0x08;
else
return -EINVAL;
rv = cx24110_readreg(state, 0x77);
if (!(rv & 0x04))
cx24110_writereg(state, 0x77, rv | 0x04);
rv = cx24110_readreg(state, 0x76);
cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
timeout = jiffies + msecs_to_jiffies(100);
while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
; /* wait for LNB ready */
return 0;
}
static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd *cmd)
{
int i, rv;
struct cx24110_state *state = fe->demodulator_priv;
unsigned long timeout;
if (cmd->msg_len < 3 || cmd->msg_len > 6)
return -EINVAL; /* not implemented */
for (i = 0; i < cmd->msg_len; i++)
cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
rv = cx24110_readreg(state, 0x77);
if (rv & 0x04) {
cx24110_writereg(state, 0x77, rv & ~0x04);
msleep(30); /* reportedly fixes switching problems */
}
rv = cx24110_readreg(state, 0x76);
cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
timeout = jiffies + msecs_to_jiffies(100);
while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
; /* wait for LNB ready */
return 0;
}
static int cx24110_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct cx24110_state *state = fe->demodulator_priv;
int sync = cx24110_readreg (state, 0x55);
*status = 0;
if (sync & 0x10)
*status |= FE_HAS_SIGNAL;
if (sync & 0x08)
*status |= FE_HAS_CARRIER;
sync = cx24110_readreg (state, 0x08);
if (sync & 0x40)
*status |= FE_HAS_VITERBI;
if (sync & 0x20)
*status |= FE_HAS_SYNC;
if ((sync & 0x60) == 0x60)
*status |= FE_HAS_LOCK;
return 0;
}
static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct cx24110_state *state = fe->demodulator_priv;
/* fixme (maybe): value range is 16 bit. Scale? */
if(cx24110_readreg(state,0x24)&0x10) {
/* the Viterbi error counter has finished one counting window */
cx24110_writereg(state,0x24,0x04); /* select the ber reg */
state->lastber=cx24110_readreg(state,0x25)|
(cx24110_readreg(state,0x26)<<8);
cx24110_writereg(state,0x24,0x04); /* start new count window */
cx24110_writereg(state,0x24,0x14);
}
*ber = state->lastber;
return 0;
}
static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
struct cx24110_state *state = fe->demodulator_priv;
/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
u8 signal = cx24110_readreg (state, 0x27)+128;
*signal_strength = (signal << 8) | signal;
return 0;
}
static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct cx24110_state *state = fe->demodulator_priv;
/* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
if(cx24110_readreg(state,0x6a)&0x80) {
/* the Es/N0 error counter has finished one counting window */
state->lastesn0=cx24110_readreg(state,0x69)|
(cx24110_readreg(state,0x68)<<8);
cx24110_writereg(state,0x6a,0x84); /* start new count window */
}
*snr = state->lastesn0;
return 0;
}
static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct cx24110_state *state = fe->demodulator_priv;
if(cx24110_readreg(state,0x10)&0x40) {
/* the RS error counter has finished one counting window */
cx24110_writereg(state,0x10,0x60); /* select the byer reg */
(void)(cx24110_readreg(state, 0x12) |
(cx24110_readreg(state, 0x13) << 8) |
(cx24110_readreg(state, 0x14) << 16));
cx24110_writereg(state,0x10,0x70); /* select the bler reg */
state->lastbler=cx24110_readreg(state,0x12)|
(cx24110_readreg(state,0x13)<<8)|
(cx24110_readreg(state,0x14)<<16);
cx24110_writereg(state,0x10,0x20); /* start new count window */
}
*ucblocks = state->lastbler;
return 0;
}
static int cx24110_set_frontend(struct dvb_frontend *fe)
{
struct cx24110_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
cx24110_set_inversion(state, p->inversion);
cx24110_set_fec(state, p->fec_inner);
cx24110_set_symbolrate(state, p->symbol_rate);
cx24110_writereg(state,0x04,0x05); /* start acquisition */
return 0;
}
static int cx24110_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct cx24110_state *state = fe->demodulator_priv;
s32 afc; unsigned sclk;
/* cannot read back tuner settings (freq). Need to have some private storage */
sclk = cx24110_readreg (state, 0x07) & 0x03;
/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
* Need 64 bit arithmetic. Is thiss possible in the kernel? */
if (sclk==0) sclk=90999000L/2L;
else if (sclk==1) sclk=60666000L;
else if (sclk==2) sclk=80888000L;
else sclk=90999000L;
sclk>>=8;
afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
((sclk*cx24110_readreg (state, 0x45))>>8)+
((sclk*cx24110_readreg (state, 0x46))>>16);
p->frequency += afc;
p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
INVERSION_ON : INVERSION_OFF;
p->fec_inner = cx24110_get_fec(state);
return 0;
}
static int cx24110_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct cx24110_state *state = fe->demodulator_priv;
return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
}
static void cx24110_release(struct dvb_frontend* fe)
{
struct cx24110_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops cx24110_ops;
struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
struct i2c_adapter* i2c)
{
struct cx24110_state* state = NULL;
int ret;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->lastber = 0;
state->lastbler = 0;
state->lastesn0 = 0;
/* check if the demod is there */
ret = cx24110_readreg(state, 0x00);
if ((ret != 0x5a) && (ret != 0x69)) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops cx24110_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Conexant CX24110 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 29500 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = cx24110_release,
.init = cx24110_initfe,
.write = _cx24110_pll_write,
.set_frontend = cx24110_set_frontend,
.get_frontend = cx24110_get_frontend,
.read_status = cx24110_read_status,
.read_ber = cx24110_read_ber,
.read_signal_strength = cx24110_read_signal_strength,
.read_snr = cx24110_read_snr,
.read_ucblocks = cx24110_read_ucblocks,
.diseqc_send_master_cmd = cx24110_send_diseqc_msg,
.set_tone = cx24110_set_tone,
.set_voltage = cx24110_set_voltage,
.diseqc_send_burst = cx24110_diseqc_send_burst,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
MODULE_AUTHOR("Peter Hettkamp");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(cx24110_attach);
| linux-master | drivers/media/dvb-frontends/cx24110.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* stv0900_core.c
*
* Driver for ST STV0900 satellite demodulator IC.
*
* Copyright (C) ST Microelectronics.
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include "stv0900.h"
#include "stv0900_reg.h"
#include "stv0900_priv.h"
#include "stv0900_init.h"
int stvdebug = 1;
module_param_named(debug, stvdebug, int, 0644);
/* internal params node */
struct stv0900_inode {
/* pointer for internal params, one for each pair of demods */
struct stv0900_internal *internal;
struct stv0900_inode *next_inode;
};
/* first internal params */
static struct stv0900_inode *stv0900_first_inode;
/* find chip by i2c adapter and i2c address */
static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
u8 i2c_addr)
{
struct stv0900_inode *temp_chip = stv0900_first_inode;
if (temp_chip != NULL) {
/*
Search of the last stv0900 chip or
find it by i2c adapter and i2c address */
while ((temp_chip != NULL) &&
((temp_chip->internal->i2c_adap != i2c_adap) ||
(temp_chip->internal->i2c_addr != i2c_addr)))
temp_chip = temp_chip->next_inode;
}
return temp_chip;
}
/* deallocating chip */
static void remove_inode(struct stv0900_internal *internal)
{
struct stv0900_inode *prev_node = stv0900_first_inode;
struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
internal->i2c_addr);
if (del_node != NULL) {
if (del_node == stv0900_first_inode) {
stv0900_first_inode = del_node->next_inode;
} else {
while (prev_node->next_inode != del_node)
prev_node = prev_node->next_inode;
if (del_node->next_inode == NULL)
prev_node->next_inode = NULL;
else
prev_node->next_inode =
prev_node->next_inode->next_inode;
}
kfree(del_node);
}
}
/* allocating new chip */
static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
{
struct stv0900_inode *new_node = stv0900_first_inode;
if (new_node == NULL) {
new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
stv0900_first_inode = new_node;
} else {
while (new_node->next_inode != NULL)
new_node = new_node->next_inode;
new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
GFP_KERNEL);
if (new_node->next_inode != NULL)
new_node = new_node->next_inode;
else
new_node = NULL;
}
if (new_node != NULL) {
new_node->internal = internal;
new_node->next_inode = NULL;
}
return new_node;
}
s32 ge2comp(s32 a, s32 width)
{
if (width == 32)
return a;
else
return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
}
void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
u8 reg_data)
{
u8 data[3];
int ret;
struct i2c_msg i2cmsg = {
.addr = intp->i2c_addr,
.flags = 0,
.len = 3,
.buf = data,
};
data[0] = MSB(reg_addr);
data[1] = LSB(reg_addr);
data[2] = reg_data;
ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
if (ret != 1)
dprintk("%s: i2c error %d\n", __func__, ret);
}
u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
{
int ret;
u8 b0[] = { MSB(reg), LSB(reg) };
u8 buf = 0;
struct i2c_msg msg[] = {
{
.addr = intp->i2c_addr,
.flags = 0,
.buf = b0,
.len = 2,
}, {
.addr = intp->i2c_addr,
.flags = I2C_M_RD,
.buf = &buf,
.len = 1,
},
};
ret = i2c_transfer(intp->i2c_adap, msg, 2);
if (ret != 2)
dprintk("%s: i2c error %d, reg[0x%02x]\n",
__func__, ret, reg);
return buf;
}
static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
{
u8 position = 0, i = 0;
(*mask) = label & 0xff;
while ((position == 0) && (i < 8)) {
position = ((*mask) >> i) & 0x01;
i++;
}
(*pos) = (i - 1);
}
void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
{
u8 reg, mask, pos;
reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
extract_mask_pos(label, &mask, &pos);
val = mask & (val << pos);
reg = (reg & (~mask)) | val;
stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
}
u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
{
u8 val;
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
val = stv0900_read_reg(intp, label >> 16);
val = (val & mask) >> pos;
return val;
}
static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
{
s32 i;
if (intp == NULL)
return STV0900_INVALID_HANDLE;
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
if (intp->errs != STV0900_NO_ERROR)
return intp->errs;
/*Startup sequence*/
stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
msleep(3);
stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
msleep(3);
stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
switch (intp->clkmode) {
case 0:
case 2:
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
| intp->clkmode);
break;
default:
/* preserve SELOSCI bit */
i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
break;
}
msleep(3);
for (i = 0; i < 181; i++)
stv0900_write_reg(intp, STV0900_InitVal[i][0],
STV0900_InitVal[i][1]);
if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
for (i = 0; i < 32; i++)
stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
STV0900_Cut20_AddOnVal[i][1]);
}
stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
return STV0900_NO_ERROR;
}
static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
{
u32 mclk, div, ad_div;
div = stv0900_get_bits(intp, F0900_M_DIV);
ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
mclk = (div + 1) * ext_clk / ad_div;
dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
return mclk;
}
static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
{
u32 m_div, clk_sel;
if (intp == NULL)
return STV0900_INVALID_HANDLE;
if (intp->errs)
return STV0900_I2C_ERROR;
dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
intp->quartz);
clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
m_div = ((clk_sel * mclk) / intp->quartz) - 1;
stv0900_write_bits(intp, F0900_M_DIV, m_div);
intp->mclk = stv0900_get_mclk_freq(intp,
intp->quartz);
/*Set the DiseqC frequency to 22KHz */
/*
Formula:
DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
*/
m_div = intp->mclk / 704000;
stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
if ((intp->errs))
return STV0900_I2C_ERROR;
return STV0900_NO_ERROR;
}
static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
enum fe_stv0900_demod_num demod)
{
u32 lsb, msb, hsb, err_val;
switch (cntr) {
case 0:
default:
hsb = stv0900_get_bits(intp, ERR_CNT12);
msb = stv0900_get_bits(intp, ERR_CNT11);
lsb = stv0900_get_bits(intp, ERR_CNT10);
break;
case 1:
hsb = stv0900_get_bits(intp, ERR_CNT22);
msb = stv0900_get_bits(intp, ERR_CNT21);
lsb = stv0900_get_bits(intp, ERR_CNT20);
break;
}
err_val = (hsb << 16) + (msb << 8) + (lsb);
return err_val;
}
static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
stv0900_write_bits(intp, I2CT_ON, enable);
return 0;
}
static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
enum fe_stv0900_clock_type path1_ts,
enum fe_stv0900_clock_type path2_ts)
{
dprintk("%s\n", __func__);
if (intp->chip_id >= 0x20) {
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
switch (path2_ts) {
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(intp, R0900_TSGENERAL,
0x00);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(intp, R0900_TSGENERAL,
0x06);
stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
stv0900_write_reg(intp,
R0900_P1_TSSPEED, 0x14);
stv0900_write_reg(intp,
R0900_P2_TSSPEED, 0x28);
break;
}
break;
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
switch (path2_ts) {
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0C);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0A);
dprintk("%s: 0x0a\n", __func__);
break;
}
break;
}
} else {
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
switch (path2_ts) {
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x10);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x16);
stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
stv0900_write_reg(intp, R0900_P1_TSSPEED,
0x14);
stv0900_write_reg(intp, R0900_P2_TSSPEED,
0x28);
break;
}
break;
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
switch (path2_ts) {
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x14);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x12);
dprintk("%s: 0x12\n", __func__);
break;
}
break;
}
}
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
default:
break;
}
switch (path2_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
default:
break;
}
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
}
void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
u32 bandwidth)
{
struct dvb_frontend_ops *frontend_ops = NULL;
struct dvb_tuner_ops *tuner_ops = NULL;
frontend_ops = &fe->ops;
tuner_ops = &frontend_ops->tuner_ops;
if (tuner_ops->set_frequency) {
if ((tuner_ops->set_frequency(fe, frequency)) < 0)
dprintk("%s: Invalid parameter\n", __func__);
else
dprintk("%s: Frequency=%d\n", __func__, frequency);
}
if (tuner_ops->set_bandwidth) {
if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
dprintk("%s: Invalid parameter\n", __func__);
else
dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
}
}
void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
{
struct dvb_frontend_ops *frontend_ops = NULL;
struct dvb_tuner_ops *tuner_ops = NULL;
frontend_ops = &fe->ops;
tuner_ops = &frontend_ops->tuner_ops;
if (tuner_ops->set_bandwidth) {
if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
dprintk("%s: Invalid parameter\n", __func__);
else
dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
}
}
u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
{
u32 freq, round;
/* Formulat :
Tuner_Frequency(MHz) = Regs / 64
Tuner_granularity(MHz) = Regs / 2048
real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz)
*/
freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
(stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
stv0900_get_bits(intp, TUN_RFFREQ0);
freq = (freq * 1000) / 64;
round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
stv0900_get_bits(intp, TUN_RFRESTE0);
round = (round * 1000) / 2048;
return freq + round;
}
void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
u32 Bandwidth, int demod)
{
u32 tunerFrequency;
/* Formulat:
Tuner_frequency_reg= Frequency(MHz)*64
*/
tunerFrequency = (Frequency * 64) / 1000;
stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
/* Low Pass Filter = BW /2 (MHz)*/
stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
/* Tuner Write trig */
stv0900_write_reg(intp, TNRLD, 1);
}
static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
const struct stv0900_table *lookup,
enum fe_stv0900_demod_num demod)
{
s32 agc_gain = 0,
imin,
imax,
i,
rf_lvl = 0;
dprintk("%s\n", __func__);
if ((lookup == NULL) || (lookup->size <= 0))
return 0;
agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
stv0900_get_bits(intp, AGCIQ_VALUE0));
imin = 0;
imax = lookup->size - 1;
if (INRANGE(lookup->table[imin].regval, agc_gain,
lookup->table[imax].regval)) {
while ((imax - imin) > 1) {
i = (imax + imin) >> 1;
if (INRANGE(lookup->table[imin].regval,
agc_gain,
lookup->table[i].regval))
imax = i;
else
imin = i;
}
rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
rf_lvl *= (lookup->table[imax].realval -
lookup->table[imin].realval);
rf_lvl /= (lookup->table[imax].regval -
lookup->table[imin].regval);
rf_lvl += lookup->table[imin].realval;
} else if (agc_gain > lookup->table[0].regval)
rf_lvl = 5;
else if (agc_gain < lookup->table[lookup->size-1].regval)
rf_lvl = -100;
dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
return rf_lvl;
}
static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *internal = state->internal;
s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
state->demod);
rflevel = (rflevel + 100) * (65535 / 70);
if (rflevel < 0)
rflevel = 0;
if (rflevel > 65535)
rflevel = 65535;
*strength = rflevel;
return 0;
}
static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
const struct stv0900_table *lookup)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 c_n = -100,
regval,
imin,
imax,
i,
noise_field1,
noise_field0;
dprintk("%s\n", __func__);
if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
noise_field1 = NOSPLHT_NORMED1;
noise_field0 = NOSPLHT_NORMED0;
} else {
noise_field1 = NOSDATAT_NORMED1;
noise_field0 = NOSDATAT_NORMED0;
}
if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
if ((lookup != NULL) && lookup->size) {
regval = 0;
msleep(5);
for (i = 0; i < 16; i++) {
regval += MAKEWORD(stv0900_get_bits(intp,
noise_field1),
stv0900_get_bits(intp,
noise_field0));
msleep(1);
}
regval /= 16;
imin = 0;
imax = lookup->size - 1;
if (INRANGE(lookup->table[imin].regval,
regval,
lookup->table[imax].regval)) {
while ((imax - imin) > 1) {
i = (imax + imin) >> 1;
if (INRANGE(lookup->table[imin].regval,
regval,
lookup->table[i].regval))
imax = i;
else
imin = i;
}
c_n = ((regval - lookup->table[imin].regval)
* (lookup->table[imax].realval
- lookup->table[imin].realval)
/ (lookup->table[imax].regval
- lookup->table[imin].regval))
+ lookup->table[imin].realval;
} else if (regval < lookup->table[imin].regval)
c_n = 1000;
}
}
return c_n;
}
static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u8 err_val1, err_val0;
u32 header_err_val = 0;
*ucblocks = 0x0;
if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
/* DVB-S2 delineator errors count */
/* retrieving number for errnous headers */
err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
header_err_val = (err_val1 << 8) | err_val0;
/* retrieving number for errnous packets */
err_val1 = stv0900_read_reg(intp, UPCRCKO1);
err_val0 = stv0900_read_reg(intp, UPCRCKO0);
*ucblocks = (err_val1 << 8) | err_val0;
*ucblocks += header_err_val;
}
return 0;
}
static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
{
s32 snrlcl = stv0900_carr_get_quality(fe,
(const struct stv0900_table *)&stv0900_s2_cn);
snrlcl = (snrlcl + 30) * 384;
if (snrlcl < 0)
snrlcl = 0;
if (snrlcl > 65535)
snrlcl = 65535;
*snr = snrlcl;
return 0;
}
static u32 stv0900_get_ber(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 ber = 10000000, i;
s32 demod_state;
demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
default:
ber = 10000000;
break;
case STV0900_DVBS_FOUND:
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
if (stv0900_get_bits(intp, PRFVIT)) {
ber *= 9766;
ber = ber >> 13;
}
break;
case STV0900_DVBS2_FOUND:
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
ber *= 9766;
ber = ber >> 13;
}
break;
}
return ber;
}
static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *internal = state->internal;
*ber = stv0900_get_ber(internal, state->demod);
return 0;
}
int stv0900_get_demod_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod, s32 time_out)
{
s32 timer = 0,
lock = 0;
enum fe_stv0900_search_state dmd_state;
while ((timer < time_out) && (lock == 0)) {
dmd_state = stv0900_get_bits(intp, HEADER_MODE);
dprintk("Demod State = %d\n", dmd_state);
switch (dmd_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
default:
lock = 0;
break;
case STV0900_DVBS2_FOUND:
case STV0900_DVBS_FOUND:
lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
break;
}
if (lock == 0)
msleep(10);
timer += 10;
}
if (lock)
dprintk("DEMOD LOCK OK\n");
else
dprintk("DEMOD LOCK FAIL\n");
return lock;
}
void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 regflist,
i;
dprintk("%s\n", __func__);
regflist = MODCODLST0;
for (i = 0; i < 16; i++)
stv0900_write_reg(intp, regflist + i, 0xff);
}
void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 matype,
mod_code,
fmod,
reg_index,
field_index;
dprintk("%s\n", __func__);
if (intp->chip_id <= 0x11) {
msleep(5);
mod_code = stv0900_read_reg(intp, PLHMODCOD);
matype = mod_code & 0x3;
mod_code = (mod_code & 0x7f) >> 2;
reg_index = MODCODLSTF - mod_code / 2;
field_index = mod_code % 2;
switch (matype) {
case 0:
default:
fmod = 14;
break;
case 1:
fmod = 13;
break;
case 2:
fmod = 11;
break;
case 3:
fmod = 7;
break;
}
if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
&& (matype <= 1)) {
if (field_index == 0)
stv0900_write_reg(intp, reg_index,
0xf0 | fmod);
else
stv0900_write_reg(intp, reg_index,
(fmod << 4) | 0xf);
}
} else if (intp->chip_id >= 0x12) {
for (reg_index = 0; reg_index < 7; reg_index++)
stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
stv0900_write_reg(intp, MODCODLSTE, 0xff);
stv0900_write_reg(intp, MODCODLSTF, 0xcf);
for (reg_index = 0; reg_index < 8; reg_index++)
stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
}
}
void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 reg_index;
dprintk("%s\n", __func__);
stv0900_write_reg(intp, MODCODLST0, 0xff);
stv0900_write_reg(intp, MODCODLST1, 0xf0);
stv0900_write_reg(intp, MODCODLSTF, 0x0f);
for (reg_index = 0; reg_index < 13; reg_index++)
stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
}
static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
void stv0900_start_search(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 freq;
s16 freq_s16 ;
stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
if (intp->chip_id == 0x10)
stv0900_write_reg(intp, CORRELEXP, 0xaa);
if (intp->chip_id < 0x20)
stv0900_write_reg(intp, CARHDR, 0x55);
if (intp->chip_id <= 0x20) {
if (intp->symbol_rate[0] <= 5000000) {
stv0900_write_reg(intp, CARCFG, 0x44);
stv0900_write_reg(intp, CFRUP1, 0x0f);
stv0900_write_reg(intp, CFRUP0, 0xff);
stv0900_write_reg(intp, CFRLOW1, 0xf0);
stv0900_write_reg(intp, CFRLOW0, 0x00);
stv0900_write_reg(intp, RTCS2, 0x68);
} else {
stv0900_write_reg(intp, CARCFG, 0xc4);
stv0900_write_reg(intp, RTCS2, 0x44);
}
} else { /*cut 3.0 above*/
if (intp->symbol_rate[demod] <= 5000000)
stv0900_write_reg(intp, RTCS2, 0x68);
else
stv0900_write_reg(intp, RTCS2, 0x44);
stv0900_write_reg(intp, CARCFG, 0x46);
if (intp->srch_algo[demod] == STV0900_WARM_START) {
freq = 1000 << 16;
freq /= (intp->mclk / 1000);
freq_s16 = (s16)freq;
} else {
freq = (intp->srch_range[demod] / 2000);
if (intp->symbol_rate[demod] <= 5000000)
freq += 80;
else
freq += 600;
freq = freq << 16;
freq /= (intp->mclk / 1000);
freq_s16 = (s16)freq;
}
stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
freq_s16 *= (-1);
stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
}
stv0900_write_reg(intp, CFRINIT1, 0);
stv0900_write_reg(intp, CFRINIT0, 0);
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, EQUALCFG, 0x41);
stv0900_write_reg(intp, FFECFG, 0x41);
if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
(intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
(intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
stv0900_write_reg(intp, VITSCALE,
0x82);
stv0900_write_reg(intp, VAVSRVIT, 0x0);
}
}
stv0900_write_reg(intp, SFRSTEP, 0x00);
stv0900_write_reg(intp, TMGTHRISE, 0xe0);
stv0900_write_reg(intp, TMGTHFALL, 0xc0);
stv0900_write_bits(intp, SCAN_ENABLE, 0);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
stv0900_write_reg(intp, RTC, 0x88);
if (intp->chip_id >= 0x20) {
if (intp->symbol_rate[demod] < 2000000) {
if (intp->chip_id <= 0x20)
stv0900_write_reg(intp, CARFREQ, 0x39);
else /*cut 3.0*/
stv0900_write_reg(intp, CARFREQ, 0x89);
stv0900_write_reg(intp, CARHDR, 0x40);
} else if (intp->symbol_rate[demod] < 10000000) {
stv0900_write_reg(intp, CARFREQ, 0x4c);
stv0900_write_reg(intp, CARHDR, 0x20);
} else {
stv0900_write_reg(intp, CARFREQ, 0x4b);
stv0900_write_reg(intp, CARHDR, 0x20);
}
} else {
if (intp->symbol_rate[demod] < 10000000)
stv0900_write_reg(intp, CARFREQ, 0xef);
else
stv0900_write_reg(intp, CARFREQ, 0xed);
}
switch (intp->srch_algo[demod]) {
case STV0900_WARM_START:
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x18);
break;
case STV0900_COLD_START:
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x15);
break;
default:
break;
}
}
u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
s32 pilot, u8 chip_id)
{
u8 aclc_value = 0x29;
s32 i, cllas2_size;
const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
dprintk("%s\n", __func__);
if (chip_id <= 0x12) {
cls2 = FE_STV0900_S2CarLoop;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
cllas2 = FE_STV0900_S2APSKCarLoopCut30;
cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
} else if (chip_id == 0x20) {
cls2 = FE_STV0900_S2CarLoopCut20;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
cllas2 = FE_STV0900_S2APSKCarLoopCut20;
cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut20);
} else {
cls2 = FE_STV0900_S2CarLoopCut30;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
cllas2 = FE_STV0900_S2APSKCarLoopCut30;
cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
}
if (modcode < STV0900_QPSK_12) {
i = 0;
while ((i < 3) && (modcode != cllqs2[i].modcode))
i++;
if (i >= 3)
i = 2;
} else {
i = 0;
while ((i < 14) && (modcode != cls2[i].modcode))
i++;
if (i >= 14) {
i = 0;
while ((i < 11) && (modcode != cllas2[i].modcode))
i++;
if (i >= 11)
i = 10;
}
}
if (modcode <= STV0900_QPSK_25) {
if (pilot) {
if (srate <= 3000000)
aclc_value = cllqs2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = cllqs2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = cllqs2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = cllqs2[i].car_loop_pilots_on_20;
else
aclc_value = cllqs2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
aclc_value = cllqs2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
aclc_value = cllqs2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
aclc_value = cllqs2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
aclc_value = cllqs2[i].car_loop_pilots_off_20;
else
aclc_value = cllqs2[i].car_loop_pilots_off_30;
}
} else if (modcode <= STV0900_8PSK_910) {
if (pilot) {
if (srate <= 3000000)
aclc_value = cls2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = cls2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = cls2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = cls2[i].car_loop_pilots_on_20;
else
aclc_value = cls2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
aclc_value = cls2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
aclc_value = cls2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
aclc_value = cls2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
aclc_value = cls2[i].car_loop_pilots_off_20;
else
aclc_value = cls2[i].car_loop_pilots_off_30;
}
} else if (i < cllas2_size) {
if (srate <= 3000000)
aclc_value = cllas2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = cllas2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = cllas2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = cllas2[i].car_loop_pilots_on_20;
else
aclc_value = cllas2[i].car_loop_pilots_on_30;
}
return aclc_value;
}
u8 stv0900_get_optim_short_carr_loop(s32 srate,
enum fe_stv0900_modulation modulation,
u8 chip_id)
{
const struct stv0900_short_frames_car_loop_optim *s2scl;
const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
s32 mod_index = 0;
u8 aclc_value = 0x0b;
dprintk("%s\n", __func__);
s2scl = FE_STV0900_S2ShortCarLoop;
s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
switch (modulation) {
case STV0900_QPSK:
default:
mod_index = 0;
break;
case STV0900_8PSK:
mod_index = 1;
break;
case STV0900_16APSK:
mod_index = 2;
break;
case STV0900_32APSK:
mod_index = 3;
break;
}
if (chip_id >= 0x30) {
if (srate <= 3000000)
aclc_value = s2sclc30[mod_index].car_loop_2;
else if (srate <= 7000000)
aclc_value = s2sclc30[mod_index].car_loop_5;
else if (srate <= 15000000)
aclc_value = s2sclc30[mod_index].car_loop_10;
else if (srate <= 25000000)
aclc_value = s2sclc30[mod_index].car_loop_20;
else
aclc_value = s2sclc30[mod_index].car_loop_30;
} else if (chip_id >= 0x20) {
if (srate <= 3000000)
aclc_value = s2scl[mod_index].car_loop_cut20_2;
else if (srate <= 7000000)
aclc_value = s2scl[mod_index].car_loop_cut20_5;
else if (srate <= 15000000)
aclc_value = s2scl[mod_index].car_loop_cut20_10;
else if (srate <= 25000000)
aclc_value = s2scl[mod_index].car_loop_cut20_20;
else
aclc_value = s2scl[mod_index].car_loop_cut20_30;
} else {
if (srate <= 3000000)
aclc_value = s2scl[mod_index].car_loop_cut12_2;
else if (srate <= 7000000)
aclc_value = s2scl[mod_index].car_loop_cut12_5;
else if (srate <= 15000000)
aclc_value = s2scl[mod_index].car_loop_cut12_10;
else if (srate <= 25000000)
aclc_value = s2scl[mod_index].car_loop_cut12_20;
else
aclc_value = s2scl[mod_index].car_loop_cut12_30;
}
return aclc_value;
}
static
enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_mode LDPC_Mode,
enum fe_stv0900_demod_num demod)
{
s32 reg_ind;
dprintk("%s\n", __func__);
switch (LDPC_Mode) {
case STV0900_DUAL:
default:
if ((intp->demod_mode != STV0900_DUAL)
|| (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
intp->demod_mode = STV0900_DUAL;
stv0900_write_bits(intp, F0900_FRESFEC, 1);
stv0900_write_bits(intp, F0900_FRESFEC, 0);
for (reg_ind = 0; reg_ind < 7; reg_ind++)
stv0900_write_reg(intp,
R0900_P1_MODCODLST0 + reg_ind,
0xff);
for (reg_ind = 0; reg_ind < 8; reg_ind++)
stv0900_write_reg(intp,
R0900_P1_MODCODLST7 + reg_ind,
0xcc);
stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
for (reg_ind = 0; reg_ind < 7; reg_ind++)
stv0900_write_reg(intp,
R0900_P2_MODCODLST0 + reg_ind,
0xff);
for (reg_ind = 0; reg_ind < 8; reg_ind++)
stv0900_write_reg(intp,
R0900_P2_MODCODLST7 + reg_ind,
0xcc);
stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
}
break;
case STV0900_SINGLE:
if (demod == STV0900_DEMOD_2) {
stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
stv0900_activate_s2_modcod_single(intp,
STV0900_DEMOD_2);
stv0900_write_reg(intp, R0900_GENCFG, 0x06);
} else {
stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
stv0900_activate_s2_modcod_single(intp,
STV0900_DEMOD_1);
stv0900_write_reg(intp, R0900_GENCFG, 0x04);
}
intp->demod_mode = STV0900_SINGLE;
stv0900_write_bits(intp, F0900_FRESFEC, 1);
stv0900_write_bits(intp, F0900_FRESFEC, 0);
stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
break;
}
return STV0900_NO_ERROR;
}
static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
struct stv0900_init_params *p_init)
{
struct stv0900_state *state = fe->demodulator_priv;
enum fe_stv0900_error error = STV0900_NO_ERROR;
enum fe_stv0900_error demodError = STV0900_NO_ERROR;
struct stv0900_internal *intp = NULL;
int selosci, i;
struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
state->config->demod_address);
dprintk("%s\n", __func__);
if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
state->internal = temp_int->internal;
(state->internal->dmds_used)++;
dprintk("%s: Find Internal Structure!\n", __func__);
return STV0900_NO_ERROR;
} else {
state->internal = kmalloc(sizeof(struct stv0900_internal),
GFP_KERNEL);
if (state->internal == NULL)
return STV0900_INVALID_HANDLE;
temp_int = append_internal(state->internal);
if (temp_int == NULL) {
kfree(state->internal);
state->internal = NULL;
return STV0900_INVALID_HANDLE;
}
state->internal->dmds_used = 1;
state->internal->i2c_adap = state->i2c_adap;
state->internal->i2c_addr = state->config->demod_address;
state->internal->clkmode = state->config->clkmode;
state->internal->errs = STV0900_NO_ERROR;
dprintk("%s: Create New Internal Structure!\n", __func__);
}
if (state->internal == NULL) {
error = STV0900_INVALID_HANDLE;
return error;
}
demodError = stv0900_initialize(state->internal);
if (demodError == STV0900_NO_ERROR) {
error = STV0900_NO_ERROR;
} else {
if (demodError == STV0900_INVALID_HANDLE)
error = STV0900_INVALID_HANDLE;
else
error = STV0900_I2C_ERROR;
return error;
}
intp = state->internal;
intp->demod_mode = p_init->demod_mode;
stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
intp->rolloff = p_init->rolloff;
intp->quartz = p_init->dmd_ref_clk;
stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
intp->ts_config = p_init->ts_config;
if (intp->ts_config == NULL)
stv0900_set_ts_parallel_serial(intp,
p_init->path1_ts_clock,
p_init->path2_ts_clock);
else {
for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
stv0900_write_reg(intp,
intp->ts_config[i].addr,
intp->ts_config[i].val);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
}
intp->tuner_type[0] = p_init->tuner1_type;
intp->tuner_type[1] = p_init->tuner2_type;
/* tuner init */
switch (p_init->tuner1_type) {
case 3: /*FE_AUTO_STB6100:*/
stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */
stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
break;
/* case FE_SW_TUNER: */
default:
stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
break;
}
stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
switch (p_init->tuner1_adc) {
case 1:
stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
break;
default:
break;
}
stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */
/* tuner init */
switch (p_init->tuner2_type) {
case 3: /*FE_AUTO_STB6100:*/
stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */
stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
break;
/* case FE_SW_TUNER: */
default:
stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
break;
}
stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
switch (p_init->tuner2_adc) {
case 1:
stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
break;
default:
break;
}
stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */
stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
stv0900_set_mclk(intp, 135000000);
msleep(3);
switch (intp->clkmode) {
case 0:
case 2:
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
break;
default:
selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
break;
}
msleep(3);
intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
if (intp->errs)
error = STV0900_I2C_ERROR;
return error;
}
static int stv0900_status(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_search_state demod_state;
int locked = FALSE;
u8 tsbitrate0_val, tsbitrate1_val;
s32 bitrate;
demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
default:
locked = FALSE;
break;
case STV0900_DVBS2_FOUND:
locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
stv0900_get_bits(intp, PKTDELIN_LOCK) &&
stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
case STV0900_DVBS_FOUND:
locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
stv0900_get_bits(intp, LOCKEDVIT) &&
stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
}
dprintk("%s: locked = %d\n", __func__, locked);
if (stvdebug) {
/* Print TS bitrate */
tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
/* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
* (tsbitrate1_val << 8 | tsbitrate0_val);
bitrate /= 16384;
dprintk("TS bitrate = %d Mbit/sec\n", bitrate);
}
return locked;
}
static int stv0900_set_mis(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod, int mis)
{
dprintk("%s\n", __func__);
if (mis < 0 || mis > 255) {
dprintk("Disable MIS filtering\n");
stv0900_write_bits(intp, FILTER_EN, 0);
} else {
dprintk("Enable MIS filtering - %d\n", mis);
stv0900_write_bits(intp, FILTER_EN, 1);
stv0900_write_reg(intp, ISIENTRY, mis);
stv0900_write_reg(intp, ISIBITENA, 0xff);
}
return STV0900_NO_ERROR;
}
static enum dvbfe_search stv0900_search(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct stv0900_search_params p_search;
struct stv0900_signal_info p_result = intp->result[demod];
enum fe_stv0900_error error = STV0900_NO_ERROR;
dprintk("%s: ", __func__);
if (!(INRANGE(100000, c->symbol_rate, 70000000)))
return DVBFE_ALGO_SEARCH_FAILED;
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
stv0900_set_mis(intp, demod, c->stream_id);
p_result.locked = FALSE;
p_search.path = demod;
p_search.frequency = c->frequency;
p_search.symbol_rate = c->symbol_rate;
p_search.search_range = 10000000;
p_search.fec = STV0900_FEC_UNKNOWN;
p_search.standard = STV0900_AUTO_SEARCH;
p_search.iq_inversion = STV0900_IQ_AUTO;
p_search.search_algo = STV0900_BLIND_SEARCH;
/* Speeds up DVB-S searching */
if (c->delivery_system == SYS_DVBS)
p_search.standard = STV0900_SEARCH_DVBS1;
intp->srch_standard[demod] = p_search.standard;
intp->symbol_rate[demod] = p_search.symbol_rate;
intp->srch_range[demod] = p_search.search_range;
intp->freq[demod] = p_search.frequency;
intp->srch_algo[demod] = p_search.search_algo;
intp->srch_iq_inv[demod] = p_search.iq_inversion;
intp->fec[demod] = p_search.fec;
if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
(intp->errs == STV0900_NO_ERROR)) {
p_result.locked = intp->result[demod].locked;
p_result.standard = intp->result[demod].standard;
p_result.frequency = intp->result[demod].frequency;
p_result.symbol_rate = intp->result[demod].symbol_rate;
p_result.fec = intp->result[demod].fec;
p_result.modcode = intp->result[demod].modcode;
p_result.pilot = intp->result[demod].pilot;
p_result.frame_len = intp->result[demod].frame_len;
p_result.spectrum = intp->result[demod].spectrum;
p_result.rolloff = intp->result[demod].rolloff;
p_result.modulation = intp->result[demod].modulation;
} else {
p_result.locked = FALSE;
switch (intp->err[demod]) {
case STV0900_I2C_ERROR:
error = STV0900_I2C_ERROR;
break;
case STV0900_NO_ERROR:
default:
error = STV0900_SEARCH_FAILED;
break;
}
}
if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
dprintk("Search Success\n");
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
dprintk("Search Fail\n");
return DVBFE_ALGO_SEARCH_FAILED;
}
}
static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stv0900_state *state = fe->demodulator_priv;
dprintk("%s: ", __func__);
if ((stv0900_status(state->internal, state->demod)) == TRUE) {
dprintk("DEMOD LOCK OK\n");
*status = FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 1);
} else {
*status = 0;
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 0);
dprintk("DEMOD LOCK FAIL\n");
}
return 0;
}
static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
if (stop_ts == TRUE)
stv0900_write_bits(intp, RST_HWARE, 1);
else
stv0900_write_bits(intp, RST_HWARE, 0);
return 0;
}
static int stv0900_diseqc_init(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
stv0900_write_bits(intp, DISEQC_RESET, 1);
stv0900_write_bits(intp, DISEQC_RESET, 0);
return 0;
}
static int stv0900_init(struct dvb_frontend *fe)
{
dprintk("%s\n", __func__);
stv0900_stop_ts(fe, 1);
stv0900_diseqc_init(fe);
return 0;
}
static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
u32 NbData, enum fe_stv0900_demod_num demod)
{
s32 i = 0;
stv0900_write_bits(intp, DIS_PRECHARGE, 1);
while (i < NbData) {
while (stv0900_get_bits(intp, FIFO_FULL))
;/* checkpatch complains */
stv0900_write_reg(intp, DISTXDATA, data[i]);
i++;
}
stv0900_write_bits(intp, DIS_PRECHARGE, 0);
i = 0;
while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
msleep(10);
i++;
}
return 0;
}
static int stv0900_send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct stv0900_state *state = fe->demodulator_priv;
return stv0900_diseqc_send(state->internal,
cmd->msg,
cmd->msg_len,
state->demod);
}
static int stv0900_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u8 data;
switch (burst) {
case SEC_MINI_A:
stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
data = 0x00;
stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
case SEC_MINI_B:
stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
data = 0xff;
stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
}
return 0;
}
static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
struct dvb_diseqc_slave_reply *reply)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 i = 0;
reply->msg_len = 0;
while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
msleep(10);
i++;
}
if (stv0900_get_bits(intp, RX_END)) {
reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
for (i = 0; i < reply->msg_len; i++)
reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
}
return 0;
}
static int stv0900_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode toneoff)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
switch (toneoff) {
case SEC_TONE_ON:
/*Set the DiseqC mode to 22Khz _continues_ tone*/
stv0900_write_bits(intp, DISTX_MODE, 0);
stv0900_write_bits(intp, DISEQC_RESET, 1);
/*release DiseqC reset to enable the 22KHz tone*/
stv0900_write_bits(intp, DISEQC_RESET, 0);
break;
case SEC_TONE_OFF:
/*return diseqc mode to config->diseqc_mode.
Usually it's without _continues_ tone */
stv0900_write_bits(intp, DISTX_MODE,
state->config->diseqc_mode);
/*maintain the DiseqC reset to disable the 22KHz tone*/
stv0900_write_bits(intp, DISEQC_RESET, 1);
stv0900_write_bits(intp, DISEQC_RESET, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static void stv0900_release(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 0);
if ((--(state->internal->dmds_used)) <= 0) {
dprintk("%s: Actually removing\n", __func__);
remove_inode(state->internal);
kfree(state->internal);
}
kfree(state);
}
static int stv0900_sleep(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (state->config->set_lock_led)
state->config->set_lock_led(fe, 0);
return 0;
}
static int stv0900_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
struct stv0900_signal_info p_result = intp->result[demod];
p->frequency = p_result.locked ? p_result.frequency : 0;
p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0;
return 0;
}
static const struct dvb_frontend_ops stv0900_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
.info = {
.name = "STV0900 frontend",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 | FE_CAN_QPSK |
FE_CAN_2G_MODULATION |
FE_CAN_FEC_AUTO
},
.release = stv0900_release,
.init = stv0900_init,
.get_frontend = stv0900_get_frontend,
.sleep = stv0900_sleep,
.get_frontend_algo = stv0900_frontend_algo,
.i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
.diseqc_send_master_cmd = stv0900_send_master_cmd,
.diseqc_send_burst = stv0900_send_burst,
.diseqc_recv_slave_reply = stv0900_recv_slave_reply,
.set_tone = stv0900_set_tone,
.search = stv0900_search,
.read_status = stv0900_read_status,
.read_ber = stv0900_read_ber,
.read_signal_strength = stv0900_read_signal_strength,
.read_snr = stv0900_read_snr,
.read_ucblocks = stv0900_read_ucblocks,
};
struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
struct i2c_adapter *i2c,
int demod)
{
struct stv0900_state *state = NULL;
struct stv0900_init_params init_params;
enum fe_stv0900_error err_stv0900;
state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->demod = demod;
state->config = config;
state->i2c_adap = i2c;
memcpy(&state->frontend.ops, &stv0900_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
switch (demod) {
case 0:
case 1:
init_params.dmd_ref_clk = config->xtal;
init_params.demod_mode = config->demod_mode;
init_params.rolloff = STV0900_35;
init_params.path1_ts_clock = config->path1_mode;
init_params.tun1_maddress = config->tun1_maddress;
init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
init_params.tuner1_adc = config->tun1_adc;
init_params.tuner1_type = config->tun1_type;
init_params.path2_ts_clock = config->path2_mode;
init_params.ts_config = config->ts_config_regs;
init_params.tun2_maddress = config->tun2_maddress;
init_params.tuner2_adc = config->tun2_adc;
init_params.tuner2_type = config->tun2_type;
init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
err_stv0900 = stv0900_init_internal(&state->frontend,
&init_params);
if (err_stv0900)
goto error;
if (state->internal->chip_id >= 0x30)
state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
break;
default:
goto error;
break;
}
dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
return &state->frontend;
error:
dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
__func__, demod);
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0900_attach);
MODULE_PARM_DESC(debug, "Set debug");
MODULE_AUTHOR("Igor M. Liplianin");
MODULE_DESCRIPTION("ST STV0900 frontend");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv0900_core.c |
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