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// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for DiBcom DiB3000MC/P-demodulator.
*
* Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
* Copyright (C) 2004-5 Patrick Boettcher ([email protected])
*
* This code is partially based on the previous dib3000mc.c .
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <media/dvb_frontend.h>
#include "dib3000mc.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
static int buggy_sfn_workaround;
module_param(buggy_sfn_workaround, int, 0644);
MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
struct dib3000mc_state {
struct dvb_frontend demod;
struct dib3000mc_config *cfg;
u8 i2c_addr;
struct i2c_adapter *i2c_adap;
struct dibx000_i2c_master i2c_master;
u32 timf;
u32 current_bandwidth;
u16 dev_id;
u8 sfn_workaround_active :1;
};
static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
{
struct i2c_msg msg[2] = {
{ .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 },
{ .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .len = 2 },
};
u16 word;
u8 *b;
b = kmalloc(4, GFP_KERNEL);
if (!b)
return 0;
b[0] = (reg >> 8) | 0x80;
b[1] = reg;
b[2] = 0;
b[3] = 0;
msg[0].buf = b;
msg[1].buf = b + 2;
if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
dprintk("i2c read error on %d\n",reg);
word = (b[2] << 8) | b[3];
kfree(b);
return word;
}
static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
{
struct i2c_msg msg = {
.addr = state->i2c_addr >> 1, .flags = 0, .len = 4
};
int rc;
u8 *b;
b = kmalloc(4, GFP_KERNEL);
if (!b)
return -ENOMEM;
b[0] = reg >> 8;
b[1] = reg;
b[2] = val >> 8;
b[3] = val;
msg.buf = b;
rc = i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
kfree(b);
return rc;
}
static int dib3000mc_identify(struct dib3000mc_state *state)
{
u16 value;
if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value);
return -EREMOTEIO;
}
value = dib3000mc_read_word(state, 1026);
if (value != 0x3001 && value != 0x3002) {
dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value);
return -EREMOTEIO;
}
state->dev_id = value;
dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id);
return 0;
}
static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
{
u32 timf;
if (state->timf == 0) {
timf = 1384402; // default value for 8MHz
if (update_offset)
msleep(200); // first time we do an update
} else
timf = state->timf;
timf *= (bw / 1000);
if (update_offset) {
s16 tim_offs = dib3000mc_read_word(state, 416);
if (tim_offs & 0x2000)
tim_offs -= 0x4000;
if (nfft == TRANSMISSION_MODE_2K)
tim_offs *= 4;
timf += tim_offs;
state->timf = timf / (bw / 1000);
}
dprintk("timf: %d\n", timf);
dib3000mc_write_word(state, 23, (u16) (timf >> 16));
dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
return 0;
}
static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
{
u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
if (state->cfg->pwm3_inversion) {
reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
reg_52 |= (1 << 2);
} else {
reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
reg_52 |= (1 << 8);
}
dib3000mc_write_word(state, 51, reg_51);
dib3000mc_write_word(state, 52, reg_52);
if (state->cfg->use_pwm3)
dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
else
dib3000mc_write_word(state, 245, 0);
dib3000mc_write_word(state, 1040, 0x3);
return 0;
}
static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
{
int ret = 0;
u16 fifo_threshold = 1792;
u16 outreg = 0;
u16 outmode = 0;
u16 elecout = 1;
u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
dprintk("-I- Setting output mode for demod %p to %d\n",
&state->demod, mode);
switch (mode) {
case OUTMODE_HIGH_Z: // disable
elecout = 0;
break;
case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
outmode = 0;
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
outmode = 1;
break;
case OUTMODE_MPEG2_SERIAL: // STBs with serial input
outmode = 2;
break;
case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
elecout = 3;
/*ADDR @ 206 :
P_smo_error_discard [1;6:6] = 0
P_smo_rs_discard [1;5:5] = 0
P_smo_pid_parse [1;4:4] = 0
P_smo_fifo_flush [1;3:3] = 0
P_smo_mode [2;2:1] = 11
P_smo_ovf_prot [1;0:0] = 0
*/
smo_reg |= 3 << 1;
fifo_threshold = 512;
outmode = 5;
break;
case OUTMODE_DIVERSITY:
outmode = 4;
elecout = 1;
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
outmode = 0;
break;
}
if ((state->cfg->output_mpeg2_in_188_bytes))
smo_reg |= (1 << 5); // P_smo_rs_discard [1;5:5] = 1
outreg = dib3000mc_read_word(state, 244) & 0x07FF;
outreg |= (outmode << 11);
ret |= dib3000mc_write_word(state, 244, outreg);
ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
return ret;
}
static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
{
u16 bw_cfg[6] = { 0 };
u16 imp_bw_cfg[3] = { 0 };
u16 reg;
/* settings here are for 27.7MHz */
switch (bw) {
case 8000:
bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
break;
case 7000:
bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
break;
case 6000:
bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
break;
case 5000:
bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
break;
default: return -EINVAL;
}
for (reg = 6; reg < 12; reg++)
dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
dib3000mc_write_word(state, 12, 0x0000);
dib3000mc_write_word(state, 13, 0x03e8);
dib3000mc_write_word(state, 14, 0x0000);
dib3000mc_write_word(state, 15, 0x03f2);
dib3000mc_write_word(state, 16, 0x0001);
dib3000mc_write_word(state, 17, 0xb0d0);
// P_sec_len
dib3000mc_write_word(state, 18, 0x0393);
dib3000mc_write_word(state, 19, 0x8700);
for (reg = 55; reg < 58; reg++)
dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
// Timing configuration
dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
return 0;
}
static u16 impulse_noise_val[29] =
{
0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
};
static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
{
u16 i;
for (i = 58; i < 87; i++)
dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
if (nfft == TRANSMISSION_MODE_8K) {
dib3000mc_write_word(state, 58, 0x3b);
dib3000mc_write_word(state, 84, 0x00);
dib3000mc_write_word(state, 85, 0x8200);
}
dib3000mc_write_word(state, 34, 0x1294);
dib3000mc_write_word(state, 35, 0x1ff8);
if (mode == 1)
dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
}
static int dib3000mc_init(struct dvb_frontend *demod)
{
struct dib3000mc_state *state = demod->demodulator_priv;
struct dibx000_agc_config *agc = state->cfg->agc;
// Restart Configuration
dib3000mc_write_word(state, 1027, 0x8000);
dib3000mc_write_word(state, 1027, 0x0000);
// power up the demod + mobility configuration
dib3000mc_write_word(state, 140, 0x0000);
dib3000mc_write_word(state, 1031, 0);
if (state->cfg->mobile_mode) {
dib3000mc_write_word(state, 139, 0x0000);
dib3000mc_write_word(state, 141, 0x0000);
dib3000mc_write_word(state, 175, 0x0002);
dib3000mc_write_word(state, 1032, 0x0000);
} else {
dib3000mc_write_word(state, 139, 0x0001);
dib3000mc_write_word(state, 141, 0x0000);
dib3000mc_write_word(state, 175, 0x0000);
dib3000mc_write_word(state, 1032, 0x012C);
}
dib3000mc_write_word(state, 1033, 0x0000);
// P_clk_cfg
dib3000mc_write_word(state, 1037, 0x3130);
// other configurations
// P_ctrl_sfreq
dib3000mc_write_word(state, 33, (5 << 0));
dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
// Phase noise control
// P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange
dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
if (state->cfg->phase_noise_mode == 0)
dib3000mc_write_word(state, 111, 0x00);
else
dib3000mc_write_word(state, 111, 0x02);
// P_agc_global
dib3000mc_write_word(state, 50, 0x8000);
// agc setup misc
dib3000mc_setup_pwm_state(state);
// P_agc_counter_lock
dib3000mc_write_word(state, 53, 0x87);
// P_agc_counter_unlock
dib3000mc_write_word(state, 54, 0x87);
/* agc */
dib3000mc_write_word(state, 36, state->cfg->max_time);
dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
// set_agc_loop_Bw
dib3000mc_write_word(state, 40, 0x0179);
dib3000mc_write_word(state, 41, 0x03f0);
dib3000mc_write_word(state, 42, agc->agc1_max);
dib3000mc_write_word(state, 43, agc->agc1_min);
dib3000mc_write_word(state, 44, agc->agc2_max);
dib3000mc_write_word(state, 45, agc->agc2_min);
dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
// Begin: TimeOut registers
// P_pha3_thres
dib3000mc_write_word(state, 110, 3277);
// P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80
dib3000mc_write_word(state, 26, 0x6680);
// lock_mask0
dib3000mc_write_word(state, 1, 4);
// lock_mask1
dib3000mc_write_word(state, 2, 4);
// lock_mask2
dib3000mc_write_word(state, 3, 0x1000);
// P_search_maxtrial=1
dib3000mc_write_word(state, 5, 1);
dib3000mc_set_bandwidth(state, 8000);
// div_lock_mask
dib3000mc_write_word(state, 4, 0x814);
dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
dib3000mc_write_word(state, 22, 0x463d);
// Spurious rm cfg
// P_cspu_regul, P_cspu_win_cut
dib3000mc_write_word(state, 120, 0x200f);
// P_adp_selec_monit
dib3000mc_write_word(state, 134, 0);
// Fec cfg
dib3000mc_write_word(state, 195, 0x10);
// diversity register: P_dvsy_sync_wait..
dib3000mc_write_word(state, 180, 0x2FF0);
// Impulse noise configuration
dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
// output mode set-up
dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
/* close the i2c-gate */
dib3000mc_write_word(state, 769, (1 << 7) );
return 0;
}
static int dib3000mc_sleep(struct dvb_frontend *demod)
{
struct dib3000mc_state *state = demod->demodulator_priv;
dib3000mc_write_word(state, 1031, 0xFFFF);
dib3000mc_write_word(state, 1032, 0xFFFF);
dib3000mc_write_word(state, 1033, 0xFFF0);
return 0;
}
static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
{
u16 cfg[4] = { 0 },reg;
switch (qam) {
case QPSK:
cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
break;
case QAM_16:
cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
break;
case QAM_64:
cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
break;
}
for (reg = 129; reg < 133; reg++)
dib3000mc_write_word(state, reg, cfg[reg - 129]);
}
static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state,
struct dtv_frontend_properties *ch, u16 seq)
{
u16 value;
u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
dib3000mc_set_bandwidth(state, bw);
dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
#if 1
dib3000mc_write_word(state, 100, (16 << 6) + 9);
#else
if (boost)
dib3000mc_write_word(state, 100, (11 << 6) + 6);
else
dib3000mc_write_word(state, 100, (16 << 6) + 9);
#endif
dib3000mc_write_word(state, 1027, 0x0800);
dib3000mc_write_word(state, 1027, 0x0000);
//Default cfg isi offset adp
dib3000mc_write_word(state, 26, 0x6680);
dib3000mc_write_word(state, 29, 0x1273);
dib3000mc_write_word(state, 33, 5);
dib3000mc_set_adp_cfg(state, QAM_16);
dib3000mc_write_word(state, 133, 15564);
dib3000mc_write_word(state, 12 , 0x0);
dib3000mc_write_word(state, 13 , 0x3e8);
dib3000mc_write_word(state, 14 , 0x0);
dib3000mc_write_word(state, 15 , 0x3f2);
dib3000mc_write_word(state, 93,0);
dib3000mc_write_word(state, 94,0);
dib3000mc_write_word(state, 95,0);
dib3000mc_write_word(state, 96,0);
dib3000mc_write_word(state, 97,0);
dib3000mc_write_word(state, 98,0);
dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode);
value = 0;
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
default:
case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
default:
case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
}
switch (ch->modulation) {
case QPSK: value |= (0 << 3); break;
case QAM_16: value |= (1 << 3); break;
default:
case QAM_64: value |= (2 << 3); break;
}
switch (HIERARCHY_1) {
case HIERARCHY_2: value |= 2; break;
case HIERARCHY_4: value |= 4; break;
default:
case HIERARCHY_1: value |= 1; break;
}
dib3000mc_write_word(state, 0, value);
dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
value = 0;
if (ch->hierarchy == 1)
value |= (1 << 4);
if (1 == 1)
value |= 1;
switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
case FEC_2_3: value |= (2 << 1); break;
case FEC_3_4: value |= (3 << 1); break;
case FEC_5_6: value |= (5 << 1); break;
case FEC_7_8: value |= (7 << 1); break;
default:
case FEC_1_2: value |= (1 << 1); break;
}
dib3000mc_write_word(state, 181, value);
// diversity synchro delay add 50% SFN margin
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_8K: value = 256; break;
case TRANSMISSION_MODE_2K:
default: value = 64; break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_16: value *= 2; break;
case GUARD_INTERVAL_1_8: value *= 4; break;
case GUARD_INTERVAL_1_4: value *= 8; break;
default:
case GUARD_INTERVAL_1_32: value *= 1; break;
}
value <<= 4;
value |= dib3000mc_read_word(state, 180) & 0x000f;
dib3000mc_write_word(state, 180, value);
// restart demod
value = dib3000mc_read_word(state, 0);
dib3000mc_write_word(state, 0, value | (1 << 9));
dib3000mc_write_word(state, 0, value);
msleep(30);
dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode);
}
static int dib3000mc_autosearch_start(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *chan = &demod->dtv_property_cache;
struct dib3000mc_state *state = demod->demodulator_priv;
u16 reg;
// u32 val;
struct dtv_frontend_properties schan;
schan = *chan;
/* TODO what is that ? */
/* a channel for autosearch */
schan.transmission_mode = TRANSMISSION_MODE_8K;
schan.guard_interval = GUARD_INTERVAL_1_32;
schan.modulation = QAM_64;
schan.code_rate_HP = FEC_2_3;
schan.code_rate_LP = FEC_2_3;
schan.hierarchy = 0;
dib3000mc_set_channel_cfg(state, &schan, 11);
reg = dib3000mc_read_word(state, 0);
dib3000mc_write_word(state, 0, reg | (1 << 8));
dib3000mc_read_word(state, 511);
dib3000mc_write_word(state, 0, reg);
return 0;
}
static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
{
struct dib3000mc_state *state = demod->demodulator_priv;
u16 irq_pending = dib3000mc_read_word(state, 511);
if (irq_pending & 0x1) // failed
return 1;
if (irq_pending & 0x2) // succeeded
return 2;
return 0; // still pending
}
static int dib3000mc_tune(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib3000mc_state *state = demod->demodulator_priv;
// ** configure demod **
dib3000mc_set_channel_cfg(state, ch, 0);
// activates isi
if (state->sfn_workaround_active) {
dprintk("SFN workaround is active\n");
dib3000mc_write_word(state, 29, 0x1273);
dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift
} else {
dib3000mc_write_word(state, 29, 0x1073);
dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
}
dib3000mc_set_adp_cfg(state, (u8)ch->modulation);
if (ch->transmission_mode == TRANSMISSION_MODE_8K) {
dib3000mc_write_word(state, 26, 38528);
dib3000mc_write_word(state, 33, 8);
} else {
dib3000mc_write_word(state, 26, 30336);
dib3000mc_write_word(state, 33, 6);
}
if (dib3000mc_read_word(state, 509) & 0x80)
dib3000mc_set_timing(state, ch->transmission_mode,
BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1);
return 0;
}
struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating)
{
struct dib3000mc_state *st = demod->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating);
}
EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
static int dib3000mc_get_frontend(struct dvb_frontend* fe,
struct dtv_frontend_properties *fep)
{
struct dib3000mc_state *state = fe->demodulator_priv;
u16 tps = dib3000mc_read_word(state,458);
fep->inversion = INVERSION_AUTO;
fep->bandwidth_hz = state->current_bandwidth;
switch ((tps >> 8) & 0x1) {
case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
}
switch (tps & 0x3) {
case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
}
switch ((tps >> 13) & 0x3) {
case 0: fep->modulation = QPSK; break;
case 1: fep->modulation = QAM_16; break;
case 2:
default: fep->modulation = QAM_64; break;
}
/* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
/* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
fep->hierarchy = HIERARCHY_NONE;
switch ((tps >> 5) & 0x7) {
case 1: fep->code_rate_HP = FEC_1_2; break;
case 2: fep->code_rate_HP = FEC_2_3; break;
case 3: fep->code_rate_HP = FEC_3_4; break;
case 5: fep->code_rate_HP = FEC_5_6; break;
case 7:
default: fep->code_rate_HP = FEC_7_8; break;
}
switch ((tps >> 2) & 0x7) {
case 1: fep->code_rate_LP = FEC_1_2; break;
case 2: fep->code_rate_LP = FEC_2_3; break;
case 3: fep->code_rate_LP = FEC_3_4; break;
case 5: fep->code_rate_LP = FEC_5_6; break;
case 7:
default: fep->code_rate_LP = FEC_7_8; break;
}
return 0;
}
static int dib3000mc_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
struct dib3000mc_state *state = fe->demodulator_priv;
int ret;
dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
state->current_bandwidth = fep->bandwidth_hz;
dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
/* maybe the parameter has been changed */
state->sfn_workaround_active = buggy_sfn_workaround;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
msleep(100);
}
if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
fep->guard_interval == GUARD_INTERVAL_AUTO ||
fep->modulation == QAM_AUTO ||
fep->code_rate_HP == FEC_AUTO) {
int i = 1000, found;
dib3000mc_autosearch_start(fe);
do {
msleep(1);
found = dib3000mc_autosearch_is_irq(fe);
} while (found == 0 && i--);
dprintk("autosearch returns: %d\n",found);
if (found == 0 || found == 1)
return 0; // no channel found
dib3000mc_get_frontend(fe, fep);
}
ret = dib3000mc_tune(fe);
/* make this a config parameter */
dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
return ret;
}
static int dib3000mc_read_status(struct dvb_frontend *fe, enum fe_status *stat)
{
struct dib3000mc_state *state = fe->demodulator_priv;
u16 lock = dib3000mc_read_word(state, 509);
*stat = 0;
if (lock & 0x8000)
*stat |= FE_HAS_SIGNAL;
if (lock & 0x3000)
*stat |= FE_HAS_CARRIER;
if (lock & 0x0100)
*stat |= FE_HAS_VITERBI;
if (lock & 0x0010)
*stat |= FE_HAS_SYNC;
if (lock & 0x0008)
*stat |= FE_HAS_LOCK;
return 0;
}
static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct dib3000mc_state *state = fe->demodulator_priv;
*ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
return 0;
}
static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
{
struct dib3000mc_state *state = fe->demodulator_priv;
*unc = dib3000mc_read_word(state, 508);
return 0;
}
static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct dib3000mc_state *state = fe->demodulator_priv;
u16 val = dib3000mc_read_word(state, 392);
*strength = 65535 - val;
return 0;
}
static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
{
*snr = 0x0000;
return 0;
}
static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void dib3000mc_release(struct dvb_frontend *fe)
{
struct dib3000mc_state *state = fe->demodulator_priv;
dibx000_exit_i2c_master(&state->i2c_master);
kfree(state);
}
int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff)
{
struct dib3000mc_state *state = fe->demodulator_priv;
dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
return 0;
}
EXPORT_SYMBOL(dib3000mc_pid_control);
int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
{
struct dib3000mc_state *state = fe->demodulator_priv;
u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
tmp |= (onoff << 4);
return dib3000mc_write_word(state, 206, tmp);
}
EXPORT_SYMBOL(dib3000mc_pid_parse);
void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg)
{
struct dib3000mc_state *state = fe->demodulator_priv;
state->cfg = cfg;
}
EXPORT_SYMBOL(dib3000mc_set_config);
int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[])
{
struct dib3000mc_state *dmcst;
int k;
u8 new_addr;
static const u8 DIB3000MC_I2C_ADDRESS[] = { 20, 22, 24, 26 };
dmcst = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
if (dmcst == NULL)
return -ENOMEM;
dmcst->i2c_adap = i2c;
for (k = no_of_demods-1; k >= 0; k--) {
dmcst->cfg = &cfg[k];
/* designated i2c address */
new_addr = DIB3000MC_I2C_ADDRESS[k];
dmcst->i2c_addr = new_addr;
if (dib3000mc_identify(dmcst) != 0) {
dmcst->i2c_addr = default_addr;
if (dib3000mc_identify(dmcst) != 0) {
dprintk("-E- DiB3000P/MC #%d: not identified\n", k);
kfree(dmcst);
return -ENODEV;
}
}
dib3000mc_set_output_mode(dmcst, OUTMODE_MPEG2_PAR_CONT_CLK);
// set new i2c address and force divstr (Bit 1) to value 0 (Bit 0)
dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1);
dmcst->i2c_addr = new_addr;
}
for (k = 0; k < no_of_demods; k++) {
dmcst->cfg = &cfg[k];
dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k];
dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3);
/* turn off data output */
dib3000mc_set_output_mode(dmcst, OUTMODE_HIGH_Z);
}
kfree(dmcst);
return 0;
}
EXPORT_SYMBOL(dib3000mc_i2c_enumeration);
static const struct dvb_frontend_ops dib3000mc_ops;
struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg)
{
struct dvb_frontend *demod;
struct dib3000mc_state *st;
st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
if (st == NULL)
return NULL;
st->cfg = cfg;
st->i2c_adap = i2c_adap;
st->i2c_addr = i2c_addr;
demod = &st->demod;
demod->demodulator_priv = st;
memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
if (dib3000mc_identify(st) != 0)
goto error;
dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
dib3000mc_write_word(st, 1037, 0x3130);
return demod;
error:
kfree(st);
return NULL;
}
EXPORT_SYMBOL_GPL(dib3000mc_attach);
static const struct dvb_frontend_ops dib3000mc_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 3000MC/P",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = dib3000mc_release,
.init = dib3000mc_init,
.sleep = dib3000mc_sleep,
.set_frontend = dib3000mc_set_frontend,
.get_tune_settings = dib3000mc_fe_get_tune_settings,
.get_frontend = dib3000mc_get_frontend,
.read_status = dib3000mc_read_status,
.read_ber = dib3000mc_read_ber,
.read_signal_strength = dib3000mc_read_signal_strength,
.read_snr = dib3000mc_read_snr,
.read_ucblocks = dib3000mc_read_unc_blocks,
};
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib3000mc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* isl6421.h - driver for lnb supply and control ic ISL6421
*
* Copyright (C) 2006 Andrew de Quincey
* Copyright (C) 2006 Oliver Endriss
*
* the project's page is at https://linuxtv.org
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "isl6421.h"
struct isl6421 {
u8 config;
u8 override_or;
u8 override_and;
struct i2c_adapter *i2c;
u8 i2c_addr;
bool is_off;
};
static int isl6421_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
int ret;
u8 buf;
bool is_off;
struct isl6421 *isl6421 = (struct isl6421 *) fe->sec_priv;
struct i2c_msg msg[2] = {
{
.addr = isl6421->i2c_addr,
.flags = 0,
.buf = &isl6421->config,
.len = 1,
}, {
.addr = isl6421->i2c_addr,
.flags = I2C_M_RD,
.buf = &buf,
.len = 1,
}
};
isl6421->config &= ~(ISL6421_VSEL1 | ISL6421_EN1);
switch(voltage) {
case SEC_VOLTAGE_OFF:
is_off = true;
break;
case SEC_VOLTAGE_13:
is_off = false;
isl6421->config |= ISL6421_EN1;
break;
case SEC_VOLTAGE_18:
is_off = false;
isl6421->config |= (ISL6421_EN1 | ISL6421_VSEL1);
break;
default:
return -EINVAL;
}
/*
* If LNBf were not powered on, disable dynamic current limit, as,
* according with datasheet, highly capacitive load on the output may
* cause a difficult start-up.
*/
if (isl6421->is_off && !is_off)
isl6421->config |= ISL6421_DCL;
isl6421->config |= isl6421->override_or;
isl6421->config &= isl6421->override_and;
ret = i2c_transfer(isl6421->i2c, msg, 2);
if (ret < 0)
return ret;
if (ret != 2)
return -EIO;
/* Store off status now in case future commands fail */
isl6421->is_off = is_off;
/* On overflow, the device will try again after 900 ms (typically) */
if (!is_off && (buf & ISL6421_OLF1))
msleep(1000);
/* Re-enable dynamic current limit */
if ((isl6421->config & ISL6421_DCL) &&
!(isl6421->override_or & ISL6421_DCL)) {
isl6421->config &= ~ISL6421_DCL;
ret = i2c_transfer(isl6421->i2c, msg, 2);
if (ret < 0)
return ret;
if (ret != 2)
return -EIO;
}
/* Check if overload flag is active. If so, disable power */
if (!is_off && (buf & ISL6421_OLF1)) {
isl6421->config &= ~(ISL6421_VSEL1 | ISL6421_EN1);
ret = i2c_transfer(isl6421->i2c, msg, 1);
if (ret < 0)
return ret;
if (ret != 1)
return -EIO;
isl6421->is_off = true;
dev_warn(&isl6421->i2c->dev,
"Overload current detected. disabling LNBf power\n");
return -EINVAL;
}
return 0;
}
static int isl6421_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct isl6421 *isl6421 = (struct isl6421 *) fe->sec_priv;
struct i2c_msg msg = { .addr = isl6421->i2c_addr, .flags = 0,
.buf = &isl6421->config,
.len = sizeof(isl6421->config) };
if (arg)
isl6421->config |= ISL6421_LLC1;
else
isl6421->config &= ~ISL6421_LLC1;
isl6421->config |= isl6421->override_or;
isl6421->config &= isl6421->override_and;
return (i2c_transfer(isl6421->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int isl6421_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct isl6421 *isl6421 = (struct isl6421 *) fe->sec_priv;
struct i2c_msg msg = { .addr = isl6421->i2c_addr, .flags = 0,
.buf = &isl6421->config,
.len = sizeof(isl6421->config) };
switch (tone) {
case SEC_TONE_ON:
isl6421->config |= ISL6421_ENT1;
break;
case SEC_TONE_OFF:
isl6421->config &= ~ISL6421_ENT1;
break;
default:
return -EINVAL;
}
isl6421->config |= isl6421->override_or;
isl6421->config &= isl6421->override_and;
return (i2c_transfer(isl6421->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static void isl6421_release(struct dvb_frontend *fe)
{
/* power off */
isl6421_set_voltage(fe, SEC_VOLTAGE_OFF);
/* free */
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 i2c_addr,
u8 override_set, u8 override_clear, bool override_tone)
{
struct isl6421 *isl6421 = kmalloc(sizeof(struct isl6421), GFP_KERNEL);
if (!isl6421)
return NULL;
/* default configuration */
isl6421->config = ISL6421_ISEL1;
isl6421->i2c = i2c;
isl6421->i2c_addr = i2c_addr;
fe->sec_priv = isl6421;
/* bits which should be forced to '1' */
isl6421->override_or = override_set;
/* bits which should be forced to '0' */
isl6421->override_and = ~override_clear;
/* detect if it is present or not */
if (isl6421_set_voltage(fe, SEC_VOLTAGE_OFF)) {
kfree(isl6421);
fe->sec_priv = NULL;
return NULL;
}
isl6421->is_off = true;
/* install release callback */
fe->ops.release_sec = isl6421_release;
/* override frontend ops */
fe->ops.set_voltage = isl6421_set_voltage;
fe->ops.enable_high_lnb_voltage = isl6421_enable_high_lnb_voltage;
if (override_tone)
fe->ops.set_tone = isl6421_set_tone;
return fe;
}
EXPORT_SYMBOL_GPL(isl6421_attach);
MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6421");
MODULE_AUTHOR("Andrew de Quincey & Oliver Endriss");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/isl6421.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drxd_firm.c : DRXD firmware tables
*
* Copyright (C) 2006-2007 Micronas
*/
/* TODO: generate this file with a script from a settings file */
/* Contains A2 firmware version: 1.4.2
* Contains B1 firmware version: 3.3.33
* Contains settings from driver 1.4.23
*/
#include "drxd_firm.h"
#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
/* Is written via block write, must be little endian */
#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
#define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
#define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
#define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
/* HI firmware patches */
#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
u8 DRXD_InitAtomicRead[] = {
WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
0x26, 0x00, /* 0 -> ring.rdy; */
0x60, 0x04, /* r0rami.dt -> ring.xba; */
0x61, 0x04, /* r0rami.dt -> ring.xad; */
0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
0x40, 0x00, /* (long immediate) */
0x64, 0x04, /* r0rami.dt -> ring.len; */
0x65, 0x04, /* r0rami.dt -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0x38, 0x00, /* 0 -> jumps.ad; */
END_OF_TABLE
};
/* Pins D0 and D1 of the parallel MPEG output can be used
to set the I2C address of a device. */
#define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
/* D0 Version */
u8 DRXD_HiI2cPatch_1[] = {
WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
0x23, 0x00, /* &data -> ring.iad; */
0x24, 0x00, /* 0 -> ring.len; */
0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0x42, 0x00, /* &data+1 -> w0ram.ad; */
0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
0x63, 0x00, /* &data+1 -> ring.iad; */
0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
0x23, 0x00, /* &data -> ring.iad; */
0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0x42, 0x00, /* &data+1 -> w0ram.ad; */
0x0F, 0x04, /* r0ram.dt -> and.op; */
0x1C, 0x06, /* reg0.dt -> and.tr; */
0xCF, 0x04, /* and.rs -> add.op; */
0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
0xD0, 0x04, /* add.rs -> add.tr; */
0xC8, 0x04, /* add.rs -> reg0.dt; */
0x60, 0x00, /* reg0.dt -> w0ram.dt; */
0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x06, /* reg0.dt -> w0rami.dt; */
0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x06, /* reg0.dt -> w0rami.dt; */
0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
/* Force quick and dirty reset */
WR16(B_HI_CT_REG_COMM_STATE__A, 0),
END_OF_TABLE
};
/* D0,D1 Version */
u8 DRXD_HiI2cPatch_3[] = {
WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
0x23, 0x00, /* &data -> ring.iad; */
0x24, 0x00, /* 0 -> ring.len; */
0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0x42, 0x00, /* &data+1 -> w0ram.ad; */
0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
0x63, 0x00, /* &data+1 -> ring.iad; */
0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
0x23, 0x00, /* &data -> ring.iad; */
0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
0x26, 0x00, /* 0 -> ring.rdy; */
0x42, 0x00, /* &data+1 -> w0ram.ad; */
0x0F, 0x04, /* r0ram.dt -> and.op; */
0x1C, 0x06, /* reg0.dt -> and.tr; */
0xCF, 0x04, /* and.rs -> add.op; */
0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
0xD0, 0x04, /* add.rs -> add.tr; */
0xC8, 0x04, /* add.rs -> reg0.dt; */
0x60, 0x00, /* reg0.dt -> w0ram.dt; */
0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x06, /* reg0.dt -> w0rami.dt; */
0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x06, /* reg0.dt -> w0rami.dt; */
0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x01, 0x00, /* 0 -> w0rami.dt; */
0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
/* Force quick and dirty reset */
WR16(B_HI_CT_REG_COMM_STATE__A, 0),
END_OF_TABLE
};
u8 DRXD_ResetCEFR[] = {
WRBLOCK(CE_REG_FR_TREAL00__A, 57),
0x52, 0x00, /* CE_REG_FR_TREAL00__A */
0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
0x52, 0x00, /* CE_REG_FR_TREAL01__A */
0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
0x52, 0x00, /* CE_REG_FR_TREAL02__A */
0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
0x52, 0x00, /* CE_REG_FR_TREAL03__A */
0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
0x52, 0x00, /* CE_REG_FR_TREAL04__A */
0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
0x52, 0x00, /* CE_REG_FR_TREAL05__A */
0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
0x52, 0x00, /* CE_REG_FR_TREAL06__A */
0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
0x52, 0x00, /* CE_REG_FR_TREAL07__A */
0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
0x52, 0x00, /* CE_REG_FR_TREAL08__A */
0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
0x52, 0x00, /* CE_REG_FR_TREAL09__A */
0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
0x52, 0x00, /* CE_REG_FR_TREAL10__A */
0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
0x52, 0x00, /* CE_REG_FR_TREAL11__A */
0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
0x10, 0x00, /* CE_REG_FR_MODE__A */
0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
0x00, 0x02, /* CE_REG_FR_BYPASS__A */
0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
END_OF_TABLE
};
u8 DRXD_InitFEA2_1[] = {
WRBLOCK(FE_AD_REG_PD__A, 3),
0x00, 0x00, /* FE_AD_REG_PD__A */
0x01, 0x00, /* FE_AD_REG_INVEXT__A */
0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
WRBLOCK(FE_FD_REG_SCL__A, 3),
0x05, 0x00, /* FE_FD_REG_SCL__A */
0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
0x05, 0x00, /* FE_FD_REG_NR__A */
WRBLOCK(FE_CF_REG_SCL__A, 5),
0x16, 0x00, /* FE_CF_REG_SCL__A */
0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
0x06, 0x00, /* FE_CF_REG_NR__A */
0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
END_OF_TABLE
};
/* with PGA */
/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
/* without PGA */
/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
u8 DRXD_InitFEA2_2[] = {
WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
WR16(FE_AG_REG_FGM_WRI__A, 48),
/* Activate measurement, activate scale */
WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
END_OF_TABLE
};
u8 DRXD_InitFEB1_1[] = {
WR16(B_FE_AD_REG_PD__A, 0x0000),
WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
WR16(B_FE_AG_REG_IND_WIN__A, 0),
WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
WR16(B_FE_CF_REG_IMP_VAL__A, 1),
WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
END_OF_TABLE
};
/* with PGA */
/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
/* without PGA */
/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
u8 DRXD_InitFEB1_2[] = {
WR16(B_FE_COMM_EXEC__A, 0x0001),
/* RF-AGC setup */
WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
END_OF_TABLE
};
u8 DRXD_InitCPA2[] = {
WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
WR16(CP_REG_INTERVAL__A, 0x0005),
WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
WR16(CP_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_InitCPB1[] = {
WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
WR16(B_CP_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_InitCEA2[] = {
WRBLOCK(CE_REG_AVG_POW__A, 4),
0x62, 0x00, /* CE_REG_AVG_POW__A */
0x78, 0x00, /* CE_REG_MAX_POW__A */
0x62, 0x00, /* CE_REG_ATT__A */
0x17, 0x00, /* CE_REG_NRED__A */
WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
END_OF_TABLE
};
u8 DRXD_InitCEB1[] = {
WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
END_OF_TABLE
};
u8 DRXD_InitEQA2[] = {
WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
WR16(EQ_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_InitEQB1[] = {
WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_ResetECRAM[] = {
/* Reset packet sync bytes in EC_VD ram */
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
/* Reset packet sync bytes in EC_RS ram */
WR16(EC_RS_EC_RAM__A, 0x0000),
WR16(EC_RS_EC_RAM__A + 204, 0x0000),
END_OF_TABLE
};
u8 DRXD_InitECA2[] = {
WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
WR16(EC_VD_REG_FORCE__A, 0x0002),
WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
WR16(EC_OD_REG_SYNC__A, 0x0664),
WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
/* Output zero on monitorbus pads, power saving */
WR16(EC_OC_REG_OCR_MON_UOS__A,
(EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
WR16(EC_OC_REG_OCR_MON_WRI__A,
EC_OC_REG_OCR_MON_WRI_INIT),
/* CHK_ERROR(ResetECRAM(demod)); */
/* Reset packet sync bytes in EC_VD ram */
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
/* Reset packet sync bytes in EC_RS ram */
WR16(EC_RS_EC_RAM__A, 0x0000),
WR16(EC_RS_EC_RAM__A + 204, 0x0000),
WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_InitECB1[] = {
WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
/* Needed because shadow registers do not have correct default value */
WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
WR16(B_EC_OD_REG_SYNC__A, 0x0664),
WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
/* CHK_ERROR(ResetECRAM(demod)); */
/* Reset packet sync bytes in EC_VD ram */
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
/* Reset packet sync bytes in EC_RS ram */
WR16(EC_RS_EC_RAM__A, 0x0000),
WR16(EC_RS_EC_RAM__A + 204, 0x0000),
WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_ResetECA2[] = {
WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
WR16(EC_OD_REG_SYNC__A, 0x0664),
WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
/* Output zero on monitorbus pads, power saving */
WR16(EC_OC_REG_OCR_MON_UOS__A,
(EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
WR16(EC_OC_REG_OCR_MON_WRI__A,
EC_OC_REG_OCR_MON_WRI_INIT),
/* CHK_ERROR(ResetECRAM(demod)); */
/* Reset packet sync bytes in EC_VD ram */
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
/* Reset packet sync bytes in EC_RS ram */
WR16(EC_RS_EC_RAM__A, 0x0000),
WR16(EC_RS_EC_RAM__A + 204, 0x0000),
WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_InitSC[] = {
WR16(SC_COMM_EXEC__A, 0),
WR16(SC_COMM_STATE__A, 0),
#ifdef COMPILE_FOR_QT
WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
#endif
/* SC is not started, this is done in SetChannels() */
END_OF_TABLE
};
/* Diversity settings */
u8 DRXD_InitDiversityFront[] = {
/* Start demod ********* RF in , diversity out **************************** */
WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
B_SC_RA_RAM_CONFIG_FREQSCAN__M),
WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
WR16(B_CC_REG_DIVERSITY__A, 0x0001),
WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
/* 0x2a ), *//* CE to PASS mux */
END_OF_TABLE
};
u8 DRXD_InitDiversityEnd[] = {
/* End demod *********** combining RF in and diversity in, MPEG TS out **** */
/* disable near/far; switch on timing slave mode */
WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
B_SC_RA_RAM_CONFIG_FREQSCAN__M |
B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
B_SC_RA_RAM_CONFIG_SLAVE__M |
B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
/* MV from CtrlDiversity */
),
#ifdef DRXDDIV_SRMM_SLAVING
WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
#else
WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
#endif
WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
WR16(B_CC_REG_DIVERSITY__A, 0x0001),
END_OF_TABLE
};
u8 DRXD_DisableDiversity[] = {
WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
WR16(B_CC_REG_DIVERSITY__A, 0x0000),
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
END_OF_TABLE
};
u8 DRXD_StartDiversityFront[] = {
/* Start demod, RF in and diversity out, no combining */
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
WR16(B_FE_AD_REG_INVEXT__A, 0x0),
WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
END_OF_TABLE
};
u8 DRXD_StartDiversityEnd[] = {
/* End demod, combining RF in and diversity in, MPEG TS out */
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apparently no mb delay matching is best */
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
END_OF_TABLE
};
u8 DRXD_DiversityDelay8MHZ[] = {
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
END_OF_TABLE
};
u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
{
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
END_OF_TABLE
};
| linux-master | drivers/media/dvb-frontends/drxd_firm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for Philips TDA8083 based QPSK Demodulator
Copyright (C) 2001 Convergence Integrated Media GmbH
written by Ralph Metzler <[email protected]>
adoption to the new DVB frontend API and diagnostic ioctl's
by Holger Waechtler <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <media/dvb_frontend.h>
#include "tda8083.h"
struct tda8083_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct tda8083_config* config;
struct dvb_frontend frontend;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda8083: " args); \
} while (0)
static u8 tda8083_init_tab [] = {
0x04, 0x00, 0x4a, 0x79, 0x04, 0x00, 0xff, 0xea,
0x48, 0x42, 0x79, 0x60, 0x70, 0x52, 0x9a, 0x10,
0x0e, 0x10, 0xf2, 0xa7, 0x93, 0x0b, 0x05, 0xc8,
0x9d, 0x00, 0x42, 0x80, 0x00, 0x60, 0x40, 0x00,
0x00, 0x75, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
static int tda8083_writereg (struct tda8083_state* state, u8 reg, u8 data)
{
int ret;
u8 buf [] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk ("%s: writereg error (reg %02x, ret == %i)\n",
__func__, reg, ret);
return (ret != 1) ? -1 : 0;
}
static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len)
{
int ret;
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
dprintk ("%s: readreg error (reg %02x, ret == %i)\n",
__func__, reg1, ret);
return ret == 2 ? 0 : -1;
}
static inline u8 tda8083_readreg (struct tda8083_state* state, u8 reg)
{
u8 val;
tda8083_readregs (state, reg, &val, 1);
return val;
}
static int tda8083_set_inversion(struct tda8083_state *state,
enum fe_spectral_inversion inversion)
{
/* XXX FIXME: implement other modes than FEC_AUTO */
if (inversion == INVERSION_AUTO)
return 0;
return -EINVAL;
}
static int tda8083_set_fec(struct tda8083_state *state, enum fe_code_rate fec)
{
if (fec == FEC_AUTO)
return tda8083_writereg (state, 0x07, 0xff);
if (fec >= FEC_1_2 && fec <= FEC_8_9)
return tda8083_writereg (state, 0x07, 1 << (FEC_8_9 - fec));
return -EINVAL;
}
static enum fe_code_rate tda8083_get_fec(struct tda8083_state *state)
{
u8 index;
static enum fe_code_rate fec_tab[] = {
FEC_8_9, FEC_1_2, FEC_2_3, FEC_3_4,
FEC_4_5, FEC_5_6, FEC_6_7, FEC_7_8
};
index = tda8083_readreg(state, 0x0e) & 0x07;
return fec_tab [index];
}
static int tda8083_set_symbolrate (struct tda8083_state* state, u32 srate)
{
u32 ratio;
u32 tmp;
u8 filter;
if (srate > 32000000)
srate = 32000000;
if (srate < 500000)
srate = 500000;
filter = 0;
if (srate < 24000000)
filter = 2;
if (srate < 16000000)
filter = 3;
tmp = 31250 << 16;
ratio = tmp / srate;
tmp = (tmp % srate) << 8;
ratio = (ratio << 8) + tmp / srate;
tmp = (tmp % srate) << 8;
ratio = (ratio << 8) + tmp / srate;
dprintk("tda8083: ratio == %08x\n", (unsigned int) ratio);
tda8083_writereg (state, 0x05, filter);
tda8083_writereg (state, 0x02, (ratio >> 16) & 0xff);
tda8083_writereg (state, 0x03, (ratio >> 8) & 0xff);
tda8083_writereg (state, 0x04, (ratio ) & 0xff);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 1;
}
static void tda8083_wait_diseqc_fifo (struct tda8083_state* state, int timeout)
{
unsigned long start = jiffies;
while (time_is_after_jiffies(start + timeout) &&
!(tda8083_readreg(state, 0x02) & 0x80))
{
msleep(50);
}
}
static int tda8083_set_tone(struct tda8083_state *state,
enum fe_sec_tone_mode tone)
{
tda8083_writereg (state, 0x26, 0xf1);
switch (tone) {
case SEC_TONE_OFF:
return tda8083_writereg (state, 0x29, 0x00);
case SEC_TONE_ON:
return tda8083_writereg (state, 0x29, 0x80);
default:
return -EINVAL;
}
}
static int tda8083_set_voltage(struct tda8083_state *state,
enum fe_sec_voltage voltage)
{
switch (voltage) {
case SEC_VOLTAGE_13:
return tda8083_writereg (state, 0x20, 0x00);
case SEC_VOLTAGE_18:
return tda8083_writereg (state, 0x20, 0x11);
default:
return -EINVAL;
}
}
static int tda8083_send_diseqc_burst(struct tda8083_state *state,
enum fe_sec_mini_cmd burst)
{
switch (burst) {
case SEC_MINI_A:
tda8083_writereg (state, 0x29, (5 << 2)); /* send burst A */
break;
case SEC_MINI_B:
tda8083_writereg (state, 0x29, (7 << 2)); /* send B */
break;
default:
return -EINVAL;
}
tda8083_wait_diseqc_fifo (state, 100);
return 0;
}
static int tda8083_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *m)
{
struct tda8083_state* state = fe->demodulator_priv;
int i;
tda8083_writereg (state, 0x29, (m->msg_len - 3) | (1 << 2)); /* enable */
for (i=0; i<m->msg_len; i++)
tda8083_writereg (state, 0x23 + i, m->msg[i]);
tda8083_writereg (state, 0x29, (m->msg_len - 3) | (3 << 2)); /* send!! */
tda8083_wait_diseqc_fifo (state, 100);
return 0;
}
static int tda8083_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct tda8083_state* state = fe->demodulator_priv;
u8 signal = ~tda8083_readreg (state, 0x01);
u8 sync = tda8083_readreg (state, 0x02);
*status = 0;
if (signal > 10)
*status |= FE_HAS_SIGNAL;
if (sync & 0x01)
*status |= FE_HAS_CARRIER;
if (sync & 0x02)
*status |= FE_HAS_VITERBI;
if (sync & 0x10)
*status |= FE_HAS_SYNC;
if (sync & 0x20) /* frontend can not lock */
*status |= FE_TIMEDOUT;
if ((sync & 0x1f) == 0x1f)
*status |= FE_HAS_LOCK;
return 0;
}
static int tda8083_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda8083_state* state = fe->demodulator_priv;
int ret;
u8 buf[3];
if ((ret = tda8083_readregs(state, 0x0b, buf, sizeof(buf))))
return ret;
*ber = ((buf[0] & 0x1f) << 16) | (buf[1] << 8) | buf[2];
return 0;
}
static int tda8083_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct tda8083_state* state = fe->demodulator_priv;
u8 signal = ~tda8083_readreg (state, 0x01);
*strength = (signal << 8) | signal;
return 0;
}
static int tda8083_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct tda8083_state* state = fe->demodulator_priv;
u8 _snr = tda8083_readreg (state, 0x08);
*snr = (_snr << 8) | _snr;
return 0;
}
static int tda8083_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda8083_state* state = fe->demodulator_priv;
*ucblocks = tda8083_readreg(state, 0x0f);
if (*ucblocks == 0xff)
*ucblocks = 0xffffffff;
return 0;
}
static int tda8083_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct tda8083_state* state = fe->demodulator_priv;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
tda8083_set_inversion (state, p->inversion);
tda8083_set_fec(state, p->fec_inner);
tda8083_set_symbolrate(state, p->symbol_rate);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 0;
}
static int tda8083_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct tda8083_state* state = fe->demodulator_priv;
/* FIXME: get symbolrate & frequency offset...*/
/*p->frequency = ???;*/
p->inversion = (tda8083_readreg (state, 0x0e) & 0x80) ?
INVERSION_ON : INVERSION_OFF;
p->fec_inner = tda8083_get_fec(state);
/*p->symbol_rate = tda8083_get_symbolrate (state);*/
return 0;
}
static int tda8083_sleep(struct dvb_frontend* fe)
{
struct tda8083_state* state = fe->demodulator_priv;
tda8083_writereg (state, 0x00, 0x02);
return 0;
}
static int tda8083_init(struct dvb_frontend* fe)
{
struct tda8083_state* state = fe->demodulator_priv;
int i;
for (i=0; i<44; i++)
tda8083_writereg (state, i, tda8083_init_tab[i]);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 0;
}
static int tda8083_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct tda8083_state* state = fe->demodulator_priv;
tda8083_send_diseqc_burst (state, burst);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 0;
}
static int tda8083_diseqc_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct tda8083_state* state = fe->demodulator_priv;
tda8083_set_tone (state, tone);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 0;
}
static int tda8083_diseqc_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct tda8083_state* state = fe->demodulator_priv;
tda8083_set_voltage (state, voltage);
tda8083_writereg (state, 0x00, 0x3c);
tda8083_writereg (state, 0x00, 0x04);
return 0;
}
static void tda8083_release(struct dvb_frontend* fe)
{
struct tda8083_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops tda8083_ops;
struct dvb_frontend* tda8083_attach(const struct tda8083_config* config,
struct i2c_adapter* i2c)
{
struct tda8083_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda8083_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if ((tda8083_readreg(state, 0x00)) != 0x05) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda8083_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops tda8083_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Philips TDA8083 DVB-S",
.frequency_min_hz = 920 * MHz, /* TDA8060 */
.frequency_max_hz = 2200 * MHz, /* TDA8060 */
.frequency_stepsize_hz = 125 * kHz,
.symbol_rate_min = 12000000,
.symbol_rate_max = 30000000,
/* .symbol_rate_tolerance = ???,*/
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_MUTE_TS
},
.release = tda8083_release,
.init = tda8083_init,
.sleep = tda8083_sleep,
.set_frontend = tda8083_set_frontend,
.get_frontend = tda8083_get_frontend,
.read_status = tda8083_read_status,
.read_signal_strength = tda8083_read_signal_strength,
.read_snr = tda8083_read_snr,
.read_ber = tda8083_read_ber,
.read_ucblocks = tda8083_read_ucblocks,
.diseqc_send_master_cmd = tda8083_send_diseqc_msg,
.diseqc_send_burst = tda8083_diseqc_send_burst,
.set_tone = tda8083_diseqc_set_tone,
.set_voltage = tda8083_diseqc_set_voltage,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Philips TDA8083 DVB-S Demodulator");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(tda8083_attach);
| linux-master | drivers/media/dvb-frontends/tda8083.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cxd2841er.c
*
* Sony digital demodulator driver for
* CXD2841ER - DVB-S/S2/T/T2/C/C2
* CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
*
* Copyright 2012 Sony Corporation
* Copyright (C) 2014 NetUP Inc.
* Copyright (C) 2014 Sergey Kozlov <[email protected]>
* Copyright (C) 2014 Abylay Ospan <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/math64.h>
#include <linux/log2.h>
#include <linux/dynamic_debug.h>
#include <linux/kernel.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "cxd2841er.h"
#include "cxd2841er_priv.h"
#define MAX_WRITE_REGSIZE 16
#define LOG2_E_100X 144
#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
/* DVB-C constellation */
enum sony_dvbc_constellation_t {
SONY_DVBC_CONSTELLATION_16QAM,
SONY_DVBC_CONSTELLATION_32QAM,
SONY_DVBC_CONSTELLATION_64QAM,
SONY_DVBC_CONSTELLATION_128QAM,
SONY_DVBC_CONSTELLATION_256QAM
};
enum cxd2841er_state {
STATE_SHUTDOWN = 0,
STATE_SLEEP_S,
STATE_ACTIVE_S,
STATE_SLEEP_TC,
STATE_ACTIVE_TC
};
struct cxd2841er_priv {
struct dvb_frontend frontend;
struct i2c_adapter *i2c;
u8 i2c_addr_slvx;
u8 i2c_addr_slvt;
const struct cxd2841er_config *config;
enum cxd2841er_state state;
u8 system;
enum cxd2841er_xtal xtal;
enum fe_caps caps;
u32 flags;
unsigned long stats_time;
};
static const struct cxd2841er_cnr_data s_cn_data[] = {
{ 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
{ 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
{ 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
{ 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
{ 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
{ 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
{ 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
{ 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
{ 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
{ 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
{ 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
{ 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
{ 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
{ 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
{ 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
{ 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
{ 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
{ 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
{ 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
{ 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
{ 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
{ 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
{ 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
{ 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
{ 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
{ 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
{ 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
{ 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
{ 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
{ 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
{ 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
{ 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
{ 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
{ 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
{ 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
{ 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
{ 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
{ 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
{ 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
{ 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
{ 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
{ 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
{ 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
{ 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
{ 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
{ 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
{ 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
{ 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
{ 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
{ 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
{ 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
{ 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
{ 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
{ 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
{ 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
{ 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
{ 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
{ 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
{ 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
{ 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
{ 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
{ 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
{ 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
{ 0x0015, 19900 }, { 0x0014, 20000 },
};
static const struct cxd2841er_cnr_data s2_cn_data[] = {
{ 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
{ 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
{ 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
{ 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
{ 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
{ 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
{ 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
{ 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
{ 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
{ 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
{ 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
{ 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
{ 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
{ 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
{ 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
{ 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
{ 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
{ 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
{ 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
{ 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
{ 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
{ 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
{ 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
{ 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
{ 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
{ 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
{ 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
{ 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
{ 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
{ 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
{ 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
{ 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
{ 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
{ 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
{ 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
{ 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
{ 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
{ 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
{ 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
{ 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
{ 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
{ 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
{ 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
{ 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
{ 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
{ 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
{ 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
{ 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
{ 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
{ 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
{ 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
{ 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
{ 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
{ 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
{ 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
{ 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
{ 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
{ 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
{ 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
{ 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
{ 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
{ 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
{ 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
{ 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
};
static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
u8 addr, u8 reg, u8 write,
const u8 *data, u32 len)
{
dev_dbg(&priv->i2c->dev,
"cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
(write == 0 ? "read" : "write"), addr, reg, len, len, data);
}
static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
u8 addr, u8 reg, const u8 *data, u32 len)
{
int ret;
u8 buf[MAX_WRITE_REGSIZE + 1];
u8 i2c_addr = (addr == I2C_SLVX ?
priv->i2c_addr_slvx : priv->i2c_addr_slvt);
struct i2c_msg msg[1] = {
{
.addr = i2c_addr,
.flags = 0,
.len = len + 1,
.buf = buf,
}
};
if (len + 1 >= sizeof(buf)) {
dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
reg, len + 1);
return -E2BIG;
}
cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
buf[0] = reg;
memcpy(&buf[1], data, len);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret >= 0 && ret != 1)
ret = -EIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
KBUILD_MODNAME, ret, i2c_addr, reg, len);
return ret;
}
return 0;
}
static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
u8 addr, u8 reg, u8 val)
{
u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
}
static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
u8 addr, u8 reg, u8 *val, u32 len)
{
int ret;
u8 i2c_addr = (addr == I2C_SLVX ?
priv->i2c_addr_slvx : priv->i2c_addr_slvt);
struct i2c_msg msg[2] = {
{
.addr = i2c_addr,
.flags = 0,
.len = 1,
.buf = ®,
}, {
.addr = i2c_addr,
.flags = I2C_M_RD,
.len = len,
.buf = val,
}
};
ret = i2c_transfer(priv->i2c, msg, 2);
if (ret >= 0 && ret != 2)
ret = -EIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c rd failed=%d addr=%02x reg=%02x\n",
KBUILD_MODNAME, ret, i2c_addr, reg);
return ret;
}
cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
return 0;
}
static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
u8 addr, u8 reg, u8 *val)
{
return cxd2841er_read_regs(priv, addr, reg, val, 1);
}
static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
u8 addr, u8 reg, u8 data, u8 mask)
{
int res;
u8 rdata;
if (mask != 0xff) {
res = cxd2841er_read_reg(priv, addr, reg, &rdata);
if (res)
return res;
data = ((data & mask) | (rdata & (mask ^ 0xFF)));
}
return cxd2841er_write_reg(priv, addr, reg, data);
}
static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
{
u64 tmp;
tmp = (u64) ifhz * 16777216;
do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
return (u32) tmp;
}
static u32 cxd2841er_calc_iffreq(u32 ifhz)
{
return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
}
static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
{
u32 hz;
if (priv->frontend.ops.tuner_ops.get_if_frequency
&& (priv->flags & CXD2841ER_AUTO_IFHZ))
priv->frontend.ops.tuner_ops.get_if_frequency(
&priv->frontend, &hz);
else
hz = def_hz;
return hz;
}
static int cxd2841er_tuner_set(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
u32 symbol_rate)
{
u32 reg_value = 0;
u8 data[3] = {0, 0, 0};
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
/*
* regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
* = ((symbolRateKSps * 2^14) + 500) / 1000
* = ((symbolRateKSps * 16384) + 500) / 1000
*/
reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
dev_err(&priv->i2c->dev,
"%s(): reg_value is out of range\n", __func__);
return -EINVAL;
}
data[0] = (u8)((reg_value >> 16) & 0x0F);
data[1] = (u8)((reg_value >> 8) & 0xFF);
data[2] = (u8)(reg_value & 0xFF);
/* Set SLV-T Bank : 0xAE */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
return 0;
}
static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
u8 system);
static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
u8 system, u32 symbol_rate)
{
int ret;
u8 data[4] = { 0, 0, 0, 0 };
if (priv->state != STATE_SLEEP_S) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, (int)priv->state);
return -EINVAL;
}
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
/* Set demod mode */
if (system == SYS_DVBS) {
data[0] = 0x0A;
} else if (system == SYS_DVBS2) {
data[0] = 0x0B;
} else {
dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
__func__, system);
return -EINVAL;
}
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
/* DVB-S/S2 */
data[0] = 0x00;
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable S/S2 auto detection 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
/* Set SLV-T Bank : 0xAE */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
/* Enable S/S2 auto detection 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
/* Enable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
/* Enable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
/* Enable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Enable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
/* Set SLV-T Bank : 0xA3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
data[0] = 0x07;
data[1] = 0x3B;
data[2] = 0x08;
data[3] = 0xC5;
/* Set SLV-T Bank : 0xAB */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
data[0] = 0x05;
data[1] = 0x80;
data[2] = 0x0A;
data[3] = 0x80;
cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
data[0] = 0x0C;
data[1] = 0xCC;
cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
/* Set demod parameter */
ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
if (ret != 0)
return ret;
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
/* disable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
priv->state = STATE_ACTIVE_S;
return 0;
}
static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
u32 bandwidth);
static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
u32 bandwidth);
static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
u32 bandwidth);
static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
u32 bandwidth);
static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
struct dtv_frontend_properties *p)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_S &&
priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
if (priv->state == STATE_ACTIVE_S)
return cxd2841er_dvbs2_set_symbol_rate(
priv, p->symbol_rate / 1000);
else if (priv->state == STATE_ACTIVE_TC) {
switch (priv->system) {
case SYS_DVBT:
return cxd2841er_sleep_tc_to_active_t_band(
priv, p->bandwidth_hz);
case SYS_DVBT2:
return cxd2841er_sleep_tc_to_active_t2_band(
priv, p->bandwidth_hz);
case SYS_DVBC_ANNEX_A:
return cxd2841er_sleep_tc_to_active_c_band(
priv, p->bandwidth_hz);
case SYS_ISDBT:
cxd2841er_active_i_to_sleep_tc(priv);
cxd2841er_sleep_tc_to_shutdown(priv);
cxd2841er_shutdown_to_sleep_tc(priv);
return cxd2841er_sleep_tc_to_active_i(
priv, p->bandwidth_hz);
}
}
dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_S) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
/* enable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
/* enable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* disable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
/* disable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
/* disable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
/* SADC Bias ON */
cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
/* disable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
/* Set SLV-T Bank : 0xAE */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
/* disable S/S2 auto detection1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable S/S2 auto detection2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
priv->state = STATE_SLEEP_S;
return 0;
}
static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_SLEEP_S) {
dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable DSQOUT */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
/* Disable DSQIN */
cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Disable oscillator */
cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
priv->state = STATE_SHUTDOWN;
return 0;
}
static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_SLEEP_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Disable oscillator */
cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
priv->state = STATE_SHUTDOWN;
return 0;
}
static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
/* enable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
/* enable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* disable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
/* Disable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* Disable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Disable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
priv->state = STATE_SLEEP_TC;
return 0;
}
static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
/* enable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
/* enable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
/* Cancel DVB-T2 setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* disable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
/* Disable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* Disable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Disable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
priv->state = STATE_SLEEP_TC;
return 0;
}
static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
/* enable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
/* enable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
/* Cancel DVB-C setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* disable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
/* Disable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* Disable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Disable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
priv->state = STATE_SLEEP_TC;
return 0;
}
static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* disable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
/* enable Hi-Z setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
/* enable Hi-Z setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
/* TODO: Cancel demod parameter */
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* disable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable ADC 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
/* Disable ADC 3 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* Disable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Disable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
priv->state = STATE_SLEEP_TC;
return 0;
}
static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_SHUTDOWN) {
dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Clear all demodulator registers */
cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
usleep_range(3000, 5000);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod SW reset */
cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
switch (priv->xtal) {
case SONY_XTAL_20500:
cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
break;
case SONY_XTAL_24000:
/* Select demod frequency */
cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
break;
case SONY_XTAL_41000:
cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
__func__, priv->xtal);
return -EINVAL;
}
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
/* Clear demod SW reset */
cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
usleep_range(1000, 2000);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* enable DSQOUT */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
/* enable DSQIN */
cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
/* TADC Bias On */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* SADC Bias On */
cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
priv->state = STATE_SLEEP_S;
return 0;
}
static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
{
u8 data = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_SHUTDOWN) {
dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Clear all demodulator registers */
cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
usleep_range(3000, 5000);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod SW reset */
cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
/* Select ADC clock mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
switch (priv->xtal) {
case SONY_XTAL_20500:
data = 0x0;
break;
case SONY_XTAL_24000:
/* Select demod frequency */
cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
data = 0x3;
break;
case SONY_XTAL_41000:
cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
data = 0x1;
break;
}
cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
/* Clear demod SW reset */
cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
usleep_range(1000, 2000);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* TADC Bias On */
cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
/* SADC Bias On */
cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
priv->state = STATE_SLEEP_TC;
return 0;
}
static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
{
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
/* SW Reset */
cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
/* Enable TS output */
cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
return 0;
}
/* Set TS parallel mode */
static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
u8 system)
{
u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
__func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
/*
* slave Bank Addr Bit default Name
* <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
*/
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
/*
* slave Bank Addr Bit default Name
* <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
*/
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
/*
* slave Bank Addr Bit default Name
* <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
*/
cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
/*
* Disable TS IF Clock
* slave Bank Addr Bit default Name
* <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
*/
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
/*
* slave Bank Addr Bit default Name
* <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
*/
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
/*
* Enable TS IF Clock
* slave Bank Addr Bit default Name
* <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
*/
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
if (system == SYS_DVBT) {
/* Enable parity period for DVB-T */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
} else if (system == SYS_DVBC_ANNEX_A) {
/* Enable parity period for DVB-C */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
}
}
static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
{
u8 chip_id = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
return chip_id;
}
static int cxd2841er_read_status_s(struct dvb_frontend *fe,
enum fe_status *status)
{
u8 reg = 0;
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
*status = 0;
if (priv->state != STATE_ACTIVE_S) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/* Set SLV-T Bank : 0xA0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 11h [2] ITSLOCK
*/
cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
if (reg & 0x04) {
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
}
dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
return 0;
}
static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
u8 *sync, u8 *tslock, u8 *unlock)
{
u8 data = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC)
return -EINVAL;
if (priv->system == SYS_DVBT) {
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
} else {
/* Set SLV-T Bank : 0x20 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
}
cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
if ((data & 0x07) == 0x07) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid hardware state detected\n", __func__);
*sync = 0;
*tslock = 0;
*unlock = 0;
} else {
*sync = ((data & 0x07) == 0x6 ? 1 : 0);
*tslock = ((data & 0x20) ? 1 : 0);
*unlock = ((data & 0x10) ? 1 : 0);
}
return 0;
}
static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
{
u8 data;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC)
return -EINVAL;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
if ((data & 0x01) == 0) {
*tslock = 0;
} else {
cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
*tslock = ((data & 0x20) ? 1 : 0);
}
return 0;
}
static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
u8 *sync, u8 *tslock, u8 *unlock)
{
u8 data = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC)
return -EINVAL;
/* Set SLV-T Bank : 0x60 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
dev_dbg(&priv->i2c->dev,
"%s(): lock=0x%x\n", __func__, data);
*sync = ((data & 0x02) ? 1 : 0);
*tslock = ((data & 0x01) ? 1 : 0);
*unlock = ((data & 0x10) ? 1 : 0);
return 0;
}
static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
enum fe_status *status)
{
int ret = 0;
u8 sync = 0;
u8 tslock = 0;
u8 unlock = 0;
struct cxd2841er_priv *priv = fe->demodulator_priv;
*status = 0;
if (priv->state == STATE_ACTIVE_TC) {
if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
ret = cxd2841er_read_status_t_t2(
priv, &sync, &tslock, &unlock);
if (ret)
goto done;
if (unlock)
goto done;
if (sync)
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER |
FE_HAS_VITERBI |
FE_HAS_SYNC;
if (tslock)
*status |= FE_HAS_LOCK;
} else if (priv->system == SYS_ISDBT) {
ret = cxd2841er_read_status_i(
priv, &sync, &tslock, &unlock);
if (ret)
goto done;
if (unlock)
goto done;
if (sync)
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER |
FE_HAS_VITERBI |
FE_HAS_SYNC;
if (tslock)
*status |= FE_HAS_LOCK;
} else if (priv->system == SYS_DVBC_ANNEX_A) {
ret = cxd2841er_read_status_c(priv, &tslock);
if (ret)
goto done;
if (tslock)
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER |
FE_HAS_VITERBI |
FE_HAS_SYNC |
FE_HAS_LOCK;
}
}
done:
dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
return ret;
}
static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
int *offset)
{
u8 data[3];
u8 is_hs_mode;
s32 cfrl_ctrlval;
s32 temp_div, temp_q, temp_r;
if (priv->state != STATE_ACTIVE_S) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
/*
* Get High Sampling Rate mode
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 10h [0] ITRL_LOCK
*/
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
if (data[0] & 0x01) {
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 50h [4] IHSMODE
*/
cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
is_hs_mode = (data[0] & 0x10 ? 1 : 0);
} else {
dev_dbg(&priv->i2c->dev,
"%s(): unable to detect sampling rate mode\n",
__func__);
return -EINVAL;
}
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
* <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
* <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
*/
cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
(((u32)data[1] & 0xFF) << 8) |
((u32)data[2] & 0xFF), 20);
temp_div = (is_hs_mode ? 1048576 : 1572864);
if (cfrl_ctrlval > 0) {
temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
temp_div, &temp_r);
} else {
temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
temp_div, &temp_r);
}
if (temp_r >= temp_div / 2)
temp_q++;
if (cfrl_ctrlval > 0)
temp_q *= -1;
*offset = temp_q;
return 0;
}
static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
u32 bandwidth, int *offset)
{
u8 data[4];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
if (priv->system != SYS_ISDBT) {
dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
*offset = -1 * sign_extend32(
((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
((u32)data[2] << 8) | (u32)data[3], 29);
switch (bandwidth) {
case 6000000:
*offset = -1 * ((*offset) * 8/264);
break;
case 7000000:
*offset = -1 * ((*offset) * 8/231);
break;
case 8000000:
*offset = -1 * ((*offset) * 8/198);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
__func__, bandwidth);
return -EINVAL;
}
dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
__func__, bandwidth, *offset);
return 0;
}
static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
u32 bandwidth, int *offset)
{
u8 data[4];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
if (priv->system != SYS_DVBT) {
dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
*offset = -1 * sign_extend32(
((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
((u32)data[2] << 8) | (u32)data[3], 29);
*offset *= (bandwidth / 1000000);
*offset /= 235;
return 0;
}
static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
u32 bandwidth, int *offset)
{
u8 data[4];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
if (priv->system != SYS_DVBT2) {
dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
*offset = -1 * sign_extend32(
((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
((u32)data[2] << 8) | (u32)data[3], 27);
switch (bandwidth) {
case 1712000:
*offset /= 582;
break;
case 5000000:
case 6000000:
case 7000000:
case 8000000:
*offset *= (bandwidth / 1000000);
*offset /= 940;
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
__func__, bandwidth);
return -EINVAL;
}
return 0;
}
static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
int *offset)
{
u8 data[2];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
if (priv->system != SYS_DVBC_ANNEX_A) {
dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
*offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
| (u32)data[1], 13), 16384);
return 0;
}
static int cxd2841er_read_packet_errors_c(
struct cxd2841er_priv *priv, u32 *penum)
{
u8 data[3];
*penum = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
if (data[2] & 0x01)
*penum = ((u32)data[0] << 8) | (u32)data[1];
return 0;
}
static int cxd2841er_read_packet_errors_t(
struct cxd2841er_priv *priv, u32 *penum)
{
u8 data[3];
*penum = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
if (data[2] & 0x01)
*penum = ((u32)data[0] << 8) | (u32)data[1];
return 0;
}
static int cxd2841er_read_packet_errors_t2(
struct cxd2841er_priv *priv, u32 *penum)
{
u8 data[3];
*penum = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
if (data[0] & 0x01)
*penum = ((u32)data[1] << 8) | (u32)data[2];
return 0;
}
static int cxd2841er_read_packet_errors_i(
struct cxd2841er_priv *priv, u32 *penum)
{
u8 data[2];
*penum = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
if (!(data[0] & 0x01))
return 0;
/* Layer A */
cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
*penum = ((u32)data[0] << 8) | (u32)data[1];
/* Layer B */
cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
*penum += ((u32)data[0] << 8) | (u32)data[1];
/* Layer C */
cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
*penum += ((u32)data[0] << 8) | (u32)data[1];
return 0;
}
static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[3];
u32 bit_err, period_exp;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
if (!(data[0] & 0x80)) {
dev_dbg(&priv->i2c->dev,
"%s(): no valid BER data\n", __func__);
return -EINVAL;
}
bit_err = ((u32)(data[0] & 0x3f) << 16) |
((u32)data[1] << 8) |
(u32)data[2];
cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
period_exp = data[0] & 0x1f;
if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
dev_dbg(&priv->i2c->dev,
"%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
__func__, period_exp, bit_err);
return -EINVAL;
}
dev_dbg(&priv->i2c->dev,
"%s(): period_exp(%u) or bit_err(%u) count=%d\n",
__func__, period_exp, bit_err,
((1 << period_exp) * 204 * 8));
*bit_error = bit_err;
*bit_count = ((1 << period_exp) * 204 * 8);
return 0;
}
static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[3];
u8 pktnum[2];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_freeze_regs(priv);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
cxd2841er_unfreeze_regs(priv);
if (!pktnum[0] && !pktnum[1]) {
dev_dbg(&priv->i2c->dev,
"%s(): no valid BER data\n", __func__);
return -EINVAL;
}
*bit_error = ((u32)(data[0] & 0x7F) << 16) |
((u32)data[1] << 8) | data[2];
*bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
__func__, *bit_error, *bit_count);
return 0;
}
static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[11];
/* Set SLV-T Bank : 0xA0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 35h [0] IFVBER_VALID
* <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
* <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
* <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
* <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
* <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
* <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
*/
cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
if (data[0] & 0x01) {
*bit_error = ((u32)(data[1] & 0x3F) << 16) |
((u32)(data[2] & 0xFF) << 8) |
(u32)(data[3] & 0xFF);
*bit_count = ((u32)(data[8] & 0x3F) << 16) |
((u32)(data[9] & 0xFF) << 8) |
(u32)(data[10] & 0xFF);
if ((*bit_count == 0) || (*bit_error > *bit_count)) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid bit_error %d, bit_count %d\n",
__func__, *bit_error, *bit_count);
return -EINVAL;
}
return 0;
}
dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
return -EINVAL;
}
static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[5];
u32 period;
/* Set SLV-T Bank : 0xB2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
/*
* slave Bank Addr Bit Signal name
* <SLV-T> B2h 30h [0] IFLBER_VALID
* <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
* <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
* <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
* <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
*/
cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
if (data[0] & 0x01) {
/* Bit error count */
*bit_error = ((u32)(data[1] & 0x0F) << 24) |
((u32)(data[2] & 0xFF) << 16) |
((u32)(data[3] & 0xFF) << 8) |
(u32)(data[4] & 0xFF);
/* Set SLV-T Bank : 0xA0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
/* Measurement period */
period = (u32)(1 << (data[0] & 0x0F));
if (period == 0) {
dev_dbg(&priv->i2c->dev,
"%s(): period is 0\n", __func__);
return -EINVAL;
}
if (*bit_error > (period * 64800)) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid bit_err 0x%x period 0x%x\n",
__func__, *bit_error, period);
return -EINVAL;
}
*bit_count = period * 64800;
return 0;
} else {
dev_dbg(&priv->i2c->dev,
"%s(): no data available\n", __func__);
}
return -EINVAL;
}
static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[4];
u32 period_exp, n_ldpc;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n", __func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
if (!(data[0] & 0x10)) {
dev_dbg(&priv->i2c->dev,
"%s(): no valid BER data\n", __func__);
return -EINVAL;
}
*bit_error = ((u32)(data[0] & 0x0f) << 24) |
((u32)data[1] << 16) |
((u32)data[2] << 8) |
(u32)data[3];
cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
period_exp = data[0] & 0x0f;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
if (*bit_error > ((1U << period_exp) * n_ldpc)) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid BER value\n", __func__);
return -EINVAL;
}
/*
* FIXME: the right thing would be to return bit_error untouched,
* but, as we don't know the scale returned by the counters, let's
* at least preserver BER = bit_error/bit_count.
*/
if (period_exp >= 4) {
*bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
*bit_error *= 3125ULL;
} else {
*bit_count = (1U << period_exp) * (n_ldpc / 200);
*bit_error *= 50000ULL;
}
return 0;
}
static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
u32 *bit_error, u32 *bit_count)
{
u8 data[2];
u32 period;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n", __func__, priv->state);
return -EINVAL;
}
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
if (!(data[0] & 0x01)) {
dev_dbg(&priv->i2c->dev,
"%s(): no valid BER data\n", __func__);
return 0;
}
cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
*bit_error = ((u32)data[0] << 8) | (u32)data[1];
cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
/*
* FIXME: the right thing would be to return bit_error untouched,
* but, as we don't know the scale returned by the counters, let's
* at least preserver BER = bit_error/bit_count.
*/
*bit_count = period / 128;
*bit_error *= 78125ULL;
return 0;
}
static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
{
/*
* Freeze registers: ensure multiple separate register reads
* are from the same snapshot
*/
cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
return 0;
}
static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
{
/*
* un-freeze registers
*/
cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
return 0;
}
static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
u8 delsys, u32 *snr)
{
u8 data[3];
u32 res = 0, value;
int min_index, max_index, index;
static const struct cxd2841er_cnr_data *cn_data;
cxd2841er_freeze_regs(priv);
/* Set SLV-T Bank : 0xA1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A1h 10h [0] ICPM_QUICKRDY
* <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
* <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
*/
cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
cxd2841er_unfreeze_regs(priv);
if (data[0] & 0x01) {
value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
min_index = 0;
if (delsys == SYS_DVBS) {
cn_data = s_cn_data;
max_index = ARRAY_SIZE(s_cn_data) - 1;
} else {
cn_data = s2_cn_data;
max_index = ARRAY_SIZE(s2_cn_data) - 1;
}
if (value >= cn_data[min_index].value) {
res = cn_data[min_index].cnr_x1000;
goto done;
}
if (value <= cn_data[max_index].value) {
res = cn_data[max_index].cnr_x1000;
goto done;
}
while ((max_index - min_index) > 1) {
index = (max_index + min_index) / 2;
if (value == cn_data[index].value) {
res = cn_data[index].cnr_x1000;
goto done;
} else if (value > cn_data[index].value)
max_index = index;
else
min_index = index;
if ((max_index - min_index) <= 1) {
if (value == cn_data[max_index].value) {
res = cn_data[max_index].cnr_x1000;
goto done;
} else {
res = cn_data[min_index].cnr_x1000;
goto done;
}
}
}
} else {
dev_dbg(&priv->i2c->dev,
"%s(): no data available\n", __func__);
return -EINVAL;
}
done:
*snr = res;
return 0;
}
static uint32_t sony_log(uint32_t x)
{
return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
}
static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
{
u32 reg;
u8 data[2];
enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
*snr = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
cxd2841er_freeze_regs(priv);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
cxd2841er_unfreeze_regs(priv);
reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
if (reg == 0) {
dev_dbg(&priv->i2c->dev,
"%s(): reg value out of range\n", __func__);
return 0;
}
switch (qam) {
case SONY_DVBC_CONSTELLATION_16QAM:
case SONY_DVBC_CONSTELLATION_64QAM:
case SONY_DVBC_CONSTELLATION_256QAM:
/* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
if (reg < 126)
reg = 126;
*snr = -95 * (int32_t)sony_log(reg) + 95941;
break;
case SONY_DVBC_CONSTELLATION_32QAM:
case SONY_DVBC_CONSTELLATION_128QAM:
/* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
if (reg < 69)
reg = 69;
*snr = -88 * (int32_t)sony_log(reg) + 86999;
break;
default:
return -EINVAL;
}
return 0;
}
static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
{
u32 reg;
u8 data[2];
*snr = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n", __func__, priv->state);
return -EINVAL;
}
cxd2841er_freeze_regs(priv);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
cxd2841er_unfreeze_regs(priv);
reg = ((u32)data[0] << 8) | (u32)data[1];
if (reg == 0) {
dev_dbg(&priv->i2c->dev,
"%s(): reg value out of range\n", __func__);
return 0;
}
if (reg > 4996)
reg = 4996;
*snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
return 0;
}
static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
{
u32 reg;
u8 data[2];
*snr = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n", __func__, priv->state);
return -EINVAL;
}
cxd2841er_freeze_regs(priv);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
cxd2841er_unfreeze_regs(priv);
reg = ((u32)data[0] << 8) | (u32)data[1];
if (reg == 0) {
dev_dbg(&priv->i2c->dev,
"%s(): reg value out of range\n", __func__);
return 0;
}
if (reg > 10876)
reg = 10876;
*snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
return 0;
}
static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
{
u32 reg;
u8 data[2];
*snr = 0;
if (priv->state != STATE_ACTIVE_TC) {
dev_dbg(&priv->i2c->dev,
"%s(): invalid state %d\n", __func__,
priv->state);
return -EINVAL;
}
cxd2841er_freeze_regs(priv);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
cxd2841er_unfreeze_regs(priv);
reg = ((u32)data[0] << 8) | (u32)data[1];
if (reg == 0) {
dev_dbg(&priv->i2c->dev,
"%s(): reg value out of range\n", __func__);
return 0;
}
*snr = 10000 * (intlog10(reg) >> 24) - 9031;
return 0;
}
static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
u8 delsys)
{
u8 data[2];
cxd2841er_write_reg(
priv, I2C_SLVT, 0x00, 0x40);
cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
dev_dbg(&priv->i2c->dev,
"%s(): AGC value=%u\n",
__func__, (((u16)data[0] & 0x0F) << 8) |
(u16)(data[1] & 0xFF));
return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
}
static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
u8 delsys)
{
u8 data[2];
cxd2841er_write_reg(
priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
dev_dbg(&priv->i2c->dev,
"%s(): AGC value=%u\n",
__func__, (((u16)data[0] & 0x0F) << 8) |
(u16)(data[1] & 0xFF));
return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
}
static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
u8 delsys)
{
u8 data[2];
cxd2841er_write_reg(
priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
dev_dbg(&priv->i2c->dev,
"%s(): AGC value=%u\n",
__func__, (((u16)data[0] & 0x0F) << 8) |
(u16)(data[1] & 0xFF));
return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
}
static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
{
u8 data[2];
/* Set SLV-T Bank : 0xA0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
/*
* slave Bank Addr Bit Signal name
* <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
* <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
*/
cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
}
static void cxd2841er_read_ber(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cxd2841er_priv *priv = fe->demodulator_priv;
u32 ret, bit_error = 0, bit_count = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
switch (p->delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_B:
case SYS_DVBC_ANNEX_C:
ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
break;
case SYS_ISDBT:
ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
break;
case SYS_DVBS:
ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
break;
case SYS_DVBS2:
ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
break;
case SYS_DVBT:
ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
break;
case SYS_DVBT2:
ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
break;
default:
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
if (!ret) {
p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_error.stat[0].uvalue += bit_error;
p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_count.stat[0].uvalue += bit_count;
} else {
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
}
static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cxd2841er_priv *priv = fe->demodulator_priv;
s32 strength;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
switch (p->delivery_system) {
case SYS_DVBT:
case SYS_DVBT2:
strength = cxd2841er_read_agc_gain_t_t2(priv,
p->delivery_system);
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
/* Formula was empirically determinated @ 410 MHz */
p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
break; /* Code moved out of the function */
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_B:
case SYS_DVBC_ANNEX_C:
strength = cxd2841er_read_agc_gain_c(priv,
p->delivery_system);
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
/*
* Formula was empirically determinated via linear regression,
* using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
* stream modulated with QAM64
*/
p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
break;
case SYS_ISDBT:
strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
/*
* Formula was empirically determinated via linear regression,
* using frequencies: 175 MHz, 410 MHz and 800 MHz.
*/
p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
break;
case SYS_DVBS:
case SYS_DVBS2:
strength = 65535 - cxd2841er_read_agc_gain_s(priv);
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->strength.stat[0].uvalue = strength;
break;
default:
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
}
static void cxd2841er_read_snr(struct dvb_frontend *fe)
{
u32 tmp = 0;
int ret = 0;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
switch (p->delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_B:
case SYS_DVBC_ANNEX_C:
ret = cxd2841er_read_snr_c(priv, &tmp);
break;
case SYS_DVBT:
ret = cxd2841er_read_snr_t(priv, &tmp);
break;
case SYS_DVBT2:
ret = cxd2841er_read_snr_t2(priv, &tmp);
break;
case SYS_ISDBT:
ret = cxd2841er_read_snr_i(priv, &tmp);
break;
case SYS_DVBS:
case SYS_DVBS2:
ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
__func__, p->delivery_system);
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
__func__, (int32_t)tmp);
if (!ret) {
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = tmp;
} else {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
}
static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cxd2841er_priv *priv = fe->demodulator_priv;
u32 ucblocks = 0;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
switch (p->delivery_system) {
case SYS_DVBC_ANNEX_A:
case SYS_DVBC_ANNEX_B:
case SYS_DVBC_ANNEX_C:
cxd2841er_read_packet_errors_c(priv, &ucblocks);
break;
case SYS_DVBT:
cxd2841er_read_packet_errors_t(priv, &ucblocks);
break;
case SYS_DVBT2:
cxd2841er_read_packet_errors_t2(priv, &ucblocks);
break;
case SYS_ISDBT:
cxd2841er_read_packet_errors_i(priv, &ucblocks);
break;
default:
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return;
}
dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_error.stat[0].uvalue = ucblocks;
}
static int cxd2841er_dvbt2_set_profile(
struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
{
u8 tune_mode;
u8 seq_not2d_time;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
switch (profile) {
case DVBT2_PROFILE_BASE:
tune_mode = 0x01;
/* Set early unlock time */
seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
break;
case DVBT2_PROFILE_LITE:
tune_mode = 0x05;
/* Set early unlock time */
seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
break;
case DVBT2_PROFILE_ANY:
tune_mode = 0x00;
/* Set early unlock time */
seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
break;
default:
return -EINVAL;
}
/* Set SLV-T Bank : 0x2E */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
/* Set profile and tune mode */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
/* Set SLV-T Bank : 0x2B */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
/* Set early unlock detection time */
cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
return 0;
}
static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
u8 is_auto, u8 plp_id)
{
if (is_auto) {
dev_dbg(&priv->i2c->dev,
"%s() using auto PLP selection\n", __func__);
} else {
dev_dbg(&priv->i2c->dev,
"%s() using manual PLP selection, ID %d\n",
__func__, plp_id);
}
/* Set SLV-T Bank : 0x23 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
if (!is_auto) {
/* Manual PLP selection mode. Set the data PLP Id. */
cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
}
/* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
return 0;
}
static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u32 iffreq, ifhz;
u8 data[MAX_WRITE_REGSIZE];
static const uint8_t nominalRate8bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const uint8_t nominalRate7bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const uint8_t nominalRate6bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
{0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
};
static const uint8_t nominalRate5bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
{0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
{0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
};
static const uint8_t nominalRate17bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
{0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
{0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
};
static const uint8_t itbCoef8bw[3][14] = {
{0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
{0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
{0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
};
static const uint8_t itbCoef7bw[3][14] = {
{0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
{0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
{0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
};
static const uint8_t itbCoef6bw[3][14] = {
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
{0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
};
static const uint8_t itbCoef5bw[3][14] = {
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
{0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
};
static const uint8_t itbCoef17bw[3][14] = {
{0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
{0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
{0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
};
/* Set SLV-T Bank : 0x20 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
switch (bandwidth) {
case 8000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate8bw[priv->xtal], 5);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_set_reg_bits(priv, I2C_SLVT,
0x7a, 0x00, 0x0f);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef8bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 4800000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x00, 0x07);
break;
case 7000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate7bw[priv->xtal], 5);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_set_reg_bits(priv, I2C_SLVT,
0x7a, 0x00, 0x0f);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef7bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 4200000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x02, 0x07);
break;
case 6000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate6bw[priv->xtal], 5);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_set_reg_bits(priv, I2C_SLVT,
0x7a, 0x00, 0x0f);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef6bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 3600000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x04, 0x07);
break;
case 5000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate5bw[priv->xtal], 5);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_set_reg_bits(priv, I2C_SLVT,
0x7a, 0x00, 0x0f);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef5bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 3600000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x06, 0x07);
break;
case 1712000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate17bw[priv->xtal], 5);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_set_reg_bits(priv, I2C_SLVT,
0x7a, 0x03, 0x0f);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef17bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 3500000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x03, 0x07);
break;
default:
return -EINVAL;
}
return 0;
}
static int cxd2841er_sleep_tc_to_active_t_band(
struct cxd2841er_priv *priv, u32 bandwidth)
{
u8 data[MAX_WRITE_REGSIZE];
u32 iffreq, ifhz;
static const u8 nominalRate8bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const u8 nominalRate7bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const u8 nominalRate6bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
{0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
};
static const u8 nominalRate5bw[3][5] = {
/* TRCG Nominal Rate [37:0] */
{0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
{0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
{0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
};
static const u8 itbCoef8bw[3][14] = {
{0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
{0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
{0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
};
static const u8 itbCoef7bw[3][14] = {
{0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
{0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
{0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
};
static const u8 itbCoef6bw[3][14] = {
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
{0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
};
static const u8 itbCoef5bw[3][14] = {
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
{0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
};
/* Set SLV-T Bank : 0x13 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
/* Echo performance optimization setting */
data[0] = 0x01;
data[1] = 0x14;
cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
switch (bandwidth) {
case 8000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate8bw[priv->xtal], 5);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef8bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 4800000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x00, 0x07);
/* Demod core latency setting */
if (priv->xtal == SONY_XTAL_24000) {
data[0] = 0x15;
data[1] = 0x28;
} else {
data[0] = 0x01;
data[1] = 0xE0;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Notch filter setting */
data[0] = 0x01;
data[1] = 0x02;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
break;
case 7000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate7bw[priv->xtal], 5);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef7bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 4200000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x02, 0x07);
/* Demod core latency setting */
if (priv->xtal == SONY_XTAL_24000) {
data[0] = 0x1F;
data[1] = 0xF8;
} else {
data[0] = 0x12;
data[1] = 0xF8;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Notch filter setting */
data[0] = 0x00;
data[1] = 0x03;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
break;
case 6000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate6bw[priv->xtal], 5);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef6bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 3600000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x04, 0x07);
/* Demod core latency setting */
if (priv->xtal == SONY_XTAL_24000) {
data[0] = 0x25;
data[1] = 0x4C;
} else {
data[0] = 0x1F;
data[1] = 0xDC;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Notch filter setting */
data[0] = 0x00;
data[1] = 0x03;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
break;
case 5000000:
/* <Timing Recovery setting> */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate5bw[priv->xtal], 5);
/* Group delay equaliser settings for
* ASCOT2D, ASCOT2E and ASCOT3 tuners
*/
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef5bw[priv->xtal], 14);
/* <IF freq setting> */
ifhz = cxd2841er_get_if_hz(priv, 3600000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xD7, 0x06, 0x07);
/* Demod core latency setting */
if (priv->xtal == SONY_XTAL_24000) {
data[0] = 0x2C;
data[1] = 0xC2;
} else {
data[0] = 0x26;
data[1] = 0x3C;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Notch filter setting */
data[0] = 0x00;
data[1] = 0x03;
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
break;
}
return 0;
}
static int cxd2841er_sleep_tc_to_active_i_band(
struct cxd2841er_priv *priv, u32 bandwidth)
{
u32 iffreq, ifhz;
u8 data[3];
/* TRCG Nominal Rate */
static const u8 nominalRate8bw[3][5] = {
{0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const u8 nominalRate7bw[3][5] = {
{0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const u8 nominalRate6bw[3][5] = {
{0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
{0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
{0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
};
static const u8 itbCoef8bw[3][14] = {
{0x00}, /* 20.5MHz XTal */
{0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
{0x0}, /* 41MHz XTal */
};
static const u8 itbCoef7bw[3][14] = {
{0x00}, /* 20.5MHz XTal */
{0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
{0x00}, /* 41MHz XTal */
};
static const u8 itbCoef6bw[3][14] = {
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
{0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
{0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
};
dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* 20.5/41MHz Xtal support is not available
* on ISDB-T 7MHzBW and 8MHzBW
*/
if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
dev_err(&priv->i2c->dev,
"%s(): bandwidth %d supported only for 24MHz xtal\n",
__func__, bandwidth);
return -EINVAL;
}
switch (bandwidth) {
case 8000000:
/* TRCG Nominal Rate */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate8bw[priv->xtal], 5);
/* Group delay equaliser settings for ASCOT tuners optimized */
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef8bw[priv->xtal], 14);
/* IF freq setting */
ifhz = cxd2841er_get_if_hz(priv, 4750000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
/* Demod core latency setting */
data[0] = 0x13;
data[1] = 0xFC;
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Acquisition optimization setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
break;
case 7000000:
/* TRCG Nominal Rate */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate7bw[priv->xtal], 5);
/* Group delay equaliser settings for ASCOT tuners optimized */
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef7bw[priv->xtal], 14);
/* IF freq setting */
ifhz = cxd2841er_get_if_hz(priv, 4150000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
/* Demod core latency setting */
data[0] = 0x1A;
data[1] = 0xFA;
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Acquisition optimization setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
break;
case 6000000:
/* TRCG Nominal Rate */
cxd2841er_write_regs(priv, I2C_SLVT,
0x9F, nominalRate6bw[priv->xtal], 5);
/* Group delay equaliser settings for ASCOT tuners optimized */
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(priv, I2C_SLVT,
0xA6, itbCoef6bw[priv->xtal], 14);
/* IF freq setting */
ifhz = cxd2841er_get_if_hz(priv, 3550000);
iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
data[0] = (u8) ((iffreq >> 16) & 0xff);
data[1] = (u8)((iffreq >> 8) & 0xff);
data[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
/* System bandwidth setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
/* Demod core latency setting */
if (priv->xtal == SONY_XTAL_24000) {
data[0] = 0x1F;
data[1] = 0x79;
} else {
data[0] = 0x1A;
data[1] = 0xE2;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Acquisition optimization setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
__func__, bandwidth);
return -EINVAL;
}
return 0;
}
static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u8 bw7_8mhz_b10_a6[] = {
0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
u8 bw6mhz_b10_a6[] = {
0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
u8 b10_b6[3];
u32 iffreq, ifhz;
if (bandwidth != 6000000 &&
bandwidth != 7000000 &&
bandwidth != 8000000) {
dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
__func__, bandwidth);
bandwidth = 8000000;
}
dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
switch (bandwidth) {
case 8000000:
case 7000000:
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(
priv, I2C_SLVT, 0xa6,
bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
ifhz = cxd2841er_get_if_hz(priv, 4900000);
iffreq = cxd2841er_calc_iffreq(ifhz);
break;
case 6000000:
if (priv->flags & CXD2841ER_ASCOT)
cxd2841er_write_regs(
priv, I2C_SLVT, 0xa6,
bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
ifhz = cxd2841er_get_if_hz(priv, 3700000);
iffreq = cxd2841er_calc_iffreq(ifhz);
break;
default:
dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
__func__, bandwidth);
return -EINVAL;
}
/* <IF freq setting> */
b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
b10_b6[2] = (u8)(iffreq & 0xff);
cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
/* Set SLV-T Bank : 0x11 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
switch (bandwidth) {
case 8000000:
case 7000000:
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
break;
case 6000000:
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
break;
}
/* Set SLV-T Bank : 0x40 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
switch (bandwidth) {
case 8000000:
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
break;
case 7000000:
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0x26, 0x09, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
break;
case 6000000:
cxd2841er_set_reg_bits(
priv, I2C_SLVT, 0x26, 0x08, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
break;
}
return 0;
}
static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u8 data[2] = { 0x09, 0x54 };
u8 data24m[3] = {0xDC, 0x6C, 0x00};
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Enable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Enable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
/* Enable ADC 2 & 3 */
if (priv->xtal == SONY_XTAL_41000) {
data[0] = 0x0A;
data[1] = 0xD4;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
/* Enable ADC 4 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* IFAGC gain settings */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
/* Set SLV-T Bank : 0x11 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
/* BBAGC TARGET level setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* ASCOT setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
/* Set SLV-T Bank : 0x18 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
/* Pre-RS BER monitor setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
/* FEC Auto Recovery setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* TSIF setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
if (priv->xtal == SONY_XTAL_24000) {
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
}
cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable HiZ Setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
/* Disable HiZ Setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
priv->state = STATE_ACTIVE_TC;
return 0;
}
static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u8 data[MAX_WRITE_REGSIZE];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Enable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Enable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
if (priv->xtal == SONY_XTAL_41000) {
data[0] = 0x0A;
data[1] = 0xD4;
} else {
data[0] = 0x09;
data[1] = 0x54;
}
cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
/* Enable ADC 4 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* IFAGC gain settings */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
/* Set SLV-T Bank : 0x11 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
/* BBAGC TARGET level setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* ASCOT setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
/* Set SLV-T Bank : 0x20 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
/* Acquisition optimization setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
/* Set SLV-T Bank : 0x2b */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
/* Set SLV-T Bank : 0x23 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
/* L1 Control setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* TSIF setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
/* DVB-T2 initial setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
/* Set SLV-T Bank : 0x2a */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
/* Set SLV-T Bank : 0x2b */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
/* 24MHz Xtal setting */
if (priv->xtal == SONY_XTAL_24000) {
/* Set SLV-T Bank : 0x11 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
data[0] = 0xEB;
data[1] = 0x03;
data[2] = 0x3B;
cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
/* Set SLV-T Bank : 0x20 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
data[0] = 0x5E;
data[1] = 0x5E;
data[2] = 0x47;
cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
data[0] = 0x3F;
data[1] = 0xFF;
cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
/* Set SLV-T Bank : 0x24 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
data[0] = 0x0B;
data[1] = 0x72;
cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
data[0] = 0x93;
data[1] = 0xF3;
data[2] = 0x00;
cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
data[0] = 0x05;
data[1] = 0xB8;
data[2] = 0xD8;
cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
/* Set SLV-T Bank : 0x25 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
/* Set SLV-T Bank : 0x27 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
/* Set SLV-T Bank : 0x2B */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
/* Set SLV-T Bank : 0x2D */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
data[0] = 0x89;
data[1] = 0x89;
cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
/* Set SLV-T Bank : 0x5E */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
data[0] = 0x24;
data[1] = 0x95;
cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
}
cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable HiZ Setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
/* Disable HiZ Setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
priv->state = STATE_ACTIVE_TC;
return 0;
}
/* ISDB-Tb part */
static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u8 data[2] = { 0x09, 0x54 };
u8 data24m[2] = {0x60, 0x00};
u8 data24m2[3] = {0xB7, 0x1B, 0x00};
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
/* Enable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
/* Enable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Enable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
/* xtal freq 20.5MHz or 24M */
cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
/* Enable ADC 4 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
/* ASCOT setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
/* FEC Auto Recovery setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
/* ISDB-T initial setting */
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
/* Set SLV-T Bank : 0x15 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
/* Set SLV-T Bank : 0x1E */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
/* Set SLV-T Bank : 0x63 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
/* for xtal 24MHz */
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
/* Set SLV-T Bank : 0x60 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable HiZ Setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
/* Disable HiZ Setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
priv->state = STATE_ACTIVE_TC;
return 0;
}
static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
u32 bandwidth)
{
u8 data[2] = { 0x09, 0x54 };
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
/* Set SLV-X Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
/* Set demod mode */
cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Enable demod clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
/* Disable RF level monitor */
cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
/* Enable ADC clock */
cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
/* Enable ADC 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
/* xtal freq 20.5MHz */
cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
/* Enable ADC 4 */
cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* IFAGC gain settings */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
/* Set SLV-T Bank : 0x11 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
/* BBAGC TARGET level setting */
cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
/* Set SLV-T Bank : 0x10 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
/* ASCOT setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
/* Set SLV-T Bank : 0x40 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
/* Demod setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* TSIF setting */
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
/* Set SLV-T Bank : 0x00 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
/* Disable HiZ Setting 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
/* Disable HiZ Setting 2 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
priv->state = STATE_ACTIVE_TC;
return 0;
}
static int cxd2841er_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
enum fe_status status = 0;
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_ACTIVE_S)
cxd2841er_read_status_s(fe, &status);
else if (priv->state == STATE_ACTIVE_TC)
cxd2841er_read_status_tc(fe, &status);
if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
cxd2841er_read_signal_strength(fe);
else
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (status & FE_HAS_LOCK) {
if (priv->stats_time &&
(!time_after(jiffies, priv->stats_time)))
return 0;
/* Prevent retrieving stats faster than once per second */
priv->stats_time = jiffies + msecs_to_jiffies(1000);
cxd2841er_read_snr(fe);
cxd2841er_read_ucblocks(fe);
cxd2841er_read_ber(fe);
} else {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
{
int ret = 0, i, timeout, carr_offset;
enum fe_status status;
struct cxd2841er_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u32 symbol_rate = p->symbol_rate/1000;
dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
__func__,
(p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
p->frequency, symbol_rate, priv->xtal);
if (priv->flags & CXD2841ER_EARLY_TUNE)
cxd2841er_tuner_set(fe);
switch (priv->state) {
case STATE_SLEEP_S:
ret = cxd2841er_sleep_s_to_active_s(
priv, p->delivery_system, symbol_rate);
break;
case STATE_ACTIVE_S:
ret = cxd2841er_retune_active(priv, p);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
ret = -EINVAL;
goto done;
}
if (ret) {
dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
goto done;
}
if (!(priv->flags & CXD2841ER_EARLY_TUNE))
cxd2841er_tuner_set(fe);
cxd2841er_tune_done(priv);
timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150;
i = 0;
do {
usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
(CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
cxd2841er_read_status_s(fe, &status);
if (status & FE_HAS_LOCK)
break;
i++;
} while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
if (status & FE_HAS_LOCK) {
if (cxd2841er_get_carrier_offset_s_s2(
priv, &carr_offset)) {
ret = -EINVAL;
goto done;
}
dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
__func__, carr_offset);
}
done:
/* Reset stats */
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* Reset the wait for jiffies logic */
priv->stats_time = 0;
return ret;
}
static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
{
int ret = 0, timeout;
enum fe_status status;
struct cxd2841er_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
__func__, p->delivery_system, p->bandwidth_hz);
if (priv->flags & CXD2841ER_EARLY_TUNE)
cxd2841er_tuner_set(fe);
/* deconfigure/put demod to sleep on delsys switch if active */
if (priv->state == STATE_ACTIVE_TC &&
priv->system != p->delivery_system) {
dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
__func__, priv->system, p->delivery_system);
cxd2841er_sleep_tc(fe);
}
if (p->delivery_system == SYS_DVBT) {
priv->system = SYS_DVBT;
switch (priv->state) {
case STATE_SLEEP_TC:
ret = cxd2841er_sleep_tc_to_active_t(
priv, p->bandwidth_hz);
break;
case STATE_ACTIVE_TC:
ret = cxd2841er_retune_active(priv, p);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
ret = -EINVAL;
}
} else if (p->delivery_system == SYS_DVBT2) {
priv->system = SYS_DVBT2;
cxd2841er_dvbt2_set_plp_config(priv,
(int)(p->stream_id > 255), p->stream_id);
cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
switch (priv->state) {
case STATE_SLEEP_TC:
ret = cxd2841er_sleep_tc_to_active_t2(priv,
p->bandwidth_hz);
break;
case STATE_ACTIVE_TC:
ret = cxd2841er_retune_active(priv, p);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
ret = -EINVAL;
}
} else if (p->delivery_system == SYS_ISDBT) {
priv->system = SYS_ISDBT;
switch (priv->state) {
case STATE_SLEEP_TC:
ret = cxd2841er_sleep_tc_to_active_i(
priv, p->bandwidth_hz);
break;
case STATE_ACTIVE_TC:
ret = cxd2841er_retune_active(priv, p);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
ret = -EINVAL;
}
} else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
p->delivery_system == SYS_DVBC_ANNEX_C) {
priv->system = SYS_DVBC_ANNEX_A;
/* correct bandwidth */
if (p->bandwidth_hz != 6000000 &&
p->bandwidth_hz != 7000000 &&
p->bandwidth_hz != 8000000) {
p->bandwidth_hz = 8000000;
dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
__func__, p->bandwidth_hz);
}
switch (priv->state) {
case STATE_SLEEP_TC:
ret = cxd2841er_sleep_tc_to_active_c(
priv, p->bandwidth_hz);
break;
case STATE_ACTIVE_TC:
ret = cxd2841er_retune_active(priv, p);
break;
default:
dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
ret = -EINVAL;
}
} else {
dev_dbg(&priv->i2c->dev,
"%s(): invalid delivery system %d\n",
__func__, p->delivery_system);
ret = -EINVAL;
}
if (ret)
goto done;
if (!(priv->flags & CXD2841ER_EARLY_TUNE))
cxd2841er_tuner_set(fe);
cxd2841er_tune_done(priv);
if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
goto done;
timeout = 2500;
while (timeout > 0) {
ret = cxd2841er_read_status_tc(fe, &status);
if (ret)
goto done;
if (status & FE_HAS_LOCK)
break;
msleep(20);
timeout -= 20;
}
if (timeout < 0)
dev_dbg(&priv->i2c->dev,
"%s(): LOCK wait timeout\n", __func__);
done:
return ret;
}
static int cxd2841er_tune_s(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
int ret, carrier_offset;
struct cxd2841er_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
if (re_tune) {
ret = cxd2841er_set_frontend_s(fe);
if (ret)
return ret;
cxd2841er_read_status_s(fe, status);
if (*status & FE_HAS_LOCK) {
if (cxd2841er_get_carrier_offset_s_s2(
priv, &carrier_offset))
return -EINVAL;
p->frequency += carrier_offset;
ret = cxd2841er_set_frontend_s(fe);
if (ret)
return ret;
}
}
*delay = HZ / 5;
return cxd2841er_read_status_s(fe, status);
}
static int cxd2841er_tune_tc(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
int ret, carrier_offset;
struct cxd2841er_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
re_tune, p->bandwidth_hz);
if (re_tune) {
ret = cxd2841er_set_frontend_tc(fe);
if (ret)
return ret;
cxd2841er_read_status_tc(fe, status);
if (*status & FE_HAS_LOCK) {
switch (priv->system) {
case SYS_ISDBT:
ret = cxd2841er_get_carrier_offset_i(
priv, p->bandwidth_hz,
&carrier_offset);
if (ret)
return ret;
break;
case SYS_DVBT:
ret = cxd2841er_get_carrier_offset_t(
priv, p->bandwidth_hz,
&carrier_offset);
if (ret)
return ret;
break;
case SYS_DVBT2:
ret = cxd2841er_get_carrier_offset_t2(
priv, p->bandwidth_hz,
&carrier_offset);
if (ret)
return ret;
break;
case SYS_DVBC_ANNEX_A:
ret = cxd2841er_get_carrier_offset_c(
priv, &carrier_offset);
if (ret)
return ret;
break;
default:
dev_dbg(&priv->i2c->dev,
"%s(): invalid delivery system %d\n",
__func__, priv->system);
return -EINVAL;
}
dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
__func__, carrier_offset);
p->frequency += carrier_offset;
ret = cxd2841er_set_frontend_tc(fe);
if (ret)
return ret;
}
}
*delay = HZ / 5;
return cxd2841er_read_status_tc(fe, status);
}
static int cxd2841er_sleep_s(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
return 0;
}
static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_ACTIVE_TC) {
switch (priv->system) {
case SYS_DVBT:
cxd2841er_active_t_to_sleep_tc(priv);
break;
case SYS_DVBT2:
cxd2841er_active_t2_to_sleep_tc(priv);
break;
case SYS_ISDBT:
cxd2841er_active_i_to_sleep_tc(priv);
break;
case SYS_DVBC_ANNEX_A:
cxd2841er_active_c_to_sleep_tc(priv);
break;
default:
dev_warn(&priv->i2c->dev,
"%s(): unknown delivery system %d\n",
__func__, priv->system);
}
}
if (priv->state != STATE_SLEEP_TC) {
dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
__func__, priv->state);
return -EINVAL;
}
return 0;
}
static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (!cxd2841er_sleep_tc(fe))
cxd2841er_sleep_tc_to_shutdown(priv);
return 0;
}
static int cxd2841er_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
u8 data;
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
(burst == SEC_MINI_A ? "A" : "B"));
if (priv->state != STATE_SLEEP_S &&
priv->state != STATE_ACTIVE_S) {
dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
data = (burst == SEC_MINI_A ? 0 : 1);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
return 0;
}
static int cxd2841er_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
u8 data;
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
(tone == SEC_TONE_ON ? "On" : "Off"));
if (priv->state != STATE_SLEEP_S &&
priv->state != STATE_ACTIVE_S) {
dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
data = (tone == SEC_TONE_ON ? 1 : 0);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
return 0;
}
static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
int i;
u8 data[12];
struct cxd2841er_priv *priv = fe->demodulator_priv;
if (priv->state != STATE_SLEEP_S &&
priv->state != STATE_ACTIVE_S) {
dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
__func__, priv->state);
return -EINVAL;
}
dev_dbg(&priv->i2c->dev,
"%s(): cmd->len %d\n", __func__, cmd->msg_len);
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
/* DiDEqC enable */
cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
/* cmd1 length & data */
cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
memset(data, 0, sizeof(data));
for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
data[i] = cmd->msg[i];
cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
/* repeat count for cmd1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
/* repeat count for cmd2: always 0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
/* start transmit */
cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
/* wait for 1 sec timeout */
for (i = 0; i < 50; i++) {
cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
if (!data[0]) {
dev_dbg(&priv->i2c->dev,
"%s(): DiSEqC cmd has been sent\n", __func__);
return 0;
}
msleep(20);
}
dev_dbg(&priv->i2c->dev,
"%s(): DiSEqC cmd transmit timeout\n", __func__);
return -ETIMEDOUT;
}
static void cxd2841er_release(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
kfree(priv);
}
static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
cxd2841er_set_reg_bits(
priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
return 0;
}
static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
return DVBFE_ALGO_HW;
}
static void cxd2841er_init_stats(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
p->strength.len = 1;
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->cnr.len = 1;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.len = 1;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.len = 1;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.len = 1;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
static int cxd2841er_init_s(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
/* sanity. force demod to SHUTDOWN state */
if (priv->state == STATE_SLEEP_S) {
dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
__func__);
cxd2841er_sleep_s_to_shutdown(priv);
} else if (priv->state == STATE_ACTIVE_S) {
dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
__func__);
cxd2841er_active_s_to_sleep_s(priv);
cxd2841er_sleep_s_to_shutdown(priv);
}
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
cxd2841er_shutdown_to_sleep_s(priv);
/* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
cxd2841er_init_stats(fe);
return 0;
}
static int cxd2841er_init_tc(struct dvb_frontend *fe)
{
struct cxd2841er_priv *priv = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
__func__, p->bandwidth_hz);
cxd2841er_shutdown_to_sleep_tc(priv);
/* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
/* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
/* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
/* clear TSCFG bits 3+4 */
if (priv->flags & CXD2841ER_TSBITS)
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
cxd2841er_init_stats(fe);
return 0;
}
static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
static struct dvb_frontend_ops cxd2841er_t_c_ops;
static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
struct i2c_adapter *i2c,
u8 system)
{
u8 chip_id = 0;
const char *type;
const char *name;
struct cxd2841er_priv *priv = NULL;
/* allocate memory for the internal state */
priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
if (!priv)
return NULL;
priv->i2c = i2c;
priv->config = cfg;
priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
priv->xtal = cfg->xtal;
priv->flags = cfg->flags;
priv->frontend.demodulator_priv = priv;
dev_info(&priv->i2c->dev,
"%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
__func__, priv->i2c,
priv->i2c_addr_slvx, priv->i2c_addr_slvt);
chip_id = cxd2841er_chip_id(priv);
switch (chip_id) {
case CXD2837ER_CHIP_ID:
snprintf(cxd2841er_t_c_ops.info.name, 128,
"Sony CXD2837ER DVB-T/T2/C demodulator");
name = "CXD2837ER";
type = "C/T/T2";
break;
case CXD2838ER_CHIP_ID:
snprintf(cxd2841er_t_c_ops.info.name, 128,
"Sony CXD2838ER ISDB-T demodulator");
cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
name = "CXD2838ER";
type = "ISDB-T";
break;
case CXD2841ER_CHIP_ID:
snprintf(cxd2841er_t_c_ops.info.name, 128,
"Sony CXD2841ER DVB-T/T2/C demodulator");
name = "CXD2841ER";
type = "T/T2/C/ISDB-T";
break;
case CXD2843ER_CHIP_ID:
snprintf(cxd2841er_t_c_ops.info.name, 128,
"Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
name = "CXD2843ER";
type = "C/C2/T/T2";
break;
case CXD2854ER_CHIP_ID:
snprintf(cxd2841er_t_c_ops.info.name, 128,
"Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
name = "CXD2854ER";
type = "C/C2/T/T2/ISDB-T";
break;
default:
dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
__func__, chip_id);
priv->frontend.demodulator_priv = NULL;
kfree(priv);
return NULL;
}
/* create dvb_frontend */
if (system == SYS_DVBS) {
memcpy(&priv->frontend.ops,
&cxd2841er_dvbs_s2_ops,
sizeof(struct dvb_frontend_ops));
type = "S/S2";
} else {
memcpy(&priv->frontend.ops,
&cxd2841er_t_c_ops,
sizeof(struct dvb_frontend_ops));
}
dev_info(&priv->i2c->dev,
"%s(): attaching %s DVB-%s frontend\n",
__func__, name, type);
dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
__func__, chip_id);
return &priv->frontend;
}
struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
struct i2c_adapter *i2c)
{
return cxd2841er_attach(cfg, i2c, SYS_DVBS);
}
EXPORT_SYMBOL_GPL(cxd2841er_attach_s);
struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
struct i2c_adapter *i2c)
{
return cxd2841er_attach(cfg, i2c, 0);
}
EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c);
static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "Sony CXD2841ER DVB-S/S2 demodulator",
.frequency_min_hz = 500 * MHz,
.frequency_max_hz = 2500 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK,
},
.init = cxd2841er_init_s,
.sleep = cxd2841er_sleep_s,
.release = cxd2841er_release,
.set_frontend = cxd2841er_set_frontend_s,
.get_frontend = cxd2841er_get_frontend,
.read_status = cxd2841er_read_status_s,
.i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
.get_frontend_algo = cxd2841er_get_algo,
.set_tone = cxd2841er_set_tone,
.diseqc_send_burst = cxd2841er_send_burst,
.diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
.tune = cxd2841er_tune_s
};
static struct dvb_frontend_ops cxd2841er_t_c_ops = {
.delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
.info = {
.name = "", /* will set in attach function */
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_2G_MODULATION,
.frequency_min_hz = 42 * MHz,
.frequency_max_hz = 1002 * MHz,
.symbol_rate_min = 870000,
.symbol_rate_max = 11700000
},
.init = cxd2841er_init_tc,
.sleep = cxd2841er_shutdown_tc,
.release = cxd2841er_release,
.set_frontend = cxd2841er_set_frontend_tc,
.get_frontend = cxd2841er_get_frontend,
.read_status = cxd2841er_read_status_tc,
.tune = cxd2841er_tune_tc,
.i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
.get_frontend_algo = cxd2841er_get_algo
};
MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
MODULE_AUTHOR("Sergey Kozlov <[email protected]>, Abylay Ospan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cxd2841er.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
VES1820 - Single Chip Cable Channel Receiver driver module
Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]>
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "ves1820.h"
struct ves1820_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct ves1820_config* config;
struct dvb_frontend frontend;
/* private demodulator data */
u8 reg0;
u8 pwm;
};
static int verbose;
static u8 ves1820_inittab[] = {
0x69, 0x6A, 0x93, 0x1A, 0x12, 0x46, 0x26, 0x1A,
0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x40
};
static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
{
u8 buf[] = { 0x00, reg, data };
struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
int ret;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk("ves1820: %s(): writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
{
u8 b0[] = { 0x00, reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
};
int ret;
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk("ves1820: %s(): readreg error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return b1[0];
}
static int ves1820_setup_reg0(struct ves1820_state *state,
u8 reg0, enum fe_spectral_inversion inversion)
{
reg0 |= state->reg0 & 0x62;
if (INVERSION_ON == inversion) {
if (!state->config->invert) reg0 |= 0x20;
else reg0 &= ~0x20;
} else if (INVERSION_OFF == inversion) {
if (!state->config->invert) reg0 &= ~0x20;
else reg0 |= 0x20;
}
ves1820_writereg(state, 0x00, reg0 & 0xfe);
ves1820_writereg(state, 0x00, reg0 | 0x01);
state->reg0 = reg0;
return 0;
}
static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
{
s32 BDR;
s32 BDRI;
s16 SFIL = 0;
u16 NDEC = 0;
u32 ratio;
u32 fin;
u32 tmp;
u64 fptmp;
u64 fpxin;
if (symbolrate > state->config->xin / 2)
symbolrate = state->config->xin / 2;
if (symbolrate < 500000)
symbolrate = 500000;
if (symbolrate < state->config->xin / 16)
NDEC = 1;
if (symbolrate < state->config->xin / 32)
NDEC = 2;
if (symbolrate < state->config->xin / 64)
NDEC = 3;
/* yeuch! */
fpxin = state->config->xin * 10ULL;
fptmp = fpxin; do_div(fptmp, 123);
if (symbolrate < fptmp)
SFIL = 1;
fptmp = fpxin; do_div(fptmp, 160);
if (symbolrate < fptmp)
SFIL = 0;
fptmp = fpxin; do_div(fptmp, 246);
if (symbolrate < fptmp)
SFIL = 1;
fptmp = fpxin; do_div(fptmp, 320);
if (symbolrate < fptmp)
SFIL = 0;
fptmp = fpxin; do_div(fptmp, 492);
if (symbolrate < fptmp)
SFIL = 1;
fptmp = fpxin; do_div(fptmp, 640);
if (symbolrate < fptmp)
SFIL = 0;
fptmp = fpxin; do_div(fptmp, 984);
if (symbolrate < fptmp)
SFIL = 1;
fin = state->config->xin >> 4;
symbolrate <<= NDEC;
ratio = (symbolrate << 4) / fin;
tmp = ((symbolrate << 4) % fin) << 8;
ratio = (ratio << 8) + tmp / fin;
tmp = (tmp % fin) << 8;
ratio = (ratio << 8) + DIV_ROUND_CLOSEST(tmp, fin);
BDR = ratio;
BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
if (BDRI > 0xFF)
BDRI = 0xFF;
SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
NDEC = (NDEC << 6) | ves1820_inittab[0x03];
ves1820_writereg(state, 0x03, NDEC);
ves1820_writereg(state, 0x0a, BDR & 0xff);
ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
ves1820_writereg(state, 0x0d, BDRI);
ves1820_writereg(state, 0x0e, SFIL);
return 0;
}
static int ves1820_init(struct dvb_frontend* fe)
{
struct ves1820_state* state = fe->demodulator_priv;
int i;
ves1820_writereg(state, 0, 0);
for (i = 0; i < sizeof(ves1820_inittab); i++)
ves1820_writereg(state, i, ves1820_inittab[i]);
if (state->config->selagc)
ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
ves1820_writereg(state, 0x34, state->pwm);
return 0;
}
static int ves1820_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct ves1820_state* state = fe->demodulator_priv;
static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
int real_qam = p->modulation - QAM_16;
if (real_qam < 0 || real_qam > 4)
return -EINVAL;
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
ves1820_set_symbolrate(state, p->symbol_rate);
ves1820_writereg(state, 0x34, state->pwm);
ves1820_writereg(state, 0x01, reg0x01[real_qam]);
ves1820_writereg(state, 0x05, reg0x05[real_qam]);
ves1820_writereg(state, 0x08, reg0x08[real_qam]);
ves1820_writereg(state, 0x09, reg0x09[real_qam]);
ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
return 0;
}
static int ves1820_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct ves1820_state* state = fe->demodulator_priv;
int sync;
*status = 0;
sync = ves1820_readreg(state, 0x11);
if (sync & 1)
*status |= FE_HAS_SIGNAL;
if (sync & 2)
*status |= FE_HAS_CARRIER;
if (sync & 2) /* XXX FIXME! */
*status |= FE_HAS_VITERBI;
if (sync & 4)
*status |= FE_HAS_SYNC;
if (sync & 8)
*status |= FE_HAS_LOCK;
return 0;
}
static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct ves1820_state* state = fe->demodulator_priv;
u32 _ber = ves1820_readreg(state, 0x14) |
(ves1820_readreg(state, 0x15) << 8) |
((ves1820_readreg(state, 0x16) & 0x0f) << 16);
*ber = 10 * _ber;
return 0;
}
static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct ves1820_state* state = fe->demodulator_priv;
u8 gain = ves1820_readreg(state, 0x17);
*strength = (gain << 8) | gain;
return 0;
}
static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct ves1820_state* state = fe->demodulator_priv;
u8 quality = ~ves1820_readreg(state, 0x18);
*snr = (quality << 8) | quality;
return 0;
}
static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct ves1820_state* state = fe->demodulator_priv;
*ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
if (*ucblocks == 0x7f)
*ucblocks = 0xffffffff;
/* reset uncorrected block counter */
ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
return 0;
}
static int ves1820_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct ves1820_state* state = fe->demodulator_priv;
int sync;
s8 afc = 0;
sync = ves1820_readreg(state, 0x11);
afc = ves1820_readreg(state, 0x19);
if (verbose) {
/* AFC only valid when carrier has been recovered */
printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
"ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->symbol_rate * afc) >> 10);
}
if (!state->config->invert) {
p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
} else {
p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
}
p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
p->fec_inner = FEC_NONE;
p->frequency = ((p->frequency + 31250) / 62500) * 62500;
if (sync & 2)
p->frequency -= ((s32) p->symbol_rate * afc) >> 10;
return 0;
}
static int ves1820_sleep(struct dvb_frontend* fe)
{
struct ves1820_state* state = fe->demodulator_priv;
ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
ves1820_writereg(state, 0x00, 0x80); /* standby */
return 0;
}
static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 200;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void ves1820_release(struct dvb_frontend* fe)
{
struct ves1820_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops ves1820_ops;
struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
struct i2c_adapter* i2c,
u8 pwm)
{
struct ves1820_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->reg0 = ves1820_inittab[0];
state->config = config;
state->i2c = i2c;
state->pwm = pwm;
/* check if the demod is there */
if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
goto error;
if (verbose)
printk("ves1820: pwm=0x%02x\n", state->pwm);
/* create dvb_frontend */
memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops ves1820_ops = {
.delsys = { SYS_DVBC_ANNEX_A },
.info = {
.name = "VLSI VES1820 DVB-C",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_FEC_AUTO
},
.release = ves1820_release,
.init = ves1820_init,
.sleep = ves1820_sleep,
.set_frontend = ves1820_set_parameters,
.get_frontend = ves1820_get_frontend,
.get_tune_settings = ves1820_get_tune_settings,
.read_status = ves1820_read_status,
.read_ber = ves1820_read_ber,
.read_signal_strength = ves1820_read_signal_strength,
.read_snr = ves1820_read_snr,
.read_ucblocks = ves1820_read_ucblocks,
};
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(ves1820_attach);
| linux-master | drivers/media/dvb-frontends/ves1820.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Samsung S5H1411 VSB/QAM demodulator driver
Copyright (C) 2008 Steven Toth <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <media/dvb_frontend.h>
#include "s5h1411.h"
struct s5h1411_state {
struct i2c_adapter *i2c;
/* configuration settings */
const struct s5h1411_config *config;
struct dvb_frontend frontend;
enum fe_modulation current_modulation;
unsigned int first_tune:1;
u32 current_frequency;
int if_freq;
u8 inversion;
};
static int debug;
#define dprintk(arg...) do { \
if (debug) \
printk(arg); \
} while (0)
/* Register values to initialise the demod, defaults to VSB */
static struct init_tab {
u8 addr;
u8 reg;
u16 data;
} init_tab[] = {
{ S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
{ S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
{ S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
{ S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
{ S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
{ S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
{ S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
{ S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
{ S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
{ S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
{ S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
{ S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
{ S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
{ S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
{ S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
{ S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
{ S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
{ S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
{ S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
{ S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
{ S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
{ S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
{ S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
{ S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
{ S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
{ S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
{ S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
{ S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
{ S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
{ S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
{ S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
{ S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
{ S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
{ S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
{ S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
{ S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
{ S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
{ S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
{ S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
{ S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
{ S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
{ S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
{ S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
{ S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
{ S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
{ S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
{ S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
{ S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
{ S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
{ S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
{ S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
{ S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
{ S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
{ S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
{ S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
{ S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
{ S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
{ S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
{ S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
{ S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
{ S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
{ S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
{ S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
{ S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
{ S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
{ S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
{ S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
{ S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
{ S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
{ S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
{ S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
{ S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
{ S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
{ S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
{ S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
{ S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
{ S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
{ S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
};
/* VSB SNR lookup table */
static struct vsb_snr_tab {
u16 val;
u16 data;
} vsb_snr_tab[] = {
{ 0x39f, 300, },
{ 0x39b, 295, },
{ 0x397, 290, },
{ 0x394, 285, },
{ 0x38f, 280, },
{ 0x38b, 275, },
{ 0x387, 270, },
{ 0x382, 265, },
{ 0x37d, 260, },
{ 0x377, 255, },
{ 0x370, 250, },
{ 0x36a, 245, },
{ 0x364, 240, },
{ 0x35b, 235, },
{ 0x353, 230, },
{ 0x349, 225, },
{ 0x340, 220, },
{ 0x337, 215, },
{ 0x327, 210, },
{ 0x31b, 205, },
{ 0x310, 200, },
{ 0x302, 195, },
{ 0x2f3, 190, },
{ 0x2e4, 185, },
{ 0x2d7, 180, },
{ 0x2cd, 175, },
{ 0x2bb, 170, },
{ 0x2a9, 165, },
{ 0x29e, 160, },
{ 0x284, 155, },
{ 0x27a, 150, },
{ 0x260, 145, },
{ 0x23a, 140, },
{ 0x224, 135, },
{ 0x213, 130, },
{ 0x204, 125, },
{ 0x1fe, 120, },
{ 0, 0, },
};
/* QAM64 SNR lookup table */
static struct qam64_snr_tab {
u16 val;
u16 data;
} qam64_snr_tab[] = {
{ 0x0001, 0, },
{ 0x0af0, 300, },
{ 0x0d80, 290, },
{ 0x10a0, 280, },
{ 0x14b5, 270, },
{ 0x1590, 268, },
{ 0x1680, 266, },
{ 0x17b0, 264, },
{ 0x18c0, 262, },
{ 0x19b0, 260, },
{ 0x1ad0, 258, },
{ 0x1d00, 256, },
{ 0x1da0, 254, },
{ 0x1ef0, 252, },
{ 0x2050, 250, },
{ 0x20f0, 249, },
{ 0x21d0, 248, },
{ 0x22b0, 247, },
{ 0x23a0, 246, },
{ 0x2470, 245, },
{ 0x24f0, 244, },
{ 0x25a0, 243, },
{ 0x26c0, 242, },
{ 0x27b0, 241, },
{ 0x28d0, 240, },
{ 0x29b0, 239, },
{ 0x2ad0, 238, },
{ 0x2ba0, 237, },
{ 0x2c80, 236, },
{ 0x2d20, 235, },
{ 0x2e00, 234, },
{ 0x2f10, 233, },
{ 0x3050, 232, },
{ 0x3190, 231, },
{ 0x3300, 230, },
{ 0x3340, 229, },
{ 0x3200, 228, },
{ 0x3550, 227, },
{ 0x3610, 226, },
{ 0x3600, 225, },
{ 0x3700, 224, },
{ 0x3800, 223, },
{ 0x3920, 222, },
{ 0x3a20, 221, },
{ 0x3b30, 220, },
{ 0x3d00, 219, },
{ 0x3e00, 218, },
{ 0x4000, 217, },
{ 0x4100, 216, },
{ 0x4300, 215, },
{ 0x4400, 214, },
{ 0x4600, 213, },
{ 0x4700, 212, },
{ 0x4800, 211, },
{ 0x4a00, 210, },
{ 0x4b00, 209, },
{ 0x4d00, 208, },
{ 0x4f00, 207, },
{ 0x5050, 206, },
{ 0x5200, 205, },
{ 0x53c0, 204, },
{ 0x5450, 203, },
{ 0x5650, 202, },
{ 0x5820, 201, },
{ 0x6000, 200, },
{ 0xffff, 0, },
};
/* QAM256 SNR lookup table */
static struct qam256_snr_tab {
u16 val;
u16 data;
} qam256_snr_tab[] = {
{ 0x0001, 0, },
{ 0x0970, 400, },
{ 0x0a90, 390, },
{ 0x0b90, 380, },
{ 0x0d90, 370, },
{ 0x0ff0, 360, },
{ 0x1240, 350, },
{ 0x1345, 348, },
{ 0x13c0, 346, },
{ 0x14c0, 344, },
{ 0x1500, 342, },
{ 0x1610, 340, },
{ 0x1700, 338, },
{ 0x1800, 336, },
{ 0x18b0, 334, },
{ 0x1900, 332, },
{ 0x1ab0, 330, },
{ 0x1bc0, 328, },
{ 0x1cb0, 326, },
{ 0x1db0, 324, },
{ 0x1eb0, 322, },
{ 0x2030, 320, },
{ 0x2200, 318, },
{ 0x2280, 316, },
{ 0x2410, 314, },
{ 0x25b0, 312, },
{ 0x27a0, 310, },
{ 0x2840, 308, },
{ 0x29d0, 306, },
{ 0x2b10, 304, },
{ 0x2d30, 302, },
{ 0x2f20, 300, },
{ 0x30c0, 298, },
{ 0x3260, 297, },
{ 0x32c0, 296, },
{ 0x3300, 295, },
{ 0x33b0, 294, },
{ 0x34b0, 293, },
{ 0x35a0, 292, },
{ 0x3650, 291, },
{ 0x3800, 290, },
{ 0x3900, 289, },
{ 0x3a50, 288, },
{ 0x3b30, 287, },
{ 0x3cb0, 286, },
{ 0x3e20, 285, },
{ 0x3fa0, 284, },
{ 0x40a0, 283, },
{ 0x41c0, 282, },
{ 0x42f0, 281, },
{ 0x44a0, 280, },
{ 0x4600, 279, },
{ 0x47b0, 278, },
{ 0x4900, 277, },
{ 0x4a00, 276, },
{ 0x4ba0, 275, },
{ 0x4d00, 274, },
{ 0x4f00, 273, },
{ 0x5000, 272, },
{ 0x51f0, 272, },
{ 0x53a0, 270, },
{ 0x5520, 269, },
{ 0x5700, 268, },
{ 0x5800, 267, },
{ 0x5a00, 266, },
{ 0x5c00, 265, },
{ 0x5d00, 264, },
{ 0x5f00, 263, },
{ 0x6000, 262, },
{ 0x6200, 261, },
{ 0x6400, 260, },
{ 0xffff, 0, },
};
/* 8 bit registers, 16 bit values */
static int s5h1411_writereg(struct s5h1411_state *state,
u8 addr, u8 reg, u16 data)
{
int ret;
u8 buf[] = { reg, data >> 8, data & 0xff };
struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
__func__, addr, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0, 0 };
struct i2c_msg msg[] = {
{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk(KERN_ERR "%s: readreg error (ret == %i)\n",
__func__, ret);
return (b1[0] << 8) | b1[1];
}
static int s5h1411_softreset(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
return 0;
}
static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d KHz)\n", __func__, KHz);
switch (KHz) {
case 3250:
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
break;
case 3500:
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
break;
case 4000:
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
break;
default:
dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
__func__, KHz);
fallthrough;
case 5380:
case 44000:
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
break;
}
state->if_freq = KHz;
return 0;
}
static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, mode);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
switch (mode) {
case S5H1411_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
val |= 0x0000;
break;
case S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
val |= 0x1000;
break;
case S5H1411_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
val |= 0x2000;
break;
case S5H1411_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
val |= 0x3000;
break;
default:
return -EINVAL;
}
/* Configure MPEG Signal Timing charactistics */
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
}
static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, inversion);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
if (inversion == 1)
val |= 0x1000; /* Inverted */
state->inversion = inversion;
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
}
static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, serial);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
if (serial == 1)
val |= 0x100;
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
}
static int s5h1411_enable_modulation(struct dvb_frontend *fe,
enum fe_modulation m)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(0x%08x)\n", __func__, m);
if ((state->first_tune == 0) && (m == state->current_modulation)) {
dprintk("%s() Already at desired modulation. Skipping...\n",
__func__);
return 0;
}
switch (m) {
case VSB_8:
dprintk("%s() VSB_8\n", __func__);
s5h1411_set_if_freq(fe, state->config->vsb_if);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
break;
case QAM_64:
case QAM_256:
case QAM_AUTO:
dprintk("%s() QAM_AUTO (64/256)\n", __func__);
s5h1411_set_if_freq(fe, state->config->qam_if);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
break;
default:
dprintk("%s() Invalid modulation\n", __func__);
return -EINVAL;
}
state->current_modulation = m;
state->first_tune = 0;
s5h1411_softreset(fe);
return 0;
}
static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
else
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
}
static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, enable);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
if (enable)
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
val | 0x02);
else
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
}
static int s5h1411_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
else {
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
s5h1411_softreset(fe);
}
return 0;
}
static int s5h1411_sleep(struct dvb_frontend *fe)
{
return s5h1411_set_powerstate(fe, 1);
}
static int s5h1411_register_reset(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
}
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int s5h1411_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(frequency=%d)\n", __func__, p->frequency);
s5h1411_softreset(fe);
state->current_frequency = p->frequency;
s5h1411_enable_modulation(fe, p->modulation);
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Issue a reset to the demod so it knows to resync against the
newly tuned frequency */
s5h1411_softreset(fe);
return 0;
}
/* Reset the demod hardware and reset all of the configuration registers
to a default state. */
static int s5h1411_init(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
int i;
dprintk("%s()\n", __func__);
s5h1411_set_powerstate(fe, 0);
s5h1411_register_reset(fe);
for (i = 0; i < ARRAY_SIZE(init_tab); i++)
s5h1411_writereg(state, init_tab[i].addr,
init_tab[i].reg,
init_tab[i].data);
/* The datasheet says that after initialisation, VSB is default */
state->current_modulation = VSB_8;
/* Although the datasheet says it's in VSB, empirical evidence
shows problems getting lock on the first tuning request. Make
sure we call enable_modulation the first time around */
state->first_tune = 1;
if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
/* Serial */
s5h1411_set_serialmode(fe, 1);
else
/* Parallel */
s5h1411_set_serialmode(fe, 0);
s5h1411_set_spectralinversion(fe, state->config->inversion);
s5h1411_set_if_freq(fe, state->config->vsb_if);
s5h1411_set_gpio(fe, state->config->gpio);
s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
s5h1411_softreset(fe);
/* Note: Leaving the I2C gate closed. */
s5h1411_i2c_gate_ctrl(fe, 0);
return 0;
}
static int s5h1411_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 reg;
u32 tuner_status = 0;
*status = 0;
/* Register F2 bit 15 = Master Lock, removed */
switch (state->current_modulation) {
case QAM_64:
case QAM_256:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
if (reg & 0x10) /* QAM FEC Lock */
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
if (reg & 0x100) /* QAM EQ Lock */
*status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
case VSB_8:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
if (reg & 0x1000) /* FEC Lock */
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
if (reg & 0x2000) /* EQ Lock */
*status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53);
if (reg & 0x1) /* AFC Lock */
*status |= FE_HAS_SIGNAL;
break;
default:
return -EINVAL;
}
switch (state->config->status_mode) {
case S5H1411_DEMODLOCKING:
if (*status & FE_HAS_VITERBI)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
case S5H1411_TUNERLOCKING:
/* Get the tuner status */
if (fe->ops.tuner_ops.get_status) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.get_status(fe, &tuner_status);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (tuner_status)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
break;
}
dprintk("%s() status 0x%08x\n", __func__, *status);
return 0;
}
static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
if (v < qam256_snr_tab[i].val) {
*snr = qam256_snr_tab[i].data;
ret = 0;
break;
}
}
return ret;
}
static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
if (v < qam64_snr_tab[i].val) {
*snr = qam64_snr_tab[i].data;
ret = 0;
break;
}
}
return ret;
}
static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
if (v > vsb_snr_tab[i].val) {
*snr = vsb_snr_tab[i].data;
ret = 0;
break;
}
}
dprintk("%s() snr=%d\n", __func__, *snr);
return ret;
}
static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 reg;
dprintk("%s()\n", __func__);
switch (state->current_modulation) {
case QAM_64:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
return s5h1411_qam64_lookup_snr(fe, snr, reg);
case QAM_256:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
return s5h1411_qam256_lookup_snr(fe, snr, reg);
case VSB_8:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
0xf2) & 0x3ff;
return s5h1411_vsb_lookup_snr(fe, snr, reg);
default:
break;
}
return -EINVAL;
}
static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
/* borrowed from lgdt330x.c
*
* Calculate strength from SNR up to 35dB
* Even though the SNR can go higher than 35dB,
* there is some comfort factor in having a range of
* strong signals that can show at 100%
*/
u16 snr;
u32 tmp;
int ret = s5h1411_read_snr(fe, &snr);
*signal_strength = 0;
if (0 == ret) {
/* The following calculation method was chosen
* purely for the sake of code re-use from the
* other demod drivers that use this method */
/* Convert from SNR in dB * 10 to 8.24 fixed-point */
tmp = (snr * ((1 << 24) / 10));
/* Convert from 8.24 fixed-point to
* scale the range 0 - 35*2^24 into 0 - 65535*/
if (tmp >= 8960 * 0x10000)
*signal_strength = 0xffff;
else
*signal_strength = tmp / 8960;
}
return ret;
}
static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct s5h1411_state *state = fe->demodulator_priv;
*ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
return 0;
}
static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
{
return s5h1411_read_ucblocks(fe, ber);
}
static int s5h1411_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct s5h1411_state *state = fe->demodulator_priv;
p->frequency = state->current_frequency;
p->modulation = state->current_modulation;
return 0;
}
static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void s5h1411_release(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops s5h1411_ops;
struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
struct i2c_adapter *i2c)
{
struct s5h1411_state *state = NULL;
u16 reg;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->current_modulation = VSB_8;
state->inversion = state->config->inversion;
/* check if the demod exists */
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
if (reg != 0x0066)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1411_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
if (s5h1411_init(&state->frontend) != 0) {
printk(KERN_ERR "%s: Failed to initialize correctly\n",
__func__);
goto error;
}
/* Note: Leaving the I2C gate open here. */
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
/* Put the device into low-power mode until first use */
s5h1411_set_powerstate(&state->frontend, 1);
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(s5h1411_attach);
static const struct dvb_frontend_ops s5h1411_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Samsung S5H1411 QAM/8VSB Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = s5h1411_init,
.sleep = s5h1411_sleep,
.i2c_gate_ctrl = s5h1411_i2c_gate_ctrl,
.set_frontend = s5h1411_set_frontend,
.get_frontend = s5h1411_get_frontend,
.get_tune_settings = s5h1411_get_tune_settings,
.read_status = s5h1411_read_status,
.read_ber = s5h1411_read_ber,
.read_signal_strength = s5h1411_read_signal_strength,
.read_snr = s5h1411_read_snr,
.read_ucblocks = s5h1411_read_ucblocks,
.release = s5h1411_release,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/s5h1411.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "mb86a16.h"
#include "mb86a16_priv.h"
static unsigned int verbose = 5;
module_param(verbose, int, 0644);
struct mb86a16_state {
struct i2c_adapter *i2c_adap;
const struct mb86a16_config *config;
struct dvb_frontend frontend;
/* tuning parameters */
int frequency;
int srate;
/* Internal stuff */
int master_clk;
int deci;
int csel;
int rsel;
};
#define MB86A16_ERROR 0
#define MB86A16_NOTICE 1
#define MB86A16_INFO 2
#define MB86A16_DEBUG 3
#define dprintk(x, y, z, format, arg...) do { \
if (z) { \
if ((x > MB86A16_ERROR) && (x > y)) \
printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_NOTICE) && (x > y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_INFO) && (x > y)) \
printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_DEBUG) && (x > y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
} else { \
if (x > y) \
printk(format, ##arg); \
} \
} while (0)
#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
{
int ret;
u8 buf[] = { reg, val };
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
dprintk(verbose, MB86A16_DEBUG, 1,
"writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
state->config->demod_address, buf[0], buf[1]);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)",
reg, ret);
if (ret < 0)
return ret;
return -EREMOTEIO;
}
*val = b1[0];
return ret;
}
static int CNTM_set(struct mb86a16_state *state,
unsigned char timint1,
unsigned char timint2,
unsigned char cnext)
{
unsigned char val;
val = (timint1 << 4) | (timint2 << 2) | cnext;
if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int smrt_set(struct mb86a16_state *state, int rate)
{
int tmp ;
int m ;
unsigned char STOFS0, STOFS1;
m = 1 << state->deci;
tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
STOFS0 = tmp & 0x0ff;
STOFS1 = (tmp & 0xf00) >> 8;
if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
(state->csel << 1) |
state->rsel) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int afcex_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int afcofs_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int stlp_set(struct mb86a16_state *state,
unsigned char STRAS,
unsigned char STRBS)
{
if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
{
if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int initial_set(struct mb86a16_state *state)
{
if (stlp_set(state, 5, 7))
goto err;
udelay(100);
if (afcex_data_set(state, 0, 0))
goto err;
udelay(100);
if (afcofs_data_set(state, 0, 0))
goto err;
udelay(100);
if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
goto err;
if (mb86a16_write(state, 0x2f, 0x21) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
goto err;
if (mb86a16_write(state, 0x54, 0xff) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int S01T_set(struct mb86a16_state *state,
unsigned char s1t,
unsigned s0t)
{
if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int EN_set(struct mb86a16_state *state,
int cren,
int afcen)
{
unsigned char val;
val = 0x7a | (cren << 7) | (afcen << 2);
if (mb86a16_write(state, 0x49, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int AFCEXEN_set(struct mb86a16_state *state,
int afcexen,
int smrt)
{
unsigned char AFCA ;
if (smrt > 18875)
AFCA = 4;
else if (smrt > 9375)
AFCA = 3;
else if (smrt > 2250)
AFCA = 2;
else
AFCA = 1;
if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int DAGC_data_set(struct mb86a16_state *state,
unsigned char DAGCA,
unsigned char DAGCW)
{
if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static void smrt_info_get(struct mb86a16_state *state, int rate)
{
if (rate >= 37501) {
state->deci = 0; state->csel = 0; state->rsel = 0;
} else if (rate >= 30001) {
state->deci = 0; state->csel = 0; state->rsel = 1;
} else if (rate >= 26251) {
state->deci = 0; state->csel = 1; state->rsel = 0;
} else if (rate >= 22501) {
state->deci = 0; state->csel = 1; state->rsel = 1;
} else if (rate >= 18751) {
state->deci = 1; state->csel = 0; state->rsel = 0;
} else if (rate >= 15001) {
state->deci = 1; state->csel = 0; state->rsel = 1;
} else if (rate >= 13126) {
state->deci = 1; state->csel = 1; state->rsel = 0;
} else if (rate >= 11251) {
state->deci = 1; state->csel = 1; state->rsel = 1;
} else if (rate >= 9376) {
state->deci = 2; state->csel = 0; state->rsel = 0;
} else if (rate >= 7501) {
state->deci = 2; state->csel = 0; state->rsel = 1;
} else if (rate >= 6563) {
state->deci = 2; state->csel = 1; state->rsel = 0;
} else if (rate >= 5626) {
state->deci = 2; state->csel = 1; state->rsel = 1;
} else if (rate >= 4688) {
state->deci = 3; state->csel = 0; state->rsel = 0;
} else if (rate >= 3751) {
state->deci = 3; state->csel = 0; state->rsel = 1;
} else if (rate >= 3282) {
state->deci = 3; state->csel = 1; state->rsel = 0;
} else if (rate >= 2814) {
state->deci = 3; state->csel = 1; state->rsel = 1;
} else if (rate >= 2344) {
state->deci = 4; state->csel = 0; state->rsel = 0;
} else if (rate >= 1876) {
state->deci = 4; state->csel = 0; state->rsel = 1;
} else if (rate >= 1641) {
state->deci = 4; state->csel = 1; state->rsel = 0;
} else if (rate >= 1407) {
state->deci = 4; state->csel = 1; state->rsel = 1;
} else if (rate >= 1172) {
state->deci = 5; state->csel = 0; state->rsel = 0;
} else if (rate >= 939) {
state->deci = 5; state->csel = 0; state->rsel = 1;
} else if (rate >= 821) {
state->deci = 5; state->csel = 1; state->rsel = 0;
} else {
state->deci = 5; state->csel = 1; state->rsel = 1;
}
if (state->csel == 0)
state->master_clk = 92000;
else
state->master_clk = 61333;
}
static int signal_det(struct mb86a16_state *state,
int smrt,
unsigned char *SIG)
{
int ret;
int smrtd;
unsigned char S[3];
int i;
if (*SIG > 45) {
if (CNTM_set(state, 2, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
} else {
if (CNTM_set(state, 3, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
}
for (i = 0; i < 3; i++) {
if (i == 0)
smrtd = smrt * 98 / 100;
else if (i == 1)
smrtd = smrt;
else
smrtd = smrt * 102 / 100;
smrt_info_get(state, smrtd);
smrt_set(state, smrtd);
srst(state);
msleep_interruptible(10);
if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
}
if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100))
ret = 1;
else
ret = 0;
*SIG = S[1];
if (CNTM_set(state, 0, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
return ret;
}
static int rf_val_set(struct mb86a16_state *state,
int f,
int smrt,
unsigned char R)
{
unsigned char C, F, B;
int M;
unsigned char rf_val[5];
int ack = -1;
if (smrt > 37750)
C = 1;
else if (smrt > 18875)
C = 2;
else if (smrt > 5500)
C = 3;
else
C = 4;
if (smrt > 30500)
F = 3;
else if (smrt > 9375)
F = 1;
else if (smrt > 4625)
F = 0;
else
F = 2;
if (f < 1060)
B = 0;
else if (f < 1175)
B = 1;
else if (f < 1305)
B = 2;
else if (f < 1435)
B = 3;
else if (f < 1570)
B = 4;
else if (f < 1715)
B = 5;
else if (f < 1845)
B = 6;
else if (f < 1980)
B = 7;
else if (f < 2080)
B = 8;
else
B = 9;
M = f * (1 << R) / 2;
rf_val[0] = 0x01 | (C << 3) | (F << 1);
rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
rf_val[2] = (M & 0x00ff0) >> 4;
rf_val[3] = ((M & 0x0000f) << 4) | B;
/* Frequency Set */
if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
ack = 0;
if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
ack = 0;
if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
ack = 0;
if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
ack = 0;
if (mb86a16_write(state, 0x25, 0x01) < 0)
ack = 0;
if (ack == 0) {
dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int afcerr_chk(struct mb86a16_state *state)
{
unsigned char AFCM_L, AFCM_H ;
int AFCM ;
int afcm, afcerr ;
if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
goto err;
AFCM = (AFCM_H << 8) + AFCM_L;
if (AFCM > 2048)
afcm = AFCM - 4096;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
return afcerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int dagcm_val_get(struct mb86a16_state *state)
{
int DAGCM;
unsigned char DAGCM_H, DAGCM_L;
if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
goto err;
DAGCM = (DAGCM_H << 8) + DAGCM_L;
return DAGCM;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
u8 stat, stat2;
struct mb86a16_state *state = fe->demodulator_priv;
*status = 0;
if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
goto err;
if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
goto err;
if ((stat > 25) && (stat2 > 25))
*status |= FE_HAS_SIGNAL;
if ((stat > 45) && (stat2 > 45))
*status |= FE_HAS_CARRIER;
if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
goto err;
if (stat & 0x01)
*status |= FE_HAS_SYNC;
if (stat & 0x01)
*status |= FE_HAS_VITERBI;
if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
goto err;
if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
*status |= FE_HAS_LOCK;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int sync_chk(struct mb86a16_state *state,
unsigned char *VIRM)
{
unsigned char val;
int sync;
if (mb86a16_read(state, 0x0d, &val) != 2)
goto err;
dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
sync = val & 0x01;
*VIRM = (val & 0x1c) >> 2;
return sync;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
*VIRM = 0;
return -EREMOTEIO;
}
static int freqerr_chk(struct mb86a16_state *state,
int fTP,
int smrt,
int unit)
{
unsigned char CRM, AFCML, AFCMH;
unsigned char temp1, temp2, temp3;
int crm, afcm, AFCM;
int crrerr, afcerr; /* kHz */
int frqerr; /* MHz */
int afcen, afcexen = 0;
int R, M, fOSC, fOSC_OFS;
if (mb86a16_read(state, 0x43, &CRM) != 2)
goto err;
if (CRM > 127)
crm = CRM - 256;
else
crm = CRM;
crrerr = smrt * crm / 256;
if (mb86a16_read(state, 0x49, &temp1) != 2)
goto err;
afcen = (temp1 & 0x04) >> 2;
if (afcen == 0) {
if (mb86a16_read(state, 0x2a, &temp1) != 2)
goto err;
afcexen = (temp1 & 0x20) >> 5;
}
if (afcen == 1) {
if (mb86a16_read(state, 0x0e, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
goto err;
} else if (afcexen == 1) {
if (mb86a16_read(state, 0x2b, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
goto err;
}
if ((afcen == 1) || (afcexen == 1)) {
smrt_info_get(state, smrt);
AFCM = ((AFCMH & 0x01) << 8) + AFCML;
if (AFCM > 255)
afcm = AFCM - 512;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
} else
afcerr = 0;
if (mb86a16_read(state, 0x22, &temp1) != 2)
goto err;
if (mb86a16_read(state, 0x23, &temp2) != 2)
goto err;
if (mb86a16_read(state, 0x24, &temp3) != 2)
goto err;
R = (temp1 & 0xe0) >> 5;
M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
if (R == 0)
fOSC = 2 * M;
else
fOSC = M;
fOSC_OFS = fOSC - fTP;
if (unit == 0) { /* MHz */
if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
else
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
} else { /* kHz */
frqerr = crrerr + afcerr + fOSC_OFS * 1000;
}
return frqerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
{
unsigned char R;
if (smrt > 9375)
R = 0;
else
R = 1;
return R;
}
static void swp_info_get(struct mb86a16_state *state,
int fOSC_start,
int smrt,
int v, int R,
int swp_ofs,
int *fOSC,
int *afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
int crnt_swp_freq ;
crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
if (R == 0)
*fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
else
*fOSC = (crnt_swp_freq + 500) / 1000;
if (*fOSC >= crnt_swp_freq)
*afcex_freq = *fOSC * 1000 - crnt_swp_freq;
else
*afcex_freq = crnt_swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
{
int swp_freq ;
if ((i % 2 == 1) && (v <= vmax)) {
/* positive v (case 1) */
if ((v - 1 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 1)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v - 1) > 0) &&
(*(V + 30 + v - 2) > 0) &&
(*(V + 30 + v - 3) > 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
((*(V + 30 + v - 1) > SIGMIN) ||
(*(V + 30 + v - 2) > SIGMIN))) {
/* (case 3) */
if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
*SIG1 = *(V + 30 + v - 2);
}
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 2) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 2)) &&
(*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v - 1) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
}
} else {
swp_freq = -1 ;
}
} else if ((i % 2 == 0) && (v >= vmin)) {
/* Negative v (case 1) */
if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else if ((v + 1 == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v);
} else if ((v == vmin) &&
(*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v) > *(V + 30 + v + 1)) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 3) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > *(V + 30 + v + 3)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v + 1) > SIGMIN))) {
/* (case 5) */
if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
}
} else if ((v + 2 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 6) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
swp_freq = fOSC * 1000;
*SIG1 = *(V + 30 + v);
} else
swp_freq = -1;
} else
swp_freq = -1;
return swp_freq;
}
static void swp_info_get2(struct mb86a16_state *state,
int smrt,
int R,
int swp_freq,
int *afcex_freq,
int *fOSC,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
if (R == 0)
*fOSC = (swp_freq + 1000) / 2000 * 2;
else
*fOSC = (swp_freq + 500) / 1000;
if (*fOSC >= swp_freq)
*afcex_freq = *fOSC * 1000 - swp_freq;
else
*afcex_freq = swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static void afcex_info_get(struct mb86a16_state *state,
int afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
AFCEX = afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
{
/* SLOCK0 = 0 */
if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
{
/* Viterbi Rate, IQ Settings */
if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int FEC_srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
{
if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
{
if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int mb86a16_set_fe(struct mb86a16_state *state)
{
u8 agcval, cnmval;
int i, j;
int fOSC = 0;
int fOSC_start = 0;
int wait_t;
int fcp;
int swp_ofs;
int V[60];
u8 SIG1MIN;
unsigned char CREN, AFCEN, AFCEXEN;
unsigned char SIG1;
unsigned char TIMINT1, TIMINT2, TIMEXT;
unsigned char S0T, S1T;
unsigned char S2T;
/* unsigned char S2T, S3T; */
unsigned char S4T, S5T;
unsigned char AFCEX_L, AFCEX_H;
unsigned char R;
unsigned char VIRM;
unsigned char ETH, VIA;
unsigned char junk;
int loop;
int ftemp;
int v, vmax, vmin;
int vmax_his, vmin_his;
int swp_freq, prev_swp_freq[20];
int prev_freq_num;
int signal_dupl;
int afcex_freq;
int signal;
int afcerr;
int temp_freq, delta_freq;
int dagcm[4];
int smrt_d;
/* int freq_err; */
int n;
int ret = -1;
int sync;
dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
fcp = 3000;
swp_ofs = state->srate / 4;
for (i = 0; i < 60; i++)
V[i] = -1;
for (i = 0; i < 20; i++)
prev_swp_freq[i] = 0;
SIG1MIN = 25;
for (n = 0; ((n < 3) && (ret == -1)); n++) {
SEQ_set(state, 0);
iq_vt_set(state, 0);
CREN = 0;
AFCEN = 0;
AFCEXEN = 1;
TIMINT1 = 0;
TIMINT2 = 1;
TIMEXT = 2;
S1T = 0;
S0T = 0;
if (initial_set(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
return -1;
}
if (DAGC_data_set(state, 3, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1; /* (0, 0) */
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1; /* (1, smrt) = (1, symbolrate) */
}
if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
return -1; /* (0, 1, 2) */
}
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1; /* (0, 0) */
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
return -1;
}
R = vco_dev_get(state, state->srate);
if (R == 1)
fOSC_start = state->frequency;
else if (R == 0) {
if (state->frequency % 2 == 0) {
fOSC_start = state->frequency;
} else {
fOSC_start = state->frequency + 1;
if (fOSC_start > 2150)
fOSC_start = state->frequency - 1;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmax = 0 ;
while (loop == 1) {
ftemp = ftemp + swp_ofs;
vmax++;
/* Upper bound */
if (ftemp > 2150000) {
loop = 0;
vmax--;
} else {
if ((ftemp == 2150000) ||
(ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
loop = 0;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmin = 0 ;
while (loop == 1) {
ftemp = ftemp - swp_ofs;
vmin--;
/* Lower bound */
if (ftemp < 950000) {
loop = 0;
vmin++;
} else {
if ((ftemp == 950000) ||
(state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
loop = 0;
}
}
wait_t = (8000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
i = 0;
j = 0;
prev_freq_num = 0;
loop = 1;
signal = 0;
vmax_his = 0;
vmin_his = 0;
v = 0;
while (loop == 1) {
swp_info_get(state, fOSC_start, state->srate,
v, R, swp_ofs, &fOSC,
&afcex_freq, &AFCEX_L, &AFCEX_H);
udelay(100);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
udelay(100);
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
V[30 + v] = SIG1 ;
swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
SIG1MIN, fOSC, afcex_freq,
swp_ofs, &SIG1); /* changed */
signal_dupl = 0;
for (j = 0; j < prev_freq_num; j++) {
if ((abs(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
signal_dupl = 1;
dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
}
}
if ((signal_dupl == 0) && (swp_freq > 0) && (abs(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
prev_swp_freq[prev_freq_num] = swp_freq;
prev_freq_num++;
swp_info_get2(state, state->srate, R, swp_freq,
&afcex_freq, &fOSC,
&AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
signal = signal_det(state, state->srate, &SIG1);
if (signal == 1) {
dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
loop = 0;
} else {
dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
}
}
if (v > vmax)
vmax_his = 1 ;
if (v < vmin)
vmin_his = 1 ;
i++;
if ((i % 2 == 1) && (vmax_his == 1))
i++;
if ((i % 2 == 0) && (vmin_his == 1))
i++;
if (i % 2 == 1)
v = (i + 1) / 2;
else
v = -i / 2;
if ((vmax_his == 1) && (vmin_his == 1))
loop = 0 ;
}
if (signal == 1) {
dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
S1T = 7 ;
S0T = 1 ;
CREN = 0 ;
AFCEN = 1 ;
AFCEXEN = 0 ;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
/* delay 4~200 */
wait_t = 200000 / state->master_clk + 200000 / state->srate;
msleep(wait_t);
afcerr = afcerr_chk(state);
if (afcerr == -1)
return -1;
swp_freq = fOSC * 1000 + afcerr ;
AFCEXEN = 1 ;
if (state->srate >= 1500)
smrt_d = state->srate / 3;
else
smrt_d = state->srate / 2;
smrt_info_get(state, smrt_d);
if (smrt_set(state, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
R = vco_dev_get(state, smrt_d);
if (DAGC_data_set(state, 2, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
for (i = 0; i < 3; i++) {
temp_freq = swp_freq + (i - 1) * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[i] = dagcm_val_get(state);
}
if ((dagcm[0] > dagcm[1]) &&
(dagcm[0] > dagcm[2]) &&
(dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
temp_freq = swp_freq - 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
else
delta_freq = 0;
} else if ((dagcm[2] > dagcm[1]) &&
(dagcm[2] > dagcm[0]) &&
(dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
temp_freq = swp_freq + 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
else
delta_freq = 0 ;
} else {
delta_freq = 0 ;
}
dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
swp_freq += delta_freq;
dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
if (abs(state->frequency * 1000 - swp_freq) > 3800) {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
} else {
S1T = 0;
S0T = 3;
CREN = 1;
AFCEN = 0;
AFCEXEN = 1;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
if (DAGC_data_set(state, 0, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
R = vco_dev_get(state, state->srate);
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
wait_t = 7 + (10000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
if (SIG1 > 110) {
S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
wait_t = 7 + (917504 + state->srate / 2) / state->srate;
} else if (SIG1 > 105) {
S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
} else if (SIG1 > 85) {
S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
} else if (SIG1 > 65) {
S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
} else {
S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
}
wait_t *= 2; /* FOS */
S2T_set(state, S2T);
S45T_set(state, S4T, S5T);
Vi_set(state, ETH, VIA);
srst(state);
msleep_interruptible(wait_t);
sync = sync_chk(state, &VIRM);
dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
if (VIRM) {
if (VIRM == 4) {
/* 5/6 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
msleep_interruptible(wait_t);
if (sync_chk(state, &junk) == 0) {
iq_vt_set(state, 1);
FEC_srst(state);
}
}
/* 1/2, 2/3, 3/4, 7/8 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
msleep_interruptible(wait_t);
SEQ_set(state, 1);
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
SEQ_set(state, 1);
ret = -1;
}
}
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
ret = -1;
}
sync = sync_chk(state, &junk);
if (sync) {
dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
freqerr_chk(state, state->frequency, state->srate, 1);
ret = 0;
break;
}
}
if (mb86a16_read(state, 0x15, &agcval) != 2 || mb86a16_read(state, 0x26, &cnmval) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
ret = -EREMOTEIO;
} else {
dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
}
return ret;
}
static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct mb86a16_state *state = fe->demodulator_priv;
int ret = -EREMOTEIO;
int i;
u8 regs;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
regs = 0x18;
if (cmd->msg_len > 5 || cmd->msg_len < 4) {
ret = -EINVAL;
goto err;
}
for (i = 0; i < cmd->msg_len; i++) {
if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
goto err;
regs++;
}
i += 0x90;
msleep_interruptible(10);
if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return ret;
}
static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (burst) {
case SEC_MINI_A:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN |
MB86A16_DCC1_TBO) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_MINI_B:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (tone) {
case SEC_TONE_ON:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_CTOE) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_TONE_OFF:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
break;
default:
return -EINVAL;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mb86a16_state *state = fe->demodulator_priv;
state->frequency = p->frequency / 1000;
state->srate = p->symbol_rate / 1000;
if (!mb86a16_set_fe(state)) {
dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
return DVBFE_ALGO_SEARCH_SUCCESS;
}
dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
return DVBFE_ALGO_SEARCH_FAILED;
}
static void mb86a16_release(struct dvb_frontend *fe)
{
struct mb86a16_state *state = fe->demodulator_priv;
kfree(state);
}
static int mb86a16_init(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
{
u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
u32 timer;
struct mb86a16_state *state = fe->demodulator_priv;
*ber = 0;
if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
goto err;
/* BER monitor invalid when BER_EN = 0 */
if (ber_mon & 0x04) {
/* coarse, fast calculation */
*ber = ber_tab & 0x1f;
dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
if (ber_mon & 0x01) {
/*
* BER_SEL = 1, The monitored BER is the estimated
* value with a Reed-Solomon decoder error amount at
* the deinterleaver output.
* monitored BER is expressed as a 20 bit output in total
*/
ber_rst = (ber_mon >> 3) & 0x03;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_rst == 0)
timer = 12500000;
else if (ber_rst == 1)
timer = 25000000;
else if (ber_rst == 2)
timer = 50000000;
else /* ber_rst == 3 */
timer = 100000000;
*ber /= timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
} else {
/*
* BER_SEL = 0, The monitored BER is the estimated
* value with a Viterbi decoder error amount at the
* QPSK demodulator output.
* monitored BER is expressed as a 24 bit output in total
*/
ber_tim = (ber_mon >> 1) & 0x01;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_tim == 0)
timer = 16;
else /* ber_tim == 1 */
timer = 24;
*ber /= 2 ^ timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
}
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
u8 agcm = 0;
struct mb86a16_state *state = fe->demodulator_priv;
*strength = 0;
if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*strength = ((0xff - agcm) * 100) / 256;
dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
*strength = (0xffff - 0xff) + agcm;
return 0;
}
struct cnr {
u8 cn_reg;
u8 cn_val;
};
static const struct cnr cnr_tab[] = {
{ 35, 2 },
{ 40, 3 },
{ 50, 4 },
{ 60, 5 },
{ 70, 6 },
{ 80, 7 },
{ 92, 8 },
{ 103, 9 },
{ 115, 10 },
{ 138, 12 },
{ 162, 15 },
{ 180, 18 },
{ 185, 19 },
{ 189, 20 },
{ 195, 22 },
{ 199, 24 },
{ 201, 25 },
{ 202, 26 },
{ 203, 27 },
{ 205, 28 },
{ 208, 30 }
};
static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct mb86a16_state *state = fe->demodulator_priv;
int i = 0;
int low_tide = 2, high_tide = 30, q_level;
u8 cn;
*snr = 0;
if (mb86a16_read(state, 0x26, &cn) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
if (cn < cnr_tab[i].cn_reg) {
*snr = cnr_tab[i].cn_val;
break;
}
}
q_level = (*snr * 100) / (high_tide - low_tide);
dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
*snr = (0xffff - 0xff) + *snr;
return 0;
}
static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
u8 dist;
struct mb86a16_state *state = fe->demodulator_priv;
if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*ucblocks = dist;
return 0;
}
static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static const struct dvb_frontend_ops mb86a16_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Fujitsu MB86A16 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 3 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 | FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = mb86a16_release,
.get_frontend_algo = mb86a16_frontend_algo,
.search = mb86a16_search,
.init = mb86a16_init,
.sleep = mb86a16_sleep,
.read_status = mb86a16_read_status,
.read_ber = mb86a16_read_ber,
.read_signal_strength = mb86a16_read_signal_strength,
.read_snr = mb86a16_read_snr,
.read_ucblocks = mb86a16_read_ucblocks,
.diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
.diseqc_send_burst = mb86a16_send_diseqc_burst,
.set_tone = mb86a16_set_tone,
};
struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
struct i2c_adapter *i2c_adap)
{
u8 dev_id = 0;
struct mb86a16_state *state = NULL;
state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->config = config;
state->i2c_adap = i2c_adap;
mb86a16_read(state, 0x7f, &dev_id);
if (dev_id != 0xfe)
goto error;
memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
state->frontend.ops.set_voltage = state->config->set_voltage;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(mb86a16_attach);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Manu Abraham");
| linux-master | drivers/media/dvb-frontends/mb86a16.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2099.c: Driver for the Sony CXD2099AR Common Interface Controller
*
* Copyright (C) 2010-2013 Digital Devices GmbH
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include "cxd2099.h"
static int buffermode;
module_param(buffermode, int, 0444);
MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
struct cxd {
struct dvb_ca_en50221 en;
struct cxd2099_cfg cfg;
struct i2c_client *client;
struct regmap *regmap;
u8 regs[0x23];
u8 lastaddress;
u8 clk_reg_f;
u8 clk_reg_b;
int mode;
int ready;
int dr;
int write_busy;
int slot_stat;
u8 amem[1024];
int amem_read;
int cammode;
struct mutex lock; /* device access lock */
u8 rbuf[1028];
u8 wbuf[1028];
};
static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
int status = 0;
if (ci->lastaddress != adr)
status = regmap_write(ci->regmap, 0, adr);
if (!status) {
ci->lastaddress = adr;
while (n) {
int len = n;
if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
len = ci->cfg.max_i2c;
status = regmap_raw_read(ci->regmap, 1, data, len);
if (status)
return status;
data += len;
n -= len;
}
}
return status;
}
static int read_reg(struct cxd *ci, u8 reg, u8 *val)
{
return read_block(ci, reg, val, 1);
}
static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
u8 addr[2] = {address & 0xff, address >> 8};
status = regmap_raw_write(ci->regmap, 2, addr, 2);
if (!status)
status = regmap_raw_read(ci->regmap, 3, data, n);
return status;
}
static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
u8 addr[2] = {address & 0xff, address >> 8};
status = regmap_raw_write(ci->regmap, 2, addr, 2);
if (!status) {
u8 buf[256];
memcpy(buf, data, n);
status = regmap_raw_write(ci->regmap, 3, buf, n);
}
return status;
}
static int read_io(struct cxd *ci, u16 address, unsigned int *val)
{
int status;
u8 addr[2] = {address & 0xff, address >> 8};
status = regmap_raw_write(ci->regmap, 2, addr, 2);
if (!status)
status = regmap_read(ci->regmap, 3, val);
return status;
}
static int write_io(struct cxd *ci, u16 address, u8 val)
{
int status;
u8 addr[2] = {address & 0xff, address >> 8};
status = regmap_raw_write(ci->regmap, 2, addr, 2);
if (!status)
status = regmap_write(ci->regmap, 3, val);
return status;
}
static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
int status = 0;
unsigned int regval;
if (ci->lastaddress != reg)
status = regmap_write(ci->regmap, 0, reg);
if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
status = regmap_read(ci->regmap, 1, ®val);
ci->regs[reg] = regval;
}
ci->lastaddress = reg;
ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
if (!status)
status = regmap_write(ci->regmap, 1, ci->regs[reg]);
if (reg == 0x20)
ci->regs[reg] &= 0x7f;
return status;
}
static int write_reg(struct cxd *ci, u8 reg, u8 val)
{
return write_regm(ci, reg, val, 0xff);
}
static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
int status = 0;
u8 *buf = ci->wbuf;
if (ci->lastaddress != adr)
status = regmap_write(ci->regmap, 0, adr);
if (status)
return status;
ci->lastaddress = adr;
while (n) {
int len = n;
if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
len = ci->cfg.max_i2c - 1;
memcpy(buf, data, len);
status = regmap_raw_write(ci->regmap, 1, buf, len);
if (status)
return status;
n -= len;
data += len;
}
return status;
}
static void set_mode(struct cxd *ci, int mode)
{
if (mode == ci->mode)
return;
switch (mode) {
case 0x00: /* IO mem */
write_regm(ci, 0x06, 0x00, 0x07);
break;
case 0x01: /* ATT mem */
write_regm(ci, 0x06, 0x02, 0x07);
break;
default:
break;
}
ci->mode = mode;
}
static void cam_mode(struct cxd *ci, int mode)
{
u8 dummy;
if (mode == ci->cammode)
return;
switch (mode) {
case 0x00:
write_regm(ci, 0x20, 0x80, 0x80);
break;
case 0x01:
if (!ci->en.read_data)
return;
ci->write_busy = 0;
dev_info(&ci->client->dev, "enable cam buffer mode\n");
write_reg(ci, 0x0d, 0x00);
write_reg(ci, 0x0e, 0x01);
write_regm(ci, 0x08, 0x40, 0x40);
read_reg(ci, 0x12, &dummy);
write_regm(ci, 0x08, 0x80, 0x80);
break;
default:
break;
}
ci->cammode = mode;
}
static int init(struct cxd *ci)
{
int status;
mutex_lock(&ci->lock);
ci->mode = -1;
do {
status = write_reg(ci, 0x00, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x01, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x02, 0x10);
if (status < 0)
break;
status = write_reg(ci, 0x03, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x05, 0xFF);
if (status < 0)
break;
status = write_reg(ci, 0x06, 0x1F);
if (status < 0)
break;
status = write_reg(ci, 0x07, 0x1F);
if (status < 0)
break;
status = write_reg(ci, 0x08, 0x28);
if (status < 0)
break;
status = write_reg(ci, 0x14, 0x20);
if (status < 0)
break;
/* TOSTRT = 8, Mode B (gated clock), falling Edge,
* Serial, POL=HIGH, MSB
*/
status = write_reg(ci, 0x0A, 0xA7);
if (status < 0)
break;
status = write_reg(ci, 0x0B, 0x33);
if (status < 0)
break;
status = write_reg(ci, 0x0C, 0x33);
if (status < 0)
break;
status = write_regm(ci, 0x14, 0x00, 0x0F);
if (status < 0)
break;
status = write_reg(ci, 0x15, ci->clk_reg_b);
if (status < 0)
break;
status = write_regm(ci, 0x16, 0x00, 0x0F);
if (status < 0)
break;
status = write_reg(ci, 0x17, ci->clk_reg_f);
if (status < 0)
break;
if (ci->cfg.clock_mode == 2) {
/* bitrate*2^13/ 72000 */
u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
if (ci->cfg.polarity) {
status = write_reg(ci, 0x09, 0x6f);
if (status < 0)
break;
} else {
status = write_reg(ci, 0x09, 0x6d);
if (status < 0)
break;
}
status = write_reg(ci, 0x20, 0x08);
if (status < 0)
break;
status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
if (status < 0)
break;
status = write_reg(ci, 0x22, reg & 0xff);
if (status < 0)
break;
} else if (ci->cfg.clock_mode == 1) {
if (ci->cfg.polarity) {
status = write_reg(ci, 0x09, 0x6f); /* D */
if (status < 0)
break;
} else {
status = write_reg(ci, 0x09, 0x6d);
if (status < 0)
break;
}
status = write_reg(ci, 0x20, 0x68);
if (status < 0)
break;
status = write_reg(ci, 0x21, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x22, 0x02);
if (status < 0)
break;
} else {
if (ci->cfg.polarity) {
status = write_reg(ci, 0x09, 0x4f); /* C */
if (status < 0)
break;
} else {
status = write_reg(ci, 0x09, 0x4d);
if (status < 0)
break;
}
status = write_reg(ci, 0x20, 0x28);
if (status < 0)
break;
status = write_reg(ci, 0x21, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x22, 0x07);
if (status < 0)
break;
}
status = write_regm(ci, 0x20, 0x80, 0x80);
if (status < 0)
break;
status = write_regm(ci, 0x03, 0x02, 0x02);
if (status < 0)
break;
status = write_reg(ci, 0x01, 0x04);
if (status < 0)
break;
status = write_reg(ci, 0x00, 0x31);
if (status < 0)
break;
/* Put TS in bypass */
status = write_regm(ci, 0x09, 0x08, 0x08);
if (status < 0)
break;
ci->cammode = -1;
cam_mode(ci, 0);
} while (0);
mutex_unlock(&ci->lock);
return 0;
}
static int read_attribute_mem(struct dvb_ca_en50221 *ca,
int slot, int address)
{
struct cxd *ci = ca->data;
u8 val;
mutex_lock(&ci->lock);
set_mode(ci, 1);
read_pccard(ci, address, &val, 1);
mutex_unlock(&ci->lock);
return val;
}
static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
int address, u8 value)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
set_mode(ci, 1);
write_pccard(ci, address, &value, 1);
mutex_unlock(&ci->lock);
return 0;
}
static int read_cam_control(struct dvb_ca_en50221 *ca,
int slot, u8 address)
{
struct cxd *ci = ca->data;
unsigned int val;
mutex_lock(&ci->lock);
set_mode(ci, 0);
read_io(ci, address, &val);
mutex_unlock(&ci->lock);
return val;
}
static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
u8 address, u8 value)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
set_mode(ci, 0);
write_io(ci, address, value);
mutex_unlock(&ci->lock);
return 0;
}
static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
if (ci->cammode)
read_data(ca, slot, ci->rbuf, 0);
mutex_lock(&ci->lock);
cam_mode(ci, 0);
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
write_reg(ci, 0x00, 0x31);
write_regm(ci, 0x20, 0x80, 0x80);
write_reg(ci, 0x03, 0x02);
ci->ready = 0;
ci->mode = -1;
{
int i;
for (i = 0; i < 100; i++) {
usleep_range(10000, 11000);
if (ci->ready)
break;
}
}
mutex_unlock(&ci->lock);
return 0;
}
static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
dev_dbg(&ci->client->dev, "%s\n", __func__);
if (ci->cammode)
read_data(ca, slot, ci->rbuf, 0);
mutex_lock(&ci->lock);
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
msleep(300);
write_regm(ci, 0x09, 0x08, 0x08);
write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
ci->mode = -1;
ci->write_busy = 0;
mutex_unlock(&ci->lock);
return 0;
}
static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
write_regm(ci, 0x09, 0x00, 0x08);
set_mode(ci, 0);
cam_mode(ci, 1);
mutex_unlock(&ci->lock);
return 0;
}
static int campoll(struct cxd *ci)
{
u8 istat;
read_reg(ci, 0x04, &istat);
if (!istat)
return 0;
write_reg(ci, 0x05, istat);
if (istat & 0x40)
ci->dr = 1;
if (istat & 0x20)
ci->write_busy = 0;
if (istat & 2) {
u8 slotstat;
read_reg(ci, 0x01, &slotstat);
if (!(2 & slotstat)) {
if (!ci->slot_stat) {
ci->slot_stat |=
DVB_CA_EN50221_POLL_CAM_PRESENT;
write_regm(ci, 0x03, 0x08, 0x08);
}
} else {
if (ci->slot_stat) {
ci->slot_stat = 0;
write_regm(ci, 0x03, 0x00, 0x08);
dev_info(&ci->client->dev, "NO CAM\n");
ci->ready = 0;
}
}
if ((istat & 8) &&
ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
ci->ready = 1;
ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
}
}
return 0;
}
static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
{
struct cxd *ci = ca->data;
u8 slotstat;
mutex_lock(&ci->lock);
campoll(ci);
read_reg(ci, 0x01, &slotstat);
mutex_unlock(&ci->lock);
return ci->slot_stat;
}
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
u8 msb, lsb;
u16 len;
mutex_lock(&ci->lock);
campoll(ci);
mutex_unlock(&ci->lock);
if (!ci->dr)
return 0;
mutex_lock(&ci->lock);
read_reg(ci, 0x0f, &msb);
read_reg(ci, 0x10, &lsb);
len = ((u16)msb << 8) | lsb;
if (len > ecount || len < 2) {
/* read it anyway or cxd may hang */
read_block(ci, 0x12, ci->rbuf, len);
mutex_unlock(&ci->lock);
return -EIO;
}
read_block(ci, 0x12, ebuf, len);
ci->dr = 0;
mutex_unlock(&ci->lock);
return len;
}
static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
if (ci->write_busy)
return -EAGAIN;
mutex_lock(&ci->lock);
write_reg(ci, 0x0d, ecount >> 8);
write_reg(ci, 0x0e, ecount & 0xff);
write_block(ci, 0x11, ebuf, ecount);
ci->write_busy = 1;
mutex_unlock(&ci->lock);
return ecount;
}
static const struct dvb_ca_en50221 en_templ = {
.read_attribute_mem = read_attribute_mem,
.write_attribute_mem = write_attribute_mem,
.read_cam_control = read_cam_control,
.write_cam_control = write_cam_control,
.slot_reset = slot_reset,
.slot_shutdown = slot_shutdown,
.slot_ts_enable = slot_ts_enable,
.poll_slot_status = poll_slot_status,
.read_data = read_data,
.write_data = write_data,
};
static int cxd2099_probe(struct i2c_client *client)
{
struct cxd *ci;
struct cxd2099_cfg *cfg = client->dev.platform_data;
static const struct regmap_config rm_cfg = {
.reg_bits = 8,
.val_bits = 8,
};
unsigned int val;
int ret;
ci = kzalloc(sizeof(*ci), GFP_KERNEL);
if (!ci) {
ret = -ENOMEM;
goto err;
}
ci->client = client;
memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
ci->regmap = regmap_init_i2c(client, &rm_cfg);
if (IS_ERR(ci->regmap)) {
ret = PTR_ERR(ci->regmap);
goto err_kfree;
}
ret = regmap_read(ci->regmap, 0x00, &val);
if (ret < 0) {
dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
client->addr);
goto err_rmexit;
}
mutex_init(&ci->lock);
ci->lastaddress = 0xff;
ci->clk_reg_b = 0x4a;
ci->clk_reg_f = 0x1b;
ci->en = en_templ;
ci->en.data = ci;
init(ci);
dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
*cfg->en = &ci->en;
if (!buffermode) {
ci->en.read_data = NULL;
ci->en.write_data = NULL;
} else {
dev_info(&client->dev, "Using CXD2099AR buffer mode");
}
i2c_set_clientdata(client, ci);
return 0;
err_rmexit:
regmap_exit(ci->regmap);
err_kfree:
kfree(ci);
err:
return ret;
}
static void cxd2099_remove(struct i2c_client *client)
{
struct cxd *ci = i2c_get_clientdata(client);
regmap_exit(ci->regmap);
kfree(ci);
}
static const struct i2c_device_id cxd2099_id[] = {
{"cxd2099", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cxd2099_id);
static struct i2c_driver cxd2099_driver = {
.driver = {
.name = "cxd2099",
},
.probe = cxd2099_probe,
.remove = cxd2099_remove,
.id_table = cxd2099_id,
};
module_i2c_driver(cxd2099_driver);
MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/cxd2099.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for Philips tda8262/tda8263 DVBS Silicon tuners
(c) 2006 Andrew de Quincey
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <asm/types.h>
#include "tda826x.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda826x: " args); \
} while (0)
struct tda826x_priv {
/* i2c details */
int i2c_address;
struct i2c_adapter *i2c;
u8 has_loopthrough:1;
u32 frequency;
};
static void tda826x_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int tda826x_sleep(struct dvb_frontend *fe)
{
struct tda826x_priv *priv = fe->tuner_priv;
int ret;
u8 buf [] = { 0x00, 0x8d };
struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = buf, .len = 2 };
dprintk("%s:\n", __func__);
if (!priv->has_loopthrough)
buf[1] = 0xad;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if ((ret = i2c_transfer (priv->i2c, &msg, 1)) != 1) {
dprintk("%s: i2c error\n", __func__);
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return (ret == 1) ? 0 : ret;
}
static int tda826x_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct tda826x_priv *priv = fe->tuner_priv;
int ret;
u32 div;
u32 ksyms;
u32 bandwidth;
u8 buf [11];
struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = buf, .len = 11 };
dprintk("%s:\n", __func__);
div = (p->frequency + (1000-1)) / 1000;
/* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */
/* with R0 = 0.35 and some transformations: */
ksyms = p->symbol_rate / 1000;
bandwidth = (878 * ksyms + 6500000) / 1000000 + 1;
if (bandwidth < 5)
bandwidth = 5;
else if (bandwidth > 36)
bandwidth = 36;
buf[0] = 0x00; // subaddress
buf[1] = 0x09; // powerdown RSSI + the magic value 1
if (!priv->has_loopthrough)
buf[1] |= 0x20; // power down loopthrough if not needed
buf[2] = (1<<5) | 0x0b; // 1Mhz + 0.45 VCO
buf[3] = div >> 7;
buf[4] = div << 1;
buf[5] = ((bandwidth - 5) << 3) | 7; /* baseband cut-off */
buf[6] = 0xfe; // baseband gain 9 db + no RF attenuation
buf[7] = 0x83; // charge pumps at high, tests off
buf[8] = 0x80; // recommended value 4 for AMPVCO + disable ports.
buf[9] = 0x1a; // normal caltime + recommended values for SELTH + SELVTL
buf[10] = 0xd4; // recommended value 13 for BBIAS + unknown bit set on
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if ((ret = i2c_transfer (priv->i2c, &msg, 1)) != 1) {
dprintk("%s: i2c error\n", __func__);
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
priv->frequency = div * 1000;
return (ret == 1) ? 0 : ret;
}
static int tda826x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda826x_priv *priv = fe->tuner_priv;
*frequency = priv->frequency;
return 0;
}
static const struct dvb_tuner_ops tda826x_tuner_ops = {
.info = {
.name = "Philips TDA826X",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2175 * MHz
},
.release = tda826x_release,
.sleep = tda826x_sleep,
.set_params = tda826x_set_params,
.get_frequency = tda826x_get_frequency,
};
struct dvb_frontend *tda826x_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c, int has_loopthrough)
{
struct tda826x_priv *priv = NULL;
u8 b1 [] = { 0, 0 };
struct i2c_msg msg[2] = {
{ .addr = addr, .flags = 0, .buf = NULL, .len = 0 },
{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 }
};
int ret;
dprintk("%s:\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = i2c_transfer (i2c, msg, 2);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (ret != 2)
return NULL;
if (!(b1[1] & 0x80))
return NULL;
priv = kzalloc(sizeof(struct tda826x_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = addr;
priv->i2c = i2c;
priv->has_loopthrough = has_loopthrough;
memcpy(&fe->ops.tuner_ops, &tda826x_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
return fe;
}
EXPORT_SYMBOL_GPL(tda826x_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("DVB TDA826x driver");
MODULE_AUTHOR("Andrew de Quincey");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tda826x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
TDA665x tuner driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "tda665x.h"
struct tda665x_state {
struct dvb_frontend *fe;
struct i2c_adapter *i2c;
const struct tda665x_config *config;
u32 frequency;
u32 bandwidth;
};
static int tda665x_read(struct tda665x_state *state, u8 *buf)
{
const struct tda665x_config *config = state->config;
int err = 0;
struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 };
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1)
goto exit;
return err;
exit:
printk(KERN_ERR "%s: I/O Error err=<%d>\n", __func__, err);
return err;
}
static int tda665x_write(struct tda665x_state *state, u8 *buf, u8 length)
{
const struct tda665x_config *config = state->config;
int err = 0;
struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length };
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1)
goto exit;
return err;
exit:
printk(KERN_ERR "%s: I/O Error err=<%d>\n", __func__, err);
return err;
}
static int tda665x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda665x_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static int tda665x_get_status(struct dvb_frontend *fe, u32 *status)
{
struct tda665x_state *state = fe->tuner_priv;
u8 result = 0;
int err = 0;
*status = 0;
err = tda665x_read(state, &result);
if (err < 0)
goto exit;
if ((result >> 6) & 0x01) {
printk(KERN_DEBUG "%s: Tuner Phase Locked\n", __func__);
*status = 1;
}
return err;
exit:
printk(KERN_ERR "%s: I/O Error\n", __func__);
return err;
}
static int tda665x_set_frequency(struct dvb_frontend *fe,
u32 new_frequency)
{
struct tda665x_state *state = fe->tuner_priv;
const struct tda665x_config *config = state->config;
u32 frequency, status = 0;
u8 buf[4];
int err = 0;
if ((new_frequency < config->frequency_max)
|| (new_frequency > config->frequency_min)) {
printk(KERN_ERR "%s: Frequency beyond limits, frequency=%d\n",
__func__, new_frequency);
return -EINVAL;
}
frequency = new_frequency;
frequency += config->frequency_offst;
frequency *= config->ref_multiplier;
frequency += config->ref_divider >> 1;
frequency /= config->ref_divider;
buf[0] = (u8) ((frequency & 0x7f00) >> 8);
buf[1] = (u8) (frequency & 0x00ff) >> 0;
buf[2] = 0x80 | 0x40 | 0x02;
buf[3] = 0x00;
/* restore frequency */
frequency = new_frequency;
if (frequency < 153000000) {
/* VHF-L */
buf[3] |= 0x01; /* fc, Low Band, 47 - 153 MHz */
if (frequency < 68000000)
buf[3] |= 0x40; /* 83uA */
if (frequency < 1040000000)
buf[3] |= 0x60; /* 122uA */
if (frequency < 1250000000)
buf[3] |= 0x80; /* 163uA */
else
buf[3] |= 0xa0; /* 254uA */
} else if (frequency < 438000000) {
/* VHF-H */
buf[3] |= 0x02; /* fc, Mid Band, 153 - 438 MHz */
if (frequency < 230000000)
buf[3] |= 0x40;
if (frequency < 300000000)
buf[3] |= 0x60;
else
buf[3] |= 0x80;
} else {
/* UHF */
buf[3] |= 0x04; /* fc, High Band, 438 - 862 MHz */
if (frequency < 470000000)
buf[3] |= 0x60;
if (frequency < 526000000)
buf[3] |= 0x80;
else
buf[3] |= 0xa0;
}
/* Set params */
err = tda665x_write(state, buf, 5);
if (err < 0)
goto exit;
/* sleep for some time */
printk(KERN_DEBUG "%s: Waiting to Phase LOCK\n", __func__);
msleep(20);
/* check status */
err = tda665x_get_status(fe, &status);
if (err < 0)
goto exit;
if (status == 1) {
printk(KERN_DEBUG "%s: Tuner Phase locked: status=%d\n",
__func__, status);
state->frequency = frequency; /* cache successful state */
} else {
printk(KERN_ERR "%s: No Phase lock: status=%d\n",
__func__, status);
}
return 0;
exit:
printk(KERN_ERR "%s: I/O Error\n", __func__);
return err;
}
static int tda665x_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
tda665x_set_frequency(fe, c->frequency);
return 0;
}
static void tda665x_release(struct dvb_frontend *fe)
{
struct tda665x_state *state = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(state);
}
static const struct dvb_tuner_ops tda665x_ops = {
.get_status = tda665x_get_status,
.set_params = tda665x_set_params,
.get_frequency = tda665x_get_frequency,
.release = tda665x_release
};
struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
const struct tda665x_config *config,
struct i2c_adapter *i2c)
{
struct tda665x_state *state = NULL;
struct dvb_tuner_info *info;
state = kzalloc(sizeof(struct tda665x_state), GFP_KERNEL);
if (!state)
return NULL;
state->config = config;
state->i2c = i2c;
state->fe = fe;
fe->tuner_priv = state;
fe->ops.tuner_ops = tda665x_ops;
info = &fe->ops.tuner_ops.info;
memcpy(info->name, config->name, sizeof(config->name));
info->frequency_min_hz = config->frequency_min;
info->frequency_max_hz = config->frequency_max;
info->frequency_step_hz = config->frequency_offst;
printk(KERN_DEBUG "%s: Attaching TDA665x (%s) tuner\n", __func__, info->name);
return fe;
}
EXPORT_SYMBOL_GPL(tda665x_attach);
MODULE_DESCRIPTION("TDA665x driver");
MODULE_AUTHOR("Manu Abraham");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/tda665x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for LGDT3302 and LGDT3303 - VSB/QAM
*
* Copyright (C) 2005 Wilson Michaels <[email protected]>
*/
/*
* NOTES ABOUT THIS DRIVER
*
* This Linux driver supports:
* DViCO FusionHDTV 3 Gold-Q
* DViCO FusionHDTV 3 Gold-T
* DViCO FusionHDTV 5 Gold
* DViCO FusionHDTV 5 Lite
* DViCO FusionHDTV 5 USB Gold
* Air2PC/AirStar 2 ATSC 3rd generation (HD5000)
* pcHDTV HD5500
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <media/dvb_frontend.h>
#include <linux/int_log.h>
#include "lgdt330x_priv.h"
#include "lgdt330x.h"
/* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */
/* #define USE_EQMSE */
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off lgdt330x frontend debugging (default:off).");
#define dprintk(state, fmt, arg...) do { \
if (debug) \
dev_printk(KERN_DEBUG, &state->client->dev, fmt, ##arg);\
} while (0)
struct lgdt330x_state {
struct i2c_client *client;
/* Configuration settings */
struct lgdt330x_config config;
struct dvb_frontend frontend;
/* Demodulator private data */
enum fe_modulation current_modulation;
u32 snr; /* Result of last SNR calculation */
u16 ucblocks;
unsigned long last_stats_time;
/* Tuner private data */
u32 current_frequency;
};
static int i2c_write_demod_bytes(struct lgdt330x_state *state,
const u8 *buf, /* data bytes to send */
int len /* number of bytes to send */)
{
int i;
int err;
for (i = 0; i < len - 1; i += 2) {
err = i2c_master_send(state->client, buf, 2);
if (err != 2) {
dev_warn(&state->client->dev,
"%s: error (addr %02x <- %02x, err = %i)\n",
__func__, buf[0], buf[1], err);
if (err < 0)
return err;
else
return -EREMOTEIO;
}
buf += 2;
}
return 0;
}
/*
* This routine writes the register (reg) to the demod bus
* then reads the data returned for (len) bytes.
*/
static int i2c_read_demod_bytes(struct lgdt330x_state *state,
enum I2C_REG reg, u8 *buf, int len)
{
u8 wr[] = { reg };
struct i2c_msg msg[] = {
{
.addr = state->client->addr,
.flags = 0,
.buf = wr,
.len = 1
}, {
.addr = state->client->addr,
.flags = I2C_M_RD,
.buf = buf,
.len = len
},
};
int ret;
ret = i2c_transfer(state->client->adapter, msg, 2);
if (ret != 2) {
dev_warn(&state->client->dev,
"%s: addr 0x%02x select 0x%02x error (ret == %i)\n",
__func__, state->client->addr, reg, ret);
if (ret >= 0)
ret = -EIO;
} else {
ret = 0;
}
return ret;
}
/* Software reset */
static int lgdt3302_sw_reset(struct lgdt330x_state *state)
{
u8 ret;
u8 reset[] = {
IRQ_MASK,
/*
* bit 6 is active low software reset
* bits 5-0 are 1 to mask interrupts
*/
0x00
};
ret = i2c_write_demod_bytes(state,
reset, sizeof(reset));
if (ret == 0) {
/* force reset high (inactive) and unmask interrupts */
reset[1] = 0x7f;
ret = i2c_write_demod_bytes(state,
reset, sizeof(reset));
}
return ret;
}
static int lgdt3303_sw_reset(struct lgdt330x_state *state)
{
u8 ret;
u8 reset[] = {
0x02,
0x00 /* bit 0 is active low software reset */
};
ret = i2c_write_demod_bytes(state,
reset, sizeof(reset));
if (ret == 0) {
/* force reset high (inactive) */
reset[1] = 0x01;
ret = i2c_write_demod_bytes(state,
reset, sizeof(reset));
}
return ret;
}
static int lgdt330x_sw_reset(struct lgdt330x_state *state)
{
switch (state->config.demod_chip) {
case LGDT3302:
return lgdt3302_sw_reset(state);
case LGDT3303:
return lgdt3303_sw_reset(state);
default:
return -ENODEV;
}
}
static int lgdt330x_init(struct dvb_frontend *fe)
{
struct lgdt330x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
char *chip_name;
int err;
/*
* Array of byte pairs <address, value>
* to initialize each different chip
*/
static const u8 lgdt3302_init_data[] = {
/* Use 50MHz param values from spec sheet since xtal is 50 */
/*
* Change the value of NCOCTFV[25:0] of carrier
* recovery center frequency register
*/
VSB_CARRIER_FREQ0, 0x00,
VSB_CARRIER_FREQ1, 0x87,
VSB_CARRIER_FREQ2, 0x8e,
VSB_CARRIER_FREQ3, 0x01,
/*
* Change the TPCLK pin polarity
* data is valid on falling clock
*/
DEMUX_CONTROL, 0xfb,
/*
* Change the value of IFBW[11:0] of
* AGC IF/RF loop filter bandwidth register
*/
AGC_RF_BANDWIDTH0, 0x40,
AGC_RF_BANDWIDTH1, 0x93,
AGC_RF_BANDWIDTH2, 0x00,
/*
* Change the value of bit 6, 'nINAGCBY' and
* 'NSSEL[1:0] of ACG function control register 2
*/
AGC_FUNC_CTRL2, 0xc6,
/*
* Change the value of bit 6 'RFFIX'
* of AGC function control register 3
*/
AGC_FUNC_CTRL3, 0x40,
/*
* Set the value of 'INLVTHD' register 0x2a/0x2c
* to 0x7fe
*/
AGC_DELAY0, 0x07,
AGC_DELAY2, 0xfe,
/*
* Change the value of IAGCBW[15:8]
* of inner AGC loop filter bandwidth
*/
AGC_LOOP_BANDWIDTH0, 0x08,
AGC_LOOP_BANDWIDTH1, 0x9a
};
static const u8 lgdt3303_init_data[] = {
0x4c, 0x14
};
static const u8 flip_1_lgdt3303_init_data[] = {
0x4c, 0x14,
0x87, 0xf3
};
static const u8 flip_2_lgdt3303_init_data[] = {
0x4c, 0x14,
0x87, 0xda
};
/*
* Hardware reset is done using gpio[0] of cx23880x chip.
* I'd like to do it here, but don't know how to find chip address.
* cx88-cards.c arranges for the reset bit to be inactive (high).
* Maybe there needs to be a callable function in cx88-core or
* the caller of this function needs to do it.
*/
switch (state->config.demod_chip) {
case LGDT3302:
chip_name = "LGDT3302";
err = i2c_write_demod_bytes(state, lgdt3302_init_data,
sizeof(lgdt3302_init_data));
break;
case LGDT3303:
chip_name = "LGDT3303";
switch (state->config.clock_polarity_flip) {
case 2:
err = i2c_write_demod_bytes(state,
flip_2_lgdt3303_init_data,
sizeof(flip_2_lgdt3303_init_data));
break;
case 1:
err = i2c_write_demod_bytes(state,
flip_1_lgdt3303_init_data,
sizeof(flip_1_lgdt3303_init_data));
break;
case 0:
default:
err = i2c_write_demod_bytes(state, lgdt3303_init_data,
sizeof(lgdt3303_init_data));
}
break;
default:
chip_name = "undefined";
dev_warn(&state->client->dev,
"Only LGDT3302 and LGDT3303 are supported chips.\n");
err = -ENODEV;
}
dprintk(state, "Initialized the %s chip\n", chip_name);
if (err < 0)
return err;
p->cnr.len = 1;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.len = 1;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.len = 1;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
state->last_stats_time = 0;
return lgdt330x_sw_reset(state);
}
static int lgdt330x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct lgdt330x_state *state = fe->demodulator_priv;
*ucblocks = state->ucblocks;
return 0;
}
static int lgdt330x_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct lgdt330x_state *state = fe->demodulator_priv;
/*
* Array of byte pairs <address, value>
* to initialize 8VSB for lgdt3303 chip 50 MHz IF
*/
static const u8 lgdt3303_8vsb_44_data[] = {
0x04, 0x00,
0x0d, 0x40,
0x0e, 0x87,
0x0f, 0x8e,
0x10, 0x01,
0x47, 0x8b
};
/*
* Array of byte pairs <address, value>
* to initialize QAM for lgdt3303 chip
*/
static const u8 lgdt3303_qam_data[] = {
0x04, 0x00,
0x0d, 0x00,
0x0e, 0x00,
0x0f, 0x00,
0x10, 0x00,
0x51, 0x63,
0x47, 0x66,
0x48, 0x66,
0x4d, 0x1a,
0x49, 0x08,
0x4a, 0x9b
};
u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
int err = 0;
/* Change only if we are actually changing the modulation */
if (state->current_modulation != p->modulation) {
switch (p->modulation) {
case VSB_8:
dprintk(state, "VSB_8 MODE\n");
/* Select VSB mode */
top_ctrl_cfg[1] = 0x03;
/* Select ANT connector if supported by card */
if (state->config.pll_rf_set)
state->config.pll_rf_set(fe, 1);
if (state->config.demod_chip == LGDT3303) {
err = i2c_write_demod_bytes(state,
lgdt3303_8vsb_44_data,
sizeof(lgdt3303_8vsb_44_data));
}
break;
case QAM_64:
dprintk(state, "QAM_64 MODE\n");
/* Select QAM_64 mode */
top_ctrl_cfg[1] = 0x00;
/* Select CABLE connector if supported by card */
if (state->config.pll_rf_set)
state->config.pll_rf_set(fe, 0);
if (state->config.demod_chip == LGDT3303) {
err = i2c_write_demod_bytes(state,
lgdt3303_qam_data,
sizeof(lgdt3303_qam_data));
}
break;
case QAM_256:
dprintk(state, "QAM_256 MODE\n");
/* Select QAM_256 mode */
top_ctrl_cfg[1] = 0x01;
/* Select CABLE connector if supported by card */
if (state->config.pll_rf_set)
state->config.pll_rf_set(fe, 0);
if (state->config.demod_chip == LGDT3303) {
err = i2c_write_demod_bytes(state,
lgdt3303_qam_data,
sizeof(lgdt3303_qam_data));
}
break;
default:
dev_warn(&state->client->dev,
"%s: Modulation type(%d) UNSUPPORTED\n",
__func__, p->modulation);
return -1;
}
if (err < 0)
dev_warn(&state->client->dev,
"%s: error blasting bytes to lgdt3303 for modulation type(%d)\n",
__func__, p->modulation);
/*
* select serial or parallel MPEG hardware interface
* Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
* Parallel: 0x00
*/
top_ctrl_cfg[1] |= state->config.serial_mpeg;
/* Select the requested mode */
i2c_write_demod_bytes(state, top_ctrl_cfg,
sizeof(top_ctrl_cfg));
if (state->config.set_ts_params)
state->config.set_ts_params(fe, 0);
state->current_modulation = p->modulation;
}
/* Tune to the specified frequency */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* Keep track of the new frequency */
/*
* FIXME this is the wrong way to do this...
* The tuner is shared with the video4linux analog API
*/
state->current_frequency = p->frequency;
lgdt330x_sw_reset(state);
return 0;
}
static int lgdt330x_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct lgdt330x_state *state = fe->demodulator_priv;
p->frequency = state->current_frequency;
return 0;
}
/*
* Calculate SNR estimation (scaled by 2^24)
*
* 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM
* equations from LGDT3303 datasheet. VSB is the same between the '02
* and '03, so maybe QAM is too? Perhaps someone with a newer datasheet
* that has QAM information could verify?
*
* For 8-VSB: (two ways, take your pick)
* LGDT3302:
* SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE)
* LGDT3303:
* SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE)
* LGDT3302 & LGDT3303:
* SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one)
* For 64-QAM:
* SNR = 10 * log10( 688128 / MSEQAM)
* For 256-QAM:
* SNR = 10 * log10( 696320 / MSEQAM)
*
* We re-write the snr equation as:
* SNR * 2^24 = 10*(c - intlog10(MSE))
* Where for 256-QAM, c = log10(696320) * 2^24, and so on.
*/
static u32 calculate_snr(u32 mse, u32 c)
{
if (mse == 0) /* No signal */
return 0;
mse = intlog10(mse);
if (mse > c) {
/*
* Negative SNR, which is possible, but realisticly the
* demod will lose lock before the signal gets this bad.
* The API only allows for unsigned values, so just return 0
*/
return 0;
}
return 10 * (c - mse);
}
static int lgdt3302_read_snr(struct dvb_frontend *fe)
{
struct lgdt330x_state *state = fe->demodulator_priv;
u8 buf[5]; /* read data buffer */
u32 noise; /* noise value */
u32 c; /* per-modulation SNR calculation constant */
switch (state->current_modulation) {
case VSB_8:
i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5);
#ifdef USE_EQMSE
/* Use Equalizer Mean-Square Error Register */
/* SNR for ranges from -15.61 to +41.58 */
noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
c = 69765745; /* log10(25*24^2)*2^24 */
#else
/* Use Phase Tracker Mean-Square Error Register */
/* SNR for ranges from -13.11 to +44.08 */
noise = ((buf[0] & 7 << 3) << 13) | (buf[3] << 8) | buf[4];
c = 73957994; /* log10(25*32^2)*2^24 */
#endif
break;
case QAM_64:
case QAM_256:
i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
noise = ((buf[0] & 3) << 8) | buf[1];
c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
/* log10(688128)*2^24 and log10(696320)*2^24 */
break;
default:
dev_err(&state->client->dev,
"%s: Modulation set to unsupported value\n",
__func__);
state->snr = 0;
return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
}
state->snr = calculate_snr(noise, c);
dprintk(state, "noise = 0x%08x, snr = %d.%02d dB\n", noise,
state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
return 0;
}
static int lgdt3303_read_snr(struct dvb_frontend *fe)
{
struct lgdt330x_state *state = fe->demodulator_priv;
u8 buf[5]; /* read data buffer */
u32 noise; /* noise value */
u32 c; /* per-modulation SNR calculation constant */
switch (state->current_modulation) {
case VSB_8:
i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5);
#ifdef USE_EQMSE
/* Use Equalizer Mean-Square Error Register */
/* SNR for ranges from -16.12 to +44.08 */
noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2];
c = 73957994; /* log10(25*32^2)*2^24 */
#else
/* Use Phase Tracker Mean-Square Error Register */
/* SNR for ranges from -13.11 to +44.08 */
noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
c = 73957994; /* log10(25*32^2)*2^24 */
#endif
break;
case QAM_64:
case QAM_256:
i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
noise = (buf[0] << 8) | buf[1];
c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
/* log10(688128)*2^24 and log10(696320)*2^24 */
break;
default:
dev_err(&state->client->dev,
"%s: Modulation set to unsupported value\n",
__func__);
state->snr = 0;
return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
}
state->snr = calculate_snr(noise, c);
dprintk(state, "noise = 0x%08x, snr = %d.%02d dB\n", noise,
state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
return 0;
}
static int lgdt330x_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct lgdt330x_state *state = fe->demodulator_priv;
*snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
return 0;
}
static int lgdt330x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
/* Calculate Strength from SNR up to 35dB */
/*
* Even though the SNR can go higher than 35dB, there is some comfort
* factor in having a range of strong signals that can show at 100%
*/
struct lgdt330x_state *state = fe->demodulator_priv;
u16 snr;
int ret;
ret = fe->ops.read_snr(fe, &snr);
if (ret != 0)
return ret;
/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
/* scale the range 0 - 35*2^24 into 0 - 65535 */
if (state->snr >= 8960 * 0x10000)
*strength = 0xffff;
else
*strength = state->snr / 8960;
return 0;
}
static int lgdt3302_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct lgdt330x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u8 buf[3];
int err;
*status = 0; /* Reset status result */
/* AGC status register */
i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
dprintk(state, "AGC_STATUS = 0x%02x\n", buf[0]);
if ((buf[0] & 0x0c) == 0x8) {
/*
* Test signal does not exist flag
* as well as the AGC lock flag.
*/
*status |= FE_HAS_SIGNAL;
}
/*
* You must set the Mask bits to 1 in the IRQ_MASK in order
* to see that status bit in the IRQ_STATUS register.
* This is done in SwReset();
*/
/* signal status */
i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
dprintk(state,
"TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n",
buf[0], buf[1], buf[2]);
/* sync status */
if ((buf[2] & 0x03) == 0x01)
*status |= FE_HAS_SYNC;
/* FEC error status */
if ((buf[2] & 0x0c) == 0x08)
*status |= FE_HAS_LOCK | FE_HAS_VITERBI;
/* Carrier Recovery Lock Status Register */
i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
dprintk(state, "CARRIER_LOCK = 0x%02x\n", buf[0]);
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
/* Need to understand why there are 3 lock levels here */
if ((buf[0] & 0x07) == 0x07)
*status |= FE_HAS_CARRIER;
break;
case VSB_8:
if ((buf[0] & 0x80) == 0x80)
*status |= FE_HAS_CARRIER;
break;
default:
dev_warn(&state->client->dev,
"%s: Modulation set to unsupported value\n",
__func__);
}
if (!(*status & FE_HAS_LOCK)) {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
if (state->last_stats_time &&
time_is_after_jiffies(state->last_stats_time))
return 0;
state->last_stats_time = jiffies + msecs_to_jiffies(1000);
err = lgdt3302_read_snr(fe);
if (!err) {
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = (((u64)state->snr) * 1000) >> 24;
} else {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
buf, sizeof(buf));
if (!err) {
state->ucblocks = (buf[0] << 8) | buf[1];
dprintk(state, "UCB = 0x%02x\n", state->ucblocks);
p->block_error.stat[0].uvalue += state->ucblocks;
/* FIXME: what's the basis for block count */
p->block_count.stat[0].uvalue += 10000;
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_count.stat[0].scale = FE_SCALE_COUNTER;
} else {
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int lgdt3303_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct lgdt330x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u8 buf[3];
int err;
*status = 0; /* Reset status result */
/* lgdt3303 AGC status register */
err = i2c_read_demod_bytes(state, 0x58, buf, 1);
if (err < 0)
return err;
dprintk(state, "AGC_STATUS = 0x%02x\n", buf[0]);
if ((buf[0] & 0x21) == 0x01) {
/*
* Test input signal does not exist flag
* as well as the AGC lock flag.
*/
*status |= FE_HAS_SIGNAL;
}
/* Carrier Recovery Lock Status Register */
i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
dprintk(state, "CARRIER_LOCK = 0x%02x\n", buf[0]);
switch (state->current_modulation) {
case QAM_256:
case QAM_64:
/* Need to understand why there are 3 lock levels here */
if ((buf[0] & 0x07) == 0x07)
*status |= FE_HAS_CARRIER;
else
break;
i2c_read_demod_bytes(state, 0x8a, buf, 1);
dprintk(state, "QAM LOCK = 0x%02x\n", buf[0]);
if ((buf[0] & 0x04) == 0x04)
*status |= FE_HAS_SYNC;
if ((buf[0] & 0x01) == 0x01)
*status |= FE_HAS_LOCK;
if ((buf[0] & 0x08) == 0x08)
*status |= FE_HAS_VITERBI;
break;
case VSB_8:
if ((buf[0] & 0x80) == 0x80)
*status |= FE_HAS_CARRIER;
else
break;
i2c_read_demod_bytes(state, 0x38, buf, 1);
dprintk(state, "8-VSB LOCK = 0x%02x\n", buf[0]);
if ((buf[0] & 0x02) == 0x00)
*status |= FE_HAS_SYNC;
if ((buf[0] & 0x01) == 0x01)
*status |= FE_HAS_VITERBI | FE_HAS_LOCK;
break;
default:
dev_warn(&state->client->dev,
"%s: Modulation set to unsupported value\n",
__func__);
}
if (!(*status & FE_HAS_LOCK)) {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
if (state->last_stats_time &&
time_is_after_jiffies(state->last_stats_time))
return 0;
state->last_stats_time = jiffies + msecs_to_jiffies(1000);
err = lgdt3303_read_snr(fe);
if (!err) {
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = (((u64)state->snr) * 1000) >> 24;
} else {
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
buf, sizeof(buf));
if (!err) {
state->ucblocks = (buf[0] << 8) | buf[1];
dprintk(state, "UCB = 0x%02x\n", state->ucblocks);
p->block_error.stat[0].uvalue += state->ucblocks;
/* FIXME: what's the basis for block count */
p->block_count.stat[0].uvalue += 10000;
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_count.stat[0].scale = FE_SCALE_COUNTER;
} else {
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
}
static int
lgdt330x_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fe_tune_settings)
{
/* I have no idea about this - it may not be needed */
fe_tune_settings->min_delay_ms = 500;
fe_tune_settings->step_size = 0;
fe_tune_settings->max_drift = 0;
return 0;
}
static void lgdt330x_release(struct dvb_frontend *fe)
{
struct lgdt330x_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
dev_dbg(&client->dev, "\n");
i2c_unregister_device(client);
}
static struct dvb_frontend *lgdt330x_get_dvb_frontend(struct i2c_client *client)
{
struct lgdt330x_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &state->frontend;
}
static const struct dvb_frontend_ops lgdt3302_ops;
static const struct dvb_frontend_ops lgdt3303_ops;
static int lgdt330x_probe(struct i2c_client *client)
{
struct lgdt330x_state *state = NULL;
u8 buf[1];
/* Allocate memory for the internal state */
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
goto error;
/* Setup the state */
memcpy(&state->config, client->dev.platform_data,
sizeof(state->config));
i2c_set_clientdata(client, state);
state->client = client;
/* Create dvb_frontend */
switch (state->config.demod_chip) {
case LGDT3302:
memcpy(&state->frontend.ops, &lgdt3302_ops,
sizeof(struct dvb_frontend_ops));
break;
case LGDT3303:
memcpy(&state->frontend.ops, &lgdt3303_ops,
sizeof(struct dvb_frontend_ops));
break;
default:
goto error;
}
state->frontend.demodulator_priv = state;
/* Setup get frontend callback */
state->config.get_dvb_frontend = lgdt330x_get_dvb_frontend;
/* Verify communication with demod chip */
if (i2c_read_demod_bytes(state, 2, buf, 1))
goto error;
state->current_frequency = -1;
state->current_modulation = -1;
dev_info(&state->client->dev,
"Demod loaded for LGDT330%s chip\n",
state->config.demod_chip == LGDT3302 ? "2" : "3");
return 0;
error:
kfree(state);
if (debug)
dev_printk(KERN_DEBUG, &client->dev, "Error loading lgdt330x driver\n");
return -ENODEV;
}
struct dvb_frontend *lgdt330x_attach(const struct lgdt330x_config *_config,
u8 demod_address,
struct i2c_adapter *i2c)
{
struct i2c_client *client;
struct i2c_board_info board_info = {};
struct lgdt330x_config config = *_config;
strscpy(board_info.type, "lgdt330x", sizeof(board_info.type));
board_info.addr = demod_address;
board_info.platform_data = &config;
client = i2c_new_client_device(i2c, &board_info);
if (!i2c_client_has_driver(client))
return NULL;
return lgdt330x_get_dvb_frontend(client);
}
EXPORT_SYMBOL_GPL(lgdt330x_attach);
static const struct dvb_frontend_ops lgdt3302_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "LG Electronics LGDT3302 VSB/QAM Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 5056941, /* QAM 64 */
.symbol_rate_max = 10762000, /* VSB 8 */
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = lgdt330x_init,
.set_frontend = lgdt330x_set_parameters,
.get_frontend = lgdt330x_get_frontend,
.get_tune_settings = lgdt330x_get_tune_settings,
.read_status = lgdt3302_read_status,
.read_signal_strength = lgdt330x_read_signal_strength,
.read_snr = lgdt330x_read_snr,
.read_ucblocks = lgdt330x_read_ucblocks,
.release = lgdt330x_release,
};
static const struct dvb_frontend_ops lgdt3303_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "LG Electronics LGDT3303 VSB/QAM Frontend",
.frequency_min_hz = 54 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 5056941, /* QAM 64 */
.symbol_rate_max = 10762000, /* VSB 8 */
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = lgdt330x_init,
.set_frontend = lgdt330x_set_parameters,
.get_frontend = lgdt330x_get_frontend,
.get_tune_settings = lgdt330x_get_tune_settings,
.read_status = lgdt3303_read_status,
.read_signal_strength = lgdt330x_read_signal_strength,
.read_snr = lgdt330x_read_snr,
.read_ucblocks = lgdt330x_read_ucblocks,
.release = lgdt330x_release,
};
static void lgdt330x_remove(struct i2c_client *client)
{
struct lgdt330x_state *state = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
kfree(state);
}
static const struct i2c_device_id lgdt330x_id_table[] = {
{"lgdt330x", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, lgdt330x_id_table);
static struct i2c_driver lgdt330x_driver = {
.driver = {
.name = "lgdt330x",
.suppress_bind_attrs = true,
},
.probe = lgdt330x_probe,
.remove = lgdt330x_remove,
.id_table = lgdt330x_id_table,
};
module_i2c_driver(lgdt330x_driver);
MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
MODULE_AUTHOR("Wilson Michaels");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/lgdt330x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
Driver for the Spase sp887x demodulator
*/
/*
* This driver needs external firmware. Please use the command
* "<kerneldir>/scripts/get_dvb_firmware sp887x" to
* download/extract it, and then copy it to /usr/lib/hotplug/firmware
* or /lib/firmware (depending on configuration of firmware hotplug).
*/
#define SP887X_DEFAULT_FIRMWARE "dvb-fe-sp887x.fw"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "sp887x.h"
struct sp887x_state {
struct i2c_adapter* i2c;
const struct sp887x_config* config;
struct dvb_frontend frontend;
/* demodulator private data */
u8 initialised:1;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "sp887x: " args); \
} while (0)
static int i2c_writebytes (struct sp887x_state* state, u8 *buf, u8 len)
{
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len };
int err;
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
printk ("%s: i2c write error (addr %02x, err == %i)\n",
__func__, state->config->demod_address, err);
return -EREMOTEIO;
}
return 0;
}
static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data)
{
u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 };
int ret;
if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) {
/*
* in case of soft reset we ignore ACK errors...
*/
if (!(reg == 0xf1a && data == 0x000 &&
(ret == -EREMOTEIO || ret == -EFAULT)))
{
printk("%s: writereg error (reg %03x, data %03x, ret == %i)\n",
__func__, reg & 0xffff, data & 0xffff, ret);
return ret;
}
}
return 0;
}
static int sp887x_readreg (struct sp887x_state* state, u16 reg)
{
u8 b0 [] = { reg >> 8 , reg & 0xff };
u8 b1 [2];
int ret;
struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 }};
if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
printk("%s: readreg error (ret == %i)\n", __func__, ret);
return -1;
}
return (((b1[0] << 8) | b1[1]) & 0xfff);
}
static void sp887x_microcontroller_stop (struct sp887x_state* state)
{
dprintk("%s\n", __func__);
sp887x_writereg(state, 0xf08, 0x000);
sp887x_writereg(state, 0xf09, 0x000);
/* microcontroller STOP */
sp887x_writereg(state, 0xf00, 0x000);
}
static void sp887x_microcontroller_start (struct sp887x_state* state)
{
dprintk("%s\n", __func__);
sp887x_writereg(state, 0xf08, 0x000);
sp887x_writereg(state, 0xf09, 0x000);
/* microcontroller START */
sp887x_writereg(state, 0xf00, 0x001);
}
static void sp887x_setup_agc (struct sp887x_state* state)
{
/* setup AGC parameters */
dprintk("%s\n", __func__);
sp887x_writereg(state, 0x33c, 0x054);
sp887x_writereg(state, 0x33b, 0x04c);
sp887x_writereg(state, 0x328, 0x000);
sp887x_writereg(state, 0x327, 0x005);
sp887x_writereg(state, 0x326, 0x001);
sp887x_writereg(state, 0x325, 0x001);
sp887x_writereg(state, 0x324, 0x001);
sp887x_writereg(state, 0x318, 0x050);
sp887x_writereg(state, 0x317, 0x3fe);
sp887x_writereg(state, 0x316, 0x001);
sp887x_writereg(state, 0x313, 0x005);
sp887x_writereg(state, 0x312, 0x002);
sp887x_writereg(state, 0x306, 0x000);
sp887x_writereg(state, 0x303, 0x000);
}
#define BLOCKSIZE 30
#define FW_SIZE 0x4000
/*
* load firmware and setup MPEG interface...
*/
static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw)
{
struct sp887x_state* state = fe->demodulator_priv;
u8 buf [BLOCKSIZE + 2];
int i;
int fw_size = fw->size;
const unsigned char *mem = fw->data + 10;
dprintk("%s\n", __func__);
/* ignore the first 10 bytes, then we expect 0x4000 bytes of firmware */
if (fw_size < FW_SIZE + 10)
return -ENODEV;
/* soft reset */
sp887x_writereg(state, 0xf1a, 0x000);
sp887x_microcontroller_stop (state);
printk ("%s: firmware upload... ", __func__);
/* setup write pointer to -1 (end of memory) */
/* bit 0x8000 in address is set to enable 13bit mode */
sp887x_writereg(state, 0x8f08, 0x1fff);
/* dummy write (wrap around to start of memory) */
sp887x_writereg(state, 0x8f0a, 0x0000);
for (i = 0; i < FW_SIZE; i += BLOCKSIZE) {
int c = BLOCKSIZE;
int err;
if (c > FW_SIZE - i)
c = FW_SIZE - i;
/* bit 0x8000 in address is set to enable 13bit mode */
/* bit 0x4000 enables multibyte read/write transfers */
/* write register is 0xf0a */
buf[0] = 0xcf;
buf[1] = 0x0a;
memcpy(&buf[2], mem + i, c);
if ((err = i2c_writebytes (state, buf, c+2)) < 0) {
printk ("failed.\n");
printk ("%s: i2c error (err == %i)\n", __func__, err);
return err;
}
}
/* don't write RS bytes between packets */
sp887x_writereg(state, 0xc13, 0x001);
/* suppress clock if (!data_valid) */
sp887x_writereg(state, 0xc14, 0x000);
/* setup MPEG interface... */
sp887x_writereg(state, 0xc1a, 0x872);
sp887x_writereg(state, 0xc1b, 0x001);
sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */
sp887x_writereg(state, 0xc1a, 0x871);
/* ADC mode, 2 for MT8872, 3 for SP8870/SP8871 */
sp887x_writereg(state, 0x301, 0x002);
sp887x_setup_agc(state);
/* bit 0x010: enable data valid signal */
sp887x_writereg(state, 0xd00, 0x010);
sp887x_writereg(state, 0x0d1, 0x000);
return 0;
};
static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
{
int known_parameters = 1;
*reg0xc05 = 0x000;
switch (p->modulation) {
case QPSK:
break;
case QAM_16:
*reg0xc05 |= (1 << 10);
break;
case QAM_64:
*reg0xc05 |= (2 << 10);
break;
case QAM_AUTO:
known_parameters = 0;
break;
default:
return -EINVAL;
}
switch (p->hierarchy) {
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
*reg0xc05 |= (1 << 7);
break;
case HIERARCHY_2:
*reg0xc05 |= (2 << 7);
break;
case HIERARCHY_4:
*reg0xc05 |= (3 << 7);
break;
case HIERARCHY_AUTO:
known_parameters = 0;
break;
default:
return -EINVAL;
}
switch (p->code_rate_HP) {
case FEC_1_2:
break;
case FEC_2_3:
*reg0xc05 |= (1 << 3);
break;
case FEC_3_4:
*reg0xc05 |= (2 << 3);
break;
case FEC_5_6:
*reg0xc05 |= (3 << 3);
break;
case FEC_7_8:
*reg0xc05 |= (4 << 3);
break;
case FEC_AUTO:
known_parameters = 0;
break;
default:
return -EINVAL;
}
if (known_parameters)
*reg0xc05 |= (2 << 1); /* use specified parameters */
else
*reg0xc05 |= (1 << 1); /* enable autoprobing */
return 0;
}
/*
* estimates division of two 24bit numbers,
* derived from the ves1820/stv0299 driver code
*/
static void divide (int n, int d, int *quotient_i, int *quotient_f)
{
unsigned int q, r;
r = (n % d) << 8;
q = (r / d);
if (quotient_i)
*quotient_i = q;
if (quotient_f) {
r = (r % d) << 8;
q = (q << 8) | (r / d);
r = (r % d) << 8;
*quotient_f = (q << 8) | (r / d);
}
}
static void sp887x_correct_offsets (struct sp887x_state* state,
struct dtv_frontend_properties *p,
int actual_freq)
{
static const u32 srate_correction [] = { 1879617, 4544878, 8098561 };
int bw_index;
int freq_offset = actual_freq - p->frequency;
int sysclock = 61003; //[kHz]
int ifreq = 36000000;
int freq;
int frequency_shift;
switch (p->bandwidth_hz) {
default:
case 8000000:
bw_index = 0;
break;
case 7000000:
bw_index = 1;
break;
case 6000000:
bw_index = 2;
break;
}
if (p->inversion == INVERSION_ON)
freq = ifreq - freq_offset;
else
freq = ifreq + freq_offset;
divide(freq / 333, sysclock, NULL, &frequency_shift);
if (p->inversion == INVERSION_ON)
frequency_shift = -frequency_shift;
/* sample rate correction */
sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12);
sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff);
/* carrier offset correction */
sp887x_writereg(state, 0x309, frequency_shift >> 12);
sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);
}
static int sp887x_setup_frontend_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct sp887x_state* state = fe->demodulator_priv;
unsigned actual_freq;
int err;
u16 val, reg0xc05;
if (p->bandwidth_hz != 8000000 &&
p->bandwidth_hz != 7000000 &&
p->bandwidth_hz != 6000000)
return -EINVAL;
if ((err = configure_reg0xc05(p, ®0xc05)))
return err;
sp887x_microcontroller_stop(state);
/* setup the PLL */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
if (fe->ops.tuner_ops.get_frequency) {
fe->ops.tuner_ops.get_frequency(fe, &actual_freq);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
} else {
actual_freq = p->frequency;
}
/* read status reg in order to clear <pending irqs */
sp887x_readreg(state, 0x200);
sp887x_correct_offsets(state, p, actual_freq);
/* filter for 6/7/8 Mhz channel */
if (p->bandwidth_hz == 6000000)
val = 2;
else if (p->bandwidth_hz == 7000000)
val = 1;
else
val = 0;
sp887x_writereg(state, 0x311, val);
/* scan order: 2k first = 0, 8k first = 1 */
if (p->transmission_mode == TRANSMISSION_MODE_2K)
sp887x_writereg(state, 0x338, 0x000);
else
sp887x_writereg(state, 0x338, 0x001);
sp887x_writereg(state, 0xc05, reg0xc05);
if (p->bandwidth_hz == 6000000)
val = 2 << 3;
else if (p->bandwidth_hz == 7000000)
val = 3 << 3;
else
val = 0 << 3;
/* enable OFDM and SAW bits as lock indicators in sync register 0xf17,
* optimize algorithm for given bandwidth...
*/
sp887x_writereg(state, 0xf14, 0x160 | val);
sp887x_writereg(state, 0xf15, 0x000);
sp887x_microcontroller_start(state);
return 0;
}
static int sp887x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct sp887x_state* state = fe->demodulator_priv;
u16 snr12 = sp887x_readreg(state, 0xf16);
u16 sync0x200 = sp887x_readreg(state, 0x200);
u16 sync0xf17 = sp887x_readreg(state, 0xf17);
*status = 0;
if (snr12 > 0x00f)
*status |= FE_HAS_SIGNAL;
//if (sync0x200 & 0x004)
// *status |= FE_HAS_SYNC | FE_HAS_CARRIER;
//if (sync0x200 & 0x008)
// *status |= FE_HAS_VITERBI;
if ((sync0xf17 & 0x00f) == 0x002) {
*status |= FE_HAS_LOCK;
*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_CARRIER;
}
if (sync0x200 & 0x001) { /* tuner adjustment requested...*/
int steps = (sync0x200 >> 4) & 0x00f;
if (steps & 0x008)
steps = -steps;
dprintk("sp887x: implement tuner adjustment (%+i steps)!!\n",
steps);
}
return 0;
}
static int sp887x_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct sp887x_state* state = fe->demodulator_priv;
*ber = (sp887x_readreg(state, 0xc08) & 0x3f) |
(sp887x_readreg(state, 0xc07) << 6);
sp887x_writereg(state, 0xc08, 0x000);
sp887x_writereg(state, 0xc07, 0x000);
if (*ber >= 0x3fff0)
*ber = ~0;
return 0;
}
static int sp887x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct sp887x_state* state = fe->demodulator_priv;
u16 snr12 = sp887x_readreg(state, 0xf16);
u32 signal = 3 * (snr12 << 4);
*strength = (signal < 0xffff) ? signal : 0xffff;
return 0;
}
static int sp887x_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct sp887x_state* state = fe->demodulator_priv;
u16 snr12 = sp887x_readreg(state, 0xf16);
*snr = (snr12 << 4) | (snr12 >> 8);
return 0;
}
static int sp887x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct sp887x_state* state = fe->demodulator_priv;
*ucblocks = sp887x_readreg(state, 0xc0c);
if (*ucblocks == 0xfff)
*ucblocks = ~0;
return 0;
}
static int sp887x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct sp887x_state* state = fe->demodulator_priv;
if (enable) {
return sp887x_writereg(state, 0x206, 0x001);
} else {
return sp887x_writereg(state, 0x206, 0x000);
}
}
static int sp887x_sleep(struct dvb_frontend* fe)
{
struct sp887x_state* state = fe->demodulator_priv;
/* tristate TS output and disable interface pins */
sp887x_writereg(state, 0xc18, 0x000);
return 0;
}
static int sp887x_init(struct dvb_frontend* fe)
{
struct sp887x_state* state = fe->demodulator_priv;
const struct firmware *fw = NULL;
int ret;
if (!state->initialised) {
/* request the firmware, this will block until someone uploads it */
printk("sp887x: waiting for firmware upload (%s)...\n", SP887X_DEFAULT_FIRMWARE);
ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE);
if (ret) {
printk("sp887x: no firmware upload (timeout or file not found?)\n");
return ret;
}
ret = sp887x_initial_setup(fe, fw);
release_firmware(fw);
if (ret) {
printk("sp887x: writing firmware to device failed\n");
return ret;
}
printk("sp887x: firmware upload complete\n");
state->initialised = 1;
}
/* enable TS output and interface pins */
sp887x_writereg(state, 0xc18, 0x00d);
return 0;
}
static int sp887x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 350;
fesettings->step_size = 166666*2;
fesettings->max_drift = (166666*2)+1;
return 0;
}
static void sp887x_release(struct dvb_frontend* fe)
{
struct sp887x_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops sp887x_ops;
struct dvb_frontend* sp887x_attach(const struct sp887x_config* config,
struct i2c_adapter* i2c)
{
struct sp887x_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct sp887x_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->initialised = 0;
/* check if the demod is there */
if (sp887x_readreg(state, 0x0200) < 0) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &sp887x_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops sp887x_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Spase SP887x DVB-T",
.frequency_min_hz = 50500 * kHz,
.frequency_max_hz = 858000 * kHz,
.frequency_stepsize_hz = 166666,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_RECOVER
},
.release = sp887x_release,
.init = sp887x_init,
.sleep = sp887x_sleep,
.i2c_gate_ctrl = sp887x_i2c_gate_ctrl,
.set_frontend = sp887x_setup_frontend_parameters,
.get_tune_settings = sp887x_get_tune_settings,
.read_status = sp887x_read_status,
.read_ber = sp887x_read_ber,
.read_signal_strength = sp887x_read_signal_strength,
.read_snr = sp887x_read_snr,
.read_ucblocks = sp887x_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(sp887x_attach);
| linux-master | drivers/media/dvb-frontends/sp887x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Auvitek AU8522 QAM/8VSB demodulator driver
Copyright (C) 2008 Steven Toth <[email protected]>
Copyright (C) 2008 Devin Heitmueller <[email protected]>
Copyright (C) 2005-2008 Auvitek International, Ltd.
Copyright (C) 2012 Michael Krufky <[email protected]>
*/
#include <linux/i2c.h>
#include <media/dvb_frontend.h>
#include "au8522_priv.h"
static int debug;
#define dprintk(arg...)\
do { if (debug)\
printk(arg);\
} while (0)
/* Despite the name "hybrid_tuner", the framework works just as well for
hybrid demodulators as well... */
static LIST_HEAD(hybrid_tuner_instance_list);
static DEFINE_MUTEX(au8522_list_mutex);
/* 16 bit registers, 8 bit values */
int au8522_writereg(struct au8522_state *state, u16 reg, u8 data)
{
int ret;
u8 buf[] = { (reg >> 8) | 0x80, reg & 0xff, data };
struct i2c_msg msg = { .addr = state->config.demod_address,
.flags = 0, .buf = buf, .len = 3 };
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
printk("%s: writereg error (reg == 0x%02x, val == 0x%04x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
EXPORT_SYMBOL(au8522_writereg);
u8 au8522_readreg(struct au8522_state *state, u16 reg)
{
int ret;
u8 b0[] = { (reg >> 8) | 0x40, reg & 0xff };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = state->config.demod_address, .flags = 0,
.buf = b0, .len = 2 },
{ .addr = state->config.demod_address, .flags = I2C_M_RD,
.buf = b1, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
printk(KERN_ERR "%s: readreg error (ret == %i)\n",
__func__, ret);
return b1[0];
}
EXPORT_SYMBOL(au8522_readreg);
int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct au8522_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (state->operational_mode == AU8522_ANALOG_MODE) {
/* We're being asked to manage the gate even though we're
not in digital mode. This can occur if we get switched
over to analog mode before the dvb_frontend kernel thread
has completely shutdown */
return 0;
}
if (enable)
return au8522_writereg(state, 0x106, 1);
else
return au8522_writereg(state, 0x106, 0);
}
EXPORT_SYMBOL(au8522_i2c_gate_ctrl);
int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct au8522_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
return au8522_writereg(state, 0x106, 1);
else
return au8522_writereg(state, 0x106, 0);
}
EXPORT_SYMBOL(au8522_analog_i2c_gate_ctrl);
/* Reset the demod hardware and reset all of the configuration registers
to a default state. */
int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
u8 client_address)
{
int ret;
mutex_lock(&au8522_list_mutex);
ret = hybrid_tuner_request_state(struct au8522_state, (*state),
hybrid_tuner_instance_list,
i2c, client_address, "au8522");
mutex_unlock(&au8522_list_mutex);
return ret;
}
EXPORT_SYMBOL(au8522_get_state);
void au8522_release_state(struct au8522_state *state)
{
mutex_lock(&au8522_list_mutex);
if (state != NULL)
hybrid_tuner_release_state(state);
mutex_unlock(&au8522_list_mutex);
}
EXPORT_SYMBOL(au8522_release_state);
static int au8522_led_gpio_enable(struct au8522_state *state, int onoff)
{
struct au8522_led_config *led_config = state->config.led_cfg;
u8 val;
/* bail out if we can't control an LED */
if (!led_config || !led_config->gpio_output ||
!led_config->gpio_output_enable || !led_config->gpio_output_disable)
return 0;
val = au8522_readreg(state, 0x4000 |
(led_config->gpio_output & ~0xc000));
if (onoff) {
/* enable GPIO output */
val &= ~((led_config->gpio_output_enable >> 8) & 0xff);
val |= (led_config->gpio_output_enable & 0xff);
} else {
/* disable GPIO output */
val &= ~((led_config->gpio_output_disable >> 8) & 0xff);
val |= (led_config->gpio_output_disable & 0xff);
}
return au8522_writereg(state, 0x8000 |
(led_config->gpio_output & ~0xc000), val);
}
/* led = 0 | off
* led = 1 | signal ok
* led = 2 | signal strong
* led < 0 | only light led if leds are currently off
*/
int au8522_led_ctrl(struct au8522_state *state, int led)
{
struct au8522_led_config *led_config = state->config.led_cfg;
int i, ret = 0;
/* bail out if we can't control an LED */
if (!led_config || !led_config->gpio_leds ||
!led_config->num_led_states || !led_config->led_states)
return 0;
if (led < 0) {
/* if LED is already lit, then leave it as-is */
if (state->led_state)
return 0;
else
led *= -1;
}
/* toggle LED if changing state */
if (state->led_state != led) {
u8 val;
dprintk("%s: %d\n", __func__, led);
au8522_led_gpio_enable(state, 1);
val = au8522_readreg(state, 0x4000 |
(led_config->gpio_leds & ~0xc000));
/* start with all leds off */
for (i = 0; i < led_config->num_led_states; i++)
val &= ~led_config->led_states[i];
/* set selected LED state */
if (led < led_config->num_led_states)
val |= led_config->led_states[led];
else if (led_config->num_led_states)
val |=
led_config->led_states[led_config->num_led_states - 1];
ret = au8522_writereg(state, 0x8000 |
(led_config->gpio_leds & ~0xc000), val);
if (ret < 0)
return ret;
state->led_state = led;
if (led == 0)
au8522_led_gpio_enable(state, 0);
}
return 0;
}
EXPORT_SYMBOL(au8522_led_ctrl);
int au8522_init(struct dvb_frontend *fe)
{
struct au8522_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
state->operational_mode = AU8522_DIGITAL_MODE;
/* Clear out any state associated with the digital side of the
chip, so that when it gets powered back up it won't think
that it is already tuned */
state->current_frequency = 0;
state->current_modulation = VSB_8;
au8522_writereg(state, 0xa4, 1 << 5);
au8522_i2c_gate_ctrl(fe, 1);
return 0;
}
EXPORT_SYMBOL(au8522_init);
int au8522_sleep(struct dvb_frontend *fe)
{
struct au8522_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
/* Only power down if the digital side is currently using the chip */
if (state->operational_mode == AU8522_ANALOG_MODE) {
/* We're not in one of the expected power modes, which means
that the DVB thread is probably telling us to go to sleep
even though the analog frontend has already started using
the chip. So ignore the request */
return 0;
}
/* turn off led */
au8522_led_ctrl(state, 0);
/* Power down the chip */
au8522_writereg(state, 0xa4, 1 << 5);
state->current_frequency = 0;
return 0;
}
EXPORT_SYMBOL(au8522_sleep);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
MODULE_DESCRIPTION("Auvitek AU8522 QAM-B/ATSC Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/au8522_common.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner
*
* Copyright (C) 2010 Malcolm Priestley
*/
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "ix2505v.h"
static int ix2505v_debug;
#define dprintk(level, args...) do { \
if (ix2505v_debug & level) \
printk(KERN_DEBUG "ix2505v: " args); \
} while (0)
#define deb_info(args...) dprintk(0x01, args)
#define deb_i2c(args...) dprintk(0x02, args)
struct ix2505v_state {
struct i2c_adapter *i2c;
const struct ix2505v_config *config;
u32 frequency;
};
/*
* Data read format of the Sharp IX2505V B0017
*
* byte1: 1 | 1 | 0 | 0 | 0 | MA1 | MA0 | 1
* byte2: POR | FL | RD2 | RD1 | RD0 | X | X | X
*
* byte1 = address
* byte2;
* POR = Power on Reset (VCC H=<2.2v L=>2.2v)
* FL = Phase Lock (H=lock L=unlock)
* RD0-2 = Reserved internal operations
*
* Only POR can be used to check the tuner is present
*
* Caution: after byte2 the I2C reverts to write mode continuing to read
* may corrupt tuning data.
*
*/
static int ix2505v_read_status_reg(struct ix2505v_state *state)
{
u8 addr = state->config->tuner_address;
u8 b2[] = {0};
int ret;
struct i2c_msg msg[1] = {
{ .addr = addr, .flags = I2C_M_RD, .buf = b2, .len = 1 }
};
ret = i2c_transfer(state->i2c, msg, 1);
deb_i2c("Read %s ", __func__);
return (ret == 1) ? (int) b2[0] : -1;
}
static int ix2505v_write(struct ix2505v_state *state, u8 buf[], u8 count)
{
struct i2c_msg msg[1] = {
{ .addr = state->config->tuner_address, .flags = 0,
.buf = buf, .len = count },
};
int ret;
ret = i2c_transfer(state->i2c, msg, 1);
if (ret != 1) {
deb_i2c("%s: i2c error, ret=%d\n", __func__, ret);
return -EIO;
}
return 0;
}
static void ix2505v_release(struct dvb_frontend *fe)
{
struct ix2505v_state *state = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(state);
}
/*
* Data write format of the Sharp IX2505V B0017
*
* byte1: 1 | 1 | 0 | 0 | 0 | 0(MA1)| 0(MA0)| 0
* byte2: 0 | BG1 | BG2 | N8 | N7 | N6 | N5 | N4
* byte3: N3 | N2 | N1 | A5 | A4 | A3 | A2 | A1
* byte4: 1 | 1(C1) | 1(C0) | PD5 | PD4 | TM | 0(RTS)| 1(REF)
* byte5: BA2 | BA1 | BA0 | PSC | PD3 |PD2/TS2|DIV/TS1|PD0/TS0
*
* byte1 = address
*
* Write order
* 1) byte1 -> byte2 -> byte3 -> byte4 -> byte5
* 2) byte1 -> byte4 -> byte5 -> byte2 -> byte3
* 3) byte1 -> byte2 -> byte3 -> byte4
* 4) byte1 -> byte4 -> byte5 -> byte2
* 5) byte1 -> byte2 -> byte3
* 6) byte1 -> byte4 -> byte5
* 7) byte1 -> byte2
* 8) byte1 -> byte4
*
* Recommended Setup
* 1 -> 8 -> 6
*/
static int ix2505v_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct ix2505v_state *state = fe->tuner_priv;
u32 frequency = c->frequency;
u32 b_w = (c->symbol_rate * 27) / 32000;
u32 div_factor, N , A, x;
int ret = 0, len;
u8 gain, cc, ref, psc, local_osc, lpf;
u8 data[4] = {0};
if ((frequency < fe->ops.info.frequency_min_hz / kHz)
|| (frequency > fe->ops.info.frequency_max_hz / kHz))
return -EINVAL;
if (state->config->tuner_gain)
gain = (state->config->tuner_gain < 4)
? state->config->tuner_gain : 0;
else
gain = 0x0;
if (state->config->tuner_chargepump)
cc = state->config->tuner_chargepump;
else
cc = 0x3;
ref = 8; /* REF =1 */
psc = 32; /* PSC = 0 */
div_factor = (frequency * ref) / 40; /* local osc = 4Mhz */
x = div_factor / psc;
N = x/100;
A = ((x - (N * 100)) * psc) / 100;
data[0] = ((gain & 0x3) << 5) | (N >> 3);
data[1] = (N << 5) | (A & 0x1f);
data[2] = 0x81 | ((cc & 0x3) << 5) ; /*PD5,PD4 & TM = 0|C1,C0|REF=1*/
deb_info("Frq=%d x=%d N=%d A=%d\n", frequency, x, N, A);
if (frequency <= 1065000)
local_osc = (6 << 5) | 2;
else if (frequency <= 1170000)
local_osc = (7 << 5) | 2;
else if (frequency <= 1300000)
local_osc = (1 << 5);
else if (frequency <= 1445000)
local_osc = (2 << 5);
else if (frequency <= 1607000)
local_osc = (3 << 5);
else if (frequency <= 1778000)
local_osc = (4 << 5);
else if (frequency <= 1942000)
local_osc = (5 << 5);
else /*frequency up to 2150000*/
local_osc = (6 << 5);
data[3] = local_osc; /* all other bits set 0 */
if (b_w <= 10000)
lpf = 0xc;
else if (b_w <= 12000)
lpf = 0x2;
else if (b_w <= 14000)
lpf = 0xa;
else if (b_w <= 16000)
lpf = 0x6;
else if (b_w <= 18000)
lpf = 0xe;
else if (b_w <= 20000)
lpf = 0x1;
else if (b_w <= 22000)
lpf = 0x9;
else if (b_w <= 24000)
lpf = 0x5;
else if (b_w <= 26000)
lpf = 0xd;
else if (b_w <= 28000)
lpf = 0x3;
else
lpf = 0xb;
deb_info("Osc=%x b_w=%x lpf=%x\n", local_osc, b_w, lpf);
deb_info("Data 0=[%4phN]\n", data);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
len = sizeof(data);
ret |= ix2505v_write(state, data, len);
data[2] |= 0x4; /* set TM = 1 other bits same */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
len = 1;
ret |= ix2505v_write(state, &data[2], len); /* write byte 4 only */
msleep(10);
data[2] |= ((lpf >> 2) & 0x3) << 3; /* lpf */
data[3] |= (lpf & 0x3) << 2;
deb_info("Data 2=[%x%x]\n", data[2], data[3]);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
len = 2;
ret |= ix2505v_write(state, &data[2], len); /* write byte 4 & 5 */
if (state->config->min_delay_ms)
msleep(state->config->min_delay_ms);
state->frequency = frequency;
return ret;
}
static int ix2505v_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct ix2505v_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static const struct dvb_tuner_ops ix2505v_tuner_ops = {
.info = {
.name = "Sharp IX2505V (B0017)",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2175 * MHz
},
.release = ix2505v_release,
.set_params = ix2505v_set_params,
.get_frequency = ix2505v_get_frequency,
};
struct dvb_frontend *ix2505v_attach(struct dvb_frontend *fe,
const struct ix2505v_config *config,
struct i2c_adapter *i2c)
{
struct ix2505v_state *state = NULL;
int ret;
if (NULL == config) {
deb_i2c("%s: no config ", __func__);
goto error;
}
state = kzalloc(sizeof(struct ix2505v_state), GFP_KERNEL);
if (NULL == state)
return NULL;
state->config = config;
state->i2c = i2c;
if (state->config->tuner_write_only) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
ret = ix2505v_read_status_reg(state);
if (ret & 0x80) {
deb_i2c("%s: No IX2505V found\n", __func__);
goto error;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
fe->tuner_priv = state;
memcpy(&fe->ops.tuner_ops, &ix2505v_tuner_ops,
sizeof(struct dvb_tuner_ops));
deb_i2c("%s: initialization (%s addr=0x%02x) ok\n",
__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
return fe;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(ix2505v_attach);
module_param_named(debug, ix2505v_debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("DVB IX2505V tuner driver");
MODULE_AUTHOR("Malcolm Priestley");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/ix2505v.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Zarlink DVB-T ZL10353 demodulator
*
* Copyright (C) 2006, 2007 Christopher Pascoe <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "zl10353_priv.h"
#include "zl10353.h"
struct zl10353_state {
struct i2c_adapter *i2c;
struct dvb_frontend frontend;
struct zl10353_config config;
u32 bandwidth;
u32 ucblocks;
u32 frequency;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "zl10353: " args); \
} while (0)
static int debug_regs;
static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
struct zl10353_state *state = fe->demodulator_priv;
u8 buf[2] = { reg, val };
struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
.buf = buf, .len = 2 };
int err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
return err;
}
return 0;
}
static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
{
int err, i;
for (i = 0; i < ilen - 1; i++)
if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
return err;
return 0;
}
static int zl10353_read_register(struct zl10353_state *state, u8 reg)
{
int ret;
u8 b0[1] = { reg };
u8 b1[1] = { 0 };
struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
.flags = 0,
.buf = b0, .len = 1 },
{ .addr = state->config.demod_address,
.flags = I2C_M_RD,
.buf = b1, .len = 1 } };
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk("%s: readreg error (reg=%d, ret==%i)\n",
__func__, reg, ret);
return ret;
}
return b1[0];
}
static void zl10353_dump_regs(struct dvb_frontend *fe)
{
struct zl10353_state *state = fe->demodulator_priv;
int ret;
u8 reg;
/* Dump all registers. */
for (reg = 0; ; reg++) {
if (reg % 16 == 0) {
if (reg)
printk(KERN_CONT "\n");
printk(KERN_DEBUG "%02x:", reg);
}
ret = zl10353_read_register(state, reg);
if (ret >= 0)
printk(KERN_CONT " %02x", (u8)ret);
else
printk(KERN_CONT " --");
if (reg == 0xff)
break;
}
printk(KERN_CONT "\n");
}
static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
u32 bandwidth,
u16 *nominal_rate)
{
struct zl10353_state *state = fe->demodulator_priv;
u32 adc_clock = 450560; /* 45.056 MHz */
u64 value;
u8 bw = bandwidth / 1000000;
if (state->config.adc_clock)
adc_clock = state->config.adc_clock;
value = (u64)10 * (1 << 23) / 7 * 125;
value = (bw * value) + adc_clock / 2;
*nominal_rate = div_u64(value, adc_clock);
dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
__func__, bw, adc_clock, *nominal_rate);
}
static void zl10353_calc_input_freq(struct dvb_frontend *fe,
u16 *input_freq)
{
struct zl10353_state *state = fe->demodulator_priv;
u32 adc_clock = 450560; /* 45.056 MHz */
int if2 = 361667; /* 36.1667 MHz */
int ife;
u64 value;
if (state->config.adc_clock)
adc_clock = state->config.adc_clock;
if (state->config.if2)
if2 = state->config.if2;
if (adc_clock >= if2 * 2)
ife = if2;
else {
ife = adc_clock - (if2 % adc_clock);
if (ife > adc_clock / 2)
ife = adc_clock - ife;
}
value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock);
*input_freq = -value;
dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
__func__, if2, ife, adc_clock, -(int)value, *input_freq);
}
static int zl10353_sleep(struct dvb_frontend *fe)
{
static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
return 0;
}
static int zl10353_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct zl10353_state *state = fe->demodulator_priv;
u16 nominal_rate, input_freq;
u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
u16 tps = 0;
state->frequency = c->frequency;
zl10353_single_write(fe, RESET, 0x80);
udelay(200);
zl10353_single_write(fe, 0xEA, 0x01);
udelay(200);
zl10353_single_write(fe, 0xEA, 0x00);
zl10353_single_write(fe, AGC_TARGET, 0x28);
if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
acq_ctl |= (1 << 0);
if (c->guard_interval != GUARD_INTERVAL_AUTO)
acq_ctl |= (1 << 1);
zl10353_single_write(fe, ACQ_CTL, acq_ctl);
switch (c->bandwidth_hz) {
case 6000000:
/* These are extrapolated from the 7 and 8MHz values */
zl10353_single_write(fe, MCLK_RATIO, 0x97);
zl10353_single_write(fe, 0x64, 0x34);
zl10353_single_write(fe, 0xcc, 0xdd);
break;
case 7000000:
zl10353_single_write(fe, MCLK_RATIO, 0x86);
zl10353_single_write(fe, 0x64, 0x35);
zl10353_single_write(fe, 0xcc, 0x73);
break;
default:
c->bandwidth_hz = 8000000;
fallthrough;
case 8000000:
zl10353_single_write(fe, MCLK_RATIO, 0x75);
zl10353_single_write(fe, 0x64, 0x36);
zl10353_single_write(fe, 0xcc, 0x73);
}
zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
state->bandwidth = c->bandwidth_hz;
zl10353_calc_input_freq(fe, &input_freq);
zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
/* Hint at TPS settings */
switch (c->code_rate_HP) {
case FEC_2_3:
tps |= (1 << 7);
break;
case FEC_3_4:
tps |= (2 << 7);
break;
case FEC_5_6:
tps |= (3 << 7);
break;
case FEC_7_8:
tps |= (4 << 7);
break;
case FEC_1_2:
case FEC_AUTO:
break;
default:
return -EINVAL;
}
switch (c->code_rate_LP) {
case FEC_2_3:
tps |= (1 << 4);
break;
case FEC_3_4:
tps |= (2 << 4);
break;
case FEC_5_6:
tps |= (3 << 4);
break;
case FEC_7_8:
tps |= (4 << 4);
break;
case FEC_1_2:
case FEC_AUTO:
break;
case FEC_NONE:
if (c->hierarchy == HIERARCHY_AUTO ||
c->hierarchy == HIERARCHY_NONE)
break;
fallthrough;
default:
return -EINVAL;
}
switch (c->modulation) {
case QPSK:
break;
case QAM_AUTO:
case QAM_16:
tps |= (1 << 13);
break;
case QAM_64:
tps |= (2 << 13);
break;
default:
return -EINVAL;
}
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
case TRANSMISSION_MODE_AUTO:
break;
case TRANSMISSION_MODE_8K:
tps |= (1 << 0);
break;
default:
return -EINVAL;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_1_32:
case GUARD_INTERVAL_AUTO:
break;
case GUARD_INTERVAL_1_16:
tps |= (1 << 2);
break;
case GUARD_INTERVAL_1_8:
tps |= (2 << 2);
break;
case GUARD_INTERVAL_1_4:
tps |= (3 << 2);
break;
default:
return -EINVAL;
}
switch (c->hierarchy) {
case HIERARCHY_AUTO:
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
tps |= (1 << 10);
break;
case HIERARCHY_2:
tps |= (2 << 10);
break;
case HIERARCHY_4:
tps |= (3 << 10);
break;
default:
return -EINVAL;
}
zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
/*
* If there is no tuner attached to the secondary I2C bus, we call
* set_params to program a potential tuner attached somewhere else.
* Otherwise, we update the PLL registers via calc_regs.
*/
if (state->config.no_tuner) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
} else if (fe->ops.tuner_ops.calc_regs) {
fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
pllbuf[1] <<= 1;
zl10353_write(fe, pllbuf, sizeof(pllbuf));
}
zl10353_single_write(fe, 0x5F, 0x13);
/* If no attached tuner or invalid PLL registers, just start the FSM. */
if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
zl10353_single_write(fe, FSM_GO, 0x01);
else
zl10353_single_write(fe, TUNER_GO, 0x01);
return 0;
}
static int zl10353_get_parameters(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct zl10353_state *state = fe->demodulator_priv;
int s6, s9;
u16 tps;
static const u8 tps_fec_to_api[8] = {
FEC_1_2,
FEC_2_3,
FEC_3_4,
FEC_5_6,
FEC_7_8,
FEC_AUTO,
FEC_AUTO,
FEC_AUTO
};
s6 = zl10353_read_register(state, STATUS_6);
s9 = zl10353_read_register(state, STATUS_9);
if (s6 < 0 || s9 < 0)
return -EREMOTEIO;
if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
return -EINVAL; /* no FE or TPS lock */
tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
zl10353_read_register(state, TPS_RECEIVED_0);
c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
switch ((tps >> 13) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
default:
c->modulation = QAM_AUTO;
break;
}
c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
TRANSMISSION_MODE_2K;
switch ((tps >> 2) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
default:
c->guard_interval = GUARD_INTERVAL_AUTO;
break;
}
switch ((tps >> 10) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
default:
c->hierarchy = HIERARCHY_AUTO;
break;
}
c->frequency = state->frequency;
c->bandwidth_hz = state->bandwidth;
c->inversion = INVERSION_AUTO;
return 0;
}
static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct zl10353_state *state = fe->demodulator_priv;
int s6, s7, s8;
if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
return -EREMOTEIO;
if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
return -EREMOTEIO;
if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
return -EREMOTEIO;
*status = 0;
if (s6 & (1 << 2))
*status |= FE_HAS_CARRIER;
if (s6 & (1 << 1))
*status |= FE_HAS_VITERBI;
if (s6 & (1 << 5))
*status |= FE_HAS_LOCK;
if (s7 & (1 << 4))
*status |= FE_HAS_SYNC;
if (s8 & (1 << 6))
*status |= FE_HAS_SIGNAL;
if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
(FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
*status &= ~FE_HAS_LOCK;
return 0;
}
static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct zl10353_state *state = fe->demodulator_priv;
*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
zl10353_read_register(state, RS_ERR_CNT_0);
return 0;
}
static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct zl10353_state *state = fe->demodulator_priv;
u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;
*strength = ~signal;
return 0;
}
static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct zl10353_state *state = fe->demodulator_priv;
u8 _snr;
if (debug_regs)
zl10353_dump_regs(fe);
_snr = zl10353_read_register(state, SNR);
*snr = 10 * _snr / 8;
return 0;
}
static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct zl10353_state *state = fe->demodulator_priv;
u32 ubl = 0;
ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
zl10353_read_register(state, RS_UBC_0);
state->ucblocks += ubl;
*ucblocks = state->ucblocks;
return 0;
}
static int zl10353_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings
*fe_tune_settings)
{
fe_tune_settings->min_delay_ms = 1000;
fe_tune_settings->step_size = 0;
fe_tune_settings->max_drift = 0;
return 0;
}
static int zl10353_init(struct dvb_frontend *fe)
{
struct zl10353_state *state = fe->demodulator_priv;
u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
if (debug_regs)
zl10353_dump_regs(fe);
if (state->config.parallel_ts)
zl10353_reset_attach[2] &= ~0x20;
if (state->config.clock_ctl_1)
zl10353_reset_attach[3] = state->config.clock_ctl_1;
if (state->config.pll_0)
zl10353_reset_attach[4] = state->config.pll_0;
/* Do a "hard" reset if not already done */
if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
zl10353_write(fe, zl10353_reset_attach,
sizeof(zl10353_reset_attach));
if (debug_regs)
zl10353_dump_regs(fe);
}
return 0;
}
static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct zl10353_state *state = fe->demodulator_priv;
u8 val = 0x0a;
if (state->config.disable_i2c_gate_ctrl) {
/* No tuner attached to the internal I2C bus */
/* If set enable I2C bridge, the main I2C bus stopped hardly */
return 0;
}
if (enable)
val |= 0x10;
return zl10353_single_write(fe, 0x62, val);
}
static void zl10353_release(struct dvb_frontend *fe)
{
struct zl10353_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops zl10353_ops;
struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
struct i2c_adapter *i2c)
{
struct zl10353_state *state = NULL;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
memcpy(&state->config, config, sizeof(struct zl10353_config));
/* check if the demod is there */
id = zl10353_read_register(state, CHIP_ID);
if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops zl10353_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Zarlink ZL10353 DVB-T",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.release = zl10353_release,
.init = zl10353_init,
.sleep = zl10353_sleep,
.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
.write = zl10353_write,
.set_frontend = zl10353_set_parameters,
.get_frontend = zl10353_get_parameters,
.get_tune_settings = zl10353_get_tune_settings,
.read_status = zl10353_read_status,
.read_ber = zl10353_read_ber,
.read_signal_strength = zl10353_read_signal_strength,
.read_snr = zl10353_read_snr,
.read_ucblocks = zl10353_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
module_param(debug_regs, int, 0644);
MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
MODULE_AUTHOR("Chris Pascoe");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(zl10353_attach);
| linux-master | drivers/media/dvb-frontends/zl10353.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Frontend driver for the GENPIX 8pks/qpsk/DCII USB2.0 DVB-S module
*
* Copyright (C) 2006,2007 Alan Nisota ([email protected])
* Copyright (C) 2006,2007 Genpix Electronics ([email protected])
*
* Thanks to GENPIX for the sample code used to implement this module.
*
* This module is based off the vp7045 and vp702x modules
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include "gp8psk-fe.h"
#include <media/dvb_frontend.h>
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
struct gp8psk_fe_state {
struct dvb_frontend fe;
void *priv;
const struct gp8psk_fe_ops *ops;
bool is_rev1;
u8 lock;
u16 snr;
unsigned long next_status_check;
unsigned long status_check_interval;
};
static int gp8psk_tuned_to_DCII(struct dvb_frontend *fe)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
u8 status;
st->ops->in(st->priv, GET_8PSK_CONFIG, 0, 0, &status, 1);
return status & bmDCtuned;
}
static int gp8psk_set_tuner_mode(struct dvb_frontend *fe, int mode)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
return st->ops->out(st->priv, SET_8PSK_CONFIG, mode, 0, NULL, 0);
}
static int gp8psk_fe_update_status(struct gp8psk_fe_state *st)
{
u8 buf[6];
if (time_after(jiffies,st->next_status_check)) {
st->ops->in(st->priv, GET_SIGNAL_LOCK, 0, 0, &st->lock, 1);
st->ops->in(st->priv, GET_SIGNAL_STRENGTH, 0, 0, buf, 6);
st->snr = (buf[1]) << 8 | buf[0];
st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000;
}
return 0;
}
static int gp8psk_fe_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
gp8psk_fe_update_status(st);
if (st->lock)
*status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_SIGNAL | FE_HAS_CARRIER;
else
*status = 0;
if (*status & FE_HAS_LOCK)
st->status_check_interval = 1000;
else
st->status_check_interval = 100;
return 0;
}
/* not supported by this Frontend */
static int gp8psk_fe_read_ber(struct dvb_frontend* fe, u32 *ber)
{
(void) fe;
*ber = 0;
return 0;
}
/* not supported by this Frontend */
static int gp8psk_fe_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
{
(void) fe;
*unc = 0;
return 0;
}
static int gp8psk_fe_read_snr(struct dvb_frontend* fe, u16 *snr)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
gp8psk_fe_update_status(st);
/* snr is reported in dBu*256 */
*snr = st->snr;
return 0;
}
static int gp8psk_fe_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
gp8psk_fe_update_status(st);
/* snr is reported in dBu*256 */
/* snr / 38.4 ~= 100% strength */
/* snr * 17 returns 100% strength as 65535 */
if (st->snr > 0xf00)
*strength = 0xffff;
else
*strength = (st->snr << 4) + st->snr; /* snr*17 */
return 0;
}
static int gp8psk_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 800;
return 0;
}
static int gp8psk_fe_set_frontend(struct dvb_frontend *fe)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 cmd[10];
u32 freq = c->frequency * 1000;
dprintk("%s()\n", __func__);
cmd[4] = freq & 0xff;
cmd[5] = (freq >> 8) & 0xff;
cmd[6] = (freq >> 16) & 0xff;
cmd[7] = (freq >> 24) & 0xff;
/* backwards compatibility: DVB-S + 8-PSK were used for Turbo-FEC */
if (c->delivery_system == SYS_DVBS && c->modulation == PSK_8)
c->delivery_system = SYS_TURBO;
switch (c->delivery_system) {
case SYS_DVBS:
if (c->modulation != QPSK) {
dprintk("%s: unsupported modulation selected (%d)\n",
__func__, c->modulation);
return -EOPNOTSUPP;
}
c->fec_inner = FEC_AUTO;
break;
case SYS_DVBS2: /* kept for backwards compatibility */
dprintk("%s: DVB-S2 delivery system selected\n", __func__);
break;
case SYS_TURBO:
dprintk("%s: Turbo-FEC delivery system selected\n", __func__);
break;
default:
dprintk("%s: unsupported delivery system selected (%d)\n",
__func__, c->delivery_system);
return -EOPNOTSUPP;
}
cmd[0] = c->symbol_rate & 0xff;
cmd[1] = (c->symbol_rate >> 8) & 0xff;
cmd[2] = (c->symbol_rate >> 16) & 0xff;
cmd[3] = (c->symbol_rate >> 24) & 0xff;
switch (c->modulation) {
case QPSK:
if (st->is_rev1)
if (gp8psk_tuned_to_DCII(fe))
st->ops->reload(st->priv);
switch (c->fec_inner) {
case FEC_1_2:
cmd[9] = 0; break;
case FEC_2_3:
cmd[9] = 1; break;
case FEC_3_4:
cmd[9] = 2; break;
case FEC_5_6:
cmd[9] = 3; break;
case FEC_7_8:
cmd[9] = 4; break;
case FEC_AUTO:
cmd[9] = 5; break;
default:
cmd[9] = 5; break;
}
if (c->delivery_system == SYS_TURBO)
cmd[8] = ADV_MOD_TURBO_QPSK;
else
cmd[8] = ADV_MOD_DVB_QPSK;
break;
case PSK_8: /* PSK_8 is for compatibility with DN */
cmd[8] = ADV_MOD_TURBO_8PSK;
switch (c->fec_inner) {
case FEC_2_3:
cmd[9] = 0; break;
case FEC_3_4:
cmd[9] = 1; break;
case FEC_3_5:
cmd[9] = 2; break;
case FEC_5_6:
cmd[9] = 3; break;
case FEC_8_9:
cmd[9] = 4; break;
default:
cmd[9] = 0; break;
}
break;
case QAM_16: /* QAM_16 is for compatibility with DN */
cmd[8] = ADV_MOD_TURBO_16QAM;
cmd[9] = 0;
break;
default: /* Unknown modulation */
dprintk("%s: unsupported modulation selected (%d)\n",
__func__, c->modulation);
return -EOPNOTSUPP;
}
if (st->is_rev1)
gp8psk_set_tuner_mode(fe, 0);
st->ops->out(st->priv, TUNE_8PSK, 0, 0, cmd, 10);
st->lock = 0;
st->next_status_check = jiffies;
st->status_check_interval = 200;
return 0;
}
static int gp8psk_fe_send_diseqc_msg (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd *m)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (st->ops->out(st->priv, SEND_DISEQC_COMMAND, m->msg[0], 0,
m->msg, m->msg_len)) {
return -EINVAL;
}
return 0;
}
static int gp8psk_fe_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
u8 cmd;
dprintk("%s\n", __func__);
/* These commands are certainly wrong */
cmd = (burst == SEC_MINI_A) ? 0x00 : 0x01;
if (st->ops->out(st->priv, SEND_DISEQC_COMMAND, cmd, 0,
&cmd, 0)) {
return -EINVAL;
}
return 0;
}
static int gp8psk_fe_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
if (st->ops->out(st->priv, SET_22KHZ_TONE,
(tone == SEC_TONE_ON), 0, NULL, 0)) {
return -EINVAL;
}
return 0;
}
static int gp8psk_fe_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
if (st->ops->out(st->priv, SET_LNB_VOLTAGE,
voltage == SEC_VOLTAGE_18, 0, NULL, 0)) {
return -EINVAL;
}
return 0;
}
static int gp8psk_fe_enable_high_lnb_voltage(struct dvb_frontend* fe, long onoff)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
return st->ops->out(st->priv, USE_EXTRA_VOLT, onoff, 0, NULL, 0);
}
static int gp8psk_fe_send_legacy_dish_cmd (struct dvb_frontend* fe, unsigned long sw_cmd)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
u8 cmd = sw_cmd & 0x7f;
if (st->ops->out(st->priv, SET_DN_SWITCH, cmd, 0, NULL, 0))
return -EINVAL;
if (st->ops->out(st->priv, SET_LNB_VOLTAGE, !!(sw_cmd & 0x80),
0, NULL, 0))
return -EINVAL;
return 0;
}
static void gp8psk_fe_release(struct dvb_frontend* fe)
{
struct gp8psk_fe_state *st = fe->demodulator_priv;
kfree(st);
}
static const struct dvb_frontend_ops gp8psk_fe_ops;
struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops,
void *priv, bool is_rev1)
{
struct gp8psk_fe_state *st;
if (!ops || !ops->in || !ops->out || !ops->reload) {
pr_err("Error! gp8psk-fe ops not defined.\n");
return NULL;
}
st = kzalloc(sizeof(struct gp8psk_fe_state), GFP_KERNEL);
if (!st)
return NULL;
memcpy(&st->fe.ops, &gp8psk_fe_ops, sizeof(struct dvb_frontend_ops));
st->fe.demodulator_priv = st;
st->ops = ops;
st->priv = priv;
st->is_rev1 = is_rev1;
pr_info("Frontend %sattached\n", is_rev1 ? "revision 1 " : "");
return &st->fe;
}
EXPORT_SYMBOL_GPL(gp8psk_fe_attach);
static const struct dvb_frontend_ops gp8psk_fe_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Genpix DVB-S",
.frequency_min_hz = 800 * MHz,
.frequency_max_hz = 2250 * MHz,
.frequency_stepsize_hz = 100 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500, /* ppm */
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
/*
* FE_CAN_QAM_16 is for compatibility
* (Myth incorrectly detects Turbo-QPSK as plain QAM-16)
*/
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_TURBO_FEC
},
.release = gp8psk_fe_release,
.init = NULL,
.sleep = NULL,
.set_frontend = gp8psk_fe_set_frontend,
.get_tune_settings = gp8psk_fe_get_tune_settings,
.read_status = gp8psk_fe_read_status,
.read_ber = gp8psk_fe_read_ber,
.read_signal_strength = gp8psk_fe_read_signal_strength,
.read_snr = gp8psk_fe_read_snr,
.read_ucblocks = gp8psk_fe_read_unc_blocks,
.diseqc_send_master_cmd = gp8psk_fe_send_diseqc_msg,
.diseqc_send_burst = gp8psk_fe_send_diseqc_burst,
.set_tone = gp8psk_fe_set_tone,
.set_voltage = gp8psk_fe_set_voltage,
.dishnetwork_send_legacy_command = gp8psk_fe_send_legacy_dish_cmd,
.enable_high_lnb_voltage = gp8psk_fe_enable_high_lnb_voltage
};
MODULE_AUTHOR("Alan Nisota <[email protected]>");
MODULE_DESCRIPTION("Frontend Driver for Genpix DVB-S");
MODULE_VERSION("1.1");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/gp8psk-fe.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CIMaX SP2/SP2HF (Atmel T90FJR) CI driver
*
* Copyright (C) 2014 Olli Salonen <[email protected]>
*
* Heavily based on CIMax2(R) SP2 driver in conjunction with NetUp Dual
* DVB-S2 CI card (cimax2) with following copyrights:
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
* Copyright (C) 2009 Abylay Ospan <[email protected]>
*/
#include "sp2_priv.h"
static int sp2_read_i2c(struct sp2 *s, u8 reg, u8 *buf, int len)
{
int ret;
struct i2c_client *client = s->client;
struct i2c_adapter *adap = client->adapter;
struct i2c_msg msg[] = {
{
.addr = client->addr,
.flags = 0,
.buf = ®,
.len = 1
}, {
.addr = client->addr,
.flags = I2C_M_RD,
.buf = buf,
.len = len
}
};
ret = i2c_transfer(adap, msg, 2);
if (ret != 2) {
dev_err(&client->dev, "i2c read error, reg = 0x%02x, status = %d\n",
reg, ret);
if (ret < 0)
return ret;
else
return -EIO;
}
dev_dbg(&s->client->dev, "addr=0x%04x, reg = 0x%02x, data = %02x\n",
client->addr, reg, buf[0]);
return 0;
}
static int sp2_write_i2c(struct sp2 *s, u8 reg, u8 *buf, int len)
{
int ret;
u8 buffer[35];
struct i2c_client *client = s->client;
struct i2c_adapter *adap = client->adapter;
struct i2c_msg msg = {
.addr = client->addr,
.flags = 0,
.buf = &buffer[0],
.len = len + 1
};
if ((len + 1) > sizeof(buffer)) {
dev_err(&client->dev, "i2c wr reg=%02x: len=%d is too big!\n",
reg, len);
return -EINVAL;
}
buffer[0] = reg;
memcpy(&buffer[1], buf, len);
ret = i2c_transfer(adap, &msg, 1);
if (ret != 1) {
dev_err(&client->dev, "i2c write error, reg = 0x%02x, status = %d\n",
reg, ret);
if (ret < 0)
return ret;
else
return -EIO;
}
dev_dbg(&s->client->dev, "addr=0x%04x, reg = 0x%02x, data = %*ph\n",
client->addr, reg, len, buf);
return 0;
}
static int sp2_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, u8 acs,
u8 read, int addr, u8 data)
{
struct sp2 *s = en50221->data;
u8 store;
int mem, ret;
int (*ci_op_cam)(void*, u8, int, u8, int*) = s->ci_control;
if (slot != 0)
return -EINVAL;
/*
* change module access type between IO space and attribute memory
* when needed
*/
if (s->module_access_type != acs) {
ret = sp2_read_i2c(s, 0x00, &store, 1);
if (ret)
return ret;
store &= ~(SP2_MOD_CTL_ACS1 | SP2_MOD_CTL_ACS0);
store |= acs;
ret = sp2_write_i2c(s, 0x00, &store, 1);
if (ret)
return ret;
}
s->module_access_type = acs;
/* implementation of ci_op_cam is device specific */
if (ci_op_cam) {
ret = ci_op_cam(s->priv, read, addr, data, &mem);
} else {
dev_err(&s->client->dev, "callback not defined");
return -EINVAL;
}
if (ret)
return ret;
dev_dbg(&s->client->dev, "%s: slot=%d, addr=0x%04x, %s, data=%x",
(read) ? "read" : "write", slot, addr,
(acs == SP2_CI_ATTR_ACS) ? "attr" : "io",
(read) ? mem : data);
if (read)
return mem;
else
return 0;
}
int sp2_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr)
{
return sp2_ci_op_cam(en50221, slot, SP2_CI_ATTR_ACS,
SP2_CI_RD, addr, 0);
}
int sp2_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr, u8 data)
{
return sp2_ci_op_cam(en50221, slot, SP2_CI_ATTR_ACS,
SP2_CI_WR, addr, data);
}
int sp2_ci_read_cam_control(struct dvb_ca_en50221 *en50221,
int slot, u8 addr)
{
return sp2_ci_op_cam(en50221, slot, SP2_CI_IO_ACS,
SP2_CI_RD, addr, 0);
}
int sp2_ci_write_cam_control(struct dvb_ca_en50221 *en50221,
int slot, u8 addr, u8 data)
{
return sp2_ci_op_cam(en50221, slot, SP2_CI_IO_ACS,
SP2_CI_WR, addr, data);
}
int sp2_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
{
struct sp2 *s = en50221->data;
u8 buf;
int ret;
dev_dbg(&s->client->dev, "slot: %d\n", slot);
if (slot != 0)
return -EINVAL;
/* RST on */
buf = SP2_MOD_CTL_RST;
ret = sp2_write_i2c(s, 0x00, &buf, 1);
if (ret)
return ret;
usleep_range(500, 600);
/* RST off */
buf = 0x00;
ret = sp2_write_i2c(s, 0x00, &buf, 1);
if (ret)
return ret;
msleep(1000);
return 0;
}
int sp2_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
{
struct sp2 *s = en50221->data;
dev_dbg(&s->client->dev, "slot:%d\n", slot);
/* not implemented */
return 0;
}
int sp2_ci_slot_ts_enable(struct dvb_ca_en50221 *en50221, int slot)
{
struct sp2 *s = en50221->data;
u8 buf;
dev_dbg(&s->client->dev, "slot:%d\n", slot);
if (slot != 0)
return -EINVAL;
sp2_read_i2c(s, 0x00, &buf, 1);
/* disable bypass and enable TS */
buf |= (SP2_MOD_CTL_TSOEN | SP2_MOD_CTL_TSIEN);
return sp2_write_i2c(s, 0, &buf, 1);
}
int sp2_ci_poll_slot_status(struct dvb_ca_en50221 *en50221,
int slot, int open)
{
struct sp2 *s = en50221->data;
u8 buf[2];
int ret;
dev_dbg(&s->client->dev, "slot:%d open:%d\n", slot, open);
/*
* CAM module INSERT/REMOVE processing. Slow operation because of i2c
* transfers. Throttle read to one per sec.
*/
if (time_after(jiffies, s->next_status_checked_time)) {
ret = sp2_read_i2c(s, 0x00, buf, 1);
s->next_status_checked_time = jiffies + msecs_to_jiffies(1000);
if (ret)
return 0;
if (buf[0] & SP2_MOD_CTL_DET)
s->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY;
else
s->status = 0;
}
return s->status;
}
static int sp2_init(struct sp2 *s)
{
int ret = 0;
u8 buf;
u8 cimax_init[34] = {
0x00, /* module A control*/
0x00, /* auto select mask high A */
0x00, /* auto select mask low A */
0x00, /* auto select pattern high A */
0x00, /* auto select pattern low A */
0x44, /* memory access time A, 600 ns */
0x00, /* invert input A */
0x00, /* RFU */
0x00, /* RFU */
0x00, /* module B control*/
0x00, /* auto select mask high B */
0x00, /* auto select mask low B */
0x00, /* auto select pattern high B */
0x00, /* auto select pattern low B */
0x44, /* memory access time B, 600 ns */
0x00, /* invert input B */
0x00, /* RFU */
0x00, /* RFU */
0x00, /* auto select mask high Ext */
0x00, /* auto select mask low Ext */
0x00, /* auto select pattern high Ext */
0x00, /* auto select pattern low Ext */
0x00, /* RFU */
0x02, /* destination - module A */
0x01, /* power control reg, VCC power on */
0x00, /* RFU */
0x00, /* int status read only */
0x00, /* Interrupt Mask Register */
0x05, /* EXTINT=active-high, INT=push-pull */
0x00, /* USCG1 */
0x04, /* ack active low */
0x00, /* LOCK = 0 */
0x22, /* unknown */
0x00, /* synchronization? */
};
dev_dbg(&s->client->dev, "\n");
s->ca.owner = THIS_MODULE;
s->ca.read_attribute_mem = sp2_ci_read_attribute_mem;
s->ca.write_attribute_mem = sp2_ci_write_attribute_mem;
s->ca.read_cam_control = sp2_ci_read_cam_control;
s->ca.write_cam_control = sp2_ci_write_cam_control;
s->ca.slot_reset = sp2_ci_slot_reset;
s->ca.slot_shutdown = sp2_ci_slot_shutdown;
s->ca.slot_ts_enable = sp2_ci_slot_ts_enable;
s->ca.poll_slot_status = sp2_ci_poll_slot_status;
s->ca.data = s;
s->module_access_type = 0;
/* initialize all regs */
ret = sp2_write_i2c(s, 0x00, &cimax_init[0], 34);
if (ret)
goto err;
/* lock registers */
buf = 1;
ret = sp2_write_i2c(s, 0x1f, &buf, 1);
if (ret)
goto err;
/* power on slots */
ret = sp2_write_i2c(s, 0x18, &buf, 1);
if (ret)
goto err;
ret = dvb_ca_en50221_init(s->dvb_adap, &s->ca, 0, 1);
if (ret)
goto err;
return 0;
err:
dev_dbg(&s->client->dev, "init failed=%d\n", ret);
return ret;
}
static int sp2_exit(struct i2c_client *client)
{
struct sp2 *s;
dev_dbg(&client->dev, "\n");
if (!client)
return 0;
s = i2c_get_clientdata(client);
if (!s)
return 0;
if (!s->ca.data)
return 0;
dvb_ca_en50221_release(&s->ca);
return 0;
}
static int sp2_probe(struct i2c_client *client)
{
struct sp2_config *cfg = client->dev.platform_data;
struct sp2 *s;
int ret;
dev_dbg(&client->dev, "\n");
s = kzalloc(sizeof(*s), GFP_KERNEL);
if (!s) {
ret = -ENOMEM;
goto err;
}
s->client = client;
s->dvb_adap = cfg->dvb_adap;
s->priv = cfg->priv;
s->ci_control = cfg->ci_control;
i2c_set_clientdata(client, s);
ret = sp2_init(s);
if (ret)
goto err;
dev_info(&s->client->dev, "CIMaX SP2 successfully attached\n");
return 0;
err:
dev_dbg(&client->dev, "init failed=%d\n", ret);
kfree(s);
return ret;
}
static void sp2_remove(struct i2c_client *client)
{
struct sp2 *s = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
sp2_exit(client);
kfree(s);
}
static const struct i2c_device_id sp2_id[] = {
{"sp2", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, sp2_id);
static struct i2c_driver sp2_driver = {
.driver = {
.name = "sp2",
},
.probe = sp2_probe,
.remove = sp2_remove,
.id_table = sp2_id,
};
module_i2c_driver(sp2_driver);
MODULE_DESCRIPTION("CIMaX SP2/HF CI driver");
MODULE_AUTHOR("Olli Salonen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/sp2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* NXP TDA10071 + Conexant CX24118A DVB-S/S2 demodulator + tuner driver
*
* Copyright (C) 2011 Antti Palosaari <[email protected]>
*/
#include "tda10071_priv.h"
static const struct dvb_frontend_ops tda10071_ops;
/*
* XXX: regmap_update_bits() does not fit our needs as it does not support
* partially volatile registers. Also it performs register read even mask is as
* wide as register value.
*/
/* write single register with mask */
static int tda10071_wr_reg_mask(struct tda10071_dev *dev,
u8 reg, u8 val, u8 mask)
{
int ret;
u8 tmp;
/* no need for read if whole reg is written */
if (mask != 0xff) {
ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
if (ret)
return ret;
val &= mask;
tmp &= ~mask;
val |= tmp;
}
return regmap_bulk_write(dev->regmap, reg, &val, 1);
}
/* execute firmware command */
static int tda10071_cmd_execute(struct tda10071_dev *dev,
struct tda10071_cmd *cmd)
{
struct i2c_client *client = dev->client;
int ret, i;
unsigned int uitmp;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
mutex_lock(&dev->cmd_execute_mutex);
/* write cmd and args for firmware */
ret = regmap_bulk_write(dev->regmap, 0x00, cmd->args, cmd->len);
if (ret)
goto error_mutex_unlock;
/* start cmd execution */
ret = regmap_write(dev->regmap, 0x1f, 1);
if (ret)
goto error_mutex_unlock;
/* wait cmd execution terminate */
for (i = 1000, uitmp = 1; i && uitmp; i--) {
ret = regmap_read(dev->regmap, 0x1f, &uitmp);
if (ret)
goto error_mutex_unlock;
usleep_range(200, 5000);
}
mutex_unlock(&dev->cmd_execute_mutex);
dev_dbg(&client->dev, "loop=%d\n", i);
if (i == 0) {
ret = -ETIMEDOUT;
goto error;
}
return ret;
error_mutex_unlock:
mutex_unlock(&dev->cmd_execute_mutex);
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode fe_sec_tone_mode)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret;
u8 tone;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
dev_dbg(&client->dev, "tone_mode=%d\n", fe_sec_tone_mode);
switch (fe_sec_tone_mode) {
case SEC_TONE_ON:
tone = 1;
break;
case SEC_TONE_OFF:
tone = 0;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
ret = -EINVAL;
goto error;
}
cmd.args[0] = CMD_LNB_PCB_CONFIG;
cmd.args[1] = 0;
cmd.args[2] = 0x00;
cmd.args[3] = 0x00;
cmd.args[4] = tone;
cmd.len = 5;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage fe_sec_voltage)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret;
u8 voltage;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
dev_dbg(&client->dev, "voltage=%d\n", fe_sec_voltage);
switch (fe_sec_voltage) {
case SEC_VOLTAGE_13:
voltage = 0;
break;
case SEC_VOLTAGE_18:
voltage = 1;
break;
case SEC_VOLTAGE_OFF:
voltage = 0;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
ret = -EINVAL;
goto error;
}
cmd.args[0] = CMD_LNB_SET_DC_LEVEL;
cmd.args[1] = 0;
cmd.args[2] = voltage;
cmd.len = 3;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_diseqc_send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *diseqc_cmd)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret, i;
unsigned int uitmp;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
dev_dbg(&client->dev, "msg_len=%d\n", diseqc_cmd->msg_len);
if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
ret = -EINVAL;
goto error;
}
/* wait LNB TX */
for (i = 500, uitmp = 0; i && !uitmp; i--) {
ret = regmap_read(dev->regmap, 0x47, &uitmp);
if (ret)
goto error;
uitmp = (uitmp >> 0) & 1;
usleep_range(10000, 20000);
}
dev_dbg(&client->dev, "loop=%d\n", i);
if (i == 0) {
ret = -ETIMEDOUT;
goto error;
}
ret = regmap_update_bits(dev->regmap, 0x47, 0x01, 0x00);
if (ret)
goto error;
cmd.args[0] = CMD_LNB_SEND_DISEQC;
cmd.args[1] = 0;
cmd.args[2] = 0;
cmd.args[3] = 0;
cmd.args[4] = 2;
cmd.args[5] = 0;
cmd.args[6] = diseqc_cmd->msg_len;
memcpy(&cmd.args[7], diseqc_cmd->msg, diseqc_cmd->msg_len);
cmd.len = 7 + diseqc_cmd->msg_len;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_diseqc_recv_slave_reply(struct dvb_frontend *fe,
struct dvb_diseqc_slave_reply *reply)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret, i;
unsigned int uitmp;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
dev_dbg(&client->dev, "\n");
/* wait LNB RX */
for (i = 500, uitmp = 0; i && !uitmp; i--) {
ret = regmap_read(dev->regmap, 0x47, &uitmp);
if (ret)
goto error;
uitmp = (uitmp >> 1) & 1;
usleep_range(10000, 20000);
}
dev_dbg(&client->dev, "loop=%d\n", i);
if (i == 0) {
ret = -ETIMEDOUT;
goto error;
}
/* reply len */
ret = regmap_read(dev->regmap, 0x46, &uitmp);
if (ret)
goto error;
reply->msg_len = uitmp & 0x1f; /* [4:0] */
if (reply->msg_len > sizeof(reply->msg))
reply->msg_len = sizeof(reply->msg); /* truncate API max */
/* read reply */
cmd.args[0] = CMD_LNB_UPDATE_REPLY;
cmd.args[1] = 0;
cmd.len = 2;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
ret = regmap_bulk_read(dev->regmap, cmd.len, reply->msg,
reply->msg_len);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd fe_sec_mini_cmd)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret, i;
unsigned int uitmp;
u8 burst;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
switch (fe_sec_mini_cmd) {
case SEC_MINI_A:
burst = 0;
break;
case SEC_MINI_B:
burst = 1;
break;
default:
dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
ret = -EINVAL;
goto error;
}
/* wait LNB TX */
for (i = 500, uitmp = 0; i && !uitmp; i--) {
ret = regmap_read(dev->regmap, 0x47, &uitmp);
if (ret)
goto error;
uitmp = (uitmp >> 0) & 1;
usleep_range(10000, 20000);
}
dev_dbg(&client->dev, "loop=%d\n", i);
if (i == 0) {
ret = -ETIMEDOUT;
goto error;
}
ret = regmap_update_bits(dev->regmap, 0x47, 0x01, 0x00);
if (ret)
goto error;
cmd.args[0] = CMD_LNB_SEND_TONEBURST;
cmd.args[1] = 0;
cmd.args[2] = burst;
cmd.len = 3;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tda10071_cmd cmd;
int ret;
unsigned int uitmp;
u8 buf[8];
*status = 0;
if (!dev->warm) {
ret = 0;
goto error;
}
ret = regmap_read(dev->regmap, 0x39, &uitmp);
if (ret)
goto error;
/* 0x39[0] tuner PLL */
if (uitmp & 0x02) /* demod PLL */
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
if (uitmp & 0x04) /* viterbi or LDPC*/
*status |= FE_HAS_VITERBI;
if (uitmp & 0x08) /* RS or BCH */
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
dev->fe_status = *status;
/* signal strength */
if (dev->fe_status & FE_HAS_SIGNAL) {
cmd.args[0] = CMD_GET_AGCACC;
cmd.args[1] = 0;
cmd.len = 2;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
/* input power estimate dBm */
ret = regmap_read(dev->regmap, 0x50, &uitmp);
if (ret)
goto error;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = (int) (uitmp - 256) * 1000;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (dev->fe_status & FE_HAS_VITERBI) {
/* Es/No */
ret = regmap_bulk_read(dev->regmap, 0x3a, buf, 2);
if (ret)
goto error;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = (buf[0] << 8 | buf[1] << 0) * 100;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* UCB/PER/BER */
if (dev->fe_status & FE_HAS_LOCK) {
/* TODO: report total bits/packets */
u8 delivery_system, reg, len;
switch (dev->delivery_system) {
case SYS_DVBS:
reg = 0x4c;
len = 8;
delivery_system = 1;
break;
case SYS_DVBS2:
reg = 0x4d;
len = 4;
delivery_system = 0;
break;
default:
ret = -EINVAL;
goto error;
}
ret = regmap_read(dev->regmap, reg, &uitmp);
if (ret)
goto error;
if (dev->meas_count == uitmp) {
dev_dbg(&client->dev, "meas not ready=%02x\n", uitmp);
ret = 0;
goto error;
} else {
dev->meas_count = uitmp;
}
cmd.args[0] = CMD_BER_UPDATE_COUNTERS;
cmd.args[1] = 0;
cmd.args[2] = delivery_system;
cmd.len = 3;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
ret = regmap_bulk_read(dev->regmap, cmd.len, buf, len);
if (ret)
goto error;
if (dev->delivery_system == SYS_DVBS) {
u32 bit_error = buf[0] << 24 | buf[1] << 16 |
buf[2] << 8 | buf[3] << 0;
dev->dvbv3_ber = bit_error;
dev->post_bit_error += bit_error;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
dev->block_error += buf[4] << 8 | buf[5] << 0;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = dev->block_error;
} else {
dev->dvbv3_ber = buf[0] << 8 | buf[1] << 0;
dev->post_bit_error += buf[0] << 8 | buf[1] << 0;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int tda10071_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
unsigned int uitmp;
if (c->strength.stat[0].scale == FE_SCALE_DECIBEL) {
uitmp = div_s64(c->strength.stat[0].svalue, 1000) + 256;
uitmp = clamp(uitmp, 181U, 236U); /* -75dBm - -20dBm */
/* scale value to 0x0000-0xffff */
*strength = (uitmp-181) * 0xffff / (236-181);
} else {
*strength = 0;
}
return 0;
}
static int tda10071_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct tda10071_dev *dev = fe->demodulator_priv;
*ber = dev->dvbv3_ber;
return 0;
}
static int tda10071_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->block_error.stat[0].scale == FE_SCALE_COUNTER)
*ucblocks = c->block_error.stat[0].uvalue;
else
*ucblocks = 0;
return 0;
}
static int tda10071_set_frontend(struct dvb_frontend *fe)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
u8 mode, rolloff, pilot, inversion, div;
enum fe_modulation modulation;
dev_dbg(&client->dev,
"delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
c->inversion, c->pilot, c->rolloff);
dev->delivery_system = SYS_UNDEFINED;
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
switch (c->inversion) {
case INVERSION_OFF:
inversion = 1;
break;
case INVERSION_ON:
inversion = 0;
break;
case INVERSION_AUTO:
/* 2 = auto; try first on then off
* 3 = auto; try first off then on */
inversion = 3;
break;
default:
dev_dbg(&client->dev, "invalid inversion\n");
ret = -EINVAL;
goto error;
}
switch (c->delivery_system) {
case SYS_DVBS:
modulation = QPSK;
rolloff = 0;
pilot = 2;
break;
case SYS_DVBS2:
modulation = c->modulation;
switch (c->rolloff) {
case ROLLOFF_20:
rolloff = 2;
break;
case ROLLOFF_25:
rolloff = 1;
break;
case ROLLOFF_35:
rolloff = 0;
break;
case ROLLOFF_AUTO:
default:
dev_dbg(&client->dev, "invalid rolloff\n");
ret = -EINVAL;
goto error;
}
switch (c->pilot) {
case PILOT_OFF:
pilot = 0;
break;
case PILOT_ON:
pilot = 1;
break;
case PILOT_AUTO:
pilot = 2;
break;
default:
dev_dbg(&client->dev, "invalid pilot\n");
ret = -EINVAL;
goto error;
}
break;
default:
dev_dbg(&client->dev, "invalid delivery_system\n");
ret = -EINVAL;
goto error;
}
for (i = 0, mode = 0xff; i < ARRAY_SIZE(TDA10071_MODCOD); i++) {
if (c->delivery_system == TDA10071_MODCOD[i].delivery_system &&
modulation == TDA10071_MODCOD[i].modulation &&
c->fec_inner == TDA10071_MODCOD[i].fec) {
mode = TDA10071_MODCOD[i].val;
dev_dbg(&client->dev, "mode found=%02x\n", mode);
break;
}
}
if (mode == 0xff) {
dev_dbg(&client->dev, "invalid parameter combination\n");
ret = -EINVAL;
goto error;
}
if (c->symbol_rate <= 5000000)
div = 14;
else
div = 4;
ret = regmap_write(dev->regmap, 0x81, div);
if (ret)
goto error;
ret = regmap_write(dev->regmap, 0xe3, div);
if (ret)
goto error;
cmd.args[0] = CMD_CHANGE_CHANNEL;
cmd.args[1] = 0;
cmd.args[2] = mode;
cmd.args[3] = (c->frequency >> 16) & 0xff;
cmd.args[4] = (c->frequency >> 8) & 0xff;
cmd.args[5] = (c->frequency >> 0) & 0xff;
cmd.args[6] = ((c->symbol_rate / 1000) >> 8) & 0xff;
cmd.args[7] = ((c->symbol_rate / 1000) >> 0) & 0xff;
cmd.args[8] = ((tda10071_ops.info.frequency_tolerance_hz / 1000) >> 8) & 0xff;
cmd.args[9] = ((tda10071_ops.info.frequency_tolerance_hz / 1000) >> 0) & 0xff;
cmd.args[10] = rolloff;
cmd.args[11] = inversion;
cmd.args[12] = pilot;
cmd.args[13] = 0x00;
cmd.args[14] = 0x00;
cmd.len = 15;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
dev->delivery_system = c->delivery_system;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret, i;
u8 buf[5], tmp;
if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
ret = 0;
goto error;
}
ret = regmap_bulk_read(dev->regmap, 0x30, buf, 5);
if (ret)
goto error;
tmp = buf[0] & 0x3f;
for (i = 0; i < ARRAY_SIZE(TDA10071_MODCOD); i++) {
if (tmp == TDA10071_MODCOD[i].val) {
c->modulation = TDA10071_MODCOD[i].modulation;
c->fec_inner = TDA10071_MODCOD[i].fec;
c->delivery_system = TDA10071_MODCOD[i].delivery_system;
}
}
switch ((buf[1] >> 0) & 0x01) {
case 0:
c->inversion = INVERSION_ON;
break;
case 1:
c->inversion = INVERSION_OFF;
break;
}
switch ((buf[1] >> 7) & 0x01) {
case 0:
c->pilot = PILOT_OFF;
break;
case 1:
c->pilot = PILOT_ON;
break;
}
c->frequency = (buf[2] << 16) | (buf[3] << 8) | (buf[4] << 0);
ret = regmap_bulk_read(dev->regmap, 0x52, buf, 3);
if (ret)
goto error;
c->symbol_rate = ((buf[0] << 16) | (buf[1] << 8) | (buf[2] << 0)) * 1000;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_init(struct dvb_frontend *fe)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct tda10071_cmd cmd;
int ret, i, len, remaining, fw_size;
unsigned int uitmp;
const struct firmware *fw;
u8 *fw_file = TDA10071_FIRMWARE;
u8 tmp, buf[4];
struct tda10071_reg_val_mask tab[] = {
{ 0xcd, 0x00, 0x07 },
{ 0x80, 0x00, 0x02 },
{ 0xcd, 0x00, 0xc0 },
{ 0xce, 0x00, 0x1b },
{ 0x9d, 0x00, 0x01 },
{ 0x9d, 0x00, 0x02 },
{ 0x9e, 0x00, 0x01 },
{ 0x87, 0x00, 0x80 },
{ 0xce, 0x00, 0x08 },
{ 0xce, 0x00, 0x10 },
};
struct tda10071_reg_val_mask tab2[] = {
{ 0xf1, 0x70, 0xff },
{ 0x88, dev->pll_multiplier, 0x3f },
{ 0x89, 0x00, 0x10 },
{ 0x89, 0x10, 0x10 },
{ 0xc0, 0x01, 0x01 },
{ 0xc0, 0x00, 0x01 },
{ 0xe0, 0xff, 0xff },
{ 0xe0, 0x00, 0xff },
{ 0x96, 0x1e, 0x7e },
{ 0x8b, 0x08, 0x08 },
{ 0x8b, 0x00, 0x08 },
{ 0x8f, 0x1a, 0x7e },
{ 0x8c, 0x68, 0xff },
{ 0x8d, 0x08, 0xff },
{ 0x8e, 0x4c, 0xff },
{ 0x8f, 0x01, 0x01 },
{ 0x8b, 0x04, 0x04 },
{ 0x8b, 0x00, 0x04 },
{ 0x87, 0x05, 0x07 },
{ 0x80, 0x00, 0x20 },
{ 0xc8, 0x01, 0xff },
{ 0xb4, 0x47, 0xff },
{ 0xb5, 0x9c, 0xff },
{ 0xb6, 0x7d, 0xff },
{ 0xba, 0x00, 0x03 },
{ 0xb7, 0x47, 0xff },
{ 0xb8, 0x9c, 0xff },
{ 0xb9, 0x7d, 0xff },
{ 0xba, 0x00, 0x0c },
{ 0xc8, 0x00, 0xff },
{ 0xcd, 0x00, 0x04 },
{ 0xcd, 0x00, 0x20 },
{ 0xe8, 0x02, 0xff },
{ 0xcf, 0x20, 0xff },
{ 0x9b, 0xd7, 0xff },
{ 0x9a, 0x01, 0x03 },
{ 0xa8, 0x05, 0x0f },
{ 0xa8, 0x65, 0xf0 },
{ 0xa6, 0xa0, 0xf0 },
{ 0x9d, 0x50, 0xfc },
{ 0x9e, 0x20, 0xe0 },
{ 0xa3, 0x1c, 0x7c },
{ 0xd5, 0x03, 0x03 },
};
if (dev->warm) {
/* warm state - wake up device from sleep */
for (i = 0; i < ARRAY_SIZE(tab); i++) {
ret = tda10071_wr_reg_mask(dev, tab[i].reg,
tab[i].val, tab[i].mask);
if (ret)
goto error;
}
cmd.args[0] = CMD_SET_SLEEP_MODE;
cmd.args[1] = 0;
cmd.args[2] = 0;
cmd.len = 3;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
} else {
/* cold state - try to download firmware */
/* request the firmware, this will block and timeout */
ret = request_firmware(&fw, fw_file, &client->dev);
if (ret) {
dev_err(&client->dev,
"did not find the firmware file '%s' (status %d). You can use <kernel_dir>/scripts/get_dvb_firmware to get the firmware\n",
fw_file, ret);
goto error;
}
/* init */
for (i = 0; i < ARRAY_SIZE(tab2); i++) {
ret = tda10071_wr_reg_mask(dev, tab2[i].reg,
tab2[i].val, tab2[i].mask);
if (ret)
goto error_release_firmware;
}
/* download firmware */
ret = regmap_write(dev->regmap, 0xe0, 0x7f);
if (ret)
goto error_release_firmware;
ret = regmap_write(dev->regmap, 0xf7, 0x81);
if (ret)
goto error_release_firmware;
ret = regmap_write(dev->regmap, 0xf8, 0x00);
if (ret)
goto error_release_firmware;
ret = regmap_write(dev->regmap, 0xf9, 0x00);
if (ret)
goto error_release_firmware;
dev_info(&client->dev,
"found a '%s' in cold state, will try to load a firmware\n",
tda10071_ops.info.name);
dev_info(&client->dev, "downloading firmware from file '%s'\n",
fw_file);
/* do not download last byte */
fw_size = fw->size - 1;
for (remaining = fw_size; remaining > 0;
remaining -= (dev->i2c_wr_max - 1)) {
len = remaining;
if (len > (dev->i2c_wr_max - 1))
len = (dev->i2c_wr_max - 1);
ret = regmap_bulk_write(dev->regmap, 0xfa,
(u8 *) &fw->data[fw_size - remaining], len);
if (ret) {
dev_err(&client->dev,
"firmware download failed=%d\n", ret);
goto error_release_firmware;
}
}
release_firmware(fw);
ret = regmap_write(dev->regmap, 0xf7, 0x0c);
if (ret)
goto error;
ret = regmap_write(dev->regmap, 0xe0, 0x00);
if (ret)
goto error;
/* wait firmware start */
msleep(250);
/* firmware status */
ret = regmap_read(dev->regmap, 0x51, &uitmp);
if (ret)
goto error;
if (uitmp) {
dev_info(&client->dev, "firmware did not run\n");
ret = -EFAULT;
goto error;
} else {
dev->warm = true;
}
cmd.args[0] = CMD_GET_FW_VERSION;
cmd.len = 1;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
ret = regmap_bulk_read(dev->regmap, cmd.len, buf, 4);
if (ret)
goto error;
dev_info(&client->dev, "firmware version %d.%d.%d.%d\n",
buf[0], buf[1], buf[2], buf[3]);
dev_info(&client->dev, "found a '%s' in warm state\n",
tda10071_ops.info.name);
ret = regmap_bulk_read(dev->regmap, 0x81, buf, 2);
if (ret)
goto error;
cmd.args[0] = CMD_DEMOD_INIT;
cmd.args[1] = ((dev->clk / 1000) >> 8) & 0xff;
cmd.args[2] = ((dev->clk / 1000) >> 0) & 0xff;
cmd.args[3] = buf[0];
cmd.args[4] = buf[1];
cmd.args[5] = dev->pll_multiplier;
cmd.args[6] = dev->spec_inv;
cmd.args[7] = 0x00;
cmd.len = 8;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
if (dev->tuner_i2c_addr)
tmp = dev->tuner_i2c_addr;
else
tmp = 0x14;
cmd.args[0] = CMD_TUNER_INIT;
cmd.args[1] = 0x00;
cmd.args[2] = 0x00;
cmd.args[3] = 0x00;
cmd.args[4] = 0x00;
cmd.args[5] = tmp;
cmd.args[6] = 0x00;
cmd.args[7] = 0x03;
cmd.args[8] = 0x02;
cmd.args[9] = 0x02;
cmd.args[10] = 0x00;
cmd.args[11] = 0x00;
cmd.args[12] = 0x00;
cmd.args[13] = 0x00;
cmd.args[14] = 0x00;
cmd.len = 15;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
cmd.args[0] = CMD_MPEG_CONFIG;
cmd.args[1] = 0;
cmd.args[2] = dev->ts_mode;
cmd.args[3] = 0x00;
cmd.args[4] = 0x04;
cmd.args[5] = 0x00;
cmd.len = 6;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
ret = regmap_update_bits(dev->regmap, 0xf0, 0x01, 0x01);
if (ret)
goto error;
cmd.args[0] = CMD_LNB_CONFIG;
cmd.args[1] = 0;
cmd.args[2] = 150;
cmd.args[3] = 3;
cmd.args[4] = 22;
cmd.args[5] = 1;
cmd.args[6] = 1;
cmd.args[7] = 30;
cmd.args[8] = 30;
cmd.args[9] = 30;
cmd.args[10] = 30;
cmd.len = 11;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
cmd.args[0] = CMD_BER_CONTROL;
cmd.args[1] = 0;
cmd.args[2] = 14;
cmd.args[3] = 14;
cmd.len = 4;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
}
/* init stats here in order signal app which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return ret;
error_release_firmware:
release_firmware(fw);
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_sleep(struct dvb_frontend *fe)
{
struct tda10071_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct tda10071_cmd cmd;
int ret, i;
struct tda10071_reg_val_mask tab[] = {
{ 0xcd, 0x07, 0x07 },
{ 0x80, 0x02, 0x02 },
{ 0xcd, 0xc0, 0xc0 },
{ 0xce, 0x1b, 0x1b },
{ 0x9d, 0x01, 0x01 },
{ 0x9d, 0x02, 0x02 },
{ 0x9e, 0x01, 0x01 },
{ 0x87, 0x80, 0x80 },
{ 0xce, 0x08, 0x08 },
{ 0xce, 0x10, 0x10 },
};
if (!dev->warm) {
ret = -EFAULT;
goto error;
}
cmd.args[0] = CMD_SET_SLEEP_MODE;
cmd.args[1] = 0;
cmd.args[2] = 1;
cmd.len = 3;
ret = tda10071_cmd_execute(dev, &cmd);
if (ret)
goto error;
for (i = 0; i < ARRAY_SIZE(tab); i++) {
ret = tda10071_wr_reg_mask(dev, tab[i].reg, tab[i].val,
tab[i].mask);
if (ret)
goto error;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tda10071_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 8000;
s->step_size = 0;
s->max_drift = 0;
return 0;
}
static const struct dvb_frontend_ops tda10071_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "NXP TDA10071",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_8_9 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_RECOVER |
FE_CAN_2G_MODULATION
},
.get_tune_settings = tda10071_get_tune_settings,
.init = tda10071_init,
.sleep = tda10071_sleep,
.set_frontend = tda10071_set_frontend,
.get_frontend = tda10071_get_frontend,
.read_status = tda10071_read_status,
.read_snr = tda10071_read_snr,
.read_signal_strength = tda10071_read_signal_strength,
.read_ber = tda10071_read_ber,
.read_ucblocks = tda10071_read_ucblocks,
.diseqc_send_master_cmd = tda10071_diseqc_send_master_cmd,
.diseqc_recv_slave_reply = tda10071_diseqc_recv_slave_reply,
.diseqc_send_burst = tda10071_diseqc_send_burst,
.set_tone = tda10071_set_tone,
.set_voltage = tda10071_set_voltage,
};
static struct dvb_frontend *tda10071_get_dvb_frontend(struct i2c_client *client)
{
struct tda10071_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &dev->fe;
}
static int tda10071_probe(struct i2c_client *client)
{
struct tda10071_dev *dev;
struct tda10071_platform_data *pdata = client->dev.platform_data;
int ret;
unsigned int uitmp;
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
dev->client = client;
mutex_init(&dev->cmd_execute_mutex);
dev->clk = pdata->clk;
dev->i2c_wr_max = pdata->i2c_wr_max;
dev->ts_mode = pdata->ts_mode;
dev->spec_inv = pdata->spec_inv;
dev->pll_multiplier = pdata->pll_multiplier;
dev->tuner_i2c_addr = pdata->tuner_i2c_addr;
dev->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
/* chip ID */
ret = regmap_read(dev->regmap, 0xff, &uitmp);
if (ret)
goto err_kfree;
if (uitmp != 0x0f) {
ret = -ENODEV;
goto err_kfree;
}
/* chip type */
ret = regmap_read(dev->regmap, 0xdd, &uitmp);
if (ret)
goto err_kfree;
if (uitmp != 0x00) {
ret = -ENODEV;
goto err_kfree;
}
/* chip version */
ret = regmap_read(dev->regmap, 0xfe, &uitmp);
if (ret)
goto err_kfree;
if (uitmp != 0x01) {
ret = -ENODEV;
goto err_kfree;
}
/* create dvb_frontend */
memcpy(&dev->fe.ops, &tda10071_ops, sizeof(struct dvb_frontend_ops));
dev->fe.demodulator_priv = dev;
i2c_set_clientdata(client, dev);
/* setup callbacks */
pdata->get_dvb_frontend = tda10071_get_dvb_frontend;
dev_info(&client->dev, "NXP TDA10071 successfully identified\n");
return 0;
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void tda10071_remove(struct i2c_client *client)
{
struct tda10071_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
kfree(dev);
}
static const struct i2c_device_id tda10071_id_table[] = {
{"tda10071_cx24118", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tda10071_id_table);
static struct i2c_driver tda10071_driver = {
.driver = {
.name = "tda10071",
.suppress_bind_attrs = true,
},
.probe = tda10071_probe,
.remove = tda10071_remove,
.id_table = tda10071_id_table,
};
module_i2c_driver(tda10071_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("NXP TDA10071 DVB-S/S2 demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(TDA10071_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/tda10071.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
*
* Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <asm/div64.h>
#include <linux/int_log.h>
#include <media/dvb_frontend.h>
#include "dib7000p.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
static int buggy_sfn_workaround;
module_param(buggy_sfn_workaround, int, 0644);
MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
#define dprintk(fmt, arg...) do { \
if (debug) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
struct i2c_device {
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
};
struct dib7000p_state {
struct dvb_frontend demod;
struct dib7000p_config cfg;
u8 i2c_addr;
struct i2c_adapter *i2c_adap;
struct dibx000_i2c_master i2c_master;
u16 wbd_ref;
u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;
u8 div_force_off:1;
u8 div_state:1;
u16 div_sync_wait;
u8 agc_state;
u16 gpio_dir;
u16 gpio_val;
u8 sfn_workaround_active:1;
#define SOC7090 0x7090
u16 version;
u16 tuner_enable;
struct i2c_adapter dib7090_tuner_adap;
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[4];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
u8 input_mode_mpeg;
/* for DVBv5 stats */
s64 old_ucb;
unsigned long per_jiffies_stats;
unsigned long ber_jiffies_stats;
unsigned long get_stats_time;
};
enum dib7000p_power_mode {
DIB7000P_POWER_ALL = 0,
DIB7000P_POWER_ANALOG_ADC,
DIB7000P_POWER_INTERFACE_ONLY,
};
/* dib7090 specific functions */
static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return 0;
}
state->i2c_write_buffer[0] = reg >> 8;
state->i2c_write_buffer[1] = reg & 0xff;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 2;
state->msg[1].addr = state->i2c_addr >> 1;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
dprintk("i2c read error on %d\n", reg);
ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock\n");
return -EINVAL;
}
state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
state->i2c_write_buffer[1] = reg & 0xff;
state->i2c_write_buffer[2] = (val >> 8) & 0xff;
state->i2c_write_buffer[3] = val & 0xff;
memset(&state->msg[0], 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c_addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 4;
ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
-EREMOTEIO : 0);
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
{
u16 l = 0, r, *n;
n = buf;
l = *n++;
while (l) {
r = *n++;
do {
dib7000p_write_word(state, r, *n++);
r++;
} while (--l);
l = *n++;
}
}
static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
{
int ret = 0;
u16 outreg, fifo_threshold, smo_mode;
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK:
outreg = (1 << 10); /* 0x0400 */
break;
case OUTMODE_MPEG2_PAR_CONT_CLK:
outreg = (1 << 10) | (1 << 6); /* 0x0440 */
break;
case OUTMODE_MPEG2_SERIAL:
outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
break;
case OUTMODE_DIVERSITY:
if (state->cfg.hostbus_diversity)
outreg = (1 << 10) | (4 << 6); /* 0x0500 */
else
outreg = (1 << 11);
break;
case OUTMODE_MPEG2_FIFO:
smo_mode |= (3 << 1);
fifo_threshold = 512;
outreg = (1 << 10) | (5 << 6);
break;
case OUTMODE_ANALOG_ADC:
outreg = (1 << 10) | (3 << 6);
break;
case OUTMODE_HIGH_Z:
outreg = 0;
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
break;
}
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
ret |= dib7000p_write_word(state, 235, smo_mode);
ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
if (state->version != SOC7090)
ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
return ret;
}
static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
{
struct dib7000p_state *state = demod->demodulator_priv;
if (state->div_force_off) {
dprintk("diversity combination deactivated - forced by COFDM parameters\n");
onoff = 0;
dib7000p_write_word(state, 207, 0);
} else
dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
state->div_state = (u8) onoff;
if (onoff) {
dib7000p_write_word(state, 204, 6);
dib7000p_write_word(state, 205, 16);
/* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
} else {
dib7000p_write_word(state, 204, 1);
dib7000p_write_word(state, 205, 0);
}
return 0;
}
static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
{
/* by default everything is powered off */
u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
case DIB7000P_POWER_ALL:
reg_774 = 0x0000;
reg_775 = 0x0000;
reg_776 = 0x0;
reg_899 = 0x0;
if (state->version == SOC7090)
reg_1280 &= 0x001f;
else
reg_1280 &= 0x01ff;
break;
case DIB7000P_POWER_ANALOG_ADC:
/* dem, cfg, iqc, sad, agc */
reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
/* nud */
reg_776 &= ~((1 << 0));
/* Dout */
if (state->version != SOC7090)
reg_1280 &= ~((1 << 11));
reg_1280 &= ~(1 << 6);
fallthrough;
case DIB7000P_POWER_INTERFACE_ONLY:
/* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
/* TODO power up either SDIO or I2C */
if (state->version == SOC7090)
reg_1280 &= ~((1 << 7) | (1 << 5));
else
reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
break;
/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
}
dib7000p_write_word(state, 774, reg_774);
dib7000p_write_word(state, 775, reg_775);
dib7000p_write_word(state, 776, reg_776);
dib7000p_write_word(state, 1280, reg_1280);
if (state->version != SOC7090)
dib7000p_write_word(state, 899, reg_899);
return 0;
}
static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
{
u16 reg_908 = 0, reg_909 = 0;
u16 reg;
if (state->version != SOC7090) {
reg_908 = dib7000p_read_word(state, 908);
reg_909 = dib7000p_read_word(state, 909);
}
switch (no) {
case DIBX000_SLOW_ADC_ON:
if (state->version == SOC7090) {
reg = dib7000p_read_word(state, 1925);
dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
reg = dib7000p_read_word(state, 1925); /* read access to make it works... strange ... */
msleep(200);
dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
} else {
reg_909 |= (1 << 1) | (1 << 0);
dib7000p_write_word(state, 909, reg_909);
reg_909 &= ~(1 << 1);
}
break;
case DIBX000_SLOW_ADC_OFF:
if (state->version == SOC7090) {
reg = dib7000p_read_word(state, 1925);
dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
} else
reg_909 |= (1 << 1) | (1 << 0);
break;
case DIBX000_ADC_ON:
reg_908 &= 0x0fff;
reg_909 &= 0x0003;
break;
case DIBX000_ADC_OFF:
reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
break;
case DIBX000_VBG_ENABLE:
reg_908 &= ~(1 << 15);
break;
case DIBX000_VBG_DISABLE:
reg_908 |= (1 << 15);
break;
default:
break;
}
// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
if (state->version != SOC7090) {
dib7000p_write_word(state, 908, reg_908);
dib7000p_write_word(state, 909, reg_909);
}
}
static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
{
u32 timf;
// store the current bandwidth for later use
state->current_bandwidth = bw;
if (state->timf == 0) {
dprintk("using default timf\n");
timf = state->cfg.bw->timf;
} else {
dprintk("using updated timf\n");
timf = state->timf;
}
timf = timf * (bw / 50) / 160;
dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
return 0;
}
static int dib7000p_sad_calib(struct dib7000p_state *state)
{
/* internal */
dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
if (state->version == SOC7090)
dib7000p_write_word(state, 74, 2048);
else
dib7000p_write_word(state, 74, 776);
/* do the calibration */
dib7000p_write_word(state, 73, (1 << 0));
dib7000p_write_word(state, 73, (0 << 0));
msleep(1);
return 0;
}
static int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
{
struct dib7000p_state *state = demod->demodulator_priv;
if (value > 4095)
value = 4095;
state->wbd_ref = value;
return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
}
static int dib7000p_get_agc_values(struct dvb_frontend *fe,
u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
{
struct dib7000p_state *state = fe->demodulator_priv;
if (agc_global != NULL)
*agc_global = dib7000p_read_word(state, 394);
if (agc1 != NULL)
*agc1 = dib7000p_read_word(state, 392);
if (agc2 != NULL)
*agc2 = dib7000p_read_word(state, 393);
if (wbd != NULL)
*wbd = dib7000p_read_word(state, 397);
return 0;
}
static int dib7000p_set_agc1_min(struct dvb_frontend *fe, u16 v)
{
struct dib7000p_state *state = fe->demodulator_priv;
return dib7000p_write_word(state, 108, v);
}
static void dib7000p_reset_pll(struct dib7000p_state *state)
{
struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
u16 clk_cfg0;
if (state->version == SOC7090) {
dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
;
dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
} else {
/* force PLL bypass */
clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
dib7000p_write_word(state, 900, clk_cfg0);
/* P_pll_cfg */
dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
dib7000p_write_word(state, 900, clk_cfg0);
}
dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
dib7000p_write_word(state, 72, bw->sad_cfg);
}
static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
{
u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
internal |= (u32) dib7000p_read_word(state, 19);
internal /= 1000;
return internal;
}
static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
u8 loopdiv, prediv;
u32 internal, xtal;
/* get back old values */
prediv = reg_1856 & 0x3f;
loopdiv = (reg_1856 >> 6) & 0x3f;
if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
reg_1856 &= 0xf000;
reg_1857 = dib7000p_read_word(state, 1857);
dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
/* write new system clk into P_sec_len */
internal = dib7000p_get_internal_freq(state);
xtal = (internal / loopdiv) * prediv;
internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
dprintk("Waiting for PLL to lock\n");
return 0;
}
return -EIO;
}
static int dib7000p_reset_gpio(struct dib7000p_state *st)
{
/* reset the GPIOs */
dprintk("gpio dir: %x: val: %x, pwm_pos: %x\n", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
dib7000p_write_word(st, 1029, st->gpio_dir);
dib7000p_write_word(st, 1030, st->gpio_val);
/* TODO 1031 is P_gpio_od */
dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
return 0;
}
static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
{
st->gpio_dir = dib7000p_read_word(st, 1029);
st->gpio_dir &= ~(1 << num); /* reset the direction bit */
st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
dib7000p_write_word(st, 1029, st->gpio_dir);
st->gpio_val = dib7000p_read_word(st, 1030);
st->gpio_val &= ~(1 << num); /* reset the direction bit */
st->gpio_val |= (val & 0x01) << num; /* set the new value */
dib7000p_write_word(st, 1030, st->gpio_val);
return 0;
}
static int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
{
struct dib7000p_state *state = demod->demodulator_priv;
return dib7000p_cfg_gpio(state, num, dir, val);
}
static u16 dib7000p_defaults[] = {
// auto search configuration
3, 2,
0x0004,
(1<<3)|(1<<11)|(1<<12)|(1<<13),
0x0814, /* Equal Lock */
12, 6,
0x001b,
0x7740,
0x005b,
0x8d80,
0x01c9,
0xc380,
0x0000,
0x0080,
0x0000,
0x0090,
0x0001,
0xd4c0,
1, 26,
0x6680,
/* set ADC level to -16 */
11, 79,
(1 << 13) - 825 - 117,
(1 << 13) - 837 - 117,
(1 << 13) - 811 - 117,
(1 << 13) - 766 - 117,
(1 << 13) - 737 - 117,
(1 << 13) - 693 - 117,
(1 << 13) - 648 - 117,
(1 << 13) - 619 - 117,
(1 << 13) - 575 - 117,
(1 << 13) - 531 - 117,
(1 << 13) - 501 - 117,
1, 142,
0x0410,
/* disable power smoothing */
8, 145,
0,
0,
0,
0,
0,
0,
0,
0,
1, 154,
1 << 13,
1, 168,
0x0ccd,
1, 183,
0x200f,
1, 212,
0x169,
5, 187,
0x023d,
0x00a4,
0x00a4,
0x7ff0,
0x3ccc,
1, 198,
0x800,
1, 222,
0x0010,
1, 235,
0x0062,
0,
};
static void dib7000p_reset_stats(struct dvb_frontend *fe);
static int dib7000p_demod_reset(struct dib7000p_state *state)
{
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
if (state->version == SOC7090)
dibx000_reset_i2c_master(&state->i2c_master);
dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
/* restart all parts */
dib7000p_write_word(state, 770, 0xffff);
dib7000p_write_word(state, 771, 0xffff);
dib7000p_write_word(state, 772, 0x001f);
dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
dib7000p_write_word(state, 770, 0);
dib7000p_write_word(state, 771, 0);
dib7000p_write_word(state, 772, 0);
dib7000p_write_word(state, 1280, 0);
if (state->version != SOC7090) {
dib7000p_write_word(state, 898, 0x0003);
dib7000p_write_word(state, 898, 0);
}
/* default */
dib7000p_reset_pll(state);
if (dib7000p_reset_gpio(state) != 0)
dprintk("GPIO reset was not successful.\n");
if (state->version == SOC7090) {
dib7000p_write_word(state, 899, 0);
/* impulse noise */
dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
dib7000p_write_word(state, 273, (0<<6) | 30);
}
if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
dprintk("OUTPUT_MODE could not be reset.\n");
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
dib7000p_sad_calib(state);
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
/* unforce divstr regardless whether i2c enumeration was done or not */
dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
dib7000p_set_bandwidth(state, 8000);
if (state->version == SOC7090) {
dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
} else {
if (state->cfg.tuner_is_baseband)
dib7000p_write_word(state, 36, 0x0755);
else
dib7000p_write_word(state, 36, 0x1f55);
}
dib7000p_write_tab(state, dib7000p_defaults);
if (state->version != SOC7090) {
dib7000p_write_word(state, 901, 0x0006);
dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
dib7000p_write_word(state, 905, 0x2c8e);
}
dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
return 0;
}
static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
{
u16 tmp = 0;
tmp = dib7000p_read_word(state, 903);
dib7000p_write_word(state, 903, (tmp | 0x1));
tmp = dib7000p_read_word(state, 900);
dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
}
static void dib7000p_restart_agc(struct dib7000p_state *state)
{
// P_restart_iqc & P_restart_agc
dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
dib7000p_write_word(state, 770, 0x0000);
}
static int dib7000p_update_lna(struct dib7000p_state *state)
{
u16 dyn_gain;
if (state->cfg.update_lna) {
dyn_gain = dib7000p_read_word(state, 394);
if (state->cfg.update_lna(&state->demod, dyn_gain)) {
dib7000p_restart_agc(state);
return 1;
}
}
return 0;
}
static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
{
struct dibx000_agc_config *agc = NULL;
int i;
if (state->current_band == band && state->current_agc != NULL)
return 0;
state->current_band = band;
for (i = 0; i < state->cfg.agc_config_count; i++)
if (state->cfg.agc[i].band_caps & band) {
agc = &state->cfg.agc[i];
break;
}
if (agc == NULL) {
dprintk("no valid AGC configuration found for band 0x%02x\n", band);
return -EINVAL;
}
state->current_agc = agc;
/* AGC */
dib7000p_write_word(state, 75, agc->setup);
dib7000p_write_word(state, 76, agc->inv_gain);
dib7000p_write_word(state, 77, agc->time_stabiliz);
dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
// Demod AGC loop configuration
dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
/* AGC continued */
dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
if (state->wbd_ref != 0)
dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
else
dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
dib7000p_write_word(state, 107, agc->agc1_max);
dib7000p_write_word(state, 108, agc->agc1_min);
dib7000p_write_word(state, 109, agc->agc2_max);
dib7000p_write_word(state, 110, agc->agc2_min);
dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
dib7000p_write_word(state, 112, agc->agc1_pt3);
dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
return 0;
}
static int dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
{
u32 internal = dib7000p_get_internal_freq(state);
s32 unit_khz_dds_val;
u32 abs_offset_khz = abs(offset_khz);
u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
if (internal == 0) {
pr_warn("DIB7000P: dib7000p_get_internal_freq returned 0\n");
return -1;
}
/* 2**26 / Fsampling is the unit 1KHz offset */
unit_khz_dds_val = 67108864 / (internal);
dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d\n", offset_khz, internal, invert);
if (offset_khz < 0)
unit_khz_dds_val *= -1;
/* IF tuner */
if (invert)
dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
else
dds += (abs_offset_khz * unit_khz_dds_val);
if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
}
return 0;
}
static int dib7000p_agc_startup(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000p_state *state = demod->demodulator_priv;
int ret = -1;
u8 *agc_state = &state->agc_state;
u8 agc_split;
u16 reg;
u32 upd_demod_gain_period = 0x1000;
s32 frequency_offset = 0;
switch (state->agc_state) {
case 0:
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
if (state->version == SOC7090) {
reg = dib7000p_read_word(state, 0x79b) & 0xff00;
dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
/* enable adc i & q */
reg = dib7000p_read_word(state, 0x780);
dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
} else {
dib7000p_set_adc_state(state, DIBX000_ADC_ON);
dib7000p_pll_clk_cfg(state);
}
if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
return -1;
if (demod->ops.tuner_ops.get_frequency) {
u32 frequency_tuner;
demod->ops.tuner_ops.get_frequency(demod, &frequency_tuner);
frequency_offset = (s32)frequency_tuner / 1000 - ch->frequency / 1000;
}
if (dib7000p_set_dds(state, frequency_offset) < 0)
return -1;
ret = 7;
(*agc_state)++;
break;
case 1:
if (state->cfg.agc_control)
state->cfg.agc_control(&state->demod, 1);
dib7000p_write_word(state, 78, 32768);
if (!state->current_agc->perform_agc_softsplit) {
/* we are using the wbd - so slow AGC startup */
/* force 0 split on WBD and restart AGC */
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
(*agc_state)++;
ret = 5;
} else {
/* default AGC startup */
(*agc_state) = 4;
/* wait AGC rough lock time */
ret = 7;
}
dib7000p_restart_agc(state);
break;
case 2: /* fast split search path after 5sec */
dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
(*agc_state)++;
ret = 14;
break;
case 3: /* split search ended */
agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
dib7000p_restart_agc(state);
dprintk("SPLIT %p: %u\n", demod, agc_split);
(*agc_state)++;
ret = 5;
break;
case 4: /* LNA startup */
ret = 7;
if (dib7000p_update_lna(state))
ret = 5;
else
(*agc_state)++;
break;
case 5:
if (state->cfg.agc_control)
state->cfg.agc_control(&state->demod, 0);
(*agc_state)++;
break;
default:
break;
}
return ret;
}
static void dib7000p_update_timf(struct dib7000p_state *state)
{
u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
state->timf = timf * 160 / (state->current_bandwidth / 50);
dib7000p_write_word(state, 23, (u16) (timf >> 16));
dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->cfg.bw->timf);
}
static u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
{
struct dib7000p_state *state = fe->demodulator_priv;
switch (op) {
case DEMOD_TIMF_SET:
state->timf = timf;
break;
case DEMOD_TIMF_UPDATE:
dib7000p_update_timf(state);
break;
case DEMOD_TIMF_GET:
break;
}
dib7000p_set_bandwidth(state, state->current_bandwidth);
return state->timf;
}
static void dib7000p_set_channel(struct dib7000p_state *state,
struct dtv_frontend_properties *ch, u8 seq)
{
u16 value, est[4];
dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
/* nfft, guard, qam, alpha */
value = 0;
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K:
value |= (0 << 7);
break;
case TRANSMISSION_MODE_4K:
value |= (2 << 7);
break;
default:
case TRANSMISSION_MODE_8K:
value |= (1 << 7);
break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_32:
value |= (0 << 5);
break;
case GUARD_INTERVAL_1_16:
value |= (1 << 5);
break;
case GUARD_INTERVAL_1_4:
value |= (3 << 5);
break;
default:
case GUARD_INTERVAL_1_8:
value |= (2 << 5);
break;
}
switch (ch->modulation) {
case QPSK:
value |= (0 << 3);
break;
case QAM_16:
value |= (1 << 3);
break;
default:
case QAM_64:
value |= (2 << 3);
break;
}
switch (HIERARCHY_1) {
case HIERARCHY_2:
value |= 2;
break;
case HIERARCHY_4:
value |= 4;
break;
default:
case HIERARCHY_1:
value |= 1;
break;
}
dib7000p_write_word(state, 0, value);
dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
/* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
value = 0;
if (1 != 0)
value |= (1 << 6);
if (ch->hierarchy == 1)
value |= (1 << 4);
if (1 == 1)
value |= 1;
switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
case FEC_2_3:
value |= (2 << 1);
break;
case FEC_3_4:
value |= (3 << 1);
break;
case FEC_5_6:
value |= (5 << 1);
break;
case FEC_7_8:
value |= (7 << 1);
break;
default:
case FEC_1_2:
value |= (1 << 1);
break;
}
dib7000p_write_word(state, 208, value);
/* offset loop parameters */
dib7000p_write_word(state, 26, 0x6680);
dib7000p_write_word(state, 32, 0x0003);
dib7000p_write_word(state, 29, 0x1273);
dib7000p_write_word(state, 33, 0x0005);
/* P_dvsy_sync_wait */
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_8K:
value = 256;
break;
case TRANSMISSION_MODE_4K:
value = 128;
break;
case TRANSMISSION_MODE_2K:
default:
value = 64;
break;
}
switch (ch->guard_interval) {
case GUARD_INTERVAL_1_16:
value *= 2;
break;
case GUARD_INTERVAL_1_8:
value *= 4;
break;
case GUARD_INTERVAL_1_4:
value *= 8;
break;
default:
case GUARD_INTERVAL_1_32:
value *= 1;
break;
}
if (state->cfg.diversity_delay == 0)
state->div_sync_wait = (value * 3) / 2 + 48;
else
state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
/* deactivate the possibility of diversity reception if extended interleaver */
state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
dib7000p_set_diversity_in(&state->demod, state->div_state);
/* channel estimation fine configuration */
switch (ch->modulation) {
case QAM_64:
est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
break;
case QAM_16:
est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
break;
default:
est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
break;
}
for (value = 0; value < 4; value++)
dib7000p_write_word(state, 187 + value, est[value]);
}
static int dib7000p_autosearch_start(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000p_state *state = demod->demodulator_priv;
struct dtv_frontend_properties schan;
u32 value, factor;
u32 internal = dib7000p_get_internal_freq(state);
schan = *ch;
schan.modulation = QAM_64;
schan.guard_interval = GUARD_INTERVAL_1_32;
schan.transmission_mode = TRANSMISSION_MODE_8K;
schan.code_rate_HP = FEC_2_3;
schan.code_rate_LP = FEC_3_4;
schan.hierarchy = 0;
dib7000p_set_channel(state, &schan, 7);
factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
if (factor >= 5000) {
if (state->version == SOC7090)
factor = 2;
else
factor = 1;
} else
factor = 6;
value = 30 * internal * factor;
dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
dib7000p_write_word(state, 7, (u16) (value & 0xffff));
value = 100 * internal * factor;
dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
dib7000p_write_word(state, 9, (u16) (value & 0xffff));
value = 500 * internal * factor;
dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
dib7000p_write_word(state, 11, (u16) (value & 0xffff));
value = dib7000p_read_word(state, 0);
dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
dib7000p_read_word(state, 1284);
dib7000p_write_word(state, 0, (u16) value);
return 0;
}
static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
{
struct dib7000p_state *state = demod->demodulator_priv;
u16 irq_pending = dib7000p_read_word(state, 1284);
if (irq_pending & 0x1)
return 1;
if (irq_pending & 0x2)
return 2;
return 0;
}
static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
{
static const s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
static const u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255
};
u32 xtal = state->cfg.bw->xtal_hz / 1000;
int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
int k;
int coef_re[8], coef_im[8];
int bw_khz = bw;
u32 pha;
dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)\n", f_rel, rf_khz, xtal);
if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
return;
bw_khz /= 100;
dib7000p_write_word(state, 142, 0x0610);
for (k = 0; k < 8; k++) {
pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
if (pha == 0) {
coef_re[k] = 256;
coef_im[k] = 0;
} else if (pha < 256) {
coef_re[k] = sine[256 - (pha & 0xff)];
coef_im[k] = sine[pha & 0xff];
} else if (pha == 256) {
coef_re[k] = 0;
coef_im[k] = 256;
} else if (pha < 512) {
coef_re[k] = -sine[pha & 0xff];
coef_im[k] = sine[256 - (pha & 0xff)];
} else if (pha == 512) {
coef_re[k] = -256;
coef_im[k] = 0;
} else if (pha < 768) {
coef_re[k] = -sine[256 - (pha & 0xff)];
coef_im[k] = -sine[pha & 0xff];
} else if (pha == 768) {
coef_re[k] = 0;
coef_im[k] = -256;
} else {
coef_re[k] = sine[pha & 0xff];
coef_im[k] = -sine[256 - (pha & 0xff)];
}
coef_re[k] *= notch[k];
coef_re[k] += (1 << 14);
if (coef_re[k] >= (1 << 24))
coef_re[k] = (1 << 24) - 1;
coef_re[k] /= (1 << 15);
coef_im[k] *= notch[k];
coef_im[k] += (1 << 14);
if (coef_im[k] >= (1 << 24))
coef_im[k] = (1 << 24) - 1;
coef_im[k] /= (1 << 15);
dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]);
dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
}
dib7000p_write_word(state, 143, 0);
}
static int dib7000p_tune(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
struct dib7000p_state *state = demod->demodulator_priv;
u16 tmp = 0;
if (ch != NULL)
dib7000p_set_channel(state, ch, 0);
else
return -EINVAL;
// restart demod
dib7000p_write_word(state, 770, 0x4000);
dib7000p_write_word(state, 770, 0x0000);
msleep(45);
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
if (state->sfn_workaround_active) {
dprintk("SFN workaround is active\n");
tmp |= (1 << 9);
dib7000p_write_word(state, 166, 0x4000);
} else {
dib7000p_write_word(state, 166, 0x0000);
}
dib7000p_write_word(state, 29, tmp);
// never achieved a lock with that bandwidth so far - wait for osc-freq to update
if (state->timf == 0)
msleep(200);
/* offset loop parameters */
/* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
tmp = (6 << 8) | 0x80;
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K:
tmp |= (2 << 12);
break;
case TRANSMISSION_MODE_4K:
tmp |= (3 << 12);
break;
default:
case TRANSMISSION_MODE_8K:
tmp |= (4 << 12);
break;
}
dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
/* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
tmp = (0 << 4);
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K:
tmp |= 0x6;
break;
case TRANSMISSION_MODE_4K:
tmp |= 0x7;
break;
default:
case TRANSMISSION_MODE_8K:
tmp |= 0x8;
break;
}
dib7000p_write_word(state, 32, tmp);
/* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
tmp = (0 << 4);
switch (ch->transmission_mode) {
case TRANSMISSION_MODE_2K:
tmp |= 0x6;
break;
case TRANSMISSION_MODE_4K:
tmp |= 0x7;
break;
default:
case TRANSMISSION_MODE_8K:
tmp |= 0x8;
break;
}
dib7000p_write_word(state, 33, tmp);
tmp = dib7000p_read_word(state, 509);
if (!((tmp >> 6) & 0x1)) {
/* restart the fec */
tmp = dib7000p_read_word(state, 771);
dib7000p_write_word(state, 771, tmp | (1 << 1));
dib7000p_write_word(state, 771, tmp);
msleep(40);
tmp = dib7000p_read_word(state, 509);
}
// we achieved a lock - it's time to update the osc freq
if ((tmp >> 6) & 0x1) {
dib7000p_update_timf(state);
/* P_timf_alpha += 2 */
tmp = dib7000p_read_word(state, 26);
dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
}
if (state->cfg.spur_protect)
dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
dib7000p_reset_stats(demod);
return 0;
}
static int dib7000p_wakeup(struct dvb_frontend *demod)
{
struct dib7000p_state *state = demod->demodulator_priv;
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
if (state->version == SOC7090)
dib7000p_sad_calib(state);
return 0;
}
static int dib7000p_sleep(struct dvb_frontend *demod)
{
struct dib7000p_state *state = demod->demodulator_priv;
if (state->version == SOC7090)
return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
}
static int dib7000p_identify(struct dib7000p_state *st)
{
u16 value;
dprintk("checking demod on I2C address: %d (%x)\n", st->i2c_addr, st->i2c_addr);
if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
dprintk("wrong Vendor ID (read=0x%x)\n", value);
return -EREMOTEIO;
}
if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
dprintk("wrong Device ID (%x)\n", value);
return -EREMOTEIO;
}
return 0;
}
static int dib7000p_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *fep)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 tps = dib7000p_read_word(state, 463);
fep->inversion = INVERSION_AUTO;
fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
switch ((tps >> 8) & 0x3) {
case 0:
fep->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
fep->transmission_mode = TRANSMISSION_MODE_8K;
break;
/* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
}
switch (tps & 0x3) {
case 0:
fep->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
fep->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
fep->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
fep->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((tps >> 14) & 0x3) {
case 0:
fep->modulation = QPSK;
break;
case 1:
fep->modulation = QAM_16;
break;
case 2:
default:
fep->modulation = QAM_64;
break;
}
/* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
/* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
fep->hierarchy = HIERARCHY_NONE;
switch ((tps >> 5) & 0x7) {
case 1:
fep->code_rate_HP = FEC_1_2;
break;
case 2:
fep->code_rate_HP = FEC_2_3;
break;
case 3:
fep->code_rate_HP = FEC_3_4;
break;
case 5:
fep->code_rate_HP = FEC_5_6;
break;
case 7:
default:
fep->code_rate_HP = FEC_7_8;
break;
}
switch ((tps >> 2) & 0x7) {
case 1:
fep->code_rate_LP = FEC_1_2;
break;
case 2:
fep->code_rate_LP = FEC_2_3;
break;
case 3:
fep->code_rate_LP = FEC_3_4;
break;
case 5:
fep->code_rate_LP = FEC_5_6;
break;
case 7:
default:
fep->code_rate_LP = FEC_7_8;
break;
}
/* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
return 0;
}
static int dib7000p_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
struct dib7000p_state *state = fe->demodulator_priv;
int time, ret;
if (state->version == SOC7090)
dib7090_set_diversity_in(fe, 0);
else
dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
/* maybe the parameter has been changed */
state->sfn_workaround_active = buggy_sfn_workaround;
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* start up the AGC */
state->agc_state = 0;
do {
time = dib7000p_agc_startup(fe);
if (time != -1)
msleep(time);
} while (time != -1);
if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
int i = 800, found;
dib7000p_autosearch_start(fe);
do {
msleep(1);
found = dib7000p_autosearch_is_irq(fe);
} while (found == 0 && i--);
dprintk("autosearch returns: %d\n", found);
if (found == 0 || found == 1)
return 0;
dib7000p_get_frontend(fe, fep);
}
ret = dib7000p_tune(fe);
/* make this a config parameter */
if (state->version == SOC7090) {
dib7090_set_output_mode(fe, state->cfg.output_mode);
if (state->cfg.enMpegOutput == 0) {
dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
}
} else
dib7000p_set_output_mode(state, state->cfg.output_mode);
return ret;
}
static int dib7000p_get_stats(struct dvb_frontend *fe, enum fe_status stat);
static int dib7000p_read_status(struct dvb_frontend *fe, enum fe_status *stat)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 lock = dib7000p_read_word(state, 509);
*stat = 0;
if (lock & 0x8000)
*stat |= FE_HAS_SIGNAL;
if (lock & 0x3000)
*stat |= FE_HAS_CARRIER;
if (lock & 0x0100)
*stat |= FE_HAS_VITERBI;
if (lock & 0x0010)
*stat |= FE_HAS_SYNC;
if ((lock & 0x0038) == 0x38)
*stat |= FE_HAS_LOCK;
dib7000p_get_stats(fe, *stat);
return 0;
}
static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib7000p_state *state = fe->demodulator_priv;
*ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
return 0;
}
static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib7000p_state *state = fe->demodulator_priv;
*unc = dib7000p_read_word(state, 506);
return 0;
}
static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 val = dib7000p_read_word(state, 394);
*strength = 65535 - val;
return 0;
}
static u32 dib7000p_get_snr(struct dvb_frontend *fe)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 val;
s32 signal_mant, signal_exp, noise_mant, noise_exp;
u32 result = 0;
val = dib7000p_read_word(state, 479);
noise_mant = (val >> 4) & 0xff;
noise_exp = ((val & 0xf) << 2);
val = dib7000p_read_word(state, 480);
noise_exp += ((val >> 14) & 0x3);
if ((noise_exp & 0x20) != 0)
noise_exp -= 0x40;
signal_mant = (val >> 6) & 0xFF;
signal_exp = (val & 0x3F);
if ((signal_exp & 0x20) != 0)
signal_exp -= 0x40;
if (signal_mant != 0)
result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
else
result = intlog10(2) * 10 * signal_exp - 100;
if (noise_mant != 0)
result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
else
result -= intlog10(2) * 10 * noise_exp - 100;
return result;
}
static int dib7000p_read_snr(struct dvb_frontend *fe, u16 *snr)
{
u32 result;
result = dib7000p_get_snr(fe);
*snr = result / ((1 << 24) / 10);
return 0;
}
static void dib7000p_reset_stats(struct dvb_frontend *demod)
{
struct dib7000p_state *state = demod->demodulator_priv;
struct dtv_frontend_properties *c = &demod->dtv_property_cache;
u32 ucb;
memset(&c->strength, 0, sizeof(c->strength));
memset(&c->cnr, 0, sizeof(c->cnr));
memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
memset(&c->block_error, 0, sizeof(c->block_error));
c->strength.len = 1;
c->cnr.len = 1;
c->block_error.len = 1;
c->block_count.len = 1;
c->post_bit_error.len = 1;
c->post_bit_count.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].uvalue = 0;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dib7000p_read_unc_blocks(demod, &ucb);
state->old_ucb = ucb;
state->ber_jiffies_stats = 0;
state->per_jiffies_stats = 0;
}
struct linear_segments {
unsigned x;
signed y;
};
/*
* Table to estimate signal strength in dBm.
* This table should be empirically determinated by measuring the signal
* strength generated by a RF generator directly connected into
* a device.
* This table was determinated by measuring the signal strength generated
* by a DTA-2111 RF generator directly connected into a dib7000p device
* (a Hauppauge Nova-TD stick), using a good quality 3 meters length
* RC6 cable and good RC6 connectors, connected directly to antenna 1.
* As the minimum output power of DTA-2111 is -31dBm, a 16 dBm attenuator
* were used, for the lower power values.
* The real value can actually be on other devices, or even at the
* second antena input, depending on several factors, like if LNA
* is enabled or not, if diversity is enabled, type of connectors, etc.
* Yet, it is better to use this measure in dB than a random non-linear
* percentage value, especially for antenna adjustments.
* On my tests, the precision of the measure using this table is about
* 0.5 dB, with sounds reasonable enough to adjust antennas.
*/
#define DB_OFFSET 131000
static struct linear_segments strength_to_db_table[] = {
{ 63630, DB_OFFSET - 20500},
{ 62273, DB_OFFSET - 21000},
{ 60162, DB_OFFSET - 22000},
{ 58730, DB_OFFSET - 23000},
{ 58294, DB_OFFSET - 24000},
{ 57778, DB_OFFSET - 25000},
{ 57320, DB_OFFSET - 26000},
{ 56779, DB_OFFSET - 27000},
{ 56293, DB_OFFSET - 28000},
{ 55724, DB_OFFSET - 29000},
{ 55145, DB_OFFSET - 30000},
{ 54680, DB_OFFSET - 31000},
{ 54293, DB_OFFSET - 32000},
{ 53813, DB_OFFSET - 33000},
{ 53427, DB_OFFSET - 34000},
{ 52981, DB_OFFSET - 35000},
{ 52636, DB_OFFSET - 36000},
{ 52014, DB_OFFSET - 37000},
{ 51674, DB_OFFSET - 38000},
{ 50692, DB_OFFSET - 39000},
{ 49824, DB_OFFSET - 40000},
{ 49052, DB_OFFSET - 41000},
{ 48436, DB_OFFSET - 42000},
{ 47836, DB_OFFSET - 43000},
{ 47368, DB_OFFSET - 44000},
{ 46468, DB_OFFSET - 45000},
{ 45597, DB_OFFSET - 46000},
{ 44586, DB_OFFSET - 47000},
{ 43667, DB_OFFSET - 48000},
{ 42673, DB_OFFSET - 49000},
{ 41816, DB_OFFSET - 50000},
{ 40876, DB_OFFSET - 51000},
{ 0, 0},
};
static u32 interpolate_value(u32 value, struct linear_segments *segments,
unsigned len)
{
u64 tmp64;
u32 dx;
s32 dy;
int i, ret;
if (value >= segments[0].x)
return segments[0].y;
if (value < segments[len-1].x)
return segments[len-1].y;
for (i = 1; i < len - 1; i++) {
/* If value is identical, no need to interpolate */
if (value == segments[i].x)
return segments[i].y;
if (value > segments[i].x)
break;
}
/* Linear interpolation between the two (x,y) points */
dy = segments[i - 1].y - segments[i].y;
dx = segments[i - 1].x - segments[i].x;
tmp64 = value - segments[i].x;
tmp64 *= dy;
do_div(tmp64, dx);
ret = segments[i].y + tmp64;
return ret;
}
/* FIXME: may require changes - this one was borrowed from dib8000 */
static u32 dib7000p_get_time_us(struct dvb_frontend *demod)
{
struct dtv_frontend_properties *c = &demod->dtv_property_cache;
u64 time_us, tmp64;
u32 tmp, denom;
int guard, rate_num, rate_denum = 1, bits_per_symbol;
int interleaving = 0, fft_div;
switch (c->guard_interval) {
case GUARD_INTERVAL_1_4:
guard = 4;
break;
case GUARD_INTERVAL_1_8:
guard = 8;
break;
case GUARD_INTERVAL_1_16:
guard = 16;
break;
default:
case GUARD_INTERVAL_1_32:
guard = 32;
break;
}
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
fft_div = 4;
break;
case TRANSMISSION_MODE_4K:
fft_div = 2;
break;
default:
case TRANSMISSION_MODE_8K:
fft_div = 1;
break;
}
switch (c->modulation) {
case DQPSK:
case QPSK:
bits_per_symbol = 2;
break;
case QAM_16:
bits_per_symbol = 4;
break;
default:
case QAM_64:
bits_per_symbol = 6;
break;
}
switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) {
case FEC_1_2:
rate_num = 1;
rate_denum = 2;
break;
case FEC_2_3:
rate_num = 2;
rate_denum = 3;
break;
case FEC_3_4:
rate_num = 3;
rate_denum = 4;
break;
case FEC_5_6:
rate_num = 5;
rate_denum = 6;
break;
default:
case FEC_7_8:
rate_num = 7;
rate_denum = 8;
break;
}
denom = bits_per_symbol * rate_num * fft_div * 384;
/*
* FIXME: check if the math makes sense. If so, fill the
* interleaving var.
*/
/* If calculus gets wrong, wait for 1s for the next stats */
if (!denom)
return 0;
/* Estimate the period for the total bit rate */
time_us = rate_denum * (1008 * 1562500L);
tmp64 = time_us;
do_div(tmp64, guard);
time_us = time_us + tmp64;
time_us += denom / 2;
do_div(time_us, denom);
tmp = 1008 * 96 * interleaving;
time_us += tmp + tmp / guard;
return time_us;
}
static int dib7000p_get_stats(struct dvb_frontend *demod, enum fe_status stat)
{
struct dib7000p_state *state = demod->demodulator_priv;
struct dtv_frontend_properties *c = &demod->dtv_property_cache;
int show_per_stats = 0;
u32 time_us = 0, val, snr;
u64 blocks, ucb;
s32 db;
u16 strength;
/* Get Signal strength */
dib7000p_read_signal_strength(demod, &strength);
val = strength;
db = interpolate_value(val,
strength_to_db_table,
ARRAY_SIZE(strength_to_db_table)) - DB_OFFSET;
c->strength.stat[0].svalue = db;
/* UCB/BER/CNR measures require lock */
if (!(stat & FE_HAS_LOCK)) {
c->cnr.len = 1;
c->block_count.len = 1;
c->block_error.len = 1;
c->post_bit_error.len = 1;
c->post_bit_count.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
/* Check if time for stats was elapsed */
if (time_after(jiffies, state->per_jiffies_stats)) {
state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
/* Get SNR */
snr = dib7000p_get_snr(demod);
if (snr)
snr = (1000L * snr) >> 24;
else
snr = 0;
c->cnr.stat[0].svalue = snr;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
/* Get UCB measures */
dib7000p_read_unc_blocks(demod, &val);
ucb = val - state->old_ucb;
if (val < state->old_ucb)
ucb += 0x100000000LL;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue = ucb;
/* Estimate the number of packets based on bitrate */
if (!time_us)
time_us = dib7000p_get_time_us(demod);
if (time_us) {
blocks = 1250000ULL * 1000000ULL;
do_div(blocks, time_us * 8 * 204);
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += blocks;
}
show_per_stats = 1;
}
/* Get post-BER measures */
if (time_after(jiffies, state->ber_jiffies_stats)) {
time_us = dib7000p_get_time_us(demod);
state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
dprintk("Next all layers stats available in %u us.\n", time_us);
dib7000p_read_ber(demod, &val);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += val;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += 100000000;
}
/* Get PER measures */
if (show_per_stats) {
dib7000p_read_unc_blocks(demod, &val);
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += val;
time_us = dib7000p_get_time_us(demod);
if (time_us) {
blocks = 1250000ULL * 1000000ULL;
do_div(blocks, time_us * 8 * 204);
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += blocks;
}
}
return 0;
}
static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void dib7000p_release(struct dvb_frontend *demod)
{
struct dib7000p_state *st = demod->demodulator_priv;
dibx000_exit_i2c_master(&st->i2c_master);
i2c_del_adapter(&st->dib7090_tuner_adap);
kfree(st);
}
static int dib7000pc_detection(struct i2c_adapter *i2c_adap)
{
u8 *tx, *rx;
struct i2c_msg msg[2] = {
{.addr = 18 >> 1, .flags = 0, .len = 2},
{.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
};
int ret = 0;
tx = kzalloc(2, GFP_KERNEL);
if (!tx)
return -ENOMEM;
rx = kzalloc(2, GFP_KERNEL);
if (!rx) {
ret = -ENOMEM;
goto rx_memory_error;
}
msg[0].buf = tx;
msg[1].buf = rx;
tx[0] = 0x03;
tx[1] = 0x00;
if (i2c_transfer(i2c_adap, msg, 2) == 2)
if (rx[0] == 0x01 && rx[1] == 0xb3) {
dprintk("-D- DiB7000PC detected\n");
ret = 1;
goto out;
}
msg[0].addr = msg[1].addr = 0x40;
if (i2c_transfer(i2c_adap, msg, 2) == 2)
if (rx[0] == 0x01 && rx[1] == 0xb3) {
dprintk("-D- DiB7000PC detected\n");
ret = 1;
goto out;
}
dprintk("-D- DiB7000PC not detected\n");
out:
kfree(rx);
rx_memory_error:
kfree(tx);
return ret;
}
static struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
{
struct dib7000p_state *st = demod->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
}
static int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 val = dib7000p_read_word(state, 235) & 0xffef;
val |= (onoff & 0x1) << 4;
dprintk("PID filter enabled %d\n", onoff);
return dib7000p_write_word(state, 235, val);
}
static int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib7000p_state *state = fe->demodulator_priv;
dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff);
return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
}
static int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
{
struct dib7000p_state *dpst;
int k = 0;
u8 new_addr = 0;
dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
if (!dpst)
return -ENOMEM;
dpst->i2c_adap = i2c;
mutex_init(&dpst->i2c_buffer_lock);
for (k = no_of_demods - 1; k >= 0; k--) {
dpst->cfg = cfg[k];
/* designated i2c address */
if (cfg[k].default_i2c_addr != 0)
new_addr = cfg[k].default_i2c_addr + (k << 1);
else
new_addr = (0x40 + k) << 1;
dpst->i2c_addr = new_addr;
dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(dpst) != 0) {
dpst->i2c_addr = default_addr;
dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(dpst) != 0) {
dprintk("DiB7000P #%d: not identified\n", k);
kfree(dpst);
return -EIO;
}
}
/* start diversity to pull_down div_str - just for i2c-enumeration */
dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
/* set new i2c address and force divstart */
dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
}
for (k = 0; k < no_of_demods; k++) {
dpst->cfg = cfg[k];
if (cfg[k].default_i2c_addr != 0)
dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
else
dpst->i2c_addr = (0x40 + k) << 1;
// unforce divstr
dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
/* deactivate div - it was just for i2c-enumeration */
dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
}
kfree(dpst);
return 0;
}
static const s32 lut_1000ln_mant[] = {
6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
};
static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
{
struct dib7000p_state *state = fe->demodulator_priv;
u32 tmp_val = 0, exp = 0, mant = 0;
s32 pow_i;
u16 buf[2];
u8 ix = 0;
buf[0] = dib7000p_read_word(state, 0x184);
buf[1] = dib7000p_read_word(state, 0x185);
pow_i = (buf[0] << 16) | buf[1];
dprintk("raw pow_i = %d\n", pow_i);
tmp_val = pow_i;
while (tmp_val >>= 1)
exp++;
mant = (pow_i * 1000 / (1 << exp));
dprintk(" mant = %d exp = %d\n", mant / 1000, exp);
ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
dprintk(" ix = %d\n", ix);
pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
pow_i = (pow_i << 8) / 1000;
dprintk(" pow_i = %d\n", pow_i);
return pow_i;
}
static int map_addr_to_serpar_number(struct i2c_msg *msg)
{
if ((msg->buf[0] <= 15))
msg->buf[0] -= 1;
else if (msg->buf[0] == 17)
msg->buf[0] = 15;
else if (msg->buf[0] == 16)
msg->buf[0] = 17;
else if (msg->buf[0] == 19)
msg->buf[0] = 16;
else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
msg->buf[0] -= 3;
else if (msg->buf[0] == 28)
msg->buf[0] = 23;
else
return -EINVAL;
return 0;
}
static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
while (n_overflow == 1 && i) {
n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("Tuner ITF: write busy (overflow)\n");
}
dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
return num;
}
static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1, n_empty = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
u16 read_word;
while (n_overflow == 1 && i) {
n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (overflow)\n");
}
dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
i = 1000;
while (n_empty == 1 && i) {
n_empty = dib7000p_read_word(state, 1984) & 0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (empty)\n");
}
read_word = dib7000p_read_word(state, 1987);
msg[1].buf[0] = (read_word >> 8) & 0xff;
msg[1].buf[1] = (read_word) & 0xff;
return num;
}
static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
if (num == 1) { /* write */
return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
} else { /* read */
return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
}
}
return num;
}
static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num, u16 apb_address)
{
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
u16 word;
if (num == 1) { /* write */
dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
} else {
word = dib7000p_read_word(state, apb_address);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
}
return num;
}
static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
u16 apb_address = 0, word;
int i = 0;
switch (msg[0].buf[0]) {
case 0x12:
apb_address = 1920;
break;
case 0x14:
apb_address = 1921;
break;
case 0x24:
apb_address = 1922;
break;
case 0x1a:
apb_address = 1923;
break;
case 0x22:
apb_address = 1924;
break;
case 0x33:
apb_address = 1926;
break;
case 0x34:
apb_address = 1927;
break;
case 0x35:
apb_address = 1928;
break;
case 0x36:
apb_address = 1929;
break;
case 0x37:
apb_address = 1930;
break;
case 0x38:
apb_address = 1931;
break;
case 0x39:
apb_address = 1932;
break;
case 0x2a:
apb_address = 1935;
break;
case 0x2b:
apb_address = 1936;
break;
case 0x2c:
apb_address = 1937;
break;
case 0x2d:
apb_address = 1938;
break;
case 0x2e:
apb_address = 1939;
break;
case 0x2f:
apb_address = 1940;
break;
case 0x30:
apb_address = 1941;
break;
case 0x31:
apb_address = 1942;
break;
case 0x32:
apb_address = 1943;
break;
case 0x3e:
apb_address = 1944;
break;
case 0x3f:
apb_address = 1945;
break;
case 0x40:
apb_address = 1948;
break;
case 0x25:
apb_address = 914;
break;
case 0x26:
apb_address = 915;
break;
case 0x27:
apb_address = 917;
break;
case 0x28:
apb_address = 916;
break;
case 0x1d:
i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
word = dib7000p_read_word(state, 384 + i);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
return num;
case 0x1f:
if (num == 1) { /* write */
word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
word &= 0x3;
word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
dib7000p_write_word(state, 72, word); /* Set the proper input */
return num;
}
}
if (apb_address != 0) /* R/W access via APB */
return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
else /* R/W access via SERPAR */
return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
return 0;
}
static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static const struct i2c_algorithm dib7090_tuner_xfer_algo = {
.master_xfer = dib7090_tuner_xfer,
.functionality = dib7000p_i2c_func,
};
static struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
{
struct dib7000p_state *st = fe->demodulator_priv;
return &st->dib7090_tuner_adap;
}
static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
{
u16 reg;
/* drive host bus 2, 3, 4 */
reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
reg |= (drive << 12) | (drive << 6) | drive;
dib7000p_write_word(state, 1798, reg);
/* drive host bus 5,6 */
reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive << 8) | (drive << 2);
dib7000p_write_word(state, 1799, reg);
/* drive host bus 7, 8, 9 */
reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
reg |= (drive << 12) | (drive << 6) | drive;
dib7000p_write_word(state, 1800, reg);
/* drive host bus 10, 11 */
reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive << 8) | (drive << 2);
dib7000p_write_word(state, 1801, reg);
/* drive host bus 12, 13, 14 */
reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
reg |= (drive << 12) | (drive << 6) | drive;
dib7000p_write_word(state, 1802, reg);
return 0;
}
static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
{
u32 quantif = 3;
u32 nom = (insertExtSynchro * P_Kin + syncSize);
u32 denom = P_Kout;
u32 syncFreq = ((nom << quantif) / denom);
if ((syncFreq & ((1 << quantif) - 1)) != 0)
syncFreq = (syncFreq >> quantif) + 1;
else
syncFreq = (syncFreq >> quantif);
if (syncFreq != 0)
syncFreq = syncFreq - 1;
return syncFreq;
}
static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
{
dprintk("Configure DibStream Tx\n");
dib7000p_write_word(state, 1615, 1);
dib7000p_write_word(state, 1603, P_Kin);
dib7000p_write_word(state, 1605, P_Kout);
dib7000p_write_word(state, 1606, insertExtSynchro);
dib7000p_write_word(state, 1608, synchroMode);
dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
dib7000p_write_word(state, 1610, syncWord & 0xffff);
dib7000p_write_word(state, 1612, syncSize);
dib7000p_write_word(state, 1615, 0);
return 0;
}
static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
u32 dataOutRate)
{
u32 syncFreq;
dprintk("Configure DibStream Rx\n");
if ((P_Kin != 0) && (P_Kout != 0)) {
syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
dib7000p_write_word(state, 1542, syncFreq);
}
dib7000p_write_word(state, 1554, 1);
dib7000p_write_word(state, 1536, P_Kin);
dib7000p_write_word(state, 1537, P_Kout);
dib7000p_write_word(state, 1539, synchroMode);
dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
dib7000p_write_word(state, 1541, syncWord & 0xffff);
dib7000p_write_word(state, 1543, syncSize);
dib7000p_write_word(state, 1544, dataOutRate);
dib7000p_write_word(state, 1554, 0);
return 0;
}
static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
{
u16 reg_1287 = dib7000p_read_word(state, 1287);
switch (onoff) {
case 1:
reg_1287 &= ~(1<<7);
break;
case 0:
reg_1287 |= (1<<7);
break;
}
dib7000p_write_word(state, 1287, reg_1287);
}
static void dib7090_configMpegMux(struct dib7000p_state *state,
u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
{
dprintk("Enable Mpeg mux\n");
dib7090_enMpegMux(state, 0);
/* If the input mode is MPEG do not divide the serial clock */
if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
enSerialClkDiv2 = 0;
dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
| ((enSerialMode & 0x1) << 1)
| (enSerialClkDiv2 & 0x1));
dib7090_enMpegMux(state, 1);
}
static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
{
u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
switch (mode) {
case MPEG_ON_DIBTX:
dprintk("SET MPEG ON DIBSTREAM TX\n");
dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
reg_1288 |= (1<<9);
break;
case DIV_ON_DIBTX:
dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
reg_1288 |= (1<<8);
break;
case ADC_ON_DIBTX:
dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
reg_1288 |= (1<<7);
break;
default:
break;
}
dib7000p_write_word(state, 1288, reg_1288);
}
static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
{
u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
switch (mode) {
case DEMOUT_ON_HOSTBUS:
dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
dib7090_enMpegMux(state, 0);
reg_1288 |= (1<<6);
break;
case DIBTX_ON_HOSTBUS:
dprintk("SET DIBSTREAM TX ON HOST BUS\n");
dib7090_enMpegMux(state, 0);
reg_1288 |= (1<<5);
break;
case MPEG_ON_HOSTBUS:
dprintk("SET MPEG MUX ON HOST BUS\n");
reg_1288 |= (1<<4);
break;
default:
break;
}
dib7000p_write_word(state, 1288, reg_1288);
}
static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 reg_1287;
switch (onoff) {
case 0: /* only use the internal way - not the diversity input */
dprintk("%s mode OFF : by default Enable Mpeg INPUT\n", __func__);
dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
/* Do not divide the serial clock of MPEG MUX */
/* in SERIAL MODE in case input mode MPEG is used */
reg_1287 = dib7000p_read_word(state, 1287);
/* enSerialClkDiv2 == 1 ? */
if ((reg_1287 & 0x1) == 1) {
/* force enSerialClkDiv2 = 0 */
reg_1287 &= ~0x1;
dib7000p_write_word(state, 1287, reg_1287);
}
state->input_mode_mpeg = 1;
break;
case 1: /* both ways */
case 2: /* only the diversity input */
dprintk("%s ON : Enable diversity INPUT\n", __func__);
dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
state->input_mode_mpeg = 0;
break;
}
dib7000p_set_diversity_in(&state->demod, onoff);
return 0;
}
static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 outreg, smo_mode, fifo_threshold;
u8 prefer_mpeg_mux_use = 1;
int ret = 0;
dib7090_host_bus_drive(state, 1);
fifo_threshold = 1792;
smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
switch (mode) {
case OUTMODE_HIGH_Z:
outreg = 0;
break;
case OUTMODE_MPEG2_SERIAL:
if (prefer_mpeg_mux_use) {
dprintk("setting output mode TS_SERIAL using Mpeg Mux\n");
dib7090_configMpegMux(state, 3, 1, 1);
dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else {/* Use Smooth block */
dprintk("setting output mode TS_SERIAL using Smooth bloc\n");
dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (2<<6) | (0 << 1);
}
break;
case OUTMODE_MPEG2_PAR_GATED_CLK:
if (prefer_mpeg_mux_use) {
dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
dib7090_configMpegMux(state, 2, 0, 0);
dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else { /* Use Smooth block */
dprintk("setting output mode TS_PARALLEL_GATED using Smooth block\n");
dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (0<<6);
}
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
dprintk("setting output mode TS_PARALLEL_CONT using Smooth block\n");
dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (1<<6);
break;
case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
dprintk("setting output mode TS_FIFO using Smooth block\n");
dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (5<<6);
smo_mode |= (3 << 1);
fifo_threshold = 512;
break;
case OUTMODE_DIVERSITY:
dprintk("setting output mode MODE_DIVERSITY\n");
dib7090_setDibTxMux(state, DIV_ON_DIBTX);
dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
case OUTMODE_ANALOG_ADC:
dprintk("setting output mode MODE_ANALOG_ADC\n");
dib7090_setDibTxMux(state, ADC_ON_DIBTX);
dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
}
if (mode != OUTMODE_HIGH_Z)
outreg |= (1 << 10);
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
ret |= dib7000p_write_word(state, 235, smo_mode);
ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
ret |= dib7000p_write_word(state, 1286, outreg);
return ret;
}
static int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 en_cur_state;
dprintk("sleep dib7090: %d\n", onoff);
en_cur_state = dib7000p_read_word(state, 1922);
if (en_cur_state > 0xff)
state->tuner_enable = en_cur_state;
if (onoff)
en_cur_state &= 0x00ff;
else {
if (state->tuner_enable != 0)
en_cur_state = state->tuner_enable;
}
dib7000p_write_word(state, 1922, en_cur_state);
return 0;
}
static int dib7090_get_adc_power(struct dvb_frontend *fe)
{
return dib7000p_get_adc_power(fe);
}
static int dib7090_slave_reset(struct dvb_frontend *fe)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 reg;
reg = dib7000p_read_word(state, 1794);
dib7000p_write_word(state, 1794, reg | (4 << 12));
dib7000p_write_word(state, 1032, 0xffff);
return 0;
}
static const struct dvb_frontend_ops dib7000p_ops;
static struct dvb_frontend *dib7000p_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
{
struct dvb_frontend *demod;
struct dib7000p_state *st;
st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
if (st == NULL)
return NULL;
memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
st->i2c_adap = i2c_adap;
st->i2c_addr = i2c_addr;
st->gpio_val = cfg->gpio_val;
st->gpio_dir = cfg->gpio_dir;
/* Ensure the output mode remains at the previous default if it's
* not specifically set by the caller.
*/
if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
demod = &st->demod;
demod->demodulator_priv = st;
memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
mutex_init(&st->i2c_buffer_lock);
dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(st) != 0)
goto error;
st->version = dib7000p_read_word(st, 897);
/* FIXME: make sure the dev.parent field is initialized, or else
request_firmware() will hit an OOPS (this should be moved somewhere
more common) */
st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
/* init 7090 tuner adapter */
strscpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface",
sizeof(st->dib7090_tuner_adap.name));
st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
st->dib7090_tuner_adap.algo_data = NULL;
st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
i2c_set_adapdata(&st->dib7090_tuner_adap, st);
i2c_add_adapter(&st->dib7090_tuner_adap);
dib7000p_demod_reset(st);
dib7000p_reset_stats(demod);
if (st->version == SOC7090) {
dib7090_set_output_mode(demod, st->cfg.output_mode);
dib7090_set_diversity_in(demod, 0);
}
return demod;
error:
kfree(st);
return NULL;
}
void *dib7000p_attach(struct dib7000p_ops *ops)
{
if (!ops)
return NULL;
ops->slave_reset = dib7090_slave_reset;
ops->get_adc_power = dib7090_get_adc_power;
ops->dib7000pc_detection = dib7000pc_detection;
ops->get_i2c_tuner = dib7090_get_i2c_tuner;
ops->tuner_sleep = dib7090_tuner_sleep;
ops->init = dib7000p_init;
ops->set_agc1_min = dib7000p_set_agc1_min;
ops->set_gpio = dib7000p_set_gpio;
ops->i2c_enumeration = dib7000p_i2c_enumeration;
ops->pid_filter = dib7000p_pid_filter;
ops->pid_filter_ctrl = dib7000p_pid_filter_ctrl;
ops->get_i2c_master = dib7000p_get_i2c_master;
ops->update_pll = dib7000p_update_pll;
ops->ctrl_timf = dib7000p_ctrl_timf;
ops->get_agc_values = dib7000p_get_agc_values;
ops->set_wbd_ref = dib7000p_set_wbd_ref;
return ops;
}
EXPORT_SYMBOL_GPL(dib7000p_attach);
static const struct dvb_frontend_ops dib7000p_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 7000PC",
.frequency_min_hz = 44250 * kHz,
.frequency_max_hz = 867250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
},
.release = dib7000p_release,
.init = dib7000p_wakeup,
.sleep = dib7000p_sleep,
.set_frontend = dib7000p_set_frontend,
.get_tune_settings = dib7000p_fe_get_tune_settings,
.get_frontend = dib7000p_get_frontend,
.read_status = dib7000p_read_status,
.read_ber = dib7000p_read_ber,
.read_signal_strength = dib7000p_read_signal_strength,
.read_snr = dib7000p_read_snr,
.read_ucblocks = dib7000p_read_unc_blocks,
};
MODULE_AUTHOR("Olivier Grenie <[email protected]>");
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dib7000p.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for M88RS2000 demodulator and tuner
Copyright (C) 2012 Malcolm Priestley ([email protected])
Beta Driver
Include various calculation code from DS3000 driver.
Copyright (C) 2009 Konstantin Dimitrov.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/dvb_frontend.h>
#include "m88rs2000.h"
struct m88rs2000_state {
struct i2c_adapter *i2c;
const struct m88rs2000_config *config;
struct dvb_frontend frontend;
u8 no_lock_count;
u32 tuner_frequency;
u32 symbol_rate;
enum fe_code_rate fec_inner;
u8 tuner_level;
int errmode;
};
static int m88rs2000_debug;
module_param_named(debug, m88rs2000_debug, int, 0644);
MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
#define dprintk(level, args...) do { \
if (level & m88rs2000_debug) \
printk(KERN_DEBUG "m88rs2000-fe: " args); \
} while (0)
#define deb_info(args...) dprintk(0x01, args)
#define info(format, arg...) \
printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
static int m88rs2000_writereg(struct m88rs2000_state *state,
u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = state->config->demod_addr,
.flags = 0,
.buf = buf,
.len = 2
};
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_addr,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_addr,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return b1[0];
}
static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u32 mclk;
u8 reg;
/* Must not be 0x00 or 0xff */
reg = m88rs2000_readreg(state, 0x86);
if (!reg || reg == 0xff)
return 0;
reg /= 2;
reg += 1;
mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
return mclk;
}
static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u32 mclk;
s32 tmp;
u8 reg;
int ret;
mclk = m88rs2000_get_mclk(fe);
if (!mclk)
return -EINVAL;
tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
if (tmp < 0)
tmp += 4096;
/* Carrier Offset */
ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
reg = m88rs2000_readreg(state, 0x9d);
reg &= 0xf;
reg |= (u8)(tmp & 0xf) << 4;
ret |= m88rs2000_writereg(state, 0x9d, reg);
return ret;
}
static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
{
struct m88rs2000_state *state = fe->demodulator_priv;
int ret;
u64 temp;
u32 mclk;
u8 b[3];
if ((srate < 1000000) || (srate > 45000000))
return -EINVAL;
mclk = m88rs2000_get_mclk(fe);
if (!mclk)
return -EINVAL;
temp = srate / 1000;
temp *= 1 << 24;
do_div(temp, mclk);
b[0] = (u8) (temp >> 16) & 0xff;
b[1] = (u8) (temp >> 8) & 0xff;
b[2] = (u8) temp & 0xff;
ret = m88rs2000_writereg(state, 0x93, b[2]);
ret |= m88rs2000_writereg(state, 0x94, b[1]);
ret |= m88rs2000_writereg(state, 0x95, b[0]);
if (srate > 10000000)
ret |= m88rs2000_writereg(state, 0xa0, 0x20);
else
ret |= m88rs2000_writereg(state, 0xa0, 0x60);
ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
if (srate > 12000000)
ret |= m88rs2000_writereg(state, 0xa3, 0x20);
else if (srate > 2800000)
ret |= m88rs2000_writereg(state, 0xa3, 0x98);
else
ret |= m88rs2000_writereg(state, 0xa3, 0x90);
deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
return ret;
}
static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *m)
{
struct m88rs2000_state *state = fe->demodulator_priv;
int i;
u8 reg;
deb_info("%s\n", __func__);
m88rs2000_writereg(state, 0x9a, 0x30);
reg = m88rs2000_readreg(state, 0xb2);
reg &= 0x3f;
m88rs2000_writereg(state, 0xb2, reg);
for (i = 0; i < m->msg_len; i++)
m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
reg = m88rs2000_readreg(state, 0xb1);
reg &= 0x87;
reg |= ((m->msg_len - 1) << 3) | 0x07;
reg &= 0x7f;
m88rs2000_writereg(state, 0xb1, reg);
for (i = 0; i < 15; i++) {
if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
break;
msleep(20);
}
reg = m88rs2000_readreg(state, 0xb1);
if ((reg & 0x40) > 0x0) {
reg &= 0x7f;
reg |= 0x40;
m88rs2000_writereg(state, 0xb1, reg);
}
reg = m88rs2000_readreg(state, 0xb2);
reg &= 0x3f;
reg |= 0x80;
m88rs2000_writereg(state, 0xb2, reg);
m88rs2000_writereg(state, 0x9a, 0xb0);
return 0;
}
static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 reg0, reg1;
deb_info("%s\n", __func__);
m88rs2000_writereg(state, 0x9a, 0x30);
msleep(50);
reg0 = m88rs2000_readreg(state, 0xb1);
reg1 = m88rs2000_readreg(state, 0xb2);
/* TODO complete this section */
m88rs2000_writereg(state, 0xb2, reg1);
m88rs2000_writereg(state, 0xb1, reg0);
m88rs2000_writereg(state, 0x9a, 0xb0);
return 0;
}
static int m88rs2000_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 reg0, reg1;
m88rs2000_writereg(state, 0x9a, 0x30);
reg0 = m88rs2000_readreg(state, 0xb1);
reg1 = m88rs2000_readreg(state, 0xb2);
reg1 &= 0x3f;
switch (tone) {
case SEC_TONE_ON:
reg0 |= 0x4;
reg0 &= 0xbc;
break;
case SEC_TONE_OFF:
reg1 |= 0x80;
break;
default:
break;
}
m88rs2000_writereg(state, 0xb2, reg1);
m88rs2000_writereg(state, 0xb1, reg0);
m88rs2000_writereg(state, 0x9a, 0xb0);
return 0;
}
struct inittab {
u8 cmd;
u8 reg;
u8 val;
};
static struct inittab m88rs2000_setup[] = {
{DEMOD_WRITE, 0x9a, 0x30},
{DEMOD_WRITE, 0x00, 0x01},
{WRITE_DELAY, 0x19, 0x00},
{DEMOD_WRITE, 0x00, 0x00},
{DEMOD_WRITE, 0x9a, 0xb0},
{DEMOD_WRITE, 0x81, 0xc1},
{DEMOD_WRITE, 0x81, 0x81},
{DEMOD_WRITE, 0x86, 0xc6},
{DEMOD_WRITE, 0x9a, 0x30},
{DEMOD_WRITE, 0xf0, 0x22},
{DEMOD_WRITE, 0xf1, 0xbf},
{DEMOD_WRITE, 0xb0, 0x45},
{DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
{DEMOD_WRITE, 0x9a, 0xb0},
{0xff, 0xaa, 0xff}
};
static struct inittab m88rs2000_shutdown[] = {
{DEMOD_WRITE, 0x9a, 0x30},
{DEMOD_WRITE, 0xb0, 0x00},
{DEMOD_WRITE, 0xf1, 0x89},
{DEMOD_WRITE, 0x00, 0x01},
{DEMOD_WRITE, 0x9a, 0xb0},
{DEMOD_WRITE, 0x81, 0x81},
{0xff, 0xaa, 0xff}
};
static struct inittab fe_reset[] = {
{DEMOD_WRITE, 0x00, 0x01},
{DEMOD_WRITE, 0x20, 0x81},
{DEMOD_WRITE, 0x21, 0x80},
{DEMOD_WRITE, 0x10, 0x33},
{DEMOD_WRITE, 0x11, 0x44},
{DEMOD_WRITE, 0x12, 0x07},
{DEMOD_WRITE, 0x18, 0x20},
{DEMOD_WRITE, 0x28, 0x04},
{DEMOD_WRITE, 0x29, 0x8e},
{DEMOD_WRITE, 0x3b, 0xff},
{DEMOD_WRITE, 0x32, 0x10},
{DEMOD_WRITE, 0x33, 0x02},
{DEMOD_WRITE, 0x34, 0x30},
{DEMOD_WRITE, 0x35, 0xff},
{DEMOD_WRITE, 0x38, 0x50},
{DEMOD_WRITE, 0x39, 0x68},
{DEMOD_WRITE, 0x3c, 0x7f},
{DEMOD_WRITE, 0x3d, 0x0f},
{DEMOD_WRITE, 0x45, 0x20},
{DEMOD_WRITE, 0x46, 0x24},
{DEMOD_WRITE, 0x47, 0x7c},
{DEMOD_WRITE, 0x48, 0x16},
{DEMOD_WRITE, 0x49, 0x04},
{DEMOD_WRITE, 0x4a, 0x01},
{DEMOD_WRITE, 0x4b, 0x78},
{DEMOD_WRITE, 0X4d, 0xd2},
{DEMOD_WRITE, 0x4e, 0x6d},
{DEMOD_WRITE, 0x50, 0x30},
{DEMOD_WRITE, 0x51, 0x30},
{DEMOD_WRITE, 0x54, 0x7b},
{DEMOD_WRITE, 0x56, 0x09},
{DEMOD_WRITE, 0x58, 0x59},
{DEMOD_WRITE, 0x59, 0x37},
{DEMOD_WRITE, 0x63, 0xfa},
{0xff, 0xaa, 0xff}
};
static struct inittab fe_trigger[] = {
{DEMOD_WRITE, 0x97, 0x04},
{DEMOD_WRITE, 0x99, 0x77},
{DEMOD_WRITE, 0x9b, 0x64},
{DEMOD_WRITE, 0x9e, 0x00},
{DEMOD_WRITE, 0x9f, 0xf8},
{DEMOD_WRITE, 0x98, 0xff},
{DEMOD_WRITE, 0xc0, 0x0f},
{DEMOD_WRITE, 0x89, 0x01},
{DEMOD_WRITE, 0x00, 0x00},
{WRITE_DELAY, 0x0a, 0x00},
{DEMOD_WRITE, 0x00, 0x01},
{DEMOD_WRITE, 0x00, 0x00},
{DEMOD_WRITE, 0x9a, 0xb0},
{0xff, 0xaa, 0xff}
};
static int m88rs2000_tab_set(struct m88rs2000_state *state,
struct inittab *tab)
{
int ret = 0;
u8 i;
if (tab == NULL)
return -EINVAL;
for (i = 0; i < 255; i++) {
switch (tab[i].cmd) {
case 0x01:
ret = m88rs2000_writereg(state, tab[i].reg,
tab[i].val);
break;
case 0x10:
if (tab[i].reg > 0)
mdelay(tab[i].reg);
break;
case 0xff:
if (tab[i].reg == 0xaa && tab[i].val == 0xff)
return 0;
break;
case 0x00:
break;
default:
return -EINVAL;
}
if (ret < 0)
return -ENODEV;
}
return 0;
}
static int m88rs2000_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage volt)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 data;
data = m88rs2000_readreg(state, 0xb2);
data |= 0x03; /* bit0 V/H, bit1 off/on */
switch (volt) {
case SEC_VOLTAGE_18:
data &= ~0x03;
break;
case SEC_VOLTAGE_13:
data &= ~0x03;
data |= 0x01;
break;
case SEC_VOLTAGE_OFF:
break;
}
m88rs2000_writereg(state, 0xb2, data);
return 0;
}
static int m88rs2000_init(struct dvb_frontend *fe)
{
struct m88rs2000_state *state = fe->demodulator_priv;
int ret;
deb_info("m88rs2000: init chip\n");
/* Setup frontend from shutdown/cold */
if (state->config->inittab)
ret = m88rs2000_tab_set(state,
(struct inittab *)state->config->inittab);
else
ret = m88rs2000_tab_set(state, m88rs2000_setup);
return ret;
}
static int m88rs2000_sleep(struct dvb_frontend *fe)
{
struct m88rs2000_state *state = fe->demodulator_priv;
int ret;
/* Shutdown the frondend */
ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
return ret;
}
static int m88rs2000_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 reg = m88rs2000_readreg(state, 0x8c);
*status = 0;
if ((reg & 0xee) == 0xee) {
*status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
| FE_HAS_SYNC | FE_HAS_LOCK;
if (state->config->set_ts_params)
state->config->set_ts_params(fe, CALL_IS_READ);
}
return 0;
}
static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 tmp0, tmp1;
m88rs2000_writereg(state, 0x9a, 0x30);
tmp0 = m88rs2000_readreg(state, 0xd8);
if ((tmp0 & 0x10) != 0) {
m88rs2000_writereg(state, 0x9a, 0xb0);
*ber = 0xffffffff;
return 0;
}
*ber = (m88rs2000_readreg(state, 0xd7) << 8) |
m88rs2000_readreg(state, 0xd6);
tmp1 = m88rs2000_readreg(state, 0xd9);
m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
/* needs twice */
m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
m88rs2000_writereg(state, 0x9a, 0xb0);
return 0;
}
static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
if (fe->ops.tuner_ops.get_rf_strength)
fe->ops.tuner_ops.get_rf_strength(fe, strength);
return 0;
}
static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct m88rs2000_state *state = fe->demodulator_priv;
*snr = 512 * m88rs2000_readreg(state, 0x65);
return 0;
}
static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct m88rs2000_state *state = fe->demodulator_priv;
u8 tmp;
*ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
m88rs2000_readreg(state, 0xd4);
tmp = m88rs2000_readreg(state, 0xd8);
m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
/* needs two times */
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
return 0;
}
static int m88rs2000_set_fec(struct m88rs2000_state *state,
enum fe_code_rate fec)
{
u8 fec_set, reg;
int ret;
switch (fec) {
case FEC_1_2:
fec_set = 0x8;
break;
case FEC_2_3:
fec_set = 0x10;
break;
case FEC_3_4:
fec_set = 0x20;
break;
case FEC_5_6:
fec_set = 0x40;
break;
case FEC_7_8:
fec_set = 0x80;
break;
case FEC_AUTO:
default:
fec_set = 0x0;
}
reg = m88rs2000_readreg(state, 0x70);
reg &= 0x7;
ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
ret |= m88rs2000_writereg(state, 0x76, 0x8);
return ret;
}
static enum fe_code_rate m88rs2000_get_fec(struct m88rs2000_state *state)
{
u8 reg;
m88rs2000_writereg(state, 0x9a, 0x30);
reg = m88rs2000_readreg(state, 0x76);
m88rs2000_writereg(state, 0x9a, 0xb0);
reg &= 0xf0;
reg >>= 5;
switch (reg) {
case 0x4:
return FEC_1_2;
case 0x3:
return FEC_2_3;
case 0x2:
return FEC_3_4;
case 0x1:
return FEC_5_6;
case 0x0:
return FEC_7_8;
default:
break;
}
return FEC_AUTO;
}
static int m88rs2000_set_frontend(struct dvb_frontend *fe)
{
struct m88rs2000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
enum fe_status status = 0;
int i, ret = 0;
u32 tuner_freq;
s16 offset = 0;
u8 reg;
state->no_lock_count = 0;
if (c->delivery_system != SYS_DVBS) {
deb_info("%s: unsupported delivery system selected (%d)\n",
__func__, c->delivery_system);
return -EOPNOTSUPP;
}
/* Set Tuner */
if (fe->ops.tuner_ops.set_params)
ret = fe->ops.tuner_ops.set_params(fe);
if (ret < 0)
return -ENODEV;
if (fe->ops.tuner_ops.get_frequency) {
ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
if (ret < 0)
return -ENODEV;
offset = (s16)((s32)tuner_freq - c->frequency);
} else {
offset = 0;
}
/* default mclk value 96.4285 * 2 * 1000 = 192857 */
if (((c->frequency % 192857) >= (192857 - 3000)) ||
(c->frequency % 192857) <= 3000)
ret = m88rs2000_writereg(state, 0x86, 0xc2);
else
ret = m88rs2000_writereg(state, 0x86, 0xc6);
ret |= m88rs2000_set_carrieroffset(fe, offset);
if (ret < 0)
return -ENODEV;
/* Reset demod by symbol rate */
if (c->symbol_rate > 27500000)
ret = m88rs2000_writereg(state, 0xf1, 0xa4);
else
ret = m88rs2000_writereg(state, 0xf1, 0xbf);
ret |= m88rs2000_tab_set(state, fe_reset);
if (ret < 0)
return -ENODEV;
/* Set FEC */
ret = m88rs2000_set_fec(state, c->fec_inner);
ret |= m88rs2000_writereg(state, 0x85, 0x1);
ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
ret |= m88rs2000_writereg(state, 0x90, 0xf1);
ret |= m88rs2000_writereg(state, 0x91, 0x08);
if (ret < 0)
return -ENODEV;
/* Set Symbol Rate */
ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
if (ret < 0)
return -ENODEV;
/* Set up Demod */
ret = m88rs2000_tab_set(state, fe_trigger);
if (ret < 0)
return -ENODEV;
for (i = 0; i < 25; i++) {
reg = m88rs2000_readreg(state, 0x8c);
if ((reg & 0xee) == 0xee) {
status = FE_HAS_LOCK;
break;
}
state->no_lock_count++;
if (state->no_lock_count == 15) {
reg = m88rs2000_readreg(state, 0x70);
reg ^= 0x4;
m88rs2000_writereg(state, 0x70, reg);
state->no_lock_count = 0;
}
msleep(20);
}
if (status & FE_HAS_LOCK) {
state->fec_inner = m88rs2000_get_fec(state);
/* Unknown suspect SNR level */
reg = m88rs2000_readreg(state, 0x65);
}
state->tuner_frequency = c->frequency;
state->symbol_rate = c->symbol_rate;
return 0;
}
static int m88rs2000_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct m88rs2000_state *state = fe->demodulator_priv;
c->fec_inner = state->fec_inner;
c->frequency = state->tuner_frequency;
c->symbol_rate = state->symbol_rate;
return 0;
}
static int m88rs2000_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->symbol_rate > 3000000)
tune->min_delay_ms = 2000;
else
tune->min_delay_ms = 3000;
tune->step_size = c->symbol_rate / 16000;
tune->max_drift = c->symbol_rate / 2000;
return 0;
}
static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct m88rs2000_state *state = fe->demodulator_priv;
if (enable)
m88rs2000_writereg(state, 0x81, 0x84);
else
m88rs2000_writereg(state, 0x81, 0x81);
udelay(10);
return 0;
}
static void m88rs2000_release(struct dvb_frontend *fe)
{
struct m88rs2000_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops m88rs2000_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "M88RS2000 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1 * MHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500, /* ppm */
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_QPSK | FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_AUTO
},
.release = m88rs2000_release,
.init = m88rs2000_init,
.sleep = m88rs2000_sleep,
.i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
.read_status = m88rs2000_read_status,
.read_ber = m88rs2000_read_ber,
.read_signal_strength = m88rs2000_read_signal_strength,
.read_snr = m88rs2000_read_snr,
.read_ucblocks = m88rs2000_read_ucblocks,
.diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
.diseqc_send_burst = m88rs2000_send_diseqc_burst,
.set_tone = m88rs2000_set_tone,
.set_voltage = m88rs2000_set_voltage,
.set_frontend = m88rs2000_set_frontend,
.get_frontend = m88rs2000_get_frontend,
.get_tune_settings = m88rs2000_get_tune_settings,
};
struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
struct i2c_adapter *i2c)
{
struct m88rs2000_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->tuner_frequency = 0;
state->symbol_rate = 0;
state->fec_inner = 0;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &m88rs2000_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(m88rs2000_attach);
MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
MODULE_AUTHOR("Malcolm Priestley [email protected]");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.13");
| linux-master | drivers/media/dvb-frontends/m88rs2000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ascot2e.c
*
* Sony Ascot3E DVB-T/T2/C/C2 tuner driver
*
* Copyright 2012 Sony Corporation
* Copyright (C) 2014 NetUP Inc.
* Copyright (C) 2014 Sergey Kozlov <[email protected]>
* Copyright (C) 2014 Abylay Ospan <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/types.h>
#include "ascot2e.h"
#include <media/dvb_frontend.h>
#define MAX_WRITE_REGSIZE 10
enum ascot2e_state {
STATE_UNKNOWN,
STATE_SLEEP,
STATE_ACTIVE
};
struct ascot2e_priv {
u32 frequency;
u8 i2c_address;
struct i2c_adapter *i2c;
enum ascot2e_state state;
void *set_tuner_data;
int (*set_tuner)(void *, int);
};
enum ascot2e_tv_system_t {
ASCOT2E_DTV_DVBT_5,
ASCOT2E_DTV_DVBT_6,
ASCOT2E_DTV_DVBT_7,
ASCOT2E_DTV_DVBT_8,
ASCOT2E_DTV_DVBT2_1_7,
ASCOT2E_DTV_DVBT2_5,
ASCOT2E_DTV_DVBT2_6,
ASCOT2E_DTV_DVBT2_7,
ASCOT2E_DTV_DVBT2_8,
ASCOT2E_DTV_DVBC_6,
ASCOT2E_DTV_DVBC_8,
ASCOT2E_DTV_DVBC2_6,
ASCOT2E_DTV_DVBC2_8,
ASCOT2E_DTV_UNKNOWN
};
struct ascot2e_band_sett {
u8 if_out_sel;
u8 agc_sel;
u8 mix_oll;
u8 rf_gain;
u8 if_bpf_gc;
u8 fif_offset;
u8 bw_offset;
u8 bw;
u8 rf_oldet;
u8 if_bpf_f0;
};
#define ASCOT2E_AUTO 0xff
#define ASCOT2E_OFFSET(ofs) ((u8)(ofs) & 0x1F)
#define ASCOT2E_BW_6 0x00
#define ASCOT2E_BW_7 0x01
#define ASCOT2E_BW_8 0x02
#define ASCOT2E_BW_1_7 0x03
static struct ascot2e_band_sett ascot2e_sett[] = {
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-10), ASCOT2E_OFFSET(-16), ASCOT2E_BW_1_7, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-8), ASCOT2E_BW_6, 0x09, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(-1), ASCOT2E_BW_8, 0x09, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_6, 0x09, 0x00 },
{ ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(2), ASCOT2E_BW_8, 0x09, 0x00 }
};
static void ascot2e_i2c_debug(struct ascot2e_priv *priv,
u8 reg, u8 write, const u8 *data, u32 len)
{
dev_dbg(&priv->i2c->dev, "ascot2e: I2C %s reg 0x%02x size %d\n",
(write == 0 ? "read" : "write"), reg, len);
print_hex_dump_bytes("ascot2e: I2C data: ",
DUMP_PREFIX_OFFSET, data, len);
}
static int ascot2e_write_regs(struct ascot2e_priv *priv,
u8 reg, const u8 *data, u32 len)
{
int ret;
u8 buf[MAX_WRITE_REGSIZE + 1];
struct i2c_msg msg[1] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = len + 1,
.buf = buf,
}
};
if (len + 1 > sizeof(buf)) {
dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
reg, len + 1);
return -E2BIG;
}
ascot2e_i2c_debug(priv, reg, 1, data, len);
buf[0] = reg;
memcpy(&buf[1], data, len);
ret = i2c_transfer(priv->i2c, msg, 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c wr failed=%d reg=%02x len=%d\n",
KBUILD_MODNAME, ret, reg, len);
return ret;
}
return 0;
}
static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val)
{
u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
return ascot2e_write_regs(priv, reg, &tmp, 1);
}
static int ascot2e_read_regs(struct ascot2e_priv *priv,
u8 reg, u8 *val, u32 len)
{
int ret;
struct i2c_msg msg[2] = {
{
.addr = priv->i2c_address,
.flags = 0,
.len = 1,
.buf = ®,
}, {
.addr = priv->i2c_address,
.flags = I2C_M_RD,
.len = len,
.buf = val,
}
};
ret = i2c_transfer(priv->i2c, &msg[0], 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: I2C rw failed=%d addr=%02x reg=%02x\n",
KBUILD_MODNAME, ret, priv->i2c_address, reg);
return ret;
}
ret = i2c_transfer(priv->i2c, &msg[1], 1);
if (ret >= 0 && ret != 1)
ret = -EREMOTEIO;
if (ret < 0) {
dev_warn(&priv->i2c->dev,
"%s: i2c rd failed=%d addr=%02x reg=%02x\n",
KBUILD_MODNAME, ret, priv->i2c_address, reg);
return ret;
}
ascot2e_i2c_debug(priv, reg, 0, val, len);
return 0;
}
static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val)
{
return ascot2e_read_regs(priv, reg, val, 1);
}
static int ascot2e_set_reg_bits(struct ascot2e_priv *priv,
u8 reg, u8 data, u8 mask)
{
int res;
u8 rdata;
if (mask != 0xff) {
res = ascot2e_read_reg(priv, reg, &rdata);
if (res != 0)
return res;
data = ((data & mask) | (rdata & (mask ^ 0xFF)));
}
return ascot2e_write_reg(priv, reg, data);
}
static int ascot2e_enter_power_save(struct ascot2e_priv *priv)
{
u8 data[2];
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_SLEEP)
return 0;
data[0] = 0x00;
data[1] = 0x04;
ascot2e_write_regs(priv, 0x14, data, 2);
ascot2e_write_reg(priv, 0x50, 0x01);
priv->state = STATE_SLEEP;
return 0;
}
static int ascot2e_leave_power_save(struct ascot2e_priv *priv)
{
u8 data[2] = { 0xFB, 0x0F };
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
if (priv->state == STATE_ACTIVE)
return 0;
ascot2e_write_regs(priv, 0x14, data, 2);
ascot2e_write_reg(priv, 0x50, 0x00);
priv->state = STATE_ACTIVE;
return 0;
}
static int ascot2e_init(struct dvb_frontend *fe)
{
struct ascot2e_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
return ascot2e_leave_power_save(priv);
}
static void ascot2e_release(struct dvb_frontend *fe)
{
struct ascot2e_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static int ascot2e_sleep(struct dvb_frontend *fe)
{
struct ascot2e_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
ascot2e_enter_power_save(priv);
return 0;
}
static enum ascot2e_tv_system_t ascot2e_get_tv_system(struct dvb_frontend *fe)
{
enum ascot2e_tv_system_t system = ASCOT2E_DTV_UNKNOWN;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct ascot2e_priv *priv = fe->tuner_priv;
if (p->delivery_system == SYS_DVBT) {
if (p->bandwidth_hz <= 5000000)
system = ASCOT2E_DTV_DVBT_5;
else if (p->bandwidth_hz <= 6000000)
system = ASCOT2E_DTV_DVBT_6;
else if (p->bandwidth_hz <= 7000000)
system = ASCOT2E_DTV_DVBT_7;
else if (p->bandwidth_hz <= 8000000)
system = ASCOT2E_DTV_DVBT_8;
else {
system = ASCOT2E_DTV_DVBT_8;
p->bandwidth_hz = 8000000;
}
} else if (p->delivery_system == SYS_DVBT2) {
if (p->bandwidth_hz <= 5000000)
system = ASCOT2E_DTV_DVBT2_5;
else if (p->bandwidth_hz <= 6000000)
system = ASCOT2E_DTV_DVBT2_6;
else if (p->bandwidth_hz <= 7000000)
system = ASCOT2E_DTV_DVBT2_7;
else if (p->bandwidth_hz <= 8000000)
system = ASCOT2E_DTV_DVBT2_8;
else {
system = ASCOT2E_DTV_DVBT2_8;
p->bandwidth_hz = 8000000;
}
} else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
if (p->bandwidth_hz <= 6000000)
system = ASCOT2E_DTV_DVBC_6;
else if (p->bandwidth_hz <= 8000000)
system = ASCOT2E_DTV_DVBC_8;
}
dev_dbg(&priv->i2c->dev,
"%s(): ASCOT2E DTV system %d (delsys %d, bandwidth %d)\n",
__func__, (int)system, p->delivery_system, p->bandwidth_hz);
return system;
}
static int ascot2e_set_params(struct dvb_frontend *fe)
{
u8 data[10];
u32 frequency;
enum ascot2e_tv_system_t tv_system;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct ascot2e_priv *priv = fe->tuner_priv;
dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n",
__func__, p->frequency / 1000);
tv_system = ascot2e_get_tv_system(fe);
if (tv_system == ASCOT2E_DTV_UNKNOWN) {
dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n",
__func__);
return -EINVAL;
}
if (priv->set_tuner)
priv->set_tuner(priv->set_tuner_data, 1);
frequency = roundup(p->frequency / 1000, 25);
if (priv->state == STATE_SLEEP)
ascot2e_leave_power_save(priv);
/* IF_OUT_SEL / AGC_SEL setting */
data[0] = 0x00;
if (ascot2e_sett[tv_system].agc_sel != ASCOT2E_AUTO) {
/* AGC pin setting from parameter table */
data[0] |= (u8)(
(ascot2e_sett[tv_system].agc_sel & 0x03) << 3);
}
if (ascot2e_sett[tv_system].if_out_sel != ASCOT2E_AUTO) {
/* IFOUT pin setting from parameter table */
data[0] |= (u8)(
(ascot2e_sett[tv_system].if_out_sel & 0x01) << 2);
}
/* Set bit[4:2] only */
ascot2e_set_reg_bits(priv, 0x05, data[0], 0x1c);
/* 0x06 - 0x0F */
/* REF_R setting (0x06) */
if (tv_system == ASCOT2E_DTV_DVBC_6 ||
tv_system == ASCOT2E_DTV_DVBC_8) {
/* xtal, xtal*2 */
data[0] = (frequency > 500000) ? 16 : 32;
} else {
/* xtal/8, xtal/4 */
data[0] = (frequency > 500000) ? 2 : 4;
}
/* XOSC_SEL=100uA */
data[1] = 0x04;
/* KBW setting (0x08), KC0 setting (0x09), KC1 setting (0x0A) */
if (tv_system == ASCOT2E_DTV_DVBC_6 ||
tv_system == ASCOT2E_DTV_DVBC_8) {
data[2] = 18;
data[3] = 120;
data[4] = 20;
} else {
data[2] = 48;
data[3] = 10;
data[4] = 30;
}
/* ORDER/R2_RANGE/R2_BANK/C2_BANK setting (0x0B) */
if (tv_system == ASCOT2E_DTV_DVBC_6 ||
tv_system == ASCOT2E_DTV_DVBC_8)
data[5] = (frequency > 500000) ? 0x08 : 0x0c;
else
data[5] = (frequency > 500000) ? 0x30 : 0x38;
/* Set MIX_OLL (0x0C) value from parameter table */
data[6] = ascot2e_sett[tv_system].mix_oll;
/* Set RF_GAIN (0x0D) setting from parameter table */
if (ascot2e_sett[tv_system].rf_gain == ASCOT2E_AUTO) {
/* RF_GAIN auto control enable */
ascot2e_write_reg(priv, 0x4E, 0x01);
/* RF_GAIN Default value */
data[7] = 0x00;
} else {
/* RF_GAIN auto control disable */
ascot2e_write_reg(priv, 0x4E, 0x00);
data[7] = ascot2e_sett[tv_system].rf_gain;
}
/* Set IF_BPF_GC/FIF_OFFSET (0x0E) value from parameter table */
data[8] = (u8)((ascot2e_sett[tv_system].fif_offset << 3) |
(ascot2e_sett[tv_system].if_bpf_gc & 0x07));
/* Set BW_OFFSET (0x0F) value from parameter table */
data[9] = ascot2e_sett[tv_system].bw_offset;
ascot2e_write_regs(priv, 0x06, data, 10);
/*
* 0x45 - 0x47
* LNA optimization setting
* RF_LNA_DIST1-5, RF_LNA_CM
*/
if (tv_system == ASCOT2E_DTV_DVBC_6 ||
tv_system == ASCOT2E_DTV_DVBC_8) {
data[0] = 0x0F;
data[1] = 0x00;
data[2] = 0x01;
} else {
data[0] = 0x0F;
data[1] = 0x00;
data[2] = 0x03;
}
ascot2e_write_regs(priv, 0x45, data, 3);
/* 0x49 - 0x4A
Set RF_OLDET_ENX/RF_OLDET_OLL value from parameter table */
data[0] = ascot2e_sett[tv_system].rf_oldet;
/* Set IF_BPF_F0 value from parameter table */
data[1] = ascot2e_sett[tv_system].if_bpf_f0;
ascot2e_write_regs(priv, 0x49, data, 2);
/*
* Tune now
* RFAGC fast mode / RFAGC auto control enable
* (set bit[7], bit[5:4] only)
* vco_cal = 1, set MIX_OL_CPU_EN
*/
ascot2e_set_reg_bits(priv, 0x0c, 0x90, 0xb0);
/* Logic wake up, CPU wake up */
data[0] = 0xc4;
data[1] = 0x40;
ascot2e_write_regs(priv, 0x03, data, 2);
/* 0x10 - 0x14 */
data[0] = (u8)(frequency & 0xFF); /* 0x10: FRF_L */
data[1] = (u8)((frequency >> 8) & 0xFF); /* 0x11: FRF_M */
data[2] = (u8)((frequency >> 16) & 0x0F); /* 0x12: FRF_H (bit[3:0]) */
/* 0x12: BW (bit[5:4]) */
data[2] |= (u8)(ascot2e_sett[tv_system].bw << 4);
data[3] = 0xFF; /* 0x13: VCO calibration enable */
data[4] = 0xFF; /* 0x14: Analog block enable */
/* Tune (Burst write) */
ascot2e_write_regs(priv, 0x10, data, 5);
msleep(50);
/* CPU deep sleep */
ascot2e_write_reg(priv, 0x04, 0x00);
/* Logic sleep */
ascot2e_write_reg(priv, 0x03, 0xC0);
/* RFAGC normal mode (set bit[5:4] only) */
ascot2e_set_reg_bits(priv, 0x0C, 0x00, 0x30);
priv->frequency = frequency;
return 0;
}
static int ascot2e_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct ascot2e_priv *priv = fe->tuner_priv;
*frequency = priv->frequency * 1000;
return 0;
}
static const struct dvb_tuner_ops ascot2e_tuner_ops = {
.info = {
.name = "Sony ASCOT2E",
.frequency_min_hz = 1 * MHz,
.frequency_max_hz = 1200 * MHz,
.frequency_step_hz = 25 * kHz,
},
.init = ascot2e_init,
.release = ascot2e_release,
.sleep = ascot2e_sleep,
.set_params = ascot2e_set_params,
.get_frequency = ascot2e_get_frequency,
};
struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe,
const struct ascot2e_config *config,
struct i2c_adapter *i2c)
{
u8 data[4];
struct ascot2e_priv *priv = NULL;
priv = kzalloc(sizeof(struct ascot2e_priv), GFP_KERNEL);
if (priv == NULL)
return NULL;
priv->i2c_address = (config->i2c_address >> 1);
priv->i2c = i2c;
priv->set_tuner_data = config->set_tuner_priv;
priv->set_tuner = config->set_tuner_callback;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* 16 MHz xTal frequency */
data[0] = 16;
/* VCO current setting */
data[1] = 0x06;
/* Logic wake up, CPU boot */
data[2] = 0xC4;
data[3] = 0x40;
ascot2e_write_regs(priv, 0x01, data, 4);
/* RFVGA optimization setting (RF_DIST0 - RF_DIST2) */
data[0] = 0x10;
data[1] = 0x3F;
data[2] = 0x25;
ascot2e_write_regs(priv, 0x22, data, 3);
/* PLL mode setting */
ascot2e_write_reg(priv, 0x28, 0x1e);
/* RSSI setting */
ascot2e_write_reg(priv, 0x59, 0x04);
/* TODO check CPU HW error state here */
msleep(80);
/* Xtal oscillator current control setting */
ascot2e_write_reg(priv, 0x4c, 0x01);
/* XOSC_SEL=100uA */
ascot2e_write_reg(priv, 0x07, 0x04);
/* CPU deep sleep */
ascot2e_write_reg(priv, 0x04, 0x00);
/* Logic sleep */
ascot2e_write_reg(priv, 0x03, 0xc0);
/* Power save setting */
data[0] = 0x00;
data[1] = 0x04;
ascot2e_write_regs(priv, 0x14, data, 2);
ascot2e_write_reg(priv, 0x50, 0x01);
priv->state = STATE_SLEEP;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
memcpy(&fe->ops.tuner_ops, &ascot2e_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = priv;
dev_info(&priv->i2c->dev,
"Sony ASCOT2E attached on addr=%x at I2C adapter %p\n",
priv->i2c_address, priv->i2c);
return fe;
}
EXPORT_SYMBOL_GPL(ascot2e_attach);
MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver");
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/ascot2e.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Zarlink zl10036 DVB-S silicon tuner
*
* Copyright (C) 2006 Tino Reichardt
* Copyright (C) 2007-2009 Matthias Schwarzott <[email protected]>
*
**
* The data sheet for this tuner can be found at:
* http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
*
* This one is working: (at my Avermedia DVB-S Pro)
* - zl10036 (40pin, FTA)
*
* A driver for zl10038 should be very similar.
*/
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "zl10036.h"
static int zl10036_debug;
#define dprintk(level, args...) \
do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
} while (0)
#define deb_info(args...) dprintk(0x01, args)
#define deb_i2c(args...) dprintk(0x02, args)
struct zl10036_state {
struct i2c_adapter *i2c;
const struct zl10036_config *config;
u32 frequency;
u8 br, bf;
};
/* This driver assumes the tuner is driven by a 10.111MHz Cristal */
#define _XTAL 10111
/* Some of the possible dividers:
* 64, (write 0x05 to reg), freq step size 158kHz
* 10, (write 0x0a to reg), freq step size 1.011kHz (used here)
* 5, (write 0x09 to reg), freq step size 2.022kHz
*/
#define _RDIV 10
#define _RDIV_REG 0x0a
#define _FR (_XTAL/_RDIV)
#define STATUS_POR 0x80 /* Power on Reset */
#define STATUS_FL 0x40 /* Frequency & Phase Lock */
/* read/write for zl10036 and zl10038 */
static int zl10036_read_status_reg(struct zl10036_state *state)
{
u8 status;
struct i2c_msg msg[1] = {
{ .addr = state->config->tuner_address, .flags = I2C_M_RD,
.buf = &status, .len = sizeof(status) },
};
if (i2c_transfer(state->i2c, msg, 1) != 1) {
printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
__func__, state->config->tuner_address);
return -EIO;
}
deb_i2c("R(status): %02x [FL=%d]\n", status,
(status & STATUS_FL) ? 1 : 0);
if (status & STATUS_POR)
deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n",
__func__);
return status;
}
static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
{
struct i2c_msg msg[1] = {
{ .addr = state->config->tuner_address, .flags = 0,
.buf = buf, .len = count },
};
u8 reg = 0;
int ret;
if (zl10036_debug & 0x02) {
/* every 8bit-value satisifes this!
* so only check for debug log */
if ((buf[0] & 0x80) == 0x00)
reg = 2;
else if ((buf[0] & 0xc0) == 0x80)
reg = 4;
else if ((buf[0] & 0xf0) == 0xc0)
reg = 6;
else if ((buf[0] & 0xf0) == 0xd0)
reg = 8;
else if ((buf[0] & 0xf0) == 0xe0)
reg = 10;
else if ((buf[0] & 0xf0) == 0xf0)
reg = 12;
deb_i2c("W(%d):", reg);
{
int i;
for (i = 0; i < count; i++)
printk(KERN_CONT " %02x", buf[i]);
printk(KERN_CONT "\n");
}
}
ret = i2c_transfer(state->i2c, msg, 1);
if (ret != 1) {
printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
return -EIO;
}
return 0;
}
static void zl10036_release(struct dvb_frontend *fe)
{
struct zl10036_state *state = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(state);
}
static int zl10036_sleep(struct dvb_frontend *fe)
{
struct zl10036_state *state = fe->tuner_priv;
u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
int ret;
deb_info("%s\n", __func__);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = zl10036_write(state, buf, sizeof(buf));
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return ret;
}
/*
* register map of the ZL10036/ZL10038
*
* reg[default] content
* 2[0x00]: 0 | N14 | N13 | N12 | N11 | N10 | N9 | N8
* 3[0x00]: N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0
* 4[0x80]: 1 | 0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
* 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
* 6[0xc0]: 1 | 1 | 0 | 0 | RSD | 0 | 0 | 0
* 7[0x20]: P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 | 0
* 8[0xdb]: 1 | 1 | 0 | 1 | 0 | CC | 1 | 1
* 9[0x30]: VSD | V2 | V1 | V0 | S3 | S2 | S1 | S0
* 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0
* 11[0xf5]: WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
* 12[0xf0]: 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0
* 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL
*/
static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
{
u8 buf[2];
u32 div, foffset;
div = (frequency + _FR/2) / _FR;
state->frequency = div * _FR;
foffset = frequency - state->frequency;
buf[0] = (div >> 8) & 0x7f;
buf[1] = (div >> 0) & 0xff;
deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
frequency, state->frequency, foffset, div);
return zl10036_write(state, buf, sizeof(buf));
}
static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
{
/* fbw is measured in kHz */
u8 br, bf;
int ret;
u8 buf_bf[] = {
0xc0, 0x00, /* 6/7: rsd=0 bf=0 */
};
u8 buf_br[] = {
0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
};
u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
/* ensure correct values */
if (fbw > 35000)
fbw = 35000;
if (fbw < 8000)
fbw = 8000;
#define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
/* <= 28,82 MHz */
if (fbw <= 28820) {
br = _BR_MAXIMUM;
} else {
/*
* f(bw)=34,6MHz f(xtal)=10.111MHz
* br = (10111/34600) * 63 * 1/K = 14;
*/
br = ((_XTAL * 21 * 1000) / (fbw * 419));
}
/* ensure correct values */
if (br < 4)
br = 4;
if (br > _BR_MAXIMUM)
br = _BR_MAXIMUM;
/*
* k = 1.257
* bf = fbw/_XTAL * br * k - 1 */
bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
/* ensure correct values */
if (bf > 62)
bf = 62;
buf_bf[1] = (bf << 1) & 0x7e;
buf_br[1] = (br << 2) & 0x7c;
deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
if (br != state->br) {
ret = zl10036_write(state, buf_br, sizeof(buf_br));
if (ret < 0)
return ret;
}
if (bf != state->bf) {
ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
if (ret < 0)
return ret;
/* time = br/(32* fxtal) */
/* minimal sleep time to be calculated
* maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
msleep(1);
ret = zl10036_write(state, zl10036_rsd_off,
sizeof(zl10036_rsd_off));
if (ret < 0)
return ret;
}
state->br = br;
state->bf = bf;
return 0;
}
static int zl10036_set_gain_params(struct zl10036_state *state,
int c)
{
u8 buf[2];
u8 rfg, ba, bg;
/* default values */
rfg = 0; /* enable when using an lna */
ba = 1;
bg = 1;
/* reg 4 */
buf[0] = 0x80 | ((rfg << 5) & 0x20)
| ((ba << 3) & 0x18) | ((bg << 1) & 0x06);
if (!state->config->rf_loop_enable)
buf[0] |= 0x01;
/* P0=0 */
buf[1] = _RDIV_REG | ((c << 5) & 0x60);
deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
return zl10036_write(state, buf, sizeof(buf));
}
static int zl10036_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct zl10036_state *state = fe->tuner_priv;
int ret = 0;
u32 frequency = p->frequency;
u32 fbw;
int i;
u8 c;
/* ensure correct values
* maybe redundant as core already checks this */
if ((frequency < fe->ops.info.frequency_min_hz / kHz)
|| (frequency > fe->ops.info.frequency_max_hz / kHz))
return -EINVAL;
/*
* alpha = 1.35 for dvb-s
* fBW = (alpha*symbolrate)/(2*0.8)
* 1.35 / (2*0.8) = 27 / 32
*/
fbw = (27 * p->symbol_rate) / 32;
/* scale to kHz */
fbw /= 1000;
/* Add safe margin of 3MHz */
fbw += 3000;
/* setting the charge pump - guessed values */
if (frequency < 950000)
return -EINVAL;
else if (frequency < 1250000)
c = 0;
else if (frequency < 1750000)
c = 1;
else if (frequency < 2175000)
c = 2;
else
return -EINVAL;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = zl10036_set_gain_params(state, c);
if (ret < 0)
goto error;
ret = zl10036_set_frequency(state, p->frequency);
if (ret < 0)
goto error;
ret = zl10036_set_bandwidth(state, fbw);
if (ret < 0)
goto error;
/* wait for tuner lock - no idea if this is really needed */
for (i = 0; i < 20; i++) {
ret = zl10036_read_status_reg(state);
if (ret < 0)
goto error;
/* check Frequency & Phase Lock Bit */
if (ret & STATUS_FL)
break;
msleep(10);
}
error:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return ret;
}
static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct zl10036_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static int zl10036_init_regs(struct zl10036_state *state)
{
int ret;
int i;
/* could also be one block from reg 2 to 13 and additional 10/11 */
u8 zl10036_init_tab[][2] = {
{ 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */
{ 0x8b, _RDIV_REG }, /* 4/5: rfg=0 ba=1 bg=1 len=? */
/* p0=0 c=0 r=_RDIV_REG */
{ 0xc0, 0x20 }, /* 6/7: rsd=0 bf=0x10 */
{ 0xd3, 0x40 }, /* 8/9: from datasheet */
{ 0xe3, 0x5b }, /* 10/11: lock window level */
{ 0xf0, 0x28 }, /* 12/13: br=0xa clr=0 tl=0*/
{ 0xe3, 0xf9 }, /* 10/11: unlock window level */
};
/* invalid values to trigger writing */
state->br = 0xff;
state->bf = 0xff;
if (!state->config->rf_loop_enable)
zl10036_init_tab[1][0] |= 0x01;
deb_info("%s\n", __func__);
for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
ret = zl10036_write(state, zl10036_init_tab[i], 2);
if (ret < 0)
return ret;
}
return 0;
}
static int zl10036_init(struct dvb_frontend *fe)
{
struct zl10036_state *state = fe->tuner_priv;
int ret = 0;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = zl10036_read_status_reg(state);
if (ret < 0)
return ret;
/* Only init if Power-on-Reset bit is set? */
ret = zl10036_init_regs(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
return ret;
}
static const struct dvb_tuner_ops zl10036_tuner_ops = {
.info = {
.name = "Zarlink ZL10036",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2175 * MHz
},
.init = zl10036_init,
.release = zl10036_release,
.sleep = zl10036_sleep,
.set_params = zl10036_set_params,
.get_frequency = zl10036_get_frequency,
};
struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
const struct zl10036_config *config,
struct i2c_adapter *i2c)
{
struct zl10036_state *state;
int ret;
if (!config) {
printk(KERN_ERR "%s: no config specified", __func__);
return NULL;
}
state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
if (!state)
return NULL;
state->config = config;
state->i2c = i2c;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
ret = zl10036_read_status_reg(state);
if (ret < 0) {
printk(KERN_ERR "%s: No zl10036 found\n", __func__);
goto error;
}
ret = zl10036_init_regs(state);
if (ret < 0) {
printk(KERN_ERR "%s: tuner initialization failed\n",
__func__);
goto error;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
fe->tuner_priv = state;
memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
sizeof(struct dvb_tuner_ops));
printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
return fe;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(zl10036_attach);
module_param_named(debug, zl10036_debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("DVB ZL10036 driver");
MODULE_AUTHOR("Tino Reichardt");
MODULE_AUTHOR("Matthias Schwarzott");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/zl10036.c |
// SPDX-License-Identifier: GPL-2.0
//
// Socionext MN88443x series demodulator driver for ISDB-S/ISDB-T.
//
// Copyright (c) 2018 Socionext Inc.
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/int_log.h>
#include "mn88443x.h"
/* ISDB-S registers */
#define ATSIDU_S 0x2f
#define ATSIDL_S 0x30
#define TSSET_S 0x31
#define AGCREAD_S 0x5a
#define CPMON1_S 0x5e
#define CPMON1_S_FSYNC BIT(5)
#define CPMON1_S_ERRMON BIT(4)
#define CPMON1_S_SIGOFF BIT(3)
#define CPMON1_S_W2LOCK BIT(2)
#define CPMON1_S_W1LOCK BIT(1)
#define CPMON1_S_DW1LOCK BIT(0)
#define TRMON_S 0x60
#define BERCNFLG_S 0x68
#define BERCNFLG_S_BERVRDY BIT(5)
#define BERCNFLG_S_BERVCHK BIT(4)
#define BERCNFLG_S_BERDRDY BIT(3)
#define BERCNFLG_S_BERDCHK BIT(2)
#define CNRDXU_S 0x69
#define CNRDXL_S 0x6a
#define CNRDYU_S 0x6b
#define CNRDYL_S 0x6c
#define BERVRDU_S 0x71
#define BERVRDL_S 0x72
#define DOSET1_S 0x73
/* Primary ISDB-T */
#define PLLASET1 0x00
#define PLLASET2 0x01
#define PLLBSET1 0x02
#define PLLBSET2 0x03
#define PLLSET 0x04
#define OUTCSET 0x08
#define OUTCSET_CHDRV_8MA 0xff
#define OUTCSET_CHDRV_4MA 0x00
#define PLDWSET 0x09
#define PLDWSET_NORMAL 0x00
#define PLDWSET_PULLDOWN 0xff
#define HIZSET1 0x0a
#define HIZSET2 0x0b
/* Secondary ISDB-T (for MN884434 only) */
#define RCVSET 0x00
#define TSSET1_M 0x01
#define TSSET2_M 0x02
#define TSSET3_M 0x03
#define INTACSET 0x08
#define HIZSET3 0x0b
/* ISDB-T registers */
#define TSSET1 0x05
#define TSSET1_TSASEL_MASK GENMASK(4, 3)
#define TSSET1_TSASEL_ISDBT (0x0 << 3)
#define TSSET1_TSASEL_ISDBS (0x1 << 3)
#define TSSET1_TSASEL_NONE (0x2 << 3)
#define TSSET1_TSBSEL_MASK GENMASK(2, 1)
#define TSSET1_TSBSEL_ISDBS (0x0 << 1)
#define TSSET1_TSBSEL_ISDBT (0x1 << 1)
#define TSSET1_TSBSEL_NONE (0x2 << 1)
#define TSSET2 0x06
#define TSSET3 0x07
#define TSSET3_INTASEL_MASK GENMASK(7, 6)
#define TSSET3_INTASEL_T (0x0 << 6)
#define TSSET3_INTASEL_S (0x1 << 6)
#define TSSET3_INTASEL_NONE (0x2 << 6)
#define TSSET3_INTBSEL_MASK GENMASK(5, 4)
#define TSSET3_INTBSEL_S (0x0 << 4)
#define TSSET3_INTBSEL_T (0x1 << 4)
#define TSSET3_INTBSEL_NONE (0x2 << 4)
#define OUTSET2 0x0d
#define PWDSET 0x0f
#define PWDSET_OFDMPD_MASK GENMASK(3, 2)
#define PWDSET_OFDMPD_DOWN BIT(3)
#define PWDSET_PSKPD_MASK GENMASK(1, 0)
#define PWDSET_PSKPD_DOWN BIT(1)
#define CLKSET1_T 0x11
#define MDSET_T 0x13
#define MDSET_T_MDAUTO_MASK GENMASK(7, 4)
#define MDSET_T_MDAUTO_AUTO (0xf << 4)
#define MDSET_T_MDAUTO_MANUAL (0x0 << 4)
#define MDSET_T_FFTS_MASK GENMASK(3, 2)
#define MDSET_T_FFTS_MODE1 (0x0 << 2)
#define MDSET_T_FFTS_MODE2 (0x1 << 2)
#define MDSET_T_FFTS_MODE3 (0x2 << 2)
#define MDSET_T_GI_MASK GENMASK(1, 0)
#define MDSET_T_GI_1_32 (0x0 << 0)
#define MDSET_T_GI_1_16 (0x1 << 0)
#define MDSET_T_GI_1_8 (0x2 << 0)
#define MDSET_T_GI_1_4 (0x3 << 0)
#define MDASET_T 0x14
#define ADCSET1_T 0x20
#define ADCSET1_T_REFSEL_MASK GENMASK(1, 0)
#define ADCSET1_T_REFSEL_2V (0x3 << 0)
#define ADCSET1_T_REFSEL_1_5V (0x2 << 0)
#define ADCSET1_T_REFSEL_1V (0x1 << 0)
#define NCOFREQU_T 0x24
#define NCOFREQM_T 0x25
#define NCOFREQL_T 0x26
#define FADU_T 0x27
#define FADM_T 0x28
#define FADL_T 0x29
#define AGCSET2_T 0x2c
#define AGCSET2_T_IFPOLINV_INC BIT(0)
#define AGCSET2_T_RFPOLINV_INC BIT(1)
#define AGCV3_T 0x3e
#define MDRD_T 0xa2
#define MDRD_T_SEGID_MASK GENMASK(5, 4)
#define MDRD_T_SEGID_13 (0x0 << 4)
#define MDRD_T_SEGID_1 (0x1 << 4)
#define MDRD_T_SEGID_3 (0x2 << 4)
#define MDRD_T_FFTS_MASK GENMASK(3, 2)
#define MDRD_T_FFTS_MODE1 (0x0 << 2)
#define MDRD_T_FFTS_MODE2 (0x1 << 2)
#define MDRD_T_FFTS_MODE3 (0x2 << 2)
#define MDRD_T_GI_MASK GENMASK(1, 0)
#define MDRD_T_GI_1_32 (0x0 << 0)
#define MDRD_T_GI_1_16 (0x1 << 0)
#define MDRD_T_GI_1_8 (0x2 << 0)
#define MDRD_T_GI_1_4 (0x3 << 0)
#define SSEQRD_T 0xa3
#define SSEQRD_T_SSEQSTRD_MASK GENMASK(3, 0)
#define SSEQRD_T_SSEQSTRD_RESET (0x0 << 0)
#define SSEQRD_T_SSEQSTRD_TUNING (0x1 << 0)
#define SSEQRD_T_SSEQSTRD_AGC (0x2 << 0)
#define SSEQRD_T_SSEQSTRD_SEARCH (0x3 << 0)
#define SSEQRD_T_SSEQSTRD_CLOCK_SYNC (0x4 << 0)
#define SSEQRD_T_SSEQSTRD_FREQ_SYNC (0x8 << 0)
#define SSEQRD_T_SSEQSTRD_FRAME_SYNC (0x9 << 0)
#define SSEQRD_T_SSEQSTRD_SYNC (0xa << 0)
#define SSEQRD_T_SSEQSTRD_LOCK (0xb << 0)
#define AGCRDU_T 0xa8
#define AGCRDL_T 0xa9
#define CNRDU_T 0xbe
#define CNRDL_T 0xbf
#define BERFLG_T 0xc0
#define BERFLG_T_BERDRDY BIT(7)
#define BERFLG_T_BERDCHK BIT(6)
#define BERFLG_T_BERVRDYA BIT(5)
#define BERFLG_T_BERVCHKA BIT(4)
#define BERFLG_T_BERVRDYB BIT(3)
#define BERFLG_T_BERVCHKB BIT(2)
#define BERFLG_T_BERVRDYC BIT(1)
#define BERFLG_T_BERVCHKC BIT(0)
#define BERRDU_T 0xc1
#define BERRDM_T 0xc2
#define BERRDL_T 0xc3
#define BERLENRDU_T 0xc4
#define BERLENRDL_T 0xc5
#define ERRFLG_T 0xc6
#define ERRFLG_T_BERDOVF BIT(7)
#define ERRFLG_T_BERVOVFA BIT(6)
#define ERRFLG_T_BERVOVFB BIT(5)
#define ERRFLG_T_BERVOVFC BIT(4)
#define ERRFLG_T_NERRFA BIT(3)
#define ERRFLG_T_NERRFB BIT(2)
#define ERRFLG_T_NERRFC BIT(1)
#define ERRFLG_T_NERRF BIT(0)
#define DOSET1_T 0xcf
#define CLK_LOW 4000000
#define CLK_DIRECT 20200000
#define CLK_MAX 25410000
#define S_T_FREQ 8126984 /* 512 / 63 MHz */
struct mn88443x_spec {
bool primary;
};
struct mn88443x_priv {
const struct mn88443x_spec *spec;
struct dvb_frontend fe;
struct clk *mclk;
struct gpio_desc *reset_gpio;
u32 clk_freq;
u32 if_freq;
/* Common */
bool use_clkbuf;
/* ISDB-S */
struct i2c_client *client_s;
struct regmap *regmap_s;
/* ISDB-T */
struct i2c_client *client_t;
struct regmap *regmap_t;
};
static int mn88443x_cmn_power_on(struct mn88443x_priv *chip)
{
struct device *dev = &chip->client_s->dev;
struct regmap *r_t = chip->regmap_t;
int ret;
ret = clk_prepare_enable(chip->mclk);
if (ret) {
dev_err(dev, "Failed to prepare and enable mclk: %d\n",
ret);
return ret;
}
gpiod_set_value_cansleep(chip->reset_gpio, 1);
usleep_range(100, 1000);
gpiod_set_value_cansleep(chip->reset_gpio, 0);
if (chip->spec->primary) {
regmap_write(r_t, OUTCSET, OUTCSET_CHDRV_8MA);
regmap_write(r_t, PLDWSET, PLDWSET_NORMAL);
regmap_write(r_t, HIZSET1, 0x80);
regmap_write(r_t, HIZSET2, 0xe0);
} else {
regmap_write(r_t, HIZSET3, 0x8f);
}
return 0;
}
static void mn88443x_cmn_power_off(struct mn88443x_priv *chip)
{
gpiod_set_value_cansleep(chip->reset_gpio, 1);
clk_disable_unprepare(chip->mclk);
}
static void mn88443x_s_sleep(struct mn88443x_priv *chip)
{
struct regmap *r_t = chip->regmap_t;
regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK,
PWDSET_PSKPD_DOWN);
}
static void mn88443x_s_wake(struct mn88443x_priv *chip)
{
struct regmap *r_t = chip->regmap_t;
regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK, 0);
}
static void mn88443x_s_tune(struct mn88443x_priv *chip,
struct dtv_frontend_properties *c)
{
struct regmap *r_s = chip->regmap_s;
regmap_write(r_s, ATSIDU_S, c->stream_id >> 8);
regmap_write(r_s, ATSIDL_S, c->stream_id);
regmap_write(r_s, TSSET_S, 0);
}
static int mn88443x_s_read_status(struct mn88443x_priv *chip,
struct dtv_frontend_properties *c,
enum fe_status *status)
{
struct regmap *r_s = chip->regmap_s;
u32 cpmon, tmpu, tmpl, flg;
u64 tmp;
/* Sync detection */
regmap_read(r_s, CPMON1_S, &cpmon);
*status = 0;
if (cpmon & CPMON1_S_FSYNC)
*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
if (cpmon & CPMON1_S_W2LOCK)
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
/* Signal strength */
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (*status & FE_HAS_SIGNAL) {
u32 agc;
regmap_read(r_s, AGCREAD_S, &tmpu);
agc = tmpu << 8;
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = agc;
}
/* C/N rate */
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (*status & FE_HAS_VITERBI) {
u32 cnr = 0, x, y, d;
u64 d_3 = 0;
regmap_read(r_s, CNRDXU_S, &tmpu);
regmap_read(r_s, CNRDXL_S, &tmpl);
x = (tmpu << 8) | tmpl;
regmap_read(r_s, CNRDYU_S, &tmpu);
regmap_read(r_s, CNRDYL_S, &tmpl);
y = (tmpu << 8) | tmpl;
/* CNR[dB]: 10 * log10(D) - 30.74 / D^3 - 3 */
/* D = x^2 / (2^15 * y - x^2) */
d = (y << 15) - x * x;
if (d > 0) {
/* (2^4 * D)^3 = 2^12 * D^3 */
/* 3.074 * 2^(12 + 24) = 211243671486 */
d_3 = div_u64(16 * x * x, d);
d_3 = d_3 * d_3 * d_3;
if (d_3)
d_3 = div_u64(211243671486ULL, d_3);
}
if (d_3) {
/* 0.3 * 2^24 = 5033164 */
tmp = (s64)2 * intlog10(x) - intlog10(abs(d)) - d_3
- 5033164;
cnr = div_u64(tmp * 10000, 1 << 24);
}
if (cnr) {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].uvalue = cnr;
}
}
/* BER */
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
regmap_read(r_s, BERCNFLG_S, &flg);
if ((*status & FE_HAS_VITERBI) && (flg & BERCNFLG_S_BERVRDY)) {
u32 bit_err, bit_cnt;
regmap_read(r_s, BERVRDU_S, &tmpu);
regmap_read(r_s, BERVRDL_S, &tmpl);
bit_err = (tmpu << 8) | tmpl;
bit_cnt = (1 << 13) * 204;
if (bit_cnt) {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = bit_err;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = bit_cnt;
}
}
return 0;
}
static void mn88443x_t_sleep(struct mn88443x_priv *chip)
{
struct regmap *r_t = chip->regmap_t;
regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK,
PWDSET_OFDMPD_DOWN);
}
static void mn88443x_t_wake(struct mn88443x_priv *chip)
{
struct regmap *r_t = chip->regmap_t;
regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK, 0);
}
static bool mn88443x_t_is_valid_clk(u32 adckt, u32 if_freq)
{
if (if_freq == DIRECT_IF_57MHZ) {
if (adckt >= CLK_DIRECT && adckt <= 21000000)
return true;
if (adckt >= 25300000 && adckt <= CLK_MAX)
return true;
} else if (if_freq == DIRECT_IF_44MHZ) {
if (adckt >= 25000000 && adckt <= CLK_MAX)
return true;
} else if (if_freq >= LOW_IF_4MHZ && if_freq < DIRECT_IF_44MHZ) {
if (adckt >= CLK_DIRECT && adckt <= CLK_MAX)
return true;
}
return false;
}
static int mn88443x_t_set_freq(struct mn88443x_priv *chip)
{
struct device *dev = &chip->client_s->dev;
struct regmap *r_t = chip->regmap_t;
s64 adckt, nco, ad_t;
u32 m, v;
/* Clock buffer (but not supported) or XTAL */
if (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) {
chip->use_clkbuf = true;
regmap_write(r_t, CLKSET1_T, 0x07);
adckt = 0;
} else {
chip->use_clkbuf = false;
regmap_write(r_t, CLKSET1_T, 0x00);
adckt = chip->clk_freq;
}
if (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) {
dev_err(dev, "Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\n",
chip->clk_freq, adckt, chip->if_freq);
return -EINVAL;
}
/* Direct IF or Low IF */
if (chip->if_freq == DIRECT_IF_57MHZ ||
chip->if_freq == DIRECT_IF_44MHZ)
nco = adckt * 2 - chip->if_freq;
else
nco = -((s64)chip->if_freq);
nco = div_s64(nco << 24, adckt);
ad_t = div_s64(adckt << 22, S_T_FREQ);
regmap_write(r_t, NCOFREQU_T, nco >> 16);
regmap_write(r_t, NCOFREQM_T, nco >> 8);
regmap_write(r_t, NCOFREQL_T, nco);
regmap_write(r_t, FADU_T, ad_t >> 16);
regmap_write(r_t, FADM_T, ad_t >> 8);
regmap_write(r_t, FADL_T, ad_t);
/* Level of IF */
m = ADCSET1_T_REFSEL_MASK;
v = ADCSET1_T_REFSEL_1_5V;
regmap_update_bits(r_t, ADCSET1_T, m, v);
/* Polarity of AGC */
v = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC;
regmap_update_bits(r_t, AGCSET2_T, v, v);
/* Lower output level of AGC */
regmap_write(r_t, AGCV3_T, 0x00);
regmap_write(r_t, MDSET_T, 0xfa);
return 0;
}
static void mn88443x_t_tune(struct mn88443x_priv *chip,
struct dtv_frontend_properties *c)
{
struct regmap *r_t = chip->regmap_t;
u32 m, v;
m = MDSET_T_MDAUTO_MASK | MDSET_T_FFTS_MASK | MDSET_T_GI_MASK;
v = MDSET_T_MDAUTO_AUTO | MDSET_T_FFTS_MODE3 | MDSET_T_GI_1_8;
regmap_update_bits(r_t, MDSET_T, m, v);
regmap_write(r_t, MDASET_T, 0);
}
static int mn88443x_t_read_status(struct mn88443x_priv *chip,
struct dtv_frontend_properties *c,
enum fe_status *status)
{
struct regmap *r_t = chip->regmap_t;
u32 seqrd, st, flg, tmpu, tmpm, tmpl;
u64 tmp;
/* Sync detection */
regmap_read(r_t, SSEQRD_T, &seqrd);
st = seqrd & SSEQRD_T_SSEQSTRD_MASK;
*status = 0;
if (st >= SSEQRD_T_SSEQSTRD_SYNC)
*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
if (st >= SSEQRD_T_SSEQSTRD_FRAME_SYNC)
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
/* Signal strength */
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (*status & FE_HAS_SIGNAL) {
u32 agc;
regmap_read(r_t, AGCRDU_T, &tmpu);
regmap_read(r_t, AGCRDL_T, &tmpl);
agc = (tmpu << 8) | tmpl;
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = agc;
}
/* C/N rate */
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
if (*status & FE_HAS_VITERBI) {
u32 cnr;
regmap_read(r_t, CNRDU_T, &tmpu);
regmap_read(r_t, CNRDL_T, &tmpl);
if (tmpu || tmpl) {
/* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
/* intlog10(65536) = 80807124, 0.2 * 2^24 = 3355443 */
tmp = (u64)80807124 - intlog10((tmpu << 8) | tmpl)
+ 3355443;
cnr = div_u64(tmp * 10000, 1 << 24);
} else {
cnr = 0;
}
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].uvalue = cnr;
}
/* BER */
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
regmap_read(r_t, BERFLG_T, &flg);
if ((*status & FE_HAS_VITERBI) && (flg & BERFLG_T_BERVRDYA)) {
u32 bit_err, bit_cnt;
regmap_read(r_t, BERRDU_T, &tmpu);
regmap_read(r_t, BERRDM_T, &tmpm);
regmap_read(r_t, BERRDL_T, &tmpl);
bit_err = (tmpu << 16) | (tmpm << 8) | tmpl;
regmap_read(r_t, BERLENRDU_T, &tmpu);
regmap_read(r_t, BERLENRDL_T, &tmpl);
bit_cnt = ((tmpu << 8) | tmpl) * 203 * 8;
if (bit_cnt) {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = bit_err;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = bit_cnt;
}
}
return 0;
}
static int mn88443x_sleep(struct dvb_frontend *fe)
{
struct mn88443x_priv *chip = fe->demodulator_priv;
mn88443x_s_sleep(chip);
mn88443x_t_sleep(chip);
return 0;
}
static int mn88443x_set_frontend(struct dvb_frontend *fe)
{
struct mn88443x_priv *chip = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct regmap *r_s = chip->regmap_s;
struct regmap *r_t = chip->regmap_t;
u8 tssel = 0, intsel = 0;
if (c->delivery_system == SYS_ISDBS) {
mn88443x_s_wake(chip);
mn88443x_t_sleep(chip);
tssel = TSSET1_TSASEL_ISDBS;
intsel = TSSET3_INTASEL_S;
} else if (c->delivery_system == SYS_ISDBT) {
mn88443x_s_sleep(chip);
mn88443x_t_wake(chip);
mn88443x_t_set_freq(chip);
tssel = TSSET1_TSASEL_ISDBT;
intsel = TSSET3_INTASEL_T;
}
regmap_update_bits(r_t, TSSET1,
TSSET1_TSASEL_MASK | TSSET1_TSBSEL_MASK,
tssel | TSSET1_TSBSEL_NONE);
regmap_write(r_t, TSSET2, 0);
regmap_update_bits(r_t, TSSET3,
TSSET3_INTASEL_MASK | TSSET3_INTBSEL_MASK,
intsel | TSSET3_INTBSEL_NONE);
regmap_write(r_t, DOSET1_T, 0x95);
regmap_write(r_s, DOSET1_S, 0x80);
if (c->delivery_system == SYS_ISDBS)
mn88443x_s_tune(chip, c);
else if (c->delivery_system == SYS_ISDBT)
mn88443x_t_tune(chip, c);
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
return 0;
}
static int mn88443x_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
s->min_delay_ms = 850;
if (c->delivery_system == SYS_ISDBS) {
s->max_drift = 30000 * 2 + 1;
s->step_size = 30000;
} else if (c->delivery_system == SYS_ISDBT) {
s->max_drift = 142857 * 2 + 1;
s->step_size = 142857 * 2;
}
return 0;
}
static int mn88443x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct mn88443x_priv *chip = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
if (c->delivery_system == SYS_ISDBS)
return mn88443x_s_read_status(chip, c, status);
if (c->delivery_system == SYS_ISDBT)
return mn88443x_t_read_status(chip, c, status);
return -EINVAL;
}
static const struct dvb_frontend_ops mn88443x_ops = {
.delsys = { SYS_ISDBS, SYS_ISDBT },
.info = {
.name = "Socionext MN88443x",
.frequency_min_hz = 470 * MHz,
.frequency_max_hz = 2071 * MHz,
.symbol_rate_min = 28860000,
.symbol_rate_max = 28860000,
.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
},
.sleep = mn88443x_sleep,
.set_frontend = mn88443x_set_frontend,
.get_tune_settings = mn88443x_get_tune_settings,
.read_status = mn88443x_read_status,
};
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_NONE,
};
static int mn88443x_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct mn88443x_config *conf = client->dev.platform_data;
struct mn88443x_priv *chip;
struct device *dev = &client->dev;
int ret;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
if (dev->of_node)
chip->spec = of_device_get_match_data(dev);
else
chip->spec = (struct mn88443x_spec *)id->driver_data;
if (!chip->spec)
return -EINVAL;
chip->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(chip->mclk) && !conf) {
dev_err(dev, "Failed to request mclk: %ld\n",
PTR_ERR(chip->mclk));
return PTR_ERR(chip->mclk);
}
ret = of_property_read_u32(dev->of_node, "if-frequency",
&chip->if_freq);
if (ret && !conf) {
dev_err(dev, "Failed to load IF frequency: %d.\n", ret);
return ret;
}
chip->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(chip->reset_gpio)) {
dev_err(dev, "Failed to request reset_gpio: %ld\n",
PTR_ERR(chip->reset_gpio));
return PTR_ERR(chip->reset_gpio);
}
if (conf) {
chip->mclk = conf->mclk;
chip->if_freq = conf->if_freq;
chip->reset_gpio = conf->reset_gpio;
*conf->fe = &chip->fe;
}
chip->client_s = client;
chip->regmap_s = devm_regmap_init_i2c(chip->client_s, ®map_config);
if (IS_ERR(chip->regmap_s))
return PTR_ERR(chip->regmap_s);
/*
* Chip has two I2C addresses for each satellite/terrestrial system.
* ISDB-T uses address ISDB-S + 4, so we register a dummy client.
*/
chip->client_t = i2c_new_dummy_device(client->adapter, client->addr + 4);
if (IS_ERR(chip->client_t))
return PTR_ERR(chip->client_t);
chip->regmap_t = devm_regmap_init_i2c(chip->client_t, ®map_config);
if (IS_ERR(chip->regmap_t)) {
ret = PTR_ERR(chip->regmap_t);
goto err_i2c_t;
}
chip->clk_freq = clk_get_rate(chip->mclk);
memcpy(&chip->fe.ops, &mn88443x_ops, sizeof(mn88443x_ops));
chip->fe.demodulator_priv = chip;
i2c_set_clientdata(client, chip);
ret = mn88443x_cmn_power_on(chip);
if (ret)
goto err_i2c_t;
mn88443x_s_sleep(chip);
mn88443x_t_sleep(chip);
return 0;
err_i2c_t:
i2c_unregister_device(chip->client_t);
return ret;
}
static void mn88443x_remove(struct i2c_client *client)
{
struct mn88443x_priv *chip = i2c_get_clientdata(client);
mn88443x_cmn_power_off(chip);
i2c_unregister_device(chip->client_t);
}
static const struct mn88443x_spec mn88443x_spec_pri = {
.primary = true,
};
static const struct mn88443x_spec mn88443x_spec_sec = {
.primary = false,
};
static const struct of_device_id mn88443x_of_match[] = {
{ .compatible = "socionext,mn884433", .data = &mn88443x_spec_pri, },
{ .compatible = "socionext,mn884434-0", .data = &mn88443x_spec_pri, },
{ .compatible = "socionext,mn884434-1", .data = &mn88443x_spec_sec, },
{}
};
MODULE_DEVICE_TABLE(of, mn88443x_of_match);
static const struct i2c_device_id mn88443x_i2c_id[] = {
{ "mn884433", (kernel_ulong_t)&mn88443x_spec_pri },
{ "mn884434-0", (kernel_ulong_t)&mn88443x_spec_pri },
{ "mn884434-1", (kernel_ulong_t)&mn88443x_spec_sec },
{}
};
MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id);
static struct i2c_driver mn88443x_driver = {
.driver = {
.name = "mn88443x",
.of_match_table = mn88443x_of_match,
},
.probe = mn88443x_probe,
.remove = mn88443x_remove,
.id_table = mn88443x_i2c_id,
};
module_i2c_driver(mn88443x_driver);
MODULE_AUTHOR("Katsuhiro Suzuki <[email protected]>");
MODULE_DESCRIPTION("Socionext MN88443x series demodulator driver.");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/mn88443x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for Philips tda10086 DVBS Demodulator
(c) 2006 Andrew de Quincey
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "tda10086.h"
#define SACLK 96000000U
struct tda10086_state {
struct i2c_adapter* i2c;
const struct tda10086_config* config;
struct dvb_frontend frontend;
/* private demod data */
u32 frequency;
u32 symbol_rate;
bool has_lock;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda10086: " args); \
} while (0)
static int tda10086_write_byte(struct tda10086_state *state, int reg, int data)
{
int ret;
u8 b0[] = { reg, data };
struct i2c_msg msg = { .flags = 0, .buf = b0, .len = 2 };
msg.addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
__func__, reg, data, ret);
return (ret != 1) ? ret : 0;
}
static int tda10086_read_byte(struct tda10086_state *state, int reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
{ .flags = I2C_M_RD, .buf = b1, .len = 1 }};
msg[0].addr = state->config->demod_address;
msg[1].addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
ret);
return ret;
}
return b1[0];
}
static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data)
{
int val;
/* read a byte and check */
val = tda10086_read_byte(state, reg);
if (val < 0)
return val;
/* mask if off */
val = val & ~mask;
val |= data & 0xff;
/* write it out again */
return tda10086_write_byte(state, reg, val);
}
static int tda10086_init(struct dvb_frontend* fe)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 t22k_off = 0x80;
dprintk ("%s\n", __func__);
if (state->config->diseqc_tone)
t22k_off = 0;
/* reset */
tda10086_write_byte(state, 0x00, 0x00);
msleep(10);
/* misc setup */
tda10086_write_byte(state, 0x01, 0x94);
tda10086_write_byte(state, 0x02, 0x35); /* NOTE: TT drivers appear to disable CSWP */
tda10086_write_byte(state, 0x03, 0xe4);
tda10086_write_byte(state, 0x04, 0x43);
tda10086_write_byte(state, 0x0c, 0x0c);
tda10086_write_byte(state, 0x1b, 0xb0); /* noise threshold */
tda10086_write_byte(state, 0x20, 0x89); /* misc */
tda10086_write_byte(state, 0x30, 0x04); /* acquisition period length */
tda10086_write_byte(state, 0x32, 0x00); /* irq off */
tda10086_write_byte(state, 0x31, 0x56); /* setup AFC */
/* setup PLL (this assumes SACLK = 96MHz) */
tda10086_write_byte(state, 0x55, 0x2c); /* misc PLL setup */
if (state->config->xtal_freq == TDA10086_XTAL_16M) {
tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */
tda10086_write_byte(state, 0x3b, 0x01); /* P=2 */
} else {
tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */
tda10086_write_byte(state, 0x3b, 0x00); /* P=1 */
}
tda10086_write_mask(state, 0x55, 0x20, 0x00); /* powerup PLL */
/* setup TS interface */
tda10086_write_byte(state, 0x11, 0x81);
tda10086_write_byte(state, 0x12, 0x81);
tda10086_write_byte(state, 0x19, 0x40); /* parallel mode A + MSBFIRST */
tda10086_write_byte(state, 0x56, 0x80); /* powerdown WPLL - unused in the mode we use */
tda10086_write_byte(state, 0x57, 0x08); /* bypass WPLL - unused in the mode we use */
tda10086_write_byte(state, 0x10, 0x2a);
/* setup ADC */
tda10086_write_byte(state, 0x58, 0x61); /* ADC setup */
tda10086_write_mask(state, 0x58, 0x01, 0x00); /* powerup ADC */
/* setup AGC */
tda10086_write_byte(state, 0x05, 0x0B);
tda10086_write_byte(state, 0x37, 0x63);
tda10086_write_byte(state, 0x3f, 0x0a); /* NOTE: flydvb varies it */
tda10086_write_byte(state, 0x40, 0x64);
tda10086_write_byte(state, 0x41, 0x4f);
tda10086_write_byte(state, 0x42, 0x43);
/* setup viterbi */
tda10086_write_byte(state, 0x1a, 0x11); /* VBER 10^6, DVB, QPSK */
/* setup carrier recovery */
tda10086_write_byte(state, 0x3d, 0x80);
/* setup SEC */
tda10086_write_byte(state, 0x36, t22k_off); /* all SEC off, 22k tone */
tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000)));
tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8);
return 0;
}
static void tda10086_diseqc_wait(struct tda10086_state *state)
{
unsigned long timeout = jiffies + msecs_to_jiffies(200);
while (!(tda10086_read_byte(state, 0x50) & 0x01)) {
if(time_after(jiffies, timeout)) {
printk("%s: diseqc queue not ready, command may be lost.\n", __func__);
break;
}
msleep(10);
}
}
static int tda10086_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 t22k_off = 0x80;
dprintk ("%s\n", __func__);
if (state->config->diseqc_tone)
t22k_off = 0;
switch (tone) {
case SEC_TONE_OFF:
tda10086_write_byte(state, 0x36, t22k_off);
break;
case SEC_TONE_ON:
tda10086_write_byte(state, 0x36, 0x01 + t22k_off);
break;
}
return 0;
}
static int tda10086_send_master_cmd (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd* cmd)
{
struct tda10086_state* state = fe->demodulator_priv;
int i;
u8 oldval;
u8 t22k_off = 0x80;
dprintk ("%s\n", __func__);
if (state->config->diseqc_tone)
t22k_off = 0;
if (cmd->msg_len > 6)
return -EINVAL;
oldval = tda10086_read_byte(state, 0x36);
for(i=0; i< cmd->msg_len; i++) {
tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
}
tda10086_write_byte(state, 0x36, (0x08 + t22k_off)
| ((cmd->msg_len - 1) << 4));
tda10086_diseqc_wait(state);
tda10086_write_byte(state, 0x36, oldval);
return 0;
}
static int tda10086_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd minicmd)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 oldval = tda10086_read_byte(state, 0x36);
u8 t22k_off = 0x80;
dprintk ("%s\n", __func__);
if (state->config->diseqc_tone)
t22k_off = 0;
switch(minicmd) {
case SEC_MINI_A:
tda10086_write_byte(state, 0x36, 0x04 + t22k_off);
break;
case SEC_MINI_B:
tda10086_write_byte(state, 0x36, 0x06 + t22k_off);
break;
}
tda10086_diseqc_wait(state);
tda10086_write_byte(state, 0x36, oldval);
return 0;
}
static int tda10086_set_inversion(struct tda10086_state *state,
struct dtv_frontend_properties *fe_params)
{
u8 invval = 0x80;
dprintk ("%s %i %i\n", __func__, fe_params->inversion, state->config->invert);
switch(fe_params->inversion) {
case INVERSION_OFF:
if (state->config->invert)
invval = 0x40;
break;
case INVERSION_ON:
if (!state->config->invert)
invval = 0x40;
break;
case INVERSION_AUTO:
invval = 0x00;
break;
}
tda10086_write_mask(state, 0x0c, 0xc0, invval);
return 0;
}
static int tda10086_set_symbol_rate(struct tda10086_state *state,
struct dtv_frontend_properties *fe_params)
{
u8 dfn = 0;
u8 afs = 0;
u8 byp = 0;
u8 reg37 = 0x43;
u8 reg42 = 0x43;
u64 big;
u32 tmp;
u32 bdr;
u32 bdri;
u32 symbol_rate = fe_params->symbol_rate;
dprintk ("%s %i\n", __func__, symbol_rate);
/* setup the decimation and anti-aliasing filters.. */
if (symbol_rate < SACLK / 10000 * 137) {
dfn=4;
afs=1;
} else if (symbol_rate < SACLK / 10000 * 208) {
dfn=4;
afs=0;
} else if (symbol_rate < SACLK / 10000 * 270) {
dfn=3;
afs=1;
} else if (symbol_rate < SACLK / 10000 * 416) {
dfn=3;
afs=0;
} else if (symbol_rate < SACLK / 10000 * 550) {
dfn=2;
afs=1;
} else if (symbol_rate < SACLK / 10000 * 833) {
dfn=2;
afs=0;
} else if (symbol_rate < SACLK / 10000 * 1100) {
dfn=1;
afs=1;
} else if (symbol_rate < SACLK / 10000 * 1666) {
dfn=1;
afs=0;
} else if (symbol_rate < SACLK / 10000 * 2200) {
dfn=0;
afs=1;
} else if (symbol_rate < SACLK / 10000 * 3333) {
dfn=0;
afs=0;
} else {
reg37 = 0x63;
reg42 = 0x4f;
byp=1;
}
/* calculate BDR */
big = (1ULL<<21) * ((u64) symbol_rate/1000ULL) * (1ULL<<dfn);
big += ((SACLK/1000ULL)-1ULL);
do_div(big, (SACLK/1000ULL));
bdr = big & 0xfffff;
/* calculate BDRI */
tmp = (1<<dfn)*(symbol_rate/1000);
bdri = ((32 * (SACLK/1000)) + (tmp-1)) / tmp;
tda10086_write_byte(state, 0x21, (afs << 7) | dfn);
tda10086_write_mask(state, 0x20, 0x08, byp << 3);
tda10086_write_byte(state, 0x06, bdr);
tda10086_write_byte(state, 0x07, bdr >> 8);
tda10086_write_byte(state, 0x08, bdr >> 16);
tda10086_write_byte(state, 0x09, bdri);
tda10086_write_byte(state, 0x37, reg37);
tda10086_write_byte(state, 0x42, reg42);
return 0;
}
static int tda10086_set_fec(struct tda10086_state *state,
struct dtv_frontend_properties *fe_params)
{
u8 fecval;
dprintk("%s %i\n", __func__, fe_params->fec_inner);
switch (fe_params->fec_inner) {
case FEC_1_2:
fecval = 0x00;
break;
case FEC_2_3:
fecval = 0x01;
break;
case FEC_3_4:
fecval = 0x02;
break;
case FEC_4_5:
fecval = 0x03;
break;
case FEC_5_6:
fecval = 0x04;
break;
case FEC_6_7:
fecval = 0x05;
break;
case FEC_7_8:
fecval = 0x06;
break;
case FEC_8_9:
fecval = 0x07;
break;
case FEC_AUTO:
fecval = 0x08;
break;
default:
return -1;
}
tda10086_write_byte(state, 0x0d, fecval);
return 0;
}
static int tda10086_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
struct tda10086_state *state = fe->demodulator_priv;
int ret;
u32 freq = 0;
int freqoff;
dprintk ("%s\n", __func__);
/* modify parameters for tuning */
tda10086_write_byte(state, 0x02, 0x35);
state->has_lock = false;
/* set params */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (fe->ops.tuner_ops.get_frequency)
fe->ops.tuner_ops.get_frequency(fe, &freq);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
/* calculate the frequency offset (in *Hz* not kHz) */
freqoff = fe_params->frequency - freq;
freqoff = ((1<<16) * freqoff) / (SACLK/1000);
tda10086_write_byte(state, 0x3d, 0x80 | ((freqoff >> 8) & 0x7f));
tda10086_write_byte(state, 0x3e, freqoff);
if ((ret = tda10086_set_inversion(state, fe_params)) < 0)
return ret;
if ((ret = tda10086_set_symbol_rate(state, fe_params)) < 0)
return ret;
if ((ret = tda10086_set_fec(state, fe_params)) < 0)
return ret;
/* soft reset + disable TS output until lock */
tda10086_write_mask(state, 0x10, 0x40, 0x40);
tda10086_write_mask(state, 0x00, 0x01, 0x00);
state->symbol_rate = fe_params->symbol_rate;
state->frequency = fe_params->frequency;
return 0;
}
static int tda10086_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *fe_params)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 val;
int tmp;
u64 tmp64;
dprintk ("%s\n", __func__);
/* check for invalid symbol rate */
if (fe_params->symbol_rate < 500000)
return -EINVAL;
/* calculate the updated frequency (note: we convert from Hz->kHz) */
tmp64 = ((u64)tda10086_read_byte(state, 0x52)
| (tda10086_read_byte(state, 0x51) << 8));
if (tmp64 & 0x8000)
tmp64 |= 0xffffffffffff0000ULL;
tmp64 = (tmp64 * (SACLK/1000ULL));
do_div(tmp64, (1ULL<<15) * (1ULL<<1));
fe_params->frequency = (int) state->frequency + (int) tmp64;
/* the inversion */
val = tda10086_read_byte(state, 0x0c);
if (val & 0x80) {
switch(val & 0x40) {
case 0x00:
fe_params->inversion = INVERSION_OFF;
if (state->config->invert)
fe_params->inversion = INVERSION_ON;
break;
default:
fe_params->inversion = INVERSION_ON;
if (state->config->invert)
fe_params->inversion = INVERSION_OFF;
break;
}
} else {
tda10086_read_byte(state, 0x0f);
switch(val & 0x02) {
case 0x00:
fe_params->inversion = INVERSION_OFF;
if (state->config->invert)
fe_params->inversion = INVERSION_ON;
break;
default:
fe_params->inversion = INVERSION_ON;
if (state->config->invert)
fe_params->inversion = INVERSION_OFF;
break;
}
}
/* calculate the updated symbol rate */
tmp = tda10086_read_byte(state, 0x1d);
if (tmp & 0x80)
tmp |= 0xffffff00;
tmp = (tmp * 480 * (1<<1)) / 128;
tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000);
fe_params->symbol_rate = state->symbol_rate + tmp;
/* the FEC */
val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4;
switch(val) {
case 0x00:
fe_params->fec_inner = FEC_1_2;
break;
case 0x01:
fe_params->fec_inner = FEC_2_3;
break;
case 0x02:
fe_params->fec_inner = FEC_3_4;
break;
case 0x03:
fe_params->fec_inner = FEC_4_5;
break;
case 0x04:
fe_params->fec_inner = FEC_5_6;
break;
case 0x05:
fe_params->fec_inner = FEC_6_7;
break;
case 0x06:
fe_params->fec_inner = FEC_7_8;
break;
case 0x07:
fe_params->fec_inner = FEC_8_9;
break;
}
return 0;
}
static int tda10086_read_status(struct dvb_frontend *fe,
enum fe_status *fe_status)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 val;
dprintk ("%s\n", __func__);
val = tda10086_read_byte(state, 0x0e);
*fe_status = 0;
if (val & 0x01)
*fe_status |= FE_HAS_SIGNAL;
if (val & 0x02)
*fe_status |= FE_HAS_CARRIER;
if (val & 0x04)
*fe_status |= FE_HAS_VITERBI;
if (val & 0x08)
*fe_status |= FE_HAS_SYNC;
if (val & 0x10) {
*fe_status |= FE_HAS_LOCK;
if (!state->has_lock) {
state->has_lock = true;
/* modify parameters for stable reception */
tda10086_write_byte(state, 0x02, 0x00);
}
}
return 0;
}
static int tda10086_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 _str;
dprintk ("%s\n", __func__);
_str = 0xff - tda10086_read_byte(state, 0x43);
*signal = (_str << 8) | _str;
return 0;
}
static int tda10086_read_snr(struct dvb_frontend* fe, u16 * snr)
{
struct tda10086_state* state = fe->demodulator_priv;
u8 _snr;
dprintk ("%s\n", __func__);
_snr = 0xff - tda10086_read_byte(state, 0x1c);
*snr = (_snr << 8) | _snr;
return 0;
}
static int tda10086_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda10086_state* state = fe->demodulator_priv;
dprintk ("%s\n", __func__);
/* read it */
*ucblocks = tda10086_read_byte(state, 0x18) & 0x7f;
/* reset counter */
tda10086_write_byte(state, 0x18, 0x00);
tda10086_write_byte(state, 0x18, 0x80);
return 0;
}
static int tda10086_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda10086_state* state = fe->demodulator_priv;
dprintk ("%s\n", __func__);
/* read it */
*ber = 0;
*ber |= tda10086_read_byte(state, 0x15);
*ber |= tda10086_read_byte(state, 0x16) << 8;
*ber |= (tda10086_read_byte(state, 0x17) & 0xf) << 16;
return 0;
}
static int tda10086_sleep(struct dvb_frontend* fe)
{
struct tda10086_state* state = fe->demodulator_priv;
dprintk ("%s\n", __func__);
tda10086_write_mask(state, 0x00, 0x08, 0x08);
return 0;
}
static int tda10086_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct tda10086_state* state = fe->demodulator_priv;
dprintk ("%s\n", __func__);
if (enable) {
tda10086_write_mask(state, 0x00, 0x10, 0x10);
} else {
tda10086_write_mask(state, 0x00, 0x10, 0x00);
}
return 0;
}
static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->symbol_rate > 20000000) {
fesettings->min_delay_ms = 50;
fesettings->step_size = 2000;
fesettings->max_drift = 8000;
} else if (p->symbol_rate > 12000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 1500;
fesettings->max_drift = 9000;
} else if (p->symbol_rate > 8000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 1000;
fesettings->max_drift = 8000;
} else if (p->symbol_rate > 4000000) {
fesettings->min_delay_ms = 100;
fesettings->step_size = 500;
fesettings->max_drift = 7000;
} else if (p->symbol_rate > 2000000) {
fesettings->min_delay_ms = 200;
fesettings->step_size = p->symbol_rate / 8000;
fesettings->max_drift = 14 * fesettings->step_size;
} else {
fesettings->min_delay_ms = 200;
fesettings->step_size = p->symbol_rate / 8000;
fesettings->max_drift = 18 * fesettings->step_size;
}
return 0;
}
static void tda10086_release(struct dvb_frontend* fe)
{
struct tda10086_state *state = fe->demodulator_priv;
tda10086_sleep(fe);
kfree(state);
}
static const struct dvb_frontend_ops tda10086_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Philips TDA10086 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 125 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK
},
.release = tda10086_release,
.init = tda10086_init,
.sleep = tda10086_sleep,
.i2c_gate_ctrl = tda10086_i2c_gate_ctrl,
.set_frontend = tda10086_set_frontend,
.get_frontend = tda10086_get_frontend,
.get_tune_settings = tda10086_get_tune_settings,
.read_status = tda10086_read_status,
.read_ber = tda10086_read_ber,
.read_signal_strength = tda10086_read_signal_strength,
.read_snr = tda10086_read_snr,
.read_ucblocks = tda10086_read_ucblocks,
.diseqc_send_master_cmd = tda10086_send_master_cmd,
.diseqc_send_burst = tda10086_send_burst,
.set_tone = tda10086_set_tone,
};
struct dvb_frontend* tda10086_attach(const struct tda10086_config* config,
struct i2c_adapter* i2c)
{
struct tda10086_state *state;
dprintk ("%s\n", __func__);
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda10086_state), GFP_KERNEL);
if (!state)
return NULL;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if (tda10086_read_byte(state, 0x1e) != 0xe1) {
kfree(state);
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10086_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator");
MODULE_AUTHOR("Andrew de Quincey");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(tda10086_attach);
| linux-master | drivers/media/dvb-frontends/tda10086.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for Philips tda1004xh OFDM Demodulator
(c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
*/
/*
* This driver needs external firmware. Please use the commands
* "<kerneldir>/scripts/get_dvb_firmware tda10045",
* "<kerneldir>/scripts/get_dvb_firmware tda10046" to
* download/extract them, and then copy them to /usr/lib/hotplug/firmware
* or /lib/firmware (depending on configuration of firmware hotplug).
*/
#define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
#define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "tda1004x.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda1004x: " args); \
} while (0)
#define TDA1004X_CHIPID 0x00
#define TDA1004X_AUTO 0x01
#define TDA1004X_IN_CONF1 0x02
#define TDA1004X_IN_CONF2 0x03
#define TDA1004X_OUT_CONF1 0x04
#define TDA1004X_OUT_CONF2 0x05
#define TDA1004X_STATUS_CD 0x06
#define TDA1004X_CONFC4 0x07
#define TDA1004X_DSSPARE2 0x0C
#define TDA10045H_CODE_IN 0x0D
#define TDA10045H_FWPAGE 0x0E
#define TDA1004X_SCAN_CPT 0x10
#define TDA1004X_DSP_CMD 0x11
#define TDA1004X_DSP_ARG 0x12
#define TDA1004X_DSP_DATA1 0x13
#define TDA1004X_DSP_DATA2 0x14
#define TDA1004X_CONFADC1 0x15
#define TDA1004X_CONFC1 0x16
#define TDA10045H_S_AGC 0x1a
#define TDA10046H_AGC_TUN_LEVEL 0x1a
#define TDA1004X_SNR 0x1c
#define TDA1004X_CONF_TS1 0x1e
#define TDA1004X_CONF_TS2 0x1f
#define TDA1004X_CBER_RESET 0x20
#define TDA1004X_CBER_MSB 0x21
#define TDA1004X_CBER_LSB 0x22
#define TDA1004X_CVBER_LUT 0x23
#define TDA1004X_VBER_MSB 0x24
#define TDA1004X_VBER_MID 0x25
#define TDA1004X_VBER_LSB 0x26
#define TDA1004X_UNCOR 0x27
#define TDA10045H_CONFPLL_P 0x2D
#define TDA10045H_CONFPLL_M_MSB 0x2E
#define TDA10045H_CONFPLL_M_LSB 0x2F
#define TDA10045H_CONFPLL_N 0x30
#define TDA10046H_CONFPLL1 0x2D
#define TDA10046H_CONFPLL2 0x2F
#define TDA10046H_CONFPLL3 0x30
#define TDA10046H_TIME_WREF1 0x31
#define TDA10046H_TIME_WREF2 0x32
#define TDA10046H_TIME_WREF3 0x33
#define TDA10046H_TIME_WREF4 0x34
#define TDA10046H_TIME_WREF5 0x35
#define TDA10045H_UNSURW_MSB 0x31
#define TDA10045H_UNSURW_LSB 0x32
#define TDA10045H_WREF_MSB 0x33
#define TDA10045H_WREF_MID 0x34
#define TDA10045H_WREF_LSB 0x35
#define TDA10045H_MUXOUT 0x36
#define TDA1004X_CONFADC2 0x37
#define TDA10045H_IOFFSET 0x38
#define TDA10046H_CONF_TRISTATE1 0x3B
#define TDA10046H_CONF_TRISTATE2 0x3C
#define TDA10046H_CONF_POLARITY 0x3D
#define TDA10046H_FREQ_OFFSET 0x3E
#define TDA10046H_GPIO_OUT_SEL 0x41
#define TDA10046H_GPIO_SELECT 0x42
#define TDA10046H_AGC_CONF 0x43
#define TDA10046H_AGC_THR 0x44
#define TDA10046H_AGC_RENORM 0x45
#define TDA10046H_AGC_GAINS 0x46
#define TDA10046H_AGC_TUN_MIN 0x47
#define TDA10046H_AGC_TUN_MAX 0x48
#define TDA10046H_AGC_IF_MIN 0x49
#define TDA10046H_AGC_IF_MAX 0x4A
#define TDA10046H_FREQ_PHY2_MSB 0x4D
#define TDA10046H_FREQ_PHY2_LSB 0x4E
#define TDA10046H_CVBER_CTRL 0x4F
#define TDA10046H_AGC_IF_LEVEL 0x52
#define TDA10046H_CODE_CPT 0x57
#define TDA10046H_CODE_IN 0x58
static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
msg.addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
__func__, reg, data, ret);
dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
{ .flags = I2C_M_RD, .buf = b1, .len = 1 }};
dprintk("%s: reg=0x%x\n", __func__, reg);
msg[0].addr = state->config->demod_address;
msg[1].addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
ret);
return -EINVAL;
}
dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
reg, b1[0], ret);
return b1[0];
}
static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
{
int val;
dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
mask, data);
// read a byte and check
val = tda1004x_read_byte(state, reg);
if (val < 0)
return val;
// mask if off
val = val & ~mask;
val |= data & 0xff;
// write it out again
return tda1004x_write_byteI(state, reg, val);
}
static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
{
int i;
int result;
dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
result = 0;
for (i = 0; i < len; i++) {
result = tda1004x_write_byteI(state, reg + i, buf[i]);
if (result != 0)
break;
}
return result;
}
static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
{
int result;
dprintk("%s\n", __func__);
result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
msleep(20);
return result;
}
static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
{
dprintk("%s\n", __func__);
return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
}
static int tda10045h_set_bandwidth(struct tda1004x_state *state,
u32 bandwidth)
{
static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
switch (bandwidth) {
case 6000000:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
break;
case 7000000:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
break;
case 8000000:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
break;
default:
return -EINVAL;
}
tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
return 0;
}
static int tda10046h_set_bandwidth(struct tda1004x_state *state,
u32 bandwidth)
{
static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
int tda10046_clk53m;
if ((state->config->if_freq == TDA10046_FREQ_045) ||
(state->config->if_freq == TDA10046_FREQ_052))
tda10046_clk53m = 0;
else
tda10046_clk53m = 1;
switch (bandwidth) {
case 6000000:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
sizeof(bandwidth_6mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
sizeof(bandwidth_6mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
}
break;
case 7000000:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
sizeof(bandwidth_7mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
sizeof(bandwidth_7mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
}
break;
case 8000000:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
sizeof(bandwidth_8mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
sizeof(bandwidth_8mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int tda1004x_do_upload(struct tda1004x_state *state,
const unsigned char *mem, unsigned int len,
u8 dspCodeCounterReg, u8 dspCodeInReg)
{
u8 buf[65];
struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
int tx_size;
int pos = 0;
/* clear code counter */
tda1004x_write_byteI(state, dspCodeCounterReg, 0);
fw_msg.addr = state->config->demod_address;
i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
buf[0] = dspCodeInReg;
while (pos != len) {
// work out how much to send this time
tx_size = len - pos;
if (tx_size > 0x10)
tx_size = 0x10;
// send the chunk
memcpy(buf + 1, mem + pos, tx_size);
fw_msg.len = tx_size + 1;
if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
printk(KERN_ERR "tda1004x: Error during firmware upload\n");
i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
return -EIO;
}
pos += tx_size;
dprintk("%s: fw_pos=0x%x\n", __func__, pos);
}
i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
/* give the DSP a chance to settle 03/10/05 Hac */
msleep(100);
return 0;
}
static int tda1004x_check_upload_ok(struct tda1004x_state *state)
{
u8 data1, data2;
unsigned long timeout;
if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
timeout = jiffies + 2 * HZ;
while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
if (time_after(jiffies, timeout)) {
printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
break;
}
msleep(1);
}
} else
msleep(100);
// check upload was OK
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
return -EIO;
}
printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
return 0;
}
static int tda10045_fwupload(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int ret;
const struct firmware *fw;
/* don't re-upload unless necessary */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/* request the firmware, this will block until someone uploads it */
printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
if (ret) {
printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
return ret;
}
/* reset chip */
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
msleep(10);
/* set parameters */
tda10045h_set_bandwidth(state, 8000000);
ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
release_firmware(fw);
if (ret)
return ret;
printk(KERN_INFO "tda1004x: firmware upload complete\n");
/* wait for DSP to initialise */
/* DSPREADY doesn't seem to work on the TDA10045H */
msleep(100);
return tda1004x_check_upload_ok(state);
}
static void tda10046_init_plls(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tda10046_clk53m;
if ((state->config->if_freq == TDA10046_FREQ_045) ||
(state->config->if_freq == TDA10046_FREQ_052))
tda10046_clk53m = 0;
else
tda10046_clk53m = 1;
tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
if(tda10046_clk53m) {
printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
} else {
printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
}
if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
} else {
dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
}
if(tda10046_clk53m)
tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
else
tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
/* Note clock frequency is handled implicitly */
switch (state->config->if_freq) {
case TDA10046_FREQ_045:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
break;
case TDA10046_FREQ_052:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
break;
case TDA10046_FREQ_3617:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
break;
case TDA10046_FREQ_3613:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
break;
}
tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
/* let the PLLs settle */
msleep(120);
}
static int tda10046_fwupload(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int ret, confc4;
const struct firmware *fw;
/* reset + wake up chip */
if (state->config->xtal_freq == TDA10046_XTAL_4M) {
confc4 = 0;
} else {
dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
confc4 = 0x80;
}
tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
/* set GPIO 1 and 3 */
if (state->config->gpio_config != TDA10046_GPTRI) {
tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
}
/* let the clocks recover from sleep */
msleep(10);
/* The PLLs need to be reprogrammed after sleep */
tda10046_init_plls(fe);
tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
/* don't re-upload unless necessary */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/*
For i2c normal work, we need to slow down the bus speed.
However, the slow down breaks the eeprom firmware load.
So, use normal speed for eeprom booting and then restore the
i2c speed after that. Tested with MSI TV @nyware A/D board,
that comes with firmware version 29 inside their eeprom.
It should also be noticed that no other I2C transfer should
be in course while booting from eeprom, otherwise, tda10046
goes into an instable state. So, proper locking are needed
at the i2c bus master.
*/
printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
msleep(300);
tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
/* Checks if eeprom firmware went without troubles */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/* eeprom firmware didn't work. Load one manually. */
if (state->config->request_firmware != NULL) {
/* request the firmware, this will block until someone uploads it */
printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
if (ret) {
/* remain compatible to old bug: try to load with tda10045 image name */
ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
if (ret) {
printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
return ret;
} else {
printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
TDA10046_DEFAULT_FIRMWARE);
}
}
} else {
printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
return -EIO;
}
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
release_firmware(fw);
return tda1004x_check_upload_ok(state);
}
static int tda1004x_encode_fec(int fec)
{
// convert known FEC values
switch (fec) {
case FEC_1_2:
return 0;
case FEC_2_3:
return 1;
case FEC_3_4:
return 2;
case FEC_5_6:
return 3;
case FEC_7_8:
return 4;
}
// unsupported
return -EINVAL;
}
static int tda1004x_decode_fec(int tdafec)
{
// convert known FEC values
switch (tdafec) {
case 0:
return FEC_1_2;
case 1:
return FEC_2_3;
case 2:
return FEC_3_4;
case 3:
return FEC_5_6;
case 4:
return FEC_7_8;
}
// unsupported
return -1;
}
static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
{
struct tda1004x_state* state = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return tda1004x_write_byteI(state, buf[0], buf[1]);
}
static int tda10045_init(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (tda10045_fwupload(fe)) {
printk("tda1004x: firmware upload failed\n");
return -EIO;
}
tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
// tda setup
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
return 0;
}
static int tda10046_init(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (tda10046_fwupload(fe)) {
printk("tda1004x: firmware upload failed\n");
return -EIO;
}
// tda setup
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
switch (state->config->agc_config) {
case TDA10046_AGC_DEFAULT:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
case TDA10046_AGC_IFO_AUTO_NEG:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
case TDA10046_AGC_IFO_AUTO_POS:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
break;
case TDA10046_AGC_TDA827X:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
}
if (state->config->ts_mode == 0) {
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
} else {
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
state->config->invert_oclk << 4);
}
tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
// tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
return 0;
}
static int tda1004x_set_fe(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int inversion;
dprintk("%s\n", __func__);
if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
// setup auto offset
tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
// disable agc_conf[2]
tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
}
// set frequency
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
// Hardcoded to use auto as much as possible on the TDA10045 as it
// is very unreliable if AUTO mode is _not_ used.
if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
fe_params->code_rate_HP = FEC_AUTO;
fe_params->guard_interval = GUARD_INTERVAL_AUTO;
fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
}
// Set standard params.. or put them to auto
if ((fe_params->code_rate_HP == FEC_AUTO) ||
(fe_params->code_rate_LP == FEC_AUTO) ||
(fe_params->modulation == QAM_AUTO) ||
(fe_params->hierarchy == HIERARCHY_AUTO)) {
tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
} else {
tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
// set HP FEC
tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
if (tmp < 0)
return tmp;
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
// set LP FEC
tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
if (tmp < 0)
return tmp;
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
/* set modulation */
switch (fe_params->modulation) {
case QPSK:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
break;
case QAM_16:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
break;
case QAM_64:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
break;
default:
return -EINVAL;
}
// set hierarchy
switch (fe_params->hierarchy) {
case HIERARCHY_NONE:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
break;
case HIERARCHY_1:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
break;
case HIERARCHY_2:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
break;
case HIERARCHY_4:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
break;
default:
return -EINVAL;
}
}
// set bandwidth
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
break;
case TDA1004X_DEMOD_TDA10046:
tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
break;
}
// set inversion
inversion = fe_params->inversion;
if (state->config->invert)
inversion = inversion ? INVERSION_OFF : INVERSION_ON;
switch (inversion) {
case INVERSION_OFF:
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
break;
case INVERSION_ON:
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
break;
default:
return -EINVAL;
}
// set guard interval
switch (fe_params->guard_interval) {
case GUARD_INTERVAL_1_32:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
break;
case GUARD_INTERVAL_1_16:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
break;
case GUARD_INTERVAL_1_8:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
break;
case GUARD_INTERVAL_1_4:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
break;
case GUARD_INTERVAL_AUTO:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
break;
default:
return -EINVAL;
}
// set transmission mode
switch (fe_params->transmission_mode) {
case TRANSMISSION_MODE_2K:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
break;
case TRANSMISSION_MODE_8K:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
break;
case TRANSMISSION_MODE_AUTO:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
break;
default:
return -EINVAL;
}
// start the lock
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
break;
case TDA1004X_DEMOD_TDA10046:
tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
msleep(1);
tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
break;
}
msleep(10);
return 0;
}
static int tda1004x_get_fe(struct dvb_frontend *fe,
struct dtv_frontend_properties *fe_params)
{
struct tda1004x_state* state = fe->demodulator_priv;
int status;
dprintk("%s\n", __func__);
status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
if (status == -1)
return -EIO;
/* Only update the properties cache if device is locked */
if (!(status & 8))
return 0;
// inversion status
fe_params->inversion = INVERSION_OFF;
if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
fe_params->inversion = INVERSION_ON;
if (state->config->invert)
fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
// bandwidth
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
case 0x14:
fe_params->bandwidth_hz = 8000000;
break;
case 0xdb:
fe_params->bandwidth_hz = 7000000;
break;
case 0x4f:
fe_params->bandwidth_hz = 6000000;
break;
}
break;
case TDA1004X_DEMOD_TDA10046:
switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
case 0x5c:
case 0x54:
fe_params->bandwidth_hz = 8000000;
break;
case 0x6a:
case 0x60:
fe_params->bandwidth_hz = 7000000;
break;
case 0x7b:
case 0x70:
fe_params->bandwidth_hz = 6000000;
break;
}
break;
}
// FEC
fe_params->code_rate_HP =
tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
fe_params->code_rate_LP =
tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
/* modulation */
switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
case 0:
fe_params->modulation = QPSK;
break;
case 1:
fe_params->modulation = QAM_16;
break;
case 2:
fe_params->modulation = QAM_64;
break;
}
// transmission mode
fe_params->transmission_mode = TRANSMISSION_MODE_2K;
if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
fe_params->transmission_mode = TRANSMISSION_MODE_8K;
// guard interval
switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
case 0:
fe_params->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
fe_params->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
fe_params->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
fe_params->guard_interval = GUARD_INTERVAL_1_4;
break;
}
// hierarchy
switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
case 0:
fe_params->hierarchy = HIERARCHY_NONE;
break;
case 1:
fe_params->hierarchy = HIERARCHY_1;
break;
case 2:
fe_params->hierarchy = HIERARCHY_2;
break;
case 3:
fe_params->hierarchy = HIERARCHY_4;
break;
}
return 0;
}
static int tda1004x_read_status(struct dvb_frontend *fe,
enum fe_status *fe_status)
{
struct tda1004x_state* state = fe->demodulator_priv;
int status;
int cber;
int vber;
dprintk("%s\n", __func__);
// read status
status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
if (status == -1)
return -EIO;
// decode
*fe_status = 0;
if (status & 4)
*fe_status |= FE_HAS_SIGNAL;
if (status & 2)
*fe_status |= FE_HAS_CARRIER;
if (status & 8)
*fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
// if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
// is getting anything valid
if (!(*fe_status & FE_HAS_VITERBI)) {
// read the CBER
cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
if (cber == -1)
return -EIO;
status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
if (status == -1)
return -EIO;
cber |= (status << 8);
// The address 0x20 should be read to cope with a TDA10046 bug
tda1004x_read_byte(state, TDA1004X_CBER_RESET);
if (cber != 65535)
*fe_status |= FE_HAS_VITERBI;
}
// if we DO have some valid VITERBI output, but don't already have SYNC
// bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
// read the VBER
vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
if (vber == -1)
return -EIO;
status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
if (status == -1)
return -EIO;
vber |= (status << 8);
status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
if (status == -1)
return -EIO;
vber |= (status & 0x0f) << 16;
// The CVBER_LUT should be read to cope with TDA10046 hardware bug
tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
// if RS has passed some valid TS packets, then we must be
// getting some SYNC bytes
if (vber < 16632)
*fe_status |= FE_HAS_SYNC;
}
// success
dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
return 0;
}
static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int reg = 0;
dprintk("%s\n", __func__);
// determine the register to use
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
reg = TDA10045H_S_AGC;
break;
case TDA1004X_DEMOD_TDA10046:
reg = TDA10046H_AGC_IF_LEVEL;
break;
}
// read it
tmp = tda1004x_read_byte(state, reg);
if (tmp < 0)
return -EIO;
*signal = (tmp << 8) | tmp;
dprintk("%s: signal=0x%x\n", __func__, *signal);
return 0;
}
static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
dprintk("%s\n", __func__);
// read it
tmp = tda1004x_read_byte(state, TDA1004X_SNR);
if (tmp < 0)
return -EIO;
tmp = 255 - tmp;
*snr = ((tmp << 8) | tmp);
dprintk("%s: snr=0x%x\n", __func__, *snr);
return 0;
}
static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int tmp2;
int counter;
dprintk("%s\n", __func__);
// read the UCBLOCKS and reset
counter = 0;
tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
if (tmp < 0)
return -EIO;
tmp &= 0x7f;
while (counter++ < 5) {
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
if (tmp2 < 0)
return -EIO;
tmp2 &= 0x7f;
if ((tmp2 < tmp) || (tmp2 == 0))
break;
}
if (tmp != 0x7f)
*ucblocks = tmp;
else
*ucblocks = 0xffffffff;
dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
return 0;
}
static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
dprintk("%s\n", __func__);
// read it in
tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
if (tmp < 0)
return -EIO;
*ber = tmp << 1;
tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
if (tmp < 0)
return -EIO;
*ber |= (tmp << 9);
// The address 0x20 should be read to cope with a TDA10046 bug
tda1004x_read_byte(state, TDA1004X_CBER_RESET);
dprintk("%s: ber=0x%x\n", __func__, *ber);
return 0;
}
static int tda1004x_sleep(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int gpio_conf;
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
break;
case TDA1004X_DEMOD_TDA10046:
/* set outputs to tristate */
tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
/* invert GPIO 1 and 3 if desired*/
gpio_conf = state->config->gpio_config;
if (gpio_conf >= TDA10046_GP00_I)
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
(gpio_conf & 0x0f) ^ 0x0a);
tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
break;
}
return 0;
}
static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct tda1004x_state* state = fe->demodulator_priv;
if (enable) {
return tda1004x_enable_tuner_i2c(state);
} else {
return tda1004x_disable_tuner_i2c(state);
}
}
static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 800;
/* Drift compensation makes no sense for DVB-T */
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void tda1004x_release(struct dvb_frontend* fe)
{
struct tda1004x_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops tda10045_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Philips TDA10045H DVB-T",
.frequency_min_hz = 51 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 166667,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
},
.release = tda1004x_release,
.init = tda10045_init,
.sleep = tda1004x_sleep,
.write = tda1004x_write,
.i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
.set_frontend = tda1004x_set_fe,
.get_frontend = tda1004x_get_fe,
.get_tune_settings = tda1004x_get_tune_settings,
.read_status = tda1004x_read_status,
.read_ber = tda1004x_read_ber,
.read_signal_strength = tda1004x_read_signal_strength,
.read_snr = tda1004x_read_snr,
.read_ucblocks = tda1004x_read_ucblocks,
};
struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
struct i2c_adapter* i2c)
{
struct tda1004x_state *state;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
if (!state) {
printk(KERN_ERR "Can't allocate memory for tda10045 state\n");
return NULL;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
state->demod_type = TDA1004X_DEMOD_TDA10045;
/* check if the demod is there */
id = tda1004x_read_byte(state, TDA1004X_CHIPID);
if (id < 0) {
printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
kfree(state);
return NULL;
}
if (id != 0x25) {
printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
kfree(state);
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
static const struct dvb_frontend_ops tda10046_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Philips TDA10046H DVB-T",
.frequency_min_hz = 51 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 166667,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
},
.release = tda1004x_release,
.init = tda10046_init,
.sleep = tda1004x_sleep,
.write = tda1004x_write,
.i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
.set_frontend = tda1004x_set_fe,
.get_frontend = tda1004x_get_fe,
.get_tune_settings = tda1004x_get_tune_settings,
.read_status = tda1004x_read_status,
.read_ber = tda1004x_read_ber,
.read_signal_strength = tda1004x_read_signal_strength,
.read_snr = tda1004x_read_snr,
.read_ucblocks = tda1004x_read_ucblocks,
};
struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
struct i2c_adapter* i2c)
{
struct tda1004x_state *state;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
if (!state) {
printk(KERN_ERR "Can't allocate memory for tda10046 state\n");
return NULL;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
state->demod_type = TDA1004X_DEMOD_TDA10046;
/* check if the demod is there */
id = tda1004x_read_byte(state, TDA1004X_CHIPID);
if (id < 0) {
printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
kfree(state);
return NULL;
}
if (id != 0x46) {
printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
kfree(state);
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(tda10045_attach);
EXPORT_SYMBOL_GPL(tda10046_attach);
| linux-master | drivers/media/dvb-frontends/tda1004x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Conexant cx22700 DVB OFDM demodulator driver
Copyright (C) 2001-2002 Convergence Integrated Media GmbH
Holger Waechtler <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "cx22700.h"
struct cx22700_state {
struct i2c_adapter* i2c;
const struct cx22700_config* config;
struct dvb_frontend frontend;
};
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "cx22700: " args); \
} while (0)
static u8 init_tab [] = {
0x04, 0x10,
0x05, 0x09,
0x06, 0x00,
0x08, 0x04,
0x09, 0x00,
0x0a, 0x01,
0x15, 0x40,
0x16, 0x10,
0x17, 0x87,
0x18, 0x17,
0x1a, 0x10,
0x25, 0x04,
0x2e, 0x00,
0x39, 0x00,
0x3a, 0x04,
0x45, 0x08,
0x46, 0x02,
0x47, 0x05,
};
static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data)
{
int ret;
u8 buf [] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
dprintk ("%s\n", __func__);
ret = i2c_transfer (state->i2c, &msg, 1);
if (ret != 1)
printk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static int cx22700_readreg (struct cx22700_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
dprintk ("%s\n", __func__);
ret = i2c_transfer (state->i2c, msg, 2);
if (ret != 2) return -EIO;
return b1[0];
}
static int cx22700_set_inversion (struct cx22700_state* state, int inversion)
{
u8 val;
dprintk ("%s\n", __func__);
switch (inversion) {
case INVERSION_AUTO:
return -EOPNOTSUPP;
case INVERSION_ON:
val = cx22700_readreg (state, 0x09);
return cx22700_writereg (state, 0x09, val | 0x01);
case INVERSION_OFF:
val = cx22700_readreg (state, 0x09);
return cx22700_writereg (state, 0x09, val & 0xfe);
default:
return -EINVAL;
}
}
static int cx22700_set_tps(struct cx22700_state *state,
struct dtv_frontend_properties *p)
{
static const u8 qam_tab [4] = { 0, 1, 0, 2 };
static const u8 fec_tab [6] = { 0, 1, 2, 0, 3, 4 };
u8 val;
dprintk ("%s\n", __func__);
if (p->code_rate_HP < FEC_1_2 || p->code_rate_HP > FEC_7_8)
return -EINVAL;
if (p->code_rate_LP < FEC_1_2 || p->code_rate_LP > FEC_7_8)
return -EINVAL;
if (p->code_rate_HP == FEC_4_5 || p->code_rate_LP == FEC_4_5)
return -EINVAL;
if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
p->guard_interval > GUARD_INTERVAL_1_4)
return -EINVAL;
if (p->transmission_mode != TRANSMISSION_MODE_2K &&
p->transmission_mode != TRANSMISSION_MODE_8K)
return -EINVAL;
if (p->modulation != QPSK &&
p->modulation != QAM_16 &&
p->modulation != QAM_64)
return -EINVAL;
if ((int)p->hierarchy < HIERARCHY_NONE ||
p->hierarchy > HIERARCHY_4)
return -EINVAL;
if (p->bandwidth_hz > 8000000 || p->bandwidth_hz < 6000000)
return -EINVAL;
if (p->bandwidth_hz == 7000000)
cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10));
else
cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10));
val = qam_tab[p->modulation - QPSK];
val |= p->hierarchy - HIERARCHY_NONE;
cx22700_writereg (state, 0x04, val);
if (p->code_rate_HP - FEC_1_2 >= sizeof(fec_tab) ||
p->code_rate_LP - FEC_1_2 >= sizeof(fec_tab))
return -EINVAL;
val = fec_tab[p->code_rate_HP - FEC_1_2] << 3;
val |= fec_tab[p->code_rate_LP - FEC_1_2];
cx22700_writereg (state, 0x05, val);
val = (p->guard_interval - GUARD_INTERVAL_1_32) << 2;
val |= p->transmission_mode - TRANSMISSION_MODE_2K;
cx22700_writereg (state, 0x06, val);
cx22700_writereg (state, 0x08, 0x04 | 0x02); /* use user tps parameters */
cx22700_writereg (state, 0x08, 0x04); /* restart acquisition */
return 0;
}
static int cx22700_get_tps(struct cx22700_state *state,
struct dtv_frontend_properties *p)
{
static const enum fe_modulation qam_tab[3] = { QPSK, QAM_16, QAM_64 };
static const enum fe_code_rate fec_tab[5] = {
FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8
};
u8 val;
dprintk ("%s\n", __func__);
if (!(cx22700_readreg(state, 0x07) & 0x20)) /* tps valid? */
return -EAGAIN;
val = cx22700_readreg (state, 0x01);
if ((val & 0x7) > 4)
p->hierarchy = HIERARCHY_AUTO;
else
p->hierarchy = HIERARCHY_NONE + (val & 0x7);
if (((val >> 3) & 0x3) > 2)
p->modulation = QAM_AUTO;
else
p->modulation = qam_tab[(val >> 3) & 0x3];
val = cx22700_readreg (state, 0x02);
if (((val >> 3) & 0x07) > 4)
p->code_rate_HP = FEC_AUTO;
else
p->code_rate_HP = fec_tab[(val >> 3) & 0x07];
if ((val & 0x07) > 4)
p->code_rate_LP = FEC_AUTO;
else
p->code_rate_LP = fec_tab[val & 0x07];
val = cx22700_readreg (state, 0x03);
p->guard_interval = GUARD_INTERVAL_1_32 + ((val >> 6) & 0x3);
p->transmission_mode = TRANSMISSION_MODE_2K + ((val >> 5) & 0x1);
return 0;
}
static int cx22700_init (struct dvb_frontend* fe)
{ struct cx22700_state* state = fe->demodulator_priv;
int i;
dprintk("cx22700_init: init chip\n");
cx22700_writereg (state, 0x00, 0x02); /* soft reset */
cx22700_writereg (state, 0x00, 0x00);
msleep(10);
for (i=0; i<sizeof(init_tab); i+=2)
cx22700_writereg (state, init_tab[i], init_tab[i+1]);
cx22700_writereg (state, 0x00, 0x01);
return 0;
}
static int cx22700_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx22700_state* state = fe->demodulator_priv;
u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
| (cx22700_readreg (state, 0x0e) << 1);
u8 sync = cx22700_readreg (state, 0x07);
*status = 0;
if (rs_ber < 0xff00)
*status |= FE_HAS_SIGNAL;
if (sync & 0x20)
*status |= FE_HAS_CARRIER;
if (sync & 0x10)
*status |= FE_HAS_VITERBI;
if (sync & 0x10)
*status |= FE_HAS_SYNC;
if (*status == 0x0f)
*status |= FE_HAS_LOCK;
return 0;
}
static int cx22700_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct cx22700_state* state = fe->demodulator_priv;
*ber = cx22700_readreg (state, 0x0c) & 0x7f;
cx22700_writereg (state, 0x0c, 0x00);
return 0;
}
static int cx22700_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
struct cx22700_state* state = fe->demodulator_priv;
u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
| (cx22700_readreg (state, 0x0e) << 1);
*signal_strength = ~rs_ber;
return 0;
}
static int cx22700_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct cx22700_state* state = fe->demodulator_priv;
u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
| (cx22700_readreg (state, 0x0e) << 1);
*snr = ~rs_ber;
return 0;
}
static int cx22700_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct cx22700_state* state = fe->demodulator_priv;
*ucblocks = cx22700_readreg (state, 0x0f);
cx22700_writereg (state, 0x0f, 0x00);
return 0;
}
static int cx22700_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx22700_state* state = fe->demodulator_priv;
cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/
cx22700_writereg (state, 0x00, 0x00);
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
cx22700_set_inversion(state, c->inversion);
cx22700_set_tps(state, c);
cx22700_writereg (state, 0x37, 0x01); /* PAL loop filter off */
cx22700_writereg (state, 0x00, 0x01); /* restart acquire */
return 0;
}
static int cx22700_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cx22700_state* state = fe->demodulator_priv;
u8 reg09 = cx22700_readreg (state, 0x09);
c->inversion = reg09 & 0x1 ? INVERSION_ON : INVERSION_OFF;
return cx22700_get_tps(state, c);
}
static int cx22700_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct cx22700_state* state = fe->demodulator_priv;
if (enable) {
return cx22700_writereg(state, 0x0a, 0x00);
} else {
return cx22700_writereg(state, 0x0a, 0x01);
}
}
static int cx22700_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 150;
fesettings->step_size = 166667;
fesettings->max_drift = 166667*2;
return 0;
}
static void cx22700_release(struct dvb_frontend* fe)
{
struct cx22700_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops cx22700_ops;
struct dvb_frontend* cx22700_attach(const struct cx22700_config* config,
struct i2c_adapter* i2c)
{
struct cx22700_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct cx22700_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
/* check if the demod is there */
if (cx22700_readreg(state, 0x07) < 0) goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx22700_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops cx22700_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Conexant CX22700 DVB-T",
.frequency_min_hz = 470 * MHz,
.frequency_max_hz = 860 * MHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_RECOVER
},
.release = cx22700_release,
.init = cx22700_init,
.i2c_gate_ctrl = cx22700_i2c_gate_ctrl,
.set_frontend = cx22700_set_frontend,
.get_frontend = cx22700_get_frontend,
.get_tune_settings = cx22700_get_tune_settings,
.read_status = cx22700_read_status,
.read_ber = cx22700_read_ber,
.read_signal_strength = cx22700_read_signal_strength,
.read_snr = cx22700_read_snr,
.read_ucblocks = cx22700_read_ucblocks,
};
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Conexant CX22700 DVB-T Demodulator driver");
MODULE_AUTHOR("Holger Waechtler");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(cx22700_attach);
| linux-master | drivers/media/dvb-frontends/cx22700.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
*
* Copyright (c) 2007-8 Patrick Boettcher <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/delay.h>
#include <linux/dvb/frontend.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "itd1000.h"
#include "itd1000_priv.h"
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
#define itd_dbg(args...) do { \
if (debug) { \
printk(KERN_DEBUG "ITD1000: " args);\
} \
} while (0)
#define itd_warn(args...) do { \
printk(KERN_WARNING "ITD1000: " args); \
} while (0)
#define itd_info(args...) do { \
printk(KERN_INFO "ITD1000: " args); \
} while (0)
/* don't write more than one byte with flexcop behind */
static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
{
u8 buf[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
};
if (1 + len > sizeof(buf)) {
printk(KERN_WARNING
"itd1000: i2c wr reg=%04x: len=%d is too big!\n",
reg, len);
return -EINVAL;
}
buf[0] = reg;
memcpy(&buf[1], v, len);
/* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "itd1000 I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
{
u8 val;
struct i2c_msg msg[2] = {
{ .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
{ .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
};
/* ugly flexcop workaround */
itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
if (i2c_transfer(state->i2c, msg, 2) != 2) {
itd_warn("itd1000 I2C read failed\n");
return -EREMOTEIO;
}
return val;
}
static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
{
u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
int ret = itd1000_write_regs(state, r, &tmp, 1);
state->shadow[r] = tmp;
return ret;
}
static struct {
u32 symbol_rate;
u8 pgaext : 4; /* PLLFH */
u8 bbgvmin : 4; /* BBGVMIN */
} itd1000_lpf_pga[] = {
{ 0, 0x8, 0x3 },
{ 5200000, 0x8, 0x3 },
{ 12200000, 0x4, 0x3 },
{ 15400000, 0x2, 0x3 },
{ 19800000, 0x2, 0x3 },
{ 21500000, 0x2, 0x3 },
{ 24500000, 0x2, 0x3 },
{ 28400000, 0x2, 0x3 },
{ 33400000, 0x2, 0x3 },
{ 34400000, 0x1, 0x4 },
{ 34400000, 0x1, 0x4 },
{ 38400000, 0x1, 0x4 },
{ 38400000, 0x1, 0x4 },
{ 40400000, 0x1, 0x4 },
{ 45400000, 0x1, 0x4 },
};
static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
{
u8 i;
u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
u8 bw = itd1000_read_reg(state, BW) & 0xf0;
itd_dbg("symbol_rate = %d\n", symbol_rate);
/* not sure what is that ? - starting to download the table */
itd1000_write_reg(state, CON1, con1 | (1 << 1));
for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
itd1000_write_reg(state, BW, bw | (i & 0x0f));
break;
}
itd1000_write_reg(state, CON1, con1 | (0 << 1));
}
static struct {
u8 vcorg;
u32 fmax_rg;
} itd1000_vcorg[] = {
{ 1, 920000 },
{ 2, 971000 },
{ 3, 1031000 },
{ 4, 1091000 },
{ 5, 1171000 },
{ 6, 1281000 },
{ 7, 1381000 },
{ 8, 500000 }, /* this is intentional. */
{ 9, 1451000 },
{ 10, 1531000 },
{ 11, 1631000 },
{ 12, 1741000 },
{ 13, 1891000 },
{ 14, 2071000 },
{ 15, 2250000 },
};
static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
{
u8 i;
u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
u8 adcout;
/* reserved bit again (reset ?) */
itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
if (freq_khz < itd1000_vcorg[i].fmax_rg) {
itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
msleep(1);
adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
if (adcout > 13) {
if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
} else if (adcout < 2) {
if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
}
break;
}
}
}
static const struct {
u32 freq;
u8 values[10]; /* RFTR, RFST1 - RFST9 */
} itd1000_fre_values[] = {
{ 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
{ 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
{ 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
{ 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
{ 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
{ 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
{ 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
{ 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
{ 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
{ 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
};
#define FREF 16
static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
{
int i, j;
u32 plln, pllf;
u64 tmp;
plln = (freq_khz * 1000) / 2 / FREF;
/* Compute the factional part times 1000 */
tmp = plln % 1000000;
plln /= 1000000;
tmp *= 1048576;
do_div(tmp, 1000000);
pllf = (u32) tmp;
state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
itd1000_write_reg(state, PLLNL, plln & 0xff);
itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
if (freq_khz <= itd1000_fre_values[i].freq) {
itd_dbg("fre_values: %d\n", i);
itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
for (j = 0; j < 9; j++)
itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
break;
}
}
itd1000_set_vco(state, freq_khz);
}
static int itd1000_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct itd1000_state *state = fe->tuner_priv;
u8 pllcon1;
itd1000_set_lo(state, c->frequency);
itd1000_set_lpf_bw(state, c->symbol_rate);
pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
itd1000_write_reg(state, PLLCON1, pllcon1);
return 0;
}
static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct itd1000_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
return 0;
}
static u8 itd1000_init_tab[][2] = {
{ PLLCON1, 0x65 }, /* Register does not change */
{ PLLNH, 0x80 }, /* Bits [7:6] do not change */
{ RESERVED_0X6D, 0x3b },
{ VCO_CHP2_I2C, 0x12 },
{ 0x72, 0xf9 }, /* No such regsister defined */
{ RESERVED_0X73, 0xff },
{ RESERVED_0X74, 0xb2 },
{ RESERVED_0X75, 0xc7 },
{ EXTGVBBRF, 0xf0 },
{ DIVAGCCK, 0x80 },
{ BBTR, 0xa0 },
{ RESERVED_0X7E, 0x4f },
{ 0x82, 0x88 }, /* No such regsister defined */
{ 0x83, 0x80 }, /* No such regsister defined */
{ 0x84, 0x80 }, /* No such regsister defined */
{ RESERVED_0X85, 0x74 },
{ RESERVED_0X86, 0xff },
{ RESERVED_0X88, 0x02 },
{ RESERVED_0X89, 0x16 },
{ RFST0, 0x1f },
{ RESERVED_0X94, 0x66 },
{ RESERVED_0X95, 0x66 },
{ RESERVED_0X96, 0x77 },
{ RESERVED_0X97, 0x99 },
{ RESERVED_0X98, 0xff },
{ RESERVED_0X99, 0xfc },
{ RESERVED_0X9A, 0xba },
{ RESERVED_0X9B, 0xaa },
};
static u8 itd1000_reinit_tab[][2] = {
{ VCO_CHP1_I2C, 0x8a },
{ BW, 0x87 },
{ GVBB_I2C, 0x03 },
{ BBGVMIN, 0x03 },
{ CON1, 0x2e },
};
static int itd1000_init(struct dvb_frontend *fe)
{
struct itd1000_state *state = fe->tuner_priv;
int i;
for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
return 0;
}
static int itd1000_sleep(struct dvb_frontend *fe)
{
return 0;
}
static void itd1000_release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
}
static const struct dvb_tuner_ops itd1000_tuner_ops = {
.info = {
.name = "Integrant ITD1000",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_step_hz = 125 * kHz,
},
.release = itd1000_release,
.init = itd1000_init,
.sleep = itd1000_sleep,
.set_params = itd1000_set_parameters,
.get_frequency = itd1000_get_frequency,
.get_bandwidth = itd1000_get_bandwidth
};
struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
{
struct itd1000_state *state = NULL;
u8 i = 0;
state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
if (state == NULL)
return NULL;
state->cfg = cfg;
state->i2c = i2c;
i = itd1000_read_reg(state, 0);
if (i != 0) {
kfree(state);
return NULL;
}
itd_info("successfully identified (ID: %d)\n", i);
memset(state->shadow, 0xff, sizeof(state->shadow));
for (i = 0x65; i < 0x9c; i++)
state->shadow[i] = itd1000_read_reg(state, i);
memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
fe->tuner_priv = state;
return fe;
}
EXPORT_SYMBOL_GPL(itd1000_attach);
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("Integrant ITD1000 driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/itd1000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Conexant CX24113/CX24128 Tuner (Satellite)
*
* Copyright (C) 2007-8 Patrick Boettcher <[email protected]>
*
* Developed for BBTI / Technisat
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <media/dvb_frontend.h>
#include "cx24113.h"
static int debug;
#define cx_info(args...) do { printk(KERN_INFO "CX24113: " args); } while (0)
#define cx_err(args...) do { printk(KERN_ERR "CX24113: " args); } while (0)
#define dprintk(args...) \
do { \
if (debug) { \
printk(KERN_DEBUG "CX24113: %s: ", __func__); \
printk(args); \
} \
} while (0)
struct cx24113_state {
struct i2c_adapter *i2c;
const struct cx24113_config *config;
#define REV_CX24113 0x23
u8 rev;
u8 ver;
u8 icp_mode:1;
#define ICP_LEVEL1 0
#define ICP_LEVEL2 1
#define ICP_LEVEL3 2
#define ICP_LEVEL4 3
u8 icp_man:2;
u8 icp_auto_low:2;
u8 icp_auto_mlow:2;
u8 icp_auto_mhi:2;
u8 icp_auto_hi:2;
u8 icp_dig;
#define LNA_MIN_GAIN 0
#define LNA_MID_GAIN 1
#define LNA_MAX_GAIN 2
u8 lna_gain:2;
u8 acp_on:1;
u8 vco_mode:2;
u8 vco_shift:1;
#define VCOBANDSEL_6 0x80
#define VCOBANDSEL_5 0x01
#define VCOBANDSEL_4 0x02
#define VCOBANDSEL_3 0x04
#define VCOBANDSEL_2 0x08
#define VCOBANDSEL_1 0x10
u8 vco_band;
#define VCODIV4 4
#define VCODIV2 2
u8 vcodiv;
u8 bs_delay:4;
u16 bs_freqcnt:13;
u16 bs_rdiv;
u8 prescaler_mode:1;
u8 rfvga_bias_ctrl;
s16 tuner_gain_thres;
u8 gain_level;
u32 frequency;
u8 refdiv;
u8 Fwindow_enabled;
};
static int cx24113_writereg(struct cx24113_state *state, int reg, int data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->i2c_addr,
.flags = 0, .buf = buf, .len = 2 };
int err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
printk(KERN_DEBUG "%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n",
__func__, err, reg, data);
return err;
}
return 0;
}
static int cx24113_readreg(struct cx24113_state *state, u8 reg)
{
int ret;
u8 b;
struct i2c_msg msg[] = {
{ .addr = state->config->i2c_addr,
.flags = 0, .buf = ®, .len = 1 },
{ .addr = state->config->i2c_addr,
.flags = I2C_M_RD, .buf = &b, .len = 1 }
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
printk(KERN_DEBUG "%s: reg=0x%x (error=%d)\n",
__func__, reg, ret);
return ret;
}
return b;
}
static void cx24113_set_parameters(struct cx24113_state *state)
{
u8 r;
r = cx24113_readreg(state, 0x10) & 0x82;
r |= state->icp_mode;
r |= state->icp_man << 4;
r |= state->icp_dig << 2;
r |= state->prescaler_mode << 5;
cx24113_writereg(state, 0x10, r);
r = (state->icp_auto_low << 0) | (state->icp_auto_mlow << 2)
| (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6);
cx24113_writereg(state, 0x11, r);
if (state->rev == REV_CX24113) {
r = cx24113_readreg(state, 0x20) & 0xec;
r |= state->lna_gain;
r |= state->rfvga_bias_ctrl << 4;
cx24113_writereg(state, 0x20, r);
}
r = cx24113_readreg(state, 0x12) & 0x03;
r |= state->acp_on << 2;
r |= state->bs_delay << 4;
cx24113_writereg(state, 0x12, r);
r = cx24113_readreg(state, 0x18) & 0x40;
r |= state->vco_shift;
if (state->vco_band == VCOBANDSEL_6)
r |= (1 << 7);
else
r |= (state->vco_band << 1);
cx24113_writereg(state, 0x18, r);
r = cx24113_readreg(state, 0x14) & 0x20;
r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f);
cx24113_writereg(state, 0x14, r);
cx24113_writereg(state, 0x15, (state->bs_freqcnt & 0xff));
cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff);
r = (cx24113_readreg(state, 0x17) & 0x0f) |
((state->bs_rdiv & 0x0f) << 4);
cx24113_writereg(state, 0x17, r);
}
#define VGA_0 0x00
#define VGA_1 0x04
#define VGA_2 0x02
#define VGA_3 0x06
#define VGA_4 0x01
#define VGA_5 0x05
#define VGA_6 0x03
#define VGA_7 0x07
#define RFVGA_0 0x00
#define RFVGA_1 0x01
#define RFVGA_2 0x02
#define RFVGA_3 0x03
static int cx24113_set_gain_settings(struct cx24113_state *state,
s16 power_estimation)
{
u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0,
vga = cx24113_readreg(state, 0x1f) & 0x3f,
rfvga = cx24113_readreg(state, 0x20) & 0xf3;
u8 gain_level = power_estimation >= state->tuner_gain_thres;
dprintk("power estimation: %d, thres: %d, gain_level: %d/%d\n",
power_estimation, state->tuner_gain_thres,
state->gain_level, gain_level);
if (gain_level == state->gain_level)
return 0; /* nothing to be done */
ampout |= 0xf;
if (gain_level) {
rfvga |= RFVGA_0 << 2;
vga |= (VGA_7 << 3) | VGA_7;
} else {
rfvga |= RFVGA_2 << 2;
vga |= (VGA_6 << 3) | VGA_2;
}
state->gain_level = gain_level;
cx24113_writereg(state, 0x1d, ampout);
cx24113_writereg(state, 0x1f, vga);
cx24113_writereg(state, 0x20, rfvga);
return 1; /* did something */
}
static int cx24113_set_Fref(struct cx24113_state *state, u8 high)
{
u8 xtal = cx24113_readreg(state, 0x02);
if (state->rev == 0x43 && state->vcodiv == VCODIV4)
high = 1;
xtal &= ~0x2;
if (high)
xtal |= high << 1;
return cx24113_writereg(state, 0x02, xtal);
}
static int cx24113_enable(struct cx24113_state *state, u8 enable)
{
u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable;
if (state->rev == REV_CX24113)
r21 |= (1 << 1);
return cx24113_writereg(state, 0x21, r21);
}
static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz)
{
u8 r;
if (bandwidth_khz <= 19000)
r = 0x03 << 6;
else if (bandwidth_khz <= 25000)
r = 0x02 << 6;
else
r = 0x01 << 6;
dprintk("bandwidth to be set: %d\n", bandwidth_khz);
bandwidth_khz *= 10;
bandwidth_khz -= 10000;
bandwidth_khz /= 1000;
bandwidth_khz += 5;
bandwidth_khz /= 10;
dprintk("bandwidth: %d %d\n", r >> 6, bandwidth_khz);
r |= bandwidth_khz & 0x3f;
return cx24113_writereg(state, 0x1e, r);
}
static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on)
{
u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7);
return cx24113_writereg(state, 0x10, r);
}
static int cx24113_get_status(struct dvb_frontend *fe, u32 *status)
{
struct cx24113_state *state = fe->tuner_priv;
u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1;
if (r)
*status |= TUNER_STATUS_LOCKED;
dprintk("PLL locked: %d\n", r);
return 0;
}
static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv)
{
if (state->rev == 0x43 && state->vcodiv == VCODIV4)
refdiv = 2;
return state->refdiv = refdiv;
}
static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f)
{
s32 N;
s64 F;
u64 dividend;
u8 R, r;
u8 vcodiv;
u8 factor;
s32 freq_hz = state->frequency * 1000;
if (state->config->xtal_khz < 20000)
factor = 1;
else
factor = 2;
if (state->rev == REV_CX24113) {
if (state->frequency >= 1100000)
vcodiv = VCODIV2;
else
vcodiv = VCODIV4;
} else {
if (state->frequency >= 1165000)
vcodiv = VCODIV2;
else
vcodiv = VCODIV4;
}
state->vcodiv = vcodiv;
dprintk("calculating N/F for %dHz with vcodiv %d\n", freq_hz, vcodiv);
R = 0;
do {
R = cx24113_set_ref_div(state, R + 1);
/* calculate tuner PLL settings: */
N = (freq_hz / 100 * vcodiv) * R;
N /= (state->config->xtal_khz) * factor * 2;
N += 5; /* For round up. */
N /= 10;
N -= 32;
} while (N < 6 && R < 3);
if (N < 6) {
cx_err("strange frequency: N < 6\n");
return;
}
F = freq_hz;
F *= (u64) (R * vcodiv * 262144);
dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
/* do_div needs an u64 as first argument */
dividend = F;
do_div(dividend, state->config->xtal_khz * 1000 * factor * 2);
F = dividend;
dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
F -= (N + 32) * 262144;
dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
if (state->Fwindow_enabled) {
if (F > (262144 / 2 - 1638))
F = 262144 / 2 - 1638;
if (F < (-262144 / 2 + 1638))
F = -262144 / 2 + 1638;
if ((F < 3277 && F > 0) || (F > -3277 && F < 0)) {
F = 0;
r = cx24113_readreg(state, 0x10);
cx24113_writereg(state, 0x10, r | (1 << 6));
}
}
dprintk("4 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
*n = (u16) N;
*f = (s32) F;
}
static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r)
{
u8 reg;
cx24113_writereg(state, 0x19, (n >> 1) & 0xff);
reg = ((n & 0x1) << 7) | ((f >> 11) & 0x7f);
cx24113_writereg(state, 0x1a, reg);
cx24113_writereg(state, 0x1b, (f >> 3) & 0xff);
reg = cx24113_readreg(state, 0x1c) & 0x1f;
cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5));
cx24113_set_Fref(state, r - 1);
}
static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency)
{
u8 r;
u16 n = 6;
s32 f = 0;
r = cx24113_readreg(state, 0x14);
cx24113_writereg(state, 0x14, r & 0x3f);
r = cx24113_readreg(state, 0x10);
cx24113_writereg(state, 0x10, r & 0xbf);
state->frequency = frequency;
dprintk("tuning to frequency: %d\n", frequency);
cx24113_calc_pll_nf(state, &n, &f);
cx24113_set_nfr(state, n, f, state->refdiv);
r = cx24113_readreg(state, 0x18) & 0xbf;
if (state->vcodiv != VCODIV2)
r |= 1 << 6;
cx24113_writereg(state, 0x18, r);
/* The need for this sleep is not clear. But helps in some cases */
msleep(5);
r = cx24113_readreg(state, 0x1c) & 0xef;
cx24113_writereg(state, 0x1c, r | (1 << 4));
return 0;
}
static int cx24113_init(struct dvb_frontend *fe)
{
struct cx24113_state *state = fe->tuner_priv;
int ret;
state->tuner_gain_thres = -50;
state->gain_level = 255; /* to force a gain-setting initialization */
state->icp_mode = 0;
if (state->config->xtal_khz < 11000) {
state->icp_auto_hi = ICP_LEVEL4;
state->icp_auto_mhi = ICP_LEVEL4;
state->icp_auto_mlow = ICP_LEVEL3;
state->icp_auto_low = ICP_LEVEL3;
} else {
state->icp_auto_hi = ICP_LEVEL4;
state->icp_auto_mhi = ICP_LEVEL4;
state->icp_auto_mlow = ICP_LEVEL3;
state->icp_auto_low = ICP_LEVEL2;
}
state->icp_dig = ICP_LEVEL3;
state->icp_man = ICP_LEVEL1;
state->acp_on = 1;
state->vco_mode = 0;
state->vco_shift = 0;
state->vco_band = VCOBANDSEL_1;
state->bs_delay = 8;
state->bs_freqcnt = 0x0fff;
state->bs_rdiv = 0x0fff;
state->prescaler_mode = 0;
state->lna_gain = LNA_MAX_GAIN;
state->rfvga_bias_ctrl = 1;
state->Fwindow_enabled = 1;
cx24113_set_Fref(state, 0);
cx24113_enable(state, 0x3d);
cx24113_set_parameters(state);
cx24113_set_gain_settings(state, -30);
cx24113_set_bandwidth(state, 18025);
cx24113_set_clk_inversion(state, 1);
if (state->config->xtal_khz >= 40000)
ret = cx24113_writereg(state, 0x02,
(cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2));
else
ret = cx24113_writereg(state, 0x02,
(cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2));
return ret;
}
static int cx24113_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24113_state *state = fe->tuner_priv;
/* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */
u32 roll_off = 675;
u32 bw;
bw = ((c->symbol_rate/100) * roll_off) / 1000;
bw += (10000000/100) + 5;
bw /= 10;
bw += 1000;
cx24113_set_bandwidth(state, bw);
cx24113_set_frequency(state, c->frequency);
msleep(5);
return cx24113_get_status(fe, &bw);
}
static s8 cx24113_agc_table[2][10] = {
{-54, -41, -35, -30, -25, -21, -16, -10, -6, -2},
{-39, -35, -30, -25, -19, -15, -11, -5, 1, 9},
};
void cx24113_agc_callback(struct dvb_frontend *fe)
{
struct cx24113_state *state = fe->tuner_priv;
s16 s, i;
if (!fe->ops.read_signal_strength)
return;
do {
/* this only works with the current CX24123 implementation */
fe->ops.read_signal_strength(fe, (u16 *) &s);
s >>= 8;
dprintk("signal strength: %d\n", s);
for (i = 0; i < sizeof(cx24113_agc_table[0]); i++)
if (cx24113_agc_table[state->gain_level][i] > s)
break;
s = -25 - i*5;
} while (cx24113_set_gain_settings(state, s));
}
EXPORT_SYMBOL(cx24113_agc_callback);
static int cx24113_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct cx24113_state *state = fe->tuner_priv;
*frequency = state->frequency;
return 0;
}
static void cx24113_release(struct dvb_frontend *fe)
{
struct cx24113_state *state = fe->tuner_priv;
dprintk("\n");
fe->tuner_priv = NULL;
kfree(state);
}
static const struct dvb_tuner_ops cx24113_tuner_ops = {
.info = {
.name = "Conexant CX24113",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_step_hz = 125 * kHz,
},
.release = cx24113_release,
.init = cx24113_init,
.set_params = cx24113_set_params,
.get_frequency = cx24113_get_frequency,
.get_status = cx24113_get_status,
};
struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
const struct cx24113_config *config, struct i2c_adapter *i2c)
{
/* allocate memory for the internal state */
struct cx24113_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
int rc;
if (!state)
return NULL;
/* setup the state */
state->config = config;
state->i2c = i2c;
cx_info("trying to detect myself\n");
/* making a dummy read, because of some expected troubles
* after power on */
cx24113_readreg(state, 0x00);
rc = cx24113_readreg(state, 0x00);
if (rc < 0) {
cx_info("CX24113 not found.\n");
goto error;
}
state->rev = rc;
switch (rc) {
case 0x43:
cx_info("detected CX24113 variant\n");
break;
case REV_CX24113:
cx_info("successfully detected\n");
break;
default:
cx_err("unsupported device id: %x\n", state->rev);
goto error;
}
state->ver = cx24113_readreg(state, 0x01);
cx_info("version: %x\n", state->ver);
/* create dvb_frontend */
memcpy(&fe->ops.tuner_ops, &cx24113_tuner_ops,
sizeof(struct dvb_tuner_ops));
fe->tuner_priv = state;
return fe;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(cx24113_attach);
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
MODULE_AUTHOR("Patrick Boettcher <[email protected]>");
MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24113/CX24128hardware");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/cx24113.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Realtek RTL2832 DVB-T demodulator driver
*
* Copyright (C) 2012 Thomas Mair <[email protected]>
* Copyright (C) 2012-2014 Antti Palosaari <[email protected]>
*/
#include "rtl2832_priv.h"
#define REG_MASK(b) (BIT(b + 1) - 1)
static const struct rtl2832_reg_entry registers[] = {
[DVBT_SOFT_RST] = {0x101, 2, 2},
[DVBT_IIC_REPEAT] = {0x101, 3, 3},
[DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
[DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
[DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
[DVBT_AD_EN_REG] = {0x008, 7, 7},
[DVBT_AD_EN_REG1] = {0x008, 6, 6},
[DVBT_EN_BBIN] = {0x1b1, 0, 0},
[DVBT_MGD_THD0] = {0x195, 7, 0},
[DVBT_MGD_THD1] = {0x196, 7, 0},
[DVBT_MGD_THD2] = {0x197, 7, 0},
[DVBT_MGD_THD3] = {0x198, 7, 0},
[DVBT_MGD_THD4] = {0x199, 7, 0},
[DVBT_MGD_THD5] = {0x19a, 7, 0},
[DVBT_MGD_THD6] = {0x19b, 7, 0},
[DVBT_MGD_THD7] = {0x19c, 7, 0},
[DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
[DVBT_AD_AV_REF] = {0x009, 6, 0},
[DVBT_REG_PI] = {0x00a, 2, 0},
[DVBT_PIP_ON] = {0x021, 3, 3},
[DVBT_SCALE1_B92] = {0x292, 7, 0},
[DVBT_SCALE1_B93] = {0x293, 7, 0},
[DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
[DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
[DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
[DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
[DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
[DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
[DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
[DVBT_KB_P1] = {0x164, 3, 1},
[DVBT_KB_P2] = {0x164, 6, 4},
[DVBT_KB_P3] = {0x165, 2, 0},
[DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
[DVBT_AD_AVI] = {0x009, 1, 0},
[DVBT_AD_AVQ] = {0x009, 3, 2},
[DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
[DVBT_TRK_KS_P2] = {0x16f, 2, 0},
[DVBT_TRK_KS_I2] = {0x170, 5, 3},
[DVBT_TR_THD_SET2] = {0x172, 3, 0},
[DVBT_TRK_KC_P2] = {0x173, 5, 3},
[DVBT_TRK_KC_I2] = {0x175, 2, 0},
[DVBT_CR_THD_SET2] = {0x176, 7, 6},
[DVBT_PSET_IFFREQ] = {0x119, 21, 0},
[DVBT_SPEC_INV] = {0x115, 0, 0},
[DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
[DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
[DVBT_FSM_STAGE] = {0x351, 6, 3},
[DVBT_RX_CONSTEL] = {0x33c, 3, 2},
[DVBT_RX_HIER] = {0x33c, 6, 4},
[DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
[DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
[DVBT_GI_IDX] = {0x351, 1, 0},
[DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
[DVBT_RSD_BER_EST] = {0x34e, 15, 0},
[DVBT_CE_EST_EVM] = {0x40c, 15, 0},
[DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
[DVBT_IF_AGC_VAL] = {0x359, 13, 0},
[DVBT_DAGC_VAL] = {0x305, 7, 0},
[DVBT_SFREQ_OFF] = {0x318, 13, 0},
[DVBT_CFREQ_OFF] = {0x35f, 17, 0},
[DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
[DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
[DVBT_AAGC_HOLD] = {0x104, 5, 5},
[DVBT_EN_RF_AGC] = {0x104, 6, 6},
[DVBT_EN_IF_AGC] = {0x104, 7, 7},
[DVBT_IF_AGC_MIN] = {0x108, 7, 0},
[DVBT_IF_AGC_MAX] = {0x109, 7, 0},
[DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
[DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
[DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
[DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
[DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
[DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
[DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
[DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
[DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
[DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
[DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
[DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
[DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
[DVBT_VTOP1] = {0x106, 5, 0},
[DVBT_VTOP2] = {0x1c9, 5, 0},
[DVBT_VTOP3] = {0x1ca, 5, 0},
[DVBT_KRF1] = {0x1cb, 7, 0},
[DVBT_KRF2] = {0x107, 7, 0},
[DVBT_KRF3] = {0x1cd, 7, 0},
[DVBT_KRF4] = {0x1ce, 7, 0},
[DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
[DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
[DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
[DVBT_THD_UP1] = {0x1dd, 7, 0},
[DVBT_THD_DW1] = {0x1de, 7, 0},
[DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
[DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
[DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
[DVBT_CKOUTPAR] = {0x17b, 5, 5},
[DVBT_CKOUT_PWR] = {0x17b, 6, 6},
[DVBT_SYNC_DUR] = {0x17b, 7, 7},
[DVBT_ERR_DUR] = {0x17c, 0, 0},
[DVBT_SYNC_LVL] = {0x17c, 1, 1},
[DVBT_ERR_LVL] = {0x17c, 2, 2},
[DVBT_VAL_LVL] = {0x17c, 3, 3},
[DVBT_SERIAL] = {0x17c, 4, 4},
[DVBT_SER_LSB] = {0x17c, 5, 5},
[DVBT_CDIV_PH0] = {0x17d, 3, 0},
[DVBT_CDIV_PH1] = {0x17d, 7, 4},
[DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
[DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
[DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
[DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
[DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
[DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
[DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
[DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
[DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
[DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
[DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
[DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
[DVBT_SM_PASS] = {0x193, 11, 0},
[DVBT_AD7_SETTING] = {0x011, 15, 0},
[DVBT_RSSI_R] = {0x301, 6, 0},
[DVBT_ACI_DET_IND] = {0x312, 0, 0},
[DVBT_REG_MON] = {0x00d, 1, 0},
[DVBT_REG_MONSEL] = {0x00d, 2, 2},
[DVBT_REG_GPE] = {0x00d, 7, 7},
[DVBT_REG_GPO] = {0x010, 0, 0},
[DVBT_REG_4MSEL] = {0x013, 0, 0},
};
static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
{
struct i2c_client *client = dev->client;
int ret, i;
u16 reg_start_addr;
u8 msb, lsb, reading[4], len;
u32 reading_tmp, mask;
reg_start_addr = registers[reg].start_address;
msb = registers[reg].msb;
lsb = registers[reg].lsb;
len = (msb >> 3) + 1;
mask = REG_MASK(msb - lsb);
ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
if (ret)
goto err;
reading_tmp = 0;
for (i = 0; i < len; i++)
reading_tmp |= reading[i] << ((len - 1 - i) * 8);
*val = (reading_tmp >> lsb) & mask;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
{
struct i2c_client *client = dev->client;
int ret, i;
u16 reg_start_addr;
u8 msb, lsb, reading[4], writing[4], len;
u32 reading_tmp, writing_tmp, mask;
reg_start_addr = registers[reg].start_address;
msb = registers[reg].msb;
lsb = registers[reg].lsb;
len = (msb >> 3) + 1;
mask = REG_MASK(msb - lsb);
ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
if (ret)
goto err;
reading_tmp = 0;
for (i = 0; i < len; i++)
reading_tmp |= reading[i] << ((len - 1 - i) * 8);
writing_tmp = reading_tmp & ~(mask << lsb);
writing_tmp |= ((val & mask) << lsb);
for (i = 0; i < len; i++)
writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
ret = regmap_bulk_write(dev->regmap, reg_start_addr, writing, len);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u64 pset_iffreq;
u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
/*
* PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
* / CrystalFreqHz)
*/
pset_iffreq = if_freq % dev->pdata->clk;
pset_iffreq *= 0x400000;
pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
pset_iffreq = -pset_iffreq;
pset_iffreq = pset_iffreq & 0x3fffff;
dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
if_freq, (unsigned)pset_iffreq);
ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
if (ret)
goto err;
ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_init(struct dvb_frontend *fe)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
const struct rtl2832_reg_value *init;
int i, ret, len;
/* initialization values for the demodulator registers */
struct rtl2832_reg_value rtl2832_initial_regs[] = {
{DVBT_AD_EN_REG, 0x1},
{DVBT_AD_EN_REG1, 0x1},
{DVBT_RSD_BER_FAIL_VAL, 0x2800},
{DVBT_MGD_THD0, 0x10},
{DVBT_MGD_THD1, 0x20},
{DVBT_MGD_THD2, 0x20},
{DVBT_MGD_THD3, 0x40},
{DVBT_MGD_THD4, 0x22},
{DVBT_MGD_THD5, 0x32},
{DVBT_MGD_THD6, 0x37},
{DVBT_MGD_THD7, 0x39},
{DVBT_EN_BK_TRK, 0x0},
{DVBT_EN_CACQ_NOTCH, 0x0},
{DVBT_AD_AV_REF, 0x2a},
{DVBT_REG_PI, 0x6},
{DVBT_PIP_ON, 0x0},
{DVBT_CDIV_PH0, 0x8},
{DVBT_CDIV_PH1, 0x8},
{DVBT_SCALE1_B92, 0x4},
{DVBT_SCALE1_B93, 0xb0},
{DVBT_SCALE1_BA7, 0x78},
{DVBT_SCALE1_BA9, 0x28},
{DVBT_SCALE1_BAA, 0x59},
{DVBT_SCALE1_BAB, 0x83},
{DVBT_SCALE1_BAC, 0xd4},
{DVBT_SCALE1_BB0, 0x65},
{DVBT_SCALE1_BB1, 0x43},
{DVBT_KB_P1, 0x1},
{DVBT_KB_P2, 0x4},
{DVBT_KB_P3, 0x7},
{DVBT_K1_CR_STEP12, 0xa},
{DVBT_REG_GPE, 0x1},
{DVBT_SERIAL, 0x0},
{DVBT_CDIV_PH0, 0x9},
{DVBT_CDIV_PH1, 0x9},
{DVBT_MPEG_IO_OPT_2_2, 0x0},
{DVBT_MPEG_IO_OPT_1_0, 0x0},
{DVBT_TRK_KS_P2, 0x4},
{DVBT_TRK_KS_I2, 0x7},
{DVBT_TR_THD_SET2, 0x6},
{DVBT_TRK_KC_I2, 0x5},
{DVBT_CR_THD_SET2, 0x1},
};
dev_dbg(&client->dev, "\n");
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
if (ret)
goto err;
for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
rtl2832_initial_regs[i].value);
if (ret)
goto err;
}
/* load tuner specific settings */
dev_dbg(&client->dev, "load settings for tuner=%02x\n",
dev->pdata->tuner);
switch (dev->pdata->tuner) {
case RTL2832_TUNER_FC2580:
len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
init = rtl2832_tuner_init_fc2580;
break;
case RTL2832_TUNER_FC0012:
case RTL2832_TUNER_FC0013:
len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
init = rtl2832_tuner_init_fc0012;
break;
case RTL2832_TUNER_TUA9001:
len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
init = rtl2832_tuner_init_tua9001;
break;
case RTL2832_TUNER_E4000:
len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
init = rtl2832_tuner_init_e4000;
break;
case RTL2832_TUNER_R820T:
case RTL2832_TUNER_R828D:
len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
init = rtl2832_tuner_init_r820t;
break;
case RTL2832_TUNER_SI2157:
len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
init = rtl2832_tuner_init_si2157;
break;
default:
ret = -EINVAL;
goto err;
}
for (i = 0; i < len; i++) {
ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
if (ret)
goto err;
}
/* init stats here in order signal app which stats are supported */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dev->sleeping = false;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_sleep(struct dvb_frontend *fe)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
dev_dbg(&client->dev, "\n");
dev->sleeping = true;
dev->fe_status = 0;
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
dev_dbg(&client->dev, "\n");
s->min_delay_ms = 1000;
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
return 0;
}
static int rtl2832_set_frontend(struct dvb_frontend *fe)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, j;
u64 bw_mode, num, num2;
u32 resamp_ratio, cfreq_off_ratio;
static u8 bw_params[3][32] = {
/* 6 MHz bandwidth */
{
0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
0x19, 0xe0,
},
/* 7 MHz bandwidth */
{
0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
0x19, 0x10,
},
/* 8 MHz bandwidth */
{
0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
0x19, 0xe0,
},
};
dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
c->frequency, c->bandwidth_hz, c->inversion);
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
/* If the frontend has get_if_frequency(), use it */
if (fe->ops.tuner_ops.get_if_frequency) {
u32 if_freq;
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
if (ret)
goto err;
ret = rtl2832_set_if(fe, if_freq);
if (ret)
goto err;
}
switch (c->bandwidth_hz) {
case 6000000:
i = 0;
bw_mode = 48000000;
break;
case 7000000:
i = 1;
bw_mode = 56000000;
break;
case 8000000:
i = 2;
bw_mode = 64000000;
break;
default:
dev_err(&client->dev, "invalid bandwidth_hz %u\n",
c->bandwidth_hz);
ret = -EINVAL;
goto err;
}
for (j = 0; j < sizeof(bw_params[0]); j++) {
ret = regmap_bulk_write(dev->regmap,
0x11c + j, &bw_params[i][j], 1);
if (ret)
goto err;
}
/* calculate and set resample ratio
* RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
* / ConstWithBandwidthMode)
*/
num = dev->pdata->clk * 7ULL;
num *= 0x400000;
num = div_u64(num, bw_mode);
resamp_ratio = num & 0x3ffffff;
ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
if (ret)
goto err;
/* calculate and set cfreq off ratio
* CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
* / (CrystalFreqHz * 7))
*/
num = bw_mode << 20;
num2 = dev->pdata->clk * 7ULL;
num = div_u64(num, num2);
num = -num;
cfreq_off_ratio = num & 0xfffff;
ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
if (ret)
goto err;
/* soft reset */
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
if (ret)
goto err;
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 buf[3];
if (dev->sleeping)
return 0;
ret = regmap_bulk_read(dev->regmap, 0x33c, buf, 2);
if (ret)
goto err;
ret = regmap_bulk_read(dev->regmap, 0x351, &buf[2], 1);
if (ret)
goto err;
dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
switch ((buf[0] >> 2) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[2] >> 2) & 1) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
}
switch ((buf[2] >> 0) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[0] >> 4) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[1] >> 3) & 7) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
}
switch ((buf[1] >> 0) & 7) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
u32 tmp;
u8 u8tmp, buf[2];
u16 u16tmp;
dev_dbg(&client->dev, "\n");
*status = 0;
if (dev->sleeping)
return 0;
ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
if (ret)
goto err;
if (tmp == 11) {
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else if (tmp == 10) {
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
}
dev->fe_status = *status;
/* signal strength */
if (dev->fe_status & FE_HAS_SIGNAL) {
/* read digital AGC */
ret = regmap_bulk_read(dev->regmap, 0x305, &u8tmp, 1);
if (ret)
goto err;
dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
u8tmp = ~u8tmp;
u16tmp = u8tmp << 8 | u8tmp << 0;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = u16tmp;
} else {
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (dev->fe_status & FE_HAS_VITERBI) {
unsigned hierarchy, constellation;
#define CONSTELLATION_NUM 3
#define HIERARCHY_NUM 4
static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
{85387325, 85387325, 85387325, 85387325},
{86676178, 86676178, 87167949, 87795660},
{87659938, 87659938, 87885178, 88241743},
};
ret = regmap_bulk_read(dev->regmap, 0x33c, &u8tmp, 1);
if (ret)
goto err;
constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
ret = -EINVAL;
if (constellation > CONSTELLATION_NUM - 1)
goto err;
hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
if (hierarchy > HIERARCHY_NUM - 1)
goto err;
ret = regmap_bulk_read(dev->regmap, 0x40c, buf, 2);
if (ret)
goto err;
u16tmp = buf[0] << 8 | buf[1] << 0;
if (u16tmp)
tmp = (constant[constellation][hierarchy] -
intlog10(u16tmp)) / ((1 << 24) / 10000);
else
tmp = 0;
dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = tmp;
} else {
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (dev->fe_status & FE_HAS_LOCK) {
ret = regmap_bulk_read(dev->regmap, 0x34e, buf, 2);
if (ret)
goto err;
u16tmp = buf[0] << 8 | buf[1] << 0;
dev->post_bit_error += u16tmp;
dev->post_bit_count += 1000000;
dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
/* report SNR in resolution of 0.1 dB */
if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
*snr = div_s64(c->cnr.stat[0].svalue, 100);
else
*snr = 0;
return 0;
}
static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
*ber = (dev->post_bit_error - dev->post_bit_error_prev);
dev->post_bit_error_prev = dev->post_bit_error;
return 0;
}
/*
* I2C gate/mux/repeater logic
* There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
* is delayed here a little bit in order to see if there is sequence of I2C
* messages sent to same I2C bus.
*/
static void rtl2832_i2c_gate_work(struct work_struct *work)
{
struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
struct i2c_client *client = dev->client;
int ret;
/* close gate */
ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x00);
if (ret)
goto err;
return;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
}
static int rtl2832_select(struct i2c_mux_core *muxc, u32 chan_id)
{
struct rtl2832_dev *dev = i2c_mux_priv(muxc);
struct i2c_client *client = dev->client;
int ret;
/* terminate possible gate closing */
cancel_delayed_work(&dev->i2c_gate_work);
/* open gate */
ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_deselect(struct i2c_mux_core *muxc, u32 chan_id)
{
struct rtl2832_dev *dev = i2c_mux_priv(muxc);
schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
return 0;
}
static const struct dvb_frontend_ops rtl2832_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Realtek RTL2832 (DVB-T)",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER |
FE_CAN_MUTE_TS
},
.init = rtl2832_init,
.sleep = rtl2832_sleep,
.get_tune_settings = rtl2832_get_tune_settings,
.set_frontend = rtl2832_set_frontend,
.get_frontend = rtl2832_get_frontend,
.read_status = rtl2832_read_status,
.read_snr = rtl2832_read_snr,
.read_ber = rtl2832_read_ber,
};
static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x305:
case 0x33c:
case 0x34e:
case 0x351:
case 0x40c ... 0x40d:
return true;
default:
break;
}
return false;
}
static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
{
struct rtl2832_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return &dev->fe;
}
static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
{
struct rtl2832_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
return dev->muxc->adapter[0];
}
static int rtl2832_slave_ts_ctrl(struct i2c_client *client, bool enable)
{
struct rtl2832_dev *dev = i2c_get_clientdata(client);
int ret;
dev_dbg(&client->dev, "enable=%d\n", enable);
if (enable) {
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x10c, "\x5f\xff", 2);
if (ret)
goto err;
ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x18", 1);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x192, "\x7f\xf7\xff", 3);
if (ret)
goto err;
} else {
ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x08", 1);
if (ret)
goto err;
ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x10c, "\x00\x00", 2);
if (ret)
goto err;
ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
if (ret)
goto err;
}
dev->slave_ts = enable;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 u8tmp;
dev_dbg(&client->dev, "onoff=%d, slave_ts=%d\n", onoff, dev->slave_ts);
/* enable / disable PID filter */
if (onoff)
u8tmp = 0x80;
else
u8tmp = 0x00;
if (dev->slave_ts)
ret = regmap_update_bits(dev->regmap, 0x021, 0xc0, u8tmp);
else
ret = regmap_update_bits(dev->regmap, 0x061, 0xc0, u8tmp);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
int onoff)
{
struct rtl2832_dev *dev = fe->demodulator_priv;
struct i2c_client *client = dev->client;
int ret;
u8 buf[4];
dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d slave_ts=%d\n",
index, pid, onoff, dev->slave_ts);
/* skip invalid PIDs (0x2000) */
if (pid > 0x1fff || index > 32)
return 0;
if (onoff)
set_bit(index, &dev->filters);
else
clear_bit(index, &dev->filters);
/* enable / disable PIDs */
buf[0] = (dev->filters >> 0) & 0xff;
buf[1] = (dev->filters >> 8) & 0xff;
buf[2] = (dev->filters >> 16) & 0xff;
buf[3] = (dev->filters >> 24) & 0xff;
if (dev->slave_ts)
ret = regmap_bulk_write(dev->regmap, 0x022, buf, 4);
else
ret = regmap_bulk_write(dev->regmap, 0x062, buf, 4);
if (ret)
goto err;
/* add PID */
buf[0] = (pid >> 8) & 0xff;
buf[1] = (pid >> 0) & 0xff;
if (dev->slave_ts)
ret = regmap_bulk_write(dev->regmap, 0x026 + 2 * index, buf, 2);
else
ret = regmap_bulk_write(dev->regmap, 0x066 + 2 * index, buf, 2);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int rtl2832_probe(struct i2c_client *client)
{
struct rtl2832_platform_data *pdata = client->dev.platform_data;
struct i2c_adapter *i2c = client->adapter;
struct rtl2832_dev *dev;
int ret;
u8 tmp;
static const struct regmap_range_cfg regmap_range_cfg[] = {
{
.selector_reg = 0x00,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 0x100,
.range_min = 0 * 0x100,
.range_max = 5 * 0x100,
},
};
dev_dbg(&client->dev, "\n");
/* allocate memory for the internal state */
dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
if (dev == NULL) {
ret = -ENOMEM;
goto err;
}
/* setup the state */
i2c_set_clientdata(client, dev);
dev->client = client;
dev->pdata = client->dev.platform_data;
dev->sleeping = true;
INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
/* create regmap */
dev->regmap_config.reg_bits = 8;
dev->regmap_config.val_bits = 8;
dev->regmap_config.volatile_reg = rtl2832_volatile_reg;
dev->regmap_config.max_register = 5 * 0x100;
dev->regmap_config.ranges = regmap_range_cfg;
dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg);
dev->regmap_config.cache_type = REGCACHE_NONE;
dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
/* check if the demod is there */
ret = regmap_bulk_read(dev->regmap, 0x000, &tmp, 1);
if (ret)
goto err_regmap_exit;
/* create muxed i2c adapter for demod tuner bus */
dev->muxc = i2c_mux_alloc(i2c, &i2c->dev, 1, 0, I2C_MUX_LOCKED,
rtl2832_select, rtl2832_deselect);
if (!dev->muxc) {
ret = -ENOMEM;
goto err_regmap_exit;
}
dev->muxc->priv = dev;
ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
if (ret)
goto err_regmap_exit;
/* create dvb_frontend */
memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
dev->fe.demodulator_priv = dev;
/* setup callbacks */
pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
pdata->slave_ts_ctrl = rtl2832_slave_ts_ctrl;
pdata->pid_filter = rtl2832_pid_filter;
pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
pdata->regmap = dev->regmap;
dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
return 0;
err_regmap_exit:
regmap_exit(dev->regmap);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void rtl2832_remove(struct i2c_client *client)
{
struct rtl2832_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
cancel_delayed_work_sync(&dev->i2c_gate_work);
i2c_mux_del_adapters(dev->muxc);
regmap_exit(dev->regmap);
kfree(dev);
}
static const struct i2c_device_id rtl2832_id_table[] = {
{"rtl2832", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
static struct i2c_driver rtl2832_driver = {
.driver = {
.name = "rtl2832",
.suppress_bind_attrs = true,
},
.probe = rtl2832_probe,
.remove = rtl2832_remove,
.id_table = rtl2832_id_table,
};
module_i2c_driver(rtl2832_driver);
MODULE_AUTHOR("Thomas Mair <[email protected]>");
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/rtl2832.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
*
* Copyright (C) 2003-2007 Micronas
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "drxd.h"
#include "drxd_firm.h"
#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
#define CHUNK_SIZE 48
#define DRX_I2C_RMW 0x10
#define DRX_I2C_BROADCAST 0x20
#define DRX_I2C_CLEARCRC 0x80
#define DRX_I2C_SINGLE_MASTER 0xC0
#define DRX_I2C_MODEFLAGS 0xC0
#define DRX_I2C_FLAGS 0xF0
#define DEFAULT_LOCK_TIMEOUT 1100
#define DRX_CHANNEL_AUTO 0
#define DRX_CHANNEL_HIGH 1
#define DRX_CHANNEL_LOW 2
#define DRX_LOCK_MPEG 1
#define DRX_LOCK_FEC 2
#define DRX_LOCK_DEMOD 4
/****************************************************************************/
enum CSCDState {
CSCD_INIT = 0,
CSCD_SET,
CSCD_SAVED
};
enum CDrxdState {
DRXD_UNINITIALIZED = 0,
DRXD_STOPPED,
DRXD_STARTED
};
enum AGC_CTRL_MODE {
AGC_CTRL_AUTO = 0,
AGC_CTRL_USER,
AGC_CTRL_OFF
};
enum OperationMode {
OM_Default,
OM_DVBT_Diversity_Front,
OM_DVBT_Diversity_End
};
struct SCfgAgc {
enum AGC_CTRL_MODE ctrlMode;
u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
u16 R1;
u16 R2;
u16 R3;
};
struct SNoiseCal {
int cpOpt;
short cpNexpOfs;
short tdCal2k;
short tdCal8k;
};
enum app_env {
APPENV_STATIC = 0,
APPENV_PORTABLE = 1,
APPENV_MOBILE = 2
};
enum EIFFilter {
IFFILTER_SAW = 0,
IFFILTER_DISCRETE = 1
};
struct drxd_state {
struct dvb_frontend frontend;
struct dvb_frontend_ops ops;
struct dtv_frontend_properties props;
const struct firmware *fw;
struct device *dev;
struct i2c_adapter *i2c;
void *priv;
struct drxd_config config;
int i2c_access;
int init_done;
struct mutex mutex;
u8 chip_adr;
u16 hi_cfg_timing_div;
u16 hi_cfg_bridge_delay;
u16 hi_cfg_wakeup_key;
u16 hi_cfg_ctrl;
u16 intermediate_freq;
u16 osc_clock_freq;
enum CSCDState cscd_state;
enum CDrxdState drxd_state;
u16 sys_clock_freq;
s16 osc_clock_deviation;
u16 expected_sys_clock_freq;
u16 insert_rs_byte;
u16 enable_parallel;
int operation_mode;
struct SCfgAgc if_agc_cfg;
struct SCfgAgc rf_agc_cfg;
struct SNoiseCal noise_cal;
u32 fe_fs_add_incr;
u32 org_fe_fs_add_incr;
u16 current_fe_if_incr;
u16 m_FeAgRegAgPwd;
u16 m_FeAgRegAgAgcSio;
u16 m_EcOcRegOcModeLop;
u16 m_EcOcRegSncSncLvl;
u8 *m_InitAtomicRead;
u8 *m_HiI2cPatch;
u8 *m_ResetCEFR;
u8 *m_InitFE_1;
u8 *m_InitFE_2;
u8 *m_InitCP;
u8 *m_InitCE;
u8 *m_InitEQ;
u8 *m_InitSC;
u8 *m_InitEC;
u8 *m_ResetECRAM;
u8 *m_InitDiversityFront;
u8 *m_InitDiversityEnd;
u8 *m_DisableDiversity;
u8 *m_StartDiversityFront;
u8 *m_StartDiversityEnd;
u8 *m_DiversityDelay8MHZ;
u8 *m_DiversityDelay6MHZ;
u8 *microcode;
u32 microcode_length;
int type_A;
int PGA;
int diversity;
int tuner_mirrors;
enum app_env app_env_default;
enum app_env app_env_diversity;
};
/****************************************************************************/
/* I2C **********************************************************************/
/****************************************************************************/
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
if (i2c_transfer(adap, &msg, 1) != 1)
return -1;
return 0;
}
static int i2c_read(struct i2c_adapter *adap,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
struct i2c_msg msgs[2] = {
{
.addr = adr, .flags = 0,
.buf = msg, .len = len
}, {
.addr = adr, .flags = I2C_M_RD,
.buf = answ, .len = alen
}
};
if (i2c_transfer(adap, msgs, 2) != 2)
return -1;
return 0;
}
static inline u32 MulDiv32(u32 a, u32 b, u32 c)
{
u64 tmp64;
tmp64 = (u64)a * (u64)b;
do_div(tmp64, c);
return (u32) tmp64;
}
static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
{
u8 adr = state->config.demod_address;
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
u8 mm2[2];
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
return -1;
if (data)
*data = mm2[0] | (mm2[1] << 8);
return mm2[0] | (mm2[1] << 8);
}
static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
{
u8 adr = state->config.demod_address;
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
u8 mm2[4];
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
return -1;
if (data)
*data =
mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
return 0;
}
static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
{
u8 adr = state->config.demod_address;
u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
data & 0xff, (data >> 8) & 0xff
};
if (i2c_write(state->i2c, adr, mm, 6) < 0)
return -1;
return 0;
}
static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
{
u8 adr = state->config.demod_address;
u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
data & 0xff, (data >> 8) & 0xff,
(data >> 16) & 0xff, (data >> 24) & 0xff
};
if (i2c_write(state->i2c, adr, mm, 8) < 0)
return -1;
return 0;
}
static int write_chunk(struct drxd_state *state,
u32 reg, u8 *data, u32 len, u8 flags)
{
u8 adr = state->config.demod_address;
u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
int i;
for (i = 0; i < len; i++)
mm[4 + i] = data[i];
if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
printk(KERN_ERR "error in write_chunk\n");
return -1;
}
return 0;
}
static int WriteBlock(struct drxd_state *state,
u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
{
while (BlockSize > 0) {
u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
return -1;
pBlock += Chunk;
Address += (Chunk >> 1);
BlockSize -= Chunk;
}
return 0;
}
static int WriteTable(struct drxd_state *state, u8 * pTable)
{
int status = 0;
if (!pTable)
return 0;
while (!status) {
u16 Length;
u32 Address = pTable[0] | (pTable[1] << 8) |
(pTable[2] << 16) | (pTable[3] << 24);
if (Address == 0xFFFFFFFF)
break;
pTable += sizeof(u32);
Length = pTable[0] | (pTable[1] << 8);
pTable += sizeof(u16);
if (!Length)
break;
status = WriteBlock(state, Address, Length * 2, pTable, 0);
pTable += (Length * 2);
}
return status;
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
static int ResetCEFR(struct drxd_state *state)
{
return WriteTable(state, state->m_ResetCEFR);
}
static int InitCP(struct drxd_state *state)
{
return WriteTable(state, state->m_InitCP);
}
static int InitCE(struct drxd_state *state)
{
int status;
enum app_env AppEnv = state->app_env_default;
do {
status = WriteTable(state, state->m_InitCE);
if (status < 0)
break;
if (state->operation_mode == OM_DVBT_Diversity_Front ||
state->operation_mode == OM_DVBT_Diversity_End) {
AppEnv = state->app_env_diversity;
}
if (AppEnv == APPENV_STATIC) {
status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
if (status < 0)
break;
} else if (AppEnv == APPENV_PORTABLE) {
status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
if (status < 0)
break;
} else if (AppEnv == APPENV_MOBILE && state->type_A) {
status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
if (status < 0)
break;
} else if (AppEnv == APPENV_MOBILE && !state->type_A) {
status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
if (status < 0)
break;
}
/* start ce */
status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
if (status < 0)
break;
} while (0);
return status;
}
static int StopOC(struct drxd_state *state)
{
int status = 0;
u16 ocSyncLvl = 0;
u16 ocModeLop = state->m_EcOcRegOcModeLop;
u16 dtoIncLop = 0;
u16 dtoIncHip = 0;
do {
/* Store output configuration */
status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
if (status < 0)
break;
/* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
state->m_EcOcRegSncSncLvl = ocSyncLvl;
/* m_EcOcRegOcModeLop = ocModeLop; */
/* Flush FIFO (byte-boundary) at fixed rate */
status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
if (status < 0)
break;
status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
if (status < 0)
break;
ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
if (status < 0)
break;
msleep(1);
/* Output pins to '0' */
status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
if (status < 0)
break;
/* Force the OC out of sync */
ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
if (status < 0)
break;
ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
ocModeLop |= 0x2; /* Magically-out-of-sync */
status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
if (status < 0)
break;
} while (0);
return status;
}
static int StartOC(struct drxd_state *state)
{
int status = 0;
do {
/* Stop OC */
status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
if (status < 0)
break;
/* Restore output configuration */
status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
if (status < 0)
break;
/* Output pins active again */
status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
if (status < 0)
break;
/* Start OC */
status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
if (status < 0)
break;
} while (0);
return status;
}
static int InitEQ(struct drxd_state *state)
{
return WriteTable(state, state->m_InitEQ);
}
static int InitEC(struct drxd_state *state)
{
return WriteTable(state, state->m_InitEC);
}
static int InitSC(struct drxd_state *state)
{
return WriteTable(state, state->m_InitSC);
}
static int InitAtomicRead(struct drxd_state *state)
{
return WriteTable(state, state->m_InitAtomicRead);
}
static int CorrectSysClockDeviation(struct drxd_state *state);
static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
{
u16 ScRaRamLock = 0;
const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
SC_RA_RAM_LOCK_FEC__M |
SC_RA_RAM_LOCK_DEMOD__M);
const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
SC_RA_RAM_LOCK_DEMOD__M);
const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
int status;
*pLockStatus = 0;
status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
if (status < 0) {
printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
return status;
}
if (state->drxd_state != DRXD_STARTED)
return 0;
if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
*pLockStatus |= DRX_LOCK_MPEG;
CorrectSysClockDeviation(state);
}
if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
*pLockStatus |= DRX_LOCK_FEC;
if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
*pLockStatus |= DRX_LOCK_DEMOD;
return 0;
}
/****************************************************************************/
static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
{
int status;
if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
return -1;
if (cfg->ctrlMode == AGC_CTRL_USER) {
do {
u16 FeAgRegPm1AgcWri;
u16 FeAgRegAgModeLop;
status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
if (status < 0)
break;
FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
if (status < 0)
break;
FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
FE_AG_REG_PM1_AGC_WRI__M);
status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
if (status < 0)
break;
} while (0);
} else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
((cfg->speed) > DRXD_FE_CTRL_MAX) ||
((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
)
return -1;
do {
u16 FeAgRegAgModeLop;
u16 FeAgRegEgcSetLvl;
u16 slope, offset;
/* == Mode == */
status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
if (status < 0)
break;
FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
FeAgRegAgModeLop |=
FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
if (status < 0)
break;
/* == Settle level == */
FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
FE_AG_REG_EGC_SET_LVL__M);
status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
if (status < 0)
break;
/* == Min/Max == */
slope = (u16) ((cfg->maxOutputLevel -
cfg->minOutputLevel) / 2);
offset = (u16) ((cfg->maxOutputLevel +
cfg->minOutputLevel) / 2 - 511);
status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
if (status < 0)
break;
/* == Speed == */
{
const u16 maxRur = 8;
static const u16 slowIncrDecLUT[] = {
3, 4, 4, 5, 6 };
static const u16 fastIncrDecLUT[] = {
14, 15, 15, 16,
17, 18, 18, 19,
20, 21, 22, 23,
24, 26, 27, 28,
29, 31
};
u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
(maxRur + 1);
u16 fineSpeed = (u16) (cfg->speed -
((cfg->speed /
fineSteps) *
fineSteps));
u16 invRurCount = (u16) (cfg->speed /
fineSteps);
u16 rurCount;
if (invRurCount > maxRur) {
rurCount = 0;
fineSpeed += fineSteps;
} else {
rurCount = maxRur - invRurCount;
}
/*
fastInc = default *
(2^(fineSpeed/fineSteps))
=> range[default...2*default>
slowInc = default *
(2^(fineSpeed/fineSteps))
*/
{
u16 fastIncrDec =
fastIncrDecLUT[fineSpeed /
((fineSteps /
(14 + 1)) + 1)];
u16 slowIncrDec =
slowIncrDecLUT[fineSpeed /
(fineSteps /
(3 + 1))];
status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
if (status < 0)
break;
}
}
} while (0);
} else {
/* No OFF mode for IF control */
return -1;
}
return status;
}
static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
{
int status = 0;
if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
return -1;
if (cfg->ctrlMode == AGC_CTRL_USER) {
do {
u16 AgModeLop = 0;
u16 level = (cfg->outputLevel);
if (level == DRXD_FE_CTRL_MAX)
level++;
status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
if (status < 0)
break;
/*==== Mode ====*/
/* Powerdown PD2, WRI source */
state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
state->m_FeAgRegAgPwd |=
FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
if (status < 0)
break;
status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
if (status < 0)
break;
AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
FE_AG_REG_AG_MODE_LOP_MODE_E__M));
AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
if (status < 0)
break;
/* enable AGC2 pin */
{
u16 FeAgRegAgAgcSio = 0;
status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
FeAgRegAgAgcSio &=
~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
FeAgRegAgAgcSio |=
FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
}
} while (0);
} else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
u16 AgModeLop = 0;
do {
u16 level;
/* Automatic control */
/* Powerup PD2, AGC2 as output, TGC source */
(state->m_FeAgRegAgPwd) &=
~(FE_AG_REG_AG_PWD_PWD_PD2__M);
(state->m_FeAgRegAgPwd) |=
FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
if (status < 0)
break;
status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
if (status < 0)
break;
AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
FE_AG_REG_AG_MODE_LOP_MODE_E__M));
AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
if (status < 0)
break;
/* Settle level */
level = (((cfg->settleLevel) >> 4) &
FE_AG_REG_TGC_SET_LVL__M);
status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
if (status < 0)
break;
/* Min/max: don't care */
/* Speed: TODO */
/* enable AGC2 pin */
{
u16 FeAgRegAgAgcSio = 0;
status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
FeAgRegAgAgcSio &=
~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
FeAgRegAgAgcSio |=
FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
}
} while (0);
} else {
u16 AgModeLop = 0;
do {
/* No RF AGC control */
/* Powerdown PD2, AGC2 as output, WRI source */
(state->m_FeAgRegAgPwd) &=
~(FE_AG_REG_AG_PWD_PWD_PD2__M);
(state->m_FeAgRegAgPwd) |=
FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
if (status < 0)
break;
status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
if (status < 0)
break;
AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
FE_AG_REG_AG_MODE_LOP_MODE_E__M));
AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
if (status < 0)
break;
/* set FeAgRegAgAgcSio AGC2 (RF) as input */
{
u16 FeAgRegAgAgcSio = 0;
status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
FeAgRegAgAgcSio &=
~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
FeAgRegAgAgcSio |=
FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
}
} while (0);
}
return status;
}
static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
{
int status = 0;
*pValue = 0;
if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
u16 Value;
status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
Value &= FE_AG_REG_GC1_AGC_DAT__M;
if (status >= 0) {
/* 3.3V
|
R1
|
Vin - R3 - * -- Vout
|
R2
|
GND
*/
u32 R1 = state->if_agc_cfg.R1;
u32 R2 = state->if_agc_cfg.R2;
u32 R3 = state->if_agc_cfg.R3;
u32 Vmax, Rpar, Vmin, Vout;
if (R2 == 0 && (R1 == 0 || R3 == 0))
return 0;
Vmax = (3300 * R2) / (R1 + R2);
Rpar = (R2 * R3) / (R3 + R2);
Vmin = (3300 * Rpar) / (R1 + Rpar);
Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
*pValue = Vout;
}
}
return status;
}
static int load_firmware(struct drxd_state *state, const char *fw_name)
{
const struct firmware *fw;
if (request_firmware(&fw, fw_name, state->dev) < 0) {
printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
return -EIO;
}
state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
if (!state->microcode) {
release_firmware(fw);
return -ENOMEM;
}
state->microcode_length = fw->size;
release_firmware(fw);
return 0;
}
static int DownloadMicrocode(struct drxd_state *state,
const u8 *pMCImage, u32 Length)
{
u8 *pSrc;
u32 Address;
u16 nBlocks;
u16 BlockSize;
int i, status = 0;
pSrc = (u8 *) pMCImage;
/* We're not using Flags */
/* Flags = (pSrc[0] << 8) | pSrc[1]; */
pSrc += sizeof(u16);
nBlocks = (pSrc[0] << 8) | pSrc[1];
pSrc += sizeof(u16);
for (i = 0; i < nBlocks; i++) {
Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
(pSrc[2] << 8) | pSrc[3];
pSrc += sizeof(u32);
BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
pSrc += sizeof(u16);
/* We're not using Flags */
/* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
pSrc += sizeof(u16);
/* We're not using BlockCRC */
/* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
pSrc += sizeof(u16);
status = WriteBlock(state, Address, BlockSize,
pSrc, DRX_I2C_CLEARCRC);
if (status < 0)
break;
pSrc += BlockSize;
}
return status;
}
static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
{
u32 nrRetries = 0;
int status;
status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
if (status < 0)
return status;
do {
nrRetries += 1;
if (nrRetries > DRXD_MAX_RETRIES) {
status = -1;
break;
}
status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
} while (status != 0);
if (status >= 0)
status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
return status;
}
static int HI_CfgCommand(struct drxd_state *state)
{
int status = 0;
mutex_lock(&state->mutex);
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
status = Write16(state, HI_RA_RAM_SRV_CMD__A,
HI_RA_RAM_SRV_CMD_CONFIG, 0);
else
status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
mutex_unlock(&state->mutex);
return status;
}
static int InitHI(struct drxd_state *state)
{
state->hi_cfg_wakeup_key = (state->chip_adr);
/* port/bridge/power down ctrl */
state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
return HI_CfgCommand(state);
}
static int HI_ResetCommand(struct drxd_state *state)
{
int status;
mutex_lock(&state->mutex);
status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
HI_RA_RAM_SRV_RST_KEY_ACT, 0);
if (status == 0)
status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
mutex_unlock(&state->mutex);
msleep(1);
return status;
}
static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
{
state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
if (bEnableBridge)
state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
else
state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
return HI_CfgCommand(state);
}
#define HI_TR_WRITE 0x9
#define HI_TR_READ 0xA
#define HI_TR_READ_WRITE 0xB
#define HI_TR_BROADCAST 0x4
#if 0
static int AtomicReadBlock(struct drxd_state *state,
u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
{
int status;
int i = 0;
/* Parameter check */
if ((!pData) || ((DataSize & 1) != 0))
return -1;
mutex_lock(&state->mutex);
do {
/* Instruct HI to read n bytes */
/* TODO use proper names forthese egisters */
status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
if (status < 0)
break;
status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
if (status < 0)
break;
status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
if (status < 0)
break;
status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
if (status < 0)
break;
status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
if (status < 0)
break;
status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
if (status < 0)
break;
} while (0);
if (status >= 0) {
for (i = 0; i < (DataSize / 2); i += 1) {
u16 word;
status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
&word, 0);
if (status < 0)
break;
pData[2 * i] = (u8) (word & 0xFF);
pData[(2 * i) + 1] = (u8) (word >> 8);
}
}
mutex_unlock(&state->mutex);
return status;
}
static int AtomicReadReg32(struct drxd_state *state,
u32 Addr, u32 *pData, u8 Flags)
{
u8 buf[sizeof(u32)];
int status;
if (!pData)
return -1;
status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
*pData = (((u32) buf[0]) << 0) +
(((u32) buf[1]) << 8) +
(((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
return status;
}
#endif
static int StopAllProcessors(struct drxd_state *state)
{
return Write16(state, HI_COMM_EXEC__A,
SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
}
static int EnableAndResetMB(struct drxd_state *state)
{
if (state->type_A) {
/* disable? monitor bus observe @ EC_OC */
Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
}
/* do inverse broadcast, followed by explicit write to HI */
Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
return 0;
}
static int InitCC(struct drxd_state *state)
{
int status = 0;
if (state->osc_clock_freq == 0 ||
state->osc_clock_freq > 20000 ||
(state->osc_clock_freq % 4000) != 0) {
printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
return -1;
}
status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
status |= Write16(state, CC_REG_PLL_MODE__A,
CC_REG_PLL_MODE_BYPASS_PLL |
CC_REG_PLL_MODE_PUMP_CUR_12, 0);
status |= Write16(state, CC_REG_REF_DIVIDE__A,
state->osc_clock_freq / 4000, 0);
status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
0);
status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
return status;
}
static int ResetECOD(struct drxd_state *state)
{
int status = 0;
if (state->type_A)
status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
else
status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
if (!(status < 0))
status = WriteTable(state, state->m_ResetECRAM);
if (!(status < 0))
status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
return status;
}
/* Configure PGA switch */
static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
{
int status;
u16 AgModeLop = 0;
u16 AgModeHip = 0;
do {
if (pgaSwitch) {
/* PGA on */
/* fine gain */
status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
if (status < 0)
break;
AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
if (status < 0)
break;
/* coarse gain */
status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
if (status < 0)
break;
AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
if (status < 0)
break;
/* enable fine and coarse gain, enable AAF,
no ext resistor */
status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
if (status < 0)
break;
} else {
/* PGA off, bypass */
/* fine gain */
status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
if (status < 0)
break;
AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
if (status < 0)
break;
/* coarse gain */
status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
if (status < 0)
break;
AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
if (status < 0)
break;
/* disable fine and coarse gain, enable AAF,
no ext resistor */
status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
if (status < 0)
break;
}
} while (0);
return status;
}
static int InitFE(struct drxd_state *state)
{
int status;
do {
status = WriteTable(state, state->m_InitFE_1);
if (status < 0)
break;
if (state->type_A) {
status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
0);
} else {
if (state->PGA)
status = SetCfgPga(state, 0);
else
status =
Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
0);
}
if (status < 0)
break;
status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
if (status < 0)
break;
status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
if (status < 0)
break;
status = WriteTable(state, state->m_InitFE_2);
if (status < 0)
break;
} while (0);
return status;
}
static int InitFT(struct drxd_state *state)
{
/*
norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
SC stuff
*/
return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
}
static int SC_WaitForReady(struct drxd_state *state)
{
int i;
for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
if (status == 0)
return status;
}
return -1;
}
static int SC_SendCommand(struct drxd_state *state, u16 cmd)
{
int status = 0, ret;
u16 errCode;
status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
if (status < 0)
return status;
SC_WaitForReady(state);
ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
if (ret < 0 || errCode == 0xFFFF) {
printk(KERN_ERR "Command Error\n");
status = -1;
}
return status;
}
static int SC_ProcStartCommand(struct drxd_state *state,
u16 subCmd, u16 param0, u16 param1)
{
int ret, status = 0;
u16 scExec;
mutex_lock(&state->mutex);
do {
ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
if (ret < 0 || scExec != 1) {
status = -1;
break;
}
SC_WaitForReady(state);
status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
} while (0);
mutex_unlock(&state->mutex);
return status;
}
static int SC_SetPrefParamCommand(struct drxd_state *state,
u16 subCmd, u16 param0, u16 param1)
{
int status;
mutex_lock(&state->mutex);
do {
status = SC_WaitForReady(state);
if (status < 0)
break;
status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
if (status < 0)
break;
status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
if (status < 0)
break;
status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
if (status < 0)
break;
status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
if (status < 0)
break;
} while (0);
mutex_unlock(&state->mutex);
return status;
}
#if 0
static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
{
int status = 0;
mutex_lock(&state->mutex);
do {
status = SC_WaitForReady(state);
if (status < 0)
break;
status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
if (status < 0)
break;
status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
if (status < 0)
break;
} while (0);
mutex_unlock(&state->mutex);
return status;
}
#endif
static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
{
int status;
do {
u16 EcOcRegIprInvMpg = 0;
u16 EcOcRegOcModeLop = 0;
u16 EcOcRegOcModeHip = 0;
u16 EcOcRegOcMpgSio = 0;
/*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
if (state->operation_mode == OM_DVBT_Diversity_Front) {
if (bEnableOutput) {
EcOcRegOcModeHip |=
B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
} else
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
EcOcRegOcModeLop |=
EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
} else {
EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
if (bEnableOutput)
EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
else
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
/* Don't Insert RS Byte */
if (state->insert_rs_byte) {
EcOcRegOcModeLop &=
(~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
EcOcRegOcModeHip &=
(~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
EcOcRegOcModeHip |=
EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
} else {
EcOcRegOcModeLop |=
EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
EcOcRegOcModeHip &=
(~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
EcOcRegOcModeHip |=
EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
}
/* Mode = Parallel */
if (state->enable_parallel)
EcOcRegOcModeLop &=
(~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
else
EcOcRegOcModeLop |=
EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
}
/* Invert Data */
/* EcOcRegIprInvMpg |= 0x00FF; */
EcOcRegIprInvMpg &= (~(0x00FF));
/* Invert Error ( we don't use the pin ) */
/* EcOcRegIprInvMpg |= 0x0100; */
EcOcRegIprInvMpg &= (~(0x0100));
/* Invert Start ( we don't use the pin ) */
/* EcOcRegIprInvMpg |= 0x0200; */
EcOcRegIprInvMpg &= (~(0x0200));
/* Invert Valid ( we don't use the pin ) */
/* EcOcRegIprInvMpg |= 0x0400; */
EcOcRegIprInvMpg &= (~(0x0400));
/* Invert Clock */
/* EcOcRegIprInvMpg |= 0x0800; */
EcOcRegIprInvMpg &= (~(0x0800));
/* EcOcRegOcModeLop =0x05; */
status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
if (status < 0)
break;
} while (0);
return status;
}
static int SetDeviceTypeId(struct drxd_state *state)
{
int status = 0;
u16 deviceId = 0;
do {
status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
if (status < 0)
break;
/* TODO: why twice? */
status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
if (status < 0)
break;
printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
state->type_A = 0;
state->PGA = 0;
state->diversity = 0;
if (deviceId == 0) { /* on A2 only 3975 available */
state->type_A = 1;
printk(KERN_INFO "DRX3975D-A2\n");
} else {
deviceId >>= 12;
printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
switch (deviceId) {
case 4:
state->diversity = 1;
fallthrough;
case 3:
case 7:
state->PGA = 1;
break;
case 6:
state->diversity = 1;
fallthrough;
case 5:
case 8:
break;
default:
status = -1;
break;
}
}
} while (0);
if (status < 0)
return status;
/* Init Table selection */
state->m_InitAtomicRead = DRXD_InitAtomicRead;
state->m_InitSC = DRXD_InitSC;
state->m_ResetECRAM = DRXD_ResetECRAM;
if (state->type_A) {
state->m_ResetCEFR = DRXD_ResetCEFR;
state->m_InitFE_1 = DRXD_InitFEA2_1;
state->m_InitFE_2 = DRXD_InitFEA2_2;
state->m_InitCP = DRXD_InitCPA2;
state->m_InitCE = DRXD_InitCEA2;
state->m_InitEQ = DRXD_InitEQA2;
state->m_InitEC = DRXD_InitECA2;
if (load_firmware(state, DRX_FW_FILENAME_A2))
return -EIO;
} else {
state->m_ResetCEFR = NULL;
state->m_InitFE_1 = DRXD_InitFEB1_1;
state->m_InitFE_2 = DRXD_InitFEB1_2;
state->m_InitCP = DRXD_InitCPB1;
state->m_InitCE = DRXD_InitCEB1;
state->m_InitEQ = DRXD_InitEQB1;
state->m_InitEC = DRXD_InitECB1;
if (load_firmware(state, DRX_FW_FILENAME_B1))
return -EIO;
}
if (state->diversity) {
state->m_InitDiversityFront = DRXD_InitDiversityFront;
state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
state->m_DisableDiversity = DRXD_DisableDiversity;
state->m_StartDiversityFront = DRXD_StartDiversityFront;
state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
} else {
state->m_InitDiversityFront = NULL;
state->m_InitDiversityEnd = NULL;
state->m_DisableDiversity = NULL;
state->m_StartDiversityFront = NULL;
state->m_StartDiversityEnd = NULL;
state->m_DiversityDelay8MHZ = NULL;
state->m_DiversityDelay6MHZ = NULL;
}
return status;
}
static int CorrectSysClockDeviation(struct drxd_state *state)
{
int status;
s32 incr = 0;
s32 nomincr = 0;
u32 bandwidth = 0;
u32 sysClockInHz = 0;
u32 sysClockFreq = 0; /* in kHz */
s16 oscClockDeviation;
s16 Diff;
do {
/* Retrieve bandwidth and incr, sanity check */
/* These accesses should be AtomicReadReg32, but that
causes trouble (at least for diversity */
status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
if (status < 0)
break;
status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
if (status < 0)
break;
if (state->type_A) {
if ((nomincr - incr < -500) || (nomincr - incr > 500))
break;
} else {
if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
break;
}
switch (state->props.bandwidth_hz) {
case 8000000:
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
break;
case 7000000:
bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
break;
case 6000000:
bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
break;
default:
return -1;
}
/* Compute new sysclock value
sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
incr += (1 << 23);
sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
sysClockFreq = (u32) (sysClockInHz / 1000);
/* rounding */
if ((sysClockInHz % 1000) > 500)
sysClockFreq++;
/* Compute clock deviation in ppm */
oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
(s32)
(state->expected_sys_clock_freq)) *
1000000L) /
(s32)
(state->expected_sys_clock_freq));
Diff = oscClockDeviation - state->osc_clock_deviation;
/*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
if (Diff >= -200 && Diff <= 200) {
state->sys_clock_freq = (u16) sysClockFreq;
if (oscClockDeviation != state->osc_clock_deviation) {
if (state->config.osc_deviation) {
state->config.osc_deviation(state->priv,
oscClockDeviation,
1);
state->osc_clock_deviation =
oscClockDeviation;
}
}
/* switch OFF SRMM scan in SC */
status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
if (status < 0)
break;
/* overrule FE_IF internal value for
proper re-locking */
status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
if (status < 0)
break;
state->cscd_state = CSCD_SAVED;
}
} while (0);
return status;
}
static int DRX_Stop(struct drxd_state *state)
{
int status;
if (state->drxd_state != DRXD_STARTED)
return 0;
do {
if (state->cscd_state != CSCD_SAVED) {
u32 lock;
status = DRX_GetLockStatus(state, &lock);
if (status < 0)
break;
}
status = StopOC(state);
if (status < 0)
break;
state->drxd_state = DRXD_STOPPED;
status = ConfigureMPEGOutput(state, 0);
if (status < 0)
break;
if (state->type_A) {
/* Stop relevant processors off the device */
status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
} else {
/* Stop all processors except HI & CC & FE */
status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
if (status < 0)
break;
}
} while (0);
return status;
}
#if 0 /* Currently unused */
static int SetOperationMode(struct drxd_state *state, int oMode)
{
int status;
do {
if (state->drxd_state != DRXD_STOPPED) {
status = -1;
break;
}
if (oMode == state->operation_mode) {
status = 0;
break;
}
if (oMode != OM_Default && !state->diversity) {
status = -1;
break;
}
switch (oMode) {
case OM_DVBT_Diversity_Front:
status = WriteTable(state, state->m_InitDiversityFront);
break;
case OM_DVBT_Diversity_End:
status = WriteTable(state, state->m_InitDiversityEnd);
break;
case OM_Default:
/* We need to check how to
get DRXD out of diversity */
default:
status = WriteTable(state, state->m_DisableDiversity);
break;
}
} while (0);
if (!status)
state->operation_mode = oMode;
return status;
}
#endif
static int StartDiversity(struct drxd_state *state)
{
int status = 0;
u16 rcControl;
do {
if (state->operation_mode == OM_DVBT_Diversity_Front) {
status = WriteTable(state, state->m_StartDiversityFront);
if (status < 0)
break;
} else if (state->operation_mode == OM_DVBT_Diversity_End) {
status = WriteTable(state, state->m_StartDiversityEnd);
if (status < 0)
break;
if (state->props.bandwidth_hz == 8000000) {
status = WriteTable(state, state->m_DiversityDelay8MHZ);
if (status < 0)
break;
} else {
status = WriteTable(state, state->m_DiversityDelay6MHZ);
if (status < 0)
break;
}
status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
if (status < 0)
break;
rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
/* combining enabled */
B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
if (status < 0)
break;
}
} while (0);
return status;
}
static int SetFrequencyShift(struct drxd_state *state,
u32 offsetFreq, int channelMirrored)
{
int negativeShift = (state->tuner_mirrors == channelMirrored);
/* Handle all mirroring
*
* Note: ADC mirroring (aliasing) is implictly handled by limiting
* feFsRegAddInc to 28 bits below
* (if the result before masking is more than 28 bits, this means
* that the ADC is mirroring.
* The masking is in fact the aliasing of the ADC)
*
*/
/* Compute register value, unsigned computation */
state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
offsetFreq,
1 << 28, state->sys_clock_freq);
/* Remove integer part */
state->fe_fs_add_incr &= 0x0FFFFFFFL;
if (negativeShift)
state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
/* Save the frequency shift without tunerOffset compensation
for CtrlGetChannel. */
state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1 << 28, state->sys_clock_freq);
/* Remove integer part */
state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
if (negativeShift)
state->org_fe_fs_add_incr = ((1L << 28) -
state->org_fe_fs_add_incr);
return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
state->fe_fs_add_incr, 0);
}
static int SetCfgNoiseCalibration(struct drxd_state *state,
struct SNoiseCal *noiseCal)
{
u16 beOptEna;
int status = 0;
do {
status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
if (status < 0)
break;
if (noiseCal->cpOpt) {
beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
} else {
beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
if (status < 0)
break;
}
status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
if (status < 0)
break;
if (!state->type_A) {
status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
if (status < 0)
break;
status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
if (status < 0)
break;
}
} while (0);
return status;
}
static int DRX_Start(struct drxd_state *state, s32 off)
{
struct dtv_frontend_properties *p = &state->props;
int status;
u16 transmissionParams = 0;
u16 operationMode = 0;
u16 qpskTdTpsPwr = 0;
u16 qam16TdTpsPwr = 0;
u16 qam64TdTpsPwr = 0;
u32 feIfIncr = 0;
u32 bandwidth = 0;
int mirrorFreqSpect;
u16 qpskSnCeGain = 0;
u16 qam16SnCeGain = 0;
u16 qam64SnCeGain = 0;
u16 qpskIsGainMan = 0;
u16 qam16IsGainMan = 0;
u16 qam64IsGainMan = 0;
u16 qpskIsGainExp = 0;
u16 qam16IsGainExp = 0;
u16 qam64IsGainExp = 0;
u16 bandwidthParam = 0;
if (off < 0)
off = (off - 500) / 1000;
else
off = (off + 500) / 1000;
do {
if (state->drxd_state != DRXD_STOPPED)
return -1;
status = ResetECOD(state);
if (status < 0)
break;
if (state->type_A) {
status = InitSC(state);
if (status < 0)
break;
} else {
status = InitFT(state);
if (status < 0)
break;
status = InitCP(state);
if (status < 0)
break;
status = InitCE(state);
if (status < 0)
break;
status = InitEQ(state);
if (status < 0)
break;
status = InitSC(state);
if (status < 0)
break;
}
/* Restore current IF & RF AGC settings */
status = SetCfgIfAgc(state, &state->if_agc_cfg);
if (status < 0)
break;
status = SetCfgRfAgc(state, &state->rf_agc_cfg);
if (status < 0)
break;
mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
switch (p->transmission_mode) {
default: /* Not set, detect it automatically */
operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
fallthrough; /* try first guess DRX_FFTMODE_8K */
case TRANSMISSION_MODE_8K:
transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
if (state->type_A) {
status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
if (status < 0)
break;
qpskSnCeGain = 99;
qam16SnCeGain = 83;
qam64SnCeGain = 67;
}
break;
case TRANSMISSION_MODE_2K:
transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
if (state->type_A) {
status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
if (status < 0)
break;
qpskSnCeGain = 97;
qam16SnCeGain = 71;
qam64SnCeGain = 65;
}
break;
}
switch (p->guard_interval) {
case GUARD_INTERVAL_1_4:
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
break;
case GUARD_INTERVAL_1_8:
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
break;
case GUARD_INTERVAL_1_16:
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
break;
case GUARD_INTERVAL_1_32:
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
break;
default: /* Not set, detect it automatically */
operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
/* try first guess 1/4 */
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
break;
}
switch (p->hierarchy) {
case HIERARCHY_1:
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
if (status < 0)
break;
qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
qpskIsGainMan =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
qam16IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
qam64IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
qpskIsGainExp =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
qam16IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
qam64IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
}
break;
case HIERARCHY_2:
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
if (status < 0)
break;
qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
qpskIsGainMan =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
qam16IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
qam64IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
qpskIsGainExp =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
qam16IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
qam64IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
}
break;
case HIERARCHY_4:
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
if (status < 0)
break;
qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
qpskIsGainMan =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
qam16IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
qam64IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
qpskIsGainExp =
SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
qam16IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
qam64IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
}
break;
case HIERARCHY_AUTO:
default:
/* Not set, detect it automatically, start with none */
operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
if (status < 0)
break;
qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
qpskIsGainMan =
SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
qam16IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
qam64IsGainMan =
SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
qpskIsGainExp =
SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
qam16IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
qam64IsGainExp =
SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
}
break;
}
if (status < 0)
break;
switch (p->modulation) {
default:
operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */
case QAM_64:
transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
if (status < 0)
break;
}
break;
case QPSK:
transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
if (status < 0)
break;
}
break;
case QAM_16:
transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
if (state->type_A) {
status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
if (status < 0)
break;
status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
if (status < 0)
break;
status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
if (status < 0)
break;
}
break;
}
if (status < 0)
break;
switch (DRX_CHANNEL_HIGH) {
default:
case DRX_CHANNEL_AUTO:
case DRX_CHANNEL_LOW:
transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
break;
case DRX_CHANNEL_HIGH:
transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
break;
}
switch (p->code_rate_HP) {
case FEC_1_2:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
if (state->type_A)
status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
break;
default:
operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
fallthrough;
case FEC_2_3:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
if (state->type_A)
status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
break;
case FEC_3_4:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
if (state->type_A)
status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
break;
case FEC_5_6:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
if (state->type_A)
status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
break;
case FEC_7_8:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
if (state->type_A)
status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
break;
}
if (status < 0)
break;
/* First determine real bandwidth (Hz) */
/* Also set delay for impulse noise cruncher (only A2) */
/* Also set parameters for EC_OC fix, note
EC_OC_REG_TMD_HIL_MAR is changed
by SC for fix for some 8K,1/8 guard but is restored by
InitEC and ResetEC
functions */
switch (p->bandwidth_hz) {
case 0:
p->bandwidth_hz = 8000000;
fallthrough;
case 8000000:
/* (64/7)*(8/8)*1000000 */
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
bandwidthParam = 0;
status = Write16(state,
FE_AG_REG_IND_DEL__A, 50, 0x0000);
break;
case 7000000:
/* (64/7)*(7/8)*1000000 */
bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
status = Write16(state,
FE_AG_REG_IND_DEL__A, 59, 0x0000);
break;
case 6000000:
/* (64/7)*(6/8)*1000000 */
bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
status = Write16(state,
FE_AG_REG_IND_DEL__A, 71, 0x0000);
break;
default:
status = -EINVAL;
}
if (status < 0)
break;
status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
if (status < 0)
break;
{
u16 sc_config;
status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
if (status < 0)
break;
/* enable SLAVE mode in 2k 1/32 to
prevent timing change glitches */
if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
(p->guard_interval == GUARD_INTERVAL_1_32)) {
/* enable slave */
sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
} else {
/* disable slave */
sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
}
status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
if (status < 0)
break;
}
status = SetCfgNoiseCalibration(state, &state->noise_cal);
if (status < 0)
break;
if (state->cscd_state == CSCD_INIT) {
/* switch on SRMM scan in SC */
status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
if (status < 0)
break;
/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
state->cscd_state = CSCD_SET;
}
/* Now compute FE_IF_REG_INCR */
/*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
((SysFreq / BandWidth) * (2^21) ) - (2^23) */
feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
(1ULL << 21), bandwidth) - (1 << 23);
status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
if (status < 0)
break;
status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
if (status < 0)
break;
/* Bandwidth setting done */
/* Mirror & frequency offset */
SetFrequencyShift(state, off, mirrorFreqSpect);
/* Start SC, write channel settings to SC */
/* Enable SC after setting all other parameters */
status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
if (status < 0)
break;
status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
if (status < 0)
break;
/* Write SC parameter registers, operation mode */
#if 1
operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
SC_RA_RAM_OP_AUTO_GUARD__M |
SC_RA_RAM_OP_AUTO_CONST__M |
SC_RA_RAM_OP_AUTO_HIER__M |
SC_RA_RAM_OP_AUTO_RATE__M);
#endif
status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
if (status < 0)
break;
/* Start correct processes to get in lock */
status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
if (status < 0)
break;
status = StartOC(state);
if (status < 0)
break;
if (state->operation_mode != OM_Default) {
status = StartDiversity(state);
if (status < 0)
break;
}
state->drxd_state = DRXD_STARTED;
} while (0);
return status;
}
static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
{
u32 ulRfAgcOutputLevel = 0xffffffff;
u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
u32 ulRfAgcMinLevel = 0; /* Currently unused */
u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
u32 ulRfAgcSpeed = 0; /* Currently unused */
u32 ulRfAgcMode = 0; /*2; Off */
u32 ulRfAgcR1 = 820;
u32 ulRfAgcR2 = 2200;
u32 ulRfAgcR3 = 150;
u32 ulIfAgcMode = 0; /* Auto */
u32 ulIfAgcOutputLevel = 0xffffffff;
u32 ulIfAgcSettleLevel = 0xffffffff;
u32 ulIfAgcMinLevel = 0xffffffff;
u32 ulIfAgcMaxLevel = 0xffffffff;
u32 ulIfAgcSpeed = 0xffffffff;
u32 ulIfAgcR1 = 820;
u32 ulIfAgcR2 = 2200;
u32 ulIfAgcR3 = 150;
u32 ulClock = state->config.clock;
u32 ulSerialMode = 0;
u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
u32 ulHiI2cDelay = HI_I2C_DELAY;
u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
u32 ulHiI2cPatch = 0;
u32 ulEnvironment = APPENV_PORTABLE;
u32 ulEnvironmentDiversity = APPENV_MOBILE;
u32 ulIFFilter = IFFILTER_SAW;
state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
state->if_agc_cfg.outputLevel = 0;
state->if_agc_cfg.settleLevel = 140;
state->if_agc_cfg.minOutputLevel = 0;
state->if_agc_cfg.maxOutputLevel = 1023;
state->if_agc_cfg.speed = 904;
if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
}
if (ulIfAgcMode == 0 &&
ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
}
state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
/* rest of the RFAgcCfg structure currently unused */
if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
}
if (ulRfAgcMode == 0 &&
ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
}
if (ulRfAgcMode == 2)
state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
if (ulEnvironment <= 2)
state->app_env_default = (enum app_env)
(ulEnvironment);
if (ulEnvironmentDiversity <= 2)
state->app_env_diversity = (enum app_env)
(ulEnvironmentDiversity);
if (ulIFFilter == IFFILTER_DISCRETE) {
/* discrete filter */
state->noise_cal.cpOpt = 0;
state->noise_cal.cpNexpOfs = 40;
state->noise_cal.tdCal2k = -40;
state->noise_cal.tdCal8k = -24;
} else {
/* SAW filter */
state->noise_cal.cpOpt = 1;
state->noise_cal.cpNexpOfs = 0;
state->noise_cal.tdCal2k = -21;
state->noise_cal.tdCal8k = -24;
}
state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
state->chip_adr = (state->config.demod_address << 1) | 1;
switch (ulHiI2cPatch) {
case 1:
state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
break;
case 3:
state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
break;
default:
state->m_HiI2cPatch = NULL;
}
/* modify tuner and clock attributes */
state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
/* expected system clock frequency in kHz */
state->expected_sys_clock_freq = 48000;
/* real system clock frequency in kHz */
state->sys_clock_freq = 48000;
state->osc_clock_freq = (u16) ulClock;
state->osc_clock_deviation = 0;
state->cscd_state = CSCD_INIT;
state->drxd_state = DRXD_UNINITIALIZED;
state->PGA = 0;
state->type_A = 0;
state->tuner_mirrors = 0;
/* modify MPEG output attributes */
state->insert_rs_byte = state->config.insert_rs_byte;
state->enable_parallel = (ulSerialMode != 1);
/* Timing div, 250ns/Psys */
/* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
ulHiI2cDelay) / 1000;
/* Bridge delay, uses oscilator clock */
/* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
ulHiI2cBridgeDelay) / 1000;
state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
/* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
return 0;
}
static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
{
int status = 0;
u32 driverVersion;
if (state->init_done)
return 0;
CDRXD(state, state->config.IF ? state->config.IF : 36000000);
do {
state->operation_mode = OM_Default;
status = SetDeviceTypeId(state);
if (status < 0)
break;
/* Apply I2c address patch to B1 */
if (!state->type_A && state->m_HiI2cPatch) {
status = WriteTable(state, state->m_HiI2cPatch);
if (status < 0)
break;
}
if (state->type_A) {
/* HI firmware patch for UIO readout,
avoid clearing of result register */
status = Write16(state, 0x43012D, 0x047f, 0);
if (status < 0)
break;
}
status = HI_ResetCommand(state);
if (status < 0)
break;
status = StopAllProcessors(state);
if (status < 0)
break;
status = InitCC(state);
if (status < 0)
break;
state->osc_clock_deviation = 0;
if (state->config.osc_deviation)
state->osc_clock_deviation =
state->config.osc_deviation(state->priv, 0, 0);
{
/* Handle clock deviation */
s32 devB;
s32 devA = (s32) (state->osc_clock_deviation) *
(s32) (state->expected_sys_clock_freq);
/* deviation in kHz */
s32 deviation = (devA / (1000000L));
/* rounding, signed */
if (devA > 0)
devB = (2);
else
devB = (-2);
if ((devB * (devA % 1000000L) > 1000000L)) {
/* add +1 or -1 */
deviation += (devB / 2);
}
state->sys_clock_freq =
(u16) ((state->expected_sys_clock_freq) +
deviation);
}
status = InitHI(state);
if (status < 0)
break;
status = InitAtomicRead(state);
if (status < 0)
break;
status = EnableAndResetMB(state);
if (status < 0)
break;
if (state->type_A) {
status = ResetCEFR(state);
if (status < 0)
break;
}
if (fw) {
status = DownloadMicrocode(state, fw, fw_size);
if (status < 0)
break;
} else {
status = DownloadMicrocode(state, state->microcode, state->microcode_length);
if (status < 0)
break;
}
if (state->PGA) {
state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
SetCfgPga(state, 0); /* PGA = 0 dB */
} else {
state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
}
state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
status = InitFE(state);
if (status < 0)
break;
status = InitFT(state);
if (status < 0)
break;
status = InitCP(state);
if (status < 0)
break;
status = InitCE(state);
if (status < 0)
break;
status = InitEQ(state);
if (status < 0)
break;
status = InitEC(state);
if (status < 0)
break;
status = InitSC(state);
if (status < 0)
break;
status = SetCfgIfAgc(state, &state->if_agc_cfg);
if (status < 0)
break;
status = SetCfgRfAgc(state, &state->rf_agc_cfg);
if (status < 0)
break;
state->cscd_state = CSCD_INIT;
status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
if (status < 0)
break;
driverVersion = (((VERSION_MAJOR / 10) << 4) +
(VERSION_MAJOR % 10)) << 24;
driverVersion += (((VERSION_MINOR / 10) << 4) +
(VERSION_MINOR % 10)) << 16;
driverVersion += ((VERSION_PATCH / 1000) << 12) +
((VERSION_PATCH / 100) << 8) +
((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
if (status < 0)
break;
status = StopOC(state);
if (status < 0)
break;
state->drxd_state = DRXD_STOPPED;
state->init_done = 1;
status = 0;
} while (0);
return status;
}
static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
{
DRX_GetLockStatus(state, pLockStatus);
/*if (*pLockStatus&DRX_LOCK_MPEG) */
if (*pLockStatus & DRX_LOCK_FEC) {
ConfigureMPEGOutput(state, 1);
/* Get status again, in case we have MPEG lock now */
/*DRX_GetLockStatus(state, pLockStatus); */
}
return 0;
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct drxd_state *state = fe->demodulator_priv;
u32 value;
int res;
res = ReadIFAgc(state, &value);
if (res < 0)
*strength = 0;
else
*strength = 0xffff - (value << 4);
return 0;
}
static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct drxd_state *state = fe->demodulator_priv;
u32 lock;
DRXD_status(state, &lock);
*status = 0;
/* No MPEG lock in V255 firmware, bug ? */
#if 1
if (lock & DRX_LOCK_MPEG)
*status |= FE_HAS_LOCK;
#else
if (lock & DRX_LOCK_FEC)
*status |= FE_HAS_LOCK;
#endif
if (lock & DRX_LOCK_FEC)
*status |= FE_HAS_VITERBI | FE_HAS_SYNC;
if (lock & DRX_LOCK_DEMOD)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
return 0;
}
static int drxd_init(struct dvb_frontend *fe)
{
struct drxd_state *state = fe->demodulator_priv;
return DRXD_init(state, NULL, 0);
}
static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
{
struct drxd_state *state = fe->demodulator_priv;
if (state->config.disable_i2c_gate_ctrl == 1)
return 0;
return DRX_ConfigureI2CBridge(state, onoff);
}
static int drxd_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *sets)
{
sets->min_delay_ms = 10000;
sets->max_drift = 0;
sets->step_size = 0;
return 0;
}
static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
{
*ber = 0;
return 0;
}
static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
{
*snr = 0;
return 0;
}
static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
*ucblocks = 0;
return 0;
}
static int drxd_sleep(struct dvb_frontend *fe)
{
struct drxd_state *state = fe->demodulator_priv;
ConfigureMPEGOutput(state, 0);
return 0;
}
static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
return drxd_config_i2c(fe, enable);
}
static int drxd_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct drxd_state *state = fe->demodulator_priv;
s32 off = 0;
state->props = *p;
DRX_Stop(state);
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
msleep(200);
return DRX_Start(state, off);
}
static void drxd_release(struct dvb_frontend *fe)
{
struct drxd_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops drxd_ops = {
.delsys = { SYS_DVBT},
.info = {
.name = "Micronas DRXD DVB-T",
.frequency_min_hz = 47125 * kHz,
.frequency_max_hz = 855250 * kHz,
.frequency_stepsize_hz = 166667,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
.release = drxd_release,
.init = drxd_init,
.sleep = drxd_sleep,
.i2c_gate_ctrl = drxd_i2c_gate_ctrl,
.set_frontend = drxd_set_frontend,
.get_tune_settings = drxd_get_tune_settings,
.read_status = drxd_read_status,
.read_ber = drxd_read_ber,
.read_signal_strength = drxd_read_signal_strength,
.read_snr = drxd_read_snr,
.read_ucblocks = drxd_read_ucblocks,
};
struct dvb_frontend *drxd_attach(const struct drxd_config *config,
void *priv, struct i2c_adapter *i2c,
struct device *dev)
{
struct drxd_state *state = NULL;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
state->ops = drxd_ops;
state->dev = dev;
state->config = *config;
state->i2c = i2c;
state->priv = priv;
mutex_init(&state->mutex);
if (Read16(state, 0, NULL, 0) < 0)
goto error;
state->frontend.ops = drxd_ops;
state->frontend.demodulator_priv = state;
ConfigureMPEGOutput(state, 0);
/* add few initialization to allow gate control */
CDRXD(state, state->config.IF ? state->config.IF : 36000000);
InitHI(state);
return &state->frontend;
error:
printk(KERN_ERR "drxd: not found\n");
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(drxd_attach);
MODULE_DESCRIPTION("DRXD driver");
MODULE_AUTHOR("Micronas");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/drxd_hard.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Conexant cx24117/cx24132 - Dual DVBS/S2 Satellite demod/tuner driver
Copyright (C) 2013 Luis Alves <[email protected]>
July, 6th 2013
First release based on cx24116 driver by:
Steven Toth and Georg Acher, Darron Broad, Igor Liplianin
Cards currently supported:
TBS6980 - Dual DVBS/S2 PCIe card
TBS6981 - Dual DVBS/S2 PCIe card
*/
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include "tuner-i2c.h"
#include <media/dvb_frontend.h>
#include "cx24117.h"
#define CX24117_DEFAULT_FIRMWARE "dvb-fe-cx24117.fw"
#define CX24117_SEARCH_RANGE_KHZ 5000
/* known registers */
#define CX24117_REG_COMMAND (0x00) /* command buffer */
#define CX24117_REG_EXECUTE (0x1f) /* execute command */
#define CX24117_REG_FREQ3_0 (0x34) /* frequency */
#define CX24117_REG_FREQ2_0 (0x35)
#define CX24117_REG_FREQ1_0 (0x36)
#define CX24117_REG_STATE0 (0x39)
#define CX24117_REG_SSTATUS0 (0x3a) /* demod0 signal high / status */
#define CX24117_REG_SIGNAL0 (0x3b)
#define CX24117_REG_FREQ5_0 (0x3c) /* +-freq */
#define CX24117_REG_FREQ6_0 (0x3d)
#define CX24117_REG_SRATE2_0 (0x3e) /* +- 1000 * srate */
#define CX24117_REG_SRATE1_0 (0x3f)
#define CX24117_REG_QUALITY2_0 (0x40)
#define CX24117_REG_QUALITY1_0 (0x41)
#define CX24117_REG_BER4_0 (0x47)
#define CX24117_REG_BER3_0 (0x48)
#define CX24117_REG_BER2_0 (0x49)
#define CX24117_REG_BER1_0 (0x4a)
#define CX24117_REG_DVBS_UCB2_0 (0x4b)
#define CX24117_REG_DVBS_UCB1_0 (0x4c)
#define CX24117_REG_DVBS2_UCB2_0 (0x50)
#define CX24117_REG_DVBS2_UCB1_0 (0x51)
#define CX24117_REG_QSTATUS0 (0x93)
#define CX24117_REG_CLKDIV0 (0xe6)
#define CX24117_REG_RATEDIV0 (0xf0)
#define CX24117_REG_FREQ3_1 (0x55) /* frequency */
#define CX24117_REG_FREQ2_1 (0x56)
#define CX24117_REG_FREQ1_1 (0x57)
#define CX24117_REG_STATE1 (0x5a)
#define CX24117_REG_SSTATUS1 (0x5b) /* demod1 signal high / status */
#define CX24117_REG_SIGNAL1 (0x5c)
#define CX24117_REG_FREQ5_1 (0x5d) /* +- freq */
#define CX24117_REG_FREQ4_1 (0x5e)
#define CX24117_REG_SRATE2_1 (0x5f)
#define CX24117_REG_SRATE1_1 (0x60)
#define CX24117_REG_QUALITY2_1 (0x61)
#define CX24117_REG_QUALITY1_1 (0x62)
#define CX24117_REG_BER4_1 (0x68)
#define CX24117_REG_BER3_1 (0x69)
#define CX24117_REG_BER2_1 (0x6a)
#define CX24117_REG_BER1_1 (0x6b)
#define CX24117_REG_DVBS_UCB2_1 (0x6c)
#define CX24117_REG_DVBS_UCB1_1 (0x6d)
#define CX24117_REG_DVBS2_UCB2_1 (0x71)
#define CX24117_REG_DVBS2_UCB1_1 (0x72)
#define CX24117_REG_QSTATUS1 (0x9f)
#define CX24117_REG_CLKDIV1 (0xe7)
#define CX24117_REG_RATEDIV1 (0xf1)
/* arg buffer size */
#define CX24117_ARGLEN (0x1e)
/* rolloff */
#define CX24117_ROLLOFF_020 (0x00)
#define CX24117_ROLLOFF_025 (0x01)
#define CX24117_ROLLOFF_035 (0x02)
/* pilot bit */
#define CX24117_PILOT_OFF (0x00)
#define CX24117_PILOT_ON (0x40)
#define CX24117_PILOT_AUTO (0x80)
/* signal status */
#define CX24117_HAS_SIGNAL (0x01)
#define CX24117_HAS_CARRIER (0x02)
#define CX24117_HAS_VITERBI (0x04)
#define CX24117_HAS_SYNCLOCK (0x08)
#define CX24117_STATUS_MASK (0x0f)
#define CX24117_SIGNAL_MASK (0xc0)
/* arg offset for DiSEqC */
#define CX24117_DISEQC_DEMOD (1)
#define CX24117_DISEQC_BURST (2)
#define CX24117_DISEQC_ARG3_2 (3) /* unknown value=2 */
#define CX24117_DISEQC_ARG4_0 (4) /* unknown value=0 */
#define CX24117_DISEQC_ARG5_0 (5) /* unknown value=0 */
#define CX24117_DISEQC_MSGLEN (6)
#define CX24117_DISEQC_MSGOFS (7)
/* DiSEqC burst */
#define CX24117_DISEQC_MINI_A (0)
#define CX24117_DISEQC_MINI_B (1)
#define CX24117_PNE (0) /* 0 disabled / 2 enabled */
#define CX24117_OCC (1) /* 0 disabled / 1 enabled */
enum cmds {
CMD_SET_VCOFREQ = 0x10,
CMD_TUNEREQUEST = 0x11,
CMD_GLOBAL_MPEGCFG = 0x13,
CMD_MPEGCFG = 0x14,
CMD_TUNERINIT = 0x15,
CMD_GET_SRATE = 0x18,
CMD_SET_GOLDCODE = 0x19,
CMD_GET_AGCACC = 0x1a,
CMD_DEMODINIT = 0x1b,
CMD_GETCTLACC = 0x1c,
CMD_LNBCONFIG = 0x20,
CMD_LNBSEND = 0x21,
CMD_LNBDCLEVEL = 0x22,
CMD_LNBPCBCONFIG = 0x23,
CMD_LNBSENDTONEBST = 0x24,
CMD_LNBUPDREPLY = 0x25,
CMD_SET_GPIOMODE = 0x30,
CMD_SET_GPIOEN = 0x31,
CMD_SET_GPIODIR = 0x32,
CMD_SET_GPIOOUT = 0x33,
CMD_ENABLERSCORR = 0x34,
CMD_FWVERSION = 0x35,
CMD_SET_SLEEPMODE = 0x36,
CMD_BERCTRL = 0x3c,
CMD_EVENTCTRL = 0x3d,
};
static LIST_HEAD(hybrid_tuner_instance_list);
static DEFINE_MUTEX(cx24117_list_mutex);
/* The Demod/Tuner can't easily provide these, we cache them */
struct cx24117_tuning {
u32 frequency;
u32 symbol_rate;
enum fe_spectral_inversion inversion;
enum fe_code_rate fec;
enum fe_delivery_system delsys;
enum fe_modulation modulation;
enum fe_pilot pilot;
enum fe_rolloff rolloff;
/* Demod values */
u8 fec_val;
u8 fec_mask;
u8 inversion_val;
u8 pilot_val;
u8 rolloff_val;
};
/* Basic commands that are sent to the firmware */
struct cx24117_cmd {
u8 len;
u8 args[CX24117_ARGLEN];
};
/* common to both fe's */
struct cx24117_priv {
u8 demod_address;
struct i2c_adapter *i2c;
u8 skip_fw_load;
struct mutex fe_lock;
/* Used for sharing this struct between demods */
struct tuner_i2c_props i2c_props;
struct list_head hybrid_tuner_instance_list;
};
/* one per each fe */
struct cx24117_state {
struct cx24117_priv *priv;
struct dvb_frontend frontend;
struct cx24117_tuning dcur;
struct cx24117_tuning dnxt;
struct cx24117_cmd dsec_cmd;
int demod;
};
/* modfec (modulation and FEC) lookup table */
/* Check cx24116.c for a detailed description of each field */
static struct cx24117_modfec {
enum fe_delivery_system delivery_system;
enum fe_modulation modulation;
enum fe_code_rate fec;
u8 mask; /* In DVBS mode this is used to autodetect */
u8 val; /* Passed to the firmware to indicate mode selection */
} cx24117_modfec_modes[] = {
/* QPSK. For unknown rates we set hardware to auto detect 0xfe 0x30 */
/*mod fec mask val */
{ SYS_DVBS, QPSK, FEC_NONE, 0xfe, 0x30 },
{ SYS_DVBS, QPSK, FEC_1_2, 0x02, 0x2e }, /* 00000010 00101110 */
{ SYS_DVBS, QPSK, FEC_2_3, 0x04, 0x2f }, /* 00000100 00101111 */
{ SYS_DVBS, QPSK, FEC_3_4, 0x08, 0x30 }, /* 00001000 00110000 */
{ SYS_DVBS, QPSK, FEC_4_5, 0xfe, 0x30 }, /* 000?0000 ? */
{ SYS_DVBS, QPSK, FEC_5_6, 0x20, 0x31 }, /* 00100000 00110001 */
{ SYS_DVBS, QPSK, FEC_6_7, 0xfe, 0x30 }, /* 0?000000 ? */
{ SYS_DVBS, QPSK, FEC_7_8, 0x80, 0x32 }, /* 10000000 00110010 */
{ SYS_DVBS, QPSK, FEC_8_9, 0xfe, 0x30 }, /* 0000000? ? */
{ SYS_DVBS, QPSK, FEC_AUTO, 0xfe, 0x30 },
/* NBC-QPSK */
{ SYS_DVBS2, QPSK, FEC_NONE, 0x00, 0x00 },
{ SYS_DVBS2, QPSK, FEC_1_2, 0x00, 0x04 },
{ SYS_DVBS2, QPSK, FEC_3_5, 0x00, 0x05 },
{ SYS_DVBS2, QPSK, FEC_2_3, 0x00, 0x06 },
{ SYS_DVBS2, QPSK, FEC_3_4, 0x00, 0x07 },
{ SYS_DVBS2, QPSK, FEC_4_5, 0x00, 0x08 },
{ SYS_DVBS2, QPSK, FEC_5_6, 0x00, 0x09 },
{ SYS_DVBS2, QPSK, FEC_8_9, 0x00, 0x0a },
{ SYS_DVBS2, QPSK, FEC_9_10, 0x00, 0x0b },
{ SYS_DVBS2, QPSK, FEC_AUTO, 0x00, 0x00 },
/* 8PSK */
{ SYS_DVBS2, PSK_8, FEC_NONE, 0x00, 0x00 },
{ SYS_DVBS2, PSK_8, FEC_3_5, 0x00, 0x0c },
{ SYS_DVBS2, PSK_8, FEC_2_3, 0x00, 0x0d },
{ SYS_DVBS2, PSK_8, FEC_3_4, 0x00, 0x0e },
{ SYS_DVBS2, PSK_8, FEC_5_6, 0x00, 0x0f },
{ SYS_DVBS2, PSK_8, FEC_8_9, 0x00, 0x10 },
{ SYS_DVBS2, PSK_8, FEC_9_10, 0x00, 0x11 },
{ SYS_DVBS2, PSK_8, FEC_AUTO, 0x00, 0x00 },
/*
* 'val' can be found in the FECSTATUS register when tuning.
* FECSTATUS will give the actual FEC in use if tuning was successful.
*/
};
static int cx24117_writereg(struct cx24117_state *state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->priv->demod_address,
.flags = 0, .buf = buf, .len = 2 };
int ret;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d i2c wr @0x%02x=0x%02x\n",
__func__, state->demod, reg, data);
ret = i2c_transfer(state->priv->i2c, &msg, 1);
if (ret < 0) {
dev_warn(&state->priv->i2c->dev,
"%s: demod%d i2c wr err(%i) @0x%02x=0x%02x\n",
KBUILD_MODNAME, state->demod, ret, reg, data);
return ret;
}
return 0;
}
static int cx24117_writecmd(struct cx24117_state *state,
struct cx24117_cmd *cmd)
{
struct i2c_msg msg;
u8 buf[CX24117_ARGLEN+1];
int ret;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d i2c wr cmd len=%d\n",
__func__, state->demod, cmd->len);
buf[0] = CX24117_REG_COMMAND;
memcpy(&buf[1], cmd->args, cmd->len);
msg.addr = state->priv->demod_address;
msg.flags = 0;
msg.len = cmd->len+1;
msg.buf = buf;
ret = i2c_transfer(state->priv->i2c, &msg, 1);
if (ret < 0) {
dev_warn(&state->priv->i2c->dev,
"%s: demod%d i2c wr cmd err(%i) len=%d\n",
KBUILD_MODNAME, state->demod, ret, cmd->len);
return ret;
}
return 0;
}
static int cx24117_readreg(struct cx24117_state *state, u8 reg)
{
int ret;
u8 recv = 0;
struct i2c_msg msg[] = {
{ .addr = state->priv->demod_address, .flags = 0,
.buf = ®, .len = 1 },
{ .addr = state->priv->demod_address, .flags = I2C_M_RD,
.buf = &recv, .len = 1 }
};
ret = i2c_transfer(state->priv->i2c, msg, 2);
if (ret < 0) {
dev_warn(&state->priv->i2c->dev,
"%s: demod%d i2c rd err(%d) @0x%x\n",
KBUILD_MODNAME, state->demod, ret, reg);
return ret;
}
dev_dbg(&state->priv->i2c->dev, "%s() demod%d i2c rd @0x%02x=0x%02x\n",
__func__, state->demod, reg, recv);
return recv;
}
static int cx24117_readregN(struct cx24117_state *state,
u8 reg, u8 *buf, int len)
{
int ret;
struct i2c_msg msg[] = {
{ .addr = state->priv->demod_address, .flags = 0,
.buf = ®, .len = 1 },
{ .addr = state->priv->demod_address, .flags = I2C_M_RD,
.buf = buf, .len = len }
};
ret = i2c_transfer(state->priv->i2c, msg, 2);
if (ret < 0) {
dev_warn(&state->priv->i2c->dev,
"%s: demod%d i2c rd err(%d) @0x%x\n",
KBUILD_MODNAME, state->demod, ret, reg);
return ret;
}
return 0;
}
static int cx24117_set_inversion(struct cx24117_state *state,
enum fe_spectral_inversion inversion)
{
dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n",
__func__, inversion, state->demod);
switch (inversion) {
case INVERSION_OFF:
state->dnxt.inversion_val = 0x00;
break;
case INVERSION_ON:
state->dnxt.inversion_val = 0x04;
break;
case INVERSION_AUTO:
state->dnxt.inversion_val = 0x0C;
break;
default:
return -EINVAL;
}
state->dnxt.inversion = inversion;
return 0;
}
static int cx24117_lookup_fecmod(struct cx24117_state *state,
enum fe_delivery_system d, enum fe_modulation m, enum fe_code_rate f)
{
int i, ret = -EINVAL;
dev_dbg(&state->priv->i2c->dev,
"%s(demod(0x%02x,0x%02x) demod%d\n",
__func__, m, f, state->demod);
for (i = 0; i < ARRAY_SIZE(cx24117_modfec_modes); i++) {
if ((d == cx24117_modfec_modes[i].delivery_system) &&
(m == cx24117_modfec_modes[i].modulation) &&
(f == cx24117_modfec_modes[i].fec)) {
ret = i;
break;
}
}
return ret;
}
static int cx24117_set_fec(struct cx24117_state *state,
enum fe_delivery_system delsys,
enum fe_modulation mod,
enum fe_code_rate fec)
{
int ret;
dev_dbg(&state->priv->i2c->dev,
"%s(0x%02x,0x%02x) demod%d\n",
__func__, mod, fec, state->demod);
ret = cx24117_lookup_fecmod(state, delsys, mod, fec);
if (ret < 0)
return ret;
state->dnxt.fec = fec;
state->dnxt.fec_val = cx24117_modfec_modes[ret].val;
state->dnxt.fec_mask = cx24117_modfec_modes[ret].mask;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d mask/val = 0x%02x/0x%02x\n", __func__,
state->demod, state->dnxt.fec_mask, state->dnxt.fec_val);
return 0;
}
static int cx24117_set_symbolrate(struct cx24117_state *state, u32 rate)
{
dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n",
__func__, rate, state->demod);
state->dnxt.symbol_rate = rate;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d symbol_rate = %d\n",
__func__, state->demod, rate);
return 0;
}
static int cx24117_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw);
static int cx24117_firmware_ondemand(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
const struct firmware *fw;
int ret = 0;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d skip_fw_load=%d\n",
__func__, state->demod, state->priv->skip_fw_load);
if (state->priv->skip_fw_load)
return 0;
/* check if firmware is already running */
if (cx24117_readreg(state, 0xeb) != 0xa) {
/* Load firmware */
/* request the firmware, this will block until loaded */
dev_dbg(&state->priv->i2c->dev,
"%s: Waiting for firmware upload (%s)...\n",
__func__, CX24117_DEFAULT_FIRMWARE);
ret = request_firmware(&fw, CX24117_DEFAULT_FIRMWARE,
state->priv->i2c->dev.parent);
dev_dbg(&state->priv->i2c->dev,
"%s: Waiting for firmware upload(2)...\n", __func__);
if (ret) {
dev_err(&state->priv->i2c->dev,
"%s: No firmware uploaded (timeout or file not found?)\n",
__func__);
return ret;
}
/* Make sure we don't recurse back through here
* during loading */
state->priv->skip_fw_load = 1;
ret = cx24117_load_firmware(fe, fw);
if (ret)
dev_err(&state->priv->i2c->dev,
"%s: Writing firmware failed\n", __func__);
release_firmware(fw);
dev_info(&state->priv->i2c->dev,
"%s: Firmware upload %s\n", __func__,
ret == 0 ? "complete" : "failed");
/* Ensure firmware is always loaded if required */
state->priv->skip_fw_load = 0;
}
return ret;
}
/* Take a basic firmware command structure, format it
* and forward it for processing
*/
static int cx24117_cmd_execute_nolock(struct dvb_frontend *fe,
struct cx24117_cmd *cmd)
{
struct cx24117_state *state = fe->demodulator_priv;
int i, ret;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n",
__func__, state->demod);
/* Load the firmware if required */
ret = cx24117_firmware_ondemand(fe);
if (ret != 0)
return ret;
/* Write the command */
cx24117_writecmd(state, cmd);
/* Start execution and wait for cmd to terminate */
cx24117_writereg(state, CX24117_REG_EXECUTE, 0x01);
i = 0;
while (cx24117_readreg(state, CX24117_REG_EXECUTE)) {
msleep(20);
if (i++ > 40) {
/* Avoid looping forever if the firmware does
not respond */
dev_warn(&state->priv->i2c->dev,
"%s() Firmware not responding\n", __func__);
return -EIO;
}
}
return 0;
}
static int cx24117_cmd_execute(struct dvb_frontend *fe, struct cx24117_cmd *cmd)
{
struct cx24117_state *state = fe->demodulator_priv;
int ret;
mutex_lock(&state->priv->fe_lock);
ret = cx24117_cmd_execute_nolock(fe, cmd);
mutex_unlock(&state->priv->fe_lock);
return ret;
}
static int cx24117_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
int i, ret;
unsigned char vers[4];
struct i2c_msg msg;
u8 *buf;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d FW is %zu bytes (%02x %02x .. %02x %02x)\n",
__func__, state->demod, fw->size, fw->data[0], fw->data[1],
fw->data[fw->size - 2], fw->data[fw->size - 1]);
cx24117_writereg(state, 0xea, 0x00);
cx24117_writereg(state, 0xea, 0x01);
cx24117_writereg(state, 0xea, 0x00);
cx24117_writereg(state, 0xce, 0x92);
cx24117_writereg(state, 0xfb, 0x00);
cx24117_writereg(state, 0xfc, 0x00);
cx24117_writereg(state, 0xc3, 0x04);
cx24117_writereg(state, 0xc4, 0x04);
cx24117_writereg(state, 0xce, 0x00);
cx24117_writereg(state, 0xcf, 0x00);
cx24117_writereg(state, 0xea, 0x00);
cx24117_writereg(state, 0xeb, 0x0c);
cx24117_writereg(state, 0xec, 0x06);
cx24117_writereg(state, 0xed, 0x05);
cx24117_writereg(state, 0xee, 0x03);
cx24117_writereg(state, 0xef, 0x05);
cx24117_writereg(state, 0xf3, 0x03);
cx24117_writereg(state, 0xf4, 0x44);
cx24117_writereg(state, CX24117_REG_RATEDIV0, 0x04);
cx24117_writereg(state, CX24117_REG_CLKDIV0, 0x02);
cx24117_writereg(state, CX24117_REG_RATEDIV1, 0x04);
cx24117_writereg(state, CX24117_REG_CLKDIV1, 0x02);
cx24117_writereg(state, 0xf2, 0x04);
cx24117_writereg(state, 0xe8, 0x02);
cx24117_writereg(state, 0xea, 0x01);
cx24117_writereg(state, 0xc8, 0x00);
cx24117_writereg(state, 0xc9, 0x00);
cx24117_writereg(state, 0xca, 0x00);
cx24117_writereg(state, 0xcb, 0x00);
cx24117_writereg(state, 0xcc, 0x00);
cx24117_writereg(state, 0xcd, 0x00);
cx24117_writereg(state, 0xe4, 0x03);
cx24117_writereg(state, 0xeb, 0x0a);
cx24117_writereg(state, 0xfb, 0x00);
cx24117_writereg(state, 0xe0, 0x76);
cx24117_writereg(state, 0xf7, 0x81);
cx24117_writereg(state, 0xf8, 0x00);
cx24117_writereg(state, 0xf9, 0x00);
buf = kmalloc(fw->size + 1, GFP_KERNEL);
if (buf == NULL) {
state->priv->skip_fw_load = 0;
return -ENOMEM;
}
/* fw upload reg */
buf[0] = 0xfa;
memcpy(&buf[1], fw->data, fw->size);
/* prepare i2c message to send */
msg.addr = state->priv->demod_address;
msg.flags = 0;
msg.len = fw->size + 1;
msg.buf = buf;
/* send fw */
ret = i2c_transfer(state->priv->i2c, &msg, 1);
if (ret < 0) {
kfree(buf);
return ret;
}
kfree(buf);
cx24117_writereg(state, 0xf7, 0x0c);
cx24117_writereg(state, 0xe0, 0x00);
/* Init demodulator */
cmd.args[0] = CMD_DEMODINIT;
cmd.args[1] = 0x00;
cmd.args[2] = 0x01;
cmd.args[3] = 0x00;
cmd.len = 4;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
/* Set VCO frequency */
cmd.args[0] = CMD_SET_VCOFREQ;
cmd.args[1] = 0x06;
cmd.args[2] = 0x2b;
cmd.args[3] = 0xd8;
cmd.args[4] = 0xa5;
cmd.args[5] = 0xee;
cmd.args[6] = 0x03;
cmd.args[7] = 0x9d;
cmd.args[8] = 0xfc;
cmd.args[9] = 0x06;
cmd.args[10] = 0x02;
cmd.args[11] = 0x9d;
cmd.args[12] = 0xfc;
cmd.len = 13;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
/* Tuner init */
cmd.args[0] = CMD_TUNERINIT;
cmd.args[1] = 0x00;
cmd.args[2] = 0x01;
cmd.args[3] = 0x00;
cmd.args[4] = 0x00;
cmd.args[5] = 0x01;
cmd.args[6] = 0x01;
cmd.args[7] = 0x01;
cmd.args[8] = 0x00;
cmd.args[9] = 0x05;
cmd.args[10] = 0x02;
cmd.args[11] = 0x02;
cmd.args[12] = 0x00;
cmd.len = 13;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
/* Global MPEG config */
cmd.args[0] = CMD_GLOBAL_MPEGCFG;
cmd.args[1] = 0x00;
cmd.args[2] = 0x00;
cmd.args[3] = 0x00;
cmd.args[4] = 0x01;
cmd.args[5] = 0x00;
cmd.len = 6;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
/* MPEG config for each demod */
for (i = 0; i < 2; i++) {
cmd.args[0] = CMD_MPEGCFG;
cmd.args[1] = (u8) i;
cmd.args[2] = 0x00;
cmd.args[3] = 0x05;
cmd.args[4] = 0x00;
cmd.args[5] = 0x00;
cmd.args[6] = 0x55;
cmd.args[7] = 0x00;
cmd.len = 8;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
}
cx24117_writereg(state, 0xce, 0xc0);
cx24117_writereg(state, 0xcf, 0x00);
cx24117_writereg(state, 0xe5, 0x04);
/* Get firmware version */
cmd.args[0] = CMD_FWVERSION;
cmd.len = 2;
for (i = 0; i < 4; i++) {
cmd.args[1] = i;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto error;
vers[i] = cx24117_readreg(state, 0x33);
}
dev_info(&state->priv->i2c->dev,
"%s: FW version %i.%i.%i.%i\n", __func__,
vers[0], vers[1], vers[2], vers[3]);
return 0;
error:
state->priv->skip_fw_load = 0;
dev_err(&state->priv->i2c->dev, "%s() Error running FW.\n", __func__);
return ret;
}
static int cx24117_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct cx24117_state *state = fe->demodulator_priv;
int lock;
lock = cx24117_readreg(state,
(state->demod == 0) ? CX24117_REG_SSTATUS0 :
CX24117_REG_SSTATUS1) &
CX24117_STATUS_MASK;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d status = 0x%02x\n",
__func__, state->demod, lock);
*status = 0;
if (lock & CX24117_HAS_SIGNAL)
*status |= FE_HAS_SIGNAL;
if (lock & CX24117_HAS_CARRIER)
*status |= FE_HAS_CARRIER;
if (lock & CX24117_HAS_VITERBI)
*status |= FE_HAS_VITERBI;
if (lock & CX24117_HAS_SYNCLOCK)
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
static int cx24117_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct cx24117_state *state = fe->demodulator_priv;
int ret;
u8 buf[4];
u8 base_reg = (state->demod == 0) ?
CX24117_REG_BER4_0 :
CX24117_REG_BER4_1;
ret = cx24117_readregN(state, base_reg, buf, 4);
if (ret != 0)
return ret;
*ber = (buf[0] << 24) | (buf[1] << 16) |
(buf[1] << 8) | buf[0];
dev_dbg(&state->priv->i2c->dev, "%s() demod%d ber=0x%04x\n",
__func__, state->demod, *ber);
return 0;
}
static int cx24117_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
int ret;
u16 sig_reading;
u8 buf[2];
u8 reg = (state->demod == 0) ?
CX24117_REG_SSTATUS0 : CX24117_REG_SSTATUS1;
/* Read AGC accumulator register */
cmd.args[0] = CMD_GET_AGCACC;
cmd.args[1] = (u8) state->demod;
cmd.len = 2;
ret = cx24117_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
ret = cx24117_readregN(state, reg, buf, 2);
if (ret != 0)
return ret;
sig_reading = ((buf[0] & CX24117_SIGNAL_MASK) << 2) | buf[1];
*signal_strength = -100 * sig_reading + 94324;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d raw / cooked = 0x%04x / 0x%04x\n",
__func__, state->demod, sig_reading, *signal_strength);
return 0;
}
static int cx24117_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct cx24117_state *state = fe->demodulator_priv;
int ret;
u8 buf[2];
u8 reg = (state->demod == 0) ?
CX24117_REG_QUALITY2_0 : CX24117_REG_QUALITY2_1;
ret = cx24117_readregN(state, reg, buf, 2);
if (ret != 0)
return ret;
*snr = (buf[0] << 8) | buf[1];
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d snr = 0x%04x\n",
__func__, state->demod, *snr);
return ret;
}
static int cx24117_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct cx24117_state *state = fe->demodulator_priv;
enum fe_delivery_system delsys = fe->dtv_property_cache.delivery_system;
int ret;
u8 buf[2];
u8 reg = (state->demod == 0) ?
CX24117_REG_DVBS_UCB2_0 :
CX24117_REG_DVBS_UCB2_1;
switch (delsys) {
case SYS_DVBS:
break;
case SYS_DVBS2:
reg += (CX24117_REG_DVBS2_UCB2_0 - CX24117_REG_DVBS_UCB2_0);
break;
default:
return -EINVAL;
}
ret = cx24117_readregN(state, reg, buf, 2);
if (ret != 0)
return ret;
*ucblocks = (buf[0] << 8) | buf[1];
dev_dbg(&state->priv->i2c->dev, "%s() demod%d ucb=0x%04x\n",
__func__, state->demod, *ucblocks);
return 0;
}
/* Overwrite the current tuning params, we are about to tune */
static void cx24117_clone_params(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
state->dcur = state->dnxt;
}
/* Wait for LNB */
static int cx24117_wait_for_lnb(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
int i;
u8 val, reg = (state->demod == 0) ? CX24117_REG_QSTATUS0 :
CX24117_REG_QSTATUS1;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d qstatus = 0x%02x\n",
__func__, state->demod, cx24117_readreg(state, reg));
/* Wait for up to 300 ms */
for (i = 0; i < 10; i++) {
val = cx24117_readreg(state, reg) & 0x01;
if (val != 0)
return 0;
msleep(30);
}
dev_warn(&state->priv->i2c->dev, "%s: demod%d LNB not ready\n",
KBUILD_MODNAME, state->demod);
return -ETIMEDOUT; /* -EBUSY ? */
}
static int cx24117_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
int ret;
u8 reg = (state->demod == 0) ? 0x10 : 0x20;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d %s\n",
__func__, state->demod,
voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" :
"SEC_VOLTAGE_OFF");
/* Prepare a set GPIO logic level CMD */
cmd.args[0] = CMD_SET_GPIOOUT;
cmd.args[2] = reg; /* mask */
cmd.len = 3;
if ((voltage == SEC_VOLTAGE_13) ||
(voltage == SEC_VOLTAGE_18)) {
/* power on LNB */
cmd.args[1] = reg;
ret = cx24117_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
ret = cx24117_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Wait for voltage/min repeat delay */
msleep(100);
/* Set 13V/18V select pin */
cmd.args[0] = CMD_LNBDCLEVEL;
cmd.args[1] = state->demod ? 0 : 1;
cmd.args[2] = (voltage == SEC_VOLTAGE_18 ? 0x01 : 0x00);
cmd.len = 3;
ret = cx24117_cmd_execute(fe, &cmd);
/* Min delay time before DiSEqC send */
msleep(20);
} else {
/* power off LNB */
cmd.args[1] = 0x00;
ret = cx24117_cmd_execute(fe, &cmd);
}
return ret;
}
static int cx24117_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
int ret;
dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n",
__func__, state->demod, tone);
if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
dev_warn(&state->priv->i2c->dev, "%s: demod%d invalid tone=%d\n",
KBUILD_MODNAME, state->demod, tone);
return -EINVAL;
}
/* Wait for LNB ready */
ret = cx24117_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Min delay time after DiSEqC send */
msleep(20);
/* Set the tone */
cmd.args[0] = CMD_LNBPCBCONFIG;
cmd.args[1] = (state->demod ? 0 : 1);
cmd.args[2] = 0x00;
cmd.args[3] = 0x00;
cmd.len = 5;
switch (tone) {
case SEC_TONE_ON:
cmd.args[4] = 0x01;
break;
case SEC_TONE_OFF:
cmd.args[4] = 0x00;
break;
}
msleep(20);
return cx24117_cmd_execute(fe, &cmd);
}
/* Initialise DiSEqC */
static int cx24117_diseqc_init(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
/* Prepare a DiSEqC command */
state->dsec_cmd.args[0] = CMD_LNBSEND;
/* demod */
state->dsec_cmd.args[CX24117_DISEQC_DEMOD] = state->demod ? 0 : 1;
/* DiSEqC burst */
state->dsec_cmd.args[CX24117_DISEQC_BURST] = CX24117_DISEQC_MINI_A;
/* Unknown */
state->dsec_cmd.args[CX24117_DISEQC_ARG3_2] = 0x02;
state->dsec_cmd.args[CX24117_DISEQC_ARG4_0] = 0x00;
/* Continuation flag? */
state->dsec_cmd.args[CX24117_DISEQC_ARG5_0] = 0x00;
/* DiSEqC message length */
state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] = 0x00;
/* Command length */
state->dsec_cmd.len = 7;
return 0;
}
/* Send DiSEqC message */
static int cx24117_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *d)
{
struct cx24117_state *state = fe->demodulator_priv;
int i, ret;
/* Dump DiSEqC message */
dev_dbg(&state->priv->i2c->dev, "%s: demod %d (",
__func__, state->demod);
for (i = 0; i < d->msg_len; i++)
dev_dbg(&state->priv->i2c->dev, "0x%02x ", d->msg[i]);
dev_dbg(&state->priv->i2c->dev, ")\n");
/* Validate length */
if (d->msg_len > sizeof(d->msg))
return -EINVAL;
/* DiSEqC message */
for (i = 0; i < d->msg_len; i++)
state->dsec_cmd.args[CX24117_DISEQC_MSGOFS + i] = d->msg[i];
/* DiSEqC message length */
state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] = d->msg_len;
/* Command length */
state->dsec_cmd.len = CX24117_DISEQC_MSGOFS +
state->dsec_cmd.args[CX24117_DISEQC_MSGLEN];
/*
* Message is sent with derived else cached burst
*
* WRITE PORT GROUP COMMAND 38
*
* 0/A/A: E0 10 38 F0..F3
* 1/B/B: E0 10 38 F4..F7
* 2/C/A: E0 10 38 F8..FB
* 3/D/B: E0 10 38 FC..FF
*
* databyte[3]= 8421:8421
* ABCD:WXYZ
* CLR :SET
*
* WX= PORT SELECT 0..3 (X=TONEBURST)
* Y = VOLTAGE (0=13V, 1=18V)
* Z = BAND (0=LOW, 1=HIGH(22K))
*/
if (d->msg_len >= 4 && d->msg[2] == 0x38)
state->dsec_cmd.args[CX24117_DISEQC_BURST] =
((d->msg[3] & 4) >> 2);
dev_dbg(&state->priv->i2c->dev, "%s() demod%d burst=%d\n",
__func__, state->demod,
state->dsec_cmd.args[CX24117_DISEQC_BURST]);
/* Wait for LNB ready */
ret = cx24117_wait_for_lnb(fe);
if (ret != 0)
return ret;
/* Wait for voltage/min repeat delay */
msleep(100);
/* Command */
ret = cx24117_cmd_execute(fe, &state->dsec_cmd);
if (ret != 0)
return ret;
/*
* Wait for send
*
* Eutelsat spec:
* >15ms delay + (XXX determine if FW does this, see set_tone)
* 13.5ms per byte +
* >15ms delay +
* 12.5ms burst +
* >15ms delay (XXX determine if FW does this, see set_tone)
*/
msleep((state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] << 4) + 60);
return 0;
}
/* Send DiSEqC burst */
static int cx24117_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct cx24117_state *state = fe->demodulator_priv;
dev_dbg(&state->priv->i2c->dev, "%s(%d) demod=%d\n",
__func__, burst, state->demod);
/* DiSEqC burst */
if (burst == SEC_MINI_A)
state->dsec_cmd.args[CX24117_DISEQC_BURST] =
CX24117_DISEQC_MINI_A;
else if (burst == SEC_MINI_B)
state->dsec_cmd.args[CX24117_DISEQC_BURST] =
CX24117_DISEQC_MINI_B;
else
return -EINVAL;
return 0;
}
static int cx24117_get_priv(struct cx24117_priv **priv,
struct i2c_adapter *i2c, u8 client_address)
{
int ret;
mutex_lock(&cx24117_list_mutex);
ret = hybrid_tuner_request_state(struct cx24117_priv, (*priv),
hybrid_tuner_instance_list, i2c, client_address, "cx24117");
mutex_unlock(&cx24117_list_mutex);
return ret;
}
static void cx24117_release_priv(struct cx24117_priv *priv)
{
mutex_lock(&cx24117_list_mutex);
if (priv != NULL)
hybrid_tuner_release_state(priv);
mutex_unlock(&cx24117_list_mutex);
}
static void cx24117_release(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
dev_dbg(&state->priv->i2c->dev, "%s demod%d\n",
__func__, state->demod);
cx24117_release_priv(state->priv);
kfree(state);
}
static const struct dvb_frontend_ops cx24117_ops;
struct dvb_frontend *cx24117_attach(const struct cx24117_config *config,
struct i2c_adapter *i2c)
{
struct cx24117_state *state = NULL;
struct cx24117_priv *priv = NULL;
int demod = 0;
/* get the common data struct for both demods */
demod = cx24117_get_priv(&priv, i2c, config->demod_address);
switch (demod) {
case 0:
dev_err(&i2c->dev,
"%s: Error attaching frontend %d\n",
KBUILD_MODNAME, demod);
goto error1;
case 1:
/* new priv instance */
priv->i2c = i2c;
priv->demod_address = config->demod_address;
mutex_init(&priv->fe_lock);
break;
default:
/* existing priv instance */
break;
}
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct cx24117_state), GFP_KERNEL);
if (state == NULL)
goto error2;
state->demod = demod - 1;
state->priv = priv;
dev_info(&state->priv->i2c->dev,
"%s: Attaching frontend %d\n",
KBUILD_MODNAME, state->demod);
/* create dvb_frontend */
memcpy(&state->frontend.ops, &cx24117_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error2:
cx24117_release_priv(priv);
error1:
return NULL;
}
EXPORT_SYMBOL_GPL(cx24117_attach);
/*
* Initialise or wake up device
*
* Power config will reset and load initial firmware if required
*/
static int cx24117_initfe(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
int ret;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n",
__func__, state->demod);
mutex_lock(&state->priv->fe_lock);
/* Set sleep mode off */
cmd.args[0] = CMD_SET_SLEEPMODE;
cmd.args[1] = (state->demod ? 1 : 0);
cmd.args[2] = 0;
cmd.len = 3;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto exit;
ret = cx24117_diseqc_init(fe);
if (ret != 0)
goto exit;
/* Set BER control */
cmd.args[0] = CMD_BERCTRL;
cmd.args[1] = (state->demod ? 1 : 0);
cmd.args[2] = 0x10;
cmd.args[3] = 0x10;
cmd.len = 4;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto exit;
/* Set RS correction (enable/disable) */
cmd.args[0] = CMD_ENABLERSCORR;
cmd.args[1] = (state->demod ? 1 : 0);
cmd.args[2] = CX24117_OCC;
cmd.len = 3;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
if (ret != 0)
goto exit;
/* Set GPIO direction */
/* Set as output - controls LNB power on/off */
cmd.args[0] = CMD_SET_GPIODIR;
cmd.args[1] = 0x30;
cmd.args[2] = 0x30;
cmd.len = 3;
ret = cx24117_cmd_execute_nolock(fe, &cmd);
exit:
mutex_unlock(&state->priv->fe_lock);
return ret;
}
/*
* Put device to sleep
*/
static int cx24117_sleep(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n",
__func__, state->demod);
/* Set sleep mode on */
cmd.args[0] = CMD_SET_SLEEPMODE;
cmd.args[1] = (state->demod ? 1 : 0);
cmd.args[2] = 1;
cmd.len = 3;
return cx24117_cmd_execute(fe, &cmd);
}
/* dvb-core told us to tune, the tv property cache will be complete,
* it's safe for is to pull values and use them for tuning purposes.
*/
static int cx24117_set_frontend(struct dvb_frontend *fe)
{
struct cx24117_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx24117_cmd cmd;
enum fe_status tunerstat;
int i, status, ret, retune = 1;
u8 reg_clkdiv, reg_ratediv;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n",
__func__, state->demod);
switch (c->delivery_system) {
case SYS_DVBS:
dev_dbg(&state->priv->i2c->dev, "%s() demod%d DVB-S\n",
__func__, state->demod);
/* Only QPSK is supported for DVB-S */
if (c->modulation != QPSK) {
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d unsupported modulation (%d)\n",
__func__, state->demod, c->modulation);
return -EINVAL;
}
/* Pilot doesn't exist in DVB-S, turn bit off */
state->dnxt.pilot_val = CX24117_PILOT_OFF;
/* DVB-S only supports 0.35 */
state->dnxt.rolloff_val = CX24117_ROLLOFF_035;
break;
case SYS_DVBS2:
dev_dbg(&state->priv->i2c->dev, "%s() demod%d DVB-S2\n",
__func__, state->demod);
/*
* NBC 8PSK/QPSK with DVB-S is supported for DVB-S2,
* but not hardware auto detection
*/
if (c->modulation != PSK_8 && c->modulation != QPSK) {
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d unsupported modulation (%d)\n",
__func__, state->demod, c->modulation);
return -EOPNOTSUPP;
}
switch (c->pilot) {
case PILOT_AUTO:
state->dnxt.pilot_val = CX24117_PILOT_AUTO;
break;
case PILOT_OFF:
state->dnxt.pilot_val = CX24117_PILOT_OFF;
break;
case PILOT_ON:
state->dnxt.pilot_val = CX24117_PILOT_ON;
break;
default:
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d unsupported pilot mode (%d)\n",
__func__, state->demod, c->pilot);
return -EOPNOTSUPP;
}
switch (c->rolloff) {
case ROLLOFF_20:
state->dnxt.rolloff_val = CX24117_ROLLOFF_020;
break;
case ROLLOFF_25:
state->dnxt.rolloff_val = CX24117_ROLLOFF_025;
break;
case ROLLOFF_35:
state->dnxt.rolloff_val = CX24117_ROLLOFF_035;
break;
case ROLLOFF_AUTO:
state->dnxt.rolloff_val = CX24117_ROLLOFF_035;
/* soft-auto rolloff */
retune = 3;
break;
default:
dev_warn(&state->priv->i2c->dev,
"%s: demod%d unsupported rolloff (%d)\n",
KBUILD_MODNAME, state->demod, c->rolloff);
return -EOPNOTSUPP;
}
break;
default:
dev_warn(&state->priv->i2c->dev,
"%s: demod %d unsupported delivery system (%d)\n",
KBUILD_MODNAME, state->demod, c->delivery_system);
return -EINVAL;
}
state->dnxt.delsys = c->delivery_system;
state->dnxt.modulation = c->modulation;
state->dnxt.frequency = c->frequency;
state->dnxt.pilot = c->pilot;
state->dnxt.rolloff = c->rolloff;
ret = cx24117_set_inversion(state, c->inversion);
if (ret != 0)
return ret;
ret = cx24117_set_fec(state,
c->delivery_system, c->modulation, c->fec_inner);
if (ret != 0)
return ret;
ret = cx24117_set_symbolrate(state, c->symbol_rate);
if (ret != 0)
return ret;
/* discard the 'current' tuning parameters and prepare to tune */
cx24117_clone_params(fe);
dev_dbg(&state->priv->i2c->dev,
"%s: delsys = %d\n", __func__, state->dcur.delsys);
dev_dbg(&state->priv->i2c->dev,
"%s: modulation = %d\n", __func__, state->dcur.modulation);
dev_dbg(&state->priv->i2c->dev,
"%s: frequency = %d\n", __func__, state->dcur.frequency);
dev_dbg(&state->priv->i2c->dev,
"%s: pilot = %d (val = 0x%02x)\n", __func__,
state->dcur.pilot, state->dcur.pilot_val);
dev_dbg(&state->priv->i2c->dev,
"%s: retune = %d\n", __func__, retune);
dev_dbg(&state->priv->i2c->dev,
"%s: rolloff = %d (val = 0x%02x)\n", __func__,
state->dcur.rolloff, state->dcur.rolloff_val);
dev_dbg(&state->priv->i2c->dev,
"%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
dev_dbg(&state->priv->i2c->dev,
"%s: FEC = %d (mask/val = 0x%02x/0x%02x)\n", __func__,
state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
dev_dbg(&state->priv->i2c->dev,
"%s: Inversion = %d (val = 0x%02x)\n", __func__,
state->dcur.inversion, state->dcur.inversion_val);
/* Prepare a tune request */
cmd.args[0] = CMD_TUNEREQUEST;
/* demod */
cmd.args[1] = state->demod;
/* Frequency */
cmd.args[2] = (state->dcur.frequency & 0xff0000) >> 16;
cmd.args[3] = (state->dcur.frequency & 0x00ff00) >> 8;
cmd.args[4] = (state->dcur.frequency & 0x0000ff);
/* Symbol Rate */
cmd.args[5] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
cmd.args[6] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
/* Automatic Inversion */
cmd.args[7] = state->dcur.inversion_val;
/* Modulation / FEC / Pilot */
cmd.args[8] = state->dcur.fec_val | state->dcur.pilot_val;
cmd.args[9] = CX24117_SEARCH_RANGE_KHZ >> 8;
cmd.args[10] = CX24117_SEARCH_RANGE_KHZ & 0xff;
cmd.args[11] = state->dcur.rolloff_val;
cmd.args[12] = state->dcur.fec_mask;
if (state->dcur.symbol_rate > 30000000) {
reg_ratediv = 0x04;
reg_clkdiv = 0x02;
} else if (state->dcur.symbol_rate > 10000000) {
reg_ratediv = 0x06;
reg_clkdiv = 0x03;
} else {
reg_ratediv = 0x0a;
reg_clkdiv = 0x05;
}
cmd.args[13] = reg_ratediv;
cmd.args[14] = reg_clkdiv;
cx24117_writereg(state, (state->demod == 0) ?
CX24117_REG_CLKDIV0 : CX24117_REG_CLKDIV1, reg_clkdiv);
cx24117_writereg(state, (state->demod == 0) ?
CX24117_REG_RATEDIV0 : CX24117_REG_RATEDIV1, reg_ratediv);
cmd.args[15] = CX24117_PNE;
cmd.len = 16;
do {
/* Reset status register */
status = cx24117_readreg(state, (state->demod == 0) ?
CX24117_REG_SSTATUS0 : CX24117_REG_SSTATUS1) &
CX24117_SIGNAL_MASK;
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d status_setfe = %02x\n",
__func__, state->demod, status);
cx24117_writereg(state, (state->demod == 0) ?
CX24117_REG_SSTATUS0 : CX24117_REG_SSTATUS1, status);
/* Tune */
ret = cx24117_cmd_execute(fe, &cmd);
if (ret != 0)
break;
/*
* Wait for up to 500 ms before retrying
*
* If we are able to tune then generally it occurs within 100ms.
* If it takes longer, try a different rolloff setting.
*/
for (i = 0; i < 50; i++) {
cx24117_read_status(fe, &tunerstat);
status = tunerstat & (FE_HAS_SIGNAL | FE_HAS_SYNC);
if (status == (FE_HAS_SIGNAL | FE_HAS_SYNC)) {
dev_dbg(&state->priv->i2c->dev,
"%s() demod%d tuned\n",
__func__, state->demod);
return 0;
}
msleep(20);
}
dev_dbg(&state->priv->i2c->dev, "%s() demod%d not tuned\n",
__func__, state->demod);
/* try next rolloff value */
if (state->dcur.rolloff == 3)
cmd.args[11]--;
} while (--retune);
return -EINVAL;
}
static int cx24117_tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
{
struct cx24117_state *state = fe->demodulator_priv;
dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n",
__func__, state->demod);
*delay = HZ / 5;
if (re_tune) {
int ret = cx24117_set_frontend(fe);
if (ret)
return ret;
}
return cx24117_read_status(fe, status);
}
static enum dvbfe_algo cx24117_get_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static int cx24117_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cx24117_state *state = fe->demodulator_priv;
struct cx24117_cmd cmd;
u8 reg, st, inv;
int ret, idx;
unsigned int freq;
short srate_os, freq_os;
u8 buf[0x1f-4];
/* Read current tune parameters */
cmd.args[0] = CMD_GETCTLACC;
cmd.args[1] = (u8) state->demod;
cmd.len = 2;
ret = cx24117_cmd_execute(fe, &cmd);
if (ret != 0)
return ret;
/* read all required regs at once */
reg = (state->demod == 0) ? CX24117_REG_FREQ3_0 : CX24117_REG_FREQ3_1;
ret = cx24117_readregN(state, reg, buf, 0x1f-4);
if (ret != 0)
return ret;
st = buf[5];
/* get spectral inversion */
inv = (((state->demod == 0) ? ~st : st) >> 6) & 1;
if (inv == 0)
c->inversion = INVERSION_OFF;
else
c->inversion = INVERSION_ON;
/* modulation and fec */
idx = st & 0x3f;
if (c->delivery_system == SYS_DVBS2) {
if (idx > 11)
idx += 9;
else
idx += 7;
}
c->modulation = cx24117_modfec_modes[idx].modulation;
c->fec_inner = cx24117_modfec_modes[idx].fec;
/* frequency */
freq = (buf[0] << 16) | (buf[1] << 8) | buf[2];
freq_os = (buf[8] << 8) | buf[9];
c->frequency = freq + freq_os;
/* symbol rate */
srate_os = (buf[10] << 8) | buf[11];
c->symbol_rate = -1000 * srate_os + state->dcur.symbol_rate;
return 0;
}
static const struct dvb_frontend_ops cx24117_ops = {
.delsys = { SYS_DVBS, SYS_DVBS2 },
.info = {
.name = "Conexant CX24117/CX24132",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1011 * kHz,
.frequency_tolerance_hz = 5 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_QPSK | FE_CAN_RECOVER
},
.release = cx24117_release,
.init = cx24117_initfe,
.sleep = cx24117_sleep,
.read_status = cx24117_read_status,
.read_ber = cx24117_read_ber,
.read_signal_strength = cx24117_read_signal_strength,
.read_snr = cx24117_read_snr,
.read_ucblocks = cx24117_read_ucblocks,
.set_tone = cx24117_set_tone,
.set_voltage = cx24117_set_voltage,
.diseqc_send_master_cmd = cx24117_send_diseqc_msg,
.diseqc_send_burst = cx24117_diseqc_send_burst,
.get_frontend_algo = cx24117_get_algo,
.tune = cx24117_tune,
.set_frontend = cx24117_set_frontend,
.get_frontend = cx24117_get_frontend,
};
MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24117/cx24132 hardware");
MODULE_AUTHOR("Luis Alves ([email protected])");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.1");
MODULE_FIRMWARE(CX24117_DEFAULT_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/cx24117.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Silicon Labs Si2168 DVB-T/T2/C demodulator driver
*
* Copyright (C) 2014 Antti Palosaari <[email protected]>
*/
#include <linux/delay.h>
#include "si2168_priv.h"
static const struct dvb_frontend_ops si2168_ops;
static void cmd_init(struct si2168_cmd *cmd, const u8 *buf, int wlen, int rlen)
{
memcpy(cmd->args, buf, wlen);
cmd->wlen = wlen;
cmd->rlen = rlen;
}
/* execute firmware command */
static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
{
struct si2168_dev *dev = i2c_get_clientdata(client);
int ret;
unsigned long timeout;
mutex_lock(&dev->i2c_mutex);
if (cmd->wlen) {
/* write cmd and args for firmware */
ret = i2c_master_send(client, cmd->args, cmd->wlen);
if (ret < 0) {
goto err_mutex_unlock;
} else if (ret != cmd->wlen) {
ret = -EREMOTEIO;
goto err_mutex_unlock;
}
}
if (cmd->rlen) {
/* wait cmd execution terminate */
#define TIMEOUT 70
timeout = jiffies + msecs_to_jiffies(TIMEOUT);
while (!time_after(jiffies, timeout)) {
ret = i2c_master_recv(client, cmd->args, cmd->rlen);
if (ret < 0) {
goto err_mutex_unlock;
} else if (ret != cmd->rlen) {
ret = -EREMOTEIO;
goto err_mutex_unlock;
}
/* firmware ready? */
if ((cmd->args[0] >> 7) & 0x01)
break;
}
dev_dbg(&client->dev, "cmd execution took %d ms\n",
jiffies_to_msecs(jiffies) -
(jiffies_to_msecs(timeout) - TIMEOUT));
/* error bit set? */
if ((cmd->args[0] >> 6) & 0x01) {
ret = -EREMOTEIO;
goto err_mutex_unlock;
}
if (!((cmd->args[0] >> 7) & 0x01)) {
ret = -ETIMEDOUT;
goto err_mutex_unlock;
}
}
mutex_unlock(&dev->i2c_mutex);
return 0;
err_mutex_unlock:
mutex_unlock(&dev->i2c_mutex);
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
struct si2168_cmd cmd;
int ret = 0;
dev_dbg(&client->dev, "%s acquire: %d\n", __func__, acquire);
/* set manual value */
if (dev->ts_mode & SI2168_TS_CLK_MANUAL) {
cmd_init(&cmd, "\x14\x00\x0d\x10\xe8\x03", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
return ret;
}
/* set TS_MODE property */
cmd_init(&cmd, "\x14\x00\x01\x10\x10\x00", 6, 4);
if (dev->ts_mode & SI2168_TS_CLK_MANUAL)
cmd.args[4] = SI2168_TS_CLK_MANUAL;
if (acquire)
cmd.args[4] |= dev->ts_mode;
else
cmd.args[4] |= SI2168_TS_TRISTATE;
if (dev->ts_clock_gapped)
cmd.args[4] |= 0x40;
ret = si2168_cmd_execute(client, &cmd);
return ret;
}
static int si2168_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i;
unsigned int utmp, utmp1, utmp2;
struct si2168_cmd cmd;
*status = 0;
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
cmd_init(&cmd, "\xa0\x01", 2, 13);
break;
case SYS_DVBC_ANNEX_A:
cmd_init(&cmd, "\x90\x01", 2, 9);
break;
case SYS_DVBT2:
cmd_init(&cmd, "\x50\x01", 2, 14);
break;
default:
ret = -EINVAL;
goto err;
}
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
switch ((cmd.args[2] >> 1) & 0x03) {
case 0x01:
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
break;
case 0x03:
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
FE_HAS_SYNC | FE_HAS_LOCK;
break;
}
dev->fe_status = *status;
if (*status & FE_HAS_LOCK) {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cmd.args[3] * 1000 / 4;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
dev_dbg(&client->dev, "status=%02x args=%*ph\n",
*status, cmd.rlen, cmd.args);
/* BER */
if (*status & FE_HAS_VITERBI) {
cmd_init(&cmd, "\x82\x00", 2, 3);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
/*
* Firmware returns [0, 255] mantissa and [0, 8] exponent.
* Convert to DVB API: mantissa * 10^(8 - exponent) / 10^8
*/
utmp = clamp(8 - cmd.args[1], 0, 8);
for (i = 0, utmp1 = 1; i < utmp; i++)
utmp1 = utmp1 * 10;
utmp1 = cmd.args[2] * utmp1;
utmp2 = 100000000; /* 10^8 */
dev_dbg(&client->dev,
"post_bit_error=%u post_bit_count=%u ber=%u*10^-%u\n",
utmp1, utmp2, cmd.args[2], cmd.args[1]);
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += utmp1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += utmp2;
} else {
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* UCB */
if (*status & FE_HAS_SYNC) {
cmd_init(&cmd, "\x84\x01", 2, 3);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
utmp1 = cmd.args[2] << 8 | cmd.args[1] << 0;
dev_dbg(&client->dev, "block_error=%u\n", utmp1);
/* Sometimes firmware returns bogus value */
if (utmp1 == 0xffff)
utmp1 = 0;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += utmp1;
} else {
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_set_frontend(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
struct si2168_cmd cmd;
u8 bandwidth, delivery_system;
dev_dbg(&client->dev,
"delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%u stream_id=%u\n",
c->delivery_system, c->modulation, c->frequency,
c->bandwidth_hz, c->symbol_rate, c->inversion,
c->stream_id);
if (!dev->active) {
ret = -EAGAIN;
goto err;
}
switch (c->delivery_system) {
case SYS_DVBT:
delivery_system = 0x20;
break;
case SYS_DVBC_ANNEX_A:
delivery_system = 0x30;
break;
case SYS_DVBT2:
delivery_system = 0x70;
break;
default:
ret = -EINVAL;
goto err;
}
if (c->bandwidth_hz == 0) {
ret = -EINVAL;
goto err;
} else if (c->bandwidth_hz <= 2000000)
bandwidth = 0x02;
else if (c->bandwidth_hz <= 5000000)
bandwidth = 0x05;
else if (c->bandwidth_hz <= 6000000)
bandwidth = 0x06;
else if (c->bandwidth_hz <= 7000000)
bandwidth = 0x07;
else if (c->bandwidth_hz <= 8000000)
bandwidth = 0x08;
else if (c->bandwidth_hz <= 9000000)
bandwidth = 0x09;
else if (c->bandwidth_hz <= 10000000)
bandwidth = 0x0a;
else
bandwidth = 0x0f;
/* program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
cmd_init(&cmd, "\x88\x02\x02\x02\x02", 5, 5);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
/* that has no big effect */
if (c->delivery_system == SYS_DVBT)
cmd_init(&cmd, "\x89\x21\x06\x11\xff\x98", 6, 3);
else if (c->delivery_system == SYS_DVBC_ANNEX_A)
cmd_init(&cmd, "\x89\x21\x06\x11\x89\xf0", 6, 3);
else if (c->delivery_system == SYS_DVBT2)
cmd_init(&cmd, "\x89\x21\x06\x11\x89\x20", 6, 3);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
if (c->delivery_system == SYS_DVBT2) {
/* select PLP */
cmd.args[0] = 0x52;
cmd.args[1] = c->stream_id & 0xff;
cmd.args[2] = c->stream_id == NO_STREAM_ID_FILTER ? 0 : 1;
cmd.wlen = 3;
cmd.rlen = 1;
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
}
cmd_init(&cmd, "\x51\x03", 2, 12);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x12\x08\x04", 3, 3);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x0c\x10\x12\x00", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x06\x10\x24\x00", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x07\x10\x00\x24", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x0a\x10\x00\x00", 6, 4);
cmd.args[4] = delivery_system | bandwidth;
if (dev->spectral_inversion)
cmd.args[5] |= 1;
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
/* set DVB-C symbol rate */
if (c->delivery_system == SYS_DVBC_ANNEX_A) {
cmd_init(&cmd, "\x14\x00\x02\x11\x00\x00", 6, 4);
cmd.args[4] = ((c->symbol_rate / 1000) >> 0) & 0xff;
cmd.args[5] = ((c->symbol_rate / 1000) >> 8) & 0xff;
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
}
cmd_init(&cmd, "\x14\x00\x0f\x10\x10\x00", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x09\x10\xe3\x08", 6, 4);
cmd.args[5] |= dev->ts_clock_inv ? 0x00 : 0x10;
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x08\x10\xd7\x05", 6, 4);
cmd.args[5] |= dev->ts_clock_inv ? 0x00 : 0x10;
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x01\x12\x00\x00", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x14\x00\x01\x03\x0c\x00", 6, 4);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
cmd_init(&cmd, "\x85", 1, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
dev->delivery_system = c->delivery_system;
/* enable ts bus */
ret = si2168_ts_bus_ctrl(fe, 1);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_init(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, len, remaining;
const struct firmware *fw;
struct si2168_cmd cmd;
dev_dbg(&client->dev, "\n");
/* initialize */
cmd_init(&cmd, "\xc0\x12\x00\x0c\x00\x0d\x16\x00\x00\x00\x00\x00\x00",
13, 0);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
if (dev->warm) {
/* resume */
cmd_init(&cmd, "\xc0\x06\x08\x0f\x00\x20\x21\x01", 8, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
udelay(100);
cmd_init(&cmd, "\x85", 1, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
goto warm;
}
/* power up */
cmd_init(&cmd, "\xc0\x06\x01\x0f\x00\x20\x20\x01", 8, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
/* request the firmware, this will block and timeout */
ret = request_firmware(&fw, dev->firmware_name, &client->dev);
if (ret) {
dev_err(&client->dev,
"firmware file '%s' not found\n",
dev->firmware_name);
goto err_release_firmware;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n",
dev->firmware_name);
if ((fw->size % 17 == 0) && (fw->data[0] > 5)) {
/* firmware is in the new format */
for (remaining = fw->size; remaining > 0; remaining -= 17) {
len = fw->data[fw->size - remaining];
if (len > SI2168_ARGLEN) {
ret = -EINVAL;
break;
}
cmd_init(&cmd, &fw->data[(fw->size - remaining) + 1],
len, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
break;
}
} else if (fw->size % 8 == 0) {
/* firmware is in the old format */
for (remaining = fw->size; remaining > 0; remaining -= 8) {
cmd_init(&cmd, &fw->data[fw->size - remaining], 8, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
break;
}
} else {
/* bad or unknown firmware format */
ret = -EINVAL;
}
if (ret) {
dev_err(&client->dev, "firmware download failed %d\n", ret);
goto err_release_firmware;
}
release_firmware(fw);
cmd_init(&cmd, "\x01\x01", 2, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
/* query firmware version */
cmd_init(&cmd, "\x11", 1, 10);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
dev->version = (cmd.args[9] + '@') << 24 | (cmd.args[6] - '0') << 16 |
(cmd.args[7] - '0') << 8 | (cmd.args[8]) << 0;
dev_info(&client->dev, "firmware version: %c %d.%d.%d\n",
dev->version >> 24 & 0xff, dev->version >> 16 & 0xff,
dev->version >> 8 & 0xff, dev->version >> 0 & 0xff);
/* set ts mode */
ret = si2168_ts_bus_ctrl(fe, 1);
if (ret)
goto err;
dev->warm = true;
dev->initialized = true;
warm:
/* Init stats here to indicate which stats are supported */
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
dev->active = true;
return 0;
err_release_firmware:
release_firmware(fw);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_resume(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
/*
* check whether si2168_init() has been called successfully
* outside of a resume cycle. Only call it (and load firmware)
* in this case. si2168_init() is only called during resume
* once the device has actually been used. Otherwise, leave the
* device untouched.
*/
if (dev->initialized) {
dev_dbg(&client->dev, "previously initialized, call si2168_init()\n");
return si2168_init(fe);
}
dev_dbg(&client->dev, "not initialized yet, skipping init on resume\n");
return 0;
}
static int si2168_sleep(struct dvb_frontend *fe)
{
struct i2c_client *client = fe->demodulator_priv;
struct si2168_dev *dev = i2c_get_clientdata(client);
int ret;
struct si2168_cmd cmd;
dev_dbg(&client->dev, "\n");
dev->active = false;
/* tri-state data bus */
ret = si2168_ts_bus_ctrl(fe, 0);
if (ret)
goto err;
/* Firmware later than B 4.0-11 loses warm state during sleep */
if (dev->version > ('B' << 24 | 4 << 16 | 0 << 8 | 11 << 0))
dev->warm = false;
cmd_init(&cmd, "\x13", 1, 0);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 900;
return 0;
}
static int si2168_select(struct i2c_mux_core *muxc, u32 chan)
{
struct i2c_client *client = i2c_mux_priv(muxc);
int ret;
struct si2168_cmd cmd;
/* open I2C gate */
cmd_init(&cmd, "\xc0\x0d\x01", 3, 0);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int si2168_deselect(struct i2c_mux_core *muxc, u32 chan)
{
struct i2c_client *client = i2c_mux_priv(muxc);
int ret;
struct si2168_cmd cmd;
/* close I2C gate */
cmd_init(&cmd, "\xc0\x0d\x00", 3, 0);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static const struct dvb_frontend_ops si2168_ops = {
.delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
.info = {
.name = "Silicon Labs Si2168",
.frequency_min_hz = 48 * MHz,
.frequency_max_hz = 870 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = 1000000,
.symbol_rate_max = 7200000,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO |
FE_CAN_MUTE_TS |
FE_CAN_2G_MODULATION |
FE_CAN_MULTISTREAM
},
.get_tune_settings = si2168_get_tune_settings,
.init = si2168_init,
.sleep = si2168_sleep,
.resume = si2168_resume,
.set_frontend = si2168_set_frontend,
.read_status = si2168_read_status,
};
static int si2168_probe(struct i2c_client *client)
{
struct si2168_config *config = client->dev.platform_data;
struct si2168_dev *dev;
int ret;
struct si2168_cmd cmd;
dev_dbg(&client->dev, "\n");
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
i2c_set_clientdata(client, dev);
mutex_init(&dev->i2c_mutex);
/* Initialize */
cmd_init(&cmd, "\xc0\x12\x00\x0c\x00\x0d\x16\x00\x00\x00\x00\x00\x00",
13, 0);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err_kfree;
/* Power up */
cmd_init(&cmd, "\xc0\x06\x01\x0f\x00\x20\x20\x01", 8, 1);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err_kfree;
/* Query chip revision */
cmd_init(&cmd, "\x02", 1, 13);
ret = si2168_cmd_execute(client, &cmd);
if (ret)
goto err_kfree;
dev->chip_id = cmd.args[1] << 24 | cmd.args[2] << 16 |
cmd.args[3] << 8 | cmd.args[4] << 0;
switch (dev->chip_id) {
case SI2168_CHIP_ID_A20:
dev->firmware_name = SI2168_A20_FIRMWARE;
break;
case SI2168_CHIP_ID_A30:
dev->firmware_name = SI2168_A30_FIRMWARE;
break;
case SI2168_CHIP_ID_B40:
dev->firmware_name = SI2168_B40_FIRMWARE;
break;
case SI2168_CHIP_ID_D60:
dev->firmware_name = SI2168_D60_FIRMWARE;
break;
default:
dev_dbg(&client->dev, "unknown chip version Si21%d-%c%c%c\n",
cmd.args[2], cmd.args[1], cmd.args[3], cmd.args[4]);
ret = -ENODEV;
goto err_kfree;
}
dev->version = (cmd.args[1]) << 24 | (cmd.args[3] - '0') << 16 |
(cmd.args[4] - '0') << 8 | (cmd.args[5]) << 0;
/* create mux i2c adapter for tuner */
dev->muxc = i2c_mux_alloc(client->adapter, &client->dev,
1, 0, I2C_MUX_LOCKED,
si2168_select, si2168_deselect);
if (!dev->muxc) {
ret = -ENOMEM;
goto err_kfree;
}
dev->muxc->priv = client;
ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
if (ret)
goto err_kfree;
/* create dvb_frontend */
memcpy(&dev->fe.ops, &si2168_ops, sizeof(struct dvb_frontend_ops));
dev->fe.demodulator_priv = client;
*config->i2c_adapter = dev->muxc->adapter[0];
*config->fe = &dev->fe;
dev->ts_mode = config->ts_mode;
dev->ts_clock_inv = config->ts_clock_inv;
dev->ts_clock_gapped = config->ts_clock_gapped;
dev->spectral_inversion = config->spectral_inversion;
dev_info(&client->dev, "Silicon Labs Si2168-%c%d%d successfully identified\n",
dev->version >> 24 & 0xff, dev->version >> 16 & 0xff,
dev->version >> 8 & 0xff);
dev_info(&client->dev, "firmware version: %c %d.%d.%d\n",
dev->version >> 24 & 0xff, dev->version >> 16 & 0xff,
dev->version >> 8 & 0xff, dev->version >> 0 & 0xff);
return 0;
err_kfree:
kfree(dev);
err:
dev_warn(&client->dev, "probe failed = %d\n", ret);
return ret;
}
static void si2168_remove(struct i2c_client *client)
{
struct si2168_dev *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
i2c_mux_del_adapters(dev->muxc);
dev->fe.ops.release = NULL;
dev->fe.demodulator_priv = NULL;
kfree(dev);
}
static const struct i2c_device_id si2168_id_table[] = {
{"si2168", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, si2168_id_table);
static struct i2c_driver si2168_driver = {
.driver = {
.name = "si2168",
.suppress_bind_attrs = true,
},
.probe = si2168_probe,
.remove = si2168_remove,
.id_table = si2168_id_table,
};
module_i2c_driver(si2168_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Silicon Labs Si2168 DVB-T/T2/C demodulator driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(SI2168_A20_FIRMWARE);
MODULE_FIRMWARE(SI2168_A30_FIRMWARE);
MODULE_FIRMWARE(SI2168_B40_FIRMWARE);
MODULE_FIRMWARE(SI2168_D60_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/si2168.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
TDA10021 - Single Chip Cable Channel Receiver driver module
used on the Siemens DVB-C cards
Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]>
Copyright (C) 2004 Markus Schulz <[email protected]>
Support for TDA10021
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "tda1002x.h"
struct tda10021_state {
struct i2c_adapter* i2c;
/* configuration settings */
const struct tda1002x_config* config;
struct dvb_frontend frontend;
u8 pwm;
u8 reg0;
};
#if 0
#define dprintk(x...) printk(x)
#else
#define dprintk(x...)
#endif
static int verbose;
#define XIN 57840000UL
#define FIN (XIN >> 4)
static int tda10021_inittab_size = 0x40;
static u8 tda10021_inittab[0x40]=
{
0x73, 0x6a, 0x23, 0x0a, 0x02, 0x37, 0x77, 0x1a,
0x37, 0x6a, 0x17, 0x8a, 0x1e, 0x86, 0x43, 0x40,
0xb8, 0x3f, 0xa1, 0x00, 0xcd, 0x01, 0x00, 0xff,
0x11, 0x00, 0x7c, 0x31, 0x30, 0x20, 0x00, 0x00,
0x02, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x00,
0x07, 0x00, 0x33, 0x11, 0x0d, 0x95, 0x08, 0x58,
0x00, 0x00, 0x80, 0x00, 0x80, 0xff, 0x00, 0x00,
0x04, 0x2d, 0x2f, 0xff, 0x00, 0x00, 0x00, 0x00,
};
static int _tda10021_writereg (struct tda10021_state* state, u8 reg, u8 data)
{
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int ret;
ret = i2c_transfer (state->i2c, &msg, 1);
if (ret != 1)
printk("DVB: TDA10021(%d): %s, writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
state->frontend.dvb->num, __func__, reg, data, ret);
msleep(10);
return (ret != 1) ? -EREMOTEIO : 0;
}
static u8 tda10021_readreg (struct tda10021_state* state, u8 reg)
{
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
int ret;
ret = i2c_transfer (state->i2c, msg, 2);
// Don't print an error message if the id is read.
if (ret != 2 && reg != 0x1a)
printk("DVB: TDA10021: %s: readreg error (ret == %i)\n",
__func__, ret);
return b1[0];
}
//get access to tuner
static int lock_tuner(struct tda10021_state* state)
{
u8 buf[2] = { 0x0f, tda10021_inittab[0x0f] | 0x80 };
struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
if(i2c_transfer(state->i2c, &msg, 1) != 1)
{
printk("tda10021: lock tuner fails\n");
return -EREMOTEIO;
}
return 0;
}
//release access from tuner
static int unlock_tuner(struct tda10021_state* state)
{
u8 buf[2] = { 0x0f, tda10021_inittab[0x0f] & 0x7f };
struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
{
printk("tda10021: unlock tuner fails\n");
return -EREMOTEIO;
}
return 0;
}
static int tda10021_setup_reg0(struct tda10021_state *state, u8 reg0,
enum fe_spectral_inversion inversion)
{
reg0 |= state->reg0 & 0x63;
if ((INVERSION_ON == inversion) ^ (state->config->invert == 0))
reg0 &= ~0x20;
else
reg0 |= 0x20;
_tda10021_writereg (state, 0x00, reg0 & 0xfe);
_tda10021_writereg (state, 0x00, reg0 | 0x01);
state->reg0 = reg0;
return 0;
}
static int tda10021_set_symbolrate (struct tda10021_state* state, u32 symbolrate)
{
s32 BDR;
s32 BDRI;
s16 SFIL = 0;
u16 NDEC = 0;
u32 tmp, ratio;
if (symbolrate > XIN / 2)
symbolrate = XIN / 2;
else if (symbolrate < 500000)
symbolrate = 500000;
if (symbolrate < XIN / 16)
NDEC = 1;
if (symbolrate < XIN / 32)
NDEC = 2;
if (symbolrate < XIN / 64)
NDEC = 3;
if (symbolrate < XIN * 10 / 123)
SFIL = 1;
if (symbolrate < XIN * 10 / 160)
SFIL = 0;
if (symbolrate < XIN * 10 / 246)
SFIL = 1;
if (symbolrate < XIN * 10 / 320)
SFIL = 0;
if (symbolrate < XIN * 10 / 492)
SFIL = 1;
if (symbolrate < XIN * 10 / 640)
SFIL = 0;
if (symbolrate < XIN * 10 / 984)
SFIL = 1;
symbolrate <<= NDEC;
ratio = (symbolrate << 4) / FIN;
tmp = ((symbolrate << 4) % FIN) << 8;
ratio = (ratio << 8) + tmp / FIN;
tmp = (tmp % FIN) << 8;
ratio = (ratio << 8) + DIV_ROUND_CLOSEST(tmp, FIN);
BDR = ratio;
BDRI = (((XIN << 5) / symbolrate) + 1) / 2;
if (BDRI > 0xFF)
BDRI = 0xFF;
SFIL = (SFIL << 4) | tda10021_inittab[0x0E];
NDEC = (NDEC << 6) | tda10021_inittab[0x03];
_tda10021_writereg (state, 0x03, NDEC);
_tda10021_writereg (state, 0x0a, BDR&0xff);
_tda10021_writereg (state, 0x0b, (BDR>> 8)&0xff);
_tda10021_writereg (state, 0x0c, (BDR>>16)&0x3f);
_tda10021_writereg (state, 0x0d, BDRI);
_tda10021_writereg (state, 0x0e, SFIL);
return 0;
}
static int tda10021_init (struct dvb_frontend *fe)
{
struct tda10021_state* state = fe->demodulator_priv;
int i;
dprintk("DVB: TDA10021(%d): init chip\n", fe->adapter->num);
//_tda10021_writereg (fe, 0, 0);
for (i=0; i<tda10021_inittab_size; i++)
_tda10021_writereg (state, i, tda10021_inittab[i]);
_tda10021_writereg (state, 0x34, state->pwm);
//Comment by markus
//0x2A[3-0] == PDIV -> P multiplaying factor (P=PDIV+1)(default 0)
//0x2A[4] == BYPPLL -> Power down mode (default 1)
//0x2A[5] == LCK -> PLL Lock Flag
//0x2A[6] == POLAXIN -> Polarity of the input reference clock (default 0)
//Activate PLL
_tda10021_writereg(state, 0x2a, tda10021_inittab[0x2a] & 0xef);
return 0;
}
struct qam_params {
u8 conf, agcref, lthr, mseth, aref;
};
static int tda10021_set_parameters(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 delsys = c->delivery_system;
unsigned qam = c->modulation;
bool is_annex_c;
u32 reg0x3d;
struct tda10021_state* state = fe->demodulator_priv;
static const struct qam_params qam_params[] = {
/* Modulation Conf AGCref LTHR MSETH AREF */
[QPSK] = { 0x14, 0x78, 0x78, 0x8c, 0x96 },
[QAM_16] = { 0x00, 0x8c, 0x87, 0xa2, 0x91 },
[QAM_32] = { 0x04, 0x8c, 0x64, 0x74, 0x96 },
[QAM_64] = { 0x08, 0x6a, 0x46, 0x43, 0x6a },
[QAM_128] = { 0x0c, 0x78, 0x36, 0x34, 0x7e },
[QAM_256] = { 0x10, 0x5c, 0x26, 0x23, 0x6b },
};
switch (delsys) {
case SYS_DVBC_ANNEX_A:
is_annex_c = false;
break;
case SYS_DVBC_ANNEX_C:
is_annex_c = true;
break;
default:
return -EINVAL;
}
/*
* gcc optimizes the code below the same way as it would code:
* "if (qam > 5) return -EINVAL;"
* Yet, the code is clearer, as it shows what QAM standards are
* supported by the driver, and avoids the usage of magic numbers on
* it.
*/
switch (qam) {
case QPSK:
case QAM_16:
case QAM_32:
case QAM_64:
case QAM_128:
case QAM_256:
break;
default:
return -EINVAL;
}
if (c->inversion != INVERSION_ON && c->inversion != INVERSION_OFF)
return -EINVAL;
/*printk("tda10021: set frequency to %d qam=%d symrate=%d\n", p->frequency,qam,p->symbol_rate);*/
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
}
tda10021_set_symbolrate(state, c->symbol_rate);
_tda10021_writereg(state, 0x34, state->pwm);
_tda10021_writereg(state, 0x01, qam_params[qam].agcref);
_tda10021_writereg(state, 0x05, qam_params[qam].lthr);
_tda10021_writereg(state, 0x08, qam_params[qam].mseth);
_tda10021_writereg(state, 0x09, qam_params[qam].aref);
/*
* Bit 0 == 0 means roll-off = 0.15 (Annex A)
* == 1 means roll-off = 0.13 (Annex C)
*/
reg0x3d = tda10021_readreg (state, 0x3d);
if (is_annex_c)
_tda10021_writereg (state, 0x3d, 0x01 | reg0x3d);
else
_tda10021_writereg (state, 0x3d, 0xfe & reg0x3d);
tda10021_setup_reg0(state, qam_params[qam].conf, c->inversion);
return 0;
}
static int tda10021_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
struct tda10021_state* state = fe->demodulator_priv;
int sync;
*status = 0;
//0x11[0] == EQALGO -> Equalizer algorithms state
//0x11[1] == CARLOCK -> Carrier locked
//0x11[2] == FSYNC -> Frame synchronisation
//0x11[3] == FEL -> Front End locked
//0x11[6] == NODVB -> DVB Mode Information
sync = tda10021_readreg (state, 0x11);
if (sync & 2)
*status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;
if (sync & 4)
*status |= FE_HAS_SYNC|FE_HAS_VITERBI;
if (sync & 8)
*status |= FE_HAS_LOCK;
return 0;
}
static int tda10021_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda10021_state* state = fe->demodulator_priv;
u32 _ber = tda10021_readreg(state, 0x14) |
(tda10021_readreg(state, 0x15) << 8) |
((tda10021_readreg(state, 0x16) & 0x0f) << 16);
_tda10021_writereg(state, 0x10, (tda10021_readreg(state, 0x10) & ~0xc0)
| (tda10021_inittab[0x10] & 0xc0));
*ber = 10 * _ber;
return 0;
}
static int tda10021_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct tda10021_state* state = fe->demodulator_priv;
u8 config = tda10021_readreg(state, 0x02);
u8 gain = tda10021_readreg(state, 0x17);
if (config & 0x02)
/* the agc value is inverted */
gain = ~gain;
*strength = (gain << 8) | gain;
return 0;
}
static int tda10021_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct tda10021_state* state = fe->demodulator_priv;
u8 quality = ~tda10021_readreg(state, 0x18);
*snr = (quality << 8) | quality;
return 0;
}
static int tda10021_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda10021_state* state = fe->demodulator_priv;
*ucblocks = tda10021_readreg (state, 0x13) & 0x7f;
if (*ucblocks == 0x7f)
*ucblocks = 0xffffffff;
/* reset uncorrected block counter */
_tda10021_writereg (state, 0x10, tda10021_inittab[0x10] & 0xdf);
_tda10021_writereg (state, 0x10, tda10021_inittab[0x10]);
return 0;
}
static int tda10021_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
struct tda10021_state* state = fe->demodulator_priv;
int sync;
s8 afc = 0;
sync = tda10021_readreg(state, 0x11);
afc = tda10021_readreg(state, 0x19);
if (verbose) {
/* AFC only valid when carrier has been recovered */
printk(sync & 2 ? "DVB: TDA10021(%d): AFC (%d) %dHz\n" :
"DVB: TDA10021(%d): [AFC (%d) %dHz]\n",
state->frontend.dvb->num, afc,
-((s32)p->symbol_rate * afc) >> 10);
}
p->inversion = ((state->reg0 & 0x20) == 0x20) ^ (state->config->invert != 0) ? INVERSION_ON : INVERSION_OFF;
p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
p->fec_inner = FEC_NONE;
p->frequency = ((p->frequency + 31250) / 62500) * 62500;
if (sync & 2)
p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
return 0;
}
static int tda10021_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct tda10021_state* state = fe->demodulator_priv;
if (enable) {
lock_tuner(state);
} else {
unlock_tuner(state);
}
return 0;
}
static int tda10021_sleep(struct dvb_frontend* fe)
{
struct tda10021_state* state = fe->demodulator_priv;
_tda10021_writereg (state, 0x1b, 0x02); /* pdown ADC */
_tda10021_writereg (state, 0x00, 0x80); /* standby */
return 0;
}
static void tda10021_release(struct dvb_frontend* fe)
{
struct tda10021_state* state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops tda10021_ops;
struct dvb_frontend* tda10021_attach(const struct tda1002x_config* config,
struct i2c_adapter* i2c,
u8 pwm)
{
struct tda10021_state* state = NULL;
u8 id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda10021_state), GFP_KERNEL);
if (state == NULL) goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->pwm = pwm;
state->reg0 = tda10021_inittab[0];
/* check if the demod is there */
id = tda10021_readreg(state, 0x1a);
if ((id & 0xf0) != 0x70) goto error;
/* Don't claim TDA10023 */
if (id == 0x7d)
goto error;
printk("TDA10021: i2c-addr = 0x%02x, id = 0x%02x\n",
state->config->demod_address, id);
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10021_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static const struct dvb_frontend_ops tda10021_ops = {
.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
.info = {
.name = "Philips TDA10021 DVB-C",
.frequency_min_hz = 47 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 62500,
.symbol_rate_min = (XIN / 2) / 64, /* SACLK/64 == (XIN/2)/64 */
.symbol_rate_max = (XIN / 2) / 4, /* SACLK/4 */
#if 0
.frequency_tolerance = ???,
.symbol_rate_tolerance = ???, /* ppm */ /* == 8% (spec p. 5) */
#endif
.caps = 0x400 | //FE_CAN_QAM_4
FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
FE_CAN_QAM_128 | FE_CAN_QAM_256 |
FE_CAN_FEC_AUTO
},
.release = tda10021_release,
.init = tda10021_init,
.sleep = tda10021_sleep,
.i2c_gate_ctrl = tda10021_i2c_gate_ctrl,
.set_frontend = tda10021_set_parameters,
.get_frontend = tda10021_get_frontend,
.read_status = tda10021_read_status,
.read_ber = tda10021_read_ber,
.read_signal_strength = tda10021_read_signal_strength,
.read_snr = tda10021_read_snr,
.read_ucblocks = tda10021_read_ucblocks,
};
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
MODULE_DESCRIPTION("Philips TDA10021 DVB-C demodulator driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Markus Schulz");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL_GPL(tda10021_attach);
| linux-master | drivers/media/dvb-frontends/tda10021.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Montage Technology TS2020 - Silicon Tuner driver
Copyright (C) 2009-2012 Konstantin Dimitrov <[email protected]>
Copyright (C) 2009-2012 TurboSight.com
*/
#include <media/dvb_frontend.h>
#include "ts2020.h"
#include <linux/regmap.h>
#include <linux/math64.h>
#define TS2020_XTAL_FREQ 27000 /* in kHz */
#define FREQ_OFFSET_LOW_SYM_RATE 3000
struct ts2020_priv {
struct i2c_client *client;
struct mutex regmap_mutex;
struct regmap_config regmap_config;
struct regmap *regmap;
struct dvb_frontend *fe;
struct delayed_work stat_work;
int (*get_agc_pwm)(struct dvb_frontend *fe, u8 *_agc_pwm);
/* i2c details */
struct i2c_adapter *i2c;
int i2c_address;
bool loop_through:1;
u8 clk_out:2;
u8 clk_out_div:5;
bool dont_poll:1;
u32 frequency_div; /* LO output divider switch frequency */
u32 frequency_khz; /* actual used LO frequency */
#define TS2020_M88TS2020 0
#define TS2020_M88TS2022 1
u8 tuner;
};
struct ts2020_reg_val {
u8 reg;
u8 val;
};
static void ts2020_stat_work(struct work_struct *work);
static void ts2020_release(struct dvb_frontend *fe)
{
struct ts2020_priv *priv = fe->tuner_priv;
struct i2c_client *client = priv->client;
dev_dbg(&client->dev, "\n");
i2c_unregister_device(client);
}
static int ts2020_sleep(struct dvb_frontend *fe)
{
struct ts2020_priv *priv = fe->tuner_priv;
int ret;
u8 u8tmp;
if (priv->tuner == TS2020_M88TS2020)
u8tmp = 0x0a; /* XXX: probably wrong */
else
u8tmp = 0x00;
ret = regmap_write(priv->regmap, u8tmp, 0x00);
if (ret < 0)
return ret;
/* stop statistics polling */
if (!priv->dont_poll)
cancel_delayed_work_sync(&priv->stat_work);
return 0;
}
static int ts2020_init(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct ts2020_priv *priv = fe->tuner_priv;
int i;
u8 u8tmp;
if (priv->tuner == TS2020_M88TS2020) {
regmap_write(priv->regmap, 0x42, 0x73);
regmap_write(priv->regmap, 0x05, priv->clk_out_div);
regmap_write(priv->regmap, 0x20, 0x27);
regmap_write(priv->regmap, 0x07, 0x02);
regmap_write(priv->regmap, 0x11, 0xff);
regmap_write(priv->regmap, 0x60, 0xf9);
regmap_write(priv->regmap, 0x08, 0x01);
regmap_write(priv->regmap, 0x00, 0x41);
} else {
static const struct ts2020_reg_val reg_vals[] = {
{0x7d, 0x9d},
{0x7c, 0x9a},
{0x7a, 0x76},
{0x3b, 0x01},
{0x63, 0x88},
{0x61, 0x85},
{0x22, 0x30},
{0x30, 0x40},
{0x20, 0x23},
{0x24, 0x02},
{0x12, 0xa0},
};
regmap_write(priv->regmap, 0x00, 0x01);
regmap_write(priv->regmap, 0x00, 0x03);
switch (priv->clk_out) {
case TS2020_CLK_OUT_DISABLED:
u8tmp = 0x60;
break;
case TS2020_CLK_OUT_ENABLED:
u8tmp = 0x70;
regmap_write(priv->regmap, 0x05, priv->clk_out_div);
break;
case TS2020_CLK_OUT_ENABLED_XTALOUT:
u8tmp = 0x6c;
break;
default:
u8tmp = 0x60;
break;
}
regmap_write(priv->regmap, 0x42, u8tmp);
if (priv->loop_through)
u8tmp = 0xec;
else
u8tmp = 0x6c;
regmap_write(priv->regmap, 0x62, u8tmp);
for (i = 0; i < ARRAY_SIZE(reg_vals); i++)
regmap_write(priv->regmap, reg_vals[i].reg,
reg_vals[i].val);
}
/* Initialise v5 stats here */
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].uvalue = 0;
/* Start statistics polling by invoking the work function */
ts2020_stat_work(&priv->stat_work.work);
return 0;
}
static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
{
struct ts2020_priv *priv = fe->tuner_priv;
int ret;
ret = regmap_write(priv->regmap, 0x51, 0x1f - offset);
ret |= regmap_write(priv->regmap, 0x51, 0x1f);
ret |= regmap_write(priv->regmap, 0x50, offset);
ret |= regmap_write(priv->regmap, 0x50, 0x00);
msleep(20);
return ret;
}
static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
{
struct ts2020_priv *dev = fe->tuner_priv;
int ret;
unsigned int utmp;
ret = regmap_read(dev->regmap, 0x3d, &utmp);
if (ret)
return ret;
utmp &= 0x7f;
if (utmp < 0x16)
utmp = 0xa1;
else if (utmp == 0x16)
utmp = 0x99;
else
utmp = 0xf9;
regmap_write(dev->regmap, 0x60, utmp);
ret = ts2020_tuner_gate_ctrl(fe, 0x08);
return ret;
}
static int ts2020_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct ts2020_priv *priv = fe->tuner_priv;
int ret;
unsigned int utmp;
u32 f3db, gdiv28;
u16 u16tmp, value, lpf_coeff;
u8 buf[3], reg10, lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n;
unsigned int frequency_khz = c->frequency;
/*
* Integer-N PLL synthesizer
* kHz is used for all calculations to keep calculations within 32-bit
*/
f_ref_khz = TS2020_XTAL_FREQ;
div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
/* select LO output divider */
if (frequency_khz < priv->frequency_div) {
div_out = 4;
reg10 = 0x10;
} else {
div_out = 2;
reg10 = 0x00;
}
f_vco_khz = frequency_khz * div_out;
pll_n = f_vco_khz * div_ref / f_ref_khz;
pll_n += pll_n % 2;
priv->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
pr_debug("frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
priv->frequency_khz, priv->frequency_khz - c->frequency,
f_vco_khz, pll_n, div_ref, div_out);
if (priv->tuner == TS2020_M88TS2020) {
lpf_coeff = 2766;
reg10 |= 0x01;
ret = regmap_write(priv->regmap, 0x10, reg10);
} else {
lpf_coeff = 3200;
reg10 |= 0x0b;
ret = regmap_write(priv->regmap, 0x10, reg10);
ret |= regmap_write(priv->regmap, 0x11, 0x40);
}
u16tmp = pll_n - 1024;
buf[0] = (u16tmp >> 8) & 0xff;
buf[1] = (u16tmp >> 0) & 0xff;
buf[2] = div_ref - 8;
ret |= regmap_write(priv->regmap, 0x01, buf[0]);
ret |= regmap_write(priv->regmap, 0x02, buf[1]);
ret |= regmap_write(priv->regmap, 0x03, buf[2]);
ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
if (ret < 0)
return -ENODEV;
ret |= ts2020_tuner_gate_ctrl(fe, 0x08);
/* Tuner RF */
if (priv->tuner == TS2020_M88TS2020)
ret |= ts2020_set_tuner_rf(fe);
gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
ret |= regmap_write(priv->regmap, 0x04, gdiv28 & 0xff);
ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
if (ret < 0)
return -ENODEV;
if (priv->tuner == TS2020_M88TS2022) {
ret = regmap_write(priv->regmap, 0x25, 0x00);
ret |= regmap_write(priv->regmap, 0x27, 0x70);
ret |= regmap_write(priv->regmap, 0x41, 0x09);
ret |= regmap_write(priv->regmap, 0x08, 0x0b);
if (ret < 0)
return -ENODEV;
}
regmap_read(priv->regmap, 0x26, &utmp);
value = utmp;
f3db = (c->bandwidth_hz / 1000 / 2) + 2000;
f3db += FREQ_OFFSET_LOW_SYM_RATE; /* FIXME: ~always too wide filter */
f3db = clamp(f3db, 7000U, 40000U);
gdiv28 = gdiv28 * 207 / (value * 2 + 151);
mlpf_max = gdiv28 * 135 / 100;
mlpf_min = gdiv28 * 78 / 100;
if (mlpf_max > 63)
mlpf_max = 63;
nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
(TS2020_XTAL_FREQ / 1000) + 1) / 2;
if (nlpf > 23)
nlpf = 23;
if (nlpf < 1)
nlpf = 1;
lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
* lpf_coeff * 2 / f3db + 1) / 2;
if (lpf_mxdiv < mlpf_min) {
nlpf++;
lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
* lpf_coeff * 2 / f3db + 1) / 2;
}
if (lpf_mxdiv > mlpf_max)
lpf_mxdiv = mlpf_max;
ret = regmap_write(priv->regmap, 0x04, lpf_mxdiv);
ret |= regmap_write(priv->regmap, 0x06, nlpf);
ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
ret |= ts2020_tuner_gate_ctrl(fe, 0x01);
msleep(80);
return (ret < 0) ? -EINVAL : 0;
}
static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct ts2020_priv *priv = fe->tuner_priv;
*frequency = priv->frequency_khz;
return 0;
}
static int ts2020_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 0; /* Zero-IF */
return 0;
}
/*
* Get the tuner gain.
* @fe: The front end for which we're determining the gain
* @v_agc: The voltage of the AGC from the demodulator (0-2600mV)
* @_gain: Where to store the gain (in 0.001dB units)
*
* Returns 0 or a negative error code.
*/
static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc,
__s64 *_gain)
{
struct ts2020_priv *priv = fe->tuner_priv;
unsigned long gain1, gain2, gain3;
unsigned utmp;
int ret;
/* Read the RF gain */
ret = regmap_read(priv->regmap, 0x3d, &utmp);
if (ret < 0)
return ret;
gain1 = utmp & 0x1f;
/* Read the baseband gain */
ret = regmap_read(priv->regmap, 0x21, &utmp);
if (ret < 0)
return ret;
gain2 = utmp & 0x1f;
switch (priv->tuner) {
case TS2020_M88TS2020:
gain1 = clamp_t(long, gain1, 0, 15);
gain2 = clamp_t(long, gain2, 0, 13);
v_agc = clamp_t(long, v_agc, 400, 1100);
*_gain = -((__s64)gain1 * 2330 +
gain2 * 3500 +
v_agc * 24 / 10 * 10 +
10000);
/* gain in range -19600 to -116850 in units of 0.001dB */
break;
case TS2020_M88TS2022:
ret = regmap_read(priv->regmap, 0x66, &utmp);
if (ret < 0)
return ret;
gain3 = (utmp >> 3) & 0x07;
gain1 = clamp_t(long, gain1, 0, 15);
gain2 = clamp_t(long, gain2, 2, 16);
gain3 = clamp_t(long, gain3, 0, 6);
v_agc = clamp_t(long, v_agc, 600, 1600);
*_gain = -((__s64)gain1 * 2650 +
gain2 * 3380 +
gain3 * 2850 +
v_agc * 176 / 100 * 10 -
30000);
/* gain in range -47320 to -158950 in units of 0.001dB */
break;
}
return 0;
}
/*
* Get the AGC information from the demodulator and use that to calculate the
* tuner gain.
*/
static int ts2020_get_tuner_gain(struct dvb_frontend *fe, __s64 *_gain)
{
struct ts2020_priv *priv = fe->tuner_priv;
int v_agc = 0, ret;
u8 agc_pwm;
/* Read the AGC PWM rate from the demodulator */
if (priv->get_agc_pwm) {
ret = priv->get_agc_pwm(fe, &agc_pwm);
if (ret < 0)
return ret;
switch (priv->tuner) {
case TS2020_M88TS2020:
v_agc = (int)agc_pwm * 20 - 1166;
break;
case TS2020_M88TS2022:
v_agc = (int)agc_pwm * 16 - 670;
break;
}
if (v_agc < 0)
v_agc = 0;
}
return ts2020_read_tuner_gain(fe, v_agc, _gain);
}
/*
* Gather statistics on a regular basis
*/
static void ts2020_stat_work(struct work_struct *work)
{
struct ts2020_priv *priv = container_of(work, struct ts2020_priv,
stat_work.work);
struct i2c_client *client = priv->client;
struct dtv_frontend_properties *c = &priv->fe->dtv_property_cache;
int ret;
dev_dbg(&client->dev, "\n");
ret = ts2020_get_tuner_gain(priv->fe, &c->strength.stat[0].svalue);
if (ret < 0)
goto err;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
if (!priv->dont_poll)
schedule_delayed_work(&priv->stat_work, msecs_to_jiffies(2000));
return;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
}
/*
* Read TS2020 signal strength in v3 format.
*/
static int ts2020_read_signal_strength(struct dvb_frontend *fe,
u16 *_signal_strength)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct ts2020_priv *priv = fe->tuner_priv;
unsigned strength;
__s64 gain;
if (priv->dont_poll)
ts2020_stat_work(&priv->stat_work.work);
if (c->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
*_signal_strength = 0;
return 0;
}
gain = c->strength.stat[0].svalue;
/* Calculate the signal strength based on the total gain of the tuner */
if (gain < -85000)
/* 0%: no signal or weak signal */
strength = 0;
else if (gain < -65000)
/* 0% - 60%: weak signal */
strength = 0 + div64_s64((85000 + gain) * 3, 1000);
else if (gain < -45000)
/* 60% - 90%: normal signal */
strength = 60 + div64_s64((65000 + gain) * 3, 2000);
else
/* 90% - 99%: strong signal */
strength = 90 + div64_s64((45000 + gain), 5000);
*_signal_strength = strength * 65535 / 100;
return 0;
}
static const struct dvb_tuner_ops ts2020_tuner_ops = {
.info = {
.name = "TS2020",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz
},
.init = ts2020_init,
.release = ts2020_release,
.sleep = ts2020_sleep,
.set_params = ts2020_set_params,
.get_frequency = ts2020_get_frequency,
.get_if_frequency = ts2020_get_if_frequency,
.get_rf_strength = ts2020_read_signal_strength,
};
struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
const struct ts2020_config *config,
struct i2c_adapter *i2c)
{
struct i2c_client *client;
struct i2c_board_info board_info;
/* This is only used by ts2020_probe() so can be on the stack */
struct ts2020_config pdata;
memcpy(&pdata, config, sizeof(pdata));
pdata.fe = fe;
pdata.attach_in_use = true;
memset(&board_info, 0, sizeof(board_info));
strscpy(board_info.type, "ts2020", I2C_NAME_SIZE);
board_info.addr = config->tuner_address;
board_info.platform_data = &pdata;
client = i2c_new_client_device(i2c, &board_info);
if (!i2c_client_has_driver(client))
return NULL;
return fe;
}
EXPORT_SYMBOL_GPL(ts2020_attach);
/*
* We implement own regmap locking due to legacy DVB attach which uses frontend
* gate control callback to control I2C bus access. We can open / close gate and
* serialize whole open / I2C-operation / close sequence at the same.
*/
static void ts2020_regmap_lock(void *__dev)
{
struct ts2020_priv *dev = __dev;
mutex_lock(&dev->regmap_mutex);
if (dev->fe->ops.i2c_gate_ctrl)
dev->fe->ops.i2c_gate_ctrl(dev->fe, 1);
}
static void ts2020_regmap_unlock(void *__dev)
{
struct ts2020_priv *dev = __dev;
if (dev->fe->ops.i2c_gate_ctrl)
dev->fe->ops.i2c_gate_ctrl(dev->fe, 0);
mutex_unlock(&dev->regmap_mutex);
}
static int ts2020_probe(struct i2c_client *client)
{
struct ts2020_config *pdata = client->dev.platform_data;
struct dvb_frontend *fe = pdata->fe;
struct ts2020_priv *dev;
int ret;
u8 u8tmp;
unsigned int utmp;
char *chip_str;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err;
}
/* create regmap */
mutex_init(&dev->regmap_mutex);
dev->regmap_config.reg_bits = 8;
dev->regmap_config.val_bits = 8;
dev->regmap_config.lock = ts2020_regmap_lock;
dev->regmap_config.unlock = ts2020_regmap_unlock;
dev->regmap_config.lock_arg = dev;
dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
goto err_kfree;
}
dev->i2c = client->adapter;
dev->i2c_address = client->addr;
dev->loop_through = pdata->loop_through;
dev->clk_out = pdata->clk_out;
dev->clk_out_div = pdata->clk_out_div;
dev->dont_poll = pdata->dont_poll;
dev->frequency_div = pdata->frequency_div;
dev->fe = fe;
dev->get_agc_pwm = pdata->get_agc_pwm;
fe->tuner_priv = dev;
dev->client = client;
INIT_DELAYED_WORK(&dev->stat_work, ts2020_stat_work);
/* check if the tuner is there */
ret = regmap_read(dev->regmap, 0x00, &utmp);
if (ret)
goto err_regmap_exit;
if ((utmp & 0x03) == 0x00) {
ret = regmap_write(dev->regmap, 0x00, 0x01);
if (ret)
goto err_regmap_exit;
usleep_range(2000, 50000);
}
ret = regmap_write(dev->regmap, 0x00, 0x03);
if (ret)
goto err_regmap_exit;
usleep_range(2000, 50000);
ret = regmap_read(dev->regmap, 0x00, &utmp);
if (ret)
goto err_regmap_exit;
dev_dbg(&client->dev, "chip_id=%02x\n", utmp);
switch (utmp) {
case 0x01:
case 0x41:
case 0x81:
dev->tuner = TS2020_M88TS2020;
chip_str = "TS2020";
if (!dev->frequency_div)
dev->frequency_div = 1060000;
break;
case 0xc3:
case 0x83:
dev->tuner = TS2020_M88TS2022;
chip_str = "TS2022";
if (!dev->frequency_div)
dev->frequency_div = 1103000;
break;
default:
ret = -ENODEV;
goto err_regmap_exit;
}
if (dev->tuner == TS2020_M88TS2022) {
switch (dev->clk_out) {
case TS2020_CLK_OUT_DISABLED:
u8tmp = 0x60;
break;
case TS2020_CLK_OUT_ENABLED:
u8tmp = 0x70;
ret = regmap_write(dev->regmap, 0x05, dev->clk_out_div);
if (ret)
goto err_regmap_exit;
break;
case TS2020_CLK_OUT_ENABLED_XTALOUT:
u8tmp = 0x6c;
break;
default:
ret = -EINVAL;
goto err_regmap_exit;
}
ret = regmap_write(dev->regmap, 0x42, u8tmp);
if (ret)
goto err_regmap_exit;
if (dev->loop_through)
u8tmp = 0xec;
else
u8tmp = 0x6c;
ret = regmap_write(dev->regmap, 0x62, u8tmp);
if (ret)
goto err_regmap_exit;
}
/* sleep */
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err_regmap_exit;
dev_info(&client->dev,
"Montage Technology %s successfully identified\n", chip_str);
memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
sizeof(struct dvb_tuner_ops));
if (!pdata->attach_in_use)
fe->ops.tuner_ops.release = NULL;
i2c_set_clientdata(client, dev);
return 0;
err_regmap_exit:
regmap_exit(dev->regmap);
err_kfree:
kfree(dev);
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static void ts2020_remove(struct i2c_client *client)
{
struct ts2020_priv *dev = i2c_get_clientdata(client);
dev_dbg(&client->dev, "\n");
/* stop statistics polling */
if (!dev->dont_poll)
cancel_delayed_work_sync(&dev->stat_work);
regmap_exit(dev->regmap);
kfree(dev);
}
static const struct i2c_device_id ts2020_id_table[] = {
{"ts2020", 0},
{"ts2022", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, ts2020_id_table);
static struct i2c_driver ts2020_driver = {
.driver = {
.name = "ts2020",
},
.probe = ts2020_probe,
.remove = ts2020_remove,
.id_table = ts2020_id_table,
};
module_i2c_driver(ts2020_driver);
MODULE_AUTHOR("Konstantin Dimitrov <[email protected]>");
MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/ts2020.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Driver for ST STV0288 demodulator
Copyright (C) 2006 Georg Acher, BayCom GmbH, acher (at) baycom (dot) de
for Reel Multimedia
Copyright (C) 2008 TurboSight.com, Bob Liu <[email protected]>
Copyright (C) 2008 Igor M. Liplianin <[email protected]>
Removed stb6000 specific tuner code and revised some
procedures.
2010-09-01 Josef Pavlik <[email protected]>
Fixed diseqc_msg, diseqc_burst and set_tone problems
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "stv0288.h"
struct stv0288_state {
struct i2c_adapter *i2c;
const struct stv0288_config *config;
struct dvb_frontend frontend;
u8 initialised:1;
u32 tuner_frequency;
u32 symbol_rate;
enum fe_code_rate fec_inner;
int errmode;
};
#define STATUS_BER 0
#define STATUS_UCBLOCKS 1
static int debug;
static int debug_legacy_dish_switch;
#define dprintk(args...) \
do { \
if (debug) \
printk(KERN_DEBUG "stv0288: " args); \
} while (0)
static int stv0288_writeregI(struct stv0288_state *state, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
__func__, reg, data, ret);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int stv0288_write(struct dvb_frontend *fe, const u8 buf[], int len)
{
struct stv0288_state *state = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return stv0288_writeregI(state, buf[0], buf[1]);
}
static u8 stv0288_readreg(struct stv0288_state *state, u8 reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2)
dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n",
__func__, reg, ret);
return b1[0];
}
static int stv0288_set_symbolrate(struct dvb_frontend *fe, u32 srate)
{
struct stv0288_state *state = fe->demodulator_priv;
unsigned int temp;
unsigned char b[3];
if ((srate < 1000000) || (srate > 45000000))
return -EINVAL;
stv0288_writeregI(state, 0x22, 0);
stv0288_writeregI(state, 0x23, 0);
stv0288_writeregI(state, 0x2b, 0xff);
stv0288_writeregI(state, 0x2c, 0xf7);
temp = (unsigned int)srate / 1000;
temp = temp * 32768;
temp = temp / 25;
temp = temp / 125;
b[0] = (unsigned char)((temp >> 12) & 0xff);
b[1] = (unsigned char)((temp >> 4) & 0xff);
b[2] = (unsigned char)((temp << 4) & 0xf0);
stv0288_writeregI(state, 0x28, 0x80); /* SFRH */
stv0288_writeregI(state, 0x29, 0); /* SFRM */
stv0288_writeregI(state, 0x2a, 0); /* SFRL */
stv0288_writeregI(state, 0x28, b[0]);
stv0288_writeregI(state, 0x29, b[1]);
stv0288_writeregI(state, 0x2a, b[2]);
dprintk("stv0288: stv0288_set_symbolrate\n");
return 0;
}
static int stv0288_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *m)
{
struct stv0288_state *state = fe->demodulator_priv;
int i;
dprintk("%s\n", __func__);
stv0288_writeregI(state, 0x09, 0);
msleep(30);
stv0288_writeregI(state, 0x05, 0x12);/* modulated mode, single shot */
for (i = 0; i < m->msg_len; i++) {
if (stv0288_writeregI(state, 0x06, m->msg[i]))
return -EREMOTEIO;
}
msleep(m->msg_len*12);
return 0;
}
static int stv0288_send_diseqc_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd burst)
{
struct stv0288_state *state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (stv0288_writeregI(state, 0x05, 0x03))/* burst mode, single shot */
return -EREMOTEIO;
if (stv0288_writeregI(state, 0x06, burst == SEC_MINI_A ? 0x00 : 0xff))
return -EREMOTEIO;
msleep(15);
if (stv0288_writeregI(state, 0x05, 0x12))
return -EREMOTEIO;
return 0;
}
static int stv0288_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct stv0288_state *state = fe->demodulator_priv;
switch (tone) {
case SEC_TONE_ON:
if (stv0288_writeregI(state, 0x05, 0x10))/* cont carrier */
return -EREMOTEIO;
break;
case SEC_TONE_OFF:
if (stv0288_writeregI(state, 0x05, 0x12))/* burst mode off*/
return -EREMOTEIO;
break;
default:
return -EINVAL;
}
return 0;
}
static u8 stv0288_inittab[] = {
0x01, 0x15,
0x02, 0x20,
0x09, 0x0,
0x0a, 0x4,
0x0b, 0x0,
0x0c, 0x0,
0x0d, 0x0,
0x0e, 0xd4,
0x0f, 0x30,
0x11, 0x80,
0x12, 0x03,
0x13, 0x48,
0x14, 0x84,
0x15, 0x45,
0x16, 0xb7,
0x17, 0x9c,
0x18, 0x0,
0x19, 0xa6,
0x1a, 0x88,
0x1b, 0x8f,
0x1c, 0xf0,
0x20, 0x0b,
0x21, 0x54,
0x22, 0x0,
0x23, 0x0,
0x2b, 0xff,
0x2c, 0xf7,
0x30, 0x0,
0x31, 0x1e,
0x32, 0x14,
0x33, 0x0f,
0x34, 0x09,
0x35, 0x0c,
0x36, 0x05,
0x37, 0x2f,
0x38, 0x16,
0x39, 0xbe,
0x3a, 0x0,
0x3b, 0x13,
0x3c, 0x11,
0x3d, 0x30,
0x40, 0x63,
0x41, 0x04,
0x42, 0x20,
0x43, 0x00,
0x44, 0x00,
0x45, 0x00,
0x46, 0x00,
0x47, 0x00,
0x4a, 0x00,
0x50, 0x10,
0x51, 0x38,
0x52, 0x21,
0x58, 0x54,
0x59, 0x86,
0x5a, 0x0,
0x5b, 0x9b,
0x5c, 0x08,
0x5d, 0x7f,
0x5e, 0x0,
0x5f, 0xff,
0x70, 0x0,
0x71, 0x0,
0x72, 0x0,
0x74, 0x0,
0x75, 0x0,
0x76, 0x0,
0x81, 0x0,
0x82, 0x3f,
0x83, 0x3f,
0x84, 0x0,
0x85, 0x0,
0x88, 0x0,
0x89, 0x0,
0x8a, 0x0,
0x8b, 0x0,
0x8c, 0x0,
0x90, 0x0,
0x91, 0x0,
0x92, 0x0,
0x93, 0x0,
0x94, 0x1c,
0x97, 0x0,
0xa0, 0x48,
0xa1, 0x0,
0xb0, 0xb8,
0xb1, 0x3a,
0xb2, 0x10,
0xb3, 0x82,
0xb4, 0x80,
0xb5, 0x82,
0xb6, 0x82,
0xb7, 0x82,
0xb8, 0x20,
0xb9, 0x0,
0xf0, 0x0,
0xf1, 0x0,
0xf2, 0xc0,
0x51, 0x36,
0x52, 0x09,
0x53, 0x94,
0x54, 0x62,
0x55, 0x29,
0x56, 0x64,
0x57, 0x2b,
0xff, 0xff,
};
static int stv0288_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage volt)
{
dprintk("%s: %s\n", __func__,
volt == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
volt == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
return 0;
}
static int stv0288_init(struct dvb_frontend *fe)
{
struct stv0288_state *state = fe->demodulator_priv;
int i;
u8 reg;
u8 val;
dprintk("stv0288: init chip\n");
stv0288_writeregI(state, 0x41, 0x04);
msleep(50);
/* we have default inittab */
if (state->config->inittab == NULL) {
for (i = 0; !(stv0288_inittab[i] == 0xff &&
stv0288_inittab[i + 1] == 0xff); i += 2)
stv0288_writeregI(state, stv0288_inittab[i],
stv0288_inittab[i + 1]);
} else {
for (i = 0; ; i += 2) {
reg = state->config->inittab[i];
val = state->config->inittab[i+1];
if (reg == 0xff && val == 0xff)
break;
stv0288_writeregI(state, reg, val);
}
}
return 0;
}
static int stv0288_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stv0288_state *state = fe->demodulator_priv;
u8 sync = stv0288_readreg(state, 0x24);
if (sync == 255)
sync = 0;
dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync);
*status = 0;
if (sync & 0x80)
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
if (sync & 0x10)
*status |= FE_HAS_VITERBI;
if (sync & 0x08) {
*status |= FE_HAS_LOCK;
dprintk("stv0288 has locked\n");
}
return 0;
}
static int stv0288_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct stv0288_state *state = fe->demodulator_priv;
if (state->errmode != STATUS_BER)
return 0;
*ber = (stv0288_readreg(state, 0x26) << 8) |
stv0288_readreg(state, 0x27);
dprintk("stv0288_read_ber %d\n", *ber);
return 0;
}
static int stv0288_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stv0288_state *state = fe->demodulator_priv;
s32 signal = 0xffff - ((stv0288_readreg(state, 0x10) << 8));
signal = signal * 5 / 4;
*strength = (signal > 0xffff) ? 0xffff : (signal < 0) ? 0 : signal;
dprintk("stv0288_read_signal_strength %d\n", *strength);
return 0;
}
static int stv0288_sleep(struct dvb_frontend *fe)
{
struct stv0288_state *state = fe->demodulator_priv;
stv0288_writeregI(state, 0x41, 0x84);
state->initialised = 0;
return 0;
}
static int stv0288_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct stv0288_state *state = fe->demodulator_priv;
s32 xsnr = 0xffff - ((stv0288_readreg(state, 0x2d) << 8)
| stv0288_readreg(state, 0x2e));
xsnr = 3 * (xsnr - 0xa100);
*snr = (xsnr > 0xffff) ? 0xffff : (xsnr < 0) ? 0 : xsnr;
dprintk("stv0288_read_snr %d\n", *snr);
return 0;
}
static int stv0288_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct stv0288_state *state = fe->demodulator_priv;
if (state->errmode != STATUS_BER)
return 0;
*ucblocks = (stv0288_readreg(state, 0x26) << 8) |
stv0288_readreg(state, 0x27);
dprintk("stv0288_read_ber %d\n", *ucblocks);
return 0;
}
static int stv0288_set_frontend(struct dvb_frontend *fe)
{
struct stv0288_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 tda[3], reg, time_out = 0;
s8 tm;
dprintk("%s : FE_SET_FRONTEND\n", __func__);
if (c->delivery_system != SYS_DVBS) {
dprintk("%s: unsupported delivery system selected (%d)\n",
__func__, c->delivery_system);
return -EOPNOTSUPP;
}
if (state->config->set_ts_params)
state->config->set_ts_params(fe, 0);
/* only frequency & symbol_rate are used for tuner*/
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
udelay(10);
stv0288_set_symbolrate(fe, c->symbol_rate);
/* Carrier lock control register */
stv0288_writeregI(state, 0x15, 0xc5);
tda[2] = 0x0; /* CFRL */
for (tm = -9; tm < 7;) {
/* Viterbi status */
reg = stv0288_readreg(state, 0x24);
if (reg & 0x8)
break;
if (reg & 0x80) {
time_out++;
if (time_out > 10)
break;
tda[2] += 40;
if (tda[2] < 40)
tm++;
} else {
tm++;
tda[2] = 0;
time_out = 0;
}
tda[1] = (unsigned char)tm;
stv0288_writeregI(state, 0x2b, tda[1]);
stv0288_writeregI(state, 0x2c, tda[2]);
msleep(30);
}
state->tuner_frequency = c->frequency;
state->fec_inner = FEC_AUTO;
state->symbol_rate = c->symbol_rate;
return 0;
}
static int stv0288_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0288_state *state = fe->demodulator_priv;
if (enable)
stv0288_writeregI(state, 0x01, 0xb5);
else
stv0288_writeregI(state, 0x01, 0x35);
udelay(1);
return 0;
}
static void stv0288_release(struct dvb_frontend *fe)
{
struct stv0288_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops stv0288_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "ST STV0288 DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 1 * MHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500, /* ppm */
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = stv0288_release,
.init = stv0288_init,
.sleep = stv0288_sleep,
.write = stv0288_write,
.i2c_gate_ctrl = stv0288_i2c_gate_ctrl,
.read_status = stv0288_read_status,
.read_ber = stv0288_read_ber,
.read_signal_strength = stv0288_read_signal_strength,
.read_snr = stv0288_read_snr,
.read_ucblocks = stv0288_read_ucblocks,
.diseqc_send_master_cmd = stv0288_send_diseqc_msg,
.diseqc_send_burst = stv0288_send_diseqc_burst,
.set_tone = stv0288_set_tone,
.set_voltage = stv0288_set_voltage,
.set_frontend = stv0288_set_frontend,
};
struct dvb_frontend *stv0288_attach(const struct stv0288_config *config,
struct i2c_adapter *i2c)
{
struct stv0288_state *state = NULL;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct stv0288_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->config = config;
state->i2c = i2c;
state->initialised = 0;
state->tuner_frequency = 0;
state->symbol_rate = 0;
state->fec_inner = 0;
state->errmode = STATUS_BER;
stv0288_writeregI(state, 0x41, 0x04);
msleep(200);
id = stv0288_readreg(state, 0x00);
dprintk("stv0288 id %x\n", id);
/* register 0x00 contains 0x11 for STV0288 */
if (id != 0x11)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &stv0288_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(stv0288_attach);
module_param(debug_legacy_dish_switch, int, 0444);
MODULE_PARM_DESC(debug_legacy_dish_switch,
"Enable timing analysis for Dish Network legacy switches");
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("ST STV0288 DVB Demodulator driver");
MODULE_AUTHOR("Georg Acher, Bob Liu, Igor liplianin");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/stv0288.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Dummy Frontend
*
* Written by Emard <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <media/dvb_frontend.h>
#include "dvb_dummy_fe.h"
struct dvb_dummy_fe_state {
struct dvb_frontend frontend;
};
static int dvb_dummy_fe_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
return 0;
}
static int dvb_dummy_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
{
*ber = 0;
return 0;
}
static int dvb_dummy_fe_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
*strength = 0;
return 0;
}
static int dvb_dummy_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
{
*snr = 0;
return 0;
}
static int dvb_dummy_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
*ucblocks = 0;
return 0;
}
/*
* Should only be implemented if it actually reads something from the hardware.
* Also, it should check for the locks, in order to avoid report wrong data
* to userspace.
*/
static int dvb_dummy_fe_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *p)
{
return 0;
}
static int dvb_dummy_fe_set_frontend(struct dvb_frontend *fe)
{
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
return 0;
}
static int dvb_dummy_fe_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int dvb_dummy_fe_init(struct dvb_frontend *fe)
{
return 0;
}
static int dvb_dummy_fe_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
return 0;
}
static int dvb_dummy_fe_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
return 0;
}
static void dvb_dummy_fe_release(struct dvb_frontend *fe)
{
struct dvb_dummy_fe_state *state = fe->demodulator_priv;
kfree(state);
}
static const struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops;
struct dvb_frontend *dvb_dummy_fe_ofdm_attach(void)
{
struct dvb_dummy_fe_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
if (!state)
return NULL;
/* create dvb_frontend */
memcpy(&state->frontend.ops,
&dvb_dummy_fe_ofdm_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL(dvb_dummy_fe_ofdm_attach);
static const struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops;
struct dvb_frontend *dvb_dummy_fe_qpsk_attach(void)
{
struct dvb_dummy_fe_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
if (!state)
return NULL;
/* create dvb_frontend */
memcpy(&state->frontend.ops,
&dvb_dummy_fe_qpsk_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL(dvb_dummy_fe_qpsk_attach);
static const struct dvb_frontend_ops dvb_dummy_fe_qam_ops;
struct dvb_frontend *dvb_dummy_fe_qam_attach(void)
{
struct dvb_dummy_fe_state *state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
if (!state)
return NULL;
/* create dvb_frontend */
memcpy(&state->frontend.ops,
&dvb_dummy_fe_qam_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
EXPORT_SYMBOL(dvb_dummy_fe_qam_attach);
static const struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "Dummy DVB-T",
.frequency_min_hz = 0,
.frequency_max_hz = 863250 * kHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_6_7 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_8_9 |
FE_CAN_FEC_AUTO |
FE_CAN_QAM_16 |
FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO,
},
.release = dvb_dummy_fe_release,
.init = dvb_dummy_fe_init,
.sleep = dvb_dummy_fe_sleep,
.set_frontend = dvb_dummy_fe_set_frontend,
.get_frontend = dvb_dummy_fe_get_frontend,
.read_status = dvb_dummy_fe_read_status,
.read_ber = dvb_dummy_fe_read_ber,
.read_signal_strength = dvb_dummy_fe_read_signal_strength,
.read_snr = dvb_dummy_fe_read_snr,
.read_ucblocks = dvb_dummy_fe_read_ucblocks,
};
static const struct dvb_frontend_ops dvb_dummy_fe_qam_ops = {
.delsys = { SYS_DVBC_ANNEX_A },
.info = {
.name = "Dummy DVB-C",
.frequency_min_hz = 51 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
/* symbol_rate_min: SACLK/64 == (XIN/2)/64 */
.symbol_rate_min = (57840000 / 2) / 64,
.symbol_rate_max = (57840000 / 2) / 4, /* SACLK/4 */
.caps = FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_FEC_AUTO |
FE_CAN_INVERSION_AUTO
},
.release = dvb_dummy_fe_release,
.init = dvb_dummy_fe_init,
.sleep = dvb_dummy_fe_sleep,
.set_frontend = dvb_dummy_fe_set_frontend,
.get_frontend = dvb_dummy_fe_get_frontend,
.read_status = dvb_dummy_fe_read_status,
.read_ber = dvb_dummy_fe_read_ber,
.read_signal_strength = dvb_dummy_fe_read_signal_strength,
.read_snr = dvb_dummy_fe_read_snr,
.read_ucblocks = dvb_dummy_fe_read_ucblocks,
};
static const struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Dummy DVB-S",
.frequency_min_hz = 950 * MHz,
.frequency_max_hz = 2150 * MHz,
.frequency_stepsize_hz = 250 * kHz,
.frequency_tolerance_hz = 29500 * kHz,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK
},
.release = dvb_dummy_fe_release,
.init = dvb_dummy_fe_init,
.sleep = dvb_dummy_fe_sleep,
.set_frontend = dvb_dummy_fe_set_frontend,
.get_frontend = dvb_dummy_fe_get_frontend,
.read_status = dvb_dummy_fe_read_status,
.read_ber = dvb_dummy_fe_read_ber,
.read_signal_strength = dvb_dummy_fe_read_signal_strength,
.read_snr = dvb_dummy_fe_read_snr,
.read_ucblocks = dvb_dummy_fe_read_ucblocks,
.set_voltage = dvb_dummy_fe_set_voltage,
.set_tone = dvb_dummy_fe_set_tone,
};
MODULE_DESCRIPTION("DVB DUMMY Frontend");
MODULE_AUTHOR("Emard");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/dvb-frontends/dvb_dummy_fe.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Sony CXD2820R demodulator driver
*
* Copyright (C) 2010 Antti Palosaari <[email protected]>
*/
#include "cxd2820r_priv.h"
int cxd2820r_set_frontend_c(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
unsigned int utmp;
u8 buf[2];
u32 if_frequency;
struct reg_val_mask tab[] = {
{ 0x00080, 0x01, 0xff },
{ 0x00081, 0x05, 0xff },
{ 0x00085, 0x07, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x00082, 0x20, 0x60 },
{ 0x1016a, 0x48, 0xff },
{ 0x100a5, 0x00, 0x01 },
{ 0x10020, 0x06, 0x07 },
{ 0x10059, 0x50, 0xff },
{ 0x10087, 0x0c, 0x3c },
{ 0x1008b, 0x07, 0xff },
{ 0x1001f, priv->if_agc_polarity << 7, 0x80 },
{ 0x10070, priv->ts_mode, 0xff },
{ 0x10071, !priv->ts_clk_inv << 4, 0x10 },
};
dev_dbg(&client->dev,
"delivery_system=%d modulation=%d frequency=%u symbol_rate=%u inversion=%d\n",
c->delivery_system, c->modulation, c->frequency,
c->symbol_rate, c->inversion);
/* program tuner */
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe);
if (priv->delivery_system != SYS_DVBC_ANNEX_A) {
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
}
priv->delivery_system = SYS_DVBC_ANNEX_A;
priv->ber_running = false; /* tune stops BER counter */
/* program IF frequency */
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
if (ret)
goto error;
dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
} else {
ret = -EINVAL;
goto error;
}
utmp = 0x4000 - DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x4000, CXD2820R_CLK);
buf[0] = (utmp >> 8) & 0xff;
buf[1] = (utmp >> 0) & 0xff;
ret = regmap_bulk_write(priv->regmap[1], 0x0042, buf, 2);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
if (ret)
goto error;
ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_frontend_c(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
unsigned int utmp;
u8 buf[2];
dev_dbg(&client->dev, "\n");
ret = regmap_bulk_read(priv->regmap[1], 0x001a, buf, 2);
if (ret)
goto error;
c->symbol_rate = 2500 * ((buf[0] & 0x0f) << 8 | buf[1]);
ret = regmap_read(priv->regmap[1], 0x0019, &utmp);
if (ret)
goto error;
switch ((utmp >> 0) & 0x07) {
case 0:
c->modulation = QAM_16;
break;
case 1:
c->modulation = QAM_32;
break;
case 2:
c->modulation = QAM_64;
break;
case 3:
c->modulation = QAM_128;
break;
case 4:
c->modulation = QAM_256;
break;
}
switch ((utmp >> 7) & 0x01) {
case 0:
c->inversion = INVERSION_OFF;
break;
case 1:
c->inversion = INVERSION_ON;
break;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_read_status_c(struct dvb_frontend *fe, enum fe_status *status)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret;
unsigned int utmp, utmp1, utmp2;
u8 buf[3];
/* Lock detection */
ret = regmap_bulk_read(priv->regmap[1], 0x0088, &buf[0], 1);
if (ret)
goto error;
ret = regmap_bulk_read(priv->regmap[1], 0x0073, &buf[1], 1);
if (ret)
goto error;
utmp1 = (buf[0] >> 0) & 0x01;
utmp2 = (buf[1] >> 3) & 0x01;
if (utmp1 == 1 && utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else if (utmp1 == 1 || utmp2 == 1) {
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC;
} else {
*status = 0;
}
dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
*status, 2, buf, utmp1, utmp2);
/* Signal strength */
if (*status & FE_HAS_SIGNAL) {
unsigned int strength;
ret = regmap_bulk_read(priv->regmap[1], 0x0049, buf, 2);
if (ret)
goto error;
utmp = buf[0] << 8 | buf[1] << 0;
utmp = 511 - sign_extend32(utmp, 9);
/* Scale value to 0x0000-0xffff */
strength = utmp << 6 | utmp >> 4;
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_RELATIVE;
c->strength.stat[0].uvalue = strength;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* CNR */
if (*status & FE_HAS_VITERBI) {
unsigned int cnr, const_a, const_b;
ret = regmap_read(priv->regmap[1], 0x0019, &utmp);
if (ret)
goto error;
if (((utmp >> 0) & 0x03) % 2) {
const_a = 8750;
const_b = 650;
} else {
const_a = 9500;
const_b = 760;
}
ret = regmap_read(priv->regmap[1], 0x004d, &utmp);
if (ret)
goto error;
#define CXD2820R_LOG2_E_24 24204406 /* log2(e) << 24 */
if (utmp)
cnr = div_u64((u64)(intlog2(const_b) - intlog2(utmp))
* const_a, CXD2820R_LOG2_E_24);
else
cnr = 0;
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = cnr;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
/* BER */
if (*status & FE_HAS_SYNC) {
unsigned int post_bit_error;
bool start_ber;
if (priv->ber_running) {
ret = regmap_bulk_read(priv->regmap[1], 0x0076, buf, 3);
if (ret)
goto error;
if ((buf[2] >> 7) & 0x01) {
post_bit_error = buf[2] << 16 | buf[1] << 8 |
buf[0] << 0;
post_bit_error &= 0x0fffff;
start_ber = true;
} else {
post_bit_error = 0;
start_ber = false;
}
} else {
post_bit_error = 0;
start_ber = true;
}
if (start_ber) {
ret = regmap_write(priv->regmap[1], 0x0079, 0x01);
if (ret)
goto error;
priv->ber_running = true;
}
priv->post_bit_error += post_bit_error;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
} else {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
}
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_init_c(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
dev_dbg(&client->dev, "\n");
ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_sleep_c(struct dvb_frontend *fe)
{
struct cxd2820r_priv *priv = fe->demodulator_priv;
struct i2c_client *client = priv->client[0];
int ret;
static const struct reg_val_mask tab[] = {
{ 0x000ff, 0x1f, 0xff },
{ 0x00085, 0x00, 0xff },
{ 0x00088, 0x01, 0xff },
{ 0x00081, 0x00, 0xff },
{ 0x00080, 0x00, 0xff },
};
dev_dbg(&client->dev, "\n");
priv->delivery_system = SYS_UNDEFINED;
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
if (ret)
goto error;
return ret;
error:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *s)
{
s->min_delay_ms = 500;
s->step_size = 0; /* no zigzag */
s->max_drift = 0;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2820r_c.c |
/*
Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Trident Microsystems nor Hauppauge Computer Works
nor the names of its contributors may be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
DRXJ specific implementation of DRX driver
authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
written by Devin Heitmueller <[email protected]>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*-----------------------------------------------------------------------------
INCLUDE FILES
----------------------------------------------------------------------------*/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <media/dvb_frontend.h>
#include "drx39xxj.h"
#include "drxj.h"
#include "drxj_map.h"
/*============================================================================*/
/*=== DEFINES ================================================================*/
/*============================================================================*/
#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
/*
* \brief Maximum u32 value.
*/
#ifndef MAX_U32
#define MAX_U32 ((u32) (0xFFFFFFFFL))
#endif
/* Customer configurable hardware settings, etc */
#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
#endif
#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
#endif
#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
#endif
#ifndef OOB_CRX_DRIVE_STRENGTH
#define OOB_CRX_DRIVE_STRENGTH 0x02
#endif
#ifndef OOB_DRX_DRIVE_STRENGTH
#define OOB_DRX_DRIVE_STRENGTH 0x02
#endif
/*** START DJCOMBO patches to DRXJ registermap constants *********************/
/*** registermap 200706071303 from drxj **************************************/
#define ATV_TOP_CR_AMP_TH_FM 0x0
#define ATV_TOP_CR_AMP_TH_L 0xA
#define ATV_TOP_CR_AMP_TH_LP 0xA
#define ATV_TOP_CR_AMP_TH_BG 0x8
#define ATV_TOP_CR_AMP_TH_DK 0x8
#define ATV_TOP_CR_AMP_TH_I 0x8
#define ATV_TOP_CR_CONT_CR_D_MN 0x18
#define ATV_TOP_CR_CONT_CR_D_FM 0x0
#define ATV_TOP_CR_CONT_CR_D_L 0x20
#define ATV_TOP_CR_CONT_CR_D_LP 0x20
#define ATV_TOP_CR_CONT_CR_D_BG 0x18
#define ATV_TOP_CR_CONT_CR_D_DK 0x18
#define ATV_TOP_CR_CONT_CR_D_I 0x18
#define ATV_TOP_CR_CONT_CR_I_MN 0x80
#define ATV_TOP_CR_CONT_CR_I_FM 0x0
#define ATV_TOP_CR_CONT_CR_I_L 0x80
#define ATV_TOP_CR_CONT_CR_I_LP 0x80
#define ATV_TOP_CR_CONT_CR_I_BG 0x80
#define ATV_TOP_CR_CONT_CR_I_DK 0x80
#define ATV_TOP_CR_CONT_CR_I_I 0x80
#define ATV_TOP_CR_CONT_CR_P_MN 0x4
#define ATV_TOP_CR_CONT_CR_P_FM 0x0
#define ATV_TOP_CR_CONT_CR_P_L 0x4
#define ATV_TOP_CR_CONT_CR_P_LP 0x4
#define ATV_TOP_CR_CONT_CR_P_BG 0x4
#define ATV_TOP_CR_CONT_CR_P_DK 0x4
#define ATV_TOP_CR_CONT_CR_P_I 0x4
#define ATV_TOP_CR_OVM_TH_MN 0xA0
#define ATV_TOP_CR_OVM_TH_FM 0x0
#define ATV_TOP_CR_OVM_TH_L 0xA0
#define ATV_TOP_CR_OVM_TH_LP 0xA0
#define ATV_TOP_CR_OVM_TH_BG 0xA0
#define ATV_TOP_CR_OVM_TH_DK 0xA0
#define ATV_TOP_CR_OVM_TH_I 0xA0
#define ATV_TOP_EQU0_EQU_C0_FM 0x0
#define ATV_TOP_EQU0_EQU_C0_L 0x3
#define ATV_TOP_EQU0_EQU_C0_LP 0x3
#define ATV_TOP_EQU0_EQU_C0_BG 0x7
#define ATV_TOP_EQU0_EQU_C0_DK 0x0
#define ATV_TOP_EQU0_EQU_C0_I 0x3
#define ATV_TOP_EQU1_EQU_C1_FM 0x0
#define ATV_TOP_EQU1_EQU_C1_L 0x1F6
#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
#define ATV_TOP_EQU1_EQU_C1_BG 0x197
#define ATV_TOP_EQU1_EQU_C1_DK 0x198
#define ATV_TOP_EQU1_EQU_C1_I 0x1F6
#define ATV_TOP_EQU2_EQU_C2_FM 0x0
#define ATV_TOP_EQU2_EQU_C2_L 0x28
#define ATV_TOP_EQU2_EQU_C2_LP 0x28
#define ATV_TOP_EQU2_EQU_C2_BG 0xC5
#define ATV_TOP_EQU2_EQU_C2_DK 0xB0
#define ATV_TOP_EQU2_EQU_C2_I 0x28
#define ATV_TOP_EQU3_EQU_C3_FM 0x0
#define ATV_TOP_EQU3_EQU_C3_L 0x192
#define ATV_TOP_EQU3_EQU_C3_LP 0x192
#define ATV_TOP_EQU3_EQU_C3_BG 0x12E
#define ATV_TOP_EQU3_EQU_C3_DK 0x18E
#define ATV_TOP_EQU3_EQU_C3_I 0x192
#define ATV_TOP_STD_MODE_MN 0x0
#define ATV_TOP_STD_MODE_FM 0x1
#define ATV_TOP_STD_MODE_L 0x0
#define ATV_TOP_STD_MODE_LP 0x0
#define ATV_TOP_STD_MODE_BG 0x0
#define ATV_TOP_STD_MODE_DK 0x0
#define ATV_TOP_STD_MODE_I 0x0
#define ATV_TOP_STD_VID_POL_MN 0x0
#define ATV_TOP_STD_VID_POL_FM 0x0
#define ATV_TOP_STD_VID_POL_L 0x2
#define ATV_TOP_STD_VID_POL_LP 0x2
#define ATV_TOP_STD_VID_POL_BG 0x0
#define ATV_TOP_STD_VID_POL_DK 0x0
#define ATV_TOP_STD_VID_POL_I 0x0
#define ATV_TOP_VID_AMP_MN 0x380
#define ATV_TOP_VID_AMP_FM 0x0
#define ATV_TOP_VID_AMP_L 0xF50
#define ATV_TOP_VID_AMP_LP 0xF50
#define ATV_TOP_VID_AMP_BG 0x380
#define ATV_TOP_VID_AMP_DK 0x394
#define ATV_TOP_VID_AMP_I 0x3D8
#define IQM_CF_OUT_ENA_OFDM__M 0x4
#define IQM_FS_ADJ_SEL_B_QAM 0x1
#define IQM_FS_ADJ_SEL_B_OFF 0x0
#define IQM_FS_ADJ_SEL_B_VSB 0x2
#define IQM_RC_ADJ_SEL_B_OFF 0x0
#define IQM_RC_ADJ_SEL_B_QAM 0x1
#define IQM_RC_ADJ_SEL_B_VSB 0x2
/*** END DJCOMBO patches to DRXJ registermap *********************************/
#include "drx_driver_version.h"
/* #define DRX_DEBUG */
#ifdef DRX_DEBUG
#include <stdio.h>
#endif
/*-----------------------------------------------------------------------------
ENUMS
----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
DEFINES
----------------------------------------------------------------------------*/
#ifndef DRXJ_WAKE_UP_KEY
#define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
#endif
/*
* \def DRXJ_DEF_I2C_ADDR
* \brief Default I2C address of a demodulator instance.
*/
#define DRXJ_DEF_I2C_ADDR (0x52)
/*
* \def DRXJ_DEF_DEMOD_DEV_ID
* \brief Default device identifier of a demodultor instance.
*/
#define DRXJ_DEF_DEMOD_DEV_ID (1)
/*
* \def DRXJ_SCAN_TIMEOUT
* \brief Timeout value for waiting on demod lock during channel scan (millisec).
*/
#define DRXJ_SCAN_TIMEOUT 1000
/*
* \def HI_I2C_DELAY
* \brief HI timing delay for I2C timing (in nano seconds)
*
* Used to compute HI_CFG_DIV
*/
#define HI_I2C_DELAY 42
/*
* \def HI_I2C_BRIDGE_DELAY
* \brief HI timing delay for I2C timing (in nano seconds)
*
* Used to compute HI_CFG_BDL
*/
#define HI_I2C_BRIDGE_DELAY 750
/*
* \brief Time Window for MER and SER Measurement in Units of Segment duration.
*/
#define VSB_TOP_MEASUREMENT_PERIOD 64
#define SYMBOLS_PER_SEGMENT 832
/*
* \brief bit rate and segment rate constants used for SER and BER.
*/
/* values taken from the QAM microcode */
#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
/*
* \brief Min supported symbolrates.
*/
#ifndef DRXJ_QAM_SYMBOLRATE_MIN
#define DRXJ_QAM_SYMBOLRATE_MIN (520000)
#endif
/*
* \brief Max supported symbolrates.
*/
#ifndef DRXJ_QAM_SYMBOLRATE_MAX
#define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
#endif
/*
* \def DRXJ_QAM_MAX_WAITTIME
* \brief Maximal wait time for QAM auto constellation in ms
*/
#ifndef DRXJ_QAM_MAX_WAITTIME
#define DRXJ_QAM_MAX_WAITTIME 900
#endif
#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
#define DRXJ_QAM_FEC_LOCK_WAITTIME 150
#endif
#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
#endif
/*
* \def SCU status and results
* \brief SCU
*/
#define DRX_SCU_READY 0
#define DRXJ_MAX_WAITTIME 100 /* ms */
#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */
#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */
/*
* \def DRX_AUD_MAX_DEVIATION
* \brief Needed for calculation of prescale feature in AUD
*/
#ifndef DRXJ_AUD_MAX_FM_DEVIATION
#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */
#endif
/*
* \brief Needed for calculation of NICAM prescale feature in AUD
*/
#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */
#endif
/*
* \brief Needed for calculation of NICAM prescale feature in AUD
*/
#ifndef DRXJ_AUD_MAX_WAITTIME
#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */
#endif
/* ATV config changed flags */
#define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
/* UIO define */
#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
/*
* MICROCODE RELATED DEFINES
*/
/* Magic word for checking correct Endianness of microcode data */
#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
/* CRC flag in ucode header, flags field. */
#define DRX_UCODE_CRC_FLAG (0x0001)
/*
* Maximum size of buffer used to verify the microcode.
* Must be an even number
*/
#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
#if DRX_UCODE_MAX_BUF_SIZE & 1
#error DRX_UCODE_MAX_BUF_SIZE must be an even number
#endif
/*
* Power mode macros
*/
#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
(mode == DRX_POWER_MODE_10) || \
(mode == DRX_POWER_MODE_11) || \
(mode == DRX_POWER_MODE_12) || \
(mode == DRX_POWER_MODE_13) || \
(mode == DRX_POWER_MODE_14) || \
(mode == DRX_POWER_MODE_15) || \
(mode == DRX_POWER_MODE_16) || \
(mode == DRX_POWER_DOWN))
/* Pin safe mode macro */
#define DRXJ_PIN_SAFE_MODE 0x0000
/*============================================================================*/
/*=== GLOBAL VARIABLEs =======================================================*/
/*============================================================================*/
/*
*/
/*
* \brief Temporary register definitions.
* (register definitions that are not yet available in register master)
*/
/*****************************************************************************/
/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
/* RAM addresses directly. This must be READ ONLY to avoid problems. */
/* Writing to the interface addresses are more than only writing the RAM */
/* locations */
/*****************************************************************************/
/*
* \brief RAM location of MODUS registers
*/
#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
#define AUD_DEM_RAM_MODUS_HI__M 0xF000
#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
/*
* \brief RAM location of I2S config registers
*/
#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
/*
* \brief RAM location of DCO config registers
*/
#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
/*
* \brief RAM location of Threshold registers
*/
#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
/*
* \brief RAM location of Carrier Threshold registers
*/
#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
/*
* \brief FM Matrix register fix
*/
#ifdef AUD_DEM_WR_FM_MATRIX__A
#undef AUD_DEM_WR_FM_MATRIX__A
#endif
#define AUD_DEM_WR_FM_MATRIX__A 0x105006F
/*============================================================================*/
/*
* \brief Defines required for audio
*/
#define AUD_VOLUME_ZERO_DB 115
#define AUD_VOLUME_DB_MIN -60
#define AUD_VOLUME_DB_MAX 12
#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
#define AUD_MAX_AVC_REF_LEVEL 15
#define AUD_I2S_FREQUENCY_MAX 48000UL
#define AUD_I2S_FREQUENCY_MIN 12000UL
#define AUD_RDS_ARRAY_SIZE 18
/*
* \brief Needed for calculation of prescale feature in AUD
*/
#ifndef DRX_AUD_MAX_FM_DEVIATION
#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */
#endif
/*
* \brief Needed for calculation of NICAM prescale feature in AUD
*/
#ifndef DRX_AUD_MAX_NICAM_PRESCALE
#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */
#endif
/*============================================================================*/
/* Values for I2S Master/Slave pin configurations */
#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
/*============================================================================*/
/*=== REGISTER ACCESS MACROS =================================================*/
/*============================================================================*/
/*
* This macro is used to create byte arrays for block writes.
* Block writes speed up I2C traffic between host and demod.
* The macro takes care of the required byte order in a 16 bits word.
* x -> lowbyte(x), highbyte(x)
*/
#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
((u8)((((u16)x)>>8)&0xFF))
/*
* This macro is used to convert byte array to 16 bit register value for block read.
* Block read speed up I2C traffic between host and demod.
* The macro takes care of the required byte order in a 16 bits word.
*/
#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
/*============================================================================*/
/*=== MISC DEFINES ===========================================================*/
/*============================================================================*/
/*============================================================================*/
/*=== HI COMMAND RELATED DEFINES =============================================*/
/*============================================================================*/
/*
* \brief General maximum number of retries for ucode command interfaces
*/
#define DRXJ_MAX_RETRIES (100)
/*============================================================================*/
/*=== STANDARD RELATED MACROS ================================================*/
/*============================================================================*/
#define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
(std == DRX_STANDARD_PAL_SECAM_DK) || \
(std == DRX_STANDARD_PAL_SECAM_I) || \
(std == DRX_STANDARD_PAL_SECAM_L) || \
(std == DRX_STANDARD_PAL_SECAM_LP) || \
(std == DRX_STANDARD_NTSC) || \
(std == DRX_STANDARD_FM))
#define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
(std == DRX_STANDARD_ITU_B) || \
(std == DRX_STANDARD_ITU_C) || \
(std == DRX_STANDARD_ITU_D))
/*-----------------------------------------------------------------------------
GLOBAL VARIABLES
----------------------------------------------------------------------------*/
/*
* DRXJ DAP structures
*/
static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
u32 addr,
u16 datasize,
u8 *data, u32 flags);
static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
u32 waddr,
u32 raddr,
u16 wdata, u16 *rdata);
static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 *data, u32 flags);
static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
u32 addr,
u32 *data, u32 flags);
static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
u32 addr,
u16 datasize,
u8 *data, u32 flags);
static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 data, u32 flags);
static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
u32 addr,
u32 data, u32 flags);
static struct drxj_data drxj_data_g = {
false, /* has_lna : true if LNA (aka PGA) present */
false, /* has_oob : true if OOB supported */
false, /* has_ntsc: true if NTSC supported */
false, /* has_btsc: true if BTSC supported */
false, /* has_smatx: true if SMA_TX pin is available */
false, /* has_smarx: true if SMA_RX pin is available */
false, /* has_gpio : true if GPIO pin is available */
false, /* has_irqn : true if IRQN pin is available */
0, /* mfx A1/A2/A... */
/* tuner settings */
false, /* tuner mirrors RF signal */
/* standard/channel settings */
DRX_STANDARD_UNKNOWN, /* current standard */
DRX_CONSTELLATION_AUTO, /* constellation */
0, /* frequency in KHz */
DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */
DRX_MIRROR_NO, /* mirror */
/* signal quality information: */
/* default values taken from the QAM Programming guide */
/* fec_bits_desired should not be less than 4000000 */
4000000, /* fec_bits_desired */
5, /* fec_vd_plen */
4, /* qam_vd_prescale */
0xFFFF, /* qamVDPeriod */
204 * 8, /* fec_rs_plen annex A */
1, /* fec_rs_prescale */
FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */
true, /* reset_pkt_err_acc */
0, /* pkt_err_acc_start */
/* HI configuration */
0, /* hi_cfg_timing_div */
0, /* hi_cfg_bridge_delay */
0, /* hi_cfg_wake_up_key */
0, /* hi_cfg_ctrl */
0, /* HICfgTimeout */
/* UIO configuration */
DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */
DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */
DRX_UIO_MODE_DISABLE, /* uioASELMode */
DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */
/* FS setting */
0UL, /* iqm_fs_rate_ofs */
false, /* pos_image */
/* RC setting */
0UL, /* iqm_rc_rate_ofs */
/* AUD information */
/* false, * flagSetAUDdone */
/* false, * detectedRDS */
/* true, * flagASDRequest */
/* false, * flagHDevClear */
/* false, * flagHDevSet */
/* (u16) 0xFFF, * rdsLastCount */
/* ATV configuration */
0UL, /* flags cfg changes */
/* shadow of ATV_TOP_EQU0__A */
{-5,
ATV_TOP_EQU0_EQU_C0_FM,
ATV_TOP_EQU0_EQU_C0_L,
ATV_TOP_EQU0_EQU_C0_LP,
ATV_TOP_EQU0_EQU_C0_BG,
ATV_TOP_EQU0_EQU_C0_DK,
ATV_TOP_EQU0_EQU_C0_I},
/* shadow of ATV_TOP_EQU1__A */
{-50,
ATV_TOP_EQU1_EQU_C1_FM,
ATV_TOP_EQU1_EQU_C1_L,
ATV_TOP_EQU1_EQU_C1_LP,
ATV_TOP_EQU1_EQU_C1_BG,
ATV_TOP_EQU1_EQU_C1_DK,
ATV_TOP_EQU1_EQU_C1_I},
/* shadow of ATV_TOP_EQU2__A */
{210,
ATV_TOP_EQU2_EQU_C2_FM,
ATV_TOP_EQU2_EQU_C2_L,
ATV_TOP_EQU2_EQU_C2_LP,
ATV_TOP_EQU2_EQU_C2_BG,
ATV_TOP_EQU2_EQU_C2_DK,
ATV_TOP_EQU2_EQU_C2_I},
/* shadow of ATV_TOP_EQU3__A */
{-160,
ATV_TOP_EQU3_EQU_C3_FM,
ATV_TOP_EQU3_EQU_C3_L,
ATV_TOP_EQU3_EQU_C3_LP,
ATV_TOP_EQU3_EQU_C3_BG,
ATV_TOP_EQU3_EQU_C3_DK,
ATV_TOP_EQU3_EQU_C3_I},
false, /* flag: true=bypass */
ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
true, /* flag CVBS output enable */
false, /* flag SIF output enable */
DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
{ /* qam_rf_agc_cfg */
DRX_STANDARD_ITU_B, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level */
0xFFFF, /* max_output_level */
0x0000, /* speed */
0x0000, /* top */
0x0000 /* c.o.c. */
},
{ /* qam_if_agc_cfg */
DRX_STANDARD_ITU_B, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level */
0xFFFF, /* max_output_level */
0x0000, /* speed */
0x0000, /* top (don't care) */
0x0000 /* c.o.c. (don't care) */
},
{ /* vsb_rf_agc_cfg */
DRX_STANDARD_8VSB, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level */
0xFFFF, /* max_output_level */
0x0000, /* speed */
0x0000, /* top (don't care) */
0x0000 /* c.o.c. (don't care) */
},
{ /* vsb_if_agc_cfg */
DRX_STANDARD_8VSB, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level */
0xFFFF, /* max_output_level */
0x0000, /* speed */
0x0000, /* top (don't care) */
0x0000 /* c.o.c. (don't care) */
},
0, /* qam_pga_cfg */
0, /* vsb_pga_cfg */
{ /* qam_pre_saw_cfg */
DRX_STANDARD_ITU_B, /* standard */
0, /* reference */
false /* use_pre_saw */
},
{ /* vsb_pre_saw_cfg */
DRX_STANDARD_8VSB, /* standard */
0, /* reference */
false /* use_pre_saw */
},
/* Version information */
#ifndef _CH_
{
"01234567890", /* human readable version microcode */
"01234567890" /* human readable version device specific code */
},
{
{ /* struct drx_version for microcode */
DRX_MODULE_UNKNOWN,
(char *)(NULL),
0,
0,
0,
(char *)(NULL)
},
{ /* struct drx_version for device specific code */
DRX_MODULE_UNKNOWN,
(char *)(NULL),
0,
0,
0,
(char *)(NULL)
}
},
{
{ /* struct drx_version_list for microcode */
(struct drx_version *) (NULL),
(struct drx_version_list *) (NULL)
},
{ /* struct drx_version_list for device specific code */
(struct drx_version *) (NULL),
(struct drx_version_list *) (NULL)
}
},
#endif
false, /* smart_ant_inverted */
/* Tracking filter setting for OOB */
{
12000,
9300,
6600,
5280,
3700,
3000,
2000,
0},
false, /* oob_power_on */
0, /* mpeg_ts_static_bitrate */
false, /* disable_te_ihandling */
false, /* bit_reverse_mpeg_outout */
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */
DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */
/* Pre SAW & Agc configuration for ATV */
{
DRX_STANDARD_NTSC, /* standard */
7, /* reference */
true /* use_pre_saw */
},
{ /* ATV RF-AGC */
DRX_STANDARD_NTSC, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level (d.c.) */
0, /* max_output_level (d.c.) */
3, /* speed */
9500, /* top */
4000 /* cut-off current */
},
{ /* ATV IF-AGC */
DRX_STANDARD_NTSC, /* standard */
DRX_AGC_CTRL_AUTO, /* ctrl_mode */
0, /* output_level */
0, /* min_output_level (d.c.) */
0, /* max_output_level (d.c.) */
3, /* speed */
2400, /* top */
0 /* c.o.c. (d.c.) */
},
140, /* ATV PGA config */
0, /* curr_symbol_rate */
false, /* pdr_safe_mode */
SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */
SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */
SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */
4, /* oob_pre_saw */
DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */
{
false /* aud_data, only first member */
},
};
/*
* \var drxj_default_addr_g
* \brief Default I2C address and device identifier.
*/
static struct i2c_device_addr drxj_default_addr_g = {
DRXJ_DEF_I2C_ADDR, /* i2c address */
DRXJ_DEF_DEMOD_DEV_ID /* device id */
};
/*
* \var drxj_default_comm_attr_g
* \brief Default common attributes of a drxj demodulator instance.
*/
static struct drx_common_attr drxj_default_comm_attr_g = {
NULL, /* ucode file */
true, /* ucode verify switch */
{0}, /* version record */
44000, /* IF in kHz in case no tuner instance is used */
(151875 - 0), /* system clock frequency in kHz */
0, /* oscillator frequency kHz */
0, /* oscillator deviation in ppm, signed */
false, /* If true mirror frequency spectrum */
{
/* MPEG output configuration */
true, /* If true, enable MPEG output */
false, /* If true, insert RS byte */
false, /* If true, parallel out otherwise serial */
false, /* If true, invert DATA signals */
false, /* If true, invert ERR signal */
false, /* If true, invert STR signals */
false, /* If true, invert VAL signals */
false, /* If true, invert CLK signals */
true, /* If true, static MPEG clockrate will
be used, otherwise clockrate will
adapt to the bitrate of the TS */
19392658UL, /* Maximum bitrate in b/s in case
static clockrate is selected */
DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
},
/* Initilisations below can be omitted, they require no user input and
are initially 0, NULL or false. The compiler will initialize them to these
values when omitted. */
false, /* is_opened */
/* SCAN */
NULL, /* no scan params yet */
0, /* current scan index */
0, /* next scan frequency */
false, /* scan ready flag */
0, /* max channels to scan */
0, /* nr of channels scanned */
NULL, /* default scan function */
NULL, /* default context pointer */
0, /* millisec to wait for demod lock */
DRXJ_DEMOD_LOCK, /* desired lock */
false,
/* Power management */
DRX_POWER_UP,
/* Tuner */
1, /* nr of I2C port to which tuner is */
0L, /* minimum RF input frequency, in kHz */
0L, /* maximum RF input frequency, in kHz */
false, /* Rf Agc Polarity */
false, /* If Agc Polarity */
false, /* tuner slow mode */
{ /* current channel (all 0) */
0UL /* channel.frequency */
},
DRX_STANDARD_UNKNOWN, /* current standard */
DRX_STANDARD_UNKNOWN, /* previous standard */
DRX_STANDARD_UNKNOWN, /* di_cache_standard */
false, /* use_bootloader */
0UL, /* capabilities */
0 /* mfx */
};
/*
* \var drxj_default_demod_g
* \brief Default drxj demodulator instance.
*/
static struct drx_demod_instance drxj_default_demod_g = {
&drxj_default_addr_g, /* i2c address & device id */
&drxj_default_comm_attr_g, /* demod common attributes */
&drxj_data_g /* demod device specific attributes */
};
/*
* \brief Default audio data structure for DRK demodulator instance.
*
* This structure is DRXK specific.
*
*/
static struct drx_aud_data drxj_default_aud_data_g = {
false, /* audio_is_active */
DRX_AUD_STANDARD_AUTO, /* audio_standard */
/* i2sdata */
{
false, /* output_enable */
48000, /* frequency */
DRX_I2S_MODE_MASTER, /* mode */
DRX_I2S_WORDLENGTH_32, /* word_length */
DRX_I2S_POLARITY_RIGHT, /* polarity */
DRX_I2S_FORMAT_WS_WITH_DATA /* format */
},
/* volume */
{
true, /* mute; */
0, /* volume */
DRX_AUD_AVC_OFF, /* avc_mode */
0, /* avc_ref_level */
DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */
DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */
0, /* strength_left */
0 /* strength_right */
},
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
/* ass_thresholds */
{
440, /* A2 */
12, /* BTSC */
700, /* NICAM */
},
/* carrier */
{
/* a */
{
42, /* thres */
DRX_NO_CARRIER_NOISE, /* opt */
0, /* shift */
0 /* dco */
},
/* b */
{
42, /* thres */
DRX_NO_CARRIER_MUTE, /* opt */
0, /* shift */
0 /* dco */
},
},
/* mixer */
{
DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */
DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */
DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
},
DRX_AUD_DEVIATION_NORMAL, /* deviation */
DRX_AUD_AVSYNC_OFF, /* av_sync */
/* prescale */
{
DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */
DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
},
DRX_AUD_FM_DEEMPH_75US, /* deemph */
DRX_BTSC_STEREO, /* btsc_detect */
0, /* rds_data_counter */
false /* rds_data_present */
};
/*-----------------------------------------------------------------------------
STRUCTURES
----------------------------------------------------------------------------*/
struct drxjeq_stat {
u16 eq_mse;
u8 eq_mode;
u8 eq_ctrl;
u8 eq_stat;
};
/* HI command */
struct drxj_hi_cmd {
u16 cmd;
u16 param1;
u16 param2;
u16 param3;
u16 param4;
u16 param5;
u16 param6;
};
/*============================================================================*/
/*=== MICROCODE RELATED STRUCTURES ===========================================*/
/*============================================================================*/
/*
* struct drxu_code_block_hdr - Structure of the microcode block headers
*
* @addr: Destination address of the data in this block
* @size: Size of the block data following this header counted in
* 16 bits words
* @CRC: CRC value of the data block, only valid if CRC flag is
* set.
*/
struct drxu_code_block_hdr {
u32 addr;
u16 size;
u16 flags;
u16 CRC;
};
/*-----------------------------------------------------------------------------
FUNCTIONS
----------------------------------------------------------------------------*/
/* Some prototypes */
static int
hi_command(struct i2c_device_addr *dev_addr,
const struct drxj_hi_cmd *cmd, u16 *result);
static int
ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
static int
ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
static int power_down_aud(struct drx_demod_instance *demod);
static int
ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
static int
ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
/*============================================================================*/
/*============================================================================*/
/*== HELPER FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn u32 frac28(u32 N, u32 D)
* \brief Compute: (1<<28)*N/D
* \param N 32 bits
* \param D 32 bits
* \return (1<<28)*N/D
* This function is used to avoid floating-point calculations as they may
* not be present on the target platform.
* frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
* fraction used for setting the Frequency Shifter registers.
* N and D can hold numbers up to width: 28-bits.
* The 4 bits integer part and the 28 bits fractional part are calculated.
* Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
* N: 0...(1<<28)-1 = 268435454
* D: 0...(1<<28)-1
* Q: 0...(1<<32)-1
*/
static u32 frac28(u32 N, u32 D)
{
int i = 0;
u32 Q1 = 0;
u32 R0 = 0;
R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
Q1 = N / D; /* integer part, only the 4 least significant bits
will be visible in the result */
/* division using radix 16, 7 nibbles in the result */
for (i = 0; i < 7; i++) {
Q1 = (Q1 << 4) | R0 / D;
R0 = (R0 % D) << 4;
}
/* rounding */
if ((R0 >> 3) >= D)
Q1++;
return Q1;
}
/*
* \fn u32 log1_times100( u32 x)
* \brief Compute: 100*log10(x)
* \param x 32 bits
* \return 100*log10(x)
*
* 100*log10(x)
* = 100*(log2(x)/log2(10)))
* = (100*(2^15)*log2(x))/((2^15)*log2(10))
* = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
* = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
* = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
*
* where y = 2^k and 1<= (x/y) < 2
*/
static u32 log1_times100(u32 x)
{
static const u8 scale = 15;
static const u8 index_width = 5;
/*
log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
0 <= n < ((1<<INDEXWIDTH)+1)
*/
static const u32 log2lut[] = {
0, /* 0.000000 */
290941, /* 290941.300628 */
573196, /* 573196.476418 */
847269, /* 847269.179851 */
1113620, /* 1113620.489452 */
1372674, /* 1372673.576986 */
1624818, /* 1624817.752104 */
1870412, /* 1870411.981536 */
2109788, /* 2109787.962654 */
2343253, /* 2343252.817465 */
2571091, /* 2571091.461923 */
2793569, /* 2793568.696416 */
3010931, /* 3010931.055901 */
3223408, /* 3223408.452106 */
3431216, /* 3431215.635215 */
3634553, /* 3634553.498355 */
3833610, /* 3833610.244726 */
4028562, /* 4028562.434393 */
4219576, /* 4219575.925308 */
4406807, /* 4406806.721144 */
4590402, /* 4590401.736809 */
4770499, /* 4770499.491025 */
4947231, /* 4947230.734179 */
5120719, /* 5120719.018555 */
5291081, /* 5291081.217197 */
5458428, /* 5458427.996830 */
5622864, /* 5622864.249668 */
5784489, /* 5784489.488298 */
5943398, /* 5943398.207380 */
6099680, /* 6099680.215452 */
6253421, /* 6253420.939751 */
6404702, /* 6404701.706649 */
6553600, /* 6553600.000000 */
};
u8 i = 0;
u32 y = 0;
u32 d = 0;
u32 k = 0;
u32 r = 0;
if (x == 0)
return 0;
/* Scale x (normalize) */
/* computing y in log(x/y) = log(x) - log(y) */
if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
for (k = scale; k > 0; k--) {
if (x & (((u32) 1) << scale))
break;
x <<= 1;
}
} else {
for (k = scale; k < 31; k++) {
if ((x & (((u32) (-1)) << (scale + 1))) == 0)
break;
x >>= 1;
}
}
/*
Now x has binary point between bit[scale] and bit[scale-1]
and 1.0 <= x < 2.0 */
/* correction for division: log(x) = log(x/y)+log(y) */
y = k * ((((u32) 1) << scale) * 200);
/* remove integer part */
x &= ((((u32) 1) << scale) - 1);
/* get index */
i = (u8) (x >> (scale - index_width));
/* compute delta (x-a) */
d = x & ((((u32) 1) << (scale - index_width)) - 1);
/* compute log, multiplication ( d* (.. )) must be within range ! */
y += log2lut[i] +
((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
/* Conver to log10() */
y /= 108853; /* (log2(10) << scale) */
r = (y >> 1);
/* rounding */
if (y & ((u32)1))
r++;
return r;
}
/*
* \fn u32 frac_times1e6( u16 N, u32 D)
* \brief Compute: (N/D) * 1000000.
* \param N nominator 16-bits.
* \param D denominator 32-bits.
* \return u32
* \retval ((N/D) * 1000000), 32 bits
*
* No check on D=0!
*/
static u32 frac_times1e6(u32 N, u32 D)
{
u32 remainder = 0;
u32 frac = 0;
/*
frac = (N * 1000000) / D
To let it fit in a 32 bits computation:
frac = (N * (1000000 >> 4)) / (D >> 4)
This would result in a problem in case D < 16 (div by 0).
So we do it more elaborate as shown below.
*/
frac = (((u32) N) * (1000000 >> 4)) / D;
frac <<= 4;
remainder = (((u32) N) * (1000000 >> 4)) % D;
remainder <<= 4;
frac += remainder / D;
remainder = remainder % D;
if ((remainder * 2) > D)
frac++;
return frac;
}
/*============================================================================*/
/*
* \brief Values for NICAM prescaler gain. Computed from dB to integer
* and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
*
*/
#if 0
/* Currently, unused as we lack support for analog TV */
static const u16 nicam_presc_table_val[43] = {
1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
18, 20, 23, 25, 28, 32, 36, 40, 45,
51, 57, 64, 71, 80, 90, 101, 113, 127
};
#endif
/*============================================================================*/
/*== END HELPER FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== DRXJ DAP FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
This layer takes care of some device specific register access protocols:
-conversion to short address format
-access to audio block
This layer is placed between the drx_dap_fasi and the rest of the drxj
specific implementation. This layer can use address map knowledge whereas
dap_fasi may not use memory map knowledge.
* For audio currently only 16 bits read and write register access is
supported. More is not needed. RMW and 32 or 8 bit access on audio
registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
single/multi master) will be ignored.
TODO: check ignoring single/multimaster is ok for AUD access ?
*/
#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
/*============================================================================*/
/*
* \fn bool is_handled_by_aud_tr_if( u32 addr )
* \brief Check if this address is handled by the audio token ring interface.
* \param addr
* \return bool
* \retval true Yes, handled by audio token ring interface
* \retval false No, not handled by audio token ring interface
*
*/
static
bool is_handled_by_aud_tr_if(u32 addr)
{
bool retval = false;
if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
(DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
(DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
retval = true;
}
return retval;
}
/*============================================================================*/
int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data)
{
struct drx39xxj_state *state;
struct i2c_msg msg[2];
unsigned int num_msgs;
if (w_dev_addr == NULL) {
/* Read only */
state = r_dev_addr->user_data;
msg[0].addr = r_dev_addr->i2c_addr >> 1;
msg[0].flags = I2C_M_RD;
msg[0].buf = r_data;
msg[0].len = r_count;
num_msgs = 1;
} else if (r_dev_addr == NULL) {
/* Write only */
state = w_dev_addr->user_data;
msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = w_count;
num_msgs = 1;
} else {
/* Both write and read */
state = w_dev_addr->user_data;
msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = w_count;
msg[1].addr = r_dev_addr->i2c_addr >> 1;
msg[1].flags = I2C_M_RD;
msg[1].buf = r_data;
msg[1].len = r_count;
num_msgs = 2;
}
if (state->i2c == NULL) {
pr_err("i2c was zero, aborting\n");
return 0;
}
if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
pr_warn("drx3933: I2C write/read failed\n");
return -EREMOTEIO;
}
#ifdef DJH_DEBUG
if (w_dev_addr == NULL || r_dev_addr == NULL)
return 0;
state = w_dev_addr->user_data;
if (state->i2c == NULL)
return 0;
msg[0].addr = w_dev_addr->i2c_addr;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = w_count;
msg[1].addr = r_dev_addr->i2c_addr;
msg[1].flags = I2C_M_RD;
msg[1].buf = r_data;
msg[1].len = r_count;
num_msgs = 2;
pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
if (i2c_transfer(state->i2c, msg, 2) != 2) {
pr_warn("drx3933: I2C write/read failed\n");
return -EREMOTEIO;
}
#endif
return 0;
}
/*============================================================================*/
/*****************************
*
* int drxdap_fasi_read_block (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive
* u32 flags) -- special device flags
*
* Read block data from chip address. Because the chip is word oriented,
* the number of bytes to read must be even.
*
* Make sure that the buffer to receive the data is large enough.
*
* Although this function expects an even number of bytes, it is still byte
* oriented, and the data read back is NOT translated to the endianness of
* the target platform.
*
* Output:
* - 0 if reading was successful
* in that case: data read is in *data.
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
u32 addr,
u16 datasize,
u8 *data, u32 flags)
{
u8 buf[4];
u16 bufx;
int rc;
u16 overhead_size = 0;
/* Check parameters ******************************************************* */
if (dev_addr == NULL)
return -EINVAL;
overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return -EINVAL;
}
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Read block from I2C **************************************************** */
do {
u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
bufx = 0;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
#endif
#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
} else {
#endif
#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
buf[bufx++] = (u8) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
}
#endif
#if DRXDAP_SINGLE_MASTER
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
NULL, 0, NULL);
if (rc == 0)
rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
#else
/* In multi master mode, do everything in one RW action */
rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
data);
#endif
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == 0);
return rc;
}
/*****************************
*
* int drxdap_fasi_read_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u16 *data, -- data to receive
* u32 flags) -- special device flags
*
* Read one 16-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
*
* Output:
* - 0 if reading was successful
* in that case: read data is at *data
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 *data, u32 flags)
{
u8 buf[sizeof(*data)];
int rc;
if (!data)
return -EINVAL;
rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = buf[0] + (((u16) buf[1]) << 8);
return rc;
}
/*****************************
*
* int drxdap_fasi_read_reg32 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u32 *data, -- data to receive
* u32 flags) -- special device flags
*
* Read one 32-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
*
* Output:
* - 0 if reading was successful
* in that case: read data is at *data
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
u32 addr,
u32 *data, u32 flags)
{
u8 buf[sizeof(*data)];
int rc;
if (!data)
return -EINVAL;
rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = (((u32) buf[0]) << 0) +
(((u32) buf[1]) << 8) +
(((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
return rc;
}
/*****************************
*
* int drxdap_fasi_write_block (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive
* u32 flags) -- special device flags
*
* Write block data to chip address. Because the chip is word oriented,
* the number of bytes to write must be even.
*
* Although this function expects an even number of bytes, it is still byte
* oriented, and the data being written is NOT translated from the endianness of
* the target platform.
*
* Output:
* - 0 if writing was successful
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
u32 addr,
u16 datasize,
u8 *data, u32 flags)
{
u8 buf[DRXDAP_MAX_WCHUNKSIZE];
int st = -EIO;
int first_err = 0;
u16 overhead_size = 0;
u16 block_size = 0;
/* Check parameters ******************************************************* */
if (dev_addr == NULL)
return -EINVAL;
overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
return -EINVAL;
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Write block to I2C ***************************************************** */
block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
do {
u16 todo = 0;
u16 bufx = 0;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
#endif
#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
} else {
#endif
#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
buf[bufx++] = (u8) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
}
#endif
/*
In single master mode block_size can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Address must be rewritten because HI is reset after data transport and
expects an address.
*/
todo = (block_size < datasize ? block_size : datasize);
if (todo == 0) {
u16 overhead_size_i2c_addr = 0;
u16 data_block_size = 0;
overhead_size_i2c_addr =
(IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
data_block_size =
(DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
/* write device address */
st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx),
buf,
(struct i2c_device_addr *)(NULL),
0, (u8 *)(NULL));
if ((st != 0) && (first_err == 0)) {
/* at the end, return the first error encountered */
first_err = st;
}
bufx = 0;
todo =
(data_block_size <
datasize ? data_block_size : datasize);
}
memcpy(&buf[bufx], data, todo);
/* write (address if can do and) data */
st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx + todo),
buf,
(struct i2c_device_addr *)(NULL),
0, (u8 *)(NULL));
if ((st != 0) && (first_err == 0)) {
/* at the end, return the first error encountered */
first_err = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return first_err;
}
/*****************************
*
* int drxdap_fasi_write_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u16 data, -- data to send
* u32 flags) -- special device flags
*
* Write one 16-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
*
* Output:
* - 0 if writing was successful
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 data, u32 flags)
{
u8 buf[sizeof(data)];
buf[0] = (u8) ((data >> 0) & 0xFF);
buf[1] = (u8) ((data >> 8) & 0xFF);
return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
}
/*****************************
*
* int drxdap_fasi_read_modify_write_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 waddr, -- address of chip register/memory
* u32 raddr, -- chip address to read back from
* u16 wdata, -- data to send
* u16 *rdata) -- data to receive back
*
* Write 16-bit data, then read back the original contents of that location.
* Requires long addressing format to be allowed.
*
* Before sending data, the data is converted to little endian. The
* data received back is converted back to the target platform's endianness.
*
* WARNING: This function is only guaranteed to work if there is one
* master on the I2C bus.
*
* Output:
* - 0 if reading was successful
* in that case: read back data is at *rdata
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
u32 waddr,
u32 raddr,
u16 wdata, u16 *rdata)
{
int rc = -EIO;
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
if (rdata == NULL)
return -EINVAL;
rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == 0)
rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
#endif
return rc;
}
/*****************************
*
* int drxdap_fasi_write_reg32 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* u32 addr, -- address of chip register/memory
* u32 data, -- data to send
* u32 flags) -- special device flags
*
* Write one 32-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
*
* Output:
* - 0 if writing was successful
* - -EIO if anything went wrong
*
******************************/
static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
u32 addr,
u32 data, u32 flags)
{
u8 buf[sizeof(data)];
buf[0] = (u8) ((data >> 0) & 0xFF);
buf[1] = (u8) ((data >> 8) & 0xFF);
buf[2] = (u8) ((data >> 16) & 0xFF);
buf[3] = (u8) ((data >> 24) & 0xFF);
return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
}
/*============================================================================*/
/*
* \fn int drxj_dap_rm_write_reg16short
* \brief Read modify write 16 bits audio register using short format only.
* \param dev_addr
* \param waddr Address to write to
* \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
* \param wdata Data to write
* \param rdata Buffer for data to read
* \return int
* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register read modify write access using short addressing format only.
* Requires knowledge of the registermap, thus device dependent.
* Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
*
*/
/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
See comments drxj_dap_read_modify_write_reg16 */
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
u32 waddr,
u32 raddr,
u16 wdata, u16 *rdata)
{
int rc;
if (rdata == NULL)
return -EINVAL;
/* Set RMW flag */
rc = drxdap_fasi_write_reg16(dev_addr,
SIO_HI_RA_RAM_S0_FLG_ACC__A,
SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
0x0000);
if (rc == 0) {
/* Write new data: triggers RMW */
rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
0x0000);
}
if (rc == 0) {
/* Read old data */
rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
0x0000);
}
if (rc == 0) {
/* Reset RMW flag */
rc = drxdap_fasi_write_reg16(dev_addr,
SIO_HI_RA_RAM_S0_FLG_ACC__A,
0, 0x0000);
}
return rc;
}
#endif
/*============================================================================*/
static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
u32 waddr,
u32 raddr,
u16 wdata, u16 *rdata)
{
/* TODO: correct short/long addressing format decision,
now long format has higher prio then short because short also
needs virt bnks (not impl yet) for certain audio registers */
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
return drxdap_fasi_read_modify_write_reg16(dev_addr,
waddr,
raddr, wdata, rdata);
#else
return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
#endif
}
/*============================================================================*/
/*
* \fn int drxj_dap_read_aud_reg16
* \brief Read 16 bits audio register
* \param dev_addr
* \param addr
* \param data
* \return int
* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register read access via audio token ring interface.
*
*/
static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
u32 addr, u16 *data)
{
u32 start_timer = 0;
u32 current_timer = 0;
u32 delta_timer = 0;
u16 tr_status = 0;
int stat = -EIO;
/* No read possible for bank 3, return with error */
if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
stat = -EINVAL;
} else {
const u32 write_bit = ((dr_xaddr_t) 1) << 16;
/* Force reset write bit */
addr &= (~write_bit);
/* Set up read */
start_timer = jiffies_to_msecs(jiffies);
do {
/* RMW to aud TR IF until request is granted or timeout */
stat = drxj_dap_read_modify_write_reg16(dev_addr,
addr,
SIO_HI_RA_RAM_S0_RMWBUF__A,
0x0000, &tr_status);
if (stat != 0)
break;
current_timer = jiffies_to_msecs(jiffies);
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = -EIO;
break;
}
} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
AUD_TOP_TR_CTR_FIFO_FULL_FULL));
} /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
/* Wait for read ready status or timeout */
if (stat == 0) {
start_timer = jiffies_to_msecs(jiffies);
while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
stat = drxj_dap_read_reg16(dev_addr,
AUD_TOP_TR_CTR__A,
&tr_status, 0x0000);
if (stat != 0)
break;
current_timer = jiffies_to_msecs(jiffies);
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = -EIO;
break;
}
} /* while ( ... ) */
}
/* Read value */
if (stat == 0)
stat = drxj_dap_read_modify_write_reg16(dev_addr,
AUD_TOP_TR_RD_REG__A,
SIO_HI_RA_RAM_S0_RMWBUF__A,
0x0000, data);
return stat;
}
/*============================================================================*/
static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 *data, u32 flags)
{
int stat = -EIO;
/* Check param */
if ((dev_addr == NULL) || (data == NULL))
return -EINVAL;
if (is_handled_by_aud_tr_if(addr))
stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
else
stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
return stat;
}
/*============================================================================*/
/*
* \fn int drxj_dap_write_aud_reg16
* \brief Write 16 bits audio register
* \param dev_addr
* \param addr
* \param data
* \return int
* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register write access via audio token ring interface.
*
*/
static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
u32 addr, u16 data)
{
int stat = -EIO;
/* No write possible for bank 2, return with error */
if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
stat = -EINVAL;
} else {
u32 start_timer = 0;
u32 current_timer = 0;
u32 delta_timer = 0;
u16 tr_status = 0;
const u32 write_bit = ((dr_xaddr_t) 1) << 16;
/* Force write bit */
addr |= write_bit;
start_timer = jiffies_to_msecs(jiffies);
do {
/* RMW to aud TR IF until request is granted or timeout */
stat = drxj_dap_read_modify_write_reg16(dev_addr,
addr,
SIO_HI_RA_RAM_S0_RMWBUF__A,
data, &tr_status);
if (stat != 0)
break;
current_timer = jiffies_to_msecs(jiffies);
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = -EIO;
break;
}
} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
AUD_TOP_TR_CTR_FIFO_FULL_FULL));
} /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
return stat;
}
/*============================================================================*/
static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 data, u32 flags)
{
int stat = -EIO;
/* Check param */
if (dev_addr == NULL)
return -EINVAL;
if (is_handled_by_aud_tr_if(addr))
stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
else
stat = drxdap_fasi_write_reg16(dev_addr,
addr, data, flags);
return stat;
}
/*============================================================================*/
/* Free data ram in SIO HI */
#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
#define SIO_HI_RA_RAM_USR_END__A 0x420060
#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
/*
* \fn int drxj_dap_atomic_read_write_block()
* \brief Basic access routine for atomic read or write access
* \param dev_addr pointer to i2c dev address
* \param addr destination/source address
* \param datasize size of data buffer in bytes
* \param data pointer to data buffer
* \return int
* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
*/
static
int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
u32 addr,
u16 datasize,
u8 *data, bool read_flag)
{
struct drxj_hi_cmd hi_cmd;
int rc;
u16 word;
u16 dummy = 0;
u16 i = 0;
/* Parameter check */
if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
return -EINVAL;
/* Set up HI parameters to read or write n bytes */
hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
hi_cmd.param1 =
(u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
hi_cmd.param2 =
(u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
hi_cmd.param3 = (u16) ((datasize / 2) - 1);
if (!read_flag)
hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
else
hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
DRXDAP_FASI_ADDR2BANK(addr));
hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
if (!read_flag) {
/* write data to buffer */
for (i = 0; i < (datasize / 2); i++) {
word = ((u16) data[2 * i]);
word += (((u16) data[(2 * i) + 1]) << 8);
drxj_dap_write_reg16(dev_addr,
(DRXJ_HI_ATOMIC_BUF_START + i),
word, 0);
}
}
rc = hi_command(dev_addr, &hi_cmd, &dummy);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (read_flag) {
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
rc = drxj_dap_read_reg16(dev_addr,
(DRXJ_HI_ATOMIC_BUF_START + i),
&word, 0);
if (rc) {
pr_err("error %d\n", rc);
goto rw_error;
}
data[2 * i] = (u8) (word & 0xFF);
data[(2 * i) + 1] = (u8) (word >> 8);
}
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int drxj_dap_atomic_read_reg32()
* \brief Atomic read of 32 bits words
*/
static
int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
u32 addr,
u32 *data, u32 flags)
{
u8 buf[sizeof(*data)] = { 0 };
int rc;
u32 word = 0;
if (!data)
return -EINVAL;
rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
sizeof(*data), buf, true);
if (rc < 0)
return 0;
word = (u32) buf[3];
word <<= 8;
word |= (u32) buf[2];
word <<= 8;
word |= (u32) buf[1];
word <<= 8;
word |= (u32) buf[0];
*data = word;
return rc;
}
/*============================================================================*/
/*============================================================================*/
/*== END DRXJ DAP FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== HOST INTERFACE FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn int hi_cfg_command()
* \brief Configure HI with settings stored in the demod structure.
* \param demod Demodulator.
* \return int.
*
* This routine was created because to much orthogonal settings have
* been put into one HI API function (configure). Especially the I2C bridge
* enable/disable should not need re-configuration of the HI.
*
*/
static int hi_cfg_command(const struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct drxj_hi_cmd hi_cmd;
u16 result = 0;
int rc;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
hi_cmd.param6 = ext_attr->hi_cfg_transmit;
rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Reset power down flag (set one call only) */
ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
return 0;
rw_error:
return rc;
}
/*
* \fn int hi_command()
* \brief Configure HI with settings stored in the demod structure.
* \param dev_addr I2C address.
* \param cmd HI command.
* \param result HI command result.
* \return int.
*
* Sends command to HI
*
*/
static int
hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
{
u16 wait_cmd = 0;
u16 nr_retries = 0;
bool powerdown_cmd = false;
int rc;
/* Write parameters */
switch (cmd->cmd) {
case SIO_HI_RA_RAM_CMD_CONFIG:
case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case SIO_HI_RA_RAM_CMD_BRDCTRL:
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case SIO_HI_RA_RAM_CMD_NULL:
/* No parameters */
break;
default:
return -EINVAL;
}
/* Write command */
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
msleep(1);
/* Detect power down to omit reading result */
powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
(((cmd->
param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
== SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
if (!powerdown_cmd) {
/* Wait until command rdy */
do {
nr_retries++;
if (nr_retries > DRXJ_MAX_RETRIES) {
rc = -ETIMEDOUT;
pr_err("timeout\n");
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} while (wait_cmd != 0);
/* Read result */
rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* if ( powerdown_cmd == true ) */
return 0;
rw_error:
return rc;
}
/*
* \fn int init_hi( const struct drx_demod_instance *demod )
* \brief Initialise and configurate HI.
* \param demod pointer to demod data.
* \return int Return status.
* \retval 0 Success.
* \retval -EIO Failure.
*
* Needs to know Psys (System Clock period) and Posc (Osc Clock period)
* Need to store configuration in driver because of the way I2C
* bridging is controlled.
*
*/
static int init_hi(const struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
int rc;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
dev_addr = demod->my_i2c_dev_addr;
/* PATCH for bug 5003, HI ucode v3.1.0 */
rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Timing div, 250ns/Psys */
/* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
ext_attr->hi_cfg_timing_div =
(u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
/* Clipping */
if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
/* Bridge delay, uses oscilator clock */
/* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
/* SDA brdige delay */
ext_attr->hi_cfg_bridge_delay =
(u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
1000;
/* Clipping */
if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
/* SCL bridge delay, same as SDA for now */
ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
/* Wakeup key, setting the read flag (as suggest in the documentation) does
not always result into a working solution (barebones worked VI2C failed).
Not setting the bit works in all cases . */
ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
/* port/bridge/power down ctrl */
ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
/* transit mode time out delay and watch dog divider */
ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
rc = hi_cfg_command(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== END HOST INTERFACE FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== AUXILIARY FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn int get_device_capabilities()
* \brief Get and store device capabilities.
* \param demod Pointer to demodulator instance.
* \return int.
* \return 0 Success
* \retval -EIO Failure
*
* Depending on pulldowns on MDx pins the following internals are set:
* * common_attr->osc_clock_freq
* * ext_attr->has_lna
* * ext_attr->has_ntsc
* * ext_attr->has_btsc
* * ext_attr->has_oob
*
*/
static int get_device_capabilities(struct drx_demod_instance *demod)
{
struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
struct drxj_data *ext_attr = (struct drxj_data *) NULL;
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
u16 sio_pdr_ohw_cfg = 0;
u32 sio_top_jtagid_lo = 0;
u16 bid = 0;
int rc;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
dev_addr = demod->my_i2c_dev_addr;
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
case 0:
/* ignore (bypass ?) */
break;
case 1:
/* 27 MHz */
common_attr->osc_clock_freq = 27000;
break;
case 2:
/* 20.25 MHz */
common_attr->osc_clock_freq = 20250;
break;
case 3:
/* 4 MHz */
common_attr->osc_clock_freq = 4000;
break;
default:
return -EIO;
}
/*
Determine device capabilities
Based on pinning v47
*/
rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
case 0x31:
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
bid = (bid >> 10) & 0xf;
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->has_lna = true;
ext_attr->has_ntsc = false;
ext_attr->has_btsc = false;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = false;
ext_attr->has_gpio = false;
ext_attr->has_irqn = false;
break;
case 0x33:
ext_attr->has_lna = false;
ext_attr->has_ntsc = false;
ext_attr->has_btsc = false;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = false;
ext_attr->has_gpio = false;
ext_attr->has_irqn = false;
break;
case 0x45:
ext_attr->has_lna = true;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = false;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = false;
break;
case 0x46:
ext_attr->has_lna = false;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = false;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = false;
break;
case 0x41:
ext_attr->has_lna = true;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = true;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = false;
break;
case 0x43:
ext_attr->has_lna = false;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = true;
ext_attr->has_oob = false;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = false;
break;
case 0x32:
ext_attr->has_lna = true;
ext_attr->has_ntsc = false;
ext_attr->has_btsc = false;
ext_attr->has_oob = true;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = true;
break;
case 0x34:
ext_attr->has_lna = false;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = true;
ext_attr->has_oob = true;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = true;
break;
case 0x42:
ext_attr->has_lna = true;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = true;
ext_attr->has_oob = true;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = true;
break;
case 0x44:
ext_attr->has_lna = false;
ext_attr->has_ntsc = true;
ext_attr->has_btsc = true;
ext_attr->has_oob = true;
ext_attr->has_smatx = true;
ext_attr->has_smarx = true;
ext_attr->has_gpio = true;
ext_attr->has_irqn = true;
break;
default:
/* Unknown device variant */
return -EIO;
break;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int power_up_device()
* \brief Power up device.
* \param demod Pointer to demodulator instance.
* \return int.
* \return 0 Success
* \retval -EIO Failure, I2C or max retries reached
*
*/
#ifndef DRXJ_MAX_RETRIES_POWERUP
#define DRXJ_MAX_RETRIES_POWERUP 10
#endif
static int power_up_device(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
u8 data = 0;
u16 retry_count = 0;
struct i2c_device_addr wake_up_addr;
dev_addr = demod->my_i2c_dev_addr;
wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
wake_up_addr.user_data = dev_addr->user_data;
/*
* I2C access may fail in this case: no ack
* dummy write must be used to wake uop device, dummy read must be used to
* reset HI state machine (avoiding actual writes)
*/
do {
data = 0;
drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
(struct i2c_device_addr *)(NULL), 0,
(u8 *)(NULL));
msleep(10);
retry_count++;
} while ((drxbsp_i2c_write_read
((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
&data)
!= 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
/* Need some recovery time .... */
msleep(10);
if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
return -EIO;
return 0;
}
/*----------------------------------------------------------------------------*/
/* MPEG Output Configuration Functions - begin */
/*----------------------------------------------------------------------------*/
/*
* \fn int ctrl_set_cfg_mpeg_output()
* \brief Set MPEG output configuration of the device.
* \param devmod Pointer to demodulator instance.
* \param cfg_data Pointer to mpeg output configuaration.
* \return int.
*
* Configure MPEG output parameters.
*
*/
static int
ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
{
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
int rc;
u16 fec_oc_reg_mode = 0;
u16 fec_oc_reg_ipr_mode = 0;
u16 fec_oc_reg_ipr_invert = 0;
u32 max_bit_rate = 0;
u32 rcn_rate = 0;
u32 nr_bits = 0;
u16 sio_pdr_md_cfg = 0;
/* data mask for the output data byte */
u16 invert_data_mask =
FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
/* check arguments */
if ((demod == NULL) || (cfg_data == NULL))
return -EINVAL;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
if (cfg_data->enable_mpeg_output == true) {
/* quick and dirty patch to set MPEG in case current std is not
producing MPEG */
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
break;
default:
return 0;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* 2048 bytes fifo ram */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Low Water Mark for synchronization */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* High Water Mark for synchronization */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
switch (ext_attr->constellation) {
case DRX_CONSTELLATION_QAM256:
nr_bits = 8;
break;
case DRX_CONSTELLATION_QAM128:
nr_bits = 7;
break;
case DRX_CONSTELLATION_QAM64:
nr_bits = 6;
break;
case DRX_CONSTELLATION_QAM32:
nr_bits = 5;
break;
case DRX_CONSTELLATION_QAM16:
nr_bits = 4;
break;
default:
return -EIO;
} /* ext_attr->constellation */
/* max_bit_rate = symbol_rate * nr_bits * coef */
/* coef = 188/204 */
max_bit_rate =
(ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
fallthrough; /* as b/c Annex A/C need following settings */
case DRX_STANDARD_ITU_B:
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (cfg_data->static_clk == true) {
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
break;
} /* switch (standard) */
/* Check insertion of the Reed-Solomon parity bytes */
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (cfg_data->insert_rs_byte == true) {
/* enable parity symbol forward */
fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
/* MVAL disable during parity bytes */
fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
rcn_rate = 0x004854D3;
break;
case DRX_STANDARD_ITU_B:
fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
switch (ext_attr->constellation) {
case DRX_CONSTELLATION_QAM256:
rcn_rate = 0x008945E7;
break;
case DRX_CONSTELLATION_QAM64:
rcn_rate = 0x005F64D4;
break;
default:
return -EIO;
}
break;
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
/* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
rcn_rate =
(frac28
(max_bit_rate,
(u32) (common_attr->sys_clock_freq / 8))) /
188;
break;
default:
return -EIO;
} /* ext_attr->standard */
} else { /* insert_rs_byte == false */
/* disable parity symbol forward */
fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
/* MVAL enable during parity bytes */
fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
rcn_rate = 0x0041605C;
break;
case DRX_STANDARD_ITU_B:
fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
switch (ext_attr->constellation) {
case DRX_CONSTELLATION_QAM256:
rcn_rate = 0x0082D6A0;
break;
case DRX_CONSTELLATION_QAM64:
rcn_rate = 0x005AEC1A;
break;
default:
return -EIO;
}
break;
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
/* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
rcn_rate =
(frac28
(max_bit_rate,
(u32) (common_attr->sys_clock_freq / 8))) /
204;
break;
default:
return -EIO;
} /* ext_attr->standard */
}
if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
} else { /* MPEG data output is serial -> set ipr_mode[0] */
fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
}
/* Control slective inversion of output bits */
if (cfg_data->invert_data == true)
fec_oc_reg_ipr_invert |= invert_data_mask;
else
fec_oc_reg_ipr_invert &= (~(invert_data_mask));
if (cfg_data->invert_err == true)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
else
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
if (cfg_data->invert_str == true)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
else
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
if (cfg_data->invert_val == true)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
else
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
if (cfg_data->invert_clk == true)
fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
else
fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
if (cfg_data->static_clk == true) { /* Static mode */
u32 dto_rate = 0;
u32 bit_rate = 0;
u16 fec_oc_dto_burst_len = 0;
u16 fec_oc_dto_period = 0;
fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
fec_oc_dto_period = 4;
if (cfg_data->insert_rs_byte == true)
fec_oc_dto_burst_len = 208;
break;
case DRX_STANDARD_ITU_A:
{
u32 symbol_rate_th = 6400000;
if (cfg_data->insert_rs_byte == true) {
fec_oc_dto_burst_len = 204;
symbol_rate_th = 5900000;
}
if (ext_attr->curr_symbol_rate >=
symbol_rate_th) {
fec_oc_dto_period = 0;
} else {
fec_oc_dto_period = 1;
}
}
break;
case DRX_STANDARD_ITU_B:
fec_oc_dto_period = 1;
if (cfg_data->insert_rs_byte == true)
fec_oc_dto_burst_len = 128;
break;
case DRX_STANDARD_ITU_C:
fec_oc_dto_period = 1;
if (cfg_data->insert_rs_byte == true)
fec_oc_dto_burst_len = 204;
break;
default:
return -EIO;
}
bit_rate =
common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
2);
dto_rate =
frac28(bit_rate, common_attr->sys_clock_freq * 1000);
dto_rate >>= 3;
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else { /* Dynamic mode */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write appropriate registers with requested configuration */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* enabling for both parallel and serial now */
/* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Set MPEG TS pads to outputmode */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
sio_pdr_md_cfg =
MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
sio_pdr_md_cfg =
MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
SIO_PDR_MD0_CFG_MODE__B;
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* Enable Monitor Bus output over MPEG pads and ctl input */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write nomagic word to enable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
/* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Set MPEG TS pads to inputmode */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Enable Monitor Bus output over MPEG pads and ctl input */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write nomagic word to enable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* save values for restore after re-acquire */
common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
return 0;
rw_error:
return rc;
}
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* MPEG Output Configuration Functions - end */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* miscellaneous configurations - begin */
/*----------------------------------------------------------------------------*/
/*
* \fn int set_mpegtei_handling()
* \brief Activate MPEG TEI handling settings.
* \param devmod Pointer to demodulator instance.
* \return int.
*
* This routine should be called during a set channel of QAM/VSB
*
*/
static int set_mpegtei_handling(struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
int rc;
u16 fec_oc_dpr_mode = 0;
u16 fec_oc_snc_mode = 0;
u16 fec_oc_ems_mode = 0;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* reset to default, allow TEI bit to be changed */
fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
FEC_OC_SNC_MODE_CORR_DISABLE__M));
fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
if (ext_attr->disable_te_ihandling) {
/* do not change TEI bit */
fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*----------------------------------------------------------------------------*/
/*
* \fn int bit_reverse_mpeg_output()
* \brief Set MPEG output bit-endian settings.
* \param devmod Pointer to demodulator instance.
* \return int.
*
* This routine should be called during a set channel of QAM/VSB
*
*/
static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
int rc;
u16 fec_oc_ipr_mode = 0;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* reset to default (normal bit order) */
fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
if (ext_attr->bit_reverse_mpeg_outout)
fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*----------------------------------------------------------------------------*/
/*
* \fn int set_mpeg_start_width()
* \brief Set MPEG start width.
* \param devmod Pointer to demodulator instance.
* \return int.
*
* This routine should be called during a set channel of QAM/VSB
*
*/
static int set_mpeg_start_width(struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
int rc;
u16 fec_oc_comm_mb = 0;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
common_attr = demod->my_common_attr;
if ((common_attr->mpeg_cfg.static_clk == true)
&& (common_attr->mpeg_cfg.enable_parallel == false)) {
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
return 0;
rw_error:
return rc;
}
/*----------------------------------------------------------------------------*/
/* miscellaneous configurations - end */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* UIO Configuration Functions - begin */
/*----------------------------------------------------------------------------*/
/*
* \fn int ctrl_set_uio_cfg()
* \brief Configure modus oprandi UIO.
* \param demod Pointer to demodulator instance.
* \param uio_cfg Pointer to a configuration setting for a certain UIO.
* \return int.
*/
static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
int rc;
if ((uio_cfg == NULL) || (demod == NULL))
return -EINVAL;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch (uio_cfg->uio) {
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
if (!ext_attr->has_smatx)
return -EIO;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE_SMA:
case DRX_UIO_MODE_FIRMWARE_SAW:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_sma_tx_mode = uio_cfg->mode;
break;
case DRX_UIO_MODE_DISABLE:
ext_attr->uio_sma_tx_mode = uio_cfg->mode;
/* pad configuration register is set 0 - input mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EINVAL;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
if (!ext_attr->has_smarx)
return -EIO;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE0:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_sma_rx_mode = uio_cfg->mode;
break;
case DRX_UIO_MODE_DISABLE:
ext_attr->uio_sma_rx_mode = uio_cfg->mode;
/* pad configuration register is set 0 - input mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EINVAL;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: GPIO UIO-3 */
if (!ext_attr->has_gpio)
return -EIO;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE0:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_gpio_mode = uio_cfg->mode;
break;
case DRX_UIO_MODE_DISABLE:
ext_attr->uio_gpio_mode = uio_cfg->mode;
/* pad configuration register is set 0 - input mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EINVAL;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
if (!ext_attr->has_irqn)
return -EIO;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_irqn_mode = uio_cfg->mode;
break;
case DRX_UIO_MODE_DISABLE:
/* pad configuration register is set 0 - input mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->uio_irqn_mode = uio_cfg->mode;
break;
case DRX_UIO_MODE_FIRMWARE0:
default:
return -EINVAL;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
default:
return -EINVAL;
} /* switch ( uio_cfg->uio ) */
/* Write magic word to disable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int ctrl_uio_write()
* \brief Write to a UIO.
* \param demod Pointer to demodulator instance.
* \param uio_data Pointer to data container for a certain UIO.
* \return int.
*/
static int
ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
{
struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
int rc;
u16 pin_cfg_value = 0;
u16 value = 0;
if ((uio_data == NULL) || (demod == NULL))
return -EINVAL;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch (uio_data->uio) {
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
if (!ext_attr->has_smatx)
return -EIO;
if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
&& (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
return -EIO;
}
pin_cfg_value = 0;
/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
pin_cfg_value |= 0x0113;
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
/* write to io pad configuration register - output mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* use corresponding bit in io data output registar */
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (!uio_data->value)
value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
else
value |= 0x8000; /* write one to 15th bit - 1st UIO */
/* write back to io data output register */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
/*======================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
if (!ext_attr->has_smarx)
return -EIO;
if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
return -EIO;
pin_cfg_value = 0;
/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
pin_cfg_value |= 0x0113;
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
/* write to io pad configuration register - output mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* use corresponding bit in io data output registar */
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (!uio_data->value)
value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
else
value |= 0x4000; /* write one to 14th bit - 2nd UIO */
/* write back to io data output register */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: ASEL UIO-3 */
if (!ext_attr->has_gpio)
return -EIO;
if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
return -EIO;
pin_cfg_value = 0;
/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
pin_cfg_value |= 0x0113;
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
/* write to io pad configuration register - output mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* use corresponding bit in io data output registar */
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (!uio_data->value)
value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
else
value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
/* write back to io data output register */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
/*=====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
if (!ext_attr->has_irqn)
return -EIO;
if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
return -EIO;
pin_cfg_value = 0;
/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
pin_cfg_value |= 0x0113;
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
/* write to io pad configuration register - output mode */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* use corresponding bit in io data output registar */
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (uio_data->value == false)
value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
else
value |= 0x1000; /* write one to 12th bit - 4th UIO */
/* write back to io data output register */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
/*=====================================================================*/
default:
return -EINVAL;
} /* switch ( uio_data->uio ) */
/* Write magic word to disable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*---------------------------------------------------------------------------*/
/* UIO Configuration Functions - end */
/*---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* I2C Bridge Functions - begin */
/*----------------------------------------------------------------------------*/
/*
* \fn int ctrl_i2c_bridge()
* \brief Open or close the I2C switch to tuner.
* \param demod Pointer to demodulator instance.
* \param bridge_closed Pointer to bool indication if bridge is closed not.
* \return int.
*/
static int
ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
{
struct drxj_hi_cmd hi_cmd;
u16 result = 0;
/* check arguments */
if (bridge_closed == NULL)
return -EINVAL;
hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
if (*bridge_closed)
hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
else
hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
}
/*----------------------------------------------------------------------------*/
/* I2C Bridge Functions - end */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* Smart antenna Functions - begin */
/*----------------------------------------------------------------------------*/
/*
* \fn int smart_ant_init()
* \brief Initialize Smart Antenna.
* \param pointer to struct drx_demod_instance.
* \return int.
*
*/
static int smart_ant_init(struct drx_demod_instance *demod)
{
struct drxj_data *ext_attr = NULL;
struct i2c_device_addr *dev_addr = NULL;
struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
int rc;
u16 data = 0;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* init smart antenna */
rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (ext_attr->smart_ant_inverted) {
rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* config SMA_TX pin to smart antenna mode */
rc = ctrl_set_uio_cfg(demod, &uio_cfg);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write magic word to disable pdr reg write */
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
{
int rc;
u16 cur_cmd = 0;
unsigned long timeout;
/* Check param */
if (cmd == NULL)
return -EINVAL;
/* Wait until SCU command interface is ready to receive command */
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (cur_cmd != DRX_SCU_READY)
return -EIO;
switch (cmd->parameter_len) {
case 5:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 4:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 3:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 2:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 1:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 0:
/* do nothing */
break;
default:
/* this number of parameters is not supported */
return -EIO;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Wait until SCU has processed command */
timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
while (time_is_after_jiffies(timeout)) {
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (cur_cmd == DRX_SCU_READY)
break;
usleep_range(1000, 2000);
}
if (cur_cmd != DRX_SCU_READY)
return -EIO;
/* read results */
if ((cmd->result_len > 0) && (cmd->result != NULL)) {
s16 err;
switch (cmd->result_len) {
case 4:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 3:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 2:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 1:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
fallthrough;
case 0:
/* do nothing */
break;
default:
/* this number of parameters is not supported */
return -EIO;
}
/* Check if an error was reported by SCU */
err = cmd->result[0];
/* check a few fixed error codes */
if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
|| (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
|| (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
|| (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
) {
return -EINVAL;
}
/* here it is assumed that negative means error, and positive no error */
else if (err < 0)
return -EIO;
else
return 0;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
* \brief Basic access routine for SCU atomic read or write access
* \param dev_addr pointer to i2c dev address
* \param addr destination/source address
* \param datasize size of data buffer in bytes
* \param data pointer to data buffer
* \return int
* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
*/
#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
static
int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
u8 *data, bool read_flag)
{
struct drxjscu_cmd scu_cmd;
int rc;
u16 set_param_parameters[18];
u16 cmd_result[15];
/* Parameter check */
if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
return -EINVAL;
set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
if (read_flag) { /* read */
set_param_parameters[0] = ((~(0x0080)) & datasize);
scu_cmd.parameter_len = 2;
scu_cmd.result_len = datasize / 2 + 2;
} else {
int i = 0;
set_param_parameters[0] = 0x0080 | datasize;
for (i = 0; i < (datasize / 2); i++) {
set_param_parameters[i + 2] =
(data[2 * i] | (data[(2 * i) + 1] << 8));
}
scu_cmd.parameter_len = datasize / 2 + 2;
scu_cmd.result_len = 1;
}
scu_cmd.command =
SCU_RAM_COMMAND_STANDARD_TOP |
SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
scu_cmd.result = cmd_result;
scu_cmd.parameter = set_param_parameters;
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (read_flag) {
int i = 0;
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
}
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int DRXJ_DAP_AtomicReadReg16()
* \brief Atomic read of 16 bits words
*/
static
int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 *data, u32 flags)
{
u8 buf[2] = { 0 };
int rc;
u16 word = 0;
if (!data)
return -EINVAL;
rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
if (rc < 0)
return rc;
word = (u16) (buf[0] + (buf[1] << 8));
*data = word;
return rc;
}
/*============================================================================*/
/*
* \fn int drxj_dap_scu_atomic_write_reg16()
* \brief Atomic read of 16 bits words
*/
static
int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
u32 addr,
u16 data, u32 flags)
{
u8 buf[2];
int rc;
buf[0] = (u8) (data & 0xff);
buf[1] = (u8) ((data >> 8) & 0xff);
rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
return rc;
}
/* -------------------------------------------------------------------------- */
/*
* \brief Measure result of ADC synchronisation
* \param demod demod instance
* \param count (returned) count
* \return int.
* \retval 0 Success
* \retval -EIO Failure: I2C error
*
*/
static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
{
struct i2c_device_addr *dev_addr = NULL;
int rc;
u16 data = 0;
dev_addr = demod->my_i2c_dev_addr;
/* Start measurement */
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
msleep(1);
*count = 0;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (data == 127)
*count = *count + 1;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (data == 127)
*count = *count + 1;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (data == 127)
*count = *count + 1;
return 0;
rw_error:
return rc;
}
/*
* \brief Synchronize analog and digital clock domains
* \param demod demod instance
* \return int.
* \retval 0 Success
* \retval -EIO Failure: I2C error or failure to synchronize
*
* An IQM reset will also reset the results of this synchronization.
* After an IQM reset this routine needs to be called again.
*
*/
static int adc_synchronization(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
int rc;
u16 count = 0;
dev_addr = demod->my_i2c_dev_addr;
rc = adc_sync_measurement(demod, &count);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (count == 1) {
/* Try sampling on a different edge */
u16 clk_neg = 0;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = adc_sync_measurement(demod, &count);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* TODO: implement fallback scenarios */
if (count < 2)
return -EIO;
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== END AUXILIARY FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn int init_agc ()
* \brief Initialize AGC for all standards.
* \param demod instance of demodulator.
* \param channel pointer to channel data.
* \return int.
*/
static int init_agc(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
struct drx_common_attr *common_attr = NULL;
struct drxj_data *ext_attr = NULL;
struct drxj_cfg_agc *p_agc_rf_settings = NULL;
struct drxj_cfg_agc *p_agc_if_settings = NULL;
int rc;
u16 ingain_tgt_max = 0;
u16 clp_dir_to = 0;
u16 sns_sum_max = 0;
u16 clp_sum_max = 0;
u16 sns_dir_to = 0;
u16 ki_innergain_min = 0;
u16 agc_ki = 0;
u16 ki_max = 0;
u16 if_iaccu_hi_tgt_min = 0;
u16 data = 0;
u16 agc_ki_dgain = 0;
u16 ki_min = 0;
u16 clp_ctrl_mode = 0;
u16 agc_rf = 0;
u16 agc_if = 0;
dev_addr = demod->my_i2c_dev_addr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
clp_sum_max = 1023;
clp_dir_to = (u16) (-9);
sns_sum_max = 1023;
sns_dir_to = (u16) (-9);
ki_innergain_min = (u16) (-32768);
ki_max = 0x032C;
agc_ki_dgain = 0xC;
if_iaccu_hi_tgt_min = 2047;
ki_min = 0x0117;
ingain_tgt_max = 16383;
clp_ctrl_mode = 0;
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
case DRX_STANDARD_ITU_B:
ingain_tgt_max = 5119;
clp_sum_max = 1023;
clp_dir_to = (u16) (-5);
sns_sum_max = 127;
sns_dir_to = (u16) (-3);
ki_innergain_min = 0;
ki_max = 0x0657;
if_iaccu_hi_tgt_min = 2047;
agc_ki_dgain = 0x7;
ki_min = 0x0117;
clp_ctrl_mode = 0;
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
agc_ki &= 0xf000;
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
#endif
default:
return -EINVAL;
}
/* for new AGC interface */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* Gain fed from inner to outer AGC */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* set to p_agc_settings->top before */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
if (common_attr->tuner_rf_agc_pol == true)
agc_rf = 0x87ff - agc_rf;
agc_if = 0x800;
if (common_attr->tuner_if_agc_pol == true)
agc_rf = 0x87ff - agc_rf;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Set/restore Ki DGAIN factor */
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_DGAIN__M;
data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int set_frequency ()
* \brief Set frequency shift.
* \param demod instance of demodulator.
* \param channel pointer to channel data.
* \param tuner_freq_offset residual frequency from tuner.
* \return int.
*/
static int
set_frequency(struct drx_demod_instance *demod,
struct drx_channel *channel, s32 tuner_freq_offset)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxj_data *ext_attr = demod->my_ext_attr;
int rc;
s32 sampling_frequency = 0;
s32 frequency_shift = 0;
s32 if_freq_actual = 0;
s32 rf_freq_residual = -1 * tuner_freq_offset;
s32 adc_freq = 0;
s32 intermediate_freq = 0;
u32 iqm_fs_rate_ofs = 0;
bool adc_flip = true;
bool select_pos_image = false;
bool rf_mirror;
bool tuner_mirror;
bool image_to_select;
s32 fm_frequency_shift = 0;
rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
/*
Program frequency shifter
No need to account for mirroring on RF
*/
switch (ext_attr->standard) {
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
case DRX_STANDARD_PAL_SECAM_LP:
case DRX_STANDARD_8VSB:
select_pos_image = true;
break;
case DRX_STANDARD_FM:
/* After IQM FS sound carrier must appear at 4 Mhz in spect.
Sound carrier is already 3Mhz above centre frequency due
to tuner setting so now add an extra shift of 1MHz... */
fm_frequency_shift = 1000;
fallthrough;
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_NTSC:
case DRX_STANDARD_PAL_SECAM_BG:
case DRX_STANDARD_PAL_SECAM_DK:
case DRX_STANDARD_PAL_SECAM_I:
case DRX_STANDARD_PAL_SECAM_L:
select_pos_image = false;
break;
default:
return -EINVAL;
}
intermediate_freq = demod->my_common_attr->intermediate_freq;
sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
if (tuner_mirror)
if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
else
if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
if (if_freq_actual > sampling_frequency / 2) {
/* adc mirrors */
adc_freq = sampling_frequency - if_freq_actual;
adc_flip = true;
} else {
/* adc doesn't mirror */
adc_freq = if_freq_actual;
adc_flip = false;
}
frequency_shift = adc_freq;
image_to_select =
(bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
if (image_to_select)
iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
/* Program frequency shifter with tuner offset compensation */
/* frequency_shift += tuner_freq_offset; TODO */
rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
return 0;
rw_error:
return rc;
}
/*
* \fn int get_acc_pkt_err()
* \brief Retrieve signal strength for VSB and QAM.
* \param demod Pointer to demod instance
* \param packet_err Pointer to packet error
* \return int.
* \retval 0 sig_strength contains valid data.
* \retval -EINVAL sig_strength is NULL.
* \retval -EIO Erroneous data, sig_strength contains invalid data.
*/
#ifdef DRXJ_SIGNAL_ACCUM_ERR
static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
{
int rc;
static u16 pkt_err;
static u16 last_pkt_err;
u16 data = 0;
struct drxj_data *ext_attr = NULL;
struct i2c_device_addr *dev_addr = NULL;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
dev_addr = demod->my_i2c_dev_addr;
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (ext_attr->reset_pkt_err_acc) {
last_pkt_err = data;
pkt_err = 0;
ext_attr->reset_pkt_err_acc = false;
}
if (data < last_pkt_err) {
pkt_err += 0xffff - last_pkt_err;
pkt_err += data;
} else {
pkt_err += (data - last_pkt_err);
}
*packet_err = pkt_err;
last_pkt_err = data;
return 0;
rw_error:
return rc;
}
#endif
/*============================================================================*/
/*
* \fn int set_agc_rf ()
* \brief Configure RF AGC
* \param demod instance of demodulator.
* \param agc_settings AGC configuration structure
* \return int.
*/
static int
set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
struct drxj_cfg_agc *p_agc_settings = NULL;
struct drx_common_attr *common_attr = NULL;
int rc;
drx_write_reg16func_t scu_wr16 = NULL;
drx_read_reg16func_t scu_rr16 = NULL;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
if (atomic) {
scu_rr16 = drxj_dap_scu_atomic_read_reg16;
scu_wr16 = drxj_dap_scu_atomic_write_reg16;
} else {
scu_rr16 = drxj_dap_read_reg16;
scu_wr16 = drxj_dap_write_reg16;
}
/* Configure AGC only if standard is currently active */
if ((ext_attr->standard == agc_settings->standard) ||
(DRXJ_ISQAMSTD(ext_attr->standard) &&
DRXJ_ISQAMSTD(agc_settings->standard)) ||
(DRXJ_ISATVSTD(ext_attr->standard) &&
DRXJ_ISATVSTD(agc_settings->standard))) {
u16 data = 0;
switch (agc_settings->ctrl_mode) {
case DRX_AGC_CTRL_AUTO:
/* Enable RF AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Enable SCU RF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_RF__M;
if (ext_attr->standard == DRX_STANDARD_8VSB)
data |= (2 << SCU_RAM_AGC_KI_RF__B);
else if (DRXJ_ISQAMSTD(ext_attr->standard))
data |= (5 << SCU_RAM_AGC_KI_RF__B);
else
data |= (4 << SCU_RAM_AGC_KI_RF__B);
if (common_attr->tuner_rf_agc_pol)
data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
else
data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Set speed ( using complementary reduction value ) */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (agc_settings->standard == DRX_STANDARD_8VSB)
p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
else if (DRXJ_ISQAMSTD(agc_settings->standard))
p_agc_settings = &(ext_attr->qam_if_agc_cfg);
else if (DRXJ_ISATVSTD(agc_settings->standard))
p_agc_settings = &(ext_attr->atv_if_agc_cfg);
else
return -EINVAL;
/* Set TOP, only if IF-AGC is in AUTO mode */
if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* Cut-Off current */
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_AGC_CTRL_USER:
/* Enable RF AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Disable SCU RF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_RF__M;
if (common_attr->tuner_rf_agc_pol)
data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
else
data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write value to output pin */
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_AGC_CTRL_OFF:
/* Disable RF AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Disable SCU RF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_RF__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EINVAL;
} /* switch ( agcsettings->ctrl_mode ) */
}
/* Store rf agc settings */
switch (agc_settings->standard) {
case DRX_STANDARD_8VSB:
ext_attr->vsb_rf_agc_cfg = *agc_settings;
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_rf_agc_cfg = *agc_settings;
break;
#endif
default:
return -EIO;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int set_agc_if ()
* \brief Configure If AGC
* \param demod instance of demodulator.
* \param agc_settings AGC configuration structure
* \return int.
*/
static int
set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
struct drxj_cfg_agc *p_agc_settings = NULL;
struct drx_common_attr *common_attr = NULL;
drx_write_reg16func_t scu_wr16 = NULL;
drx_read_reg16func_t scu_rr16 = NULL;
int rc;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
if (atomic) {
scu_rr16 = drxj_dap_scu_atomic_read_reg16;
scu_wr16 = drxj_dap_scu_atomic_write_reg16;
} else {
scu_rr16 = drxj_dap_read_reg16;
scu_wr16 = drxj_dap_write_reg16;
}
/* Configure AGC only if standard is currently active */
if ((ext_attr->standard == agc_settings->standard) ||
(DRXJ_ISQAMSTD(ext_attr->standard) &&
DRXJ_ISQAMSTD(agc_settings->standard)) ||
(DRXJ_ISATVSTD(ext_attr->standard) &&
DRXJ_ISATVSTD(agc_settings->standard))) {
u16 data = 0;
switch (agc_settings->ctrl_mode) {
case DRX_AGC_CTRL_AUTO:
/* Enable IF AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Enable SCU IF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
data &= ~SCU_RAM_AGC_KI_IF__M;
if (ext_attr->standard == DRX_STANDARD_8VSB)
data |= (3 << SCU_RAM_AGC_KI_IF__B);
else if (DRXJ_ISQAMSTD(ext_attr->standard))
data |= (6 << SCU_RAM_AGC_KI_IF__B);
else
data |= (5 << SCU_RAM_AGC_KI_IF__B);
if (common_attr->tuner_if_agc_pol)
data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
else
data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Set speed (using complementary reduction value) */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (agc_settings->standard == DRX_STANDARD_8VSB)
p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
else if (DRXJ_ISQAMSTD(agc_settings->standard))
p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
else if (DRXJ_ISATVSTD(agc_settings->standard))
p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
else
return -EINVAL;
/* Restore TOP */
if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
break;
case DRX_AGC_CTRL_USER:
/* Enable IF AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Disable SCU IF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
if (common_attr->tuner_if_agc_pol)
data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
else
data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Write value to output pin */
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_AGC_CTRL_OFF:
/* Disable If AGC DAC */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Disable SCU IF AGC loop */
rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EINVAL;
} /* switch ( agcsettings->ctrl_mode ) */
/* always set the top to support configurations without if-loop */
rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* Store if agc settings */
switch (agc_settings->standard) {
case DRX_STANDARD_8VSB:
ext_attr->vsb_if_agc_cfg = *agc_settings;
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_if_agc_cfg = *agc_settings;
break;
#endif
default:
return -EIO;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int set_iqm_af ()
* \brief Configure IQM AF registers
* \param demod instance of demodulator.
* \param active
* \return int.
*/
static int set_iqm_af(struct drx_demod_instance *demod, bool active)
{
u16 data = 0;
struct i2c_device_addr *dev_addr = NULL;
int rc;
dev_addr = demod->my_i2c_dev_addr;
/* Configure IQM */
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (!active)
data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
else
data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== 8VSB DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn int power_down_vsb ()
* \brief Powr down QAM related blocks.
* \param demod instance of demodulator.
* \param channel pointer to channel data.
* \return int.
*/
static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxjscu_cmd cmd_scu = { /* command */ 0,
/* parameter_len */ 0,
/* result_len */ 0,
/* *parameter */ NULL,
/* *result */ NULL
};
struct drx_cfg_mpeg_output cfg_mpeg_output;
int rc;
u16 cmd_result = 0;
/*
STOP demodulator
reset of FEC and VSB HW
*/
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
SCU_RAM_COMMAND_CMD_DEMOD_STOP;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* stop all comm_exec */
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (primary) {
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_iqm_af(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
cfg_mpeg_output.enable_mpeg_output = false;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int set_vsb_leak_n_gain ()
* \brief Set ATSC demod.
* \param demod instance of demodulator.
* \return int.
*/
static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
int rc;
static const u8 vsb_ffe_leak_gain_ram0[] = {
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */
DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */
DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */
DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */
DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */
DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */
DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */
DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */
DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */
DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */
DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */
DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */
DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */
DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */
DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */
DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */
DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */
DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */
DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */
DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */
DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */
DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */
DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */
DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */
DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */
DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */
};
static const u8 vsb_ffe_leak_gain_ram1[] = {
DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */
DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */
DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */
DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */
DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */
DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */
DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */
DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */
DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */
DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */
DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */
DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */
DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */
DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */
DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */
DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */
DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */
DRXJ_16TO8(0x0000), /* DFETRAINGAIN */
DRXJ_16TO8(0x2020), /* DFERCA1GAIN */
DRXJ_16TO8(0x1010), /* DFERCA2GAIN */
DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */
DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */
};
dev_addr = demod->my_i2c_dev_addr;
rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int set_vsb()
* \brief Set 8VSB demod.
* \param demod instance of demodulator.
* \return int.
*
*/
static int set_vsb(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
int rc;
struct drx_common_attr *common_attr = NULL;
struct drxjscu_cmd cmd_scu;
struct drxj_data *ext_attr = NULL;
u16 cmd_result = 0;
u16 cmd_param = 0;
static const u8 vsb_taps_re[] = {
DRXJ_16TO8(-2), /* re0 */
DRXJ_16TO8(4), /* re1 */
DRXJ_16TO8(1), /* re2 */
DRXJ_16TO8(-4), /* re3 */
DRXJ_16TO8(1), /* re4 */
DRXJ_16TO8(4), /* re5 */
DRXJ_16TO8(-3), /* re6 */
DRXJ_16TO8(-3), /* re7 */
DRXJ_16TO8(6), /* re8 */
DRXJ_16TO8(1), /* re9 */
DRXJ_16TO8(-9), /* re10 */
DRXJ_16TO8(3), /* re11 */
DRXJ_16TO8(12), /* re12 */
DRXJ_16TO8(-9), /* re13 */
DRXJ_16TO8(-15), /* re14 */
DRXJ_16TO8(17), /* re15 */
DRXJ_16TO8(19), /* re16 */
DRXJ_16TO8(-29), /* re17 */
DRXJ_16TO8(-22), /* re18 */
DRXJ_16TO8(45), /* re19 */
DRXJ_16TO8(25), /* re20 */
DRXJ_16TO8(-70), /* re21 */
DRXJ_16TO8(-28), /* re22 */
DRXJ_16TO8(111), /* re23 */
DRXJ_16TO8(30), /* re24 */
DRXJ_16TO8(-201), /* re25 */
DRXJ_16TO8(-31), /* re26 */
DRXJ_16TO8(629) /* re27 */
};
dev_addr = demod->my_i2c_dev_addr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* stop all comm_exec */
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* reset demodulator */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_RESET;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* set higher threshold */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* burst detection on */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* drop thresholds by 1 dB */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* drop thresholds by 2 dB */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* cma on */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* GPIO */
/* Initialize the FEC Subsystem */
rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
u16 fec_oc_snc_mode = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* output data even when not locked */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* set clip */
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no transparent, no A&C framing; parity is set in mpegoutput */
{
u16 fec_oc_reg_mode = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* timeout counter for restarting */
rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* bypass disabled */
/* initialize RS packet error measurement parameters */
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* init measurement period of MER/SER */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* B-Input to ADC, PGA+filter in standby */
if (!ext_attr->has_lna) {
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* turn on IQMAF. It has to be in front of setAgc**() */
rc = set_iqm_af(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = adc_synchronization(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = init_agc(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
of only the gain */
struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Mpeg output has to be in front of FEC active */
rc = set_mpegtei_handling(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = bit_reverse_mpeg_output(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_mpeg_start_width(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO: move to set_standard after hardware reset value problem is solved */
/* Configure initial MPEG output */
struct drx_cfg_mpeg_output cfg_mpeg_output;
memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
cfg_mpeg_output.enable_mpeg_output = true;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* TBD: what parameters should be set */
cmd_param = 0x00; /* Default mode AGC on, etc */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
cmd_scu.parameter_len = 1;
cmd_scu.result_len = 1;
cmd_scu.parameter = &cmd_param;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* start demodulator */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_START;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
* \brief Get the values of packet error in 8VSB mode
* \return Error code
*/
static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
u32 *pck_errs, u32 *pck_count)
{
int rc;
u16 data = 0;
u16 period = 0;
u16 prescale = 0;
u16 packet_errors_mant = 0;
u16 packet_errors_exp = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
>> FEC_RS_NR_FAILURES_EXP__B;
period = FEC_RS_MEASUREMENT_PERIOD;
prescale = FEC_RS_MEASUREMENT_PRESCALE;
/* packet error rate = (error packet number) per second */
/* 77.3 us is time for per packet */
if (period * prescale == 0) {
pr_err("error: period and/or prescale is zero!\n");
return -EIO;
}
*pck_errs = packet_errors_mant * (1 << packet_errors_exp);
*pck_count = period * prescale * 77;
return 0;
rw_error:
return rc;
}
/*
* \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
* \brief Get the values of ber in VSB mode
* \return Error code
*/
static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
u32 *ber, u32 *cnt)
{
int rc;
u16 data = 0;
u16 period = 0;
u16 prescale = 0;
u16 bit_errors_mant = 0;
u16 bit_errors_exp = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
period = FEC_RS_MEASUREMENT_PERIOD;
prescale = FEC_RS_MEASUREMENT_PRESCALE;
bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
>> FEC_RS_NR_BIT_ERRORS_EXP__B;
*cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
*ber = (*cnt) * 26570;
else {
if (period * prescale == 0) {
pr_err("error: period and/or prescale is zero!\n");
return -EIO;
}
*ber = bit_errors_mant << ((bit_errors_exp > 2) ?
(bit_errors_exp - 3) : bit_errors_exp);
}
return 0;
rw_error:
return rc;
}
/*
* \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
* \brief Get the values of ber in VSB mode
* \return Error code
*/
static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
u32 *ber, u32 *cnt)
{
u16 data = 0;
int rc;
rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
return -EIO;
}
*ber = data;
*cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
return 0;
}
/*
* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
* \brief Get the values of MER
* \return Error code
*/
static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
{
int rc;
u16 data_hi = 0;
rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
*mer =
(u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== END 8VSB DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== QAM DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
* \fn int power_down_qam ()
* \brief Powr down QAM related blocks.
* \param demod instance of demodulator.
* \param channel pointer to channel data.
* \return int.
*/
static int power_down_qam(struct drx_demod_instance *demod, bool primary)
{
struct drxjscu_cmd cmd_scu = { /* command */ 0,
/* parameter_len */ 0,
/* result_len */ 0,
/* *parameter */ NULL,
/* *result */ NULL
};
int rc;
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drx_cfg_mpeg_output cfg_mpeg_output;
struct drx_common_attr *common_attr = demod->my_common_attr;
u16 cmd_result = 0;
/*
STOP demodulator
resets IQM, QAM and FEC HW blocks
*/
/* stop all comm_exec */
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_STOP;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (primary) {
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_iqm_af(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
cfg_mpeg_output.enable_mpeg_output = false;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam_measurement ()
* \brief Setup of the QAM Measuremnt intervals for signal quality
* \param demod instance of demod.
* \param constellation current constellation.
* \return int.
*
* NOTE:
* Take into account that for certain settings the errorcounters can overflow.
* The implementation does not check this.
*
* TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
* constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
* field ?
*
*/
#ifndef DRXJ_VSB_ONLY
static int
set_qam_measurement(struct drx_demod_instance *demod,
enum drx_modulation constellation, u32 symbol_rate)
{
struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */
struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
int rc;
u32 fec_bits_desired = 0; /* BER accounting period */
u16 fec_rs_plen = 0; /* defines RS BER measurement period */
u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
u32 fec_rs_period = 0; /* Value for corresponding I2C register */
u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
u32 qam_vd_period = 0; /* Value for corresponding I2C register */
u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */
u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
fec_bits_desired = ext_attr->fec_bits_desired;
fec_rs_prescale = ext_attr->fec_rs_prescale;
switch (constellation) {
case DRX_CONSTELLATION_QAM16:
fec_bits_desired = 4 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM32:
fec_bits_desired = 5 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM64:
fec_bits_desired = 6 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM128:
fec_bits_desired = 7 * symbol_rate;
break;
case DRX_CONSTELLATION_QAM256:
fec_bits_desired = 8 * symbol_rate;
break;
default:
return -EINVAL;
}
/* Parameters for Reed-Solomon Decoder */
/* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
/* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
/* result is within 32 bit arithmetic -> */
/* no need for mult or frac functions */
/* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
switch (ext_attr->standard) {
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
fec_rs_plen = 204 * 8;
break;
case DRX_STANDARD_ITU_B:
fec_rs_plen = 128 * 7;
break;
default:
return -EINVAL;
}
ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */
if (fec_rs_bit_cnt == 0) {
pr_err("error: fec_rs_bit_cnt is zero!\n");
return -EIO;
}
fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */
if (ext_attr->standard != DRX_STANDARD_ITU_B)
fec_oc_snc_fail_period = fec_rs_period;
/* limit to max 16 bit value (I2C register width) if needed */
if (fec_rs_period > 0xFFFF)
fec_rs_period = 0xFFFF;
/* write corresponding registers */
switch (ext_attr->standard) {
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
break;
case DRX_STANDARD_ITU_B:
switch (constellation) {
case DRX_CONSTELLATION_QAM64:
fec_rs_period = 31581;
fec_oc_snc_fail_period = 17932;
break;
case DRX_CONSTELLATION_QAM256:
fec_rs_period = 45446;
fec_oc_snc_fail_period = 25805;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->fec_rs_period = (u16) fec_rs_period;
ext_attr->fec_rs_prescale = fec_rs_prescale;
rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (ext_attr->standard == DRX_STANDARD_ITU_B) {
/* Parameters for Viterbi Decoder */
/* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
/* (qamvd_prescale*plen*(qam_constellation+1))) */
/* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
/* result is within 32 bit arithmetic -> */
/* no need for mult or frac functions */
/* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
fec_vd_plen = ext_attr->fec_vd_plen;
qam_vd_prescale = ext_attr->qam_vd_prescale;
qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
switch (constellation) {
case DRX_CONSTELLATION_QAM64:
/* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
qam_vd_period =
qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
* (QAM_TOP_CONSTELLATION_QAM64 + 1);
break;
case DRX_CONSTELLATION_QAM256:
/* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
qam_vd_period =
qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
* (QAM_TOP_CONSTELLATION_QAM256 + 1);
break;
default:
return -EINVAL;
}
if (qam_vd_period == 0) {
pr_err("error: qam_vd_period is zero!\n");
return -EIO;
}
qam_vd_period = fec_bits_desired / qam_vd_period;
/* limit to max 16 bit value (I2C register width) if needed */
if (qam_vd_period > 0xFFFF)
qam_vd_period = 0xFFFF;
/* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
qam_vd_bit_cnt *= qam_vd_period;
rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->qam_vd_period = (u16) qam_vd_period;
ext_attr->qam_vd_prescale = qam_vd_prescale;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam16 ()
* \brief QAM16 specific setup
* \param demod instance of demod.
* \return int.
*/
static int set_qam16(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
static const u8 qam_dq_qual_fun[] = {
DRXJ_16TO8(2), /* fun0 */
DRXJ_16TO8(2), /* fun1 */
DRXJ_16TO8(2), /* fun2 */
DRXJ_16TO8(2), /* fun3 */
DRXJ_16TO8(3), /* fun4 */
DRXJ_16TO8(3), /* fun5 */
};
static const u8 qam_eq_cma_rad[] = {
DRXJ_16TO8(13517), /* RAD0 */
DRXJ_16TO8(13517), /* RAD1 */
DRXJ_16TO8(13517), /* RAD2 */
DRXJ_16TO8(13517), /* RAD3 */
DRXJ_16TO8(13517), /* RAD4 */
DRXJ_16TO8(13517), /* RAD5 */
};
rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam32 ()
* \brief QAM32 specific setup
* \param demod instance of demod.
* \return int.
*/
static int set_qam32(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
static const u8 qam_dq_qual_fun[] = {
DRXJ_16TO8(3), /* fun0 */
DRXJ_16TO8(3), /* fun1 */
DRXJ_16TO8(3), /* fun2 */
DRXJ_16TO8(3), /* fun3 */
DRXJ_16TO8(4), /* fun4 */
DRXJ_16TO8(4), /* fun5 */
};
static const u8 qam_eq_cma_rad[] = {
DRXJ_16TO8(6707), /* RAD0 */
DRXJ_16TO8(6707), /* RAD1 */
DRXJ_16TO8(6707), /* RAD2 */
DRXJ_16TO8(6707), /* RAD3 */
DRXJ_16TO8(6707), /* RAD4 */
DRXJ_16TO8(6707), /* RAD5 */
};
rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam64 ()
* \brief QAM64 specific setup
* \param demod instance of demod.
* \return int.
*/
static int set_qam64(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
static const u8 qam_dq_qual_fun[] = {
/* this is hw reset value. no necessary to re-write */
DRXJ_16TO8(4), /* fun0 */
DRXJ_16TO8(4), /* fun1 */
DRXJ_16TO8(4), /* fun2 */
DRXJ_16TO8(4), /* fun3 */
DRXJ_16TO8(6), /* fun4 */
DRXJ_16TO8(6), /* fun5 */
};
static const u8 qam_eq_cma_rad[] = {
DRXJ_16TO8(13336), /* RAD0 */
DRXJ_16TO8(12618), /* RAD1 */
DRXJ_16TO8(11988), /* RAD2 */
DRXJ_16TO8(13809), /* RAD3 */
DRXJ_16TO8(13809), /* RAD4 */
DRXJ_16TO8(15609), /* RAD5 */
};
rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam128 ()
* \brief QAM128 specific setup
* \param demod: instance of demod.
* \return int.
*/
static int set_qam128(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
static const u8 qam_dq_qual_fun[] = {
DRXJ_16TO8(6), /* fun0 */
DRXJ_16TO8(6), /* fun1 */
DRXJ_16TO8(6), /* fun2 */
DRXJ_16TO8(6), /* fun3 */
DRXJ_16TO8(9), /* fun4 */
DRXJ_16TO8(9), /* fun5 */
};
static const u8 qam_eq_cma_rad[] = {
DRXJ_16TO8(6164), /* RAD0 */
DRXJ_16TO8(6598), /* RAD1 */
DRXJ_16TO8(6394), /* RAD2 */
DRXJ_16TO8(6409), /* RAD3 */
DRXJ_16TO8(6656), /* RAD4 */
DRXJ_16TO8(7238), /* RAD5 */
};
rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int set_qam256 ()
* \brief QAM256 specific setup
* \param demod: instance of demod.
* \return int.
*/
static int set_qam256(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
static const u8 qam_dq_qual_fun[] = {
DRXJ_16TO8(8), /* fun0 */
DRXJ_16TO8(8), /* fun1 */
DRXJ_16TO8(8), /* fun2 */
DRXJ_16TO8(8), /* fun3 */
DRXJ_16TO8(12), /* fun4 */
DRXJ_16TO8(12), /* fun5 */
};
static const u8 qam_eq_cma_rad[] = {
DRXJ_16TO8(12345), /* RAD0 */
DRXJ_16TO8(12345), /* RAD1 */
DRXJ_16TO8(13626), /* RAD2 */
DRXJ_16TO8(12931), /* RAD3 */
DRXJ_16TO8(14719), /* RAD4 */
DRXJ_16TO8(15356), /* RAD5 */
};
rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
#define QAM_SET_OP_ALL 0x1
#define QAM_SET_OP_CONSTELLATION 0x2
#define QAM_SET_OP_SPECTRUM 0X4
/*
* \fn int set_qam ()
* \brief Set QAM demod.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \return int.
*/
static int
set_qam(struct drx_demod_instance *demod,
struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
struct drx_common_attr *common_attr = NULL;
int rc;
u32 adc_frequency = 0;
u32 iqm_rc_rate = 0;
u16 cmd_result = 0;
u16 lc_symbol_freq = 0;
u16 iqm_rc_stretch = 0;
u16 set_env_parameters = 0;
u16 set_param_parameters[2] = { 0 };
struct drxjscu_cmd cmd_scu = { /* command */ 0,
/* parameter_len */ 0,
/* result_len */ 0,
/* parameter */ NULL,
/* result */ NULL
};
static const u8 qam_a_taps[] = {
DRXJ_16TO8(-1), /* re0 */
DRXJ_16TO8(1), /* re1 */
DRXJ_16TO8(1), /* re2 */
DRXJ_16TO8(-1), /* re3 */
DRXJ_16TO8(-1), /* re4 */
DRXJ_16TO8(2), /* re5 */
DRXJ_16TO8(1), /* re6 */
DRXJ_16TO8(-2), /* re7 */
DRXJ_16TO8(0), /* re8 */
DRXJ_16TO8(3), /* re9 */
DRXJ_16TO8(-1), /* re10 */
DRXJ_16TO8(-3), /* re11 */
DRXJ_16TO8(4), /* re12 */
DRXJ_16TO8(1), /* re13 */
DRXJ_16TO8(-8), /* re14 */
DRXJ_16TO8(4), /* re15 */
DRXJ_16TO8(13), /* re16 */
DRXJ_16TO8(-13), /* re17 */
DRXJ_16TO8(-19), /* re18 */
DRXJ_16TO8(28), /* re19 */
DRXJ_16TO8(25), /* re20 */
DRXJ_16TO8(-53), /* re21 */
DRXJ_16TO8(-31), /* re22 */
DRXJ_16TO8(96), /* re23 */
DRXJ_16TO8(37), /* re24 */
DRXJ_16TO8(-190), /* re25 */
DRXJ_16TO8(-40), /* re26 */
DRXJ_16TO8(619) /* re27 */
};
static const u8 qam_b64_taps[] = {
DRXJ_16TO8(0), /* re0 */
DRXJ_16TO8(-2), /* re1 */
DRXJ_16TO8(1), /* re2 */
DRXJ_16TO8(2), /* re3 */
DRXJ_16TO8(-2), /* re4 */
DRXJ_16TO8(0), /* re5 */
DRXJ_16TO8(4), /* re6 */
DRXJ_16TO8(-2), /* re7 */
DRXJ_16TO8(-4), /* re8 */
DRXJ_16TO8(4), /* re9 */
DRXJ_16TO8(3), /* re10 */
DRXJ_16TO8(-6), /* re11 */
DRXJ_16TO8(0), /* re12 */
DRXJ_16TO8(6), /* re13 */
DRXJ_16TO8(-5), /* re14 */
DRXJ_16TO8(-3), /* re15 */
DRXJ_16TO8(11), /* re16 */
DRXJ_16TO8(-4), /* re17 */
DRXJ_16TO8(-19), /* re18 */
DRXJ_16TO8(19), /* re19 */
DRXJ_16TO8(28), /* re20 */
DRXJ_16TO8(-45), /* re21 */
DRXJ_16TO8(-36), /* re22 */
DRXJ_16TO8(90), /* re23 */
DRXJ_16TO8(42), /* re24 */
DRXJ_16TO8(-185), /* re25 */
DRXJ_16TO8(-46), /* re26 */
DRXJ_16TO8(614) /* re27 */
};
static const u8 qam_b256_taps[] = {
DRXJ_16TO8(-2), /* re0 */
DRXJ_16TO8(4), /* re1 */
DRXJ_16TO8(1), /* re2 */
DRXJ_16TO8(-4), /* re3 */
DRXJ_16TO8(0), /* re4 */
DRXJ_16TO8(4), /* re5 */
DRXJ_16TO8(-2), /* re6 */
DRXJ_16TO8(-4), /* re7 */
DRXJ_16TO8(5), /* re8 */
DRXJ_16TO8(2), /* re9 */
DRXJ_16TO8(-8), /* re10 */
DRXJ_16TO8(2), /* re11 */
DRXJ_16TO8(11), /* re12 */
DRXJ_16TO8(-8), /* re13 */
DRXJ_16TO8(-15), /* re14 */
DRXJ_16TO8(16), /* re15 */
DRXJ_16TO8(19), /* re16 */
DRXJ_16TO8(-27), /* re17 */
DRXJ_16TO8(-22), /* re18 */
DRXJ_16TO8(44), /* re19 */
DRXJ_16TO8(26), /* re20 */
DRXJ_16TO8(-69), /* re21 */
DRXJ_16TO8(-28), /* re22 */
DRXJ_16TO8(110), /* re23 */
DRXJ_16TO8(31), /* re24 */
DRXJ_16TO8(-201), /* re25 */
DRXJ_16TO8(-32), /* re26 */
DRXJ_16TO8(628) /* re27 */
};
static const u8 qam_c_taps[] = {
DRXJ_16TO8(-3), /* re0 */
DRXJ_16TO8(3), /* re1 */
DRXJ_16TO8(2), /* re2 */
DRXJ_16TO8(-4), /* re3 */
DRXJ_16TO8(0), /* re4 */
DRXJ_16TO8(4), /* re5 */
DRXJ_16TO8(-1), /* re6 */
DRXJ_16TO8(-4), /* re7 */
DRXJ_16TO8(3), /* re8 */
DRXJ_16TO8(3), /* re9 */
DRXJ_16TO8(-5), /* re10 */
DRXJ_16TO8(0), /* re11 */
DRXJ_16TO8(9), /* re12 */
DRXJ_16TO8(-4), /* re13 */
DRXJ_16TO8(-12), /* re14 */
DRXJ_16TO8(10), /* re15 */
DRXJ_16TO8(16), /* re16 */
DRXJ_16TO8(-21), /* re17 */
DRXJ_16TO8(-20), /* re18 */
DRXJ_16TO8(37), /* re19 */
DRXJ_16TO8(25), /* re20 */
DRXJ_16TO8(-62), /* re21 */
DRXJ_16TO8(-28), /* re22 */
DRXJ_16TO8(105), /* re23 */
DRXJ_16TO8(31), /* re24 */
DRXJ_16TO8(-197), /* re25 */
DRXJ_16TO8(-33), /* re26 */
DRXJ_16TO8(626) /* re27 */
};
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
if (ext_attr->standard == DRX_STANDARD_ITU_B) {
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM256:
iqm_rc_rate = 0x00AE3562;
lc_symbol_freq =
QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
channel->symbolrate = 5360537;
iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
break;
case DRX_CONSTELLATION_QAM64:
iqm_rc_rate = 0x00C05A0E;
lc_symbol_freq = 409;
channel->symbolrate = 5056941;
iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
break;
default:
return -EINVAL;
}
} else {
adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
if (channel->symbolrate == 0) {
pr_err("error: channel symbolrate is zero!\n");
return -EIO;
}
iqm_rc_rate =
(adc_frequency / channel->symbolrate) * (1 << 21) +
(frac28
((adc_frequency % channel->symbolrate),
channel->symbolrate) >> 7) - (1 << 23);
lc_symbol_freq =
(u16) (frac28
(channel->symbolrate +
(adc_frequency >> 13),
adc_frequency) >> 16);
if (lc_symbol_freq > 511)
lc_symbol_freq = 511;
iqm_rc_stretch = 21;
}
if (ext_attr->standard == DRX_STANDARD_ITU_A) {
set_env_parameters = QAM_TOP_ANNEX_A; /* annex */
set_param_parameters[0] = channel->constellation; /* constellation */
set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
} else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
set_env_parameters = QAM_TOP_ANNEX_B; /* annex */
set_param_parameters[0] = channel->constellation; /* constellation */
set_param_parameters[1] = channel->interleavemode; /* interleave mode */
} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
set_env_parameters = QAM_TOP_ANNEX_C; /* annex */
set_param_parameters[0] = channel->constellation; /* constellation */
set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
} else {
return -EINVAL;
}
}
if (op & QAM_SET_OP_ALL) {
/*
STEP 1: reset demodulator
resets IQM, QAM and FEC HW blocks
resets SCU variables
*/
/* stop all comm_exec */
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_RESET;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
/*
STEP 2: configure demodulator
-set env
-set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
*/
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
cmd_scu.parameter_len = 1;
cmd_scu.result_len = 1;
cmd_scu.parameter = &set_env_parameters;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
cmd_scu.parameter_len = 2;
cmd_scu.result_len = 1;
cmd_scu.parameter = set_param_parameters;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* set symbol rate */
rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* STEP 3: enable the system in a mode where the ADC provides valid signal
setup constellation independent registers */
/* from qam_cmd.py script (qam_driver_b) */
/* TODO: remove re-writes of HW reset values */
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
rc = set_frequency(demod, channel, tuner_freq_offset);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
if (op & QAM_SET_OP_ALL) {
if (!ext_attr->has_lna) {
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* scu temporary shut down agc */
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
if (ext_attr->standard == DRX_STANDARD_ITU_B) {
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
} else {
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM16:
case DRX_CONSTELLATION_QAM64:
case DRX_CONSTELLATION_QAM256:
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
break;
case DRX_CONSTELLATION_QAM32:
case DRX_CONSTELLATION_QAM128:
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EIO;
} /* switch */
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /*! reset default val ! */
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* No more resets of the IQM, current standard correctly set =>
now AGCs can be configured. */
/* turn on IQMAF. It has to be in front of setAgc**() */
rc = set_iqm_af(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = adc_synchronization(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = init_agc(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
of only the gain */
struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
if (ext_attr->standard == DRX_STANDARD_ITU_A) {
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM64:
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_QAM256:
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EIO;
}
} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* SETP 4: constellation specific setup */
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM16:
rc = set_qam16(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_QAM32:
rc = set_qam32(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_QAM64:
rc = set_qam64(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_QAM128:
rc = set_qam128(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_QAM256:
rc = set_qam256(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
return -EIO;
} /* switch */
}
if ((op & QAM_SET_OP_ALL)) {
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Mpeg output has to be in front of FEC active */
rc = set_mpegtei_handling(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = bit_reverse_mpeg_output(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_mpeg_start_width(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO: move to set_standard after hardware reset value problem is solved */
/* Configure initial MPEG output */
struct drx_cfg_mpeg_output cfg_mpeg_output;
memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
cfg_mpeg_output.enable_mpeg_output = true;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
}
if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_START;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxj_data *ext_attr = demod->my_ext_attr;
int rc;
u32 iqm_fs_rate_ofs = 0;
u32 iqm_fs_rate_lo = 0;
u16 qam_ctl_ena = 0;
u16 data = 0;
u16 equ_mode = 0;
u16 fsm_state = 0;
int i = 0;
int ofsofs = 0;
/* Silence the controlling of lc, equ, and the acquisition state machine */
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* freeze the frequency control loop */
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
iqm_fs_rate_ofs -= 2 * ofsofs;
/* freeze dq/fq updating */
rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
data = (data & 0xfff9);
rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* lc_cp / _ci / _ca */
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* flip the spec */
rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
/* freeze dq/fq updating */
rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
equ_mode = data;
data = (data & 0xfff9);
rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
for (i = 0; i < 28; i++) {
rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
for (i = 0; i < 24; i++) {
rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
data = equ_mode;
rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
i = 0;
while ((fsm_state != 4) && (i++ < 100)) {
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
#define NO_LOCK 0x0
#define DEMOD_LOCKED 0x1
#define SYNC_FLIPPED 0x2
#define SPEC_MIRRORED 0x4
/*
* \fn int qam64auto ()
* \brief auto do sync pattern switching and mirroring.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \param tuner_freq_offset: tuner frequency offset.
* \param lock_status: pointer to lock status.
* \return int.
*/
static int
qam64auto(struct drx_demod_instance *demod,
struct drx_channel *channel,
s32 tuner_freq_offset, enum drx_lock_status *lock_status)
{
struct drxj_data *ext_attr = demod->my_ext_attr;
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drx39xxj_state *state = dev_addr->user_data;
struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
int rc;
u32 lck_state = NO_LOCK;
u32 start_time = 0;
u32 d_locked_time = 0;
u32 timeout_ofs = 0;
u16 data = 0;
/* external attributes for storing acquired channel constellation */
*lock_status = DRX_NOT_LOCKED;
start_time = jiffies_to_msecs(jiffies);
lck_state = NO_LOCK;
do {
rc = ctrl_lock_status(demod, lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch (lck_state) {
case NO_LOCK:
if (*lock_status == DRXJ_DEMOD_LOCK) {
rc = ctrl_get_qam_sig_quality(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (p->cnr.stat[0].svalue > 20800) {
lck_state = DEMOD_LOCKED;
/* some delay to see if fec_lock possible TODO find the right value */
timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */
d_locked_time = jiffies_to_msecs(jiffies);
}
}
break;
case DEMOD_LOCKED:
if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
((jiffies_to_msecs(jiffies) - d_locked_time) >
DRXJ_QAM_FEC_LOCK_WAITTIME)) {
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
lck_state = SYNC_FLIPPED;
msleep(10);
}
break;
case SYNC_FLIPPED:
if (*lock_status == DRXJ_DEMOD_LOCK) {
if (channel->mirror == DRX_MIRROR_AUTO) {
/* flip sync pattern back */
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* flip spectrum */
ext_attr->mirror = DRX_MIRROR_YES;
rc = qam_flip_spec(demod, channel);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
lck_state = SPEC_MIRRORED;
/* reset timer TODO: still need 500ms? */
start_time = d_locked_time =
jiffies_to_msecs(jiffies);
timeout_ofs = 0;
} else { /* no need to wait lock */
start_time =
jiffies_to_msecs(jiffies) -
DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
}
}
break;
case SPEC_MIRRORED:
if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
((jiffies_to_msecs(jiffies) - d_locked_time) >
DRXJ_QAM_FEC_LOCK_WAITTIME)) {
rc = ctrl_get_qam_sig_quality(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (p->cnr.stat[0].svalue > 20800) {
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no need to wait lock */
start_time =
jiffies_to_msecs(jiffies) -
DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
}
}
break;
default:
break;
}
msleep(10);
} while
((*lock_status != DRX_LOCKED) &&
(*lock_status != DRX_NEVER_LOCK) &&
((jiffies_to_msecs(jiffies) - start_time) <
(DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
);
/* Returning control to application ... */
return 0;
rw_error:
return rc;
}
/*
* \fn int qam256auto ()
* \brief auto do sync pattern switching and mirroring.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \param tuner_freq_offset: tuner frequency offset.
* \param lock_status: pointer to lock status.
* \return int.
*/
static int
qam256auto(struct drx_demod_instance *demod,
struct drx_channel *channel,
s32 tuner_freq_offset, enum drx_lock_status *lock_status)
{
struct drxj_data *ext_attr = demod->my_ext_attr;
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drx39xxj_state *state = dev_addr->user_data;
struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
int rc;
u32 lck_state = NO_LOCK;
u32 start_time = 0;
u32 d_locked_time = 0;
u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
/* external attributes for storing acquired channel constellation */
*lock_status = DRX_NOT_LOCKED;
start_time = jiffies_to_msecs(jiffies);
lck_state = NO_LOCK;
do {
rc = ctrl_lock_status(demod, lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
switch (lck_state) {
case NO_LOCK:
if (*lock_status == DRXJ_DEMOD_LOCK) {
rc = ctrl_get_qam_sig_quality(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (p->cnr.stat[0].svalue > 26800) {
lck_state = DEMOD_LOCKED;
timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */
d_locked_time = jiffies_to_msecs(jiffies);
}
}
break;
case DEMOD_LOCKED:
if (*lock_status == DRXJ_DEMOD_LOCK) {
if ((channel->mirror == DRX_MIRROR_AUTO) &&
((jiffies_to_msecs(jiffies) - d_locked_time) >
DRXJ_QAM_FEC_LOCK_WAITTIME)) {
ext_attr->mirror = DRX_MIRROR_YES;
rc = qam_flip_spec(demod, channel);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
lck_state = SPEC_MIRRORED;
/* reset timer TODO: still need 300ms? */
start_time = jiffies_to_msecs(jiffies);
timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
}
}
break;
case SPEC_MIRRORED:
break;
default:
break;
}
msleep(10);
} while
((*lock_status < DRX_LOCKED) &&
(*lock_status != DRX_NEVER_LOCK) &&
((jiffies_to_msecs(jiffies) - start_time) <
(DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
return 0;
rw_error:
return rc;
}
/*
* \fn int set_qam_channel ()
* \brief Set QAM channel according to the requested constellation.
* \param demod: instance of demod.
* \param channel: pointer to channel data.
* \return int.
*/
static int
set_qam_channel(struct drx_demod_instance *demod,
struct drx_channel *channel, s32 tuner_freq_offset)
{
struct drxj_data *ext_attr = NULL;
int rc;
enum drx_lock_status lock_status = DRX_NOT_LOCKED;
bool auto_flag = false;
/* external attributes for storing acquired channel constellation */
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* set QAM channel constellation */
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM16:
case DRX_CONSTELLATION_QAM32:
case DRX_CONSTELLATION_QAM128:
return -EINVAL;
case DRX_CONSTELLATION_QAM64:
case DRX_CONSTELLATION_QAM256:
if (ext_attr->standard != DRX_STANDARD_ITU_B)
return -EINVAL;
ext_attr->constellation = channel->constellation;
if (channel->mirror == DRX_MIRROR_AUTO)
ext_attr->mirror = DRX_MIRROR_NO;
else
ext_attr->mirror = channel->mirror;
rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (channel->constellation == DRX_CONSTELLATION_QAM64)
rc = qam64auto(demod, channel, tuner_freq_offset,
&lock_status);
else
rc = qam256auto(demod, channel, tuner_freq_offset,
&lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_CONSTELLATION_AUTO: /* for channel scan */
if (ext_attr->standard == DRX_STANDARD_ITU_B) {
u16 qam_ctl_ena = 0;
auto_flag = true;
/* try to lock default QAM constellation: QAM256 */
channel->constellation = DRX_CONSTELLATION_QAM256;
ext_attr->constellation = DRX_CONSTELLATION_QAM256;
if (channel->mirror == DRX_MIRROR_AUTO)
ext_attr->mirror = DRX_MIRROR_NO;
else
ext_attr->mirror = channel->mirror;
rc = set_qam(demod, channel, tuner_freq_offset,
QAM_SET_OP_ALL);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = qam256auto(demod, channel, tuner_freq_offset,
&lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (lock_status >= DRX_LOCKED) {
channel->constellation = DRX_CONSTELLATION_AUTO;
break;
}
/* QAM254 not locked. Try QAM64 constellation */
channel->constellation = DRX_CONSTELLATION_QAM64;
ext_attr->constellation = DRX_CONSTELLATION_QAM64;
if (channel->mirror == DRX_MIRROR_AUTO)
ext_attr->mirror = DRX_MIRROR_NO;
else
ext_attr->mirror = channel->mirror;
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
&qam_ctl_ena, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_FSM_STATE_TGT__A,
0x2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* force to rate hunting */
rc = set_qam(demod, channel, tuner_freq_offset,
QAM_SET_OP_CONSTELLATION);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
qam_ctl_ena, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = qam64auto(demod, channel, tuner_freq_offset,
&lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
channel->constellation = DRX_CONSTELLATION_AUTO;
} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
u16 qam_ctl_ena = 0;
channel->constellation = DRX_CONSTELLATION_QAM64;
ext_attr->constellation = DRX_CONSTELLATION_QAM64;
auto_flag = true;
if (channel->mirror == DRX_MIRROR_AUTO)
ext_attr->mirror = DRX_MIRROR_NO;
else
ext_attr->mirror = channel->mirror;
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
&qam_ctl_ena, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_FSM_STATE_TGT__A,
0x2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* force to rate hunting */
rc = set_qam(demod, channel, tuner_freq_offset,
QAM_SET_OP_CONSTELLATION);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
SCU_RAM_QAM_CTL_ENA__A,
qam_ctl_ena, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = qam64auto(demod, channel, tuner_freq_offset,
&lock_status);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
channel->constellation = DRX_CONSTELLATION_AUTO;
} else {
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
rw_error:
/* restore starting value */
if (auto_flag)
channel->constellation = DRX_CONSTELLATION_AUTO;
return rc;
}
/*============================================================================*/
/*
* \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
* \brief Get RS error count in QAM mode (used for post RS BER calculation)
* \return Error code
*
* precondition: measurement period & measurement prescale must be set
*
*/
static int
get_qamrs_err_count(struct i2c_device_addr *dev_addr,
struct drxjrs_errors *rs_errors)
{
int rc;
u16 nr_bit_errors = 0,
nr_symbol_errors = 0,
nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
/* check arguments */
if (dev_addr == NULL)
return -EINVAL;
/* all reported errors are received in the */
/* most recently finished measurement period */
/* no of pre RS bit errors */
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no of symbol errors */
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no of packet errors */
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no of failures to decode */
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no of post RS bit erros */
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* TODO: NOTE */
/* These register values are fetched in non-atomic fashion */
/* It is possible that the read values contain unrelated information */
rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
rs_errors->nr_snc_par_fail_count =
nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int get_sig_strength()
* \brief Retrieve signal strength for VSB and QAM.
* \param demod Pointer to demod instance
* \param u16-t Pointer to signal strength data; range 0, .. , 100.
* \return int.
* \retval 0 sig_strength contains valid data.
* \retval -EINVAL sig_strength is NULL.
* \retval -EIO Erroneous data, sig_strength contains invalid data.
*/
#define DRXJ_AGC_TOP 0x2800
#define DRXJ_AGC_SNS 0x1600
#define DRXJ_RFAGC_MAX 0x3fff
#define DRXJ_RFAGC_MIN 0x800
static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
u16 rf_gain = 0;
u16 if_gain = 0;
u16 if_agc_sns = 0;
u16 if_agc_top = 0;
u16 rf_agc_max = 0;
u16 rf_agc_min = 0;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if_gain &= IQM_AF_AGC_IF__M;
rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rf_gain &= IQM_AF_AGC_RF__M;
if_agc_sns = DRXJ_AGC_SNS;
if_agc_top = DRXJ_AGC_TOP;
rf_agc_max = DRXJ_RFAGC_MAX;
rf_agc_min = DRXJ_RFAGC_MIN;
if (if_gain > if_agc_top) {
if (rf_gain > rf_agc_max)
*sig_strength = 100;
else if (rf_gain > rf_agc_min) {
if (rf_agc_max == rf_agc_min) {
pr_err("error: rf_agc_max == rf_agc_min\n");
return -EIO;
}
*sig_strength =
75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
rf_agc_min);
} else
*sig_strength = 75;
} else if (if_gain > if_agc_sns) {
if (if_agc_top == if_agc_sns) {
pr_err("error: if_agc_top == if_agc_sns\n");
return -EIO;
}
*sig_strength =
20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
} else {
if (!if_agc_sns) {
pr_err("error: if_agc_sns is zero!\n");
return -EIO;
}
*sig_strength = (20 * if_gain / if_agc_sns);
}
if (*sig_strength <= 7)
*sig_strength = 0;
return 0;
rw_error:
return rc;
}
/*
* \fn int ctrl_get_qam_sig_quality()
* \brief Retrieve QAM signal quality from device.
* \param devmod Pointer to demodulator instance.
* \param sig_quality Pointer to signal quality data.
* \return int.
* \retval 0 sig_quality contains valid data.
* \retval -EINVAL sig_quality is NULL.
* \retval -EIO Erroneous data, sig_quality contains invalid data.
* Pre-condition: Device must be started and in lock.
*/
static int
ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxj_data *ext_attr = demod->my_ext_attr;
struct drx39xxj_state *state = dev_addr->user_data;
struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
enum drx_modulation constellation = ext_attr->constellation;
int rc;
u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */
u32 pkt_errs = 0; /* no of packet errors in RS */
u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */
u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */
u16 fec_oc_period = 0; /* SNC sync failure measurement period */
u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
u16 fec_rs_period = 0; /* Value for corresponding I2C register */
/* calculation constants */
u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */
u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */
/* intermediate results */
u32 e = 0; /* exponent value used for QAM BER/SER */
u32 m = 0; /* mantisa value used for QAM BER/SER */
u32 ber_cnt = 0; /* BER count */
/* signal quality info */
u32 qam_sl_mer = 0; /* QAM MER */
u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */
u32 qam_vd_ser = 0; /* ViterbiDecoder SER */
u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
u16 qam_vd_period = 0; /* Viterbi Measurement period */
u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
/* read the physical registers */
/* Get the RS error data */
rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* get the register value needed for MER */
rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* get the register value needed for post RS BER */
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* get constants needed for signal quality calculation */
fec_rs_period = ext_attr->fec_rs_period;
fec_rs_prescale = ext_attr->fec_rs_prescale;
rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
qam_vd_period = ext_attr->qam_vd_period;
qam_vd_prescale = ext_attr->qam_vd_prescale;
vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
/* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
switch (constellation) {
case DRX_CONSTELLATION_QAM16:
qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
break;
case DRX_CONSTELLATION_QAM32:
qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
break;
case DRX_CONSTELLATION_QAM64:
qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
break;
case DRX_CONSTELLATION_QAM128:
qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
break;
case DRX_CONSTELLATION_QAM256:
qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
break;
default:
rc = -EIO;
goto rw_error;
}
/* ------------------------------ */
/* MER Calculation */
/* ------------------------------ */
/* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
/* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
if (qam_sl_err_power == 0)
qam_sl_mer = 0;
else
qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
/* ----------------------------------------- */
/* Pre Viterbi Symbol Error Rate Calculation */
/* ----------------------------------------- */
/* pre viterbi SER is good if it is below 0.025 */
/* get the register value */
/* no of quadrature symbol errors */
rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Extract the Exponent and the Mantisa */
/* of number of quadrature symbol errors */
e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
QAM_VD_NR_QSYM_ERRORS_EXP__B;
m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
if ((m << e) >> 3 > 549752)
qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
else
qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
/* --------------------------------------- */
/* pre and post RedSolomon BER Calculation */
/* --------------------------------------- */
/* pre RS BER is good if it is below 3.5e-4 */
/* get the register values */
pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
/* Extract the Exponent and the Mantisa of the */
/* pre Reed-Solomon bit error count */
e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
FEC_RS_NR_BIT_ERRORS_EXP__B;
m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
ber_cnt = m << e;
/*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
else
qam_pre_rs_ber = ber_cnt;
/* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
/* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
/*
=> c = (1000000*100*11.17)/1504 =
post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
(100 * FEC_OC_SNC_FAIL_PERIOD__A)
*100 and /100 is for more precision.
=> (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
Precision errors still possible.
*/
if (!fec_oc_period) {
qam_post_rs_ber = 0xFFFFFFFF;
} else {
e = post_bit_err_rs * 742686;
m = fec_oc_period * 100;
qam_post_rs_ber = e / m;
}
/* fill signal quality data structure */
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
if (ext_attr->standard == DRX_STANDARD_ITU_B) {
p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
} else {
p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
}
p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
p->block_error.stat[0].uvalue += pkt_errs;
#ifdef DRXJ_SIGNAL_ACCUM_ERR
rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
#endif
return 0;
rw_error:
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return rc;
}
#endif /* #ifndef DRXJ_VSB_ONLY */
/*============================================================================*/
/*== END QAM DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== ATV DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*============================================================================*/
/*
Implementation notes.
NTSC/FM AGCs
Four AGCs are used for NTSC:
(1) RF (used to attenuate the input signal in case of to much power)
(2) IF (used to attenuate the input signal in case of to much power)
(3) Video AGC (used to amplify the output signal in case input to low)
(4) SIF AGC (used to amplify the output signal in case input to low)
Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
that the coupling between Video AGC and the RF and IF AGCs also works in
favor of the SIF AGC.
Three AGCs are used for FM:
(1) RF (used to attenuate the input signal in case of to much power)
(2) IF (used to attenuate the input signal in case of to much power)
(3) SIF AGC (used to amplify the output signal in case input to low)
The SIF AGC is now coupled to the RF/IF AGCs.
The SIF AGC is needed for both SIF output and the internal SIF signal to
the AUD block.
RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
the ATV block. The AGC control algorithms are all implemented in
microcode.
ATV SETTINGS
(Shadow settings will not be used for now, they will be implemented
later on because of the schedule)
Several HW/SCU "settings" can be used for ATV. The standard selection
will reset most of these settings. To avoid that the end user application
has to perform these settings each time the ATV or FM standards is
selected the driver will shadow these settings. This enables the end user
to perform the settings only once after a drx_open(). The driver must
write the shadow settings to HW/SCU in case:
( setstandard FM/ATV) ||
( settings have changed && FM/ATV standard is active)
The shadow settings will be stored in the device specific data container.
A set of flags will be defined to flag changes in shadow settings.
A routine will be implemented to write all changed shadow settings to
HW/SCU.
The "settings" will consist of: AGC settings, filter settings etc.
Disadvantage of use of shadow settings:
Direct changes in HW/SCU registers will not be reflected in the
shadow settings and these changes will be overwritten during a next
update. This can happen during evaluation. This will not be a problem
for normal customer usage.
*/
/* -------------------------------------------------------------------------- */
/*
* \fn int power_down_atv ()
* \brief Power down ATV.
* \param demod instance of demodulator
* \param standard either NTSC or FM (sub strandard for ATV )
* \return int.
*
* Stops and thus resets ATV and IQM block
* SIF and CVBS ADC are powered down
* Calls audio power down
*/
static int
power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxjscu_cmd cmd_scu = { /* command */ 0,
/* parameter_len */ 0,
/* result_len */ 0,
/* *parameter */ NULL,
/* *result */ NULL
};
int rc;
u16 cmd_result = 0;
/* ATV NTSC */
/* Stop ATV SCU (will reset ATV and IQM hardware */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
SCU_RAM_COMMAND_CMD_DEMOD_STOP;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Disable ATV outputs (ATV reset enables CVBS, undo this) */
rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (primary) {
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_iqm_af(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} else {
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = power_down_aud(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \brief Power up AUD.
* \param demod instance of demodulator
* \return int.
*
*/
static int power_down_aud(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
int rc;
dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->aud_data.audio_is_active = false;
return 0;
rw_error:
return rc;
}
/*
* \fn int set_orx_nsu_aox()
* \brief Configure OrxNsuAox for OOB
* \param demod instance of demodulator.
* \param active
* \return int.
*/
static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
u16 data = 0;
/* Configure NSU_AOX */
rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (!active)
data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
else
data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}
/*
* \fn int ctrl_set_oob()
* \brief Set OOB channel to be used.
* \param demod instance of demodulator
* \param oob_param OOB parameters for channel setting.
* \frequency should be in KHz
* \return int.
*
* Accepts only. Returns error otherwise.
* Demapper value is written after scu_command START
* because START command causes COMM_EXEC transition
* from 0 to 1 which causes all registers to be
* overwritten with initial value
*
*/
/* Nyquist filter impulse response */
#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
/* Coefficients for the nyquist filter (total: 27 taps) */
#define NYQFILTERLEN 27
static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
{
int rc;
s32 freq = 0; /* KHz */
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
u16 i = 0;
bool mirror_freq_spect_oob = false;
u16 trk_filter_value = 0;
struct drxjscu_cmd scu_cmd;
u16 set_param_parameters[3];
u16 cmd_result[2] = { 0, 0 };
s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */
IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */
IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */
IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
};
u8 mode_val[4] = { 2, 2, 0, 1 };
u8 pfi_coeffs[4][6] = {
{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
};
u16 mode_index;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
/* Check parameters */
if (oob_param == NULL) {
/* power off oob module */
scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
| SCU_RAM_COMMAND_CMD_DEMOD_STOP;
scu_cmd.parameter_len = 0;
scu_cmd.result_len = 1;
scu_cmd.result = cmd_result;
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_orx_nsu_aox(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->oob_power_on = false;
return 0;
}
freq = oob_param->frequency;
if ((freq < 70000) || (freq > 130000))
return -EIO;
freq = (freq - 50000) / 50;
{
u16 index = 0;
u16 remainder = 0;
u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
index = (u16) ((freq - 400) / 200);
remainder = (u16) ((freq - 400) % 200);
trk_filter_value =
trk_filtercfg[index] - (trk_filtercfg[index] -
trk_filtercfg[index +
1]) / 10 * remainder /
20;
}
/********/
/* Stop */
/********/
rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
| SCU_RAM_COMMAND_CMD_DEMOD_STOP;
scu_cmd.parameter_len = 0;
scu_cmd.result_len = 1;
scu_cmd.result = cmd_result;
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/********/
/* Reset */
/********/
scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
| SCU_RAM_COMMAND_CMD_DEMOD_RESET;
scu_cmd.parameter_len = 0;
scu_cmd.result_len = 1;
scu_cmd.result = cmd_result;
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/**********/
/* SET_ENV */
/**********/
/* set frequency, spectrum inversion and data rate */
scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
scu_cmd.parameter_len = 3;
/* 1-data rate;2-frequency */
switch (oob_param->standard) {
case DRX_OOB_MODE_A:
if (
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &&
/* and tuner is not mirroring the signal */
(!mirror_freq_spect_oob)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &&
/* and tuner is mirroring the signal */
(mirror_freq_spect_oob))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
else
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
break;
case DRX_OOB_MODE_B_GRADE_A:
if (
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &&
/* and tuner is not mirroring the signal */
(!mirror_freq_spect_oob)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &&
/* and tuner is mirroring the signal */
(mirror_freq_spect_oob))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
else
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
break;
case DRX_OOB_MODE_B_GRADE_B:
default:
if (
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &&
/* and tuner is not mirroring the signal */
(!mirror_freq_spect_oob)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &&
/* and tuner is mirroring the signal */
(mirror_freq_spect_oob))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
else
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
break;
}
set_param_parameters[1] = (u16) (freq & 0xFFFF);
set_param_parameters[2] = trk_filter_value;
scu_cmd.parameter = set_param_parameters;
scu_cmd.result_len = 1;
scu_cmd.result = cmd_result;
mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* Write magic word to enable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* Write magic word to disable pdr reg write */
rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* ddc */
rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* nsu */
rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* initialization for target mode */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Reset bits for timing and freq. recovery */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* PRE-Filter coefficients (PFI) */
rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* NYQUIST-Filter coefficients (NYQ) */
for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/********/
/* Start */
/********/
scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
| SCU_RAM_COMMAND_CMD_DEMOD_START;
scu_cmd.parameter_len = 0;
scu_cmd.result_len = 1;
scu_cmd.result = cmd_result;
rc = scu_command(dev_addr, &scu_cmd);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_orx_nsu_aox(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->oob_power_on = true;
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== END OOB DATAPATH FUNCTIONS ==*/
/*============================================================================*/
/*=============================================================================
===== MC command related functions ==========================================
===========================================================================*/
/*=============================================================================
===== ctrl_set_channel() ==========================================================
===========================================================================*/
/*
* \fn int ctrl_set_channel()
* \brief Select a new transmission channel.
* \param demod instance of demod.
* \param channel Pointer to channel data.
* \return int.
*
* In case the tuner module is not used and in case of NTSC/FM the pogrammer
* must tune the tuner to the centre frequency of the NTSC/FM channel.
*
*/
static int
ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
{
int rc;
s32 tuner_freq_offset = 0;
struct drxj_data *ext_attr = NULL;
struct i2c_device_addr *dev_addr = NULL;
enum drx_standard standard = DRX_STANDARD_UNKNOWN;
#ifndef DRXJ_VSB_ONLY
u32 min_symbol_rate = 0;
u32 max_symbol_rate = 0;
int bandwidth_temp = 0;
int bandwidth = 0;
#endif
/*== check arguments ======================================================*/
if ((demod == NULL) || (channel == NULL))
return -EINVAL;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
standard = ext_attr->standard;
/* check valid standards */
switch (standard) {
case DRX_STANDARD_8VSB:
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
#endif /* DRXJ_VSB_ONLY */
break;
case DRX_STANDARD_UNKNOWN:
default:
return -EINVAL;
}
/* check bandwidth QAM annex B, NTSC and 8VSB */
if ((standard == DRX_STANDARD_ITU_B) ||
(standard == DRX_STANDARD_8VSB) ||
(standard == DRX_STANDARD_NTSC)) {
switch (channel->bandwidth) {
case DRX_BANDWIDTH_6MHZ:
case DRX_BANDWIDTH_UNKNOWN:
channel->bandwidth = DRX_BANDWIDTH_6MHZ;
break;
case DRX_BANDWIDTH_8MHZ:
case DRX_BANDWIDTH_7MHZ:
default:
return -EINVAL;
}
}
/* For QAM annex A and annex C:
-check symbolrate and constellation
-derive bandwidth from symbolrate (input bandwidth is ignored)
*/
#ifndef DRXJ_VSB_ONLY
if ((standard == DRX_STANDARD_ITU_A) ||
(standard == DRX_STANDARD_ITU_C)) {
struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
int bw_rolloff_factor = 0;
bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
/* config SMA_TX pin to SAW switch mode */
rc = ctrl_set_uio_cfg(demod, &uio_cfg);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (channel->symbolrate < min_symbol_rate ||
channel->symbolrate > max_symbol_rate) {
return -EINVAL;
}
switch (channel->constellation) {
case DRX_CONSTELLATION_QAM16:
case DRX_CONSTELLATION_QAM32:
case DRX_CONSTELLATION_QAM64:
case DRX_CONSTELLATION_QAM128:
case DRX_CONSTELLATION_QAM256:
bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
bandwidth = bandwidth_temp / 100;
if ((bandwidth_temp % 100) >= 50)
bandwidth++;
if (bandwidth <= 6100000) {
channel->bandwidth = DRX_BANDWIDTH_6MHZ;
} else if ((bandwidth > 6100000)
&& (bandwidth <= 7100000)) {
channel->bandwidth = DRX_BANDWIDTH_7MHZ;
} else if (bandwidth > 7100000) {
channel->bandwidth = DRX_BANDWIDTH_8MHZ;
}
break;
default:
return -EINVAL;
}
}
/* For QAM annex B:
-check constellation
*/
if (standard == DRX_STANDARD_ITU_B) {
switch (channel->constellation) {
case DRX_CONSTELLATION_AUTO:
case DRX_CONSTELLATION_QAM256:
case DRX_CONSTELLATION_QAM64:
break;
default:
return -EINVAL;
}
switch (channel->interleavemode) {
case DRX_INTERLEAVEMODE_I128_J1:
case DRX_INTERLEAVEMODE_I128_J1_V2:
case DRX_INTERLEAVEMODE_I128_J2:
case DRX_INTERLEAVEMODE_I64_J2:
case DRX_INTERLEAVEMODE_I128_J3:
case DRX_INTERLEAVEMODE_I32_J4:
case DRX_INTERLEAVEMODE_I128_J4:
case DRX_INTERLEAVEMODE_I16_J8:
case DRX_INTERLEAVEMODE_I128_J5:
case DRX_INTERLEAVEMODE_I8_J16:
case DRX_INTERLEAVEMODE_I128_J6:
case DRX_INTERLEAVEMODE_I128_J7:
case DRX_INTERLEAVEMODE_I128_J8:
case DRX_INTERLEAVEMODE_I12_J17:
case DRX_INTERLEAVEMODE_I5_J4:
case DRX_INTERLEAVEMODE_B52_M240:
case DRX_INTERLEAVEMODE_B52_M720:
case DRX_INTERLEAVEMODE_UNKNOWN:
case DRX_INTERLEAVEMODE_AUTO:
break;
default:
return -EINVAL;
}
}
if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
/* SAW SW, user UIO is used for switchable SAW */
struct drxuio_data uio1 = { DRX_UIO1, false };
switch (channel->bandwidth) {
case DRX_BANDWIDTH_8MHZ:
uio1.value = true;
break;
case DRX_BANDWIDTH_7MHZ:
uio1.value = false;
break;
case DRX_BANDWIDTH_6MHZ:
uio1.value = false;
break;
case DRX_BANDWIDTH_UNKNOWN:
default:
return -EINVAL;
}
rc = ctrl_uio_write(demod, &uio1);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
#endif /* DRXJ_VSB_ONLY */
rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
tuner_freq_offset = 0;
/*== Setup demod for specific standard ====================================*/
switch (standard) {
case DRX_STANDARD_8VSB:
if (channel->mirror == DRX_MIRROR_AUTO)
ext_attr->mirror = DRX_MIRROR_NO;
else
ext_attr->mirror = channel->mirror;
rc = set_vsb(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_frequency(demod, channel, tuner_freq_offset);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = set_qam_channel(demod, channel, tuner_freq_offset);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
#endif
case DRX_STANDARD_UNKNOWN:
default:
return -EIO;
}
/* flag the packet error counter reset */
ext_attr->reset_pkt_err_acc = true;
return 0;
rw_error:
return rc;
}
/*=============================================================================
===== SigQuality() ==========================================================
===========================================================================*/
/*
* \fn int ctrl_sig_quality()
* \brief Retrieve signal quality form device.
* \param devmod Pointer to demodulator instance.
* \param sig_quality Pointer to signal quality data.
* \return int.
* \retval 0 sig_quality contains valid data.
* \retval -EINVAL sig_quality is NULL.
* \retval -EIO Erroneous data, sig_quality contains invalid data.
*/
static int
ctrl_sig_quality(struct drx_demod_instance *demod,
enum drx_lock_status lock_status)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
struct drxj_data *ext_attr = demod->my_ext_attr;
struct drx39xxj_state *state = dev_addr->user_data;
struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
enum drx_standard standard = ext_attr->standard;
int rc;
u32 ber, cnt, err, pkt;
u16 mer, strength = 0;
rc = get_sig_strength(demod, &strength);
if (rc < 0) {
pr_err("error getting signal strength %d\n", rc);
p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->strength.stat[0].uvalue = 65535UL * strength/ 100;
}
switch (standard) {
case DRX_STANDARD_8VSB:
#ifdef DRXJ_SIGNAL_ACCUM_ERR
rc = get_acc_pkt_err(demod, &pkt);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
#endif
if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
if (rc != 0) {
pr_err("error %d getting UCB\n", rc);
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
p->block_error.stat[0].scale = FE_SCALE_COUNTER;
p->block_error.stat[0].uvalue += err;
p->block_count.stat[0].scale = FE_SCALE_COUNTER;
p->block_count.stat[0].uvalue += pkt;
}
/* PostViterbi is compute in steps of 10^(-6) */
rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
if (rc != 0) {
pr_err("error %d getting pre-ber\n", rc);
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_error.stat[0].uvalue += ber;
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->pre_bit_count.stat[0].uvalue += cnt;
}
rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
if (rc != 0) {
pr_err("error %d getting post-ber\n", rc);
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_error.stat[0].uvalue += ber;
p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
p->post_bit_count.stat[0].uvalue += cnt;
}
rc = get_vsbmer(dev_addr, &mer);
if (rc != 0) {
pr_err("error %d getting MER\n", rc);
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
} else {
p->cnr.stat[0].svalue = mer * 100;
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
}
}
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = ctrl_get_qam_sig_quality(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
#endif
default:
return -EIO;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int ctrl_lock_status()
* \brief Retrieve lock status .
* \param dev_addr Pointer to demodulator device address.
* \param lock_stat Pointer to lock status structure.
* \return int.
*
*/
static int
ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
{
enum drx_standard standard = DRX_STANDARD_UNKNOWN;
struct drxj_data *ext_attr = NULL;
struct i2c_device_addr *dev_addr = NULL;
struct drxjscu_cmd cmd_scu = { /* command */ 0,
/* parameter_len */ 0,
/* result_len */ 0,
/* *parameter */ NULL,
/* *result */ NULL
};
int rc;
u16 cmd_result[2] = { 0, 0 };
u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
/* check arguments */
if ((demod == NULL) || (lock_stat == NULL))
return -EINVAL;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
standard = ext_attr->standard;
*lock_stat = DRX_NOT_LOCKED;
/* define the SCU command code */
switch (standard) {
case DRX_STANDARD_8VSB:
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
demod_lock |= 0x6;
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
break;
#endif
case DRX_STANDARD_UNKNOWN:
default:
return -EIO;
}
/* define the SCU command parameters and execute the command */
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 2;
cmd_scu.parameter = NULL;
cmd_scu.result = cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* set the lock status */
if (cmd_scu.result[1] < demod_lock) {
/* 0x0000 NOT LOCKED */
*lock_stat = DRX_NOT_LOCKED;
} else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
*lock_stat = DRXJ_DEMOD_LOCK;
} else if (cmd_scu.result[1] <
SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
/* 0x8000 DEMOD + FEC LOCKED (system lock) */
*lock_stat = DRX_LOCKED;
} else {
/* 0xC000 NEVER LOCKED */
/* (system will never be able to lock to the signal) */
*lock_stat = DRX_NEVER_LOCK;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int ctrl_set_standard()
* \brief Set modulation standard to be used.
* \param standard Modulation standard.
* \return int.
*
* Setup stuff for the desired demodulation standard.
* Disable and power down the previous selected demodulation standard
*
*/
static int
ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
{
struct drxj_data *ext_attr = NULL;
int rc;
enum drx_standard prev_standard;
/* check arguments */
if ((standard == NULL) || (demod == NULL))
return -EINVAL;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
prev_standard = ext_attr->standard;
/*
Stop and power down previous standard
*/
switch (prev_standard) {
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = power_down_qam(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
#endif
case DRX_STANDARD_8VSB:
rc = power_down_vsb(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_STANDARD_UNKNOWN:
/* Do nothing */
break;
case DRX_STANDARD_AUTO:
default:
rc = -EINVAL;
goto rw_error;
}
/*
Initialize channel independent registers
Power up new standard
*/
ext_attr->standard = *standard;
switch (*standard) {
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
do {
u16 dummy;
rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
} while (0);
break;
#endif
case DRX_STANDARD_8VSB:
rc = set_vsb_leak_n_gain(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
default:
ext_attr->standard = DRX_STANDARD_UNKNOWN;
return -EINVAL;
}
return 0;
rw_error:
/* Don't know what the standard is now ... try again */
ext_attr->standard = DRX_STANDARD_UNKNOWN;
return rc;
}
/*============================================================================*/
static void drxj_reset_mode(struct drxj_data *ext_attr)
{
/* Initialize default AFE configuration for QAM */
if (ext_attr->has_lna) {
/* IF AGC off, PGA active */
#ifndef DRXJ_VSB_ONLY
ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
ext_attr->qam_pga_cfg = 140 + (11 * 13);
#endif
ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
ext_attr->vsb_pga_cfg = 140 + (11 * 13);
} else {
/* IF AGC on, PGA not active */
#ifndef DRXJ_VSB_ONLY
ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
ext_attr->qam_if_agc_cfg.min_output_level = 0;
ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
ext_attr->qam_if_agc_cfg.speed = 3;
ext_attr->qam_if_agc_cfg.top = 1297;
ext_attr->qam_pga_cfg = 140;
#endif
ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
ext_attr->vsb_if_agc_cfg.min_output_level = 0;
ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
ext_attr->vsb_if_agc_cfg.speed = 3;
ext_attr->vsb_if_agc_cfg.top = 1024;
ext_attr->vsb_pga_cfg = 140;
}
/* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
/* mc has not used them */
#ifndef DRXJ_VSB_ONLY
ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
ext_attr->qam_rf_agc_cfg.min_output_level = 0;
ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
ext_attr->qam_rf_agc_cfg.speed = 3;
ext_attr->qam_rf_agc_cfg.top = 9500;
ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
ext_attr->qam_pre_saw_cfg.reference = 0x07;
ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
#endif
/* Initialize default AFE configuration for VSB */
ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
ext_attr->vsb_rf_agc_cfg.speed = 3;
ext_attr->vsb_rf_agc_cfg.top = 9500;
ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
ext_attr->vsb_pre_saw_cfg.reference = 0x07;
ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
}
/*
* \fn int ctrl_power_mode()
* \brief Set the power mode of the device to the specified power mode
* \param demod Pointer to demodulator instance.
* \param mode Pointer to new power mode.
* \return int.
* \retval 0 Success
* \retval -EIO I2C error or other failure
* \retval -EINVAL Invalid mode argument.
*
*
*/
static int
ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
{
struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
struct drxj_data *ext_attr = (struct drxj_data *) NULL;
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
int rc;
u16 sio_cc_pwd_mode = 0;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
dev_addr = demod->my_i2c_dev_addr;
/* Check arguments */
if (mode == NULL)
return -EINVAL;
/* If already in requested power mode, do nothing */
if (common_attr->current_power_mode == *mode)
return 0;
switch (*mode) {
case DRX_POWER_UP:
case DRXJ_POWER_DOWN_MAIN_PATH:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
break;
case DRXJ_POWER_DOWN_CORE:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
break;
case DRXJ_POWER_DOWN_PLL:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
break;
case DRX_POWER_DOWN:
sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
break;
default:
/* Unknown sleep mode */
return -EINVAL;
}
/* Check if device needs to be powered up */
if ((common_attr->current_power_mode != DRX_POWER_UP)) {
rc = power_up_device(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
if (*mode == DRX_POWER_UP) {
/* Restore analog & pin configuration */
/* Initialize default AFE configuration for VSB */
drxj_reset_mode(ext_attr);
} else {
/* Power down to requested mode */
/* Backup some register settings */
/* Set pins with possible pull-ups connected to them in input mode */
/* Analog power down */
/* ADC power down */
/* Power down device */
/* stop all comm_exec */
/*
Stop and power down previous standard
*/
switch (ext_attr->standard) {
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = power_down_qam(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_STANDARD_8VSB:
rc = power_down_vsb(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_STANDARD_PAL_SECAM_BG:
case DRX_STANDARD_PAL_SECAM_DK:
case DRX_STANDARD_PAL_SECAM_I:
case DRX_STANDARD_PAL_SECAM_L:
case DRX_STANDARD_PAL_SECAM_LP:
case DRX_STANDARD_NTSC:
case DRX_STANDARD_FM:
rc = power_down_atv(demod, ext_attr->standard, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
break;
case DRX_STANDARD_UNKNOWN:
/* Do nothing */
break;
case DRX_STANDARD_AUTO:
default:
return -EIO;
}
ext_attr->standard = DRX_STANDARD_UNKNOWN;
}
if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if ((*mode != DRX_POWER_UP)) {
/* Initialize HI, wakeup key especially before put IC to sleep */
rc = init_hi(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
rc = hi_cfg_command(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
}
common_attr->current_power_mode = *mode;
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*== CTRL Set/Get Config related functions ===================================*/
/*============================================================================*/
/*
* \fn int ctrl_set_cfg_pre_saw()
* \brief Set Pre-saw reference.
* \param demod demod instance
* \param u16 *
* \return int.
*
* Check arguments
* Dispatch handling to standard specific function.
*
*/
static int
ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
int rc;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* check arguments */
if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
) {
return -EINVAL;
}
/* Only if standard is currently active */
if ((ext_attr->standard == pre_saw->standard) ||
(DRXJ_ISQAMSTD(ext_attr->standard) &&
DRXJ_ISQAMSTD(pre_saw->standard)) ||
(DRXJ_ISATVSTD(ext_attr->standard) &&
DRXJ_ISATVSTD(pre_saw->standard))) {
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* Store pre-saw settings */
switch (pre_saw->standard) {
case DRX_STANDARD_8VSB:
ext_attr->vsb_pre_saw_cfg = *pre_saw;
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_pre_saw_cfg = *pre_saw;
break;
#endif
default:
return -EINVAL;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*
* \fn int ctrl_set_cfg_afe_gain()
* \brief Set AFE Gain.
* \param demod demod instance
* \param u16 *
* \return int.
*
* Check arguments
* Dispatch handling to standard specific function.
*
*/
static int
ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
int rc;
u8 gain = 0;
/* check arguments */
if (afe_gain == NULL)
return -EINVAL;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
switch (afe_gain->standard) {
case DRX_STANDARD_8VSB: fallthrough;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
#endif
/* Do nothing */
break;
default:
return -EINVAL;
}
/* TODO PGA gain is also written by microcode (at least by QAM and VSB)
So I (PJ) think interface requires choice between auto, user mode */
if (afe_gain->gain >= 329)
gain = 15;
else if (afe_gain->gain <= 147)
gain = 0;
else
gain = (afe_gain->gain - 140 + 6) / 13;
/* Only if standard is currently active */
if (ext_attr->standard == afe_gain->standard) {
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* Store AFE Gain settings */
switch (afe_gain->standard) {
case DRX_STANDARD_8VSB:
ext_attr->vsb_pga_cfg = gain * 13 + 140;
break;
#ifndef DRXJ_VSB_ONLY
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_pga_cfg = gain * 13 + 140;
break;
#endif
default:
return -EIO;
}
return 0;
rw_error:
return rc;
}
/*============================================================================*/
/*=============================================================================
===== EXPORTED FUNCTIONS ====================================================*/
static int drx_ctrl_u_code(struct drx_demod_instance *demod,
struct drxu_code_info *mc_info,
enum drxu_code_action action);
static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
/*
* \fn drxj_open()
* \brief Open the demod instance, configure device, configure drxdriver
* \return Status_t Return status.
*
* drxj_open() can be called with a NULL ucode image => no ucode upload.
* This means that drxj_open() must NOT contain SCU commands or, in general,
* rely on SCU or AUD ucode to be present.
*
*/
static int drxj_open(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
struct drxj_data *ext_attr = NULL;
struct drx_common_attr *common_attr = NULL;
u32 driver_version = 0;
struct drxu_code_info ucode_info;
struct drx_cfg_mpeg_output cfg_mpeg_output;
int rc;
enum drx_power_mode power_mode = DRX_POWER_UP;
if ((demod == NULL) ||
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
(demod->my_common_attr->is_opened)) {
return -EINVAL;
}
/* Check arguments */
if (demod->my_ext_attr == NULL)
return -EINVAL;
dev_addr = demod->my_i2c_dev_addr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
rc = ctrl_power_mode(demod, &power_mode);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
if (power_mode != DRX_POWER_UP) {
rc = -EINVAL;
pr_err("failed to powerup device\n");
goto rw_error;
}
/* has to be in front of setIqmAf and setOrxNsuAox */
rc = get_device_capabilities(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/*
* Soft reset of sys- and osc-clockdomain
*
* HACK: On windows, it writes a 0x07 here, instead of just 0x03.
* As we didn't load the firmware here yet, we should do the same.
* Btw, this is coherent with DRX-K, where we send reset codes
* for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
*/
rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
msleep(1);
/* TODO first make sure that everything keeps working before enabling this */
/* PowerDownAnalogBlocks() */
rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_iqm_af(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_orx_nsu_aox(demod, false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = init_hi(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* disable mpegoutput pins */
memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
cfg_mpeg_output.enable_mpeg_output = false;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Stop AUD Inform SetAudio it will need to do all setting */
rc = power_down_aud(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Stop SCU */
rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Upload microcode */
if (common_attr->microcode_file != NULL) {
/* Dirty trick to use common ucode upload & verify,
pretend device is already open */
common_attr->is_opened = true;
ucode_info.mc_file = common_attr->microcode_file;
if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
pr_err("Should powerup before loading the firmware.");
rc = -EINVAL;
goto rw_error;
}
rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
if (rc != 0) {
pr_err("error %d while uploading the firmware\n", rc);
goto rw_error;
}
if (common_attr->verify_microcode == true) {
rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
if (rc != 0) {
pr_err("error %d while verifying the firmware\n",
rc);
goto rw_error;
}
}
common_attr->is_opened = false;
}
/* Run SCU for a little while to initialize microcode version numbers */
rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Initialize scan timeout */
common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
common_attr->scan_desired_lock = DRX_LOCKED;
drxj_reset_mode(ext_attr);
ext_attr->standard = DRX_STANDARD_UNKNOWN;
rc = smart_ant_init(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Stamp driver version number in SCU data RAM in BCD code
Done to enable field application engineers to retrieve drxdriver version
via I2C from SCU RAM
*/
driver_version = (VERSION_MAJOR / 100) % 10;
driver_version <<= 4;
driver_version += (VERSION_MAJOR / 10) % 10;
driver_version <<= 4;
driver_version += (VERSION_MAJOR % 10);
driver_version <<= 4;
driver_version += (VERSION_MINOR % 10);
driver_version <<= 4;
driver_version += (VERSION_PATCH / 1000) % 10;
driver_version <<= 4;
driver_version += (VERSION_PATCH / 100) % 10;
driver_version <<= 4;
driver_version += (VERSION_PATCH / 10) % 10;
driver_version <<= 4;
driver_version += (VERSION_PATCH % 10);
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = ctrl_set_oob(demod, NULL);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* refresh the audio data structure with default */
ext_attr->aud_data = drxj_default_aud_data_g;
demod->my_common_attr->is_opened = true;
drxj_set_lna_state(demod, false);
return 0;
rw_error:
common_attr->is_opened = false;
return rc;
}
/*============================================================================*/
/*
* \fn drxj_close()
* \brief Close the demod instance, power down the device
* \return Status_t Return status.
*
*/
static int drxj_close(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
enum drx_power_mode power_mode = DRX_POWER_UP;
if ((demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
(!demod->my_common_attr->is_opened)) {
return -EINVAL;
}
/* power up */
rc = ctrl_power_mode(demod, &power_mode);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
power_mode = DRX_POWER_DOWN;
rc = ctrl_power_mode(demod, &power_mode);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
DRX_ATTR_ISOPENED(demod) = false;
return 0;
rw_error:
DRX_ATTR_ISOPENED(demod) = false;
return rc;
}
/*
* Microcode related functions
*/
/*
* drx_u_code_compute_crc - Compute CRC of block of microcode data.
* @block_data: Pointer to microcode data.
* @nr_words: Size of microcode block (number of 16 bits words).
*
* returns The computed CRC residue.
*/
static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
{
u16 i = 0;
u16 j = 0;
u32 crc_word = 0;
u32 carry = 0;
while (i < nr_words) {
crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
for (j = 0; j < 16; j++) {
crc_word <<= 1;
if (carry != 0)
crc_word ^= 0x80050000UL;
carry = crc_word & 0x80000000UL;
}
i++;
block_data += (sizeof(u16));
}
return (u16)(crc_word >> 16);
}
/*
* drx_check_firmware - checks if the loaded firmware is valid
*
* @demod: demod structure
* @mc_data: pointer to the start of the firmware
* @size: firmware size
*/
static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
unsigned size)
{
struct drxu_code_block_hdr block_hdr;
int i;
unsigned count = 2 * sizeof(u16);
u32 mc_dev_type, mc_version, mc_base_version;
u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
/*
* Scan microcode blocks first for version info
* and firmware check
*/
/* Clear version block */
DRX_ATTR_MCRECORD(demod).aux_type = 0;
DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
DRX_ATTR_MCRECORD(demod).mc_version = 0;
DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
for (i = 0; i < mc_nr_of_blks; i++) {
if (count + 3 * sizeof(u16) + sizeof(u32) > size)
goto eof;
/* Process block header */
block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
count += sizeof(u32);
block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
count += sizeof(u16);
block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
count += sizeof(u16);
block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
count += sizeof(u16);
pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
count, block_hdr.addr, block_hdr.size, block_hdr.flags,
block_hdr.CRC);
if (block_hdr.flags & 0x8) {
u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
u16 auxtype;
if (block_hdr.addr + sizeof(u16) > size)
goto eof;
auxtype = be16_to_cpu(*(__be16 *)(auxblk));
/* Aux block. Check type */
if (DRX_ISMCVERTYPE(auxtype)) {
if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
goto eof;
auxblk += sizeof(u16);
mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
auxblk += sizeof(u32);
mc_version = be32_to_cpu(*(__be32 *)(auxblk));
auxblk += sizeof(u32);
mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
pr_info("Firmware dev %x, ver %x, base ver %x\n",
mc_dev_type, mc_version, mc_base_version);
}
} else if (count + block_hdr.size * sizeof(u16) > size)
goto eof;
count += block_hdr.size * sizeof(u16);
}
return 0;
eof:
pr_err("Firmware is truncated at pos %u/%u\n", count, size);
return -EINVAL;
}
/*
* drx_ctrl_u_code - Handle microcode upload or verify.
* @dev_addr: Address of device.
* @mc_info: Pointer to information about microcode data.
* @action: Either UCODE_UPLOAD or UCODE_VERIFY
*
* This function returns:
* 0:
* - In case of UCODE_UPLOAD: code is successfully uploaded.
* - In case of UCODE_VERIFY: image on device is equal to
* image provided to this control function.
* -EIO:
* - In case of UCODE_UPLOAD: I2C error.
* - In case of UCODE_VERIFY: I2C error or image on device
* is not equal to image provided to this control function.
* -EINVAL:
* - Invalid arguments.
* - Provided image is corrupt
*/
static int drx_ctrl_u_code(struct drx_demod_instance *demod,
struct drxu_code_info *mc_info,
enum drxu_code_action action)
{
struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
int rc;
u16 i = 0;
u16 mc_nr_of_blks = 0;
u16 mc_magic_word = 0;
const u8 *mc_data_init = NULL;
u8 *mc_data = NULL;
unsigned size;
char *mc_file;
/* Check arguments */
if (!mc_info || !mc_info->mc_file)
return -EINVAL;
mc_file = mc_info->mc_file;
if (!demod->firmware) {
const struct firmware *fw = NULL;
rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
if (rc < 0) {
pr_err("Couldn't read firmware %s\n", mc_file);
return rc;
}
demod->firmware = fw;
if (demod->firmware->size < 2 * sizeof(u16)) {
rc = -EINVAL;
pr_err("Firmware is too short!\n");
goto release;
}
pr_info("Firmware %s, size %zu\n",
mc_file, demod->firmware->size);
}
mc_data_init = demod->firmware->data;
size = demod->firmware->size;
mc_data = (void *)mc_data_init;
/* Check data */
mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
mc_data += sizeof(u16);
mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
mc_data += sizeof(u16);
if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
rc = -EINVAL;
pr_err("Firmware magic word doesn't match\n");
goto release;
}
if (action == UCODE_UPLOAD) {
rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
if (rc)
goto release;
pr_info("Uploading firmware %s\n", mc_file);
} else {
pr_info("Verifying if firmware upload was ok.\n");
}
/* Process microcode blocks */
for (i = 0; i < mc_nr_of_blks; i++) {
struct drxu_code_block_hdr block_hdr;
u16 mc_block_nr_bytes = 0;
/* Process block header */
block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
mc_data += sizeof(u32);
block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
mc_data += sizeof(u16);
block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
mc_data += sizeof(u16);
block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
mc_data += sizeof(u16);
pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
(mc_data - mc_data_init), block_hdr.addr,
block_hdr.size, block_hdr.flags, block_hdr.CRC);
/* Check block header on:
- data larger than 64Kb
- if CRC enabled check CRC
*/
if ((block_hdr.size > 0x7FFF) ||
(((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
(block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
) {
/* Wrong data ! */
rc = -EINVAL;
pr_err("firmware CRC is wrong\n");
goto release;
}
if (!block_hdr.size)
continue;
mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
/* Perform the desired action */
switch (action) {
case UCODE_UPLOAD: /* Upload microcode */
if (drxdap_fasi_write_block(dev_addr,
block_hdr.addr,
mc_block_nr_bytes,
mc_data, 0x0000)) {
rc = -EIO;
pr_err("error writing firmware at pos %zd\n",
mc_data - mc_data_init);
goto release;
}
break;
case UCODE_VERIFY: { /* Verify uploaded microcode */
int result = 0;
u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
u32 bytes_to_comp = 0;
u32 bytes_left = mc_block_nr_bytes;
u32 curr_addr = block_hdr.addr;
u8 *curr_ptr = mc_data;
while (bytes_left != 0) {
if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
else
bytes_to_comp = bytes_left;
if (drxdap_fasi_read_block(dev_addr,
curr_addr,
(u16)bytes_to_comp,
(u8 *)mc_data_buffer,
0x0000)) {
pr_err("error reading firmware at pos %zd\n",
mc_data - mc_data_init);
return -EIO;
}
result = memcmp(curr_ptr, mc_data_buffer,
bytes_to_comp);
if (result) {
pr_err("error verifying firmware at pos %zd\n",
mc_data - mc_data_init);
return -EIO;
}
curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
curr_ptr =&(curr_ptr[bytes_to_comp]);
bytes_left -=((u32) bytes_to_comp);
}
break;
}
default:
return -EINVAL;
}
mc_data += mc_block_nr_bytes;
}
return 0;
release:
release_firmware(demod->firmware);
demod->firmware = NULL;
return rc;
}
/* caller is expected to check if lna is supported before enabling */
static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
{
struct drxuio_cfg uio_cfg;
struct drxuio_data uio_data;
int result;
uio_cfg.uio = DRX_UIO1;
uio_cfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */
result = ctrl_set_uio_cfg(demod, &uio_cfg);
if (result) {
pr_err("Failed to setup LNA GPIO!\n");
return result;
}
uio_data.uio = DRX_UIO1;
uio_data.value = state;
result = ctrl_uio_write(demod, &uio_data);
if (result != 0) {
pr_err("Failed to %sable LNA!\n",
state ? "en" : "dis");
return result;
}
return 0;
}
/*
* The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
*
* Written by Devin Heitmueller <[email protected]>
*/
static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
int result;
enum drx_power_mode power_mode;
if (enable)
power_mode = DRX_POWER_UP;
else
power_mode = DRX_POWER_DOWN;
result = ctrl_power_mode(demod, &power_mode);
if (result != 0) {
pr_err("Power state change failed\n");
return 0;
}
return 0;
}
static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
int result;
enum drx_lock_status lock_status;
*status = 0;
result = ctrl_lock_status(demod, &lock_status);
if (result != 0) {
pr_err("drx39xxj: could not get lock status!\n");
*status = 0;
}
switch (lock_status) {
case DRX_NEVER_LOCK:
*status = 0;
pr_err("drx says NEVER_LOCK\n");
break;
case DRX_NOT_LOCKED:
*status = 0;
break;
case DRX_LOCK_STATE_1:
case DRX_LOCK_STATE_2:
case DRX_LOCK_STATE_3:
case DRX_LOCK_STATE_4:
case DRX_LOCK_STATE_5:
case DRX_LOCK_STATE_6:
case DRX_LOCK_STATE_7:
case DRX_LOCK_STATE_8:
case DRX_LOCK_STATE_9:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
break;
case DRX_LOCKED:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
break;
default:
pr_err("Lock state unknown %d\n", lock_status);
}
ctrl_sig_quality(demod, lock_status);
return 0;
}
static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
*ber = 0;
return 0;
}
if (!p->pre_bit_count.stat[0].uvalue) {
if (!p->pre_bit_error.stat[0].uvalue)
*ber = 0;
else
*ber = 1000000;
} else {
*ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
p->pre_bit_count.stat[0].uvalue);
}
return 0;
}
static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
*strength = 0;
return 0;
}
*strength = p->strength.stat[0].uvalue;
return 0;
}
static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u64 tmp64;
if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
*snr = 0;
return 0;
}
tmp64 = p->cnr.stat[0].svalue;
do_div(tmp64, 10);
*snr = tmp64;
return 0;
}
static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
*ucb = 0;
return 0;
}
*ucb = p->block_error.stat[0].uvalue;
return 0;
}
static int drx39xxj_set_frontend(struct dvb_frontend *fe)
{
#ifdef DJH_DEBUG
int i;
#endif
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
enum drx_standard standard = DRX_STANDARD_8VSB;
struct drx_channel channel;
int result;
static const struct drx_channel def_channel = {
/* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
u32 constellation = DRX_CONSTELLATION_AUTO;
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
if (fe->ops.tuner_ops.set_params) {
u32 int_freq;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
/* Set tuner to desired frequency and standard */
fe->ops.tuner_ops.set_params(fe);
/* Use the tuner's IF */
if (fe->ops.tuner_ops.get_if_frequency) {
fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
demod->my_common_attr->intermediate_freq = int_freq / 1000;
}
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
switch (p->delivery_system) {
case SYS_ATSC:
standard = DRX_STANDARD_8VSB;
break;
case SYS_DVBC_ANNEX_B:
standard = DRX_STANDARD_ITU_B;
switch (p->modulation) {
case QAM_64:
constellation = DRX_CONSTELLATION_QAM64;
break;
case QAM_256:
constellation = DRX_CONSTELLATION_QAM256;
break;
default:
constellation = DRX_CONSTELLATION_AUTO;
break;
}
break;
default:
return -EINVAL;
}
/* Set the standard (will be powered up if necessary */
result = ctrl_set_standard(demod, &standard);
if (result != 0) {
pr_err("Failed to set standard! result=%02x\n",
result);
return -EINVAL;
}
/* set channel parameters */
channel = def_channel;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = constellation;
/* program channel */
result = ctrl_set_channel(demod, &channel);
if (result != 0) {
pr_err("Failed to set channel!\n");
return -EINVAL;
}
/* Just for giggles, let's shut off the LNA again.... */
drxj_set_lna_state(demod, false);
/* After set_frontend, except for strength, stats aren't available */
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
return 0;
}
static int drx39xxj_sleep(struct dvb_frontend *fe)
{
/* power-down the demodulator */
return drx39xxj_set_powerstate(fe, 0);
}
static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
bool i2c_gate_state;
int result;
#ifdef DJH_DEBUG
pr_debug("i2c gate call: enable=%d state=%d\n", enable,
state->i2c_gate_open);
#endif
if (enable)
i2c_gate_state = true;
else
i2c_gate_state = false;
if (state->i2c_gate_open == enable) {
/* We're already in the desired state */
return 0;
}
result = ctrl_i2c_bridge(demod, &i2c_gate_state);
if (result != 0) {
pr_err("drx39xxj: could not open i2c gate [%d]\n",
result);
dump_stack();
} else {
state->i2c_gate_open = enable;
}
return 0;
}
static int drx39xxj_init(struct dvb_frontend *fe)
{
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
int rc = 0;
if (fe->exit == DVB_FE_DEVICE_RESUME) {
/* so drxj_open() does what it needs to do */
demod->my_common_attr->is_opened = false;
rc = drxj_open(demod);
if (rc != 0)
pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
} else
drx39xxj_set_powerstate(fe, 1);
return rc;
}
static int drx39xxj_set_lna(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
struct drxj_data *ext_attr = demod->my_ext_attr;
if (c->lna) {
if (!ext_attr->has_lna) {
pr_err("LNA is not supported on this device!\n");
return -EINVAL;
}
}
return drxj_set_lna_state(demod, c->lna);
}
static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void drx39xxj_release(struct dvb_frontend *fe)
{
struct drx39xxj_state *state = fe->demodulator_priv;
struct drx_demod_instance *demod = state->demod;
/* if device is removed don't access it */
if (fe->exit != DVB_FE_DEVICE_REMOVED)
drxj_close(demod);
kfree(demod->my_ext_attr);
kfree(demod->my_common_attr);
kfree(demod->my_i2c_dev_addr);
release_firmware(demod->firmware);
kfree(demod);
kfree(state);
}
static const struct dvb_frontend_ops drx39xxj_ops;
struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{
struct drx39xxj_state *state = NULL;
struct i2c_device_addr *demod_addr = NULL;
struct drx_common_attr *demod_comm_attr = NULL;
struct drxj_data *demod_ext_attr = NULL;
struct drx_demod_instance *demod = NULL;
struct dtv_frontend_properties *p;
int result;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
if (state == NULL)
goto error;
demod = kmemdup(&drxj_default_demod_g,
sizeof(struct drx_demod_instance), GFP_KERNEL);
if (demod == NULL)
goto error;
demod_addr = kmemdup(&drxj_default_addr_g,
sizeof(struct i2c_device_addr), GFP_KERNEL);
if (demod_addr == NULL)
goto error;
demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
sizeof(struct drx_common_attr), GFP_KERNEL);
if (demod_comm_attr == NULL)
goto error;
demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
GFP_KERNEL);
if (demod_ext_attr == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
state->demod = demod;
/* setup the demod data */
demod->my_i2c_dev_addr = demod_addr;
demod->my_common_attr = demod_comm_attr;
demod->my_i2c_dev_addr->user_data = state;
demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
demod->my_common_attr->verify_microcode = true;
demod->my_common_attr->intermediate_freq = 5000;
demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
demod->my_ext_attr = demod_ext_attr;
((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
demod->i2c = i2c;
result = drxj_open(demod);
if (result != 0) {
pr_err("DRX open failed! Aborting\n");
goto error;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &drx39xxj_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* Initialize stats - needed for DVBv5 stats to work */
p = &state->frontend.dtv_property_cache;
p->strength.len = 1;
p->pre_bit_count.len = 1;
p->pre_bit_error.len = 1;
p->post_bit_count.len = 1;
p->post_bit_error.len = 1;
p->block_count.len = 1;
p->block_error.len = 1;
p->cnr.len = 1;
p->strength.stat[0].scale = FE_SCALE_RELATIVE;
p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return &state->frontend;
error:
kfree(demod_ext_attr);
kfree(demod_comm_attr);
kfree(demod_addr);
kfree(demod);
kfree(state);
return NULL;
}
EXPORT_SYMBOL_GPL(drx39xxj_attach);
static const struct dvb_frontend_ops drx39xxj_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
.info = {
.name = "Micronas DRX39xxj family Frontend",
.frequency_min_hz = 51 * MHz,
.frequency_max_hz = 858 * MHz,
.frequency_stepsize_hz = 62500,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = drx39xxj_init,
.i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
.sleep = drx39xxj_sleep,
.set_frontend = drx39xxj_set_frontend,
.get_tune_settings = drx39xxj_get_tune_settings,
.read_status = drx39xxj_read_status,
.read_ber = drx39xxj_read_ber,
.read_signal_strength = drx39xxj_read_signal_strength,
.read_snr = drx39xxj_read_snr,
.read_ucblocks = drx39xxj_read_ucblocks,
.release = drx39xxj_release,
.set_lna = drx39xxj_set_lna,
};
MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
MODULE_AUTHOR("Devin Heitmueller");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);
| linux-master | drivers/media/dvb-frontends/drx39xyj/drxj.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd_mon.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* common monitor functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_common.h"
#include "cxd2880_tnrdmd_mon.h"
static const u8 rf_lvl_seq[2] = {
0x80, 0x00,
};
int cxd2880_tnrdmd_mon_rf_lvl(struct cxd2880_tnrdmd *tnr_dmd,
int *rf_lvl_db)
{
u8 rdata[2];
int ret;
if (!tnr_dmd || !rf_lvl_db)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, 0x01);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x5b, rf_lvl_seq, 2);
if (ret)
return ret;
usleep_range(2000, 3000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x1a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x15, rdata, 2);
if (ret)
return ret;
if (rdata[0] || rdata[1])
return -EINVAL;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x11, rdata, 2);
if (ret)
return ret;
*rf_lvl_db =
cxd2880_convert2s_complement((rdata[0] << 3) |
((rdata[1] & 0xe0) >> 5), 11);
*rf_lvl_db *= 125;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, 0x00);
if (ret)
return ret;
if (tnr_dmd->rf_lvl_cmpstn)
ret = tnr_dmd->rf_lvl_cmpstn(tnr_dmd, rf_lvl_db);
return ret;
}
int cxd2880_tnrdmd_mon_rf_lvl_sub(struct cxd2880_tnrdmd *tnr_dmd,
int *rf_lvl_db)
{
if (!tnr_dmd || !rf_lvl_db)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, rf_lvl_db);
}
int cxd2880_tnrdmd_mon_internal_cpu_status(struct cxd2880_tnrdmd
*tnr_dmd, u16 *status)
{
u8 data[2] = { 0 };
int ret;
if (!tnr_dmd || !status)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x1a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x15, data, 2);
if (ret)
return ret;
*status = (data[0] << 8) | data[1];
return 0;
}
int cxd2880_tnrdmd_mon_internal_cpu_status_sub(struct
cxd2880_tnrdmd
*tnr_dmd,
u16 *status)
{
if (!tnr_dmd || !status)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_mon_internal_cpu_status(tnr_dmd->diver_sub,
status);
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_mon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd_dvbt_mon.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* DVB-T monitor functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_tnrdmd_mon.h"
#include "cxd2880_tnrdmd_dvbt.h"
#include "cxd2880_tnrdmd_dvbt_mon.h"
#include <linux/int_log.h>
static const int ref_dbm_1000[3][5] = {
{-93000, -91000, -90000, -89000, -88000},
{-87000, -85000, -84000, -83000, -82000},
{-82000, -80000, -78000, -77000, -76000},
};
static int is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd);
int cxd2880_tnrdmd_dvbt_mon_sync_stat(struct cxd2880_tnrdmd
*tnr_dmd, u8 *sync_stat,
u8 *ts_lock_stat,
u8 *unlock_detected)
{
u8 rdata = 0x00;
int ret;
if (!tnr_dmd || !sync_stat || !ts_lock_stat || !unlock_detected)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, &rdata, 1);
if (ret)
return ret;
*unlock_detected = (rdata & 0x10) ? 1 : 0;
*sync_stat = rdata & 0x07;
*ts_lock_stat = (rdata & 0x20) ? 1 : 0;
if (*sync_stat == 0x07)
return -EAGAIN;
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(struct cxd2880_tnrdmd
*tnr_dmd, u8 *sync_stat,
u8 *unlock_detected)
{
u8 ts_lock_stat = 0;
if (!tnr_dmd || !sync_stat || !unlock_detected)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd->diver_sub,
sync_stat,
&ts_lock_stat,
unlock_detected);
}
int cxd2880_tnrdmd_dvbt_mon_mode_guard(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dvbt_mode
*mode,
enum cxd2880_dvbt_guard
*guard)
{
u8 rdata = 0x00;
int ret;
if (!tnr_dmd || !mode || !guard)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret =
cxd2880_tnrdmd_dvbt_mon_mode_guard(tnr_dmd->diver_sub,
mode, guard);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, &rdata, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*mode = (enum cxd2880_dvbt_mode)((rdata >> 2) & 0x03);
*guard = (enum cxd2880_dvbt_guard)(rdata & 0x03);
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_carrier_offset(struct cxd2880_tnrdmd
*tnr_dmd, int *offset)
{
u8 rdata[4];
u32 ctl_val = 0;
int ret;
if (!tnr_dmd || !offset)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1d, rdata, 4);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
ctl_val =
((rdata[0] & 0x1f) << 24) | (rdata[1] << 16) | (rdata[2] << 8) |
(rdata[3]);
*offset = cxd2880_convert2s_complement(ctl_val, 29);
*offset = -1 * ((*offset) * tnr_dmd->bandwidth / 235);
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_carrier_offset_sub(struct
cxd2880_tnrdmd
*tnr_dmd,
int *offset)
{
if (!tnr_dmd || !offset)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt_mon_carrier_offset(tnr_dmd->diver_sub,
offset);
}
int cxd2880_tnrdmd_dvbt_mon_tps_info(struct cxd2880_tnrdmd
*tnr_dmd,
struct cxd2880_dvbt_tpsinfo
*info)
{
u8 rdata[7];
u8 cell_id_ok = 0;
int ret;
if (!tnr_dmd || !info)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret =
cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd->diver_sub,
info);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x29, rdata, 7);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x11);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xd5, &cell_id_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
info->constellation =
(enum cxd2880_dvbt_constellation)((rdata[0] >> 6) & 0x03);
info->hierarchy = (enum cxd2880_dvbt_hierarchy)((rdata[0] >> 3) & 0x07);
info->rate_hp = (enum cxd2880_dvbt_coderate)(rdata[0] & 0x07);
info->rate_lp = (enum cxd2880_dvbt_coderate)((rdata[1] >> 5) & 0x07);
info->guard = (enum cxd2880_dvbt_guard)((rdata[1] >> 3) & 0x03);
info->mode = (enum cxd2880_dvbt_mode)((rdata[1] >> 1) & 0x03);
info->fnum = (rdata[2] >> 6) & 0x03;
info->length_indicator = rdata[2] & 0x3f;
info->cell_id = (rdata[3] << 8) | rdata[4];
info->reserved_even = rdata[5] & 0x3f;
info->reserved_odd = rdata[6] & 0x3f;
info->cell_id_ok = cell_id_ok & 0x01;
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_packet_error_number(struct
cxd2880_tnrdmd
*tnr_dmd,
u32 *pen)
{
u8 rdata[3];
int ret;
if (!tnr_dmd || !pen)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x26, rdata, 3);
if (ret)
return ret;
if (!(rdata[0] & 0x01))
return -EAGAIN;
*pen = (rdata[1] << 8) | rdata[2];
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_spectrum_sense(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_spectrum_sense
*sense)
{
u8 data = 0;
int ret;
if (!tnr_dmd || !sense)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(tnr_dmd->diver_sub,
sense);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1c, &data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*sense =
(data & 0x01) ? CXD2880_TNRDMD_SPECTRUM_INV :
CXD2880_TNRDMD_SPECTRUM_NORMAL;
return ret;
}
static int dvbt_read_snr_reg(struct cxd2880_tnrdmd *tnr_dmd,
u16 *reg_value)
{
u8 rdata[2];
int ret;
if (!tnr_dmd || !reg_value)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x13, rdata, 2);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*reg_value = (rdata[0] << 8) | rdata[1];
return ret;
}
static int dvbt_calc_snr(struct cxd2880_tnrdmd *tnr_dmd,
u32 reg_value, int *snr)
{
if (!tnr_dmd || !snr)
return -EINVAL;
if (reg_value == 0)
return -EAGAIN;
if (reg_value > 4996)
reg_value = 4996;
*snr = intlog10(reg_value) - intlog10(5350 - reg_value);
*snr = (*snr + 839) / 1678 + 28500;
return 0;
}
int cxd2880_tnrdmd_dvbt_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
int *snr)
{
u16 reg_value = 0;
int ret;
if (!tnr_dmd || !snr)
return -EINVAL;
*snr = -1000 * 1000;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
ret = dvbt_read_snr_reg(tnr_dmd, ®_value);
if (ret)
return ret;
ret = dvbt_calc_snr(tnr_dmd, reg_value, snr);
} else {
int snr_main = 0;
int snr_sub = 0;
ret =
cxd2880_tnrdmd_dvbt_mon_snr_diver(tnr_dmd, snr, &snr_main,
&snr_sub);
}
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_snr_diver(struct cxd2880_tnrdmd
*tnr_dmd, int *snr,
int *snr_main, int *snr_sub)
{
u16 reg_value = 0;
u32 reg_value_sum = 0;
int ret;
if (!tnr_dmd || !snr || !snr_main || !snr_sub)
return -EINVAL;
*snr = -1000 * 1000;
*snr_main = -1000 * 1000;
*snr_sub = -1000 * 1000;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = dvbt_read_snr_reg(tnr_dmd, ®_value);
if (!ret) {
ret = dvbt_calc_snr(tnr_dmd, reg_value, snr_main);
if (ret)
reg_value = 0;
} else if (ret == -EAGAIN) {
reg_value = 0;
} else {
return ret;
}
reg_value_sum += reg_value;
ret = dvbt_read_snr_reg(tnr_dmd->diver_sub, ®_value);
if (!ret) {
ret = dvbt_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
if (ret)
reg_value = 0;
} else if (ret == -EAGAIN) {
reg_value = 0;
} else {
return ret;
}
reg_value_sum += reg_value;
return dvbt_calc_snr(tnr_dmd, reg_value_sum, snr);
}
int cxd2880_tnrdmd_dvbt_mon_sampling_offset(struct cxd2880_tnrdmd
*tnr_dmd, int *ppm)
{
u8 ctl_val_reg[5];
u8 nominal_rate_reg[5];
u32 trl_ctl_val = 0;
u32 trcg_nominal_rate = 0;
int num;
int den;
s8 diff_upper = 0;
int ret;
if (!tnr_dmd || !ppm)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = is_tps_locked(tnr_dmd);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x21, ctl_val_reg,
sizeof(ctl_val_reg));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, nominal_rate_reg,
sizeof(nominal_rate_reg));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
diff_upper =
(ctl_val_reg[0] & 0x7f) - (nominal_rate_reg[0] & 0x7f);
if (diff_upper < -1 || diff_upper > 1)
return -EAGAIN;
trl_ctl_val = ctl_val_reg[1] << 24;
trl_ctl_val |= ctl_val_reg[2] << 16;
trl_ctl_val |= ctl_val_reg[3] << 8;
trl_ctl_val |= ctl_val_reg[4];
trcg_nominal_rate = nominal_rate_reg[1] << 24;
trcg_nominal_rate |= nominal_rate_reg[2] << 16;
trcg_nominal_rate |= nominal_rate_reg[3] << 8;
trcg_nominal_rate |= nominal_rate_reg[4];
trl_ctl_val >>= 1;
trcg_nominal_rate >>= 1;
if (diff_upper == 1)
num =
(int)((trl_ctl_val + 0x80000000u) -
trcg_nominal_rate);
else if (diff_upper == -1)
num =
-(int)((trcg_nominal_rate + 0x80000000u) -
trl_ctl_val);
else
num = (int)(trl_ctl_val - trcg_nominal_rate);
den = (nominal_rate_reg[0] & 0x7f) << 24;
den |= nominal_rate_reg[1] << 16;
den |= nominal_rate_reg[2] << 8;
den |= nominal_rate_reg[3];
den = (den + (390625 / 2)) / 390625;
den >>= 1;
if (num >= 0)
*ppm = (num + (den / 2)) / den;
else
*ppm = (num - (den / 2)) / den;
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_sampling_offset_sub(struct
cxd2880_tnrdmd
*tnr_dmd, int *ppm)
{
if (!tnr_dmd || !ppm)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt_mon_sampling_offset(tnr_dmd->diver_sub, ppm);
}
static int dvbt_calc_ssi(struct cxd2880_tnrdmd *tnr_dmd,
int rf_lvl, u8 *ssi)
{
struct cxd2880_dvbt_tpsinfo tps;
int prel;
int temp_ssi = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
ret = cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd, &tps);
if (ret)
return ret;
if (tps.constellation >= CXD2880_DVBT_CONSTELLATION_RESERVED_3 ||
tps.rate_hp >= CXD2880_DVBT_CODERATE_RESERVED_5)
return -EINVAL;
prel = rf_lvl - ref_dbm_1000[tps.constellation][tps.rate_hp];
if (prel < -15000)
temp_ssi = 0;
else if (prel < 0)
temp_ssi = ((2 * (prel + 15000)) + 1500) / 3000;
else if (prel < 20000)
temp_ssi = (((4 * prel) + 500) / 1000) + 10;
else if (prel < 35000)
temp_ssi = (((2 * (prel - 20000)) + 1500) / 3000) + 90;
else
temp_ssi = 100;
*ssi = (temp_ssi > 100) ? 100 : (u8)temp_ssi;
return ret;
}
int cxd2880_tnrdmd_dvbt_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
u8 *ssi)
{
int rf_lvl = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd, &rf_lvl);
if (ret)
return ret;
return dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi);
}
int cxd2880_tnrdmd_dvbt_mon_ssi_sub(struct cxd2880_tnrdmd *tnr_dmd,
u8 *ssi)
{
int rf_lvl = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, &rf_lvl);
if (ret)
return ret;
return dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi);
}
static int is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 sync = 0;
u8 tslock = 0;
u8 early_unlock = 0;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync, &tslock,
&early_unlock);
if (ret)
return ret;
if (sync != 6)
return -EAGAIN;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd_dvbt.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* control functions for DVB-T
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include <media/dvb_frontend.h>
#include "cxd2880_tnrdmd_dvbt.h"
#include "cxd2880_tnrdmd_dvbt_mon.h"
static const struct cxd2880_reg_value tune_dmd_setting_seq1[] = {
{0x00, 0x00}, {0x31, 0x01},
};
static const struct cxd2880_reg_value tune_dmd_setting_seq2[] = {
{0x00, 0x04}, {0x5c, 0xfb}, {0x00, 0x10}, {0xa4, 0x03},
{0x00, 0x14}, {0xb0, 0x00}, {0x00, 0x25},
};
static const struct cxd2880_reg_value tune_dmd_setting_seq3[] = {
{0x00, 0x12}, {0x44, 0x00},
};
static const struct cxd2880_reg_value tune_dmd_setting_seq4[] = {
{0x00, 0x11}, {0x87, 0xd2},
};
static const struct cxd2880_reg_value tune_dmd_setting_seq5[] = {
{0x00, 0x00}, {0xfd, 0x01},
};
static const struct cxd2880_reg_value sleep_dmd_setting_seq1[] = {
{0x00, 0x04}, {0x5c, 0xd8}, {0x00, 0x10}, {0xa4, 0x00},
};
static const struct cxd2880_reg_value sleep_dmd_setting_seq2[] = {
{0x00, 0x11}, {0x87, 0x04},
};
static int x_tune_dvbt_demod_setting(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dtv_bandwidth
bandwidth,
enum cxd2880_tnrdmd_clockmode
clk_mode)
{
static const u8 clk_mode_ckffrq_a[2] = { 0x52, 0x49 };
static const u8 clk_mode_ckffrq_b[2] = { 0x5d, 0x55 };
static const u8 clk_mode_ckffrq_c[2] = { 0x60, 0x00 };
static const u8 ratectl_margin[2] = { 0x01, 0xf0 };
static const u8 maxclkcnt_a[3] = { 0x73, 0xca, 0x49 };
static const u8 maxclkcnt_b[3] = { 0xc8, 0x13, 0xaa };
static const u8 maxclkcnt_c[3] = { 0xdc, 0x6c, 0x00 };
static const u8 bw8_nomi_ac[5] = { 0x15, 0x00, 0x00, 0x00, 0x00};
static const u8 bw8_nomi_b[5] = { 0x14, 0x6a, 0xaa, 0xaa, 0xaa};
static const u8 bw8_gtdofst_a[2] = { 0x01, 0x28 };
static const u8 bw8_gtdofst_b[2] = { 0x11, 0x44 };
static const u8 bw8_gtdofst_c[2] = { 0x15, 0x28 };
static const u8 bw8_mrc_a[5] = { 0x30, 0x00, 0x00, 0x90, 0x00 };
static const u8 bw8_mrc_b[5] = { 0x36, 0x71, 0x00, 0xa3, 0x55 };
static const u8 bw8_mrc_c[5] = { 0x38, 0x00, 0x00, 0xa8, 0x00 };
static const u8 bw8_notch[4] = { 0xb3, 0x00, 0x01, 0x02 };
static const u8 bw7_nomi_ac[5] = { 0x18, 0x00, 0x00, 0x00, 0x00};
static const u8 bw7_nomi_b[5] = { 0x17, 0x55, 0x55, 0x55, 0x55};
static const u8 bw7_gtdofst_a[2] = { 0x12, 0x4c };
static const u8 bw7_gtdofst_b[2] = { 0x1f, 0x15 };
static const u8 bw7_gtdofst_c[2] = { 0x1f, 0xf8 };
static const u8 bw7_mrc_a[5] = { 0x36, 0xdb, 0x00, 0xa4, 0x92 };
static const u8 bw7_mrc_b[5] = { 0x3e, 0x38, 0x00, 0xba, 0xaa };
static const u8 bw7_mrc_c[5] = { 0x40, 0x00, 0x00, 0xc0, 0x00 };
static const u8 bw7_notch[4] = { 0xb8, 0x00, 0x00, 0x03 };
static const u8 bw6_nomi_ac[5] = { 0x1c, 0x00, 0x00, 0x00, 0x00};
static const u8 bw6_nomi_b[5] = { 0x1b, 0x38, 0xe3, 0x8e, 0x38};
static const u8 bw6_gtdofst_a[2] = { 0x1f, 0xf8 };
static const u8 bw6_gtdofst_b[2] = { 0x24, 0x43 };
static const u8 bw6_gtdofst_c[2] = { 0x25, 0x4c };
static const u8 bw6_mrc_a[5] = { 0x40, 0x00, 0x00, 0xc0, 0x00 };
static const u8 bw6_mrc_b[5] = { 0x48, 0x97, 0x00, 0xd9, 0xc7 };
static const u8 bw6_mrc_c[5] = { 0x4a, 0xaa, 0x00, 0xdf, 0xff };
static const u8 bw6_notch[4] = { 0xbe, 0xab, 0x00, 0x03 };
static const u8 bw5_nomi_ac[5] = { 0x21, 0x99, 0x99, 0x99, 0x99};
static const u8 bw5_nomi_b[5] = { 0x20, 0xaa, 0xaa, 0xaa, 0xaa};
static const u8 bw5_gtdofst_a[2] = { 0x26, 0x5d };
static const u8 bw5_gtdofst_b[2] = { 0x2b, 0x84 };
static const u8 bw5_gtdofst_c[2] = { 0x2c, 0xc2 };
static const u8 bw5_mrc_a[5] = { 0x4c, 0xcc, 0x00, 0xe6, 0x66 };
static const u8 bw5_mrc_b[5] = { 0x57, 0x1c, 0x01, 0x05, 0x55 };
static const u8 bw5_mrc_c[5] = { 0x59, 0x99, 0x01, 0x0c, 0xcc };
static const u8 bw5_notch[4] = { 0xc8, 0x01, 0x00, 0x03 };
const u8 *data = NULL;
u8 sst_data;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
tune_dmd_setting_seq1,
ARRAY_SIZE(tune_dmd_setting_seq1));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = clk_mode_ckffrq_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = clk_mode_ckffrq_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = clk_mode_ckffrq_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x65, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x5d, 0x07);
if (ret)
return ret;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
u8 data[2] = { 0x01, 0x01 };
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xce, data, 2);
if (ret)
return ret;
}
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
tune_dmd_setting_seq2,
ARRAY_SIZE(tune_dmd_setting_seq2));
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xf0, ratectl_margin, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN ||
tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
tune_dmd_setting_seq3,
ARRAY_SIZE(tune_dmd_setting_seq3));
if (ret)
return ret;
}
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
tune_dmd_setting_seq4,
ARRAY_SIZE(tune_dmd_setting_seq4));
if (ret)
return ret;
}
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = maxclkcnt_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = maxclkcnt_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = maxclkcnt_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x68, data, 3);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret)
return ret;
switch (bandwidth) {
case CXD2880_DTV_BW_8_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 5);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x00);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw8_gtdofst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_gtdofst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_gtdofst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x7d, data, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_B:
sst_data = 0x35;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
sst_data = 0x34;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x71, sst_data);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw8_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, &data[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x51, &data[2], 3);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x72, &bw8_notch[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x6b, &bw8_notch[2], 2);
if (ret)
return ret;
break;
case CXD2880_DTV_BW_7_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 5);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x02);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw7_gtdofst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_gtdofst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_gtdofst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x7d, data, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_B:
sst_data = 0x2f;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
sst_data = 0x2e;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x71, sst_data);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw7_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, &data[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x51, &data[2], 3);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x72, &bw7_notch[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x6b, &bw7_notch[2], 2);
if (ret)
return ret;
break;
case CXD2880_DTV_BW_6_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 5);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x04);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw6_gtdofst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_gtdofst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_gtdofst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x7d, data, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
sst_data = 0x29;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
sst_data = 0x2a;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x71, sst_data);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw6_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, &data[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x51, &data[2], 3);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x72, &bw6_notch[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x6b, &bw6_notch[2], 2);
if (ret)
return ret;
break;
case CXD2880_DTV_BW_5_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 5);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x06);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw5_gtdofst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_gtdofst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_gtdofst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x7d, data, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_B:
sst_data = 0x24;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
sst_data = 0x23;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x71, sst_data);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw5_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, &data[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x51, &data[2], 3);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x72, &bw5_notch[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x6b, &bw5_notch[2], 2);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
tune_dmd_setting_seq5,
ARRAY_SIZE(tune_dmd_setting_seq5));
}
static int x_sleep_dvbt_demod_setting(struct cxd2880_tnrdmd
*tnr_dmd)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
sleep_dmd_setting_seq1,
ARRAY_SIZE(sleep_dmd_setting_seq1));
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
sleep_dmd_setting_seq2,
ARRAY_SIZE(sleep_dmd_setting_seq2));
return ret;
}
static int dvbt_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dvbt_profile profile)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (ret)
return ret;
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x67,
(profile == CXD2880_DVBT_PROFILE_HP)
? 0x00 : 0x01);
}
int cxd2880_tnrdmd_dvbt_tune1(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt_tune_param
*tune_param)
{
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT,
tune_param->center_freq_khz,
tune_param->bandwidth, 0, 0);
if (ret)
return ret;
ret =
x_tune_dvbt_demod_setting(tnr_dmd, tune_param->bandwidth,
tnr_dmd->clk_mode);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
x_tune_dvbt_demod_setting(tnr_dmd->diver_sub,
tune_param->bandwidth,
tnr_dmd->diver_sub->clk_mode);
if (ret)
return ret;
}
return dvbt_set_profile(tnr_dmd, tune_param->profile);
}
int cxd2880_tnrdmd_dvbt_tune2(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt_tune_param
*tune_param)
{
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_common_tune_setting2(tnr_dmd, CXD2880_DTV_SYS_DVBT,
0);
if (ret)
return ret;
tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
tnr_dmd->frequency_khz = tune_param->center_freq_khz;
tnr_dmd->sys = CXD2880_DTV_SYS_DVBT;
tnr_dmd->bandwidth = tune_param->bandwidth;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT;
tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
}
return 0;
}
int cxd2880_tnrdmd_dvbt_sleep_setting(struct cxd2880_tnrdmd *tnr_dmd)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = x_sleep_dvbt_demod_setting(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret = x_sleep_dvbt_demod_setting(tnr_dmd->diver_sub);
return ret;
}
int cxd2880_tnrdmd_dvbt_check_demod_lock(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_lock_result
*lock)
{
int ret;
u8 sync_stat = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 unlock_detected_sub = 0;
if (!tnr_dmd || !lock)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
&unlock_detected);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
if (sync_stat == 6)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
if (sync_stat == 6) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
return 0;
}
ret =
cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
&unlock_detected_sub);
if (ret)
return ret;
if (sync_stat == 6)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected && unlock_detected_sub)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
int cxd2880_tnrdmd_dvbt_check_ts_lock(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_lock_result
*lock)
{
int ret;
u8 sync_stat = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 unlock_detected_sub = 0;
if (!tnr_dmd || !lock)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
&unlock_detected);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
if (ts_lock)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
if (ts_lock) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
return 0;
} else if (!unlock_detected) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
ret =
cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
&unlock_detected_sub);
if (ret)
return ret;
if (unlock_detected && unlock_detected_sub)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd_dvbt2.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* control functions for DVB-T2
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include <media/dvb_frontend.h>
#include "cxd2880_tnrdmd_dvbt2.h"
#include "cxd2880_tnrdmd_dvbt2_mon.h"
static const struct cxd2880_reg_value tune_dmd_setting_seq1[] = {
{0x00, 0x00}, {0x31, 0x02},
};
static const struct cxd2880_reg_value tune_dmd_setting_seq2[] = {
{0x00, 0x04}, {0x5d, 0x0b},
};
static int x_tune_dvbt2_demod_setting(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dtv_bandwidth
bandwidth,
enum cxd2880_tnrdmd_clockmode
clk_mode)
{
static const u8 tsif_settings[2] = { 0x01, 0x01 };
static const u8 init_settings[14] = {
0x07, 0x06, 0x01, 0xf0, 0x00, 0x00, 0x04, 0xb0, 0x00, 0x00,
0x09, 0x9c, 0x0e, 0x4c
};
static const u8 clk_mode_settings_a1[9] = {
0x52, 0x49, 0x2c, 0x51, 0x51, 0x3d, 0x15, 0x29, 0x0c
};
static const u8 clk_mode_settings_b1[9] = {
0x5d, 0x55, 0x32, 0x5c, 0x5c, 0x45, 0x17, 0x2e, 0x0d
};
static const u8 clk_mode_settings_c1[9] = {
0x60, 0x00, 0x34, 0x5e, 0x5e, 0x47, 0x18, 0x2f, 0x0e
};
static const u8 clk_mode_settings_a2[13] = {
0x04, 0xe7, 0x94, 0x92, 0x09, 0xcf, 0x7e, 0xd0, 0x49,
0xcd, 0xcd, 0x1f, 0x5b
};
static const u8 clk_mode_settings_b2[13] = {
0x05, 0x90, 0x27, 0x55, 0x0b, 0x20, 0x8f, 0xd6, 0xea,
0xc8, 0xc8, 0x23, 0x91
};
static const u8 clk_mode_settings_c2[13] = {
0x05, 0xb8, 0xd8, 0x00, 0x0b, 0x72, 0x93, 0xf3, 0x00,
0xcd, 0xcd, 0x24, 0x95
};
static const u8 clk_mode_settings_a3[5] = {
0x0b, 0x6a, 0xc9, 0x03, 0x33
};
static const u8 clk_mode_settings_b3[5] = {
0x01, 0x02, 0xe4, 0x03, 0x39
};
static const u8 clk_mode_settings_c3[5] = {
0x01, 0x02, 0xeb, 0x03, 0x3b
};
static const u8 gtdofst[2] = { 0x3f, 0xff };
static const u8 bw8_gtdofst_a[2] = { 0x19, 0xd2 };
static const u8 bw8_nomi_ac[6] = { 0x15, 0x00, 0x00, 0x00, 0x00, 0x00 };
static const u8 bw8_nomi_b[6] = { 0x14, 0x6a, 0xaa, 0xaa, 0xab, 0x00 };
static const u8 bw8_sst_a[2] = { 0x06, 0x2a };
static const u8 bw8_sst_b[2] = { 0x06, 0x29 };
static const u8 bw8_sst_c[2] = { 0x06, 0x28 };
static const u8 bw8_mrc_a[9] = {
0x28, 0x00, 0x50, 0x00, 0x60, 0x00, 0x00, 0x90, 0x00
};
static const u8 bw8_mrc_b[9] = {
0x2d, 0x5e, 0x5a, 0xbd, 0x6c, 0xe3, 0x00, 0xa3, 0x55
};
static const u8 bw8_mrc_c[9] = {
0x2e, 0xaa, 0x5d, 0x55, 0x70, 0x00, 0x00, 0xa8, 0x00
};
static const u8 bw7_nomi_ac[6] = { 0x18, 0x00, 0x00, 0x00, 0x00, 0x00 };
static const u8 bw7_nomi_b[6] = { 0x17, 0x55, 0x55, 0x55, 0x55, 0x00 };
static const u8 bw7_sst_a[2] = { 0x06, 0x23 };
static const u8 bw7_sst_b[2] = { 0x06, 0x22 };
static const u8 bw7_sst_c[2] = { 0x06, 0x21 };
static const u8 bw7_mrc_a[9] = {
0x2d, 0xb6, 0x5b, 0x6d, 0x6d, 0xb6, 0x00, 0xa4, 0x92
};
static const u8 bw7_mrc_b[9] = {
0x33, 0xda, 0x67, 0xb4, 0x7c, 0x71, 0x00, 0xba, 0xaa
};
static const u8 bw7_mrc_c[9] = {
0x35, 0x55, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xc0, 0x00
};
static const u8 bw6_nomi_ac[6] = { 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00 };
static const u8 bw6_nomi_b[6] = { 0x1b, 0x38, 0xe3, 0x8e, 0x39, 0x00 };
static const u8 bw6_sst_a[2] = { 0x06, 0x1c };
static const u8 bw6_sst_b[2] = { 0x06, 0x1b };
static const u8 bw6_sst_c[2] = { 0x06, 0x1a };
static const u8 bw6_mrc_a[9] = {
0x35, 0x55, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xc0, 0x00
};
static const u8 bw6_mrc_b[9] = {
0x3c, 0x7e, 0x78, 0xfc, 0x91, 0x2f, 0x00, 0xd9, 0xc7
};
static const u8 bw6_mrc_c[9] = {
0x3e, 0x38, 0x7c, 0x71, 0x95, 0x55, 0x00, 0xdf, 0xff
};
static const u8 bw5_nomi_ac[6] = { 0x21, 0x99, 0x99, 0x99, 0x9a, 0x00 };
static const u8 bw5_nomi_b[6] = { 0x20, 0xaa, 0xaa, 0xaa, 0xab, 0x00 };
static const u8 bw5_sst_a[2] = { 0x06, 0x15 };
static const u8 bw5_sst_b[2] = { 0x06, 0x15 };
static const u8 bw5_sst_c[2] = { 0x06, 0x14 };
static const u8 bw5_mrc_a[9] = {
0x40, 0x00, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xe6, 0x66
};
static const u8 bw5_mrc_b[9] = {
0x48, 0x97, 0x78, 0xfc, 0x91, 0x2f, 0x01, 0x05, 0x55
};
static const u8 bw5_mrc_c[9] = {
0x4a, 0xaa, 0x7c, 0x71, 0x95, 0x55, 0x01, 0x0c, 0xcc
};
static const u8 bw1_7_nomi_a[6] = {
0x68, 0x0f, 0xa2, 0x32, 0xcf, 0x03
};
static const u8 bw1_7_nomi_c[6] = {
0x68, 0x0f, 0xa2, 0x32, 0xcf, 0x03
};
static const u8 bw1_7_nomi_b[6] = {
0x65, 0x2b, 0xa4, 0xcd, 0xd8, 0x03
};
static const u8 bw1_7_sst_a[2] = { 0x06, 0x0c };
static const u8 bw1_7_sst_b[2] = { 0x06, 0x0c };
static const u8 bw1_7_sst_c[2] = { 0x06, 0x0b };
static const u8 bw1_7_mrc_a[9] = {
0x40, 0x00, 0x6a, 0xaa, 0x80, 0x00, 0x02, 0xc9, 0x8f
};
static const u8 bw1_7_mrc_b[9] = {
0x48, 0x97, 0x78, 0xfc, 0x91, 0x2f, 0x03, 0x29, 0x5d
};
static const u8 bw1_7_mrc_c[9] = {
0x4a, 0xaa, 0x7c, 0x71, 0x95, 0x55, 0x03, 0x40, 0x7d
};
const u8 *data = NULL;
const u8 *data2 = NULL;
const u8 *data3 = NULL;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
tune_dmd_setting_seq1,
ARRAY_SIZE(tune_dmd_setting_seq1));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
tune_dmd_setting_seq2,
ARRAY_SIZE(tune_dmd_setting_seq2));
if (ret)
return ret;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xce, tsif_settings, 2);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x20);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x8a, init_settings[0]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x90, init_settings[1]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x25);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xf0, &init_settings[2], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x2a);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xdc, init_settings[4]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xde, init_settings[5]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x2d);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x73, &init_settings[6], 4);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x8f, &init_settings[10], 4);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = clk_mode_settings_a1;
data2 = clk_mode_settings_a2;
data3 = clk_mode_settings_a3;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = clk_mode_settings_b1;
data2 = clk_mode_settings_b2;
data3 = clk_mode_settings_b3;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = clk_mode_settings_c1;
data2 = clk_mode_settings_c2;
data3 = clk_mode_settings_c3;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1d, &data[0], 3);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x22, data[3]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x24, data[4]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x26, data[5]);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x29, &data[6], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x2d, data[8]);
if (ret)
return ret;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x2e, &data2[0], 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x35, &data2[6], 7);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x3c, &data3[0], 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x56, &data3[2], 3);
if (ret)
return ret;
switch (bandwidth) {
case CXD2880_DTV_BW_8_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x00);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw8_gtdofst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = gtdofst;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x19, data, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw8_sst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_sst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_sst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, data, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw8_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw8_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw8_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, data, 9);
if (ret)
return ret;
}
break;
case CXD2880_DTV_BW_7_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x02);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x19, gtdofst, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw7_sst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_sst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_sst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, data, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw7_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw7_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw7_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, data, 9);
if (ret)
return ret;
}
break;
case CXD2880_DTV_BW_6_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x04);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x19, gtdofst, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw6_sst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_sst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_sst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, data, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw6_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw6_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw6_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, data, 9);
if (ret)
return ret;
}
break;
case CXD2880_DTV_BW_5_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_nomi_ac;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x06);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x19, gtdofst, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw5_sst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_sst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_sst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, data, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw5_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw5_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw5_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, data, 9);
if (ret)
return ret;
}
break;
case CXD2880_DTV_BW_1_7_MHZ:
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw1_7_nomi_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw1_7_nomi_c;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw1_7_nomi_b;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4a, 0x03);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x19, gtdofst, 2);
if (ret)
return ret;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw1_7_sst_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw1_7_sst_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw1_7_sst_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1b, data, 2);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data = bw1_7_mrc_a;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data = bw1_7_mrc_b;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data = bw1_7_mrc_c;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x4b, data, 9);
if (ret)
return ret;
}
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xfd, 0x01);
}
static int x_sleep_dvbt2_demod_setting(struct cxd2880_tnrdmd
*tnr_dmd)
{
static const u8 difint_clip[] = {
0, 1, 0, 2, 0, 4, 0, 8, 0, 16, 0, 32
};
int ret = 0;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x1d);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x47, difint_clip, 12);
}
return ret;
}
static int dvbt2_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dvbt2_profile profile)
{
u8 t2_mode_tune_mode = 0;
u8 seq_not2_dtime = 0;
u8 dtime1 = 0;
u8 dtime2 = 0;
int ret;
if (!tnr_dmd)
return -EINVAL;
switch (tnr_dmd->clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
dtime1 = 0x27;
dtime2 = 0x0c;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
dtime1 = 0x2c;
dtime2 = 0x0d;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
dtime1 = 0x2e;
dtime2 = 0x0e;
break;
default:
return -EINVAL;
}
switch (profile) {
case CXD2880_DVBT2_PROFILE_BASE:
t2_mode_tune_mode = 0x01;
seq_not2_dtime = dtime2;
break;
case CXD2880_DVBT2_PROFILE_LITE:
t2_mode_tune_mode = 0x05;
seq_not2_dtime = dtime1;
break;
case CXD2880_DVBT2_PROFILE_ANY:
t2_mode_tune_mode = 0x00;
seq_not2_dtime = dtime1;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x2e);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, t2_mode_tune_mode);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret)
return ret;
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x2c, seq_not2_dtime);
}
int cxd2880_tnrdmd_dvbt2_tune1(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt2_tune_param
*tune_param)
{
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN &&
tune_param->profile == CXD2880_DVBT2_PROFILE_ANY)
return -ENOTTY;
ret =
cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT2,
tune_param->center_freq_khz,
tune_param->bandwidth, 0, 0);
if (ret)
return ret;
ret =
x_tune_dvbt2_demod_setting(tnr_dmd, tune_param->bandwidth,
tnr_dmd->clk_mode);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
x_tune_dvbt2_demod_setting(tnr_dmd->diver_sub,
tune_param->bandwidth,
tnr_dmd->diver_sub->clk_mode);
if (ret)
return ret;
}
ret = dvbt2_set_profile(tnr_dmd, tune_param->profile);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
dvbt2_set_profile(tnr_dmd->diver_sub, tune_param->profile);
if (ret)
return ret;
}
if (tune_param->data_plp_id == CXD2880_DVBT2_TUNE_PARAM_PLPID_AUTO)
ret = cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 1, 0);
else
ret =
cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 0,
(u8)(tune_param->data_plp_id));
return ret;
}
int cxd2880_tnrdmd_dvbt2_tune2(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt2_tune_param
*tune_param)
{
u8 en_fef_intmtnt_ctrl = 1;
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
switch (tune_param->profile) {
case CXD2880_DVBT2_PROFILE_BASE:
en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_base;
break;
case CXD2880_DVBT2_PROFILE_LITE:
en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_lite;
break;
case CXD2880_DVBT2_PROFILE_ANY:
if (tnr_dmd->en_fef_intmtnt_base &&
tnr_dmd->en_fef_intmtnt_lite)
en_fef_intmtnt_ctrl = 1;
else
en_fef_intmtnt_ctrl = 0;
break;
default:
return -EINVAL;
}
ret =
cxd2880_tnrdmd_common_tune_setting2(tnr_dmd,
CXD2880_DTV_SYS_DVBT2,
en_fef_intmtnt_ctrl);
if (ret)
return ret;
tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
tnr_dmd->frequency_khz = tune_param->center_freq_khz;
tnr_dmd->sys = CXD2880_DTV_SYS_DVBT2;
tnr_dmd->bandwidth = tune_param->bandwidth;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT2;
tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
}
return 0;
}
int cxd2880_tnrdmd_dvbt2_sleep_setting(struct cxd2880_tnrdmd
*tnr_dmd)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = x_sleep_dvbt2_demod_setting(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret = x_sleep_dvbt2_demod_setting(tnr_dmd->diver_sub);
return ret;
}
int cxd2880_tnrdmd_dvbt2_check_demod_lock(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_lock_result
*lock)
{
int ret;
u8 sync_stat = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 unlock_detected_sub = 0;
if (!tnr_dmd || !lock)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
&unlock_detected);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
if (sync_stat == 6)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
if (sync_stat == 6) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
return 0;
}
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
&unlock_detected_sub);
if (ret)
return ret;
if (sync_stat == 6)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected && unlock_detected_sub)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
int cxd2880_tnrdmd_dvbt2_check_ts_lock(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_lock_result
*lock)
{
int ret;
u8 sync_stat = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 unlock_detected_sub = 0;
if (!tnr_dmd || !lock)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
&unlock_detected);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
if (ts_lock)
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
else if (unlock_detected)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
if (ts_lock) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
return 0;
} else if (!unlock_detected) {
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
&unlock_detected_sub);
if (ret)
return ret;
if (unlock_detected && unlock_detected_sub)
*lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
else
*lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
return 0;
}
int cxd2880_tnrdmd_dvbt2_set_plp_cfg(struct cxd2880_tnrdmd
*tnr_dmd, u8 auto_plp,
u8 plp_id)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x23);
if (ret)
return ret;
if (!auto_plp) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xaf, plp_id);
if (ret)
return ret;
}
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xad, auto_plp ? 0x00 : 0x01);
}
int cxd2880_tnrdmd_dvbt2_diver_fef_setting(struct cxd2880_tnrdmd
*tnr_dmd)
{
struct cxd2880_dvbt2_ofdm ofdm;
static const u8 data[] = { 0, 8, 0, 16, 0, 32, 0, 64, 0, 128, 1, 0};
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE)
return 0;
ret = cxd2880_tnrdmd_dvbt2_mon_ofdm(tnr_dmd, &ofdm);
if (ret)
return ret;
if (!ofdm.mixed)
return 0;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x1d);
if (ret)
return ret;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x47, data, 12);
}
int cxd2880_tnrdmd_dvbt2_check_l1post_valid(struct cxd2880_tnrdmd
*tnr_dmd,
u8 *l1_post_valid)
{
int ret;
u8 data;
if (!tnr_dmd || !l1_post_valid)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &data, 1);
if (ret)
return ret;
*l1_post_valid = data & 0x01;
return ret;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_spi_device.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* SPI access functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include <linux/spi/spi.h>
#include "cxd2880_spi_device.h"
static int cxd2880_spi_device_write(struct cxd2880_spi *spi,
const u8 *data, u32 size)
{
struct cxd2880_spi_device *spi_device = NULL;
struct spi_message msg;
struct spi_transfer tx;
int result = 0;
if (!spi || !spi->user || !data || size == 0)
return -EINVAL;
spi_device = spi->user;
memset(&tx, 0, sizeof(tx));
tx.tx_buf = data;
tx.len = size;
spi_message_init(&msg);
spi_message_add_tail(&tx, &msg);
result = spi_sync(spi_device->spi, &msg);
if (result < 0)
return -EIO;
return 0;
}
static int cxd2880_spi_device_write_read(struct cxd2880_spi *spi,
const u8 *tx_data,
u32 tx_size,
u8 *rx_data,
u32 rx_size)
{
struct cxd2880_spi_device *spi_device = NULL;
int result = 0;
if (!spi || !spi->user || !tx_data ||
!tx_size || !rx_data || !rx_size)
return -EINVAL;
spi_device = spi->user;
result = spi_write_then_read(spi_device->spi, tx_data,
tx_size, rx_data, rx_size);
if (result < 0)
return -EIO;
return 0;
}
int
cxd2880_spi_device_initialize(struct cxd2880_spi_device *spi_device,
enum cxd2880_spi_mode mode,
u32 speed_hz)
{
int result = 0;
struct spi_device *spi = spi_device->spi;
switch (mode) {
case CXD2880_SPI_MODE_0:
spi->mode = SPI_MODE_0;
break;
case CXD2880_SPI_MODE_1:
spi->mode = SPI_MODE_1;
break;
case CXD2880_SPI_MODE_2:
spi->mode = SPI_MODE_2;
break;
case CXD2880_SPI_MODE_3:
spi->mode = SPI_MODE_3;
break;
default:
return -EINVAL;
}
spi->max_speed_hz = speed_hz;
spi->bits_per_word = 8;
result = spi_setup(spi);
if (result != 0) {
pr_err("spi_setup failed %d\n", result);
return -EINVAL;
}
return 0;
}
int cxd2880_spi_device_create_spi(struct cxd2880_spi *spi,
struct cxd2880_spi_device *spi_device)
{
if (!spi || !spi_device)
return -EINVAL;
spi->read = NULL;
spi->write = cxd2880_spi_device_write;
spi->write_read = cxd2880_spi_device_write_read;
spi->flags = 0;
spi->user = spi_device;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_spi_device.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_integ.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* integration layer common functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include <linux/ktime.h>
#include <linux/errno.h>
#include "cxd2880_tnrdmd.h"
#include "cxd2880_tnrdmd_mon.h"
#include "cxd2880_integ.h"
int cxd2880_integ_init(struct cxd2880_tnrdmd *tnr_dmd)
{
int ret;
ktime_t start;
u8 cpu_task_completed = 0;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_tnrdmd_init1(tnr_dmd);
if (ret)
return ret;
start = ktime_get();
while (1) {
ret =
cxd2880_tnrdmd_check_internal_cpu_status(tnr_dmd,
&cpu_task_completed);
if (ret)
return ret;
if (cpu_task_completed)
break;
if (ktime_to_ms(ktime_sub(ktime_get(), start)) >
CXD2880_TNRDMD_WAIT_INIT_TIMEOUT)
return -ETIMEDOUT;
usleep_range(CXD2880_TNRDMD_WAIT_INIT_INTVL,
CXD2880_TNRDMD_WAIT_INIT_INTVL + 1000);
}
return cxd2880_tnrdmd_init2(tnr_dmd);
}
int cxd2880_integ_cancel(struct cxd2880_tnrdmd *tnr_dmd)
{
if (!tnr_dmd)
return -EINVAL;
atomic_set(&tnr_dmd->cancel, 1);
return 0;
}
int cxd2880_integ_check_cancellation(struct cxd2880_tnrdmd *tnr_dmd)
{
if (!tnr_dmd)
return -EINVAL;
if (atomic_read(&tnr_dmd->cancel) != 0)
return -ECANCELED;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_integ.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd_dvbt2_mon.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* DVB-T2 monitor functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_tnrdmd_mon.h"
#include "cxd2880_tnrdmd_dvbt2.h"
#include "cxd2880_tnrdmd_dvbt2_mon.h"
#include <linux/int_log.h>
static const int ref_dbm_1000[4][8] = {
{-96000, -95000, -94000, -93000, -92000, -92000, -98000, -97000},
{-91000, -89000, -88000, -87000, -86000, -86000, -93000, -92000},
{-86000, -85000, -83000, -82000, -81000, -80000, -89000, -88000},
{-82000, -80000, -78000, -76000, -75000, -74000, -86000, -84000},
};
int cxd2880_tnrdmd_dvbt2_mon_sync_stat(struct cxd2880_tnrdmd
*tnr_dmd, u8 *sync_stat,
u8 *ts_lock_stat,
u8 *unlock_detected)
{
u8 data;
int ret;
if (!tnr_dmd || !sync_stat || !ts_lock_stat || !unlock_detected)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, &data, sizeof(data));
if (ret)
return ret;
*sync_stat = data & 0x07;
*ts_lock_stat = ((data & 0x20) ? 1 : 0);
*unlock_detected = ((data & 0x10) ? 1 : 0);
if (*sync_stat == 0x07)
return -EAGAIN;
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(struct cxd2880_tnrdmd
*tnr_dmd,
u8 *sync_stat,
u8 *unlock_detected)
{
u8 ts_lock_stat = 0;
if (!tnr_dmd || !sync_stat || !unlock_detected)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd->diver_sub,
sync_stat,
&ts_lock_stat,
unlock_detected);
}
int cxd2880_tnrdmd_dvbt2_mon_carrier_offset(struct cxd2880_tnrdmd
*tnr_dmd, int *offset)
{
u8 data[4];
u32 ctl_val = 0;
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
int ret;
if (!tnr_dmd || !offset)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state != 6) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x30, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
ctl_val =
((data[0] & 0x0f) << 24) | (data[1] << 16) | (data[2] << 8)
| (data[3]);
*offset = cxd2880_convert2s_complement(ctl_val, 28);
switch (tnr_dmd->bandwidth) {
case CXD2880_DTV_BW_1_7_MHZ:
*offset = -1 * ((*offset) / 582);
break;
case CXD2880_DTV_BW_5_MHZ:
case CXD2880_DTV_BW_6_MHZ:
case CXD2880_DTV_BW_7_MHZ:
case CXD2880_DTV_BW_8_MHZ:
*offset = -1 * ((*offset) * tnr_dmd->bandwidth / 940);
break;
default:
return -EINVAL;
}
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_carrier_offset_sub(struct
cxd2880_tnrdmd
*tnr_dmd,
int *offset)
{
if (!tnr_dmd || !offset)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt2_mon_carrier_offset(tnr_dmd->diver_sub,
offset);
}
int cxd2880_tnrdmd_dvbt2_mon_l1_pre(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt2_l1pre
*l1_pre)
{
u8 data[37];
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 version = 0;
enum cxd2880_dvbt2_profile profile;
int ret;
if (!tnr_dmd || !l1_pre)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
(tnr_dmd, &sync_state, &unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
} else {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
}
ret = cxd2880_tnrdmd_dvbt2_mon_profile(tnr_dmd, &profile);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x61, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
l1_pre->type = (enum cxd2880_dvbt2_l1pre_type)data[0];
l1_pre->bw_ext = data[1] & 0x01;
l1_pre->s1 = (enum cxd2880_dvbt2_s1)(data[2] & 0x07);
l1_pre->s2 = data[3] & 0x0f;
l1_pre->l1_rep = data[4] & 0x01;
l1_pre->gi = (enum cxd2880_dvbt2_guard)(data[5] & 0x07);
l1_pre->papr = (enum cxd2880_dvbt2_papr)(data[6] & 0x0f);
l1_pre->mod =
(enum cxd2880_dvbt2_l1post_constell)(data[7] & 0x0f);
l1_pre->cr = (enum cxd2880_dvbt2_l1post_cr)(data[8] & 0x03);
l1_pre->fec =
(enum cxd2880_dvbt2_l1post_fec_type)(data[9] & 0x03);
l1_pre->l1_post_size = (data[10] & 0x03) << 16;
l1_pre->l1_post_size |= (data[11]) << 8;
l1_pre->l1_post_size |= (data[12]);
l1_pre->l1_post_info_size = (data[13] & 0x03) << 16;
l1_pre->l1_post_info_size |= (data[14]) << 8;
l1_pre->l1_post_info_size |= (data[15]);
l1_pre->pp = (enum cxd2880_dvbt2_pp)(data[16] & 0x0f);
l1_pre->tx_id_availability = data[17];
l1_pre->cell_id = (data[18] << 8);
l1_pre->cell_id |= (data[19]);
l1_pre->network_id = (data[20] << 8);
l1_pre->network_id |= (data[21]);
l1_pre->sys_id = (data[22] << 8);
l1_pre->sys_id |= (data[23]);
l1_pre->num_frames = data[24];
l1_pre->num_symbols = (data[25] & 0x0f) << 8;
l1_pre->num_symbols |= data[26];
l1_pre->regen = data[27] & 0x07;
l1_pre->post_ext = data[28] & 0x01;
l1_pre->num_rf_freqs = data[29] & 0x07;
l1_pre->rf_idx = data[30] & 0x07;
version = (data[31] & 0x03) << 2;
version |= (data[32] & 0xc0) >> 6;
l1_pre->t2_version = (enum cxd2880_dvbt2_version)version;
l1_pre->l1_post_scrambled = (data[32] & 0x20) >> 5;
l1_pre->t2_base_lite = (data[32] & 0x10) >> 4;
l1_pre->crc32 = (data[33] << 24);
l1_pre->crc32 |= (data[34] << 16);
l1_pre->crc32 |= (data[35] << 8);
l1_pre->crc32 |= data[36];
if (profile == CXD2880_DVBT2_PROFILE_BASE) {
switch ((l1_pre->s2 >> 1)) {
case CXD2880_DVBT2_BASE_S2_M1K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M1K;
break;
case CXD2880_DVBT2_BASE_S2_M2K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M2K;
break;
case CXD2880_DVBT2_BASE_S2_M4K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M4K;
break;
case CXD2880_DVBT2_BASE_S2_M8K_G_DVBT:
case CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2:
l1_pre->fft_mode = CXD2880_DVBT2_M8K;
break;
case CXD2880_DVBT2_BASE_S2_M16K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M16K;
break;
case CXD2880_DVBT2_BASE_S2_M32K_G_DVBT:
case CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2:
l1_pre->fft_mode = CXD2880_DVBT2_M32K;
break;
default:
return -EAGAIN;
}
} else if (profile == CXD2880_DVBT2_PROFILE_LITE) {
switch ((l1_pre->s2 >> 1)) {
case CXD2880_DVBT2_LITE_S2_M2K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M2K;
break;
case CXD2880_DVBT2_LITE_S2_M4K_G_ANY:
l1_pre->fft_mode = CXD2880_DVBT2_M4K;
break;
case CXD2880_DVBT2_LITE_S2_M8K_G_DVBT:
case CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2:
l1_pre->fft_mode = CXD2880_DVBT2_M8K;
break;
case CXD2880_DVBT2_LITE_S2_M16K_G_DVBT:
case CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2:
l1_pre->fft_mode = CXD2880_DVBT2_M16K;
break;
default:
return -EAGAIN;
}
} else {
return -EAGAIN;
}
l1_pre->mixed = l1_pre->s2 & 0x01;
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_version(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dvbt2_version
*ver)
{
u8 data[2];
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 version = 0;
int ret;
if (!tnr_dmd || !ver)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
(tnr_dmd, &sync_state, &unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
} else {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x80, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
version = ((data[0] & 0x03) << 2);
version |= ((data[1] & 0xc0) >> 6);
*ver = (enum cxd2880_dvbt2_version)version;
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_ofdm(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt2_ofdm *ofdm)
{
u8 data[5];
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
int ret;
if (!tnr_dmd || !ofdm)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state != 6) {
slvt_unfreeze_reg(tnr_dmd);
ret = -EAGAIN;
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN)
ret =
cxd2880_tnrdmd_dvbt2_mon_ofdm(tnr_dmd->diver_sub,
ofdm);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x1d, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
ofdm->mixed = ((data[0] & 0x20) ? 1 : 0);
ofdm->is_miso = ((data[0] & 0x10) >> 4);
ofdm->mode = (enum cxd2880_dvbt2_mode)(data[0] & 0x07);
ofdm->gi = (enum cxd2880_dvbt2_guard)((data[1] & 0x70) >> 4);
ofdm->pp = (enum cxd2880_dvbt2_pp)(data[1] & 0x07);
ofdm->bw_ext = (data[2] & 0x10) >> 4;
ofdm->papr = (enum cxd2880_dvbt2_papr)(data[2] & 0x0f);
ofdm->num_symbols = (data[3] << 8) | data[4];
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_data_plps(struct cxd2880_tnrdmd
*tnr_dmd, u8 *plp_ids,
u8 *num_plps)
{
u8 l1_post_ok = 0;
int ret;
if (!tnr_dmd || !num_plps)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!(l1_post_ok & 0x01)) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xc1, num_plps, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (*num_plps == 0) {
slvt_unfreeze_reg(tnr_dmd);
return -EINVAL;
}
if (!plp_ids) {
slvt_unfreeze_reg(tnr_dmd);
return 0;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xc2,
plp_ids,
((*num_plps > 62) ?
62 : *num_plps));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (*num_plps > 62) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0c);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, plp_ids + 62,
*num_plps - 62);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
}
slvt_unfreeze_reg(tnr_dmd);
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_active_plp(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_dvbt2_plp_btype
type,
struct cxd2880_dvbt2_plp
*plp_info)
{
u8 data[20];
u8 addr = 0;
u8 index = 0;
u8 l1_post_ok = 0;
int ret;
if (!tnr_dmd || !plp_info)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!l1_post_ok) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
if (type == CXD2880_DVBT2_PLP_COMMON)
addr = 0xa9;
else
addr = 0x96;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
addr, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
if (type == CXD2880_DVBT2_PLP_COMMON && !data[13])
return -EAGAIN;
plp_info->id = data[index++];
plp_info->type =
(enum cxd2880_dvbt2_plp_type)(data[index++] & 0x07);
plp_info->payload =
(enum cxd2880_dvbt2_plp_payload)(data[index++] & 0x1f);
plp_info->ff = data[index++] & 0x01;
plp_info->first_rf_idx = data[index++] & 0x07;
plp_info->first_frm_idx = data[index++];
plp_info->group_id = data[index++];
plp_info->plp_cr =
(enum cxd2880_dvbt2_plp_code_rate)(data[index++] & 0x07);
plp_info->constell =
(enum cxd2880_dvbt2_plp_constell)(data[index++] & 0x07);
plp_info->rot = data[index++] & 0x01;
plp_info->fec =
(enum cxd2880_dvbt2_plp_fec)(data[index++] & 0x03);
plp_info->num_blocks_max = (data[index++] & 0x03) << 8;
plp_info->num_blocks_max |= data[index++];
plp_info->frm_int = data[index++];
plp_info->til_len = data[index++];
plp_info->til_type = data[index++] & 0x01;
plp_info->in_band_a_flag = data[index++] & 0x01;
plp_info->rsvd = data[index++] << 8;
plp_info->rsvd |= data[index++];
plp_info->in_band_b_flag =
(plp_info->rsvd & 0x8000) >> 15;
plp_info->plp_mode =
(enum cxd2880_dvbt2_plp_mode)((plp_info->rsvd & 0x000c) >> 2);
plp_info->static_flag = (plp_info->rsvd & 0x0002) >> 1;
plp_info->static_padding_flag = plp_info->rsvd & 0x0001;
plp_info->rsvd = (plp_info->rsvd & 0x7ff0) >> 4;
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_data_plp_error(struct cxd2880_tnrdmd
*tnr_dmd,
u8 *plp_error)
{
u8 data;
int ret;
if (!tnr_dmd || !plp_error)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if ((data & 0x01) == 0x00) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xc0, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*plp_error = data & 0x01;
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_l1_change(struct cxd2880_tnrdmd
*tnr_dmd, u8 *l1_change)
{
u8 data;
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
int ret;
if (!tnr_dmd || !l1_change)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
(tnr_dmd, &sync_state, &unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state < 5) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
} else {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x5f, &data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
*l1_change = data & 0x01;
if (*l1_change) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x22);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x16, 0x01);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
}
slvt_unfreeze_reg(tnr_dmd);
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_l1_post(struct cxd2880_tnrdmd
*tnr_dmd,
struct cxd2880_dvbt2_l1post
*l1_post)
{
u8 data[16];
int ret;
if (!tnr_dmd || !l1_post)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, data, sizeof(data));
if (ret)
return ret;
if (!(data[0] & 0x01))
return -EAGAIN;
l1_post->sub_slices_per_frame = (data[1] & 0x7f) << 8;
l1_post->sub_slices_per_frame |= data[2];
l1_post->num_plps = data[3];
l1_post->num_aux = data[4] & 0x0f;
l1_post->aux_cfg_rfu = data[5];
l1_post->rf_idx = data[6] & 0x07;
l1_post->freq = data[7] << 24;
l1_post->freq |= data[8] << 16;
l1_post->freq |= data[9] << 8;
l1_post->freq |= data[10];
l1_post->fef_type = data[11] & 0x0f;
l1_post->fef_length = data[12] << 16;
l1_post->fef_length |= data[13] << 8;
l1_post->fef_length |= data[14];
l1_post->fef_intvl = data[15];
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_bbheader(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dvbt2_plp_btype
type,
struct cxd2880_dvbt2_bbheader
*bbheader)
{
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 data[14];
u8 addr = 0;
int ret;
if (!tnr_dmd || !bbheader)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!ts_lock) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (type == CXD2880_DVBT2_PLP_COMMON) {
u8 l1_post_ok;
u8 data;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!(l1_post_ok & 0x01)) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb6, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (data == 0) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
}
if (type == CXD2880_DVBT2_PLP_COMMON)
addr = 0x51;
else
addr = 0x42;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
addr, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
bbheader->stream_input =
(enum cxd2880_dvbt2_stream)((data[0] >> 6) & 0x03);
bbheader->is_single_input_stream = (data[0] >> 5) & 0x01;
bbheader->is_constant_coding_modulation =
(data[0] >> 4) & 0x01;
bbheader->issy_indicator = (data[0] >> 3) & 0x01;
bbheader->null_packet_deletion = (data[0] >> 2) & 0x01;
bbheader->ext = data[0] & 0x03;
bbheader->input_stream_identifier = data[1];
bbheader->plp_mode =
(data[3] & 0x01) ? CXD2880_DVBT2_PLP_MODE_HEM :
CXD2880_DVBT2_PLP_MODE_NM;
bbheader->data_field_length = (data[4] << 8) | data[5];
if (bbheader->plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {
bbheader->user_packet_length =
(data[6] << 8) | data[7];
bbheader->sync_byte = data[8];
bbheader->issy = 0;
} else {
bbheader->user_packet_length = 0;
bbheader->sync_byte = 0;
bbheader->issy =
(data[11] << 16) | (data[12] << 8) | data[13];
}
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_in_bandb_ts_rate(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_dvbt2_plp_btype
type,
u32 *ts_rate_bps)
{
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 l1_post_ok = 0;
u8 data[4];
u8 addr = 0;
int ret;
if (!tnr_dmd || !ts_rate_bps)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!ts_lock) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!(l1_post_ok & 0x01)) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
if (type == CXD2880_DVBT2_PLP_COMMON)
addr = 0xba;
else
addr = 0xa7;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
addr, &data[0], 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if ((data[0] & 0x80) == 0x00) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x25);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (type == CXD2880_DVBT2_PLP_COMMON)
addr = 0xa6;
else
addr = 0xaa;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
addr, &data[0], 4);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
*ts_rate_bps = ((data[0] & 0x07) << 24) | (data[1] << 16) |
(data[2] << 8) | data[3];
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(struct cxd2880_tnrdmd
*tnr_dmd,
enum
cxd2880_tnrdmd_spectrum_sense
*sense)
{
u8 sync_state = 0;
u8 ts_lock = 0;
u8 early_unlock = 0;
u8 data = 0;
int ret;
if (!tnr_dmd || !sense)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state, &ts_lock,
&early_unlock);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state != 6) {
slvt_unfreeze_reg(tnr_dmd);
ret = -EAGAIN;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret =
cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(tnr_dmd->diver_sub,
sense);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x2f, &data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*sense =
(data & 0x01) ? CXD2880_TNRDMD_SPECTRUM_INV :
CXD2880_TNRDMD_SPECTRUM_NORMAL;
return 0;
}
static int dvbt2_read_snr_reg(struct cxd2880_tnrdmd *tnr_dmd,
u16 *reg_value)
{
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
u8 data[2];
int ret;
if (!tnr_dmd || !reg_value)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state != 6) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x13, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
*reg_value = (data[0] << 8) | data[1];
return ret;
}
static int dvbt2_calc_snr(struct cxd2880_tnrdmd *tnr_dmd,
u32 reg_value, int *snr)
{
if (!tnr_dmd || !snr)
return -EINVAL;
if (reg_value == 0)
return -EAGAIN;
if (reg_value > 10876)
reg_value = 10876;
*snr = intlog10(reg_value) - intlog10(12600 - reg_value);
*snr = (*snr + 839) / 1678 + 32000;
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
int *snr)
{
u16 reg_value = 0;
int ret;
if (!tnr_dmd || !snr)
return -EINVAL;
*snr = -1000 * 1000;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
ret = dvbt2_read_snr_reg(tnr_dmd, ®_value);
if (ret)
return ret;
ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr);
} else {
int snr_main = 0;
int snr_sub = 0;
ret =
cxd2880_tnrdmd_dvbt2_mon_snr_diver(tnr_dmd, snr, &snr_main,
&snr_sub);
}
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_snr_diver(struct cxd2880_tnrdmd
*tnr_dmd, int *snr,
int *snr_main, int *snr_sub)
{
u16 reg_value = 0;
u32 reg_value_sum = 0;
int ret;
if (!tnr_dmd || !snr || !snr_main || !snr_sub)
return -EINVAL;
*snr = -1000 * 1000;
*snr_main = -1000 * 1000;
*snr_sub = -1000 * 1000;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = dvbt2_read_snr_reg(tnr_dmd, ®_value);
if (!ret) {
ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr_main);
if (ret)
reg_value = 0;
} else if (ret == -EAGAIN) {
reg_value = 0;
} else {
return ret;
}
reg_value_sum += reg_value;
ret = dvbt2_read_snr_reg(tnr_dmd->diver_sub, ®_value);
if (!ret) {
ret = dvbt2_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
if (ret)
reg_value = 0;
} else if (ret == -EAGAIN) {
reg_value = 0;
} else {
return ret;
}
reg_value_sum += reg_value;
return dvbt2_calc_snr(tnr_dmd, reg_value_sum, snr);
}
int cxd2880_tnrdmd_dvbt2_mon_packet_error_number(struct
cxd2880_tnrdmd
*tnr_dmd,
u32 *pen)
{
int ret;
u8 data[3];
if (!tnr_dmd || !pen)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x39, data, sizeof(data));
if (ret)
return ret;
if (!(data[0] & 0x01))
return -EAGAIN;
*pen = ((data[1] << 8) | data[2]);
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_sampling_offset(struct cxd2880_tnrdmd
*tnr_dmd, int *ppm)
{
u8 ctl_val_reg[5];
u8 nominal_rate_reg[5];
u32 trl_ctl_val = 0;
u32 trcg_nominal_rate = 0;
int num;
int den;
int ret;
u8 sync_state = 0;
u8 ts_lock = 0;
u8 unlock_detected = 0;
s8 diff_upper = 0;
if (!tnr_dmd || !ppm)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
&ts_lock,
&unlock_detected);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (sync_state != 6) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x34, ctl_val_reg,
sizeof(ctl_val_reg));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x04);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x10, nominal_rate_reg,
sizeof(nominal_rate_reg));
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
slvt_unfreeze_reg(tnr_dmd);
diff_upper =
(ctl_val_reg[0] & 0x7f) - (nominal_rate_reg[0] & 0x7f);
if (diff_upper < -1 || diff_upper > 1)
return -EAGAIN;
trl_ctl_val = ctl_val_reg[1] << 24;
trl_ctl_val |= ctl_val_reg[2] << 16;
trl_ctl_val |= ctl_val_reg[3] << 8;
trl_ctl_val |= ctl_val_reg[4];
trcg_nominal_rate = nominal_rate_reg[1] << 24;
trcg_nominal_rate |= nominal_rate_reg[2] << 16;
trcg_nominal_rate |= nominal_rate_reg[3] << 8;
trcg_nominal_rate |= nominal_rate_reg[4];
trl_ctl_val >>= 1;
trcg_nominal_rate >>= 1;
if (diff_upper == 1)
num =
(int)((trl_ctl_val + 0x80000000u) -
trcg_nominal_rate);
else if (diff_upper == -1)
num =
-(int)((trcg_nominal_rate + 0x80000000u) -
trl_ctl_val);
else
num = (int)(trl_ctl_val - trcg_nominal_rate);
den = (nominal_rate_reg[0] & 0x7f) << 24;
den |= nominal_rate_reg[1] << 16;
den |= nominal_rate_reg[2] << 8;
den |= nominal_rate_reg[3];
den = (den + (390625 / 2)) / 390625;
den >>= 1;
if (num >= 0)
*ppm = (num + (den / 2)) / den;
else
*ppm = (num - (den / 2)) / den;
return 0;
}
int cxd2880_tnrdmd_dvbt2_mon_sampling_offset_sub(struct
cxd2880_tnrdmd
*tnr_dmd,
int *ppm)
{
if (!tnr_dmd || !ppm)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_dvbt2_mon_sampling_offset(tnr_dmd->diver_sub,
ppm);
}
int cxd2880_tnrdmd_dvbt2_mon_qam(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dvbt2_plp_btype type,
enum cxd2880_dvbt2_plp_constell *qam)
{
u8 data;
u8 l1_post_ok = 0;
int ret;
if (!tnr_dmd || !qam)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!(l1_post_ok & 0x01)) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
if (type == CXD2880_DVBT2_PLP_COMMON) {
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb6, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (data == 0) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb1, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
} else {
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x9e, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
}
slvt_unfreeze_reg(tnr_dmd);
*qam = (enum cxd2880_dvbt2_plp_constell)(data & 0x07);
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_code_rate(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dvbt2_plp_btype
type,
enum
cxd2880_dvbt2_plp_code_rate
*code_rate)
{
u8 data;
u8 l1_post_ok = 0;
int ret;
if (!tnr_dmd || !code_rate)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x86, &l1_post_ok, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (!(l1_post_ok & 0x01)) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
if (type == CXD2880_DVBT2_PLP_COMMON) {
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb6, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
if (data == 0) {
slvt_unfreeze_reg(tnr_dmd);
return -EAGAIN;
}
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb0, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
} else {
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x9d, &data, 1);
if (ret) {
slvt_unfreeze_reg(tnr_dmd);
return ret;
}
}
slvt_unfreeze_reg(tnr_dmd);
*code_rate = (enum cxd2880_dvbt2_plp_code_rate)(data & 0x07);
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_profile(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dvbt2_profile
*profile)
{
u8 data;
int ret;
if (!tnr_dmd || !profile)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x22, &data, sizeof(data));
if (ret)
return ret;
if (data & 0x02) {
if (data & 0x01)
*profile = CXD2880_DVBT2_PROFILE_LITE;
else
*profile = CXD2880_DVBT2_PROFILE_BASE;
} else {
ret = -EAGAIN;
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN)
ret =
cxd2880_tnrdmd_dvbt2_mon_profile(tnr_dmd->diver_sub,
profile);
return ret;
}
return 0;
}
static int dvbt2_calc_ssi(struct cxd2880_tnrdmd *tnr_dmd,
int rf_lvl, u8 *ssi)
{
enum cxd2880_dvbt2_plp_constell qam;
enum cxd2880_dvbt2_plp_code_rate code_rate;
int prel;
int temp_ssi = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
ret =
cxd2880_tnrdmd_dvbt2_mon_qam(tnr_dmd, CXD2880_DVBT2_PLP_DATA, &qam);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_dvbt2_mon_code_rate(tnr_dmd, CXD2880_DVBT2_PLP_DATA,
&code_rate);
if (ret)
return ret;
if (code_rate > CXD2880_DVBT2_R2_5 || qam > CXD2880_DVBT2_QAM256)
return -EINVAL;
prel = rf_lvl - ref_dbm_1000[qam][code_rate];
if (prel < -15000)
temp_ssi = 0;
else if (prel < 0)
temp_ssi = ((2 * (prel + 15000)) + 1500) / 3000;
else if (prel < 20000)
temp_ssi = (((4 * prel) + 500) / 1000) + 10;
else if (prel < 35000)
temp_ssi = (((2 * (prel - 20000)) + 1500) / 3000) + 90;
else
temp_ssi = 100;
*ssi = (temp_ssi > 100) ? 100 : (u8)temp_ssi;
return ret;
}
int cxd2880_tnrdmd_dvbt2_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
u8 *ssi)
{
int rf_lvl = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd, &rf_lvl);
if (ret)
return ret;
return dvbt2_calc_ssi(tnr_dmd, rf_lvl, ssi);
}
int cxd2880_tnrdmd_dvbt2_mon_ssi_sub(struct cxd2880_tnrdmd
*tnr_dmd, u8 *ssi)
{
int rf_lvl = 0;
int ret;
if (!tnr_dmd || !ssi)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, &rf_lvl);
if (ret)
return ret;
return dvbt2_calc_ssi(tnr_dmd, rf_lvl, ssi);
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_devio_spi.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* I/O interface via SPI
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_devio_spi.h"
#define BURST_WRITE_MAX 128
static int cxd2880_io_spi_read_reg(struct cxd2880_io *io,
enum cxd2880_io_tgt tgt,
u8 sub_address, u8 *data,
u32 size)
{
int ret = 0;
struct cxd2880_spi *spi = NULL;
u8 send_data[6];
u8 *read_data_top = data;
if (!io || !io->if_object || !data)
return -EINVAL;
if (sub_address + size > 0x100)
return -EINVAL;
spi = io->if_object;
if (tgt == CXD2880_IO_TGT_SYS)
send_data[0] = 0x0b;
else
send_data[0] = 0x0a;
send_data[3] = 0;
send_data[4] = 0;
send_data[5] = 0;
while (size > 0) {
send_data[1] = sub_address;
if (size > 255)
send_data[2] = 255;
else
send_data[2] = size;
ret =
spi->write_read(spi, send_data, sizeof(send_data),
read_data_top, send_data[2]);
if (ret)
return ret;
sub_address += send_data[2];
read_data_top += send_data[2];
size -= send_data[2];
}
return ret;
}
static int cxd2880_io_spi_write_reg(struct cxd2880_io *io,
enum cxd2880_io_tgt tgt,
u8 sub_address,
const u8 *data, u32 size)
{
int ret = 0;
struct cxd2880_spi *spi = NULL;
u8 send_data[BURST_WRITE_MAX + 4];
const u8 *write_data_top = data;
if (!io || !io->if_object || !data)
return -EINVAL;
if (size > BURST_WRITE_MAX)
return -EINVAL;
if (sub_address + size > 0x100)
return -EINVAL;
spi = io->if_object;
if (tgt == CXD2880_IO_TGT_SYS)
send_data[0] = 0x0f;
else
send_data[0] = 0x0e;
while (size > 0) {
send_data[1] = sub_address;
if (size > 255)
send_data[2] = 255;
else
send_data[2] = size;
memcpy(&send_data[3], write_data_top, send_data[2]);
if (tgt == CXD2880_IO_TGT_SYS) {
send_data[3 + send_data[2]] = 0x00;
ret = spi->write(spi, send_data, send_data[2] + 4);
} else {
ret = spi->write(spi, send_data, send_data[2] + 3);
}
if (ret)
return ret;
sub_address += send_data[2];
write_data_top += send_data[2];
size -= send_data[2];
}
return ret;
}
int cxd2880_io_spi_create(struct cxd2880_io *io,
struct cxd2880_spi *spi, u8 slave_select)
{
if (!io || !spi)
return -EINVAL;
io->read_regs = cxd2880_io_spi_read_reg;
io->write_regs = cxd2880_io_spi_write_reg;
io->write_reg = cxd2880_io_common_write_one_reg;
io->if_object = spi;
io->i2c_address_sys = 0;
io->i2c_address_demod = 0;
io->slave_select = slave_select;
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_devio_spi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_common.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* common functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_common.h"
int cxd2880_convert2s_complement(u32 value, u32 bitlen)
{
if (!bitlen || bitlen >= 32)
return (int)value;
if (value & (u32)(1 << (bitlen - 1)))
return (int)(GENMASK(31, bitlen) | value);
else
return (int)(GENMASK(bitlen - 1, 0) & value);
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_common.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_io.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* register I/O interface functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include "cxd2880_io.h"
int cxd2880_io_common_write_one_reg(struct cxd2880_io *io,
enum cxd2880_io_tgt tgt,
u8 sub_address, u8 data)
{
if (!io)
return -EINVAL;
return io->write_regs(io, tgt, sub_address, &data, 1);
}
int cxd2880_io_set_reg_bits(struct cxd2880_io *io,
enum cxd2880_io_tgt tgt,
u8 sub_address, u8 data, u8 mask)
{
int ret;
if (!io)
return -EINVAL;
if (mask == 0x00)
return 0;
if (mask != 0xff) {
u8 rdata = 0x00;
ret = io->read_regs(io, tgt, sub_address, &rdata, 1);
if (ret)
return ret;
data = (data & mask) | (rdata & (mask ^ 0xff));
}
return io->write_reg(io, tgt, sub_address, data);
}
int cxd2880_io_write_multi_regs(struct cxd2880_io *io,
enum cxd2880_io_tgt tgt,
const struct cxd2880_reg_value reg_value[],
u8 size)
{
int ret;
int i;
if (!io)
return -EINVAL;
for (i = 0; i < size ; i++) {
ret = io->write_reg(io, tgt, reg_value[i].addr,
reg_value[i].value);
if (ret)
return ret;
}
return 0;
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_io.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_top.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
#include <linux/spi/spi.h>
#include <media/dvb_frontend.h>
#include <linux/int_log.h>
#include "cxd2880.h"
#include "cxd2880_tnrdmd_mon.h"
#include "cxd2880_tnrdmd_dvbt2_mon.h"
#include "cxd2880_tnrdmd_dvbt_mon.h"
#include "cxd2880_integ.h"
#include "cxd2880_tnrdmd_dvbt2.h"
#include "cxd2880_tnrdmd_dvbt.h"
#include "cxd2880_devio_spi.h"
#include "cxd2880_spi_device.h"
#include "cxd2880_tnrdmd_driver_version.h"
struct cxd2880_priv {
struct cxd2880_tnrdmd tnrdmd;
struct spi_device *spi;
struct cxd2880_io regio;
struct cxd2880_spi_device spi_device;
struct cxd2880_spi cxd2880_spi;
struct cxd2880_dvbt_tune_param dvbt_tune_param;
struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
struct mutex *spi_mutex; /* For SPI access exclusive control */
unsigned long pre_ber_update;
unsigned long pre_ber_interval;
unsigned long post_ber_update;
unsigned long post_ber_interval;
unsigned long ucblock_update;
unsigned long ucblock_interval;
enum fe_status s;
};
static int cxd2880_pre_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
u32 *pre_bit_err, u32 *pre_bit_count)
{
u8 rdata[2];
int ret;
if (!tnrdmd || !pre_bit_err || !pre_bit_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = slvt_freeze_reg(tnrdmd);
if (ret)
return ret;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x39, rdata, 1);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
if ((rdata[0] & 0x01) == 0) {
slvt_unfreeze_reg(tnrdmd);
return -EAGAIN;
}
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x22, rdata, 2);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
*pre_bit_err = (rdata[0] << 8) | rdata[1];
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x6f, rdata, 1);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
slvt_unfreeze_reg(tnrdmd);
*pre_bit_count = ((rdata[0] & 0x07) == 0) ?
256 : (0x1000 << (rdata[0] & 0x07));
return 0;
}
static int cxd2880_pre_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
u32 *pre_bit_err,
u32 *pre_bit_count)
{
u32 period_exp = 0;
u32 n_ldpc = 0;
u8 data[5];
int ret;
if (!tnrdmd || !pre_bit_err || !pre_bit_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnrdmd);
if (ret)
return ret;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x3c, data, sizeof(data));
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
if (!(data[0] & 0x01)) {
slvt_unfreeze_reg(tnrdmd);
return -EAGAIN;
}
*pre_bit_err =
((data[1] & 0x0f) << 24) | (data[2] << 16) | (data[3] << 8) | data[4];
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0xa0, data, 1);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
CXD2880_DVBT2_FEC_LDPC_16K)
n_ldpc = 16200;
else
n_ldpc = 64800;
slvt_unfreeze_reg(tnrdmd);
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x20);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x6f, data, 1);
if (ret)
return ret;
period_exp = data[0] & 0x0f;
*pre_bit_count = (1U << period_exp) * n_ldpc;
return 0;
}
static int cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
u32 *post_bit_err,
u32 *post_bit_count)
{
u8 rdata[3];
u32 bit_error = 0;
u32 period_exp = 0;
int ret;
if (!tnrdmd || !post_bit_err || !post_bit_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x15, rdata, 3);
if (ret)
return ret;
if ((rdata[0] & 0x40) == 0)
return -EAGAIN;
*post_bit_err = ((rdata[0] & 0x3f) << 16) | (rdata[1] << 8) | rdata[2];
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x60, rdata, 1);
if (ret)
return ret;
period_exp = (rdata[0] & 0x1f);
if (period_exp <= 11 && (bit_error > (1U << period_exp) * 204 * 8))
return -EAGAIN;
*post_bit_count = (1U << period_exp) * 204 * 8;
return 0;
}
static int cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
u32 *post_bit_err,
u32 *post_bit_count)
{
u32 period_exp = 0;
u32 n_bch = 0;
u8 data[3];
enum cxd2880_dvbt2_plp_fec plp_fec_type =
CXD2880_DVBT2_FEC_LDPC_16K;
enum cxd2880_dvbt2_plp_code_rate plp_code_rate =
CXD2880_DVBT2_R1_2;
int ret;
static const u16 n_bch_bits_lookup[2][8] = {
{7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
{32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
};
if (!tnrdmd || !post_bit_err || !post_bit_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = slvt_freeze_reg(tnrdmd);
if (ret)
return ret;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x15, data, 3);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
if (!(data[0] & 0x40)) {
slvt_unfreeze_reg(tnrdmd);
return -EAGAIN;
}
*post_bit_err =
((data[0] & 0x3f) << 16) | (data[1] << 8) | data[2];
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x9d, data, 1);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
plp_code_rate =
(enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0xa0, data, 1);
if (ret) {
slvt_unfreeze_reg(tnrdmd);
return ret;
}
plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
slvt_unfreeze_reg(tnrdmd);
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x20);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x72, data, 1);
if (ret)
return ret;
period_exp = data[0] & 0x0f;
if (plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K ||
plp_code_rate > CXD2880_DVBT2_R2_5)
return -EAGAIN;
n_bch = n_bch_bits_lookup[plp_fec_type][plp_code_rate];
if (*post_bit_err > ((1U << period_exp) * n_bch))
return -EAGAIN;
*post_bit_count = (1U << period_exp) * n_bch;
return 0;
}
static int cxd2880_read_block_err_t(struct cxd2880_tnrdmd *tnrdmd,
u32 *block_err,
u32 *block_count)
{
u8 rdata[3];
int ret;
if (!tnrdmd || !block_err || !block_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
return -EINVAL;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0d);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x18, rdata, 3);
if (ret)
return ret;
if ((rdata[0] & 0x01) == 0)
return -EAGAIN;
*block_err = (rdata[1] << 8) | rdata[2];
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x5c, rdata, 1);
if (ret)
return ret;
*block_count = 1U << (rdata[0] & 0x0f);
if ((*block_count == 0) || (*block_err > *block_count))
return -EAGAIN;
return 0;
}
static int cxd2880_read_block_err_t2(struct cxd2880_tnrdmd *tnrdmd,
u32 *block_err,
u32 *block_count)
{
u8 rdata[3];
int ret;
if (!tnrdmd || !block_err || !block_count)
return -EINVAL;
if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
return -EINVAL;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x0b);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x18, rdata, 3);
if (ret)
return ret;
if ((rdata[0] & 0x01) == 0)
return -EAGAIN;
*block_err = (rdata[1] << 8) | rdata[2];
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x24);
if (ret)
return ret;
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0xdc, rdata, 1);
if (ret)
return ret;
*block_count = 1U << (rdata[0] & 0x0f);
if ((*block_count == 0) || (*block_err > *block_count))
return -EAGAIN;
return 0;
}
static void cxd2880_release(struct dvb_frontend *fe)
{
struct cxd2880_priv *priv = NULL;
if (!fe) {
pr_err("invalid arg.\n");
return;
}
priv = fe->demodulator_priv;
kfree(priv);
}
static int cxd2880_init(struct dvb_frontend *fe)
{
int ret;
struct cxd2880_priv *priv = NULL;
struct cxd2880_tnrdmd_create_param create_param;
if (!fe) {
pr_err("invalid arg.\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
create_param.ts_output_if = CXD2880_TNRDMD_TSOUT_IF_SPI;
create_param.xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_NONE;
create_param.en_internal_ldo = 1;
create_param.xosc_cap = 18;
create_param.xosc_i = 8;
create_param.stationary_use = 1;
mutex_lock(priv->spi_mutex);
if (priv->tnrdmd.io != &priv->regio) {
ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
&priv->regio, &create_param);
if (ret) {
mutex_unlock(priv->spi_mutex);
pr_info("cxd2880 tnrdmd create failed %d\n", ret);
return ret;
}
}
ret = cxd2880_integ_init(&priv->tnrdmd);
if (ret) {
mutex_unlock(priv->spi_mutex);
pr_err("cxd2880 integ init failed %d\n", ret);
return ret;
}
ret = cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
0x00);
if (ret) {
mutex_unlock(priv->spi_mutex);
pr_err("cxd2880 set config failed %d\n", ret);
return ret;
}
mutex_unlock(priv->spi_mutex);
pr_debug("OK.\n");
return ret;
}
static int cxd2880_sleep(struct dvb_frontend *fe)
{
int ret;
struct cxd2880_priv *priv = NULL;
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
mutex_unlock(priv->spi_mutex);
pr_debug("tnrdmd_sleep ret %d\n", ret);
return ret;
}
static int cxd2880_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
int ret;
struct cxd2880_priv *priv = NULL;
struct dtv_frontend_properties *c = NULL;
int level = 0;
if (!fe || !strength) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT ||
c->delivery_system == SYS_DVBT2) {
ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
} else {
pr_debug("invalid system\n");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
level /= 125;
/*
* level should be between -105dBm and -30dBm.
* E.g. they should be between:
* -105000/125 = -840 and -30000/125 = -240
*/
level = clamp(level, -840, -240);
/* scale value to 0x0000-0xffff */
*strength = ((level + 840) * 0xffff) / (-240 + 840);
if (ret)
pr_debug("ret = %d\n", ret);
return ret;
}
static int cxd2880_read_snr(struct dvb_frontend *fe, u16 *snr)
{
int ret;
int snrvalue = 0;
struct cxd2880_priv *priv = NULL;
struct dtv_frontend_properties *c = NULL;
if (!fe || !snr) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT) {
ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
&snrvalue);
} else if (c->delivery_system == SYS_DVBT2) {
ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
&snrvalue);
} else {
pr_err("invalid system\n");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
if (snrvalue < 0)
snrvalue = 0;
*snr = snrvalue;
if (ret)
pr_debug("ret = %d\n", ret);
return ret;
}
static int cxd2880_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
int ret;
struct cxd2880_priv *priv = NULL;
struct dtv_frontend_properties *c = NULL;
if (!fe || !ucblocks) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT) {
ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(&priv->tnrdmd,
ucblocks);
} else if (c->delivery_system == SYS_DVBT2) {
ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(&priv->tnrdmd,
ucblocks);
} else {
pr_err("invalid system\n");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
if (ret)
pr_debug("ret = %d\n", ret);
return ret;
}
static int cxd2880_read_ber(struct dvb_frontend *fe, u32 *ber)
{
*ber = 0;
return 0;
}
static int cxd2880_set_ber_per_period_t(struct dvb_frontend *fe)
{
int ret;
struct cxd2880_priv *priv;
struct cxd2880_dvbt_tpsinfo info;
enum cxd2880_dtv_bandwidth bw;
u32 pre_ber_rate = 0;
u32 post_ber_rate = 0;
u32 ucblock_rate = 0;
u32 mes_exp = 0;
static const int cr_table[5] = {31500, 42000, 47250, 52500, 55125};
static const int denominator_tbl[4] = {125664, 129472, 137088, 152320};
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
bw = priv->dvbt_tune_param.bandwidth;
ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,
&info);
if (ret) {
pr_err("tps monitor error ret = %d\n", ret);
info.hierarchy = CXD2880_DVBT_HIERARCHY_NON;
info.constellation = CXD2880_DVBT_CONSTELLATION_QPSK;
info.guard = CXD2880_DVBT_GUARD_1_4;
info.rate_hp = CXD2880_DVBT_CODERATE_1_2;
info.rate_lp = CXD2880_DVBT_CODERATE_1_2;
}
if (info.hierarchy == CXD2880_DVBT_HIERARCHY_NON) {
pre_ber_rate = 63000000 * bw * (info.constellation * 2 + 2) /
denominator_tbl[info.guard];
post_ber_rate = 1000 * cr_table[info.rate_hp] * bw *
(info.constellation * 2 + 2) /
denominator_tbl[info.guard];
ucblock_rate = 875 * cr_table[info.rate_hp] * bw *
(info.constellation * 2 + 2) /
denominator_tbl[info.guard];
} else {
u8 data = 0;
struct cxd2880_tnrdmd *tnrdmd = &priv->tnrdmd;
ret = tnrdmd->io->write_reg(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (!ret) {
ret = tnrdmd->io->read_regs(tnrdmd->io,
CXD2880_IO_TGT_DMD,
0x67, &data, 1);
if (ret)
data = 0x00;
} else {
data = 0x00;
}
if (data & 0x01) { /* Low priority */
pre_ber_rate =
63000000 * bw * (info.constellation * 2 + 2) /
denominator_tbl[info.guard];
post_ber_rate = 1000 * cr_table[info.rate_lp] * bw *
(info.constellation * 2 + 2) /
denominator_tbl[info.guard];
ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_lp] *
bw * (info.constellation * 2 + 2) /
denominator_tbl[info.guard];
} else { /* High priority */
pre_ber_rate =
63000000 * bw * 2 / denominator_tbl[info.guard];
post_ber_rate = 1000 * cr_table[info.rate_hp] * bw * 2 /
denominator_tbl[info.guard];
ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_hp] *
bw * 2 / denominator_tbl[info.guard];
}
}
mes_exp = pre_ber_rate < 8192 ? 8 : intlog2(pre_ber_rate) >> 24;
priv->pre_ber_interval =
((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
pre_ber_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
mes_exp == 8 ? 0 : mes_exp - 12);
mes_exp = intlog2(post_ber_rate) >> 24;
priv->post_ber_interval =
((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
post_ber_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
mes_exp);
mes_exp = intlog2(ucblock_rate) >> 24;
priv->ucblock_interval =
((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
ucblock_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT_PER_MES,
mes_exp);
return 0;
}
static int cxd2880_set_ber_per_period_t2(struct dvb_frontend *fe)
{
int ret;
struct cxd2880_priv *priv;
struct cxd2880_dvbt2_l1pre l1pre;
struct cxd2880_dvbt2_l1post l1post;
struct cxd2880_dvbt2_plp plp;
struct cxd2880_dvbt2_bbheader bbheader;
enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
u32 pre_ber_rate = 0;
u32 post_ber_rate = 0;
u32 ucblock_rate = 0;
u32 mes_exp = 0;
u32 term_a = 0;
u32 term_b = 0;
u32 denominator = 0;
static const u32 gi_tbl[7] = {32, 64, 128, 256, 8, 152, 76};
static const u8 n_tbl[6] = {8, 2, 4, 16, 1, 1};
static const u8 mode_tbl[6] = {2, 8, 4, 1, 16, 32};
static const u32 kbch_tbl[2][8] = {
{6952, 9472, 10552, 11632, 12352, 13072, 5152, 6232},
{32128, 38608, 42960, 48328, 51568, 53760, 0, 0}
};
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
bw = priv->dvbt2_tune_param.bandwidth;
ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
if (ret) {
pr_info("l1 pre error\n");
goto error_ber_setting;
}
ret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,
CXD2880_DVBT2_PLP_DATA, &plp);
if (ret) {
pr_info("plp info error\n");
goto error_ber_setting;
}
ret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);
if (ret) {
pr_info("l1 post error\n");
goto error_ber_setting;
}
term_a =
(mode_tbl[l1pre.fft_mode] * (1024 + gi_tbl[l1pre.gi])) *
(l1pre.num_symbols + n_tbl[l1pre.fft_mode]) + 2048;
if (l1pre.mixed && l1post.fef_intvl) {
term_b = (l1post.fef_length + (l1post.fef_intvl / 2)) /
l1post.fef_intvl;
} else {
term_b = 0;
}
switch (bw) {
case CXD2880_DTV_BW_1_7_MHZ:
denominator = ((term_a + term_b) * 71 + (131 / 2)) / 131;
break;
case CXD2880_DTV_BW_5_MHZ:
denominator = ((term_a + term_b) * 7 + 20) / 40;
break;
case CXD2880_DTV_BW_6_MHZ:
denominator = ((term_a + term_b) * 7 + 24) / 48;
break;
case CXD2880_DTV_BW_7_MHZ:
denominator = ((term_a + term_b) + 4) / 8;
break;
case CXD2880_DTV_BW_8_MHZ:
default:
denominator = ((term_a + term_b) * 7 + 32) / 64;
break;
}
if (plp.til_type && plp.til_len) {
pre_ber_rate =
(plp.num_blocks_max * 1000000 + (denominator / 2)) /
denominator;
pre_ber_rate = (pre_ber_rate + (plp.til_len / 2)) /
plp.til_len;
} else {
pre_ber_rate =
(plp.num_blocks_max * 1000000 + (denominator / 2)) /
denominator;
}
post_ber_rate = pre_ber_rate;
mes_exp = intlog2(pre_ber_rate) >> 24;
priv->pre_ber_interval =
((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
pre_ber_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
mes_exp);
mes_exp = intlog2(post_ber_rate) >> 24;
priv->post_ber_interval =
((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
post_ber_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
mes_exp);
ret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,
CXD2880_DVBT2_PLP_DATA,
&bbheader);
if (ret) {
pr_info("bb header error\n");
goto error_ucblock_setting;
}
if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {
if (!bbheader.issy_indicator) {
ucblock_rate =
(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
752) / 1504;
} else {
ucblock_rate =
(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
764) / 1528;
}
} else if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_HEM) {
ucblock_rate =
(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] + 748) /
1496;
} else {
pr_info("plp mode is not Normal or HEM\n");
goto error_ucblock_setting;
}
mes_exp = intlog2(ucblock_rate) >> 24;
priv->ucblock_interval =
((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
ucblock_rate;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
mes_exp);
return 0;
error_ber_setting:
priv->pre_ber_interval = 1000;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_LBER_MES, 0);
priv->post_ber_interval = 1000;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_BBER_MES, 0);
error_ucblock_setting:
priv->ucblock_interval = 1000;
cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
CXD2880_TNRDMD_CFG_DVBT2_PER_MES, 8);
return 0;
}
static int cxd2880_dvbt_tune(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt_tune_param
*tune_param)
{
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
atomic_set(&tnr_dmd->cancel, 0);
if (tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ) {
return -ENOTTY;
}
ret = cxd2880_tnrdmd_dvbt_tune1(tnr_dmd, tune_param);
if (ret)
return ret;
usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
return cxd2880_tnrdmd_dvbt_tune2(tnr_dmd, tune_param);
}
static int cxd2880_dvbt2_tune(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_dvbt2_tune_param
*tune_param)
{
int ret;
if (!tnr_dmd || !tune_param)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
atomic_set(&tnr_dmd->cancel, 0);
if (tune_param->bandwidth != CXD2880_DTV_BW_1_7_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ &&
tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ) {
return -ENOTTY;
}
if (tune_param->profile != CXD2880_DVBT2_PROFILE_BASE &&
tune_param->profile != CXD2880_DVBT2_PROFILE_LITE)
return -EINVAL;
ret = cxd2880_tnrdmd_dvbt2_tune1(tnr_dmd, tune_param);
if (ret)
return ret;
usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
return cxd2880_tnrdmd_dvbt2_tune2(tnr_dmd, tune_param);
}
static int cxd2880_set_frontend(struct dvb_frontend *fe)
{
int ret;
struct dtv_frontend_properties *c;
struct cxd2880_priv *priv;
enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_error.stat[0].uvalue = 0;
c->pre_bit_error.len = 1;
c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.stat[0].uvalue = 0;
c->pre_bit_count.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.stat[0].uvalue = 0;
c->post_bit_error.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].uvalue = 0;
c->post_bit_count.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].uvalue = 0;
c->block_error.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].uvalue = 0;
c->block_count.len = 1;
switch (c->bandwidth_hz) {
case 1712000:
bw = CXD2880_DTV_BW_1_7_MHZ;
break;
case 5000000:
bw = CXD2880_DTV_BW_5_MHZ;
break;
case 6000000:
bw = CXD2880_DTV_BW_6_MHZ;
break;
case 7000000:
bw = CXD2880_DTV_BW_7_MHZ;
break;
case 8000000:
bw = CXD2880_DTV_BW_8_MHZ;
break;
default:
return -EINVAL;
}
priv->s = 0;
pr_info("sys:%d freq:%d bw:%d\n",
c->delivery_system, c->frequency, bw);
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT) {
priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
priv->dvbt_tune_param.center_freq_khz = c->frequency / 1000;
priv->dvbt_tune_param.bandwidth = bw;
priv->dvbt_tune_param.profile = CXD2880_DVBT_PROFILE_HP;
ret = cxd2880_dvbt_tune(&priv->tnrdmd,
&priv->dvbt_tune_param);
} else if (c->delivery_system == SYS_DVBT2) {
priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
priv->dvbt2_tune_param.center_freq_khz = c->frequency / 1000;
priv->dvbt2_tune_param.bandwidth = bw;
priv->dvbt2_tune_param.data_plp_id = (u16)c->stream_id;
priv->dvbt2_tune_param.profile = CXD2880_DVBT2_PROFILE_BASE;
ret = cxd2880_dvbt2_tune(&priv->tnrdmd,
&priv->dvbt2_tune_param);
} else {
pr_err("invalid system\n");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
pr_info("tune result %d\n", ret);
return ret;
}
static int cxd2880_get_stats(struct dvb_frontend *fe,
enum fe_status status)
{
struct cxd2880_priv *priv = NULL;
struct dtv_frontend_properties *c = NULL;
u32 pre_bit_err = 0, pre_bit_count = 0;
u32 post_bit_err = 0, post_bit_count = 0;
u32 block_err = 0, block_count = 0;
int ret;
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
if (!(status & FE_HAS_LOCK) || !(status & FE_HAS_CARRIER)) {
c->pre_bit_error.len = 1;
c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.len = 1;
c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
return 0;
}
if (time_after(jiffies, priv->pre_ber_update)) {
priv->pre_ber_update =
jiffies + msecs_to_jiffies(priv->pre_ber_interval);
if (c->delivery_system == SYS_DVBT) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_pre_bit_err_t(&priv->tnrdmd,
&pre_bit_err,
&pre_bit_count);
mutex_unlock(priv->spi_mutex);
} else if (c->delivery_system == SYS_DVBT2) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
&pre_bit_err,
&pre_bit_count);
mutex_unlock(priv->spi_mutex);
} else {
return -EINVAL;
}
if (!ret) {
c->pre_bit_error.len = 1;
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_error.stat[0].uvalue += pre_bit_err;
c->pre_bit_count.len = 1;
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->pre_bit_count.stat[0].uvalue += pre_bit_count;
} else {
c->pre_bit_error.len = 1;
c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->pre_bit_count.len = 1;
c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("pre_bit_error_t failed %d\n", ret);
}
}
if (time_after(jiffies, priv->post_ber_update)) {
priv->post_ber_update =
jiffies + msecs_to_jiffies(priv->post_ber_interval);
if (c->delivery_system == SYS_DVBT) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
&post_bit_err,
&post_bit_count);
mutex_unlock(priv->spi_mutex);
} else if (c->delivery_system == SYS_DVBT2) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
&post_bit_err,
&post_bit_count);
mutex_unlock(priv->spi_mutex);
} else {
return -EINVAL;
}
if (!ret) {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += post_bit_err;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += post_bit_count;
} else {
c->post_bit_error.len = 1;
c->post_bit_error.stat[0].scale =
FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.len = 1;
c->post_bit_count.stat[0].scale =
FE_SCALE_NOT_AVAILABLE;
pr_debug("post_bit_err_t %d\n", ret);
}
}
if (time_after(jiffies, priv->ucblock_update)) {
priv->ucblock_update =
jiffies + msecs_to_jiffies(priv->ucblock_interval);
if (c->delivery_system == SYS_DVBT) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_read_block_err_t(&priv->tnrdmd,
&block_err,
&block_count);
mutex_unlock(priv->spi_mutex);
} else if (c->delivery_system == SYS_DVBT2) {
mutex_lock(priv->spi_mutex);
ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
&block_err,
&block_count);
mutex_unlock(priv->spi_mutex);
} else {
return -EINVAL;
}
if (!ret) {
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += block_err;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += block_count;
} else {
c->block_error.len = 1;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.len = 1;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("read_block_err_t %d\n", ret);
}
}
return 0;
}
static int cxd2880_check_l1post_plp(struct dvb_frontend *fe)
{
u8 valid = 0;
u8 plp_not_found;
int ret;
struct cxd2880_priv *priv = NULL;
if (!fe) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
ret = cxd2880_tnrdmd_dvbt2_check_l1post_valid(&priv->tnrdmd,
&valid);
if (ret)
return ret;
if (!valid)
return -EAGAIN;
ret = cxd2880_tnrdmd_dvbt2_mon_data_plp_error(&priv->tnrdmd,
&plp_not_found);
if (ret)
return ret;
if (plp_not_found) {
priv->dvbt2_tune_param.tune_info =
CXD2880_TNRDMD_DVBT2_TUNE_INFO_INVALID_PLP_ID;
} else {
priv->dvbt2_tune_param.tune_info =
CXD2880_TNRDMD_DVBT2_TUNE_INFO_OK;
}
return 0;
}
static int cxd2880_read_status(struct dvb_frontend *fe,
enum fe_status *status)
{
int ret;
u8 sync = 0;
u8 lock = 0;
u8 unlock = 0;
struct cxd2880_priv *priv = NULL;
struct dtv_frontend_properties *c = NULL;
if (!fe || !status) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
c = &fe->dtv_property_cache;
*status = 0;
if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT) {
ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(&priv->tnrdmd,
&sync,
&lock,
&unlock);
} else if (c->delivery_system == SYS_DVBT2) {
ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(&priv->tnrdmd,
&sync,
&lock,
&unlock);
} else {
pr_err("invalid system");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
if (ret) {
pr_err("failed. sys = %d\n", priv->tnrdmd.sys);
return ret;
}
if (sync == 6) {
*status = FE_HAS_SIGNAL |
FE_HAS_CARRIER;
}
if (lock)
*status |= FE_HAS_VITERBI |
FE_HAS_SYNC |
FE_HAS_LOCK;
}
pr_debug("status %d\n", *status);
if (priv->s == 0 && (*status & FE_HAS_LOCK) &&
(*status & FE_HAS_CARRIER)) {
mutex_lock(priv->spi_mutex);
if (c->delivery_system == SYS_DVBT) {
ret = cxd2880_set_ber_per_period_t(fe);
priv->s = *status;
} else if (c->delivery_system == SYS_DVBT2) {
ret = cxd2880_check_l1post_plp(fe);
if (!ret) {
ret = cxd2880_set_ber_per_period_t2(fe);
priv->s = *status;
}
} else {
pr_err("invalid system\n");
mutex_unlock(priv->spi_mutex);
return -EINVAL;
}
mutex_unlock(priv->spi_mutex);
}
cxd2880_get_stats(fe, *status);
return 0;
}
static int cxd2880_tune(struct dvb_frontend *fe,
bool retune,
unsigned int mode_flags,
unsigned int *delay,
enum fe_status *status)
{
int ret;
if (!fe || !delay || !status) {
pr_err("invalid arg.");
return -EINVAL;
}
if (retune) {
ret = cxd2880_set_frontend(fe);
if (ret) {
pr_err("cxd2880_set_frontend failed %d\n", ret);
return ret;
}
}
*delay = HZ / 5;
return cxd2880_read_status(fe, status);
}
static int cxd2880_get_frontend_t(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
int ret;
struct cxd2880_priv *priv = NULL;
enum cxd2880_dvbt_mode mode = CXD2880_DVBT_MODE_2K;
enum cxd2880_dvbt_guard guard = CXD2880_DVBT_GUARD_1_32;
struct cxd2880_dvbt_tpsinfo tps;
enum cxd2880_tnrdmd_spectrum_sense sense;
u16 snr = 0;
int strength = 0;
if (!fe || !c) {
pr_err("invalid arg\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
&mode, &guard);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (mode) {
case CXD2880_DVBT_MODE_2K:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case CXD2880_DVBT_MODE_8K:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
c->transmission_mode = TRANSMISSION_MODE_2K;
pr_debug("transmission mode is invalid %d\n", mode);
break;
}
switch (guard) {
case CXD2880_DVBT_GUARD_1_32:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case CXD2880_DVBT_GUARD_1_16:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case CXD2880_DVBT_GUARD_1_8:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case CXD2880_DVBT_GUARD_1_4:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
default:
c->guard_interval = GUARD_INTERVAL_1_32;
pr_debug("guard interval is invalid %d\n",
guard);
break;
}
} else {
c->transmission_mode = TRANSMISSION_MODE_2K;
c->guard_interval = GUARD_INTERVAL_1_32;
pr_debug("ModeGuard err %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (tps.hierarchy) {
case CXD2880_DVBT_HIERARCHY_NON:
c->hierarchy = HIERARCHY_NONE;
break;
case CXD2880_DVBT_HIERARCHY_1:
c->hierarchy = HIERARCHY_1;
break;
case CXD2880_DVBT_HIERARCHY_2:
c->hierarchy = HIERARCHY_2;
break;
case CXD2880_DVBT_HIERARCHY_4:
c->hierarchy = HIERARCHY_4;
break;
default:
c->hierarchy = HIERARCHY_NONE;
pr_debug("TPSInfo hierarchy is invalid %d\n",
tps.hierarchy);
break;
}
switch (tps.rate_hp) {
case CXD2880_DVBT_CODERATE_1_2:
c->code_rate_HP = FEC_1_2;
break;
case CXD2880_DVBT_CODERATE_2_3:
c->code_rate_HP = FEC_2_3;
break;
case CXD2880_DVBT_CODERATE_3_4:
c->code_rate_HP = FEC_3_4;
break;
case CXD2880_DVBT_CODERATE_5_6:
c->code_rate_HP = FEC_5_6;
break;
case CXD2880_DVBT_CODERATE_7_8:
c->code_rate_HP = FEC_7_8;
break;
default:
c->code_rate_HP = FEC_NONE;
pr_debug("TPSInfo rateHP is invalid %d\n",
tps.rate_hp);
break;
}
switch (tps.rate_lp) {
case CXD2880_DVBT_CODERATE_1_2:
c->code_rate_LP = FEC_1_2;
break;
case CXD2880_DVBT_CODERATE_2_3:
c->code_rate_LP = FEC_2_3;
break;
case CXD2880_DVBT_CODERATE_3_4:
c->code_rate_LP = FEC_3_4;
break;
case CXD2880_DVBT_CODERATE_5_6:
c->code_rate_LP = FEC_5_6;
break;
case CXD2880_DVBT_CODERATE_7_8:
c->code_rate_LP = FEC_7_8;
break;
default:
c->code_rate_LP = FEC_NONE;
pr_debug("TPSInfo rateLP is invalid %d\n",
tps.rate_lp);
break;
}
switch (tps.constellation) {
case CXD2880_DVBT_CONSTELLATION_QPSK:
c->modulation = QPSK;
break;
case CXD2880_DVBT_CONSTELLATION_16QAM:
c->modulation = QAM_16;
break;
case CXD2880_DVBT_CONSTELLATION_64QAM:
c->modulation = QAM_64;
break;
default:
c->modulation = QPSK;
pr_debug("TPSInfo constellation is invalid %d\n",
tps.constellation);
break;
}
} else {
c->hierarchy = HIERARCHY_NONE;
c->code_rate_HP = FEC_NONE;
c->code_rate_LP = FEC_NONE;
c->modulation = QPSK;
pr_debug("TPS info err %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (sense) {
case CXD2880_TNRDMD_SPECTRUM_NORMAL:
c->inversion = INVERSION_OFF;
break;
case CXD2880_TNRDMD_SPECTRUM_INV:
c->inversion = INVERSION_ON;
break;
default:
c->inversion = INVERSION_OFF;
pr_debug("spectrum sense is invalid %d\n", sense);
break;
}
} else {
c->inversion = INVERSION_OFF;
pr_debug("spectrum_sense %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
mutex_unlock(priv->spi_mutex);
if (!ret) {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = strength;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("mon_rf_lvl %d\n", ret);
}
ret = cxd2880_read_snr(fe, &snr);
if (!ret) {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = snr;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("read_snr %d\n", ret);
}
return 0;
}
static int cxd2880_get_frontend_t2(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
int ret;
struct cxd2880_priv *priv = NULL;
struct cxd2880_dvbt2_l1pre l1pre;
enum cxd2880_dvbt2_plp_code_rate coderate;
enum cxd2880_dvbt2_plp_constell qam;
enum cxd2880_tnrdmd_spectrum_sense sense;
u16 snr = 0;
int strength = 0;
if (!fe || !c) {
pr_err("invalid arg.\n");
return -EINVAL;
}
priv = fe->demodulator_priv;
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (l1pre.fft_mode) {
case CXD2880_DVBT2_M2K:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case CXD2880_DVBT2_M8K:
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
case CXD2880_DVBT2_M4K:
c->transmission_mode = TRANSMISSION_MODE_4K;
break;
case CXD2880_DVBT2_M1K:
c->transmission_mode = TRANSMISSION_MODE_1K;
break;
case CXD2880_DVBT2_M16K:
c->transmission_mode = TRANSMISSION_MODE_16K;
break;
case CXD2880_DVBT2_M32K:
c->transmission_mode = TRANSMISSION_MODE_32K;
break;
default:
c->transmission_mode = TRANSMISSION_MODE_2K;
pr_debug("L1Pre fft_mode is invalid %d\n",
l1pre.fft_mode);
break;
}
switch (l1pre.gi) {
case CXD2880_DVBT2_G1_32:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case CXD2880_DVBT2_G1_16:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case CXD2880_DVBT2_G1_8:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case CXD2880_DVBT2_G1_4:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
case CXD2880_DVBT2_G1_128:
c->guard_interval = GUARD_INTERVAL_1_128;
break;
case CXD2880_DVBT2_G19_128:
c->guard_interval = GUARD_INTERVAL_19_128;
break;
case CXD2880_DVBT2_G19_256:
c->guard_interval = GUARD_INTERVAL_19_256;
break;
default:
c->guard_interval = GUARD_INTERVAL_1_32;
pr_debug("L1Pre guard interval is invalid %d\n",
l1pre.gi);
break;
}
} else {
c->transmission_mode = TRANSMISSION_MODE_2K;
c->guard_interval = GUARD_INTERVAL_1_32;
pr_debug("L1Pre err %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
CXD2880_DVBT2_PLP_DATA,
&coderate);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (coderate) {
case CXD2880_DVBT2_R1_2:
c->fec_inner = FEC_1_2;
break;
case CXD2880_DVBT2_R3_5:
c->fec_inner = FEC_3_5;
break;
case CXD2880_DVBT2_R2_3:
c->fec_inner = FEC_2_3;
break;
case CXD2880_DVBT2_R3_4:
c->fec_inner = FEC_3_4;
break;
case CXD2880_DVBT2_R4_5:
c->fec_inner = FEC_4_5;
break;
case CXD2880_DVBT2_R5_6:
c->fec_inner = FEC_5_6;
break;
default:
c->fec_inner = FEC_NONE;
pr_debug("CodeRate is invalid %d\n", coderate);
break;
}
} else {
c->fec_inner = FEC_NONE;
pr_debug("CodeRate %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
CXD2880_DVBT2_PLP_DATA,
&qam);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (qam) {
case CXD2880_DVBT2_QPSK:
c->modulation = QPSK;
break;
case CXD2880_DVBT2_QAM16:
c->modulation = QAM_16;
break;
case CXD2880_DVBT2_QAM64:
c->modulation = QAM_64;
break;
case CXD2880_DVBT2_QAM256:
c->modulation = QAM_256;
break;
default:
c->modulation = QPSK;
pr_debug("QAM is invalid %d\n", qam);
break;
}
} else {
c->modulation = QPSK;
pr_debug("QAM %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
mutex_unlock(priv->spi_mutex);
if (!ret) {
switch (sense) {
case CXD2880_TNRDMD_SPECTRUM_NORMAL:
c->inversion = INVERSION_OFF;
break;
case CXD2880_TNRDMD_SPECTRUM_INV:
c->inversion = INVERSION_ON;
break;
default:
c->inversion = INVERSION_OFF;
pr_debug("spectrum sense is invalid %d\n", sense);
break;
}
} else {
c->inversion = INVERSION_OFF;
pr_debug("SpectrumSense %d\n", ret);
}
mutex_lock(priv->spi_mutex);
ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
mutex_unlock(priv->spi_mutex);
if (!ret) {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = strength;
} else {
c->strength.len = 1;
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("mon_rf_lvl %d\n", ret);
}
ret = cxd2880_read_snr(fe, &snr);
if (!ret) {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = snr;
} else {
c->cnr.len = 1;
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
pr_debug("read_snr %d\n", ret);
}
return 0;
}
static int cxd2880_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *props)
{
int ret;
if (!fe || !props) {
pr_err("invalid arg.");
return -EINVAL;
}
pr_debug("system=%d\n", fe->dtv_property_cache.delivery_system);
switch (fe->dtv_property_cache.delivery_system) {
case SYS_DVBT:
ret = cxd2880_get_frontend_t(fe, props);
break;
case SYS_DVBT2:
ret = cxd2880_get_frontend_t2(fe, props);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static enum dvbfe_algo cxd2880_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static struct dvb_frontend_ops cxd2880_dvbt_t2_ops = {
.info = {
.name = "Sony CXD2880",
.frequency_min_hz = 174 * MHz,
.frequency_max_hz = 862 * MHz,
.frequency_stepsize_hz = 1 * kHz,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_4_5 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_2G_MODULATION |
FE_CAN_RECOVER |
FE_CAN_MUTE_TS,
},
.delsys = { SYS_DVBT, SYS_DVBT2 },
.release = cxd2880_release,
.init = cxd2880_init,
.sleep = cxd2880_sleep,
.tune = cxd2880_tune,
.set_frontend = cxd2880_set_frontend,
.get_frontend = cxd2880_get_frontend,
.read_status = cxd2880_read_status,
.read_ber = cxd2880_read_ber,
.read_signal_strength = cxd2880_read_signal_strength,
.read_snr = cxd2880_read_snr,
.read_ucblocks = cxd2880_read_ucblocks,
.get_frontend_algo = cxd2880_get_frontend_algo,
};
struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe,
struct cxd2880_config *cfg)
{
int ret;
enum cxd2880_tnrdmd_chip_id chipid =
CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
static struct cxd2880_priv *priv;
u8 data = 0;
if (!fe) {
pr_err("invalid arg.\n");
return NULL;
}
priv = kzalloc(sizeof(struct cxd2880_priv), GFP_KERNEL);
if (!priv)
return NULL;
priv->spi = cfg->spi;
priv->spi_mutex = cfg->spi_mutex;
priv->spi_device.spi = cfg->spi;
memcpy(&fe->ops, &cxd2880_dvbt_t2_ops,
sizeof(struct dvb_frontend_ops));
ret = cxd2880_spi_device_initialize(&priv->spi_device,
CXD2880_SPI_MODE_0,
55000000);
if (ret) {
pr_err("spi_device_initialize failed. %d\n", ret);
kfree(priv);
return NULL;
}
ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
&priv->spi_device);
if (ret) {
pr_err("spi_device_create_spi failed. %d\n", ret);
kfree(priv);
return NULL;
}
ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
if (ret) {
pr_err("io_spi_create failed. %d\n", ret);
kfree(priv);
return NULL;
}
ret = priv->regio.write_reg(&priv->regio,
CXD2880_IO_TGT_SYS, 0x00, 0x00);
if (ret) {
pr_err("set bank to 0x00 failed.\n");
kfree(priv);
return NULL;
}
ret = priv->regio.read_regs(&priv->regio,
CXD2880_IO_TGT_SYS, 0xfd, &data, 1);
if (ret) {
pr_err("read chip id failed.\n");
kfree(priv);
return NULL;
}
chipid = (enum cxd2880_tnrdmd_chip_id)data;
if (chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X &&
chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11) {
pr_err("chip id invalid.\n");
kfree(priv);
return NULL;
}
fe->demodulator_priv = priv;
pr_info("CXD2880 driver version: Ver %s\n",
CXD2880_TNRDMD_DRIVER_VERSION);
return fe;
}
EXPORT_SYMBOL_GPL(cxd2880_attach);
MODULE_DESCRIPTION("Sony CXD2880 DVB-T2/T tuner + demod driver");
MODULE_AUTHOR("Sony Semiconductor Solutions Corporation");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_top.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cxd2880_tnrdmd.c
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
* common control functions
*
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
*/
#include <media/dvb_frontend.h>
#include "cxd2880_common.h"
#include "cxd2880_tnrdmd.h"
#include "cxd2880_tnrdmd_mon.h"
#include "cxd2880_tnrdmd_dvbt.h"
#include "cxd2880_tnrdmd_dvbt2.h"
static const struct cxd2880_reg_value p_init1_seq[] = {
{0x11, 0x16}, {0x00, 0x10},
};
static const struct cxd2880_reg_value rf_init1_seq1[] = {
{0x4f, 0x18}, {0x61, 0x00}, {0x71, 0x00}, {0x9d, 0x01},
{0x7d, 0x02}, {0x8f, 0x01}, {0x8b, 0xc6}, {0x9a, 0x03},
{0x1c, 0x00},
};
static const struct cxd2880_reg_value rf_init1_seq2[] = {
{0xb9, 0x07}, {0x33, 0x01}, {0xc1, 0x01}, {0xc4, 0x1e},
};
static const struct cxd2880_reg_value rf_init1_seq3[] = {
{0x00, 0x10}, {0x51, 0x01}, {0xc5, 0x07}, {0x00, 0x11},
{0x70, 0xe9}, {0x76, 0x0a}, {0x78, 0x32}, {0x7a, 0x46},
{0x7c, 0x86}, {0x7e, 0xa4}, {0x00, 0x10}, {0xe1, 0x01},
};
static const struct cxd2880_reg_value rf_init1_seq4[] = {
{0x15, 0x00}, {0x00, 0x16}
};
static const struct cxd2880_reg_value rf_init1_seq5[] = {
{0x00, 0x00}, {0x25, 0x00}
};
static const struct cxd2880_reg_value rf_init1_seq6[] = {
{0x02, 0x00}, {0x00, 0x00}, {0x21, 0x01}, {0x00, 0xe1},
{0x8f, 0x16}, {0x67, 0x60}, {0x6a, 0x0f}, {0x6c, 0x17}
};
static const struct cxd2880_reg_value rf_init1_seq7[] = {
{0x00, 0xe2}, {0x41, 0xa0}, {0x4b, 0x68}, {0x00, 0x00},
{0x21, 0x00}, {0x10, 0x01},
};
static const struct cxd2880_reg_value rf_init1_seq8[] = {
{0x00, 0x10}, {0x25, 0x01},
};
static const struct cxd2880_reg_value rf_init1_seq9[] = {
{0x00, 0x10}, {0x14, 0x01}, {0x00, 0x00}, {0x26, 0x00},
};
static const struct cxd2880_reg_value rf_init2_seq1[] = {
{0x00, 0x14}, {0x1b, 0x01},
};
static const struct cxd2880_reg_value rf_init2_seq2[] = {
{0x00, 0x00}, {0x21, 0x01}, {0x00, 0xe1}, {0xd3, 0x00},
{0x00, 0x00}, {0x21, 0x00},
};
static const struct cxd2880_reg_value x_tune1_seq1[] = {
{0x00, 0x00}, {0x10, 0x01},
};
static const struct cxd2880_reg_value x_tune1_seq2[] = {
{0x62, 0x00}, {0x00, 0x15},
};
static const struct cxd2880_reg_value x_tune2_seq1[] = {
{0x00, 0x1a}, {0x29, 0x01},
};
static const struct cxd2880_reg_value x_tune2_seq2[] = {
{0x62, 0x01}, {0x00, 0x11}, {0x2d, 0x00}, {0x2f, 0x00},
};
static const struct cxd2880_reg_value x_tune2_seq3[] = {
{0x00, 0x00}, {0x10, 0x00}, {0x21, 0x01},
};
static const struct cxd2880_reg_value x_tune2_seq4[] = {
{0x00, 0xe1}, {0x8a, 0x87},
};
static const struct cxd2880_reg_value x_tune2_seq5[] = {
{0x00, 0x00}, {0x21, 0x00},
};
static const struct cxd2880_reg_value x_tune3_seq[] = {
{0x00, 0x00}, {0x21, 0x01}, {0x00, 0xe2}, {0x41, 0xa0},
{0x00, 0x00}, {0x21, 0x00}, {0xfe, 0x01},
};
static const struct cxd2880_reg_value x_tune4_seq[] = {
{0x00, 0x00}, {0xfe, 0x01},
};
static const struct cxd2880_reg_value x_sleep1_seq[] = {
{0x00, 0x00}, {0x57, 0x03},
};
static const struct cxd2880_reg_value x_sleep2_seq1[] = {
{0x00, 0x2d}, {0xb1, 0x01},
};
static const struct cxd2880_reg_value x_sleep2_seq2[] = {
{0x00, 0x10}, {0xf4, 0x00}, {0xf3, 0x00}, {0xf2, 0x00},
{0xf1, 0x00}, {0xf0, 0x00}, {0xef, 0x00},
};
static const struct cxd2880_reg_value x_sleep3_seq[] = {
{0x00, 0x00}, {0xfd, 0x00},
};
static const struct cxd2880_reg_value x_sleep4_seq[] = {
{0x00, 0x00}, {0x21, 0x01}, {0x00, 0xe2}, {0x41, 0x00},
{0x00, 0x00}, {0x21, 0x00},
};
static const struct cxd2880_reg_value spll_reset_seq1[] = {
{0x00, 0x10}, {0x29, 0x01}, {0x28, 0x01}, {0x27, 0x01},
{0x26, 0x01},
};
static const struct cxd2880_reg_value spll_reset_seq2[] = {
{0x00, 0x00}, {0x10, 0x00},
};
static const struct cxd2880_reg_value spll_reset_seq3[] = {
{0x00, 0x00}, {0x27, 0x00}, {0x22, 0x01},
};
static const struct cxd2880_reg_value spll_reset_seq4[] = {
{0x00, 0x00}, {0x27, 0x01},
};
static const struct cxd2880_reg_value spll_reset_seq5[] = {
{0x00, 0x00}, {0x10, 0x01},
};
static const struct cxd2880_reg_value t_power_x_seq1[] = {
{0x00, 0x10}, {0x29, 0x01}, {0x28, 0x01}, {0x27, 0x01},
};
static const struct cxd2880_reg_value t_power_x_seq2[] = {
{0x00, 0x00}, {0x10, 0x00},
};
static const struct cxd2880_reg_value t_power_x_seq3[] = {
{0x00, 0x00}, {0x27, 0x00}, {0x25, 0x01},
};
static const struct cxd2880_reg_value t_power_x_seq4[] = {
{0x00, 0x00}, {0x2a, 0x00},
};
static const struct cxd2880_reg_value t_power_x_seq5[] = {
{0x00, 0x00}, {0x25, 0x00},
};
static const struct cxd2880_reg_value t_power_x_seq6[] = {
{0x00, 0x00}, {0x27, 0x01},
};
static const struct cxd2880_reg_value t_power_x_seq7[] = {
{0x00, 0x00}, {0x10, 0x01},
};
static const struct cxd2880_reg_value set_ts_pin_seq[] = {
{0x50, 0x3f}, {0x52, 0x1f},
};
static const struct cxd2880_reg_value set_ts_output_seq1[] = {
{0x00, 0x00}, {0x52, 0x00},
};
static const struct cxd2880_reg_value set_ts_output_seq2[] = {
{0x00, 0x00}, {0xc3, 0x00},
};
static const struct cxd2880_reg_value set_ts_output_seq3[] = {
{0x00, 0x00}, {0xc3, 0x01},
};
static const struct cxd2880_reg_value set_ts_output_seq4[] = {
{0x00, 0x00}, {0x52, 0x1f},
};
static int p_init1(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data = 0;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE ||
tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
switch (tnr_dmd->create_param.ts_output_if) {
case CXD2880_TNRDMD_TSOUT_IF_TS:
data = 0x00;
break;
case CXD2880_TNRDMD_TSOUT_IF_SPI:
data = 0x01;
break;
case CXD2880_TNRDMD_TSOUT_IF_SDIO:
data = 0x02;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data);
if (ret)
return ret;
}
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
p_init1_seq,
ARRAY_SIZE(p_init1_seq));
if (ret)
return ret;
switch (tnr_dmd->chip_id) {
case CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X:
data = 0x1a;
break;
case CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11:
data = 0x16;
break;
default:
return -ENOTTY;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data);
if (ret)
return ret;
if (tnr_dmd->create_param.en_internal_ldo)
data = 0x01;
else
data = 0x00;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x11, data);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x13, data);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x12, data);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
switch (tnr_dmd->chip_id) {
case CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X:
data = 0x01;
break;
case CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11:
data = 0x00;
break;
default:
return -ENOTTY;
}
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x69, data);
}
static int p_init2(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[6] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = tnr_dmd->create_param.xosc_cap;
data[1] = tnr_dmd->create_param.xosc_i;
switch (tnr_dmd->create_param.xtal_share_type) {
case CXD2880_TNRDMD_XTAL_SHARE_NONE:
data[2] = 0x01;
data[3] = 0x00;
break;
case CXD2880_TNRDMD_XTAL_SHARE_EXTREF:
data[2] = 0x00;
data[3] = 0x00;
break;
case CXD2880_TNRDMD_XTAL_SHARE_MASTER:
data[2] = 0x01;
data[3] = 0x01;
break;
case CXD2880_TNRDMD_XTAL_SHARE_SLAVE:
data[2] = 0x00;
data[3] = 0x01;
break;
default:
return -EINVAL;
}
data[4] = 0x06;
data[5] = 0x00;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x13, data, 6);
}
static int p_init3(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[2] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
switch (tnr_dmd->diver_mode) {
case CXD2880_TNRDMD_DIVERMODE_SINGLE:
data[0] = 0x00;
break;
case CXD2880_TNRDMD_DIVERMODE_MAIN:
data[0] = 0x03;
break;
case CXD2880_TNRDMD_DIVERMODE_SUB:
data[0] = 0x02;
break;
default:
return -EINVAL;
}
data[1] = 0x01;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x1f, data, 2);
}
static int rf_init1(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[8] = { 0 };
static const u8 rf_init1_cdata1[40] = {
0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
0x05, 0x05, 0x04, 0x04, 0x04, 0x03, 0x03,
0x03, 0x04, 0x04, 0x05, 0x05, 0x05, 0x02,
0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
0x02, 0x03, 0x02, 0x01, 0x01, 0x01, 0x02,
0x02, 0x03, 0x04, 0x04, 0x04
};
static const u8 rf_init1_cdata2[5] = {0xff, 0x00, 0x00, 0x00, 0x00};
static const u8 rf_init1_cdata3[80] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
0x01, 0x00, 0x02, 0x00, 0x63, 0x00, 0x00,
0x00, 0x03, 0x00, 0x04, 0x00, 0x04, 0x00,
0x06, 0x00, 0x06, 0x00, 0x08, 0x00, 0x09,
0x00, 0x0b, 0x00, 0x0b, 0x00, 0x0d, 0x00,
0x0d, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x0f,
0x00, 0x10, 0x00, 0x79, 0x00, 0x00, 0x00,
0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01,
0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x04, 0x00, 0x04, 0x00, 0x06, 0x00, 0x05,
0x00, 0x07, 0x00, 0x07, 0x00, 0x08, 0x00,
0x0a, 0x03, 0xe0
};
static const u8 rf_init1_cdata4[8] = {
0x20, 0x20, 0x30, 0x41, 0x50, 0x5f, 0x6f, 0x80
};
static const u8 rf_init1_cdata5[50] = {
0x00, 0x09, 0x00, 0x08, 0x00, 0x07, 0x00,
0x06, 0x00, 0x05, 0x00, 0x03, 0x00, 0x02,
0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00,
0x06, 0x00, 0x08, 0x00, 0x08, 0x00, 0x0c,
0x00, 0x0c, 0x00, 0x0d, 0x00, 0x0f, 0x00,
0x0e, 0x00, 0x0e, 0x00, 0x10, 0x00, 0x0f,
0x00, 0x0e, 0x00, 0x10, 0x00, 0x0f, 0x00,
0x0e
};
u8 addr = 0;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x01;
data[1] = 0x00;
data[2] = 0x01;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x21, data, 3);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
data[0] = 0x01;
data[1] = 0x01;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x17, data, 2);
if (ret)
return ret;
if (tnr_dmd->create_param.stationary_use) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x1a, 0x06);
if (ret)
return ret;
}
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq1,
ARRAY_SIZE(rf_init1_seq1));
if (ret)
return ret;
data[0] = 0x00;
if (tnr_dmd->create_param.is_cxd2881gg &&
tnr_dmd->create_param.xtal_share_type ==
CXD2880_TNRDMD_XTAL_SHARE_SLAVE)
data[1] = 0x00;
else
data[1] = 0x1f;
data[2] = 0x0a;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xb5, data, 3);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq2,
ARRAY_SIZE(rf_init1_seq2));
if (ret)
return ret;
if (tnr_dmd->chip_id == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) {
data[0] = 0x34;
data[1] = 0x2c;
} else {
data[0] = 0x2f;
data[1] = 0x25;
}
data[2] = 0x15;
data[3] = 0x19;
data[4] = 0x1b;
data[5] = 0x15;
data[6] = 0x19;
data[7] = 0x1b;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xd9, data, 8);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x11);
if (ret)
return ret;
data[0] = 0x6c;
data[1] = 0x10;
data[2] = 0xa6;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x44, data, 3);
if (ret)
return ret;
data[0] = 0x16;
data[1] = 0xa8;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x50, data, 2);
if (ret)
return ret;
data[0] = 0x00;
data[1] = 0x22;
data[2] = 0x00;
data[3] = 0x88;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x62, data, 4);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x74, 0x75);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x7f, rf_init1_cdata1, 40);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x16);
if (ret)
return ret;
data[0] = 0x00;
data[1] = 0x71;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x23, 0x89);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x27, rf_init1_cdata2, 5);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x3a, rf_init1_cdata3, 80);
if (ret)
return ret;
data[0] = 0x03;
data[1] = 0xe0;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xbc, data, 2);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq3,
ARRAY_SIZE(rf_init1_seq3));
if (ret)
return ret;
if (tnr_dmd->create_param.stationary_use) {
data[0] = 0x06;
data[1] = 0x07;
data[2] = 0x1a;
} else {
data[0] = 0x00;
data[1] = 0x08;
data[2] = 0x19;
}
data[3] = 0x0e;
data[4] = 0x09;
data[5] = 0x0e;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x12);
if (ret)
return ret;
for (addr = 0x10; addr < 0x9f; addr += 6) {
if (tnr_dmd->lna_thrs_tbl_air) {
u8 idx = 0;
idx = (addr - 0x10) / 6;
data[0] =
tnr_dmd->lna_thrs_tbl_air->thrs[idx].off_on;
data[1] =
tnr_dmd->lna_thrs_tbl_air->thrs[idx].on_off;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
addr, data, 6);
if (ret)
return ret;
}
data[0] = 0x00;
data[1] = 0x08;
if (tnr_dmd->create_param.stationary_use)
data[2] = 0x1a;
else
data[2] = 0x19;
data[3] = 0x0e;
data[4] = 0x09;
data[5] = 0x0e;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x13);
if (ret)
return ret;
for (addr = 0x10; addr < 0xcf; addr += 6) {
if (tnr_dmd->lna_thrs_tbl_cable) {
u8 idx = 0;
idx = (addr - 0x10) / 6;
data[0] =
tnr_dmd->lna_thrs_tbl_cable->thrs[idx].off_on;
data[1] =
tnr_dmd->lna_thrs_tbl_cable->thrs[idx].on_off;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
addr, data, 6);
if (ret)
return ret;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x11);
if (ret)
return ret;
data[0] = 0x08;
data[1] = 0x09;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xbd, data, 2);
if (ret)
return ret;
data[0] = 0x08;
data[1] = 0x09;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xc4, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xc9, rf_init1_cdata4, 8);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x14);
if (ret)
return ret;
data[0] = 0x15;
data[1] = 0x18;
data[2] = 0x00;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data, 3);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq4,
ARRAY_SIZE(rf_init1_seq4));
if (ret)
return ret;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x12, rf_init1_cdata5, 50);
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0x00)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq5,
ARRAY_SIZE(rf_init1_seq5));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x11, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0x00)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
rf_init1_seq6,
ARRAY_SIZE(rf_init1_seq6));
if (ret)
return ret;
data[0] = 0x00;
data[1] = 0xfe;
data[2] = 0xee;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x6e, data, 3);
if (ret)
return ret;
data[0] = 0xa1;
data[1] = 0x8b;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x8d, data, 2);
if (ret)
return ret;
data[0] = 0x08;
data[1] = 0x09;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x77, data, 2);
if (ret)
return ret;
if (tnr_dmd->create_param.stationary_use) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x80, 0xaa);
if (ret)
return ret;
}
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
rf_init1_seq7,
ARRAY_SIZE(rf_init1_seq7));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq8,
ARRAY_SIZE(rf_init1_seq8));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x1a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0x00)
return -EINVAL;
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init1_seq9,
ARRAY_SIZE(rf_init1_seq9));
}
static int rf_init2(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[5] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
data[0] = 0x40;
data[1] = 0x40;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xea, data, 2);
if (ret)
return ret;
usleep_range(1000, 2000);
data[0] = 0x00;
if (tnr_dmd->chip_id == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X)
data[1] = 0x00;
else
data[1] = 0x01;
data[2] = 0x01;
data[3] = 0x03;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x30, data, 4);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
rf_init2_seq1,
ARRAY_SIZE(rf_init2_seq1));
if (ret)
return ret;
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
rf_init2_seq2,
ARRAY_SIZE(rf_init2_seq2));
}
static int x_tune1(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_sys sys, u32 freq_khz,
enum cxd2880_dtv_bandwidth bandwidth,
u8 is_cable, int shift_frequency_khz)
{
u8 data[11] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune1_seq1,
ARRAY_SIZE(x_tune1_seq1));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
data[2] = 0x0e;
data[4] = 0x03;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xe7, data, 5);
if (ret)
return ret;
data[0] = 0x1f;
data[1] = 0x80;
data[2] = 0x18;
data[3] = 0x00;
data[4] = 0x07;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xe7, data, 5);
if (ret)
return ret;
usleep_range(1000, 2000);
data[0] = 0x72;
data[1] = 0x81;
data[3] = 0x1d;
data[4] = 0x6f;
data[5] = 0x7e;
data[7] = 0x1c;
switch (sys) {
case CXD2880_DTV_SYS_DVBT:
data[2] = 0x94;
data[6] = 0x91;
break;
case CXD2880_DTV_SYS_DVBT2:
data[2] = 0x96;
data[6] = 0x93;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x44, data, 8);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
x_tune1_seq2,
ARRAY_SIZE(x_tune1_seq2));
if (ret)
return ret;
data[0] = 0x03;
data[1] = 0xe2;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x1e, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
data[0] = is_cable ? 0x01 : 0x00;
data[1] = 0x00;
data[2] = 0x6b;
data[3] = 0x4d;
switch (bandwidth) {
case CXD2880_DTV_BW_1_7_MHZ:
data[4] = 0x03;
break;
case CXD2880_DTV_BW_5_MHZ:
case CXD2880_DTV_BW_6_MHZ:
data[4] = 0x00;
break;
case CXD2880_DTV_BW_7_MHZ:
data[4] = 0x01;
break;
case CXD2880_DTV_BW_8_MHZ:
data[4] = 0x02;
break;
default:
return -EINVAL;
}
data[5] = 0x00;
freq_khz += shift_frequency_khz;
data[6] = (freq_khz >> 16) & 0x0f;
data[7] = (freq_khz >> 8) & 0xff;
data[8] = freq_khz & 0xff;
data[9] = 0xff;
data[10] = 0xfe;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x52, data, 11);
}
static int x_tune2(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_bandwidth bandwidth,
enum cxd2880_tnrdmd_clockmode clk_mode,
int shift_frequency_khz)
{
u8 data[3] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x11);
if (ret)
return ret;
data[0] = 0x01;
data[1] = 0x0e;
data[2] = 0x01;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x2d, data, 3);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
x_tune2_seq1,
ARRAY_SIZE(x_tune2_seq1));
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x2c, data, 1);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x60, data[0]);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
x_tune2_seq2,
ARRAY_SIZE(x_tune2_seq2));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune2_seq3,
ARRAY_SIZE(x_tune2_seq3));
if (ret)
return ret;
if (shift_frequency_khz != 0) {
int shift_freq = 0;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0xe1);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 2);
if (ret)
return ret;
shift_freq = shift_frequency_khz * 1000;
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
default:
if (shift_freq >= 0)
shift_freq = (shift_freq + 183 / 2) / 183;
else
shift_freq = (shift_freq - 183 / 2) / 183;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
if (shift_freq >= 0)
shift_freq = (shift_freq + 178 / 2) / 178;
else
shift_freq = (shift_freq - 178 / 2) / 178;
break;
}
shift_freq +=
cxd2880_convert2s_complement((data[0] << 8) | data[1], 16);
if (shift_freq > 32767)
shift_freq = 32767;
else if (shift_freq < -32768)
shift_freq = -32768;
data[0] = (shift_freq >> 8) & 0xff;
data[1] = shift_freq & 0xff;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x60, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x69, data, 1);
if (ret)
return ret;
shift_freq = -shift_frequency_khz;
if (bandwidth == CXD2880_DTV_BW_1_7_MHZ) {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
default:
if (shift_freq >= 0)
shift_freq =
(shift_freq * 1000 +
17578 / 2) / 17578;
else
shift_freq =
(shift_freq * 1000 -
17578 / 2) / 17578;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
if (shift_freq >= 0)
shift_freq =
(shift_freq * 1000 +
17090 / 2) / 17090;
else
shift_freq =
(shift_freq * 1000 -
17090 / 2) / 17090;
break;
}
} else {
switch (clk_mode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
case CXD2880_TNRDMD_CLOCKMODE_C:
default:
if (shift_freq >= 0)
shift_freq =
(shift_freq * 1000 +
35156 / 2) / 35156;
else
shift_freq =
(shift_freq * 1000 -
35156 / 2) / 35156;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
if (shift_freq >= 0)
shift_freq =
(shift_freq * 1000 +
34180 / 2) / 34180;
else
shift_freq =
(shift_freq * 1000 -
34180 / 2) / 34180;
break;
}
}
shift_freq += cxd2880_convert2s_complement(data[0], 8);
if (shift_freq > 127)
shift_freq = 127;
else if (shift_freq < -128)
shift_freq = -128;
data[0] = shift_freq & 0xff;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x69, data[0]);
if (ret)
return ret;
}
if (tnr_dmd->create_param.stationary_use) {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune2_seq4,
ARRAY_SIZE(x_tune2_seq4));
if (ret)
return ret;
}
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune2_seq5,
ARRAY_SIZE(x_tune2_seq5));
}
static int x_tune3(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_sys sys,
u8 en_fef_intmtnt_ctrl)
{
u8 data[6] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune3_seq,
ARRAY_SIZE(x_tune3_seq));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
if (sys == CXD2880_DTV_SYS_DVBT2 && en_fef_intmtnt_ctrl)
memset(data, 0x01, sizeof(data));
else
memset(data, 0x00, sizeof(data));
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xef, data, 6);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x2d);
if (ret)
return ret;
if (sys == CXD2880_DTV_SYS_DVBT2 && en_fef_intmtnt_ctrl)
data[0] = 0x00;
else
data[0] = 0x01;
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb1, data[0]);
}
static int x_tune4(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[2] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
ret = tnr_dmd->diver_sub->io->write_reg(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x14;
data[1] = 0x00;
ret = tnr_dmd->diver_sub->io->write_regs(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x55, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x0b;
data[1] = 0xff;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x53, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x57, 0x01);
if (ret)
return ret;
data[0] = 0x0b;
data[1] = 0xff;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x55, data, 2);
if (ret)
return ret;
ret = tnr_dmd->diver_sub->io->write_reg(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x14;
data[1] = 0x00;
ret = tnr_dmd->diver_sub->io->write_regs(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x53, data, 2);
if (ret)
return ret;
ret = tnr_dmd->diver_sub->io->write_reg(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x57, 0x02);
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_tune4_seq,
ARRAY_SIZE(x_tune4_seq));
if (ret)
return ret;
return cxd2880_io_write_multi_regs(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_DMD,
x_tune4_seq,
ARRAY_SIZE(x_tune4_seq));
}
static int x_sleep1(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data[3] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
x_sleep1_seq,
ARRAY_SIZE(x_sleep1_seq));
if (ret)
return ret;
data[0] = 0x00;
data[1] = 0x00;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x53, data, 2);
if (ret)
return ret;
ret = tnr_dmd->diver_sub->io->write_reg(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x1f;
data[1] = 0xff;
data[2] = 0x03;
ret = tnr_dmd->diver_sub->io->write_regs(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x55, data, 3);
if (ret)
return ret;
data[0] = 0x00;
data[1] = 0x00;
ret = tnr_dmd->diver_sub->io->write_regs(tnr_dmd->diver_sub->io,
CXD2880_IO_TGT_SYS,
0x53, data, 2);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = 0x1f;
data[1] = 0xff;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x55, data, 2);
}
static int x_sleep2(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data = 0;
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_sleep2_seq1,
ARRAY_SIZE(x_sleep2_seq1));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xb2, &data, 1);
if (ret)
return ret;
if ((data & 0x01) == 0x00)
return -EINVAL;
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
x_sleep2_seq2,
ARRAY_SIZE(x_sleep2_seq2));
}
static int x_sleep3(struct cxd2880_tnrdmd *tnr_dmd)
{
if (!tnr_dmd)
return -EINVAL;
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_sleep3_seq,
ARRAY_SIZE(x_sleep3_seq));
}
static int x_sleep4(struct cxd2880_tnrdmd *tnr_dmd)
{
if (!tnr_dmd)
return -EINVAL;
return cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
x_sleep4_seq,
ARRAY_SIZE(x_sleep4_seq));
}
static int spll_reset(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_tnrdmd_clockmode clockmode)
{
u8 data[4] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
spll_reset_seq1,
ARRAY_SIZE(spll_reset_seq1));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
spll_reset_seq2,
ARRAY_SIZE(spll_reset_seq2));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
spll_reset_seq3,
ARRAY_SIZE(spll_reset_seq3));
if (ret)
return ret;
switch (clockmode) {
case CXD2880_TNRDMD_CLOCKMODE_A:
data[0] = 0x00;
break;
case CXD2880_TNRDMD_CLOCKMODE_B:
data[0] = 0x01;
break;
case CXD2880_TNRDMD_CLOCKMODE_C:
data[0] = 0x02;
break;
default:
return -EINVAL;
}
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x30, data[0]);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x22, 0x00);
if (ret)
return ret;
usleep_range(2000, 3000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x10, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0x00)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
spll_reset_seq4,
ARRAY_SIZE(spll_reset_seq4));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
spll_reset_seq5,
ARRAY_SIZE(spll_reset_seq5));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
memset(data, 0x00, sizeof(data));
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x26, data, 4);
}
static int t_power_x(struct cxd2880_tnrdmd *tnr_dmd, u8 on)
{
u8 data[3] = { 0 };
int ret;
if (!tnr_dmd)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
t_power_x_seq1,
ARRAY_SIZE(t_power_x_seq1));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
t_power_x_seq2,
ARRAY_SIZE(t_power_x_seq2));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
t_power_x_seq3,
ARRAY_SIZE(t_power_x_seq3));
if (ret)
return ret;
if (on) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x2b, 0x01);
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x12, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
t_power_x_seq4,
ARRAY_SIZE(t_power_x_seq4));
if (ret)
return ret;
} else {
data[0] = 0x03;
data[1] = 0x00;
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x2a, data, 2);
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x13, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0)
return -EINVAL;
}
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
t_power_x_seq5,
ARRAY_SIZE(t_power_x_seq5));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x11, data, 1);
if (ret)
return ret;
if ((data[0] & 0x01) == 0)
return -EINVAL;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
t_power_x_seq6,
ARRAY_SIZE(t_power_x_seq6));
if (ret)
return ret;
usleep_range(1000, 2000);
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
t_power_x_seq7,
ARRAY_SIZE(t_power_x_seq7));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x10);
if (ret)
return ret;
memset(data, 0x00, sizeof(data));
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x27, data, 3);
}
struct cxd2880_tnrdmd_ts_clk_cfg {
u8 srl_clk_mode;
u8 srl_duty_mode;
u8 ts_clk_period;
};
static int set_ts_clk_mode_and_freq(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_sys sys)
{
int ret;
u8 backwards_compatible = 0;
struct cxd2880_tnrdmd_ts_clk_cfg ts_clk_cfg;
u8 ts_rate_ctrl_off = 0;
u8 ts_in_off = 0;
u8 ts_clk_manaul_on = 0;
u8 data = 0;
static const struct cxd2880_tnrdmd_ts_clk_cfg srl_ts_clk_stgs[2][2] = {
{
{3, 1, 8,},
{0, 2, 16,}
}, {
{1, 1, 8,},
{2, 2, 16,}
}
};
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
if (tnr_dmd->is_ts_backwards_compatible_mode) {
backwards_compatible = 1;
ts_rate_ctrl_off = 1;
ts_in_off = 1;
} else {
backwards_compatible = 0;
ts_rate_ctrl_off = 0;
ts_in_off = 0;
}
if (tnr_dmd->ts_byte_clk_manual_setting) {
ts_clk_manaul_on = 1;
ts_rate_ctrl_off = 0;
}
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xd3, ts_rate_ctrl_off, 0x01);
if (ret)
return ret;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xde, ts_in_off, 0x01);
if (ret)
return ret;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xda, ts_clk_manaul_on, 0x01);
if (ret)
return ret;
ts_clk_cfg = srl_ts_clk_stgs[tnr_dmd->srl_ts_clk_mod_cnts]
[tnr_dmd->srl_ts_clk_frq];
if (tnr_dmd->ts_byte_clk_manual_setting)
ts_clk_cfg.ts_clk_period = tnr_dmd->ts_byte_clk_manual_setting;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xc4, ts_clk_cfg.srl_clk_mode, 0x03);
if (ret)
return ret;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0xd1, ts_clk_cfg.srl_duty_mode, 0x03);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD, 0xd9,
ts_clk_cfg.ts_clk_period);
if (ret)
return ret;
data = backwards_compatible ? 0x00 : 0x01;
if (sys == CXD2880_DTV_SYS_DVBT) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x10);
if (ret)
return ret;
ret =
cxd2880_io_set_reg_bits(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x66, data, 0x01);
}
return ret;
}
static int pid_ftr_setting(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_tnrdmd_pid_ftr_cfg
*pid_ftr_cfg)
{
int i;
int ret;
u8 data[65];
if (!tnr_dmd)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
if (!pid_ftr_cfg)
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x50, 0x02);
data[0] = pid_ftr_cfg->is_negative ? 0x01 : 0x00;
for (i = 0; i < 32; i++) {
if (pid_ftr_cfg->pid_cfg[i].is_en) {
data[1 + (i * 2)] = (pid_ftr_cfg->pid_cfg[i].pid >> 8) | 0x20;
data[2 + (i * 2)] = pid_ftr_cfg->pid_cfg[i].pid & 0xff;
} else {
data[1 + (i * 2)] = 0x00;
data[2 + (i * 2)] = 0x00;
}
}
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x50, data, 65);
}
static int load_cfg_mem(struct cxd2880_tnrdmd *tnr_dmd)
{
int ret;
u8 i;
if (!tnr_dmd)
return -EINVAL;
for (i = 0; i < tnr_dmd->cfg_mem_last_entry; i++) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
tnr_dmd->cfg_mem[i].tgt,
0x00, tnr_dmd->cfg_mem[i].bank);
if (ret)
return ret;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
tnr_dmd->cfg_mem[i].tgt,
tnr_dmd->cfg_mem[i].address,
tnr_dmd->cfg_mem[i].value,
tnr_dmd->cfg_mem[i].bit_mask);
if (ret)
return ret;
}
return 0;
}
static int set_cfg_mem(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_io_tgt tgt,
u8 bank, u8 address, u8 value, u8 bit_mask)
{
u8 i;
u8 value_stored = 0;
if (!tnr_dmd)
return -EINVAL;
for (i = 0; i < tnr_dmd->cfg_mem_last_entry; i++) {
if (value_stored == 0 &&
tnr_dmd->cfg_mem[i].tgt == tgt &&
tnr_dmd->cfg_mem[i].bank == bank &&
tnr_dmd->cfg_mem[i].address == address) {
tnr_dmd->cfg_mem[i].value &= ~bit_mask;
tnr_dmd->cfg_mem[i].value |= (value & bit_mask);
tnr_dmd->cfg_mem[i].bit_mask |= bit_mask;
value_stored = 1;
}
}
if (value_stored)
return 0;
if (tnr_dmd->cfg_mem_last_entry < CXD2880_TNRDMD_MAX_CFG_MEM_COUNT) {
tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].tgt = tgt;
tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].bank = bank;
tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].address = address;
tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].value = (value & bit_mask);
tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].bit_mask = bit_mask;
tnr_dmd->cfg_mem_last_entry++;
} else {
return -ENOMEM;
}
return 0;
}
int cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_io *io,
struct cxd2880_tnrdmd_create_param
*create_param)
{
if (!tnr_dmd || !io || !create_param)
return -EINVAL;
memset(tnr_dmd, 0, sizeof(struct cxd2880_tnrdmd));
tnr_dmd->io = io;
tnr_dmd->create_param = *create_param;
tnr_dmd->diver_mode = CXD2880_TNRDMD_DIVERMODE_SINGLE;
tnr_dmd->diver_sub = NULL;
tnr_dmd->srl_ts_clk_mod_cnts = 1;
tnr_dmd->en_fef_intmtnt_base = 1;
tnr_dmd->en_fef_intmtnt_lite = 1;
tnr_dmd->rf_lvl_cmpstn = NULL;
tnr_dmd->lna_thrs_tbl_air = NULL;
tnr_dmd->lna_thrs_tbl_cable = NULL;
atomic_set(&tnr_dmd->cancel, 0);
return 0;
}
int cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd
*tnr_dmd_main,
struct cxd2880_io *io_main,
struct cxd2880_tnrdmd *tnr_dmd_sub,
struct cxd2880_io *io_sub,
struct
cxd2880_tnrdmd_diver_create_param
*create_param)
{
struct cxd2880_tnrdmd_create_param *main_param, *sub_param;
if (!tnr_dmd_main || !io_main || !tnr_dmd_sub || !io_sub ||
!create_param)
return -EINVAL;
memset(tnr_dmd_main, 0, sizeof(struct cxd2880_tnrdmd));
memset(tnr_dmd_sub, 0, sizeof(struct cxd2880_tnrdmd));
main_param = &tnr_dmd_main->create_param;
sub_param = &tnr_dmd_sub->create_param;
tnr_dmd_main->io = io_main;
tnr_dmd_main->diver_mode = CXD2880_TNRDMD_DIVERMODE_MAIN;
tnr_dmd_main->diver_sub = tnr_dmd_sub;
tnr_dmd_main->create_param.en_internal_ldo =
create_param->en_internal_ldo;
main_param->ts_output_if = create_param->ts_output_if;
main_param->xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_MASTER;
main_param->xosc_cap = create_param->xosc_cap_main;
main_param->xosc_i = create_param->xosc_i_main;
main_param->is_cxd2881gg = create_param->is_cxd2881gg;
main_param->stationary_use = create_param->stationary_use;
tnr_dmd_sub->io = io_sub;
tnr_dmd_sub->diver_mode = CXD2880_TNRDMD_DIVERMODE_SUB;
tnr_dmd_sub->diver_sub = NULL;
sub_param->en_internal_ldo = create_param->en_internal_ldo;
sub_param->ts_output_if = create_param->ts_output_if;
sub_param->xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_SLAVE;
sub_param->xosc_cap = 0;
sub_param->xosc_i = create_param->xosc_i_sub;
sub_param->is_cxd2881gg = create_param->is_cxd2881gg;
sub_param->stationary_use = create_param->stationary_use;
tnr_dmd_main->srl_ts_clk_mod_cnts = 1;
tnr_dmd_main->en_fef_intmtnt_base = 1;
tnr_dmd_main->en_fef_intmtnt_lite = 1;
tnr_dmd_main->rf_lvl_cmpstn = NULL;
tnr_dmd_main->lna_thrs_tbl_air = NULL;
tnr_dmd_main->lna_thrs_tbl_cable = NULL;
tnr_dmd_sub->srl_ts_clk_mod_cnts = 1;
tnr_dmd_sub->en_fef_intmtnt_base = 1;
tnr_dmd_sub->en_fef_intmtnt_lite = 1;
tnr_dmd_sub->rf_lvl_cmpstn = NULL;
tnr_dmd_sub->lna_thrs_tbl_air = NULL;
tnr_dmd_sub->lna_thrs_tbl_cable = NULL;
return 0;
}
int cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd)
{
int ret;
if (!tnr_dmd || tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
tnr_dmd->chip_id = CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
tnr_dmd->state = CXD2880_TNRDMD_STATE_UNKNOWN;
tnr_dmd->clk_mode = CXD2880_TNRDMD_CLOCKMODE_UNKNOWN;
tnr_dmd->frequency_khz = 0;
tnr_dmd->sys = CXD2880_DTV_SYS_UNKNOWN;
tnr_dmd->bandwidth = CXD2880_DTV_BW_UNKNOWN;
tnr_dmd->scan_mode = 0;
atomic_set(&tnr_dmd->cancel, 0);
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
tnr_dmd->diver_sub->chip_id = CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_UNKNOWN;
tnr_dmd->diver_sub->clk_mode = CXD2880_TNRDMD_CLOCKMODE_UNKNOWN;
tnr_dmd->diver_sub->frequency_khz = 0;
tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_UNKNOWN;
tnr_dmd->diver_sub->bandwidth = CXD2880_DTV_BW_UNKNOWN;
tnr_dmd->diver_sub->scan_mode = 0;
atomic_set(&tnr_dmd->diver_sub->cancel, 0);
}
ret = cxd2880_tnrdmd_chip_id(tnr_dmd, &tnr_dmd->chip_id);
if (ret)
return ret;
if (!CXD2880_TNRDMD_CHIP_ID_VALID(tnr_dmd->chip_id))
return -ENOTTY;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
cxd2880_tnrdmd_chip_id(tnr_dmd->diver_sub,
&tnr_dmd->diver_sub->chip_id);
if (ret)
return ret;
if (!CXD2880_TNRDMD_CHIP_ID_VALID(tnr_dmd->diver_sub->chip_id))
return -ENOTTY;
}
ret = p_init1(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = p_init1(tnr_dmd->diver_sub);
if (ret)
return ret;
}
usleep_range(1000, 2000);
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = p_init2(tnr_dmd->diver_sub);
if (ret)
return ret;
}
ret = p_init2(tnr_dmd);
if (ret)
return ret;
usleep_range(5000, 6000);
ret = p_init3(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = p_init3(tnr_dmd->diver_sub);
if (ret)
return ret;
}
ret = rf_init1(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret = rf_init1(tnr_dmd->diver_sub);
return ret;
}
int cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 cpu_task_completed;
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
ret = cxd2880_tnrdmd_check_internal_cpu_status(tnr_dmd,
&cpu_task_completed);
if (ret)
return ret;
if (!cpu_task_completed)
return -EINVAL;
ret = rf_init2(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = rf_init2(tnr_dmd->diver_sub);
if (ret)
return ret;
}
ret = load_cfg_mem(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = load_cfg_mem(tnr_dmd->diver_sub);
if (ret)
return ret;
}
tnr_dmd->state = CXD2880_TNRDMD_STATE_SLEEP;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_SLEEP;
return ret;
}
int cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd
*tnr_dmd,
u8 *task_completed)
{
u16 cpu_status = 0;
int ret;
if (!tnr_dmd || !task_completed)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
ret = cxd2880_tnrdmd_mon_internal_cpu_status(tnr_dmd, &cpu_status);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
if (cpu_status == 0)
*task_completed = 1;
else
*task_completed = 0;
return 0;
}
if (cpu_status != 0) {
*task_completed = 0;
return 0;
}
ret = cxd2880_tnrdmd_mon_internal_cpu_status_sub(tnr_dmd, &cpu_status);
if (ret)
return ret;
if (cpu_status == 0)
*task_completed = 1;
else
*task_completed = 0;
return ret;
}
int cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_sys sys,
u32 frequency_khz,
enum cxd2880_dtv_bandwidth
bandwidth, u8 one_seg_opt,
u8 one_seg_opt_shft_dir)
{
u8 data;
enum cxd2880_tnrdmd_clockmode new_clk_mode =
CXD2880_TNRDMD_CLOCKMODE_A;
int shift_frequency_khz;
u8 cpu_task_completed;
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (frequency_khz < 4000)
return -EINVAL;
ret = cxd2880_tnrdmd_sleep(tnr_dmd);
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00,
0x00);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x2b,
&data,
1);
if (ret)
return ret;
switch (sys) {
case CXD2880_DTV_SYS_DVBT:
if (data == 0x00) {
ret = t_power_x(tnr_dmd, 1);
if (ret)
return ret;
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = t_power_x(tnr_dmd->diver_sub, 1);
if (ret)
return ret;
}
}
break;
case CXD2880_DTV_SYS_DVBT2:
if (data == 0x01) {
ret = t_power_x(tnr_dmd, 0);
if (ret)
return ret;
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = t_power_x(tnr_dmd->diver_sub, 0);
if (ret)
return ret;
}
}
break;
default:
return -EINVAL;
}
ret = spll_reset(tnr_dmd, new_clk_mode);
if (ret)
return ret;
tnr_dmd->clk_mode = new_clk_mode;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = spll_reset(tnr_dmd->diver_sub, new_clk_mode);
if (ret)
return ret;
tnr_dmd->diver_sub->clk_mode = new_clk_mode;
}
ret = load_cfg_mem(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = load_cfg_mem(tnr_dmd->diver_sub);
if (ret)
return ret;
}
if (one_seg_opt) {
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
shift_frequency_khz = 350;
} else {
if (one_seg_opt_shft_dir)
shift_frequency_khz = 350;
else
shift_frequency_khz = -350;
if (tnr_dmd->create_param.xtal_share_type ==
CXD2880_TNRDMD_XTAL_SHARE_SLAVE)
shift_frequency_khz *= -1;
}
} else {
if (tnr_dmd->diver_mode ==
CXD2880_TNRDMD_DIVERMODE_MAIN) {
shift_frequency_khz = 150;
} else {
switch (tnr_dmd->create_param.xtal_share_type) {
case CXD2880_TNRDMD_XTAL_SHARE_NONE:
case CXD2880_TNRDMD_XTAL_SHARE_EXTREF:
default:
shift_frequency_khz = 0;
break;
case CXD2880_TNRDMD_XTAL_SHARE_MASTER:
shift_frequency_khz = 150;
break;
case CXD2880_TNRDMD_XTAL_SHARE_SLAVE:
shift_frequency_khz = -150;
break;
}
}
}
ret =
x_tune1(tnr_dmd, sys, frequency_khz, bandwidth,
tnr_dmd->is_cable_input, shift_frequency_khz);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
x_tune1(tnr_dmd->diver_sub, sys, frequency_khz,
bandwidth, tnr_dmd->is_cable_input,
-shift_frequency_khz);
if (ret)
return ret;
}
usleep_range(10000, 11000);
ret =
cxd2880_tnrdmd_check_internal_cpu_status(tnr_dmd,
&cpu_task_completed);
if (ret)
return ret;
if (!cpu_task_completed)
return -EINVAL;
ret =
x_tune2(tnr_dmd, bandwidth, tnr_dmd->clk_mode,
shift_frequency_khz);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret =
x_tune2(tnr_dmd->diver_sub, bandwidth,
tnr_dmd->diver_sub->clk_mode,
-shift_frequency_khz);
if (ret)
return ret;
}
if (tnr_dmd->create_param.ts_output_if == CXD2880_TNRDMD_TSOUT_IF_TS) {
ret = set_ts_clk_mode_and_freq(tnr_dmd, sys);
} else {
struct cxd2880_tnrdmd_pid_ftr_cfg *pid_ftr_cfg;
if (tnr_dmd->pid_ftr_cfg_en)
pid_ftr_cfg = &tnr_dmd->pid_ftr_cfg;
else
pid_ftr_cfg = NULL;
ret = pid_ftr_setting(tnr_dmd, pid_ftr_cfg);
}
return ret;
}
int cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_dtv_sys sys,
u8 en_fef_intmtnt_ctrl)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = x_tune3(tnr_dmd, sys, en_fef_intmtnt_ctrl);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = x_tune3(tnr_dmd->diver_sub, sys, en_fef_intmtnt_ctrl);
if (ret)
return ret;
ret = x_tune4(tnr_dmd);
if (ret)
return ret;
}
return cxd2880_tnrdmd_set_ts_output(tnr_dmd, 1);
}
int cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state == CXD2880_TNRDMD_STATE_SLEEP)
return 0;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = cxd2880_tnrdmd_set_ts_output(tnr_dmd, 0);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = x_sleep1(tnr_dmd);
if (ret)
return ret;
}
ret = x_sleep2(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = x_sleep2(tnr_dmd->diver_sub);
if (ret)
return ret;
}
switch (tnr_dmd->sys) {
case CXD2880_DTV_SYS_DVBT:
ret = cxd2880_tnrdmd_dvbt_sleep_setting(tnr_dmd);
if (ret)
return ret;
break;
case CXD2880_DTV_SYS_DVBT2:
ret = cxd2880_tnrdmd_dvbt2_sleep_setting(tnr_dmd);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
ret = x_sleep3(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = x_sleep3(tnr_dmd->diver_sub);
if (ret)
return ret;
}
ret = x_sleep4(tnr_dmd);
if (ret)
return ret;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
ret = x_sleep4(tnr_dmd->diver_sub);
if (ret)
return ret;
}
tnr_dmd->state = CXD2880_TNRDMD_STATE_SLEEP;
tnr_dmd->frequency_khz = 0;
tnr_dmd->sys = CXD2880_DTV_SYS_UNKNOWN;
tnr_dmd->bandwidth = CXD2880_DTV_BW_UNKNOWN;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_SLEEP;
tnr_dmd->diver_sub->frequency_khz = 0;
tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_UNKNOWN;
tnr_dmd->diver_sub->bandwidth = CXD2880_DTV_BW_UNKNOWN;
}
return 0;
}
int cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_tnrdmd_cfg_id id,
int value)
{
int ret = 0;
u8 data[2] = { 0 };
u8 need_sub_setting = 0;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
switch (id) {
case CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc4,
value ? 0x00 : 0x10,
0x10);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc5,
value ? 0x00 : 0x02,
0x02);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc5,
value ? 0x00 : 0x04,
0x04);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xcb,
value ? 0x00 : 0x01,
0x01);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc5,
value ? 0x01 : 0x00,
0x01);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSCLK_CONT:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
tnr_dmd->srl_ts_clk_mod_cnts = value ? 0x01 : 0x00;
break;
case CXD2880_TNRDMD_CFG_TSCLK_MASK:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 0x1f)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc6, value,
0x1f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSVALID_MASK:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 0x1f)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc8, value,
0x1f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSERR_MASK:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 0x1f)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xc9, value,
0x1f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSERR_VALID_DIS:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x91,
value ? 0x01 : 0x00,
0x01);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSPIN_CURRENT:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x51, value,
0x3f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x50,
value ? 0x80 : 0x00,
0x80);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSPIN_PULLUP:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x50, value,
0x3f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TSCLK_FREQ:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 1)
return -EINVAL;
tnr_dmd->srl_ts_clk_frq =
(enum cxd2880_tnrdmd_serial_ts_clk)value;
break;
case CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 0xff)
return -EINVAL;
tnr_dmd->ts_byte_clk_manual_setting = value;
break;
case CXD2880_TNRDMD_CFG_TS_PACKET_GAP:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (value < 0 || value > 7)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0xd6, value,
0x07);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE:
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
tnr_dmd->is_ts_backwards_compatible_mode = value ? 1 : 0;
break;
case CXD2880_TNRDMD_CFG_PWM_VALUE:
if (value < 0 || value > 0x1000)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x22,
value ? 0x01 : 0x00,
0x01);
if (ret)
return ret;
data[0] = (value >> 8) & 0x1f;
data[1] = value & 0xff;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x23,
data[0], 0x1f);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x24,
data[1], 0xff);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_INTERRUPT:
data[0] = (value >> 8) & 0xff;
data[1] = value & 0xff;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x48, data[0],
0xff);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x49, data[1],
0xff);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL:
data[0] = value & 0x07;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x4a, data[0],
0x07);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL:
data[0] = (value & 0x07) << 3;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x4a, data[0],
0x38);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE:
if (value < CXD2880_TNRDMD_CLOCKMODE_UNKNOWN ||
value > CXD2880_TNRDMD_CLOCKMODE_C)
return -EINVAL;
tnr_dmd->fixed_clk_mode = (enum cxd2880_tnrdmd_clockmode)value;
break;
case CXD2880_TNRDMD_CFG_CABLE_INPUT:
tnr_dmd->is_cable_input = value ? 1 : 0;
break;
case CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE:
tnr_dmd->en_fef_intmtnt_base = value ? 1 : 0;
break;
case CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE:
tnr_dmd->en_fef_intmtnt_lite = value ? 1 : 0;
break;
case CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS:
data[0] = (value >> 8) & 0x07;
data[1] = value & 0xff;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x99, data[0],
0x07);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x9a, data[1],
0xff);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS:
data[0] = (value >> 8) & 0x07;
data[1] = value & 0xff;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x9b, data[0],
0x07);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x9c, data[1],
0xff);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS:
data[0] = (value >> 8) & 0x07;
data[1] = value & 0xff;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x9d, data[0],
0x07);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x00, 0x9e, data[1],
0xff);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST:
tnr_dmd->blind_tune_dvbt2_first = value ? 1 : 0;
break;
case CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD:
if (value < 0 || value > 31)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x10, 0x60,
value & 0x1f, 0x1f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD:
if (value < 0 || value > 7)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x10, 0x6f,
value & 0x07, 0x07);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_DVBT2_BBER_MES:
if (value < 0 || value > 15)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x20, 0x72,
value & 0x0f, 0x0f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_DVBT2_LBER_MES:
if (value < 0 || value > 15)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x20, 0x6f,
value & 0x0f, 0x0f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_DVBT_PER_MES:
if (value < 0 || value > 15)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x10, 0x5c,
value & 0x0f, 0x0f);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_CFG_DVBT2_PER_MES:
if (value < 0 || value > 15)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_DMD,
0x24, 0xdc,
value & 0x0f, 0x0f);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
if (need_sub_setting &&
tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
ret = cxd2880_tnrdmd_set_cfg(tnr_dmd->diver_sub, id, value);
return ret;
}
int cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
u8 id,
u8 en,
enum cxd2880_tnrdmd_gpio_mode mode,
u8 open_drain, u8 invert)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (id > 2)
return -EINVAL;
if (mode > CXD2880_TNRDMD_GPIO_MODE_EEW)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd, CXD2880_IO_TGT_SYS,
0x00, 0x40 + id, mode,
0x0f);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd, CXD2880_IO_TGT_SYS,
0x00, 0x43,
open_drain ? (1 << id) : 0,
1 << id);
if (ret)
return ret;
ret =
cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd, CXD2880_IO_TGT_SYS,
0x00, 0x44,
invert ? (1 << id) : 0,
1 << id);
if (ret)
return ret;
return cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x45,
en ? 0 : (1 << id),
1 << id);
}
int cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd,
u8 id,
u8 en,
enum cxd2880_tnrdmd_gpio_mode
mode, u8 open_drain, u8 invert)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_gpio_set_cfg(tnr_dmd->diver_sub, id, en, mode,
open_drain, invert);
}
int cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd,
u8 id, u8 *value)
{
u8 data = 0;
int ret;
if (!tnr_dmd || !value)
return -EINVAL;
if (id > 2)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x20, &data, 1);
if (ret)
return ret;
*value = (data >> id) & 0x01;
return 0;
}
int cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd,
u8 id, u8 *value)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_gpio_read(tnr_dmd->diver_sub, id, value);
}
int cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd,
u8 id, u8 value)
{
if (!tnr_dmd)
return -EINVAL;
if (id > 2)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
return cxd2880_tnrdmd_set_and_save_reg_bits(tnr_dmd,
CXD2880_IO_TGT_SYS,
0x00, 0x46,
value ? (1 << id) : 0,
1 << id);
}
int cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd,
u8 id, u8 value)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_gpio_write(tnr_dmd->diver_sub, id, value);
}
int cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd,
u16 *value)
{
int ret;
u8 data[2] = { 0 };
if (!tnr_dmd || !value)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x0a);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x15, data, 2);
if (ret)
return ret;
*value = (data[0] << 8) | data[1];
return 0;
}
int cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd,
u16 value)
{
int ret;
u8 data[2] = { 0 };
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
data[0] = (value >> 8) & 0xff;
data[1] = value & 0xff;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x3c, data, 2);
}
int cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd,
u8 clear_overflow_flag,
u8 clear_underflow_flag,
u8 clear_buf)
{
int ret;
u8 data[2] = { 0 };
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, 0x00);
if (ret)
return ret;
data[0] = clear_overflow_flag ? 0x02 : 0x00;
data[0] |= clear_underflow_flag ? 0x01 : 0x00;
data[1] = clear_buf ? 0x01 : 0x00;
return tnr_dmd->io->write_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x9f, data, 2);
}
int cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_tnrdmd_chip_id *chip_id)
{
int ret;
u8 data = 0;
if (!tnr_dmd || !chip_id)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0xfd, &data, 1);
if (ret)
return ret;
*chip_id = (enum cxd2880_tnrdmd_chip_id)data;
return 0;
}
int cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd
*tnr_dmd,
enum cxd2880_io_tgt tgt,
u8 bank, u8 address,
u8 value, u8 bit_mask)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
ret = tnr_dmd->io->write_reg(tnr_dmd->io, tgt, 0x00, bank);
if (ret)
return ret;
ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
tgt, address, value, bit_mask);
if (ret)
return ret;
return set_cfg_mem(tnr_dmd, tgt, bank, address, value, bit_mask);
}
int cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd,
enum cxd2880_dtv_sys sys,
u8 scan_mode_end)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
tnr_dmd->scan_mode = scan_mode_end;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
return cxd2880_tnrdmd_set_scan_mode(tnr_dmd->diver_sub, sys,
scan_mode_end);
else
return 0;
}
int cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_tnrdmd_pid_ftr_cfg
*pid_ftr_cfg)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
if (tnr_dmd->create_param.ts_output_if == CXD2880_TNRDMD_TSOUT_IF_TS)
return -ENOTTY;
if (pid_ftr_cfg) {
tnr_dmd->pid_ftr_cfg = *pid_ftr_cfg;
tnr_dmd->pid_ftr_cfg_en = 1;
} else {
tnr_dmd->pid_ftr_cfg_en = 0;
}
if (tnr_dmd->state == CXD2880_TNRDMD_STATE_ACTIVE)
return pid_ftr_setting(tnr_dmd, pid_ftr_cfg);
else
return 0;
}
int cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd
*tnr_dmd,
int (*rf_lvl_cmpstn)
(struct cxd2880_tnrdmd *,
int *))
{
if (!tnr_dmd)
return -EINVAL;
tnr_dmd->rf_lvl_cmpstn = rf_lvl_cmpstn;
return 0;
}
int cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd
*tnr_dmd,
int (*rf_lvl_cmpstn)
(struct cxd2880_tnrdmd *,
int *))
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_set_rf_lvl_cmpstn(tnr_dmd->diver_sub,
rf_lvl_cmpstn);
}
int cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd,
struct cxd2880_tnrdmd_lna_thrs_tbl_air
*tbl_air,
struct cxd2880_tnrdmd_lna_thrs_tbl_cable
*tbl_cable)
{
if (!tnr_dmd)
return -EINVAL;
tnr_dmd->lna_thrs_tbl_air = tbl_air;
tnr_dmd->lna_thrs_tbl_cable = tbl_cable;
return 0;
}
int cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd,
struct
cxd2880_tnrdmd_lna_thrs_tbl_air
*tbl_air,
struct cxd2880_tnrdmd_lna_thrs_tbl_cable
*tbl_cable)
{
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
return -EINVAL;
return cxd2880_tnrdmd_set_lna_thrs(tnr_dmd->diver_sub,
tbl_air, tbl_cable);
}
int cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd
*tnr_dmd, u8 en, u8 value)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP)
return -EINVAL;
if (tnr_dmd->create_param.ts_output_if != CXD2880_TNRDMD_TSOUT_IF_TS)
return -ENOTTY;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x00, 0x00);
if (ret)
return ret;
if (en) {
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x50, ((value & 0x1f) | 0x80));
if (ret)
return ret;
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
0x52, (value & 0x1f));
} else {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
set_ts_pin_seq,
ARRAY_SIZE(set_ts_pin_seq));
if (ret)
return ret;
ret = load_cfg_mem(tnr_dmd);
}
return ret;
}
int cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd,
u8 en)
{
int ret;
if (!tnr_dmd)
return -EINVAL;
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
return -EINVAL;
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
return -EINVAL;
switch (tnr_dmd->create_param.ts_output_if) {
case CXD2880_TNRDMD_TSOUT_IF_TS:
if (en) {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
set_ts_output_seq1,
ARRAY_SIZE(set_ts_output_seq1));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
set_ts_output_seq2,
ARRAY_SIZE(set_ts_output_seq2));
if (ret)
return ret;
} else {
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
set_ts_output_seq3,
ARRAY_SIZE(set_ts_output_seq3));
if (ret)
return ret;
ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
CXD2880_IO_TGT_SYS,
set_ts_output_seq4,
ARRAY_SIZE(set_ts_output_seq4));
if (ret)
return ret;
}
break;
case CXD2880_TNRDMD_TSOUT_IF_SPI:
break;
case CXD2880_TNRDMD_TSOUT_IF_SDIO:
break;
default:
return -EINVAL;
}
return 0;
}
int slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd)
{
u8 data;
int ret;
if (!tnr_dmd)
return -EINVAL;
switch (tnr_dmd->create_param.ts_output_if) {
case CXD2880_TNRDMD_TSOUT_IF_SPI:
case CXD2880_TNRDMD_TSOUT_IF_SDIO:
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x00, &data, 1);
if (ret)
return ret;
break;
case CXD2880_TNRDMD_TSOUT_IF_TS:
default:
break;
}
return tnr_dmd->io->write_reg(tnr_dmd->io,
CXD2880_IO_TGT_DMD,
0x01, 0x01);
}
| linux-master | drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FireDTV driver (formerly known as FireSAT)
*
* Copyright (C) 2004 Andreas Monitzer <[email protected]>
* Copyright (C) 2008 Henrik Kurelid <[email protected]>
*/
#include <linux/device.h>
#include <linux/dvb/ca.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <media/dvbdev.h>
#include "firedtv.h"
#define EN50221_TAG_APP_INFO_ENQUIRY 0x9f8020
#define EN50221_TAG_CA_INFO_ENQUIRY 0x9f8030
#define EN50221_TAG_CA_PMT 0x9f8032
#define EN50221_TAG_ENTER_MENU 0x9f8022
static int fdtv_ca_ready(struct firedtv_tuner_status *stat)
{
return stat->ca_initialization_status == 1 &&
stat->ca_error_flag == 0 &&
stat->ca_dvb_flag == 1 &&
stat->ca_module_present_status == 1;
}
static int fdtv_get_ca_flags(struct firedtv_tuner_status *stat)
{
int flags = 0;
if (stat->ca_module_present_status == 1)
flags |= CA_CI_MODULE_PRESENT;
if (stat->ca_initialization_status == 1 &&
stat->ca_error_flag == 0 &&
stat->ca_dvb_flag == 1)
flags |= CA_CI_MODULE_READY;
return flags;
}
static int fdtv_ca_get_caps(void *arg)
{
struct ca_caps *cap = arg;
cap->slot_num = 1;
cap->slot_type = CA_CI;
cap->descr_num = 1;
cap->descr_type = CA_ECD;
return 0;
}
static int fdtv_ca_get_slot_info(struct firedtv *fdtv, void *arg)
{
struct firedtv_tuner_status stat;
struct ca_slot_info *slot = arg;
int err;
err = avc_tuner_status(fdtv, &stat);
if (err)
return err;
if (slot->num != 0)
return -EACCES;
slot->type = CA_CI;
slot->flags = fdtv_get_ca_flags(&stat);
return 0;
}
static int fdtv_ca_app_info(struct firedtv *fdtv, void *arg)
{
struct ca_msg *reply = arg;
return avc_ca_app_info(fdtv, reply->msg, &reply->length);
}
static int fdtv_ca_info(struct firedtv *fdtv, void *arg)
{
struct ca_msg *reply = arg;
return avc_ca_info(fdtv, reply->msg, &reply->length);
}
static int fdtv_ca_get_mmi(struct firedtv *fdtv, void *arg)
{
struct ca_msg *reply = arg;
return avc_ca_get_mmi(fdtv, reply->msg, &reply->length);
}
static int fdtv_ca_get_msg(struct firedtv *fdtv, void *arg)
{
struct firedtv_tuner_status stat;
int err;
switch (fdtv->ca_last_command) {
case EN50221_TAG_APP_INFO_ENQUIRY:
err = fdtv_ca_app_info(fdtv, arg);
break;
case EN50221_TAG_CA_INFO_ENQUIRY:
err = fdtv_ca_info(fdtv, arg);
break;
default:
err = avc_tuner_status(fdtv, &stat);
if (err)
break;
if (stat.ca_mmi == 1)
err = fdtv_ca_get_mmi(fdtv, arg);
else {
dev_info(fdtv->device, "unhandled CA message 0x%08x\n",
fdtv->ca_last_command);
err = -EACCES;
}
}
fdtv->ca_last_command = 0;
return err;
}
static int fdtv_ca_pmt(struct firedtv *fdtv, void *arg)
{
struct ca_msg *msg = arg;
int data_pos;
int data_length;
int i;
data_pos = 4;
if (msg->msg[3] & 0x80) {
data_length = 0;
for (i = 0; i < (msg->msg[3] & 0x7f); i++)
data_length = (data_length << 8) + msg->msg[data_pos++];
} else {
data_length = msg->msg[3];
}
if (data_length > sizeof(msg->msg) - data_pos)
return -EINVAL;
return avc_ca_pmt(fdtv, &msg->msg[data_pos], data_length);
}
static int fdtv_ca_send_msg(struct firedtv *fdtv, void *arg)
{
struct ca_msg *msg = arg;
int err;
/* Do we need a semaphore for this? */
fdtv->ca_last_command =
(msg->msg[0] << 16) + (msg->msg[1] << 8) + msg->msg[2];
switch (fdtv->ca_last_command) {
case EN50221_TAG_CA_PMT:
err = fdtv_ca_pmt(fdtv, arg);
break;
case EN50221_TAG_APP_INFO_ENQUIRY:
/* handled in ca_get_msg */
err = 0;
break;
case EN50221_TAG_CA_INFO_ENQUIRY:
/* handled in ca_get_msg */
err = 0;
break;
case EN50221_TAG_ENTER_MENU:
err = avc_ca_enter_menu(fdtv);
break;
default:
dev_err(fdtv->device, "unhandled CA message 0x%08x\n",
fdtv->ca_last_command);
err = -EACCES;
}
return err;
}
static int fdtv_ca_ioctl(struct file *file, unsigned int cmd, void *arg)
{
struct dvb_device *dvbdev = file->private_data;
struct firedtv *fdtv = dvbdev->priv;
struct firedtv_tuner_status stat;
int err;
switch (cmd) {
case CA_RESET:
err = avc_ca_reset(fdtv);
break;
case CA_GET_CAP:
err = fdtv_ca_get_caps(arg);
break;
case CA_GET_SLOT_INFO:
err = fdtv_ca_get_slot_info(fdtv, arg);
break;
case CA_GET_MSG:
err = fdtv_ca_get_msg(fdtv, arg);
break;
case CA_SEND_MSG:
err = fdtv_ca_send_msg(fdtv, arg);
break;
default:
dev_info(fdtv->device, "unhandled CA ioctl %u\n", cmd);
err = -EOPNOTSUPP;
}
/* FIXME Is this necessary? */
avc_tuner_status(fdtv, &stat);
return err;
}
static __poll_t fdtv_ca_io_poll(struct file *file, poll_table *wait)
{
return EPOLLIN;
}
static const struct file_operations fdtv_ca_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = dvb_generic_ioctl,
.open = dvb_generic_open,
.release = dvb_generic_release,
.poll = fdtv_ca_io_poll,
.llseek = noop_llseek,
};
static const struct dvb_device fdtv_ca = {
.users = 1,
.readers = 1,
.writers = 1,
.fops = &fdtv_ca_fops,
.kernel_ioctl = fdtv_ca_ioctl,
};
int fdtv_ca_register(struct firedtv *fdtv)
{
struct firedtv_tuner_status stat;
int err;
if (avc_tuner_status(fdtv, &stat))
return -EINVAL;
if (!fdtv_ca_ready(&stat))
return -EFAULT;
err = dvb_register_device(&fdtv->adapter, &fdtv->cadev,
&fdtv_ca, fdtv, DVB_DEVICE_CA, 0);
if (stat.ca_application_info == 0)
dev_err(fdtv->device, "CaApplicationInfo is not set\n");
if (stat.ca_date_time_request == 1)
avc_ca_get_time_date(fdtv, &fdtv->ca_time_interval);
return err;
}
void fdtv_ca_release(struct firedtv *fdtv)
{
dvb_unregister_device(fdtv->cadev);
}
| linux-master | drivers/media/firewire/firedtv-ci.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FireDTV driver (formerly known as FireSAT)
*
* Copyright (C) 2004 Andreas Monitzer <[email protected]>
* Copyright (C) 2008 Henrik Kurelid <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <media/dmxdev.h>
#include <media/dvb_demux.h>
#include <media/dvbdev.h>
#include <media/dvb_frontend.h>
#include "firedtv.h"
static int alloc_channel(struct firedtv *fdtv)
{
int i;
for (i = 0; i < 16; i++)
if (!__test_and_set_bit(i, &fdtv->channel_active))
break;
return i;
}
static void collect_channels(struct firedtv *fdtv, int *pidc, u16 pid[])
{
int i, n;
for (i = 0, n = 0; i < 16; i++)
if (test_bit(i, &fdtv->channel_active))
pid[n++] = fdtv->channel_pid[i];
*pidc = n;
}
static inline void dealloc_channel(struct firedtv *fdtv, int i)
{
__clear_bit(i, &fdtv->channel_active);
}
int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct firedtv *fdtv = dvbdmxfeed->demux->priv;
int pidc, c, ret;
u16 pids[16];
switch (dvbdmxfeed->type) {
case DMX_TYPE_TS:
case DMX_TYPE_SEC:
break;
default:
dev_err(fdtv->device, "can't start dmx feed: invalid type %u\n",
dvbdmxfeed->type);
return -EINVAL;
}
if (mutex_lock_interruptible(&fdtv->demux_mutex))
return -EINTR;
if (dvbdmxfeed->type == DMX_TYPE_TS) {
switch (dvbdmxfeed->pes_type) {
case DMX_PES_VIDEO:
case DMX_PES_AUDIO:
case DMX_PES_TELETEXT:
case DMX_PES_PCR:
case DMX_PES_OTHER:
c = alloc_channel(fdtv);
break;
default:
dev_err(fdtv->device,
"can't start dmx feed: invalid pes type %u\n",
dvbdmxfeed->pes_type);
ret = -EINVAL;
goto out;
}
} else {
c = alloc_channel(fdtv);
}
if (c > 15) {
dev_err(fdtv->device, "can't start dmx feed: busy\n");
ret = -EBUSY;
goto out;
}
dvbdmxfeed->priv = (typeof(dvbdmxfeed->priv))(unsigned long)c;
fdtv->channel_pid[c] = dvbdmxfeed->pid;
collect_channels(fdtv, &pidc, pids);
if (dvbdmxfeed->pid == 8192) {
ret = avc_tuner_get_ts(fdtv);
if (ret) {
dealloc_channel(fdtv, c);
dev_err(fdtv->device, "can't get TS\n");
goto out;
}
} else {
ret = avc_tuner_set_pids(fdtv, pidc, pids);
if (ret) {
dealloc_channel(fdtv, c);
dev_err(fdtv->device, "can't set PIDs\n");
goto out;
}
}
out:
mutex_unlock(&fdtv->demux_mutex);
return ret;
}
int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *demux = dvbdmxfeed->demux;
struct firedtv *fdtv = demux->priv;
int pidc, c, ret;
u16 pids[16];
if (dvbdmxfeed->type == DMX_TYPE_TS &&
!((dvbdmxfeed->ts_type & TS_PACKET) &&
(demux->dmx.frontend->source != DMX_MEMORY_FE))) {
if (dvbdmxfeed->ts_type & TS_DECODER) {
if (dvbdmxfeed->pes_type >= DMX_PES_OTHER ||
!demux->pesfilter[dvbdmxfeed->pes_type])
return -EINVAL;
demux->pids[dvbdmxfeed->pes_type] |= 0x8000;
demux->pesfilter[dvbdmxfeed->pes_type] = NULL;
}
if (!(dvbdmxfeed->ts_type & TS_DECODER &&
dvbdmxfeed->pes_type < DMX_PES_OTHER))
return 0;
}
if (mutex_lock_interruptible(&fdtv->demux_mutex))
return -EINTR;
c = (unsigned long)dvbdmxfeed->priv;
dealloc_channel(fdtv, c);
collect_channels(fdtv, &pidc, pids);
ret = avc_tuner_set_pids(fdtv, pidc, pids);
mutex_unlock(&fdtv->demux_mutex);
return ret;
}
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
int fdtv_dvb_register(struct firedtv *fdtv, const char *name)
{
int err;
err = dvb_register_adapter(&fdtv->adapter, name,
THIS_MODULE, fdtv->device, adapter_nr);
if (err < 0)
goto fail_log;
/*DMX_TS_FILTERING | DMX_SECTION_FILTERING*/
fdtv->demux.dmx.capabilities = 0;
fdtv->demux.priv = fdtv;
fdtv->demux.filternum = 16;
fdtv->demux.feednum = 16;
fdtv->demux.start_feed = fdtv_start_feed;
fdtv->demux.stop_feed = fdtv_stop_feed;
fdtv->demux.write_to_decoder = NULL;
err = dvb_dmx_init(&fdtv->demux);
if (err)
goto fail_unreg_adapter;
fdtv->dmxdev.filternum = 16;
fdtv->dmxdev.demux = &fdtv->demux.dmx;
fdtv->dmxdev.capabilities = 0;
err = dvb_dmxdev_init(&fdtv->dmxdev, &fdtv->adapter);
if (err)
goto fail_dmx_release;
fdtv->frontend.source = DMX_FRONTEND_0;
err = fdtv->demux.dmx.add_frontend(&fdtv->demux.dmx, &fdtv->frontend);
if (err)
goto fail_dmxdev_release;
err = fdtv->demux.dmx.connect_frontend(&fdtv->demux.dmx,
&fdtv->frontend);
if (err)
goto fail_rem_frontend;
err = dvb_net_init(&fdtv->adapter, &fdtv->dvbnet, &fdtv->demux.dmx);
if (err)
goto fail_disconnect_frontend;
fdtv_frontend_init(fdtv, name);
err = dvb_register_frontend(&fdtv->adapter, &fdtv->fe);
if (err)
goto fail_net_release;
err = fdtv_ca_register(fdtv);
if (err)
dev_info(fdtv->device,
"Conditional Access Module not enabled\n");
return 0;
fail_net_release:
dvb_net_release(&fdtv->dvbnet);
fail_disconnect_frontend:
fdtv->demux.dmx.close(&fdtv->demux.dmx);
fail_rem_frontend:
fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
fail_dmxdev_release:
dvb_dmxdev_release(&fdtv->dmxdev);
fail_dmx_release:
dvb_dmx_release(&fdtv->demux);
fail_unreg_adapter:
dvb_unregister_adapter(&fdtv->adapter);
fail_log:
dev_err(fdtv->device, "DVB initialization failed\n");
return err;
}
void fdtv_dvb_unregister(struct firedtv *fdtv)
{
fdtv_ca_release(fdtv);
dvb_unregister_frontend(&fdtv->fe);
dvb_net_release(&fdtv->dvbnet);
fdtv->demux.dmx.close(&fdtv->demux.dmx);
fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
dvb_dmxdev_release(&fdtv->dmxdev);
dvb_dmx_release(&fdtv->demux);
dvb_unregister_adapter(&fdtv->adapter);
}
| linux-master | drivers/media/firewire/firedtv-dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FireDTV driver (formerly known as FireSAT)
*
* Copyright (C) 2004 Andreas Monitzer <[email protected]>
* Copyright (C) 2008 Henrik Kurelid <[email protected]>
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/dvb_frontend.h>
#include "firedtv.h"
static int fdtv_dvb_init(struct dvb_frontend *fe)
{
struct firedtv *fdtv = fe->sec_priv;
int err;
/* FIXME - allocate free channel at IRM */
fdtv->isochannel = fdtv->adapter.num;
err = cmp_establish_pp_connection(fdtv, fdtv->subunit,
fdtv->isochannel);
if (err) {
dev_err(fdtv->device,
"could not establish point to point connection\n");
return err;
}
return fdtv_start_iso(fdtv);
}
static int fdtv_sleep(struct dvb_frontend *fe)
{
struct firedtv *fdtv = fe->sec_priv;
fdtv_stop_iso(fdtv);
cmp_break_pp_connection(fdtv, fdtv->subunit, fdtv->isochannel);
fdtv->isochannel = -1;
return 0;
}
#define LNBCONTROL_DONTCARE 0xff
static int fdtv_diseqc_send_master_cmd(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct firedtv *fdtv = fe->sec_priv;
return avc_lnb_control(fdtv, LNBCONTROL_DONTCARE, LNBCONTROL_DONTCARE,
LNBCONTROL_DONTCARE, 1, cmd);
}
static int fdtv_diseqc_send_burst(struct dvb_frontend *fe,
enum fe_sec_mini_cmd minicmd)
{
return 0;
}
static int fdtv_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
{
struct firedtv *fdtv = fe->sec_priv;
fdtv->tone = tone;
return 0;
}
static int fdtv_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct firedtv *fdtv = fe->sec_priv;
fdtv->voltage = voltage;
return 0;
}
static int fdtv_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct firedtv *fdtv = fe->sec_priv;
struct firedtv_tuner_status stat;
if (avc_tuner_status(fdtv, &stat))
return -EINVAL;
if (stat.no_rf)
*status = 0;
else
*status = FE_HAS_SIGNAL | FE_HAS_VITERBI | FE_HAS_SYNC |
FE_HAS_CARRIER | FE_HAS_LOCK;
return 0;
}
static int fdtv_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct firedtv *fdtv = fe->sec_priv;
struct firedtv_tuner_status stat;
if (avc_tuner_status(fdtv, &stat))
return -EINVAL;
*ber = stat.ber;
return 0;
}
static int fdtv_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct firedtv *fdtv = fe->sec_priv;
struct firedtv_tuner_status stat;
if (avc_tuner_status(fdtv, &stat))
return -EINVAL;
*strength = stat.signal_strength << 8;
return 0;
}
static int fdtv_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct firedtv *fdtv = fe->sec_priv;
struct firedtv_tuner_status stat;
if (avc_tuner_status(fdtv, &stat))
return -EINVAL;
/* C/N[dB] = -10 * log10(snr / 65535) */
*snr = stat.carrier_noise_ratio * 257;
return 0;
}
static int fdtv_read_uncorrected_blocks(struct dvb_frontend *fe, u32 *ucblocks)
{
return -EOPNOTSUPP;
}
static int fdtv_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct firedtv *fdtv = fe->sec_priv;
return avc_tuner_dsd(fdtv, p);
}
void fdtv_frontend_init(struct firedtv *fdtv, const char *name)
{
struct dvb_frontend_ops *ops = &fdtv->fe.ops;
struct dvb_frontend_internal_info *fi = &ops->info;
ops->init = fdtv_dvb_init;
ops->sleep = fdtv_sleep;
ops->set_frontend = fdtv_set_frontend;
ops->read_status = fdtv_read_status;
ops->read_ber = fdtv_read_ber;
ops->read_signal_strength = fdtv_read_signal_strength;
ops->read_snr = fdtv_read_snr;
ops->read_ucblocks = fdtv_read_uncorrected_blocks;
ops->diseqc_send_master_cmd = fdtv_diseqc_send_master_cmd;
ops->diseqc_send_burst = fdtv_diseqc_send_burst;
ops->set_tone = fdtv_set_tone;
ops->set_voltage = fdtv_set_voltage;
switch (fdtv->type) {
case FIREDTV_DVB_S:
ops->delsys[0] = SYS_DVBS;
fi->frequency_min_hz = 950 * MHz;
fi->frequency_max_hz = 2150 * MHz;
fi->frequency_stepsize_hz = 125 * kHz;
fi->symbol_rate_min = 1000000;
fi->symbol_rate_max = 40000000;
fi->caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK;
break;
case FIREDTV_DVB_S2:
ops->delsys[0] = SYS_DVBS;
ops->delsys[1] = SYS_DVBS2;
fi->frequency_min_hz = 950 * MHz;
fi->frequency_max_hz = 2150 * MHz;
fi->frequency_stepsize_hz = 125 * kHz;
fi->symbol_rate_min = 1000000;
fi->symbol_rate_max = 40000000;
fi->caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 |
FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 |
FE_CAN_FEC_AUTO |
FE_CAN_QPSK |
FE_CAN_2G_MODULATION;
break;
case FIREDTV_DVB_C:
ops->delsys[0] = SYS_DVBC_ANNEX_A;
fi->frequency_min_hz = 47 * MHz;
fi->frequency_max_hz = 866 * MHz;
fi->frequency_stepsize_hz = 62500;
fi->symbol_rate_min = 870000;
fi->symbol_rate_max = 6900000;
fi->caps = FE_CAN_INVERSION_AUTO |
FE_CAN_QAM_16 |
FE_CAN_QAM_32 |
FE_CAN_QAM_64 |
FE_CAN_QAM_128 |
FE_CAN_QAM_256 |
FE_CAN_QAM_AUTO;
break;
case FIREDTV_DVB_T:
ops->delsys[0] = SYS_DVBT;
fi->frequency_min_hz = 49 * MHz;
fi->frequency_max_hz = 861 * MHz;
fi->frequency_stepsize_hz = 62500;
fi->caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_2_3 |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO;
break;
default:
dev_err(fdtv->device, "no frontend for model type %d\n",
fdtv->type);
}
strscpy(fi->name, name, sizeof(fi->name));
fdtv->fe.dvb = &fdtv->adapter;
fdtv->fe.sec_priv = fdtv;
}
| linux-master | drivers/media/firewire/firedtv-fe.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FireDTV driver (formerly known as FireSAT)
*
* Copyright (C) 2004 Andreas Monitzer <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/workqueue.h>
#include "firedtv.h"
/* fixed table with older keycodes, geared towards MythTV */
static const u16 oldtable[] = {
/* code from device: 0x4501...0x451f */
KEY_ESC,
KEY_F9,
KEY_1,
KEY_2,
KEY_3,
KEY_4,
KEY_5,
KEY_6,
KEY_7,
KEY_8,
KEY_9,
KEY_I,
KEY_0,
KEY_ENTER,
KEY_RED,
KEY_UP,
KEY_GREEN,
KEY_F10,
KEY_SPACE,
KEY_F11,
KEY_YELLOW,
KEY_DOWN,
KEY_BLUE,
KEY_Z,
KEY_P,
KEY_PAGEDOWN,
KEY_LEFT,
KEY_W,
KEY_RIGHT,
KEY_P,
KEY_M,
/* code from device: 0x4540...0x4542 */
KEY_R,
KEY_V,
KEY_C,
};
/* user-modifiable table for a remote as sold in 2008 */
static const u16 keytable[] = {
/* code from device: 0x0300...0x031f */
[0x00] = KEY_POWER,
[0x01] = KEY_SLEEP,
[0x02] = KEY_STOP,
[0x03] = KEY_OK,
[0x04] = KEY_RIGHT,
[0x05] = KEY_1,
[0x06] = KEY_2,
[0x07] = KEY_3,
[0x08] = KEY_LEFT,
[0x09] = KEY_4,
[0x0a] = KEY_5,
[0x0b] = KEY_6,
[0x0c] = KEY_UP,
[0x0d] = KEY_7,
[0x0e] = KEY_8,
[0x0f] = KEY_9,
[0x10] = KEY_DOWN,
[0x11] = KEY_TITLE, /* "OSD" - fixme */
[0x12] = KEY_0,
[0x13] = KEY_F20, /* "16:9" - fixme */
[0x14] = KEY_SCREEN, /* "FULL" - fixme */
[0x15] = KEY_MUTE,
[0x16] = KEY_SUBTITLE,
[0x17] = KEY_RECORD,
[0x18] = KEY_TEXT,
[0x19] = KEY_AUDIO,
[0x1a] = KEY_RED,
[0x1b] = KEY_PREVIOUS,
[0x1c] = KEY_REWIND,
[0x1d] = KEY_PLAYPAUSE,
[0x1e] = KEY_NEXT,
[0x1f] = KEY_VOLUMEUP,
/* code from device: 0x0340...0x0354 */
[0x20] = KEY_CHANNELUP,
[0x21] = KEY_F21, /* "4:3" - fixme */
[0x22] = KEY_TV,
[0x23] = KEY_DVD,
[0x24] = KEY_VCR,
[0x25] = KEY_AUX,
[0x26] = KEY_GREEN,
[0x27] = KEY_YELLOW,
[0x28] = KEY_BLUE,
[0x29] = KEY_CHANNEL, /* "CH.LIST" */
[0x2a] = KEY_VENDOR, /* "CI" - fixme */
[0x2b] = KEY_VOLUMEDOWN,
[0x2c] = KEY_CHANNELDOWN,
[0x2d] = KEY_LAST,
[0x2e] = KEY_INFO,
[0x2f] = KEY_FORWARD,
[0x30] = KEY_LIST,
[0x31] = KEY_FAVORITES,
[0x32] = KEY_MENU,
[0x33] = KEY_EPG,
[0x34] = KEY_EXIT,
};
int fdtv_register_rc(struct firedtv *fdtv, struct device *dev)
{
struct input_dev *idev;
int i, err;
idev = input_allocate_device();
if (!idev)
return -ENOMEM;
fdtv->remote_ctrl_dev = idev;
idev->name = "FireDTV remote control";
idev->dev.parent = dev;
idev->evbit[0] = BIT_MASK(EV_KEY);
idev->keycode = kmemdup(keytable, sizeof(keytable), GFP_KERNEL);
if (!idev->keycode) {
err = -ENOMEM;
goto fail;
}
idev->keycodesize = sizeof(keytable[0]);
idev->keycodemax = ARRAY_SIZE(keytable);
for (i = 0; i < ARRAY_SIZE(keytable); i++)
set_bit(keytable[i], idev->keybit);
err = input_register_device(idev);
if (err)
goto fail_free_keymap;
return 0;
fail_free_keymap:
kfree(idev->keycode);
fail:
input_free_device(idev);
return err;
}
void fdtv_unregister_rc(struct firedtv *fdtv)
{
cancel_work_sync(&fdtv->remote_ctrl_work);
kfree(fdtv->remote_ctrl_dev->keycode);
input_unregister_device(fdtv->remote_ctrl_dev);
}
void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code)
{
struct input_dev *idev = fdtv->remote_ctrl_dev;
u16 *keycode = idev->keycode;
if (code >= 0x0300 && code <= 0x031f)
code = keycode[code - 0x0300];
else if (code >= 0x0340 && code <= 0x0354)
code = keycode[code - 0x0320];
else if (code >= 0x4501 && code <= 0x451f)
code = oldtable[code - 0x4501];
else if (code >= 0x4540 && code <= 0x4542)
code = oldtable[code - 0x4521];
else {
dev_dbg(fdtv->device,
"invalid key code 0x%04x from remote control\n",
code);
return;
}
input_report_key(idev, code, 1);
input_sync(idev);
input_report_key(idev, code, 0);
input_sync(idev);
}
| linux-master | drivers/media/firewire/firedtv-rc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FireDTV driver (formerly known as FireSAT)
*
* Copyright (C) 2004 Andreas Monitzer <[email protected]>
* Copyright (C) 2008 Ben Backx <[email protected]>
* Copyright (C) 2008 Henrik Kurelid <[email protected]>
*/
#include <linux/bug.h>
#include <linux/crc32.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/string.h>
#include <linux/stringify.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <media/dvb_frontend.h>
#include "firedtv.h"
#define FCP_COMMAND_REGISTER 0xfffff0000b00ULL
#define AVC_CTYPE_CONTROL 0x0
#define AVC_CTYPE_STATUS 0x1
#define AVC_CTYPE_NOTIFY 0x3
#define AVC_RESPONSE_ACCEPTED 0x9
#define AVC_RESPONSE_STABLE 0xc
#define AVC_RESPONSE_CHANGED 0xd
#define AVC_RESPONSE_INTERIM 0xf
#define AVC_SUBUNIT_TYPE_TUNER (0x05 << 3)
#define AVC_SUBUNIT_TYPE_UNIT (0x1f << 3)
#define AVC_OPCODE_VENDOR 0x00
#define AVC_OPCODE_READ_DESCRIPTOR 0x09
#define AVC_OPCODE_DSIT 0xc8
#define AVC_OPCODE_DSD 0xcb
#define DESCRIPTOR_TUNER_STATUS 0x80
#define DESCRIPTOR_SUBUNIT_IDENTIFIER 0x00
#define SFE_VENDOR_DE_COMPANYID_0 0x00 /* OUI of Digital Everywhere */
#define SFE_VENDOR_DE_COMPANYID_1 0x12
#define SFE_VENDOR_DE_COMPANYID_2 0x87
#define SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL 0x0a
#define SFE_VENDOR_OPCODE_LNB_CONTROL 0x52
#define SFE_VENDOR_OPCODE_TUNE_QPSK 0x58 /* for DVB-S */
#define SFE_VENDOR_OPCODE_GET_FIRMWARE_VERSION 0x00
#define SFE_VENDOR_OPCODE_HOST2CA 0x56
#define SFE_VENDOR_OPCODE_CA2HOST 0x57
#define SFE_VENDOR_OPCODE_CISTATUS 0x59
#define SFE_VENDOR_OPCODE_TUNE_QPSK2 0x60 /* for DVB-S2 */
#define SFE_VENDOR_TAG_CA_RESET 0x00
#define SFE_VENDOR_TAG_CA_APPLICATION_INFO 0x01
#define SFE_VENDOR_TAG_CA_PMT 0x02
#define SFE_VENDOR_TAG_CA_DATE_TIME 0x04
#define SFE_VENDOR_TAG_CA_MMI 0x05
#define SFE_VENDOR_TAG_CA_ENTER_MENU 0x07
#define EN50221_LIST_MANAGEMENT_ONLY 0x03
#define EN50221_TAG_APP_INFO 0x9f8021
#define EN50221_TAG_CA_INFO 0x9f8031
struct avc_command_frame {
u8 ctype;
u8 subunit;
u8 opcode;
u8 operand[509];
};
struct avc_response_frame {
u8 response;
u8 subunit;
u8 opcode;
u8 operand[509];
};
#define LAST_OPERAND (509 - 1)
static inline void clear_operands(struct avc_command_frame *c, int from, int to)
{
memset(&c->operand[from], 0, to - from + 1);
}
static void pad_operands(struct avc_command_frame *c, int from)
{
int to = ALIGN(from, 4);
if (from <= to && to <= LAST_OPERAND)
clear_operands(c, from, to);
}
#define AVC_DEBUG_READ_DESCRIPTOR 0x0001
#define AVC_DEBUG_DSIT 0x0002
#define AVC_DEBUG_DSD 0x0004
#define AVC_DEBUG_REGISTER_REMOTE_CONTROL 0x0008
#define AVC_DEBUG_LNB_CONTROL 0x0010
#define AVC_DEBUG_TUNE_QPSK 0x0020
#define AVC_DEBUG_TUNE_QPSK2 0x0040
#define AVC_DEBUG_HOST2CA 0x0080
#define AVC_DEBUG_CA2HOST 0x0100
#define AVC_DEBUG_APPLICATION_PMT 0x4000
#define AVC_DEBUG_FCP_PAYLOADS 0x8000
static int avc_debug;
module_param_named(debug, avc_debug, int, 0644);
MODULE_PARM_DESC(debug, "Verbose logging (none = 0"
", FCP subactions"
": READ DESCRIPTOR = " __stringify(AVC_DEBUG_READ_DESCRIPTOR)
", DSIT = " __stringify(AVC_DEBUG_DSIT)
", REGISTER_REMOTE_CONTROL = " __stringify(AVC_DEBUG_REGISTER_REMOTE_CONTROL)
", LNB CONTROL = " __stringify(AVC_DEBUG_LNB_CONTROL)
", TUNE QPSK = " __stringify(AVC_DEBUG_TUNE_QPSK)
", TUNE QPSK2 = " __stringify(AVC_DEBUG_TUNE_QPSK2)
", HOST2CA = " __stringify(AVC_DEBUG_HOST2CA)
", CA2HOST = " __stringify(AVC_DEBUG_CA2HOST)
"; Application sent PMT = " __stringify(AVC_DEBUG_APPLICATION_PMT)
", FCP payloads = " __stringify(AVC_DEBUG_FCP_PAYLOADS)
", or a combination, or all = -1)");
/*
* This is a workaround since there is no vendor specific command to retrieve
* ca_info using AVC. If this parameter is not used, ca_system_id will be
* filled with application_manufacturer from ca_app_info.
* Digital Everywhere have said that adding ca_info is on their TODO list.
*/
static unsigned int num_fake_ca_system_ids;
static int fake_ca_system_ids[4] = { -1, -1, -1, -1 };
module_param_array(fake_ca_system_ids, int, &num_fake_ca_system_ids, 0644);
MODULE_PARM_DESC(fake_ca_system_ids, "If your CAM application manufacturer "
"does not have the same ca_system_id as your CAS, you can "
"override what ca_system_ids are presented to the "
"application by setting this field to an array of ids.");
static const char *debug_fcp_ctype(unsigned int ctype)
{
static const char *ctypes[] = {
[0x0] = "CONTROL", [0x1] = "STATUS",
[0x2] = "SPECIFIC INQUIRY", [0x3] = "NOTIFY",
[0x4] = "GENERAL INQUIRY", [0x8] = "NOT IMPLEMENTED",
[0x9] = "ACCEPTED", [0xa] = "REJECTED",
[0xb] = "IN TRANSITION", [0xc] = "IMPLEMENTED/STABLE",
[0xd] = "CHANGED", [0xf] = "INTERIM",
};
const char *ret = ctype < ARRAY_SIZE(ctypes) ? ctypes[ctype] : NULL;
return ret ? ret : "?";
}
static const char *debug_fcp_opcode(unsigned int opcode,
const u8 *data, int length)
{
switch (opcode) {
case AVC_OPCODE_VENDOR:
break;
case AVC_OPCODE_READ_DESCRIPTOR:
return avc_debug & AVC_DEBUG_READ_DESCRIPTOR ?
"ReadDescriptor" : NULL;
case AVC_OPCODE_DSIT:
return avc_debug & AVC_DEBUG_DSIT ?
"DirectSelectInfo.Type" : NULL;
case AVC_OPCODE_DSD:
return avc_debug & AVC_DEBUG_DSD ? "DirectSelectData" : NULL;
default:
return "Unknown";
}
if (length < 7 ||
data[3] != SFE_VENDOR_DE_COMPANYID_0 ||
data[4] != SFE_VENDOR_DE_COMPANYID_1 ||
data[5] != SFE_VENDOR_DE_COMPANYID_2)
return "Vendor/Unknown";
switch (data[6]) {
case SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL:
return avc_debug & AVC_DEBUG_REGISTER_REMOTE_CONTROL ?
"RegisterRC" : NULL;
case SFE_VENDOR_OPCODE_LNB_CONTROL:
return avc_debug & AVC_DEBUG_LNB_CONTROL ? "LNBControl" : NULL;
case SFE_VENDOR_OPCODE_TUNE_QPSK:
return avc_debug & AVC_DEBUG_TUNE_QPSK ? "TuneQPSK" : NULL;
case SFE_VENDOR_OPCODE_TUNE_QPSK2:
return avc_debug & AVC_DEBUG_TUNE_QPSK2 ? "TuneQPSK2" : NULL;
case SFE_VENDOR_OPCODE_HOST2CA:
return avc_debug & AVC_DEBUG_HOST2CA ? "Host2CA" : NULL;
case SFE_VENDOR_OPCODE_CA2HOST:
return avc_debug & AVC_DEBUG_CA2HOST ? "CA2Host" : NULL;
}
return "Vendor/Unknown";
}
static void debug_fcp(const u8 *data, int length)
{
unsigned int subunit_type, subunit_id, opcode;
const char *op, *prefix;
prefix = data[0] > 7 ? "FCP <- " : "FCP -> ";
subunit_type = data[1] >> 3;
subunit_id = data[1] & 7;
opcode = subunit_type == 0x1e || subunit_id == 5 ? ~0 : data[2];
op = debug_fcp_opcode(opcode, data, length);
if (op) {
printk(KERN_INFO "%ssu=%x.%x l=%d: %-8s - %s\n",
prefix, subunit_type, subunit_id, length,
debug_fcp_ctype(data[0]), op);
if (avc_debug & AVC_DEBUG_FCP_PAYLOADS)
print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_NONE,
16, 1, data, length, false);
}
}
static void debug_pmt(char *msg, int length)
{
printk(KERN_INFO "APP PMT -> l=%d\n", length);
print_hex_dump(KERN_INFO, "APP PMT -> ", DUMP_PREFIX_NONE,
16, 1, msg, length, false);
}
static int avc_write(struct firedtv *fdtv)
{
int err, retry;
fdtv->avc_reply_received = false;
for (retry = 0; retry < 6; retry++) {
if (unlikely(avc_debug))
debug_fcp(fdtv->avc_data, fdtv->avc_data_length);
err = fdtv_write(fdtv, FCP_COMMAND_REGISTER,
fdtv->avc_data, fdtv->avc_data_length);
if (err) {
dev_err(fdtv->device, "FCP command write failed\n");
return err;
}
/*
* AV/C specs say that answers should be sent within 150 ms.
* Time out after 200 ms.
*/
if (wait_event_timeout(fdtv->avc_wait,
fdtv->avc_reply_received,
msecs_to_jiffies(200)) != 0)
return 0;
}
dev_err(fdtv->device, "FCP response timed out\n");
return -ETIMEDOUT;
}
static bool is_register_rc(struct avc_response_frame *r)
{
return r->opcode == AVC_OPCODE_VENDOR &&
r->operand[0] == SFE_VENDOR_DE_COMPANYID_0 &&
r->operand[1] == SFE_VENDOR_DE_COMPANYID_1 &&
r->operand[2] == SFE_VENDOR_DE_COMPANYID_2 &&
r->operand[3] == SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL;
}
int avc_recv(struct firedtv *fdtv, void *data, size_t length)
{
struct avc_response_frame *r = data;
if (unlikely(avc_debug))
debug_fcp(data, length);
if (length >= 8 && is_register_rc(r)) {
switch (r->response) {
case AVC_RESPONSE_CHANGED:
fdtv_handle_rc(fdtv, r->operand[4] << 8 | r->operand[5]);
schedule_work(&fdtv->remote_ctrl_work);
break;
case AVC_RESPONSE_INTERIM:
if (is_register_rc((void *)fdtv->avc_data))
goto wake;
break;
default:
dev_info(fdtv->device,
"remote control result = %d\n", r->response);
}
return 0;
}
if (fdtv->avc_reply_received) {
dev_err(fdtv->device, "out-of-order AVC response, ignored\n");
return -EIO;
}
memcpy(fdtv->avc_data, data, length);
fdtv->avc_data_length = length;
wake:
fdtv->avc_reply_received = true;
wake_up(&fdtv->avc_wait);
return 0;
}
static int add_pid_filter(struct firedtv *fdtv, u8 *operand)
{
int i, n, pos = 1;
for (i = 0, n = 0; i < 16; i++) {
if (test_bit(i, &fdtv->channel_active)) {
operand[pos++] = 0x13; /* flowfunction relay */
operand[pos++] = 0x80; /* dsd_sel_spec_valid_flags -> PID */
operand[pos++] = (fdtv->channel_pid[i] >> 8) & 0x1f;
operand[pos++] = fdtv->channel_pid[i] & 0xff;
operand[pos++] = 0x00; /* tableID */
operand[pos++] = 0x00; /* filter_length */
n++;
}
}
operand[0] = n;
return pos;
}
/*
* tuning command for setting the relative LNB frequency
* (not supported by the AVC standard)
*/
static int avc_tuner_tuneqpsk(struct firedtv *fdtv,
struct dtv_frontend_properties *p)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
if (fdtv->type == FIREDTV_DVB_S2)
c->operand[3] = SFE_VENDOR_OPCODE_TUNE_QPSK2;
else
c->operand[3] = SFE_VENDOR_OPCODE_TUNE_QPSK;
c->operand[4] = (p->frequency >> 24) & 0xff;
c->operand[5] = (p->frequency >> 16) & 0xff;
c->operand[6] = (p->frequency >> 8) & 0xff;
c->operand[7] = p->frequency & 0xff;
c->operand[8] = ((p->symbol_rate / 1000) >> 8) & 0xff;
c->operand[9] = (p->symbol_rate / 1000) & 0xff;
switch (p->fec_inner) {
case FEC_1_2: c->operand[10] = 0x1; break;
case FEC_2_3: c->operand[10] = 0x2; break;
case FEC_3_4: c->operand[10] = 0x3; break;
case FEC_5_6: c->operand[10] = 0x4; break;
case FEC_7_8: c->operand[10] = 0x5; break;
case FEC_4_5:
case FEC_8_9:
case FEC_AUTO:
default: c->operand[10] = 0x0;
}
if (fdtv->voltage == 0xff)
c->operand[11] = 0xff;
else if (fdtv->voltage == SEC_VOLTAGE_18) /* polarisation */
c->operand[11] = 0;
else
c->operand[11] = 1;
if (fdtv->tone == 0xff)
c->operand[12] = 0xff;
else if (fdtv->tone == SEC_TONE_ON) /* band */
c->operand[12] = 1;
else
c->operand[12] = 0;
if (fdtv->type == FIREDTV_DVB_S2) {
if (fdtv->fe.dtv_property_cache.delivery_system == SYS_DVBS2) {
switch (fdtv->fe.dtv_property_cache.modulation) {
case QAM_16: c->operand[13] = 0x1; break;
case QPSK: c->operand[13] = 0x2; break;
case PSK_8: c->operand[13] = 0x3; break;
default: c->operand[13] = 0x2; break;
}
switch (fdtv->fe.dtv_property_cache.rolloff) {
case ROLLOFF_35: c->operand[14] = 0x2; break;
case ROLLOFF_20: c->operand[14] = 0x0; break;
case ROLLOFF_25: c->operand[14] = 0x1; break;
case ROLLOFF_AUTO:
default: c->operand[14] = 0x2; break;
/* case ROLLOFF_NONE: c->operand[14] = 0xff; break; */
}
switch (fdtv->fe.dtv_property_cache.pilot) {
case PILOT_AUTO: c->operand[15] = 0x0; break;
case PILOT_OFF: c->operand[15] = 0x0; break;
case PILOT_ON: c->operand[15] = 0x1; break;
}
} else {
c->operand[13] = 0x1; /* auto modulation */
c->operand[14] = 0xff; /* disable rolloff */
c->operand[15] = 0xff; /* disable pilot */
}
return 16;
} else {
return 13;
}
}
static int avc_tuner_dsd_dvb_c(struct firedtv *fdtv,
struct dtv_frontend_properties *p)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
c->opcode = AVC_OPCODE_DSD;
c->operand[0] = 0; /* source plug */
c->operand[1] = 0xd2; /* subfunction replace */
c->operand[2] = 0x20; /* system id = DVB */
c->operand[3] = 0x00; /* antenna number */
c->operand[4] = 0x11; /* system_specific_multiplex selection_length */
/* multiplex_valid_flags, high byte */
c->operand[5] = 0 << 7 /* reserved */
| 0 << 6 /* Polarisation */
| 0 << 5 /* Orbital_Pos */
| 1 << 4 /* Frequency */
| 1 << 3 /* Symbol_Rate */
| 0 << 2 /* FEC_outer */
| (p->fec_inner != FEC_AUTO ? 1 << 1 : 0)
| (p->modulation != QAM_AUTO ? 1 << 0 : 0);
/* multiplex_valid_flags, low byte */
c->operand[6] = 0 << 7 /* NetworkID */
| 0 << 0 /* reserved */ ;
c->operand[7] = 0x00;
c->operand[8] = 0x00;
c->operand[9] = 0x00;
c->operand[10] = 0x00;
c->operand[11] = (((p->frequency / 4000) >> 16) & 0xff) | (2 << 6);
c->operand[12] = ((p->frequency / 4000) >> 8) & 0xff;
c->operand[13] = (p->frequency / 4000) & 0xff;
c->operand[14] = ((p->symbol_rate / 1000) >> 12) & 0xff;
c->operand[15] = ((p->symbol_rate / 1000) >> 4) & 0xff;
c->operand[16] = ((p->symbol_rate / 1000) << 4) & 0xf0;
c->operand[17] = 0x00;
switch (p->fec_inner) {
case FEC_1_2: c->operand[18] = 0x1; break;
case FEC_2_3: c->operand[18] = 0x2; break;
case FEC_3_4: c->operand[18] = 0x3; break;
case FEC_5_6: c->operand[18] = 0x4; break;
case FEC_7_8: c->operand[18] = 0x5; break;
case FEC_8_9: c->operand[18] = 0x6; break;
case FEC_4_5: c->operand[18] = 0x8; break;
case FEC_AUTO:
default: c->operand[18] = 0x0;
}
switch (p->modulation) {
case QAM_16: c->operand[19] = 0x08; break;
case QAM_32: c->operand[19] = 0x10; break;
case QAM_64: c->operand[19] = 0x18; break;
case QAM_128: c->operand[19] = 0x20; break;
case QAM_256: c->operand[19] = 0x28; break;
case QAM_AUTO:
default: c->operand[19] = 0x00;
}
c->operand[20] = 0x00;
c->operand[21] = 0x00;
return 22 + add_pid_filter(fdtv, &c->operand[22]);
}
static int avc_tuner_dsd_dvb_t(struct firedtv *fdtv,
struct dtv_frontend_properties *p)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
c->opcode = AVC_OPCODE_DSD;
c->operand[0] = 0; /* source plug */
c->operand[1] = 0xd2; /* subfunction replace */
c->operand[2] = 0x20; /* system id = DVB */
c->operand[3] = 0x00; /* antenna number */
c->operand[4] = 0x0c; /* system_specific_multiplex selection_length */
/* multiplex_valid_flags, high byte */
c->operand[5] =
0 << 7 /* reserved */
| 1 << 6 /* CenterFrequency */
| (p->bandwidth_hz != 0 ? 1 << 5 : 0)
| (p->modulation != QAM_AUTO ? 1 << 4 : 0)
| (p->hierarchy != HIERARCHY_AUTO ? 1 << 3 : 0)
| (p->code_rate_HP != FEC_AUTO ? 1 << 2 : 0)
| (p->code_rate_LP != FEC_AUTO ? 1 << 1 : 0)
| (p->guard_interval != GUARD_INTERVAL_AUTO ? 1 << 0 : 0);
/* multiplex_valid_flags, low byte */
c->operand[6] =
0 << 7 /* NetworkID */
| (p->transmission_mode != TRANSMISSION_MODE_AUTO ? 1 << 6 : 0)
| 0 << 5 /* OtherFrequencyFlag */
| 0 << 0 /* reserved */ ;
c->operand[7] = 0x0;
c->operand[8] = (p->frequency / 10) >> 24;
c->operand[9] = ((p->frequency / 10) >> 16) & 0xff;
c->operand[10] = ((p->frequency / 10) >> 8) & 0xff;
c->operand[11] = (p->frequency / 10) & 0xff;
switch (p->bandwidth_hz) {
case 7000000: c->operand[12] = 0x20; break;
case 8000000:
case 6000000: /* not defined by AVC spec */
case 0:
default: c->operand[12] = 0x00;
}
switch (p->modulation) {
case QAM_16: c->operand[13] = 1 << 6; break;
case QAM_64: c->operand[13] = 2 << 6; break;
case QPSK:
default: c->operand[13] = 0x00;
}
switch (p->hierarchy) {
case HIERARCHY_1: c->operand[13] |= 1 << 3; break;
case HIERARCHY_2: c->operand[13] |= 2 << 3; break;
case HIERARCHY_4: c->operand[13] |= 3 << 3; break;
case HIERARCHY_AUTO:
case HIERARCHY_NONE:
default: break;
}
switch (p->code_rate_HP) {
case FEC_2_3: c->operand[13] |= 1; break;
case FEC_3_4: c->operand[13] |= 2; break;
case FEC_5_6: c->operand[13] |= 3; break;
case FEC_7_8: c->operand[13] |= 4; break;
case FEC_1_2:
default: break;
}
switch (p->code_rate_LP) {
case FEC_2_3: c->operand[14] = 1 << 5; break;
case FEC_3_4: c->operand[14] = 2 << 5; break;
case FEC_5_6: c->operand[14] = 3 << 5; break;
case FEC_7_8: c->operand[14] = 4 << 5; break;
case FEC_1_2:
default: c->operand[14] = 0x00; break;
}
switch (p->guard_interval) {
case GUARD_INTERVAL_1_16: c->operand[14] |= 1 << 3; break;
case GUARD_INTERVAL_1_8: c->operand[14] |= 2 << 3; break;
case GUARD_INTERVAL_1_4: c->operand[14] |= 3 << 3; break;
case GUARD_INTERVAL_1_32:
case GUARD_INTERVAL_AUTO:
default: break;
}
switch (p->transmission_mode) {
case TRANSMISSION_MODE_8K: c->operand[14] |= 1 << 1; break;
case TRANSMISSION_MODE_2K:
case TRANSMISSION_MODE_AUTO:
default: break;
}
c->operand[15] = 0x00; /* network_ID[0] */
c->operand[16] = 0x00; /* network_ID[1] */
return 17 + add_pid_filter(fdtv, &c->operand[17]);
}
int avc_tuner_dsd(struct firedtv *fdtv,
struct dtv_frontend_properties *p)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int pos, ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
switch (fdtv->type) {
case FIREDTV_DVB_S:
case FIREDTV_DVB_S2: pos = avc_tuner_tuneqpsk(fdtv, p); break;
case FIREDTV_DVB_C: pos = avc_tuner_dsd_dvb_c(fdtv, p); break;
case FIREDTV_DVB_T: pos = avc_tuner_dsd_dvb_t(fdtv, p); break;
default:
ret = -EIO;
goto unlock;
}
pad_operands(c, pos);
fdtv->avc_data_length = ALIGN(3 + pos, 4);
ret = avc_write(fdtv);
#if 0
/*
* FIXME:
* u8 *status was an out-parameter of avc_tuner_dsd, unused by caller.
* Check for AVC_RESPONSE_ACCEPTED here instead?
*/
if (status)
*status = r->operand[2];
#endif
unlock:
mutex_unlock(&fdtv->avc_mutex);
if (ret == 0)
msleep(500);
return ret;
}
int avc_tuner_set_pids(struct firedtv *fdtv, unsigned char pidc, u16 pid[])
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret, pos, k;
if (pidc > 16 && pidc != 0xff)
return -EINVAL;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_DSD;
c->operand[0] = 0; /* source plug */
c->operand[1] = 0xd2; /* subfunction replace */
c->operand[2] = 0x20; /* system id = DVB */
c->operand[3] = 0x00; /* antenna number */
c->operand[4] = 0x00; /* system_specific_multiplex selection_length */
c->operand[5] = pidc; /* Nr_of_dsd_sel_specs */
pos = 6;
if (pidc != 0xff)
for (k = 0; k < pidc; k++) {
c->operand[pos++] = 0x13; /* flowfunction relay */
c->operand[pos++] = 0x80; /* dsd_sel_spec_valid_flags -> PID */
c->operand[pos++] = (pid[k] >> 8) & 0x1f;
c->operand[pos++] = pid[k] & 0xff;
c->operand[pos++] = 0x00; /* tableID */
c->operand[pos++] = 0x00; /* filter_length */
}
pad_operands(c, pos);
fdtv->avc_data_length = ALIGN(3 + pos, 4);
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
if (ret == 0)
msleep(50);
return ret;
}
int avc_tuner_get_ts(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret, sl;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_DSIT;
sl = fdtv->type == FIREDTV_DVB_T ? 0x0c : 0x11;
c->operand[0] = 0; /* source plug */
c->operand[1] = 0xd2; /* subfunction replace */
c->operand[2] = 0xff; /* status */
c->operand[3] = 0x20; /* system id = DVB */
c->operand[4] = 0x00; /* antenna number */
c->operand[5] = 0x0; /* system_specific_search_flags */
c->operand[6] = sl; /* system_specific_multiplex selection_length */
/*
* operand[7]: valid_flags[0]
* operand[8]: valid_flags[1]
* operand[7 + sl]: nr_of_dsit_sel_specs (always 0)
*/
clear_operands(c, 7, 24);
fdtv->avc_data_length = fdtv->type == FIREDTV_DVB_T ? 24 : 28;
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
if (ret == 0)
msleep(250);
return ret;
}
int avc_identify_subunit(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_READ_DESCRIPTOR;
c->operand[0] = DESCRIPTOR_SUBUNIT_IDENTIFIER;
c->operand[1] = 0xff;
c->operand[2] = 0x00;
c->operand[3] = 0x00; /* length highbyte */
c->operand[4] = 0x08; /* length lowbyte */
c->operand[5] = 0x00; /* offset highbyte */
c->operand[6] = 0x0d; /* offset lowbyte */
clear_operands(c, 7, 8); /* padding */
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
if ((r->response != AVC_RESPONSE_STABLE &&
r->response != AVC_RESPONSE_ACCEPTED) ||
(r->operand[3] << 8) + r->operand[4] != 8) {
dev_err(fdtv->device, "cannot read subunit identifier\n");
ret = -EINVAL;
}
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
#define SIZEOF_ANTENNA_INPUT_INFO 22
int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int length, ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_READ_DESCRIPTOR;
c->operand[0] = DESCRIPTOR_TUNER_STATUS;
c->operand[1] = 0xff; /* read_result_status */
/*
* operand[2]: reserved
* operand[3]: SIZEOF_ANTENNA_INPUT_INFO >> 8
* operand[4]: SIZEOF_ANTENNA_INPUT_INFO & 0xff
*/
clear_operands(c, 2, 31);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
if (r->response != AVC_RESPONSE_STABLE &&
r->response != AVC_RESPONSE_ACCEPTED) {
dev_err(fdtv->device, "cannot read tuner status\n");
ret = -EINVAL;
goto out;
}
length = r->operand[9];
if (r->operand[1] != 0x10 || length != SIZEOF_ANTENNA_INPUT_INFO) {
dev_err(fdtv->device, "got invalid tuner status\n");
ret = -EINVAL;
goto out;
}
stat->active_system = r->operand[10];
stat->searching = r->operand[11] >> 7 & 1;
stat->moving = r->operand[11] >> 6 & 1;
stat->no_rf = r->operand[11] >> 5 & 1;
stat->input = r->operand[12] >> 7 & 1;
stat->selected_antenna = r->operand[12] & 0x7f;
stat->ber = r->operand[13] << 24 |
r->operand[14] << 16 |
r->operand[15] << 8 |
r->operand[16];
stat->signal_strength = r->operand[17];
stat->raster_frequency = r->operand[18] >> 6 & 2;
stat->rf_frequency = (r->operand[18] & 0x3f) << 16 |
r->operand[19] << 8 |
r->operand[20];
stat->man_dep_info_length = r->operand[21];
stat->front_end_error = r->operand[22] >> 4 & 1;
stat->antenna_error = r->operand[22] >> 3 & 1;
stat->front_end_power_status = r->operand[22] >> 1 & 1;
stat->power_supply = r->operand[22] & 1;
stat->carrier_noise_ratio = r->operand[23] << 8 |
r->operand[24];
stat->power_supply_voltage = r->operand[27];
stat->antenna_voltage = r->operand[28];
stat->firewire_bus_voltage = r->operand[29];
stat->ca_mmi = r->operand[30] & 1;
stat->ca_pmt_reply = r->operand[31] >> 7 & 1;
stat->ca_date_time_request = r->operand[31] >> 6 & 1;
stat->ca_application_info = r->operand[31] >> 5 & 1;
stat->ca_module_present_status = r->operand[31] >> 4 & 1;
stat->ca_dvb_flag = r->operand[31] >> 3 & 1;
stat->ca_error_flag = r->operand[31] >> 2 & 1;
stat->ca_initialization_status = r->operand[31] >> 1 & 1;
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst,
char conttone, char nrdiseq,
struct dvb_diseqc_master_cmd *diseqcmd)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int pos, j, k, ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_LNB_CONTROL;
c->operand[4] = voltage;
c->operand[5] = nrdiseq;
pos = 6;
for (j = 0; j < nrdiseq; j++) {
c->operand[pos++] = diseqcmd[j].msg_len;
for (k = 0; k < diseqcmd[j].msg_len; k++)
c->operand[pos++] = diseqcmd[j].msg[k];
}
c->operand[pos++] = burst;
c->operand[pos++] = conttone;
pad_operands(c, pos);
fdtv->avc_data_length = ALIGN(3 + pos, 4);
ret = avc_write(fdtv);
if (ret < 0)
goto out;
if (r->response != AVC_RESPONSE_ACCEPTED) {
dev_err(fdtv->device, "LNB control failed\n");
ret = -EINVAL;
}
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_register_remote_control(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_NOTIFY;
c->subunit = AVC_SUBUNIT_TYPE_UNIT | 7;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL;
c->operand[4] = 0; /* padding */
fdtv->avc_data_length = 8;
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
void avc_remote_ctrl_work(struct work_struct *work)
{
struct firedtv *fdtv =
container_of(work, struct firedtv, remote_ctrl_work);
/* Should it be rescheduled in failure cases? */
avc_register_remote_control(fdtv);
}
#if 0 /* FIXME: unused */
int avc_tuner_host2ca(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
clear_operands(c, 6, 8);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
#endif
static int get_ca_object_pos(struct avc_response_frame *r)
{
int length = 1;
/* Check length of length field */
if (r->operand[7] & 0x80)
length = (r->operand[7] & 0x7f) + 1;
return length + 7;
}
static int get_ca_object_length(struct avc_response_frame *r)
{
#if 0 /* FIXME: unused */
int size = 0;
int i;
if (r->operand[7] & 0x80)
for (i = 0; i < (r->operand[7] & 0x7f); i++) {
size <<= 8;
size += r->operand[8 + i];
}
#endif
return r->operand[7];
}
int avc_ca_app_info(struct firedtv *fdtv, unsigned char *app_info,
unsigned int *len)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int pos, ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_STATUS;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
clear_operands(c, 6, LAST_OPERAND);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
/* FIXME: check response code and validate response data */
pos = get_ca_object_pos(r);
app_info[0] = (EN50221_TAG_APP_INFO >> 16) & 0xff;
app_info[1] = (EN50221_TAG_APP_INFO >> 8) & 0xff;
app_info[2] = (EN50221_TAG_APP_INFO >> 0) & 0xff;
app_info[3] = 6 + r->operand[pos + 4];
app_info[4] = 0x01;
memcpy(&app_info[5], &r->operand[pos], 5 + r->operand[pos + 4]);
*len = app_info[3] + 4;
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_info(struct firedtv *fdtv, unsigned char *app_info,
unsigned int *len)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int i, pos, ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_STATUS;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
clear_operands(c, 6, LAST_OPERAND);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
/* FIXME: check response code and validate response data */
pos = get_ca_object_pos(r);
app_info[0] = (EN50221_TAG_CA_INFO >> 16) & 0xff;
app_info[1] = (EN50221_TAG_CA_INFO >> 8) & 0xff;
app_info[2] = (EN50221_TAG_CA_INFO >> 0) & 0xff;
if (num_fake_ca_system_ids == 0) {
app_info[3] = 2;
app_info[4] = r->operand[pos + 0];
app_info[5] = r->operand[pos + 1];
} else {
app_info[3] = num_fake_ca_system_ids * 2;
for (i = 0; i < num_fake_ca_system_ids; i++) {
app_info[4 + i * 2] =
(fake_ca_system_ids[i] >> 8) & 0xff;
app_info[5 + i * 2] = fake_ca_system_ids[i] & 0xff;
}
}
*len = app_info[3] + 4;
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_reset(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_RESET; /* ca tag */
c->operand[6] = 0; /* more/last */
c->operand[7] = 1; /* length */
c->operand[8] = 0; /* force hardware reset */
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_pmt(struct firedtv *fdtv, char *msg, int length)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int list_management;
int program_info_length;
int pmt_cmd_id;
int read_pos;
int write_pos;
int es_info_length;
int crc32_csum;
int ret;
if (unlikely(avc_debug & AVC_DEBUG_APPLICATION_PMT))
debug_pmt(msg, length);
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_CONTROL;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
if (msg[0] != EN50221_LIST_MANAGEMENT_ONLY) {
dev_info(fdtv->device, "forcing list_management to ONLY\n");
msg[0] = EN50221_LIST_MANAGEMENT_ONLY;
}
/* We take the cmd_id from the programme level only! */
list_management = msg[0];
program_info_length = ((msg[4] & 0x0f) << 8) + msg[5];
if (program_info_length > 0)
program_info_length--; /* Remove pmt_cmd_id */
pmt_cmd_id = msg[6];
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_PMT; /* ca tag */
c->operand[6] = 0; /* more/last */
/* Use three bytes for length field in case length > 127 */
c->operand[10] = list_management;
c->operand[11] = 0x01; /* pmt_cmd=OK_descramble */
/* TS program map table */
c->operand[12] = 0x02; /* Table id=2 */
c->operand[13] = 0x80; /* Section syntax + length */
c->operand[15] = msg[1]; /* Program number */
c->operand[16] = msg[2];
c->operand[17] = msg[3]; /* Version number and current/next */
c->operand[18] = 0x00; /* Section number=0 */
c->operand[19] = 0x00; /* Last section number=0 */
c->operand[20] = 0x1f; /* PCR_PID=1FFF */
c->operand[21] = 0xff;
c->operand[22] = (program_info_length >> 8); /* Program info length */
c->operand[23] = (program_info_length & 0xff);
/* CA descriptors at programme level */
read_pos = 6;
write_pos = 24;
if (program_info_length > 0) {
pmt_cmd_id = msg[read_pos++];
if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
dev_err(fdtv->device,
"invalid pmt_cmd_id %d\n", pmt_cmd_id);
if (program_info_length > sizeof(c->operand) - 4 - write_pos) {
ret = -EINVAL;
goto out;
}
memcpy(&c->operand[write_pos], &msg[read_pos],
program_info_length);
read_pos += program_info_length;
write_pos += program_info_length;
}
while (read_pos + 4 < length) {
if (write_pos + 4 >= sizeof(c->operand) - 4) {
ret = -EINVAL;
goto out;
}
c->operand[write_pos++] = msg[read_pos++];
c->operand[write_pos++] = msg[read_pos++];
c->operand[write_pos++] = msg[read_pos++];
es_info_length =
((msg[read_pos] & 0x0f) << 8) + msg[read_pos + 1];
read_pos += 2;
if (es_info_length > 0)
es_info_length--; /* Remove pmt_cmd_id */
c->operand[write_pos++] = es_info_length >> 8;
c->operand[write_pos++] = es_info_length & 0xff;
if (es_info_length > 0) {
if (read_pos >= length) {
ret = -EINVAL;
goto out;
}
pmt_cmd_id = msg[read_pos++];
if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
dev_err(fdtv->device, "invalid pmt_cmd_id %d at stream level\n",
pmt_cmd_id);
if (es_info_length > sizeof(c->operand) - 4 - write_pos ||
es_info_length > length - read_pos) {
ret = -EINVAL;
goto out;
}
memcpy(&c->operand[write_pos], &msg[read_pos],
es_info_length);
read_pos += es_info_length;
write_pos += es_info_length;
}
}
write_pos += 4; /* CRC */
c->operand[7] = 0x82;
c->operand[8] = (write_pos - 10) >> 8;
c->operand[9] = (write_pos - 10) & 0xff;
c->operand[14] = write_pos - 15;
crc32_csum = crc32_be(0, &c->operand[10], c->operand[12] - 1);
c->operand[write_pos - 4] = (crc32_csum >> 24) & 0xff;
c->operand[write_pos - 3] = (crc32_csum >> 16) & 0xff;
c->operand[write_pos - 2] = (crc32_csum >> 8) & 0xff;
c->operand[write_pos - 1] = (crc32_csum >> 0) & 0xff;
pad_operands(c, write_pos);
fdtv->avc_data_length = ALIGN(3 + write_pos, 4);
ret = avc_write(fdtv);
if (ret < 0)
goto out;
if (r->response != AVC_RESPONSE_ACCEPTED) {
dev_err(fdtv->device,
"CA PMT failed with response 0x%x\n", r->response);
ret = -EACCES;
}
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_get_time_date(struct firedtv *fdtv, int *interval)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_STATUS;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_DATE_TIME; /* ca tag */
clear_operands(c, 6, LAST_OPERAND);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
/* FIXME: check response code and validate response data */
*interval = r->operand[get_ca_object_pos(r)];
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_enter_menu(struct firedtv *fdtv)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_STATUS;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_ENTER_MENU;
clear_operands(c, 6, 8);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
/* FIXME: check response code? */
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len)
{
struct avc_command_frame *c = (void *)fdtv->avc_data;
struct avc_response_frame *r = (void *)fdtv->avc_data;
int ret;
mutex_lock(&fdtv->avc_mutex);
c->ctype = AVC_CTYPE_STATUS;
c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
c->opcode = AVC_OPCODE_VENDOR;
c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
c->operand[4] = 0; /* slot */
c->operand[5] = SFE_VENDOR_TAG_CA_MMI;
clear_operands(c, 6, LAST_OPERAND);
fdtv->avc_data_length = 12;
ret = avc_write(fdtv);
if (ret < 0)
goto out;
/* FIXME: check response code and validate response data */
*len = get_ca_object_length(r);
memcpy(mmi_object, &r->operand[get_ca_object_pos(r)], *len);
out:
mutex_unlock(&fdtv->avc_mutex);
return ret;
}
#define CMP_OUTPUT_PLUG_CONTROL_REG_0 0xfffff0000904ULL
static int cmp_read(struct firedtv *fdtv, u64 addr, __be32 *data)
{
int ret;
ret = fdtv_read(fdtv, addr, data);
if (ret < 0)
dev_err(fdtv->device, "CMP: read I/O error\n");
return ret;
}
static int cmp_lock(struct firedtv *fdtv, u64 addr, __be32 data[])
{
int ret;
ret = fdtv_lock(fdtv, addr, data);
if (ret < 0)
dev_err(fdtv->device, "CMP: lock I/O error\n");
return ret;
}
static inline u32 get_opcr(__be32 opcr, u32 mask, u32 shift)
{
return (be32_to_cpu(opcr) >> shift) & mask;
}
static inline void set_opcr(__be32 *opcr, u32 value, u32 mask, u32 shift)
{
*opcr &= ~cpu_to_be32(mask << shift);
*opcr |= cpu_to_be32((value & mask) << shift);
}
#define get_opcr_online(v) get_opcr((v), 0x1, 31)
#define get_opcr_p2p_connections(v) get_opcr((v), 0x3f, 24)
#define get_opcr_channel(v) get_opcr((v), 0x3f, 16)
#define set_opcr_p2p_connections(p, v) set_opcr((p), (v), 0x3f, 24)
#define set_opcr_channel(p, v) set_opcr((p), (v), 0x3f, 16)
#define set_opcr_data_rate(p, v) set_opcr((p), (v), 0x3, 14)
#define set_opcr_overhead_id(p, v) set_opcr((p), (v), 0xf, 10)
int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel)
{
__be32 old_opcr, opcr[2];
u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
int attempts = 0;
int ret;
ret = cmp_read(fdtv, opcr_address, opcr);
if (ret < 0)
return ret;
repeat:
if (!get_opcr_online(*opcr)) {
dev_err(fdtv->device, "CMP: output offline\n");
return -EBUSY;
}
old_opcr = *opcr;
if (get_opcr_p2p_connections(*opcr)) {
if (get_opcr_channel(*opcr) != channel) {
dev_err(fdtv->device, "CMP: cannot change channel\n");
return -EBUSY;
}
dev_info(fdtv->device, "CMP: overlaying connection\n");
/* We don't allocate isochronous resources. */
} else {
set_opcr_channel(opcr, channel);
set_opcr_data_rate(opcr, 2); /* S400 */
/* FIXME: this is for the worst case - optimize */
set_opcr_overhead_id(opcr, 0);
/* FIXME: allocate isochronous channel and bandwidth at IRM */
}
set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) + 1);
opcr[1] = *opcr;
opcr[0] = old_opcr;
ret = cmp_lock(fdtv, opcr_address, opcr);
if (ret < 0)
return ret;
if (old_opcr != *opcr) {
/*
* FIXME: if old_opcr.P2P_Connections > 0,
* deallocate isochronous channel and bandwidth at IRM
*/
if (++attempts < 6) /* arbitrary limit */
goto repeat;
return -EBUSY;
}
return 0;
}
void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel)
{
__be32 old_opcr, opcr[2];
u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
int attempts = 0;
if (cmp_read(fdtv, opcr_address, opcr) < 0)
return;
repeat:
if (!get_opcr_online(*opcr) || !get_opcr_p2p_connections(*opcr) ||
get_opcr_channel(*opcr) != channel) {
dev_err(fdtv->device, "CMP: no connection to break\n");
return;
}
old_opcr = *opcr;
set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) - 1);
opcr[1] = *opcr;
opcr[0] = old_opcr;
if (cmp_lock(fdtv, opcr_address, opcr) < 0)
return;
if (old_opcr != *opcr) {
/*
* FIXME: if old_opcr.P2P_Connections == 1, i.e. we were last
* owner, deallocate isochronous channel and bandwidth at IRM
* if (...)
* fdtv->backend->dealloc_resources(fdtv, channel, bw);
*/
if (++attempts < 6) /* arbitrary limit */
goto repeat;
}
}
| linux-master | drivers/media/firewire/firedtv-avc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* FireDTV driver -- firewire I/O backend
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/firewire.h>
#include <linux/firewire-constants.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <asm/page.h>
#include <media/dvb_demux.h>
#include "firedtv.h"
static LIST_HEAD(node_list);
static DEFINE_SPINLOCK(node_list_lock);
static inline struct fw_device *device_of(struct firedtv *fdtv)
{
return fw_device(fdtv->device->parent);
}
static int node_req(struct firedtv *fdtv, u64 addr, void *data, size_t len,
int tcode)
{
struct fw_device *device = device_of(fdtv);
int rcode, generation = device->generation;
smp_rmb(); /* node_id vs. generation */
rcode = fw_run_transaction(device->card, tcode, device->node_id,
generation, device->max_speed, addr, data, len);
return rcode != RCODE_COMPLETE ? -EIO : 0;
}
int fdtv_lock(struct firedtv *fdtv, u64 addr, void *data)
{
return node_req(fdtv, addr, data, 8, TCODE_LOCK_COMPARE_SWAP);
}
int fdtv_read(struct firedtv *fdtv, u64 addr, void *data)
{
return node_req(fdtv, addr, data, 4, TCODE_READ_QUADLET_REQUEST);
}
int fdtv_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
{
return node_req(fdtv, addr, data, len, TCODE_WRITE_BLOCK_REQUEST);
}
#define ISO_HEADER_SIZE 4
#define CIP_HEADER_SIZE 8
#define MPEG2_TS_HEADER_SIZE 4
#define MPEG2_TS_SOURCE_PACKET_SIZE (4 + 188)
#define MAX_PACKET_SIZE 1024 /* 776, rounded up to 2^n */
#define PACKETS_PER_PAGE (PAGE_SIZE / MAX_PACKET_SIZE)
#define N_PACKETS 64 /* buffer size */
#define N_PAGES DIV_ROUND_UP(N_PACKETS, PACKETS_PER_PAGE)
#define IRQ_INTERVAL 16
struct fdtv_ir_context {
struct fw_iso_context *context;
struct fw_iso_buffer buffer;
int interrupt_packet;
int current_packet;
char *pages[N_PAGES];
};
static int queue_iso(struct fdtv_ir_context *ctx, int index)
{
struct fw_iso_packet p;
p.payload_length = MAX_PACKET_SIZE;
p.interrupt = !(++ctx->interrupt_packet & (IRQ_INTERVAL - 1));
p.skip = 0;
p.header_length = ISO_HEADER_SIZE;
return fw_iso_context_queue(ctx->context, &p, &ctx->buffer,
index * MAX_PACKET_SIZE);
}
static void handle_iso(struct fw_iso_context *context, u32 cycle,
size_t header_length, void *header, void *data)
{
struct firedtv *fdtv = data;
struct fdtv_ir_context *ctx = fdtv->ir_context;
__be32 *h, *h_end;
int length, err, i = ctx->current_packet;
char *p, *p_end;
for (h = header, h_end = h + header_length / 4; h < h_end; h++) {
length = be32_to_cpup(h) >> 16;
if (unlikely(length > MAX_PACKET_SIZE)) {
dev_err(fdtv->device, "length = %d\n", length);
length = MAX_PACKET_SIZE;
}
p = ctx->pages[i / PACKETS_PER_PAGE]
+ (i % PACKETS_PER_PAGE) * MAX_PACKET_SIZE;
p_end = p + length;
for (p += CIP_HEADER_SIZE + MPEG2_TS_HEADER_SIZE; p < p_end;
p += MPEG2_TS_SOURCE_PACKET_SIZE)
dvb_dmx_swfilter_packets(&fdtv->demux, p, 1);
err = queue_iso(ctx, i);
if (unlikely(err))
dev_err(fdtv->device, "requeue failed\n");
i = (i + 1) & (N_PACKETS - 1);
}
fw_iso_context_queue_flush(ctx->context);
ctx->current_packet = i;
}
int fdtv_start_iso(struct firedtv *fdtv)
{
struct fdtv_ir_context *ctx;
struct fw_device *device = device_of(fdtv);
int i, err;
ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->context = fw_iso_context_create(device->card,
FW_ISO_CONTEXT_RECEIVE, fdtv->isochannel,
device->max_speed, ISO_HEADER_SIZE, handle_iso, fdtv);
if (IS_ERR(ctx->context)) {
err = PTR_ERR(ctx->context);
goto fail_free;
}
err = fw_iso_buffer_init(&ctx->buffer, device->card,
N_PAGES, DMA_FROM_DEVICE);
if (err)
goto fail_context_destroy;
ctx->interrupt_packet = 0;
ctx->current_packet = 0;
for (i = 0; i < N_PAGES; i++)
ctx->pages[i] = page_address(ctx->buffer.pages[i]);
for (i = 0; i < N_PACKETS; i++) {
err = queue_iso(ctx, i);
if (err)
goto fail;
}
err = fw_iso_context_start(ctx->context, -1, 0,
FW_ISO_CONTEXT_MATCH_ALL_TAGS);
if (err)
goto fail;
fdtv->ir_context = ctx;
return 0;
fail:
fw_iso_buffer_destroy(&ctx->buffer, device->card);
fail_context_destroy:
fw_iso_context_destroy(ctx->context);
fail_free:
kfree(ctx);
return err;
}
void fdtv_stop_iso(struct firedtv *fdtv)
{
struct fdtv_ir_context *ctx = fdtv->ir_context;
fw_iso_context_stop(ctx->context);
fw_iso_buffer_destroy(&ctx->buffer, device_of(fdtv)->card);
fw_iso_context_destroy(ctx->context);
kfree(ctx);
}
static void handle_fcp(struct fw_card *card, struct fw_request *request,
int tcode, int destination, int source, int generation,
unsigned long long offset, void *payload, size_t length,
void *callback_data)
{
struct firedtv *f, *fdtv = NULL;
struct fw_device *device;
unsigned long flags;
int su;
if (length < 2 || (((u8 *)payload)[0] & 0xf0) != 0)
return;
su = ((u8 *)payload)[1] & 0x7;
spin_lock_irqsave(&node_list_lock, flags);
list_for_each_entry(f, &node_list, list) {
device = device_of(f);
if (device->generation != generation)
continue;
smp_rmb(); /* node_id vs. generation */
if (device->card == card &&
device->node_id == source &&
(f->subunit == su || (f->subunit == 0 && su == 0x7))) {
fdtv = f;
break;
}
}
spin_unlock_irqrestore(&node_list_lock, flags);
if (fdtv)
avc_recv(fdtv, payload, length);
}
static struct fw_address_handler fcp_handler = {
.length = CSR_FCP_END - CSR_FCP_RESPONSE,
.address_callback = handle_fcp,
};
static const struct fw_address_region fcp_region = {
.start = CSR_REGISTER_BASE + CSR_FCP_RESPONSE,
.end = CSR_REGISTER_BASE + CSR_FCP_END,
};
static const char * const model_names[] = {
[FIREDTV_UNKNOWN] = "unknown type",
[FIREDTV_DVB_S] = "FireDTV S/CI",
[FIREDTV_DVB_C] = "FireDTV C/CI",
[FIREDTV_DVB_T] = "FireDTV T/CI",
[FIREDTV_DVB_S2] = "FireDTV S2 ",
};
/* Adjust the template string if models with longer names appear. */
#define MAX_MODEL_NAME_LEN sizeof("FireDTV ????")
static int node_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
{
struct firedtv *fdtv;
char name[MAX_MODEL_NAME_LEN];
int name_len, i, err;
fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
if (!fdtv)
return -ENOMEM;
dev_set_drvdata(&unit->device, fdtv);
fdtv->device = &unit->device;
fdtv->isochannel = -1;
fdtv->voltage = 0xff;
fdtv->tone = 0xff;
mutex_init(&fdtv->avc_mutex);
init_waitqueue_head(&fdtv->avc_wait);
mutex_init(&fdtv->demux_mutex);
INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
name_len = fw_csr_string(unit->directory, CSR_MODEL,
name, sizeof(name));
if (name_len < 0) {
err = name_len;
goto fail_free;
}
for (i = ARRAY_SIZE(model_names); --i; )
if (strlen(model_names[i]) <= name_len &&
strncmp(name, model_names[i], name_len) == 0)
break;
fdtv->type = i;
err = fdtv_register_rc(fdtv, &unit->device);
if (err)
goto fail_free;
spin_lock_irq(&node_list_lock);
list_add_tail(&fdtv->list, &node_list);
spin_unlock_irq(&node_list_lock);
err = avc_identify_subunit(fdtv);
if (err)
goto fail;
err = fdtv_dvb_register(fdtv, model_names[fdtv->type]);
if (err)
goto fail;
avc_register_remote_control(fdtv);
return 0;
fail:
spin_lock_irq(&node_list_lock);
list_del(&fdtv->list);
spin_unlock_irq(&node_list_lock);
fdtv_unregister_rc(fdtv);
fail_free:
kfree(fdtv);
return err;
}
static void node_remove(struct fw_unit *unit)
{
struct firedtv *fdtv = dev_get_drvdata(&unit->device);
fdtv_dvb_unregister(fdtv);
spin_lock_irq(&node_list_lock);
list_del(&fdtv->list);
spin_unlock_irq(&node_list_lock);
fdtv_unregister_rc(fdtv);
kfree(fdtv);
}
static void node_update(struct fw_unit *unit)
{
struct firedtv *fdtv = dev_get_drvdata(&unit->device);
if (fdtv->isochannel >= 0)
cmp_establish_pp_connection(fdtv, fdtv->subunit,
fdtv->isochannel);
}
#define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
#define DIGITAL_EVERYWHERE_OUI 0x001287
#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
#define AVC_SW_VERSION_ENTRY 0x010001
static const struct ieee1394_device_id fdtv_id_table[] = {
{
/* FloppyDTV S/CI and FloppyDTV S2 */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000024,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {
/* FloppyDTV T/CI */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000025,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {
/* FloppyDTV C/CI */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000026,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {
/* FireDTV S/CI and FloppyDTV S2 */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000034,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {
/* FireDTV T/CI */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000035,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {
/* FireDTV C/CI */
.match_flags = MATCH_FLAGS,
.vendor_id = DIGITAL_EVERYWHERE_OUI,
.model_id = 0x000036,
.specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
.version = AVC_SW_VERSION_ENTRY,
}, {}
};
MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
static struct fw_driver fdtv_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "firedtv",
.bus = &fw_bus_type,
},
.probe = node_probe,
.update = node_update,
.remove = node_remove,
.id_table = fdtv_id_table,
};
static int __init fdtv_init(void)
{
int ret;
ret = fw_core_add_address_handler(&fcp_handler, &fcp_region);
if (ret < 0)
return ret;
ret = driver_register(&fdtv_driver.driver);
if (ret < 0)
fw_core_remove_address_handler(&fcp_handler);
return ret;
}
static void __exit fdtv_exit(void)
{
driver_unregister(&fdtv_driver.driver);
fw_core_remove_address_handler(&fcp_handler);
}
module_init(fdtv_init);
module_exit(fdtv_exit);
MODULE_AUTHOR("Andreas Monitzer <[email protected]>");
MODULE_AUTHOR("Ben Backx <[email protected]>");
MODULE_DESCRIPTION("FireDTV DVB Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/firewire/firedtv-fw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* video stream multiplexer controlled via mux control
*
* Copyright (C) 2013 Pengutronix, Sascha Hauer <[email protected]>
* Copyright (C) 2016-2017 Pengutronix, Philipp Zabel <[email protected]>
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/mux/consumer.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <media/v4l2-async.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mc.h>
#include <media/v4l2-subdev.h>
struct video_mux {
struct v4l2_subdev subdev;
struct v4l2_async_notifier notifier;
struct media_pad *pads;
struct mux_control *mux;
struct mutex lock;
int active;
};
static const struct v4l2_mbus_framefmt video_mux_format_mbus_default = {
.width = 1,
.height = 1,
.code = MEDIA_BUS_FMT_Y8_1X8,
.field = V4L2_FIELD_NONE,
};
static inline struct video_mux *
notifier_to_video_mux(struct v4l2_async_notifier *n)
{
return container_of(n, struct video_mux, notifier);
}
static inline struct video_mux *v4l2_subdev_to_video_mux(struct v4l2_subdev *sd)
{
return container_of(sd, struct video_mux, subdev);
}
static int video_mux_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct video_mux *vmux = v4l2_subdev_to_video_mux(sd);
u16 source_pad = entity->num_pads - 1;
int ret = 0;
/*
* The mux state is determined by the enabled sink pad link.
* Enabling or disabling the source pad link has no effect.
*/
if (local->flags & MEDIA_PAD_FL_SOURCE)
return 0;
dev_dbg(sd->dev, "link setup '%s':%d->'%s':%d[%d]",
remote->entity->name, remote->index, local->entity->name,
local->index, flags & MEDIA_LNK_FL_ENABLED);
mutex_lock(&vmux->lock);
if (flags & MEDIA_LNK_FL_ENABLED) {
struct v4l2_subdev_state *sd_state;
struct v4l2_mbus_framefmt *source_mbusformat;
if (vmux->active == local->index)
goto out;
if (vmux->active >= 0) {
ret = -EBUSY;
goto out;
}
dev_dbg(sd->dev, "setting %d active\n", local->index);
ret = mux_control_try_select(vmux->mux, local->index);
if (ret < 0)
goto out;
vmux->active = local->index;
/* Propagate the active format to the source */
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state,
source_pad);
*source_mbusformat = *v4l2_subdev_get_pad_format(sd, sd_state,
vmux->active);
v4l2_subdev_unlock_state(sd_state);
} else {
if (vmux->active != local->index)
goto out;
dev_dbg(sd->dev, "going inactive\n");
mux_control_deselect(vmux->mux);
vmux->active = -1;
}
out:
mutex_unlock(&vmux->lock);
return ret;
}
static const struct media_entity_operations video_mux_ops = {
.link_setup = video_mux_link_setup,
.link_validate = v4l2_subdev_link_validate,
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
};
static int video_mux_s_stream(struct v4l2_subdev *sd, int enable)
{
struct video_mux *vmux = v4l2_subdev_to_video_mux(sd);
struct v4l2_subdev *upstream_sd;
struct media_pad *pad;
if (vmux->active == -1) {
dev_err(sd->dev, "Can not start streaming on inactive mux\n");
return -EINVAL;
}
pad = media_pad_remote_pad_first(&sd->entity.pads[vmux->active]);
if (!pad) {
dev_err(sd->dev, "Failed to find remote source pad\n");
return -ENOLINK;
}
if (!is_media_entity_v4l2_subdev(pad->entity)) {
dev_err(sd->dev, "Upstream entity is not a v4l2 subdev\n");
return -ENODEV;
}
upstream_sd = media_entity_to_v4l2_subdev(pad->entity);
return v4l2_subdev_call(upstream_sd, video, s_stream, enable);
}
static const struct v4l2_subdev_video_ops video_mux_subdev_video_ops = {
.s_stream = video_mux_s_stream,
};
static int video_mux_set_format(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *sdformat)
{
struct video_mux *vmux = v4l2_subdev_to_video_mux(sd);
struct v4l2_mbus_framefmt *mbusformat, *source_mbusformat;
struct media_pad *pad = &vmux->pads[sdformat->pad];
u16 source_pad = sd->entity.num_pads - 1;
mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
if (!mbusformat)
return -EINVAL;
source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, source_pad);
if (!source_mbusformat)
return -EINVAL;
/* No size limitations except V4L2 compliance requirements */
v4l_bound_align_image(&sdformat->format.width, 1, 65536, 0,
&sdformat->format.height, 1, 65536, 0, 0);
/* All formats except LVDS and vendor specific formats are acceptable */
switch (sdformat->format.code) {
case MEDIA_BUS_FMT_RGB444_1X12:
case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
case MEDIA_BUS_FMT_RGB565_1X16:
case MEDIA_BUS_FMT_BGR565_2X8_BE:
case MEDIA_BUS_FMT_BGR565_2X8_LE:
case MEDIA_BUS_FMT_RGB565_2X8_BE:
case MEDIA_BUS_FMT_RGB565_2X8_LE:
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RBG888_1X24:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
case MEDIA_BUS_FMT_BGR888_1X24:
case MEDIA_BUS_FMT_GBR888_1X24:
case MEDIA_BUS_FMT_RGB888_1X24:
case MEDIA_BUS_FMT_RGB888_2X12_BE:
case MEDIA_BUS_FMT_RGB888_2X12_LE:
case MEDIA_BUS_FMT_ARGB8888_1X32:
case MEDIA_BUS_FMT_RGB888_1X32_PADHI:
case MEDIA_BUS_FMT_RGB101010_1X30:
case MEDIA_BUS_FMT_RGB121212_1X36:
case MEDIA_BUS_FMT_RGB161616_1X48:
case MEDIA_BUS_FMT_Y8_1X8:
case MEDIA_BUS_FMT_UV8_1X8:
case MEDIA_BUS_FMT_UYVY8_1_5X8:
case MEDIA_BUS_FMT_VYUY8_1_5X8:
case MEDIA_BUS_FMT_YUYV8_1_5X8:
case MEDIA_BUS_FMT_YVYU8_1_5X8:
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_VYUY8_2X8:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_Y10_1X10:
case MEDIA_BUS_FMT_UYVY10_2X10:
case MEDIA_BUS_FMT_VYUY10_2X10:
case MEDIA_BUS_FMT_YUYV10_2X10:
case MEDIA_BUS_FMT_YVYU10_2X10:
case MEDIA_BUS_FMT_Y12_1X12:
case MEDIA_BUS_FMT_UYVY12_2X12:
case MEDIA_BUS_FMT_VYUY12_2X12:
case MEDIA_BUS_FMT_YUYV12_2X12:
case MEDIA_BUS_FMT_YVYU12_2X12:
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_VYUY8_1X16:
case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_YVYU8_1X16:
case MEDIA_BUS_FMT_YDYUYDYV8_1X16:
case MEDIA_BUS_FMT_UYVY10_1X20:
case MEDIA_BUS_FMT_VYUY10_1X20:
case MEDIA_BUS_FMT_YUYV10_1X20:
case MEDIA_BUS_FMT_YVYU10_1X20:
case MEDIA_BUS_FMT_VUY8_1X24:
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
case MEDIA_BUS_FMT_UYVY12_1X24:
case MEDIA_BUS_FMT_VYUY12_1X24:
case MEDIA_BUS_FMT_YUYV12_1X24:
case MEDIA_BUS_FMT_YVYU12_1X24:
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
case MEDIA_BUS_FMT_AYUV8_1X32:
case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
case MEDIA_BUS_FMT_YUV12_1X36:
case MEDIA_BUS_FMT_YUV16_1X48:
case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
case MEDIA_BUS_FMT_JPEG_1X8:
case MEDIA_BUS_FMT_AHSV8888_1X32:
case MEDIA_BUS_FMT_SBGGR8_1X8:
case MEDIA_BUS_FMT_SGBRG8_1X8:
case MEDIA_BUS_FMT_SGRBG8_1X8:
case MEDIA_BUS_FMT_SRGGB8_1X8:
case MEDIA_BUS_FMT_SBGGR10_1X10:
case MEDIA_BUS_FMT_SGBRG10_1X10:
case MEDIA_BUS_FMT_SGRBG10_1X10:
case MEDIA_BUS_FMT_SRGGB10_1X10:
case MEDIA_BUS_FMT_SBGGR12_1X12:
case MEDIA_BUS_FMT_SGBRG12_1X12:
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SRGGB12_1X12:
case MEDIA_BUS_FMT_SBGGR14_1X14:
case MEDIA_BUS_FMT_SGBRG14_1X14:
case MEDIA_BUS_FMT_SGRBG14_1X14:
case MEDIA_BUS_FMT_SRGGB14_1X14:
case MEDIA_BUS_FMT_SBGGR16_1X16:
case MEDIA_BUS_FMT_SGBRG16_1X16:
case MEDIA_BUS_FMT_SGRBG16_1X16:
case MEDIA_BUS_FMT_SRGGB16_1X16:
break;
default:
sdformat->format.code = MEDIA_BUS_FMT_Y8_1X8;
break;
}
if (sdformat->format.field == V4L2_FIELD_ANY)
sdformat->format.field = V4L2_FIELD_NONE;
mutex_lock(&vmux->lock);
/* Source pad mirrors active sink pad, no limitations on sink pads */
if ((pad->flags & MEDIA_PAD_FL_SOURCE) && vmux->active >= 0)
sdformat->format = *v4l2_subdev_get_pad_format(sd, sd_state,
vmux->active);
*mbusformat = sdformat->format;
/* Propagate the format from an active sink to source */
if ((pad->flags & MEDIA_PAD_FL_SINK) && (pad->index == vmux->active))
*source_mbusformat = sdformat->format;
mutex_unlock(&vmux->lock);
return 0;
}
static int video_mux_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
struct video_mux *vmux = v4l2_subdev_to_video_mux(sd);
struct v4l2_mbus_framefmt *mbusformat;
unsigned int i;
mutex_lock(&vmux->lock);
for (i = 0; i < sd->entity.num_pads; i++) {
mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, i);
*mbusformat = video_mux_format_mbus_default;
}
mutex_unlock(&vmux->lock);
return 0;
}
static const struct v4l2_subdev_pad_ops video_mux_pad_ops = {
.init_cfg = video_mux_init_cfg,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = video_mux_set_format,
};
static const struct v4l2_subdev_ops video_mux_subdev_ops = {
.pad = &video_mux_pad_ops,
.video = &video_mux_subdev_video_ops,
};
static int video_mux_notify_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *sd,
struct v4l2_async_connection *asd)
{
struct video_mux *vmux = notifier_to_video_mux(notifier);
return v4l2_create_fwnode_links(sd, &vmux->subdev);
}
static const struct v4l2_async_notifier_operations video_mux_notify_ops = {
.bound = video_mux_notify_bound,
};
static int video_mux_async_register(struct video_mux *vmux,
unsigned int num_input_pads)
{
unsigned int i;
int ret;
v4l2_async_subdev_nf_init(&vmux->notifier, &vmux->subdev);
for (i = 0; i < num_input_pads; i++) {
struct v4l2_async_connection *asd;
struct fwnode_handle *ep, *remote_ep;
ep = fwnode_graph_get_endpoint_by_id(
dev_fwnode(vmux->subdev.dev), i, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep)
continue;
/* Skip dangling endpoints for backwards compatibility */
remote_ep = fwnode_graph_get_remote_endpoint(ep);
if (!remote_ep) {
fwnode_handle_put(ep);
continue;
}
fwnode_handle_put(remote_ep);
asd = v4l2_async_nf_add_fwnode_remote(&vmux->notifier, ep,
struct v4l2_async_connection);
fwnode_handle_put(ep);
if (IS_ERR(asd)) {
ret = PTR_ERR(asd);
/* OK if asd already exists */
if (ret != -EEXIST)
goto err_nf_cleanup;
}
}
vmux->notifier.ops = &video_mux_notify_ops;
ret = v4l2_async_nf_register(&vmux->notifier);
if (ret)
goto err_nf_cleanup;
ret = v4l2_async_register_subdev(&vmux->subdev);
if (ret)
goto err_nf_unregister;
return 0;
err_nf_unregister:
v4l2_async_nf_unregister(&vmux->notifier);
err_nf_cleanup:
v4l2_async_nf_cleanup(&vmux->notifier);
return ret;
}
static int video_mux_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct device_node *ep;
struct video_mux *vmux;
unsigned int num_pads = 0;
unsigned int i;
int ret;
vmux = devm_kzalloc(dev, sizeof(*vmux), GFP_KERNEL);
if (!vmux)
return -ENOMEM;
platform_set_drvdata(pdev, vmux);
v4l2_subdev_init(&vmux->subdev, &video_mux_subdev_ops);
snprintf(vmux->subdev.name, sizeof(vmux->subdev.name), "%pOFn", np);
vmux->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
vmux->subdev.dev = dev;
/*
* The largest numbered port is the output port. It determines
* total number of pads.
*/
for_each_endpoint_of_node(np, ep) {
struct of_endpoint endpoint;
of_graph_parse_endpoint(ep, &endpoint);
num_pads = max(num_pads, endpoint.port + 1);
}
if (num_pads < 2) {
dev_err(dev, "Not enough ports %d\n", num_pads);
return -EINVAL;
}
vmux->mux = devm_mux_control_get(dev, NULL);
if (IS_ERR(vmux->mux)) {
ret = PTR_ERR(vmux->mux);
return dev_err_probe(dev, ret, "Failed to get mux\n");
}
mutex_init(&vmux->lock);
vmux->active = -1;
vmux->pads = devm_kcalloc(dev, num_pads, sizeof(*vmux->pads),
GFP_KERNEL);
if (!vmux->pads)
return -ENOMEM;
for (i = 0; i < num_pads; i++)
vmux->pads[i].flags = (i < num_pads - 1) ? MEDIA_PAD_FL_SINK
: MEDIA_PAD_FL_SOURCE;
vmux->subdev.entity.function = MEDIA_ENT_F_VID_MUX;
ret = media_entity_pads_init(&vmux->subdev.entity, num_pads,
vmux->pads);
if (ret < 0)
return ret;
vmux->subdev.entity.ops = &video_mux_ops;
ret = v4l2_subdev_init_finalize(&vmux->subdev);
if (ret < 0)
goto err_entity_cleanup;
ret = video_mux_async_register(vmux, num_pads - 1);
if (ret)
goto err_subdev_cleanup;
return 0;
err_subdev_cleanup:
v4l2_subdev_cleanup(&vmux->subdev);
err_entity_cleanup:
media_entity_cleanup(&vmux->subdev.entity);
return ret;
}
static void video_mux_remove(struct platform_device *pdev)
{
struct video_mux *vmux = platform_get_drvdata(pdev);
struct v4l2_subdev *sd = &vmux->subdev;
v4l2_async_nf_unregister(&vmux->notifier);
v4l2_async_nf_cleanup(&vmux->notifier);
v4l2_async_unregister_subdev(sd);
v4l2_subdev_cleanup(sd);
media_entity_cleanup(&sd->entity);
}
static const struct of_device_id video_mux_dt_ids[] = {
{ .compatible = "video-mux", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, video_mux_dt_ids);
static struct platform_driver video_mux_driver = {
.probe = video_mux_probe,
.remove_new = video_mux_remove,
.driver = {
.of_match_table = video_mux_dt_ids,
.name = "video-mux",
},
};
module_platform_driver(video_mux_driver);
MODULE_DESCRIPTION("video stream multiplexer");
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
MODULE_AUTHOR("Philipp Zabel, Pengutronix");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/platform/video-mux.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* V4L2 deinterlacing support.
*
* Copyright (c) 2012 Vista Silicon S.L.
* Javier Martin <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-dma-contig.h>
#define MEM2MEM_TEST_MODULE_NAME "mem2mem-deinterlace"
MODULE_DESCRIPTION("mem2mem device which supports deinterlacing using dmaengine");
MODULE_AUTHOR("Javier Martin <[email protected]");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.0.1");
static bool debug;
module_param(debug, bool, 0644);
/* Flags that indicate a format can be used for capture/output */
#define MEM2MEM_CAPTURE (1 << 0)
#define MEM2MEM_OUTPUT (1 << 1)
#define MEM2MEM_NAME "m2m-deinterlace"
#define dprintk(dev, fmt, arg...) \
v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
struct deinterlace_fmt {
u32 fourcc;
/* Types the format can be used for */
u32 types;
};
static struct deinterlace_fmt formats[] = {
{
.fourcc = V4L2_PIX_FMT_YUV420,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
},
{
.fourcc = V4L2_PIX_FMT_YUYV,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
},
};
#define NUM_FORMATS ARRAY_SIZE(formats)
/* Per-queue, driver-specific private data */
struct deinterlace_q_data {
unsigned int width;
unsigned int height;
unsigned int sizeimage;
struct deinterlace_fmt *fmt;
enum v4l2_field field;
};
enum {
V4L2_M2M_SRC = 0,
V4L2_M2M_DST = 1,
};
enum {
YUV420_DMA_Y_ODD,
YUV420_DMA_Y_EVEN,
YUV420_DMA_U_ODD,
YUV420_DMA_U_EVEN,
YUV420_DMA_V_ODD,
YUV420_DMA_V_EVEN,
YUV420_DMA_Y_ODD_DOUBLING,
YUV420_DMA_U_ODD_DOUBLING,
YUV420_DMA_V_ODD_DOUBLING,
YUYV_DMA_ODD,
YUYV_DMA_EVEN,
YUYV_DMA_EVEN_DOUBLING,
};
/* Source and destination queue data */
static struct deinterlace_q_data q_data[2];
static struct deinterlace_q_data *get_q_data(enum v4l2_buf_type type)
{
switch (type) {
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
return &q_data[V4L2_M2M_SRC];
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
return &q_data[V4L2_M2M_DST];
default:
BUG();
}
return NULL;
}
static struct deinterlace_fmt *find_format(struct v4l2_format *f)
{
struct deinterlace_fmt *fmt;
unsigned int k;
for (k = 0; k < NUM_FORMATS; k++) {
fmt = &formats[k];
if ((fmt->types & f->type) &&
(fmt->fourcc == f->fmt.pix.pixelformat))
break;
}
if (k == NUM_FORMATS)
return NULL;
return &formats[k];
}
struct deinterlace_dev {
struct v4l2_device v4l2_dev;
struct video_device vfd;
atomic_t busy;
struct mutex dev_mutex;
spinlock_t irqlock;
struct dma_chan *dma_chan;
struct v4l2_m2m_dev *m2m_dev;
};
struct deinterlace_ctx {
struct v4l2_fh fh;
struct deinterlace_dev *dev;
/* Abort requested by m2m */
int aborting;
enum v4l2_colorspace colorspace;
dma_cookie_t cookie;
struct dma_interleaved_template *xt;
};
/*
* mem2mem callbacks
*/
static int deinterlace_job_ready(void *priv)
{
struct deinterlace_ctx *ctx = priv;
struct deinterlace_dev *pcdev = ctx->dev;
if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0 &&
v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) > 0 &&
!atomic_read(&ctx->dev->busy)) {
dprintk(pcdev, "Task ready\n");
return 1;
}
dprintk(pcdev, "Task not ready to run\n");
return 0;
}
static void deinterlace_job_abort(void *priv)
{
struct deinterlace_ctx *ctx = priv;
struct deinterlace_dev *pcdev = ctx->dev;
ctx->aborting = 1;
dprintk(pcdev, "Aborting task\n");
v4l2_m2m_job_finish(pcdev->m2m_dev, ctx->fh.m2m_ctx);
}
static void dma_callback(void *data)
{
struct deinterlace_ctx *curr_ctx = data;
struct deinterlace_dev *pcdev = curr_ctx->dev;
struct vb2_v4l2_buffer *src_vb, *dst_vb;
atomic_set(&pcdev->busy, 0);
src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp;
dst_vb->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
dst_vb->flags |=
src_vb->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
dst_vb->timecode = src_vb->timecode;
v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
v4l2_m2m_job_finish(pcdev->m2m_dev, curr_ctx->fh.m2m_ctx);
dprintk(pcdev, "dma transfers completed.\n");
}
static void deinterlace_issue_dma(struct deinterlace_ctx *ctx, int op,
int do_callback)
{
struct deinterlace_q_data *s_q_data;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct deinterlace_dev *pcdev = ctx->dev;
struct dma_chan *chan = pcdev->dma_chan;
struct dma_device *dmadev = chan->device;
struct dma_async_tx_descriptor *tx;
unsigned int s_width, s_height;
unsigned int s_size;
dma_addr_t p_in, p_out;
enum dma_ctrl_flags flags;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
s_q_data = get_q_data(V4L2_BUF_TYPE_VIDEO_OUTPUT);
s_width = s_q_data->width;
s_height = s_q_data->height;
s_size = s_width * s_height;
p_in = (dma_addr_t)vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
p_out = (dma_addr_t)vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf,
0);
if (!p_in || !p_out) {
v4l2_err(&pcdev->v4l2_dev,
"Acquiring kernel pointers to buffers failed\n");
return;
}
switch (op) {
case YUV420_DMA_Y_ODD:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width;
ctx->xt->sgl[0].icg = s_width;
ctx->xt->src_start = p_in;
ctx->xt->dst_start = p_out;
break;
case YUV420_DMA_Y_EVEN:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width;
ctx->xt->sgl[0].icg = s_width;
ctx->xt->src_start = p_in + s_size / 2;
ctx->xt->dst_start = p_out + s_width;
break;
case YUV420_DMA_U_ODD:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + s_size;
ctx->xt->dst_start = p_out + s_size;
break;
case YUV420_DMA_U_EVEN:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + (9 * s_size) / 8;
ctx->xt->dst_start = p_out + s_size + s_width / 2;
break;
case YUV420_DMA_V_ODD:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + (5 * s_size) / 4;
ctx->xt->dst_start = p_out + (5 * s_size) / 4;
break;
case YUV420_DMA_V_EVEN:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + (11 * s_size) / 8;
ctx->xt->dst_start = p_out + (5 * s_size) / 4 + s_width / 2;
break;
case YUV420_DMA_Y_ODD_DOUBLING:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width;
ctx->xt->sgl[0].icg = s_width;
ctx->xt->src_start = p_in;
ctx->xt->dst_start = p_out + s_width;
break;
case YUV420_DMA_U_ODD_DOUBLING:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + s_size;
ctx->xt->dst_start = p_out + s_size + s_width / 2;
break;
case YUV420_DMA_V_ODD_DOUBLING:
ctx->xt->numf = s_height / 4;
ctx->xt->sgl[0].size = s_width / 2;
ctx->xt->sgl[0].icg = s_width / 2;
ctx->xt->src_start = p_in + (5 * s_size) / 4;
ctx->xt->dst_start = p_out + (5 * s_size) / 4 + s_width / 2;
break;
case YUYV_DMA_ODD:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width * 2;
ctx->xt->sgl[0].icg = s_width * 2;
ctx->xt->src_start = p_in;
ctx->xt->dst_start = p_out;
break;
case YUYV_DMA_EVEN:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width * 2;
ctx->xt->sgl[0].icg = s_width * 2;
ctx->xt->src_start = p_in + s_size;
ctx->xt->dst_start = p_out + s_width * 2;
break;
case YUYV_DMA_EVEN_DOUBLING:
default:
ctx->xt->numf = s_height / 2;
ctx->xt->sgl[0].size = s_width * 2;
ctx->xt->sgl[0].icg = s_width * 2;
ctx->xt->src_start = p_in;
ctx->xt->dst_start = p_out + s_width * 2;
break;
}
/* Common parameters for al transfers */
ctx->xt->frame_size = 1;
ctx->xt->dir = DMA_MEM_TO_MEM;
ctx->xt->src_sgl = false;
ctx->xt->dst_sgl = true;
flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
tx = dmadev->device_prep_interleaved_dma(chan, ctx->xt, flags);
if (tx == NULL) {
v4l2_warn(&pcdev->v4l2_dev, "DMA interleaved prep error\n");
return;
}
if (do_callback) {
tx->callback = dma_callback;
tx->callback_param = ctx;
}
ctx->cookie = dmaengine_submit(tx);
if (dma_submit_error(ctx->cookie)) {
v4l2_warn(&pcdev->v4l2_dev,
"DMA submit error %d with src=0x%x dst=0x%x len=0x%x\n",
ctx->cookie, (unsigned)p_in, (unsigned)p_out,
s_size * 3/2);
return;
}
dma_async_issue_pending(chan);
}
static void deinterlace_device_run(void *priv)
{
struct deinterlace_ctx *ctx = priv;
struct deinterlace_q_data *dst_q_data;
atomic_set(&ctx->dev->busy, 1);
dprintk(ctx->dev, "%s: DMA try issue.\n", __func__);
dst_q_data = get_q_data(V4L2_BUF_TYPE_VIDEO_CAPTURE);
/*
* 4 possible field conversions are possible at the moment:
* V4L2_FIELD_SEQ_TB --> V4L2_FIELD_INTERLACED_TB:
* two separate fields in the same input buffer are interlaced
* in the output buffer using weaving. Top field comes first.
* V4L2_FIELD_SEQ_TB --> V4L2_FIELD_NONE:
* top field from the input buffer is copied to the output buffer
* using line doubling. Bottom field from the input buffer is discarded.
* V4L2_FIELD_SEQ_BT --> V4L2_FIELD_INTERLACED_BT:
* two separate fields in the same input buffer are interlaced
* in the output buffer using weaving. Bottom field comes first.
* V4L2_FIELD_SEQ_BT --> V4L2_FIELD_NONE:
* bottom field from the input buffer is copied to the output buffer
* using line doubling. Top field from the input buffer is discarded.
*/
switch (dst_q_data->fmt->fourcc) {
case V4L2_PIX_FMT_YUV420:
switch (dst_q_data->field) {
case V4L2_FIELD_INTERLACED_TB:
case V4L2_FIELD_INTERLACED_BT:
dprintk(ctx->dev, "%s: yuv420 interlaced tb.\n",
__func__);
deinterlace_issue_dma(ctx, YUV420_DMA_Y_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_Y_EVEN, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_U_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_U_EVEN, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_V_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_V_EVEN, 1);
break;
case V4L2_FIELD_NONE:
default:
dprintk(ctx->dev, "%s: yuv420 interlaced line doubling.\n",
__func__);
deinterlace_issue_dma(ctx, YUV420_DMA_Y_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_Y_ODD_DOUBLING, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_U_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_U_ODD_DOUBLING, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_V_ODD, 0);
deinterlace_issue_dma(ctx, YUV420_DMA_V_ODD_DOUBLING, 1);
break;
}
break;
case V4L2_PIX_FMT_YUYV:
default:
switch (dst_q_data->field) {
case V4L2_FIELD_INTERLACED_TB:
case V4L2_FIELD_INTERLACED_BT:
dprintk(ctx->dev, "%s: yuyv interlaced_tb.\n",
__func__);
deinterlace_issue_dma(ctx, YUYV_DMA_ODD, 0);
deinterlace_issue_dma(ctx, YUYV_DMA_EVEN, 1);
break;
case V4L2_FIELD_NONE:
default:
dprintk(ctx->dev, "%s: yuyv interlaced line doubling.\n",
__func__);
deinterlace_issue_dma(ctx, YUYV_DMA_ODD, 0);
deinterlace_issue_dma(ctx, YUYV_DMA_EVEN_DOUBLING, 1);
break;
}
break;
}
dprintk(ctx->dev, "%s: DMA issue done.\n", __func__);
}
/*
* video ioctls
*/
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
strscpy(cap->bus_info, MEM2MEM_NAME, sizeof(cap->bus_info));
return 0;
}
static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
{
int i, num;
struct deinterlace_fmt *fmt;
num = 0;
for (i = 0; i < NUM_FORMATS; ++i) {
if (formats[i].types & type) {
/* index-th format of type type found ? */
if (num == f->index)
break;
/* Correct type but haven't reached our index yet,
* just increment per-type index */
++num;
}
}
if (i < NUM_FORMATS) {
/* Format found */
fmt = &formats[i];
f->pixelformat = fmt->fourcc;
return 0;
}
/* Format not found */
return -EINVAL;
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return enum_fmt(f, MEM2MEM_CAPTURE);
}
static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return enum_fmt(f, MEM2MEM_OUTPUT);
}
static int vidioc_g_fmt(struct deinterlace_ctx *ctx, struct v4l2_format *f)
{
struct vb2_queue *vq;
struct deinterlace_q_data *q_data;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(f->type);
f->fmt.pix.width = q_data->width;
f->fmt.pix.height = q_data->height;
f->fmt.pix.field = q_data->field;
f->fmt.pix.pixelformat = q_data->fmt->fourcc;
switch (q_data->fmt->fourcc) {
case V4L2_PIX_FMT_YUV420:
f->fmt.pix.bytesperline = q_data->width * 3 / 2;
break;
case V4L2_PIX_FMT_YUYV:
default:
f->fmt.pix.bytesperline = q_data->width * 2;
}
f->fmt.pix.sizeimage = q_data->sizeimage;
f->fmt.pix.colorspace = ctx->colorspace;
return 0;
}
static int vidioc_g_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
return vidioc_g_fmt(priv, f);
}
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
return vidioc_g_fmt(priv, f);
}
static int vidioc_try_fmt(struct v4l2_format *f, struct deinterlace_fmt *fmt)
{
switch (f->fmt.pix.pixelformat) {
case V4L2_PIX_FMT_YUV420:
f->fmt.pix.bytesperline = f->fmt.pix.width * 3 / 2;
break;
case V4L2_PIX_FMT_YUYV:
default:
f->fmt.pix.bytesperline = f->fmt.pix.width * 2;
}
f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct deinterlace_fmt *fmt;
struct deinterlace_ctx *ctx = priv;
fmt = find_format(f);
if (!fmt || !(fmt->types & MEM2MEM_CAPTURE))
f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
f->fmt.pix.colorspace = ctx->colorspace;
if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
f->fmt.pix.field != V4L2_FIELD_NONE)
f->fmt.pix.field = V4L2_FIELD_INTERLACED_TB;
return vidioc_try_fmt(f, fmt);
}
static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct deinterlace_fmt *fmt;
fmt = find_format(f);
if (!fmt || !(fmt->types & MEM2MEM_OUTPUT))
f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
if (!f->fmt.pix.colorspace)
f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
if (f->fmt.pix.field != V4L2_FIELD_SEQ_TB &&
f->fmt.pix.field != V4L2_FIELD_SEQ_BT)
f->fmt.pix.field = V4L2_FIELD_SEQ_TB;
return vidioc_try_fmt(f, fmt);
}
static int vidioc_s_fmt(struct deinterlace_ctx *ctx, struct v4l2_format *f)
{
struct deinterlace_q_data *q_data;
struct vb2_queue *vq;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(f->type);
if (!q_data)
return -EINVAL;
if (vb2_is_busy(vq)) {
v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
return -EBUSY;
}
q_data->fmt = find_format(f);
if (!q_data->fmt) {
v4l2_err(&ctx->dev->v4l2_dev,
"Couldn't set format type %d, wxh: %dx%d. fmt: %d, field: %d\n",
f->type, f->fmt.pix.width, f->fmt.pix.height,
f->fmt.pix.pixelformat, f->fmt.pix.field);
return -EINVAL;
}
q_data->width = f->fmt.pix.width;
q_data->height = f->fmt.pix.height;
q_data->field = f->fmt.pix.field;
switch (f->fmt.pix.pixelformat) {
case V4L2_PIX_FMT_YUV420:
f->fmt.pix.bytesperline = f->fmt.pix.width * 3 / 2;
q_data->sizeimage = (q_data->width * q_data->height * 3) / 2;
break;
case V4L2_PIX_FMT_YUYV:
default:
f->fmt.pix.bytesperline = f->fmt.pix.width * 2;
q_data->sizeimage = q_data->width * q_data->height * 2;
}
dprintk(ctx->dev,
"Setting format for type %d, wxh: %dx%d, fmt: %d, field: %d\n",
f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
q_data->field);
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
int ret;
ret = vidioc_try_fmt_vid_cap(file, priv, f);
if (ret)
return ret;
return vidioc_s_fmt(priv, f);
}
static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct deinterlace_ctx *ctx = priv;
int ret;
ret = vidioc_try_fmt_vid_out(file, priv, f);
if (ret)
return ret;
ret = vidioc_s_fmt(priv, f);
if (!ret)
ctx->colorspace = f->fmt.pix.colorspace;
return ret;
}
static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
struct deinterlace_q_data *s_q_data, *d_q_data;
struct deinterlace_ctx *ctx = priv;
s_q_data = get_q_data(V4L2_BUF_TYPE_VIDEO_OUTPUT);
d_q_data = get_q_data(V4L2_BUF_TYPE_VIDEO_CAPTURE);
/* Check that src and dst queues have the same pix format */
if (s_q_data->fmt->fourcc != d_q_data->fmt->fourcc) {
v4l2_err(&ctx->dev->v4l2_dev,
"src and dst formats don't match.\n");
return -EINVAL;
}
/* Check that input and output deinterlacing types are compatible */
switch (s_q_data->field) {
case V4L2_FIELD_SEQ_BT:
if (d_q_data->field != V4L2_FIELD_NONE &&
d_q_data->field != V4L2_FIELD_INTERLACED_BT) {
v4l2_err(&ctx->dev->v4l2_dev,
"src and dst field conversion [(%d)->(%d)] not supported.\n",
s_q_data->field, d_q_data->field);
return -EINVAL;
}
break;
case V4L2_FIELD_SEQ_TB:
if (d_q_data->field != V4L2_FIELD_NONE &&
d_q_data->field != V4L2_FIELD_INTERLACED_TB) {
v4l2_err(&ctx->dev->v4l2_dev,
"src and dst field conversion [(%d)->(%d)] not supported.\n",
s_q_data->field, d_q_data->field);
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
}
static const struct v4l2_ioctl_ops deinterlace_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
.vidioc_g_fmt_vid_out = vidioc_g_fmt_vid_out,
.vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
.vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_streamon = vidioc_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
};
/*
* Queue operations
*/
struct vb2_dc_conf {
struct device *dev;
};
static int deinterlace_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
struct deinterlace_q_data *q_data;
unsigned int size, count = *nbuffers;
q_data = get_q_data(vq->type);
switch (q_data->fmt->fourcc) {
case V4L2_PIX_FMT_YUV420:
size = q_data->width * q_data->height * 3 / 2;
break;
case V4L2_PIX_FMT_YUYV:
default:
size = q_data->width * q_data->height * 2;
}
*nplanes = 1;
*nbuffers = count;
sizes[0] = size;
dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
return 0;
}
static int deinterlace_buf_prepare(struct vb2_buffer *vb)
{
struct deinterlace_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct deinterlace_q_data *q_data;
dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
q_data = get_q_data(vb->vb2_queue->type);
if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
dprintk(ctx->dev, "%s data will not fit into plane (%lu < %lu)\n",
__func__, vb2_plane_size(vb, 0), (long)q_data->sizeimage);
return -EINVAL;
}
vb2_set_plane_payload(vb, 0, q_data->sizeimage);
return 0;
}
static void deinterlace_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct deinterlace_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static const struct vb2_ops deinterlace_qops = {
.queue_setup = deinterlace_queue_setup,
.buf_prepare = deinterlace_buf_prepare,
.buf_queue = deinterlace_buf_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct deinterlace_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->ops = &deinterlace_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->dev = ctx->dev->v4l2_dev.dev;
src_vq->lock = &ctx->dev->dev_mutex;
q_data[V4L2_M2M_SRC].fmt = &formats[0];
q_data[V4L2_M2M_SRC].width = 640;
q_data[V4L2_M2M_SRC].height = 480;
q_data[V4L2_M2M_SRC].sizeimage = (640 * 480 * 3) / 2;
q_data[V4L2_M2M_SRC].field = V4L2_FIELD_SEQ_TB;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->ops = &deinterlace_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->dev = ctx->dev->v4l2_dev.dev;
dst_vq->lock = &ctx->dev->dev_mutex;
q_data[V4L2_M2M_DST].fmt = &formats[0];
q_data[V4L2_M2M_DST].width = 640;
q_data[V4L2_M2M_DST].height = 480;
q_data[V4L2_M2M_DST].sizeimage = (640 * 480 * 3) / 2;
q_data[V4L2_M2M_SRC].field = V4L2_FIELD_INTERLACED_TB;
return vb2_queue_init(dst_vq);
}
/*
* File operations
*/
static int deinterlace_open(struct file *file)
{
struct deinterlace_dev *pcdev = video_drvdata(file);
struct deinterlace_ctx *ctx = NULL;
ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
if (!ctx)
return -ENOMEM;
v4l2_fh_init(&ctx->fh, video_devdata(file));
file->private_data = &ctx->fh;
ctx->dev = pcdev;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(pcdev->m2m_dev, ctx, &queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
int ret = PTR_ERR(ctx->fh.m2m_ctx);
kfree(ctx);
return ret;
}
ctx->xt = kzalloc(sizeof(struct dma_interleaved_template) +
sizeof(struct data_chunk), GFP_KERNEL);
if (!ctx->xt) {
kfree(ctx);
return -ENOMEM;
}
ctx->colorspace = V4L2_COLORSPACE_REC709;
v4l2_fh_add(&ctx->fh);
dprintk(pcdev, "Created instance %p, m2m_ctx: %p\n",
ctx, ctx->fh.m2m_ctx);
return 0;
}
static int deinterlace_release(struct file *file)
{
struct deinterlace_dev *pcdev = video_drvdata(file);
struct deinterlace_ctx *ctx = file->private_data;
dprintk(pcdev, "Releasing instance %p\n", ctx);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
kfree(ctx->xt);
kfree(ctx);
return 0;
}
static const struct v4l2_file_operations deinterlace_fops = {
.owner = THIS_MODULE,
.open = deinterlace_open,
.release = deinterlace_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct video_device deinterlace_videodev = {
.name = MEM2MEM_NAME,
.fops = &deinterlace_fops,
.ioctl_ops = &deinterlace_ioctl_ops,
.minor = -1,
.release = video_device_release_empty,
.vfl_dir = VFL_DIR_M2M,
.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
};
static const struct v4l2_m2m_ops m2m_ops = {
.device_run = deinterlace_device_run,
.job_ready = deinterlace_job_ready,
.job_abort = deinterlace_job_abort,
};
static int deinterlace_probe(struct platform_device *pdev)
{
struct deinterlace_dev *pcdev;
struct video_device *vfd;
dma_cap_mask_t mask;
int ret = 0;
pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
if (!pcdev)
return -ENOMEM;
spin_lock_init(&pcdev->irqlock);
dma_cap_zero(mask);
dma_cap_set(DMA_INTERLEAVE, mask);
pcdev->dma_chan = dma_request_channel(mask, NULL, pcdev);
if (!pcdev->dma_chan)
return -ENODEV;
if (!dma_has_cap(DMA_INTERLEAVE, pcdev->dma_chan->device->cap_mask)) {
dev_err(&pdev->dev, "DMA does not support INTERLEAVE\n");
ret = -ENODEV;
goto rel_dma;
}
ret = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
if (ret)
goto rel_dma;
atomic_set(&pcdev->busy, 0);
mutex_init(&pcdev->dev_mutex);
vfd = &pcdev->vfd;
*vfd = deinterlace_videodev;
vfd->lock = &pcdev->dev_mutex;
vfd->v4l2_dev = &pcdev->v4l2_dev;
ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
if (ret) {
v4l2_err(&pcdev->v4l2_dev, "Failed to register video device\n");
goto unreg_dev;
}
video_set_drvdata(vfd, pcdev);
v4l2_info(&pcdev->v4l2_dev, MEM2MEM_TEST_MODULE_NAME
" Device registered as /dev/video%d\n", vfd->num);
platform_set_drvdata(pdev, pcdev);
pcdev->m2m_dev = v4l2_m2m_init(&m2m_ops);
if (IS_ERR(pcdev->m2m_dev)) {
v4l2_err(&pcdev->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(pcdev->m2m_dev);
goto err_m2m;
}
return 0;
err_m2m:
video_unregister_device(&pcdev->vfd);
unreg_dev:
v4l2_device_unregister(&pcdev->v4l2_dev);
rel_dma:
dma_release_channel(pcdev->dma_chan);
return ret;
}
static void deinterlace_remove(struct platform_device *pdev)
{
struct deinterlace_dev *pcdev = platform_get_drvdata(pdev);
v4l2_info(&pcdev->v4l2_dev, "Removing " MEM2MEM_TEST_MODULE_NAME);
v4l2_m2m_release(pcdev->m2m_dev);
video_unregister_device(&pcdev->vfd);
v4l2_device_unregister(&pcdev->v4l2_dev);
dma_release_channel(pcdev->dma_chan);
}
static struct platform_driver deinterlace_pdrv = {
.probe = deinterlace_probe,
.remove_new = deinterlace_remove,
.driver = {
.name = MEM2MEM_NAME,
},
};
module_platform_driver(deinterlace_pdrv);
| linux-master | drivers/media/platform/m2m-deinterlace.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* V4L2 Driver for PXA camera host
*
* Copyright (C) 2006, Sascha Hauer, Pengutronix
* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
* Copyright (C) 2016, Robert Jarzmik <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/time.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/dma/pxa-dma.h>
#include <media/v4l2-async.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-fwnode.h>
#include <media/videobuf2-dma-sg.h>
#include <linux/videodev2.h>
#include <linux/platform_data/media/camera-pxa.h>
#define PXA_CAM_VERSION "0.0.6"
#define PXA_CAM_DRV_NAME "pxa27x-camera"
#define DEFAULT_WIDTH 640
#define DEFAULT_HEIGHT 480
/* Camera Interface */
#define CICR0 0x0000
#define CICR1 0x0004
#define CICR2 0x0008
#define CICR3 0x000C
#define CICR4 0x0010
#define CISR 0x0014
#define CIFR 0x0018
#define CITOR 0x001C
#define CIBR0 0x0028
#define CIBR1 0x0030
#define CIBR2 0x0038
#define CICR0_DMAEN (1UL << 31) /* DMA request enable */
#define CICR0_PAR_EN (1 << 30) /* Parity enable */
#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
#define CICR0_ENB (1 << 28) /* Camera interface enable */
#define CICR0_DIS (1 << 27) /* Camera interface disable */
#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
#define CICR0_TOM (1 << 9) /* Time-out mask */
#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
#define CICR0_EOLM (1 << 6) /* End-of-line mask */
#define CICR0_PERRM (1 << 5) /* Parity-error mask */
#define CICR0_QDM (1 << 4) /* Quick-disable mask */
#define CICR0_CDM (1 << 3) /* Disable-done mask */
#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
#define CICR1_TBIT (1UL << 31) /* Transparency bit */
#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
#define CICR1_RGB_F (1 << 11) /* RGB format */
#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
#define CICR1_DW (0x7 << 0) /* Data width mask */
#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
wait count mask */
#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
wait count mask */
#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
wait count mask */
#define CICR2_FSW (0x7 << 0) /* Frame stabilization
wait count mask */
#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
wait count mask */
#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
wait count mask */
#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
wait count mask */
#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
#define CISR_FTO (1 << 15) /* FIFO time-out */
#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
#define CISR_EOL (1 << 8) /* End of line */
#define CISR_PAR_ERR (1 << 7) /* Parity error */
#define CISR_CQD (1 << 6) /* Camera interface quick disable */
#define CISR_CDD (1 << 5) /* Camera interface disable done */
#define CISR_SOF (1 << 4) /* Start of frame */
#define CISR_EOF (1 << 3) /* End of frame */
#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
#define CICR0_SIM_MP (0 << 24)
#define CICR0_SIM_SP (1 << 24)
#define CICR0_SIM_MS (2 << 24)
#define CICR0_SIM_EP (3 << 24)
#define CICR0_SIM_ES (4 << 24)
#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
CICR0_EOFM | CICR0_FOM)
#define sensor_call(cam, o, f, args...) \
v4l2_subdev_call(cam->sensor, o, f, ##args)
/*
* Format handling
*/
/**
* enum pxa_mbus_packing - data packing types on the media-bus
* @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
* sample represents one pixel
* @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
* possibly incomplete byte high bits are padding
* @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
* to 16 bits
*/
enum pxa_mbus_packing {
PXA_MBUS_PACKING_NONE,
PXA_MBUS_PACKING_2X8_PADHI,
PXA_MBUS_PACKING_EXTEND16,
};
/**
* enum pxa_mbus_order - sample order on the media bus
* @PXA_MBUS_ORDER_LE: least significant sample first
* @PXA_MBUS_ORDER_BE: most significant sample first
*/
enum pxa_mbus_order {
PXA_MBUS_ORDER_LE,
PXA_MBUS_ORDER_BE,
};
/**
* enum pxa_mbus_layout - planes layout in memory
* @PXA_MBUS_LAYOUT_PACKED: color components packed
* @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
* @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
* chroma plane (C plane is half the size
* of Y plane)
* @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
* chroma plane (C plane is the same size
* as Y plane)
*/
enum pxa_mbus_layout {
PXA_MBUS_LAYOUT_PACKED = 0,
PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
PXA_MBUS_LAYOUT_PLANAR_2Y_C,
PXA_MBUS_LAYOUT_PLANAR_Y_C,
};
/**
* struct pxa_mbus_pixelfmt - Data format on the media bus
* @name: Name of the format
* @fourcc: Fourcc code, that will be obtained if the data is
* stored in memory in the following way:
* @packing: Type of sample-packing, that has to be used
* @order: Sample order when storing in memory
* @layout: Planes layout in memory
* @bits_per_sample: How many bits the bridge has to sample
*/
struct pxa_mbus_pixelfmt {
const char *name;
u32 fourcc;
enum pxa_mbus_packing packing;
enum pxa_mbus_order order;
enum pxa_mbus_layout layout;
u8 bits_per_sample;
};
/**
* struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
* @code: mediabus pixel-code
* @fmt: pixel format description
*/
struct pxa_mbus_lookup {
u32 code;
struct pxa_mbus_pixelfmt fmt;
};
static const struct pxa_mbus_lookup mbus_fmt[] = {
{
.code = MEDIA_BUS_FMT_YUYV8_2X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_YUYV,
.name = "YUYV",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_YVYU8_2X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_YVYU,
.name = "YVYU",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_UYVY8_2X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_UYVY,
.name = "UYVY",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_VYUY8_2X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_VYUY,
.name = "VYUY",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
.fmt = {
.fourcc = V4L2_PIX_FMT_RGB555,
.name = "RGB555",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
.fmt = {
.fourcc = V4L2_PIX_FMT_RGB555X,
.name = "RGB555X",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_BE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_RGB565_2X8_LE,
.fmt = {
.fourcc = V4L2_PIX_FMT_RGB565,
.name = "RGB565",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_RGB565_2X8_BE,
.fmt = {
.fourcc = V4L2_PIX_FMT_RGB565X,
.name = "RGB565X",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_BE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR8,
.name = "Bayer 8 BGGR",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGBRG8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGBRG8,
.name = "Bayer 8 GBRG",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGRBG8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGRBG8,
.name = "Bayer 8 GRBG",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SRGGB8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_SRGGB8,
.name = "Bayer 8 RGGB",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SBGGR10_1X10,
.fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 10,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_Y8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_GREY,
.name = "Grey",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_Y10_1X10,
.fmt = {
.fourcc = V4L2_PIX_FMT_Y10,
.name = "Grey 10bit",
.bits_per_sample = 10,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
.fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
.fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_BE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
.fmt = {
.fourcc = V4L2_PIX_FMT_RGB444,
.name = "RGB444",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_BE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_UYVY8_1X16,
.fmt = {
.fourcc = V4L2_PIX_FMT_UYVY,
.name = "UYVY 16bit",
.bits_per_sample = 16,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_VYUY8_1X16,
.fmt = {
.fourcc = V4L2_PIX_FMT_VYUY,
.name = "VYUY 16bit",
.bits_per_sample = 16,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_YUYV8_1X16,
.fmt = {
.fourcc = V4L2_PIX_FMT_YUYV,
.name = "YUYV 16bit",
.bits_per_sample = 16,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_YVYU8_1X16,
.fmt = {
.fourcc = V4L2_PIX_FMT_YVYU,
.name = "YVYU 16bit",
.bits_per_sample = 16,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
.name = "Bayer 10 BGGR DPCM 8",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_NONE,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGBRG10_1X10,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGBRG10,
.name = "Bayer 10 GBRG",
.bits_per_sample = 10,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGRBG10_1X10,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGRBG10,
.name = "Bayer 10 GRBG",
.bits_per_sample = 10,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
.fmt = {
.fourcc = V4L2_PIX_FMT_SRGGB10,
.name = "Bayer 10 RGGB",
.bits_per_sample = 10,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SBGGR12_1X12,
.fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR12,
.name = "Bayer 12 BGGR",
.bits_per_sample = 12,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGBRG12_1X12,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGBRG12,
.name = "Bayer 12 GBRG",
.bits_per_sample = 12,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SGRBG12_1X12,
.fmt = {
.fourcc = V4L2_PIX_FMT_SGRBG12,
.name = "Bayer 12 GRBG",
.bits_per_sample = 12,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
}, {
.code = MEDIA_BUS_FMT_SRGGB12_1X12,
.fmt = {
.fourcc = V4L2_PIX_FMT_SRGGB12,
.name = "Bayer 12 RGGB",
.bits_per_sample = 12,
.packing = PXA_MBUS_PACKING_EXTEND16,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PACKED,
},
},
};
static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
{
if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
return width * mf->bits_per_sample / 8;
switch (mf->packing) {
case PXA_MBUS_PACKING_NONE:
return width * mf->bits_per_sample / 8;
case PXA_MBUS_PACKING_2X8_PADHI:
case PXA_MBUS_PACKING_EXTEND16:
return width * 2;
}
return -EINVAL;
}
static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
u32 bytes_per_line, u32 height)
{
if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
return bytes_per_line * height;
switch (mf->packing) {
case PXA_MBUS_PACKING_2X8_PADHI:
return bytes_per_line * height * 2;
default:
return -EINVAL;
}
}
static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
u32 code,
const struct pxa_mbus_lookup *lookup,
int n)
{
int i;
for (i = 0; i < n; i++)
if (lookup[i].code == code)
return &lookup[i].fmt;
return NULL;
}
static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
u32 code)
{
return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
}
/**
* struct pxa_camera_format_xlate - match between host and sensor formats
* @code: code of a sensor provided format
* @host_fmt: host format after host translation from code
*
* Host and sensor translation structure. Used in table of host and sensor
* formats matchings in pxa_camera_device. A host can override the generic list
* generation by implementing get_formats(), and use it for format checks and
* format setup.
*/
struct pxa_camera_format_xlate {
u32 code;
const struct pxa_mbus_pixelfmt *host_fmt;
};
/*
* Structures
*/
enum pxa_camera_active_dma {
DMA_Y = 0x1,
DMA_U = 0x2,
DMA_V = 0x4,
};
/* buffer for one video frame */
struct pxa_buffer {
/* common v4l buffer stuff -- must be first */
struct vb2_v4l2_buffer vbuf;
struct list_head queue;
u32 code;
int nb_planes;
/* our descriptor lists for Y, U and V channels */
struct dma_async_tx_descriptor *descs[3];
dma_cookie_t cookie[3];
struct scatterlist *sg[3];
int sg_len[3];
size_t plane_sizes[3];
int inwork;
enum pxa_camera_active_dma active_dma;
};
struct pxa_camera_dev {
struct v4l2_device v4l2_dev;
struct video_device vdev;
struct v4l2_async_notifier notifier;
struct vb2_queue vb2_vq;
struct v4l2_subdev *sensor;
struct pxa_camera_format_xlate *user_formats;
const struct pxa_camera_format_xlate *current_fmt;
struct v4l2_pix_format current_pix;
/*
* PXA27x is only supposed to handle one camera on its Quick Capture
* interface. If anyone ever builds hardware to enable more than
* one camera, they will have to modify this driver too
*/
struct clk *clk;
unsigned int irq;
void __iomem *base;
int channels;
struct dma_chan *dma_chans[3];
struct pxacamera_platform_data *pdata;
struct resource *res;
unsigned long platform_flags;
unsigned long ciclk;
unsigned long mclk;
u32 mclk_divisor;
u16 width_flags; /* max 10 bits */
struct list_head capture;
spinlock_t lock;
struct mutex mlock;
unsigned int buf_sequence;
struct pxa_buffer *active;
struct tasklet_struct task_eof;
u32 save_cicr[5];
};
struct pxa_cam {
unsigned long flags;
};
static const char *pxa_cam_driver_description = "PXA_Camera";
/*
* Format translation functions
*/
static const struct pxa_camera_format_xlate
*pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
unsigned int fourcc)
{
unsigned int i;
for (i = 0; user_formats[i].code; i++)
if (user_formats[i].host_fmt->fourcc == fourcc)
return user_formats + i;
return NULL;
}
static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
int (*get_formats)(struct v4l2_device *, unsigned int,
struct pxa_camera_format_xlate *xlate))
{
unsigned int i, fmts = 0, raw_fmts = 0;
int ret;
struct v4l2_subdev_mbus_code_enum code = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct pxa_camera_format_xlate *user_formats;
while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
raw_fmts++;
code.index++;
}
/*
* First pass - only count formats this host-sensor
* configuration can provide
*/
for (i = 0; i < raw_fmts; i++) {
ret = get_formats(v4l2_dev, i, NULL);
if (ret < 0)
return ERR_PTR(ret);
fmts += ret;
}
if (!fmts)
return ERR_PTR(-ENXIO);
user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
if (!user_formats)
return ERR_PTR(-ENOMEM);
/* Second pass - actually fill data formats */
fmts = 0;
for (i = 0; i < raw_fmts; i++) {
ret = get_formats(v4l2_dev, i, user_formats + fmts);
if (ret < 0)
goto egfmt;
fmts += ret;
}
user_formats[fmts].code = 0;
return user_formats;
egfmt:
kfree(user_formats);
return ERR_PTR(ret);
}
/*
* Videobuf operations
*/
static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
return container_of(vbuf, struct pxa_buffer, vbuf);
}
static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
{
return pcdev->v4l2_dev.dev;
}
static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
{
return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
}
static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
enum pxa_camera_active_dma act_dma);
static void pxa_camera_dma_irq_y(void *data)
{
struct pxa_camera_dev *pcdev = data;
pxa_camera_dma_irq(pcdev, DMA_Y);
}
static void pxa_camera_dma_irq_u(void *data)
{
struct pxa_camera_dev *pcdev = data;
pxa_camera_dma_irq(pcdev, DMA_U);
}
static void pxa_camera_dma_irq_v(void *data)
{
struct pxa_camera_dev *pcdev = data;
pxa_camera_dma_irq(pcdev, DMA_V);
}
/**
* pxa_init_dma_channel - init dma descriptors
* @pcdev: pxa camera device
* @buf: pxa camera buffer
* @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
* @sg: dma scatter list
* @sglen: dma scatter list length
*
* Prepares the pxa dma descriptors to transfer one camera channel.
*
* Returns 0 if success or -ENOMEM if no memory is available
*/
static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
struct pxa_buffer *buf, int channel,
struct scatterlist *sg, int sglen)
{
struct dma_chan *dma_chan = pcdev->dma_chans[channel];
struct dma_async_tx_descriptor *tx;
tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
if (!tx) {
dev_err(pcdev_to_dev(pcdev),
"dmaengine_prep_slave_sg failed\n");
goto fail;
}
tx->callback_param = pcdev;
switch (channel) {
case 0:
tx->callback = pxa_camera_dma_irq_y;
break;
case 1:
tx->callback = pxa_camera_dma_irq_u;
break;
case 2:
tx->callback = pxa_camera_dma_irq_v;
break;
}
buf->descs[channel] = tx;
return 0;
fail:
dev_dbg(pcdev_to_dev(pcdev),
"%s (vb=%p) dma_tx=%p\n",
__func__, buf, tx);
return -ENOMEM;
}
static void pxa_video_buf_set_actdma(struct pxa_camera_dev *pcdev,
struct pxa_buffer *buf)
{
buf->active_dma = DMA_Y;
if (buf->nb_planes == 3)
buf->active_dma |= DMA_U | DMA_V;
}
/**
* pxa_dma_start_channels - start DMA channel for active buffer
* @pcdev: pxa camera device
*
* Initialize DMA channels to the beginning of the active video buffer, and
* start these channels.
*/
static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
{
int i;
for (i = 0; i < pcdev->channels; i++) {
dev_dbg(pcdev_to_dev(pcdev),
"%s (channel=%d)\n", __func__, i);
dma_async_issue_pending(pcdev->dma_chans[i]);
}
}
static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
{
int i;
for (i = 0; i < pcdev->channels; i++) {
dev_dbg(pcdev_to_dev(pcdev),
"%s (channel=%d)\n", __func__, i);
dmaengine_terminate_all(pcdev->dma_chans[i]);
}
}
static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
struct pxa_buffer *buf)
{
int i;
for (i = 0; i < pcdev->channels; i++) {
buf->cookie[i] = dmaengine_submit(buf->descs[i]);
dev_dbg(pcdev_to_dev(pcdev),
"%s (channel=%d) : submit vb=%p cookie=%d\n",
__func__, i, buf, buf->descs[i]->cookie);
}
}
/**
* pxa_camera_start_capture - start video capturing
* @pcdev: camera device
*
* Launch capturing. DMA channels should not be active yet. They should get
* activated at the end of frame interrupt, to capture only whole frames, and
* never begin the capture of a partial frame.
*/
static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
{
unsigned long cicr0;
dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
__raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
/* Enable End-Of-Frame Interrupt */
cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
cicr0 &= ~CICR0_EOFM;
__raw_writel(cicr0, pcdev->base + CICR0);
}
static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
{
unsigned long cicr0;
pxa_dma_stop_channels(pcdev);
cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
__raw_writel(cicr0, pcdev->base + CICR0);
pcdev->active = NULL;
dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
}
static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
struct pxa_buffer *buf,
enum vb2_buffer_state state)
{
struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
list_del_init(&buf->queue);
vb->timestamp = ktime_get_ns();
vbuf->sequence = pcdev->buf_sequence++;
vbuf->field = V4L2_FIELD_NONE;
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
__func__, buf);
if (list_empty(&pcdev->capture)) {
pxa_camera_stop_capture(pcdev);
return;
}
pcdev->active = list_entry(pcdev->capture.next,
struct pxa_buffer, queue);
}
/**
* pxa_camera_check_link_miss - check missed DMA linking
* @pcdev: camera device
* @last_submitted: an opaque DMA cookie for last submitted
* @last_issued: an opaque DMA cookie for last issued
*
* The DMA chaining is done with DMA running. This means a tiny temporal window
* remains, where a buffer is queued on the chain, while the chain is already
* stopped. This means the tailed buffer would never be transferred by DMA.
* This function restarts the capture for this corner case, where :
* - DADR() == DADDR_STOP
* - a video buffer is queued on the pcdev->capture list
*
* Please check the "DMA hot chaining timeslice issue" in
* Documentation/driver-api/media/drivers/pxa_camera.rst
*
* Context: should only be called within the dma irq handler
*/
static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
dma_cookie_t last_submitted,
dma_cookie_t last_issued)
{
bool is_dma_stopped = last_submitted != last_issued;
dev_dbg(pcdev_to_dev(pcdev),
"%s : top queued buffer=%p, is_dma_stopped=%d\n",
__func__, pcdev->active, is_dma_stopped);
if (pcdev->active && is_dma_stopped)
pxa_camera_start_capture(pcdev);
}
static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
enum pxa_camera_active_dma act_dma)
{
struct pxa_buffer *buf, *last_buf;
unsigned long flags;
u32 camera_status, overrun;
int chan;
enum dma_status last_status;
dma_cookie_t last_issued;
spin_lock_irqsave(&pcdev->lock, flags);
camera_status = __raw_readl(pcdev->base + CISR);
dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
camera_status, act_dma);
overrun = CISR_IFO_0;
if (pcdev->channels == 3)
overrun |= CISR_IFO_1 | CISR_IFO_2;
/*
* pcdev->active should not be NULL in DMA irq handler.
*
* But there is one corner case : if capture was stopped due to an
* overrun of channel 1, and at that same channel 2 was completed.
*
* When handling the overrun in DMA irq for channel 1, we'll stop the
* capture and restart it (and thus set pcdev->active to NULL). But the
* DMA irq handler will already be pending for channel 2. So on entering
* the DMA irq handler for channel 2 there will be no active buffer, yet
* that is normal.
*/
if (!pcdev->active)
goto out;
buf = pcdev->active;
WARN_ON(buf->inwork || list_empty(&buf->queue));
/*
* It's normal if the last frame creates an overrun, as there
* are no more DMA descriptors to fetch from QCI fifos
*/
switch (act_dma) {
case DMA_U:
chan = 1;
break;
case DMA_V:
chan = 2;
break;
default:
chan = 0;
break;
}
last_buf = list_entry(pcdev->capture.prev,
struct pxa_buffer, queue);
last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
last_buf->cookie[chan],
NULL, &last_issued);
if (camera_status & overrun &&
last_status != DMA_COMPLETE) {
dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
camera_status);
pxa_camera_stop_capture(pcdev);
list_for_each_entry(buf, &pcdev->capture, queue)
pxa_dma_add_tail_buf(pcdev, buf);
pxa_camera_start_capture(pcdev);
goto out;
}
buf->active_dma &= ~act_dma;
if (!buf->active_dma) {
pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
last_issued);
}
out:
spin_unlock_irqrestore(&pcdev->lock, flags);
}
static u32 mclk_get_divisor(struct platform_device *pdev,
struct pxa_camera_dev *pcdev)
{
unsigned long mclk = pcdev->mclk;
u32 div;
unsigned long lcdclk;
lcdclk = clk_get_rate(pcdev->clk);
pcdev->ciclk = lcdclk;
/* mclk <= ciclk / 4 (27.4.2) */
if (mclk > lcdclk / 4) {
mclk = lcdclk / 4;
dev_warn(&pdev->dev,
"Limiting master clock to %lu\n", mclk);
}
/* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
/* If we're not supplying MCLK, leave it at 0 */
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
pcdev->mclk = lcdclk / (2 * (div + 1));
dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
lcdclk, mclk, div);
return div;
}
static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
unsigned long pclk)
{
/* We want a timeout > 1 pixel time, not ">=" */
u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
}
static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
{
u32 cicr4 = 0;
/* disable all interrupts */
__raw_writel(0x3ff, pcdev->base + CICR0);
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
cicr4 |= CICR4_PCLK_EN;
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
cicr4 |= CICR4_MCLK_EN;
if (pcdev->platform_flags & PXA_CAMERA_PCP)
cicr4 |= CICR4_PCP;
if (pcdev->platform_flags & PXA_CAMERA_HSP)
cicr4 |= CICR4_HSP;
if (pcdev->platform_flags & PXA_CAMERA_VSP)
cicr4 |= CICR4_VSP;
__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
/* Initialise the timeout under the assumption pclk = mclk */
recalculate_fifo_timeout(pcdev, pcdev->mclk);
else
/* "Safe default" - 13MHz */
recalculate_fifo_timeout(pcdev, 13000000);
clk_prepare_enable(pcdev->clk);
}
static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
{
clk_disable_unprepare(pcdev->clk);
}
static void pxa_camera_eof(struct tasklet_struct *t)
{
struct pxa_camera_dev *pcdev = from_tasklet(pcdev, t, task_eof);
unsigned long cifr;
struct pxa_buffer *buf;
dev_dbg(pcdev_to_dev(pcdev),
"Camera interrupt status 0x%x\n",
__raw_readl(pcdev->base + CISR));
/* Reset the FIFOs */
cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
__raw_writel(cifr, pcdev->base + CIFR);
pcdev->active = list_first_entry(&pcdev->capture,
struct pxa_buffer, queue);
buf = pcdev->active;
pxa_video_buf_set_actdma(pcdev, buf);
pxa_dma_start_channels(pcdev);
}
static irqreturn_t pxa_camera_irq(int irq, void *data)
{
struct pxa_camera_dev *pcdev = data;
unsigned long status, cicr0;
status = __raw_readl(pcdev->base + CISR);
dev_dbg(pcdev_to_dev(pcdev),
"Camera interrupt status 0x%lx\n", status);
if (!status)
return IRQ_NONE;
__raw_writel(status, pcdev->base + CISR);
if (status & CISR_EOF) {
cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
__raw_writel(cicr0, pcdev->base + CICR0);
tasklet_schedule(&pcdev->task_eof);
}
return IRQ_HANDLED;
}
static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
unsigned long flags, __u32 pixfmt)
{
unsigned long dw, bpp;
u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
if (ret < 0)
y_skip_top = 0;
/*
* Datawidth is now guaranteed to be equal to one of the three values.
* We fix bit-per-pixel equal to data-width...
*/
switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
case 10:
dw = 4;
bpp = 0x40;
break;
case 9:
dw = 3;
bpp = 0x20;
break;
default:
/*
* Actually it can only be 8 now,
* default is just to silence compiler warnings
*/
case 8:
dw = 2;
bpp = 0;
}
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
cicr4 |= CICR4_PCLK_EN;
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
cicr4 |= CICR4_MCLK_EN;
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cicr4 |= CICR4_PCP;
if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
cicr4 |= CICR4_HSP;
if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
cicr4 |= CICR4_VSP;
cicr0 = __raw_readl(pcdev->base + CICR0);
if (cicr0 & CICR0_ENB)
__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
switch (pixfmt) {
case V4L2_PIX_FMT_YUV422P:
pcdev->channels = 3;
cicr1 |= CICR1_YCBCR_F;
/*
* Normally, pxa bus wants as input UYVY format. We allow all
* reorderings of the YUV422 format, as no processing is done,
* and the YUV stream is just passed through without any
* transformation. Note that UYVY is the only format that
* should be used if pxa framebuffer Overlay2 is used.
*/
fallthrough;
case V4L2_PIX_FMT_UYVY:
case V4L2_PIX_FMT_VYUY:
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_YVYU:
cicr1 |= CICR1_COLOR_SP_VAL(2);
break;
case V4L2_PIX_FMT_RGB555:
cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
break;
case V4L2_PIX_FMT_RGB565:
cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
break;
}
cicr2 = 0;
cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
CICR3_BFW_VAL(min((u32)255, y_skip_top));
cicr4 |= pcdev->mclk_divisor;
__raw_writel(cicr1, pcdev->base + CICR1);
__raw_writel(cicr2, pcdev->base + CICR2);
__raw_writel(cicr3, pcdev->base + CICR3);
__raw_writel(cicr4, pcdev->base + CICR4);
/* CIF interrupts are not used, only DMA */
cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
__raw_writel(cicr0, pcdev->base + CICR0);
}
/*
* Videobuf2 section
*/
static void pxa_buffer_cleanup(struct pxa_buffer *buf)
{
int i;
for (i = 0; i < 3 && buf->descs[i]; i++) {
dmaengine_desc_free(buf->descs[i]);
kfree(buf->sg[i]);
buf->descs[i] = NULL;
buf->sg[i] = NULL;
buf->sg_len[i] = 0;
buf->plane_sizes[i] = 0;
}
buf->nb_planes = 0;
}
static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
struct pxa_buffer *buf)
{
struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
int nb_channels = pcdev->channels;
int i, ret = 0;
unsigned long size = vb2_plane_size(vb, 0);
switch (nb_channels) {
case 1:
buf->plane_sizes[0] = size;
break;
case 3:
buf->plane_sizes[0] = size / 2;
buf->plane_sizes[1] = size / 4;
buf->plane_sizes[2] = size / 4;
break;
default:
return -EINVAL;
}
buf->nb_planes = nb_channels;
ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
if (ret < 0) {
dev_err(pcdev_to_dev(pcdev),
"sg_split failed: %d\n", ret);
return ret;
}
for (i = 0; i < nb_channels; i++) {
ret = pxa_init_dma_channel(pcdev, buf, i,
buf->sg[i], buf->sg_len[i]);
if (ret) {
pxa_buffer_cleanup(buf);
return ret;
}
}
INIT_LIST_HEAD(&buf->queue);
return ret;
}
static void pxac_vb2_cleanup(struct vb2_buffer *vb)
{
struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
dev_dbg(pcdev_to_dev(pcdev),
"%s(vb=%p)\n", __func__, vb);
pxa_buffer_cleanup(buf);
}
static void pxac_vb2_queue(struct vb2_buffer *vb)
{
struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
dev_dbg(pcdev_to_dev(pcdev),
"%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
pcdev->active);
list_add_tail(&buf->queue, &pcdev->capture);
pxa_dma_add_tail_buf(pcdev, buf);
}
/*
* Please check the DMA prepared buffer structure in :
* Documentation/driver-api/media/drivers/pxa_camera.rst
* Please check also in pxa_camera_check_link_miss() to understand why DMA chain
* modification while DMA chain is running will work anyway.
*/
static int pxac_vb2_prepare(struct vb2_buffer *vb)
{
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
int ret = 0;
#ifdef DEBUG
int i;
#endif
switch (pcdev->channels) {
case 1:
case 3:
vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
break;
default:
return -EINVAL;
}
dev_dbg(pcdev_to_dev(pcdev),
"%s (vb=%p) nb_channels=%d size=%lu\n",
__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
WARN_ON(!pcdev->current_fmt);
#ifdef DEBUG
/*
* This can be useful if you want to see if we actually fill
* the buffer with something
*/
for (i = 0; i < vb->num_planes; i++)
memset((void *)vb2_plane_vaddr(vb, i),
0xaa, vb2_get_plane_payload(vb, i));
#endif
/*
* I think, in buf_prepare you only have to protect global data,
* the actual buffer is yours
*/
buf->inwork = 0;
pxa_video_buf_set_actdma(pcdev, buf);
return ret;
}
static int pxac_vb2_init(struct vb2_buffer *vb)
{
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
dev_dbg(pcdev_to_dev(pcdev),
"%s(nb_channels=%d)\n",
__func__, pcdev->channels);
return pxa_buffer_init(pcdev, buf);
}
static int pxac_vb2_queue_setup(struct vb2_queue *vq,
unsigned int *nbufs,
unsigned int *num_planes, unsigned int sizes[],
struct device *alloc_devs[])
{
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
int size = pcdev->current_pix.sizeimage;
dev_dbg(pcdev_to_dev(pcdev),
"%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
__func__, vq, *nbufs, *num_planes, size);
/*
* Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
* format, even if there are 3 planes Y, U and V, we reply there is only
* one plane, containing Y, U and V data, one after the other.
*/
if (*num_planes)
return sizes[0] < size ? -EINVAL : 0;
*num_planes = 1;
switch (pcdev->channels) {
case 1:
case 3:
sizes[0] = size;
break;
default:
return -EINVAL;
}
if (!*nbufs)
*nbufs = 1;
return 0;
}
static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
__func__, count, pcdev->active);
pcdev->buf_sequence = 0;
if (!pcdev->active)
pxa_camera_start_capture(pcdev);
return 0;
}
static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
{
struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
struct pxa_buffer *buf, *tmp;
dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
__func__, pcdev->active);
pxa_camera_stop_capture(pcdev);
list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
}
static const struct vb2_ops pxac_vb2_ops = {
.queue_setup = pxac_vb2_queue_setup,
.buf_init = pxac_vb2_init,
.buf_prepare = pxac_vb2_prepare,
.buf_queue = pxac_vb2_queue,
.buf_cleanup = pxac_vb2_cleanup,
.start_streaming = pxac_vb2_start_streaming,
.stop_streaming = pxac_vb2_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
{
int ret;
struct vb2_queue *vq = &pcdev->vb2_vq;
memset(vq, 0, sizeof(*vq));
vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
vq->drv_priv = pcdev;
vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
vq->buf_struct_size = sizeof(struct pxa_buffer);
vq->dev = pcdev->v4l2_dev.dev;
vq->ops = &pxac_vb2_ops;
vq->mem_ops = &vb2_dma_sg_memops;
vq->lock = &pcdev->mlock;
ret = vb2_queue_init(vq);
dev_dbg(pcdev_to_dev(pcdev),
"vb2_queue_init(vq=%p): %d\n", vq, ret);
return ret;
}
/*
* Video ioctls section
*/
static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
{
unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample;
struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
int mbus_config;
int ret;
if (!((1 << (bus_width - 1)) & pcdev->width_flags)) {
dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u",
bus_width);
return -EINVAL;
}
pcdev->channels = 1;
/* Make choices, based on platform preferences */
mbus_config = 0;
if (pcdev->platform_flags & PXA_CAMERA_MASTER)
mbus_config |= V4L2_MBUS_MASTER;
else
mbus_config |= V4L2_MBUS_SLAVE;
if (pcdev->platform_flags & PXA_CAMERA_HSP)
mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH;
else
mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW;
if (pcdev->platform_flags & PXA_CAMERA_VSP)
mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH;
else
mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW;
if (pcdev->platform_flags & PXA_CAMERA_PCP)
mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING;
else
mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH;
ret = sensor_call(pcdev, pad, get_mbus_config, 0, &cfg);
if (ret < 0 && ret != -ENOIOCTLCMD) {
dev_err(pcdev_to_dev(pcdev),
"Failed to call get_mbus_config: %d\n", ret);
return ret;
}
/*
* If the media bus configuration of the sensor differs, make sure it
* is supported by the platform.
*
* PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering
* roles should match.
*/
if (cfg.bus.parallel.flags != mbus_config) {
unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER |
V4L2_MBUS_SLAVE);
unsigned int flags = cfg.bus.parallel.flags;
if (pxa_mbus_role != (flags & (V4L2_MBUS_MASTER |
V4L2_MBUS_SLAVE))) {
dev_err(pcdev_to_dev(pcdev),
"Unsupported mbus configuration: bus mastering\n");
return -EINVAL;
}
if (flags & V4L2_MBUS_DATA_ACTIVE_LOW) {
dev_err(pcdev_to_dev(pcdev),
"Unsupported mbus configuration: DATA_ACTIVE_LOW\n");
return -EINVAL;
}
}
pxa_camera_setup_cicr(pcdev, cfg.bus.parallel.flags, pixfmt);
return 0;
}
static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
{
.fourcc = V4L2_PIX_FMT_YUV422P,
.name = "Planar YUV422 16 bit",
.bits_per_sample = 8,
.packing = PXA_MBUS_PACKING_2X8_PADHI,
.order = PXA_MBUS_ORDER_LE,
.layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
},
};
/* This will be corrected as we get more formats */
static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
{
return fmt->packing == PXA_MBUS_PACKING_NONE ||
(fmt->bits_per_sample == 8 &&
fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
(fmt->bits_per_sample > 8 &&
fmt->packing == PXA_MBUS_PACKING_EXTEND16);
}
static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
unsigned int idx,
struct pxa_camera_format_xlate *xlate)
{
struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
int formats = 0, ret;
struct v4l2_subdev_mbus_code_enum code = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
.index = idx,
};
const struct pxa_mbus_pixelfmt *fmt;
ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
if (ret < 0)
/* No more formats */
return 0;
fmt = pxa_mbus_get_fmtdesc(code.code);
if (!fmt) {
dev_err(pcdev_to_dev(pcdev),
"Invalid format code #%u: %d\n", idx, code.code);
return 0;
}
switch (code.code) {
case MEDIA_BUS_FMT_UYVY8_2X8:
formats++;
if (xlate) {
xlate->host_fmt = &pxa_camera_formats[0];
xlate->code = code.code;
xlate++;
dev_dbg(pcdev_to_dev(pcdev),
"Providing format %s using code %d\n",
pxa_camera_formats[0].name, code.code);
}
fallthrough;
case MEDIA_BUS_FMT_VYUY8_2X8:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_RGB565_2X8_LE:
case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
if (xlate)
dev_dbg(pcdev_to_dev(pcdev),
"Providing format %s packed\n",
fmt->name);
break;
default:
if (!pxa_camera_packing_supported(fmt))
return 0;
if (xlate)
dev_dbg(pcdev_to_dev(pcdev),
"Providing format %s in pass-through mode\n",
fmt->name);
break;
}
/* Generic pass-through */
formats++;
if (xlate) {
xlate->host_fmt = fmt;
xlate->code = code.code;
xlate++;
}
return formats;
}
static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
{
struct pxa_camera_format_xlate *xlate;
xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
pxa_camera_get_formats);
if (IS_ERR(xlate))
return PTR_ERR(xlate);
pcdev->user_formats = xlate;
return 0;
}
static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
{
kfree(pcdev->user_formats);
}
static int pxa_camera_check_frame(u32 width, u32 height)
{
/* limit to pxa hardware capabilities */
return height < 32 || height > 2048 || width < 48 || width > 2048 ||
(width & 0x01);
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int pxac_vidioc_g_register(struct file *file, void *priv,
struct v4l2_dbg_register *reg)
{
struct pxa_camera_dev *pcdev = video_drvdata(file);
if (reg->reg > CIBR2)
return -ERANGE;
reg->val = __raw_readl(pcdev->base + reg->reg);
reg->size = sizeof(__u32);
return 0;
}
static int pxac_vidioc_s_register(struct file *file, void *priv,
const struct v4l2_dbg_register *reg)
{
struct pxa_camera_dev *pcdev = video_drvdata(file);
if (reg->reg > CIBR2)
return -ERANGE;
if (reg->size != sizeof(__u32))
return -EINVAL;
__raw_writel(reg->val, pcdev->base + reg->reg);
return 0;
}
#endif
static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
struct v4l2_fmtdesc *f)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
const struct pxa_mbus_pixelfmt *format;
unsigned int idx;
for (idx = 0; pcdev->user_formats[idx].code; idx++);
if (f->index >= idx)
return -EINVAL;
format = pcdev->user_formats[f->index].host_fmt;
f->pixelformat = format->fourcc;
return 0;
}
static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
struct v4l2_format *f)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
struct v4l2_pix_format *pix = &f->fmt.pix;
pix->width = pcdev->current_pix.width;
pix->height = pcdev->current_pix.height;
pix->bytesperline = pcdev->current_pix.bytesperline;
pix->sizeimage = pcdev->current_pix.sizeimage;
pix->field = pcdev->current_pix.field;
pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
pix->colorspace = pcdev->current_pix.colorspace;
dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
pcdev->current_fmt->host_fmt->fourcc);
return 0;
}
static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
struct v4l2_format *f)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
const struct pxa_camera_format_xlate *xlate;
struct v4l2_pix_format *pix = &f->fmt.pix;
struct v4l2_subdev_pad_config pad_cfg;
struct v4l2_subdev_state pad_state = {
.pads = &pad_cfg,
};
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_TRY,
};
struct v4l2_mbus_framefmt *mf = &format.format;
__u32 pixfmt = pix->pixelformat;
int ret;
xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
if (!xlate) {
dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
return -EINVAL;
}
/*
* Limit to pxa hardware capabilities. YUV422P planar format requires
* images size to be a multiple of 16 bytes. If not, zeros will be
* inserted between Y and U planes, and U and V planes, which violates
* the YUV422P standard.
*/
v4l_bound_align_image(&pix->width, 48, 2048, 1,
&pix->height, 32, 2048, 0,
pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
v4l2_fill_mbus_format(mf, pix, xlate->code);
ret = sensor_call(pcdev, pad, set_fmt, &pad_state, &format);
if (ret < 0)
return ret;
v4l2_fill_pix_format(pix, mf);
/* Only progressive video supported so far */
switch (mf->field) {
case V4L2_FIELD_ANY:
case V4L2_FIELD_NONE:
pix->field = V4L2_FIELD_NONE;
break;
default:
/* TODO: support interlaced at least in pass-through mode */
dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
mf->field);
return -EINVAL;
}
ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
if (ret < 0)
return ret;
pix->bytesperline = ret;
ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
pix->height);
if (ret < 0)
return ret;
pix->sizeimage = ret;
return 0;
}
static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
struct v4l2_format *f)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
const struct pxa_camera_format_xlate *xlate;
struct v4l2_pix_format *pix = &f->fmt.pix;
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
unsigned long flags;
int ret, is_busy;
dev_dbg(pcdev_to_dev(pcdev),
"s_fmt_vid_cap(pix=%dx%d:%x)\n",
pix->width, pix->height, pix->pixelformat);
spin_lock_irqsave(&pcdev->lock, flags);
is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
spin_unlock_irqrestore(&pcdev->lock, flags);
if (is_busy)
return -EBUSY;
ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
if (ret)
return ret;
xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
pix->pixelformat);
v4l2_fill_mbus_format(&format.format, pix, xlate->code);
ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
if (ret < 0) {
dev_warn(pcdev_to_dev(pcdev),
"Failed to configure for format %x\n",
pix->pixelformat);
} else if (pxa_camera_check_frame(pix->width, pix->height)) {
dev_warn(pcdev_to_dev(pcdev),
"Camera driver produced an unsupported frame %dx%d\n",
pix->width, pix->height);
return -EINVAL;
}
pcdev->current_fmt = xlate;
pcdev->current_pix = *pix;
ret = pxa_camera_set_bus_param(pcdev);
return ret;
}
static int pxac_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
return 0;
}
static int pxac_vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
if (i->index > 0)
return -EINVAL;
i->type = V4L2_INPUT_TYPE_CAMERA;
strscpy(i->name, "Camera", sizeof(i->name));
return 0;
}
static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
*i = 0;
return 0;
}
static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
if (i > 0)
return -EINVAL;
return 0;
}
static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
{
int ret;
ret = sensor_call(pcdev, core, s_power, on);
if (ret == -ENOIOCTLCMD)
ret = 0;
if (ret) {
dev_warn(pcdev_to_dev(pcdev),
"Failed to put subdevice in %s mode: %d\n",
on ? "normal operation" : "power saving", ret);
}
return ret;
}
static int pxac_fops_camera_open(struct file *filp)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
int ret;
mutex_lock(&pcdev->mlock);
ret = v4l2_fh_open(filp);
if (ret < 0)
goto out;
if (!v4l2_fh_is_singular_file(filp))
goto out;
ret = pxac_sensor_set_power(pcdev, 1);
if (ret)
v4l2_fh_release(filp);
out:
mutex_unlock(&pcdev->mlock);
return ret;
}
static int pxac_fops_camera_release(struct file *filp)
{
struct pxa_camera_dev *pcdev = video_drvdata(filp);
int ret;
bool fh_singular;
mutex_lock(&pcdev->mlock);
fh_singular = v4l2_fh_is_singular_file(filp);
ret = _vb2_fop_release(filp, NULL);
if (fh_singular)
ret = pxac_sensor_set_power(pcdev, 0);
mutex_unlock(&pcdev->mlock);
return ret;
}
static const struct v4l2_file_operations pxa_camera_fops = {
.owner = THIS_MODULE,
.open = pxac_fops_camera_open,
.release = pxac_fops_camera_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
.vidioc_querycap = pxac_vidioc_querycap,
.vidioc_enum_input = pxac_vidioc_enum_input,
.vidioc_g_input = pxac_vidioc_g_input,
.vidioc_s_input = pxac_vidioc_s_input,
.vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = pxac_vidioc_g_register,
.vidioc_s_register = pxac_vidioc_s_register,
#endif
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static const struct video_device pxa_camera_videodev_template = {
.name = "pxa-camera",
.minor = -1,
.fops = &pxa_camera_fops,
.ioctl_ops = &pxa_camera_ioctl_ops,
.release = video_device_release_empty,
.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
};
static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *subdev,
struct v4l2_async_connection *asd)
{
int err;
struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
struct video_device *vdev = &pcdev->vdev;
struct v4l2_pix_format *pix = &pcdev->current_pix;
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct v4l2_mbus_framefmt *mf = &format.format;
dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
__func__);
mutex_lock(&pcdev->mlock);
*vdev = pxa_camera_videodev_template;
vdev->v4l2_dev = v4l2_dev;
vdev->lock = &pcdev->mlock;
pcdev->sensor = subdev;
pcdev->vdev.queue = &pcdev->vb2_vq;
pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
video_set_drvdata(&pcdev->vdev, pcdev);
err = pxa_camera_build_formats(pcdev);
if (err) {
dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
err);
goto out;
}
pcdev->current_fmt = pcdev->user_formats;
pix->field = V4L2_FIELD_NONE;
pix->width = DEFAULT_WIDTH;
pix->height = DEFAULT_HEIGHT;
pix->bytesperline =
pxa_mbus_bytes_per_line(pix->width,
pcdev->current_fmt->host_fmt);
pix->sizeimage =
pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
pix->bytesperline, pix->height);
pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
err = pxac_sensor_set_power(pcdev, 1);
if (err)
goto out;
err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
if (err)
goto out_sensor_poweroff;
v4l2_fill_pix_format(pix, mf);
pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
__func__, pix->colorspace, pix->pixelformat);
err = pxa_camera_init_videobuf2(pcdev);
if (err)
goto out_sensor_poweroff;
err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1);
if (err) {
v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
pcdev->sensor = NULL;
} else {
dev_info(pcdev_to_dev(pcdev),
"PXA Camera driver attached to camera %s\n",
subdev->name);
}
out_sensor_poweroff:
err = pxac_sensor_set_power(pcdev, 0);
out:
mutex_unlock(&pcdev->mlock);
return err;
}
static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *subdev,
struct v4l2_async_connection *asd)
{
struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
mutex_lock(&pcdev->mlock);
dev_info(pcdev_to_dev(pcdev),
"PXA Camera driver detached from camera %s\n",
subdev->name);
/* disable capture, disable interrupts */
__raw_writel(0x3ff, pcdev->base + CICR0);
/* Stop DMA engine */
pxa_dma_stop_channels(pcdev);
pxa_camera_destroy_formats(pcdev);
video_unregister_device(&pcdev->vdev);
pcdev->sensor = NULL;
mutex_unlock(&pcdev->mlock);
}
static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
.bound = pxa_camera_sensor_bound,
.unbind = pxa_camera_sensor_unbind,
};
/*
* Driver probe, remove, suspend and resume operations
*/
static int pxa_camera_suspend(struct device *dev)
{
struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
int i = 0, ret = 0;
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
if (pcdev->sensor)
ret = pxac_sensor_set_power(pcdev, 0);
return ret;
}
static int pxa_camera_resume(struct device *dev)
{
struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
int i = 0, ret = 0;
__raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
if (pcdev->sensor) {
ret = pxac_sensor_set_power(pcdev, 1);
}
/* Restart frame capture if active buffer exists */
if (!ret && pcdev->active)
pxa_camera_start_capture(pcdev);
return ret;
}
static int pxa_camera_pdata_from_dt(struct device *dev,
struct pxa_camera_dev *pcdev)
{
u32 mclk_rate;
struct v4l2_async_connection *asd;
struct device_node *np = dev->of_node;
struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
int err = of_property_read_u32(np, "clock-frequency",
&mclk_rate);
if (!err) {
pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
pcdev->mclk = mclk_rate;
}
np = of_graph_get_next_endpoint(np, NULL);
if (!np) {
dev_err(dev, "could not find endpoint\n");
return -EINVAL;
}
err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
if (err) {
dev_err(dev, "could not parse endpoint\n");
goto out;
}
switch (ep.bus.parallel.bus_width) {
case 4:
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
break;
case 5:
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
break;
case 8:
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
break;
case 9:
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
break;
case 10:
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
break;
default:
break;
}
if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
pcdev->platform_flags |= PXA_CAMERA_MASTER;
if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
pcdev->platform_flags |= PXA_CAMERA_HSP;
if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
pcdev->platform_flags |= PXA_CAMERA_VSP;
if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
asd = v4l2_async_nf_add_fwnode_remote(&pcdev->notifier,
of_fwnode_handle(np),
struct v4l2_async_connection);
if (IS_ERR(asd))
err = PTR_ERR(asd);
out:
of_node_put(np);
return err;
}
static int pxa_camera_probe(struct platform_device *pdev)
{
struct pxa_camera_dev *pcdev;
struct resource *res;
void __iomem *base;
struct dma_slave_config config = {
.src_addr_width = 0,
.src_maxburst = 8,
.direction = DMA_DEV_TO_MEM,
};
int irq;
int err = 0, i;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENODEV;
pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
if (!pcdev) {
dev_err(&pdev->dev, "Could not allocate pcdev\n");
return -ENOMEM;
}
pcdev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pcdev->clk))
return PTR_ERR(pcdev->clk);
/*
* Request the regions.
*/
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
pcdev->irq = irq;
pcdev->base = base;
err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
if (err)
return err;
v4l2_async_nf_init(&pcdev->notifier, &pcdev->v4l2_dev);
pcdev->res = res;
pcdev->pdata = pdev->dev.platform_data;
if (pcdev->pdata) {
struct v4l2_async_connection *asd;
pcdev->platform_flags = pcdev->pdata->flags;
pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
asd = v4l2_async_nf_add_i2c(&pcdev->notifier,
pcdev->pdata->sensor_i2c_adapter_id,
pcdev->pdata->sensor_i2c_address,
struct v4l2_async_connection);
if (IS_ERR(asd))
err = PTR_ERR(asd);
} else if (pdev->dev.of_node) {
err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
} else {
err = -ENODEV;
}
if (err < 0)
goto exit_v4l2_device_unregister;
if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
/*
* Platform hasn't set available data widths. This is bad.
* Warn and use a default.
*/
dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
}
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
pcdev->width_flags = 1 << 7;
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
pcdev->width_flags |= 1 << 8;
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
pcdev->width_flags |= 1 << 9;
if (!pcdev->mclk) {
dev_warn(&pdev->dev,
"mclk == 0! Please, fix your platform data. Using default 20MHz\n");
pcdev->mclk = 20000000;
}
pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
INIT_LIST_HEAD(&pcdev->capture);
spin_lock_init(&pcdev->lock);
mutex_init(&pcdev->mlock);
/* request dma */
pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y");
if (IS_ERR(pcdev->dma_chans[0])) {
dev_err(&pdev->dev, "Can't request DMA for Y\n");
err = PTR_ERR(pcdev->dma_chans[0]);
goto exit_notifier_cleanup;
}
pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U");
if (IS_ERR(pcdev->dma_chans[1])) {
dev_err(&pdev->dev, "Can't request DMA for U\n");
err = PTR_ERR(pcdev->dma_chans[1]);
goto exit_free_dma_y;
}
pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V");
if (IS_ERR(pcdev->dma_chans[2])) {
dev_err(&pdev->dev, "Can't request DMA for V\n");
err = PTR_ERR(pcdev->dma_chans[2]);
goto exit_free_dma_u;
}
for (i = 0; i < 3; i++) {
config.src_addr = pcdev->res->start + CIBR0 + i * 8;
err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
if (err < 0) {
dev_err(&pdev->dev, "dma slave config failed: %d\n",
err);
goto exit_free_dma;
}
}
tasklet_setup(&pcdev->task_eof, pxa_camera_eof);
pxa_camera_activate(pcdev);
platform_set_drvdata(pdev, pcdev);
err = pxa_camera_init_videobuf2(pcdev);
if (err)
goto exit_deactivate;
/* request irq */
err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
PXA_CAM_DRV_NAME, pcdev);
if (err) {
dev_err(&pdev->dev, "Camera interrupt register failed\n");
goto exit_v4l2_device_unregister;
}
pcdev->notifier.ops = &pxa_camera_sensor_ops;
err = v4l2_async_nf_register(&pcdev->notifier);
if (err)
goto exit_deactivate;
return 0;
exit_deactivate:
pxa_camera_deactivate(pcdev);
tasklet_kill(&pcdev->task_eof);
exit_free_dma:
dma_release_channel(pcdev->dma_chans[2]);
exit_free_dma_u:
dma_release_channel(pcdev->dma_chans[1]);
exit_free_dma_y:
dma_release_channel(pcdev->dma_chans[0]);
exit_notifier_cleanup:
v4l2_async_nf_cleanup(&pcdev->notifier);
exit_v4l2_device_unregister:
v4l2_device_unregister(&pcdev->v4l2_dev);
return err;
}
static void pxa_camera_remove(struct platform_device *pdev)
{
struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
pxa_camera_deactivate(pcdev);
tasklet_kill(&pcdev->task_eof);
dma_release_channel(pcdev->dma_chans[0]);
dma_release_channel(pcdev->dma_chans[1]);
dma_release_channel(pcdev->dma_chans[2]);
v4l2_async_nf_unregister(&pcdev->notifier);
v4l2_async_nf_cleanup(&pcdev->notifier);
v4l2_device_unregister(&pcdev->v4l2_dev);
dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
}
static const struct dev_pm_ops pxa_camera_pm = {
.suspend = pxa_camera_suspend,
.resume = pxa_camera_resume,
};
static const struct of_device_id pxa_camera_of_match[] = {
{ .compatible = "marvell,pxa270-qci", },
{},
};
MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
static struct platform_driver pxa_camera_driver = {
.driver = {
.name = PXA_CAM_DRV_NAME,
.pm = &pxa_camera_pm,
.of_match_table = pxa_camera_of_match,
},
.probe = pxa_camera_probe,
.remove_new = pxa_camera_remove,
};
module_platform_driver(pxa_camera_driver);
MODULE_DESCRIPTION("PXA27x Camera Driver");
MODULE_AUTHOR("Guennadi Liakhovetski <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_VERSION(PXA_CAM_VERSION);
MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
| linux-master | drivers/media/platform/intel/pxa_camera.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "vpu.h"
#include "vpu_core.h"
#include "vpu_rpc.h"
#include "vpu_mbox.h"
#include "vpu_defs.h"
#include "vpu_cmds.h"
#include "vpu_msgs.h"
#include "vpu_v4l2.h"
#define VPU_PKT_HEADER_LENGTH 3
struct vpu_msg_handler {
u32 id;
void (*done)(struct vpu_inst *inst, struct vpu_rpc_event *pkt);
};
static void vpu_session_handle_start_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
vpu_trace(inst->dev, "[%d]\n", inst->id);
}
static void vpu_session_handle_mem_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_pkt_mem_req_data req_data = { 0 };
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&req_data);
vpu_trace(inst->dev, "[%d] %d:%d %d:%d %d:%d\n",
inst->id,
req_data.enc_frame_size,
req_data.enc_frame_num,
req_data.ref_frame_size,
req_data.ref_frame_num,
req_data.act_buf_size,
req_data.act_buf_num);
vpu_inst_lock(inst);
call_void_vop(inst, mem_request,
req_data.enc_frame_size,
req_data.enc_frame_num,
req_data.ref_frame_size,
req_data.ref_frame_num,
req_data.act_buf_size,
req_data.act_buf_num);
vpu_inst_unlock(inst);
}
static void vpu_session_handle_stop_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
vpu_trace(inst->dev, "[%d]\n", inst->id);
call_void_vop(inst, stop_done);
}
static void vpu_session_handle_seq_hdr(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_dec_codec_info info;
const struct vpu_core_resources *res;
memset(&info, 0, sizeof(info));
res = vpu_get_resource(inst);
info.stride = res ? res->stride : 1;
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
call_void_vop(inst, event_notify, VPU_MSG_ID_SEQ_HDR_FOUND, &info);
}
static void vpu_session_handle_resolution_change(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
call_void_vop(inst, event_notify, VPU_MSG_ID_RES_CHANGE, NULL);
}
static void vpu_session_handle_enc_frame_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_enc_pic_info info = { 0 };
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
dev_dbg(inst->dev, "[%d] frame id = %d, wptr = 0x%x, size = %d\n",
inst->id, info.frame_id, info.wptr, info.frame_size);
call_void_vop(inst, get_one_frame, &info);
}
static void vpu_session_handle_frame_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_fs_info fs = { 0 };
vpu_iface_unpack_msg_data(inst->core, pkt, &fs);
call_void_vop(inst, event_notify, VPU_MSG_ID_FRAME_REQ, &fs);
}
static void vpu_session_handle_frame_release(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
if (inst->core->type == VPU_CORE_TYPE_ENC) {
struct vpu_frame_info info;
memset(&info, 0, sizeof(info));
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info.sequence);
dev_dbg(inst->dev, "[%d] %d\n", inst->id, info.sequence);
info.type = inst->out_format.type;
call_void_vop(inst, buf_done, &info);
} else if (inst->core->type == VPU_CORE_TYPE_DEC) {
struct vpu_fs_info fs = { 0 };
vpu_iface_unpack_msg_data(inst->core, pkt, &fs);
call_void_vop(inst, event_notify, VPU_MSG_ID_FRAME_RELEASE, &fs);
}
}
static void vpu_session_handle_input_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
dev_dbg(inst->dev, "[%d]\n", inst->id);
call_void_vop(inst, input_done);
}
static void vpu_session_handle_pic_decoded(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_dec_pic_info info = { 0 };
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
call_void_vop(inst, get_one_frame, &info);
}
static void vpu_session_handle_pic_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
struct vpu_dec_pic_info info = { 0 };
struct vpu_frame_info frame;
memset(&frame, 0, sizeof(frame));
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
if (inst->core->type == VPU_CORE_TYPE_DEC)
frame.type = inst->cap_format.type;
frame.id = info.id;
frame.luma = info.luma;
frame.skipped = info.skipped;
frame.timestamp = info.timestamp;
call_void_vop(inst, buf_done, &frame);
}
static void vpu_session_handle_eos(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
call_void_vop(inst, event_notify, VPU_MSG_ID_PIC_EOS, NULL);
}
static void vpu_session_handle_error(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
char *str = (char *)pkt->data;
if (strlen(str))
dev_err(inst->dev, "instance %d firmware error : %s\n", inst->id, str);
else
dev_err(inst->dev, "instance %d is unsupported stream\n", inst->id);
call_void_vop(inst, event_notify, VPU_MSG_ID_UNSUPPORTED, NULL);
vpu_v4l2_set_error(inst);
}
static void vpu_session_handle_firmware_xcpt(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
char *str = (char *)pkt->data;
dev_err(inst->dev, "%s firmware xcpt: %s\n",
vpu_core_type_desc(inst->core->type), str);
call_void_vop(inst, event_notify, VPU_MSG_ID_FIRMWARE_XCPT, NULL);
set_bit(inst->id, &inst->core->hang_mask);
vpu_v4l2_set_error(inst);
}
static void vpu_session_handle_pic_skipped(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
vpu_inst_lock(inst);
vpu_skip_frame(inst, 1);
vpu_inst_unlock(inst);
}
static struct vpu_msg_handler handlers[] = {
{VPU_MSG_ID_START_DONE, vpu_session_handle_start_done},
{VPU_MSG_ID_STOP_DONE, vpu_session_handle_stop_done},
{VPU_MSG_ID_MEM_REQUEST, vpu_session_handle_mem_request},
{VPU_MSG_ID_SEQ_HDR_FOUND, vpu_session_handle_seq_hdr},
{VPU_MSG_ID_RES_CHANGE, vpu_session_handle_resolution_change},
{VPU_MSG_ID_FRAME_INPUT_DONE, vpu_session_handle_input_done},
{VPU_MSG_ID_FRAME_REQ, vpu_session_handle_frame_request},
{VPU_MSG_ID_FRAME_RELEASE, vpu_session_handle_frame_release},
{VPU_MSG_ID_ENC_DONE, vpu_session_handle_enc_frame_done},
{VPU_MSG_ID_PIC_DECODED, vpu_session_handle_pic_decoded},
{VPU_MSG_ID_DEC_DONE, vpu_session_handle_pic_done},
{VPU_MSG_ID_PIC_EOS, vpu_session_handle_eos},
{VPU_MSG_ID_UNSUPPORTED, vpu_session_handle_error},
{VPU_MSG_ID_FIRMWARE_XCPT, vpu_session_handle_firmware_xcpt},
{VPU_MSG_ID_PIC_SKIPPED, vpu_session_handle_pic_skipped},
};
static int vpu_session_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *msg)
{
int ret;
u32 msg_id;
struct vpu_msg_handler *handler = NULL;
unsigned int i;
ret = vpu_iface_convert_msg_id(inst->core, msg->hdr.id);
if (ret < 0)
return -EINVAL;
msg_id = ret;
dev_dbg(inst->dev, "[%d] receive event(%s)\n", inst->id, vpu_id_name(msg_id));
for (i = 0; i < ARRAY_SIZE(handlers); i++) {
if (handlers[i].id == msg_id) {
handler = &handlers[i];
break;
}
}
if (handler && handler->done)
handler->done(inst, msg);
vpu_response_cmd(inst, msg_id, 1);
return 0;
}
static bool vpu_inst_receive_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
unsigned long bytes = sizeof(struct vpu_rpc_event_header);
u32 ret;
memset(pkt, 0, sizeof(*pkt));
if (kfifo_len(&inst->msg_fifo) < bytes)
return false;
ret = kfifo_out(&inst->msg_fifo, pkt, bytes);
if (ret != bytes)
return false;
if (pkt->hdr.num > 0) {
bytes = pkt->hdr.num * sizeof(u32);
ret = kfifo_out(&inst->msg_fifo, pkt->data, bytes);
if (ret != bytes)
return false;
}
return true;
}
void vpu_inst_run_work(struct work_struct *work)
{
struct vpu_inst *inst = container_of(work, struct vpu_inst, msg_work);
struct vpu_rpc_event pkt;
while (vpu_inst_receive_msg(inst, &pkt))
vpu_session_handle_msg(inst, &pkt);
}
static void vpu_inst_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
unsigned long bytes;
u32 id = pkt->hdr.id;
int ret;
if (!inst->workqueue)
return;
bytes = sizeof(pkt->hdr) + pkt->hdr.num * sizeof(u32);
ret = kfifo_in(&inst->msg_fifo, pkt, bytes);
if (ret != bytes)
dev_err(inst->dev, "[%d:%d]overflow: %d\n", inst->core->id, inst->id, id);
queue_work(inst->workqueue, &inst->msg_work);
}
static int vpu_handle_msg(struct vpu_core *core)
{
struct vpu_rpc_event pkt;
struct vpu_inst *inst;
int ret;
memset(&pkt, 0, sizeof(pkt));
while (!vpu_iface_receive_msg(core, &pkt)) {
dev_dbg(core->dev, "event index = %d, id = %d, num = %d\n",
pkt.hdr.index, pkt.hdr.id, pkt.hdr.num);
ret = vpu_iface_convert_msg_id(core, pkt.hdr.id);
if (ret < 0)
continue;
inst = vpu_core_find_instance(core, pkt.hdr.index);
if (inst) {
vpu_response_cmd(inst, ret, 0);
mutex_lock(&core->cmd_lock);
vpu_inst_record_flow(inst, ret);
mutex_unlock(&core->cmd_lock);
vpu_inst_handle_msg(inst, &pkt);
vpu_inst_put(inst);
}
memset(&pkt, 0, sizeof(pkt));
}
return 0;
}
static int vpu_isr_thread(struct vpu_core *core, u32 irq_code)
{
dev_dbg(core->dev, "irq code = 0x%x\n", irq_code);
switch (irq_code) {
case VPU_IRQ_CODE_SYNC:
vpu_mbox_send_msg(core, PRC_BUF_OFFSET, core->rpc.phys - core->fw.phys);
vpu_mbox_send_msg(core, BOOT_ADDRESS, core->fw.phys);
vpu_mbox_send_msg(core, INIT_DONE, 2);
break;
case VPU_IRQ_CODE_BOOT_DONE:
break;
case VPU_IRQ_CODE_SNAPSHOT_DONE:
break;
default:
vpu_handle_msg(core);
break;
}
return 0;
}
static void vpu_core_run_msg_work(struct vpu_core *core)
{
const unsigned int SIZE = sizeof(u32);
while (kfifo_len(&core->msg_fifo) >= SIZE) {
u32 data = 0;
if (kfifo_out(&core->msg_fifo, &data, SIZE) == SIZE)
vpu_isr_thread(core, data);
}
}
void vpu_msg_run_work(struct work_struct *work)
{
struct vpu_core *core = container_of(work, struct vpu_core, msg_work);
unsigned long delay = msecs_to_jiffies(10);
vpu_core_run_msg_work(core);
queue_delayed_work(core->workqueue, &core->msg_delayed_work, delay);
}
void vpu_msg_delayed_work(struct work_struct *work)
{
struct vpu_core *core;
struct delayed_work *dwork;
unsigned long bytes = sizeof(u32);
u32 i;
if (!work)
return;
dwork = to_delayed_work(work);
core = container_of(dwork, struct vpu_core, msg_delayed_work);
if (kfifo_len(&core->msg_fifo) >= bytes)
vpu_core_run_msg_work(core);
bytes = sizeof(struct vpu_rpc_event_header);
for (i = 0; i < core->supported_instance_count; i++) {
struct vpu_inst *inst = vpu_core_find_instance(core, i);
if (!inst)
continue;
if (inst->workqueue && kfifo_len(&inst->msg_fifo) >= bytes)
queue_work(inst->workqueue, &inst->msg_work);
vpu_inst_put(inst);
}
}
int vpu_isr(struct vpu_core *core, u32 irq)
{
switch (irq) {
case VPU_IRQ_CODE_SYNC:
break;
case VPU_IRQ_CODE_BOOT_DONE:
complete(&core->cmp);
break;
case VPU_IRQ_CODE_SNAPSHOT_DONE:
complete(&core->cmp);
break;
default:
break;
}
if (kfifo_in(&core->msg_fifo, &irq, sizeof(irq)) != sizeof(irq))
dev_err(core->dev, "[%d]overflow: %d\n", core->id, irq);
queue_work(core->workqueue, &core->msg_work);
return 0;
}
| linux-master | drivers/media/platform/amphion/vpu_msgs.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "vpu.h"
#include "vpu_mbox.h"
#include "vpu_msgs.h"
static void vpu_mbox_rx_callback(struct mbox_client *cl, void *msg)
{
struct vpu_mbox *rx = container_of(cl, struct vpu_mbox, cl);
struct vpu_core *core = container_of(rx, struct vpu_core, rx);
vpu_isr(core, *(u32 *)msg);
}
static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox)
{
struct mbox_chan *ch;
struct mbox_client *cl;
if (!dev || !mbox)
return -EINVAL;
if (mbox->ch)
return 0;
cl = &mbox->cl;
cl->dev = dev;
if (mbox->block) {
cl->tx_block = true;
cl->tx_tout = 1000;
} else {
cl->tx_block = false;
}
cl->knows_txdone = false;
cl->rx_callback = vpu_mbox_rx_callback;
ch = mbox_request_channel_byname(cl, mbox->name);
if (IS_ERR(ch))
return dev_err_probe(dev, PTR_ERR(ch),
"Failed to request mbox chan %s\n",
mbox->name);
mbox->ch = ch;
return 0;
}
int vpu_mbox_init(struct vpu_core *core)
{
scnprintf(core->tx_type.name, sizeof(core->tx_type.name) - 1, "tx0");
core->tx_type.block = true;
scnprintf(core->tx_data.name, sizeof(core->tx_data.name) - 1, "tx1");
core->tx_data.block = false;
scnprintf(core->rx.name, sizeof(core->rx.name) - 1, "rx");
core->rx.block = true;
return 0;
}
int vpu_mbox_request(struct vpu_core *core)
{
int ret;
ret = vpu_mbox_request_channel(core->dev, &core->tx_type);
if (ret)
goto error;
ret = vpu_mbox_request_channel(core->dev, &core->tx_data);
if (ret)
goto error;
ret = vpu_mbox_request_channel(core->dev, &core->rx);
if (ret)
goto error;
dev_dbg(core->dev, "%s request mbox\n", vpu_core_type_desc(core->type));
return 0;
error:
vpu_mbox_free(core);
return ret;
}
void vpu_mbox_free(struct vpu_core *core)
{
mbox_free_channel(core->tx_type.ch);
mbox_free_channel(core->tx_data.ch);
mbox_free_channel(core->rx.ch);
core->tx_type.ch = NULL;
core->tx_data.ch = NULL;
core->rx.ch = NULL;
dev_dbg(core->dev, "%s free mbox\n", vpu_core_type_desc(core->type));
}
void vpu_mbox_send_type(struct vpu_core *core, u32 type)
{
mbox_send_message(core->tx_type.ch, &type);
}
void vpu_mbox_send_msg(struct vpu_core *core, u32 type, u32 data)
{
mbox_send_message(core->tx_data.ch, &data);
mbox_send_message(core->tx_type.ch, &type);
}
void vpu_mbox_enable_rx(struct vpu_dev *dev)
{
}
| linux-master | drivers/media/platform/amphion/vpu_mbox.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-map-ops.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pm_runtime.h>
#include <linux/videodev2.h>
#include <linux/of_reserved_mem.h>
#include <media/v4l2-device.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ioctl.h>
#include <linux/debugfs.h>
#include "vpu.h"
#include "vpu_imx8q.h"
bool debug;
module_param(debug, bool, 0644);
void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val)
{
writel(val, vpu->base + reg);
}
u32 vpu_readl(struct vpu_dev *vpu, u32 reg)
{
return readl(vpu->base + reg);
}
static void vpu_dev_get(struct vpu_dev *vpu)
{
if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup)
vpu->res->setup(vpu);
}
static void vpu_dev_put(struct vpu_dev *vpu)
{
atomic_dec(&vpu->ref_vpu);
}
static void vpu_enc_get(struct vpu_dev *vpu)
{
if (atomic_inc_return(&vpu->ref_enc) == 1 && vpu->res->setup_encoder)
vpu->res->setup_encoder(vpu);
}
static void vpu_enc_put(struct vpu_dev *vpu)
{
atomic_dec(&vpu->ref_enc);
}
static void vpu_dec_get(struct vpu_dev *vpu)
{
if (atomic_inc_return(&vpu->ref_dec) == 1 && vpu->res->setup_decoder)
vpu->res->setup_decoder(vpu);
}
static void vpu_dec_put(struct vpu_dev *vpu)
{
atomic_dec(&vpu->ref_dec);
}
static int vpu_init_media_device(struct vpu_dev *vpu)
{
vpu->mdev.dev = vpu->dev;
strscpy(vpu->mdev.model, "amphion-vpu", sizeof(vpu->mdev.model));
strscpy(vpu->mdev.bus_info, "platform: amphion-vpu", sizeof(vpu->mdev.bus_info));
media_device_init(&vpu->mdev);
vpu->v4l2_dev.mdev = &vpu->mdev;
return 0;
}
static int vpu_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct vpu_dev *vpu;
int ret;
dev_dbg(dev, "probe\n");
vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL);
if (!vpu)
return -ENOMEM;
vpu->pdev = pdev;
vpu->dev = dev;
mutex_init(&vpu->lock);
INIT_LIST_HEAD(&vpu->cores);
platform_set_drvdata(pdev, vpu);
atomic_set(&vpu->ref_vpu, 0);
atomic_set(&vpu->ref_enc, 0);
atomic_set(&vpu->ref_dec, 0);
vpu->get_vpu = vpu_dev_get;
vpu->put_vpu = vpu_dev_put;
vpu->get_enc = vpu_enc_get;
vpu->put_enc = vpu_enc_put;
vpu->get_dec = vpu_dec_get;
vpu->put_dec = vpu_dec_put;
vpu->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vpu->base))
return PTR_ERR(vpu->base);
vpu->res = of_device_get_match_data(dev);
if (!vpu->res)
return -ENODEV;
pm_runtime_enable(dev);
ret = v4l2_device_register(dev, &vpu->v4l2_dev);
if (ret)
goto err_vpu_deinit;
vpu_init_media_device(vpu);
vpu->encoder.type = VPU_CORE_TYPE_ENC;
vpu->encoder.function = MEDIA_ENT_F_PROC_VIDEO_ENCODER;
vpu->decoder.type = VPU_CORE_TYPE_DEC;
vpu->decoder.function = MEDIA_ENT_F_PROC_VIDEO_DECODER;
ret = vpu_add_func(vpu, &vpu->decoder);
if (ret)
goto err_add_decoder;
ret = vpu_add_func(vpu, &vpu->encoder);
if (ret)
goto err_add_encoder;
ret = media_device_register(&vpu->mdev);
if (ret)
goto err_vpu_media;
vpu->debugfs = debugfs_create_dir("amphion_vpu", NULL);
of_platform_populate(dev->of_node, NULL, NULL, dev);
return 0;
err_vpu_media:
vpu_remove_func(&vpu->encoder);
err_add_encoder:
vpu_remove_func(&vpu->decoder);
err_add_decoder:
media_device_cleanup(&vpu->mdev);
v4l2_device_unregister(&vpu->v4l2_dev);
err_vpu_deinit:
pm_runtime_set_suspended(dev);
pm_runtime_disable(dev);
return ret;
}
static void vpu_remove(struct platform_device *pdev)
{
struct vpu_dev *vpu = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
debugfs_remove_recursive(vpu->debugfs);
vpu->debugfs = NULL;
pm_runtime_disable(dev);
media_device_unregister(&vpu->mdev);
vpu_remove_func(&vpu->decoder);
vpu_remove_func(&vpu->encoder);
media_device_cleanup(&vpu->mdev);
v4l2_device_unregister(&vpu->v4l2_dev);
mutex_destroy(&vpu->lock);
}
static int __maybe_unused vpu_runtime_resume(struct device *dev)
{
return 0;
}
static int __maybe_unused vpu_runtime_suspend(struct device *dev)
{
return 0;
}
static int __maybe_unused vpu_resume(struct device *dev)
{
return 0;
}
static int __maybe_unused vpu_suspend(struct device *dev)
{
return 0;
}
static const struct dev_pm_ops vpu_pm_ops = {
SET_RUNTIME_PM_OPS(vpu_runtime_suspend, vpu_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
};
static struct vpu_resources imx8qxp_res = {
.plat_type = IMX8QXP,
.mreg_base = 0x40000000,
.setup = vpu_imx8q_setup,
.setup_encoder = vpu_imx8q_setup_enc,
.setup_decoder = vpu_imx8q_setup_dec,
.reset = vpu_imx8q_reset
};
static struct vpu_resources imx8qm_res = {
.plat_type = IMX8QM,
.mreg_base = 0x40000000,
.setup = vpu_imx8q_setup,
.setup_encoder = vpu_imx8q_setup_enc,
.setup_decoder = vpu_imx8q_setup_dec,
.reset = vpu_imx8q_reset
};
static const struct of_device_id vpu_dt_match[] = {
{ .compatible = "nxp,imx8qxp-vpu", .data = &imx8qxp_res },
{ .compatible = "nxp,imx8qm-vpu", .data = &imx8qm_res },
{}
};
MODULE_DEVICE_TABLE(of, vpu_dt_match);
static struct platform_driver amphion_vpu_driver = {
.probe = vpu_probe,
.remove_new = vpu_remove,
.driver = {
.name = "amphion-vpu",
.of_match_table = vpu_dt_match,
.pm = &vpu_pm_ops,
},
};
static int __init vpu_driver_init(void)
{
int ret;
ret = platform_driver_register(&hion_vpu_driver);
if (ret)
return ret;
ret = vpu_core_driver_init();
if (ret)
platform_driver_unregister(&hion_vpu_driver);
return ret;
}
static void __exit vpu_driver_exit(void)
{
vpu_core_driver_exit();
platform_driver_unregister(&hion_vpu_driver);
}
module_init(vpu_driver_init);
module_exit(vpu_driver_exit);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX8Q");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/amphion/vpu_drv.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/time64.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include "vpu.h"
#include "vpu_rpc.h"
#include "vpu_defs.h"
#include "vpu_helpers.h"
#include "vpu_cmds.h"
#include "vpu_v4l2.h"
#include "vpu_imx8q.h"
#include "vpu_windsor.h"
#define CMD_SIZE 2560
#define MSG_SIZE 25600
#define WINDSOR_USER_DATA_WORDS 16
#define WINDSOR_MAX_SRC_FRAMES 0x6
#define WINDSOR_MAX_REF_FRAMES 0x3
#define WINDSOR_BITRATE_UNIT 1024
#define WINDSOR_H264_EXTENDED_SAR 255
enum {
GTB_ENC_CMD_NOOP = 0x0,
GTB_ENC_CMD_STREAM_START,
GTB_ENC_CMD_FRAME_ENCODE,
GTB_ENC_CMD_FRAME_SKIP,
GTB_ENC_CMD_STREAM_STOP,
GTB_ENC_CMD_PARAMETER_UPD,
GTB_ENC_CMD_TERMINATE,
GTB_ENC_CMD_SNAPSHOT,
GTB_ENC_CMD_ROLL_SNAPSHOT,
GTB_ENC_CMD_LOCK_SCHEDULER,
GTB_ENC_CMD_UNLOCK_SCHEDULER,
GTB_ENC_CMD_CONFIGURE_CODEC,
GTB_ENC_CMD_DEAD_MARK,
GTB_ENC_CMD_FIRM_RESET,
GTB_ENC_CMD_FW_STATUS,
GTB_ENC_CMD_RESERVED
};
enum {
VID_API_EVENT_UNDEFINED = 0x0,
VID_API_ENC_EVENT_RESET_DONE = 0x1,
VID_API_ENC_EVENT_START_DONE,
VID_API_ENC_EVENT_STOP_DONE,
VID_API_ENC_EVENT_TERMINATE_DONE,
VID_API_ENC_EVENT_FRAME_INPUT_DONE,
VID_API_ENC_EVENT_FRAME_DONE,
VID_API_ENC_EVENT_FRAME_RELEASE,
VID_API_ENC_EVENT_PARA_UPD_DONE,
VID_API_ENC_EVENT_MEM_REQUEST,
VID_API_ENC_EVENT_FIRMWARE_XCPT,
VID_API_ENC_EVENT_RESERVED
};
enum {
MEDIAIP_ENC_PIC_TYPE_B_FRAME = 0,
MEDIAIP_ENC_PIC_TYPE_P_FRAME,
MEDIAIP_ENC_PIC_TYPE_I_FRAME,
MEDIAIP_ENC_PIC_TYPE_IDR_FRAME,
MEDIAIP_ENC_PIC_TYPE_BI_FRAME
};
struct windsor_iface {
u32 exec_base_addr;
u32 exec_area_size;
struct vpu_rpc_buffer_desc cmd_buffer_desc;
struct vpu_rpc_buffer_desc msg_buffer_desc;
u32 cmd_int_enable[VID_API_NUM_STREAMS];
u32 fw_version;
u32 mvd_fw_offset;
u32 max_streams;
u32 ctrl_iface[VID_API_NUM_STREAMS];
struct vpu_rpc_system_config system_config;
u32 api_version;
struct vpu_rpc_buffer_desc log_buffer_desc;
};
struct windsor_ctrl_iface {
u32 enc_yuv_buffer_desc;
u32 enc_stream_buffer_desc;
u32 enc_expert_mode_param;
u32 enc_param;
u32 enc_mem_pool;
u32 enc_encoding_status;
u32 enc_dsa_status;
};
struct vpu_enc_yuv_desc {
u32 frame_id;
u32 luma_base;
u32 chroma_base;
u32 param_idx;
u32 key_frame;
};
struct vpu_enc_calib_params {
u32 use_ame;
u32 cme_mvx_max;
u32 cme_mvy_max;
u32 ame_prefresh_y0;
u32 ame_prefresh_y1;
u32 fme_min_sad;
u32 cme_min_sad;
u32 fme_pred_int_weight;
u32 fme_pred_hp_weight;
u32 fme_pred_qp_weight;
u32 fme_cost_weight;
u32 fme_act_thold;
u32 fme_sad_thold;
u32 fme_zero_sad_thold;
u32 fme_lrg_mvx_lmt;
u32 fme_lrg_mvy_lmt;
u32 fme_force_mode;
u32 fme_force4mvcost;
u32 fme_force2mvcost;
u32 h264_inter_thrd;
u32 i16x16_mode_cost;
u32 i4x4_mode_lambda;
u32 i8x8_mode_lambda;
u32 inter_mod_mult;
u32 inter_sel_mult;
u32 inter_bid_cost;
u32 inter_bwd_cost;
u32 inter_4mv_cost;
s32 one_mv_i16_cost;
s32 one_mv_i4x4_cost;
s32 one_mv_i8x8_cost;
s32 two_mv_i16_cost;
s32 two_mv_i4x4_cost;
s32 two_mv_i8x8_cost;
s32 four_mv_i16_cost;
s32 four_mv_i4x4_cost;
s32 four_mv_i8x8_cost;
u32 intra_pred_enab;
u32 intra_chr_pred;
u32 intra16_pred;
u32 intra4x4_pred;
u32 intra8x8_pred;
u32 cb_base;
u32 cb_size;
u32 cb_head_room;
u32 mem_page_width;
u32 mem_page_height;
u32 mem_total_size;
u32 mem_chunk_phys_addr;
u32 mem_chunk_virt_addr;
u32 mem_chunk_size;
u32 mem_y_stride;
u32 mem_uv_stride;
u32 split_wr_enab;
u32 split_wr_req_size;
u32 split_rd_enab;
u32 split_rd_req_size;
};
struct vpu_enc_config_params {
u32 param_change;
u32 start_frame;
u32 end_frame;
u32 userdata_enable;
u32 userdata_id[4];
u32 userdata_message[WINDSOR_USER_DATA_WORDS];
u32 userdata_length;
u32 h264_profile_idc;
u32 h264_level_idc;
u32 h264_au_delimiter;
u32 h264_seq_end_code;
u32 h264_recovery_points;
u32 h264_vui_parameters;
u32 h264_aspect_ratio_present;
u32 h264_aspect_ratio_sar_width;
u32 h264_aspect_ratio_sar_height;
u32 h264_overscan_present;
u32 h264_video_type_present;
u32 h264_video_format;
u32 h264_video_full_range;
u32 h264_video_colour_descriptor;
u32 h264_video_colour_primaries;
u32 h264_video_transfer_char;
u32 h264_video_matrix_coeff;
u32 h264_chroma_loc_info_present;
u32 h264_chroma_loc_type_top;
u32 h264_chroma_loc_type_bot;
u32 h264_timing_info_present;
u32 h264_buffering_period_present;
u32 h264_low_delay_hrd_flag;
u32 aspect_ratio;
u32 test_mode; // Automated firmware test mode
u32 dsa_test_mode; // Automated test mode for the DSA.
u32 fme_test_mode; // Automated test mode for the fme
u32 cbr_row_mode; //0: FW mode; 1: HW mode
u32 windsor_mode; //0: normal mode; 1: intra only mode; 2: intra+0MV mode
u32 encode_mode; // H264, VC1, MPEG2, DIVX
u32 frame_width; // display width
u32 frame_height; // display height
u32 enc_frame_width; // encoding width, should be 16-pix align
u32 enc_frame_height; // encoding height, should be 16-pix aligned
u32 frame_rate_num;
u32 frame_rate_den;
u32 vi_field_source;
u32 vi_frame_width;
u32 vi_frame_height;
u32 crop_frame_width;
u32 crop_frame_height;
u32 crop_x_start_posn;
u32 crop_y_start_posn;
u32 mode422;
u32 mode_yuy2;
u32 dsa_luma_en;
u32 dsa_chroma_en;
u32 dsa_ext_hfilt_en;
u32 dsa_di_en;
u32 dsa_di_top_ref;
u32 dsa_vertf_disable;
u32 dsa_disable_pwb;
u32 dsa_hor_phase;
u32 dsa_ver_phase;
u32 dsa_iac_enable;
u32 iac_sc_threshold;
u32 iac_vm_threshold;
u32 iac_skip_mode;
u32 iac_grp_width;
u32 iac_grp_height;
u32 rate_control_mode;
u32 rate_control_resolution;
u32 buffer_size;
u32 buffer_level_init;
u32 buffer_I_bit_budget;
u32 top_field_first;
u32 intra_lum_qoffset;
u32 intra_chr_qoffset;
u32 inter_lum_qoffset;
u32 inter_chr_qoffset;
u32 use_def_scaling_mtx;
u32 inter_8x8_enab;
u32 inter_4x4_enab;
u32 fme_enable_qpel;
u32 fme_enable_hpel;
u32 fme_nozeromv;
u32 fme_predmv_en;
u32 fme_pred_2mv4mv;
u32 fme_smallsadthresh;
u32 ame_en_lmvc;
u32 ame_x_mult;
u32 cme_enable_4mv;
u32 cme_enable_1mv;
u32 hme_enable_16x8mv;
u32 hme_enable_8x16mv;
u32 cme_mv_weight;
u32 cme_mv_cost;
u32 ame_mult_mv;
u32 ame_shift_mv;
u32 hme_forceto1mv_en;
u32 hme_2mv_cost;
u32 hme_pred_mode;
u32 hme_sc_rnge;
u32 hme_sw_rnge;
u32 output_format;
u32 timestamp_enab;
u32 initial_pts_enab;
u32 initial_pts;
};
struct vpu_enc_static_params {
u32 param_change;
u32 gop_length;
u32 rate_control_bitrate;
u32 rate_control_bitrate_min;
u32 rate_control_bitrate_max;
u32 rate_control_content_models;
u32 rate_control_iframe_maxsize;
u32 rate_control_qp_init;
u32 rate_control_islice_qp;
u32 rate_control_pslice_qp;
u32 rate_control_bslice_qp;
u32 adaptive_quantization;
u32 aq_variance;
u32 cost_optimization;
u32 fdlp_mode;
u32 enable_isegbframes;
u32 enable_adaptive_keyratio;
u32 keyratio_imin;
u32 keyratio_imax;
u32 keyratio_pmin;
u32 keyratio_pmax;
u32 keyratio_bmin;
u32 keyratio_bmax;
s32 keyratio_istep;
s32 keyratio_pstep;
s32 keyratio_bstep;
u32 enable_paff;
u32 enable_b_frame_ref;
u32 enable_adaptive_gop;
u32 enable_closed_gop;
u32 open_gop_refresh_freq;
u32 enable_adaptive_sc;
u32 enable_fade_detection;
s32 fade_detection_threshold;
u32 enable_repeat_b;
u32 enable_low_delay_b;
};
struct vpu_enc_dynamic_params {
u32 param_change;
u32 rows_per_slice;
u32 mbaff_enable;
u32 dbf_enable;
u32 field_source;
u32 gop_b_length;
u32 mb_group_size;
u32 cbr_rows_per_group;
u32 skip_enable;
u32 pts_bits_0_to_31;
u32 pts_bit_32;
u32 rm_expsv_cff;
u32 const_ipred;
s32 chr_qp_offset;
u32 intra_mb_qp_offset;
u32 h264_cabac_init_method;
u32 h264_cabac_init_idc;
u32 h264_cabac_enable;
s32 alpha_c0_offset_div2;
s32 beta_offset_div2;
u32 intra_prefresh_y0;
u32 intra_prefresh_y1;
u32 dbg_dump_rec_src;
};
struct vpu_enc_expert_mode_param {
struct vpu_enc_calib_params calib_param;
struct vpu_enc_config_params config_param;
struct vpu_enc_static_params static_param;
struct vpu_enc_dynamic_params dynamic_param;
};
enum MEDIAIP_ENC_FMT {
MEDIAIP_ENC_FMT_H264 = 0,
MEDIAIP_ENC_FMT_VC1,
MEDIAIP_ENC_FMT_MPEG2,
MEDIAIP_ENC_FMT_MPEG4SP,
MEDIAIP_ENC_FMT_H263,
MEDIAIP_ENC_FMT_MPEG1,
MEDIAIP_ENC_FMT_SHORT_HEADER,
MEDIAIP_ENC_FMT_NULL
};
enum MEDIAIP_ENC_PROFILE {
MEDIAIP_ENC_PROF_MPEG2_SP = 0,
MEDIAIP_ENC_PROF_MPEG2_MP,
MEDIAIP_ENC_PROF_MPEG2_HP,
MEDIAIP_ENC_PROF_H264_BP,
MEDIAIP_ENC_PROF_H264_MP,
MEDIAIP_ENC_PROF_H264_HP,
MEDIAIP_ENC_PROF_MPEG4_SP,
MEDIAIP_ENC_PROF_MPEG4_ASP,
MEDIAIP_ENC_PROF_VC1_SP,
MEDIAIP_ENC_PROF_VC1_MP,
MEDIAIP_ENC_PROF_VC1_AP
};
enum MEDIAIP_ENC_BITRATE_MODE {
MEDIAIP_ENC_BITRATE_MODE_VBR = 0x00000001,
MEDIAIP_ENC_BITRATE_MODE_CBR = 0x00000002,
MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP = 0x00000004
};
struct vpu_enc_memory_resource {
u32 phys;
u32 virt;
u32 size;
};
struct vpu_enc_param {
enum MEDIAIP_ENC_FMT codec_mode;
enum MEDIAIP_ENC_PROFILE profile;
u32 level;
struct vpu_enc_memory_resource enc_mem_desc;
u32 frame_rate;
u32 src_stride;
u32 src_width;
u32 src_height;
u32 src_offset_x;
u32 src_offset_y;
u32 src_crop_width;
u32 src_crop_height;
u32 out_width;
u32 out_height;
u32 iframe_interval;
u32 bframes;
u32 low_latency_mode;
enum MEDIAIP_ENC_BITRATE_MODE bitrate_mode;
u32 target_bitrate;
u32 max_bitrate;
u32 min_bitrate;
u32 init_slice_qp;
};
struct vpu_enc_mem_pool {
struct vpu_enc_memory_resource enc_frames[WINDSOR_MAX_SRC_FRAMES];
struct vpu_enc_memory_resource ref_frames[WINDSOR_MAX_REF_FRAMES];
struct vpu_enc_memory_resource act_frame;
};
struct vpu_enc_encoding_status {
u32 frame_id;
u32 error_flag; //Error type
u32 mb_y;
u32 mb_x;
u32 reserved[12];
};
struct vpu_enc_dsa_status {
u32 frame_id;
u32 dsa_cyle;
u32 mb_y;
u32 mb_x;
u32 reserved[4];
};
struct vpu_enc_ctrl {
struct vpu_enc_yuv_desc *yuv_desc;
struct vpu_rpc_buffer_desc *stream_desc;
struct vpu_enc_expert_mode_param *expert;
struct vpu_enc_param *param;
struct vpu_enc_mem_pool *pool;
struct vpu_enc_encoding_status *status;
struct vpu_enc_dsa_status *dsa;
};
struct vpu_enc_host_ctrls {
struct vpu_enc_ctrl ctrls[VID_API_NUM_STREAMS];
};
struct windsor_pic_info {
u32 frame_id;
u32 pic_encod_done;
u32 pic_type;
u32 skipped_frame;
u32 error_flag;
u32 psnr;
u32 flush_done;
u32 mb_y;
u32 mb_x;
u32 frame_size;
u32 frame_enc_ttl_cycles;
u32 frame_enc_ttl_frm_cycles;
u32 frame_enc_ttl_slc_cycles;
u32 frame_enc_ttl_enc_cycles;
u32 frame_enc_ttl_hme_cycles;
u32 frame_enc_ttl_dsa_cycles;
u32 frame_enc_fw_cycles;
u32 frame_crc;
u32 num_interrupts_1;
u32 num_interrupts_2;
u32 poc;
u32 ref_info;
u32 pic_num;
u32 pic_activity;
u32 scene_change;
u32 mb_stats;
u32 enc_cache_count0;
u32 enc_cache_count1;
u32 mtl_wr_strb_cnt;
u32 mtl_rd_strb_cnt;
u32 str_buff_wptr;
u32 diagnosticEvents;
u32 proc_iacc_tot_rd_cnt;
u32 proc_dacc_tot_rd_cnt;
u32 proc_dacc_tot_wr_cnt;
u32 proc_dacc_reg_rd_cnt;
u32 proc_dacc_reg_wr_cnt;
u32 proc_dacc_rng_rd_cnt;
u32 proc_dacc_rng_wr_cnt;
s32 tv_s;
u32 tv_ns;
};
u32 vpu_windsor_get_data_size(void)
{
return sizeof(struct vpu_enc_host_ctrls);
}
static struct vpu_enc_yuv_desc *get_yuv_desc(struct vpu_shared_addr *shared,
u32 instance)
{
struct vpu_enc_host_ctrls *hcs = shared->priv;
return hcs->ctrls[instance].yuv_desc;
}
static struct vpu_enc_mem_pool *get_mem_pool(struct vpu_shared_addr *shared,
u32 instance)
{
struct vpu_enc_host_ctrls *hcs = shared->priv;
return hcs->ctrls[instance].pool;
}
static struct vpu_rpc_buffer_desc *get_stream_buf_desc(struct vpu_shared_addr *shared,
u32 instance)
{
struct vpu_enc_host_ctrls *hcs = shared->priv;
return hcs->ctrls[instance].stream_desc;
}
static struct vpu_enc_expert_mode_param *get_expert_param(struct vpu_shared_addr *shared,
u32 instance)
{
struct vpu_enc_host_ctrls *hcs = shared->priv;
return hcs->ctrls[instance].expert;
}
static struct vpu_enc_param *get_enc_param(struct vpu_shared_addr *shared, u32 instance)
{
struct vpu_enc_host_ctrls *hcs = shared->priv;
return hcs->ctrls[instance].param;
}
static u32 get_ptr(u32 ptr)
{
return (ptr | 0x80000000);
}
void vpu_windsor_init_rpc(struct vpu_shared_addr *shared,
struct vpu_buffer *rpc, dma_addr_t boot_addr)
{
unsigned long base_phy_addr;
unsigned long phy_addr;
unsigned long offset;
struct windsor_iface *iface;
struct windsor_ctrl_iface *ctrl;
struct vpu_enc_host_ctrls *hcs;
unsigned int i;
if (rpc->phys < boot_addr)
return;
base_phy_addr = rpc->phys - boot_addr;
iface = rpc->virt;
shared->iface = iface;
shared->boot_addr = boot_addr;
hcs = shared->priv;
iface->exec_base_addr = base_phy_addr;
iface->exec_area_size = rpc->length;
offset = sizeof(struct windsor_iface);
phy_addr = base_phy_addr + offset;
shared->cmd_desc = &iface->cmd_buffer_desc;
shared->cmd_mem_vir = rpc->virt + offset;
iface->cmd_buffer_desc.start =
iface->cmd_buffer_desc.rptr =
iface->cmd_buffer_desc.wptr = phy_addr;
iface->cmd_buffer_desc.end = iface->cmd_buffer_desc.start + CMD_SIZE;
offset += CMD_SIZE;
phy_addr = base_phy_addr + offset;
shared->msg_desc = &iface->msg_buffer_desc;
shared->msg_mem_vir = rpc->virt + offset;
iface->msg_buffer_desc.start =
iface->msg_buffer_desc.wptr =
iface->msg_buffer_desc.rptr = phy_addr;
iface->msg_buffer_desc.end = iface->msg_buffer_desc.start + MSG_SIZE;
offset += MSG_SIZE;
for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) {
iface->ctrl_iface[i] = base_phy_addr + offset;
offset += sizeof(struct windsor_ctrl_iface);
}
for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) {
ctrl = rpc->virt + (iface->ctrl_iface[i] - base_phy_addr);
ctrl->enc_yuv_buffer_desc = base_phy_addr + offset;
hcs->ctrls[i].yuv_desc = rpc->virt + offset;
offset += sizeof(struct vpu_enc_yuv_desc);
ctrl->enc_stream_buffer_desc = base_phy_addr + offset;
hcs->ctrls[i].stream_desc = rpc->virt + offset;
offset += sizeof(struct vpu_rpc_buffer_desc);
ctrl->enc_expert_mode_param = base_phy_addr + offset;
hcs->ctrls[i].expert = rpc->virt + offset;
offset += sizeof(struct vpu_enc_expert_mode_param);
ctrl->enc_param = base_phy_addr + offset;
hcs->ctrls[i].param = rpc->virt + offset;
offset += sizeof(struct vpu_enc_param);
ctrl->enc_mem_pool = base_phy_addr + offset;
hcs->ctrls[i].pool = rpc->virt + offset;
offset += sizeof(struct vpu_enc_mem_pool);
ctrl->enc_encoding_status = base_phy_addr + offset;
hcs->ctrls[i].status = rpc->virt + offset;
offset += sizeof(struct vpu_enc_encoding_status);
ctrl->enc_dsa_status = base_phy_addr + offset;
hcs->ctrls[i].dsa = rpc->virt + offset;
offset += sizeof(struct vpu_enc_dsa_status);
}
rpc->bytesused = offset;
}
void vpu_windsor_set_log_buf(struct vpu_shared_addr *shared, struct vpu_buffer *log)
{
struct windsor_iface *iface = shared->iface;
iface->log_buffer_desc.start =
iface->log_buffer_desc.wptr =
iface->log_buffer_desc.rptr = log->phys - shared->boot_addr;
iface->log_buffer_desc.end = iface->log_buffer_desc.start + log->length;
}
void vpu_windsor_set_system_cfg(struct vpu_shared_addr *shared,
u32 regs_base, void __iomem *regs, u32 core_id)
{
struct windsor_iface *iface = shared->iface;
struct vpu_rpc_system_config *config = &iface->system_config;
vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
}
int vpu_windsor_get_stream_buffer_size(struct vpu_shared_addr *shared)
{
return 0x300000;
}
static struct vpu_pair windsor_cmds[] = {
{VPU_CMD_ID_NOOP, GTB_ENC_CMD_NOOP},
{VPU_CMD_ID_CONFIGURE_CODEC, GTB_ENC_CMD_CONFIGURE_CODEC},
{VPU_CMD_ID_START, GTB_ENC_CMD_STREAM_START},
{VPU_CMD_ID_STOP, GTB_ENC_CMD_STREAM_STOP},
{VPU_CMD_ID_FRAME_ENCODE, GTB_ENC_CMD_FRAME_ENCODE},
{VPU_CMD_ID_SNAPSHOT, GTB_ENC_CMD_SNAPSHOT},
{VPU_CMD_ID_FIRM_RESET, GTB_ENC_CMD_FIRM_RESET},
{VPU_CMD_ID_UPDATE_PARAMETER, GTB_ENC_CMD_PARAMETER_UPD},
{VPU_CMD_ID_DEBUG, GTB_ENC_CMD_FW_STATUS}
};
static struct vpu_pair windsor_msgs[] = {
{VPU_MSG_ID_RESET_DONE, VID_API_ENC_EVENT_RESET_DONE},
{VPU_MSG_ID_START_DONE, VID_API_ENC_EVENT_START_DONE},
{VPU_MSG_ID_STOP_DONE, VID_API_ENC_EVENT_STOP_DONE},
{VPU_MSG_ID_FRAME_INPUT_DONE, VID_API_ENC_EVENT_FRAME_INPUT_DONE},
{VPU_MSG_ID_ENC_DONE, VID_API_ENC_EVENT_FRAME_DONE},
{VPU_MSG_ID_FRAME_RELEASE, VID_API_ENC_EVENT_FRAME_RELEASE},
{VPU_MSG_ID_MEM_REQUEST, VID_API_ENC_EVENT_MEM_REQUEST},
{VPU_MSG_ID_PARAM_UPD_DONE, VID_API_ENC_EVENT_PARA_UPD_DONE},
{VPU_MSG_ID_FIRMWARE_XCPT, VID_API_ENC_EVENT_FIRMWARE_XCPT},
};
int vpu_windsor_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
{
int ret;
ret = vpu_find_dst_by_src(windsor_cmds, ARRAY_SIZE(windsor_cmds), id);
if (ret < 0)
return ret;
pkt->hdr.id = ret;
pkt->hdr.num = 0;
pkt->hdr.index = index;
if (id == VPU_CMD_ID_FRAME_ENCODE) {
s64 timestamp = *(s64 *)data;
struct timespec64 ts = ns_to_timespec64(timestamp);
pkt->hdr.num = 2;
pkt->data[0] = ts.tv_sec;
pkt->data[1] = ts.tv_nsec;
}
return 0;
}
int vpu_windsor_convert_msg_id(u32 id)
{
return vpu_find_src_by_dst(windsor_msgs, ARRAY_SIZE(windsor_msgs), id);
}
static void vpu_windsor_unpack_pic_info(struct vpu_rpc_event *pkt, void *data)
{
struct vpu_enc_pic_info *info = data;
struct windsor_pic_info *windsor = (struct windsor_pic_info *)pkt->data;
struct timespec64 ts = { windsor->tv_s, windsor->tv_ns };
info->frame_id = windsor->frame_id;
switch (windsor->pic_type) {
case MEDIAIP_ENC_PIC_TYPE_I_FRAME:
case MEDIAIP_ENC_PIC_TYPE_IDR_FRAME:
info->pic_type = V4L2_BUF_FLAG_KEYFRAME;
break;
case MEDIAIP_ENC_PIC_TYPE_P_FRAME:
info->pic_type = V4L2_BUF_FLAG_PFRAME;
break;
case MEDIAIP_ENC_PIC_TYPE_B_FRAME:
info->pic_type = V4L2_BUF_FLAG_BFRAME;
break;
default:
break;
}
info->skipped_frame = windsor->skipped_frame;
info->error_flag = windsor->error_flag;
info->psnr = windsor->psnr;
info->frame_size = windsor->frame_size;
info->wptr = get_ptr(windsor->str_buff_wptr);
info->crc = windsor->frame_crc;
info->timestamp = timespec64_to_ns(&ts);
}
static void vpu_windsor_unpack_mem_req(struct vpu_rpc_event *pkt, void *data)
{
struct vpu_pkt_mem_req_data *req_data = data;
req_data->enc_frame_size = pkt->data[0];
req_data->enc_frame_num = pkt->data[1];
req_data->ref_frame_size = pkt->data[2];
req_data->ref_frame_num = pkt->data[3];
req_data->act_buf_size = pkt->data[4];
req_data->act_buf_num = 1;
}
int vpu_windsor_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
{
if (!pkt || !data)
return -EINVAL;
switch (pkt->hdr.id) {
case VID_API_ENC_EVENT_FRAME_DONE:
vpu_windsor_unpack_pic_info(pkt, data);
break;
case VID_API_ENC_EVENT_MEM_REQUEST:
vpu_windsor_unpack_mem_req(pkt, data);
break;
case VID_API_ENC_EVENT_FRAME_RELEASE:
*(u32 *)data = pkt->data[0];
break;
default:
break;
}
return 0;
}
static int vpu_windsor_fill_yuv_frame(struct vpu_shared_addr *shared,
u32 instance,
struct vb2_buffer *vb)
{
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
struct vpu_format *out_fmt;
struct vpu_enc_yuv_desc *desc;
struct vb2_v4l2_buffer *vbuf;
if (instance >= VID_API_NUM_STREAMS)
return -EINVAL;
desc = get_yuv_desc(shared, instance);
out_fmt = vpu_get_format(inst, vb->type);
vbuf = to_vb2_v4l2_buffer(vb);
desc->frame_id = vbuf->sequence;
if (vbuf->flags & V4L2_BUF_FLAG_KEYFRAME)
desc->key_frame = 1;
else
desc->key_frame = 0;
desc->luma_base = vpu_get_vb_phy_addr(vb, 0);
if (vb->num_planes > 1)
desc->chroma_base = vpu_get_vb_phy_addr(vb, 1);
else
desc->chroma_base = desc->luma_base + out_fmt->sizeimage[0];
return 0;
}
int vpu_windsor_input_frame(struct vpu_shared_addr *shared,
struct vpu_inst *inst, struct vb2_buffer *vb)
{
vpu_windsor_fill_yuv_frame(shared, inst->id, vb);
return vpu_session_encode_frame(inst, vb->timestamp);
}
int vpu_windsor_config_memory_resource(struct vpu_shared_addr *shared,
u32 instance,
u32 type,
u32 index,
struct vpu_buffer *buf)
{
struct vpu_enc_mem_pool *pool;
struct vpu_enc_memory_resource *res;
if (instance >= VID_API_NUM_STREAMS)
return -EINVAL;
pool = get_mem_pool(shared, instance);
switch (type) {
case MEM_RES_ENC:
if (index >= ARRAY_SIZE(pool->enc_frames))
return -EINVAL;
res = &pool->enc_frames[index];
break;
case MEM_RES_REF:
if (index >= ARRAY_SIZE(pool->ref_frames))
return -EINVAL;
res = &pool->ref_frames[index];
break;
case MEM_RES_ACT:
if (index)
return -EINVAL;
res = &pool->act_frame;
break;
default:
return -EINVAL;
}
res->phys = buf->phys;
res->virt = buf->phys - shared->boot_addr;
res->size = buf->length;
return 0;
}
int vpu_windsor_config_stream_buffer(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_buffer *buf)
{
struct vpu_rpc_buffer_desc *desc;
struct vpu_enc_expert_mode_param *expert;
desc = get_stream_buf_desc(shared, instance);
expert = get_expert_param(shared, instance);
desc->start = buf->phys;
desc->wptr = buf->phys;
desc->rptr = buf->phys;
desc->end = buf->phys + buf->length;
expert->calib_param.mem_chunk_phys_addr = 0;
expert->calib_param.mem_chunk_virt_addr = 0;
expert->calib_param.mem_chunk_size = 0;
expert->calib_param.cb_base = buf->phys;
expert->calib_param.cb_size = buf->length;
return 0;
}
int vpu_windsor_update_stream_buffer(struct vpu_shared_addr *shared,
u32 instance, u32 ptr, bool write)
{
struct vpu_rpc_buffer_desc *desc;
desc = get_stream_buf_desc(shared, instance);
/*update wptr/rptr after data is written or read*/
mb();
if (write)
desc->wptr = ptr;
else
desc->rptr = ptr;
return 0;
}
int vpu_windsor_get_stream_buffer_desc(struct vpu_shared_addr *shared,
u32 instance, struct vpu_rpc_buffer_desc *desc)
{
struct vpu_rpc_buffer_desc *rpc_desc;
rpc_desc = get_stream_buf_desc(shared, instance);
if (desc) {
desc->wptr = get_ptr(rpc_desc->wptr);
desc->rptr = get_ptr(rpc_desc->rptr);
desc->start = get_ptr(rpc_desc->start);
desc->end = get_ptr(rpc_desc->end);
}
return 0;
}
u32 vpu_windsor_get_version(struct vpu_shared_addr *shared)
{
struct windsor_iface *iface = shared->iface;
return iface->fw_version;
}
static int vpu_windsor_set_frame_rate(struct vpu_enc_expert_mode_param *expert,
struct vpu_encode_params *params)
{
expert->config_param.frame_rate_num = params->frame_rate.numerator;
expert->config_param.frame_rate_den = params->frame_rate.denominator;
return 0;
}
static int vpu_windsor_set_format(struct vpu_enc_param *param, u32 pixelformat)
{
switch (pixelformat) {
case V4L2_PIX_FMT_H264:
param->codec_mode = MEDIAIP_ENC_FMT_H264;
break;
default:
return -EINVAL;
}
return 0;
}
static int vpu_windsor_set_profile(struct vpu_enc_param *param, u32 profile)
{
switch (profile) {
case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
param->profile = MEDIAIP_ENC_PROF_H264_BP;
break;
case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
param->profile = MEDIAIP_ENC_PROF_H264_MP;
break;
case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
param->profile = MEDIAIP_ENC_PROF_H264_HP;
break;
default:
return -EINVAL;
}
return 0;
}
static const u32 h264_level[] = {
[V4L2_MPEG_VIDEO_H264_LEVEL_1_0] = 10,
[V4L2_MPEG_VIDEO_H264_LEVEL_1B] = 14,
[V4L2_MPEG_VIDEO_H264_LEVEL_1_1] = 11,
[V4L2_MPEG_VIDEO_H264_LEVEL_1_2] = 12,
[V4L2_MPEG_VIDEO_H264_LEVEL_1_3] = 13,
[V4L2_MPEG_VIDEO_H264_LEVEL_2_0] = 20,
[V4L2_MPEG_VIDEO_H264_LEVEL_2_1] = 21,
[V4L2_MPEG_VIDEO_H264_LEVEL_2_2] = 22,
[V4L2_MPEG_VIDEO_H264_LEVEL_3_0] = 30,
[V4L2_MPEG_VIDEO_H264_LEVEL_3_1] = 31,
[V4L2_MPEG_VIDEO_H264_LEVEL_3_2] = 32,
[V4L2_MPEG_VIDEO_H264_LEVEL_4_0] = 40,
[V4L2_MPEG_VIDEO_H264_LEVEL_4_1] = 41,
[V4L2_MPEG_VIDEO_H264_LEVEL_4_2] = 42,
[V4L2_MPEG_VIDEO_H264_LEVEL_5_0] = 50,
[V4L2_MPEG_VIDEO_H264_LEVEL_5_1] = 51
};
static int vpu_windsor_set_level(struct vpu_enc_param *param, u32 level)
{
if (level >= ARRAY_SIZE(h264_level))
return -EINVAL;
param->level = h264_level[level];
return 0;
}
static int vpu_windsor_set_size(struct vpu_enc_param *windsor,
struct vpu_encode_params *params)
{
windsor->src_stride = params->src_stride;
windsor->src_width = params->src_width;
windsor->src_height = params->src_height;
windsor->src_offset_x = params->crop.left;
windsor->src_offset_y = params->crop.top;
windsor->src_crop_width = params->crop.width;
windsor->src_crop_height = params->crop.height;
windsor->out_width = params->out_width;
windsor->out_height = params->out_height;
return 0;
}
static int vpu_windsor_set_gop(struct vpu_enc_param *param, u32 gop)
{
param->iframe_interval = gop;
return 0;
}
static int vpu_windsor_set_bframes(struct vpu_enc_param *param, u32 bframes)
{
if (bframes) {
param->low_latency_mode = 0;
param->bframes = bframes;
} else {
param->low_latency_mode = 1;
param->bframes = 0;
}
return 0;
}
static int vpu_windsor_set_bitrate_mode(struct vpu_enc_param *param, u32 rc_enable, u32 mode)
{
if (!rc_enable)
param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP;
else if (mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR)
param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_VBR;
else
param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CBR;
return 0;
}
static u32 vpu_windsor_bitrate(u32 bitrate)
{
return DIV_ROUND_CLOSEST(bitrate, WINDSOR_BITRATE_UNIT);
}
static int vpu_windsor_set_bitrate(struct vpu_enc_param *windsor,
struct vpu_encode_params *params)
{
windsor->target_bitrate = vpu_windsor_bitrate(params->bitrate);
windsor->min_bitrate = vpu_windsor_bitrate(params->bitrate_min);
windsor->max_bitrate = vpu_windsor_bitrate(params->bitrate_max);
return 0;
}
static int vpu_windsor_set_qp(struct vpu_enc_expert_mode_param *expert,
struct vpu_encode_params *params)
{
expert->static_param.rate_control_islice_qp = params->i_frame_qp;
expert->static_param.rate_control_pslice_qp = params->p_frame_qp;
expert->static_param.rate_control_bslice_qp = params->b_frame_qp;
return 0;
}
static int vpu_windsor_set_sar(struct vpu_enc_expert_mode_param *expert,
struct vpu_encode_params *params)
{
expert->config_param.h264_aspect_ratio_present = params->sar.enable;
if (params->sar.idc == V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED)
expert->config_param.aspect_ratio = WINDSOR_H264_EXTENDED_SAR;
else
expert->config_param.aspect_ratio = params->sar.idc;
expert->config_param.h264_aspect_ratio_sar_width = params->sar.width;
expert->config_param.h264_aspect_ratio_sar_height = params->sar.height;
return 0;
}
static int vpu_windsor_set_color(struct vpu_enc_expert_mode_param *expert,
struct vpu_encode_params *params)
{
expert->config_param.h264_video_type_present = 1;
expert->config_param.h264_video_format = 5;
expert->config_param.h264_video_colour_descriptor = 1;
expert->config_param.h264_video_colour_primaries =
vpu_color_cvrt_primaries_v2i(params->color.primaries);
expert->config_param.h264_video_transfer_char =
vpu_color_cvrt_transfers_v2i(params->color.transfer);
expert->config_param.h264_video_matrix_coeff =
vpu_color_cvrt_matrix_v2i(params->color.matrix);
expert->config_param.h264_video_full_range =
vpu_color_cvrt_full_range_v2i(params->color.full_range);
return 0;
}
static int vpu_windsor_update_bitrate(struct vpu_shared_addr *shared,
u32 instance, struct vpu_encode_params *params)
{
struct vpu_enc_param *windsor;
struct vpu_enc_expert_mode_param *expert;
windsor = get_enc_param(shared, instance);
expert = get_expert_param(shared, instance);
if (windsor->bitrate_mode != MEDIAIP_ENC_BITRATE_MODE_CBR)
return 0;
if (!params->rc_enable)
return 0;
if (vpu_windsor_bitrate(params->bitrate) == windsor->target_bitrate)
return 0;
vpu_windsor_set_bitrate(windsor, params);
expert->static_param.rate_control_bitrate = windsor->target_bitrate;
expert->static_param.rate_control_bitrate_min = windsor->min_bitrate;
expert->static_param.rate_control_bitrate_max = windsor->max_bitrate;
return 0;
}
static int vpu_windsor_set_params(struct vpu_shared_addr *shared,
u32 instance, struct vpu_encode_params *params)
{
struct vpu_enc_param *windsor;
int ret;
windsor = get_enc_param(shared, instance);
if (params->input_format != V4L2_PIX_FMT_NV12 &&
params->input_format != V4L2_PIX_FMT_NV12M)
return -EINVAL;
ret = vpu_windsor_set_format(windsor, params->codec_format);
if (ret)
return ret;
vpu_windsor_set_profile(windsor, params->profile);
vpu_windsor_set_level(windsor, params->level);
vpu_windsor_set_size(windsor, params);
vpu_windsor_set_gop(windsor, params->gop_length);
vpu_windsor_set_bframes(windsor, params->bframes);
vpu_windsor_set_bitrate_mode(windsor, params->rc_enable, params->rc_mode);
vpu_windsor_set_bitrate(windsor, params);
windsor->init_slice_qp = params->i_frame_qp;
if (!params->frame_rate.numerator)
return -EINVAL;
windsor->frame_rate = params->frame_rate.denominator / params->frame_rate.numerator;
return 0;
}
static int vpu_windsor_update_params(struct vpu_shared_addr *shared,
u32 instance, struct vpu_encode_params *params)
{
struct vpu_enc_expert_mode_param *expert;
expert = get_expert_param(shared, instance);
vpu_windsor_set_frame_rate(expert, params);
vpu_windsor_set_qp(expert, params);
vpu_windsor_set_sar(expert, params);
vpu_windsor_set_color(expert, params);
vpu_windsor_update_bitrate(shared, instance, params);
/*expert->config_param.iac_sc_threshold = 0;*/
return 0;
}
int vpu_windsor_set_encode_params(struct vpu_shared_addr *shared,
u32 instance, struct vpu_encode_params *params, u32 update)
{
if (!params)
return -EINVAL;
if (!update)
return vpu_windsor_set_params(shared, instance, params);
else
return vpu_windsor_update_params(shared, instance, params);
}
u32 vpu_windsor_get_max_instance_count(struct vpu_shared_addr *shared)
{
struct windsor_iface *iface = shared->iface;
return iface->max_streams;
}
| linux-master | drivers/media/platform/amphion/vpu_windsor.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/rational.h>
#include <linux/time64.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include <linux/videodev2.h>
#include "vpu.h"
#include "vpu_rpc.h"
#include "vpu_defs.h"
#include "vpu_helpers.h"
#include "vpu_v4l2.h"
#include "vpu_cmds.h"
#include "vpu_imx8q.h"
#include "vpu_malone.h"
#define CMD_SIZE 25600
#define MSG_SIZE 25600
#define CODEC_SIZE 0x1000
#define JPEG_SIZE 0x1000
#define SEQ_SIZE 0x1000
#define GOP_SIZE 0x1000
#define PIC_SIZE 0x1000
#define QMETER_SIZE 0x1000
#define DBGLOG_SIZE 0x10000
#define DEBUG_SIZE 0x80000
#define ENG_SIZE 0x1000
#define MALONE_SKIPPED_FRAME_ID 0x555
#define MALONE_ALIGN_MBI 0x800
#define MALONE_DCP_CHUNK_BIT 16
#define MALONE_DCP_SIZE_MAX 0x3000000
#define MALONE_DCP_SIZE_MIN 0x100000
#define MALONE_DCP_FIXED_MB_ALLOC 250
#define CONFIG_SET(val, cfg, pos, mask) \
(*(cfg) |= (((val) << (pos)) & (mask)))
//x means source data , y means destination data
#define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F)
#define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300)
#define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400)
#define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800)
#define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000)
#define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000)
#define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000)
#define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000)
#define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000)
#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000)
#define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000)
#define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000)
#define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000)
#define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000)
#define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000)
#define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000)
#define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000)
#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000)
#define MALONE_DEC_FMT_RV_MASK BIT(21)
enum vpu_malone_stream_input_mode {
INVALID_MODE = 0,
FRAME_LVL,
NON_FRAME_LVL
};
enum vpu_malone_format {
MALONE_FMT_NULL = 0x0,
MALONE_FMT_AVC = 0x1,
MALONE_FMT_MP2 = 0x2,
MALONE_FMT_VC1 = 0x3,
MALONE_FMT_AVS = 0x4,
MALONE_FMT_ASP = 0x5,
MALONE_FMT_JPG = 0x6,
MALONE_FMT_RV = 0x7,
MALONE_FMT_VP6 = 0x8,
MALONE_FMT_SPK = 0x9,
MALONE_FMT_VP8 = 0xA,
MALONE_FMT_HEVC = 0xB,
MALONE_FMT_LAST = MALONE_FMT_HEVC
};
enum {
VID_API_CMD_NULL = 0x00,
VID_API_CMD_PARSE_NEXT_SEQ = 0x01,
VID_API_CMD_PARSE_NEXT_I = 0x02,
VID_API_CMD_PARSE_NEXT_IP = 0x03,
VID_API_CMD_PARSE_NEXT_ANY = 0x04,
VID_API_CMD_DEC_PIC = 0x05,
VID_API_CMD_UPDATE_ES_WR_PTR = 0x06,
VID_API_CMD_UPDATE_ES_RD_PTR = 0x07,
VID_API_CMD_UPDATE_UDATA = 0x08,
VID_API_CMD_GET_FSINFO = 0x09,
VID_API_CMD_SKIP_PIC = 0x0a,
VID_API_CMD_DEC_CHUNK = 0x0b,
VID_API_CMD_START = 0x10,
VID_API_CMD_STOP = 0x11,
VID_API_CMD_ABORT = 0x12,
VID_API_CMD_RST_BUF = 0x13,
VID_API_CMD_FS_RELEASE = 0x15,
VID_API_CMD_MEM_REGION_ATTACH = 0x16,
VID_API_CMD_MEM_REGION_DETACH = 0x17,
VID_API_CMD_MVC_VIEW_SELECT = 0x18,
VID_API_CMD_FS_ALLOC = 0x19,
VID_API_CMD_DBG_GET_STATUS = 0x1C,
VID_API_CMD_DBG_START_LOG = 0x1D,
VID_API_CMD_DBG_STOP_LOG = 0x1E,
VID_API_CMD_DBG_DUMP_LOG = 0x1F,
VID_API_CMD_YUV_READY = 0x20,
VID_API_CMD_TS = 0x21,
VID_API_CMD_FIRM_RESET = 0x40,
VID_API_CMD_SNAPSHOT = 0xAA,
VID_API_CMD_ROLL_SNAPSHOT = 0xAB,
VID_API_CMD_LOCK_SCHEDULER = 0xAC,
VID_API_CMD_UNLOCK_SCHEDULER = 0xAD,
VID_API_CMD_CQ_FIFO_DUMP = 0xAE,
VID_API_CMD_DBG_FIFO_DUMP = 0xAF,
VID_API_CMD_SVC_ILP = 0xBB,
VID_API_CMD_FW_STATUS = 0xF0,
VID_API_CMD_INVALID = 0xFF
};
enum {
VID_API_EVENT_NULL = 0x00,
VID_API_EVENT_RESET_DONE = 0x01,
VID_API_EVENT_SEQ_HDR_FOUND = 0x02,
VID_API_EVENT_PIC_HDR_FOUND = 0x03,
VID_API_EVENT_PIC_DECODED = 0x04,
VID_API_EVENT_FIFO_LOW = 0x05,
VID_API_EVENT_FIFO_HIGH = 0x06,
VID_API_EVENT_FIFO_EMPTY = 0x07,
VID_API_EVENT_FIFO_FULL = 0x08,
VID_API_EVENT_BS_ERROR = 0x09,
VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A,
VID_API_EVENT_RES_CHANGE = 0x0B,
VID_API_EVENT_FIFO_OVF = 0x0C,
VID_API_EVENT_CHUNK_DECODED = 0x0D,
VID_API_EVENT_REQ_FRAME_BUFF = 0x10,
VID_API_EVENT_FRAME_BUFF_RDY = 0x11,
VID_API_EVENT_REL_FRAME_BUFF = 0x12,
VID_API_EVENT_STR_BUF_RST = 0x13,
VID_API_EVENT_RET_PING = 0x14,
VID_API_EVENT_QMETER = 0x15,
VID_API_EVENT_STR_FMT_CHANGE = 0x16,
VID_API_EVENT_FIRMWARE_XCPT = 0x17,
VID_API_EVENT_START_DONE = 0x18,
VID_API_EVENT_STOPPED = 0x19,
VID_API_EVENT_ABORT_DONE = 0x1A,
VID_API_EVENT_FINISHED = 0x1B,
VID_API_EVENT_DBG_STAT_UPDATE = 0x1C,
VID_API_EVENT_DBG_LOG_STARTED = 0x1D,
VID_API_EVENT_DBG_LOG_STOPPED = 0x1E,
VID_API_EVENT_DBG_LOG_UPDATED = 0x1F,
VID_API_EVENT_DBG_MSG_DEC = 0x20,
VID_API_EVENT_DEC_SC_ERR = 0x21,
VID_API_EVENT_CQ_FIFO_DUMP = 0x22,
VID_API_EVENT_DBG_FIFO_DUMP = 0x23,
VID_API_EVENT_DEC_CHECK_RES = 0x24,
VID_API_EVENT_DEC_CFG_INFO = 0x25,
VID_API_EVENT_UNSUPPORTED_STREAM = 0x26,
VID_API_EVENT_PIC_SKIPPED = 0x27,
VID_API_EVENT_STR_SUSPENDED = 0x30,
VID_API_EVENT_SNAPSHOT_DONE = 0x40,
VID_API_EVENT_FW_STATUS = 0xF0,
VID_API_EVENT_INVALID = 0xFF
};
struct vpu_malone_buffer_desc {
struct vpu_rpc_buffer_desc buffer;
u32 low;
u32 high;
};
struct vpu_malone_str_buffer {
u32 wptr;
u32 rptr;
u32 start;
u32 end;
u32 lwm;
};
struct vpu_malone_picth_info {
u32 frame_pitch;
};
struct vpu_malone_table_desc {
u32 array_base;
u32 size;
};
struct vpu_malone_dbglog_desc {
u32 addr;
u32 size;
u32 level;
u32 reserved;
};
struct vpu_malone_frame_buffer {
u32 addr;
u32 size;
};
struct vpu_malone_udata {
u32 base;
u32 total_size;
u32 slot_size;
};
struct vpu_malone_buffer_info {
u32 stream_input_mode;
u32 stream_pic_input_count;
u32 stream_pic_parsed_count;
u32 stream_buffer_threshold;
u32 stream_pic_end_flag;
};
struct vpu_malone_encrypt_info {
u32 rec4key[8];
u32 obfusc;
};
struct malone_iface {
u32 exec_base_addr;
u32 exec_area_size;
struct vpu_malone_buffer_desc cmd_buffer_desc;
struct vpu_malone_buffer_desc msg_buffer_desc;
u32 cmd_int_enable[VID_API_NUM_STREAMS];
struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
u32 stream_config[VID_API_NUM_STREAMS];
struct vpu_malone_table_desc codec_param_tab_desc;
struct vpu_malone_table_desc jpeg_param_tab_desc;
u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
struct vpu_malone_table_desc seq_info_tab_desc;
struct vpu_malone_table_desc pic_info_tab_desc;
struct vpu_malone_table_desc gop_info_tab_desc;
struct vpu_malone_table_desc qmeter_info_tab_desc;
u32 stream_error[VID_API_NUM_STREAMS];
u32 fw_version;
u32 fw_offset;
u32 max_streams;
struct vpu_malone_dbglog_desc dbglog_desc;
struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
struct vpu_malone_buffer_desc debug_buffer_desc;
struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
u32 encrypt_info[VID_API_NUM_STREAMS];
struct vpu_rpc_system_config system_cfg;
u32 api_version;
struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
};
struct malone_jpg_params {
u32 rotation_angle;
u32 horiz_scale_factor;
u32 vert_scale_factor;
u32 rotation_mode;
u32 rgb_mode;
u32 chunk_mode; /* 0 ~ 1 */
u32 last_chunk; /* 0 ~ 1 */
u32 chunk_rows; /* 0 ~ 255 */
u32 num_bytes;
u32 jpg_crop_x;
u32 jpg_crop_y;
u32 jpg_crop_width;
u32 jpg_crop_height;
u32 jpg_mjpeg_mode;
u32 jpg_mjpeg_interlaced;
};
struct malone_codec_params {
u32 disp_imm;
u32 fourcc;
u32 codec_version;
u32 frame_rate;
u32 dbglog_enable;
u32 bsdma_lwm;
u32 bbd_coring;
u32 bbd_s_thr_row;
u32 bbd_p_thr_row;
u32 bbd_s_thr_logo_row;
u32 bbd_p_thr_logo_row;
u32 bbd_s_thr_col;
u32 bbd_p_thr_col;
u32 bbd_chr_thr_row;
u32 bbd_chr_thr_col;
u32 bbd_uv_mid_level;
u32 bbd_excl_win_mb_left;
u32 bbd_excl_win_mb_right;
};
struct malone_padding_scode {
u32 scode_type;
u32 pixelformat;
u32 data[2];
};
struct malone_fmt_mapping {
u32 pixelformat;
enum vpu_malone_format malone_format;
u32 is_disabled;
};
struct malone_scode_t {
struct vpu_inst *inst;
struct vb2_buffer *vb;
u32 wptr;
u32 need_data;
};
struct malone_scode_handler {
u32 pixelformat;
int (*insert_scode_seq)(struct malone_scode_t *scode);
int (*insert_scode_pic)(struct malone_scode_t *scode);
};
struct vpu_dec_ctrl {
struct malone_codec_params *codec_param;
struct malone_jpg_params *jpg;
void *seq_mem;
void *pic_mem;
void *gop_mem;
void *qmeter_mem;
void *dbglog_mem;
struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
u32 buf_addr[VID_API_NUM_STREAMS];
};
u32 vpu_malone_get_data_size(void)
{
return sizeof(struct vpu_dec_ctrl);
}
void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
struct vpu_buffer *rpc, dma_addr_t boot_addr)
{
struct malone_iface *iface;
struct vpu_dec_ctrl *hc;
unsigned long base_phy_addr;
unsigned long phy_addr;
unsigned long offset;
unsigned int i;
if (rpc->phys < boot_addr)
return;
iface = rpc->virt;
base_phy_addr = rpc->phys - boot_addr;
hc = shared->priv;
shared->iface = iface;
shared->boot_addr = boot_addr;
iface->exec_base_addr = base_phy_addr;
iface->exec_area_size = rpc->length;
offset = sizeof(struct malone_iface);
phy_addr = base_phy_addr + offset;
shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
shared->cmd_mem_vir = rpc->virt + offset;
iface->cmd_buffer_desc.buffer.start =
iface->cmd_buffer_desc.buffer.rptr =
iface->cmd_buffer_desc.buffer.wptr = phy_addr;
iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
offset += CMD_SIZE;
phy_addr = base_phy_addr + offset;
shared->msg_desc = &iface->msg_buffer_desc.buffer;
shared->msg_mem_vir = rpc->virt + offset;
iface->msg_buffer_desc.buffer.start =
iface->msg_buffer_desc.buffer.wptr =
iface->msg_buffer_desc.buffer.rptr = phy_addr;
iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
offset += MSG_SIZE;
phy_addr = base_phy_addr + offset;
iface->codec_param_tab_desc.array_base = phy_addr;
hc->codec_param = rpc->virt + offset;
offset += CODEC_SIZE;
phy_addr = base_phy_addr + offset;
iface->jpeg_param_tab_desc.array_base = phy_addr;
hc->jpg = rpc->virt + offset;
offset += JPEG_SIZE;
phy_addr = base_phy_addr + offset;
iface->seq_info_tab_desc.array_base = phy_addr;
hc->seq_mem = rpc->virt + offset;
offset += SEQ_SIZE;
phy_addr = base_phy_addr + offset;
iface->pic_info_tab_desc.array_base = phy_addr;
hc->pic_mem = rpc->virt + offset;
offset += PIC_SIZE;
phy_addr = base_phy_addr + offset;
iface->gop_info_tab_desc.array_base = phy_addr;
hc->gop_mem = rpc->virt + offset;
offset += GOP_SIZE;
phy_addr = base_phy_addr + offset;
iface->qmeter_info_tab_desc.array_base = phy_addr;
hc->qmeter_mem = rpc->virt + offset;
offset += QMETER_SIZE;
phy_addr = base_phy_addr + offset;
iface->dbglog_desc.addr = phy_addr;
iface->dbglog_desc.size = DBGLOG_SIZE;
hc->dbglog_mem = rpc->virt + offset;
offset += DBGLOG_SIZE;
phy_addr = base_phy_addr + offset;
for (i = 0; i < VID_API_NUM_STREAMS; i++) {
iface->eng_access_buff_desc[i].buffer.start =
iface->eng_access_buff_desc[i].buffer.wptr =
iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
iface->eng_access_buff_desc[i].buffer.end =
iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
offset += ENG_SIZE;
phy_addr = base_phy_addr + offset;
}
for (i = 0; i < VID_API_NUM_STREAMS; i++) {
iface->encrypt_info[i] = phy_addr;
offset += sizeof(struct vpu_malone_encrypt_info);
phy_addr = base_phy_addr + offset;
}
rpc->bytesused = offset;
}
void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
struct vpu_buffer *log)
{
struct malone_iface *iface = shared->iface;
iface->debug_buffer_desc.buffer.start =
iface->debug_buffer_desc.buffer.wptr =
iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
}
static u32 get_str_buffer_offset(u32 instance)
{
return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
}
void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
u32 regs_base, void __iomem *regs, u32 core_id)
{
struct malone_iface *iface = shared->iface;
struct vpu_rpc_system_config *config = &iface->system_cfg;
struct vpu_dec_ctrl *hc = shared->priv;
int i;
vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
for (i = 0; i < VID_API_NUM_STREAMS; i++) {
u32 offset = get_str_buffer_offset(i);
hc->buf_addr[i] = regs_base + offset;
hc->str_buf[i] = regs + offset;
}
}
u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
{
struct malone_iface *iface = shared->iface;
vpu_malone_enable_format(V4L2_PIX_FMT_RV30, iface->fw_version & MALONE_DEC_FMT_RV_MASK);
vpu_malone_enable_format(V4L2_PIX_FMT_RV40, iface->fw_version & MALONE_DEC_FMT_RV_MASK);
return iface->fw_version;
}
int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
{
return 0xc00000;
}
int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_buffer *buf)
{
struct malone_iface *iface = shared->iface;
struct vpu_dec_ctrl *hc = shared->priv;
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
writel(buf->phys, &str_buf->start);
writel(buf->phys, &str_buf->rptr);
writel(buf->phys, &str_buf->wptr);
writel(buf->phys + buf->length, &str_buf->end);
writel(0x1, &str_buf->lwm);
iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
return 0;
}
int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_rpc_buffer_desc *desc)
{
struct vpu_dec_ctrl *hc = shared->priv;
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
if (desc) {
desc->wptr = readl(&str_buf->wptr);
desc->rptr = readl(&str_buf->rptr);
desc->start = readl(&str_buf->start);
desc->end = readl(&str_buf->end);
}
return 0;
}
static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
{
/*update wptr after data is written*/
mb();
writel(wptr, &str_buf->wptr);
}
static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
{
/*update rptr after data is read*/
mb();
writel(rptr, &str_buf->rptr);
}
int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
u32 instance, u32 ptr, bool write)
{
struct vpu_dec_ctrl *hc = shared->priv;
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
if (write)
vpu_malone_update_wptr(str_buf, ptr);
else
vpu_malone_update_rptr(str_buf, ptr);
return 0;
}
static struct malone_fmt_mapping fmt_mappings[] = {
{V4L2_PIX_FMT_H264, MALONE_FMT_AVC},
{V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC},
{V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC},
{V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
{V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
{V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2},
{V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP},
{V4L2_PIX_FMT_XVID, MALONE_FMT_ASP},
{V4L2_PIX_FMT_H263, MALONE_FMT_ASP},
{V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG},
{V4L2_PIX_FMT_VP8, MALONE_FMT_VP8},
{V4L2_PIX_FMT_SPK, MALONE_FMT_SPK},
{V4L2_PIX_FMT_RV30, MALONE_FMT_RV},
{V4L2_PIX_FMT_RV40, MALONE_FMT_RV},
};
void vpu_malone_enable_format(u32 pixelformat, int enable)
{
u32 i;
for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
if (pixelformat == fmt_mappings[i].pixelformat) {
fmt_mappings[i].is_disabled = enable ? 0 : 1;
return;
}
}
}
static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
{
u32 i;
for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
if (fmt_mappings[i].is_disabled)
continue;
if (pixelformat == fmt_mappings[i].pixelformat)
return fmt_mappings[i].malone_format;
}
return MALONE_FMT_NULL;
}
bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
{
if (!vpu_imx8q_check_fmt(type, pixelfmt))
return false;
if (pixelfmt == V4L2_PIX_FMT_NV12_8L128 || pixelfmt == V4L2_PIX_FMT_NV12_10BE_8L128 ||
pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
return true;
if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL)
return false;
return true;
}
static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
u32 instance,
enum vpu_malone_format malone_format)
{
struct malone_iface *iface = shared->iface;
u32 *curr_str_cfg = &iface->stream_config[instance];
*curr_str_cfg = 0;
STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
STREAM_CONFIG_PES_SET(0, curr_str_cfg);
STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
}
static int vpu_malone_set_params(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_decode_params *params)
{
struct malone_iface *iface = shared->iface;
struct vpu_dec_ctrl *hc = shared->priv;
enum vpu_malone_format malone_format;
malone_format = vpu_malone_format_remap(params->codec_format);
if (WARN_ON(malone_format == MALONE_FMT_NULL))
return -EINVAL;
iface->udata_buffer[instance].base = params->udata.base;
iface->udata_buffer[instance].slot_size = params->udata.size;
vpu_malone_set_stream_cfg(shared, instance, malone_format);
if (malone_format == MALONE_FMT_JPG) {
//1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
hc->jpg[instance].jpg_mjpeg_mode = 1;
//0: JPGD_MJPEG_PROGRESSIVE
hc->jpg[instance].jpg_mjpeg_interlaced = 0;
}
hc->codec_param[instance].disp_imm = params->display_delay_enable ? 1 : 0;
if (malone_format != MALONE_FMT_AVC)
hc->codec_param[instance].disp_imm = 0;
hc->codec_param[instance].dbglog_enable = 0;
iface->dbglog_desc.level = 0;
if (params->b_non_frame)
iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
else
iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
iface->stream_buff_info[instance].stream_buffer_threshold = 0;
iface->stream_buff_info[instance].stream_pic_input_count = 0;
return 0;
}
static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
{
struct malone_iface *iface = shared->iface;
if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
return true;
return false;
}
static int vpu_malone_update_params(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_decode_params *params)
{
struct malone_iface *iface = shared->iface;
if (params->end_flag)
iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
params->end_flag = 0;
return 0;
}
int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_decode_params *params,
u32 update)
{
if (!params)
return -EINVAL;
if (!update)
return vpu_malone_set_params(shared, instance, params);
else
return vpu_malone_update_params(shared, instance, params);
}
static struct vpu_pair malone_cmds[] = {
{VPU_CMD_ID_NOOP, VID_API_CMD_NULL},
{VPU_CMD_ID_START, VID_API_CMD_START},
{VPU_CMD_ID_STOP, VID_API_CMD_STOP},
{VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
{VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
{VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
{VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
{VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
{VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
{VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
{VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
};
static struct vpu_pair malone_msgs[] = {
{VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
{VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
{VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
{VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
{VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
{VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
{VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
{VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
{VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
{VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
{VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
{VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
{VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
{VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
{VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
{VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
{VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
{VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED},
};
static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
struct vpu_fs_info *fs)
{
const u32 fs_type[] = {
[MEM_RES_FRAME] = 0,
[MEM_RES_MBI] = 1,
[MEM_RES_DCP] = 2,
};
pkt->hdr.num = 7;
pkt->data[0] = fs->id | (fs->tag << 24);
pkt->data[1] = fs->luma_addr;
if (fs->type == MEM_RES_FRAME) {
/*
* if luma_addr equal to chroma_addr,
* means luma(plane[0]) and chromau(plane[1]) used the
* same fd -- usage of NXP codec2. Need to manually
* offset chroma addr.
*/
if (fs->luma_addr == fs->chroma_addr)
fs->chroma_addr = fs->luma_addr + fs->luma_size;
pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
pkt->data[3] = fs->chroma_addr;
pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
pkt->data[5] = fs->bytesperline;
} else {
pkt->data[2] = fs->luma_size;
pkt->data[3] = 0;
pkt->data[4] = 0;
pkt->data[5] = 0;
}
pkt->data[6] = fs_type[fs->type];
}
static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
struct vpu_fs_info *fs)
{
pkt->hdr.num = 1;
pkt->data[0] = fs->id | (fs->tag << 24);
}
static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
struct vpu_ts_info *info)
{
struct timespec64 ts = ns_to_timespec64(info->timestamp);
pkt->hdr.num = 3;
pkt->data[0] = ts.tv_sec;
pkt->data[1] = ts.tv_nsec;
pkt->data[2] = info->size;
}
int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
{
int ret;
ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
if (ret < 0)
return ret;
pkt->hdr.id = ret;
pkt->hdr.num = 0;
pkt->hdr.index = index;
switch (id) {
case VPU_CMD_ID_FS_ALLOC:
vpu_malone_pack_fs_alloc(pkt, data);
break;
case VPU_CMD_ID_FS_RELEASE:
vpu_malone_pack_fs_release(pkt, data);
break;
case VPU_CMD_ID_TIMESTAMP:
vpu_malone_pack_timestamp(pkt, data);
break;
}
pkt->hdr.index = index;
return 0;
}
int vpu_malone_convert_msg_id(u32 id)
{
return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
}
static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
{
u32 interlaced = info->progressive ? 0 : 1;
info->bytesperline[0] = 0;
info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt,
info->decoded_width,
info->decoded_height,
0,
info->stride,
interlaced,
&info->bytesperline[0]);
info->bytesperline[1] = 0;
info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt,
info->decoded_width,
info->decoded_height,
1,
info->stride,
interlaced,
&info->bytesperline[1]);
}
static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
{
u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
vpu_malone_fill_planes(info);
info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
info->dcp_size = MALONE_DCP_SIZE_MAX;
if (chunks) {
u32 mb_num;
u32 mb_w;
u32 mb_h;
mb_w = DIV_ROUND_UP(info->decoded_width, 16);
mb_h = DIV_ROUND_UP(info->decoded_height, 16);
mb_num = mb_w * mb_h;
info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
info->dcp_size = clamp_t(u32, info->dcp_size,
MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
}
}
static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
struct vpu_dec_codec_info *info)
{
info->num_ref_frms = pkt->data[0];
info->num_dpb_frms = pkt->data[1];
info->num_dfe_area = pkt->data[2];
info->progressive = pkt->data[3];
info->width = pkt->data[5];
info->height = pkt->data[4];
info->decoded_width = pkt->data[12];
info->decoded_height = pkt->data[11];
info->frame_rate.numerator = 1000;
info->frame_rate.denominator = pkt->data[8];
info->dsp_asp_ratio = pkt->data[9];
info->level_idc = pkt->data[10];
info->bit_depth_luma = pkt->data[13];
info->bit_depth_chroma = pkt->data[14];
info->chroma_fmt = pkt->data[15];
info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
info->vui_present = pkt->data[20];
info->mvc_num_views = pkt->data[21];
info->offset_x = pkt->data[23];
info->offset_y = pkt->data[25];
info->tag = pkt->data[27];
if (info->bit_depth_luma > 8)
info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
else
info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
if (info->frame_rate.numerator && info->frame_rate.denominator) {
unsigned long n, d;
rational_best_approximation(info->frame_rate.numerator,
info->frame_rate.denominator,
info->frame_rate.numerator,
info->frame_rate.denominator,
&n, &d);
info->frame_rate.numerator = n;
info->frame_rate.denominator = d;
}
vpu_malone_init_seq_hdr(info);
}
static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
struct vpu_dec_pic_info *info)
{
info->id = pkt->data[7];
info->luma = pkt->data[0];
info->start = pkt->data[10];
info->end = pkt->data[12];
info->pic_size = pkt->data[11];
info->stride = pkt->data[5];
info->consumed_count = pkt->data[13];
if (info->id == MALONE_SKIPPED_FRAME_ID)
info->skipped = 1;
else
info->skipped = 0;
}
static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
struct vpu_fs_info *info)
{
info->type = pkt->data[1];
}
static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
struct vpu_fs_info *info)
{
info->id = pkt->data[0];
info->type = pkt->data[1];
info->not_displayed = pkt->data[2];
}
static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
struct vpu_dec_pic_info *info)
{
struct timespec64 ts = { pkt->data[9], pkt->data[10] };
info->id = pkt->data[0];
info->luma = pkt->data[1];
info->stride = pkt->data[3];
if (info->id == MALONE_SKIPPED_FRAME_ID)
info->skipped = 1;
else
info->skipped = 0;
info->timestamp = timespec64_to_ns(&ts);
}
int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
{
if (!pkt || !data)
return -EINVAL;
switch (pkt->hdr.id) {
case VID_API_EVENT_SEQ_HDR_FOUND:
vpu_malone_unpack_seq_hdr(pkt, data);
break;
case VID_API_EVENT_PIC_DECODED:
vpu_malone_unpack_pic_info(pkt, data);
break;
case VID_API_EVENT_REQ_FRAME_BUFF:
vpu_malone_unpack_req_frame(pkt, data);
break;
case VID_API_EVENT_REL_FRAME_BUFF:
vpu_malone_unpack_rel_frame(pkt, data);
break;
case VID_API_EVENT_FRAME_BUFF_RDY:
vpu_malone_unpack_buff_rdy(pkt, data);
break;
}
return 0;
}
static const struct malone_padding_scode padding_scodes[] = {
{SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}},
{SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}},
{SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}},
{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}},
{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}},
};
static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
{
const struct malone_padding_scode *s;
int i;
for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
s = &padding_scodes[i];
if (s->scode_type == type && s->pixelformat == fmt)
return s;
}
if (type != SCODE_PADDING_BUFFLUSH)
return &padding_scode_dft;
return NULL;
}
static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
struct vpu_malone_str_buffer __iomem *str_buf,
u32 pixelformat, u32 scode_type)
{
u32 wptr;
int size;
int total_size = 0;
const struct malone_padding_scode *ps;
const u32 padding_size = 4096;
int ret;
ps = get_padding_scode(scode_type, pixelformat);
if (!ps)
return -EINVAL;
wptr = readl(&str_buf->wptr);
if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
return -EINVAL;
if (wptr == stream_buffer->phys + stream_buffer->length)
wptr = stream_buffer->phys;
size = ALIGN(wptr, 4) - wptr;
if (size)
vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
total_size += size;
size = sizeof(ps->data);
ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
if (ret < 0)
return -EINVAL;
total_size += size;
size = padding_size - sizeof(ps->data);
vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
total_size += size;
vpu_malone_update_wptr(str_buf, wptr);
return total_size;
}
int vpu_malone_add_scode(struct vpu_shared_addr *shared,
u32 instance,
struct vpu_buffer *stream_buffer,
u32 pixelformat,
u32 scode_type)
{
struct vpu_dec_ctrl *hc = shared->priv;
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
int ret = -EINVAL;
switch (scode_type) {
case SCODE_PADDING_EOS:
case SCODE_PADDING_ABORT:
case SCODE_PADDING_BUFFLUSH:
ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
break;
default:
break;
}
return ret;
}
#define MALONE_PAYLOAD_HEADER_SIZE 16
#define MALONE_CODEC_VERSION_ID 0x1
#define MALONE_CODEC_ID_VC1_SIMPLE 0x10
#define MALONE_CODEC_ID_VC1_MAIN 0x11
#define MALONE_CODEC_ID_ARV8 0x28
#define MALONE_CODEC_ID_ARV9 0x29
#define MALONE_CODEC_ID_VP6 0x36
#define MALONE_CODEC_ID_VP8 0x36
#define MALONE_CODEC_ID_DIVX3 0x38
#define MALONE_CODEC_ID_SPK 0x39
#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32
#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8
#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85
#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5
#define MALONE_VC1_RCV_NUM_FRAMES 0xFF
#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4
#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20
#define MALONE_VC1_RCV_PIC_HEADER_LEN 4
#define MALONE_VC1_NAL_HEADER_LEN 4
#define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000)
static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
u32 buffer_size, u32 width, u32 height)
{
unsigned int payload_size;
/* payload_size = buffer_size + itself_size(16) - start_code(4) */
payload_size = buffer_size + 12;
dst[0] = 0x00;
dst[1] = 0x00;
dst[2] = 0x01;
dst[3] = scd_type;
/* length */
dst[4] = ((payload_size >> 16) & 0xff);
dst[5] = ((payload_size >> 8) & 0xff);
dst[6] = 0x4e;
dst[7] = ((payload_size >> 0) & 0xff);
/* Codec ID and Version */
dst[8] = codec_id;
dst[9] = MALONE_CODEC_VERSION_ID;
/* width */
dst[10] = ((width >> 8) & 0xff);
dst[11] = ((width >> 0) & 0xff);
dst[12] = 0x58;
/* height */
dst[13] = ((height >> 8) & 0xff);
dst[14] = ((height >> 0) & 0xff);
dst[15] = 0x50;
}
static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
{
/* 0-3byte signature "DKIF" */
dst[0] = 0x44;
dst[1] = 0x4b;
dst[2] = 0x49;
dst[3] = 0x46;
/* 4-5byte version: should be 0*/
dst[4] = 0x00;
dst[5] = 0x00;
/* 6-7 length of Header */
dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
/* 8-11 VP8 fourcc */
dst[8] = 0x56;
dst[9] = 0x50;
dst[10] = 0x38;
dst[11] = 0x30;
/* 12-13 width in pixels */
dst[12] = width;
dst[13] = width >> 8;
/* 14-15 height in pixels */
dst[14] = height;
dst[15] = height >> 8;
/* 16-19 frame rate */
dst[16] = 0xe8;
dst[17] = 0x03;
dst[18] = 0x00;
dst[19] = 0x00;
/* 20-23 time scale */
dst[20] = 0x01;
dst[21] = 0x00;
dst[22] = 0x00;
dst[23] = 0x00;
/* 24-27 number frames */
dst[24] = 0xdf;
dst[25] = 0xf9;
dst[26] = 0x09;
dst[27] = 0x00;
/* 28-31 reserved */
}
static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
{
/*
* firmware just parse 64-bit timestamp(8 bytes).
* As not transfer timestamp to firmware, use default value(ZERO).
* No need to do anything here
*/
}
static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
{
u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
/* 0-2 Number of frames, used default value 0xFF */
dst[0] = frames;
dst[1] = frames >> 8;
dst[2] = frames >> 16;
/* 3 RCV version, used V1 */
dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
/* 4-7 extension data size */
dst[4] = ext_data_size;
dst[5] = ext_data_size >> 8;
dst[6] = ext_data_size >> 16;
dst[7] = ext_data_size >> 24;
/* 8-11 extension data */
dst[8] = src[0];
dst[9] = src[1];
dst[10] = src[2];
dst[11] = src[3];
/* height */
dst[12] = height;
dst[13] = (height >> 8) & 0xff;
dst[14] = (height >> 16) & 0xff;
dst[15] = (height >> 24) & 0xff;
/* width */
dst[16] = width;
dst[17] = (width >> 8) & 0xff;
dst[18] = (width >> 16) & 0xff;
dst[19] = (width >> 24) & 0xff;
}
static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
{
dst[0] = buffer_size;
dst[1] = buffer_size >> 8;
dst[2] = buffer_size >> 16;
dst[3] = buffer_size >> 24;
}
static void create_vc1_nal_pichdr(u8 *dst)
{
/* need insert nal header: special ID */
dst[0] = 0x0;
dst[1] = 0x0;
dst[2] = 0x01;
dst[3] = 0x0D;
}
static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
{
u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
int ret;
set_payload_hdr(hdr,
SCODE_SEQUENCE,
codec_id,
ext_size,
scode->inst->out_format.width,
scode->inst->out_format.height);
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(hdr),
hdr);
if (ret < 0)
return ret;
return sizeof(hdr);
}
static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
{
u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
int ret;
set_payload_hdr(hdr,
SCODE_PICTURE,
codec_id,
ext_size + vb2_get_plane_payload(scode->vb, 0),
scode->inst->out_format.width,
scode->inst->out_format.height);
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(hdr),
hdr);
if (ret < 0)
return ret;
return sizeof(hdr);
}
static int vpu_malone_insert_scode_vc1_g_seq(struct malone_scode_t *scode)
{
if (!scode->inst->total_input_count)
return 0;
if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb)))
scode->need_data = 0;
return 0;
}
static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
{
struct vb2_v4l2_buffer *vbuf;
u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
u32 *data = NULL;
int ret;
vbuf = to_vb2_v4l2_buffer(scode->vb);
data = vb2_plane_vaddr(scode->vb, 0);
if (scode->inst->total_input_count == 0 || vpu_vb_is_codecconfig(vbuf))
return 0;
if (MALONE_VC1_CONTAIN_NAL(*data))
return 0;
create_vc1_nal_pichdr(nal_hdr);
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(nal_hdr),
nal_hdr);
if (ret < 0)
return ret;
return sizeof(nal_hdr);
}
static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
{
int ret;
int size = 0;
u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb)))
scode->need_data = 0;
if (scode->inst->total_input_count)
return 0;
scode->need_data = 0;
ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));
if (ret < 0)
return ret;
size = ret;
set_vc1_rcv_seqhdr(rcv_seqhdr,
vb2_plane_vaddr(scode->vb, 0),
scode->inst->out_format.width,
scode->inst->out_format.height);
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(rcv_seqhdr),
rcv_seqhdr);
if (ret < 0)
return ret;
size += sizeof(rcv_seqhdr);
return size;
}
static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
{
int ret;
int size = 0;
u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
sizeof(rcv_pichdr));
if (ret < 0)
return ret;
size = ret;
set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(rcv_pichdr),
rcv_pichdr);
if (ret < 0)
return ret;
size += sizeof(rcv_pichdr);
return size;
}
static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
{
int ret;
int size = 0;
u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
if (ret < 0)
return ret;
size = ret;
set_vp8_ivf_seqhdr(ivf_hdr,
scode->inst->out_format.width,
scode->inst->out_format.height);
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(ivf_hdr),
ivf_hdr);
if (ret < 0)
return ret;
size += sizeof(ivf_hdr);
return size;
}
static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
{
int ret;
int size = 0;
u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
if (ret < 0)
return ret;
size = ret;
set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
&scode->wptr,
sizeof(ivf_hdr),
ivf_hdr);
if (ret < 0)
return ret;
size += sizeof(ivf_hdr);
return size;
}
static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode)
{
return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, 0);
}
static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode)
{
return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, 0);
}
static const struct malone_scode_handler scode_handlers[] = {
{
/* fix me, need to swap return operation after gstreamer swap */
.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
.insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
.insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
},
{
.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
.insert_scode_seq = vpu_malone_insert_scode_vc1_g_seq,
.insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
},
{
.pixelformat = V4L2_PIX_FMT_VP8,
.insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
.insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
},
{
.pixelformat = V4L2_PIX_FMT_SPK,
.insert_scode_seq = vpu_malone_insert_scode_spk_seq,
.insert_scode_pic = vpu_malone_insert_scode_spk_pic,
},
};
static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
{
int i;
for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
if (scode_handlers[i].pixelformat == pixelformat)
return &scode_handlers[i];
}
return NULL;
}
static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
{
const struct malone_scode_handler *handler;
int ret = 0;
if (!scode || !scode->inst || !scode->vb)
return 0;
scode->need_data = 1;
handler = get_scode_handler(scode->inst->out_format.pixfmt);
if (!handler)
return 0;
switch (type) {
case SCODE_SEQUENCE:
if (handler->insert_scode_seq)
ret = handler->insert_scode_seq(scode);
break;
case SCODE_PICTURE:
if (handler->insert_scode_pic)
ret = handler->insert_scode_pic(scode);
break;
default:
break;
}
return ret;
}
static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
struct vpu_inst *inst, struct vb2_buffer *vb,
u32 disp_imm)
{
struct malone_scode_t scode;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
u32 wptr = readl(&str_buf->wptr);
int size = 0;
int ret = 0;
/*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
scode.inst = inst;
scode.vb = vb;
scode.wptr = wptr;
scode.need_data = 1;
if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
if (ret < 0)
return -ENOMEM;
size += ret;
wptr = scode.wptr;
if (!scode.need_data) {
vpu_malone_update_wptr(str_buf, wptr);
return size;
}
ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
if (ret < 0)
return -ENOMEM;
size += ret;
wptr = scode.wptr;
ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
&wptr,
vb2_get_plane_payload(vb, 0),
vb2_plane_vaddr(vb, 0));
if (ret < 0)
return -ENOMEM;
size += vb2_get_plane_payload(vb, 0);
vpu_malone_update_wptr(str_buf, wptr);
if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) {
ret = vpu_malone_add_scode(inst->core->iface,
inst->id,
&inst->stream_buffer,
inst->out_format.pixfmt,
SCODE_PADDING_BUFFLUSH);
if (ret < 0)
return ret;
size += ret;
}
return size;
}
static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
struct vpu_inst *inst, struct vb2_buffer *vb)
{
u32 wptr = readl(&str_buf->wptr);
int ret = 0;
ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
&wptr,
vb2_get_plane_payload(vb, 0),
vb2_plane_vaddr(vb, 0));
if (ret < 0)
return -ENOMEM;
vpu_malone_update_wptr(str_buf, wptr);
return ret;
}
static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
{
struct vpu_ts_info info;
memset(&info, 0, sizeof(info));
info.timestamp = timestamp;
info.size = size;
return vpu_session_fill_timestamp(inst, &info);
}
int vpu_malone_input_frame(struct vpu_shared_addr *shared,
struct vpu_inst *inst, struct vb2_buffer *vb)
{
struct vpu_dec_ctrl *hc = shared->priv;
struct vb2_v4l2_buffer *vbuf;
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
u32 disp_imm = hc->codec_param[inst->id].disp_imm;
u32 size;
int ret;
if (vpu_malone_is_non_frame_mode(shared, inst->id))
ret = vpu_malone_input_stream_data(str_buf, inst, vb);
else
ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
if (ret < 0)
return ret;
size = ret;
/*
* if buffer only contain codec data, and the timestamp is invalid,
* don't put the invalid timestamp to resync
* merge the data to next frame
*/
vbuf = to_vb2_v4l2_buffer(vb);
if (vpu_vb_is_codecconfig(vbuf)) {
inst->extra_size += size;
return 0;
}
if (inst->extra_size) {
size += inst->extra_size;
inst->extra_size = 0;
}
ret = vpu_malone_input_ts(inst, vb->timestamp, size);
if (ret)
return ret;
return 0;
}
static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
{
struct malone_iface *iface = shared->iface;
struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
u32 size = desc->end - desc->start;
u32 rptr = desc->rptr;
u32 wptr = desc->wptr;
u32 used;
if (!size)
return true;
used = (wptr + size - rptr) % size;
if (used < (size / 2))
return true;
return false;
}
bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
{
u32 cnt = 0;
while (!vpu_malone_check_ready(shared, instance)) {
if (cnt > 30)
return false;
mdelay(1);
cnt++;
}
return true;
}
int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
{
if (!vpu_malone_is_ready(shared, instance))
return -EINVAL;
return 0;
}
int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
{
struct malone_iface *iface = shared->iface;
struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
desc->wptr++;
if (desc->wptr == desc->end)
desc->wptr = desc->start;
return 0;
}
int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
{
struct malone_iface *iface = shared->iface;
struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
desc->wptr = desc->rptr;
if (desc->wptr == desc->end)
desc->wptr = desc->start;
return 0;
}
u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
{
struct malone_iface *iface = shared->iface;
return iface->max_streams;
}
| linux-master | drivers/media/platform/amphion/vpu_malone.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include "vpu.h"
#include "vpu_core.h"
#include "vpu_imx8q.h"
#include "vpu_rpc.h"
#define IMX8Q_CSR_CM0Px_ADDR_OFFSET 0x00000000
#define IMX8Q_CSR_CM0Px_CPUWAIT 0x00000004
#ifdef CONFIG_IMX_SCU
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/svc/misc.h>
#define VPU_DISABLE_BITS 0x7
#define VPU_IMX_DECODER_FUSE_OFFSET 14
#define VPU_ENCODER_MASK 0x1
#define VPU_DECODER_MASK 0x3UL
#define VPU_DECODER_H264_MASK 0x2UL
#define VPU_DECODER_HEVC_MASK 0x1UL
static u32 imx8q_fuse;
struct vpu_sc_msg_misc {
struct imx_sc_rpc_msg hdr;
u32 word;
} __packed;
#endif
int vpu_imx8q_setup_dec(struct vpu_dev *vpu)
{
const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;
vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f);
vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff);
return 0;
}
int vpu_imx8q_setup_enc(struct vpu_dev *vpu)
{
return 0;
}
int vpu_imx8q_setup(struct vpu_dev *vpu)
{
const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;
vpu_readl(vpu, offset + 0x108);
vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1);
vpu_writel(vpu, offset + 0x190, 0xffffffff);
vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff);
vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE);
vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7);
vpu_writel(vpu, XMEM_CONTROL, 0x102);
vpu_readl(vpu, offset + 0x108);
return 0;
}
static int vpu_imx8q_reset_enc(struct vpu_dev *vpu)
{
return 0;
}
static int vpu_imx8q_reset_dec(struct vpu_dev *vpu)
{
const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;
vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff);
return 0;
}
int vpu_imx8q_reset(struct vpu_dev *vpu)
{
const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;
vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7);
vpu_imx8q_reset_enc(vpu);
vpu_imx8q_reset_dec(vpu);
return 0;
}
int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id)
{
if (!config)
return -EINVAL;
switch (core_id) {
case 0:
config->malone_base_addr[0] = regs + DEC_MFD_XREG_SLV_BASE;
config->num_malones = 1;
config->num_windsors = 0;
break;
case 1:
config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_0_BASE;
config->num_windsors = 1;
config->num_malones = 0;
break;
case 2:
config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_1_BASE;
config->num_windsors = 1;
config->num_malones = 0;
break;
default:
return -EINVAL;
}
if (config->num_windsors) {
config->windsor_irq_pin[0x0][0x0] = WINDSOR_PAL_IRQ_PIN_L;
config->windsor_irq_pin[0x0][0x1] = WINDSOR_PAL_IRQ_PIN_H;
}
config->malone_base_addr[0x1] = 0x0;
config->hif_offset[0x0] = MFD_HIF;
config->hif_offset[0x1] = 0x0;
config->dpv_base_addr = 0x0;
config->dpv_irq_pin = 0x0;
config->pixif_base_addr = regs + DEC_MFD_XREG_SLV_BASE + MFD_PIX_IF;
config->cache_base_addr[0] = regs + MC_CACHE_0_BASE;
config->cache_base_addr[1] = regs + MC_CACHE_1_BASE;
return 0;
}
int vpu_imx8q_boot_core(struct vpu_core *core)
{
csr_writel(core, IMX8Q_CSR_CM0Px_ADDR_OFFSET, core->fw.phys);
csr_writel(core, IMX8Q_CSR_CM0Px_CPUWAIT, 0);
return 0;
}
int vpu_imx8q_get_power_state(struct vpu_core *core)
{
if (csr_readl(core, IMX8Q_CSR_CM0Px_CPUWAIT) == 1)
return 0;
return 1;
}
int vpu_imx8q_on_firmware_loaded(struct vpu_core *core)
{
u8 *p;
p = core->fw.virt;
p[16] = core->vpu->res->plat_type;
p[17] = core->id;
p[18] = 1;
return 0;
}
int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size)
{
const struct vpu_rpc_region_t imx8q_regions[] = {
{0x00000000, 0x08000000, VPU_CORE_MEMORY_CACHED},
{0x08000000, 0x10000000, VPU_CORE_MEMORY_UNCACHED},
{0x10000000, 0x20000000, VPU_CORE_MEMORY_CACHED},
{0x20000000, 0x40000000, VPU_CORE_MEMORY_UNCACHED}
};
int i;
if (addr < base)
return VPU_CORE_MEMORY_INVALID;
addr -= base;
for (i = 0; i < ARRAY_SIZE(imx8q_regions); i++) {
const struct vpu_rpc_region_t *region = &imx8q_regions[i];
if (addr >= region->start && addr + size < region->end)
return region->type;
}
return VPU_CORE_MEMORY_INVALID;
}
#ifdef CONFIG_IMX_SCU
static u32 vpu_imx8q_get_fuse(void)
{
static u32 fuse_got;
struct imx_sc_ipc *ipc;
struct vpu_sc_msg_misc msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
if (fuse_got)
return imx8q_fuse;
ret = imx_scu_get_handle(&ipc);
if (ret) {
pr_err("error: get sct handle fail: %d\n", ret);
return 0;
}
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_MISC;
hdr->func = IMX_SC_MISC_FUNC_OTP_FUSE_READ;
hdr->size = 2;
msg.word = VPU_DISABLE_BITS;
ret = imx_scu_call_rpc(ipc, &msg, true);
if (ret)
return 0;
imx8q_fuse = msg.word;
fuse_got = 1;
return imx8q_fuse;
}
bool vpu_imx8q_check_codec(enum vpu_core_type type)
{
u32 fuse = vpu_imx8q_get_fuse();
if (type == VPU_CORE_TYPE_ENC) {
if (fuse & VPU_ENCODER_MASK)
return false;
} else if (type == VPU_CORE_TYPE_DEC) {
fuse >>= VPU_IMX_DECODER_FUSE_OFFSET;
fuse &= VPU_DECODER_MASK;
if (fuse == VPU_DECODER_MASK)
return false;
}
return true;
}
bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt)
{
u32 fuse = vpu_imx8q_get_fuse();
if (type == VPU_CORE_TYPE_DEC) {
fuse >>= VPU_IMX_DECODER_FUSE_OFFSET;
fuse &= VPU_DECODER_MASK;
if (fuse == VPU_DECODER_HEVC_MASK && pixelfmt == V4L2_PIX_FMT_HEVC)
return false;
if (fuse == VPU_DECODER_H264_MASK && pixelfmt == V4L2_PIX_FMT_H264)
return false;
if (fuse == VPU_DECODER_MASK)
return false;
}
return true;
}
#else
bool vpu_imx8q_check_codec(enum vpu_core_type type)
{
return true;
}
bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt)
{
return true;
}
#endif
| linux-master | drivers/media/platform/amphion/vpu_imx8q.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pm_runtime.h>
#include <media/v4l2-device.h>
#include <linux/debugfs.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_core.h"
#include "vpu_helpers.h"
#include "vpu_cmds.h"
#include "vpu_rpc.h"
#include "vpu_v4l2.h"
struct print_buf_desc {
u32 start_h_phy;
u32 start_h_vir;
u32 start_m;
u32 bytes;
u32 read;
u32 write;
char buffer[];
};
static char *vb2_stat_name[] = {
[VB2_BUF_STATE_DEQUEUED] = "dequeued",
[VB2_BUF_STATE_IN_REQUEST] = "in_request",
[VB2_BUF_STATE_PREPARING] = "preparing",
[VB2_BUF_STATE_QUEUED] = "queued",
[VB2_BUF_STATE_ACTIVE] = "active",
[VB2_BUF_STATE_DONE] = "done",
[VB2_BUF_STATE_ERROR] = "error",
};
static char *vpu_stat_name[] = {
[VPU_BUF_STATE_IDLE] = "idle",
[VPU_BUF_STATE_INUSE] = "inuse",
[VPU_BUF_STATE_DECODED] = "decoded",
[VPU_BUF_STATE_READY] = "ready",
[VPU_BUF_STATE_SKIP] = "skip",
[VPU_BUF_STATE_ERROR] = "error",
};
static inline const char *to_vpu_stat_name(int state)
{
if (state <= VPU_BUF_STATE_ERROR)
return vpu_stat_name[state];
return "unknown";
}
static int vpu_dbg_instance(struct seq_file *s, void *data)
{
struct vpu_inst *inst = s->private;
char str[128];
int num;
struct vb2_queue *vq;
int i;
if (!inst->fh.m2m_ctx)
return 0;
num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(inst->type));
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "tgig = %d,pid = %d\n", inst->tgid, inst->pid);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "state = %s\n", vpu_codec_state_name(inst->state));
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str),
"min_buffer_out = %d, min_buffer_cap = %d\n",
inst->min_buffer_out, inst->min_buffer_cap);
if (seq_write(s, str, num))
return 0;
vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
num = scnprintf(str, sizeof(str),
"output (%2d, %2d): fmt = %c%c%c%c %d x %d, %d;",
vb2_is_streaming(vq),
vq->num_buffers,
inst->out_format.pixfmt,
inst->out_format.pixfmt >> 8,
inst->out_format.pixfmt >> 16,
inst->out_format.pixfmt >> 24,
inst->out_format.width,
inst->out_format.height,
vq->last_buffer_dequeued);
if (seq_write(s, str, num))
return 0;
for (i = 0; i < inst->out_format.mem_planes; i++) {
num = scnprintf(str, sizeof(str), " %d(%d)",
vpu_get_fmt_plane_size(&inst->out_format, i),
inst->out_format.bytesperline[i]);
if (seq_write(s, str, num))
return 0;
}
if (seq_write(s, "\n", 1))
return 0;
vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
num = scnprintf(str, sizeof(str),
"capture(%2d, %2d): fmt = %c%c%c%c %d x %d, %d;",
vb2_is_streaming(vq),
vq->num_buffers,
inst->cap_format.pixfmt,
inst->cap_format.pixfmt >> 8,
inst->cap_format.pixfmt >> 16,
inst->cap_format.pixfmt >> 24,
inst->cap_format.width,
inst->cap_format.height,
vq->last_buffer_dequeued);
if (seq_write(s, str, num))
return 0;
for (i = 0; i < inst->cap_format.mem_planes; i++) {
num = scnprintf(str, sizeof(str), " %d(%d)",
vpu_get_fmt_plane_size(&inst->cap_format, i),
inst->cap_format.bytesperline[i]);
if (seq_write(s, str, num))
return 0;
}
if (seq_write(s, "\n", 1))
return 0;
num = scnprintf(str, sizeof(str), "crop: (%d, %d) %d x %d\n",
inst->crop.left,
inst->crop.top,
inst->crop.width,
inst->crop.height);
if (seq_write(s, str, num))
return 0;
vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
for (i = 0; i < vq->num_buffers; i++) {
struct vb2_buffer *vb = vq->bufs[i];
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
if (vb->state == VB2_BUF_STATE_DEQUEUED)
continue;
num = scnprintf(str, sizeof(str),
"output [%2d] state = %10s, %8s\n",
i, vb2_stat_name[vb->state],
to_vpu_stat_name(vpu_get_buffer_state(vbuf)));
if (seq_write(s, str, num))
return 0;
}
vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
for (i = 0; i < vq->num_buffers; i++) {
struct vb2_buffer *vb = vq->bufs[i];
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
if (vb->state == VB2_BUF_STATE_DEQUEUED)
continue;
num = scnprintf(str, sizeof(str),
"capture[%2d] state = %10s, %8s\n",
i, vb2_stat_name[vb->state],
to_vpu_stat_name(vpu_get_buffer_state(vbuf)));
if (seq_write(s, str, num))
return 0;
}
num = scnprintf(str, sizeof(str), "sequence = %d\n", inst->sequence);
if (seq_write(s, str, num))
return 0;
if (inst->use_stream_buffer) {
num = scnprintf(str, sizeof(str), "stream_buffer = %d / %d, <%pad, 0x%x>\n",
vpu_helper_get_used_space(inst),
inst->stream_buffer.length,
&inst->stream_buffer.phys,
inst->stream_buffer.length);
if (seq_write(s, str, num))
return 0;
}
num = scnprintf(str, sizeof(str), "kfifo len = 0x%x\n", kfifo_len(&inst->msg_fifo));
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "flow :\n");
if (seq_write(s, str, num))
return 0;
mutex_lock(&inst->core->cmd_lock);
for (i = 0; i < ARRAY_SIZE(inst->flows); i++) {
u32 idx = (inst->flow_idx + i) % (ARRAY_SIZE(inst->flows));
if (!inst->flows[idx])
continue;
num = scnprintf(str, sizeof(str), "\t[%s] %s\n",
inst->flows[idx] >= VPU_MSG_ID_NOOP ? "M" : "C",
vpu_id_name(inst->flows[idx]));
if (seq_write(s, str, num)) {
mutex_unlock(&inst->core->cmd_lock);
return 0;
}
}
mutex_unlock(&inst->core->cmd_lock);
i = 0;
while (true) {
num = call_vop(inst, get_debug_info, str, sizeof(str), i++);
if (num <= 0)
break;
if (seq_write(s, str, num))
return 0;
}
return 0;
}
static int vpu_dbg_core(struct seq_file *s, void *data)
{
struct vpu_core *core = s->private;
struct vpu_shared_addr *iface = core->iface;
char str[128];
int num;
num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(core->type));
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "boot_region = <%pad, 0x%x>\n",
&core->fw.phys, core->fw.length);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "rpc_region = <%pad, 0x%x> used = 0x%x\n",
&core->rpc.phys, core->rpc.length, core->rpc.bytesused);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "fwlog_region = <%pad, 0x%x>\n",
&core->log.phys, core->log.length);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "power %s\n",
vpu_iface_get_power_state(core) ? "on" : "off");
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "state = %d\n", core->state);
if (seq_write(s, str, num))
return 0;
if (core->state == VPU_CORE_DEINIT)
return 0;
num = scnprintf(str, sizeof(str), "fw version = %d.%d.%d\n",
(core->fw_version >> 16) & 0xff,
(core->fw_version >> 8) & 0xff,
core->fw_version & 0xff);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "instances = %d/%d (0x%02lx), %d\n",
hweight32(core->instance_mask),
core->supported_instance_count,
core->instance_mask,
core->request_count);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str), "kfifo len = 0x%x\n", kfifo_len(&core->msg_fifo));
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str),
"cmd_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n",
iface->cmd_desc->start,
iface->cmd_desc->end,
iface->cmd_desc->wptr,
iface->cmd_desc->rptr);
if (seq_write(s, str, num))
return 0;
num = scnprintf(str, sizeof(str),
"msg_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n",
iface->msg_desc->start,
iface->msg_desc->end,
iface->msg_desc->wptr,
iface->msg_desc->rptr);
if (seq_write(s, str, num))
return 0;
return 0;
}
static int vpu_dbg_fwlog(struct seq_file *s, void *data)
{
struct vpu_core *core = s->private;
struct print_buf_desc *print_buf;
int length;
u32 rptr;
u32 wptr;
int ret = 0;
if (!core->log.virt || core->state == VPU_CORE_DEINIT)
return 0;
print_buf = core->log.virt;
rptr = print_buf->read;
wptr = print_buf->write;
if (rptr == wptr)
return 0;
else if (rptr < wptr)
length = wptr - rptr;
else
length = print_buf->bytes + wptr - rptr;
if (s->count + length >= s->size) {
s->count = s->size;
return 0;
}
if (rptr + length >= print_buf->bytes) {
int num = print_buf->bytes - rptr;
if (seq_write(s, print_buf->buffer + rptr, num))
ret = -1;
length -= num;
rptr = 0;
}
if (length) {
if (seq_write(s, print_buf->buffer + rptr, length))
ret = -1;
rptr += length;
}
if (!ret)
print_buf->read = rptr;
return 0;
}
static int vpu_dbg_inst_open(struct inode *inode, struct file *filp)
{
return single_open(filp, vpu_dbg_instance, inode->i_private);
}
static ssize_t vpu_dbg_inst_write(struct file *file,
const char __user *user_buf, size_t size, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct vpu_inst *inst = s->private;
vpu_session_debug(inst);
return size;
}
static ssize_t vpu_dbg_core_write(struct file *file,
const char __user *user_buf, size_t size, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct vpu_core *core = s->private;
pm_runtime_resume_and_get(core->dev);
mutex_lock(&core->lock);
if (vpu_iface_get_power_state(core) && !core->request_count) {
dev_info(core->dev, "reset\n");
if (!vpu_core_sw_reset(core)) {
vpu_core_set_state(core, VPU_CORE_ACTIVE);
core->hang_mask = 0;
}
}
mutex_unlock(&core->lock);
pm_runtime_put_sync(core->dev);
return size;
}
static int vpu_dbg_core_open(struct inode *inode, struct file *filp)
{
return single_open(filp, vpu_dbg_core, inode->i_private);
}
static int vpu_dbg_fwlog_open(struct inode *inode, struct file *filp)
{
return single_open(filp, vpu_dbg_fwlog, inode->i_private);
}
static const struct file_operations vpu_dbg_inst_fops = {
.owner = THIS_MODULE,
.open = vpu_dbg_inst_open,
.release = single_release,
.read = seq_read,
.write = vpu_dbg_inst_write,
};
static const struct file_operations vpu_dbg_core_fops = {
.owner = THIS_MODULE,
.open = vpu_dbg_core_open,
.release = single_release,
.read = seq_read,
.write = vpu_dbg_core_write,
};
static const struct file_operations vpu_dbg_fwlog_fops = {
.owner = THIS_MODULE,
.open = vpu_dbg_fwlog_open,
.release = single_release,
.read = seq_read,
};
int vpu_inst_create_dbgfs_file(struct vpu_inst *inst)
{
struct vpu_dev *vpu;
char name[64];
if (!inst || !inst->core || !inst->core->vpu)
return -EINVAL;
vpu = inst->core->vpu;
if (!vpu->debugfs)
return -EINVAL;
if (inst->debugfs)
return 0;
scnprintf(name, sizeof(name), "instance.%d.%d", inst->core->id, inst->id);
inst->debugfs = debugfs_create_file((const char *)name,
VERIFY_OCTAL_PERMISSIONS(0644),
vpu->debugfs,
inst,
&vpu_dbg_inst_fops);
return 0;
}
int vpu_inst_remove_dbgfs_file(struct vpu_inst *inst)
{
if (!inst)
return 0;
debugfs_remove(inst->debugfs);
inst->debugfs = NULL;
return 0;
}
int vpu_core_create_dbgfs_file(struct vpu_core *core)
{
struct vpu_dev *vpu;
char name[64];
if (!core || !core->vpu)
return -EINVAL;
vpu = core->vpu;
if (!vpu->debugfs)
return -EINVAL;
if (!core->debugfs) {
scnprintf(name, sizeof(name), "core.%d", core->id);
core->debugfs = debugfs_create_file((const char *)name,
VERIFY_OCTAL_PERMISSIONS(0644),
vpu->debugfs,
core,
&vpu_dbg_core_fops);
}
if (!core->debugfs_fwlog) {
scnprintf(name, sizeof(name), "fwlog.%d", core->id);
core->debugfs_fwlog = debugfs_create_file((const char *)name,
VERIFY_OCTAL_PERMISSIONS(0444),
vpu->debugfs,
core,
&vpu_dbg_fwlog_fops);
}
return 0;
}
int vpu_core_remove_dbgfs_file(struct vpu_core *core)
{
if (!core)
return 0;
debugfs_remove(core->debugfs);
core->debugfs = NULL;
debugfs_remove(core->debugfs_fwlog);
core->debugfs_fwlog = NULL;
return 0;
}
void vpu_inst_record_flow(struct vpu_inst *inst, u32 flow)
{
if (!inst)
return;
inst->flows[inst->flow_idx] = flow;
inst->flow_idx = (inst->flow_idx + 1) % (ARRAY_SIZE(inst->flows));
}
| linux-master | drivers/media/platform/amphion/vpu_dbg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/vmalloc.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-vmalloc.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_core.h"
#include "vpu_helpers.h"
#include "vpu_v4l2.h"
#include "vpu_cmds.h"
#include "vpu_rpc.h"
#define VDEC_MIN_BUFFER_CAP 8
#define VDEC_MIN_BUFFER_OUT 8
struct vdec_fs_info {
char name[8];
u32 type;
u32 max_count;
u32 req_count;
u32 count;
u32 index;
u32 size;
struct vpu_buffer buffer[32];
u32 tag;
};
struct vdec_t {
u32 seq_hdr_found;
struct vpu_buffer udata;
struct vpu_decode_params params;
struct vpu_dec_codec_info codec_info;
enum vpu_codec_state state;
struct vpu_vb2_buffer *slots[VB2_MAX_FRAME];
u32 req_frame_count;
struct vdec_fs_info mbi;
struct vdec_fs_info dcp;
u32 seq_tag;
bool reset_codec;
bool fixed_fmt;
u32 decoded_frame_count;
u32 display_frame_count;
u32 sequence;
u32 eos_received;
bool is_source_changed;
u32 source_change;
u32 drain;
bool aborting;
};
static const struct vpu_format vdec_formats[] = {
{
.pixfmt = V4L2_PIX_FMT_NV12M_8L128,
.mem_planes = 2,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
.sibling = V4L2_PIX_FMT_NV12_8L128,
},
{
.pixfmt = V4L2_PIX_FMT_NV12_8L128,
.mem_planes = 1,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
.sibling = V4L2_PIX_FMT_NV12M_8L128,
},
{
.pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128,
.mem_planes = 2,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
.sibling = V4L2_PIX_FMT_NV12_10BE_8L128,
},
{
.pixfmt = V4L2_PIX_FMT_NV12_10BE_8L128,
.mem_planes = 1,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
.sibling = V4L2_PIX_FMT_NV12M_10BE_8L128
},
{
.pixfmt = V4L2_PIX_FMT_H264,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_H264_MVC,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_HEVC,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_MPEG2,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_MPEG4,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_XVID,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_VP8,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_H263,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_SPK,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_RV30,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{
.pixfmt = V4L2_PIX_FMT_RV40,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED
},
{0, 0, 0, 0},
};
static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct vpu_inst *inst = ctrl_to_inst(ctrl);
struct vdec_t *vdec = inst->priv;
int ret = 0;
vpu_inst_lock(inst);
switch (ctrl->id) {
case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE:
vdec->params.display_delay_enable = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY:
vdec->params.display_delay = ctrl->val;
break;
default:
ret = -EINVAL;
break;
}
vpu_inst_unlock(inst);
return ret;
}
static const struct v4l2_ctrl_ops vdec_ctrl_ops = {
.s_ctrl = vdec_op_s_ctrl,
.g_volatile_ctrl = vpu_helper_g_volatile_ctrl,
};
static int vdec_ctrl_init(struct vpu_inst *inst)
{
struct v4l2_ctrl *ctrl;
int ret;
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20);
if (ret)
return ret;
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY,
0, 0, 1, 0);
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE,
0, 1, 1, 0);
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
if (inst->ctrl_handler.error) {
ret = inst->ctrl_handler.error;
v4l2_ctrl_handler_free(&inst->ctrl_handler);
return ret;
}
ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
if (ret) {
dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret);
v4l2_ctrl_handler_free(&inst->ctrl_handler);
return ret;
}
return 0;
}
static void vdec_handle_resolution_change(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
struct vb2_queue *q;
if (!inst->fh.m2m_ctx)
return;
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
return;
if (!vdec->source_change)
return;
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
if (!list_empty(&q->done_list))
return;
vdec->source_change--;
vpu_notify_source_change(inst);
vpu_set_last_buffer_dequeued(inst, false);
}
static int vdec_update_state(struct vpu_inst *inst, enum vpu_codec_state state, u32 force)
{
struct vdec_t *vdec = inst->priv;
enum vpu_codec_state pre_state = inst->state;
if (state == VPU_CODEC_STATE_SEEK) {
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
vdec->state = inst->state;
else
vdec->state = VPU_CODEC_STATE_ACTIVE;
}
if (inst->state != VPU_CODEC_STATE_SEEK || force)
inst->state = state;
else if (state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
vdec->state = VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE;
if (inst->state != pre_state)
vpu_trace(inst->dev, "[%d] %s -> %s\n", inst->id,
vpu_codec_state_name(pre_state), vpu_codec_state_name(inst->state));
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
vdec_handle_resolution_change(inst);
return 0;
}
static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
return;
if (vdec->eos_received) {
if (!vpu_set_last_buffer_dequeued(inst, true)) {
vdec->eos_received--;
vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0);
}
}
}
static int vdec_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
{
strscpy(cap->driver, "amphion-vpu", sizeof(cap->driver));
strscpy(cap->card, "amphion vpu decoder", sizeof(cap->card));
strscpy(cap->bus_info, "platform: amphion-vpu", sizeof(cap->bus_info));
return 0;
}
static int vdec_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
{
struct vpu_inst *inst = to_inst(file);
struct vdec_t *vdec = inst->priv;
const struct vpu_format *fmt;
int ret = -EINVAL;
vpu_inst_lock(inst);
if (V4L2_TYPE_IS_CAPTURE(f->type) && vdec->fixed_fmt) {
fmt = vpu_get_format(inst, f->type);
if (f->index == 1)
fmt = vpu_helper_find_sibling(inst, f->type, fmt->pixfmt);
if (f->index > 1)
fmt = NULL;
} else {
fmt = vpu_helper_enum_format(inst, f->type, f->index);
}
if (!fmt)
goto exit;
memset(f->reserved, 0, sizeof(f->reserved));
f->pixelformat = fmt->pixfmt;
f->flags = fmt->flags;
ret = 0;
exit:
vpu_inst_unlock(inst);
return ret;
}
static int vdec_g_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct vdec_t *vdec = inst->priv;
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
struct vpu_format *cur_fmt;
int i;
vpu_inst_lock(inst);
cur_fmt = vpu_get_format(inst, f->type);
pixmp->pixelformat = cur_fmt->pixfmt;
pixmp->num_planes = cur_fmt->mem_planes;
pixmp->width = cur_fmt->width;
pixmp->height = cur_fmt->height;
pixmp->field = cur_fmt->field;
pixmp->flags = cur_fmt->flags;
for (i = 0; i < pixmp->num_planes; i++) {
pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i];
pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(cur_fmt, i);
}
f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
vpu_inst_unlock(inst);
return 0;
}
static int vdec_try_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct vdec_t *vdec = inst->priv;
struct vpu_format fmt;
vpu_inst_lock(inst);
if (V4L2_TYPE_IS_CAPTURE(f->type) && vdec->fixed_fmt) {
struct vpu_format *cap_fmt = vpu_get_format(inst, f->type);
if (!vpu_helper_match_format(inst, cap_fmt->type, cap_fmt->pixfmt,
f->fmt.pix_mp.pixelformat))
f->fmt.pix_mp.pixelformat = cap_fmt->pixfmt;
}
vpu_try_fmt_common(inst, f, &fmt);
if (vdec->fixed_fmt) {
f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
} else {
f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_DEFAULT;
f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
}
vpu_inst_unlock(inst);
return 0;
}
static int vdec_s_fmt_common(struct vpu_inst *inst, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
struct vpu_format fmt;
struct vpu_format *cur_fmt;
struct vb2_queue *q;
struct vdec_t *vdec = inst->priv;
int i;
if (!inst->fh.m2m_ctx)
return -EINVAL;
q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type);
if (!q)
return -EINVAL;
if (vb2_is_busy(q))
return -EBUSY;
if (vpu_try_fmt_common(inst, f, &fmt))
return -EINVAL;
cur_fmt = vpu_get_format(inst, f->type);
if (V4L2_TYPE_IS_OUTPUT(f->type) && inst->state != VPU_CODEC_STATE_DEINIT) {
if (cur_fmt->pixfmt != fmt.pixfmt) {
vdec->reset_codec = true;
vdec->fixed_fmt = false;
}
}
if (V4L2_TYPE_IS_OUTPUT(f->type) || !vdec->fixed_fmt) {
memcpy(cur_fmt, &fmt, sizeof(*cur_fmt));
} else {
if (vpu_helper_match_format(inst, f->type, cur_fmt->pixfmt, pixmp->pixelformat)) {
cur_fmt->pixfmt = fmt.pixfmt;
cur_fmt->mem_planes = fmt.mem_planes;
}
pixmp->pixelformat = cur_fmt->pixfmt;
pixmp->num_planes = cur_fmt->mem_planes;
pixmp->width = cur_fmt->width;
pixmp->height = cur_fmt->height;
for (i = 0; i < pixmp->num_planes; i++) {
pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i];
pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(cur_fmt, i);
}
pixmp->field = cur_fmt->field;
}
if (!vdec->fixed_fmt) {
if (V4L2_TYPE_IS_OUTPUT(f->type)) {
vdec->params.codec_format = cur_fmt->pixfmt;
vdec->codec_info.color_primaries = f->fmt.pix_mp.colorspace;
vdec->codec_info.transfer_chars = f->fmt.pix_mp.xfer_func;
vdec->codec_info.matrix_coeffs = f->fmt.pix_mp.ycbcr_enc;
vdec->codec_info.full_range = f->fmt.pix_mp.quantization;
} else {
vdec->params.output_format = cur_fmt->pixfmt;
inst->crop.left = 0;
inst->crop.top = 0;
inst->crop.width = cur_fmt->width;
inst->crop.height = cur_fmt->height;
}
}
vpu_trace(inst->dev, "[%d] %c%c%c%c %dx%d\n", inst->id,
f->fmt.pix_mp.pixelformat,
f->fmt.pix_mp.pixelformat >> 8,
f->fmt.pix_mp.pixelformat >> 16,
f->fmt.pix_mp.pixelformat >> 24,
f->fmt.pix_mp.width,
f->fmt.pix_mp.height);
return 0;
}
static int vdec_s_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
struct vdec_t *vdec = inst->priv;
int ret = 0;
vpu_inst_lock(inst);
ret = vdec_s_fmt_common(inst, f);
if (ret)
goto exit;
if (V4L2_TYPE_IS_OUTPUT(f->type) && !vdec->fixed_fmt) {
struct v4l2_format fc;
memset(&fc, 0, sizeof(fc));
fc.type = inst->cap_format.type;
fc.fmt.pix_mp.pixelformat = inst->cap_format.pixfmt;
fc.fmt.pix_mp.width = pixmp->width;
fc.fmt.pix_mp.height = pixmp->height;
vdec_s_fmt_common(inst, &fc);
}
f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
exit:
vpu_inst_unlock(inst);
return ret;
}
static int vdec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct vpu_inst *inst = to_inst(file);
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
return -EINVAL;
switch (s->target) {
case V4L2_SEL_TGT_COMPOSE:
case V4L2_SEL_TGT_COMPOSE_DEFAULT:
case V4L2_SEL_TGT_COMPOSE_PADDED:
s->r = inst->crop;
break;
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
s->r.left = 0;
s->r.top = 0;
s->r.width = inst->cap_format.width;
s->r.height = inst->cap_format.height;
break;
default:
return -EINVAL;
}
return 0;
}
static int vdec_drain(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
if (!inst->fh.m2m_ctx)
return 0;
if (!vdec->drain)
return 0;
if (!vpu_is_source_empty(inst))
return 0;
if (!vdec->params.frame_count) {
vpu_set_last_buffer_dequeued(inst, true);
return 0;
}
vpu_iface_add_scode(inst, SCODE_PADDING_EOS);
vdec->params.end_flag = 1;
vpu_iface_set_decode_params(inst, &vdec->params, 1);
vdec->drain = 0;
vpu_trace(inst->dev, "[%d] frame_count = %d\n", inst->id, vdec->params.frame_count);
return 0;
}
static int vdec_cmd_start(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
switch (inst->state) {
case VPU_CODEC_STATE_STARTED:
case VPU_CODEC_STATE_DRAIN:
case VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE:
vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
break;
default:
break;
}
vpu_process_capture_buffer(inst);
if (vdec->eos_received)
vdec_set_last_buffer_dequeued(inst);
return 0;
}
static int vdec_cmd_stop(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vpu_trace(inst->dev, "[%d]\n", inst->id);
if (inst->state == VPU_CODEC_STATE_DEINIT) {
vpu_set_last_buffer_dequeued(inst, true);
} else {
vdec->drain = 1;
vdec_drain(inst);
}
return 0;
}
static int vdec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *cmd)
{
struct vpu_inst *inst = to_inst(file);
int ret;
ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, cmd);
if (ret)
return ret;
vpu_inst_lock(inst);
switch (cmd->cmd) {
case V4L2_DEC_CMD_START:
vdec_cmd_start(inst);
break;
case V4L2_DEC_CMD_STOP:
vdec_cmd_stop(inst);
break;
default:
break;
}
vpu_inst_unlock(inst);
return 0;
}
static int vdec_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_EOS:
return v4l2_event_subscribe(fh, sub, 0, NULL);
case V4L2_EVENT_SOURCE_CHANGE:
return v4l2_src_change_event_subscribe(fh, sub);
case V4L2_EVENT_CTRL:
return v4l2_ctrl_subscribe_event(fh, sub);
default:
return -EINVAL;
}
return 0;
}
static const struct v4l2_ioctl_ops vdec_ioctl_ops = {
.vidioc_querycap = vdec_querycap,
.vidioc_enum_fmt_vid_cap = vdec_enum_fmt,
.vidioc_enum_fmt_vid_out = vdec_enum_fmt,
.vidioc_g_fmt_vid_cap_mplane = vdec_g_fmt,
.vidioc_g_fmt_vid_out_mplane = vdec_g_fmt,
.vidioc_try_fmt_vid_cap_mplane = vdec_try_fmt,
.vidioc_try_fmt_vid_out_mplane = vdec_try_fmt,
.vidioc_s_fmt_vid_cap_mplane = vdec_s_fmt,
.vidioc_s_fmt_vid_out_mplane = vdec_s_fmt,
.vidioc_g_selection = vdec_g_selection,
.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
.vidioc_decoder_cmd = vdec_decoder_cmd,
.vidioc_subscribe_event = vdec_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
};
static bool vdec_check_ready(struct vpu_inst *inst, unsigned int type)
{
struct vdec_t *vdec = inst->priv;
if (V4L2_TYPE_IS_OUTPUT(type))
return true;
if (vdec->req_frame_count)
return true;
return false;
}
static struct vb2_v4l2_buffer *vdec_get_src_buffer(struct vpu_inst *inst, u32 count)
{
if (count > 1)
vpu_skip_frame(inst, count - 1);
return vpu_next_src_buf(inst);
}
static int vdec_frame_decoded(struct vpu_inst *inst, void *arg)
{
struct vdec_t *vdec = inst->priv;
struct vpu_dec_pic_info *info = arg;
struct vpu_vb2_buffer *vpu_buf;
struct vb2_v4l2_buffer *vbuf;
struct vb2_v4l2_buffer *src_buf;
int ret = 0;
if (!info || info->id >= ARRAY_SIZE(vdec->slots))
return -EINVAL;
vpu_inst_lock(inst);
vpu_buf = vdec->slots[info->id];
if (!vpu_buf) {
dev_err(inst->dev, "[%d] decoded invalid frame[%d]\n", inst->id, info->id);
ret = -EINVAL;
goto exit;
}
vbuf = &vpu_buf->m2m_buf.vb;
src_buf = vdec_get_src_buffer(inst, info->consumed_count);
if (src_buf) {
v4l2_m2m_buf_copy_metadata(src_buf, vbuf, true);
if (info->consumed_count) {
v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx);
vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
} else {
vpu_set_buffer_state(src_buf, VPU_BUF_STATE_DECODED);
}
}
if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_DECODED)
dev_info(inst->dev, "[%d] buf[%d] has been decoded\n", inst->id, info->id);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_DECODED);
vdec->decoded_frame_count++;
if (vdec->params.display_delay_enable) {
struct vpu_format *cur_fmt;
cur_fmt = vpu_get_format(inst, inst->cap_format.type);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_READY);
for (int i = 0; i < vbuf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&vbuf->vb2_buf,
i, vpu_get_fmt_plane_size(cur_fmt, i));
vbuf->field = cur_fmt->field;
vbuf->sequence = vdec->sequence++;
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
vdec->display_frame_count++;
}
exit:
vpu_inst_unlock(inst);
return ret;
}
static struct vpu_vb2_buffer *vdec_find_buffer(struct vpu_inst *inst, u32 luma)
{
struct vdec_t *vdec = inst->priv;
int i;
for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) {
if (!vdec->slots[i])
continue;
if (luma == vdec->slots[i]->luma)
return vdec->slots[i];
}
return NULL;
}
static void vdec_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame)
{
struct vdec_t *vdec = inst->priv;
struct vpu_format *cur_fmt;
struct vpu_vb2_buffer *vpu_buf;
struct vb2_v4l2_buffer *vbuf;
int i;
if (!frame)
return;
vpu_inst_lock(inst);
if (!vdec->params.display_delay_enable)
vdec->sequence++;
vpu_buf = vdec_find_buffer(inst, frame->luma);
vpu_inst_unlock(inst);
if (!vpu_buf) {
dev_err(inst->dev, "[%d] can't find buffer, id = %d, addr = 0x%x\n",
inst->id, frame->id, frame->luma);
return;
}
if (frame->skipped) {
dev_dbg(inst->dev, "[%d] frame skip\n", inst->id);
return;
}
cur_fmt = vpu_get_format(inst, inst->cap_format.type);
vbuf = &vpu_buf->m2m_buf.vb;
if (vbuf->vb2_buf.index != frame->id)
dev_err(inst->dev, "[%d] buffer id(%d, %d) dismatch\n",
inst->id, vbuf->vb2_buf.index, frame->id);
if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_READY && vdec->params.display_delay_enable)
return;
if (vpu_get_buffer_state(vbuf) != VPU_BUF_STATE_DECODED)
dev_err(inst->dev, "[%d] buffer(%d) ready without decoded\n", inst->id, frame->id);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_READY);
for (i = 0; i < vbuf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&vbuf->vb2_buf, i, vpu_get_fmt_plane_size(cur_fmt, i));
vbuf->field = cur_fmt->field;
vbuf->sequence = vdec->sequence;
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
vpu_inst_lock(inst);
vdec->display_frame_count++;
vpu_inst_unlock(inst);
dev_dbg(inst->dev, "[%d] decoded : %d, display : %d, sequence : %d\n",
inst->id, vdec->decoded_frame_count, vdec->display_frame_count, vdec->sequence);
}
static void vdec_stop_done(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vpu_inst_lock(inst);
vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 0);
vdec->seq_hdr_found = 0;
vdec->req_frame_count = 0;
vdec->reset_codec = false;
vdec->fixed_fmt = false;
vdec->params.end_flag = 0;
vdec->drain = 0;
vdec->params.frame_count = 0;
vdec->decoded_frame_count = 0;
vdec->display_frame_count = 0;
vdec->sequence = 0;
vdec->eos_received = 0;
vdec->is_source_changed = false;
vdec->source_change = 0;
inst->total_input_count = 0;
vpu_inst_unlock(inst);
}
static bool vdec_check_source_change(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
const struct vpu_format *sibling;
if (!inst->fh.m2m_ctx)
return false;
if (vdec->reset_codec)
return false;
sibling = vpu_helper_find_sibling(inst, inst->cap_format.type, inst->cap_format.pixfmt);
if (sibling && vdec->codec_info.pixfmt == sibling->pixfmt)
vdec->codec_info.pixfmt = inst->cap_format.pixfmt;
if (!vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx)))
return true;
if (inst->cap_format.pixfmt != vdec->codec_info.pixfmt)
return true;
if (inst->cap_format.width != vdec->codec_info.decoded_width)
return true;
if (inst->cap_format.height != vdec->codec_info.decoded_height)
return true;
if (vpu_get_num_buffers(inst, inst->cap_format.type) < inst->min_buffer_cap)
return true;
if (inst->crop.left != vdec->codec_info.offset_x)
return true;
if (inst->crop.top != vdec->codec_info.offset_y)
return true;
if (inst->crop.width != vdec->codec_info.width)
return true;
if (inst->crop.height != vdec->codec_info.height)
return true;
return false;
}
static void vdec_init_fmt(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
struct v4l2_format f;
memset(&f, 0, sizeof(f));
f.type = inst->cap_format.type;
f.fmt.pix_mp.pixelformat = vdec->codec_info.pixfmt;
f.fmt.pix_mp.width = vdec->codec_info.decoded_width;
f.fmt.pix_mp.height = vdec->codec_info.decoded_height;
if (vdec->codec_info.progressive)
f.fmt.pix_mp.field = V4L2_FIELD_NONE;
else
f.fmt.pix_mp.field = V4L2_FIELD_SEQ_TB;
vpu_try_fmt_common(inst, &f, &inst->cap_format);
inst->out_format.width = vdec->codec_info.width;
inst->out_format.height = vdec->codec_info.height;
}
static void vdec_init_crop(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
inst->crop.left = vdec->codec_info.offset_x;
inst->crop.top = vdec->codec_info.offset_y;
inst->crop.width = vdec->codec_info.width;
inst->crop.height = vdec->codec_info.height;
}
static void vdec_init_mbi(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vdec->mbi.size = vdec->codec_info.mbi_size;
vdec->mbi.max_count = ARRAY_SIZE(vdec->mbi.buffer);
scnprintf(vdec->mbi.name, sizeof(vdec->mbi.name), "mbi");
vdec->mbi.type = MEM_RES_MBI;
vdec->mbi.tag = vdec->seq_tag;
}
static void vdec_init_dcp(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vdec->dcp.size = vdec->codec_info.dcp_size;
vdec->dcp.max_count = ARRAY_SIZE(vdec->dcp.buffer);
scnprintf(vdec->dcp.name, sizeof(vdec->dcp.name), "dcp");
vdec->dcp.type = MEM_RES_DCP;
vdec->dcp.tag = vdec->seq_tag;
}
static void vdec_request_one_fs(struct vdec_fs_info *fs)
{
fs->req_count++;
if (fs->req_count > fs->max_count)
fs->req_count = fs->max_count;
}
static int vdec_alloc_fs_buffer(struct vpu_inst *inst, struct vdec_fs_info *fs)
{
struct vpu_buffer *buffer;
if (!fs->size)
return -EINVAL;
if (fs->count >= fs->req_count)
return -EINVAL;
buffer = &fs->buffer[fs->count];
if (buffer->virt && buffer->length >= fs->size)
return 0;
vpu_free_dma(buffer);
buffer->length = fs->size;
return vpu_alloc_dma(inst->core, buffer);
}
static void vdec_alloc_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
{
int ret;
while (fs->count < fs->req_count) {
ret = vdec_alloc_fs_buffer(inst, fs);
if (ret)
break;
fs->count++;
}
}
static void vdec_clear_fs(struct vdec_fs_info *fs)
{
u32 i;
if (!fs)
return;
for (i = 0; i < ARRAY_SIZE(fs->buffer); i++)
vpu_free_dma(&fs->buffer[i]);
memset(fs, 0, sizeof(*fs));
}
static int vdec_response_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
{
struct vpu_fs_info info;
int ret;
if (fs->index >= fs->count)
return 0;
memset(&info, 0, sizeof(info));
info.id = fs->index;
info.type = fs->type;
info.tag = fs->tag;
info.luma_addr = fs->buffer[fs->index].phys;
info.luma_size = fs->buffer[fs->index].length;
ret = vpu_session_alloc_fs(inst, &info);
if (ret)
return ret;
fs->index++;
return 0;
}
static int vdec_response_frame_abnormal(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
struct vpu_fs_info info;
int ret;
if (!vdec->req_frame_count)
return 0;
memset(&info, 0, sizeof(info));
info.type = MEM_RES_FRAME;
info.tag = vdec->seq_tag + 0xf0;
ret = vpu_session_alloc_fs(inst, &info);
if (ret)
return ret;
vdec->req_frame_count--;
return 0;
}
static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
{
struct vdec_t *vdec = inst->priv;
struct vpu_vb2_buffer *vpu_buf;
struct vpu_fs_info info;
int ret;
if (inst->state != VPU_CODEC_STATE_ACTIVE)
return -EINVAL;
if (vdec->aborting)
return -EINVAL;
if (!vdec->req_frame_count)
return -EINVAL;
if (!vbuf)
return -EINVAL;
if (vdec->slots[vbuf->vb2_buf.index]) {
dev_err(inst->dev, "[%d] repeat alloc fs %d\n",
inst->id, vbuf->vb2_buf.index);
return -EINVAL;
}
dev_dbg(inst->dev, "[%d] state = %s, alloc fs %d, tag = 0x%x\n",
inst->id, vpu_codec_state_name(inst->state), vbuf->vb2_buf.index, vdec->seq_tag);
vpu_buf = to_vpu_vb2_buffer(vbuf);
memset(&info, 0, sizeof(info));
info.id = vbuf->vb2_buf.index;
info.type = MEM_RES_FRAME;
info.tag = vdec->seq_tag;
info.luma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 0);
info.luma_size = inst->cap_format.sizeimage[0];
if (vbuf->vb2_buf.num_planes > 1)
info.chroma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 1);
else
info.chroma_addr = info.luma_addr + info.luma_size;
info.chromau_size = inst->cap_format.sizeimage[1];
info.bytesperline = inst->cap_format.bytesperline[0];
ret = vpu_session_alloc_fs(inst, &info);
if (ret)
return ret;
vpu_buf->tag = info.tag;
vpu_buf->luma = info.luma_addr;
vpu_buf->chroma_u = info.chroma_addr;
vpu_buf->chroma_v = 0;
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE);
vdec->slots[info.id] = vpu_buf;
vdec->req_frame_count--;
return 0;
}
static void vdec_response_fs_request(struct vpu_inst *inst, bool force)
{
struct vdec_t *vdec = inst->priv;
int i;
int ret;
if (force) {
for (i = vdec->req_frame_count; i > 0; i--)
vdec_response_frame_abnormal(inst);
return;
}
for (i = vdec->req_frame_count; i > 0; i--) {
ret = vpu_process_capture_buffer(inst);
if (ret)
break;
if (vdec->eos_received)
break;
}
for (i = vdec->mbi.index; i < vdec->mbi.count; i++) {
if (vdec_response_fs(inst, &vdec->mbi))
break;
if (vdec->eos_received)
break;
}
for (i = vdec->dcp.index; i < vdec->dcp.count; i++) {
if (vdec_response_fs(inst, &vdec->dcp))
break;
if (vdec->eos_received)
break;
}
}
static void vdec_response_fs_release(struct vpu_inst *inst, u32 id, u32 tag)
{
struct vpu_fs_info info;
memset(&info, 0, sizeof(info));
info.id = id;
info.tag = tag;
vpu_session_release_fs(inst, &info);
}
static void vdec_recycle_buffer(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
{
if (!inst->fh.m2m_ctx)
return;
if (vbuf->vb2_buf.state != VB2_BUF_STATE_ACTIVE)
return;
if (vpu_find_buf_by_idx(inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index))
return;
v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf);
}
static void vdec_clear_slots(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
struct vpu_vb2_buffer *vpu_buf;
struct vb2_v4l2_buffer *vbuf;
int i;
for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) {
if (!vdec->slots[i])
continue;
vpu_buf = vdec->slots[i];
vbuf = &vpu_buf->m2m_buf.vb;
vpu_trace(inst->dev, "clear slot %d\n", i);
vdec_response_fs_release(inst, i, vpu_buf->tag);
vdec_recycle_buffer(inst, vbuf);
vdec->slots[i]->state = VPU_BUF_STATE_IDLE;
vdec->slots[i] = NULL;
}
}
static void vdec_event_seq_hdr(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr)
{
struct vdec_t *vdec = inst->priv;
vpu_inst_lock(inst);
memcpy(&vdec->codec_info, hdr, sizeof(vdec->codec_info));
vpu_trace(inst->dev, "[%d] %d x %d, crop : (%d, %d) %d x %d, %d, %d\n",
inst->id,
vdec->codec_info.decoded_width,
vdec->codec_info.decoded_height,
vdec->codec_info.offset_x,
vdec->codec_info.offset_y,
vdec->codec_info.width,
vdec->codec_info.height,
hdr->num_ref_frms,
hdr->num_dpb_frms);
inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms;
vdec->is_source_changed = vdec_check_source_change(inst);
vdec_init_fmt(inst);
vdec_init_crop(inst);
vdec_init_mbi(inst);
vdec_init_dcp(inst);
if (!vdec->seq_hdr_found) {
vdec->seq_tag = vdec->codec_info.tag;
if (vdec->is_source_changed) {
vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
vdec->source_change++;
vdec_handle_resolution_change(inst);
vdec->is_source_changed = false;
}
}
if (vdec->seq_tag != vdec->codec_info.tag) {
vdec_response_fs_request(inst, true);
vpu_trace(inst->dev, "[%d] seq tag change: %d -> %d\n",
inst->id, vdec->seq_tag, vdec->codec_info.tag);
}
vdec->seq_hdr_found++;
vdec->fixed_fmt = true;
vpu_inst_unlock(inst);
}
static void vdec_event_resolution_change(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vpu_trace(inst->dev, "[%d]\n", inst->id);
vpu_inst_lock(inst);
vdec->seq_tag = vdec->codec_info.tag;
vdec_clear_fs(&vdec->mbi);
vdec_clear_fs(&vdec->dcp);
vdec_clear_slots(inst);
vdec_init_mbi(inst);
vdec_init_dcp(inst);
if (vdec->is_source_changed) {
vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
vdec->source_change++;
vdec_handle_resolution_change(inst);
vdec->is_source_changed = false;
}
vpu_inst_unlock(inst);
}
static void vdec_event_req_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
{
struct vdec_t *vdec = inst->priv;
if (!fs)
return;
vpu_inst_lock(inst);
switch (fs->type) {
case MEM_RES_FRAME:
vdec->req_frame_count++;
break;
case MEM_RES_MBI:
vdec_request_one_fs(&vdec->mbi);
break;
case MEM_RES_DCP:
vdec_request_one_fs(&vdec->dcp);
break;
default:
break;
}
vdec_alloc_fs(inst, &vdec->mbi);
vdec_alloc_fs(inst, &vdec->dcp);
vdec_response_fs_request(inst, false);
vpu_inst_unlock(inst);
}
static void vdec_evnet_rel_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
{
struct vdec_t *vdec = inst->priv;
struct vpu_vb2_buffer *vpu_buf;
struct vb2_v4l2_buffer *vbuf;
if (!fs || fs->id >= ARRAY_SIZE(vdec->slots))
return;
if (fs->type != MEM_RES_FRAME)
return;
if (fs->id >= vpu_get_num_buffers(inst, inst->cap_format.type)) {
dev_err(inst->dev, "[%d] invalid fs(%d) to release\n", inst->id, fs->id);
return;
}
vpu_inst_lock(inst);
vpu_buf = vdec->slots[fs->id];
vdec->slots[fs->id] = NULL;
if (!vpu_buf) {
dev_dbg(inst->dev, "[%d] fs[%d] has bee released\n", inst->id, fs->id);
goto exit;
}
vbuf = &vpu_buf->m2m_buf.vb;
if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_DECODED) {
dev_dbg(inst->dev, "[%d] frame skip\n", inst->id);
vdec->sequence++;
}
vdec_response_fs_release(inst, fs->id, vpu_buf->tag);
if (vpu_get_buffer_state(vbuf) != VPU_BUF_STATE_READY)
vdec_recycle_buffer(inst, vbuf);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE);
vpu_process_capture_buffer(inst);
exit:
vpu_inst_unlock(inst);
}
static void vdec_event_eos(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n",
inst->id,
vdec->params.frame_count,
vdec->decoded_frame_count,
vdec->display_frame_count,
vdec->sequence);
vpu_inst_lock(inst);
vdec->eos_received++;
vdec->fixed_fmt = false;
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
vdec_set_last_buffer_dequeued(inst);
vpu_inst_unlock(inst);
}
static void vdec_event_notify(struct vpu_inst *inst, u32 event, void *data)
{
switch (event) {
case VPU_MSG_ID_SEQ_HDR_FOUND:
vdec_event_seq_hdr(inst, data);
break;
case VPU_MSG_ID_RES_CHANGE:
vdec_event_resolution_change(inst);
break;
case VPU_MSG_ID_FRAME_REQ:
vdec_event_req_fs(inst, data);
break;
case VPU_MSG_ID_FRAME_RELEASE:
vdec_evnet_rel_fs(inst, data);
break;
case VPU_MSG_ID_PIC_EOS:
vdec_event_eos(inst);
break;
default:
break;
}
}
static int vdec_process_output(struct vpu_inst *inst, struct vb2_buffer *vb)
{
struct vdec_t *vdec = inst->priv;
struct vb2_v4l2_buffer *vbuf;
struct vpu_rpc_buffer_desc desc;
u32 free_space;
int ret;
vbuf = to_vb2_v4l2_buffer(vb);
dev_dbg(inst->dev, "[%d] dec output [%d] %d : %ld\n",
inst->id, vbuf->sequence, vb->index, vb2_get_plane_payload(vb, 0));
if (inst->state == VPU_CODEC_STATE_DEINIT)
return -EINVAL;
if (vdec->reset_codec)
return -EINVAL;
if (inst->state == VPU_CODEC_STATE_STARTED)
vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
if (ret)
return ret;
free_space = vpu_helper_get_free_space(inst);
if (free_space < vb2_get_plane_payload(vb, 0) + 0x40000)
return -ENOMEM;
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE);
ret = vpu_iface_input_frame(inst, vb);
if (ret < 0)
return -ENOMEM;
dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp);
vdec->params.frame_count++;
if (vdec->drain)
vdec_drain(inst);
return 0;
}
static int vdec_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb)
{
struct vdec_t *vdec = inst->priv;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
int ret;
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
return -EINVAL;
if (vdec->reset_codec)
return -EINVAL;
ret = vdec_response_frame(inst, vbuf);
if (ret)
return ret;
v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf);
return 0;
}
static void vdec_on_queue_empty(struct vpu_inst *inst, u32 type)
{
struct vdec_t *vdec = inst->priv;
if (V4L2_TYPE_IS_OUTPUT(type))
return;
vdec_handle_resolution_change(inst);
if (vdec->eos_received)
vdec_set_last_buffer_dequeued(inst);
}
static void vdec_abort(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
struct vpu_rpc_buffer_desc desc;
int ret;
vpu_trace(inst->dev, "[%d] state = %s\n", inst->id, vpu_codec_state_name(inst->state));
vdec->aborting = true;
vpu_iface_add_scode(inst, SCODE_PADDING_ABORT);
vdec->params.end_flag = 1;
vpu_iface_set_decode_params(inst, &vdec->params, 1);
vpu_session_abort(inst);
ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
if (!ret)
vpu_iface_update_stream_buffer(inst, desc.rptr, 1);
vpu_session_rst_buf(inst);
vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n",
inst->id,
vdec->params.frame_count,
vdec->decoded_frame_count,
vdec->display_frame_count,
vdec->sequence);
if (!vdec->seq_hdr_found)
vdec->reset_codec = true;
vdec->params.end_flag = 0;
vdec->drain = 0;
vdec->params.frame_count = 0;
vdec->decoded_frame_count = 0;
vdec->display_frame_count = 0;
vdec->sequence = 0;
vdec->aborting = false;
inst->extra_size = 0;
}
static void vdec_stop(struct vpu_inst *inst, bool free)
{
struct vdec_t *vdec = inst->priv;
vdec_clear_slots(inst);
if (inst->state != VPU_CODEC_STATE_DEINIT)
vpu_session_stop(inst);
vdec_clear_fs(&vdec->mbi);
vdec_clear_fs(&vdec->dcp);
if (free) {
vpu_free_dma(&vdec->udata);
vpu_free_dma(&inst->stream_buffer);
}
vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 1);
vdec->reset_codec = false;
}
static void vdec_release(struct vpu_inst *inst)
{
if (inst->id != VPU_INST_NULL_ID)
vpu_trace(inst->dev, "[%d]\n", inst->id);
vdec_stop(inst, true);
}
static void vdec_cleanup(struct vpu_inst *inst)
{
struct vdec_t *vdec;
if (!inst)
return;
vdec = inst->priv;
vfree(vdec);
inst->priv = NULL;
vfree(inst);
}
static void vdec_init_params(struct vdec_t *vdec)
{
vdec->params.frame_count = 0;
vdec->params.end_flag = 0;
}
static int vdec_start(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
int stream_buffer_size;
int ret;
if (inst->state != VPU_CODEC_STATE_DEINIT)
return 0;
vpu_trace(inst->dev, "[%d]\n", inst->id);
if (!vdec->udata.virt) {
vdec->udata.length = 0x1000;
ret = vpu_alloc_dma(inst->core, &vdec->udata);
if (ret) {
dev_err(inst->dev, "[%d] alloc udata fail\n", inst->id);
goto error;
}
}
if (!inst->stream_buffer.virt) {
stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core);
if (stream_buffer_size > 0) {
inst->stream_buffer.length = stream_buffer_size;
ret = vpu_alloc_dma(inst->core, &inst->stream_buffer);
if (ret) {
dev_err(inst->dev, "[%d] alloc stream buffer fail\n", inst->id);
goto error;
}
inst->use_stream_buffer = true;
}
}
if (inst->use_stream_buffer)
vpu_iface_config_stream_buffer(inst, &inst->stream_buffer);
vpu_iface_init_instance(inst);
vdec->params.udata.base = vdec->udata.phys;
vdec->params.udata.size = vdec->udata.length;
ret = vpu_iface_set_decode_params(inst, &vdec->params, 0);
if (ret) {
dev_err(inst->dev, "[%d] set decode params fail\n", inst->id);
goto error;
}
vdec_init_params(vdec);
ret = vpu_session_start(inst);
if (ret) {
dev_err(inst->dev, "[%d] start fail\n", inst->id);
goto error;
}
vdec_update_state(inst, VPU_CODEC_STATE_STARTED, 0);
return 0;
error:
vpu_free_dma(&vdec->udata);
vpu_free_dma(&inst->stream_buffer);
return ret;
}
static int vdec_start_session(struct vpu_inst *inst, u32 type)
{
struct vdec_t *vdec = inst->priv;
int ret = 0;
if (V4L2_TYPE_IS_OUTPUT(type)) {
if (vdec->reset_codec)
vdec_stop(inst, false);
if (inst->state == VPU_CODEC_STATE_DEINIT) {
ret = vdec_start(inst);
if (ret)
return ret;
}
}
if (V4L2_TYPE_IS_OUTPUT(type)) {
vdec_update_state(inst, vdec->state, 1);
vdec->eos_received = 0;
vpu_process_output_buffer(inst);
} else {
vdec_cmd_start(inst);
}
if (inst->state == VPU_CODEC_STATE_ACTIVE)
vdec_response_fs_request(inst, false);
return ret;
}
static int vdec_stop_session(struct vpu_inst *inst, u32 type)
{
struct vdec_t *vdec = inst->priv;
if (inst->state == VPU_CODEC_STATE_DEINIT)
return 0;
if (V4L2_TYPE_IS_OUTPUT(type)) {
vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0);
vdec->drain = 0;
} else {
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) {
vdec_abort(inst);
vdec->eos_received = 0;
}
vdec_clear_slots(inst);
}
return 0;
}
static int vdec_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
{
struct vdec_t *vdec = inst->priv;
int num = -1;
switch (i) {
case 0:
num = scnprintf(str, size,
"req_frame_count = %d\ninterlaced = %d\n",
vdec->req_frame_count,
vdec->codec_info.progressive ? 0 : 1);
break;
case 1:
num = scnprintf(str, size,
"mbi: size = 0x%x request = %d, alloc = %d, response = %d\n",
vdec->mbi.size,
vdec->mbi.req_count,
vdec->mbi.count,
vdec->mbi.index);
break;
case 2:
num = scnprintf(str, size,
"dcp: size = 0x%x request = %d, alloc = %d, response = %d\n",
vdec->dcp.size,
vdec->dcp.req_count,
vdec->dcp.count,
vdec->dcp.index);
break;
case 3:
num = scnprintf(str, size, "input_frame_count = %d\n", vdec->params.frame_count);
break;
case 4:
num = scnprintf(str, size, "decoded_frame_count = %d\n", vdec->decoded_frame_count);
break;
case 5:
num = scnprintf(str, size, "display_frame_count = %d\n", vdec->display_frame_count);
break;
case 6:
num = scnprintf(str, size, "sequence = %d\n", vdec->sequence);
break;
case 7:
num = scnprintf(str, size, "drain = %d, eos = %d, source_change = %d\n",
vdec->drain, vdec->eos_received, vdec->source_change);
break;
case 8:
num = scnprintf(str, size, "fps = %d/%d\n",
vdec->codec_info.frame_rate.numerator,
vdec->codec_info.frame_rate.denominator);
break;
case 9:
num = scnprintf(str, size, "colorspace: %d, %d, %d, %d (%d)\n",
vdec->codec_info.color_primaries,
vdec->codec_info.transfer_chars,
vdec->codec_info.matrix_coeffs,
vdec->codec_info.full_range,
vdec->codec_info.vui_present);
break;
default:
break;
}
return num;
}
static struct vpu_inst_ops vdec_inst_ops = {
.ctrl_init = vdec_ctrl_init,
.check_ready = vdec_check_ready,
.buf_done = vdec_buf_done,
.get_one_frame = vdec_frame_decoded,
.stop_done = vdec_stop_done,
.event_notify = vdec_event_notify,
.release = vdec_release,
.cleanup = vdec_cleanup,
.start = vdec_start_session,
.stop = vdec_stop_session,
.process_output = vdec_process_output,
.process_capture = vdec_process_capture,
.on_queue_empty = vdec_on_queue_empty,
.get_debug_info = vdec_get_debug_info,
.wait_prepare = vpu_inst_unlock,
.wait_finish = vpu_inst_lock,
};
static void vdec_init(struct file *file)
{
struct vpu_inst *inst = to_inst(file);
struct v4l2_format f;
memset(&f, 0, sizeof(f));
f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264;
f.fmt.pix_mp.width = 1280;
f.fmt.pix_mp.height = 720;
f.fmt.pix_mp.field = V4L2_FIELD_NONE;
vdec_s_fmt(file, &inst->fh, &f);
memset(&f, 0, sizeof(f));
f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12M_8L128;
f.fmt.pix_mp.width = 1280;
f.fmt.pix_mp.height = 720;
f.fmt.pix_mp.field = V4L2_FIELD_NONE;
vdec_s_fmt(file, &inst->fh, &f);
}
static int vdec_open(struct file *file)
{
struct vpu_inst *inst;
struct vdec_t *vdec;
int ret;
inst = vzalloc(sizeof(*inst));
if (!inst)
return -ENOMEM;
vdec = vzalloc(sizeof(*vdec));
if (!vdec) {
vfree(inst);
return -ENOMEM;
}
inst->ops = &vdec_inst_ops;
inst->formats = vdec_formats;
inst->type = VPU_CORE_TYPE_DEC;
inst->priv = vdec;
ret = vpu_v4l2_open(file, inst);
if (ret)
return ret;
vdec->fixed_fmt = false;
vdec->state = VPU_CODEC_STATE_ACTIVE;
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
inst->min_buffer_out = VDEC_MIN_BUFFER_OUT;
vdec_init(file);
return 0;
}
static const struct v4l2_file_operations vdec_fops = {
.owner = THIS_MODULE,
.open = vdec_open,
.release = vpu_v4l2_close,
.unlocked_ioctl = video_ioctl2,
.poll = v4l2_m2m_fop_poll,
.mmap = v4l2_m2m_fop_mmap,
};
const struct v4l2_ioctl_ops *vdec_get_ioctl_ops(void)
{
return &vdec_ioctl_ops;
}
const struct v4l2_file_operations *vdec_get_fops(void)
{
return &vdec_fops;
}
| linux-master | drivers/media/platform/amphion/vdec.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pm_runtime.h>
#include <linux/pm_domain.h>
#include <linux/firmware.h>
#include <linux/vmalloc.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_core.h"
#include "vpu_mbox.h"
#include "vpu_msgs.h"
#include "vpu_rpc.h"
#include "vpu_cmds.h"
void csr_writel(struct vpu_core *core, u32 reg, u32 val)
{
writel(val, core->base + reg);
}
u32 csr_readl(struct vpu_core *core, u32 reg)
{
return readl(core->base + reg);
}
static int vpu_core_load_firmware(struct vpu_core *core)
{
const struct firmware *pfw = NULL;
int ret = 0;
if (!core->fw.virt) {
dev_err(core->dev, "firmware buffer is not ready\n");
return -EINVAL;
}
ret = request_firmware(&pfw, core->res->fwname, core->dev);
dev_dbg(core->dev, "request_firmware %s : %d\n", core->res->fwname, ret);
if (ret) {
dev_err(core->dev, "request firmware %s failed, ret = %d\n",
core->res->fwname, ret);
return ret;
}
if (core->fw.length < pfw->size) {
dev_err(core->dev, "firmware buffer size want %zu, but %d\n",
pfw->size, core->fw.length);
ret = -EINVAL;
goto exit;
}
memset(core->fw.virt, 0, core->fw.length);
memcpy(core->fw.virt, pfw->data, pfw->size);
core->fw.bytesused = pfw->size;
ret = vpu_iface_on_firmware_loaded(core);
exit:
release_firmware(pfw);
pfw = NULL;
return ret;
}
static int vpu_core_boot_done(struct vpu_core *core)
{
u32 fw_version;
fw_version = vpu_iface_get_version(core);
dev_info(core->dev, "%s firmware version : %d.%d.%d\n",
vpu_core_type_desc(core->type),
(fw_version >> 16) & 0xff,
(fw_version >> 8) & 0xff,
fw_version & 0xff);
core->supported_instance_count = vpu_iface_get_max_instance_count(core);
if (core->res->act_size) {
u32 count = core->act.length / core->res->act_size;
core->supported_instance_count = min(core->supported_instance_count, count);
}
if (core->supported_instance_count >= BITS_PER_TYPE(core->instance_mask))
core->supported_instance_count = BITS_PER_TYPE(core->instance_mask);
core->fw_version = fw_version;
vpu_core_set_state(core, VPU_CORE_ACTIVE);
return 0;
}
static int vpu_core_wait_boot_done(struct vpu_core *core)
{
int ret;
ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT);
if (!ret) {
dev_err(core->dev, "boot timeout\n");
return -EINVAL;
}
return vpu_core_boot_done(core);
}
static int vpu_core_boot(struct vpu_core *core, bool load)
{
int ret;
reinit_completion(&core->cmp);
if (load) {
ret = vpu_core_load_firmware(core);
if (ret)
return ret;
}
vpu_iface_boot_core(core);
return vpu_core_wait_boot_done(core);
}
static int vpu_core_shutdown(struct vpu_core *core)
{
return vpu_iface_shutdown_core(core);
}
static int vpu_core_restore(struct vpu_core *core)
{
int ret;
ret = vpu_core_sw_reset(core);
if (ret)
return ret;
vpu_core_boot_done(core);
return vpu_iface_restore_core(core);
}
static int __vpu_alloc_dma(struct device *dev, struct vpu_buffer *buf)
{
gfp_t gfp = GFP_KERNEL | GFP_DMA32;
if (!buf->length)
return 0;
buf->virt = dma_alloc_coherent(dev, buf->length, &buf->phys, gfp);
if (!buf->virt)
return -ENOMEM;
buf->dev = dev;
return 0;
}
void vpu_free_dma(struct vpu_buffer *buf)
{
if (!buf->virt || !buf->dev)
return;
dma_free_coherent(buf->dev, buf->length, buf->virt, buf->phys);
buf->virt = NULL;
buf->phys = 0;
buf->length = 0;
buf->bytesused = 0;
buf->dev = NULL;
}
int vpu_alloc_dma(struct vpu_core *core, struct vpu_buffer *buf)
{
return __vpu_alloc_dma(core->dev, buf);
}
void vpu_core_set_state(struct vpu_core *core, enum vpu_core_state state)
{
if (state != core->state)
vpu_trace(core->dev, "vpu core state change from %d to %d\n", core->state, state);
core->state = state;
if (core->state == VPU_CORE_DEINIT)
core->hang_mask = 0;
}
static void vpu_core_update_state(struct vpu_core *core)
{
if (!vpu_iface_get_power_state(core)) {
if (core->request_count)
vpu_core_set_state(core, VPU_CORE_HANG);
else
vpu_core_set_state(core, VPU_CORE_DEINIT);
} else if (core->state == VPU_CORE_ACTIVE && core->hang_mask) {
vpu_core_set_state(core, VPU_CORE_HANG);
}
}
static struct vpu_core *vpu_core_find_proper_by_type(struct vpu_dev *vpu, u32 type)
{
struct vpu_core *core = NULL;
int request_count = INT_MAX;
struct vpu_core *c;
list_for_each_entry(c, &vpu->cores, list) {
dev_dbg(c->dev, "instance_mask = 0x%lx, state = %d\n", c->instance_mask, c->state);
if (c->type != type)
continue;
mutex_lock(&c->lock);
vpu_core_update_state(c);
mutex_unlock(&c->lock);
if (c->state == VPU_CORE_DEINIT) {
core = c;
break;
}
if (c->state != VPU_CORE_ACTIVE)
continue;
if (c->request_count < request_count) {
request_count = c->request_count;
core = c;
}
if (!request_count)
break;
}
return core;
}
static bool vpu_core_is_exist(struct vpu_dev *vpu, struct vpu_core *core)
{
struct vpu_core *c;
list_for_each_entry(c, &vpu->cores, list) {
if (c == core)
return true;
}
return false;
}
static void vpu_core_get_vpu(struct vpu_core *core)
{
core->vpu->get_vpu(core->vpu);
if (core->type == VPU_CORE_TYPE_ENC)
core->vpu->get_enc(core->vpu);
if (core->type == VPU_CORE_TYPE_DEC)
core->vpu->get_dec(core->vpu);
}
static int vpu_core_register(struct device *dev, struct vpu_core *core)
{
struct vpu_dev *vpu = dev_get_drvdata(dev);
int ret = 0;
dev_dbg(core->dev, "register core %s\n", vpu_core_type_desc(core->type));
if (vpu_core_is_exist(vpu, core))
return 0;
core->workqueue = alloc_ordered_workqueue("vpu", WQ_MEM_RECLAIM);
if (!core->workqueue) {
dev_err(core->dev, "fail to alloc workqueue\n");
return -ENOMEM;
}
INIT_WORK(&core->msg_work, vpu_msg_run_work);
INIT_DELAYED_WORK(&core->msg_delayed_work, vpu_msg_delayed_work);
core->msg_buffer_size = roundup_pow_of_two(VPU_MSG_BUFFER_SIZE);
core->msg_buffer = vzalloc(core->msg_buffer_size);
if (!core->msg_buffer) {
dev_err(core->dev, "failed allocate buffer for fifo\n");
ret = -ENOMEM;
goto error;
}
ret = kfifo_init(&core->msg_fifo, core->msg_buffer, core->msg_buffer_size);
if (ret) {
dev_err(core->dev, "failed init kfifo\n");
goto error;
}
list_add_tail(&core->list, &vpu->cores);
vpu_core_get_vpu(core);
return 0;
error:
if (core->msg_buffer) {
vfree(core->msg_buffer);
core->msg_buffer = NULL;
}
if (core->workqueue) {
destroy_workqueue(core->workqueue);
core->workqueue = NULL;
}
return ret;
}
static void vpu_core_put_vpu(struct vpu_core *core)
{
if (core->type == VPU_CORE_TYPE_ENC)
core->vpu->put_enc(core->vpu);
if (core->type == VPU_CORE_TYPE_DEC)
core->vpu->put_dec(core->vpu);
core->vpu->put_vpu(core->vpu);
}
static int vpu_core_unregister(struct device *dev, struct vpu_core *core)
{
list_del_init(&core->list);
vpu_core_put_vpu(core);
core->vpu = NULL;
vfree(core->msg_buffer);
core->msg_buffer = NULL;
if (core->workqueue) {
cancel_work_sync(&core->msg_work);
cancel_delayed_work_sync(&core->msg_delayed_work);
destroy_workqueue(core->workqueue);
core->workqueue = NULL;
}
return 0;
}
static int vpu_core_acquire_instance(struct vpu_core *core)
{
int id;
id = ffz(core->instance_mask);
if (id >= core->supported_instance_count)
return -EINVAL;
set_bit(id, &core->instance_mask);
return id;
}
static void vpu_core_release_instance(struct vpu_core *core, int id)
{
if (id < 0 || id >= core->supported_instance_count)
return;
clear_bit(id, &core->instance_mask);
}
struct vpu_inst *vpu_inst_get(struct vpu_inst *inst)
{
if (!inst)
return NULL;
atomic_inc(&inst->ref_count);
return inst;
}
void vpu_inst_put(struct vpu_inst *inst)
{
if (!inst)
return;
if (atomic_dec_and_test(&inst->ref_count)) {
if (inst->release)
inst->release(inst);
}
}
struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type)
{
struct vpu_core *core = NULL;
int ret;
mutex_lock(&vpu->lock);
core = vpu_core_find_proper_by_type(vpu, type);
if (!core)
goto exit;
mutex_lock(&core->lock);
pm_runtime_resume_and_get(core->dev);
if (core->state == VPU_CORE_DEINIT) {
if (vpu_iface_get_power_state(core))
ret = vpu_core_restore(core);
else
ret = vpu_core_boot(core, true);
if (ret) {
pm_runtime_put_sync(core->dev);
mutex_unlock(&core->lock);
core = NULL;
goto exit;
}
}
core->request_count++;
mutex_unlock(&core->lock);
exit:
mutex_unlock(&vpu->lock);
return core;
}
void vpu_release_core(struct vpu_core *core)
{
if (!core)
return;
mutex_lock(&core->lock);
pm_runtime_put_sync(core->dev);
if (core->request_count)
core->request_count--;
mutex_unlock(&core->lock);
}
int vpu_inst_register(struct vpu_inst *inst)
{
struct vpu_dev *vpu;
struct vpu_core *core;
int ret = 0;
vpu = inst->vpu;
core = inst->core;
if (!core) {
core = vpu_request_core(vpu, inst->type);
if (!core) {
dev_err(vpu->dev, "there is no vpu core for %s\n",
vpu_core_type_desc(inst->type));
return -EINVAL;
}
inst->core = core;
inst->dev = get_device(core->dev);
}
mutex_lock(&core->lock);
if (core->state != VPU_CORE_ACTIVE) {
dev_err(core->dev, "vpu core is not active, state = %d\n", core->state);
ret = -EINVAL;
goto exit;
}
if (inst->id >= 0 && inst->id < core->supported_instance_count)
goto exit;
ret = vpu_core_acquire_instance(core);
if (ret < 0)
goto exit;
vpu_trace(inst->dev, "[%d] %p\n", ret, inst);
inst->id = ret;
list_add_tail(&inst->list, &core->instances);
ret = 0;
if (core->res->act_size) {
inst->act.phys = core->act.phys + core->res->act_size * inst->id;
inst->act.virt = core->act.virt + core->res->act_size * inst->id;
inst->act.length = core->res->act_size;
}
vpu_inst_create_dbgfs_file(inst);
exit:
mutex_unlock(&core->lock);
if (ret)
dev_err(core->dev, "register instance fail\n");
return ret;
}
int vpu_inst_unregister(struct vpu_inst *inst)
{
struct vpu_core *core;
if (!inst->core)
return 0;
core = inst->core;
vpu_clear_request(inst);
mutex_lock(&core->lock);
if (inst->id >= 0 && inst->id < core->supported_instance_count) {
vpu_inst_remove_dbgfs_file(inst);
list_del_init(&inst->list);
vpu_core_release_instance(core, inst->id);
inst->id = VPU_INST_NULL_ID;
}
vpu_core_update_state(core);
if (core->state == VPU_CORE_HANG && !core->instance_mask) {
int err;
dev_info(core->dev, "reset hang core\n");
mutex_unlock(&core->lock);
err = vpu_core_sw_reset(core);
mutex_lock(&core->lock);
if (!err) {
vpu_core_set_state(core, VPU_CORE_ACTIVE);
core->hang_mask = 0;
}
}
mutex_unlock(&core->lock);
return 0;
}
struct vpu_inst *vpu_core_find_instance(struct vpu_core *core, u32 index)
{
struct vpu_inst *inst = NULL;
struct vpu_inst *tmp;
mutex_lock(&core->lock);
if (index >= core->supported_instance_count || !test_bit(index, &core->instance_mask))
goto exit;
list_for_each_entry(tmp, &core->instances, list) {
if (tmp->id == index) {
inst = vpu_inst_get(tmp);
break;
}
}
exit:
mutex_unlock(&core->lock);
return inst;
}
const struct vpu_core_resources *vpu_get_resource(struct vpu_inst *inst)
{
struct vpu_dev *vpu;
struct vpu_core *core = NULL;
const struct vpu_core_resources *res = NULL;
if (!inst || !inst->vpu)
return NULL;
if (inst->core && inst->core->res)
return inst->core->res;
vpu = inst->vpu;
mutex_lock(&vpu->lock);
list_for_each_entry(core, &vpu->cores, list) {
if (core->type == inst->type) {
res = core->res;
break;
}
}
mutex_unlock(&vpu->lock);
return res;
}
static int vpu_core_parse_dt(struct vpu_core *core, struct device_node *np)
{
struct device_node *node;
struct resource res;
int ret;
if (of_count_phandle_with_args(np, "memory-region", NULL) < 2) {
dev_err(core->dev, "need 2 memory-region for boot and rpc\n");
return -ENODEV;
}
node = of_parse_phandle(np, "memory-region", 0);
if (!node) {
dev_err(core->dev, "boot-region of_parse_phandle error\n");
return -ENODEV;
}
if (of_address_to_resource(node, 0, &res)) {
dev_err(core->dev, "boot-region of_address_to_resource error\n");
of_node_put(node);
return -EINVAL;
}
core->fw.phys = res.start;
core->fw.length = resource_size(&res);
of_node_put(node);
node = of_parse_phandle(np, "memory-region", 1);
if (!node) {
dev_err(core->dev, "rpc-region of_parse_phandle error\n");
return -ENODEV;
}
if (of_address_to_resource(node, 0, &res)) {
dev_err(core->dev, "rpc-region of_address_to_resource error\n");
of_node_put(node);
return -EINVAL;
}
core->rpc.phys = res.start;
core->rpc.length = resource_size(&res);
if (core->rpc.length < core->res->rpc_size + core->res->fwlog_size) {
dev_err(core->dev, "the rpc-region <%pad, 0x%x> is not enough\n",
&core->rpc.phys, core->rpc.length);
of_node_put(node);
return -EINVAL;
}
core->fw.virt = memremap(core->fw.phys, core->fw.length, MEMREMAP_WC);
core->rpc.virt = memremap(core->rpc.phys, core->rpc.length, MEMREMAP_WC);
memset(core->rpc.virt, 0, core->rpc.length);
ret = vpu_iface_check_memory_region(core, core->rpc.phys, core->rpc.length);
if (ret != VPU_CORE_MEMORY_UNCACHED) {
dev_err(core->dev, "rpc region<%pad, 0x%x> isn't uncached\n",
&core->rpc.phys, core->rpc.length);
of_node_put(node);
return -EINVAL;
}
core->log.phys = core->rpc.phys + core->res->rpc_size;
core->log.virt = core->rpc.virt + core->res->rpc_size;
core->log.length = core->res->fwlog_size;
core->act.phys = core->log.phys + core->log.length;
core->act.virt = core->log.virt + core->log.length;
core->act.length = core->rpc.length - core->res->rpc_size - core->log.length;
core->rpc.length = core->res->rpc_size;
of_node_put(node);
return 0;
}
static int vpu_core_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct vpu_core *core;
struct vpu_dev *vpu = dev_get_drvdata(dev->parent);
struct vpu_shared_addr *iface;
u32 iface_data_size;
int ret;
dev_dbg(dev, "probe\n");
if (!vpu)
return -EINVAL;
core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
if (!core)
return -ENOMEM;
core->pdev = pdev;
core->dev = dev;
platform_set_drvdata(pdev, core);
core->vpu = vpu;
INIT_LIST_HEAD(&core->instances);
mutex_init(&core->lock);
mutex_init(&core->cmd_lock);
init_completion(&core->cmp);
init_waitqueue_head(&core->ack_wq);
vpu_core_set_state(core, VPU_CORE_DEINIT);
core->res = of_device_get_match_data(dev);
if (!core->res)
return -ENODEV;
core->type = core->res->type;
core->id = of_alias_get_id(dev->of_node, "vpu_core");
if (core->id < 0) {
dev_err(dev, "can't get vpu core id\n");
return core->id;
}
dev_info(core->dev, "[%d] = %s\n", core->id, vpu_core_type_desc(core->type));
ret = vpu_core_parse_dt(core, dev->of_node);
if (ret)
return ret;
core->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(core->base))
return PTR_ERR(core->base);
if (!vpu_iface_check_codec(core)) {
dev_err(core->dev, "is not supported\n");
return -EINVAL;
}
ret = vpu_mbox_init(core);
if (ret)
return ret;
iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
if (!iface)
return -ENOMEM;
iface_data_size = vpu_iface_get_data_size(core);
if (iface_data_size) {
iface->priv = devm_kzalloc(dev, iface_data_size, GFP_KERNEL);
if (!iface->priv)
return -ENOMEM;
}
ret = vpu_iface_init(core, iface, &core->rpc, core->fw.phys);
if (ret) {
dev_err(core->dev, "init iface fail, ret = %d\n", ret);
return ret;
}
vpu_iface_config_system(core, vpu->res->mreg_base, vpu->base);
vpu_iface_set_log_buf(core, &core->log);
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret) {
pm_runtime_put_noidle(dev);
pm_runtime_set_suspended(dev);
goto err_runtime_disable;
}
ret = vpu_core_register(dev->parent, core);
if (ret)
goto err_core_register;
core->parent = dev->parent;
pm_runtime_put_sync(dev);
vpu_core_create_dbgfs_file(core);
return 0;
err_core_register:
pm_runtime_put_sync(dev);
err_runtime_disable:
pm_runtime_disable(dev);
return ret;
}
static void vpu_core_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct vpu_core *core = platform_get_drvdata(pdev);
int ret;
vpu_core_remove_dbgfs_file(core);
ret = pm_runtime_resume_and_get(dev);
WARN_ON(ret < 0);
vpu_core_shutdown(core);
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
vpu_core_unregister(core->parent, core);
memunmap(core->fw.virt);
memunmap(core->rpc.virt);
mutex_destroy(&core->lock);
mutex_destroy(&core->cmd_lock);
}
static int __maybe_unused vpu_core_runtime_resume(struct device *dev)
{
struct vpu_core *core = dev_get_drvdata(dev);
return vpu_mbox_request(core);
}
static int __maybe_unused vpu_core_runtime_suspend(struct device *dev)
{
struct vpu_core *core = dev_get_drvdata(dev);
vpu_mbox_free(core);
return 0;
}
static void vpu_core_cancel_work(struct vpu_core *core)
{
struct vpu_inst *inst = NULL;
cancel_work_sync(&core->msg_work);
cancel_delayed_work_sync(&core->msg_delayed_work);
mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list)
cancel_work_sync(&inst->msg_work);
mutex_unlock(&core->lock);
}
static void vpu_core_resume_work(struct vpu_core *core)
{
struct vpu_inst *inst = NULL;
unsigned long delay = msecs_to_jiffies(10);
queue_work(core->workqueue, &core->msg_work);
queue_delayed_work(core->workqueue, &core->msg_delayed_work, delay);
mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list)
queue_work(inst->workqueue, &inst->msg_work);
mutex_unlock(&core->lock);
}
static int __maybe_unused vpu_core_resume(struct device *dev)
{
struct vpu_core *core = dev_get_drvdata(dev);
int ret = 0;
mutex_lock(&core->lock);
pm_runtime_resume_and_get(dev);
vpu_core_get_vpu(core);
if (core->request_count) {
if (!vpu_iface_get_power_state(core))
ret = vpu_core_boot(core, false);
else
ret = vpu_core_sw_reset(core);
if (ret) {
dev_err(core->dev, "resume fail\n");
vpu_core_set_state(core, VPU_CORE_HANG);
}
}
vpu_core_update_state(core);
pm_runtime_put_sync(dev);
mutex_unlock(&core->lock);
vpu_core_resume_work(core);
return ret;
}
static int __maybe_unused vpu_core_suspend(struct device *dev)
{
struct vpu_core *core = dev_get_drvdata(dev);
int ret = 0;
mutex_lock(&core->lock);
if (core->request_count)
ret = vpu_core_snapshot(core);
mutex_unlock(&core->lock);
if (ret)
return ret;
vpu_core_cancel_work(core);
mutex_lock(&core->lock);
vpu_core_put_vpu(core);
mutex_unlock(&core->lock);
return ret;
}
static const struct dev_pm_ops vpu_core_pm_ops = {
SET_RUNTIME_PM_OPS(vpu_core_runtime_suspend, vpu_core_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(vpu_core_suspend, vpu_core_resume)
};
static struct vpu_core_resources imx8q_enc = {
.type = VPU_CORE_TYPE_ENC,
.fwname = "amphion/vpu/vpu_fw_imx8_enc.bin",
.stride = 16,
.max_width = 1920,
.max_height = 1920,
.min_width = 64,
.min_height = 48,
.step_width = 2,
.step_height = 2,
.rpc_size = 0x80000,
.fwlog_size = 0x80000,
.act_size = 0xc0000,
};
static struct vpu_core_resources imx8q_dec = {
.type = VPU_CORE_TYPE_DEC,
.fwname = "amphion/vpu/vpu_fw_imx8_dec.bin",
.stride = 256,
.max_width = 8188,
.max_height = 8188,
.min_width = 16,
.min_height = 16,
.step_width = 1,
.step_height = 1,
.rpc_size = 0x80000,
.fwlog_size = 0x80000,
};
static const struct of_device_id vpu_core_dt_match[] = {
{ .compatible = "nxp,imx8q-vpu-encoder", .data = &imx8q_enc },
{ .compatible = "nxp,imx8q-vpu-decoder", .data = &imx8q_dec },
{}
};
MODULE_DEVICE_TABLE(of, vpu_core_dt_match);
static struct platform_driver amphion_vpu_core_driver = {
.probe = vpu_core_probe,
.remove_new = vpu_core_remove,
.driver = {
.name = "amphion-vpu-core",
.of_match_table = vpu_core_dt_match,
.pm = &vpu_core_pm_ops,
},
};
int __init vpu_core_driver_init(void)
{
return platform_driver_register(&hion_vpu_core_driver);
}
void __exit vpu_core_driver_exit(void)
{
platform_driver_unregister(&hion_vpu_core_driver);
}
| linux-master | drivers/media/platform/amphion/vpu_core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include "vpu.h"
#include "vpu_helpers.h"
static const u8 colorprimaries[] = {
V4L2_COLORSPACE_LAST,
V4L2_COLORSPACE_REC709, /*Rec. ITU-R BT.709-6*/
0,
0,
V4L2_COLORSPACE_470_SYSTEM_M, /*Rec. ITU-R BT.470-6 System M*/
V4L2_COLORSPACE_470_SYSTEM_BG, /*Rec. ITU-R BT.470-6 System B, G*/
V4L2_COLORSPACE_SMPTE170M, /*SMPTE170M*/
V4L2_COLORSPACE_SMPTE240M, /*SMPTE240M*/
0, /*Generic film*/
V4L2_COLORSPACE_BT2020, /*Rec. ITU-R BT.2020-2*/
0, /*SMPTE ST 428-1*/
};
static const u8 colortransfers[] = {
V4L2_XFER_FUNC_LAST,
V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.709-6*/
0,
0,
0, /*Rec. ITU-R BT.470-6 System M*/
0, /*Rec. ITU-R BT.470-6 System B, G*/
V4L2_XFER_FUNC_709, /*SMPTE170M*/
V4L2_XFER_FUNC_SMPTE240M, /*SMPTE240M*/
V4L2_XFER_FUNC_NONE, /*Linear transfer characteristics*/
0,
0,
0, /*IEC 61966-2-4*/
0, /*Rec. ITU-R BT.1361-0 extended colour gamut*/
V4L2_XFER_FUNC_SRGB, /*IEC 61966-2-1 sRGB or sYCC*/
V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.2020-2 (10 bit system)*/
V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.2020-2 (12 bit system)*/
V4L2_XFER_FUNC_SMPTE2084, /*SMPTE ST 2084*/
0, /*SMPTE ST 428-1*/
0 /*Rec. ITU-R BT.2100-0 hybrid log-gamma (HLG)*/
};
static const u8 colormatrixcoefs[] = {
V4L2_YCBCR_ENC_LAST,
V4L2_YCBCR_ENC_709, /*Rec. ITU-R BT.709-6*/
0,
0,
0, /*Title 47 Code of Federal Regulations*/
V4L2_YCBCR_ENC_601, /*Rec. ITU-R BT.601-7 625*/
V4L2_YCBCR_ENC_601, /*Rec. ITU-R BT.601-7 525*/
V4L2_YCBCR_ENC_SMPTE240M, /*SMPTE240M*/
0,
V4L2_YCBCR_ENC_BT2020, /*Rec. ITU-R BT.2020-2*/
V4L2_YCBCR_ENC_BT2020_CONST_LUM /*Rec. ITU-R BT.2020-2 constant*/
};
u32 vpu_color_cvrt_primaries_v2i(u32 primaries)
{
return vpu_helper_find_in_array_u8(colorprimaries, ARRAY_SIZE(colorprimaries), primaries);
}
u32 vpu_color_cvrt_primaries_i2v(u32 primaries)
{
return primaries < ARRAY_SIZE(colorprimaries) ? colorprimaries[primaries] : 0;
}
u32 vpu_color_cvrt_transfers_v2i(u32 transfers)
{
return vpu_helper_find_in_array_u8(colortransfers, ARRAY_SIZE(colortransfers), transfers);
}
u32 vpu_color_cvrt_transfers_i2v(u32 transfers)
{
return transfers < ARRAY_SIZE(colortransfers) ? colortransfers[transfers] : 0;
}
u32 vpu_color_cvrt_matrix_v2i(u32 matrix)
{
return vpu_helper_find_in_array_u8(colormatrixcoefs, ARRAY_SIZE(colormatrixcoefs), matrix);
}
u32 vpu_color_cvrt_matrix_i2v(u32 matrix)
{
return matrix < ARRAY_SIZE(colormatrixcoefs) ? colormatrixcoefs[matrix] : 0;
}
u32 vpu_color_cvrt_full_range_v2i(u32 full_range)
{
return (full_range == V4L2_QUANTIZATION_FULL_RANGE);
}
u32 vpu_color_cvrt_full_range_i2v(u32 full_range)
{
if (full_range)
return V4L2_QUANTIZATION_FULL_RANGE;
return V4L2_QUANTIZATION_LIM_RANGE;
}
int vpu_color_check_primaries(u32 primaries)
{
return vpu_color_cvrt_primaries_v2i(primaries) ? 0 : -EINVAL;
}
int vpu_color_check_transfers(u32 transfers)
{
return vpu_color_cvrt_transfers_v2i(transfers) ? 0 : -EINVAL;
}
int vpu_color_check_matrix(u32 matrix)
{
return vpu_color_cvrt_matrix_v2i(matrix) ? 0 : -EINVAL;
}
int vpu_color_check_full_range(u32 full_range)
{
int ret = -EINVAL;
switch (full_range) {
case V4L2_QUANTIZATION_FULL_RANGE:
case V4L2_QUANTIZATION_LIM_RANGE:
ret = 0;
break;
default:
break;
}
return ret;
}
int vpu_color_get_default(u32 primaries, u32 *ptransfers, u32 *pmatrix, u32 *pfull_range)
{
u32 transfers;
u32 matrix;
u32 full_range;
switch (primaries) {
case V4L2_COLORSPACE_REC709:
transfers = V4L2_XFER_FUNC_709;
matrix = V4L2_YCBCR_ENC_709;
break;
case V4L2_COLORSPACE_470_SYSTEM_M:
case V4L2_COLORSPACE_470_SYSTEM_BG:
case V4L2_COLORSPACE_SMPTE170M:
transfers = V4L2_XFER_FUNC_709;
matrix = V4L2_YCBCR_ENC_601;
break;
case V4L2_COLORSPACE_SMPTE240M:
transfers = V4L2_XFER_FUNC_SMPTE240M;
matrix = V4L2_YCBCR_ENC_SMPTE240M;
break;
case V4L2_COLORSPACE_BT2020:
transfers = V4L2_XFER_FUNC_709;
matrix = V4L2_YCBCR_ENC_BT2020;
break;
default:
transfers = V4L2_XFER_FUNC_DEFAULT;
matrix = V4L2_YCBCR_ENC_DEFAULT;
break;
}
full_range = V4L2_QUANTIZATION_LIM_RANGE;
if (ptransfers)
*ptransfers = transfers;
if (pmatrix)
*pmatrix = matrix;
if (pfull_range)
*pfull_range = full_range;
return 0;
}
| linux-master | drivers/media/platform/amphion/vpu_color.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_cmds.h"
#include "vpu_rpc.h"
#include "vpu_mbox.h"
struct vpu_cmd_request {
u32 request;
u32 response;
u32 handled;
};
struct vpu_cmd_t {
struct list_head list;
u32 id;
struct vpu_cmd_request *request;
struct vpu_rpc_event *pkt;
unsigned long key;
};
static struct vpu_cmd_request vpu_cmd_requests[] = {
{
.request = VPU_CMD_ID_CONFIGURE_CODEC,
.response = VPU_MSG_ID_MEM_REQUEST,
.handled = 1,
},
{
.request = VPU_CMD_ID_START,
.response = VPU_MSG_ID_START_DONE,
.handled = 0,
},
{
.request = VPU_CMD_ID_STOP,
.response = VPU_MSG_ID_STOP_DONE,
.handled = 0,
},
{
.request = VPU_CMD_ID_ABORT,
.response = VPU_MSG_ID_ABORT_DONE,
.handled = 0,
},
{
.request = VPU_CMD_ID_RST_BUF,
.response = VPU_MSG_ID_BUF_RST,
.handled = 1,
},
};
static int vpu_cmd_send(struct vpu_core *core, struct vpu_rpc_event *pkt)
{
int ret = 0;
ret = vpu_iface_send_cmd(core, pkt);
if (ret)
return ret;
/*write cmd data to cmd buffer before trigger a cmd interrupt*/
mb();
vpu_mbox_send_type(core, COMMAND);
return ret;
}
static struct vpu_cmd_t *vpu_alloc_cmd(struct vpu_inst *inst, u32 id, void *data)
{
struct vpu_cmd_t *cmd;
int i;
int ret;
cmd = vzalloc(sizeof(*cmd));
if (!cmd)
return NULL;
cmd->pkt = vzalloc(sizeof(*cmd->pkt));
if (!cmd->pkt) {
vfree(cmd);
return NULL;
}
cmd->id = id;
ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data);
if (ret) {
dev_err(inst->dev, "iface pack cmd %s fail\n", vpu_id_name(id));
vfree(cmd->pkt);
vfree(cmd);
return NULL;
}
for (i = 0; i < ARRAY_SIZE(vpu_cmd_requests); i++) {
if (vpu_cmd_requests[i].request == id) {
cmd->request = &vpu_cmd_requests[i];
break;
}
}
return cmd;
}
static void vpu_free_cmd(struct vpu_cmd_t *cmd)
{
if (!cmd)
return;
vfree(cmd->pkt);
vfree(cmd);
}
static int vpu_session_process_cmd(struct vpu_inst *inst, struct vpu_cmd_t *cmd)
{
int ret;
dev_dbg(inst->dev, "[%d]send cmd %s\n", inst->id, vpu_id_name(cmd->id));
vpu_iface_pre_send_cmd(inst);
ret = vpu_cmd_send(inst->core, cmd->pkt);
if (!ret) {
vpu_iface_post_send_cmd(inst);
vpu_inst_record_flow(inst, cmd->id);
} else {
dev_err(inst->dev, "[%d] iface send cmd %s fail\n", inst->id, vpu_id_name(cmd->id));
}
return ret;
}
static void vpu_process_cmd_request(struct vpu_inst *inst)
{
struct vpu_cmd_t *cmd;
struct vpu_cmd_t *tmp;
if (!inst || inst->pending)
return;
list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) {
list_del_init(&cmd->list);
if (vpu_session_process_cmd(inst, cmd))
dev_err(inst->dev, "[%d] process cmd %s fail\n",
inst->id, vpu_id_name(cmd->id));
if (cmd->request) {
inst->pending = (void *)cmd;
break;
}
vpu_free_cmd(cmd);
}
}
static int vpu_request_cmd(struct vpu_inst *inst, u32 id, void *data,
unsigned long *key, int *sync)
{
struct vpu_core *core;
struct vpu_cmd_t *cmd;
if (!inst || !inst->core)
return -EINVAL;
core = inst->core;
cmd = vpu_alloc_cmd(inst, id, data);
if (!cmd)
return -ENOMEM;
mutex_lock(&core->cmd_lock);
cmd->key = core->cmd_seq++;
if (key)
*key = cmd->key;
if (sync)
*sync = cmd->request ? true : false;
list_add_tail(&cmd->list, &inst->cmd_q);
vpu_process_cmd_request(inst);
mutex_unlock(&core->cmd_lock);
return 0;
}
static void vpu_clear_pending(struct vpu_inst *inst)
{
if (!inst || !inst->pending)
return;
vpu_free_cmd(inst->pending);
wake_up_all(&inst->core->ack_wq);
inst->pending = NULL;
}
static bool vpu_check_response(struct vpu_cmd_t *cmd, u32 response, u32 handled)
{
struct vpu_cmd_request *request;
if (!cmd || !cmd->request)
return false;
request = cmd->request;
if (request->response != response)
return false;
if (request->handled != handled)
return false;
return true;
}
int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled)
{
struct vpu_core *core;
if (!inst || !inst->core)
return -EINVAL;
core = inst->core;
mutex_lock(&core->cmd_lock);
if (vpu_check_response(inst->pending, response, handled))
vpu_clear_pending(inst);
vpu_process_cmd_request(inst);
mutex_unlock(&core->cmd_lock);
return 0;
}
void vpu_clear_request(struct vpu_inst *inst)
{
struct vpu_cmd_t *cmd;
struct vpu_cmd_t *tmp;
mutex_lock(&inst->core->cmd_lock);
if (inst->pending)
vpu_clear_pending(inst);
list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) {
list_del_init(&cmd->list);
vpu_free_cmd(cmd);
}
mutex_unlock(&inst->core->cmd_lock);
}
static bool check_is_responsed(struct vpu_inst *inst, unsigned long key)
{
struct vpu_core *core = inst->core;
struct vpu_cmd_t *cmd;
bool flag = true;
mutex_lock(&core->cmd_lock);
cmd = inst->pending;
if (cmd && key == cmd->key) {
flag = false;
goto exit;
}
list_for_each_entry(cmd, &inst->cmd_q, list) {
if (key == cmd->key) {
flag = false;
break;
}
}
exit:
mutex_unlock(&core->cmd_lock);
return flag;
}
static int sync_session_response(struct vpu_inst *inst, unsigned long key, long timeout, int try)
{
struct vpu_core *core;
if (!inst || !inst->core)
return -EINVAL;
core = inst->core;
call_void_vop(inst, wait_prepare);
wait_event_timeout(core->ack_wq, check_is_responsed(inst, key), timeout);
call_void_vop(inst, wait_finish);
if (!check_is_responsed(inst, key)) {
if (try)
return -EINVAL;
dev_err(inst->dev, "[%d] sync session timeout\n", inst->id);
set_bit(inst->id, &core->hang_mask);
mutex_lock(&inst->core->cmd_lock);
vpu_clear_pending(inst);
mutex_unlock(&inst->core->cmd_lock);
return -EINVAL;
}
return 0;
}
static void vpu_core_keep_active(struct vpu_core *core)
{
struct vpu_rpc_event pkt;
memset(&pkt, 0, sizeof(pkt));
vpu_iface_pack_cmd(core, &pkt, 0, VPU_CMD_ID_NOOP, NULL);
dev_dbg(core->dev, "try to wake up\n");
mutex_lock(&core->cmd_lock);
if (vpu_cmd_send(core, &pkt))
dev_err(core->dev, "fail to keep active\n");
mutex_unlock(&core->cmd_lock);
}
static int vpu_session_send_cmd(struct vpu_inst *inst, u32 id, void *data)
{
unsigned long key;
int sync = false;
int ret;
if (inst->id < 0)
return -EINVAL;
ret = vpu_request_cmd(inst, id, data, &key, &sync);
if (ret)
goto exit;
/* workaround for a firmware issue,
* firmware should be waked up by start or configure command,
* but there is a very small change that firmware failed to wakeup.
* in such case, try to wakeup firmware again by sending a noop command
*/
if (sync && (id == VPU_CMD_ID_CONFIGURE_CODEC || id == VPU_CMD_ID_START)) {
if (sync_session_response(inst, key, VPU_TIMEOUT_WAKEUP, 1))
vpu_core_keep_active(inst->core);
else
goto exit;
}
if (sync)
ret = sync_session_response(inst, key, VPU_TIMEOUT, 0);
exit:
if (ret)
dev_err(inst->dev, "[%d] send cmd %s fail\n", inst->id, vpu_id_name(id));
return ret;
}
int vpu_session_configure_codec(struct vpu_inst *inst)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_CONFIGURE_CODEC, NULL);
}
int vpu_session_start(struct vpu_inst *inst)
{
vpu_trace(inst->dev, "[%d]\n", inst->id);
return vpu_session_send_cmd(inst, VPU_CMD_ID_START, NULL);
}
int vpu_session_stop(struct vpu_inst *inst)
{
int ret;
vpu_trace(inst->dev, "[%d]\n", inst->id);
ret = vpu_session_send_cmd(inst, VPU_CMD_ID_STOP, NULL);
/* workaround for a firmware bug,
* if the next command is too close after stop cmd,
* the firmware may enter wfi wrongly.
*/
usleep_range(3000, 5000);
return ret;
}
int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_FRAME_ENCODE, ×tamp);
}
int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_ALLOC, fs);
}
int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_RELEASE, fs);
}
int vpu_session_abort(struct vpu_inst *inst)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_ABORT, NULL);
}
int vpu_session_rst_buf(struct vpu_inst *inst)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_RST_BUF, NULL);
}
int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_TIMESTAMP, info);
}
int vpu_session_update_parameters(struct vpu_inst *inst, void *arg)
{
if (inst->type & VPU_CORE_TYPE_DEC)
vpu_iface_set_decode_params(inst, arg, 1);
else
vpu_iface_set_encode_params(inst, arg, 1);
return vpu_session_send_cmd(inst, VPU_CMD_ID_UPDATE_PARAMETER, arg);
}
int vpu_session_debug(struct vpu_inst *inst)
{
return vpu_session_send_cmd(inst, VPU_CMD_ID_DEBUG, NULL);
}
int vpu_core_snapshot(struct vpu_core *core)
{
struct vpu_inst *inst;
int ret;
if (!core || list_empty(&core->instances))
return 0;
inst = list_first_entry(&core->instances, struct vpu_inst, list);
reinit_completion(&core->cmp);
ret = vpu_session_send_cmd(inst, VPU_CMD_ID_SNAPSHOT, NULL);
if (ret)
return ret;
ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT);
if (!ret) {
dev_err(core->dev, "snapshot timeout\n");
return -EINVAL;
}
return 0;
}
int vpu_core_sw_reset(struct vpu_core *core)
{
struct vpu_rpc_event pkt;
int ret;
memset(&pkt, 0, sizeof(pkt));
vpu_iface_pack_cmd(core, &pkt, 0, VPU_CMD_ID_FIRM_RESET, NULL);
reinit_completion(&core->cmp);
mutex_lock(&core->cmd_lock);
ret = vpu_cmd_send(core, &pkt);
mutex_unlock(&core->cmd_lock);
if (ret)
return ret;
ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT);
if (!ret) {
dev_err(core->dev, "sw reset timeout\n");
return -EINVAL;
}
return 0;
}
| linux-master | drivers/media/platform/amphion/vpu_cmds.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/ktime.h>
#include <linux/rational.h>
#include <linux/vmalloc.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-vmalloc.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_core.h"
#include "vpu_helpers.h"
#include "vpu_v4l2.h"
#include "vpu_cmds.h"
#include "vpu_rpc.h"
#define VENC_OUTPUT_ENABLE BIT(0)
#define VENC_CAPTURE_ENABLE BIT(1)
#define VENC_ENABLE_MASK (VENC_OUTPUT_ENABLE | VENC_CAPTURE_ENABLE)
#define VENC_MAX_BUF_CNT 8
#define VENC_MIN_BUFFER_OUT 6
#define VENC_MIN_BUFFER_CAP 6
struct venc_t {
struct vpu_encode_params params;
u32 request_key_frame;
u32 input_ready;
u32 cpb_size;
bool bitrate_change;
struct vpu_buffer enc[VENC_MAX_BUF_CNT];
struct vpu_buffer ref[VENC_MAX_BUF_CNT];
struct vpu_buffer act[VENC_MAX_BUF_CNT];
struct list_head frames;
u32 frame_count;
u32 encode_count;
u32 ready_count;
u32 enable;
u32 stopped;
u32 skipped_count;
u32 skipped_bytes;
wait_queue_head_t wq;
};
struct venc_frame_t {
struct list_head list;
struct vpu_enc_pic_info info;
u32 bytesused;
s64 timestamp;
};
static const struct vpu_format venc_formats[] = {
{
.pixfmt = V4L2_PIX_FMT_NV12M,
.mem_planes = 2,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.sibling = V4L2_PIX_FMT_NV12,
},
{
.pixfmt = V4L2_PIX_FMT_NV12,
.mem_planes = 1,
.comp_planes = 2,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.sibling = V4L2_PIX_FMT_NV12M,
},
{
.pixfmt = V4L2_PIX_FMT_H264,
.mem_planes = 1,
.comp_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
.flags = V4L2_FMT_FLAG_COMPRESSED
},
{0, 0, 0, 0},
};
static int venc_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
{
strscpy(cap->driver, "amphion-vpu", sizeof(cap->driver));
strscpy(cap->card, "amphion vpu encoder", sizeof(cap->card));
strscpy(cap->bus_info, "platform: amphion-vpu", sizeof(cap->bus_info));
return 0;
}
static int venc_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
{
struct vpu_inst *inst = to_inst(file);
const struct vpu_format *fmt;
memset(f->reserved, 0, sizeof(f->reserved));
fmt = vpu_helper_enum_format(inst, f->type, f->index);
if (!fmt)
return -EINVAL;
f->pixelformat = fmt->pixfmt;
f->flags = fmt->flags;
return 0;
}
static int venc_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize)
{
struct vpu_inst *inst = to_inst(file);
const struct vpu_core_resources *res;
if (!fsize || fsize->index)
return -EINVAL;
if (!vpu_helper_find_format(inst, 0, fsize->pixel_format))
return -EINVAL;
res = vpu_get_resource(inst);
if (!res)
return -EINVAL;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise.max_width = res->max_width;
fsize->stepwise.max_height = res->max_height;
fsize->stepwise.min_width = res->min_width;
fsize->stepwise.min_height = res->min_height;
fsize->stepwise.step_width = res->step_width;
fsize->stepwise.step_height = res->step_height;
return 0;
}
static int venc_enum_frameintervals(struct file *file, void *fh, struct v4l2_frmivalenum *fival)
{
struct vpu_inst *inst = to_inst(file);
const struct vpu_core_resources *res;
if (!fival || fival->index)
return -EINVAL;
if (!vpu_helper_find_format(inst, 0, fival->pixel_format))
return -EINVAL;
if (!fival->width || !fival->height)
return -EINVAL;
res = vpu_get_resource(inst);
if (!res)
return -EINVAL;
if (fival->width < res->min_width || fival->width > res->max_width ||
fival->height < res->min_height || fival->height > res->max_height)
return -EINVAL;
fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
fival->stepwise.min.numerator = 1;
fival->stepwise.min.denominator = USHRT_MAX;
fival->stepwise.max.numerator = USHRT_MAX;
fival->stepwise.max.denominator = 1;
fival->stepwise.step.numerator = 1;
fival->stepwise.step.denominator = 1;
return 0;
}
static int venc_g_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct venc_t *venc = inst->priv;
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
struct vpu_format *cur_fmt;
int i;
cur_fmt = vpu_get_format(inst, f->type);
pixmp->pixelformat = cur_fmt->pixfmt;
pixmp->num_planes = cur_fmt->mem_planes;
pixmp->width = cur_fmt->width;
pixmp->height = cur_fmt->height;
pixmp->field = cur_fmt->field;
pixmp->flags = cur_fmt->flags;
for (i = 0; i < pixmp->num_planes; i++) {
pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i];
pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(cur_fmt, i);
}
f->fmt.pix_mp.colorspace = venc->params.color.primaries;
f->fmt.pix_mp.xfer_func = venc->params.color.transfer;
f->fmt.pix_mp.ycbcr_enc = venc->params.color.matrix;
f->fmt.pix_mp.quantization = venc->params.color.full_range;
return 0;
}
static int venc_try_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct vpu_format fmt;
vpu_try_fmt_common(inst, f, &fmt);
return 0;
}
static int venc_s_fmt(struct file *file, void *fh, struct v4l2_format *f)
{
struct vpu_inst *inst = to_inst(file);
struct vpu_format fmt;
struct vpu_format *cur_fmt;
struct vb2_queue *q;
struct venc_t *venc = inst->priv;
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type);
if (!q)
return -EINVAL;
if (vb2_is_busy(q))
return -EBUSY;
if (vpu_try_fmt_common(inst, f, &fmt))
return -EINVAL;
cur_fmt = vpu_get_format(inst, f->type);
memcpy(cur_fmt, &fmt, sizeof(*cur_fmt));
if (V4L2_TYPE_IS_OUTPUT(f->type)) {
venc->params.input_format = cur_fmt->pixfmt;
venc->params.src_stride = cur_fmt->bytesperline[0];
venc->params.src_width = cur_fmt->width;
venc->params.src_height = cur_fmt->height;
venc->params.crop.left = 0;
venc->params.crop.top = 0;
venc->params.crop.width = cur_fmt->width;
venc->params.crop.height = cur_fmt->height;
} else {
venc->params.codec_format = cur_fmt->pixfmt;
venc->params.out_width = cur_fmt->width;
venc->params.out_height = cur_fmt->height;
}
if (V4L2_TYPE_IS_OUTPUT(f->type)) {
venc->params.color.primaries = pix_mp->colorspace;
venc->params.color.transfer = pix_mp->xfer_func;
venc->params.color.matrix = pix_mp->ycbcr_enc;
venc->params.color.full_range = pix_mp->quantization;
}
pix_mp->colorspace = venc->params.color.primaries;
pix_mp->xfer_func = venc->params.color.transfer;
pix_mp->ycbcr_enc = venc->params.color.matrix;
pix_mp->quantization = venc->params.color.full_range;
return 0;
}
static int venc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *parm)
{
struct vpu_inst *inst = to_inst(file);
struct venc_t *venc = inst->priv;
struct v4l2_fract *timeperframe;
if (!parm)
return -EINVAL;
if (!V4L2_TYPE_IS_OUTPUT(parm->type))
return -EINVAL;
if (!vpu_helper_check_type(inst, parm->type))
return -EINVAL;
timeperframe = &parm->parm.capture.timeperframe;
parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
parm->parm.capture.readbuffers = 0;
timeperframe->numerator = venc->params.frame_rate.numerator;
timeperframe->denominator = venc->params.frame_rate.denominator;
return 0;
}
static int venc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *parm)
{
struct vpu_inst *inst = to_inst(file);
struct venc_t *venc = inst->priv;
struct v4l2_fract *timeperframe;
unsigned long n, d;
if (!parm)
return -EINVAL;
if (!V4L2_TYPE_IS_OUTPUT(parm->type))
return -EINVAL;
if (!vpu_helper_check_type(inst, parm->type))
return -EINVAL;
timeperframe = &parm->parm.capture.timeperframe;
if (!timeperframe->numerator)
timeperframe->numerator = venc->params.frame_rate.numerator;
if (!timeperframe->denominator)
timeperframe->denominator = venc->params.frame_rate.denominator;
venc->params.frame_rate.numerator = timeperframe->numerator;
venc->params.frame_rate.denominator = timeperframe->denominator;
rational_best_approximation(venc->params.frame_rate.numerator,
venc->params.frame_rate.denominator,
venc->params.frame_rate.numerator,
venc->params.frame_rate.denominator,
&n, &d);
venc->params.frame_rate.numerator = n;
venc->params.frame_rate.denominator = d;
parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
memset(parm->parm.capture.reserved, 0, sizeof(parm->parm.capture.reserved));
return 0;
}
static int venc_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct vpu_inst *inst = to_inst(file);
struct venc_t *venc = inst->priv;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return -EINVAL;
switch (s->target) {
case V4L2_SEL_TGT_CROP_DEFAULT:
case V4L2_SEL_TGT_CROP_BOUNDS:
s->r.left = 0;
s->r.top = 0;
s->r.width = inst->out_format.width;
s->r.height = inst->out_format.height;
break;
case V4L2_SEL_TGT_CROP:
s->r = venc->params.crop;
break;
default:
return -EINVAL;
}
return 0;
}
static int venc_valid_crop(struct venc_t *venc, const struct vpu_core_resources *res)
{
struct v4l2_rect *rect = NULL;
u32 min_width;
u32 min_height;
u32 src_width;
u32 src_height;
rect = &venc->params.crop;
min_width = res->min_width;
min_height = res->min_height;
src_width = venc->params.src_width;
src_height = venc->params.src_height;
if (rect->width == 0 || rect->height == 0)
return -EINVAL;
if (rect->left > src_width - min_width || rect->top > src_height - min_height)
return -EINVAL;
rect->width = min(rect->width, src_width - rect->left);
rect->width = max_t(u32, rect->width, min_width);
rect->height = min(rect->height, src_height - rect->top);
rect->height = max_t(u32, rect->height, min_height);
return 0;
}
static int venc_s_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct vpu_inst *inst = to_inst(file);
const struct vpu_core_resources *res;
struct venc_t *venc = inst->priv;
res = vpu_get_resource(inst);
if (!res)
return -EINVAL;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return -EINVAL;
if (s->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
venc->params.crop.left = ALIGN(s->r.left, res->step_width);
venc->params.crop.top = ALIGN(s->r.top, res->step_height);
venc->params.crop.width = ALIGN(s->r.width, res->step_width);
venc->params.crop.height = ALIGN(s->r.height, res->step_height);
if (venc_valid_crop(venc, res)) {
venc->params.crop.left = 0;
venc->params.crop.top = 0;
venc->params.crop.width = venc->params.src_width;
venc->params.crop.height = venc->params.src_height;
}
inst->crop = venc->params.crop;
return 0;
}
static int venc_drain(struct vpu_inst *inst)
{
struct venc_t *venc = inst->priv;
int ret;
if (!inst->fh.m2m_ctx)
return 0;
if (inst->state != VPU_CODEC_STATE_DRAIN)
return 0;
if (!vpu_is_source_empty(inst))
return 0;
if (!venc->input_ready)
return 0;
venc->input_ready = false;
vpu_trace(inst->dev, "[%d]\n", inst->id);
ret = vpu_session_stop(inst);
if (ret)
return ret;
inst->state = VPU_CODEC_STATE_STOP;
wake_up_all(&venc->wq);
return 0;
}
static int venc_request_eos(struct vpu_inst *inst)
{
inst->state = VPU_CODEC_STATE_DRAIN;
venc_drain(inst);
return 0;
}
static int venc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *cmd)
{
struct vpu_inst *inst = to_inst(file);
int ret;
ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
if (ret)
return ret;
vpu_inst_lock(inst);
if (cmd->cmd == V4L2_ENC_CMD_STOP) {
if (inst->state == VPU_CODEC_STATE_DEINIT)
vpu_set_last_buffer_dequeued(inst, true);
else
venc_request_eos(inst);
}
vpu_inst_unlock(inst);
return 0;
}
static int venc_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_EOS:
return v4l2_event_subscribe(fh, sub, 0, NULL);
case V4L2_EVENT_CTRL:
return v4l2_ctrl_subscribe_event(fh, sub);
default:
return -EINVAL;
}
}
static const struct v4l2_ioctl_ops venc_ioctl_ops = {
.vidioc_querycap = venc_querycap,
.vidioc_enum_fmt_vid_cap = venc_enum_fmt,
.vidioc_enum_fmt_vid_out = venc_enum_fmt,
.vidioc_enum_framesizes = venc_enum_framesizes,
.vidioc_enum_frameintervals = venc_enum_frameintervals,
.vidioc_g_fmt_vid_cap_mplane = venc_g_fmt,
.vidioc_g_fmt_vid_out_mplane = venc_g_fmt,
.vidioc_try_fmt_vid_cap_mplane = venc_try_fmt,
.vidioc_try_fmt_vid_out_mplane = venc_try_fmt,
.vidioc_s_fmt_vid_cap_mplane = venc_s_fmt,
.vidioc_s_fmt_vid_out_mplane = venc_s_fmt,
.vidioc_g_parm = venc_g_parm,
.vidioc_s_parm = venc_s_parm,
.vidioc_g_selection = venc_g_selection,
.vidioc_s_selection = venc_s_selection,
.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
.vidioc_encoder_cmd = venc_encoder_cmd,
.vidioc_subscribe_event = venc_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
};
static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct vpu_inst *inst = ctrl_to_inst(ctrl);
struct venc_t *venc = inst->priv;
int ret = 0;
vpu_inst_lock(inst);
switch (ctrl->id) {
case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
venc->params.profile = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
venc->params.level = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
venc->params.rc_enable = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
venc->params.rc_mode = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_BITRATE:
if (ctrl->val != venc->params.bitrate)
venc->bitrate_change = true;
venc->params.bitrate = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK:
venc->params.bitrate_max = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
venc->params.gop_length = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_B_FRAMES:
venc->params.bframes = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
venc->params.i_frame_qp = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
venc->params.p_frame_qp = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
venc->params.b_frame_qp = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME:
venc->request_key_frame = 1;
break;
case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
venc->cpb_size = ctrl->val * 1024;
break;
case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE:
venc->params.sar.enable = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC:
venc->params.sar.idc = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH:
venc->params.sar.width = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT:
venc->params.sar.height = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
break;
default:
ret = -EINVAL;
break;
}
vpu_inst_unlock(inst);
return ret;
}
static const struct v4l2_ctrl_ops venc_ctrl_ops = {
.s_ctrl = venc_op_s_ctrl,
.g_volatile_ctrl = vpu_helper_g_volatile_ctrl,
};
static int venc_ctrl_init(struct vpu_inst *inst)
{
struct v4l2_ctrl *ctrl;
int ret;
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20);
if (ret)
return ret;
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_PROFILE,
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
(1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
(1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH);
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_LEVEL,
V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
0x0,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, 0, 1, 1, 1);
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
~((1 << V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
(1 << V4L2_MPEG_VIDEO_BITRATE_MODE_CBR)),
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_BITRATE,
BITRATE_MIN,
BITRATE_MAX,
BITRATE_STEP,
BITRATE_DEFAULT);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
BITRATE_MIN, BITRATE_MAX,
BITRATE_STEP,
BITRATE_DEFAULT_PEAK);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 8000, 1, 30);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_B_FRAMES, 0, 4, 1, 0);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 26);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 28);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, 1, 51, 1, 30);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME, 0, 0, 0, 0);
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE, 64, 10240, 1, 1024);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE, 0, 1, 1, 1);
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED,
0x0,
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
0, USHRT_MAX, 1, 1);
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT,
0, USHRT_MAX, 1, 1);
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_HEADER_MODE,
V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
~(1 << V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
if (inst->ctrl_handler.error) {
ret = inst->ctrl_handler.error;
v4l2_ctrl_handler_free(&inst->ctrl_handler);
return ret;
}
ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
if (ret) {
dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret);
v4l2_ctrl_handler_free(&inst->ctrl_handler);
return ret;
}
return 0;
}
static bool venc_check_ready(struct vpu_inst *inst, unsigned int type)
{
struct venc_t *venc = inst->priv;
if (V4L2_TYPE_IS_OUTPUT(type)) {
if (vpu_helper_get_free_space(inst) < venc->cpb_size)
return false;
return venc->input_ready;
}
if (list_empty(&venc->frames))
return false;
return true;
}
static u32 venc_get_enable_mask(u32 type)
{
if (V4L2_TYPE_IS_OUTPUT(type))
return VENC_OUTPUT_ENABLE;
else
return VENC_CAPTURE_ENABLE;
}
static void venc_set_enable(struct venc_t *venc, u32 type, int enable)
{
u32 mask = venc_get_enable_mask(type);
if (enable)
venc->enable |= mask;
else
venc->enable &= ~mask;
}
static u32 venc_get_enable(struct venc_t *venc, u32 type)
{
return venc->enable & venc_get_enable_mask(type);
}
static void venc_input_done(struct vpu_inst *inst)
{
struct venc_t *venc = inst->priv;
vpu_inst_lock(inst);
venc->input_ready = true;
vpu_process_output_buffer(inst);
if (inst->state == VPU_CODEC_STATE_DRAIN)
venc_drain(inst);
vpu_inst_unlock(inst);
}
/*
* It's hardware limitation, that there may be several bytes
* redundant data at the beginning of frame.
* For android platform, the redundant data may cause cts test fail
* So driver will strip them
*/
static int venc_precheck_encoded_frame(struct vpu_inst *inst, struct venc_frame_t *frame)
{
struct venc_t *venc;
int skipped;
if (!frame || !frame->bytesused)
return -EINVAL;
venc = inst->priv;
skipped = vpu_helper_find_startcode(&inst->stream_buffer,
inst->cap_format.pixfmt,
frame->info.wptr - inst->stream_buffer.phys,
frame->bytesused);
if (skipped > 0) {
frame->bytesused -= skipped;
frame->info.wptr = vpu_helper_step_walk(&inst->stream_buffer,
frame->info.wptr, skipped);
venc->skipped_bytes += skipped;
venc->skipped_count++;
}
return 0;
}
static int venc_get_one_encoded_frame(struct vpu_inst *inst,
struct venc_frame_t *frame,
struct vb2_v4l2_buffer *vbuf)
{
struct venc_t *venc = inst->priv;
struct vb2_v4l2_buffer *src_buf;
if (!vbuf)
return -EAGAIN;
src_buf = vpu_find_buf_by_sequence(inst, inst->out_format.type, frame->info.frame_id);
if (src_buf) {
v4l2_m2m_buf_copy_metadata(src_buf, vbuf, true);
vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, src_buf);
v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
} else {
vbuf->vb2_buf.timestamp = frame->info.timestamp;
}
if (!venc_get_enable(inst->priv, vbuf->vb2_buf.type)) {
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
return 0;
}
if (frame->bytesused > vbuf->vb2_buf.planes[0].length) {
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
return -ENOMEM;
}
venc_precheck_encoded_frame(inst, frame);
if (frame->bytesused) {
u32 rptr = frame->info.wptr;
void *dst = vb2_plane_vaddr(&vbuf->vb2_buf, 0);
vpu_helper_copy_from_stream_buffer(&inst->stream_buffer,
&rptr, frame->bytesused, dst);
vpu_iface_update_stream_buffer(inst, rptr, 0);
}
vb2_set_plane_payload(&vbuf->vb2_buf, 0, frame->bytesused);
vbuf->sequence = frame->info.frame_id;
vbuf->field = inst->cap_format.field;
vbuf->flags |= frame->info.pic_type;
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE);
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
venc->ready_count++;
if (vbuf->flags & V4L2_BUF_FLAG_KEYFRAME)
dev_dbg(inst->dev, "[%d][%d]key frame\n", inst->id, frame->info.frame_id);
return 0;
}
static int venc_get_encoded_frames(struct vpu_inst *inst)
{
struct venc_t *venc;
struct venc_frame_t *frame;
struct venc_frame_t *tmp;
if (!inst->fh.m2m_ctx)
return 0;
venc = inst->priv;
list_for_each_entry_safe(frame, tmp, &venc->frames, list) {
if (venc_get_one_encoded_frame(inst, frame,
v4l2_m2m_dst_buf_remove(inst->fh.m2m_ctx)))
break;
list_del_init(&frame->list);
vfree(frame);
}
return 0;
}
static int venc_frame_encoded(struct vpu_inst *inst, void *arg)
{
struct vpu_enc_pic_info *info = arg;
struct venc_frame_t *frame;
struct venc_t *venc;
int ret = 0;
if (!info)
return -EINVAL;
venc = inst->priv;
frame = vzalloc(sizeof(*frame));
if (!frame)
return -ENOMEM;
memcpy(&frame->info, info, sizeof(frame->info));
frame->bytesused = info->frame_size;
vpu_inst_lock(inst);
list_add_tail(&frame->list, &venc->frames);
venc->encode_count++;
venc_get_encoded_frames(inst);
vpu_inst_unlock(inst);
return ret;
}
static void venc_set_last_buffer_dequeued(struct vpu_inst *inst)
{
struct venc_t *venc = inst->priv;
if (venc->stopped && list_empty(&venc->frames))
vpu_set_last_buffer_dequeued(inst, true);
}
static void venc_stop_done(struct vpu_inst *inst)
{
struct venc_t *venc = inst->priv;
vpu_inst_lock(inst);
venc->stopped = true;
venc_set_last_buffer_dequeued(inst);
vpu_inst_unlock(inst);
wake_up_all(&venc->wq);
}
static void venc_event_notify(struct vpu_inst *inst, u32 event, void *data)
{
}
static void venc_release(struct vpu_inst *inst)
{
}
static void venc_cleanup(struct vpu_inst *inst)
{
struct venc_t *venc;
if (!inst)
return;
venc = inst->priv;
vfree(venc);
inst->priv = NULL;
vfree(inst);
}
static int venc_start_session(struct vpu_inst *inst, u32 type)
{
struct venc_t *venc = inst->priv;
int stream_buffer_size;
int ret;
venc_set_enable(venc, type, 1);
if ((venc->enable & VENC_ENABLE_MASK) != VENC_ENABLE_MASK)
return 0;
vpu_iface_init_instance(inst);
stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core);
if (stream_buffer_size > 0) {
inst->stream_buffer.length = max_t(u32, stream_buffer_size, venc->cpb_size * 3);
ret = vpu_alloc_dma(inst->core, &inst->stream_buffer);
if (ret)
goto error;
inst->use_stream_buffer = true;
vpu_iface_config_stream_buffer(inst, &inst->stream_buffer);
}
ret = vpu_iface_set_encode_params(inst, &venc->params, 0);
if (ret)
goto error;
ret = vpu_session_configure_codec(inst);
if (ret)
goto error;
inst->state = VPU_CODEC_STATE_CONFIGURED;
/*vpu_iface_config_memory_resource*/
/*config enc expert mode parameter*/
ret = vpu_iface_set_encode_params(inst, &venc->params, 1);
if (ret)
goto error;
ret = vpu_session_start(inst);
if (ret)
goto error;
inst->state = VPU_CODEC_STATE_STARTED;
venc->bitrate_change = false;
venc->input_ready = true;
venc->frame_count = 0;
venc->encode_count = 0;
venc->ready_count = 0;
venc->stopped = false;
vpu_process_output_buffer(inst);
if (venc->frame_count == 0)
dev_err(inst->dev, "[%d] there is no input when starting\n", inst->id);
return 0;
error:
venc_set_enable(venc, type, 0);
inst->state = VPU_CODEC_STATE_DEINIT;
vpu_free_dma(&inst->stream_buffer);
return ret;
}
static void venc_cleanup_mem_resource(struct vpu_inst *inst)
{
struct venc_t *venc;
u32 i;
venc = inst->priv;
for (i = 0; i < ARRAY_SIZE(venc->enc); i++)
vpu_free_dma(&venc->enc[i]);
for (i = 0; i < ARRAY_SIZE(venc->ref); i++)
vpu_free_dma(&venc->ref[i]);
}
static void venc_request_mem_resource(struct vpu_inst *inst,
u32 enc_frame_size,
u32 enc_frame_num,
u32 ref_frame_size,
u32 ref_frame_num,
u32 act_frame_size,
u32 act_frame_num)
{
struct venc_t *venc;
u32 i;
int ret;
venc = inst->priv;
if (enc_frame_num > ARRAY_SIZE(venc->enc)) {
dev_err(inst->dev, "[%d] enc num(%d) is out of range\n", inst->id, enc_frame_num);
return;
}
if (ref_frame_num > ARRAY_SIZE(venc->ref)) {
dev_err(inst->dev, "[%d] ref num(%d) is out of range\n", inst->id, ref_frame_num);
return;
}
if (act_frame_num > ARRAY_SIZE(venc->act)) {
dev_err(inst->dev, "[%d] act num(%d) is out of range\n", inst->id, act_frame_num);
return;
}
for (i = 0; i < enc_frame_num; i++) {
venc->enc[i].length = enc_frame_size;
ret = vpu_alloc_dma(inst->core, &venc->enc[i]);
if (ret) {
venc_cleanup_mem_resource(inst);
return;
}
}
for (i = 0; i < ref_frame_num; i++) {
venc->ref[i].length = ref_frame_size;
ret = vpu_alloc_dma(inst->core, &venc->ref[i]);
if (ret) {
venc_cleanup_mem_resource(inst);
return;
}
}
if (act_frame_num != 1 || act_frame_size > inst->act.length) {
venc_cleanup_mem_resource(inst);
return;
}
venc->act[0].length = act_frame_size;
venc->act[0].phys = inst->act.phys;
venc->act[0].virt = inst->act.virt;
for (i = 0; i < enc_frame_num; i++)
vpu_iface_config_memory_resource(inst, MEM_RES_ENC, i, &venc->enc[i]);
for (i = 0; i < ref_frame_num; i++)
vpu_iface_config_memory_resource(inst, MEM_RES_REF, i, &venc->ref[i]);
for (i = 0; i < act_frame_num; i++)
vpu_iface_config_memory_resource(inst, MEM_RES_ACT, i, &venc->act[i]);
}
static void venc_cleanup_frames(struct venc_t *venc)
{
struct venc_frame_t *frame;
struct venc_frame_t *tmp;
list_for_each_entry_safe(frame, tmp, &venc->frames, list) {
list_del_init(&frame->list);
vfree(frame);
}
}
static int venc_stop_session(struct vpu_inst *inst, u32 type)
{
struct venc_t *venc = inst->priv;
venc_set_enable(venc, type, 0);
if (venc->enable & VENC_ENABLE_MASK)
return 0;
if (inst->state == VPU_CODEC_STATE_DEINIT)
return 0;
if (inst->state != VPU_CODEC_STATE_STOP)
venc_request_eos(inst);
call_void_vop(inst, wait_prepare);
if (!wait_event_timeout(venc->wq, venc->stopped, VPU_TIMEOUT)) {
set_bit(inst->id, &inst->core->hang_mask);
vpu_session_debug(inst);
}
call_void_vop(inst, wait_finish);
inst->state = VPU_CODEC_STATE_DEINIT;
venc_cleanup_frames(inst->priv);
vpu_free_dma(&inst->stream_buffer);
venc_cleanup_mem_resource(inst);
return 0;
}
static int venc_process_output(struct vpu_inst *inst, struct vb2_buffer *vb)
{
struct venc_t *venc = inst->priv;
struct vb2_v4l2_buffer *vbuf;
u32 flags;
if (inst->state == VPU_CODEC_STATE_DEINIT)
return -EINVAL;
vbuf = to_vb2_v4l2_buffer(vb);
if (inst->state == VPU_CODEC_STATE_STARTED)
inst->state = VPU_CODEC_STATE_ACTIVE;
flags = vbuf->flags;
if (venc->request_key_frame) {
vbuf->flags |= V4L2_BUF_FLAG_KEYFRAME;
venc->request_key_frame = 0;
}
if (venc->bitrate_change) {
vpu_session_update_parameters(inst, &venc->params);
venc->bitrate_change = false;
}
dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp);
vpu_iface_input_frame(inst, vb);
vbuf->flags = flags;
venc->input_ready = false;
venc->frame_count++;
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE);
return 0;
}
static int venc_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb)
{
struct venc_t *venc;
struct venc_frame_t *frame = NULL;
struct vb2_v4l2_buffer *vbuf;
int ret;
venc = inst->priv;
if (list_empty(&venc->frames))
return -EINVAL;
frame = list_first_entry(&venc->frames, struct venc_frame_t, list);
vbuf = to_vb2_v4l2_buffer(vb);
v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf);
ret = venc_get_one_encoded_frame(inst, frame, vbuf);
if (ret)
return ret;
list_del_init(&frame->list);
vfree(frame);
return 0;
}
static void venc_on_queue_empty(struct vpu_inst *inst, u32 type)
{
struct venc_t *venc = inst->priv;
if (V4L2_TYPE_IS_OUTPUT(type))
return;
if (venc->stopped)
venc_set_last_buffer_dequeued(inst);
}
static int venc_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
{
struct venc_t *venc = inst->priv;
int num = -1;
switch (i) {
case 0:
num = scnprintf(str, size, "profile = %d\n", venc->params.profile);
break;
case 1:
num = scnprintf(str, size, "level = %d\n", venc->params.level);
break;
case 2:
num = scnprintf(str, size, "fps = %d/%d\n",
venc->params.frame_rate.numerator,
venc->params.frame_rate.denominator);
break;
case 3:
num = scnprintf(str, size, "%d x %d -> %d x %d\n",
venc->params.src_width,
venc->params.src_height,
venc->params.out_width,
venc->params.out_height);
break;
case 4:
num = scnprintf(str, size, "(%d, %d) %d x %d\n",
venc->params.crop.left,
venc->params.crop.top,
venc->params.crop.width,
venc->params.crop.height);
break;
case 5:
num = scnprintf(str, size,
"enable = 0x%x, input = %d, encode = %d, ready = %d, stopped = %d\n",
venc->enable,
venc->frame_count, venc->encode_count,
venc->ready_count,
venc->stopped);
break;
case 6:
num = scnprintf(str, size, "gop = %d\n", venc->params.gop_length);
break;
case 7:
num = scnprintf(str, size, "bframes = %d\n", venc->params.bframes);
break;
case 8:
num = scnprintf(str, size, "rc: %s, mode = %d, bitrate = %d(%d), qp = %d\n",
venc->params.rc_enable ? "enable" : "disable",
venc->params.rc_mode,
venc->params.bitrate,
venc->params.bitrate_max,
venc->params.i_frame_qp);
break;
case 9:
num = scnprintf(str, size, "sar: enable = %d, idc = %d, %d x %d\n",
venc->params.sar.enable,
venc->params.sar.idc,
venc->params.sar.width,
venc->params.sar.height);
break;
case 10:
num = scnprintf(str, size,
"colorspace: primaries = %d, transfer = %d, matrix = %d, full_range = %d\n",
venc->params.color.primaries,
venc->params.color.transfer,
venc->params.color.matrix,
venc->params.color.full_range);
break;
case 11:
num = scnprintf(str, size, "skipped: count = %d, bytes = %d\n",
venc->skipped_count, venc->skipped_bytes);
break;
default:
break;
}
return num;
}
static struct vpu_inst_ops venc_inst_ops = {
.ctrl_init = venc_ctrl_init,
.check_ready = venc_check_ready,
.input_done = venc_input_done,
.get_one_frame = venc_frame_encoded,
.stop_done = venc_stop_done,
.event_notify = venc_event_notify,
.release = venc_release,
.cleanup = venc_cleanup,
.start = venc_start_session,
.mem_request = venc_request_mem_resource,
.stop = venc_stop_session,
.process_output = venc_process_output,
.process_capture = venc_process_capture,
.on_queue_empty = venc_on_queue_empty,
.get_debug_info = venc_get_debug_info,
.wait_prepare = vpu_inst_unlock,
.wait_finish = vpu_inst_lock,
};
static void venc_init(struct file *file)
{
struct vpu_inst *inst = to_inst(file);
struct venc_t *venc;
struct v4l2_format f;
struct v4l2_streamparm parm;
venc = inst->priv;
venc->params.qp_min = 1;
venc->params.qp_max = 51;
venc->params.qp_min_i = 1;
venc->params.qp_max_i = 51;
venc->params.bitrate_min = BITRATE_MIN;
memset(&f, 0, sizeof(f));
f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12M;
f.fmt.pix_mp.width = 1280;
f.fmt.pix_mp.height = 720;
f.fmt.pix_mp.field = V4L2_FIELD_NONE;
venc_s_fmt(file, &inst->fh, &f);
memset(&f, 0, sizeof(f));
f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264;
f.fmt.pix_mp.width = 1280;
f.fmt.pix_mp.height = 720;
f.fmt.pix_mp.field = V4L2_FIELD_NONE;
venc_s_fmt(file, &inst->fh, &f);
memset(&parm, 0, sizeof(parm));
parm.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
parm.parm.capture.timeperframe.numerator = 1;
parm.parm.capture.timeperframe.denominator = 30;
venc_s_parm(file, &inst->fh, &parm);
}
static int venc_open(struct file *file)
{
struct vpu_inst *inst;
struct venc_t *venc;
int ret;
inst = vzalloc(sizeof(*inst));
if (!inst)
return -ENOMEM;
venc = vzalloc(sizeof(*venc));
if (!venc) {
vfree(inst);
return -ENOMEM;
}
inst->ops = &venc_inst_ops;
inst->formats = venc_formats;
inst->type = VPU_CORE_TYPE_ENC;
inst->priv = venc;
INIT_LIST_HEAD(&venc->frames);
init_waitqueue_head(&venc->wq);
ret = vpu_v4l2_open(file, inst);
if (ret)
return ret;
inst->min_buffer_out = VENC_MIN_BUFFER_OUT;
inst->min_buffer_cap = VENC_MIN_BUFFER_CAP;
venc_init(file);
return 0;
}
static const struct v4l2_file_operations venc_fops = {
.owner = THIS_MODULE,
.open = venc_open,
.release = vpu_v4l2_close,
.unlocked_ioctl = video_ioctl2,
.poll = v4l2_m2m_fop_poll,
.mmap = v4l2_m2m_fop_mmap,
};
const struct v4l2_ioctl_ops *venc_get_ioctl_ops(void)
{
return &venc_ioctl_ops;
}
const struct v4l2_file_operations *venc_get_fops(void)
{
return &venc_fops;
}
| linux-master | drivers/media/platform/amphion/venc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-vmalloc.h>
#include "vpu.h"
#include "vpu_core.h"
#include "vpu_v4l2.h"
#include "vpu_msgs.h"
#include "vpu_helpers.h"
void vpu_inst_lock(struct vpu_inst *inst)
{
mutex_lock(&inst->lock);
}
void vpu_inst_unlock(struct vpu_inst *inst)
{
mutex_unlock(&inst->lock);
}
dma_addr_t vpu_get_vb_phy_addr(struct vb2_buffer *vb, u32 plane_no)
{
if (plane_no >= vb->num_planes)
return 0;
return vb2_dma_contig_plane_dma_addr(vb, plane_no) +
vb->planes[plane_no].data_offset;
}
unsigned int vpu_get_vb_length(struct vb2_buffer *vb, u32 plane_no)
{
if (plane_no >= vb->num_planes)
return 0;
return vb2_plane_size(vb, plane_no) - vb->planes[plane_no].data_offset;
}
void vpu_set_buffer_state(struct vb2_v4l2_buffer *vbuf, unsigned int state)
{
struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf);
vpu_buf->state = state;
}
unsigned int vpu_get_buffer_state(struct vb2_v4l2_buffer *vbuf)
{
struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf);
return vpu_buf->state;
}
void vpu_v4l2_set_error(struct vpu_inst *inst)
{
vpu_inst_lock(inst);
dev_err(inst->dev, "some error occurs in codec\n");
if (inst->fh.m2m_ctx) {
vb2_queue_error(v4l2_m2m_get_src_vq(inst->fh.m2m_ctx));
vb2_queue_error(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx));
}
vpu_inst_unlock(inst);
}
int vpu_notify_eos(struct vpu_inst *inst)
{
static const struct v4l2_event ev = {
.id = 0,
.type = V4L2_EVENT_EOS
};
vpu_trace(inst->dev, "[%d]\n", inst->id);
v4l2_event_queue_fh(&inst->fh, &ev);
return 0;
}
int vpu_notify_source_change(struct vpu_inst *inst)
{
static const struct v4l2_event ev = {
.id = 0,
.type = V4L2_EVENT_SOURCE_CHANGE,
.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION
};
vpu_trace(inst->dev, "[%d]\n", inst->id);
v4l2_event_queue_fh(&inst->fh, &ev);
return 0;
}
int vpu_set_last_buffer_dequeued(struct vpu_inst *inst, bool eos)
{
struct vb2_queue *q;
if (!inst || !inst->fh.m2m_ctx)
return -EINVAL;
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
if (!list_empty(&q->done_list))
return -EINVAL;
if (q->last_buffer_dequeued)
return 0;
vpu_trace(inst->dev, "last buffer dequeued\n");
q->last_buffer_dequeued = true;
wake_up(&q->done_wq);
if (eos)
vpu_notify_eos(inst);
return 0;
}
bool vpu_is_source_empty(struct vpu_inst *inst)
{
struct v4l2_m2m_buffer *buf = NULL;
if (!inst->fh.m2m_ctx)
return true;
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
if (vpu_get_buffer_state(&buf->vb) == VPU_BUF_STATE_IDLE)
return false;
}
return true;
}
static int vpu_init_format(struct vpu_inst *inst, struct vpu_format *fmt)
{
const struct vpu_format *info;
info = vpu_helper_find_format(inst, fmt->type, fmt->pixfmt);
if (!info) {
info = vpu_helper_enum_format(inst, fmt->type, 0);
if (!info)
return -EINVAL;
}
memcpy(fmt, info, sizeof(*fmt));
return 0;
}
static int vpu_calc_fmt_bytesperline(struct v4l2_format *f, struct vpu_format *fmt)
{
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
int i;
if (fmt->flags & V4L2_FMT_FLAG_COMPRESSED) {
for (i = 0; i < fmt->comp_planes; i++)
fmt->bytesperline[i] = 0;
return 0;
}
if (pixmp->num_planes == fmt->comp_planes) {
for (i = 0; i < fmt->comp_planes; i++)
fmt->bytesperline[i] = pixmp->plane_fmt[i].bytesperline;
return 0;
}
if (pixmp->num_planes > 1)
return -EINVAL;
/*amphion vpu only support nv12 and nv12 tiled,
* so the bytesperline of luma and chroma should be same
*/
for (i = 0; i < fmt->comp_planes; i++)
fmt->bytesperline[i] = pixmp->plane_fmt[0].bytesperline;
return 0;
}
static int vpu_calc_fmt_sizeimage(struct vpu_inst *inst, struct vpu_format *fmt)
{
u32 stride = 1;
int i;
if (!(fmt->flags & V4L2_FMT_FLAG_COMPRESSED)) {
const struct vpu_core_resources *res = vpu_get_resource(inst);
if (res)
stride = res->stride;
}
for (i = 0; i < fmt->comp_planes; i++) {
fmt->sizeimage[i] = vpu_helper_get_plane_size(fmt->pixfmt,
fmt->width,
fmt->height,
i,
stride,
fmt->field != V4L2_FIELD_NONE ? 1 : 0,
&fmt->bytesperline[i]);
fmt->sizeimage[i] = max_t(u32, fmt->sizeimage[i], PAGE_SIZE);
if (fmt->flags & V4L2_FMT_FLAG_COMPRESSED) {
fmt->sizeimage[i] = clamp_val(fmt->sizeimage[i], SZ_128K, SZ_8M);
fmt->bytesperline[i] = 0;
}
}
return 0;
}
u32 vpu_get_fmt_plane_size(struct vpu_format *fmt, u32 plane_no)
{
u32 size;
int i;
if (plane_no >= fmt->mem_planes)
return 0;
if (fmt->comp_planes == fmt->mem_planes)
return fmt->sizeimage[plane_no];
if (plane_no < fmt->mem_planes - 1)
return fmt->sizeimage[plane_no];
size = fmt->sizeimage[plane_no];
for (i = fmt->mem_planes; i < fmt->comp_planes; i++)
size += fmt->sizeimage[i];
return size;
}
int vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f, struct vpu_format *fmt)
{
struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
int i;
int ret;
fmt->pixfmt = pixmp->pixelformat;
fmt->type = f->type;
ret = vpu_init_format(inst, fmt);
if (ret < 0)
return ret;
fmt->width = pixmp->width;
fmt->height = pixmp->height;
if (fmt->width)
fmt->width = vpu_helper_valid_frame_width(inst, fmt->width);
if (fmt->height)
fmt->height = vpu_helper_valid_frame_height(inst, fmt->height);
fmt->field = pixmp->field == V4L2_FIELD_ANY ? V4L2_FIELD_NONE : pixmp->field;
vpu_calc_fmt_bytesperline(f, fmt);
vpu_calc_fmt_sizeimage(inst, fmt);
if ((fmt->flags & V4L2_FMT_FLAG_COMPRESSED) && pixmp->plane_fmt[0].sizeimage)
fmt->sizeimage[0] = clamp_val(pixmp->plane_fmt[0].sizeimage, SZ_128K, SZ_8M);
pixmp->pixelformat = fmt->pixfmt;
pixmp->width = fmt->width;
pixmp->height = fmt->height;
pixmp->flags = fmt->flags;
pixmp->num_planes = fmt->mem_planes;
pixmp->field = fmt->field;
memset(pixmp->reserved, 0, sizeof(pixmp->reserved));
for (i = 0; i < pixmp->num_planes; i++) {
pixmp->plane_fmt[i].bytesperline = fmt->bytesperline[i];
pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(fmt, i);
memset(pixmp->plane_fmt[i].reserved, 0, sizeof(pixmp->plane_fmt[i].reserved));
}
return 0;
}
static bool vpu_check_ready(struct vpu_inst *inst, u32 type)
{
if (!inst)
return false;
if (inst->state == VPU_CODEC_STATE_DEINIT || inst->id < 0)
return false;
if (!inst->ops->check_ready)
return true;
return call_vop(inst, check_ready, type);
}
int vpu_process_output_buffer(struct vpu_inst *inst)
{
struct v4l2_m2m_buffer *buf = NULL;
struct vb2_v4l2_buffer *vbuf = NULL;
if (!inst || !inst->fh.m2m_ctx)
return -EINVAL;
if (!vpu_check_ready(inst, inst->out_format.type))
return -EINVAL;
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_IDLE)
break;
vbuf = NULL;
}
if (!vbuf)
return -EINVAL;
dev_dbg(inst->dev, "[%d]frame id = %d / %d\n",
inst->id, vbuf->sequence, inst->sequence);
return call_vop(inst, process_output, &vbuf->vb2_buf);
}
int vpu_process_capture_buffer(struct vpu_inst *inst)
{
struct v4l2_m2m_buffer *buf = NULL;
struct vb2_v4l2_buffer *vbuf = NULL;
if (!inst || !inst->fh.m2m_ctx)
return -EINVAL;
if (!vpu_check_ready(inst, inst->cap_format.type))
return -EINVAL;
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_IDLE)
break;
vbuf = NULL;
}
if (!vbuf)
return -EINVAL;
return call_vop(inst, process_capture, &vbuf->vb2_buf);
}
struct vb2_v4l2_buffer *vpu_next_src_buf(struct vpu_inst *inst)
{
struct vb2_v4l2_buffer *src_buf = NULL;
if (!inst->fh.m2m_ctx)
return NULL;
src_buf = v4l2_m2m_next_src_buf(inst->fh.m2m_ctx);
if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE)
return NULL;
while (vpu_vb_is_codecconfig(src_buf)) {
v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx);
vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
src_buf = v4l2_m2m_next_src_buf(inst->fh.m2m_ctx);
if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE)
return NULL;
}
return src_buf;
}
void vpu_skip_frame(struct vpu_inst *inst, int count)
{
struct vb2_v4l2_buffer *src_buf;
enum vb2_buffer_state state;
int i = 0;
if (count <= 0 || !inst->fh.m2m_ctx)
return;
while (i < count) {
src_buf = v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx);
if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE)
return;
if (vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_DECODED)
state = VB2_BUF_STATE_DONE;
else
state = VB2_BUF_STATE_ERROR;
i++;
vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_buf_done(src_buf, state);
}
}
struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence)
{
struct v4l2_m2m_buffer *buf = NULL;
struct vb2_v4l2_buffer *vbuf = NULL;
if (!inst || !inst->fh.m2m_ctx)
return NULL;
if (V4L2_TYPE_IS_OUTPUT(type)) {
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vbuf->sequence == sequence)
break;
vbuf = NULL;
}
} else {
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vbuf->sequence == sequence)
break;
vbuf = NULL;
}
}
return vbuf;
}
struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 idx)
{
struct v4l2_m2m_buffer *buf = NULL;
struct vb2_v4l2_buffer *vbuf = NULL;
if (!inst || !inst->fh.m2m_ctx)
return NULL;
if (V4L2_TYPE_IS_OUTPUT(type)) {
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vbuf->vb2_buf.index == idx)
break;
vbuf = NULL;
}
} else {
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
vbuf = &buf->vb;
if (vbuf->vb2_buf.index == idx)
break;
vbuf = NULL;
}
}
return vbuf;
}
int vpu_get_num_buffers(struct vpu_inst *inst, u32 type)
{
struct vb2_queue *q;
if (!inst || !inst->fh.m2m_ctx)
return -EINVAL;
if (V4L2_TYPE_IS_OUTPUT(type))
q = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
else
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
return q->num_buffers;
}
static void vpu_m2m_device_run(void *priv)
{
}
static void vpu_m2m_job_abort(void *priv)
{
struct vpu_inst *inst = priv;
struct v4l2_m2m_ctx *m2m_ctx = inst->fh.m2m_ctx;
v4l2_m2m_job_finish(m2m_ctx->m2m_dev, m2m_ctx);
}
static const struct v4l2_m2m_ops vpu_m2m_ops = {
.device_run = vpu_m2m_device_run,
.job_abort = vpu_m2m_job_abort
};
static int vpu_vb2_queue_setup(struct vb2_queue *vq,
unsigned int *buf_count,
unsigned int *plane_count,
unsigned int psize[],
struct device *allocators[])
{
struct vpu_inst *inst = vb2_get_drv_priv(vq);
struct vpu_format *cur_fmt;
int i;
cur_fmt = vpu_get_format(inst, vq->type);
if (*plane_count) {
if (*plane_count != cur_fmt->mem_planes)
return -EINVAL;
for (i = 0; i < cur_fmt->mem_planes; i++) {
if (psize[i] < vpu_get_fmt_plane_size(cur_fmt, i))
return -EINVAL;
}
return 0;
}
if (V4L2_TYPE_IS_OUTPUT(vq->type))
*buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_out);
else
*buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_cap);
*plane_count = cur_fmt->mem_planes;
for (i = 0; i < cur_fmt->mem_planes; i++)
psize[i] = vpu_get_fmt_plane_size(cur_fmt, i);
if (V4L2_TYPE_IS_OUTPUT(vq->type) && inst->state == VPU_CODEC_STATE_SEEK) {
vpu_trace(inst->dev, "reinit when VIDIOC_REQBUFS(OUTPUT, 0)\n");
call_void_vop(inst, release);
}
return 0;
}
static int vpu_vb2_buf_init(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE);
return 0;
}
static int vpu_vb2_buf_out_validate(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
vbuf->field = V4L2_FIELD_NONE;
return 0;
}
static int vpu_vb2_buf_prepare(struct vb2_buffer *vb)
{
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct vpu_format *cur_fmt;
u32 i;
cur_fmt = vpu_get_format(inst, vb->type);
for (i = 0; i < cur_fmt->mem_planes; i++) {
if (vpu_get_vb_length(vb, i) < vpu_get_fmt_plane_size(cur_fmt, i)) {
dev_dbg(inst->dev, "[%d] %s buf[%d] is invalid\n",
inst->id, vpu_type_name(vb->type), vb->index);
vpu_set_buffer_state(vbuf, VPU_BUF_STATE_ERROR);
}
}
return 0;
}
static void vpu_vb2_buf_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
struct vb2_queue *q = vb->vb2_queue;
if (vbuf->flags & V4L2_BUF_FLAG_LAST)
vpu_notify_eos(inst);
if (list_empty(&q->done_list))
call_void_vop(inst, on_queue_empty, q->type);
}
void vpu_vb2_buffers_return(struct vpu_inst *inst, unsigned int type, enum vb2_buffer_state state)
{
struct vb2_v4l2_buffer *buf;
if (V4L2_TYPE_IS_OUTPUT(type)) {
while ((buf = v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx))) {
vpu_set_buffer_state(buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_buf_done(buf, state);
}
} else {
while ((buf = v4l2_m2m_dst_buf_remove(inst->fh.m2m_ctx))) {
vpu_set_buffer_state(buf, VPU_BUF_STATE_IDLE);
v4l2_m2m_buf_done(buf, state);
}
}
}
static int vpu_vb2_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct vpu_inst *inst = vb2_get_drv_priv(q);
struct vpu_format *fmt = vpu_get_format(inst, q->type);
int ret;
vpu_inst_unlock(inst);
ret = vpu_inst_register(inst);
vpu_inst_lock(inst);
if (ret) {
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_QUEUED);
return ret;
}
vpu_trace(inst->dev, "[%d] %s %c%c%c%c %dx%d %u(%u) %u(%u) %u(%u) %d\n",
inst->id, vpu_type_name(q->type),
fmt->pixfmt,
fmt->pixfmt >> 8,
fmt->pixfmt >> 16,
fmt->pixfmt >> 24,
fmt->width, fmt->height,
fmt->sizeimage[0], fmt->bytesperline[0],
fmt->sizeimage[1], fmt->bytesperline[1],
fmt->sizeimage[2], fmt->bytesperline[2],
q->num_buffers);
vb2_clear_last_buffer_dequeued(q);
ret = call_vop(inst, start, q->type);
if (ret)
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_QUEUED);
return ret;
}
static void vpu_vb2_stop_streaming(struct vb2_queue *q)
{
struct vpu_inst *inst = vb2_get_drv_priv(q);
vpu_trace(inst->dev, "[%d] %s\n", inst->id, vpu_type_name(q->type));
call_void_vop(inst, stop, q->type);
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_ERROR);
if (V4L2_TYPE_IS_OUTPUT(q->type))
inst->sequence = 0;
}
static void vpu_vb2_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
if (V4L2_TYPE_IS_OUTPUT(vb->type))
vbuf->sequence = inst->sequence++;
v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf);
vpu_process_output_buffer(inst);
vpu_process_capture_buffer(inst);
}
static const struct vb2_ops vpu_vb2_ops = {
.queue_setup = vpu_vb2_queue_setup,
.buf_init = vpu_vb2_buf_init,
.buf_out_validate = vpu_vb2_buf_out_validate,
.buf_prepare = vpu_vb2_buf_prepare,
.buf_finish = vpu_vb2_buf_finish,
.start_streaming = vpu_vb2_start_streaming,
.stop_streaming = vpu_vb2_stop_streaming,
.buf_queue = vpu_vb2_buf_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int vpu_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
{
struct vpu_inst *inst = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
inst->out_format.type = src_vq->type;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->ops = &vpu_vb2_ops;
src_vq->mem_ops = &vb2_dma_contig_memops;
if (inst->type == VPU_CORE_TYPE_DEC && inst->use_stream_buffer)
src_vq->mem_ops = &vb2_vmalloc_memops;
src_vq->drv_priv = inst;
src_vq->buf_struct_size = sizeof(struct vpu_vb2_buffer);
src_vq->min_buffers_needed = 1;
src_vq->dev = inst->vpu->dev;
src_vq->lock = &inst->lock;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
inst->cap_format.type = dst_vq->type;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->ops = &vpu_vb2_ops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
if (inst->type == VPU_CORE_TYPE_ENC && inst->use_stream_buffer)
dst_vq->mem_ops = &vb2_vmalloc_memops;
dst_vq->drv_priv = inst;
dst_vq->buf_struct_size = sizeof(struct vpu_vb2_buffer);
dst_vq->min_buffers_needed = 1;
dst_vq->dev = inst->vpu->dev;
dst_vq->lock = &inst->lock;
ret = vb2_queue_init(dst_vq);
if (ret) {
vb2_queue_release(src_vq);
return ret;
}
return 0;
}
static int vpu_v4l2_release(struct vpu_inst *inst)
{
vpu_trace(inst->vpu->dev, "%p\n", inst);
vpu_release_core(inst->core);
put_device(inst->dev);
if (inst->workqueue) {
cancel_work_sync(&inst->msg_work);
destroy_workqueue(inst->workqueue);
inst->workqueue = NULL;
}
v4l2_ctrl_handler_free(&inst->ctrl_handler);
mutex_destroy(&inst->lock);
v4l2_fh_del(&inst->fh);
v4l2_fh_exit(&inst->fh);
call_void_vop(inst, cleanup);
return 0;
}
int vpu_v4l2_open(struct file *file, struct vpu_inst *inst)
{
struct vpu_dev *vpu = video_drvdata(file);
struct vpu_func *func;
int ret = 0;
if (!inst || !inst->ops)
return -EINVAL;
if (inst->type == VPU_CORE_TYPE_ENC)
func = &vpu->encoder;
else
func = &vpu->decoder;
atomic_set(&inst->ref_count, 0);
vpu_inst_get(inst);
inst->vpu = vpu;
inst->core = vpu_request_core(vpu, inst->type);
if (inst->core)
inst->dev = get_device(inst->core->dev);
mutex_init(&inst->lock);
INIT_LIST_HEAD(&inst->cmd_q);
inst->id = VPU_INST_NULL_ID;
inst->release = vpu_v4l2_release;
inst->pid = current->pid;
inst->tgid = current->tgid;
inst->min_buffer_cap = 2;
inst->min_buffer_out = 2;
v4l2_fh_init(&inst->fh, func->vfd);
v4l2_fh_add(&inst->fh);
ret = call_vop(inst, ctrl_init);
if (ret)
goto error;
inst->fh.m2m_ctx = v4l2_m2m_ctx_init(func->m2m_dev, inst, vpu_m2m_queue_init);
if (IS_ERR(inst->fh.m2m_ctx)) {
dev_err(vpu->dev, "v4l2_m2m_ctx_init fail\n");
ret = PTR_ERR(inst->fh.m2m_ctx);
goto error;
}
inst->fh.ctrl_handler = &inst->ctrl_handler;
file->private_data = &inst->fh;
inst->state = VPU_CODEC_STATE_DEINIT;
inst->workqueue = alloc_ordered_workqueue("vpu_inst", WQ_MEM_RECLAIM);
if (inst->workqueue) {
INIT_WORK(&inst->msg_work, vpu_inst_run_work);
ret = kfifo_init(&inst->msg_fifo,
inst->msg_buffer,
rounddown_pow_of_two(sizeof(inst->msg_buffer)));
if (ret) {
destroy_workqueue(inst->workqueue);
inst->workqueue = NULL;
}
}
vpu_trace(vpu->dev, "tgid = %d, pid = %d, type = %s, inst = %p\n",
inst->tgid, inst->pid, vpu_core_type_desc(inst->type), inst);
return 0;
error:
vpu_inst_put(inst);
return ret;
}
int vpu_v4l2_close(struct file *file)
{
struct vpu_dev *vpu = video_drvdata(file);
struct vpu_inst *inst = to_inst(file);
vpu_trace(vpu->dev, "tgid = %d, pid = %d, inst = %p\n", inst->tgid, inst->pid, inst);
vpu_inst_lock(inst);
if (inst->fh.m2m_ctx) {
v4l2_m2m_ctx_release(inst->fh.m2m_ctx);
inst->fh.m2m_ctx = NULL;
}
call_void_vop(inst, release);
vpu_inst_unlock(inst);
vpu_inst_unregister(inst);
vpu_inst_put(inst);
return 0;
}
int vpu_add_func(struct vpu_dev *vpu, struct vpu_func *func)
{
struct video_device *vfd;
int ret;
if (!vpu || !func)
return -EINVAL;
if (func->vfd)
return 0;
func->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
if (IS_ERR(func->m2m_dev)) {
dev_err(vpu->dev, "v4l2_m2m_init fail\n");
func->vfd = NULL;
return PTR_ERR(func->m2m_dev);
}
vfd = video_device_alloc();
if (!vfd) {
v4l2_m2m_release(func->m2m_dev);
dev_err(vpu->dev, "alloc vpu decoder video device fail\n");
return -ENOMEM;
}
vfd->release = video_device_release;
vfd->vfl_dir = VFL_DIR_M2M;
vfd->v4l2_dev = &vpu->v4l2_dev;
vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
if (func->type == VPU_CORE_TYPE_ENC) {
strscpy(vfd->name, "amphion-vpu-encoder", sizeof(vfd->name));
vfd->fops = venc_get_fops();
vfd->ioctl_ops = venc_get_ioctl_ops();
} else {
strscpy(vfd->name, "amphion-vpu-decoder", sizeof(vfd->name));
vfd->fops = vdec_get_fops();
vfd->ioctl_ops = vdec_get_ioctl_ops();
}
ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
if (ret) {
video_device_release(vfd);
v4l2_m2m_release(func->m2m_dev);
return ret;
}
video_set_drvdata(vfd, vpu);
func->vfd = vfd;
ret = v4l2_m2m_register_media_controller(func->m2m_dev, func->vfd, func->function);
if (ret) {
v4l2_m2m_release(func->m2m_dev);
func->m2m_dev = NULL;
video_unregister_device(func->vfd);
func->vfd = NULL;
return ret;
}
return 0;
}
void vpu_remove_func(struct vpu_func *func)
{
if (!func)
return;
if (func->m2m_dev) {
v4l2_m2m_unregister_media_controller(func->m2m_dev);
v4l2_m2m_release(func->m2m_dev);
func->m2m_dev = NULL;
}
if (func->vfd) {
video_unregister_device(func->vfd);
func->vfd = NULL;
}
}
| linux-master | drivers/media/platform/amphion/vpu_v4l2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "vpu.h"
#include "vpu_defs.h"
#include "vpu_core.h"
#include "vpu_rpc.h"
#include "vpu_helpers.h"
int vpu_helper_find_in_array_u8(const u8 *array, u32 size, u32 x)
{
int i;
for (i = 0; i < size; i++) {
if (array[i] == x)
return i;
}
return 0;
}
bool vpu_helper_check_type(struct vpu_inst *inst, u32 type)
{
const struct vpu_format *pfmt;
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
if (!vpu_iface_check_format(inst, pfmt->pixfmt))
continue;
if (pfmt->type == type)
return true;
}
return false;
}
const struct vpu_format *vpu_helper_find_format(struct vpu_inst *inst, u32 type, u32 pixelfmt)
{
const struct vpu_format *pfmt;
if (!inst || !inst->formats)
return NULL;
if (!vpu_iface_check_format(inst, pixelfmt))
return NULL;
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
if (pfmt->pixfmt == pixelfmt && (!type || type == pfmt->type))
return pfmt;
}
return NULL;
}
const struct vpu_format *vpu_helper_find_sibling(struct vpu_inst *inst, u32 type, u32 pixelfmt)
{
const struct vpu_format *fmt;
const struct vpu_format *sibling;
fmt = vpu_helper_find_format(inst, type, pixelfmt);
if (!fmt || !fmt->sibling)
return NULL;
sibling = vpu_helper_find_format(inst, type, fmt->sibling);
if (!sibling || sibling->sibling != fmt->pixfmt ||
sibling->comp_planes != fmt->comp_planes)
return NULL;
return sibling;
}
bool vpu_helper_match_format(struct vpu_inst *inst, u32 type, u32 fmta, u32 fmtb)
{
const struct vpu_format *sibling;
if (fmta == fmtb)
return true;
sibling = vpu_helper_find_sibling(inst, type, fmta);
if (sibling && sibling->pixfmt == fmtb)
return true;
return false;
}
const struct vpu_format *vpu_helper_enum_format(struct vpu_inst *inst, u32 type, int index)
{
const struct vpu_format *pfmt;
int i = 0;
if (!inst || !inst->formats)
return NULL;
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
if (!vpu_iface_check_format(inst, pfmt->pixfmt))
continue;
if (pfmt->type == type) {
if (index == i)
return pfmt;
i++;
}
}
return NULL;
}
u32 vpu_helper_valid_frame_width(struct vpu_inst *inst, u32 width)
{
const struct vpu_core_resources *res;
if (!inst)
return width;
res = vpu_get_resource(inst);
if (!res)
return width;
if (res->max_width)
width = clamp(width, res->min_width, res->max_width);
if (res->step_width)
width = ALIGN(width, res->step_width);
return width;
}
u32 vpu_helper_valid_frame_height(struct vpu_inst *inst, u32 height)
{
const struct vpu_core_resources *res;
if (!inst)
return height;
res = vpu_get_resource(inst);
if (!res)
return height;
if (res->max_height)
height = clamp(height, res->min_height, res->max_height);
if (res->step_height)
height = ALIGN(height, res->step_height);
return height;
}
static u32 get_nv12_plane_size(u32 width, u32 height, int plane_no,
u32 stride, u32 interlaced, u32 *pbl)
{
u32 bytesperline;
u32 size = 0;
bytesperline = width;
if (pbl)
bytesperline = max(bytesperline, *pbl);
bytesperline = ALIGN(bytesperline, stride);
height = ALIGN(height, 2);
if (plane_no == 0)
size = bytesperline * height;
else if (plane_no == 1)
size = bytesperline * height >> 1;
if (pbl)
*pbl = bytesperline;
return size;
}
static u32 get_tiled_8l128_plane_size(u32 fmt, u32 width, u32 height, int plane_no,
u32 stride, u32 interlaced, u32 *pbl)
{
u32 ws = 3;
u32 hs = 7;
u32 bitdepth = 8;
u32 bytesperline;
u32 size = 0;
if (interlaced)
hs++;
if (fmt == V4L2_PIX_FMT_NV12M_10BE_8L128 || fmt == V4L2_PIX_FMT_NV12_10BE_8L128)
bitdepth = 10;
bytesperline = DIV_ROUND_UP(width * bitdepth, BITS_PER_BYTE);
if (pbl)
bytesperline = max(bytesperline, *pbl);
bytesperline = ALIGN(bytesperline, 1 << ws);
bytesperline = ALIGN(bytesperline, stride);
height = ALIGN(height, 1 << hs);
if (plane_no == 0)
size = bytesperline * height;
else if (plane_no == 1)
size = (bytesperline * ALIGN(height, 1 << (hs + 1))) >> 1;
if (pbl)
*pbl = bytesperline;
return size;
}
static u32 get_default_plane_size(u32 width, u32 height, int plane_no,
u32 stride, u32 interlaced, u32 *pbl)
{
u32 bytesperline;
u32 size = 0;
bytesperline = width;
if (pbl)
bytesperline = max(bytesperline, *pbl);
bytesperline = ALIGN(bytesperline, stride);
if (plane_no == 0)
size = bytesperline * height;
if (pbl)
*pbl = bytesperline;
return size;
}
u32 vpu_helper_get_plane_size(u32 fmt, u32 w, u32 h, int plane_no,
u32 stride, u32 interlaced, u32 *pbl)
{
switch (fmt) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV12M:
return get_nv12_plane_size(w, h, plane_no, stride, interlaced, pbl);
case V4L2_PIX_FMT_NV12_8L128:
case V4L2_PIX_FMT_NV12M_8L128:
case V4L2_PIX_FMT_NV12_10BE_8L128:
case V4L2_PIX_FMT_NV12M_10BE_8L128:
return get_tiled_8l128_plane_size(fmt, w, h, plane_no, stride, interlaced, pbl);
default:
return get_default_plane_size(w, h, plane_no, stride, interlaced, pbl);
}
}
int vpu_helper_copy_from_stream_buffer(struct vpu_buffer *stream_buffer,
u32 *rptr, u32 size, void *dst)
{
u32 offset;
u32 start;
u32 end;
void *virt;
if (!stream_buffer || !rptr || !dst)
return -EINVAL;
if (!size)
return 0;
offset = *rptr;
start = stream_buffer->phys;
end = start + stream_buffer->length;
virt = stream_buffer->virt;
if (offset < start || offset > end)
return -EINVAL;
if (offset + size <= end) {
memcpy(dst, virt + (offset - start), size);
} else {
memcpy(dst, virt + (offset - start), end - offset);
memcpy(dst + end - offset, virt, size + offset - end);
}
*rptr = vpu_helper_step_walk(stream_buffer, offset, size);
return 0;
}
int vpu_helper_copy_to_stream_buffer(struct vpu_buffer *stream_buffer,
u32 *wptr, u32 size, void *src)
{
u32 offset;
u32 start;
u32 end;
void *virt;
if (!stream_buffer || !wptr || !src)
return -EINVAL;
if (!size)
return 0;
offset = *wptr;
start = stream_buffer->phys;
end = start + stream_buffer->length;
virt = stream_buffer->virt;
if (offset < start || offset > end)
return -EINVAL;
if (offset + size <= end) {
memcpy(virt + (offset - start), src, size);
} else {
memcpy(virt + (offset - start), src, end - offset);
memcpy(virt, src + end - offset, size + offset - end);
}
*wptr = vpu_helper_step_walk(stream_buffer, offset, size);
return 0;
}
int vpu_helper_memset_stream_buffer(struct vpu_buffer *stream_buffer,
u32 *wptr, u8 val, u32 size)
{
u32 offset;
u32 start;
u32 end;
void *virt;
if (!stream_buffer || !wptr)
return -EINVAL;
if (!size)
return 0;
offset = *wptr;
start = stream_buffer->phys;
end = start + stream_buffer->length;
virt = stream_buffer->virt;
if (offset < start || offset > end)
return -EINVAL;
if (offset + size <= end) {
memset(virt + (offset - start), val, size);
} else {
memset(virt + (offset - start), val, end - offset);
memset(virt, val, size + offset - end);
}
offset += size;
if (offset >= end)
offset -= stream_buffer->length;
*wptr = offset;
return 0;
}
u32 vpu_helper_get_free_space(struct vpu_inst *inst)
{
struct vpu_rpc_buffer_desc desc;
if (vpu_iface_get_stream_buffer_desc(inst, &desc))
return 0;
if (desc.rptr > desc.wptr)
return desc.rptr - desc.wptr;
else if (desc.rptr < desc.wptr)
return (desc.end - desc.start + desc.rptr - desc.wptr);
else
return desc.end - desc.start;
}
u32 vpu_helper_get_used_space(struct vpu_inst *inst)
{
struct vpu_rpc_buffer_desc desc;
if (vpu_iface_get_stream_buffer_desc(inst, &desc))
return 0;
if (desc.wptr > desc.rptr)
return desc.wptr - desc.rptr;
else if (desc.wptr < desc.rptr)
return (desc.end - desc.start + desc.wptr - desc.rptr);
else
return 0;
}
int vpu_helper_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct vpu_inst *inst = ctrl_to_inst(ctrl);
switch (ctrl->id) {
case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
ctrl->val = inst->min_buffer_cap;
break;
case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
ctrl->val = inst->min_buffer_out;
break;
default:
return -EINVAL;
}
return 0;
}
int vpu_helper_find_startcode(struct vpu_buffer *stream_buffer,
u32 pixelformat, u32 offset, u32 bytesused)
{
u32 start_code;
int start_code_size;
u32 val = 0;
int i;
int ret = -EINVAL;
if (!stream_buffer || !stream_buffer->virt)
return -EINVAL;
switch (pixelformat) {
case V4L2_PIX_FMT_H264:
start_code_size = 4;
start_code = 0x00000001;
break;
default:
return 0;
}
for (i = 0; i < bytesused; i++) {
val = (val << 8) | vpu_helper_read_byte(stream_buffer, offset + i);
if (i < start_code_size - 1)
continue;
if (val == start_code) {
ret = i + 1 - start_code_size;
break;
}
}
return ret;
}
int vpu_find_dst_by_src(struct vpu_pair *pairs, u32 cnt, u32 src)
{
u32 i;
if (!pairs || !cnt)
return -EINVAL;
for (i = 0; i < cnt; i++) {
if (pairs[i].src == src)
return pairs[i].dst;
}
return -EINVAL;
}
int vpu_find_src_by_dst(struct vpu_pair *pairs, u32 cnt, u32 dst)
{
u32 i;
if (!pairs || !cnt)
return -EINVAL;
for (i = 0; i < cnt; i++) {
if (pairs[i].dst == dst)
return pairs[i].src;
}
return -EINVAL;
}
const char *vpu_id_name(u32 id)
{
switch (id) {
case VPU_CMD_ID_NOOP: return "noop";
case VPU_CMD_ID_CONFIGURE_CODEC: return "configure codec";
case VPU_CMD_ID_START: return "start";
case VPU_CMD_ID_STOP: return "stop";
case VPU_CMD_ID_ABORT: return "abort";
case VPU_CMD_ID_RST_BUF: return "reset buf";
case VPU_CMD_ID_SNAPSHOT: return "snapshot";
case VPU_CMD_ID_FIRM_RESET: return "reset firmware";
case VPU_CMD_ID_UPDATE_PARAMETER: return "update parameter";
case VPU_CMD_ID_FRAME_ENCODE: return "encode frame";
case VPU_CMD_ID_SKIP: return "skip";
case VPU_CMD_ID_FS_ALLOC: return "alloc fb";
case VPU_CMD_ID_FS_RELEASE: return "release fb";
case VPU_CMD_ID_TIMESTAMP: return "timestamp";
case VPU_CMD_ID_DEBUG: return "debug";
case VPU_MSG_ID_RESET_DONE: return "reset done";
case VPU_MSG_ID_START_DONE: return "start done";
case VPU_MSG_ID_STOP_DONE: return "stop done";
case VPU_MSG_ID_ABORT_DONE: return "abort done";
case VPU_MSG_ID_BUF_RST: return "buf reset done";
case VPU_MSG_ID_MEM_REQUEST: return "mem request";
case VPU_MSG_ID_PARAM_UPD_DONE: return "param upd done";
case VPU_MSG_ID_FRAME_INPUT_DONE: return "frame input done";
case VPU_MSG_ID_ENC_DONE: return "encode done";
case VPU_MSG_ID_DEC_DONE: return "frame display";
case VPU_MSG_ID_FRAME_REQ: return "fb request";
case VPU_MSG_ID_FRAME_RELEASE: return "fb release";
case VPU_MSG_ID_SEQ_HDR_FOUND: return "seq hdr found";
case VPU_MSG_ID_RES_CHANGE: return "resolution change";
case VPU_MSG_ID_PIC_HDR_FOUND: return "pic hdr found";
case VPU_MSG_ID_PIC_DECODED: return "picture decoded";
case VPU_MSG_ID_PIC_EOS: return "eos";
case VPU_MSG_ID_FIFO_LOW: return "fifo low";
case VPU_MSG_ID_BS_ERROR: return "bs error";
case VPU_MSG_ID_UNSUPPORTED: return "unsupported";
case VPU_MSG_ID_FIRMWARE_XCPT: return "exception";
case VPU_MSG_ID_PIC_SKIPPED: return "skipped";
}
return "<unknown>";
}
const char *vpu_codec_state_name(enum vpu_codec_state state)
{
switch (state) {
case VPU_CODEC_STATE_DEINIT: return "initialization";
case VPU_CODEC_STATE_CONFIGURED: return "configured";
case VPU_CODEC_STATE_START: return "start";
case VPU_CODEC_STATE_STARTED: return "started";
case VPU_CODEC_STATE_ACTIVE: return "active";
case VPU_CODEC_STATE_SEEK: return "seek";
case VPU_CODEC_STATE_STOP: return "stop";
case VPU_CODEC_STATE_DRAIN: return "drain";
case VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE: return "resolution change";
}
return "<unknown>";
}
| linux-master | drivers/media/platform/amphion/vpu_helpers.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP
*/
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/svc/misc.h>
#include "vpu.h"
#include "vpu_rpc.h"
#include "vpu_imx8q.h"
#include "vpu_windsor.h"
#include "vpu_malone.h"
int vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size)
{
struct vpu_iface_ops *ops = vpu_core_get_iface(core);
if (!ops || !ops->check_memory_region)
return VPU_CORE_MEMORY_INVALID;
return ops->check_memory_region(core->fw.phys, addr, size);
}
static u32 vpu_rpc_check_buffer_space(struct vpu_rpc_buffer_desc *desc, bool write)
{
u32 ptr1;
u32 ptr2;
u32 size;
size = desc->end - desc->start;
if (write) {
ptr1 = desc->wptr;
ptr2 = desc->rptr;
} else {
ptr1 = desc->rptr;
ptr2 = desc->wptr;
}
if (ptr1 == ptr2) {
if (!write)
return 0;
else
return size;
}
return (ptr2 + size - ptr1) % size;
}
static int vpu_rpc_send_cmd_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *cmd)
{
struct vpu_rpc_buffer_desc *desc;
u32 space = 0;
u32 *data;
u32 wptr;
u32 i;
if (cmd->hdr.num > 0xff || cmd->hdr.num >= ARRAY_SIZE(cmd->data))
return -EINVAL;
desc = shared->cmd_desc;
space = vpu_rpc_check_buffer_space(desc, true);
if (space < (((cmd->hdr.num + 1) << 2) + 16))
return -EINVAL;
wptr = desc->wptr;
data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start);
*data = 0;
*data |= ((cmd->hdr.index & 0xff) << 24);
*data |= ((cmd->hdr.num & 0xff) << 16);
*data |= (cmd->hdr.id & 0x3fff);
wptr += 4;
data++;
if (wptr >= desc->end) {
wptr = desc->start;
data = shared->cmd_mem_vir;
}
for (i = 0; i < cmd->hdr.num; i++) {
*data = cmd->data[i];
wptr += 4;
data++;
if (wptr >= desc->end) {
wptr = desc->start;
data = shared->cmd_mem_vir;
}
}
/*update wptr after data is written*/
mb();
desc->wptr = wptr;
return 0;
}
static bool vpu_rpc_check_msg(struct vpu_shared_addr *shared)
{
struct vpu_rpc_buffer_desc *desc;
u32 space = 0;
u32 msgword;
u32 msgnum;
desc = shared->msg_desc;
space = vpu_rpc_check_buffer_space(desc, 0);
space = (space >> 2);
if (space) {
msgword = *(u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
msgnum = (msgword & 0xff0000) >> 16;
if (msgnum <= space)
return true;
}
return false;
}
static int vpu_rpc_receive_msg_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *msg)
{
struct vpu_rpc_buffer_desc *desc;
u32 *data;
u32 msgword;
u32 rptr;
u32 i;
if (!vpu_rpc_check_msg(shared))
return -EINVAL;
desc = shared->msg_desc;
data = (u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
rptr = desc->rptr;
msgword = *data;
data++;
rptr += 4;
if (rptr >= desc->end) {
rptr = desc->start;
data = shared->msg_mem_vir;
}
msg->hdr.index = (msgword >> 24) & 0xff;
msg->hdr.num = (msgword >> 16) & 0xff;
msg->hdr.id = msgword & 0x3fff;
if (msg->hdr.num > ARRAY_SIZE(msg->data))
return -EINVAL;
for (i = 0; i < msg->hdr.num; i++) {
msg->data[i] = *data;
data++;
rptr += 4;
if (rptr >= desc->end) {
rptr = desc->start;
data = shared->msg_mem_vir;
}
}
/*update rptr after data is read*/
mb();
desc->rptr = rptr;
return 0;
}
static struct vpu_iface_ops imx8q_rpc_ops[] = {
[VPU_CORE_TYPE_ENC] = {
.check_codec = vpu_imx8q_check_codec,
.check_fmt = vpu_imx8q_check_fmt,
.boot_core = vpu_imx8q_boot_core,
.get_power_state = vpu_imx8q_get_power_state,
.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
.get_data_size = vpu_windsor_get_data_size,
.check_memory_region = vpu_imx8q_check_memory_region,
.init_rpc = vpu_windsor_init_rpc,
.set_log_buf = vpu_windsor_set_log_buf,
.set_system_cfg = vpu_windsor_set_system_cfg,
.get_version = vpu_windsor_get_version,
.send_cmd_buf = vpu_rpc_send_cmd_buf,
.receive_msg_buf = vpu_rpc_receive_msg_buf,
.pack_cmd = vpu_windsor_pack_cmd,
.convert_msg_id = vpu_windsor_convert_msg_id,
.unpack_msg_data = vpu_windsor_unpack_msg_data,
.config_memory_resource = vpu_windsor_config_memory_resource,
.get_stream_buffer_size = vpu_windsor_get_stream_buffer_size,
.config_stream_buffer = vpu_windsor_config_stream_buffer,
.get_stream_buffer_desc = vpu_windsor_get_stream_buffer_desc,
.update_stream_buffer = vpu_windsor_update_stream_buffer,
.set_encode_params = vpu_windsor_set_encode_params,
.input_frame = vpu_windsor_input_frame,
.get_max_instance_count = vpu_windsor_get_max_instance_count,
},
[VPU_CORE_TYPE_DEC] = {
.check_codec = vpu_imx8q_check_codec,
.check_fmt = vpu_malone_check_fmt,
.boot_core = vpu_imx8q_boot_core,
.get_power_state = vpu_imx8q_get_power_state,
.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
.get_data_size = vpu_malone_get_data_size,
.check_memory_region = vpu_imx8q_check_memory_region,
.init_rpc = vpu_malone_init_rpc,
.set_log_buf = vpu_malone_set_log_buf,
.set_system_cfg = vpu_malone_set_system_cfg,
.get_version = vpu_malone_get_version,
.send_cmd_buf = vpu_rpc_send_cmd_buf,
.receive_msg_buf = vpu_rpc_receive_msg_buf,
.get_stream_buffer_size = vpu_malone_get_stream_buffer_size,
.config_stream_buffer = vpu_malone_config_stream_buffer,
.set_decode_params = vpu_malone_set_decode_params,
.pack_cmd = vpu_malone_pack_cmd,
.convert_msg_id = vpu_malone_convert_msg_id,
.unpack_msg_data = vpu_malone_unpack_msg_data,
.get_stream_buffer_desc = vpu_malone_get_stream_buffer_desc,
.update_stream_buffer = vpu_malone_update_stream_buffer,
.add_scode = vpu_malone_add_scode,
.input_frame = vpu_malone_input_frame,
.pre_send_cmd = vpu_malone_pre_cmd,
.post_send_cmd = vpu_malone_post_cmd,
.init_instance = vpu_malone_init_instance,
.get_max_instance_count = vpu_malone_get_max_instance_count,
},
};
static struct vpu_iface_ops *vpu_get_iface(struct vpu_dev *vpu, enum vpu_core_type type)
{
struct vpu_iface_ops *rpc_ops = NULL;
u32 size = 0;
switch (vpu->res->plat_type) {
case IMX8QXP:
case IMX8QM:
rpc_ops = imx8q_rpc_ops;
size = ARRAY_SIZE(imx8q_rpc_ops);
break;
default:
return NULL;
}
if (type >= size)
return NULL;
return &rpc_ops[type];
}
struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core)
{
return vpu_get_iface(core->vpu, core->type);
}
struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst)
{
if (inst->core)
return vpu_core_get_iface(inst->core);
return vpu_get_iface(inst->vpu, inst->type);
}
| linux-master | drivers/media/platform/amphion/vpu_rpc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* V4L2 Capture CSI Subdev for Freescale i.MX6UL/L / i.MX7 SOC
*
* Copyright (c) 2019 Linaro Ltd
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/math.h>
#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mc.h>
#include <media/v4l2-subdev.h>
#include <media/videobuf2-dma-contig.h>
#define IMX7_CSI_PAD_SINK 0
#define IMX7_CSI_PAD_SRC 1
#define IMX7_CSI_PADS_NUM 2
/* csi control reg 1 */
#define BIT_SWAP16_EN BIT(31)
#define BIT_EXT_VSYNC BIT(30)
#define BIT_EOF_INT_EN BIT(29)
#define BIT_PRP_IF_EN BIT(28)
#define BIT_CCIR_MODE BIT(27)
#define BIT_COF_INT_EN BIT(26)
#define BIT_SF_OR_INTEN BIT(25)
#define BIT_RF_OR_INTEN BIT(24)
#define BIT_SFF_DMA_DONE_INTEN BIT(22)
#define BIT_STATFF_INTEN BIT(21)
#define BIT_FB2_DMA_DONE_INTEN BIT(20)
#define BIT_FB1_DMA_DONE_INTEN BIT(19)
#define BIT_RXFF_INTEN BIT(18)
#define BIT_SOF_POL BIT(17)
#define BIT_SOF_INTEN BIT(16)
#define BIT_MCLKDIV(n) ((n) << 12)
#define BIT_MCLKDIV_MASK (0xf << 12)
#define BIT_HSYNC_POL BIT(11)
#define BIT_CCIR_EN BIT(10)
#define BIT_MCLKEN BIT(9)
#define BIT_FCC BIT(8)
#define BIT_PACK_DIR BIT(7)
#define BIT_CLR_STATFIFO BIT(6)
#define BIT_CLR_RXFIFO BIT(5)
#define BIT_GCLK_MODE BIT(4)
#define BIT_INV_DATA BIT(3)
#define BIT_INV_PCLK BIT(2)
#define BIT_REDGE BIT(1)
#define BIT_PIXEL_BIT BIT(0)
/* control reg 2 */
#define BIT_DMA_BURST_TYPE_RFF_INCR4 (1 << 30)
#define BIT_DMA_BURST_TYPE_RFF_INCR8 (2 << 30)
#define BIT_DMA_BURST_TYPE_RFF_INCR16 (3 << 30)
#define BIT_DMA_BURST_TYPE_RFF_MASK (3 << 30)
/* control reg 3 */
#define BIT_FRMCNT(n) ((n) << 16)
#define BIT_FRMCNT_MASK (0xffff << 16)
#define BIT_FRMCNT_RST BIT(15)
#define BIT_DMA_REFLASH_RFF BIT(14)
#define BIT_DMA_REFLASH_SFF BIT(13)
#define BIT_DMA_REQ_EN_RFF BIT(12)
#define BIT_DMA_REQ_EN_SFF BIT(11)
#define BIT_STATFF_LEVEL(n) ((n) << 8)
#define BIT_STATFF_LEVEL_MASK (0x7 << 8)
#define BIT_HRESP_ERR_EN BIT(7)
#define BIT_RXFF_LEVEL(n) ((n) << 4)
#define BIT_RXFF_LEVEL_MASK (0x7 << 4)
#define BIT_TWO_8BIT_SENSOR BIT(3)
#define BIT_ZERO_PACK_EN BIT(2)
#define BIT_ECC_INT_EN BIT(1)
#define BIT_ECC_AUTO_EN BIT(0)
/* csi status reg */
#define BIT_ADDR_CH_ERR_INT BIT(28)
#define BIT_FIELD0_INT BIT(27)
#define BIT_FIELD1_INT BIT(26)
#define BIT_SFF_OR_INT BIT(25)
#define BIT_RFF_OR_INT BIT(24)
#define BIT_DMA_TSF_DONE_SFF BIT(22)
#define BIT_STATFF_INT BIT(21)
#define BIT_DMA_TSF_DONE_FB2 BIT(20)
#define BIT_DMA_TSF_DONE_FB1 BIT(19)
#define BIT_RXFF_INT BIT(18)
#define BIT_EOF_INT BIT(17)
#define BIT_SOF_INT BIT(16)
#define BIT_F2_INT BIT(15)
#define BIT_F1_INT BIT(14)
#define BIT_COF_INT BIT(13)
#define BIT_HRESP_ERR_INT BIT(7)
#define BIT_ECC_INT BIT(1)
#define BIT_DRDY BIT(0)
/* csi image parameter reg */
#define BIT_IMAGE_WIDTH(n) ((n) << 16)
#define BIT_IMAGE_HEIGHT(n) (n)
/* csi control reg 18 */
#define BIT_CSI_HW_ENABLE BIT(31)
#define BIT_MIPI_DATA_FORMAT_RAW8 (0x2a << 25)
#define BIT_MIPI_DATA_FORMAT_RAW10 (0x2b << 25)
#define BIT_MIPI_DATA_FORMAT_RAW12 (0x2c << 25)
#define BIT_MIPI_DATA_FORMAT_RAW14 (0x2d << 25)
#define BIT_MIPI_DATA_FORMAT_YUV422_8B (0x1e << 25)
#define BIT_MIPI_DATA_FORMAT_MASK (0x3f << 25)
#define BIT_DATA_FROM_MIPI BIT(22)
#define BIT_MIPI_YU_SWAP BIT(21)
#define BIT_MIPI_DOUBLE_CMPNT BIT(20)
#define BIT_MASK_OPTION_FIRST_FRAME (0 << 18)
#define BIT_MASK_OPTION_CSI_EN (1 << 18)
#define BIT_MASK_OPTION_SECOND_FRAME (2 << 18)
#define BIT_MASK_OPTION_ON_DATA (3 << 18)
#define BIT_BASEADDR_CHG_ERR_EN BIT(9)
#define BIT_BASEADDR_SWITCH_SEL BIT(5)
#define BIT_BASEADDR_SWITCH_EN BIT(4)
#define BIT_PARALLEL24_EN BIT(3)
#define BIT_DEINTERLACE_EN BIT(2)
#define BIT_TVDECODER_IN_EN BIT(1)
#define BIT_NTSC_EN BIT(0)
#define CSI_MCLK_VF 1
#define CSI_MCLK_ENC 2
#define CSI_MCLK_RAW 4
#define CSI_MCLK_I2C 8
#define CSI_CSICR1 0x00
#define CSI_CSICR2 0x04
#define CSI_CSICR3 0x08
#define CSI_STATFIFO 0x0c
#define CSI_CSIRXFIFO 0x10
#define CSI_CSIRXCNT 0x14
#define CSI_CSISR 0x18
#define CSI_CSIDBG 0x1c
#define CSI_CSIDMASA_STATFIFO 0x20
#define CSI_CSIDMATS_STATFIFO 0x24
#define CSI_CSIDMASA_FB1 0x28
#define CSI_CSIDMASA_FB2 0x2c
#define CSI_CSIFBUF_PARA 0x30
#define CSI_CSIIMAG_PARA 0x34
#define CSI_CSICR18 0x48
#define CSI_CSICR19 0x4c
#define IMX7_CSI_VIDEO_NAME "imx-capture"
/* In bytes, per queue */
#define IMX7_CSI_VIDEO_MEM_LIMIT SZ_512M
#define IMX7_CSI_VIDEO_EOF_TIMEOUT 2000
#define IMX7_CSI_DEF_MBUS_CODE MEDIA_BUS_FMT_UYVY8_2X8
#define IMX7_CSI_DEF_PIX_FORMAT V4L2_PIX_FMT_UYVY
#define IMX7_CSI_DEF_PIX_WIDTH 640
#define IMX7_CSI_DEF_PIX_HEIGHT 480
enum imx_csi_model {
IMX7_CSI_IMX7 = 0,
IMX7_CSI_IMX8MQ,
};
struct imx7_csi_pixfmt {
/* the in-memory FourCC pixel format */
u32 fourcc;
/*
* the set of equivalent media bus codes for the fourcc.
* NOTE! codes pointer is NULL for in-memory-only formats.
*/
const u32 *codes;
int bpp; /* total bpp */
bool yuv;
};
struct imx7_csi_vb2_buffer {
struct vb2_v4l2_buffer vbuf;
struct list_head list;
};
static inline struct imx7_csi_vb2_buffer *
to_imx7_csi_vb2_buffer(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
return container_of(vbuf, struct imx7_csi_vb2_buffer, vbuf);
}
struct imx7_csi_dma_buf {
void *virt;
dma_addr_t dma_addr;
unsigned long len;
};
struct imx7_csi {
struct device *dev;
/* Resources and locks */
void __iomem *regbase;
int irq;
struct clk *mclk;
spinlock_t irqlock; /* Protects last_eof */
/* Media and V4L2 device */
struct media_device mdev;
struct v4l2_device v4l2_dev;
struct v4l2_async_notifier notifier;
struct media_pipeline pipe;
struct v4l2_subdev *src_sd;
bool is_csi2;
/* V4L2 subdev */
struct v4l2_subdev sd;
struct media_pad pad[IMX7_CSI_PADS_NUM];
/* Video device */
struct video_device *vdev; /* Video device */
struct media_pad vdev_pad; /* Video device pad */
struct v4l2_pix_format vdev_fmt; /* The user format */
const struct imx7_csi_pixfmt *vdev_cc;
struct v4l2_rect vdev_compose; /* The compose rectangle */
struct mutex vdev_mutex; /* Protect vdev operations */
struct vb2_queue q; /* The videobuf2 queue */
struct list_head ready_q; /* List of queued buffers */
spinlock_t q_lock; /* Protect ready_q */
/* Buffers and streaming state */
struct imx7_csi_vb2_buffer *active_vb2_buf[2];
struct imx7_csi_dma_buf underrun_buf;
bool is_streaming;
int buf_num;
u32 frame_sequence;
bool last_eof;
struct completion last_eof_completion;
enum imx_csi_model model;
};
static struct imx7_csi *
imx7_csi_notifier_to_dev(struct v4l2_async_notifier *n)
{
return container_of(n, struct imx7_csi, notifier);
}
/* -----------------------------------------------------------------------------
* Hardware Configuration
*/
static u32 imx7_csi_reg_read(struct imx7_csi *csi, unsigned int offset)
{
return readl(csi->regbase + offset);
}
static void imx7_csi_reg_write(struct imx7_csi *csi, unsigned int value,
unsigned int offset)
{
writel(value, csi->regbase + offset);
}
static u32 imx7_csi_irq_clear(struct imx7_csi *csi)
{
u32 isr;
isr = imx7_csi_reg_read(csi, CSI_CSISR);
imx7_csi_reg_write(csi, isr, CSI_CSISR);
return isr;
}
static void imx7_csi_init_default(struct imx7_csi *csi)
{
imx7_csi_reg_write(csi, BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE |
BIT_HSYNC_POL | BIT_FCC | BIT_MCLKDIV(1) |
BIT_MCLKEN, CSI_CSICR1);
imx7_csi_reg_write(csi, 0, CSI_CSICR2);
imx7_csi_reg_write(csi, BIT_FRMCNT_RST, CSI_CSICR3);
imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(IMX7_CSI_DEF_PIX_WIDTH) |
BIT_IMAGE_HEIGHT(IMX7_CSI_DEF_PIX_HEIGHT),
CSI_CSIIMAG_PARA);
imx7_csi_reg_write(csi, BIT_DMA_REFLASH_RFF, CSI_CSICR3);
}
static void imx7_csi_hw_enable_irq(struct imx7_csi *csi)
{
u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
cr1 |= BIT_RFF_OR_INT;
cr1 |= BIT_FB1_DMA_DONE_INTEN;
cr1 |= BIT_FB2_DMA_DONE_INTEN;
imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
}
static void imx7_csi_hw_disable_irq(struct imx7_csi *csi)
{
u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
cr1 &= ~BIT_RFF_OR_INT;
cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
}
static void imx7_csi_hw_enable(struct imx7_csi *csi)
{
u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
cr |= BIT_CSI_HW_ENABLE;
imx7_csi_reg_write(csi, cr, CSI_CSICR18);
}
static void imx7_csi_hw_disable(struct imx7_csi *csi)
{
u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
cr &= ~BIT_CSI_HW_ENABLE;
imx7_csi_reg_write(csi, cr, CSI_CSICR18);
}
static void imx7_csi_dma_reflash(struct imx7_csi *csi)
{
u32 cr3;
cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
cr3 |= BIT_DMA_REFLASH_RFF;
imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
}
static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi)
{
u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1) & ~BIT_FCC;
imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);
}
static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi)
{
u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
cr3 |= BIT_DMA_REQ_EN_RFF;
cr3 |= BIT_HRESP_ERR_EN;
cr3 &= ~BIT_RXFF_LEVEL_MASK;
cr3 |= BIT_RXFF_LEVEL(2);
imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
}
static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi)
{
u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
cr3 &= ~BIT_DMA_REQ_EN_RFF;
cr3 &= ~BIT_HRESP_ERR_EN;
imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
}
static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t dma_addr,
int buf_num)
{
if (buf_num == 1)
imx7_csi_reg_write(csi, dma_addr, CSI_CSIDMASA_FB2);
else
imx7_csi_reg_write(csi, dma_addr, CSI_CSIDMASA_FB1);
}
static struct imx7_csi_vb2_buffer *imx7_csi_video_next_buf(struct imx7_csi *csi);
static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi)
{
struct imx7_csi_vb2_buffer *buf;
struct vb2_buffer *vb2_buf;
int i;
for (i = 0; i < 2; i++) {
dma_addr_t dma_addr;
buf = imx7_csi_video_next_buf(csi);
if (buf) {
csi->active_vb2_buf[i] = buf;
vb2_buf = &buf->vbuf.vb2_buf;
dma_addr = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
} else {
csi->active_vb2_buf[i] = NULL;
dma_addr = csi->underrun_buf.dma_addr;
}
imx7_csi_update_buf(csi, dma_addr, i);
}
}
static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi,
enum vb2_buffer_state return_status)
{
struct imx7_csi_vb2_buffer *buf;
int i;
/* return any remaining active frames with return_status */
for (i = 0; i < 2; i++) {
buf = csi->active_vb2_buf[i];
if (buf) {
struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
vb->timestamp = ktime_get_ns();
vb2_buffer_done(vb, return_status);
csi->active_vb2_buf[i] = NULL;
}
}
}
static void imx7_csi_free_dma_buf(struct imx7_csi *csi,
struct imx7_csi_dma_buf *buf)
{
if (buf->virt)
dma_free_coherent(csi->dev, buf->len, buf->virt, buf->dma_addr);
buf->virt = NULL;
buf->dma_addr = 0;
}
static int imx7_csi_alloc_dma_buf(struct imx7_csi *csi,
struct imx7_csi_dma_buf *buf, int size)
{
imx7_csi_free_dma_buf(csi, buf);
buf->len = PAGE_ALIGN(size);
buf->virt = dma_alloc_coherent(csi->dev, buf->len, &buf->dma_addr,
GFP_DMA | GFP_KERNEL);
if (!buf->virt)
return -ENOMEM;
return 0;
}
static int imx7_csi_dma_setup(struct imx7_csi *csi)
{
int ret;
ret = imx7_csi_alloc_dma_buf(csi, &csi->underrun_buf,
csi->vdev_fmt.sizeimage);
if (ret < 0) {
v4l2_warn(&csi->sd, "consider increasing the CMA area\n");
return ret;
}
csi->frame_sequence = 0;
csi->last_eof = false;
init_completion(&csi->last_eof_completion);
imx7_csi_setup_vb2_buf(csi);
return 0;
}
static void imx7_csi_dma_cleanup(struct imx7_csi *csi,
enum vb2_buffer_state return_status)
{
imx7_csi_dma_unsetup_vb2_buf(csi, return_status);
imx7_csi_free_dma_buf(csi, &csi->underrun_buf);
}
static void imx7_csi_dma_stop(struct imx7_csi *csi)
{
unsigned long timeout_jiffies;
unsigned long flags;
int ret;
/* mark next EOF interrupt as the last before stream off */
spin_lock_irqsave(&csi->irqlock, flags);
csi->last_eof = true;
spin_unlock_irqrestore(&csi->irqlock, flags);
/*
* and then wait for interrupt handler to mark completion.
*/
timeout_jiffies = msecs_to_jiffies(IMX7_CSI_VIDEO_EOF_TIMEOUT);
ret = wait_for_completion_timeout(&csi->last_eof_completion,
timeout_jiffies);
if (ret == 0)
v4l2_warn(&csi->sd, "wait last EOF timeout\n");
imx7_csi_hw_disable_irq(csi);
}
static void imx7_csi_configure(struct imx7_csi *csi,
struct v4l2_subdev_state *sd_state)
{
struct v4l2_pix_format *out_pix = &csi->vdev_fmt;
int width = out_pix->width;
u32 stride = 0;
u32 cr3 = BIT_FRMCNT_RST;
u32 cr1, cr18;
cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
cr18 &= ~(BIT_CSI_HW_ENABLE | BIT_MIPI_DATA_FORMAT_MASK |
BIT_DATA_FROM_MIPI | BIT_MIPI_DOUBLE_CMPNT |
BIT_BASEADDR_CHG_ERR_EN | BIT_BASEADDR_SWITCH_SEL |
BIT_BASEADDR_SWITCH_EN | BIT_DEINTERLACE_EN);
if (out_pix->field == V4L2_FIELD_INTERLACED) {
cr18 |= BIT_DEINTERLACE_EN;
stride = out_pix->width;
}
if (!csi->is_csi2) {
cr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL
| BIT_FCC | BIT_MCLKDIV(1) | BIT_MCLKEN;
cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
BIT_BASEADDR_CHG_ERR_EN;
if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
width *= 2;
} else {
const struct v4l2_mbus_framefmt *sink_fmt;
sink_fmt = v4l2_subdev_get_pad_format(&csi->sd, sd_state,
IMX7_CSI_PAD_SINK);
cr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC
| BIT_MCLKDIV(1) | BIT_MCLKEN;
cr18 |= BIT_DATA_FROM_MIPI;
switch (sink_fmt->code) {
case MEDIA_BUS_FMT_Y8_1X8:
case MEDIA_BUS_FMT_SBGGR8_1X8:
case MEDIA_BUS_FMT_SGBRG8_1X8:
case MEDIA_BUS_FMT_SGRBG8_1X8:
case MEDIA_BUS_FMT_SRGGB8_1X8:
cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
break;
case MEDIA_BUS_FMT_Y10_1X10:
case MEDIA_BUS_FMT_SBGGR10_1X10:
case MEDIA_BUS_FMT_SGBRG10_1X10:
case MEDIA_BUS_FMT_SGRBG10_1X10:
case MEDIA_BUS_FMT_SRGGB10_1X10:
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
break;
case MEDIA_BUS_FMT_Y12_1X12:
case MEDIA_BUS_FMT_SBGGR12_1X12:
case MEDIA_BUS_FMT_SGBRG12_1X12:
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SRGGB12_1X12:
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
break;
case MEDIA_BUS_FMT_Y14_1X14:
case MEDIA_BUS_FMT_SBGGR14_1X14:
case MEDIA_BUS_FMT_SGBRG14_1X14:
case MEDIA_BUS_FMT_SGRBG14_1X14:
case MEDIA_BUS_FMT_SRGGB14_1X14:
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
break;
/*
* The CSI bridge has a 16-bit input bus. Depending on the
* connected source, data may be transmitted with 8 or 10 bits
* per clock sample (in bits [9:2] or [9:0] respectively) or
* with 16 bits per clock sample (in bits [15:0]). The data is
* then packed into a 32-bit FIFO (as shown in figure 13-11 of
* the i.MX8MM reference manual rev. 3).
*
* The data packing in a 32-bit FIFO input word is controlled by
* the CR3 TWO_8BIT_SENSOR field (also known as SENSOR_16BITS in
* the i.MX8MM reference manual). When set to 0, data packing
* groups four 8-bit input samples (bits [9:2]). When set to 1,
* data packing groups two 16-bit input samples (bits [15:0]).
*
* The register field CR18 MIPI_DOUBLE_CMPNT also needs to be
* configured according to the input format for YUV 4:2:2 data.
* The field controls the gasket between the CSI-2 receiver and
* the CSI bridge. On i.MX7 and i.MX8MM, the field must be set
* to 1 when the CSIS outputs 16-bit samples. On i.MX8MQ, the
* gasket ignores the MIPI_DOUBLE_CMPNT bit and YUV 4:2:2 always
* uses 16-bit samples. Setting MIPI_DOUBLE_CMPNT in that case
* has no effect, but doesn't cause any issue.
*/
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_YUYV8_2X8:
cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
break;
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_YUYV8_1X16:
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B |
BIT_MIPI_DOUBLE_CMPNT;
break;
}
}
imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
imx7_csi_reg_write(csi, BIT_DMA_BURST_TYPE_RFF_INCR16, CSI_CSICR2);
imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
imx7_csi_reg_write(csi, (width * out_pix->height) >> 2, CSI_CSIRXCNT);
imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(width) |
BIT_IMAGE_HEIGHT(out_pix->height),
CSI_CSIIMAG_PARA);
imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);
}
static int imx7_csi_init(struct imx7_csi *csi,
struct v4l2_subdev_state *sd_state)
{
int ret;
ret = clk_prepare_enable(csi->mclk);
if (ret < 0)
return ret;
imx7_csi_configure(csi, sd_state);
ret = imx7_csi_dma_setup(csi);
if (ret < 0) {
clk_disable_unprepare(csi->mclk);
return ret;
}
return 0;
}
static void imx7_csi_deinit(struct imx7_csi *csi,
enum vb2_buffer_state return_status)
{
imx7_csi_dma_cleanup(csi, return_status);
imx7_csi_init_default(csi);
imx7_csi_dmareq_rff_disable(csi);
clk_disable_unprepare(csi->mclk);
}
static void imx7_csi_baseaddr_switch_on_second_frame(struct imx7_csi *csi)
{
u32 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
BIT_BASEADDR_CHG_ERR_EN;
cr18 |= BIT_MASK_OPTION_SECOND_FRAME;
imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
}
static void imx7_csi_enable(struct imx7_csi *csi)
{
/* Clear the Rx FIFO and reflash the DMA controller. */
imx7_csi_rx_fifo_clear(csi);
imx7_csi_dma_reflash(csi);
usleep_range(2000, 3000);
/* Clear and enable the interrupts. */
imx7_csi_irq_clear(csi);
imx7_csi_hw_enable_irq(csi);
/* Enable the RxFIFO DMA and the CSI. */
imx7_csi_dmareq_rff_enable(csi);
imx7_csi_hw_enable(csi);
if (csi->model == IMX7_CSI_IMX8MQ)
imx7_csi_baseaddr_switch_on_second_frame(csi);
}
static void imx7_csi_disable(struct imx7_csi *csi)
{
imx7_csi_dma_stop(csi);
imx7_csi_dmareq_rff_disable(csi);
imx7_csi_hw_disable_irq(csi);
imx7_csi_hw_disable(csi);
}
/* -----------------------------------------------------------------------------
* Interrupt Handling
*/
static void imx7_csi_error_recovery(struct imx7_csi *csi)
{
imx7_csi_hw_disable(csi);
imx7_csi_rx_fifo_clear(csi);
imx7_csi_dma_reflash(csi);
imx7_csi_hw_enable(csi);
}
static void imx7_csi_vb2_buf_done(struct imx7_csi *csi)
{
struct imx7_csi_vb2_buffer *done, *next;
struct vb2_buffer *vb;
dma_addr_t dma_addr;
done = csi->active_vb2_buf[csi->buf_num];
if (done) {
done->vbuf.field = csi->vdev_fmt.field;
done->vbuf.sequence = csi->frame_sequence;
vb = &done->vbuf.vb2_buf;
vb->timestamp = ktime_get_ns();
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
}
csi->frame_sequence++;
/* get next queued buffer */
next = imx7_csi_video_next_buf(csi);
if (next) {
dma_addr = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);
csi->active_vb2_buf[csi->buf_num] = next;
} else {
dma_addr = csi->underrun_buf.dma_addr;
csi->active_vb2_buf[csi->buf_num] = NULL;
}
imx7_csi_update_buf(csi, dma_addr, csi->buf_num);
}
static irqreturn_t imx7_csi_irq_handler(int irq, void *data)
{
struct imx7_csi *csi = data;
u32 status;
spin_lock(&csi->irqlock);
status = imx7_csi_irq_clear(csi);
if (status & BIT_RFF_OR_INT) {
dev_warn(csi->dev, "Rx fifo overflow\n");
imx7_csi_error_recovery(csi);
}
if (status & BIT_HRESP_ERR_INT) {
dev_warn(csi->dev, "Hresponse error detected\n");
imx7_csi_error_recovery(csi);
}
if (status & BIT_ADDR_CH_ERR_INT) {
imx7_csi_hw_disable(csi);
imx7_csi_dma_reflash(csi);
imx7_csi_hw_enable(csi);
}
if ((status & BIT_DMA_TSF_DONE_FB1) &&
(status & BIT_DMA_TSF_DONE_FB2)) {
/*
* For both FB1 and FB2 interrupter bits set case,
* CSI DMA is work in one of FB1 and FB2 buffer,
* but software can not know the state.
* Skip it to avoid base address updated
* when csi work in field0 and field1 will write to
* new base address.
*/
} else if (status & BIT_DMA_TSF_DONE_FB1) {
csi->buf_num = 0;
} else if (status & BIT_DMA_TSF_DONE_FB2) {
csi->buf_num = 1;
}
if ((status & BIT_DMA_TSF_DONE_FB1) ||
(status & BIT_DMA_TSF_DONE_FB2)) {
imx7_csi_vb2_buf_done(csi);
if (csi->last_eof) {
complete(&csi->last_eof_completion);
csi->last_eof = false;
}
}
spin_unlock(&csi->irqlock);
return IRQ_HANDLED;
}
/* -----------------------------------------------------------------------------
* Format Helpers
*/
#define IMX_BUS_FMTS(fmt...) (const u32[]) {fmt, 0}
/*
* List of supported pixel formats for the subdevs. Keep V4L2_PIX_FMT_UYVY and
* MEDIA_BUS_FMT_UYVY8_2X8 first to match IMX7_CSI_DEF_PIX_FORMAT and
* IMX7_CSI_DEF_MBUS_CODE.
*
* TODO: Restrict the supported formats list based on the SoC integration.
*
* The CSI bridge can be configured to sample pixel components from the Rx queue
* in single (8bpp) or double (16bpp) component modes. Image format variants
* with different sample sizes (ie YUYV_2X8 vs YUYV_1X16) determine the pixel
* components sampling size per each clock cycle and their packing mode (see
* imx7_csi_configure() for details).
*
* As the CSI bridge can be interfaced with different IP blocks depending on the
* SoC model it is integrated on, the Rx queue sampling size should match the
* size of the samples transferred by the transmitting IP block. To avoid
* misconfigurations of the capture pipeline, the enumeration of the supported
* formats should be restricted to match the pixel source transmitting mode.
*
* Example: i.MX8MM SoC integrates the CSI bridge with the Samsung CSIS CSI-2
* receiver which operates in dual pixel sampling mode. The CSI bridge should
* only expose the 1X16 formats variant which instructs it to operate in dual
* pixel sampling mode. When the CSI bridge is instead integrated on an i.MX7,
* which supports both serial and parallel input, it should expose both
* variants.
*
* This currently only applies to YUYV formats, but other formats might need to
* be handled in the same way.
*/
static const struct imx7_csi_pixfmt pixel_formats[] = {
/*** YUV formats start here ***/
{
.fourcc = V4L2_PIX_FMT_UYVY,
.codes = IMX_BUS_FMTS(
MEDIA_BUS_FMT_UYVY8_2X8,
MEDIA_BUS_FMT_UYVY8_1X16
),
.yuv = true,
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.codes = IMX_BUS_FMTS(
MEDIA_BUS_FMT_YUYV8_2X8,
MEDIA_BUS_FMT_YUYV8_1X16
),
.yuv = true,
.bpp = 16,
},
/*** raw bayer and grayscale formats start here ***/
{
.fourcc = V4L2_PIX_FMT_SBGGR8,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
.bpp = 8,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG8,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
.bpp = 8,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG8,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
.bpp = 8,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB8,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
.bpp = 8,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG10,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG10,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB10,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR12,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG12,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG12,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB12,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR14,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR14_1X14),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG14,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG14_1X14),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG14,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG14_1X14),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB14,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB14_1X14),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_GREY,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y8_1X8),
.bpp = 8,
}, {
.fourcc = V4L2_PIX_FMT_Y10,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y10_1X10),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_Y12,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y12_1X12),
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_Y14,
.codes = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y14_1X14),
.bpp = 16,
},
};
/*
* Search in the pixel_formats[] array for an entry with the given fourcc
* return it.
*/
static const struct imx7_csi_pixfmt *imx7_csi_find_pixel_format(u32 fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
if (fmt->fourcc == fourcc)
return fmt;
}
return NULL;
}
/*
* Search in the pixel_formats[] array for an entry with the given media
* bus code and return it.
*/
static const struct imx7_csi_pixfmt *imx7_csi_find_mbus_format(u32 code)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
unsigned int j;
if (!fmt->codes)
continue;
for (j = 0; fmt->codes[j]; j++) {
if (code == fmt->codes[j])
return fmt;
}
}
return NULL;
}
/*
* Enumerate entries in the pixel_formats[] array that match the
* requested search criteria. Return the media-bus code that matches
* the search criteria at the requested match index.
*
* @code: The returned media-bus code that matches the search criteria at
* the requested match index.
* @index: The requested match index.
*/
static int imx7_csi_enum_mbus_formats(u32 *code, u32 index)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
unsigned int j;
if (!fmt->codes)
continue;
for (j = 0; fmt->codes[j]; j++) {
if (index == 0) {
*code = fmt->codes[j];
return 0;
}
index--;
}
}
return -EINVAL;
}
/* -----------------------------------------------------------------------------
* Video Capture Device - IOCTLs
*/
static int imx7_csi_video_querycap(struct file *file, void *fh,
struct v4l2_capability *cap)
{
struct imx7_csi *csi = video_drvdata(file);
strscpy(cap->driver, IMX7_CSI_VIDEO_NAME, sizeof(cap->driver));
strscpy(cap->card, IMX7_CSI_VIDEO_NAME, sizeof(cap->card));
snprintf(cap->bus_info, sizeof(cap->bus_info),
"platform:%s", dev_name(csi->dev));
return 0;
}
static int imx7_csi_video_enum_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_fmtdesc *f)
{
unsigned int index = f->index;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
/*
* If a media bus code is specified, only consider formats that
* match it.
*/
if (f->mbus_code) {
unsigned int j;
if (!fmt->codes)
continue;
for (j = 0; fmt->codes[j]; j++) {
if (f->mbus_code == fmt->codes[j])
break;
}
if (!fmt->codes[j])
continue;
}
if (index == 0) {
f->pixelformat = fmt->fourcc;
return 0;
}
index--;
}
return -EINVAL;
}
static int imx7_csi_video_enum_framesizes(struct file *file, void *fh,
struct v4l2_frmsizeenum *fsize)
{
const struct imx7_csi_pixfmt *cc;
u32 walign;
if (fsize->index > 0)
return -EINVAL;
cc = imx7_csi_find_pixel_format(fsize->pixel_format);
if (!cc)
return -EINVAL;
/*
* The width alignment is 8 bytes as indicated by the
* CSI_IMAG_PARA.IMAGE_WIDTH documentation. Convert it to pixels.
*/
walign = 8 * 8 / cc->bpp;
fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
fsize->stepwise.min_width = walign;
fsize->stepwise.max_width = round_down(65535U, walign);
fsize->stepwise.min_height = 1;
fsize->stepwise.max_height = 65535;
fsize->stepwise.step_width = walign;
fsize->stepwise.step_height = 1;
return 0;
}
static int imx7_csi_video_g_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *f)
{
struct imx7_csi *csi = video_drvdata(file);
f->fmt.pix = csi->vdev_fmt;
return 0;
}
static const struct imx7_csi_pixfmt *
__imx7_csi_video_try_fmt(struct v4l2_pix_format *pixfmt,
struct v4l2_rect *compose)
{
const struct imx7_csi_pixfmt *cc;
u32 walign;
if (compose) {
compose->width = pixfmt->width;
compose->height = pixfmt->height;
}
/*
* Find the pixel format, default to the first supported format if not
* found.
*/
cc = imx7_csi_find_pixel_format(pixfmt->pixelformat);
if (!cc) {
pixfmt->pixelformat = IMX7_CSI_DEF_PIX_FORMAT;
cc = imx7_csi_find_pixel_format(pixfmt->pixelformat);
}
/*
* The width alignment is 8 bytes as indicated by the
* CSI_IMAG_PARA.IMAGE_WIDTH documentation. Convert it to pixels.
*
* TODO: Implement configurable stride support.
*/
walign = 8 * 8 / cc->bpp;
pixfmt->width = clamp(round_up(pixfmt->width, walign), walign,
round_down(65535U, walign));
pixfmt->height = clamp(pixfmt->height, 1U, 65535U);
pixfmt->bytesperline = pixfmt->width * cc->bpp / 8;
pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
pixfmt->field = V4L2_FIELD_NONE;
return cc;
}
static int imx7_csi_video_try_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *f)
{
__imx7_csi_video_try_fmt(&f->fmt.pix, NULL);
return 0;
}
static int imx7_csi_video_s_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *f)
{
struct imx7_csi *csi = video_drvdata(file);
const struct imx7_csi_pixfmt *cc;
if (vb2_is_busy(&csi->q)) {
dev_err(csi->dev, "%s queue busy\n", __func__);
return -EBUSY;
}
cc = __imx7_csi_video_try_fmt(&f->fmt.pix, &csi->vdev_compose);
csi->vdev_cc = cc;
csi->vdev_fmt = f->fmt.pix;
return 0;
}
static int imx7_csi_video_g_selection(struct file *file, void *fh,
struct v4l2_selection *s)
{
struct imx7_csi *csi = video_drvdata(file);
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
switch (s->target) {
case V4L2_SEL_TGT_COMPOSE:
case V4L2_SEL_TGT_COMPOSE_DEFAULT:
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
/* The compose rectangle is fixed to the source format. */
s->r = csi->vdev_compose;
break;
case V4L2_SEL_TGT_COMPOSE_PADDED:
/*
* The hardware writes with a configurable but fixed DMA burst
* size. If the source format width is not burst size aligned,
* the written frame contains padding to the right.
*/
s->r.left = 0;
s->r.top = 0;
s->r.width = csi->vdev_fmt.width;
s->r.height = csi->vdev_fmt.height;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct v4l2_ioctl_ops imx7_csi_video_ioctl_ops = {
.vidioc_querycap = imx7_csi_video_querycap,
.vidioc_enum_fmt_vid_cap = imx7_csi_video_enum_fmt_vid_cap,
.vidioc_enum_framesizes = imx7_csi_video_enum_framesizes,
.vidioc_g_fmt_vid_cap = imx7_csi_video_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = imx7_csi_video_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = imx7_csi_video_s_fmt_vid_cap,
.vidioc_g_selection = imx7_csi_video_g_selection,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
};
/* -----------------------------------------------------------------------------
* Video Capture Device - Queue Operations
*/
static int imx7_csi_video_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers,
unsigned int *nplanes,
unsigned int sizes[],
struct device *alloc_devs[])
{
struct imx7_csi *csi = vb2_get_drv_priv(vq);
struct v4l2_pix_format *pix = &csi->vdev_fmt;
unsigned int count = *nbuffers;
if (vq->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (*nplanes) {
if (*nplanes != 1 || sizes[0] < pix->sizeimage)
return -EINVAL;
count += vq->num_buffers;
}
count = min_t(__u32, IMX7_CSI_VIDEO_MEM_LIMIT / pix->sizeimage, count);
if (*nplanes)
*nbuffers = (count < vq->num_buffers) ? 0 :
count - vq->num_buffers;
else
*nbuffers = count;
*nplanes = 1;
sizes[0] = pix->sizeimage;
return 0;
}
static int imx7_csi_video_buf_init(struct vb2_buffer *vb)
{
struct imx7_csi_vb2_buffer *buf = to_imx7_csi_vb2_buffer(vb);
INIT_LIST_HEAD(&buf->list);
return 0;
}
static int imx7_csi_video_buf_prepare(struct vb2_buffer *vb)
{
struct imx7_csi *csi = vb2_get_drv_priv(vb->vb2_queue);
struct v4l2_pix_format *pix = &csi->vdev_fmt;
if (vb2_plane_size(vb, 0) < pix->sizeimage) {
dev_err(csi->dev,
"data will not fit into plane (%lu < %lu)\n",
vb2_plane_size(vb, 0), (long)pix->sizeimage);
return -EINVAL;
}
vb2_set_plane_payload(vb, 0, pix->sizeimage);
return 0;
}
static bool imx7_csi_fast_track_buffer(struct imx7_csi *csi,
struct imx7_csi_vb2_buffer *buf)
{
unsigned long flags;
dma_addr_t dma_addr;
int buf_num;
u32 isr;
if (!csi->is_streaming)
return false;
dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vbuf.vb2_buf, 0);
/*
* buf_num holds the framebuffer ID of the most recently (*not* the
* next anticipated) triggered interrupt. Without loss of generality,
* if buf_num is 0, the hardware is capturing to FB2. If FB1 has been
* programmed with a dummy buffer (as indicated by active_vb2_buf[0]
* being NULL), then we can fast-track the new buffer by programming
* its address in FB1 before the hardware completes FB2, instead of
* adding it to the buffer queue and incurring a delay of one
* additional frame.
*
* The irqlock prevents races with the interrupt handler that updates
* buf_num when it programs the next buffer, but we can still race with
* the hardware if we program the buffer in FB1 just after the hardware
* completes FB2 and switches to FB1 and before buf_num can be updated
* by the interrupt handler for FB2. The fast-tracked buffer would
* then be ignored by the hardware while the driver would think it has
* successfully been processed.
*
* To avoid this problem, if we can't avoid the race, we can detect
* that we have lost it by checking, after programming the buffer in
* FB1, if the interrupt flag indicating completion of FB2 has been
* raised. If that is not the case, fast-tracking succeeded, and we can
* update active_vb2_buf[0]. Otherwise, we may or may not have lost the
* race (as the interrupt flag may have been raised just after
* programming FB1 and before we read the interrupt status register),
* and we need to assume the worst case of a race loss and queue the
* buffer through the slow path.
*/
spin_lock_irqsave(&csi->irqlock, flags);
buf_num = csi->buf_num;
if (csi->active_vb2_buf[buf_num]) {
spin_unlock_irqrestore(&csi->irqlock, flags);
return false;
}
imx7_csi_update_buf(csi, dma_addr, buf_num);
isr = imx7_csi_reg_read(csi, CSI_CSISR);
if (isr & (buf_num ? BIT_DMA_TSF_DONE_FB1 : BIT_DMA_TSF_DONE_FB2)) {
/*
* The interrupt for the /other/ FB just came (the isr hasn't
* run yet though, because we have the lock here); we can't be
* sure we've programmed buf_num FB in time, so queue the buffer
* to the buffer queue normally. No need to undo writing the FB
* register, since we won't return it as active_vb2_buf is NULL,
* so it's okay to potentially write it to both FB1 and FB2;
* only the one where it was queued normally will be returned.
*/
spin_unlock_irqrestore(&csi->irqlock, flags);
return false;
}
csi->active_vb2_buf[buf_num] = buf;
spin_unlock_irqrestore(&csi->irqlock, flags);
return true;
}
static void imx7_csi_video_buf_queue(struct vb2_buffer *vb)
{
struct imx7_csi *csi = vb2_get_drv_priv(vb->vb2_queue);
struct imx7_csi_vb2_buffer *buf = to_imx7_csi_vb2_buffer(vb);
unsigned long flags;
if (imx7_csi_fast_track_buffer(csi, buf))
return;
spin_lock_irqsave(&csi->q_lock, flags);
list_add_tail(&buf->list, &csi->ready_q);
spin_unlock_irqrestore(&csi->q_lock, flags);
}
static int imx7_csi_video_validate_fmt(struct imx7_csi *csi)
{
struct v4l2_subdev_format fmt_src = {
.pad = IMX7_CSI_PAD_SRC,
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
const struct imx7_csi_pixfmt *cc;
int ret;
/* Retrieve the media bus format on the source subdev. */
ret = v4l2_subdev_call_state_active(&csi->sd, pad, get_fmt, &fmt_src);
if (ret)
return ret;
/*
* Verify that the media bus size matches the size set on the video
* node. It is sufficient to check the compose rectangle size without
* checking the rounded size from pix_fmt, as the rounded size is
* derived directly from the compose rectangle size, and will thus
* always match if the compose rectangle matches.
*/
if (csi->vdev_compose.width != fmt_src.format.width ||
csi->vdev_compose.height != fmt_src.format.height)
return -EPIPE;
/*
* Verify that the media bus code is compatible with the pixel format
* set on the video node.
*/
cc = imx7_csi_find_mbus_format(fmt_src.format.code);
if (!cc || csi->vdev_cc->yuv != cc->yuv)
return -EPIPE;
return 0;
}
static int imx7_csi_video_start_streaming(struct vb2_queue *vq,
unsigned int count)
{
struct imx7_csi *csi = vb2_get_drv_priv(vq);
struct imx7_csi_vb2_buffer *buf, *tmp;
unsigned long flags;
int ret;
ret = imx7_csi_video_validate_fmt(csi);
if (ret) {
dev_err(csi->dev, "capture format not valid\n");
goto err_buffers;
}
mutex_lock(&csi->mdev.graph_mutex);
ret = __video_device_pipeline_start(csi->vdev, &csi->pipe);
if (ret)
goto err_unlock;
ret = v4l2_subdev_call(&csi->sd, video, s_stream, 1);
if (ret)
goto err_stop;
mutex_unlock(&csi->mdev.graph_mutex);
return 0;
err_stop:
__video_device_pipeline_stop(csi->vdev);
err_unlock:
mutex_unlock(&csi->mdev.graph_mutex);
dev_err(csi->dev, "pipeline start failed with %d\n", ret);
err_buffers:
spin_lock_irqsave(&csi->q_lock, flags);
list_for_each_entry_safe(buf, tmp, &csi->ready_q, list) {
list_del(&buf->list);
vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_QUEUED);
}
spin_unlock_irqrestore(&csi->q_lock, flags);
return ret;
}
static void imx7_csi_video_stop_streaming(struct vb2_queue *vq)
{
struct imx7_csi *csi = vb2_get_drv_priv(vq);
struct imx7_csi_vb2_buffer *frame;
struct imx7_csi_vb2_buffer *tmp;
unsigned long flags;
mutex_lock(&csi->mdev.graph_mutex);
v4l2_subdev_call(&csi->sd, video, s_stream, 0);
__video_device_pipeline_stop(csi->vdev);
mutex_unlock(&csi->mdev.graph_mutex);
/* release all active buffers */
spin_lock_irqsave(&csi->q_lock, flags);
list_for_each_entry_safe(frame, tmp, &csi->ready_q, list) {
list_del(&frame->list);
vb2_buffer_done(&frame->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&csi->q_lock, flags);
}
static const struct vb2_ops imx7_csi_video_qops = {
.queue_setup = imx7_csi_video_queue_setup,
.buf_init = imx7_csi_video_buf_init,
.buf_prepare = imx7_csi_video_buf_prepare,
.buf_queue = imx7_csi_video_buf_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = imx7_csi_video_start_streaming,
.stop_streaming = imx7_csi_video_stop_streaming,
};
/* -----------------------------------------------------------------------------
* Video Capture Device - File Operations
*/
static int imx7_csi_video_open(struct file *file)
{
struct imx7_csi *csi = video_drvdata(file);
int ret;
if (mutex_lock_interruptible(&csi->vdev_mutex))
return -ERESTARTSYS;
ret = v4l2_fh_open(file);
if (ret) {
dev_err(csi->dev, "v4l2_fh_open failed\n");
goto out;
}
ret = v4l2_pipeline_pm_get(&csi->vdev->entity);
if (ret)
v4l2_fh_release(file);
out:
mutex_unlock(&csi->vdev_mutex);
return ret;
}
static int imx7_csi_video_release(struct file *file)
{
struct imx7_csi *csi = video_drvdata(file);
struct vb2_queue *vq = &csi->q;
mutex_lock(&csi->vdev_mutex);
if (file->private_data == vq->owner) {
vb2_queue_release(vq);
vq->owner = NULL;
}
v4l2_pipeline_pm_put(&csi->vdev->entity);
v4l2_fh_release(file);
mutex_unlock(&csi->vdev_mutex);
return 0;
}
static const struct v4l2_file_operations imx7_csi_video_fops = {
.owner = THIS_MODULE,
.open = imx7_csi_video_open,
.release = imx7_csi_video_release,
.poll = vb2_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = vb2_fop_mmap,
};
/* -----------------------------------------------------------------------------
* Video Capture Device - Init & Cleanup
*/
static struct imx7_csi_vb2_buffer *imx7_csi_video_next_buf(struct imx7_csi *csi)
{
struct imx7_csi_vb2_buffer *buf = NULL;
unsigned long flags;
spin_lock_irqsave(&csi->q_lock, flags);
/* get next queued buffer */
if (!list_empty(&csi->ready_q)) {
buf = list_entry(csi->ready_q.next, struct imx7_csi_vb2_buffer,
list);
list_del(&buf->list);
}
spin_unlock_irqrestore(&csi->q_lock, flags);
return buf;
}
static void imx7_csi_video_init_format(struct imx7_csi *csi)
{
struct v4l2_pix_format *pixfmt = &csi->vdev_fmt;
pixfmt->width = IMX7_CSI_DEF_PIX_WIDTH;
pixfmt->height = IMX7_CSI_DEF_PIX_HEIGHT;
csi->vdev_cc = __imx7_csi_video_try_fmt(pixfmt, &csi->vdev_compose);
}
static int imx7_csi_video_register(struct imx7_csi *csi)
{
struct v4l2_subdev *sd = &csi->sd;
struct v4l2_device *v4l2_dev = sd->v4l2_dev;
struct video_device *vdev = csi->vdev;
int ret;
vdev->v4l2_dev = v4l2_dev;
/* Initialize the default format and compose rectangle. */
imx7_csi_video_init_format(csi);
/* Register the video device. */
ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
if (ret) {
dev_err(csi->dev, "Failed to register video device\n");
return ret;
}
dev_info(csi->dev, "Registered %s as /dev/%s\n", vdev->name,
video_device_node_name(vdev));
/* Create the link from the CSI subdev to the video device. */
ret = media_create_pad_link(&sd->entity, IMX7_CSI_PAD_SRC,
&vdev->entity, 0, MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret) {
dev_err(csi->dev, "failed to create link to device node\n");
video_unregister_device(vdev);
return ret;
}
return 0;
}
static void imx7_csi_video_unregister(struct imx7_csi *csi)
{
media_entity_cleanup(&csi->vdev->entity);
video_unregister_device(csi->vdev);
}
static int imx7_csi_video_init(struct imx7_csi *csi)
{
struct video_device *vdev;
struct vb2_queue *vq;
int ret;
mutex_init(&csi->vdev_mutex);
INIT_LIST_HEAD(&csi->ready_q);
spin_lock_init(&csi->q_lock);
/* Allocate and initialize the video device. */
vdev = video_device_alloc();
if (!vdev)
return -ENOMEM;
vdev->fops = &imx7_csi_video_fops;
vdev->ioctl_ops = &imx7_csi_video_ioctl_ops;
vdev->minor = -1;
vdev->release = video_device_release;
vdev->vfl_dir = VFL_DIR_RX;
vdev->tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING
| V4L2_CAP_IO_MC;
vdev->lock = &csi->vdev_mutex;
vdev->queue = &csi->q;
snprintf(vdev->name, sizeof(vdev->name), "%s capture", csi->sd.name);
video_set_drvdata(vdev, csi);
csi->vdev = vdev;
/* Initialize the video device pad. */
csi->vdev_pad.flags = MEDIA_PAD_FL_SINK;
ret = media_entity_pads_init(&vdev->entity, 1, &csi->vdev_pad);
if (ret) {
video_device_release(vdev);
return ret;
}
/* Initialize the vb2 queue. */
vq = &csi->q;
vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
vq->io_modes = VB2_MMAP | VB2_DMABUF;
vq->drv_priv = csi;
vq->buf_struct_size = sizeof(struct imx7_csi_vb2_buffer);
vq->ops = &imx7_csi_video_qops;
vq->mem_ops = &vb2_dma_contig_memops;
vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
vq->lock = &csi->vdev_mutex;
vq->min_buffers_needed = 2;
vq->dev = csi->dev;
ret = vb2_queue_init(vq);
if (ret) {
dev_err(csi->dev, "vb2_queue_init failed\n");
video_device_release(vdev);
return ret;
}
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 Subdev Operations
*/
static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable)
{
struct imx7_csi *csi = v4l2_get_subdevdata(sd);
struct v4l2_subdev_state *sd_state;
int ret = 0;
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
if (enable) {
ret = imx7_csi_init(csi, sd_state);
if (ret < 0)
goto out_unlock;
ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1);
if (ret < 0) {
imx7_csi_deinit(csi, VB2_BUF_STATE_QUEUED);
goto out_unlock;
}
imx7_csi_enable(csi);
} else {
imx7_csi_disable(csi);
v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
imx7_csi_deinit(csi, VB2_BUF_STATE_ERROR);
}
csi->is_streaming = !!enable;
out_unlock:
v4l2_subdev_unlock_state(sd_state);
return ret;
}
static int imx7_csi_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
const struct imx7_csi_pixfmt *cc;
int i;
cc = imx7_csi_find_mbus_format(IMX7_CSI_DEF_MBUS_CODE);
for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
struct v4l2_mbus_framefmt *mf =
v4l2_subdev_get_pad_format(sd, sd_state, i);
mf->code = IMX7_CSI_DEF_MBUS_CODE;
mf->width = IMX7_CSI_DEF_PIX_WIDTH;
mf->height = IMX7_CSI_DEF_PIX_HEIGHT;
mf->field = V4L2_FIELD_NONE;
mf->colorspace = V4L2_COLORSPACE_SRGB;
mf->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(mf->colorspace);
mf->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(mf->colorspace);
mf->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!cc->yuv,
mf->colorspace, mf->ycbcr_enc);
}
return 0;
}
static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct v4l2_mbus_framefmt *in_fmt;
int ret = 0;
in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);
switch (code->pad) {
case IMX7_CSI_PAD_SINK:
ret = imx7_csi_enum_mbus_formats(&code->code, code->index);
break;
case IMX7_CSI_PAD_SRC:
if (code->index != 0) {
ret = -EINVAL;
break;
}
code->code = in_fmt->code;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
/*
* Default the colorspace in tryfmt to SRGB if set to an unsupported
* colorspace or not initialized. Then set the remaining colorimetry
* parameters based on the colorspace if they are uninitialized.
*
* tryfmt->code must be set on entry.
*/
static void imx7_csi_try_colorimetry(struct v4l2_mbus_framefmt *tryfmt)
{
const struct imx7_csi_pixfmt *cc;
bool is_rgb = false;
cc = imx7_csi_find_mbus_format(tryfmt->code);
if (cc && !cc->yuv)
is_rgb = true;
switch (tryfmt->colorspace) {
case V4L2_COLORSPACE_SMPTE170M:
case V4L2_COLORSPACE_REC709:
case V4L2_COLORSPACE_JPEG:
case V4L2_COLORSPACE_SRGB:
case V4L2_COLORSPACE_BT2020:
case V4L2_COLORSPACE_OPRGB:
case V4L2_COLORSPACE_DCI_P3:
case V4L2_COLORSPACE_RAW:
break;
default:
tryfmt->colorspace = V4L2_COLORSPACE_SRGB;
break;
}
if (tryfmt->xfer_func == V4L2_XFER_FUNC_DEFAULT)
tryfmt->xfer_func =
V4L2_MAP_XFER_FUNC_DEFAULT(tryfmt->colorspace);
if (tryfmt->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
tryfmt->ycbcr_enc =
V4L2_MAP_YCBCR_ENC_DEFAULT(tryfmt->colorspace);
if (tryfmt->quantization == V4L2_QUANTIZATION_DEFAULT)
tryfmt->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb,
tryfmt->colorspace,
tryfmt->ycbcr_enc);
}
static void imx7_csi_try_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *sdformat,
const struct imx7_csi_pixfmt **cc)
{
const struct imx7_csi_pixfmt *in_cc;
struct v4l2_mbus_framefmt *in_fmt;
u32 code;
in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);
switch (sdformat->pad) {
case IMX7_CSI_PAD_SRC:
in_cc = imx7_csi_find_mbus_format(in_fmt->code);
sdformat->format.width = in_fmt->width;
sdformat->format.height = in_fmt->height;
sdformat->format.code = in_fmt->code;
sdformat->format.field = in_fmt->field;
*cc = in_cc;
sdformat->format.colorspace = in_fmt->colorspace;
sdformat->format.xfer_func = in_fmt->xfer_func;
sdformat->format.quantization = in_fmt->quantization;
sdformat->format.ycbcr_enc = in_fmt->ycbcr_enc;
break;
case IMX7_CSI_PAD_SINK:
*cc = imx7_csi_find_mbus_format(sdformat->format.code);
if (!*cc) {
code = IMX7_CSI_DEF_MBUS_CODE;
*cc = imx7_csi_find_mbus_format(code);
sdformat->format.code = code;
}
if (sdformat->format.field != V4L2_FIELD_INTERLACED)
sdformat->format.field = V4L2_FIELD_NONE;
break;
}
imx7_csi_try_colorimetry(&sdformat->format);
}
static int imx7_csi_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *sdformat)
{
struct imx7_csi *csi = v4l2_get_subdevdata(sd);
const struct imx7_csi_pixfmt *outcc;
struct v4l2_mbus_framefmt *outfmt;
const struct imx7_csi_pixfmt *cc;
struct v4l2_mbus_framefmt *fmt;
struct v4l2_subdev_format format;
if (csi->is_streaming)
return -EBUSY;
imx7_csi_try_fmt(sd, sd_state, sdformat, &cc);
fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
*fmt = sdformat->format;
if (sdformat->pad == IMX7_CSI_PAD_SINK) {
/* propagate format to source pads */
format.pad = IMX7_CSI_PAD_SRC;
format.which = sdformat->which;
format.format = sdformat->format;
imx7_csi_try_fmt(sd, sd_state, &format, &outcc);
outfmt = v4l2_subdev_get_pad_format(sd, sd_state,
IMX7_CSI_PAD_SRC);
*outfmt = format.format;
}
return 0;
}
static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd,
struct media_link *link,
struct v4l2_subdev_format *source_fmt,
struct v4l2_subdev_format *sink_fmt)
{
struct imx7_csi *csi = v4l2_get_subdevdata(sd);
struct media_pad *pad = NULL;
unsigned int i;
int ret;
/*
* Validate the source link, and record whether the source uses the
* parallel input or the CSI-2 receiver.
*/
ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
if (ret)
return ret;
switch (csi->src_sd->entity.function) {
case MEDIA_ENT_F_VID_IF_BRIDGE:
/* The input is the CSI-2 receiver. */
csi->is_csi2 = true;
break;
case MEDIA_ENT_F_VID_MUX:
/* The input is the mux, check its input. */
for (i = 0; i < csi->src_sd->entity.num_pads; i++) {
struct media_pad *spad = &csi->src_sd->entity.pads[i];
if (!(spad->flags & MEDIA_PAD_FL_SINK))
continue;
pad = media_pad_remote_pad_first(spad);
if (pad)
break;
}
if (!pad)
return -ENODEV;
csi->is_csi2 = pad->entity->function == MEDIA_ENT_F_VID_IF_BRIDGE;
break;
default:
/*
* The input is an external entity, it must use the parallel
* bus.
*/
csi->is_csi2 = false;
break;
}
return 0;
}
static int imx7_csi_registered(struct v4l2_subdev *sd)
{
struct imx7_csi *csi = v4l2_get_subdevdata(sd);
int ret;
ret = imx7_csi_video_init(csi);
if (ret)
return ret;
ret = imx7_csi_video_register(csi);
if (ret)
return ret;
ret = v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
if (ret)
goto err_unreg;
ret = media_device_register(&csi->mdev);
if (ret)
goto err_unreg;
return 0;
err_unreg:
imx7_csi_video_unregister(csi);
return ret;
}
static void imx7_csi_unregistered(struct v4l2_subdev *sd)
{
struct imx7_csi *csi = v4l2_get_subdevdata(sd);
imx7_csi_video_unregister(csi);
}
static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {
.s_stream = imx7_csi_s_stream,
};
static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {
.init_cfg = imx7_csi_init_cfg,
.enum_mbus_code = imx7_csi_enum_mbus_code,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = imx7_csi_set_fmt,
.link_validate = imx7_csi_pad_link_validate,
};
static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {
.video = &imx7_csi_video_ops,
.pad = &imx7_csi_pad_ops,
};
static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {
.registered = imx7_csi_registered,
.unregistered = imx7_csi_unregistered,
};
/* -----------------------------------------------------------------------------
* Media Entity Operations
*/
static const struct media_entity_operations imx7_csi_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
};
/* -----------------------------------------------------------------------------
* Probe & Remove
*/
static int imx7_csi_notify_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *sd,
struct v4l2_async_connection *asd)
{
struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
struct media_pad *sink = &csi->sd.entity.pads[IMX7_CSI_PAD_SINK];
csi->src_sd = sd;
return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
}
static int imx7_csi_notify_complete(struct v4l2_async_notifier *notifier)
{
struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
return v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
}
static const struct v4l2_async_notifier_operations imx7_csi_notify_ops = {
.bound = imx7_csi_notify_bound,
.complete = imx7_csi_notify_complete,
};
static int imx7_csi_async_register(struct imx7_csi *csi)
{
struct v4l2_async_connection *asd;
struct fwnode_handle *ep;
int ret;
v4l2_async_nf_init(&csi->notifier, &csi->v4l2_dev);
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep) {
ret = dev_err_probe(csi->dev, -ENOTCONN,
"Failed to get remote endpoint\n");
goto error;
}
asd = v4l2_async_nf_add_fwnode_remote(&csi->notifier, ep,
struct v4l2_async_connection);
fwnode_handle_put(ep);
if (IS_ERR(asd)) {
ret = dev_err_probe(csi->dev, PTR_ERR(asd),
"Failed to add remote subdev to notifier\n");
goto error;
}
csi->notifier.ops = &imx7_csi_notify_ops;
ret = v4l2_async_nf_register(&csi->notifier);
if (ret)
goto error;
return 0;
error:
v4l2_async_nf_cleanup(&csi->notifier);
return ret;
}
static void imx7_csi_media_cleanup(struct imx7_csi *csi)
{
v4l2_device_unregister(&csi->v4l2_dev);
media_device_unregister(&csi->mdev);
v4l2_subdev_cleanup(&csi->sd);
media_device_cleanup(&csi->mdev);
}
static const struct media_device_ops imx7_csi_media_ops = {
.link_notify = v4l2_pipeline_link_notify,
};
static int imx7_csi_media_dev_init(struct imx7_csi *csi)
{
int ret;
strscpy(csi->mdev.model, "imx-media", sizeof(csi->mdev.model));
csi->mdev.ops = &imx7_csi_media_ops;
csi->mdev.dev = csi->dev;
csi->v4l2_dev.mdev = &csi->mdev;
strscpy(csi->v4l2_dev.name, "imx-media",
sizeof(csi->v4l2_dev.name));
snprintf(csi->mdev.bus_info, sizeof(csi->mdev.bus_info),
"platform:%s", dev_name(csi->mdev.dev));
media_device_init(&csi->mdev);
ret = v4l2_device_register(csi->dev, &csi->v4l2_dev);
if (ret < 0) {
v4l2_err(&csi->v4l2_dev,
"Failed to register v4l2_device: %d\n", ret);
goto cleanup;
}
return 0;
cleanup:
media_device_cleanup(&csi->mdev);
return ret;
}
static int imx7_csi_media_init(struct imx7_csi *csi)
{
unsigned int i;
int ret;
/* add media device */
ret = imx7_csi_media_dev_init(csi);
if (ret)
return ret;
v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops);
v4l2_set_subdevdata(&csi->sd, csi);
csi->sd.internal_ops = &imx7_csi_internal_ops;
csi->sd.entity.ops = &imx7_csi_entity_ops;
csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
csi->sd.dev = csi->dev;
csi->sd.owner = THIS_MODULE;
csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
snprintf(csi->sd.name, sizeof(csi->sd.name), "csi");
for (i = 0; i < IMX7_CSI_PADS_NUM; i++)
csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ?
MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&csi->sd.entity, IMX7_CSI_PADS_NUM,
csi->pad);
if (ret)
goto error;
ret = v4l2_subdev_init_finalize(&csi->sd);
if (ret)
goto error;
ret = v4l2_device_register_subdev(&csi->v4l2_dev, &csi->sd);
if (ret)
goto error;
return 0;
error:
imx7_csi_media_cleanup(csi);
return ret;
}
static int imx7_csi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct imx7_csi *csi;
int ret;
csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
if (!csi)
return -ENOMEM;
csi->dev = dev;
platform_set_drvdata(pdev, csi);
spin_lock_init(&csi->irqlock);
/* Acquire resources and install interrupt handler. */
csi->mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(csi->mclk)) {
ret = PTR_ERR(csi->mclk);
dev_err(dev, "Failed to get mclk: %d", ret);
return ret;
}
csi->irq = platform_get_irq(pdev, 0);
if (csi->irq < 0)
return csi->irq;
csi->regbase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(csi->regbase))
return PTR_ERR(csi->regbase);
csi->model = (enum imx_csi_model)(uintptr_t)of_device_get_match_data(&pdev->dev);
ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi",
(void *)csi);
if (ret < 0) {
dev_err(dev, "Request CSI IRQ failed.\n");
return ret;
}
/* Initialize all the media device infrastructure. */
ret = imx7_csi_media_init(csi);
if (ret)
return ret;
ret = imx7_csi_async_register(csi);
if (ret)
goto err_media_cleanup;
return 0;
err_media_cleanup:
imx7_csi_media_cleanup(csi);
return ret;
}
static void imx7_csi_remove(struct platform_device *pdev)
{
struct imx7_csi *csi = platform_get_drvdata(pdev);
imx7_csi_media_cleanup(csi);
v4l2_async_nf_unregister(&csi->notifier);
v4l2_async_nf_cleanup(&csi->notifier);
v4l2_async_unregister_subdev(&csi->sd);
}
static const struct of_device_id imx7_csi_of_match[] = {
{ .compatible = "fsl,imx8mq-csi", .data = (void *)IMX7_CSI_IMX8MQ },
{ .compatible = "fsl,imx7-csi", .data = (void *)IMX7_CSI_IMX7 },
{ .compatible = "fsl,imx6ul-csi", .data = (void *)IMX7_CSI_IMX7 },
{ },
};
MODULE_DEVICE_TABLE(of, imx7_csi_of_match);
static struct platform_driver imx7_csi_driver = {
.probe = imx7_csi_probe,
.remove_new = imx7_csi_remove,
.driver = {
.of_match_table = imx7_csi_of_match,
.name = "imx7-csi",
},
};
module_platform_driver(imx7_csi_driver);
MODULE_DESCRIPTION("i.MX7 CSI subdev driver");
MODULE_AUTHOR("Rui Miguel Silva <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx7-csi");
| linux-master | drivers/media/platform/nxp/imx7-media-csi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung CSIS MIPI CSI-2 receiver driver.
*
* The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
* i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
* version 3.6.3.
*
* Copyright (C) 2019 Linaro Ltd
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
*
*/
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mc.h>
#include <media/v4l2-subdev.h>
#define CSIS_DRIVER_NAME "imx-mipi-csis"
#define CSIS_PAD_SINK 0
#define CSIS_PAD_SOURCE 1
#define CSIS_PADS_NUM 2
#define MIPI_CSIS_DEF_PIX_WIDTH 640
#define MIPI_CSIS_DEF_PIX_HEIGHT 480
/* Register map definition */
/* CSIS version */
#define MIPI_CSIS_VERSION 0x00
#define MIPI_CSIS_VERSION_IMX7D 0x03030505
#define MIPI_CSIS_VERSION_IMX8MP 0x03060301
/* CSIS common control */
#define MIPI_CSIS_CMN_CTRL 0x04
#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
#define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
#define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
#define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
/* CSIS clock control */
#define MIPI_CSIS_CLK_CTRL 0x08
#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
/* CSIS Interrupt mask */
#define MIPI_CSIS_INT_MSK 0x10
#define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31)
#define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30)
#define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29)
#define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28)
#define MIPI_CSIS_INT_MSK_FRAME_START BIT(24)
#define MIPI_CSIS_INT_MSK_FRAME_END BIT(20)
#define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16)
#define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12)
#define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8)
#define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4)
#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
#define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
#define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
/* CSIS Interrupt source */
#define MIPI_CSIS_INT_SRC 0x14
#define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31)
#define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30)
#define MIPI_CSIS_INT_SRC_EVEN BIT(30)
#define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29)
#define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28)
#define MIPI_CSIS_INT_SRC_ODD (0x3 << 28)
#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28)
#define MIPI_CSIS_INT_SRC_FRAME_START BIT(24)
#define MIPI_CSIS_INT_SRC_FRAME_END BIT(20)
#define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16)
#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12)
#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8)
#define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4)
#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
#define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
#define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
#define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
/* D-PHY status control */
#define MIPI_CSIS_DPHY_STATUS 0x20
#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8)
#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4)
#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1)
#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0)
/* D-PHY common control */
#define MIPI_CSIS_DPHY_CMN_CTRL 0x24
#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24)
#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
/* D-PHY Master and Slave Control register Low */
#define MIPI_CSIS_DPHY_BCTRL_L 0x30
#define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30)
#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28)
#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28)
#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28)
#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28)
#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27)
#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27)
#define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26)
#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24)
#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24)
#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24)
#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24)
#define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21)
#define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17)
#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15)
#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15)
#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15)
#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13)
#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13)
#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12)
#define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11)
#define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10)
#define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0)
/* D-PHY Master and Slave Control register High */
#define MIPI_CSIS_DPHY_BCTRL_H 0x34
/* D-PHY Slave Control register Low */
#define MIPI_CSIS_DPHY_SCTRL_L 0x38
/* D-PHY Slave Control register High */
#define MIPI_CSIS_DPHY_SCTRL_H 0x3c
/* ISP Configuration register */
#define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10)
#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12)
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12)
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */
#define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12)
#define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
#define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2)
#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
/* ISP Image Resolution register */
#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
#define CSIS_MAX_PIX_WIDTH 0xffff
#define CSIS_MAX_PIX_HEIGHT 0xffff
/* ISP SYNC register */
#define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
/* ISP shadow registers */
#define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
#define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10)
#define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10)
/* Debug control register */
#define MIPI_CSIS_DBG_CTRL 0xc0
#define MIPI_CSIS_DBG_INTR_MSK 0xc4
#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25)
#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24)
#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20)
#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12)
#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8)
#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4)
#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0)
#define MIPI_CSIS_DBG_INTR_SRC 0xc8
#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25)
#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24)
#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20)
#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12)
#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8)
#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4)
#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0)
#define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4)
/* Non-image packet data buffers */
#define MIPI_CSIS_PKTDATA_ODD 0x2000
#define MIPI_CSIS_PKTDATA_EVEN 0x3000
#define MIPI_CSIS_PKTDATA_SIZE SZ_4K
#define DEFAULT_SCLK_CSIS_FREQ 166000000UL
/* MIPI CSI-2 Data Types */
#define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18
#define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19
#define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a
#define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c
#define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d
#define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e
#define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f
#define MIPI_CSI2_DATA_TYPE_RGB565 0x22
#define MIPI_CSI2_DATA_TYPE_RGB666 0x23
#define MIPI_CSI2_DATA_TYPE_RGB888 0x24
#define MIPI_CSI2_DATA_TYPE_RAW6 0x28
#define MIPI_CSI2_DATA_TYPE_RAW7 0x29
#define MIPI_CSI2_DATA_TYPE_RAW8 0x2a
#define MIPI_CSI2_DATA_TYPE_RAW10 0x2b
#define MIPI_CSI2_DATA_TYPE_RAW12 0x2c
#define MIPI_CSI2_DATA_TYPE_RAW14 0x2d
#define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x))
struct mipi_csis_event {
bool debug;
u32 mask;
const char * const name;
unsigned int counter;
};
static const struct mipi_csis_event mipi_csis_events[] = {
/* Errors */
{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
{ false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
{ true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" },
{ true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" },
{ true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" },
{ true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" },
{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" },
/* Non-image data receive events */
{ false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" },
{ false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" },
{ false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" },
{ false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" },
/* Frame start/end */
{ false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" },
{ false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" },
{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" },
{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" },
};
#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
enum mipi_csis_clk {
MIPI_CSIS_CLK_PCLK,
MIPI_CSIS_CLK_WRAP,
MIPI_CSIS_CLK_PHY,
MIPI_CSIS_CLK_AXI,
};
static const char * const mipi_csis_clk_id[] = {
"pclk",
"wrap",
"phy",
"axi",
};
enum mipi_csis_version {
MIPI_CSIS_V3_3,
MIPI_CSIS_V3_6_3,
};
struct mipi_csis_info {
enum mipi_csis_version version;
unsigned int num_clocks;
};
struct mipi_csis_device {
struct device *dev;
void __iomem *regs;
struct clk_bulk_data *clks;
struct reset_control *mrst;
struct regulator *mipi_phy_regulator;
const struct mipi_csis_info *info;
struct v4l2_subdev sd;
struct media_pad pads[CSIS_PADS_NUM];
struct v4l2_async_notifier notifier;
struct v4l2_subdev *src_sd;
struct v4l2_mbus_config_mipi_csi2 bus;
u32 clk_frequency;
u32 hs_settle;
u32 clk_settle;
spinlock_t slock; /* Protect events */
struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
struct dentry *debugfs_root;
struct {
bool enable;
u32 hs_settle;
u32 clk_settle;
} debug;
};
/* -----------------------------------------------------------------------------
* Format helpers
*/
struct csis_pix_format {
u32 code;
u32 output;
u32 data_type;
u8 width;
};
static const struct csis_pix_format mipi_csis_formats[] = {
/* YUV formats. */
{
.code = MEDIA_BUS_FMT_UYVY8_1X16,
.output = MEDIA_BUS_FMT_UYVY8_1X16,
.data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
.width = 16,
},
/* RGB formats. */
{
.code = MEDIA_BUS_FMT_RGB565_1X16,
.output = MEDIA_BUS_FMT_RGB565_1X16,
.data_type = MIPI_CSI2_DATA_TYPE_RGB565,
.width = 16,
}, {
.code = MEDIA_BUS_FMT_BGR888_1X24,
.output = MEDIA_BUS_FMT_RGB888_1X24,
.data_type = MIPI_CSI2_DATA_TYPE_RGB888,
.width = 24,
},
/* RAW (Bayer and greyscale) formats. */
{
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
.output = MEDIA_BUS_FMT_SBGGR8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGBRG8_1X8,
.output = MEDIA_BUS_FMT_SGBRG8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGRBG8_1X8,
.output = MEDIA_BUS_FMT_SGRBG8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SRGGB8_1X8,
.output = MEDIA_BUS_FMT_SRGGB8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_Y8_1X8,
.output = MEDIA_BUS_FMT_Y8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SBGGR10_1X10,
.output = MEDIA_BUS_FMT_SBGGR10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGBRG10_1X10,
.output = MEDIA_BUS_FMT_SGBRG10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGRBG10_1X10,
.output = MEDIA_BUS_FMT_SGRBG10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
.output = MEDIA_BUS_FMT_SRGGB10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_Y10_1X10,
.output = MEDIA_BUS_FMT_Y10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SBGGR12_1X12,
.output = MEDIA_BUS_FMT_SBGGR12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGBRG12_1X12,
.output = MEDIA_BUS_FMT_SGBRG12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGRBG12_1X12,
.output = MEDIA_BUS_FMT_SGRBG12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SRGGB12_1X12,
.output = MEDIA_BUS_FMT_SRGGB12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_Y12_1X12,
.output = MEDIA_BUS_FMT_Y12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SBGGR14_1X14,
.output = MEDIA_BUS_FMT_SBGGR14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGBRG14_1X14,
.output = MEDIA_BUS_FMT_SGBRG14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGRBG14_1X14,
.output = MEDIA_BUS_FMT_SGRBG14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SRGGB14_1X14,
.output = MEDIA_BUS_FMT_SRGGB14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
},
/* JPEG */
{
.code = MEDIA_BUS_FMT_JPEG_1X8,
.output = MEDIA_BUS_FMT_JPEG_1X8,
/*
* Map JPEG_1X8 to the RAW8 datatype.
*
* The CSI-2 specification suggests in Annex A "JPEG8 Data
* Format (informative)" to transmit JPEG data using one of the
* Data Types aimed to represent arbitrary data, such as the
* "User Defined Data Type 1" (0x30).
*
* However, when configured with a User Defined Data Type, the
* CSIS outputs data in quad pixel mode regardless of the mode
* selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of
* the IP cores connected to the CSIS in i.MX SoCs (CSI bridge
* or ISI) support quad pixel mode, so this will never work in
* practice.
*
* Some sensors (such as the OV5640) send JPEG data using the
* RAW8 data type. This is usable and works, so map the JPEG
* format to RAW8. If the CSIS ends up being integrated in an
* SoC that can support quad pixel mode, this will have to be
* revisited.
*/
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}
};
static const struct csis_pix_format *find_csis_format(u32 code)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
if (code == mipi_csis_formats[i].code)
return &mipi_csis_formats[i];
return NULL;
}
/* -----------------------------------------------------------------------------
* Hardware configuration
*/
static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg)
{
return readl(csis->regs + reg);
}
static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
u32 val)
{
writel(val, csis->regs + reg);
}
static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
{
mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
}
static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
{
u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
val | MIPI_CSIS_CMN_CTRL_RESET);
usleep_range(10, 20);
}
static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
{
u32 val, mask;
val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
if (on)
val |= MIPI_CSIS_CMN_CTRL_ENABLE;
else
val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
if (on) {
mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
}
mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
}
static void __mipi_csis_set_format(struct mipi_csis_device *csis,
const struct v4l2_mbus_framefmt *format,
const struct csis_pix_format *csis_fmt)
{
u32 val;
/* Color format */
val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
| MIPI_CSIS_ISPCFG_PIXEL_MASK);
/*
* YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
* (referred to in the documentation as single and dual pixel modes
* respectively, although the 8-bit mode transfers half a pixel per
* clock sample and the 16-bit mode one pixel). While both mode work
* when the CSIS is connected to a receiver that supports either option,
* single pixel mode requires clock rates twice as high. As all SoCs
* that integrate the CSIS can operate in 16-bit bit mode, and some do
* not support 8-bit mode (this is the case of the i.MX8MP), use dual
* pixel mode unconditionally.
*
* TODO: Verify which other formats require DUAL (or QUAD) modes.
*/
if (csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8)
val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
/* Pixel resolution */
val = format->width | (format->height << 16);
mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
}
static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
const struct csis_pix_format *csis_fmt)
{
s64 link_freq;
u32 lane_rate;
/* Calculate the line rate from the pixel rate. */
link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler,
csis_fmt->width,
csis->bus.num_data_lanes * 2);
if (link_freq < 0) {
dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
(int)link_freq);
return link_freq;
}
lane_rate = link_freq * 2;
if (lane_rate < 80000000 || lane_rate > 1500000000) {
dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
return -EINVAL;
}
/*
* The HSSETTLE counter value is document in a table, but can also
* easily be calculated. Hardcode the CLKSETTLE value to 0 for now
* (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
* we figure out how to compute it correctly.
*/
csis->hs_settle = (lane_rate - 5000000) / 45000000;
csis->clk_settle = 0;
dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
lane_rate, csis->clk_settle, csis->hs_settle);
if (csis->debug.hs_settle < 0xff) {
dev_dbg(csis->dev, "overriding Ths_settle with %u\n",
csis->debug.hs_settle);
csis->hs_settle = csis->debug.hs_settle;
}
if (csis->debug.clk_settle < 4) {
dev_dbg(csis->dev, "overriding Tclk_settle with %u\n",
csis->debug.clk_settle);
csis->clk_settle = csis->debug.clk_settle;
}
return 0;
}
static void mipi_csis_set_params(struct mipi_csis_device *csis,
const struct v4l2_mbus_framefmt *format,
const struct csis_pix_format *csis_fmt)
{
int lanes = csis->bus.num_data_lanes;
u32 val;
val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
if (csis->info->version == MIPI_CSIS_V3_3)
val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
__mipi_csis_set_format(csis, format, csis_fmt);
mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL,
MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0);
/* Update the shadow register. */
val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
}
static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
{
return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
}
static void mipi_csis_clk_disable(struct mipi_csis_device *csis)
{
clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks);
}
static int mipi_csis_clk_get(struct mipi_csis_device *csis)
{
unsigned int i;
int ret;
csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks,
sizeof(*csis->clks), GFP_KERNEL);
if (!csis->clks)
return -ENOMEM;
for (i = 0; i < csis->info->num_clocks; i++)
csis->clks[i].id = mipi_csis_clk_id[i];
ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
csis->clks);
if (ret < 0)
return ret;
/* Set clock rate */
ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
csis->clk_frequency);
if (ret < 0)
dev_err(csis->dev, "set rate=%d failed: %d\n",
csis->clk_frequency, ret);
return ret;
}
static void mipi_csis_start_stream(struct mipi_csis_device *csis,
const struct v4l2_mbus_framefmt *format,
const struct csis_pix_format *csis_fmt)
{
mipi_csis_sw_reset(csis);
mipi_csis_set_params(csis, format, csis_fmt);
mipi_csis_system_enable(csis, true);
mipi_csis_enable_interrupts(csis, true);
}
static void mipi_csis_stop_stream(struct mipi_csis_device *csis)
{
mipi_csis_enable_interrupts(csis, false);
mipi_csis_system_enable(csis, false);
}
static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
{
struct mipi_csis_device *csis = dev_id;
unsigned long flags;
unsigned int i;
u32 status;
u32 dbg_status;
status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC);
spin_lock_irqsave(&csis->slock, flags);
/* Update the event/error counters */
if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
struct mipi_csis_event *event = &csis->events[i];
if ((!event->debug && (status & event->mask)) ||
(event->debug && (dbg_status & event->mask)))
event->counter++;
}
}
spin_unlock_irqrestore(&csis->slock, flags);
mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
return IRQ_HANDLED;
}
/* -----------------------------------------------------------------------------
* PHY regulator and reset
*/
static int mipi_csis_phy_enable(struct mipi_csis_device *csis)
{
if (csis->info->version != MIPI_CSIS_V3_3)
return 0;
return regulator_enable(csis->mipi_phy_regulator);
}
static int mipi_csis_phy_disable(struct mipi_csis_device *csis)
{
if (csis->info->version != MIPI_CSIS_V3_3)
return 0;
return regulator_disable(csis->mipi_phy_regulator);
}
static void mipi_csis_phy_reset(struct mipi_csis_device *csis)
{
if (csis->info->version != MIPI_CSIS_V3_3)
return;
reset_control_assert(csis->mrst);
msleep(20);
reset_control_deassert(csis->mrst);
}
static int mipi_csis_phy_init(struct mipi_csis_device *csis)
{
if (csis->info->version != MIPI_CSIS_V3_3)
return 0;
/* Get MIPI PHY reset and regulator. */
csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL);
if (IS_ERR(csis->mrst))
return PTR_ERR(csis->mrst);
csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy");
if (IS_ERR(csis->mipi_phy_regulator))
return PTR_ERR(csis->mipi_phy_regulator);
return regulator_set_voltage(csis->mipi_phy_regulator, 1000000,
1000000);
}
/* -----------------------------------------------------------------------------
* Debug
*/
static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
{
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&csis->slock, flags);
for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
csis->events[i].counter = 0;
spin_unlock_irqrestore(&csis->slock, flags);
}
static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
{
unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
: MIPI_CSIS_NUM_EVENTS - 8;
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&csis->slock, flags);
for (i = 0; i < num_events; ++i) {
if (csis->events[i].counter > 0 || csis->debug.enable)
dev_info(csis->dev, "%s events: %d\n",
csis->events[i].name,
csis->events[i].counter);
}
spin_unlock_irqrestore(&csis->slock, flags);
}
static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
{
static const struct {
u32 offset;
const char * const name;
} registers[] = {
{ MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
{ MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
{ MIPI_CSIS_INT_MSK, "INT_MSK" },
{ MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
{ MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
{ MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
{ MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
{ MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
{ MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
};
unsigned int i;
u32 cfg;
if (!pm_runtime_get_if_in_use(csis->dev))
return 0;
dev_info(csis->dev, "--- REGISTERS ---\n");
for (i = 0; i < ARRAY_SIZE(registers); i++) {
cfg = mipi_csis_read(csis, registers[i].offset);
dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
}
pm_runtime_put(csis->dev);
return 0;
}
static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
{
struct mipi_csis_device *csis = m->private;
return mipi_csis_dump_regs(csis);
}
DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
static void mipi_csis_debugfs_init(struct mipi_csis_device *csis)
{
csis->debug.hs_settle = UINT_MAX;
csis->debug.clk_settle = UINT_MAX;
csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL);
debugfs_create_bool("debug_enable", 0600, csis->debugfs_root,
&csis->debug.enable);
debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis,
&mipi_csis_dump_regs_fops);
debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root,
&csis->debug.clk_settle);
debugfs_create_u32("ths_settle", 0600, csis->debugfs_root,
&csis->debug.hs_settle);
}
static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
{
debugfs_remove_recursive(csis->debugfs_root);
}
/* -----------------------------------------------------------------------------
* V4L2 subdev operations
*/
static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
{
return container_of(sdev, struct mipi_csis_device, sd);
}
static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
{
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
const struct v4l2_mbus_framefmt *format;
const struct csis_pix_format *csis_fmt;
struct v4l2_subdev_state *state;
int ret;
if (!enable) {
v4l2_subdev_call(csis->src_sd, video, s_stream, 0);
mipi_csis_stop_stream(csis);
if (csis->debug.enable)
mipi_csis_log_counters(csis, true);
pm_runtime_put(csis->dev);
return 0;
}
state = v4l2_subdev_lock_and_get_active_state(sd);
format = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SINK);
csis_fmt = find_csis_format(format->code);
ret = mipi_csis_calculate_params(csis, csis_fmt);
if (ret < 0)
goto err_unlock;
mipi_csis_clear_counters(csis);
ret = pm_runtime_resume_and_get(csis->dev);
if (ret < 0)
goto err_unlock;
mipi_csis_start_stream(csis, format, csis_fmt);
ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1);
if (ret < 0)
goto err_stop;
mipi_csis_log_counters(csis, true);
v4l2_subdev_unlock_state(state);
return 0;
err_stop:
mipi_csis_stop_stream(csis);
pm_runtime_put(csis->dev);
err_unlock:
v4l2_subdev_unlock_state(state);
return ret;
}
static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
/*
* The CSIS can't transcode in any way, the source format is identical
* to the sink format.
*/
if (code->pad == CSIS_PAD_SOURCE) {
struct v4l2_mbus_framefmt *fmt;
if (code->index > 0)
return -EINVAL;
fmt = v4l2_subdev_get_pad_format(sd, sd_state, code->pad);
code->code = fmt->code;
return 0;
}
if (code->pad != CSIS_PAD_SINK)
return -EINVAL;
if (code->index >= ARRAY_SIZE(mipi_csis_formats))
return -EINVAL;
code->code = mipi_csis_formats[code->index].code;
return 0;
}
static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *sdformat)
{
struct csis_pix_format const *csis_fmt;
struct v4l2_mbus_framefmt *fmt;
unsigned int align;
/*
* The CSIS can't transcode in any way, the source format can't be
* modified.
*/
if (sdformat->pad == CSIS_PAD_SOURCE)
return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
if (sdformat->pad != CSIS_PAD_SINK)
return -EINVAL;
/*
* Validate the media bus code and clamp and align the size.
*
* The total number of bits per line must be a multiple of 8. We thus
* need to align the width for formats that are not multiples of 8
* bits.
*/
csis_fmt = find_csis_format(sdformat->format.code);
if (!csis_fmt)
csis_fmt = &mipi_csis_formats[0];
switch (csis_fmt->width % 8) {
case 0:
align = 0;
break;
case 4:
align = 1;
break;
case 2:
case 6:
align = 2;
break;
default:
/* 1, 3, 5, 7 */
align = 3;
break;
}
v4l_bound_align_image(&sdformat->format.width, 1,
CSIS_MAX_PIX_WIDTH, align,
&sdformat->format.height, 1,
CSIS_MAX_PIX_HEIGHT, 0, 0);
fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
fmt->code = csis_fmt->code;
fmt->width = sdformat->format.width;
fmt->height = sdformat->format.height;
fmt->field = V4L2_FIELD_NONE;
fmt->colorspace = sdformat->format.colorspace;
fmt->quantization = sdformat->format.quantization;
fmt->xfer_func = sdformat->format.xfer_func;
fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
sdformat->format = *fmt;
/* Propagate the format from sink to source. */
fmt = v4l2_subdev_get_pad_format(sd, sd_state, CSIS_PAD_SOURCE);
*fmt = sdformat->format;
/* The format on the source pad might change due to unpacking. */
fmt->code = csis_fmt->output;
return 0;
}
static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_frame_desc *fd)
{
struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0];
const struct csis_pix_format *csis_fmt;
const struct v4l2_mbus_framefmt *fmt;
struct v4l2_subdev_state *state;
if (pad != CSIS_PAD_SOURCE)
return -EINVAL;
state = v4l2_subdev_lock_and_get_active_state(sd);
fmt = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SOURCE);
csis_fmt = find_csis_format(fmt->code);
v4l2_subdev_unlock_state(state);
if (!csis_fmt)
return -EPIPE;
fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
fd->num_entries = 1;
memset(entry, 0, sizeof(*entry));
entry->flags = 0;
entry->pixelcode = csis_fmt->code;
entry->bus.csi2.vc = 0;
entry->bus.csi2.dt = csis_fmt->data_type;
return 0;
}
static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
struct v4l2_subdev_format fmt = {
.pad = CSIS_PAD_SINK,
};
fmt.format.code = mipi_csis_formats[0].code;
fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH;
fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT;
fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M;
fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace);
fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace);
fmt.format.quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace,
fmt.format.ycbcr_enc);
return mipi_csis_set_fmt(sd, sd_state, &fmt);
}
static int mipi_csis_log_status(struct v4l2_subdev *sd)
{
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
mipi_csis_log_counters(csis, true);
if (csis->debug.enable)
mipi_csis_dump_regs(csis);
return 0;
}
static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
.log_status = mipi_csis_log_status,
};
static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
.s_stream = mipi_csis_s_stream,
};
static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
.init_cfg = mipi_csis_init_cfg,
.enum_mbus_code = mipi_csis_enum_mbus_code,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = mipi_csis_set_fmt,
.get_frame_desc = mipi_csis_get_frame_desc,
};
static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
.core = &mipi_csis_core_ops,
.video = &mipi_csis_video_ops,
.pad = &mipi_csis_pad_ops,
};
/* -----------------------------------------------------------------------------
* Media entity operations
*/
static int mipi_csis_link_setup(struct media_entity *entity,
const struct media_pad *local_pad,
const struct media_pad *remote_pad, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
struct v4l2_subdev *remote_sd;
dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
local_pad->entity->name);
/* We only care about the link to the source. */
if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
return 0;
remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
if (flags & MEDIA_LNK_FL_ENABLED) {
if (csis->src_sd)
return -EBUSY;
csis->src_sd = remote_sd;
} else {
csis->src_sd = NULL;
}
return 0;
}
static const struct media_entity_operations mipi_csis_entity_ops = {
.link_setup = mipi_csis_link_setup,
.link_validate = v4l2_subdev_link_validate,
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
};
/* -----------------------------------------------------------------------------
* Async subdev notifier
*/
static struct mipi_csis_device *
mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
{
return container_of(n, struct mipi_csis_device, notifier);
}
static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *sd,
struct v4l2_async_connection *asd)
{
struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier);
struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK];
return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
}
static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
.bound = mipi_csis_notify_bound,
};
static int mipi_csis_async_register(struct mipi_csis_device *csis)
{
struct v4l2_fwnode_endpoint vep = {
.bus_type = V4L2_MBUS_CSI2_DPHY,
};
struct v4l2_async_connection *asd;
struct fwnode_handle *ep;
unsigned int i;
int ret;
v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd);
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep)
return -ENOTCONN;
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
if (ret)
goto err_parse;
for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
dev_err(csis->dev,
"data lanes reordering is not supported");
ret = -EINVAL;
goto err_parse;
}
}
csis->bus = vep.bus.mipi_csi2;
dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes);
dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
struct v4l2_async_connection);
if (IS_ERR(asd)) {
ret = PTR_ERR(asd);
goto err_parse;
}
fwnode_handle_put(ep);
csis->notifier.ops = &mipi_csis_notify_ops;
ret = v4l2_async_nf_register(&csis->notifier);
if (ret)
return ret;
return v4l2_async_register_subdev(&csis->sd);
err_parse:
fwnode_handle_put(ep);
return ret;
}
/* -----------------------------------------------------------------------------
* Suspend/resume
*/
static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
int ret;
ret = mipi_csis_phy_disable(csis);
if (ret)
return -EAGAIN;
mipi_csis_clk_disable(csis);
return 0;
}
static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
int ret;
ret = mipi_csis_phy_enable(csis);
if (ret)
return -EAGAIN;
ret = mipi_csis_clk_enable(csis);
if (ret) {
mipi_csis_phy_disable(csis);
return ret;
}
return 0;
}
static const struct dev_pm_ops mipi_csis_pm_ops = {
SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
NULL)
};
/* -----------------------------------------------------------------------------
* Probe/remove & platform driver
*/
static int mipi_csis_subdev_init(struct mipi_csis_device *csis)
{
struct v4l2_subdev *sd = &csis->sd;
int ret;
v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
sd->owner = THIS_MODULE;
snprintf(sd->name, sizeof(sd->name), "csis-%s",
dev_name(csis->dev));
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
sd->ctrl_handler = NULL;
sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
sd->entity.ops = &mipi_csis_entity_ops;
sd->dev = csis->dev;
csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
| MEDIA_PAD_FL_MUST_CONNECT;
csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
| MEDIA_PAD_FL_MUST_CONNECT;
ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads);
if (ret)
return ret;
ret = v4l2_subdev_init_finalize(sd);
if (ret) {
media_entity_cleanup(&sd->entity);
return ret;
}
return 0;
}
static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
{
struct device_node *node = csis->dev->of_node;
if (of_property_read_u32(node, "clock-frequency",
&csis->clk_frequency))
csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
return 0;
}
static int mipi_csis_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mipi_csis_device *csis;
int irq;
int ret;
csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
if (!csis)
return -ENOMEM;
spin_lock_init(&csis->slock);
csis->dev = dev;
csis->info = of_device_get_match_data(dev);
memcpy(csis->events, mipi_csis_events, sizeof(csis->events));
/* Parse DT properties. */
ret = mipi_csis_parse_dt(csis);
if (ret < 0) {
dev_err(dev, "Failed to parse device tree: %d\n", ret);
return ret;
}
/* Acquire resources. */
csis->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(csis->regs))
return PTR_ERR(csis->regs);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = mipi_csis_phy_init(csis);
if (ret < 0)
return ret;
ret = mipi_csis_clk_get(csis);
if (ret < 0)
return ret;
/* Reset PHY and enable the clocks. */
mipi_csis_phy_reset(csis);
ret = mipi_csis_clk_enable(csis);
if (ret < 0) {
dev_err(csis->dev, "failed to enable clocks: %d\n", ret);
return ret;
}
/* Now that the hardware is initialized, request the interrupt. */
ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
dev_name(dev), csis);
if (ret) {
dev_err(dev, "Interrupt request failed\n");
goto err_disable_clock;
}
/* Initialize and register the subdev. */
ret = mipi_csis_subdev_init(csis);
if (ret < 0)
goto err_disable_clock;
platform_set_drvdata(pdev, &csis->sd);
ret = mipi_csis_async_register(csis);
if (ret < 0) {
dev_err(dev, "async register failed: %d\n", ret);
goto err_cleanup;
}
/* Initialize debugfs. */
mipi_csis_debugfs_init(csis);
/* Enable runtime PM. */
pm_runtime_enable(dev);
if (!pm_runtime_enabled(dev)) {
ret = mipi_csis_runtime_resume(dev);
if (ret < 0)
goto err_unregister_all;
}
dev_info(dev, "lanes: %d, freq: %u\n",
csis->bus.num_data_lanes, csis->clk_frequency);
return 0;
err_unregister_all:
mipi_csis_debugfs_exit(csis);
err_cleanup:
v4l2_subdev_cleanup(&csis->sd);
media_entity_cleanup(&csis->sd.entity);
v4l2_async_nf_unregister(&csis->notifier);
v4l2_async_nf_cleanup(&csis->notifier);
v4l2_async_unregister_subdev(&csis->sd);
err_disable_clock:
mipi_csis_clk_disable(csis);
return ret;
}
static void mipi_csis_remove(struct platform_device *pdev)
{
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
mipi_csis_debugfs_exit(csis);
v4l2_async_nf_unregister(&csis->notifier);
v4l2_async_nf_cleanup(&csis->notifier);
v4l2_async_unregister_subdev(&csis->sd);
pm_runtime_disable(&pdev->dev);
mipi_csis_runtime_suspend(&pdev->dev);
mipi_csis_clk_disable(csis);
v4l2_subdev_cleanup(&csis->sd);
media_entity_cleanup(&csis->sd.entity);
pm_runtime_set_suspended(&pdev->dev);
}
static const struct of_device_id mipi_csis_of_match[] = {
{
.compatible = "fsl,imx7-mipi-csi2",
.data = &(const struct mipi_csis_info){
.version = MIPI_CSIS_V3_3,
.num_clocks = 3,
},
}, {
.compatible = "fsl,imx8mm-mipi-csi2",
.data = &(const struct mipi_csis_info){
.version = MIPI_CSIS_V3_6_3,
.num_clocks = 4,
},
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
static struct platform_driver mipi_csis_driver = {
.probe = mipi_csis_probe,
.remove_new = mipi_csis_remove,
.driver = {
.of_match_table = mipi_csis_of_match,
.name = CSIS_DRIVER_NAME,
.pm = &mipi_csis_pm_ops,
},
};
module_platform_driver(mipi_csis_driver);
MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-mipi-csi2");
| linux-master | drivers/media/platform/nxp/imx-mipi-csis.c |
// SPDX-License-Identifier: GPL-2.0
/*
* NXP i.MX8MQ SoC series MIPI-CSI2 receiver driver
*
* Copyright (C) 2021 Purism SPC
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mc.h>
#include <media/v4l2-subdev.h>
#define MIPI_CSI2_DRIVER_NAME "imx8mq-mipi-csi2"
#define MIPI_CSI2_SUBDEV_NAME MIPI_CSI2_DRIVER_NAME
#define MIPI_CSI2_PAD_SINK 0
#define MIPI_CSI2_PAD_SOURCE 1
#define MIPI_CSI2_PADS_NUM 2
#define MIPI_CSI2_DEF_PIX_WIDTH 640
#define MIPI_CSI2_DEF_PIX_HEIGHT 480
/* Register map definition */
/* i.MX8MQ CSI-2 controller CSR */
#define CSI2RX_CFG_NUM_LANES 0x100
#define CSI2RX_CFG_DISABLE_DATA_LANES 0x104
#define CSI2RX_BIT_ERR 0x108
#define CSI2RX_IRQ_STATUS 0x10c
#define CSI2RX_IRQ_MASK 0x110
#define CSI2RX_IRQ_MASK_ALL 0x1ff
#define CSI2RX_IRQ_MASK_ULPS_STATUS_CHANGE 0x8
#define CSI2RX_ULPS_STATUS 0x114
#define CSI2RX_PPI_ERRSOT_HS 0x118
#define CSI2RX_PPI_ERRSOTSYNC_HS 0x11c
#define CSI2RX_PPI_ERRESC 0x120
#define CSI2RX_PPI_ERRSYNCESC 0x124
#define CSI2RX_PPI_ERRCONTROL 0x128
#define CSI2RX_CFG_DISABLE_PAYLOAD_0 0x12c
#define CSI2RX_CFG_VID_VC_IGNORE 0x180
#define CSI2RX_CFG_VID_VC 0x184
#define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL 0x188
#define CSI2RX_CFG_DISABLE_PAYLOAD_1 0x130
enum {
ST_POWERED = 1,
ST_STREAMING = 2,
ST_SUSPENDED = 4,
};
enum imx8mq_mipi_csi_clk {
CSI2_CLK_CORE,
CSI2_CLK_ESC,
CSI2_CLK_UI,
CSI2_NUM_CLKS,
};
static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
[CSI2_CLK_CORE] = "core",
[CSI2_CLK_ESC] = "esc",
[CSI2_CLK_UI] = "ui",
};
#define CSI2_NUM_CLKS ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
#define GPR_CSI2_1_RX_ENABLE BIT(13)
#define GPR_CSI2_1_VID_INTFC_ENB BIT(12)
#define GPR_CSI2_1_HSEL BIT(10)
#define GPR_CSI2_1_CONT_CLK_MODE BIT(8)
#define GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
/*
* The send level configures the number of entries that must accumulate in
* the Pixel FIFO before the data will be transferred to the video output.
* The exact value needed for this configuration is dependent on the rate at
* which the sensor transfers data to the CSI-2 Controller and the user
* video clock.
*
* The calculation is the classical rate-in rate-out type of problem: If the
* video bandwidth is 10% faster than the incoming mipi data and the video
* line length is 500 pixels, then the fifo should be allowed to fill
* 10% of the line length or 50 pixels. If the gap data is ok, then the level
* can be set to 16 and ignored.
*/
#define CSI2RX_SEND_LEVEL 64
struct csi_state {
struct device *dev;
void __iomem *regs;
struct clk_bulk_data clks[CSI2_NUM_CLKS];
struct reset_control *rst;
struct regulator *mipi_phy_regulator;
struct v4l2_subdev sd;
struct media_pad pads[MIPI_CSI2_PADS_NUM];
struct v4l2_async_notifier notifier;
struct v4l2_subdev *src_sd;
struct v4l2_mbus_config_mipi_csi2 bus;
struct mutex lock; /* Protect state */
u32 state;
struct regmap *phy_gpr;
u8 phy_gpr_reg;
struct icc_path *icc_path;
s32 icc_path_bw;
};
/* -----------------------------------------------------------------------------
* Format helpers
*/
struct csi2_pix_format {
u32 code;
u8 width;
};
static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
/* RAW (Bayer and greyscale) formats. */
{
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGBRG8_1X8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGRBG8_1X8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SRGGB8_1X8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_Y8_1X8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SBGGR10_1X10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGBRG10_1X10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGRBG10_1X10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_Y10_1X10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SBGGR12_1X12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGBRG12_1X12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGRBG12_1X12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SRGGB12_1X12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_Y12_1X12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SBGGR14_1X14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGBRG14_1X14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGRBG14_1X14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SRGGB14_1X14,
.width = 14,
},
/* YUV formats */
{
.code = MEDIA_BUS_FMT_YUYV8_1X16,
.width = 16,
}, {
.code = MEDIA_BUS_FMT_UYVY8_1X16,
.width = 16,
}
};
static const struct csi2_pix_format *find_csi2_format(u32 code)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(imx8mq_mipi_csi_formats); i++)
if (code == imx8mq_mipi_csi_formats[i].code)
return &imx8mq_mipi_csi_formats[i];
return NULL;
}
/* -----------------------------------------------------------------------------
* Hardware configuration
*/
static inline void imx8mq_mipi_csi_write(struct csi_state *state, u32 reg, u32 val)
{
writel(val, state->regs + reg);
}
static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
{
int ret;
/*
* these are most likely self-clearing reset bits. to make it
* more clear, the reset-imx7 driver should implement the
* .reset() operation.
*/
ret = reset_control_assert(state->rst);
if (ret < 0) {
dev_err(state->dev, "Failed to assert resets: %d\n", ret);
return ret;
}
return 0;
}
static void imx8mq_mipi_csi_set_params(struct csi_state *state)
{
int lanes = state->bus.num_data_lanes;
imx8mq_mipi_csi_write(state, CSI2RX_CFG_NUM_LANES, lanes - 1);
imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES,
(0xf << lanes) & 0xf);
imx8mq_mipi_csi_write(state, CSI2RX_IRQ_MASK, CSI2RX_IRQ_MASK_ALL);
/*
* 0x180 bit 0 controls the Virtual Channel behaviour: when set the
* interface ignores the Virtual Channel (VC) field in received packets;
* when cleared it causes the interface to only accept packets whose VC
* matches the value to which VC is set at offset 0x184.
*/
imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_VC_IGNORE, 1);
imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL,
CSI2RX_SEND_LEVEL);
}
static int imx8mq_mipi_csi_clk_enable(struct csi_state *state)
{
return clk_bulk_prepare_enable(CSI2_NUM_CLKS, state->clks);
}
static void imx8mq_mipi_csi_clk_disable(struct csi_state *state)
{
clk_bulk_disable_unprepare(CSI2_NUM_CLKS, state->clks);
}
static int imx8mq_mipi_csi_clk_get(struct csi_state *state)
{
unsigned int i;
for (i = 0; i < CSI2_NUM_CLKS; i++)
state->clks[i].id = imx8mq_mipi_csi_clk_id[i];
return devm_clk_bulk_get(state->dev, CSI2_NUM_CLKS, state->clks);
}
static int imx8mq_mipi_csi_calc_hs_settle(struct csi_state *state,
struct v4l2_subdev_state *sd_state,
u32 *hs_settle)
{
s64 link_freq;
u32 lane_rate;
unsigned long esc_clk_rate;
u32 min_ths_settle, max_ths_settle, ths_settle_ns, esc_clk_period_ns;
const struct v4l2_mbus_framefmt *fmt;
const struct csi2_pix_format *csi2_fmt;
/* Calculate the line rate from the pixel rate. */
fmt = v4l2_subdev_get_pad_format(&state->sd, sd_state, MIPI_CSI2_PAD_SINK);
csi2_fmt = find_csi2_format(fmt->code);
link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
csi2_fmt->width,
state->bus.num_data_lanes * 2);
if (link_freq < 0) {
dev_err(state->dev, "Unable to obtain link frequency: %d\n",
(int)link_freq);
return link_freq;
}
lane_rate = link_freq * 2;
if (lane_rate < 80000000 || lane_rate > 1500000000) {
dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
return -EINVAL;
}
/*
* The D-PHY specification requires Ths-settle to be in the range
* 85ns + 6*UI to 140ns + 10*UI, with the unit interval UI being half
* the clock period.
*
* The Ths-settle value is expressed in the hardware as a multiple of
* the Esc clock period:
*
* Ths-settle = (PRG_RXHS_SETTLE + 1) * Tperiod of RxClkInEsc
*
* Due to the one cycle inaccuracy introduced by rounding, the
* documentation recommends picking a value away from the boundaries.
* Let's pick the average.
*/
esc_clk_rate = clk_get_rate(state->clks[CSI2_CLK_ESC].clk);
if (!esc_clk_rate) {
dev_err(state->dev, "Could not get esc clock rate.\n");
return -EINVAL;
}
dev_dbg(state->dev, "esc clk rate: %lu\n", esc_clk_rate);
esc_clk_period_ns = 1000000000 / esc_clk_rate;
min_ths_settle = 85 + 6 * 1000000 / (lane_rate / 1000);
max_ths_settle = 140 + 10 * 1000000 / (lane_rate / 1000);
ths_settle_ns = (min_ths_settle + max_ths_settle) / 2;
*hs_settle = ths_settle_ns / esc_clk_period_ns - 1;
dev_dbg(state->dev, "lane rate %u Ths_settle %u hs_settle %u\n",
lane_rate, ths_settle_ns, *hs_settle);
return 0;
}
static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
struct v4l2_subdev_state *sd_state)
{
int ret;
u32 hs_settle = 0;
ret = imx8mq_mipi_csi_sw_reset(state);
if (ret)
return ret;
imx8mq_mipi_csi_set_params(state);
ret = imx8mq_mipi_csi_calc_hs_settle(state, sd_state, &hs_settle);
if (ret)
return ret;
regmap_update_bits(state->phy_gpr,
state->phy_gpr_reg,
0x3fff,
GPR_CSI2_1_RX_ENABLE |
GPR_CSI2_1_VID_INTFC_ENB |
GPR_CSI2_1_HSEL |
GPR_CSI2_1_CONT_CLK_MODE |
GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
return 0;
}
static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
{
imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
}
/* -----------------------------------------------------------------------------
* V4L2 subdev operations
*/
static struct csi_state *mipi_sd_to_csi2_state(struct v4l2_subdev *sdev)
{
return container_of(sdev, struct csi_state, sd);
}
static int imx8mq_mipi_csi_s_stream(struct v4l2_subdev *sd, int enable)
{
struct csi_state *state = mipi_sd_to_csi2_state(sd);
struct v4l2_subdev_state *sd_state;
int ret = 0;
if (enable) {
ret = pm_runtime_resume_and_get(state->dev);
if (ret < 0)
return ret;
}
mutex_lock(&state->lock);
if (enable) {
if (state->state & ST_SUSPENDED) {
ret = -EBUSY;
goto unlock;
}
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
ret = imx8mq_mipi_csi_start_stream(state, sd_state);
v4l2_subdev_unlock_state(sd_state);
if (ret < 0)
goto unlock;
ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
if (ret < 0)
goto unlock;
state->state |= ST_STREAMING;
} else {
v4l2_subdev_call(state->src_sd, video, s_stream, 0);
imx8mq_mipi_csi_stop_stream(state);
state->state &= ~ST_STREAMING;
}
unlock:
mutex_unlock(&state->lock);
if (!enable || ret < 0)
pm_runtime_put(state->dev);
return ret;
}
static int imx8mq_mipi_csi_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
struct v4l2_mbus_framefmt *fmt_sink;
struct v4l2_mbus_framefmt *fmt_source;
fmt_sink = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SINK);
fmt_source = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);
fmt_sink->code = MEDIA_BUS_FMT_SGBRG10_1X10;
fmt_sink->width = MIPI_CSI2_DEF_PIX_WIDTH;
fmt_sink->height = MIPI_CSI2_DEF_PIX_HEIGHT;
fmt_sink->field = V4L2_FIELD_NONE;
fmt_sink->colorspace = V4L2_COLORSPACE_RAW;
fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
fmt_sink->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
fmt_sink->ycbcr_enc);
*fmt_source = *fmt_sink;
return 0;
}
static int imx8mq_mipi_csi_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
/*
* We can't transcode in any way, the source format is identical
* to the sink format.
*/
if (code->pad == MIPI_CSI2_PAD_SOURCE) {
struct v4l2_mbus_framefmt *fmt;
if (code->index > 0)
return -EINVAL;
fmt = v4l2_subdev_get_pad_format(sd, sd_state, code->pad);
code->code = fmt->code;
return 0;
}
if (code->pad != MIPI_CSI2_PAD_SINK)
return -EINVAL;
if (code->index >= ARRAY_SIZE(imx8mq_mipi_csi_formats))
return -EINVAL;
code->code = imx8mq_mipi_csi_formats[code->index].code;
return 0;
}
static int imx8mq_mipi_csi_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *sdformat)
{
const struct csi2_pix_format *csi2_fmt;
struct v4l2_mbus_framefmt *fmt;
/*
* The device can't transcode in any way, the source format can't be
* modified.
*/
if (sdformat->pad == MIPI_CSI2_PAD_SOURCE)
return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
if (sdformat->pad != MIPI_CSI2_PAD_SINK)
return -EINVAL;
csi2_fmt = find_csi2_format(sdformat->format.code);
if (!csi2_fmt)
csi2_fmt = &imx8mq_mipi_csi_formats[0];
fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
fmt->code = csi2_fmt->code;
fmt->width = sdformat->format.width;
fmt->height = sdformat->format.height;
sdformat->format = *fmt;
/* Propagate the format from sink to source. */
fmt = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);
*fmt = sdformat->format;
return 0;
}
static const struct v4l2_subdev_video_ops imx8mq_mipi_csi_video_ops = {
.s_stream = imx8mq_mipi_csi_s_stream,
};
static const struct v4l2_subdev_pad_ops imx8mq_mipi_csi_pad_ops = {
.init_cfg = imx8mq_mipi_csi_init_cfg,
.enum_mbus_code = imx8mq_mipi_csi_enum_mbus_code,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = imx8mq_mipi_csi_set_fmt,
};
static const struct v4l2_subdev_ops imx8mq_mipi_csi_subdev_ops = {
.video = &imx8mq_mipi_csi_video_ops,
.pad = &imx8mq_mipi_csi_pad_ops,
};
/* -----------------------------------------------------------------------------
* Media entity operations
*/
static const struct media_entity_operations imx8mq_mipi_csi_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
};
/* -----------------------------------------------------------------------------
* Async subdev notifier
*/
static struct csi_state *
mipi_notifier_to_csi2_state(struct v4l2_async_notifier *n)
{
return container_of(n, struct csi_state, notifier);
}
static int imx8mq_mipi_csi_notify_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *sd,
struct v4l2_async_connection *asd)
{
struct csi_state *state = mipi_notifier_to_csi2_state(notifier);
struct media_pad *sink = &state->sd.entity.pads[MIPI_CSI2_PAD_SINK];
state->src_sd = sd;
return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
MEDIA_LNK_FL_IMMUTABLE);
}
static const struct v4l2_async_notifier_operations imx8mq_mipi_csi_notify_ops = {
.bound = imx8mq_mipi_csi_notify_bound,
};
static int imx8mq_mipi_csi_async_register(struct csi_state *state)
{
struct v4l2_fwnode_endpoint vep = {
.bus_type = V4L2_MBUS_CSI2_DPHY,
};
struct v4l2_async_connection *asd;
struct fwnode_handle *ep;
unsigned int i;
int ret;
v4l2_async_subdev_nf_init(&state->notifier, &state->sd);
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep)
return -ENOTCONN;
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
if (ret)
goto err_parse;
for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
dev_err(state->dev,
"data lanes reordering is not supported");
ret = -EINVAL;
goto err_parse;
}
}
state->bus = vep.bus.mipi_csi2;
dev_dbg(state->dev, "data lanes: %d flags: 0x%08x\n",
state->bus.num_data_lanes,
state->bus.flags);
asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep,
struct v4l2_async_connection);
if (IS_ERR(asd)) {
ret = PTR_ERR(asd);
goto err_parse;
}
fwnode_handle_put(ep);
state->notifier.ops = &imx8mq_mipi_csi_notify_ops;
ret = v4l2_async_nf_register(&state->notifier);
if (ret)
return ret;
return v4l2_async_register_subdev(&state->sd);
err_parse:
fwnode_handle_put(ep);
return ret;
}
/* -----------------------------------------------------------------------------
* Suspend/resume
*/
static void imx8mq_mipi_csi_pm_suspend(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
mutex_lock(&state->lock);
if (state->state & ST_POWERED) {
imx8mq_mipi_csi_stop_stream(state);
imx8mq_mipi_csi_clk_disable(state);
state->state &= ~ST_POWERED;
}
mutex_unlock(&state->lock);
}
static int imx8mq_mipi_csi_pm_resume(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
struct v4l2_subdev_state *sd_state;
int ret = 0;
mutex_lock(&state->lock);
if (!(state->state & ST_POWERED)) {
state->state |= ST_POWERED;
ret = imx8mq_mipi_csi_clk_enable(state);
}
if (state->state & ST_STREAMING) {
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
ret = imx8mq_mipi_csi_start_stream(state, sd_state);
v4l2_subdev_unlock_state(sd_state);
if (ret)
goto unlock;
}
state->state &= ~ST_SUSPENDED;
unlock:
mutex_unlock(&state->lock);
return ret ? -EAGAIN : 0;
}
static int __maybe_unused imx8mq_mipi_csi_suspend(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
imx8mq_mipi_csi_pm_suspend(dev);
state->state |= ST_SUSPENDED;
return 0;
}
static int __maybe_unused imx8mq_mipi_csi_resume(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
if (!(state->state & ST_SUSPENDED))
return 0;
return imx8mq_mipi_csi_pm_resume(dev);
}
static int __maybe_unused imx8mq_mipi_csi_runtime_suspend(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
int ret;
imx8mq_mipi_csi_pm_suspend(dev);
ret = icc_set_bw(state->icc_path, 0, 0);
if (ret)
dev_err(dev, "icc_set_bw failed with %d\n", ret);
return ret;
}
static int __maybe_unused imx8mq_mipi_csi_runtime_resume(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
int ret;
ret = icc_set_bw(state->icc_path, 0, state->icc_path_bw);
if (ret) {
dev_err(dev, "icc_set_bw failed with %d\n", ret);
return ret;
}
return imx8mq_mipi_csi_pm_resume(dev);
}
static const struct dev_pm_ops imx8mq_mipi_csi_pm_ops = {
SET_RUNTIME_PM_OPS(imx8mq_mipi_csi_runtime_suspend,
imx8mq_mipi_csi_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(imx8mq_mipi_csi_suspend, imx8mq_mipi_csi_resume)
};
/* -----------------------------------------------------------------------------
* Probe/remove & platform driver
*/
static int imx8mq_mipi_csi_subdev_init(struct csi_state *state)
{
struct v4l2_subdev *sd = &state->sd;
int ret;
v4l2_subdev_init(sd, &imx8mq_mipi_csi_subdev_ops);
sd->owner = THIS_MODULE;
snprintf(sd->name, sizeof(sd->name), "%s %s",
MIPI_CSI2_SUBDEV_NAME, dev_name(state->dev));
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
sd->entity.ops = &imx8mq_mipi_csi_entity_ops;
sd->dev = state->dev;
state->pads[MIPI_CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
| MEDIA_PAD_FL_MUST_CONNECT;
state->pads[MIPI_CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
| MEDIA_PAD_FL_MUST_CONNECT;
ret = media_entity_pads_init(&sd->entity, MIPI_CSI2_PADS_NUM,
state->pads);
if (ret)
return ret;
ret = v4l2_subdev_init_finalize(sd);
if (ret) {
media_entity_cleanup(&sd->entity);
return ret;
}
return 0;
}
static void imx8mq_mipi_csi_release_icc(struct platform_device *pdev)
{
struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
icc_put(state->icc_path);
}
static int imx8mq_mipi_csi_init_icc(struct platform_device *pdev)
{
struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
/* Optional interconnect request */
state->icc_path = of_icc_get(&pdev->dev, "dram");
if (IS_ERR_OR_NULL(state->icc_path))
return PTR_ERR_OR_ZERO(state->icc_path);
state->icc_path_bw = MBps_to_icc(700);
return 0;
}
static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
{
struct device *dev = state->dev;
struct device_node *np = state->dev->of_node;
struct device_node *node;
phandle ph;
u32 out_val[2];
int ret = 0;
state->rst = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(state->rst)) {
dev_err(dev, "Failed to get reset: %pe\n", state->rst);
return PTR_ERR(state->rst);
}
ret = of_property_read_u32_array(np, "fsl,mipi-phy-gpr", out_val,
ARRAY_SIZE(out_val));
if (ret) {
dev_err(dev, "no fsl,mipi-phy-gpr property found: %d\n", ret);
return ret;
}
ph = *out_val;
node = of_find_node_by_phandle(ph);
if (!node) {
dev_err(dev, "Error finding node by phandle\n");
return -ENODEV;
}
state->phy_gpr = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(state->phy_gpr)) {
dev_err(dev, "failed to get gpr regmap: %pe\n", state->phy_gpr);
return PTR_ERR(state->phy_gpr);
}
state->phy_gpr_reg = out_val[1];
dev_dbg(dev, "phy gpr register set to 0x%x\n", state->phy_gpr_reg);
return ret;
}
static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct csi_state *state;
int ret;
state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
state->dev = dev;
ret = imx8mq_mipi_csi_parse_dt(state);
if (ret < 0) {
dev_err(dev, "Failed to parse device tree: %d\n", ret);
return ret;
}
/* Acquire resources. */
state->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(state->regs))
return PTR_ERR(state->regs);
ret = imx8mq_mipi_csi_clk_get(state);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, &state->sd);
mutex_init(&state->lock);
ret = imx8mq_mipi_csi_subdev_init(state);
if (ret < 0)
goto mutex;
ret = imx8mq_mipi_csi_init_icc(pdev);
if (ret)
goto mutex;
/* Enable runtime PM. */
pm_runtime_enable(dev);
if (!pm_runtime_enabled(dev)) {
ret = imx8mq_mipi_csi_runtime_resume(dev);
if (ret < 0)
goto icc;
}
ret = imx8mq_mipi_csi_async_register(state);
if (ret < 0)
goto cleanup;
return 0;
cleanup:
pm_runtime_disable(&pdev->dev);
imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
media_entity_cleanup(&state->sd.entity);
v4l2_subdev_cleanup(&state->sd);
v4l2_async_nf_unregister(&state->notifier);
v4l2_async_nf_cleanup(&state->notifier);
v4l2_async_unregister_subdev(&state->sd);
icc:
imx8mq_mipi_csi_release_icc(pdev);
mutex:
mutex_destroy(&state->lock);
return ret;
}
static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
{
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
struct csi_state *state = mipi_sd_to_csi2_state(sd);
v4l2_async_nf_unregister(&state->notifier);
v4l2_async_nf_cleanup(&state->notifier);
v4l2_async_unregister_subdev(&state->sd);
pm_runtime_disable(&pdev->dev);
imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
media_entity_cleanup(&state->sd.entity);
v4l2_subdev_cleanup(&state->sd);
mutex_destroy(&state->lock);
pm_runtime_set_suspended(&pdev->dev);
imx8mq_mipi_csi_release_icc(pdev);
}
static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
{ .compatible = "fsl,imx8mq-mipi-csi2", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);
static struct platform_driver imx8mq_mipi_csi_driver = {
.probe = imx8mq_mipi_csi_probe,
.remove_new = imx8mq_mipi_csi_remove,
.driver = {
.of_match_table = imx8mq_mipi_csi_of_match,
.name = MIPI_CSI2_DRIVER_NAME,
.pm = &imx8mq_mipi_csi_pm_ops,
},
};
module_platform_driver(imx8mq_mipi_csi_driver);
MODULE_DESCRIPTION("i.MX8MQ MIPI CSI-2 receiver driver");
MODULE_AUTHOR("Martin Kepplinger <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx8mq-mipi-csi2");
| linux-master | drivers/media/platform/nxp/imx8mq-mipi-csi2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support eMMa-PrP through mem2mem framework.
*
* eMMa-PrP is a piece of HW that allows fetching buffers
* from one memory location and do several operations on
* them such as scaling or format conversion giving, as a result
* a new processed buffer in another memory location.
*
* Based on mem2mem_testdev.c by Pawel Osciak.
*
* Copyright (c) 2011 Vista Silicon S.L.
* Javier Martin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-dma-contig.h>
#include <linux/sizes.h>
#define EMMAPRP_MODULE_NAME "mem2mem-emmaprp"
MODULE_DESCRIPTION("Mem-to-mem device which supports eMMa-PrP present in mx2 SoCs");
MODULE_AUTHOR("Javier Martin <[email protected]");
MODULE_LICENSE("GPL");
MODULE_VERSION("0.0.1");
static bool debug;
module_param(debug, bool, 0644);
#define MIN_W 32
#define MIN_H 32
#define MAX_W 2040
#define MAX_H 2046
#define S_ALIGN 1 /* multiple of 2 */
#define W_ALIGN_YUV420 3 /* multiple of 8 */
#define W_ALIGN_OTHERS 2 /* multiple of 4 */
#define H_ALIGN 1 /* multiple of 2 */
/* Flags that indicate a format can be used for capture/output */
#define MEM2MEM_CAPTURE (1 << 0)
#define MEM2MEM_OUTPUT (1 << 1)
#define MEM2MEM_NAME "m2m-emmaprp"
/* In bytes, per queue */
#define MEM2MEM_VID_MEM_LIMIT SZ_16M
#define dprintk(dev, fmt, arg...) \
v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
/* EMMA PrP */
#define PRP_CNTL 0x00
#define PRP_INTR_CNTL 0x04
#define PRP_INTRSTATUS 0x08
#define PRP_SOURCE_Y_PTR 0x0c
#define PRP_SOURCE_CB_PTR 0x10
#define PRP_SOURCE_CR_PTR 0x14
#define PRP_DEST_RGB1_PTR 0x18
#define PRP_DEST_RGB2_PTR 0x1c
#define PRP_DEST_Y_PTR 0x20
#define PRP_DEST_CB_PTR 0x24
#define PRP_DEST_CR_PTR 0x28
#define PRP_SRC_FRAME_SIZE 0x2c
#define PRP_DEST_CH1_LINE_STRIDE 0x30
#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
#define PRP_CH1_OUT_IMAGE_SIZE 0x3c
#define PRP_CH2_OUT_IMAGE_SIZE 0x40
#define PRP_SRC_LINE_STRIDE 0x44
#define PRP_CSC_COEF_012 0x48
#define PRP_CSC_COEF_345 0x4c
#define PRP_CSC_COEF_678 0x50
#define PRP_CH1_RZ_HORI_COEF1 0x54
#define PRP_CH1_RZ_HORI_COEF2 0x58
#define PRP_CH1_RZ_HORI_VALID 0x5c
#define PRP_CH1_RZ_VERT_COEF1 0x60
#define PRP_CH1_RZ_VERT_COEF2 0x64
#define PRP_CH1_RZ_VERT_VALID 0x68
#define PRP_CH2_RZ_HORI_COEF1 0x6c
#define PRP_CH2_RZ_HORI_COEF2 0x70
#define PRP_CH2_RZ_HORI_VALID 0x74
#define PRP_CH2_RZ_VERT_COEF1 0x78
#define PRP_CH2_RZ_VERT_COEF2 0x7c
#define PRP_CH2_RZ_VERT_VALID 0x80
#define PRP_CNTL_CH1EN (1 << 0)
#define PRP_CNTL_CH2EN (1 << 1)
#define PRP_CNTL_CSIEN (1 << 2)
#define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
#define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
#define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
#define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
#define PRP_CNTL_CH1_LEN (1 << 9)
#define PRP_CNTL_CH2_LEN (1 << 10)
#define PRP_CNTL_SKIP_FRAME (1 << 11)
#define PRP_CNTL_SWRST (1 << 12)
#define PRP_CNTL_CLKEN (1 << 13)
#define PRP_CNTL_WEN (1 << 14)
#define PRP_CNTL_CH1BYP (1 << 15)
#define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
#define PRP_CNTL_CH2B1EN (1 << 29)
#define PRP_CNTL_CH2B2EN (1 << 30)
#define PRP_CNTL_CH2FEN (1UL << 31)
#define PRP_SIZE_HEIGHT(x) (x)
#define PRP_SIZE_WIDTH(x) ((x) << 16)
/* IRQ Enable and status register */
#define PRP_INTR_RDERR (1 << 0)
#define PRP_INTR_CH1WERR (1 << 1)
#define PRP_INTR_CH2WERR (1 << 2)
#define PRP_INTR_CH1FC (1 << 3)
#define PRP_INTR_CH2FC (1 << 5)
#define PRP_INTR_LBOVF (1 << 7)
#define PRP_INTR_CH2OVF (1 << 8)
#define PRP_INTR_ST_RDERR (1 << 0)
#define PRP_INTR_ST_CH1WERR (1 << 1)
#define PRP_INTR_ST_CH2WERR (1 << 2)
#define PRP_INTR_ST_CH2B2CI (1 << 3)
#define PRP_INTR_ST_CH2B1CI (1 << 4)
#define PRP_INTR_ST_CH1B2CI (1 << 5)
#define PRP_INTR_ST_CH1B1CI (1 << 6)
#define PRP_INTR_ST_LBOVF (1 << 7)
#define PRP_INTR_ST_CH2OVF (1 << 8)
struct emmaprp_fmt {
u32 fourcc;
/* Types the format can be used for */
u32 types;
};
static struct emmaprp_fmt formats[] = {
{
.fourcc = V4L2_PIX_FMT_YUV420,
.types = MEM2MEM_CAPTURE,
},
{
.fourcc = V4L2_PIX_FMT_YUYV,
.types = MEM2MEM_OUTPUT,
},
};
/* Per-queue, driver-specific private data */
struct emmaprp_q_data {
unsigned int width;
unsigned int height;
unsigned int sizeimage;
struct emmaprp_fmt *fmt;
};
enum {
V4L2_M2M_SRC = 0,
V4L2_M2M_DST = 1,
};
#define NUM_FORMATS ARRAY_SIZE(formats)
static struct emmaprp_fmt *find_format(struct v4l2_format *f)
{
struct emmaprp_fmt *fmt;
unsigned int k;
for (k = 0; k < NUM_FORMATS; k++) {
fmt = &formats[k];
if (fmt->fourcc == f->fmt.pix.pixelformat)
break;
}
if (k == NUM_FORMATS)
return NULL;
return &formats[k];
}
struct emmaprp_dev {
struct v4l2_device v4l2_dev;
struct video_device *vfd;
struct mutex dev_mutex;
spinlock_t irqlock;
void __iomem *base_emma;
struct clk *clk_emma_ahb, *clk_emma_ipg;
struct v4l2_m2m_dev *m2m_dev;
};
struct emmaprp_ctx {
struct v4l2_fh fh;
struct emmaprp_dev *dev;
/* Abort requested by m2m */
int aborting;
struct emmaprp_q_data q_data[2];
};
static struct emmaprp_q_data *get_q_data(struct emmaprp_ctx *ctx,
enum v4l2_buf_type type)
{
switch (type) {
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
return &(ctx->q_data[V4L2_M2M_SRC]);
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
return &(ctx->q_data[V4L2_M2M_DST]);
default:
BUG();
}
return NULL;
}
/*
* mem2mem callbacks
*/
static void emmaprp_job_abort(void *priv)
{
struct emmaprp_ctx *ctx = priv;
struct emmaprp_dev *pcdev = ctx->dev;
ctx->aborting = 1;
dprintk(pcdev, "Aborting task\n");
v4l2_m2m_job_finish(pcdev->m2m_dev, ctx->fh.m2m_ctx);
}
static inline void emmaprp_dump_regs(struct emmaprp_dev *pcdev)
{
dprintk(pcdev,
"eMMa-PrP Registers:\n"
" SOURCE_Y_PTR = 0x%08X\n"
" SRC_FRAME_SIZE = 0x%08X\n"
" DEST_Y_PTR = 0x%08X\n"
" DEST_CR_PTR = 0x%08X\n"
" DEST_CB_PTR = 0x%08X\n"
" CH2_OUT_IMAGE_SIZE = 0x%08X\n"
" CNTL = 0x%08X\n",
readl(pcdev->base_emma + PRP_SOURCE_Y_PTR),
readl(pcdev->base_emma + PRP_SRC_FRAME_SIZE),
readl(pcdev->base_emma + PRP_DEST_Y_PTR),
readl(pcdev->base_emma + PRP_DEST_CR_PTR),
readl(pcdev->base_emma + PRP_DEST_CB_PTR),
readl(pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE),
readl(pcdev->base_emma + PRP_CNTL));
}
static void emmaprp_device_run(void *priv)
{
struct emmaprp_ctx *ctx = priv;
struct emmaprp_q_data *s_q_data, *d_q_data;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct emmaprp_dev *pcdev = ctx->dev;
unsigned int s_width, s_height;
unsigned int d_width, d_height;
unsigned int d_size;
dma_addr_t p_in, p_out;
u32 tmp;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
s_width = s_q_data->width;
s_height = s_q_data->height;
d_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
d_width = d_q_data->width;
d_height = d_q_data->height;
d_size = d_width * d_height;
p_in = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
p_out = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
if (!p_in || !p_out) {
v4l2_err(&pcdev->v4l2_dev,
"Acquiring kernel pointers to buffers failed\n");
return;
}
/* Input frame parameters */
writel(p_in, pcdev->base_emma + PRP_SOURCE_Y_PTR);
writel(PRP_SIZE_WIDTH(s_width) | PRP_SIZE_HEIGHT(s_height),
pcdev->base_emma + PRP_SRC_FRAME_SIZE);
/* Output frame parameters */
writel(p_out, pcdev->base_emma + PRP_DEST_Y_PTR);
writel(p_out + d_size, pcdev->base_emma + PRP_DEST_CB_PTR);
writel(p_out + d_size + (d_size >> 2),
pcdev->base_emma + PRP_DEST_CR_PTR);
writel(PRP_SIZE_WIDTH(d_width) | PRP_SIZE_HEIGHT(d_height),
pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
/* IRQ configuration */
tmp = readl(pcdev->base_emma + PRP_INTR_CNTL);
writel(tmp | PRP_INTR_RDERR |
PRP_INTR_CH2WERR |
PRP_INTR_CH2FC,
pcdev->base_emma + PRP_INTR_CNTL);
emmaprp_dump_regs(pcdev);
/* Enable transfer */
tmp = readl(pcdev->base_emma + PRP_CNTL);
writel(tmp | PRP_CNTL_CH2_OUT_YUV420 |
PRP_CNTL_DATA_IN_YUV422 |
PRP_CNTL_CH2EN,
pcdev->base_emma + PRP_CNTL);
}
static irqreturn_t emmaprp_irq(int irq_emma, void *data)
{
struct emmaprp_dev *pcdev = data;
struct emmaprp_ctx *curr_ctx;
struct vb2_v4l2_buffer *src_vb, *dst_vb;
unsigned long flags;
u32 irqst;
/* Check irq flags and clear irq */
irqst = readl(pcdev->base_emma + PRP_INTRSTATUS);
writel(irqst, pcdev->base_emma + PRP_INTRSTATUS);
dprintk(pcdev, "irqst = 0x%08x\n", irqst);
curr_ctx = v4l2_m2m_get_curr_priv(pcdev->m2m_dev);
if (curr_ctx == NULL) {
pr_err("Instance released before the end of transaction\n");
return IRQ_HANDLED;
}
if (!curr_ctx->aborting) {
if ((irqst & PRP_INTR_ST_RDERR) ||
(irqst & PRP_INTR_ST_CH2WERR)) {
pr_err("PrP bus error occurred, this transfer is probably corrupted\n");
writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
} else if (irqst & PRP_INTR_ST_CH2B1CI) { /* buffer ready */
src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp;
dst_vb->flags &=
~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
dst_vb->flags |=
src_vb->flags
& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
dst_vb->timecode = src_vb->timecode;
spin_lock_irqsave(&pcdev->irqlock, flags);
v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
spin_unlock_irqrestore(&pcdev->irqlock, flags);
}
}
v4l2_m2m_job_finish(pcdev->m2m_dev, curr_ctx->fh.m2m_ctx);
return IRQ_HANDLED;
}
/*
* video ioctls
*/
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
return 0;
}
static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
{
int i, num;
struct emmaprp_fmt *fmt;
num = 0;
for (i = 0; i < NUM_FORMATS; ++i) {
if (formats[i].types & type) {
/* index-th format of type type found ? */
if (num == f->index)
break;
/* Correct type but haven't reached our index yet,
* just increment per-type index */
++num;
}
}
if (i < NUM_FORMATS) {
/* Format found */
fmt = &formats[i];
f->pixelformat = fmt->fourcc;
return 0;
}
/* Format not found */
return -EINVAL;
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return enum_fmt(f, MEM2MEM_CAPTURE);
}
static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return enum_fmt(f, MEM2MEM_OUTPUT);
}
static int vidioc_g_fmt(struct emmaprp_ctx *ctx, struct v4l2_format *f)
{
struct vb2_queue *vq;
struct emmaprp_q_data *q_data;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(ctx, f->type);
f->fmt.pix.width = q_data->width;
f->fmt.pix.height = q_data->height;
f->fmt.pix.field = V4L2_FIELD_NONE;
f->fmt.pix.pixelformat = q_data->fmt->fourcc;
if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
f->fmt.pix.bytesperline = q_data->width * 3 / 2;
else /* YUYV */
f->fmt.pix.bytesperline = q_data->width * 2;
f->fmt.pix.sizeimage = q_data->sizeimage;
return 0;
}
static int vidioc_g_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
return vidioc_g_fmt(priv, f);
}
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
return vidioc_g_fmt(priv, f);
}
static int vidioc_try_fmt(struct v4l2_format *f)
{
enum v4l2_field field;
if (!find_format(f))
return -EINVAL;
field = f->fmt.pix.field;
if (field == V4L2_FIELD_ANY)
field = V4L2_FIELD_NONE;
else if (V4L2_FIELD_NONE != field)
return -EINVAL;
/* V4L2 specification suggests the driver corrects the format struct
* if any of the dimensions is unsupported */
f->fmt.pix.field = field;
if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
W_ALIGN_YUV420, &f->fmt.pix.height,
MIN_H, MAX_H, H_ALIGN, S_ALIGN);
f->fmt.pix.bytesperline = f->fmt.pix.width * 3 / 2;
} else {
v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
W_ALIGN_OTHERS, &f->fmt.pix.height,
MIN_H, MAX_H, H_ALIGN, S_ALIGN);
f->fmt.pix.bytesperline = f->fmt.pix.width * 2;
}
f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct emmaprp_fmt *fmt;
struct emmaprp_ctx *ctx = priv;
fmt = find_format(f);
if (!fmt || !(fmt->types & MEM2MEM_CAPTURE)) {
v4l2_err(&ctx->dev->v4l2_dev,
"Fourcc format (0x%08x) invalid.\n",
f->fmt.pix.pixelformat);
return -EINVAL;
}
return vidioc_try_fmt(f);
}
static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct emmaprp_fmt *fmt;
struct emmaprp_ctx *ctx = priv;
fmt = find_format(f);
if (!fmt || !(fmt->types & MEM2MEM_OUTPUT)) {
v4l2_err(&ctx->dev->v4l2_dev,
"Fourcc format (0x%08x) invalid.\n",
f->fmt.pix.pixelformat);
return -EINVAL;
}
return vidioc_try_fmt(f);
}
static int vidioc_s_fmt(struct emmaprp_ctx *ctx, struct v4l2_format *f)
{
struct emmaprp_q_data *q_data;
struct vb2_queue *vq;
int ret;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(ctx, f->type);
if (!q_data)
return -EINVAL;
if (vb2_is_busy(vq)) {
v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
return -EBUSY;
}
ret = vidioc_try_fmt(f);
if (ret)
return ret;
q_data->fmt = find_format(f);
q_data->width = f->fmt.pix.width;
q_data->height = f->fmt.pix.height;
if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420)
q_data->sizeimage = q_data->width * q_data->height * 3 / 2;
else /* YUYV */
q_data->sizeimage = q_data->width * q_data->height * 2;
dprintk(ctx->dev,
"Setting format for type %d, wxh: %dx%d, fmt: %d\n",
f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
int ret;
ret = vidioc_try_fmt_vid_cap(file, priv, f);
if (ret)
return ret;
return vidioc_s_fmt(priv, f);
}
static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
int ret;
ret = vidioc_try_fmt_vid_out(file, priv, f);
if (ret)
return ret;
return vidioc_s_fmt(priv, f);
}
static const struct v4l2_ioctl_ops emmaprp_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
.vidioc_g_fmt_vid_out = vidioc_g_fmt_vid_out,
.vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
.vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
};
/*
* Queue operations
*/
static int emmaprp_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct emmaprp_ctx *ctx = vb2_get_drv_priv(vq);
struct emmaprp_q_data *q_data;
unsigned int size, count = *nbuffers;
q_data = get_q_data(ctx, vq->type);
if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420)
size = q_data->width * q_data->height * 3 / 2;
else
size = q_data->width * q_data->height * 2;
while (size * count > MEM2MEM_VID_MEM_LIMIT)
(count)--;
*nplanes = 1;
*nbuffers = count;
sizes[0] = size;
dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
return 0;
}
static int emmaprp_buf_prepare(struct vb2_buffer *vb)
{
struct emmaprp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct emmaprp_q_data *q_data;
dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
q_data = get_q_data(ctx, vb->vb2_queue->type);
if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
dprintk(ctx->dev,
"%s data will not fit into plane(%lu < %lu)\n",
__func__, vb2_plane_size(vb, 0),
(long)q_data->sizeimage);
return -EINVAL;
}
vb2_set_plane_payload(vb, 0, q_data->sizeimage);
return 0;
}
static void emmaprp_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct emmaprp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static const struct vb2_ops emmaprp_qops = {
.queue_setup = emmaprp_queue_setup,
.buf_prepare = emmaprp_buf_prepare,
.buf_queue = emmaprp_buf_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct emmaprp_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->ops = &emmaprp_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->dev = ctx->dev->v4l2_dev.dev;
src_vq->lock = &ctx->dev->dev_mutex;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->ops = &emmaprp_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->dev = ctx->dev->v4l2_dev.dev;
dst_vq->lock = &ctx->dev->dev_mutex;
return vb2_queue_init(dst_vq);
}
/*
* File operations
*/
static int emmaprp_open(struct file *file)
{
struct emmaprp_dev *pcdev = video_drvdata(file);
struct emmaprp_ctx *ctx;
ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
if (!ctx)
return -ENOMEM;
v4l2_fh_init(&ctx->fh, video_devdata(file));
file->private_data = &ctx->fh;
ctx->dev = pcdev;
if (mutex_lock_interruptible(&pcdev->dev_mutex)) {
kfree(ctx);
return -ERESTARTSYS;
}
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(pcdev->m2m_dev, ctx, &queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
int ret = PTR_ERR(ctx->fh.m2m_ctx);
mutex_unlock(&pcdev->dev_mutex);
kfree(ctx);
return ret;
}
clk_prepare_enable(pcdev->clk_emma_ipg);
clk_prepare_enable(pcdev->clk_emma_ahb);
ctx->q_data[V4L2_M2M_SRC].fmt = &formats[1];
ctx->q_data[V4L2_M2M_DST].fmt = &formats[0];
v4l2_fh_add(&ctx->fh);
mutex_unlock(&pcdev->dev_mutex);
dprintk(pcdev, "Created instance %p, m2m_ctx: %p\n", ctx, ctx->fh.m2m_ctx);
return 0;
}
static int emmaprp_release(struct file *file)
{
struct emmaprp_dev *pcdev = video_drvdata(file);
struct emmaprp_ctx *ctx = file->private_data;
dprintk(pcdev, "Releasing instance %p\n", ctx);
mutex_lock(&pcdev->dev_mutex);
clk_disable_unprepare(pcdev->clk_emma_ahb);
clk_disable_unprepare(pcdev->clk_emma_ipg);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
mutex_unlock(&pcdev->dev_mutex);
kfree(ctx);
return 0;
}
static const struct v4l2_file_operations emmaprp_fops = {
.owner = THIS_MODULE,
.open = emmaprp_open,
.release = emmaprp_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct video_device emmaprp_videodev = {
.name = MEM2MEM_NAME,
.fops = &emmaprp_fops,
.ioctl_ops = &emmaprp_ioctl_ops,
.minor = -1,
.release = video_device_release,
.vfl_dir = VFL_DIR_M2M,
.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
};
static const struct v4l2_m2m_ops m2m_ops = {
.device_run = emmaprp_device_run,
.job_abort = emmaprp_job_abort,
};
static int emmaprp_probe(struct platform_device *pdev)
{
struct emmaprp_dev *pcdev;
struct video_device *vfd;
int irq, ret;
pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
if (!pcdev)
return -ENOMEM;
spin_lock_init(&pcdev->irqlock);
pcdev->clk_emma_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(pcdev->clk_emma_ipg)) {
return PTR_ERR(pcdev->clk_emma_ipg);
}
pcdev->clk_emma_ahb = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(pcdev->clk_emma_ahb))
return PTR_ERR(pcdev->clk_emma_ahb);
pcdev->base_emma = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pcdev->base_emma))
return PTR_ERR(pcdev->base_emma);
ret = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
if (ret)
return ret;
mutex_init(&pcdev->dev_mutex);
vfd = video_device_alloc();
if (!vfd) {
v4l2_err(&pcdev->v4l2_dev, "Failed to allocate video device\n");
ret = -ENOMEM;
goto unreg_dev;
}
*vfd = emmaprp_videodev;
vfd->lock = &pcdev->dev_mutex;
vfd->v4l2_dev = &pcdev->v4l2_dev;
video_set_drvdata(vfd, pcdev);
pcdev->vfd = vfd;
v4l2_info(&pcdev->v4l2_dev, EMMAPRP_MODULE_NAME
" Device registered as /dev/video%d\n", vfd->num);
platform_set_drvdata(pdev, pcdev);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto rel_vdev;
}
ret = devm_request_irq(&pdev->dev, irq, emmaprp_irq, 0,
dev_name(&pdev->dev), pcdev);
if (ret)
goto rel_vdev;
pcdev->m2m_dev = v4l2_m2m_init(&m2m_ops);
if (IS_ERR(pcdev->m2m_dev)) {
v4l2_err(&pcdev->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(pcdev->m2m_dev);
goto rel_vdev;
}
ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
if (ret) {
v4l2_err(&pcdev->v4l2_dev, "Failed to register video device\n");
goto rel_m2m;
}
return 0;
rel_m2m:
v4l2_m2m_release(pcdev->m2m_dev);
rel_vdev:
video_device_release(vfd);
unreg_dev:
v4l2_device_unregister(&pcdev->v4l2_dev);
mutex_destroy(&pcdev->dev_mutex);
return ret;
}
static void emmaprp_remove(struct platform_device *pdev)
{
struct emmaprp_dev *pcdev = platform_get_drvdata(pdev);
v4l2_info(&pcdev->v4l2_dev, "Removing " EMMAPRP_MODULE_NAME);
video_unregister_device(pcdev->vfd);
v4l2_m2m_release(pcdev->m2m_dev);
v4l2_device_unregister(&pcdev->v4l2_dev);
mutex_destroy(&pcdev->dev_mutex);
}
static struct platform_driver emmaprp_pdrv = {
.probe = emmaprp_probe,
.remove_new = emmaprp_remove,
.driver = {
.name = MEM2MEM_NAME,
},
};
module_platform_driver(emmaprp_pdrv);
| linux-master | drivers/media/platform/nxp/mx2_emmaprp.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
*
* Copyright (c) 2018 Pengutronix, Philipp Zabel
*
* based on vim2m
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <[email protected]>
* Marek Szyprowski, <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <media/media-device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-contig.h>
#include "imx-pxp.h"
static unsigned int debug;
module_param(debug, uint, 0644);
MODULE_PARM_DESC(debug, "activates debug info");
#define MIN_W 8
#define MIN_H 8
#define MAX_W 4096
#define MAX_H 4096
#define ALIGN_W 3 /* 8x8 pixel blocks */
#define ALIGN_H 3
/* Flags that indicate a format can be used for capture/output */
#define MEM2MEM_CAPTURE (1 << 0)
#define MEM2MEM_OUTPUT (1 << 1)
#define MEM2MEM_NAME "pxp"
/* Flags that indicate processing mode */
#define MEM2MEM_HFLIP (1 << 0)
#define MEM2MEM_VFLIP (1 << 1)
#define PXP_VERSION_MAJOR(version) \
FIELD_GET(BM_PXP_VERSION_MAJOR, version)
#define PXP_VERSION_MINOR(version) \
FIELD_GET(BM_PXP_VERSION_MINOR, version)
#define dprintk(dev, fmt, arg...) \
v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
struct pxp_fmt {
u32 fourcc;
int depth;
/* Types the format can be used for */
u32 types;
};
static struct pxp_fmt formats[] = {
{
.fourcc = V4L2_PIX_FMT_XBGR32,
.depth = 32,
/* Both capture and output format */
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_ABGR32,
.depth = 32,
/* Capture-only format */
.types = MEM2MEM_CAPTURE,
}, {
.fourcc = V4L2_PIX_FMT_BGR24,
.depth = 24,
.types = MEM2MEM_CAPTURE,
}, {
.fourcc = V4L2_PIX_FMT_RGB565,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_RGB555,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_RGB444,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_VUYA32,
.depth = 32,
.types = MEM2MEM_CAPTURE,
}, {
.fourcc = V4L2_PIX_FMT_VUYX32,
.depth = 32,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.depth = 16,
/* Output-only format */
.types = MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_VYUY,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_YVYU,
.depth = 16,
.types = MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_GREY,
.depth = 8,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_Y4,
.depth = 4,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.depth = 12,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_NV21,
.depth = 12,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_NV61,
.depth = 16,
.types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.depth = 16,
.types = MEM2MEM_OUTPUT,
}, {
.fourcc = V4L2_PIX_FMT_YUV420,
.depth = 12,
.types = MEM2MEM_OUTPUT,
},
};
#define NUM_FORMATS ARRAY_SIZE(formats)
/* Per-queue, driver-specific private data */
struct pxp_q_data {
unsigned int width;
unsigned int height;
unsigned int bytesperline;
unsigned int sizeimage;
unsigned int sequence;
struct pxp_fmt *fmt;
enum v4l2_ycbcr_encoding ycbcr_enc;
enum v4l2_quantization quant;
};
enum {
V4L2_M2M_SRC = 0,
V4L2_M2M_DST = 1,
};
static const struct regmap_config pxp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = HW_PXP_VERSION,
};
static struct pxp_fmt *find_format(unsigned int pixelformat)
{
struct pxp_fmt *fmt;
unsigned int k;
for (k = 0; k < NUM_FORMATS; k++) {
fmt = &formats[k];
if (fmt->fourcc == pixelformat)
break;
}
if (k == NUM_FORMATS)
return NULL;
return &formats[k];
}
struct pxp_ctx;
struct pxp_pdata {
u32 (*data_path_ctrl0)(struct pxp_ctx *ctx);
};
struct pxp_dev {
struct v4l2_device v4l2_dev;
struct video_device vfd;
#ifdef CONFIG_MEDIA_CONTROLLER
struct media_device mdev;
#endif
struct clk *clk;
struct regmap *regmap;
const struct pxp_pdata *pdata;
atomic_t num_inst;
struct mutex dev_mutex;
spinlock_t irqlock;
struct v4l2_m2m_dev *m2m_dev;
};
struct pxp_ctx {
struct v4l2_fh fh;
struct pxp_dev *dev;
struct v4l2_ctrl_handler hdl;
/* Abort requested by m2m */
int aborting;
/* Processing mode */
int mode;
u8 alpha_component;
u8 rotation;
enum v4l2_colorspace colorspace;
enum v4l2_xfer_func xfer_func;
/* Source and destination queue data */
struct pxp_q_data q_data[2];
};
static inline struct pxp_ctx *file2ctx(struct file *file)
{
return container_of(file->private_data, struct pxp_ctx, fh);
}
static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
enum v4l2_buf_type type)
{
if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
return &ctx->q_data[V4L2_M2M_SRC];
else
return &ctx->q_data[V4L2_M2M_DST];
}
static inline u32 pxp_read(struct pxp_dev *dev, u32 reg)
{
u32 value;
regmap_read(dev->regmap, reg, &value);
return value;
}
static inline void pxp_write(struct pxp_dev *dev, u32 reg, u32 value)
{
regmap_write(dev->regmap, reg, value);
}
static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
{
switch (v4l2_pix_fmt) {
case V4L2_PIX_FMT_XBGR32: return BV_PXP_PS_CTRL_FORMAT__RGB888;
case V4L2_PIX_FMT_RGB555: return BV_PXP_PS_CTRL_FORMAT__RGB555;
case V4L2_PIX_FMT_RGB444: return BV_PXP_PS_CTRL_FORMAT__RGB444;
case V4L2_PIX_FMT_RGB565: return BV_PXP_PS_CTRL_FORMAT__RGB565;
case V4L2_PIX_FMT_VUYX32: return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
case V4L2_PIX_FMT_UYVY: return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
case V4L2_PIX_FMT_YUYV: return BM_PXP_PS_CTRL_WB_SWAP |
BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
case V4L2_PIX_FMT_VYUY: return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
case V4L2_PIX_FMT_YVYU: return BM_PXP_PS_CTRL_WB_SWAP |
BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
case V4L2_PIX_FMT_GREY: return BV_PXP_PS_CTRL_FORMAT__Y8;
default:
case V4L2_PIX_FMT_Y4: return BV_PXP_PS_CTRL_FORMAT__Y4;
case V4L2_PIX_FMT_NV16: return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
case V4L2_PIX_FMT_NV12: return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
case V4L2_PIX_FMT_NV21: return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
case V4L2_PIX_FMT_NV61: return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
case V4L2_PIX_FMT_YUV420: return BV_PXP_PS_CTRL_FORMAT__YUV420;
}
}
static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
{
switch (v4l2_pix_fmt) {
case V4L2_PIX_FMT_XBGR32: return BV_PXP_OUT_CTRL_FORMAT__RGB888;
case V4L2_PIX_FMT_ABGR32: return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
case V4L2_PIX_FMT_BGR24: return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
/* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
case V4L2_PIX_FMT_RGB555: return BV_PXP_OUT_CTRL_FORMAT__RGB555;
case V4L2_PIX_FMT_RGB444: return BV_PXP_OUT_CTRL_FORMAT__RGB444;
case V4L2_PIX_FMT_RGB565: return BV_PXP_OUT_CTRL_FORMAT__RGB565;
case V4L2_PIX_FMT_VUYA32:
case V4L2_PIX_FMT_VUYX32: return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
case V4L2_PIX_FMT_UYVY: return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
case V4L2_PIX_FMT_VYUY: return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
case V4L2_PIX_FMT_GREY: return BV_PXP_OUT_CTRL_FORMAT__Y8;
default:
case V4L2_PIX_FMT_Y4: return BV_PXP_OUT_CTRL_FORMAT__Y4;
case V4L2_PIX_FMT_NV16: return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
case V4L2_PIX_FMT_NV12: return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
case V4L2_PIX_FMT_NV61: return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
case V4L2_PIX_FMT_NV21: return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
}
}
static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
{
switch (v4l2_pix_fmt) {
case V4L2_PIX_FMT_VUYA32:
case V4L2_PIX_FMT_VUYX32:
case V4L2_PIX_FMT_UYVY:
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_VYUY:
case V4L2_PIX_FMT_YVYU:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV61:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_YUV420:
case V4L2_PIX_FMT_YUV422P:
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y4:
return true;
default:
return false;
}
}
static void pxp_setup_csc(struct pxp_ctx *ctx)
{
struct pxp_dev *dev = ctx->dev;
enum v4l2_ycbcr_encoding ycbcr_enc;
enum v4l2_quantization quantization;
if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
/*
* CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
*
* |R| |C0 0 C1| |Y + Yoffset |
* |G| = |C0 C3 C2| * |Cb + UVoffset|
* |B| |C0 C4 0 | |Cr + UVoffset|
*
* Results are clamped to 0..255.
*
* BT.601 limited range:
*
* |R| |1.1644 0.0000 1.5960| |Y - 16 |
* |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
* |B| |1.1644 2.0172 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_bt601_lim[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
BF_PXP_CSC1_COEF1_C1(0x198) | /* 1.5938 (-0.23 %) */
BF_PXP_CSC1_COEF1_C4(0x204), /* 2.0156 (-0.16 %) */
BF_PXP_CSC1_COEF2_C2(0x730) | /* -0.8125 (+0.04 %) */
BF_PXP_CSC1_COEF2_C3(0x79c), /* -0.3906 (+0.11 %) */
};
/*
* BT.601 full range:
*
* |R| |1.0000 0.0000 1.4020| |Y + 0 |
* |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
* |B| |1.0000 1.7720 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_bt601_full[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(0),
BF_PXP_CSC1_COEF1_C1(0x166) | /* 1.3984 (-0.36 %) */
BF_PXP_CSC1_COEF1_C4(0x1c5), /* 1.7695 (-0.25 %) */
BF_PXP_CSC1_COEF2_C2(0x74a) | /* -0.7109 (+0.32 %) */
BF_PXP_CSC1_COEF2_C3(0x7a8), /* -0.3438 (+0.04 %) */
};
/*
* Rec.709 limited range:
*
* |R| |1.1644 0.0000 1.7927| |Y - 16 |
* |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
* |B| |1.1644 2.1124 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_rec709_lim[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
BF_PXP_CSC1_COEF1_C1(0x1ca) | /* 1.7891 (-0.37 %) */
BF_PXP_CSC1_COEF1_C4(0x21c), /* 2.1094 (-0.30 %) */
BF_PXP_CSC1_COEF2_C2(0x778) | /* -0.5312 (+0.16 %) */
BF_PXP_CSC1_COEF2_C3(0x7ca), /* -0.2109 (+0.23 %) */
};
/*
* Rec.709 full range:
*
* |R| |1.0000 0.0000 1.5748| |Y + 0 |
* |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
* |B| |1.0000 1.8556 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_rec709_full[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(0),
BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.06 %) */
BF_PXP_CSC1_COEF1_C4(0x1db), /* 1.8555 (-0.01 %) */
BF_PXP_CSC1_COEF2_C2(0x789) | /* -0.4648 (+0.33 %) */
BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.37 %) */
};
/*
* BT.2020 limited range:
*
* |R| |1.1644 0.0000 1.6787| |Y - 16 |
* |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
* |B| |1.1644 2.1418 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_bt2020_lim[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
BF_PXP_CSC1_COEF1_C1(0x1ad) | /* 1.6758 (-0.29 %) */
BF_PXP_CSC1_COEF1_C4(0x224), /* 2.1406 (-0.11 %) */
BF_PXP_CSC1_COEF2_C2(0x75a) | /* -0.6484 (+0.20 %) */
BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.38 %) */
};
/*
* BT.2020 full range:
*
* |R| |1.0000 0.0000 1.4746| |Y + 0 |
* |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
* |B| |1.0000 1.8814 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_bt2020_full[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(0),
BF_PXP_CSC1_COEF1_C1(0x179) | /* 1.4727 (-0.19 %) */
BF_PXP_CSC1_COEF1_C4(0x1e1), /* 1.8789 (-0.25 %) */
BF_PXP_CSC1_COEF2_C2(0x76e) | /* -0.5703 (+0.11 %) */
BF_PXP_CSC1_COEF2_C3(0x7d6), /* -0.1641 (+0.05 %) */
};
/*
* SMPTE 240m limited range:
*
* |R| |1.1644 0.0000 1.7937| |Y - 16 |
* |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
* |B| |1.1644 2.0798 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_smpte240m_lim[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
BF_PXP_CSC1_COEF1_C1(0x1cb) | /* 1.7930 (-0.07 %) */
BF_PXP_CSC1_COEF1_C4(0x214), /* 2.0781 (-0.17 %) */
BF_PXP_CSC1_COEF2_C2(0x776) | /* -0.5391 (+0.36 %) */
BF_PXP_CSC1_COEF2_C3(0x7bf), /* -0.2539 (+0.26 %) */
};
/*
* SMPTE 240m full range:
*
* |R| |1.0000 0.0000 1.5756| |Y + 0 |
* |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
* |B| |1.0000 1.8270 0.0000| |Cr - 128|
*/
static const u32 csc1_coef_smpte240m_full[3] = {
BM_PXP_CSC1_COEF0_YCBCR_MODE |
BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
BF_PXP_CSC1_COEF0_Y_OFFSET(0),
BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.14 %) */
BF_PXP_CSC1_COEF1_C4(0x1d3), /* 1.8242 (-0.28 %) */
BF_PXP_CSC1_COEF2_C2(0x786) | /* -0.4766 (+0.01 %) */
BF_PXP_CSC1_COEF2_C3(0x7c7), /* -0.2227 (+0.26 %) */
};
const u32 *csc1_coef;
ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
quantization = ctx->q_data[V4L2_M2M_SRC].quant;
if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc1_coef = csc1_coef_bt601_full;
else
csc1_coef = csc1_coef_bt601_lim;
} else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc1_coef = csc1_coef_rec709_full;
else
csc1_coef = csc1_coef_rec709_lim;
} else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc1_coef = csc1_coef_bt2020_full;
else
csc1_coef = csc1_coef_bt2020_lim;
} else {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc1_coef = csc1_coef_smpte240m_full;
else
csc1_coef = csc1_coef_smpte240m_lim;
}
pxp_write(dev, HW_PXP_CSC1_COEF0, csc1_coef[0]);
pxp_write(dev, HW_PXP_CSC1_COEF1, csc1_coef[1]);
pxp_write(dev, HW_PXP_CSC1_COEF2, csc1_coef[2]);
} else {
pxp_write(dev, HW_PXP_CSC1_COEF0, BM_PXP_CSC1_COEF0_BYPASS);
}
if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
/*
* CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
*
* |Y | |A1 A2 A3| |R| |D1|
* |Cb| = |B1 B2 B3| * |G| + |D2|
* |Cr| |C1 C2 C3| |B| |D3|
*
* Results are clamped to 0..255.
*
* BT.601 limited range:
*
* |Y | | 0.2568 0.5041 0.0979| |R| |16 |
* |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
* |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
*/
static const u32 csc2_coef_bt601_lim[6] = {
BF_PXP_CSC2_COEF0_A2(0x081) | /* 0.5039 (-0.02 %) */
BF_PXP_CSC2_COEF0_A1(0x041), /* 0.2539 (-0.29 %) */
BF_PXP_CSC2_COEF1_B1(0x7db) | /* -0.1445 (+0.37 %) */
BF_PXP_CSC2_COEF1_A3(0x019), /* 0.0977 (-0.02 %) */
BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF2_B2(0x7b6), /* -0.2891 (+0.20 %) */
BF_PXP_CSC2_COEF3_C2(0x7a2) | /* -0.3672 (+0.06 %) */
BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF4_D1(16) |
BF_PXP_CSC2_COEF4_C3(0x7ee), /* -0.0703 (+0.11 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* BT.601 full range:
*
* |Y | | 0.2990 0.5870 0.1140| |R| |0 |
* |Cb| = |-0.1687 -0.3313 0.5000| * |G| + |128|
* |Cr| | 0.5000 0.5000 -0.4187| |B| |128|
*/
static const u32 csc2_coef_bt601_full[6] = {
BF_PXP_CSC2_COEF0_A2(0x096) | /* 0.5859 (-0.11 %) */
BF_PXP_CSC2_COEF0_A1(0x04c), /* 0.2969 (-0.21 %) */
BF_PXP_CSC2_COEF1_B1(0x7d5) | /* -0.1680 (+0.07 %) */
BF_PXP_CSC2_COEF1_A3(0x01d), /* 0.1133 (-0.07 %) */
BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF2_B2(0x7ac), /* -0.3281 (+0.32 %) */
BF_PXP_CSC2_COEF3_C2(0x795) | /* -0.4180 (+0.07 %) */
BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF4_D1(0) |
BF_PXP_CSC2_COEF4_C3(0x7ec), /* -0.0781 (+0.32 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* Rec.709 limited range:
*
* |Y | | 0.1826 0.6142 0.0620| |R| |16 |
* |Cb| = |-0.1007 -0.3385 0.4392| * |G| + |128|
* |Cr| | 0.4392 0.4392 -0.3990| |B| |128|
*/
static const u32 csc2_coef_rec709_lim[6] = {
BF_PXP_CSC2_COEF0_A2(0x09d) | /* 0.6133 (-0.09 %) */
BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.29 %) */
BF_PXP_CSC2_COEF1_B1(0x7e7) | /* -0.0977 (+0.30 %) */
BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.34 %) */
BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.26 %) */
BF_PXP_CSC2_COEF3_C2(0x79a) | /* -0.3984 (+0.05 %) */
BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF4_D1(16) |
BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.12 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* Rec.709 full range:
*
* |Y | | 0.2126 0.7152 0.0722| |R| |0 |
* |Cb| = |-0.1146 -0.3854 0.5000| * |G| + |128|
* |Cr| | 0.5000 0.5000 -0.4542| |B| |128|
*/
static const u32 csc2_coef_rec709_full[6] = {
BF_PXP_CSC2_COEF0_A2(0x0b7) | /* 0.7148 (-0.04 %) */
BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.17 %) */
BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.13 %) */
BF_PXP_CSC2_COEF1_A3(0x012), /* 0.0703 (-0.19 %) */
BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.26 %) */
BF_PXP_CSC2_COEF3_C2(0x78c) | /* -0.4531 (+0.11 %) */
BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF4_D1(0) |
BF_PXP_CSC2_COEF4_C3(0x7f5), /* -0.0430 (+0.28 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* BT.2020 limited range:
*
* |Y | | 0.2256 0.5823 0.0509| |R| |16 |
* |Cb| = |-0.1226 -0.3166 0.4392| * |G| + |128|
* |Cr| | 0.4392 0.4392 -0.4039| |B| |128|
*/
static const u32 csc2_coef_bt2020_lim[6] = {
BF_PXP_CSC2_COEF0_A2(0x095) | /* 0.5820 (-0.03 %) */
BF_PXP_CSC2_COEF0_A1(0x039), /* 0.2227 (-0.30 %) */
BF_PXP_CSC2_COEF1_B1(0x7e1) | /* -0.1211 (+0.15 %) */
BF_PXP_CSC2_COEF1_A3(0x00d), /* 0.0508 (-0.01 %) */
BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF2_B2(0x7af), /* -0.3164 (+0.02 %) */
BF_PXP_CSC2_COEF3_C2(0x799) | /* -0.4023 (+0.16 %) */
BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF4_D1(16) |
BF_PXP_CSC2_COEF4_C3(0x7f7), /* -0.0352 (+0.02 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* BT.2020 full range:
*
* |Y | | 0.2627 0.6780 0.0593| |R| |0 |
* |Cb| = |-0.1396 -0.3604 0.5000| * |G| + |128|
* |Cr| | 0.5000 0.5000 -0.4598| |B| |128|
*/
static const u32 csc2_coef_bt2020_full[6] = {
BF_PXP_CSC2_COEF0_A2(0x0ad) | /* 0.6758 (-0.22 %) */
BF_PXP_CSC2_COEF0_A1(0x043), /* 0.2617 (-0.10 %) */
BF_PXP_CSC2_COEF1_B1(0x7dd) | /* -0.1367 (+0.29 %) */
BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.07 %) */
BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF2_B2(0x7a4), /* -0.3594 (+0.10 %) */
BF_PXP_CSC2_COEF3_C2(0x78b) | /* -0.4570 (+0.28 %) */
BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF4_D1(0) |
BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.11 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* SMPTE 240m limited range:
*
* |Y | | 0.1821 0.6020 0.0747| |R| |16 |
* |Cb| = |-0.1019 -0.3373 0.4392| * |G| + |128|
* |Cr| | 0.4392 0.4392 -0.3909| |B| |128|
*/
static const u32 csc2_coef_smpte240m_lim[6] = {
BF_PXP_CSC2_COEF0_A2(0x09a) | /* 0.6016 (-0.05 %) */
BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.24 %) */
BF_PXP_CSC2_COEF1_B1(0x7e6) | /* -0.1016 (+0.03 %) */
BF_PXP_CSC2_COEF1_A3(0x013), /* 0.0742 (-0.05 %) */
BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.14 %) */
BF_PXP_CSC2_COEF3_C2(0x79c) | /* -0.3906 (+0.03 %) */
BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
BF_PXP_CSC2_COEF4_D1(16) |
BF_PXP_CSC2_COEF4_C3(0x7f4), /* -0.0469 (+0.14 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
/*
* SMPTE 240m full range:
*
* |Y | | 0.2120 0.7010 0.0870| |R| |0 |
* |Cb| = |-0.1160 -0.3840 0.5000| * |G| + |128|
* |Cr| | 0.5000 0.5000 -0.4450| |B| |128|
*/
static const u32 csc2_coef_smpte240m_full[6] = {
BF_PXP_CSC2_COEF0_A2(0x0b3) | /* 0.6992 (-0.18 %) */
BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.11 %) */
BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.27 %) */
BF_PXP_CSC2_COEF1_A3(0x016), /* 0.0859 (-0.11 %) */
BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.12 %) */
BF_PXP_CSC2_COEF3_C2(0x78f) | /* -0.4414 (+0.36 %) */
BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
BF_PXP_CSC2_COEF4_D1(0) |
BF_PXP_CSC2_COEF4_C3(0x7f2), /* -0.0547 (+0.03 %) */
BF_PXP_CSC2_COEF5_D3(128) |
BF_PXP_CSC2_COEF5_D2(128),
};
const u32 *csc2_coef;
u32 csc2_ctrl;
ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
quantization = ctx->q_data[V4L2_M2M_DST].quant;
if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc2_coef = csc2_coef_bt601_full;
else
csc2_coef = csc2_coef_bt601_lim;
} else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc2_coef = csc2_coef_rec709_full;
else
csc2_coef = csc2_coef_rec709_lim;
} else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc2_coef = csc2_coef_bt2020_full;
else
csc2_coef = csc2_coef_bt2020_lim;
} else {
if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
csc2_coef = csc2_coef_smpte240m_full;
else
csc2_coef = csc2_coef_smpte240m_lim;
}
if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
BP_PXP_CSC2_CTRL_CSC_MODE;
} else {
csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
BP_PXP_CSC2_CTRL_CSC_MODE;
}
pxp_write(dev, HW_PXP_CSC2_CTRL, csc2_ctrl);
pxp_write(dev, HW_PXP_CSC2_COEF0, csc2_coef[0]);
pxp_write(dev, HW_PXP_CSC2_COEF1, csc2_coef[1]);
pxp_write(dev, HW_PXP_CSC2_COEF2, csc2_coef[2]);
pxp_write(dev, HW_PXP_CSC2_COEF3, csc2_coef[3]);
pxp_write(dev, HW_PXP_CSC2_COEF4, csc2_coef[4]);
pxp_write(dev, HW_PXP_CSC2_COEF5, csc2_coef[5]);
} else {
pxp_write(dev, HW_PXP_CSC2_CTRL, BM_PXP_CSC2_CTRL_BYPASS);
}
}
static u32 pxp_imx6ull_data_path_ctrl0(struct pxp_ctx *ctx)
{
u32 ctrl0;
ctrl0 = 0;
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(3);
/* Bypass Dithering x3CH */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(3);
/* Select Rotation */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0);
/* Bypass LUT */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(1);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(3);
/* Select CSC 2 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(3);
/* Bypass Rotation 2 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(3);
return ctrl0;
}
static u32 pxp_imx7d_data_path_ctrl0(struct pxp_ctx *ctx)
{
u32 ctrl0;
ctrl0 = 0;
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(3);
/* Select Rotation 0 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(0);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(3);
/* Select MUX11 for Rotation 0 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(1);
/* Bypass LUT */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(1);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(3);
/* Select CSC 2 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(3);
/* Select Composite Alpha Blending/Color Key 0 for CSC 2 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(1);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(3);
/* Bypass Rotation 1 */
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(3);
ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(3);
return ctrl0;
}
static void pxp_set_data_path(struct pxp_ctx *ctx)
{
struct pxp_dev *dev = ctx->dev;
u32 ctrl0;
u32 ctrl1;
ctrl0 = dev->pdata->data_path_ctrl0(ctx);
ctrl1 = 0;
ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(3);
ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(3);
pxp_write(dev, HW_PXP_DATA_PATH_CTRL0, ctrl0);
pxp_write(dev, HW_PXP_DATA_PATH_CTRL1, ctrl1);
}
static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
struct vb2_v4l2_buffer *out_vb)
{
struct pxp_dev *dev = ctx->dev;
struct pxp_q_data *q_data;
u32 src_width, src_height, src_stride, src_fourcc;
u32 dst_width, dst_height, dst_stride, dst_fourcc;
dma_addr_t p_in, p_out;
u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
u32 out_ps_lrc;
u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
u32 as_ulc, as_lrc;
u32 y_size;
u32 decx, decy, xscale, yscale;
q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
src_width = ctx->q_data[V4L2_M2M_SRC].width;
dst_width = ctx->q_data[V4L2_M2M_DST].width;
src_height = ctx->q_data[V4L2_M2M_SRC].height;
dst_height = ctx->q_data[V4L2_M2M_DST].height;
src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
if (!p_in || !p_out) {
v4l2_err(&dev->v4l2_dev,
"Acquiring DMA addresses of buffers failed\n");
return -EFAULT;
}
out_vb->sequence =
get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
in_vb->sequence = q_data->sequence++;
out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
out_vb->timecode = in_vb->timecode;
out_vb->field = in_vb->field;
out_vb->flags = in_vb->flags &
(V4L2_BUF_FLAG_TIMECODE |
V4L2_BUF_FLAG_KEYFRAME |
V4L2_BUF_FLAG_PFRAME |
V4L2_BUF_FLAG_BFRAME |
V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
/* 8x8 block size */
ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP)) |
BF_PXP_CTRL_ROTATE0(ctx->rotation);
/* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
out_buf = p_out;
if (ctx->rotation == BV_PXP_CTRL_ROTATE0__ROT_90 ||
ctx->rotation == BV_PXP_CTRL_ROTATE0__ROT_270)
swap(dst_width, dst_height);
switch (dst_fourcc) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
out_buf2 = out_buf + dst_stride * dst_height;
break;
default:
out_buf2 = 0;
}
out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
BF_PXP_OUT_LRC_Y(dst_height - 1);
/* PS covers whole output */
out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
/* no AS */
as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
ps_buf = p_in;
y_size = src_stride * src_height;
switch (src_fourcc) {
case V4L2_PIX_FMT_YUV420:
ps_ubuf = ps_buf + y_size;
ps_vbuf = ps_ubuf + y_size / 4;
break;
case V4L2_PIX_FMT_YUV422P:
ps_ubuf = ps_buf + y_size;
ps_vbuf = ps_ubuf + y_size / 2;
break;
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
ps_ubuf = ps_buf + y_size;
ps_vbuf = 0;
break;
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y4:
ps_ubuf = 0;
/* In grayscale mode, ps_vbuf contents are reused as CbCr */
ps_vbuf = 0x8080;
break;
default:
ps_ubuf = 0;
ps_vbuf = 0;
break;
}
ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
if (decx) {
xscale = (src_width >> decx) * 0x1000 / dst_width;
} else {
switch (src_fourcc) {
case V4L2_PIX_FMT_UYVY:
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_VYUY:
case V4L2_PIX_FMT_YVYU:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_NV61:
case V4L2_PIX_FMT_YUV422P:
case V4L2_PIX_FMT_YUV420:
/*
* This avoids sampling past the right edge for
* horizontally chroma subsampled formats.
*/
xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
break;
default:
xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
break;
}
}
if (decy)
yscale = (src_height >> decy) * 0x1000 / dst_height;
else
yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
BF_PXP_PS_SCALE_XSCALE(xscale);
ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
pxp_write(dev, HW_PXP_CTRL, ctrl);
/* skip STAT */
pxp_write(dev, HW_PXP_OUT_CTRL, out_ctrl);
pxp_write(dev, HW_PXP_OUT_BUF, out_buf);
pxp_write(dev, HW_PXP_OUT_BUF2, out_buf2);
pxp_write(dev, HW_PXP_OUT_PITCH, out_pitch);
pxp_write(dev, HW_PXP_OUT_LRC, out_lrc);
pxp_write(dev, HW_PXP_OUT_PS_ULC, out_ps_ulc);
pxp_write(dev, HW_PXP_OUT_PS_LRC, out_ps_lrc);
pxp_write(dev, HW_PXP_OUT_AS_ULC, as_ulc);
pxp_write(dev, HW_PXP_OUT_AS_LRC, as_lrc);
pxp_write(dev, HW_PXP_PS_CTRL, ps_ctrl);
pxp_write(dev, HW_PXP_PS_BUF, ps_buf);
pxp_write(dev, HW_PXP_PS_UBUF, ps_ubuf);
pxp_write(dev, HW_PXP_PS_VBUF, ps_vbuf);
pxp_write(dev, HW_PXP_PS_PITCH, ps_pitch);
pxp_write(dev, HW_PXP_PS_BACKGROUND_0, 0x00ffffff);
pxp_write(dev, HW_PXP_PS_SCALE, ps_scale);
pxp_write(dev, HW_PXP_PS_OFFSET, ps_offset);
/* disable processed surface color keying */
pxp_write(dev, HW_PXP_PS_CLRKEYLOW_0, 0x00ffffff);
pxp_write(dev, HW_PXP_PS_CLRKEYHIGH_0, 0x00000000);
/* disable alpha surface color keying */
pxp_write(dev, HW_PXP_AS_CLRKEYLOW_0, 0x00ffffff);
pxp_write(dev, HW_PXP_AS_CLRKEYHIGH_0, 0x00000000);
/* setup CSC */
pxp_setup_csc(ctx);
/* bypass LUT */
pxp_write(dev, HW_PXP_LUT_CTRL, BM_PXP_LUT_CTRL_BYPASS);
pxp_set_data_path(ctx);
pxp_write(dev, HW_PXP_IRQ_MASK, 0xffff);
/* ungate, enable PS/AS/OUT and PXP operation */
pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_IRQ_ENABLE);
pxp_write(dev, HW_PXP_CTRL_SET,
BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
BM_PXP_CTRL_ENABLE_ROTATE0 | BM_PXP_CTRL_ENABLE_PS_AS_OUT);
return 0;
}
static void pxp_job_finish(struct pxp_dev *dev)
{
struct pxp_ctx *curr_ctx;
struct vb2_v4l2_buffer *src_vb, *dst_vb;
unsigned long flags;
curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
if (curr_ctx == NULL) {
pr_err("Instance released before the end of transaction\n");
return;
}
src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
spin_lock_irqsave(&dev->irqlock, flags);
v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
spin_unlock_irqrestore(&dev->irqlock, flags);
dprintk(curr_ctx->dev, "Finishing transaction\n");
v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
}
/*
* mem2mem callbacks
*/
static void pxp_device_run(void *priv)
{
struct pxp_ctx *ctx = priv;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
pxp_start(ctx, src_buf, dst_buf);
}
static int pxp_job_ready(void *priv)
{
struct pxp_ctx *ctx = priv;
if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
dprintk(ctx->dev, "Not enough buffers available\n");
return 0;
}
return 1;
}
static void pxp_job_abort(void *priv)
{
struct pxp_ctx *ctx = priv;
/* Will cancel the transaction in the next interrupt handler */
ctx->aborting = 1;
}
/*
* interrupt handler
*/
static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
{
struct pxp_dev *dev = dev_id;
u32 stat;
stat = pxp_read(dev, HW_PXP_STAT);
if (stat & BM_PXP_STAT_IRQ0) {
/* we expect x = 0, y = height, irq0 = 1 */
if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
BM_PXP_STAT_IRQ0))
dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
pxp_write(dev, HW_PXP_STAT_CLR, BM_PXP_STAT_IRQ0);
pxp_job_finish(dev);
} else {
u32 irq = pxp_read(dev, HW_PXP_IRQ);
dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
pxp_write(dev, HW_PXP_IRQ_CLR, irq);
}
return IRQ_HANDLED;
}
/*
* video ioctls
*/
static int pxp_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
return 0;
}
static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
{
int i, num;
struct pxp_fmt *fmt;
num = 0;
for (i = 0; i < NUM_FORMATS; ++i) {
if (formats[i].types & type) {
/* index-th format of type type found ? */
if (num == f->index)
break;
/*
* Correct type but haven't reached our index yet,
* just increment per-type index
*/
++num;
}
}
if (i < NUM_FORMATS) {
/* Format found */
fmt = &formats[i];
f->pixelformat = fmt->fourcc;
return 0;
}
/* Format not found */
return -EINVAL;
}
static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
}
static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
}
static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
{
struct vb2_queue *vq;
struct pxp_q_data *q_data;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(ctx, f->type);
f->fmt.pix.width = q_data->width;
f->fmt.pix.height = q_data->height;
f->fmt.pix.field = V4L2_FIELD_NONE;
f->fmt.pix.pixelformat = q_data->fmt->fourcc;
f->fmt.pix.bytesperline = q_data->bytesperline;
f->fmt.pix.sizeimage = q_data->sizeimage;
f->fmt.pix.colorspace = ctx->colorspace;
f->fmt.pix.xfer_func = ctx->xfer_func;
f->fmt.pix.ycbcr_enc = q_data->ycbcr_enc;
f->fmt.pix.quantization = q_data->quant;
return 0;
}
static int pxp_g_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
return pxp_g_fmt(file2ctx(file), f);
}
static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
return pxp_g_fmt(file2ctx(file), f);
}
static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
{
switch (fmt->fourcc) {
case V4L2_PIX_FMT_YUV420:
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_YUV422P:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
return width;
default:
return (width * fmt->depth) >> 3;
}
}
static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
{
return (fmt->depth * width * height) >> 3;
}
static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
{
v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
&f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
f->fmt.pix.height);
f->fmt.pix.field = V4L2_FIELD_NONE;
return 0;
}
static void
pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
enum v4l2_ycbcr_encoding *ycbcr_enc,
enum v4l2_quantization *quantization)
{
bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
dst_is_yuv) {
/*
* There is no support for conversion between different YCbCr
* encodings or between RGB limited and full range.
*/
*ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
*quantization = ctx->q_data[V4L2_M2M_SRC].quant;
} else {
*ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
*quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
ctx->colorspace,
*ycbcr_enc);
}
}
static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct pxp_fmt *fmt;
struct pxp_ctx *ctx = file2ctx(file);
fmt = find_format(f->fmt.pix.pixelformat);
if (!fmt) {
f->fmt.pix.pixelformat = formats[0].fourcc;
fmt = find_format(f->fmt.pix.pixelformat);
}
if (!(fmt->types & MEM2MEM_CAPTURE)) {
v4l2_err(&ctx->dev->v4l2_dev,
"Fourcc format (0x%08x) invalid.\n",
f->fmt.pix.pixelformat);
return -EINVAL;
}
f->fmt.pix.colorspace = ctx->colorspace;
f->fmt.pix.xfer_func = ctx->xfer_func;
pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
&f->fmt.pix.ycbcr_enc,
&f->fmt.pix.quantization);
return pxp_try_fmt(f, fmt);
}
static int pxp_try_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct pxp_fmt *fmt;
struct pxp_ctx *ctx = file2ctx(file);
fmt = find_format(f->fmt.pix.pixelformat);
if (!fmt) {
f->fmt.pix.pixelformat = formats[0].fourcc;
fmt = find_format(f->fmt.pix.pixelformat);
}
if (!(fmt->types & MEM2MEM_OUTPUT)) {
v4l2_err(&ctx->dev->v4l2_dev,
"Fourcc format (0x%08x) invalid.\n",
f->fmt.pix.pixelformat);
return -EINVAL;
}
if (!f->fmt.pix.colorspace)
f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
return pxp_try_fmt(f, fmt);
}
static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
{
struct pxp_q_data *q_data;
struct vb2_queue *vq;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = get_q_data(ctx, f->type);
if (!q_data)
return -EINVAL;
if (vb2_is_busy(vq)) {
v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
return -EBUSY;
}
q_data->fmt = find_format(f->fmt.pix.pixelformat);
q_data->width = f->fmt.pix.width;
q_data->height = f->fmt.pix.height;
q_data->bytesperline = f->fmt.pix.bytesperline;
q_data->sizeimage = f->fmt.pix.sizeimage;
dprintk(ctx->dev,
"Setting format for type %d, wxh: %dx%d, fmt: %d\n",
f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
return 0;
}
static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct pxp_ctx *ctx = file2ctx(file);
int ret;
ret = pxp_try_fmt_vid_cap(file, priv, f);
if (ret)
return ret;
ret = pxp_s_fmt(file2ctx(file), f);
if (ret)
return ret;
ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
return 0;
}
static int pxp_s_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct pxp_ctx *ctx = file2ctx(file);
int ret;
ret = pxp_try_fmt_vid_out(file, priv, f);
if (ret)
return ret;
ret = pxp_s_fmt(file2ctx(file), f);
if (ret)
return ret;
ctx->colorspace = f->fmt.pix.colorspace;
ctx->xfer_func = f->fmt.pix.xfer_func;
ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
&ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
&ctx->q_data[V4L2_M2M_DST].quant);
return 0;
}
static int pxp_enum_framesizes(struct file *file, void *fh,
struct v4l2_frmsizeenum *fsize)
{
if (fsize->index > 0)
return -EINVAL;
if (!find_format(fsize->pixel_format))
return -EINVAL;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise.min_width = MIN_W;
fsize->stepwise.max_width = MAX_W;
fsize->stepwise.step_width = 1 << ALIGN_W;
fsize->stepwise.min_height = MIN_H;
fsize->stepwise.max_height = MAX_H;
fsize->stepwise.step_height = 1 << ALIGN_H;
return 0;
}
static u8 pxp_degrees_to_rot_mode(u32 degrees)
{
switch (degrees) {
case 90:
return BV_PXP_CTRL_ROTATE0__ROT_90;
case 180:
return BV_PXP_CTRL_ROTATE0__ROT_180;
case 270:
return BV_PXP_CTRL_ROTATE0__ROT_270;
case 0:
default:
return BV_PXP_CTRL_ROTATE0__ROT_0;
}
}
static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct pxp_ctx *ctx =
container_of(ctrl->handler, struct pxp_ctx, hdl);
switch (ctrl->id) {
case V4L2_CID_HFLIP:
if (ctrl->val)
ctx->mode |= MEM2MEM_HFLIP;
else
ctx->mode &= ~MEM2MEM_HFLIP;
break;
case V4L2_CID_VFLIP:
if (ctrl->val)
ctx->mode |= MEM2MEM_VFLIP;
else
ctx->mode &= ~MEM2MEM_VFLIP;
break;
case V4L2_CID_ROTATE:
ctx->rotation = pxp_degrees_to_rot_mode(ctrl->val);
break;
case V4L2_CID_ALPHA_COMPONENT:
ctx->alpha_component = ctrl->val;
break;
default:
v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
return -EINVAL;
}
return 0;
}
static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
.s_ctrl = pxp_s_ctrl,
};
static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
.vidioc_querycap = pxp_querycap,
.vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = pxp_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = pxp_s_fmt_vid_cap,
.vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
.vidioc_g_fmt_vid_out = pxp_g_fmt_vid_out,
.vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
.vidioc_s_fmt_vid_out = pxp_s_fmt_vid_out,
.vidioc_enum_framesizes = pxp_enum_framesizes,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/*
* Queue operations
*/
static int pxp_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
struct pxp_q_data *q_data;
unsigned int size, count = *nbuffers;
q_data = get_q_data(ctx, vq->type);
size = q_data->sizeimage;
*nbuffers = count;
if (*nplanes)
return sizes[0] < size ? -EINVAL : 0;
*nplanes = 1;
sizes[0] = size;
dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
return 0;
}
static int pxp_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct pxp_dev *dev = ctx->dev;
struct pxp_q_data *q_data;
dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
q_data = get_q_data(ctx, vb->vb2_queue->type);
if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
if (vbuf->field == V4L2_FIELD_ANY)
vbuf->field = V4L2_FIELD_NONE;
if (vbuf->field != V4L2_FIELD_NONE) {
dprintk(dev, "%s field isn't supported\n", __func__);
return -EINVAL;
}
}
if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
__func__, vb2_plane_size(vb, 0),
(long)q_data->sizeimage);
return -EINVAL;
}
vb2_set_plane_payload(vb, 0, q_data->sizeimage);
return 0;
}
static void pxp_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct pxp_ctx *ctx = vb2_get_drv_priv(q);
struct pxp_q_data *q_data = get_q_data(ctx, q->type);
q_data->sequence = 0;
return 0;
}
static void pxp_stop_streaming(struct vb2_queue *q)
{
struct pxp_ctx *ctx = vb2_get_drv_priv(q);
struct vb2_v4l2_buffer *vbuf;
unsigned long flags;
for (;;) {
if (V4L2_TYPE_IS_OUTPUT(q->type))
vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
else
vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (vbuf == NULL)
return;
spin_lock_irqsave(&ctx->dev->irqlock, flags);
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
}
}
static const struct vb2_ops pxp_qops = {
.queue_setup = pxp_queue_setup,
.buf_prepare = pxp_buf_prepare,
.buf_queue = pxp_buf_queue,
.start_streaming = pxp_start_streaming,
.stop_streaming = pxp_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct pxp_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->ops = &pxp_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->dev->dev_mutex;
src_vq->dev = ctx->dev->v4l2_dev.dev;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->ops = &pxp_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->dev->dev_mutex;
dst_vq->dev = ctx->dev->v4l2_dev.dev;
return vb2_queue_init(dst_vq);
}
/*
* File operations
*/
static int pxp_open(struct file *file)
{
struct pxp_dev *dev = video_drvdata(file);
struct pxp_ctx *ctx = NULL;
struct v4l2_ctrl_handler *hdl;
int rc = 0;
if (mutex_lock_interruptible(&dev->dev_mutex))
return -ERESTARTSYS;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx) {
rc = -ENOMEM;
goto open_unlock;
}
v4l2_fh_init(&ctx->fh, video_devdata(file));
file->private_data = &ctx->fh;
ctx->dev = dev;
hdl = &ctx->hdl;
v4l2_ctrl_handler_init(hdl, 4);
v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
0, 255, 1, 255);
if (hdl->error) {
rc = hdl->error;
v4l2_ctrl_handler_free(hdl);
kfree(ctx);
goto open_unlock;
}
ctx->fh.ctrl_handler = hdl;
v4l2_ctrl_handler_setup(hdl);
ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
ctx->q_data[V4L2_M2M_SRC].width = 640;
ctx->q_data[V4L2_M2M_SRC].height = 480;
ctx->q_data[V4L2_M2M_SRC].bytesperline =
pxp_bytesperline(&formats[0], 640);
ctx->q_data[V4L2_M2M_SRC].sizeimage =
pxp_sizeimage(&formats[0], 640, 480);
ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
ctx->colorspace = V4L2_COLORSPACE_REC709;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
rc = PTR_ERR(ctx->fh.m2m_ctx);
v4l2_ctrl_handler_free(hdl);
v4l2_fh_exit(&ctx->fh);
kfree(ctx);
goto open_unlock;
}
v4l2_fh_add(&ctx->fh);
atomic_inc(&dev->num_inst);
dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
ctx, ctx->fh.m2m_ctx);
open_unlock:
mutex_unlock(&dev->dev_mutex);
return rc;
}
static int pxp_release(struct file *file)
{
struct pxp_dev *dev = video_drvdata(file);
struct pxp_ctx *ctx = file2ctx(file);
dprintk(dev, "Releasing instance %p\n", ctx);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_ctrl_handler_free(&ctx->hdl);
mutex_lock(&dev->dev_mutex);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
mutex_unlock(&dev->dev_mutex);
kfree(ctx);
atomic_dec(&dev->num_inst);
return 0;
}
static const struct v4l2_file_operations pxp_fops = {
.owner = THIS_MODULE,
.open = pxp_open,
.release = pxp_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct video_device pxp_videodev = {
.name = MEM2MEM_NAME,
.vfl_dir = VFL_DIR_M2M,
.fops = &pxp_fops,
.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
.ioctl_ops = &pxp_ioctl_ops,
.minor = -1,
.release = video_device_release_empty,
};
static const struct v4l2_m2m_ops m2m_ops = {
.device_run = pxp_device_run,
.job_ready = pxp_job_ready,
.job_abort = pxp_job_abort,
};
static int pxp_soft_reset(struct pxp_dev *dev)
{
int ret;
u32 val;
pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_SFTRST);
pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_CLKGATE);
pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_SFTRST);
ret = regmap_read_poll_timeout(dev->regmap, HW_PXP_CTRL, val,
val & BM_PXP_CTRL_CLKGATE, 0, 100);
if (ret < 0)
return ret;
pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_SFTRST);
pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_CLKGATE);
return 0;
}
static int pxp_probe(struct platform_device *pdev)
{
struct pxp_dev *dev;
struct video_device *vfd;
u32 hw_version;
int irq;
int ret;
void __iomem *mmio;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->pdata = of_device_get_match_data(&pdev->dev);
dev->clk = devm_clk_get(&pdev->dev, "axi");
if (IS_ERR(dev->clk)) {
ret = PTR_ERR(dev->clk);
dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
return ret;
}
mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mmio))
return PTR_ERR(mmio);
dev->regmap = devm_regmap_init_mmio(&pdev->dev, mmio,
&pxp_regmap_config);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
spin_lock_init(&dev->irqlock);
ret = devm_request_irq(&pdev->dev, irq, pxp_irq_handler, 0,
dev_name(&pdev->dev), dev);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(dev->clk);
if (ret < 0)
return ret;
ret = pxp_soft_reset(dev);
if (ret < 0) {
dev_err(&pdev->dev, "PXP reset timeout: %d\n", ret);
goto err_clk;
}
hw_version = pxp_read(dev, HW_PXP_VERSION);
dev_dbg(&pdev->dev, "PXP Version %u.%u\n",
PXP_VERSION_MAJOR(hw_version), PXP_VERSION_MINOR(hw_version));
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
if (ret)
goto err_clk;
atomic_set(&dev->num_inst, 0);
mutex_init(&dev->dev_mutex);
dev->vfd = pxp_videodev;
vfd = &dev->vfd;
vfd->lock = &dev->dev_mutex;
vfd->v4l2_dev = &dev->v4l2_dev;
video_set_drvdata(vfd, dev);
snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
v4l2_info(&dev->v4l2_dev,
"Device registered as /dev/video%d\n", vfd->num);
platform_set_drvdata(pdev, dev);
dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
if (IS_ERR(dev->m2m_dev)) {
v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(dev->m2m_dev);
goto err_v4l2;
}
ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
goto err_m2m;
}
#ifdef CONFIG_MEDIA_CONTROLLER
dev->mdev.dev = &pdev->dev;
strscpy(dev->mdev.model, MEM2MEM_NAME, sizeof(dev->mdev.model));
media_device_init(&dev->mdev);
dev->v4l2_dev.mdev = &dev->mdev;
ret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd,
MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER);
if (ret) {
dev_err(&pdev->dev, "Failed to initialize media device\n");
goto err_vfd;
}
ret = media_device_register(&dev->mdev);
if (ret) {
dev_err(&pdev->dev, "Failed to register media device\n");
goto err_m2m_mc;
}
#endif
return 0;
#ifdef CONFIG_MEDIA_CONTROLLER
err_m2m_mc:
v4l2_m2m_unregister_media_controller(dev->m2m_dev);
err_vfd:
video_unregister_device(vfd);
#endif
err_m2m:
v4l2_m2m_release(dev->m2m_dev);
err_v4l2:
v4l2_device_unregister(&dev->v4l2_dev);
err_clk:
clk_disable_unprepare(dev->clk);
return ret;
}
static void pxp_remove(struct platform_device *pdev)
{
struct pxp_dev *dev = platform_get_drvdata(pdev);
pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_CLKGATE);
pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_SFTRST);
clk_disable_unprepare(dev->clk);
v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
#ifdef CONFIG_MEDIA_CONTROLLER
media_device_unregister(&dev->mdev);
v4l2_m2m_unregister_media_controller(dev->m2m_dev);
#endif
video_unregister_device(&dev->vfd);
v4l2_m2m_release(dev->m2m_dev);
v4l2_device_unregister(&dev->v4l2_dev);
}
static const struct pxp_pdata pxp_imx6ull_pdata = {
.data_path_ctrl0 = pxp_imx6ull_data_path_ctrl0,
};
static const struct pxp_pdata pxp_imx7d_pdata = {
.data_path_ctrl0 = pxp_imx7d_data_path_ctrl0,
};
static const struct of_device_id pxp_dt_ids[] = {
{ .compatible = "fsl,imx6ull-pxp", .data = &pxp_imx6ull_pdata },
{ .compatible = "fsl,imx7d-pxp", .data = &pxp_imx7d_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, pxp_dt_ids);
static struct platform_driver pxp_driver = {
.probe = pxp_probe,
.remove_new = pxp_remove,
.driver = {
.name = MEM2MEM_NAME,
.of_match_table = pxp_dt_ids,
},
};
module_platform_driver(pxp_driver);
MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
MODULE_AUTHOR("Philipp Zabel <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/platform/nxp/imx-pxp.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* DW100 Hardware dewarper
*
* Copyright 2022 NXP
* Author: Xavier Roumegue ([email protected])
*
*/
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-contig.h>
#include <uapi/linux/dw100.h>
#include "dw100_regs.h"
#define DRV_NAME "dw100"
#define DW100_MIN_W 176u
#define DW100_MIN_H 144u
#define DW100_MAX_W 4096u
#define DW100_MAX_H 3072u
#define DW100_ALIGN_W 3
#define DW100_ALIGN_H 3
#define DW100_BLOCK_SIZE 16
#define DW100_DEF_W 640u
#define DW100_DEF_H 480u
#define DW100_DEF_LUT_W (DIV_ROUND_UP(DW100_DEF_W, DW100_BLOCK_SIZE) + 1)
#define DW100_DEF_LUT_H (DIV_ROUND_UP(DW100_DEF_H, DW100_BLOCK_SIZE) + 1)
/*
* 16 controls have been reserved for this driver for future extension, but
* let's limit the related driver allocation to the effective number of controls
* in use.
*/
#define DW100_MAX_CTRLS 1
#define DW100_CTRL_DEWARPING_MAP 0
enum {
DW100_QUEUE_SRC = 0,
DW100_QUEUE_DST = 1,
};
enum {
DW100_FMT_CAPTURE = BIT(0),
DW100_FMT_OUTPUT = BIT(1),
};
struct dw100_device {
struct platform_device *pdev;
struct v4l2_m2m_dev *m2m_dev;
struct v4l2_device v4l2_dev;
struct video_device vfd;
struct media_device mdev;
/* Video device lock */
struct mutex vfd_mutex;
void __iomem *mmio;
struct clk_bulk_data *clks;
int num_clks;
struct dentry *debugfs_root;
};
struct dw100_q_data {
struct v4l2_pix_format_mplane pix_fmt;
unsigned int sequence;
const struct dw100_fmt *fmt;
struct v4l2_rect crop;
};
struct dw100_ctx {
struct v4l2_fh fh;
struct dw100_device *dw_dev;
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *ctrls[DW100_MAX_CTRLS];
/* per context m2m queue lock */
struct mutex vq_mutex;
/* Look Up Table for pixel remapping */
unsigned int *map;
dma_addr_t map_dma;
size_t map_size;
unsigned int map_width;
unsigned int map_height;
bool user_map_is_set;
/* Source and destination queue data */
struct dw100_q_data q_data[2];
};
static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = {
.min_width = DW100_MIN_W,
.min_height = DW100_MIN_H,
.max_width = DW100_MAX_W,
.max_height = DW100_MAX_H,
.step_width = 1UL << DW100_ALIGN_W,
.step_height = 1UL << DW100_ALIGN_H,
};
static const struct dw100_fmt {
u32 fourcc;
u32 types;
u32 reg_format;
bool reg_swap_uv;
} formats[] = {
{
.fourcc = V4L2_PIX_FMT_NV16,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
.reg_swap_uv = false,
}, {
.fourcc = V4L2_PIX_FMT_NV16M,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
.reg_swap_uv = false,
}, {
.fourcc = V4L2_PIX_FMT_NV61,
.types = DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
.reg_swap_uv = true,
}, {
.fourcc = V4L2_PIX_FMT_NV61M,
.types = DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
.reg_swap_uv = true,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
.reg_swap_uv = false,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
.reg_swap_uv = true,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
.reg_swap_uv = false,
}, {
.fourcc = V4L2_PIX_FMT_NV12M,
.types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
.reg_swap_uv = false,
}, {
.fourcc = V4L2_PIX_FMT_NV21,
.types = DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
.reg_swap_uv = true,
}, {
.fourcc = V4L2_PIX_FMT_NV21M,
.types = DW100_FMT_CAPTURE,
.reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
.reg_swap_uv = true,
},
};
static inline int to_dw100_fmt_type(enum v4l2_buf_type type)
{
if (V4L2_TYPE_IS_OUTPUT(type))
return DW100_FMT_OUTPUT;
else
return DW100_FMT_CAPTURE;
}
static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format,
int fmt_type)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
const struct dw100_fmt *fmt = &formats[i];
if (fmt->fourcc == pixel_format && fmt->types & fmt_type)
return fmt;
}
return NULL;
}
static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f)
{
return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat,
to_dw100_fmt_type(f->type));
}
static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg)
{
return readl(dw_dev->mmio + reg);
}
static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val)
{
writel(val, dw_dev->mmio + reg);
}
static inline int dw100_dump_regs(struct seq_file *m)
{
struct dw100_device *dw_dev = m->private;
#define __DECLARE_REG(x) { #x, x }
unsigned int i;
static const struct reg_desc {
const char * const name;
unsigned int addr;
} dw100_regs[] = {
__DECLARE_REG(DW100_DEWARP_ID),
__DECLARE_REG(DW100_DEWARP_CTRL),
__DECLARE_REG(DW100_MAP_LUT_ADDR),
__DECLARE_REG(DW100_MAP_LUT_SIZE),
__DECLARE_REG(DW100_MAP_LUT_ADDR2),
__DECLARE_REG(DW100_MAP_LUT_SIZE2),
__DECLARE_REG(DW100_SRC_IMG_Y_BASE),
__DECLARE_REG(DW100_SRC_IMG_UV_BASE),
__DECLARE_REG(DW100_SRC_IMG_SIZE),
__DECLARE_REG(DW100_SRC_IMG_STRIDE),
__DECLARE_REG(DW100_DST_IMG_Y_BASE),
__DECLARE_REG(DW100_DST_IMG_UV_BASE),
__DECLARE_REG(DW100_DST_IMG_SIZE),
__DECLARE_REG(DW100_DST_IMG_STRIDE),
__DECLARE_REG(DW100_DST_IMG_Y_SIZE1),
__DECLARE_REG(DW100_DST_IMG_UV_SIZE1),
__DECLARE_REG(DW100_SRC_IMG_Y_BASE2),
__DECLARE_REG(DW100_SRC_IMG_UV_BASE2),
__DECLARE_REG(DW100_SRC_IMG_SIZE2),
__DECLARE_REG(DW100_SRC_IMG_STRIDE2),
__DECLARE_REG(DW100_DST_IMG_Y_BASE2),
__DECLARE_REG(DW100_DST_IMG_UV_BASE2),
__DECLARE_REG(DW100_DST_IMG_SIZE2),
__DECLARE_REG(DW100_DST_IMG_STRIDE2),
__DECLARE_REG(DW100_DST_IMG_Y_SIZE2),
__DECLARE_REG(DW100_DST_IMG_UV_SIZE2),
__DECLARE_REG(DW100_SWAP_CONTROL),
__DECLARE_REG(DW100_VERTICAL_SPLIT_LINE),
__DECLARE_REG(DW100_HORIZON_SPLIT_LINE),
__DECLARE_REG(DW100_SCALE_FACTOR),
__DECLARE_REG(DW100_ROI_START),
__DECLARE_REG(DW100_BOUNDARY_PIXEL),
__DECLARE_REG(DW100_INTERRUPT_STATUS),
__DECLARE_REG(DW100_BUS_CTRL),
__DECLARE_REG(DW100_BUS_CTRL1),
__DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE),
};
for (i = 0; i < ARRAY_SIZE(dw100_regs); i++)
seq_printf(m, "%s: %#x\n", dw100_regs[i].name,
dw100_read(dw_dev, dw100_regs[i].addr));
return 0;
}
static inline struct dw100_ctx *dw100_file2ctx(struct file *file)
{
return container_of(file->private_data, struct dw100_ctx, fh);
}
static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx,
enum v4l2_buf_type type)
{
if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return &ctx->q_data[DW100_QUEUE_SRC];
else
return &ctx->q_data[DW100_QUEUE_DST];
}
static u32 dw100_get_n_vertices_from_length(u32 length)
{
return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1;
}
static u16 dw100_map_convert_to_uq12_4(u32 a)
{
return (u16)((a & 0xfff) << 4);
}
static u32 dw100_map_format_coordinates(u16 xq, u16 yq)
{
return (u32)((yq << 16) | xq);
}
static u32 *dw100_get_user_map(struct dw100_ctx *ctx)
{
struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
return ctrl->p_cur.p_u32;
}
/*
* Create the dewarp map used by the hardware from the V4L2 control values which
* have been initialized with an identity map or set by the application.
*/
static int dw100_create_mapping(struct dw100_ctx *ctx)
{
u32 *user_map;
if (ctx->map)
dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
ctx->map, ctx->map_dma);
ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
&ctx->map_dma, GFP_KERNEL);
if (!ctx->map)
return -ENOMEM;
user_map = dw100_get_user_map(ctx);
memcpy(ctx->map, user_map, ctx->map_size);
dev_dbg(&ctx->dw_dev->pdev->dev,
"%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n",
ctx->map_width, ctx->map_height,
ctx->user_map_is_set ? "user" : "identity",
&ctx->map_dma, ctx->map,
ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
ctx->q_data[DW100_QUEUE_DST].pix_fmt.height,
ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
ctx->q_data[DW100_QUEUE_DST].pix_fmt.height);
return 0;
}
static void dw100_destroy_mapping(struct dw100_ctx *ctx)
{
if (ctx->map) {
dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
ctx->map, ctx->map_dma);
ctx->map = NULL;
}
}
static int dw100_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct dw100_ctx *ctx =
container_of(ctrl->handler, struct dw100_ctx, hdl);
switch (ctrl->id) {
case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP:
ctx->user_map_is_set = true;
break;
}
return 0;
}
static const struct v4l2_ctrl_ops dw100_ctrl_ops = {
.s_ctrl = dw100_s_ctrl,
};
/*
* Initialize the dewarping map with an identity mapping.
*
* A 16 pixels cell size grid is mapped on the destination image.
* The last cells width/height might be lesser than 16 if the destination image
* width/height is not divisible by 16. This dewarping grid map specifies the
* source image pixel location (x, y) on each grid intersection point.
* Bilinear interpolation is used to compute inner cell points locations.
*
* The coordinates are saved in UQ12.4 fixed point format.
*/
static void dw100_ctrl_dewarping_map_init(const struct v4l2_ctrl *ctrl,
u32 from_idx,
union v4l2_ctrl_ptr ptr)
{
struct dw100_ctx *ctx =
container_of(ctrl->handler, struct dw100_ctx, hdl);
u32 sw, sh, mw, mh, idx;
u16 qx, qy, qdx, qdy, qsh, qsw;
u32 *map = ctrl->p_cur.p_u32;
sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width;
sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height;
mw = ctrl->dims[0];
mh = ctrl->dims[1];
qsw = dw100_map_convert_to_uq12_4(sw);
qsh = dw100_map_convert_to_uq12_4(sh);
qdx = qsw / (mw - 1);
qdy = qsh / (mh - 1);
ctx->map_width = mw;
ctx->map_height = mh;
ctx->map_size = mh * mw * sizeof(u32);
for (idx = from_idx; idx < ctrl->elems; idx++) {
qy = min_t(u32, (idx / mw) * qdy, qsh);
qx = min_t(u32, (idx % mw) * qdx, qsw);
map[idx] = dw100_map_format_coordinates(qx, qy);
}
ctx->user_map_is_set = false;
}
static const struct v4l2_ctrl_type_ops dw100_ctrl_type_ops = {
.init = dw100_ctrl_dewarping_map_init,
.validate = v4l2_ctrl_type_op_validate,
.log = v4l2_ctrl_type_op_log,
.equal = v4l2_ctrl_type_op_equal,
};
static const struct v4l2_ctrl_config controls[] = {
[DW100_CTRL_DEWARPING_MAP] = {
.ops = &dw100_ctrl_ops,
.type_ops = &dw100_ctrl_type_ops,
.id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP,
.name = "Dewarping Vertex Map",
.type = V4L2_CTRL_TYPE_U32,
.min = 0x00000000,
.max = 0xffffffff,
.step = 1,
.def = 0,
.dims = { DW100_DEF_LUT_W, DW100_DEF_LUT_H },
},
};
static int dw100_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct dw100_ctx *ctx = vb2_get_drv_priv(vq);
const struct v4l2_pix_format_mplane *format;
unsigned int i;
format = &dw100_get_q_data(ctx, vq->type)->pix_fmt;
if (*nplanes) {
if (*nplanes != format->num_planes)
return -EINVAL;
for (i = 0; i < *nplanes; ++i) {
if (sizes[i] < format->plane_fmt[i].sizeimage)
return -EINVAL;
}
return 0;
}
*nplanes = format->num_planes;
for (i = 0; i < format->num_planes; ++i)
sizes[i] = format->plane_fmt[i].sizeimage;
return 0;
}
static int dw100_buf_prepare(struct vb2_buffer *vb)
{
unsigned int i;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct dw100_device *dw_dev = ctx->dw_dev;
const struct v4l2_pix_format_mplane *pix_fmt =
&dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt;
if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
if (vbuf->field != V4L2_FIELD_NONE) {
dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n",
vbuf->field);
return -EINVAL;
}
}
for (i = 0; i < pix_fmt->num_planes; i++) {
unsigned long size = pix_fmt->plane_fmt[i].sizeimage;
if (vb2_plane_size(vb, i) < size) {
dev_dbg(&dw_dev->pdev->dev,
"User buffer too small (%lu < %lu)\n",
vb2_plane_size(vb, i), size);
return -EINVAL;
}
vb2_set_plane_payload(vb, i, size);
}
return 0;
}
static void dw100_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static void dw100_return_all_buffers(struct vb2_queue *q,
enum vb2_buffer_state state)
{
struct dw100_ctx *ctx = vb2_get_drv_priv(q);
struct vb2_v4l2_buffer *vbuf;
for (;;) {
if (V4L2_TYPE_IS_OUTPUT(q->type))
vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
else
vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (!vbuf)
return;
v4l2_m2m_buf_done(vbuf, state);
}
}
static int dw100_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct dw100_ctx *ctx = vb2_get_drv_priv(q);
struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type);
int ret;
q_data->sequence = 0;
ret = dw100_create_mapping(ctx);
if (ret)
goto err;
ret = pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev);
if (ret) {
dw100_destroy_mapping(ctx);
goto err;
}
return 0;
err:
dw100_return_all_buffers(q, VB2_BUF_STATE_QUEUED);
return ret;
}
static void dw100_stop_streaming(struct vb2_queue *q)
{
struct dw100_ctx *ctx = vb2_get_drv_priv(q);
dw100_return_all_buffers(q, VB2_BUF_STATE_ERROR);
pm_runtime_put_sync(&ctx->dw_dev->pdev->dev);
dw100_destroy_mapping(ctx);
}
static const struct vb2_ops dw100_qops = {
.queue_setup = dw100_queue_setup,
.buf_prepare = dw100_buf_prepare,
.buf_queue = dw100_buf_queue,
.start_streaming = dw100_start_streaming,
.stop_streaming = dw100_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct dw100_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->ops = &dw100_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->vq_mutex;
src_vq->dev = ctx->dw_dev->v4l2_dev.dev;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->ops = &dw100_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->vq_mutex;
dst_vq->dev = ctx->dw_dev->v4l2_dev.dev;
return vb2_queue_init(dst_vq);
}
static int dw100_open(struct file *file)
{
struct dw100_device *dw_dev = video_drvdata(file);
struct dw100_ctx *ctx;
struct v4l2_ctrl_handler *hdl;
struct v4l2_pix_format_mplane *pix_fmt;
int ret, i;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
mutex_init(&ctx->vq_mutex);
v4l2_fh_init(&ctx->fh, video_devdata(file));
file->private_data = &ctx->fh;
ctx->dw_dev = dw_dev;
ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0];
pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt;
pix_fmt->field = V4L2_FIELD_NONE;
pix_fmt->colorspace = V4L2_COLORSPACE_REC709;
pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace);
pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace);
pix_fmt->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace,
pix_fmt->ycbcr_enc);
v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, DW100_DEF_W, DW100_DEF_H);
ctx->q_data[DW100_QUEUE_SRC].crop.top = 0;
ctx->q_data[DW100_QUEUE_SRC].crop.left = 0;
ctx->q_data[DW100_QUEUE_SRC].crop.width = DW100_DEF_W;
ctx->q_data[DW100_QUEUE_SRC].crop.height = DW100_DEF_H;
ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC];
hdl = &ctx->hdl;
v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls));
for (i = 0; i < ARRAY_SIZE(controls); i++) {
ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL);
if (hdl->error) {
dev_err(&ctx->dw_dev->pdev->dev,
"Adding control (%d) failed\n", i);
ret = hdl->error;
goto err;
}
}
ctx->fh.ctrl_handler = hdl;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev,
ctx, &dw100_m2m_queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
ret = PTR_ERR(ctx->fh.m2m_ctx);
goto err;
}
v4l2_fh_add(&ctx->fh);
return 0;
err:
v4l2_ctrl_handler_free(hdl);
v4l2_fh_exit(&ctx->fh);
mutex_destroy(&ctx->vq_mutex);
kfree(ctx);
return ret;
}
static int dw100_release(struct file *file)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_ctrl_handler_free(&ctx->hdl);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
mutex_destroy(&ctx->vq_mutex);
kfree(ctx);
return 0;
}
static const struct v4l2_file_operations dw100_fops = {
.owner = THIS_MODULE,
.open = dw100_open,
.release = dw100_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static int dw100_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, DRV_NAME, sizeof(cap->driver));
strscpy(cap->card, "DW100 dewarper", sizeof(cap->card));
return 0;
}
static int dw100_enum_fmt_vid(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
int i, num = 0;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
if (formats[i].types & to_dw100_fmt_type(f->type)) {
if (num == f->index) {
f->pixelformat = formats[i].fourcc;
return 0;
}
++num;
}
}
return -EINVAL;
}
static int dw100_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
const struct dw100_fmt *fmt;
if (fsize->index)
return -EINVAL;
fmt = dw100_find_pixel_format(fsize->pixel_format,
DW100_FMT_OUTPUT | DW100_FMT_CAPTURE);
if (!fmt)
return -EINVAL;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise = dw100_frmsize_stepwise;
return 0;
}
static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
struct vb2_queue *vq;
struct dw100_q_data *q_data;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = dw100_get_q_data(ctx, f->type);
f->fmt.pix_mp = q_data->pix_fmt;
return 0;
}
static int dw100_try_fmt(struct file *file, struct v4l2_format *f)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
const struct dw100_fmt *fmt;
fmt = dw100_find_format(f);
if (!fmt) {
fmt = &formats[0];
pix->pixelformat = fmt->fourcc;
}
v4l2_apply_frmsize_constraints(&pix->width, &pix->height,
&dw100_frmsize_stepwise);
v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height);
pix->field = V4L2_FIELD_NONE;
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
if (pix->colorspace == V4L2_COLORSPACE_DEFAULT)
pix->colorspace = V4L2_COLORSPACE_REC709;
if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT)
pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
if (pix->quantization == V4L2_QUANTIZATION_DEFAULT)
pix->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(false,
pix->colorspace,
pix->ycbcr_enc);
} else {
/*
* The DW100 can't perform colorspace conversion, the colorspace
* on the capture queue must be identical to the output queue.
*/
const struct dw100_q_data *q_data =
dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
pix->colorspace = q_data->pix_fmt.colorspace;
pix->xfer_func = q_data->pix_fmt.xfer_func;
pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
pix->quantization = q_data->pix_fmt.quantization;
}
return 0;
}
static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f)
{
struct dw100_q_data *q_data;
struct vb2_queue *vq;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
q_data = dw100_get_q_data(ctx, f->type);
if (!q_data)
return -EINVAL;
if (vb2_is_busy(vq)) {
dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__);
return -EBUSY;
}
q_data->fmt = dw100_find_format(f);
q_data->pix_fmt = f->fmt.pix_mp;
q_data->crop.top = 0;
q_data->crop.left = 0;
q_data->crop.width = f->fmt.pix_mp.width;
q_data->crop.height = f->fmt.pix_mp.height;
/* Propagate buffers encoding */
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
struct dw100_q_data *dst_q_data =
dw100_get_q_data(ctx,
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace;
dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization;
dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func;
}
dev_dbg(&ctx->dw_dev->pdev->dev,
"Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n",
f->type, q_data->pix_fmt.width, q_data->pix_fmt.height,
&q_data->pix_fmt.pixelformat);
if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
int ret;
u32 dims[V4L2_CTRL_MAX_DIMS] = {};
struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width);
dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height);
ret = v4l2_ctrl_modify_dimensions(ctrl, dims);
if (ret) {
dev_err(&ctx->dw_dev->pdev->dev,
"Modifying LUT dimensions failed with error %d\n",
ret);
return ret;
}
}
return 0;
}
static int dw100_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
return -EINVAL;
return dw100_try_fmt(file, f);
}
static int dw100_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
int ret;
ret = dw100_try_fmt_vid_cap(file, priv, f);
if (ret)
return ret;
ret = dw100_s_fmt(ctx, f);
if (ret)
return ret;
return 0;
}
static int dw100_try_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return -EINVAL;
return dw100_try_fmt(file, f);
}
static int dw100_s_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
int ret;
ret = dw100_try_fmt_vid_out(file, priv, f);
if (ret)
return ret;
ret = dw100_s_fmt(ctx, f);
if (ret)
return ret;
return 0;
}
static int dw100_g_selection(struct file *file, void *fh,
struct v4l2_selection *sel)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
struct dw100_q_data *src_q_data;
if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
switch (sel->target) {
case V4L2_SEL_TGT_CROP_DEFAULT:
case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r.top = 0;
sel->r.left = 0;
sel->r.width = src_q_data->pix_fmt.width;
sel->r.height = src_q_data->pix_fmt.height;
break;
case V4L2_SEL_TGT_CROP:
sel->r.top = src_q_data->crop.top;
sel->r.left = src_q_data->crop.left;
sel->r.width = src_q_data->crop.width;
sel->r.height = src_q_data->crop.height;
break;
default:
return -EINVAL;
}
return 0;
}
static int dw100_s_selection(struct file *file, void *fh,
struct v4l2_selection *sel)
{
struct dw100_ctx *ctx = dw100_file2ctx(file);
struct dw100_q_data *src_q_data;
u32 qscalex, qscaley, qscale;
int x, y, w, h;
unsigned int wframe, hframe;
if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
dev_dbg(&ctx->dw_dev->pdev->dev,
">>> Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n",
sel->type, sel->target,
sel->r.width, sel->r.height, sel->r.left, sel->r.top);
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
wframe = src_q_data->pix_fmt.width;
hframe = src_q_data->pix_fmt.height;
sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H);
sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W);
sel->r.height =
clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top);
sel->r.width =
clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left);
/* UQ16.16 for float operations */
qscalex = (sel->r.width << 16) / wframe;
qscaley = (sel->r.height << 16) / hframe;
y = sel->r.top;
x = sel->r.left;
if (qscalex == qscaley) {
qscale = qscalex;
} else {
switch (sel->flags) {
case 0:
qscale = (qscalex + qscaley) / 2;
break;
case V4L2_SEL_FLAG_GE:
qscale = max(qscaley, qscalex);
break;
case V4L2_SEL_FLAG_LE:
qscale = min(qscaley, qscalex);
break;
case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE:
return -ERANGE;
default:
return -EINVAL;
}
}
w = (u32)((((u64)wframe << 16) * qscale) >> 32);
h = (u32)((((u64)hframe << 16) * qscale) >> 32);
x = x + (sel->r.width - w) / 2;
y = y + (sel->r.height - h) / 2;
x = min(wframe - w, (unsigned int)max(0, x));
y = min(hframe - h, (unsigned int)max(0, y));
sel->r.top = y;
sel->r.left = x;
sel->r.width = w;
sel->r.height = h;
src_q_data->crop.top = sel->r.top;
src_q_data->crop.left = sel->r.left;
src_q_data->crop.width = sel->r.width;
src_q_data->crop.height = sel->r.height;
break;
default:
return -EINVAL;
}
dev_dbg(&ctx->dw_dev->pdev->dev,
"<<< Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n",
sel->type, sel->target,
sel->r.width, sel->r.height, sel->r.left, sel->r.top);
return 0;
}
static const struct v4l2_ioctl_ops dw100_ioctl_ops = {
.vidioc_querycap = dw100_querycap,
.vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid,
.vidioc_enum_framesizes = dw100_enum_framesizes,
.vidioc_g_fmt_vid_cap_mplane = dw100_g_fmt_vid,
.vidioc_try_fmt_vid_cap_mplane = dw100_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap_mplane = dw100_s_fmt_vid_cap,
.vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid,
.vidioc_g_fmt_vid_out_mplane = dw100_g_fmt_vid,
.vidioc_try_fmt_vid_out_mplane = dw100_try_fmt_vid_out,
.vidioc_s_fmt_vid_out_mplane = dw100_s_fmt_vid_out,
.vidioc_g_selection = dw100_g_selection,
.vidioc_s_selection = dw100_s_selection,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error)
{
struct dw100_ctx *curr_ctx;
struct vb2_v4l2_buffer *src_vb, *dst_vb;
enum vb2_buffer_state buf_state;
curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev);
if (!curr_ctx) {
dev_err(&dw_dev->pdev->dev,
"Instance released before the end of transaction\n");
return;
}
src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
if (likely(!with_error))
buf_state = VB2_BUF_STATE_DONE;
else
buf_state = VB2_BUF_STATE_ERROR;
v4l2_m2m_buf_done(src_vb, buf_state);
v4l2_m2m_buf_done(dst_vb, buf_state);
dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n",
with_error ? "" : "out");
v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx);
}
static void dw100_hw_reset(struct dw100_device *dw_dev)
{
u32 val;
val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
val |= DW100_DEWARP_CTRL_ENABLE;
val |= DW100_DEWARP_CTRL_SOFT_RESET;
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
val &= ~DW100_DEWARP_CTRL_SOFT_RESET;
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
}
static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev,
unsigned int enable)
{
u32 val;
dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n",
enable ? "En" : "Dis");
val = dw100_read(dw_dev, DW100_BUS_CTRL);
if (enable)
val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE;
else
val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE;
dw100_write(dw_dev, DW100_BUS_CTRL, val);
}
static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev)
{
_dw100_hw_set_master_bus_enable(dw_dev, 1);
}
static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev)
{
_dw100_hw_set_master_bus_enable(dw_dev, 0);
}
static void dw100_hw_dewarp_start(struct dw100_device *dw_dev)
{
u32 val;
val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val);
dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START);
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
}
static void dw100_hw_init_ctrl(struct dw100_device *dw_dev)
{
u32 val;
/*
* Input format YUV422_SP
* Output format YUV422_SP
* No hardware handshake (SW)
* No automatic double src buffering (Single)
* No automatic double dst buffering (Single)
* No Black Line
* Prefetch image pixel traversal
*/
val = DW100_DEWARP_CTRL_ENABLE
/* Valid only for auto prefetch mode*/
| DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32);
/*
* Calculation mode required to support any scaling factor,
* but x4 slower than traversal mode.
*
* DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL
* DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION
* DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO
*
* TODO: Find heuristics requiring calculation mode
*/
val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION;
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
}
static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev)
{
u32 val;
val = DW100_BOUNDARY_PIXEL_V(128)
| DW100_BOUNDARY_PIXEL_U(128)
| DW100_BOUNDARY_PIXEL_Y(0);
dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val);
}
static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale)
{
dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale);
dw100_write(dw_dev, DW100_SCALE_FACTOR, scale);
}
static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y)
{
u32 val;
dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y);
val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y);
dw100_write(dw_dev, DW100_ROI_START, val);
}
static void dw100_hw_set_src_crop(struct dw100_device *dw_dev,
const struct dw100_q_data *src_q_data,
const struct dw100_q_data *dst_q_data)
{
const struct v4l2_rect *rect = &src_q_data->crop;
u32 src_scale, qscale, left_scale, top_scale;
/* HW Scale is UQ1.7 encoded */
src_scale = (rect->width << 7) / src_q_data->pix_fmt.width;
dw100_hw_set_scale(dw_dev, src_scale);
qscale = (dst_q_data->pix_fmt.width << 7) / src_q_data->pix_fmt.width;
left_scale = ((rect->left << 7) * qscale) >> 14;
top_scale = ((rect->top << 7) * qscale) >> 14;
dw100_hw_set_roi(dw_dev, left_scale, top_scale);
}
static void dw100_hw_set_source(struct dw100_device *dw_dev,
const struct dw100_q_data *q_data,
struct vb2_buffer *buffer)
{
u32 width, height, stride, fourcc, val;
const struct dw100_fmt *fmt = q_data->fmt;
dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
dma_addr_t addr_uv;
width = q_data->pix_fmt.width;
height = q_data->pix_fmt.height;
stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
fourcc = q_data->fmt->fourcc;
if (q_data->pix_fmt.num_planes == 2)
addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
else
addr_uv = addr_y + (stride * height);
dev_dbg(&dw_dev->pdev->dev,
"Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
width, height, stride, &fourcc, &addr_y);
/* Pixel Format */
val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK;
val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format);
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
/* Swap */
val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
val &= ~DW100_SWAP_CONTROL_SRC_MASK;
/*
* Data swapping is performed only on Y plane for source image.
*/
if (fmt->reg_swap_uv &&
fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y
(DW100_SWAP_CONTROL_BYTE));
dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
/* Image resolution */
dw100_write(dw_dev, DW100_SRC_IMG_SIZE,
DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
dw100_write(dw_dev, DW100_SRC_IMG_STRIDE, stride);
/* Buffers */
dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
}
static void dw100_hw_set_destination(struct dw100_device *dw_dev,
const struct dw100_q_data *q_data,
const struct dw100_fmt *ifmt,
struct vb2_buffer *buffer)
{
u32 width, height, stride, fourcc, val, size_y, size_uv;
const struct dw100_fmt *fmt = q_data->fmt;
dma_addr_t addr_y, addr_uv;
width = q_data->pix_fmt.width;
height = q_data->pix_fmt.height;
stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
fourcc = fmt->fourcc;
addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
size_y = q_data->pix_fmt.plane_fmt[0].sizeimage;
if (q_data->pix_fmt.num_planes == 2) {
addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage;
} else {
addr_uv = addr_y + ALIGN(stride * height, 16);
size_uv = size_y;
if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP)
size_uv /= 2;
}
dev_dbg(&dw_dev->pdev->dev,
"Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
width, height, stride, &fourcc, &addr_y);
/* Pixel Format */
val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK;
val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format);
dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
/* Swap */
val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
val &= ~DW100_SWAP_CONTROL_DST_MASK;
/*
* Avoid to swap twice
*/
if (fmt->reg_swap_uv ^
(ifmt->reg_swap_uv && ifmt->reg_format !=
DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) {
if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y
(DW100_SWAP_CONTROL_BYTE));
else
val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV
(DW100_SWAP_CONTROL_BYTE));
}
dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
/* Image resolution */
dw100_write(dw_dev, DW100_DST_IMG_SIZE,
DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride);
dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y));
dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1,
DW100_DST_IMG_UV_SIZE(size_uv));
}
static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr,
u32 width, u32 height)
{
dev_dbg(&dw_dev->pdev->dev,
"Set HW mapping registers for %ux%u addr:%pad",
width, height, &addr);
dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr));
dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width)
| DW100_MAP_LUT_SIZE_HEIGHT(height));
}
static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq)
{
dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
DW100_INTERRUPT_STATUS_INT_CLEAR(irq));
}
static void dw100_hw_enable_irq(struct dw100_device *dw_dev)
{
dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
DW100_INTERRUPT_STATUS_INT_ENABLE_MASK);
}
static void dw100_hw_disable_irq(struct dw100_device *dw_dev)
{
dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0);
}
static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev)
{
u32 val;
val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS);
return DW100_INTERRUPT_STATUS_INT_STATUS(val);
}
static irqreturn_t dw100_irq_handler(int irq, void *dev_id)
{
struct dw100_device *dw_dev = dev_id;
u32 pending_irqs, err_irqs, frame_done_irq;
bool with_error = true;
pending_irqs = dw_hw_get_pending_irqs(dw_dev);
frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE;
err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs);
if (frame_done_irq) {
dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n");
with_error = false;
err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS
(DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE);
}
if (err_irqs)
dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs);
dw100_hw_disable_irq(dw_dev);
dw100_hw_master_bus_disable(dw_dev);
dw100_hw_clear_irq(dw_dev, pending_irqs |
DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT);
dw100_job_finish(dw_dev, with_error);
return IRQ_HANDLED;
}
static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
struct vb2_v4l2_buffer *out_vb)
{
struct dw100_device *dw_dev = ctx->dw_dev;
out_vb->sequence =
dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++;
in_vb->sequence =
dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++;
dev_dbg(&ctx->dw_dev->pdev->dev,
"Starting queues %p->%p, sequence %u->%u\n",
v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE),
v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE),
in_vb->sequence, out_vb->sequence);
v4l2_m2m_buf_copy_metadata(in_vb, out_vb, true);
/* Now, let's deal with hardware ... */
dw100_hw_master_bus_disable(dw_dev);
dw100_hw_init_ctrl(dw_dev);
dw100_hw_set_pixel_boundary(dw_dev);
dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
&ctx->q_data[DW100_QUEUE_DST]);
dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
&in_vb->vb2_buf);
dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST],
ctx->q_data[DW100_QUEUE_SRC].fmt,
&out_vb->vb2_buf);
dw100_hw_set_mapping(dw_dev, ctx->map_dma,
ctx->map_width, ctx->map_height);
dw100_hw_enable_irq(dw_dev);
dw100_hw_dewarp_start(dw_dev);
/* Enable Bus */
dw100_hw_master_bus_enable(dw_dev);
}
static void dw100_device_run(void *priv)
{
struct dw100_ctx *ctx = priv;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
dw100_start(ctx, src_buf, dst_buf);
}
static const struct v4l2_m2m_ops dw100_m2m_ops = {
.device_run = dw100_device_run,
};
static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev)
{
struct video_device *vfd = &dw_dev->vfd;
vfd->vfl_dir = VFL_DIR_M2M;
vfd->fops = &dw100_fops;
vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
vfd->ioctl_ops = &dw100_ioctl_ops;
vfd->minor = -1;
vfd->release = video_device_release_empty;
vfd->v4l2_dev = &dw_dev->v4l2_dev;
vfd->lock = &dw_dev->vfd_mutex;
strscpy(vfd->name, DRV_NAME, sizeof(vfd->name));
mutex_init(vfd->lock);
video_set_drvdata(vfd, dw_dev);
return vfd;
}
static int dw100_dump_regs_show(struct seq_file *m, void *private)
{
struct dw100_device *dw_dev = m->private;
int ret;
ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev);
if (ret < 0)
return ret;
ret = dw100_dump_regs(m);
pm_runtime_put_sync(&dw_dev->pdev->dev);
return ret;
}
DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs);
static void dw100_debugfs_init(struct dw100_device *dw_dev)
{
dw_dev->debugfs_root =
debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL);
debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev,
&dw100_dump_regs_fops);
}
static void dw100_debugfs_exit(struct dw100_device *dw_dev)
{
debugfs_remove_recursive(dw_dev->debugfs_root);
}
static int dw100_probe(struct platform_device *pdev)
{
struct dw100_device *dw_dev;
struct video_device *vfd;
int ret, irq;
dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL);
if (!dw_dev)
return -ENOMEM;
dw_dev->pdev = pdev;
ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret);
return ret;
}
dw_dev->num_clks = ret;
dw_dev->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(dw_dev->mmio))
return PTR_ERR(dw_dev->mmio);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
platform_set_drvdata(pdev, dw_dev);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret);
goto err_pm;
}
pm_runtime_put_sync(&pdev->dev);
ret = devm_request_irq(&pdev->dev, irq, dw100_irq_handler, IRQF_ONESHOT,
dev_name(&pdev->dev), dw_dev);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
goto err_pm;
}
ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev);
if (ret)
goto err_pm;
vfd = dw100_init_video_device(dw_dev);
dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops);
if (IS_ERR(dw_dev->m2m_dev)) {
dev_err(&pdev->dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(dw_dev->m2m_dev);
goto err_v4l2;
}
dw_dev->mdev.dev = &pdev->dev;
strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model));
media_device_init(&dw_dev->mdev);
dw_dev->v4l2_dev.mdev = &dw_dev->mdev;
ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
if (ret) {
dev_err(&pdev->dev, "Failed to register video device\n");
goto err_m2m;
}
ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd,
MEDIA_ENT_F_PROC_VIDEO_SCALER);
if (ret) {
dev_err(&pdev->dev, "Failed to init mem2mem media controller\n");
goto error_v4l2;
}
ret = media_device_register(&dw_dev->mdev);
if (ret) {
dev_err(&pdev->dev, "Failed to register mem2mem media device\n");
goto error_m2m_mc;
}
dw100_debugfs_init(dw_dev);
dev_info(&pdev->dev,
"dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num);
return 0;
error_m2m_mc:
v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
error_v4l2:
video_unregister_device(vfd);
err_m2m:
media_device_cleanup(&dw_dev->mdev);
v4l2_m2m_release(dw_dev->m2m_dev);
err_v4l2:
v4l2_device_unregister(&dw_dev->v4l2_dev);
err_pm:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void dw100_remove(struct platform_device *pdev)
{
struct dw100_device *dw_dev = platform_get_drvdata(pdev);
dw100_debugfs_exit(dw_dev);
pm_runtime_disable(&pdev->dev);
media_device_unregister(&dw_dev->mdev);
v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
media_device_cleanup(&dw_dev->mdev);
video_unregister_device(&dw_dev->vfd);
mutex_destroy(dw_dev->vfd.lock);
v4l2_m2m_release(dw_dev->m2m_dev);
v4l2_device_unregister(&dw_dev->v4l2_dev);
}
static int __maybe_unused dw100_runtime_suspend(struct device *dev)
{
struct dw100_device *dw_dev = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks);
return 0;
}
static int __maybe_unused dw100_runtime_resume(struct device *dev)
{
int ret;
struct dw100_device *dw_dev = dev_get_drvdata(dev);
ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks);
if (ret)
return ret;
dw100_hw_reset(dw_dev);
return 0;
}
static const struct dev_pm_ops dw100_pm = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(dw100_runtime_suspend,
dw100_runtime_resume, NULL)
};
static const struct of_device_id dw100_dt_ids[] = {
{ .compatible = "nxp,imx8mp-dw100", .data = NULL },
{ },
};
MODULE_DEVICE_TABLE(of, dw100_dt_ids);
static struct platform_driver dw100_driver = {
.probe = dw100_probe,
.remove_new = dw100_remove,
.driver = {
.name = DRV_NAME,
.pm = &dw100_pm,
.of_match_table = dw100_dt_ids,
},
};
module_platform_driver(dw100_driver);
MODULE_DESCRIPTION("DW100 Hardware dewarper");
MODULE_AUTHOR("Xavier Roumegue <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/platform/nxp/dw100/dw100.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019-2020 NXP
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/types.h>
#include "imx8-isi-core.h"
#include "imx8-isi-regs.h"
#define ISI_DOWNSCALE_THRESHOLD 0x4000
static inline u32 mxc_isi_read(struct mxc_isi_pipe *pipe, u32 reg)
{
return readl(pipe->regs + reg);
}
static inline void mxc_isi_write(struct mxc_isi_pipe *pipe, u32 reg, u32 val)
{
writel(val, pipe->regs + reg);
}
/* -----------------------------------------------------------------------------
* Buffers & M2M operation
*/
void mxc_isi_channel_set_inbuf(struct mxc_isi_pipe *pipe, dma_addr_t dma_addr)
{
mxc_isi_write(pipe, CHNL_IN_BUF_ADDR, lower_32_bits(dma_addr));
if (pipe->isi->pdata->has_36bit_dma)
mxc_isi_write(pipe, CHNL_IN_BUF_XTND_ADDR,
upper_32_bits(dma_addr));
}
void mxc_isi_channel_set_outbuf(struct mxc_isi_pipe *pipe,
const dma_addr_t dma_addrs[3],
enum mxc_isi_buf_id buf_id)
{
int val;
val = mxc_isi_read(pipe, CHNL_OUT_BUF_CTRL);
if (buf_id == MXC_ISI_BUF1) {
mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_Y,
lower_32_bits(dma_addrs[0]));
mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_U,
lower_32_bits(dma_addrs[1]));
mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_V,
lower_32_bits(dma_addrs[2]));
if (pipe->isi->pdata->has_36bit_dma) {
mxc_isi_write(pipe, CHNL_Y_BUF1_XTND_ADDR,
upper_32_bits(dma_addrs[0]));
mxc_isi_write(pipe, CHNL_U_BUF1_XTND_ADDR,
upper_32_bits(dma_addrs[1]));
mxc_isi_write(pipe, CHNL_V_BUF1_XTND_ADDR,
upper_32_bits(dma_addrs[2]));
}
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR;
} else {
mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_Y,
lower_32_bits(dma_addrs[0]));
mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_U,
lower_32_bits(dma_addrs[1]));
mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_V,
lower_32_bits(dma_addrs[2]));
if (pipe->isi->pdata->has_36bit_dma) {
mxc_isi_write(pipe, CHNL_Y_BUF2_XTND_ADDR,
upper_32_bits(dma_addrs[0]));
mxc_isi_write(pipe, CHNL_U_BUF2_XTND_ADDR,
upper_32_bits(dma_addrs[1]));
mxc_isi_write(pipe, CHNL_V_BUF2_XTND_ADDR,
upper_32_bits(dma_addrs[2]));
}
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR;
}
mxc_isi_write(pipe, CHNL_OUT_BUF_CTRL, val);
}
void mxc_isi_channel_m2m_start(struct mxc_isi_pipe *pipe)
{
u32 val;
val = mxc_isi_read(pipe, CHNL_MEM_RD_CTRL);
val &= ~CHNL_MEM_RD_CTRL_READ_MEM;
mxc_isi_write(pipe, CHNL_MEM_RD_CTRL, val);
fsleep(300);
val |= CHNL_MEM_RD_CTRL_READ_MEM;
mxc_isi_write(pipe, CHNL_MEM_RD_CTRL, val);
}
/* -----------------------------------------------------------------------------
* Pipeline configuration
*/
static u32 mxc_isi_channel_scaling_ratio(unsigned int from, unsigned int to,
u32 *dec)
{
unsigned int ratio = from / to;
if (ratio < 2)
*dec = 1;
else if (ratio < 4)
*dec = 2;
else if (ratio < 8)
*dec = 4;
else
*dec = 8;
return min_t(u32, from * 0x1000 / (to * *dec), ISI_DOWNSCALE_THRESHOLD);
}
static void mxc_isi_channel_set_scaling(struct mxc_isi_pipe *pipe,
enum mxc_isi_encoding encoding,
const struct v4l2_area *in_size,
const struct v4l2_area *out_size,
bool *bypass)
{
u32 xscale, yscale;
u32 decx, decy;
u32 val;
dev_dbg(pipe->isi->dev, "input %ux%u, output %ux%u\n",
in_size->width, in_size->height,
out_size->width, out_size->height);
xscale = mxc_isi_channel_scaling_ratio(in_size->width, out_size->width,
&decx);
yscale = mxc_isi_channel_scaling_ratio(in_size->height, out_size->height,
&decy);
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~(CHNL_IMG_CTRL_DEC_X_MASK | CHNL_IMG_CTRL_DEC_Y_MASK |
CHNL_IMG_CTRL_YCBCR_MODE);
val |= CHNL_IMG_CTRL_DEC_X(ilog2(decx))
| CHNL_IMG_CTRL_DEC_Y(ilog2(decy));
/*
* Contrary to what the documentation states, YCBCR_MODE does not
* control conversion between YCbCr and RGB, but whether the scaler
* operates in YUV mode or in RGB mode. It must be set when the scaler
* input is YUV.
*/
if (encoding == MXC_ISI_ENC_YUV)
val |= CHNL_IMG_CTRL_YCBCR_MODE;
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
mxc_isi_write(pipe, CHNL_SCALE_FACTOR,
CHNL_SCALE_FACTOR_Y_SCALE(yscale) |
CHNL_SCALE_FACTOR_X_SCALE(xscale));
mxc_isi_write(pipe, CHNL_SCALE_OFFSET, 0);
mxc_isi_write(pipe, CHNL_SCL_IMG_CFG,
CHNL_SCL_IMG_CFG_HEIGHT(out_size->height) |
CHNL_SCL_IMG_CFG_WIDTH(out_size->width));
*bypass = in_size->height == out_size->height &&
in_size->width == out_size->width;
}
static void mxc_isi_channel_set_crop(struct mxc_isi_pipe *pipe,
const struct v4l2_area *src,
const struct v4l2_rect *dst)
{
u32 val, val0, val1;
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~CHNL_IMG_CTRL_CROP_EN;
if (src->height == dst->height && src->width == dst->width) {
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
return;
}
val |= CHNL_IMG_CTRL_CROP_EN;
val0 = CHNL_CROP_ULC_X(dst->left) | CHNL_CROP_ULC_Y(dst->top);
val1 = CHNL_CROP_LRC_X(dst->width) | CHNL_CROP_LRC_Y(dst->height);
mxc_isi_write(pipe, CHNL_CROP_ULC, val0);
mxc_isi_write(pipe, CHNL_CROP_LRC, val1 + val0);
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
}
/*
* A2,A1, B1, A3, B3, B2,
* C2, C1, D1, C3, D3, D2
*/
static const u32 mxc_isi_yuv2rgb_coeffs[6] = {
/* YUV -> RGB */
0x0000012a, 0x012a0198, 0x0730079c,
0x0204012a, 0x01f00000, 0x01800180
};
static const u32 mxc_isi_rgb2yuv_coeffs[6] = {
/* RGB->YUV */
0x00810041, 0x07db0019, 0x007007b6,
0x07a20070, 0x001007ee, 0x00800080
};
static void mxc_isi_channel_set_csc(struct mxc_isi_pipe *pipe,
enum mxc_isi_encoding in_encoding,
enum mxc_isi_encoding out_encoding,
bool *bypass)
{
static const char * const encodings[] = {
[MXC_ISI_ENC_RAW] = "RAW",
[MXC_ISI_ENC_RGB] = "RGB",
[MXC_ISI_ENC_YUV] = "YUV",
};
const u32 *coeffs;
bool cscen = true;
u32 val;
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~(CHNL_IMG_CTRL_CSC_BYPASS | CHNL_IMG_CTRL_CSC_MODE_MASK);
if (in_encoding == MXC_ISI_ENC_YUV &&
out_encoding == MXC_ISI_ENC_RGB) {
/* YUV2RGB */
coeffs = mxc_isi_yuv2rgb_coeffs;
/* YCbCr enable??? */
val |= CHNL_IMG_CTRL_CSC_MODE(CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB);
} else if (in_encoding == MXC_ISI_ENC_RGB &&
out_encoding == MXC_ISI_ENC_YUV) {
/* RGB2YUV */
coeffs = mxc_isi_rgb2yuv_coeffs;
val |= CHNL_IMG_CTRL_CSC_MODE(CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR);
} else {
/* Bypass CSC */
cscen = false;
val |= CHNL_IMG_CTRL_CSC_BYPASS;
}
dev_dbg(pipe->isi->dev, "CSC: %s -> %s\n",
encodings[in_encoding], encodings[out_encoding]);
if (cscen) {
mxc_isi_write(pipe, CHNL_CSC_COEFF0, coeffs[0]);
mxc_isi_write(pipe, CHNL_CSC_COEFF1, coeffs[1]);
mxc_isi_write(pipe, CHNL_CSC_COEFF2, coeffs[2]);
mxc_isi_write(pipe, CHNL_CSC_COEFF3, coeffs[3]);
mxc_isi_write(pipe, CHNL_CSC_COEFF4, coeffs[4]);
mxc_isi_write(pipe, CHNL_CSC_COEFF5, coeffs[5]);
}
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
*bypass = !cscen;
}
void mxc_isi_channel_set_alpha(struct mxc_isi_pipe *pipe, u8 alpha)
{
u32 val;
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK;
val |= CHNL_IMG_CTRL_GBL_ALPHA_VAL(alpha) |
CHNL_IMG_CTRL_GBL_ALPHA_EN;
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
}
void mxc_isi_channel_set_flip(struct mxc_isi_pipe *pipe, bool hflip, bool vflip)
{
u32 val;
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~(CHNL_IMG_CTRL_VFLIP_EN | CHNL_IMG_CTRL_HFLIP_EN);
if (vflip)
val |= CHNL_IMG_CTRL_VFLIP_EN;
if (hflip)
val |= CHNL_IMG_CTRL_HFLIP_EN;
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
}
static void mxc_isi_channel_set_panic_threshold(struct mxc_isi_pipe *pipe)
{
const struct mxc_isi_set_thd *set_thd = pipe->isi->pdata->set_thd;
u32 val;
val = mxc_isi_read(pipe, CHNL_OUT_BUF_CTRL);
val &= ~(set_thd->panic_set_thd_y.mask);
val |= set_thd->panic_set_thd_y.threshold << set_thd->panic_set_thd_y.offset;
val &= ~(set_thd->panic_set_thd_u.mask);
val |= set_thd->panic_set_thd_u.threshold << set_thd->panic_set_thd_u.offset;
val &= ~(set_thd->panic_set_thd_v.mask);
val |= set_thd->panic_set_thd_v.threshold << set_thd->panic_set_thd_v.offset;
mxc_isi_write(pipe, CHNL_OUT_BUF_CTRL, val);
}
static void mxc_isi_channel_set_control(struct mxc_isi_pipe *pipe,
enum mxc_isi_input_id input,
bool bypass)
{
u32 val;
mutex_lock(&pipe->lock);
val = mxc_isi_read(pipe, CHNL_CTRL);
val &= ~(CHNL_CTRL_CHNL_BYPASS | CHNL_CTRL_CHAIN_BUF_MASK |
CHNL_CTRL_BLANK_PXL_MASK | CHNL_CTRL_SRC_TYPE_MASK |
CHNL_CTRL_MIPI_VC_ID_MASK | CHNL_CTRL_SRC_INPUT_MASK);
/*
* If no scaling or color space conversion is needed, bypass the
* channel.
*/
if (bypass)
val |= CHNL_CTRL_CHNL_BYPASS;
/* Chain line buffers if needed. */
if (pipe->chained)
val |= CHNL_CTRL_CHAIN_BUF(CHNL_CTRL_CHAIN_BUF_2_CHAIN);
val |= CHNL_CTRL_BLANK_PXL(0xff);
/* Input source (including VC configuration for CSI-2) */
if (input == MXC_ISI_INPUT_MEM) {
/*
* The memory input is connected to the last port of the
* crossbar switch, after all pixel link inputs. The SRC_INPUT
* field controls the input selection and must be set
* accordingly, despite being documented as ignored when using
* the memory input in the i.MX8MP reference manual, and
* reserved in the i.MX8MN reference manual.
*/
val |= CHNL_CTRL_SRC_TYPE(CHNL_CTRL_SRC_TYPE_MEMORY);
val |= CHNL_CTRL_SRC_INPUT(pipe->isi->pdata->num_ports);
} else {
val |= CHNL_CTRL_SRC_TYPE(CHNL_CTRL_SRC_TYPE_DEVICE);
val |= CHNL_CTRL_SRC_INPUT(input);
val |= CHNL_CTRL_MIPI_VC_ID(0); /* FIXME: For CSI-2 only */
}
mxc_isi_write(pipe, CHNL_CTRL, val);
mutex_unlock(&pipe->lock);
}
void mxc_isi_channel_config(struct mxc_isi_pipe *pipe,
enum mxc_isi_input_id input,
const struct v4l2_area *in_size,
const struct v4l2_area *scale,
const struct v4l2_rect *crop,
enum mxc_isi_encoding in_encoding,
enum mxc_isi_encoding out_encoding)
{
bool csc_bypass;
bool scaler_bypass;
/* Input frame size */
mxc_isi_write(pipe, CHNL_IMG_CFG,
CHNL_IMG_CFG_HEIGHT(in_size->height) |
CHNL_IMG_CFG_WIDTH(in_size->width));
/* Scaling */
mxc_isi_channel_set_scaling(pipe, in_encoding, in_size, scale,
&scaler_bypass);
mxc_isi_channel_set_crop(pipe, scale, crop);
/* CSC */
mxc_isi_channel_set_csc(pipe, in_encoding, out_encoding, &csc_bypass);
/* Output buffer management */
mxc_isi_channel_set_panic_threshold(pipe);
/* Channel control */
mxc_isi_channel_set_control(pipe, input, csc_bypass && scaler_bypass);
}
void mxc_isi_channel_set_input_format(struct mxc_isi_pipe *pipe,
const struct mxc_isi_format_info *info,
const struct v4l2_pix_format_mplane *format)
{
unsigned int bpl = format->plane_fmt[0].bytesperline;
mxc_isi_write(pipe, CHNL_MEM_RD_CTRL,
CHNL_MEM_RD_CTRL_IMG_TYPE(info->isi_in_format));
mxc_isi_write(pipe, CHNL_IN_BUF_PITCH,
CHNL_IN_BUF_PITCH_LINE_PITCH(bpl));
}
void mxc_isi_channel_set_output_format(struct mxc_isi_pipe *pipe,
const struct mxc_isi_format_info *info,
struct v4l2_pix_format_mplane *format)
{
u32 val;
/* set outbuf format */
dev_dbg(pipe->isi->dev, "output format %p4cc", &format->pixelformat);
val = mxc_isi_read(pipe, CHNL_IMG_CTRL);
val &= ~CHNL_IMG_CTRL_FORMAT_MASK;
val |= CHNL_IMG_CTRL_FORMAT(info->isi_out_format);
mxc_isi_write(pipe, CHNL_IMG_CTRL, val);
/* line pitch */
mxc_isi_write(pipe, CHNL_OUT_BUF_PITCH,
format->plane_fmt[0].bytesperline);
}
/* -----------------------------------------------------------------------------
* IRQ
*/
u32 mxc_isi_channel_irq_status(struct mxc_isi_pipe *pipe, bool clear)
{
u32 status;
status = mxc_isi_read(pipe, CHNL_STS);
if (clear)
mxc_isi_write(pipe, CHNL_STS, status);
return status;
}
void mxc_isi_channel_irq_clear(struct mxc_isi_pipe *pipe)
{
mxc_isi_write(pipe, CHNL_STS, 0xffffffff);
}
static void mxc_isi_channel_irq_enable(struct mxc_isi_pipe *pipe)
{
const struct mxc_isi_ier_reg *ier_reg = pipe->isi->pdata->ier_reg;
u32 val;
val = CHNL_IER_FRM_RCVD_EN |
CHNL_IER_AXI_WR_ERR_U_EN |
CHNL_IER_AXI_WR_ERR_V_EN |
CHNL_IER_AXI_WR_ERR_Y_EN;
/* Y/U/V overflow enable */
val |= ier_reg->oflw_y_buf_en.mask |
ier_reg->oflw_u_buf_en.mask |
ier_reg->oflw_v_buf_en.mask;
/* Y/U/V excess overflow enable */
val |= ier_reg->excs_oflw_y_buf_en.mask |
ier_reg->excs_oflw_u_buf_en.mask |
ier_reg->excs_oflw_v_buf_en.mask;
/* Y/U/V panic enable */
val |= ier_reg->panic_y_buf_en.mask |
ier_reg->panic_u_buf_en.mask |
ier_reg->panic_v_buf_en.mask;
mxc_isi_channel_irq_clear(pipe);
mxc_isi_write(pipe, CHNL_IER, val);
}
static void mxc_isi_channel_irq_disable(struct mxc_isi_pipe *pipe)
{
mxc_isi_write(pipe, CHNL_IER, 0);
}
/* -----------------------------------------------------------------------------
* Init, deinit, enable, disable
*/
static void mxc_isi_channel_sw_reset(struct mxc_isi_pipe *pipe, bool enable_clk)
{
mxc_isi_write(pipe, CHNL_CTRL, CHNL_CTRL_SW_RST);
mdelay(5);
mxc_isi_write(pipe, CHNL_CTRL, enable_clk ? CHNL_CTRL_CLK_EN : 0);
}
static void __mxc_isi_channel_get(struct mxc_isi_pipe *pipe)
{
if (!pipe->use_count++)
mxc_isi_channel_sw_reset(pipe, true);
}
void mxc_isi_channel_get(struct mxc_isi_pipe *pipe)
{
mutex_lock(&pipe->lock);
__mxc_isi_channel_get(pipe);
mutex_unlock(&pipe->lock);
}
static void __mxc_isi_channel_put(struct mxc_isi_pipe *pipe)
{
if (!--pipe->use_count)
mxc_isi_channel_sw_reset(pipe, false);
}
void mxc_isi_channel_put(struct mxc_isi_pipe *pipe)
{
mutex_lock(&pipe->lock);
__mxc_isi_channel_put(pipe);
mutex_unlock(&pipe->lock);
}
void mxc_isi_channel_enable(struct mxc_isi_pipe *pipe)
{
u32 val;
mxc_isi_channel_irq_enable(pipe);
mutex_lock(&pipe->lock);
val = mxc_isi_read(pipe, CHNL_CTRL);
val |= CHNL_CTRL_CHNL_EN;
mxc_isi_write(pipe, CHNL_CTRL, val);
mutex_unlock(&pipe->lock);
}
void mxc_isi_channel_disable(struct mxc_isi_pipe *pipe)
{
u32 val;
mxc_isi_channel_irq_disable(pipe);
mutex_lock(&pipe->lock);
val = mxc_isi_read(pipe, CHNL_CTRL);
val &= ~CHNL_CTRL_CHNL_EN;
mxc_isi_write(pipe, CHNL_CTRL, val);
mutex_unlock(&pipe->lock);
}
/* -----------------------------------------------------------------------------
* Resource management & chaining
*/
int mxc_isi_channel_acquire(struct mxc_isi_pipe *pipe,
mxc_isi_pipe_irq_t irq_handler, bool bypass)
{
u8 resources;
int ret = 0;
mutex_lock(&pipe->lock);
if (pipe->irq_handler) {
ret = -EBUSY;
goto unlock;
}
/*
* Make sure the resources we need are available. The output buffer is
* always needed to operate the channel, the line buffer is needed only
* when the channel isn't in bypass mode.
*/
resources = MXC_ISI_CHANNEL_RES_OUTPUT_BUF
| (!bypass ? MXC_ISI_CHANNEL_RES_LINE_BUF : 0);
if ((pipe->available_res & resources) != resources) {
ret = -EBUSY;
goto unlock;
}
/* Acquire the channel resources. */
pipe->acquired_res = resources;
pipe->available_res &= ~resources;
pipe->irq_handler = irq_handler;
unlock:
mutex_unlock(&pipe->lock);
return ret;
}
void mxc_isi_channel_release(struct mxc_isi_pipe *pipe)
{
mutex_lock(&pipe->lock);
pipe->irq_handler = NULL;
pipe->available_res |= pipe->acquired_res;
pipe->acquired_res = 0;
mutex_unlock(&pipe->lock);
}
/*
* We currently support line buffer chaining only, for handling images with a
* width larger than 2048 pixels.
*
* TODO: Support secondary line buffer for downscaling YUV420 images.
*/
int mxc_isi_channel_chain(struct mxc_isi_pipe *pipe, bool bypass)
{
/* Channel chaining requires both line and output buffer. */
const u8 resources = MXC_ISI_CHANNEL_RES_OUTPUT_BUF
| MXC_ISI_CHANNEL_RES_LINE_BUF;
struct mxc_isi_pipe *chained_pipe = pipe + 1;
int ret = 0;
/*
* If buffer chaining is required, make sure this channel is not the
* last one, otherwise there's no 'next' channel to chain with. This
* should be prevented by checks in the set format handlers, but let's
* be defensive.
*/
if (WARN_ON(pipe->id == pipe->isi->pdata->num_channels - 1))
return -EINVAL;
mutex_lock(&chained_pipe->lock);
/* Safety checks. */
if (WARN_ON(pipe->chained || chained_pipe->chained_res)) {
ret = -EINVAL;
goto unlock;
}
if ((chained_pipe->available_res & resources) != resources) {
ret = -EBUSY;
goto unlock;
}
pipe->chained = true;
chained_pipe->chained_res |= resources;
chained_pipe->available_res &= ~resources;
__mxc_isi_channel_get(chained_pipe);
unlock:
mutex_unlock(&chained_pipe->lock);
return ret;
}
void mxc_isi_channel_unchain(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_pipe *chained_pipe = pipe + 1;
if (!pipe->chained)
return;
pipe->chained = false;
mutex_lock(&chained_pipe->lock);
chained_pipe->available_res |= chained_pipe->chained_res;
chained_pipe->chained_res = 0;
__mxc_isi_channel_put(chained_pipe);
mutex_unlock(&chained_pipe->lock);
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019-2020 NXP
*/
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/types.h>
#include "imx8-isi-core.h"
#include "imx8-isi-regs.h"
static inline u32 mxc_isi_read(struct mxc_isi_pipe *pipe, u32 reg)
{
return readl(pipe->regs + reg);
}
static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)
{
#define MXC_ISI_DEBUG_REG(name) { name, #name }
static const struct {
u32 offset;
const char * const name;
} registers[] = {
MXC_ISI_DEBUG_REG(CHNL_CTRL),
MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL),
MXC_ISI_DEBUG_REG(CHNL_IMG_CFG),
MXC_ISI_DEBUG_REG(CHNL_IER),
MXC_ISI_DEBUG_REG(CHNL_STS),
MXC_ISI_DEBUG_REG(CHNL_SCALE_FACTOR),
MXC_ISI_DEBUG_REG(CHNL_SCALE_OFFSET),
MXC_ISI_DEBUG_REG(CHNL_CROP_ULC),
MXC_ISI_DEBUG_REG(CHNL_CROP_LRC),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF0),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF1),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF2),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF3),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF4),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF5),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_LRC),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_Y),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_U),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_V),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_PITCH),
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_ADDR),
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_PITCH),
MXC_ISI_DEBUG_REG(CHNL_MEM_RD_CTRL),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_Y),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_U),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_V),
MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG),
MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL),
};
struct mxc_isi_pipe *pipe = m->private;
unsigned int i;
if (!pm_runtime_get_if_in_use(pipe->isi->dev))
return 0;
seq_printf(m, "--- ISI pipe %u registers ---\n", pipe->id);
for (i = 0; i < ARRAY_SIZE(registers); ++i)
seq_printf(m, "%20s[0x%02x]: 0x%08x\n",
registers[i].name, registers[i].offset,
mxc_isi_read(pipe, registers[i].offset));
pm_runtime_put(pipe->isi->dev);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mxc_isi_debug_dump_regs);
void mxc_isi_debug_init(struct mxc_isi_dev *isi)
{
unsigned int i;
isi->debugfs_root = debugfs_create_dir(dev_name(isi->dev), NULL);
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
char name[8];
sprintf(name, "pipe%u", pipe->id);
debugfs_create_file(name, 0444, isi->debugfs_root, pipe,
&mxc_isi_debug_dump_regs_fops);
}
}
void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi)
{
debugfs_remove_recursive(isi->debugfs_root);
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019-2023 NXP
*/
#include <linux/regmap.h>
#include <media/mipi-csi2.h>
#include "imx8-isi-core.h"
/* -----------------------------------------------------------------------------
* i.MX8MN and i.MX8MP gasket
*/
#define GASKET_BASE(n) (0x0060 + (n) * 0x30)
#define GASKET_CTRL 0x0000
#define GASKET_CTRL_DATA_TYPE(dt) ((dt) << 8)
#define GASKET_CTRL_DATA_TYPE_MASK (0x3f << 8)
#define GASKET_CTRL_DUAL_COMP_ENABLE BIT(1)
#define GASKET_CTRL_ENABLE BIT(0)
#define GASKET_HSIZE 0x0004
#define GASKET_VSIZE 0x0008
static void mxc_imx8_gasket_enable(struct mxc_isi_dev *isi,
const struct v4l2_mbus_frame_desc *fd,
const struct v4l2_mbus_framefmt *fmt,
const unsigned int port)
{
u32 val;
regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_HSIZE, fmt->width);
regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_VSIZE, fmt->height);
val = GASKET_CTRL_DATA_TYPE(fd->entry[0].bus.csi2.dt);
if (fd->entry[0].bus.csi2.dt == MIPI_CSI2_DT_YUV422_8B)
val |= GASKET_CTRL_DUAL_COMP_ENABLE;
val |= GASKET_CTRL_ENABLE;
regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val);
}
static void mxc_imx8_gasket_disable(struct mxc_isi_dev *isi,
const unsigned int port)
{
regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, 0);
}
const struct mxc_gasket_ops mxc_imx8_gasket_ops = {
.enable = mxc_imx8_gasket_enable,
.disable = mxc_imx8_gasket_disable,
};
/* -----------------------------------------------------------------------------
* i.MX93 gasket
*/
#define DISP_MIX_CAMERA_MUX 0x30
#define DISP_MIX_CAMERA_MUX_DATA_TYPE(x) (((x) & 0x3f) << 3)
#define DISP_MIX_CAMERA_MUX_GASKET_ENABLE BIT(16)
static void mxc_imx93_gasket_enable(struct mxc_isi_dev *isi,
const struct v4l2_mbus_frame_desc *fd,
const struct v4l2_mbus_framefmt *fmt,
const unsigned int port)
{
u32 val;
val = DISP_MIX_CAMERA_MUX_DATA_TYPE(fd->entry[0].bus.csi2.dt);
val |= DISP_MIX_CAMERA_MUX_GASKET_ENABLE;
regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val);
}
static void mxc_imx93_gasket_disable(struct mxc_isi_dev *isi,
unsigned int port)
{
regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, 0);
}
const struct mxc_gasket_ops mxc_imx93_gasket_ops = {
.enable = mxc_imx93_gasket_enable,
.disable = mxc_imx93_gasket_disable,
};
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-gasket.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019-2020 NXP
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/media-device.h>
#include <media/v4l2-async.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mc.h>
#include "imx8-isi-core.h"
/* -----------------------------------------------------------------------------
* V4L2 async subdevs
*/
struct mxc_isi_async_subdev {
struct v4l2_async_connection asd;
unsigned int port;
};
static inline struct mxc_isi_async_subdev *
asd_to_mxc_isi_async_subdev(struct v4l2_async_connection *asd)
{
return container_of(asd, struct mxc_isi_async_subdev, asd);
};
static inline struct mxc_isi_dev *
notifier_to_mxc_isi_dev(struct v4l2_async_notifier *n)
{
return container_of(n, struct mxc_isi_dev, notifier);
};
static int mxc_isi_async_notifier_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *sd,
struct v4l2_async_connection *asc)
{
const unsigned int link_flags = MEDIA_LNK_FL_IMMUTABLE
| MEDIA_LNK_FL_ENABLED;
struct mxc_isi_dev *isi = notifier_to_mxc_isi_dev(notifier);
struct mxc_isi_async_subdev *masd = asd_to_mxc_isi_async_subdev(asc);
struct media_pad *pad = &isi->crossbar.pads[masd->port];
struct device_link *link;
dev_dbg(isi->dev, "Bound subdev %s to crossbar input %u\n", sd->name,
masd->port);
/*
* Enforce suspend/resume ordering between the source (supplier) and
* the ISI (consumer). The source will be suspended before and resume
* after the ISI.
*/
link = device_link_add(isi->dev, sd->dev, DL_FLAG_STATELESS);
if (!link) {
dev_err(isi->dev,
"Failed to create device link to source %s\n", sd->name);
return -EINVAL;
}
return v4l2_create_fwnode_links_to_pad(sd, pad, link_flags);
}
static int mxc_isi_async_notifier_complete(struct v4l2_async_notifier *notifier)
{
struct mxc_isi_dev *isi = notifier_to_mxc_isi_dev(notifier);
int ret;
dev_dbg(isi->dev, "All subdevs bound\n");
ret = v4l2_device_register_subdev_nodes(&isi->v4l2_dev);
if (ret < 0) {
dev_err(isi->dev,
"Failed to register subdev nodes: %d\n", ret);
return ret;
}
return media_device_register(&isi->media_dev);
}
static const struct v4l2_async_notifier_operations mxc_isi_async_notifier_ops = {
.bound = mxc_isi_async_notifier_bound,
.complete = mxc_isi_async_notifier_complete,
};
static int mxc_isi_pipe_register(struct mxc_isi_pipe *pipe)
{
int ret;
ret = v4l2_device_register_subdev(&pipe->isi->v4l2_dev, &pipe->sd);
if (ret < 0)
return ret;
return mxc_isi_video_register(pipe, &pipe->isi->v4l2_dev);
}
static void mxc_isi_pipe_unregister(struct mxc_isi_pipe *pipe)
{
mxc_isi_video_unregister(pipe);
}
static int mxc_isi_v4l2_init(struct mxc_isi_dev *isi)
{
struct fwnode_handle *node = dev_fwnode(isi->dev);
struct media_device *media_dev = &isi->media_dev;
struct v4l2_device *v4l2_dev = &isi->v4l2_dev;
unsigned int i;
int ret;
/* Initialize the media device. */
strscpy(media_dev->model, "FSL Capture Media Device",
sizeof(media_dev->model));
media_dev->dev = isi->dev;
media_device_init(media_dev);
/* Initialize and register the V4L2 device. */
v4l2_dev->mdev = media_dev;
strscpy(v4l2_dev->name, "mx8-img-md", sizeof(v4l2_dev->name));
ret = v4l2_device_register(isi->dev, v4l2_dev);
if (ret < 0) {
dev_err(isi->dev,
"Failed to register V4L2 device: %d\n", ret);
goto err_media;
}
/* Register the crossbar switch subdev. */
ret = mxc_isi_crossbar_register(&isi->crossbar);
if (ret < 0) {
dev_err(isi->dev, "Failed to register crossbar: %d\n", ret);
goto err_v4l2;
}
/* Register the pipeline subdevs and link them to the crossbar switch. */
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
ret = mxc_isi_pipe_register(pipe);
if (ret < 0) {
dev_err(isi->dev, "Failed to register pipe%u: %d\n", i,
ret);
goto err_v4l2;
}
ret = media_create_pad_link(&isi->crossbar.sd.entity,
isi->crossbar.num_sinks + i,
&pipe->sd.entity,
MXC_ISI_PIPE_PAD_SINK,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret < 0)
goto err_v4l2;
}
/* Register the M2M device. */
ret = mxc_isi_m2m_register(isi, v4l2_dev);
if (ret < 0) {
dev_err(isi->dev, "Failed to register M2M device: %d\n", ret);
goto err_v4l2;
}
/* Initialize, fill and register the async notifier. */
v4l2_async_nf_init(&isi->notifier, v4l2_dev);
isi->notifier.ops = &mxc_isi_async_notifier_ops;
for (i = 0; i < isi->pdata->num_ports; ++i) {
struct mxc_isi_async_subdev *masd;
struct fwnode_handle *ep;
ep = fwnode_graph_get_endpoint_by_id(node, i, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep)
continue;
masd = v4l2_async_nf_add_fwnode_remote(&isi->notifier, ep,
struct mxc_isi_async_subdev);
fwnode_handle_put(ep);
if (IS_ERR(masd)) {
ret = PTR_ERR(masd);
goto err_m2m;
}
masd->port = i;
}
ret = v4l2_async_nf_register(&isi->notifier);
if (ret < 0) {
dev_err(isi->dev,
"Failed to register async notifier: %d\n", ret);
goto err_m2m;
}
return 0;
err_m2m:
mxc_isi_m2m_unregister(isi);
v4l2_async_nf_cleanup(&isi->notifier);
err_v4l2:
v4l2_device_unregister(v4l2_dev);
err_media:
media_device_cleanup(media_dev);
return ret;
}
static void mxc_isi_v4l2_cleanup(struct mxc_isi_dev *isi)
{
unsigned int i;
v4l2_async_nf_unregister(&isi->notifier);
v4l2_async_nf_cleanup(&isi->notifier);
v4l2_device_unregister(&isi->v4l2_dev);
media_device_unregister(&isi->media_dev);
mxc_isi_m2m_unregister(isi);
for (i = 0; i < isi->pdata->num_channels; ++i)
mxc_isi_pipe_unregister(&isi->pipes[i]);
mxc_isi_crossbar_unregister(&isi->crossbar);
media_device_cleanup(&isi->media_dev);
}
/* -----------------------------------------------------------------------------
* Device information
*/
/* Panic will assert when the buffers are 50% full */
/* For i.MX8QXP C0 and i.MX8MN ISI IER version */
static const struct mxc_isi_ier_reg mxc_imx8_isi_ier_v1 = {
.oflw_y_buf_en = { .offset = 19, .mask = 0x80000 },
.oflw_u_buf_en = { .offset = 21, .mask = 0x200000 },
.oflw_v_buf_en = { .offset = 23, .mask = 0x800000 },
.panic_y_buf_en = {.offset = 20, .mask = 0x100000 },
.panic_u_buf_en = {.offset = 22, .mask = 0x400000 },
.panic_v_buf_en = {.offset = 24, .mask = 0x1000000 },
};
/* For i.MX8MP ISI IER version */
static const struct mxc_isi_ier_reg mxc_imx8_isi_ier_v2 = {
.oflw_y_buf_en = { .offset = 18, .mask = 0x40000 },
.oflw_u_buf_en = { .offset = 20, .mask = 0x100000 },
.oflw_v_buf_en = { .offset = 22, .mask = 0x400000 },
.panic_y_buf_en = {.offset = 19, .mask = 0x80000 },
.panic_u_buf_en = {.offset = 21, .mask = 0x200000 },
.panic_v_buf_en = {.offset = 23, .mask = 0x800000 },
};
/* Panic will assert when the buffers are 50% full */
static const struct mxc_isi_set_thd mxc_imx8_isi_thd_v1 = {
.panic_set_thd_y = { .mask = 0x0000f, .offset = 0, .threshold = 0x7 },
.panic_set_thd_u = { .mask = 0x00f00, .offset = 8, .threshold = 0x7 },
.panic_set_thd_v = { .mask = 0xf0000, .offset = 16, .threshold = 0x7 },
};
static const struct clk_bulk_data mxc_imx8mn_clks[] = {
{ .id = "axi" },
{ .id = "apb" },
};
static const struct mxc_isi_plat_data mxc_imx8mn_data = {
.model = MXC_ISI_IMX8MN,
.num_ports = 1,
.num_channels = 1,
.reg_offset = 0,
.ier_reg = &mxc_imx8_isi_ier_v1,
.set_thd = &mxc_imx8_isi_thd_v1,
.clks = mxc_imx8mn_clks,
.num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
.buf_active_reverse = false,
.gasket_ops = &mxc_imx8_gasket_ops,
.has_36bit_dma = false,
};
static const struct mxc_isi_plat_data mxc_imx8mp_data = {
.model = MXC_ISI_IMX8MP,
.num_ports = 2,
.num_channels = 2,
.reg_offset = 0x2000,
.ier_reg = &mxc_imx8_isi_ier_v2,
.set_thd = &mxc_imx8_isi_thd_v1,
.clks = mxc_imx8mn_clks,
.num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
.buf_active_reverse = true,
.gasket_ops = &mxc_imx8_gasket_ops,
.has_36bit_dma = true,
};
static const struct mxc_isi_plat_data mxc_imx93_data = {
.model = MXC_ISI_IMX93,
.num_ports = 1,
.num_channels = 1,
.reg_offset = 0,
.ier_reg = &mxc_imx8_isi_ier_v2,
.set_thd = &mxc_imx8_isi_thd_v1,
.clks = mxc_imx8mn_clks,
.num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
.buf_active_reverse = true,
.gasket_ops = &mxc_imx93_gasket_ops,
.has_36bit_dma = false,
};
/* -----------------------------------------------------------------------------
* Power management
*/
static int mxc_isi_pm_suspend(struct device *dev)
{
struct mxc_isi_dev *isi = dev_get_drvdata(dev);
unsigned int i;
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
mxc_isi_video_suspend(pipe);
}
return pm_runtime_force_suspend(dev);
}
static int mxc_isi_pm_resume(struct device *dev)
{
struct mxc_isi_dev *isi = dev_get_drvdata(dev);
unsigned int i;
int err = 0;
int ret;
ret = pm_runtime_force_resume(dev);
if (ret < 0)
return ret;
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
ret = mxc_isi_video_resume(pipe);
if (ret) {
dev_err(dev, "Failed to resume pipeline %u (%d)\n", i,
ret);
/*
* Record the last error as it's as meaningful as any,
* and continue resuming the other pipelines.
*/
err = ret;
}
}
return err;
}
static int mxc_isi_runtime_suspend(struct device *dev)
{
struct mxc_isi_dev *isi = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(isi->pdata->num_clks, isi->clks);
return 0;
}
static int mxc_isi_runtime_resume(struct device *dev)
{
struct mxc_isi_dev *isi = dev_get_drvdata(dev);
int ret;
ret = clk_bulk_prepare_enable(isi->pdata->num_clks, isi->clks);
if (ret) {
dev_err(dev, "Failed to enable clocks (%d)\n", ret);
return ret;
}
return 0;
}
static const struct dev_pm_ops mxc_isi_pm_ops = {
SYSTEM_SLEEP_PM_OPS(mxc_isi_pm_suspend, mxc_isi_pm_resume)
RUNTIME_PM_OPS(mxc_isi_runtime_suspend, mxc_isi_runtime_resume, NULL)
};
/* -----------------------------------------------------------------------------
* Probe, remove & driver
*/
static int mxc_isi_clk_get(struct mxc_isi_dev *isi)
{
unsigned int size = isi->pdata->num_clks
* sizeof(*isi->clks);
int ret;
isi->clks = devm_kmalloc(isi->dev, size, GFP_KERNEL);
if (!isi->clks)
return -ENOMEM;
memcpy(isi->clks, isi->pdata->clks, size);
ret = devm_clk_bulk_get(isi->dev, isi->pdata->num_clks,
isi->clks);
if (ret < 0) {
dev_err(isi->dev, "Failed to acquire clocks: %d\n",
ret);
return ret;
}
return 0;
}
static int mxc_isi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mxc_isi_dev *isi;
unsigned int dma_size;
unsigned int i;
int ret = 0;
isi = devm_kzalloc(dev, sizeof(*isi), GFP_KERNEL);
if (!isi)
return -ENOMEM;
isi->dev = dev;
platform_set_drvdata(pdev, isi);
isi->pdata = of_device_get_match_data(dev);
isi->pipes = kcalloc(isi->pdata->num_channels, sizeof(isi->pipes[0]),
GFP_KERNEL);
if (!isi->pipes)
return -ENOMEM;
ret = mxc_isi_clk_get(isi);
if (ret < 0) {
dev_err(dev, "Failed to get clocks\n");
return ret;
}
isi->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(isi->regs)) {
dev_err(dev, "Failed to get ISI register map\n");
return PTR_ERR(isi->regs);
}
if (isi->pdata->gasket_ops) {
isi->gasket = syscon_regmap_lookup_by_phandle(dev->of_node,
"fsl,blk-ctrl");
if (IS_ERR(isi->gasket)) {
ret = PTR_ERR(isi->gasket);
dev_err(dev, "failed to get gasket: %d\n", ret);
return ret;
}
}
dma_size = isi->pdata->has_36bit_dma ? 36 : 32;
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_size));
if (ret) {
dev_err(dev, "failed to set DMA mask\n");
return ret;
}
pm_runtime_enable(dev);
ret = mxc_isi_crossbar_init(isi);
if (ret) {
dev_err(dev, "Failed to initialize crossbar: %d\n", ret);
goto err_pm;
}
for (i = 0; i < isi->pdata->num_channels; ++i) {
ret = mxc_isi_pipe_init(isi, i);
if (ret < 0) {
dev_err(dev, "Failed to initialize pipe%u: %d\n", i,
ret);
goto err_xbar;
}
}
ret = mxc_isi_v4l2_init(isi);
if (ret < 0) {
dev_err(dev, "Failed to initialize V4L2: %d\n", ret);
goto err_xbar;
}
mxc_isi_debug_init(isi);
return 0;
err_xbar:
mxc_isi_crossbar_cleanup(&isi->crossbar);
err_pm:
pm_runtime_disable(isi->dev);
return ret;
}
static int mxc_isi_remove(struct platform_device *pdev)
{
struct mxc_isi_dev *isi = platform_get_drvdata(pdev);
unsigned int i;
mxc_isi_debug_cleanup(isi);
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
mxc_isi_pipe_cleanup(pipe);
}
mxc_isi_crossbar_cleanup(&isi->crossbar);
mxc_isi_v4l2_cleanup(isi);
pm_runtime_disable(isi->dev);
return 0;
}
static const struct of_device_id mxc_isi_of_match[] = {
{ .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
{ .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data },
{ .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mxc_isi_of_match);
static struct platform_driver mxc_isi_driver = {
.probe = mxc_isi_probe,
.remove = mxc_isi_remove,
.driver = {
.of_match_table = mxc_isi_of_match,
.name = MXC_ISI_DRIVER_NAME,
.pm = pm_ptr(&mxc_isi_pm_ops),
}
};
module_platform_driver(mxc_isi_driver);
MODULE_ALIAS("ISI");
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("IMX8 Image Sensing Interface driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ISI V4L2 memory to memory driver for i.MX8QXP/QM platform
*
* ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
* used to process image from camera sensor or memory to memory or DC
*
* Copyright (c) 2019 NXP Semiconductor
*/
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/minmax.h>
#include <linux/mutex.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include "imx8-isi-core.h"
struct mxc_isi_m2m_buffer {
struct v4l2_m2m_buffer buf;
dma_addr_t dma_addrs[3];
};
struct mxc_isi_m2m_ctx_queue_data {
struct v4l2_pix_format_mplane format;
const struct mxc_isi_format_info *info;
u32 sequence;
};
struct mxc_isi_m2m_ctx {
struct v4l2_fh fh;
struct mxc_isi_m2m *m2m;
/* Protects the m2m vb2 queues */
struct mutex vb2_lock;
struct {
struct mxc_isi_m2m_ctx_queue_data out;
struct mxc_isi_m2m_ctx_queue_data cap;
} queues;
struct {
struct v4l2_ctrl_handler handler;
unsigned int alpha;
bool hflip;
bool vflip;
} ctrls;
bool chained;
};
static inline struct mxc_isi_m2m_buffer *
to_isi_m2m_buffer(struct vb2_v4l2_buffer *buf)
{
return container_of(buf, struct mxc_isi_m2m_buffer, buf.vb);
}
static inline struct mxc_isi_m2m_ctx *to_isi_m2m_ctx(struct v4l2_fh *fh)
{
return container_of(fh, struct mxc_isi_m2m_ctx, fh);
}
static inline struct mxc_isi_m2m_ctx_queue_data *
mxc_isi_m2m_ctx_qdata(struct mxc_isi_m2m_ctx *ctx, enum v4l2_buf_type type)
{
if (V4L2_TYPE_IS_OUTPUT(type))
return &ctx->queues.out;
else
return &ctx->queues.cap;
}
/* -----------------------------------------------------------------------------
* V4L2 M2M device operations
*/
static void mxc_isi_m2m_frame_write_done(struct mxc_isi_pipe *pipe, u32 status)
{
struct mxc_isi_m2m *m2m = &pipe->isi->m2m;
struct vb2_v4l2_buffer *src_vbuf, *dst_vbuf;
struct mxc_isi_m2m_ctx *ctx;
ctx = v4l2_m2m_get_curr_priv(m2m->m2m_dev);
if (!ctx) {
dev_err(m2m->isi->dev,
"Instance released before the end of transaction\n");
return;
}
src_vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
dst_vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_copy_metadata(src_vbuf, dst_vbuf, false);
src_vbuf->sequence = ctx->queues.out.sequence++;
dst_vbuf->sequence = ctx->queues.cap.sequence++;
v4l2_m2m_buf_done(src_vbuf, VB2_BUF_STATE_DONE);
v4l2_m2m_buf_done(dst_vbuf, VB2_BUF_STATE_DONE);
v4l2_m2m_job_finish(m2m->m2m_dev, ctx->fh.m2m_ctx);
}
static void mxc_isi_m2m_device_run(void *priv)
{
struct mxc_isi_m2m_ctx *ctx = priv;
struct mxc_isi_m2m *m2m = ctx->m2m;
struct vb2_v4l2_buffer *src_vbuf, *dst_vbuf;
struct mxc_isi_m2m_buffer *src_buf, *dst_buf;
mxc_isi_channel_disable(m2m->pipe);
mutex_lock(&m2m->lock);
/* If the context has changed, reconfigure the channel. */
if (m2m->last_ctx != ctx) {
const struct v4l2_area in_size = {
.width = ctx->queues.out.format.width,
.height = ctx->queues.out.format.height,
};
const struct v4l2_area scale = {
.width = ctx->queues.cap.format.width,
.height = ctx->queues.cap.format.height,
};
const struct v4l2_rect crop = {
.width = ctx->queues.cap.format.width,
.height = ctx->queues.cap.format.height,
};
mxc_isi_channel_config(m2m->pipe, MXC_ISI_INPUT_MEM,
&in_size, &scale, &crop,
ctx->queues.out.info->encoding,
ctx->queues.cap.info->encoding);
mxc_isi_channel_set_input_format(m2m->pipe,
ctx->queues.out.info,
&ctx->queues.out.format);
mxc_isi_channel_set_output_format(m2m->pipe,
ctx->queues.cap.info,
&ctx->queues.cap.format);
m2m->last_ctx = ctx;
}
mutex_unlock(&m2m->lock);
mutex_lock(ctx->ctrls.handler.lock);
mxc_isi_channel_set_alpha(m2m->pipe, ctx->ctrls.alpha);
mxc_isi_channel_set_flip(m2m->pipe, ctx->ctrls.hflip, ctx->ctrls.vflip);
mutex_unlock(ctx->ctrls.handler.lock);
src_vbuf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_vbuf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
src_buf = to_isi_m2m_buffer(src_vbuf);
dst_buf = to_isi_m2m_buffer(dst_vbuf);
mxc_isi_channel_set_inbuf(m2m->pipe, src_buf->dma_addrs[0]);
mxc_isi_channel_set_outbuf(m2m->pipe, dst_buf->dma_addrs, MXC_ISI_BUF1);
mxc_isi_channel_set_outbuf(m2m->pipe, dst_buf->dma_addrs, MXC_ISI_BUF2);
mxc_isi_channel_enable(m2m->pipe);
mxc_isi_channel_m2m_start(m2m->pipe);
}
static const struct v4l2_m2m_ops mxc_isi_m2m_ops = {
.device_run = mxc_isi_m2m_device_run,
};
/* -----------------------------------------------------------------------------
* videobuf2 queue operations
*/
static int mxc_isi_m2m_vb2_queue_setup(struct vb2_queue *q,
unsigned int *num_buffers,
unsigned int *num_planes,
unsigned int sizes[],
struct device *alloc_devs[])
{
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(q);
const struct mxc_isi_m2m_ctx_queue_data *qdata =
mxc_isi_m2m_ctx_qdata(ctx, q->type);
return mxc_isi_video_queue_setup(&qdata->format, qdata->info,
num_buffers, num_planes, sizes);
}
static int mxc_isi_m2m_vb2_buffer_init(struct vb2_buffer *vb2)
{
struct vb2_queue *vq = vb2->vb2_queue;
struct mxc_isi_m2m_buffer *buf = to_isi_m2m_buffer(to_vb2_v4l2_buffer(vb2));
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(vb2->vb2_queue);
const struct mxc_isi_m2m_ctx_queue_data *qdata =
mxc_isi_m2m_ctx_qdata(ctx, vq->type);
mxc_isi_video_buffer_init(vb2, buf->dma_addrs, qdata->info,
&qdata->format);
return 0;
}
static int mxc_isi_m2m_vb2_buffer_prepare(struct vb2_buffer *vb2)
{
struct vb2_queue *vq = vb2->vb2_queue;
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(vq);
const struct mxc_isi_m2m_ctx_queue_data *qdata =
mxc_isi_m2m_ctx_qdata(ctx, vq->type);
return mxc_isi_video_buffer_prepare(ctx->m2m->isi, vb2, qdata->info,
&qdata->format);
}
static void mxc_isi_m2m_vb2_buffer_queue(struct vb2_buffer *vb2)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(vb2->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static int mxc_isi_m2m_vb2_start_streaming(struct vb2_queue *q,
unsigned int count)
{
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(q);
struct mxc_isi_m2m_ctx_queue_data *qdata =
mxc_isi_m2m_ctx_qdata(ctx, q->type);
qdata->sequence = 0;
return 0;
}
static void mxc_isi_m2m_vb2_stop_streaming(struct vb2_queue *q)
{
struct mxc_isi_m2m_ctx *ctx = vb2_get_drv_priv(q);
struct vb2_v4l2_buffer *vbuf;
for (;;) {
if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
else
vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (!vbuf)
break;
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
}
}
static const struct vb2_ops mxc_isi_m2m_vb2_qops = {
.queue_setup = mxc_isi_m2m_vb2_queue_setup,
.buf_init = mxc_isi_m2m_vb2_buffer_init,
.buf_prepare = mxc_isi_m2m_vb2_buffer_prepare,
.buf_queue = mxc_isi_m2m_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = mxc_isi_m2m_vb2_start_streaming,
.stop_streaming = mxc_isi_m2m_vb2_stop_streaming,
};
static int mxc_isi_m2m_queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct mxc_isi_m2m_ctx *ctx = priv;
struct mxc_isi_m2m *m2m = ctx->m2m;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct mxc_isi_m2m_buffer);
src_vq->ops = &mxc_isi_m2m_vb2_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->vb2_lock;
src_vq->dev = m2m->isi->dev;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct mxc_isi_m2m_buffer);
dst_vq->ops = &mxc_isi_m2m_vb2_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->vb2_lock;
dst_vq->dev = m2m->isi->dev;
return vb2_queue_init(dst_vq);
}
/* -----------------------------------------------------------------------------
* V4L2 controls
*/
static inline struct mxc_isi_m2m_ctx *
ctrl_to_mxc_isi_m2m_ctx(struct v4l2_ctrl *ctrl)
{
return container_of(ctrl->handler, struct mxc_isi_m2m_ctx, ctrls.handler);
}
static int mxc_isi_m2m_ctx_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct mxc_isi_m2m_ctx *ctx = ctrl_to_mxc_isi_m2m_ctx(ctrl);
switch (ctrl->id) {
case V4L2_CID_HFLIP:
ctx->ctrls.hflip = ctrl->val;
break;
case V4L2_CID_VFLIP:
ctx->ctrls.vflip = ctrl->val;
break;
case V4L2_CID_ALPHA_COMPONENT:
ctx->ctrls.alpha = ctrl->val;
break;
}
return 0;
}
static const struct v4l2_ctrl_ops mxc_isi_m2m_ctx_ctrl_ops = {
.s_ctrl = mxc_isi_m2m_ctx_s_ctrl,
};
static int mxc_isi_m2m_ctx_ctrls_create(struct mxc_isi_m2m_ctx *ctx)
{
struct v4l2_ctrl_handler *handler = &ctx->ctrls.handler;
int ret;
v4l2_ctrl_handler_init(handler, 3);
v4l2_ctrl_new_std(handler, &mxc_isi_m2m_ctx_ctrl_ops,
V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
v4l2_ctrl_new_std(handler, &mxc_isi_m2m_ctx_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(handler, &mxc_isi_m2m_ctx_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
if (handler->error) {
ret = handler->error;
v4l2_ctrl_handler_free(handler);
return ret;
}
ctx->fh.ctrl_handler = handler;
return 0;
}
static void mxc_isi_m2m_ctx_ctrls_delete(struct mxc_isi_m2m_ctx *ctx)
{
v4l2_ctrl_handler_free(&ctx->ctrls.handler);
}
/* -----------------------------------------------------------------------------
* V4L2 ioctls
*/
static int mxc_isi_m2m_querycap(struct file *file, void *fh,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MXC_ISI_DRIVER_NAME, sizeof(cap->driver));
strscpy(cap->card, MXC_ISI_M2M, sizeof(cap->card));
cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
return 0;
}
static int mxc_isi_m2m_enum_fmt_vid(struct file *file, void *fh,
struct v4l2_fmtdesc *f)
{
const enum mxc_isi_video_type type =
f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ?
MXC_ISI_VIDEO_M2M_OUT : MXC_ISI_VIDEO_M2M_CAP;
const struct mxc_isi_format_info *info;
info = mxc_isi_format_enum(f->index, type);
if (!info)
return -EINVAL;
f->pixelformat = info->fourcc;
f->flags |= V4L2_FMT_FLAG_CSC_COLORSPACE | V4L2_FMT_FLAG_CSC_YCBCR_ENC
| V4L2_FMT_FLAG_CSC_QUANTIZATION | V4L2_FMT_FLAG_CSC_XFER_FUNC;
return 0;
}
static const struct mxc_isi_format_info *
__mxc_isi_m2m_try_fmt_vid(struct mxc_isi_m2m_ctx *ctx,
struct v4l2_pix_format_mplane *pix,
const enum mxc_isi_video_type type)
{
if (type == MXC_ISI_VIDEO_M2M_CAP) {
/* Downscaling only */
pix->width = min(pix->width, ctx->queues.out.format.width);
pix->height = min(pix->height, ctx->queues.out.format.height);
}
return mxc_isi_format_try(ctx->m2m->pipe, pix, type);
}
static int mxc_isi_m2m_try_fmt_vid(struct file *file, void *fh,
struct v4l2_format *f)
{
const enum mxc_isi_video_type type =
f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ?
MXC_ISI_VIDEO_M2M_OUT : MXC_ISI_VIDEO_M2M_CAP;
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(fh);
__mxc_isi_m2m_try_fmt_vid(ctx, &f->fmt.pix_mp, type);
return 0;
}
static int mxc_isi_m2m_g_fmt_vid(struct file *file, void *fh,
struct v4l2_format *f)
{
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(fh);
const struct mxc_isi_m2m_ctx_queue_data *qdata =
mxc_isi_m2m_ctx_qdata(ctx, f->type);
f->fmt.pix_mp = qdata->format;
return 0;
}
static int mxc_isi_m2m_s_fmt_vid(struct file *file, void *fh,
struct v4l2_format *f)
{
const enum mxc_isi_video_type type =
f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ?
MXC_ISI_VIDEO_M2M_OUT : MXC_ISI_VIDEO_M2M_CAP;
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(fh);
struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
const struct mxc_isi_format_info *info;
struct vb2_queue *vq;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
if (vb2_is_busy(vq))
return -EBUSY;
info = __mxc_isi_m2m_try_fmt_vid(ctx, pix, type);
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
ctx->queues.out.format = *pix;
ctx->queues.out.info = info;
}
/*
* Always set the format on the capture side, due to either format
* propagation or direct setting.
*/
ctx->queues.cap.format = *pix;
ctx->queues.cap.info = info;
return 0;
}
static int mxc_isi_m2m_streamon(struct file *file, void *fh,
enum v4l2_buf_type type)
{
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(fh);
const struct v4l2_pix_format_mplane *out_pix = &ctx->queues.out.format;
const struct v4l2_pix_format_mplane *cap_pix = &ctx->queues.cap.format;
const struct mxc_isi_format_info *cap_info = ctx->queues.cap.info;
const struct mxc_isi_format_info *out_info = ctx->queues.out.info;
struct mxc_isi_m2m *m2m = ctx->m2m;
bool bypass;
int ret;
mutex_lock(&m2m->lock);
if (m2m->usage_count == INT_MAX) {
ret = -EOVERFLOW;
goto unlock;
}
bypass = cap_pix->width == out_pix->width &&
cap_pix->height == out_pix->height &&
cap_info->encoding == out_info->encoding;
/*
* Acquire the pipe and initialize the channel with the first user of
* the M2M device.
*/
if (m2m->usage_count == 0) {
ret = mxc_isi_channel_acquire(m2m->pipe,
&mxc_isi_m2m_frame_write_done,
bypass);
if (ret)
goto unlock;
mxc_isi_channel_get(m2m->pipe);
}
m2m->usage_count++;
/*
* Allocate resources for the channel, counting how many users require
* buffer chaining.
*/
if (!ctx->chained && out_pix->width > MXC_ISI_MAX_WIDTH_UNCHAINED) {
ret = mxc_isi_channel_chain(m2m->pipe, bypass);
if (ret)
goto deinit;
m2m->chained_count++;
ctx->chained = true;
}
/*
* Drop the lock to start the stream, as the .device_run() operation
* needs to acquire it.
*/
mutex_unlock(&m2m->lock);
ret = v4l2_m2m_ioctl_streamon(file, fh, type);
if (ret) {
/* Reacquire the lock for the cleanup path. */
mutex_lock(&m2m->lock);
goto unchain;
}
return 0;
unchain:
if (ctx->chained && --m2m->chained_count == 0)
mxc_isi_channel_unchain(m2m->pipe);
ctx->chained = false;
deinit:
if (--m2m->usage_count == 0) {
mxc_isi_channel_put(m2m->pipe);
mxc_isi_channel_release(m2m->pipe);
}
unlock:
mutex_unlock(&m2m->lock);
return ret;
}
static int mxc_isi_m2m_streamoff(struct file *file, void *fh,
enum v4l2_buf_type type)
{
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(fh);
struct mxc_isi_m2m *m2m = ctx->m2m;
v4l2_m2m_ioctl_streamoff(file, fh, type);
mutex_lock(&m2m->lock);
/*
* If the last context is this one, reset it to make sure the device
* will be reconfigured when streaming is restarted.
*/
if (m2m->last_ctx == ctx)
m2m->last_ctx = NULL;
/* Free the channel resources if this is the last chained context. */
if (ctx->chained && --m2m->chained_count == 0)
mxc_isi_channel_unchain(m2m->pipe);
ctx->chained = false;
/* Turn off the light with the last user. */
if (--m2m->usage_count == 0) {
mxc_isi_channel_disable(m2m->pipe);
mxc_isi_channel_put(m2m->pipe);
mxc_isi_channel_release(m2m->pipe);
}
WARN_ON(m2m->usage_count < 0);
mutex_unlock(&m2m->lock);
return 0;
}
static const struct v4l2_ioctl_ops mxc_isi_m2m_ioctl_ops = {
.vidioc_querycap = mxc_isi_m2m_querycap,
.vidioc_enum_fmt_vid_cap = mxc_isi_m2m_enum_fmt_vid,
.vidioc_enum_fmt_vid_out = mxc_isi_m2m_enum_fmt_vid,
.vidioc_g_fmt_vid_cap_mplane = mxc_isi_m2m_g_fmt_vid,
.vidioc_g_fmt_vid_out_mplane = mxc_isi_m2m_g_fmt_vid,
.vidioc_s_fmt_vid_cap_mplane = mxc_isi_m2m_s_fmt_vid,
.vidioc_s_fmt_vid_out_mplane = mxc_isi_m2m_s_fmt_vid,
.vidioc_try_fmt_vid_cap_mplane = mxc_isi_m2m_try_fmt_vid,
.vidioc_try_fmt_vid_out_mplane = mxc_isi_m2m_try_fmt_vid,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_streamon = mxc_isi_m2m_streamon,
.vidioc_streamoff = mxc_isi_m2m_streamoff,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/* -----------------------------------------------------------------------------
* Video device file operations
*/
static void mxc_isi_m2m_init_format(struct mxc_isi_m2m_ctx *ctx,
struct mxc_isi_m2m_ctx_queue_data *qdata,
enum mxc_isi_video_type type)
{
qdata->format.width = MXC_ISI_DEF_WIDTH;
qdata->format.height = MXC_ISI_DEF_HEIGHT;
qdata->format.pixelformat = MXC_ISI_DEF_PIXEL_FORMAT;
qdata->info = mxc_isi_format_try(ctx->m2m->pipe, &qdata->format, type);
}
static int mxc_isi_m2m_open(struct file *file)
{
struct video_device *vdev = video_devdata(file);
struct mxc_isi_m2m *m2m = video_drvdata(file);
struct mxc_isi_m2m_ctx *ctx;
int ret;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->m2m = m2m;
mutex_init(&ctx->vb2_lock);
v4l2_fh_init(&ctx->fh, vdev);
file->private_data = &ctx->fh;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(m2m->m2m_dev, ctx,
&mxc_isi_m2m_queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
ret = PTR_ERR(ctx->fh.m2m_ctx);
ctx->fh.m2m_ctx = NULL;
goto err_fh;
}
mxc_isi_m2m_init_format(ctx, &ctx->queues.out, MXC_ISI_VIDEO_M2M_OUT);
mxc_isi_m2m_init_format(ctx, &ctx->queues.cap, MXC_ISI_VIDEO_M2M_CAP);
ret = mxc_isi_m2m_ctx_ctrls_create(ctx);
if (ret)
goto err_ctx;
ret = pm_runtime_resume_and_get(m2m->isi->dev);
if (ret)
goto err_ctrls;
v4l2_fh_add(&ctx->fh);
return 0;
err_ctrls:
mxc_isi_m2m_ctx_ctrls_delete(ctx);
err_ctx:
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
err_fh:
v4l2_fh_exit(&ctx->fh);
mutex_destroy(&ctx->vb2_lock);
kfree(ctx);
return ret;
}
static int mxc_isi_m2m_release(struct file *file)
{
struct mxc_isi_m2m *m2m = video_drvdata(file);
struct mxc_isi_m2m_ctx *ctx = to_isi_m2m_ctx(file->private_data);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
mxc_isi_m2m_ctx_ctrls_delete(ctx);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
mutex_destroy(&ctx->vb2_lock);
kfree(ctx);
pm_runtime_put(m2m->isi->dev);
return 0;
}
static const struct v4l2_file_operations mxc_isi_m2m_fops = {
.owner = THIS_MODULE,
.open = mxc_isi_m2m_open,
.release = mxc_isi_m2m_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
/* -----------------------------------------------------------------------------
* Registration
*/
int mxc_isi_m2m_register(struct mxc_isi_dev *isi, struct v4l2_device *v4l2_dev)
{
struct mxc_isi_m2m *m2m = &isi->m2m;
struct video_device *vdev = &m2m->vdev;
struct media_link *link;
int ret;
m2m->isi = isi;
m2m->pipe = &isi->pipes[0];
mutex_init(&m2m->lock);
/* Initialize the video device and create controls. */
snprintf(vdev->name, sizeof(vdev->name), "mxc_isi.m2m");
vdev->fops = &mxc_isi_m2m_fops;
vdev->ioctl_ops = &mxc_isi_m2m_ioctl_ops;
vdev->v4l2_dev = v4l2_dev;
vdev->minor = -1;
vdev->release = video_device_release_empty;
vdev->vfl_dir = VFL_DIR_M2M;
vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
video_set_drvdata(vdev, m2m);
/* Create the M2M device. */
m2m->m2m_dev = v4l2_m2m_init(&mxc_isi_m2m_ops);
if (IS_ERR(m2m->m2m_dev)) {
dev_err(isi->dev, "failed to initialize m2m device\n");
ret = PTR_ERR(m2m->m2m_dev);
goto err_mutex;
}
/* Register the video device. */
ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
if (ret < 0) {
dev_err(isi->dev, "failed to register m2m device\n");
goto err_m2m;
}
/*
* Populate the media graph. We can't use the mem2mem helper
* v4l2_m2m_register_media_controller() as the M2M interface needs to
* be connected to the existing entities in the graph, so we have to
* wire things up manually:
*
* - The entity in the video_device, which isn't touched by the V4L2
* core for M2M devices, is used as the source I/O entity in the
* graph, connected to the crossbar switch.
*
* - The video device at the end of the pipeline provides the sink
* entity, and is already wired up in the graph.
*
* - A new interface is created, pointing at both entities. The sink
* entity will thus have two interfaces pointing to it.
*/
m2m->pad.flags = MEDIA_PAD_FL_SOURCE;
vdev->entity.name = "mxc_isi.output";
vdev->entity.function = MEDIA_ENT_F_IO_V4L;
ret = media_entity_pads_init(&vdev->entity, 1, &m2m->pad);
if (ret)
goto err_video;
ret = media_device_register_entity(v4l2_dev->mdev, &vdev->entity);
if (ret)
goto err_entity_cleanup;
ret = media_create_pad_link(&vdev->entity, 0,
&m2m->isi->crossbar.sd.entity,
m2m->isi->crossbar.num_sinks - 1,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret)
goto err_entity_unreg;
m2m->intf = media_devnode_create(v4l2_dev->mdev, MEDIA_INTF_T_V4L_VIDEO,
0, VIDEO_MAJOR, vdev->minor);
if (!m2m->intf) {
ret = -ENOMEM;
goto err_entity_unreg;
}
link = media_create_intf_link(&vdev->entity, &m2m->intf->intf,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (!link) {
ret = -ENOMEM;
goto err_devnode;
}
link = media_create_intf_link(&m2m->pipe->video.vdev.entity,
&m2m->intf->intf,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (!link) {
ret = -ENOMEM;
goto err_devnode;
}
return 0;
err_devnode:
media_devnode_remove(m2m->intf);
err_entity_unreg:
media_device_unregister_entity(&vdev->entity);
err_entity_cleanup:
media_entity_cleanup(&vdev->entity);
err_video:
video_unregister_device(vdev);
err_m2m:
v4l2_m2m_release(m2m->m2m_dev);
err_mutex:
mutex_destroy(&m2m->lock);
return ret;
}
int mxc_isi_m2m_unregister(struct mxc_isi_dev *isi)
{
struct mxc_isi_m2m *m2m = &isi->m2m;
struct video_device *vdev = &m2m->vdev;
video_unregister_device(vdev);
v4l2_m2m_release(m2m->m2m_dev);
media_devnode_remove(m2m->intf);
media_entity_cleanup(&vdev->entity);
mutex_destroy(&m2m->lock);
return 0;
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* i.MX8 ISI - Input crossbar switch
*
* Copyright (c) 2022 Laurent Pinchart <[email protected]>
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
#include "imx8-isi-core.h"
static inline struct mxc_isi_crossbar *to_isi_crossbar(struct v4l2_subdev *sd)
{
return container_of(sd, struct mxc_isi_crossbar, sd);
}
static int mxc_isi_crossbar_gasket_enable(struct mxc_isi_crossbar *xbar,
struct v4l2_subdev_state *state,
struct v4l2_subdev *remote_sd,
u32 remote_pad, unsigned int port)
{
struct mxc_isi_dev *isi = xbar->isi;
const struct mxc_gasket_ops *gasket_ops = isi->pdata->gasket_ops;
const struct v4l2_mbus_framefmt *fmt;
struct v4l2_mbus_frame_desc fd;
int ret;
if (!gasket_ops)
return 0;
/*
* Configure and enable the gasket with the frame size and CSI-2 data
* type. For YUV422 8-bit, enable dual component mode unconditionally,
* to match the configuration of the CSIS.
*/
ret = v4l2_subdev_call(remote_sd, pad, get_frame_desc, remote_pad, &fd);
if (ret) {
dev_err(isi->dev,
"failed to get frame descriptor from '%s':%u: %d\n",
remote_sd->name, remote_pad, ret);
return ret;
}
if (fd.num_entries != 1) {
dev_err(isi->dev, "invalid frame descriptor for '%s':%u\n",
remote_sd->name, remote_pad);
return -EINVAL;
}
fmt = v4l2_subdev_state_get_stream_format(state, port, 0);
if (!fmt)
return -EINVAL;
gasket_ops->enable(isi, &fd, fmt, port);
return 0;
}
static void mxc_isi_crossbar_gasket_disable(struct mxc_isi_crossbar *xbar,
unsigned int port)
{
struct mxc_isi_dev *isi = xbar->isi;
const struct mxc_gasket_ops *gasket_ops = isi->pdata->gasket_ops;
if (!gasket_ops)
return;
gasket_ops->disable(isi, port);
}
/* -----------------------------------------------------------------------------
* V4L2 subdev operations
*/
static const struct v4l2_mbus_framefmt mxc_isi_crossbar_default_format = {
.code = MXC_ISI_DEF_MBUS_CODE_SINK,
.width = MXC_ISI_DEF_WIDTH,
.height = MXC_ISI_DEF_HEIGHT,
.field = V4L2_FIELD_NONE,
.colorspace = MXC_ISI_DEF_COLOR_SPACE,
.ycbcr_enc = MXC_ISI_DEF_YCBCR_ENC,
.quantization = MXC_ISI_DEF_QUANTIZATION,
.xfer_func = MXC_ISI_DEF_XFER_FUNC,
};
static int __mxc_isi_crossbar_set_routing(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_krouting *routing)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
struct v4l2_subdev_route *route;
int ret;
ret = v4l2_subdev_routing_validate(sd, routing,
V4L2_SUBDEV_ROUTING_NO_N_TO_1);
if (ret)
return ret;
/* The memory input can be routed to the first pipeline only. */
for_each_active_route(&state->routing, route) {
if (route->sink_pad == xbar->num_sinks - 1 &&
route->source_pad != xbar->num_sinks) {
dev_dbg(xbar->isi->dev,
"invalid route from memory input (%u) to pipe %u\n",
route->sink_pad,
route->source_pad - xbar->num_sinks);
return -EINVAL;
}
}
return v4l2_subdev_set_routing_with_fmt(sd, state, routing,
&mxc_isi_crossbar_default_format);
}
static struct v4l2_subdev *
mxc_isi_crossbar_xlate_streams(struct mxc_isi_crossbar *xbar,
struct v4l2_subdev_state *state,
u32 source_pad, u64 source_streams,
u32 *__sink_pad, u64 *__sink_streams,
u32 *remote_pad)
{
struct v4l2_subdev_route *route;
struct v4l2_subdev *sd;
struct media_pad *pad;
u64 sink_streams = 0;
int sink_pad = -1;
/*
* Translate the source pad and streams to the sink side. The routing
* validation forbids stream merging, so all matching entries in the
* routing table are guaranteed to have the same sink pad.
*
* TODO: This is likely worth a helper function, it could perhaps be
* supported by v4l2_subdev_state_xlate_streams() with pad1 set to -1.
*/
for_each_active_route(&state->routing, route) {
if (route->source_pad != source_pad ||
!(source_streams & BIT(route->source_stream)))
continue;
sink_streams |= BIT(route->sink_stream);
sink_pad = route->sink_pad;
}
if (sink_pad < 0) {
dev_dbg(xbar->isi->dev,
"no stream connected to pipeline %u\n",
source_pad - xbar->num_sinks);
return ERR_PTR(-EPIPE);
}
pad = media_pad_remote_pad_first(&xbar->pads[sink_pad]);
sd = media_entity_to_v4l2_subdev(pad->entity);
if (!sd) {
dev_dbg(xbar->isi->dev,
"no entity connected to crossbar input %u\n",
sink_pad);
return ERR_PTR(-EPIPE);
}
*__sink_pad = sink_pad;
*__sink_streams = sink_streams;
*remote_pad = pad->index;
return sd;
}
static int mxc_isi_crossbar_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
struct v4l2_subdev_krouting routing = { };
struct v4l2_subdev_route *routes;
unsigned int i;
int ret;
/*
* Create a 1:1 mapping between pixel link inputs and outputs to
* pipelines by default.
*/
routes = kcalloc(xbar->num_sources, sizeof(*routes), GFP_KERNEL);
if (!routes)
return -ENOMEM;
for (i = 0; i < xbar->num_sources; ++i) {
struct v4l2_subdev_route *route = &routes[i];
route->sink_pad = i;
route->source_pad = i + xbar->num_sinks;
route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE;
}
routing.num_routes = xbar->num_sources;
routing.routes = routes;
ret = __mxc_isi_crossbar_set_routing(sd, state, &routing);
kfree(routes);
return ret;
}
static int mxc_isi_crossbar_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
const struct mxc_isi_bus_format_info *info;
if (code->pad >= xbar->num_sinks) {
const struct v4l2_mbus_framefmt *format;
/*
* The media bus code on source pads is identical to the
* connected sink pad.
*/
if (code->index > 0)
return -EINVAL;
format = v4l2_subdev_state_get_opposite_stream_format(state,
code->pad,
code->stream);
if (!format)
return -EINVAL;
code->code = format->code;
return 0;
}
info = mxc_isi_bus_format_by_index(code->index, MXC_ISI_PIPE_PAD_SINK);
if (!info)
return -EINVAL;
code->code = info->mbus_code;
return 0;
}
static int mxc_isi_crossbar_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_format *fmt)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
struct v4l2_mbus_framefmt *sink_fmt;
struct v4l2_subdev_route *route;
if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
media_pad_is_streaming(&xbar->pads[fmt->pad]))
return -EBUSY;
/*
* The source pad format is always identical to the sink pad format and
* can't be modified.
*/
if (fmt->pad >= xbar->num_sinks)
return v4l2_subdev_get_fmt(sd, state, fmt);
/* Validate the requested format. */
if (!mxc_isi_bus_format_by_code(fmt->format.code, MXC_ISI_PIPE_PAD_SINK))
fmt->format.code = MXC_ISI_DEF_MBUS_CODE_SINK;
fmt->format.width = clamp_t(unsigned int, fmt->format.width,
MXC_ISI_MIN_WIDTH, MXC_ISI_MAX_WIDTH_CHAINED);
fmt->format.height = clamp_t(unsigned int, fmt->format.height,
MXC_ISI_MIN_HEIGHT, MXC_ISI_MAX_HEIGHT);
fmt->format.field = V4L2_FIELD_NONE;
/*
* Set the format on the sink stream and propagate it to the source
* streams.
*/
sink_fmt = v4l2_subdev_state_get_stream_format(state, fmt->pad,
fmt->stream);
if (!sink_fmt)
return -EINVAL;
*sink_fmt = fmt->format;
/* TODO: A format propagation helper would be useful. */
for_each_active_route(&state->routing, route) {
struct v4l2_mbus_framefmt *source_fmt;
if (route->sink_pad != fmt->pad ||
route->sink_stream != fmt->stream)
continue;
source_fmt = v4l2_subdev_state_get_stream_format(state, route->source_pad,
route->source_stream);
if (!source_fmt)
return -EINVAL;
*source_fmt = fmt->format;
}
return 0;
}
static int mxc_isi_crossbar_set_routing(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
enum v4l2_subdev_format_whence which,
struct v4l2_subdev_krouting *routing)
{
if (which == V4L2_SUBDEV_FORMAT_ACTIVE &&
media_entity_is_streaming(&sd->entity))
return -EBUSY;
return __mxc_isi_crossbar_set_routing(sd, state, routing);
}
static int mxc_isi_crossbar_enable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
struct v4l2_subdev *remote_sd;
struct mxc_isi_input *input;
u64 sink_streams;
u32 sink_pad;
u32 remote_pad;
int ret;
remote_sd = mxc_isi_crossbar_xlate_streams(xbar, state, pad, streams_mask,
&sink_pad, &sink_streams,
&remote_pad);
if (IS_ERR(remote_sd))
return PTR_ERR(remote_sd);
input = &xbar->inputs[sink_pad];
/*
* TODO: Track per-stream enable counts to support multiplexed
* streams.
*/
if (!input->enable_count) {
ret = mxc_isi_crossbar_gasket_enable(xbar, state, remote_sd,
remote_pad, sink_pad);
if (ret)
return ret;
ret = v4l2_subdev_enable_streams(remote_sd, remote_pad,
sink_streams);
if (ret) {
dev_err(xbar->isi->dev,
"failed to %s streams 0x%llx on '%s':%u: %d\n",
"enable", sink_streams, remote_sd->name,
remote_pad, ret);
mxc_isi_crossbar_gasket_disable(xbar, sink_pad);
return ret;
}
}
input->enable_count++;
return 0;
}
static int mxc_isi_crossbar_disable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);
struct v4l2_subdev *remote_sd;
struct mxc_isi_input *input;
u64 sink_streams;
u32 sink_pad;
u32 remote_pad;
int ret = 0;
remote_sd = mxc_isi_crossbar_xlate_streams(xbar, state, pad, streams_mask,
&sink_pad, &sink_streams,
&remote_pad);
if (IS_ERR(remote_sd))
return PTR_ERR(remote_sd);
input = &xbar->inputs[sink_pad];
input->enable_count--;
if (!input->enable_count) {
ret = v4l2_subdev_disable_streams(remote_sd, remote_pad,
sink_streams);
if (ret)
dev_err(xbar->isi->dev,
"failed to %s streams 0x%llx on '%s':%u: %d\n",
"disable", sink_streams, remote_sd->name,
remote_pad, ret);
mxc_isi_crossbar_gasket_disable(xbar, sink_pad);
}
return ret;
}
static const struct v4l2_subdev_pad_ops mxc_isi_crossbar_subdev_pad_ops = {
.init_cfg = mxc_isi_crossbar_init_cfg,
.enum_mbus_code = mxc_isi_crossbar_enum_mbus_code,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = mxc_isi_crossbar_set_fmt,
.set_routing = mxc_isi_crossbar_set_routing,
.enable_streams = mxc_isi_crossbar_enable_streams,
.disable_streams = mxc_isi_crossbar_disable_streams,
};
static const struct v4l2_subdev_ops mxc_isi_crossbar_subdev_ops = {
.pad = &mxc_isi_crossbar_subdev_pad_ops,
};
static const struct media_entity_operations mxc_isi_cross_entity_ops = {
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
.link_validate = v4l2_subdev_link_validate,
.has_pad_interdep = v4l2_subdev_has_pad_interdep,
};
/* -----------------------------------------------------------------------------
* Init & cleanup
*/
int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)
{
struct mxc_isi_crossbar *xbar = &isi->crossbar;
struct v4l2_subdev *sd = &xbar->sd;
unsigned int num_pads;
unsigned int i;
int ret;
xbar->isi = isi;
v4l2_subdev_init(sd, &mxc_isi_crossbar_subdev_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
strscpy(sd->name, "crossbar", sizeof(sd->name));
sd->dev = isi->dev;
sd->entity.function = MEDIA_ENT_F_VID_MUX;
sd->entity.ops = &mxc_isi_cross_entity_ops;
/*
* The subdev has one sink and one source per port, plus one sink for
* the memory input.
*/
xbar->num_sinks = isi->pdata->num_ports + 1;
xbar->num_sources = isi->pdata->num_ports;
num_pads = xbar->num_sinks + xbar->num_sources;
xbar->pads = kcalloc(num_pads, sizeof(*xbar->pads), GFP_KERNEL);
if (!xbar->pads)
return -ENOMEM;
xbar->inputs = kcalloc(xbar->num_sinks, sizeof(*xbar->inputs),
GFP_KERNEL);
if (!xbar->inputs) {
ret = -ENOMEM;
goto err_free;
}
for (i = 0; i < xbar->num_sinks; ++i)
xbar->pads[i].flags = MEDIA_PAD_FL_SINK;
for (i = 0; i < xbar->num_sources; ++i)
xbar->pads[i + xbar->num_sinks].flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&sd->entity, num_pads, xbar->pads);
if (ret)
goto err_free;
ret = v4l2_subdev_init_finalize(sd);
if (ret < 0)
goto err_entity;
return 0;
err_entity:
media_entity_cleanup(&sd->entity);
err_free:
kfree(xbar->pads);
kfree(xbar->inputs);
return ret;
}
void mxc_isi_crossbar_cleanup(struct mxc_isi_crossbar *xbar)
{
media_entity_cleanup(&xbar->sd.entity);
kfree(xbar->pads);
kfree(xbar->inputs);
}
int mxc_isi_crossbar_register(struct mxc_isi_crossbar *xbar)
{
return v4l2_device_register_subdev(&xbar->isi->v4l2_dev, &xbar->sd);
}
void mxc_isi_crossbar_unregister(struct mxc_isi_crossbar *xbar)
{
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c |
// SPDX-License-Identifier: GPL-2.0
/*
* V4L2 Capture ISI subdev driver for i.MX8QXP/QM platform
*
* ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
* used to process image from camera sensor to memory or DC
*
* Copyright (c) 2019 NXP Semiconductor
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
#include <media/videobuf2-v4l2.h>
#include "imx8-isi-core.h"
#include "imx8-isi-regs.h"
/*
* While the ISI receives data from the gasket on a 3x12-bit bus, the pipeline
* subdev conceptually includes the gasket in order to avoid exposing an extra
* subdev between the CSIS and the ISI. We thus need to expose media bus codes
* corresponding to the CSIS output, which is narrower.
*/
static const struct mxc_isi_bus_format_info mxc_isi_bus_formats[] = {
/* YUV formats */
{
.mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
.output = MEDIA_BUS_FMT_YUV8_1X24,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK),
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.output = MEDIA_BUS_FMT_YUV8_1X24,
.pads = BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_YUV,
},
/* RGB formats */
{
.mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
.output = MEDIA_BUS_FMT_RGB888_1X24,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK),
.encoding = MXC_ISI_ENC_RGB,
}, {
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.output = MEDIA_BUS_FMT_RGB888_1X24,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RGB,
},
/* RAW formats */
{
.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
.output = MEDIA_BUS_FMT_Y8_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y10_1X10,
.output = MEDIA_BUS_FMT_Y10_1X10,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y12_1X12,
.output = MEDIA_BUS_FMT_Y12_1X12,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y14_1X14,
.output = MEDIA_BUS_FMT_Y14_1X14,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
.output = MEDIA_BUS_FMT_SBGGR8_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
.output = MEDIA_BUS_FMT_SGBRG8_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
.output = MEDIA_BUS_FMT_SGRBG8_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
.output = MEDIA_BUS_FMT_SRGGB8_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.output = MEDIA_BUS_FMT_SBGGR10_1X10,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
.output = MEDIA_BUS_FMT_SGBRG10_1X10,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
.output = MEDIA_BUS_FMT_SGRBG10_1X10,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
.output = MEDIA_BUS_FMT_SRGGB10_1X10,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
.output = MEDIA_BUS_FMT_SBGGR12_1X12,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
.output = MEDIA_BUS_FMT_SGBRG12_1X12,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
.output = MEDIA_BUS_FMT_SGRBG12_1X12,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
.output = MEDIA_BUS_FMT_SRGGB12_1X12,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR14_1X14,
.output = MEDIA_BUS_FMT_SBGGR14_1X14,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG14_1X14,
.output = MEDIA_BUS_FMT_SGBRG14_1X14,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG14_1X14,
.output = MEDIA_BUS_FMT_SGRBG14_1X14,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB14_1X14,
.output = MEDIA_BUS_FMT_SRGGB14_1X14,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
},
/* JPEG */
{
.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
.output = MEDIA_BUS_FMT_JPEG_1X8,
.pads = BIT(MXC_ISI_PIPE_PAD_SINK)
| BIT(MXC_ISI_PIPE_PAD_SOURCE),
.encoding = MXC_ISI_ENC_RAW,
}
};
const struct mxc_isi_bus_format_info *
mxc_isi_bus_format_by_code(u32 code, unsigned int pad)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mxc_isi_bus_formats); i++) {
const struct mxc_isi_bus_format_info *info =
&mxc_isi_bus_formats[i];
if (info->mbus_code == code && info->pads & BIT(pad))
return info;
}
return NULL;
}
const struct mxc_isi_bus_format_info *
mxc_isi_bus_format_by_index(unsigned int index, unsigned int pad)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mxc_isi_bus_formats); i++) {
const struct mxc_isi_bus_format_info *info =
&mxc_isi_bus_formats[i];
if (!(info->pads & BIT(pad)))
continue;
if (!index)
return info;
index--;
}
return NULL;
}
static inline struct mxc_isi_pipe *to_isi_pipe(struct v4l2_subdev *sd)
{
return container_of(sd, struct mxc_isi_pipe, sd);
}
int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_crossbar *xbar = &pipe->isi->crossbar;
const struct mxc_isi_bus_format_info *sink_info;
const struct mxc_isi_bus_format_info *src_info;
const struct v4l2_mbus_framefmt *sink_fmt;
const struct v4l2_mbus_framefmt *src_fmt;
const struct v4l2_rect *compose;
struct v4l2_subdev_state *state;
struct v4l2_subdev *sd = &pipe->sd;
struct v4l2_area in_size, scale;
struct v4l2_rect crop;
u32 input;
int ret;
/*
* Find the connected input by inspecting the crossbar switch routing
* table.
*/
state = v4l2_subdev_lock_and_get_active_state(&xbar->sd);
ret = v4l2_subdev_routing_find_opposite_end(&state->routing,
xbar->num_sinks + pipe->id,
0, &input, NULL);
v4l2_subdev_unlock_state(state);
if (ret)
return -EPIPE;
/* Configure the pipeline. */
state = v4l2_subdev_lock_and_get_active_state(sd);
sink_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SINK);
src_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);
compose = v4l2_subdev_get_try_compose(sd, state, MXC_ISI_PIPE_PAD_SINK);
crop = *v4l2_subdev_get_try_crop(sd, state, MXC_ISI_PIPE_PAD_SOURCE);
sink_info = mxc_isi_bus_format_by_code(sink_fmt->code,
MXC_ISI_PIPE_PAD_SINK);
src_info = mxc_isi_bus_format_by_code(src_fmt->code,
MXC_ISI_PIPE_PAD_SOURCE);
in_size.width = sink_fmt->width;
in_size.height = sink_fmt->height;
scale.width = compose->width;
scale.height = compose->height;
v4l2_subdev_unlock_state(state);
/* Configure the ISI channel. */
mxc_isi_channel_config(pipe, input, &in_size, &scale, &crop,
sink_info->encoding, src_info->encoding);
mxc_isi_channel_enable(pipe);
/* Enable streams on the crossbar switch. */
ret = v4l2_subdev_enable_streams(&xbar->sd, xbar->num_sinks + pipe->id,
BIT(0));
if (ret) {
mxc_isi_channel_disable(pipe);
dev_err(pipe->isi->dev, "Failed to enable pipe %u\n",
pipe->id);
return ret;
}
return 0;
}
void mxc_isi_pipe_disable(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_crossbar *xbar = &pipe->isi->crossbar;
int ret;
ret = v4l2_subdev_disable_streams(&xbar->sd, xbar->num_sinks + pipe->id,
BIT(0));
if (ret)
dev_err(pipe->isi->dev, "Failed to disable pipe %u\n",
pipe->id);
mxc_isi_channel_disable(pipe);
}
/* -----------------------------------------------------------------------------
* V4L2 subdev operations
*/
static struct v4l2_mbus_framefmt *
mxc_isi_pipe_get_pad_format(struct mxc_isi_pipe *pipe,
struct v4l2_subdev_state *state,
unsigned int pad)
{
return v4l2_subdev_get_try_format(&pipe->sd, state, pad);
}
static struct v4l2_rect *
mxc_isi_pipe_get_pad_crop(struct mxc_isi_pipe *pipe,
struct v4l2_subdev_state *state,
unsigned int pad)
{
return v4l2_subdev_get_try_crop(&pipe->sd, state, pad);
}
static struct v4l2_rect *
mxc_isi_pipe_get_pad_compose(struct mxc_isi_pipe *pipe,
struct v4l2_subdev_state *state,
unsigned int pad)
{
return v4l2_subdev_get_try_compose(&pipe->sd, state, pad);
}
static int mxc_isi_pipe_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state)
{
struct mxc_isi_pipe *pipe = to_isi_pipe(sd);
struct v4l2_mbus_framefmt *fmt_source;
struct v4l2_mbus_framefmt *fmt_sink;
struct v4l2_rect *compose;
struct v4l2_rect *crop;
fmt_sink = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
fmt_source = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
fmt_sink->width = MXC_ISI_DEF_WIDTH;
fmt_sink->height = MXC_ISI_DEF_HEIGHT;
fmt_sink->code = MXC_ISI_DEF_MBUS_CODE_SINK;
fmt_sink->field = V4L2_FIELD_NONE;
fmt_sink->colorspace = V4L2_COLORSPACE_JPEG;
fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
fmt_sink->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
fmt_sink->ycbcr_enc);
fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
*fmt_source = *fmt_sink;
fmt_source->code = MXC_ISI_DEF_MBUS_CODE_SOURCE;
compose = mxc_isi_pipe_get_pad_compose(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
crop = mxc_isi_pipe_get_pad_crop(pipe, state, MXC_ISI_PIPE_PAD_SOURCE);
compose->left = 0;
compose->top = 0;
compose->width = MXC_ISI_DEF_WIDTH;
compose->height = MXC_ISI_DEF_HEIGHT;
*crop = *compose;
return 0;
}
static int mxc_isi_pipe_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_mbus_code_enum *code)
{
static const u32 output_codes[] = {
MEDIA_BUS_FMT_YUV8_1X24,
MEDIA_BUS_FMT_RGB888_1X24,
};
struct mxc_isi_pipe *pipe = to_isi_pipe(sd);
const struct mxc_isi_bus_format_info *info;
unsigned int index;
unsigned int i;
if (code->pad == MXC_ISI_PIPE_PAD_SOURCE) {
const struct v4l2_mbus_framefmt *format;
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
info = mxc_isi_bus_format_by_code(format->code,
MXC_ISI_PIPE_PAD_SINK);
if (info->encoding == MXC_ISI_ENC_RAW) {
/*
* For RAW formats, the sink and source media bus codes
* must match.
*/
if (code->index)
return -EINVAL;
code->code = info->output;
} else {
/*
* For RGB or YUV formats, the ISI supports format
* conversion. Either of the two output formats can be
* used regardless of the input.
*/
if (code->index > 1)
return -EINVAL;
code->code = output_codes[code->index];
}
return 0;
}
index = code->index;
for (i = 0; i < ARRAY_SIZE(mxc_isi_bus_formats); ++i) {
info = &mxc_isi_bus_formats[i];
if (!(info->pads & BIT(MXC_ISI_PIPE_PAD_SINK)))
continue;
if (index == 0) {
code->code = info->mbus_code;
return 0;
}
index--;
}
return -EINVAL;
}
static int mxc_isi_pipe_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_format *fmt)
{
struct mxc_isi_pipe *pipe = to_isi_pipe(sd);
struct v4l2_mbus_framefmt *mf = &fmt->format;
const struct mxc_isi_bus_format_info *info;
struct v4l2_mbus_framefmt *format;
struct v4l2_rect *rect;
if (vb2_is_busy(&pipe->video.vb2_q))
return -EBUSY;
if (fmt->pad == MXC_ISI_PIPE_PAD_SINK) {
unsigned int max_width;
info = mxc_isi_bus_format_by_code(mf->code,
MXC_ISI_PIPE_PAD_SINK);
if (!info)
info = mxc_isi_bus_format_by_code(MXC_ISI_DEF_MBUS_CODE_SINK,
MXC_ISI_PIPE_PAD_SINK);
/*
* Limit the max line length if there's no adjacent pipe to
* chain with.
*/
max_width = pipe->id == pipe->isi->pdata->num_channels - 1
? MXC_ISI_MAX_WIDTH_UNCHAINED
: MXC_ISI_MAX_WIDTH_CHAINED;
mf->code = info->mbus_code;
mf->width = clamp(mf->width, MXC_ISI_MIN_WIDTH, max_width);
mf->height = clamp(mf->height, MXC_ISI_MIN_HEIGHT,
MXC_ISI_MAX_HEIGHT);
/* Propagate the format to the source pad. */
rect = mxc_isi_pipe_get_pad_compose(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
rect->width = mf->width;
rect->height = mf->height;
rect = mxc_isi_pipe_get_pad_crop(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
rect->left = 0;
rect->top = 0;
rect->width = mf->width;
rect->height = mf->height;
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
format->code = info->output;
format->width = mf->width;
format->height = mf->height;
} else {
/*
* For RGB or YUV formats, the ISI supports RGB <-> YUV format
* conversion. For RAW formats, the sink and source media bus
* codes must match.
*/
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
info = mxc_isi_bus_format_by_code(format->code,
MXC_ISI_PIPE_PAD_SINK);
if (info->encoding != MXC_ISI_ENC_RAW) {
if (mf->code != MEDIA_BUS_FMT_YUV8_1X24 &&
mf->code != MEDIA_BUS_FMT_RGB888_1X24)
mf->code = info->output;
info = mxc_isi_bus_format_by_code(mf->code,
MXC_ISI_PIPE_PAD_SOURCE);
}
mf->code = info->output;
/*
* The width and height on the source can't be changed, they
* must match the crop rectangle size.
*/
rect = mxc_isi_pipe_get_pad_crop(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
mf->width = rect->width;
mf->height = rect->height;
}
format = mxc_isi_pipe_get_pad_format(pipe, state, fmt->pad);
*format = *mf;
dev_dbg(pipe->isi->dev, "pad%u: code: 0x%04x, %ux%u",
fmt->pad, mf->code, mf->width, mf->height);
return 0;
}
static int mxc_isi_pipe_get_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_selection *sel)
{
struct mxc_isi_pipe *pipe = to_isi_pipe(sd);
const struct v4l2_mbus_framefmt *format;
const struct v4l2_rect *rect;
switch (sel->target) {
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
if (sel->pad != MXC_ISI_PIPE_PAD_SINK)
/* No compose rectangle on source pad. */
return -EINVAL;
/* The sink compose is bound by the sink format. */
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
sel->r.left = 0;
sel->r.top = 0;
sel->r.width = format->width;
sel->r.height = format->height;
break;
case V4L2_SEL_TGT_CROP_BOUNDS:
if (sel->pad != MXC_ISI_PIPE_PAD_SOURCE)
/* No crop rectangle on sink pad. */
return -EINVAL;
/* The source crop is bound by the sink compose. */
rect = mxc_isi_pipe_get_pad_compose(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
sel->r = *rect;
break;
case V4L2_SEL_TGT_CROP:
if (sel->pad != MXC_ISI_PIPE_PAD_SOURCE)
/* No crop rectangle on sink pad. */
return -EINVAL;
rect = mxc_isi_pipe_get_pad_crop(pipe, state, sel->pad);
sel->r = *rect;
break;
case V4L2_SEL_TGT_COMPOSE:
if (sel->pad != MXC_ISI_PIPE_PAD_SINK)
/* No compose rectangle on source pad. */
return -EINVAL;
rect = mxc_isi_pipe_get_pad_compose(pipe, state, sel->pad);
sel->r = *rect;
break;
default:
return -EINVAL;
}
return 0;
}
static int mxc_isi_pipe_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
struct v4l2_subdev_selection *sel)
{
struct mxc_isi_pipe *pipe = to_isi_pipe(sd);
struct v4l2_mbus_framefmt *format;
struct v4l2_rect *rect;
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
if (sel->pad != MXC_ISI_PIPE_PAD_SOURCE)
/* The pipeline support cropping on the source only. */
return -EINVAL;
/* The source crop is bound by the sink compose. */
rect = mxc_isi_pipe_get_pad_compose(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
sel->r.left = clamp_t(s32, sel->r.left, 0, rect->width - 1);
sel->r.top = clamp_t(s32, sel->r.top, 0, rect->height - 1);
sel->r.width = clamp(sel->r.width, MXC_ISI_MIN_WIDTH,
rect->width - sel->r.left);
sel->r.height = clamp(sel->r.height, MXC_ISI_MIN_HEIGHT,
rect->height - sel->r.top);
rect = mxc_isi_pipe_get_pad_crop(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
*rect = sel->r;
/* Propagate the crop rectangle to the source pad. */
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
format->width = sel->r.width;
format->height = sel->r.height;
break;
case V4L2_SEL_TGT_COMPOSE:
if (sel->pad != MXC_ISI_PIPE_PAD_SINK)
/* Composing is supported on the sink only. */
return -EINVAL;
/* The sink crop is bound by the sink format downscaling only). */
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
sel->r.left = 0;
sel->r.top = 0;
sel->r.width = clamp(sel->r.width, MXC_ISI_MIN_WIDTH,
format->width);
sel->r.height = clamp(sel->r.height, MXC_ISI_MIN_HEIGHT,
format->height);
rect = mxc_isi_pipe_get_pad_compose(pipe, state,
MXC_ISI_PIPE_PAD_SINK);
*rect = sel->r;
/* Propagate the compose rectangle to the source pad. */
rect = mxc_isi_pipe_get_pad_crop(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
rect->left = 0;
rect->top = 0;
rect->width = sel->r.width;
rect->height = sel->r.height;
format = mxc_isi_pipe_get_pad_format(pipe, state,
MXC_ISI_PIPE_PAD_SOURCE);
format->width = sel->r.width;
format->height = sel->r.height;
break;
default:
return -EINVAL;
}
dev_dbg(pipe->isi->dev, "%s, target %#x: (%d,%d)/%dx%d", __func__,
sel->target, sel->r.left, sel->r.top, sel->r.width,
sel->r.height);
return 0;
}
static const struct v4l2_subdev_pad_ops mxc_isi_pipe_subdev_pad_ops = {
.init_cfg = mxc_isi_pipe_init_cfg,
.enum_mbus_code = mxc_isi_pipe_enum_mbus_code,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = mxc_isi_pipe_set_fmt,
.get_selection = mxc_isi_pipe_get_selection,
.set_selection = mxc_isi_pipe_set_selection,
};
static const struct v4l2_subdev_ops mxc_isi_pipe_subdev_ops = {
.pad = &mxc_isi_pipe_subdev_pad_ops,
};
/* -----------------------------------------------------------------------------
* IRQ handling
*/
static irqreturn_t mxc_isi_pipe_irq_handler(int irq, void *priv)
{
struct mxc_isi_pipe *pipe = priv;
const struct mxc_isi_ier_reg *ier_reg = pipe->isi->pdata->ier_reg;
u32 status;
status = mxc_isi_channel_irq_status(pipe, true);
if (status & CHNL_STS_FRM_STRD) {
if (!WARN_ON(!pipe->irq_handler))
pipe->irq_handler(pipe, status);
}
if (status & (CHNL_STS_AXI_WR_ERR_Y |
CHNL_STS_AXI_WR_ERR_U |
CHNL_STS_AXI_WR_ERR_V))
dev_dbg(pipe->isi->dev, "%s: IRQ AXI Error stat=0x%X\n",
__func__, status);
if (status & (ier_reg->panic_y_buf_en.mask |
ier_reg->panic_u_buf_en.mask |
ier_reg->panic_v_buf_en.mask))
dev_dbg(pipe->isi->dev, "%s: IRQ Panic OFLW Error stat=0x%X\n",
__func__, status);
if (status & (ier_reg->oflw_y_buf_en.mask |
ier_reg->oflw_u_buf_en.mask |
ier_reg->oflw_v_buf_en.mask))
dev_dbg(pipe->isi->dev, "%s: IRQ OFLW Error stat=0x%X\n",
__func__, status);
if (status & (ier_reg->excs_oflw_y_buf_en.mask |
ier_reg->excs_oflw_u_buf_en.mask |
ier_reg->excs_oflw_v_buf_en.mask))
dev_dbg(pipe->isi->dev, "%s: IRQ EXCS OFLW Error stat=0x%X\n",
__func__, status);
return IRQ_HANDLED;
}
/* -----------------------------------------------------------------------------
* Init & cleanup
*/
static const struct media_entity_operations mxc_isi_pipe_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
};
int mxc_isi_pipe_init(struct mxc_isi_dev *isi, unsigned int id)
{
struct mxc_isi_pipe *pipe = &isi->pipes[id];
struct v4l2_subdev *sd;
int irq;
int ret;
pipe->id = id;
pipe->isi = isi;
pipe->regs = isi->regs + id * isi->pdata->reg_offset;
mutex_init(&pipe->lock);
pipe->available_res = MXC_ISI_CHANNEL_RES_LINE_BUF
| MXC_ISI_CHANNEL_RES_OUTPUT_BUF;
pipe->acquired_res = 0;
pipe->chained_res = 0;
pipe->chained = false;
sd = &pipe->sd;
v4l2_subdev_init(sd, &mxc_isi_pipe_subdev_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
snprintf(sd->name, sizeof(sd->name), "mxc_isi.%d", pipe->id);
sd->dev = isi->dev;
sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
sd->entity.ops = &mxc_isi_pipe_entity_ops;
pipe->pads[MXC_ISI_PIPE_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
pipe->pads[MXC_ISI_PIPE_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&sd->entity, MXC_ISI_PIPE_PADS_NUM,
pipe->pads);
if (ret)
goto error;
ret = v4l2_subdev_init_finalize(sd);
if (ret < 0)
goto error;
/* Register IRQ handler. */
mxc_isi_channel_irq_clear(pipe);
irq = platform_get_irq(to_platform_device(isi->dev), id);
if (irq < 0) {
ret = irq;
goto error;
}
ret = devm_request_irq(isi->dev, irq, mxc_isi_pipe_irq_handler,
0, dev_name(isi->dev), pipe);
if (ret < 0) {
dev_err(isi->dev, "failed to request IRQ (%d)\n", ret);
goto error;
}
return 0;
error:
media_entity_cleanup(&sd->entity);
mutex_destroy(&pipe->lock);
return ret;
}
void mxc_isi_pipe_cleanup(struct mxc_isi_pipe *pipe)
{
struct v4l2_subdev *sd = &pipe->sd;
media_entity_cleanup(&sd->entity);
mutex_destroy(&pipe->lock);
}
int mxc_isi_pipe_acquire(struct mxc_isi_pipe *pipe,
mxc_isi_pipe_irq_t irq_handler)
{
const struct mxc_isi_bus_format_info *sink_info;
const struct mxc_isi_bus_format_info *src_info;
struct v4l2_mbus_framefmt *sink_fmt;
const struct v4l2_mbus_framefmt *src_fmt;
struct v4l2_subdev *sd = &pipe->sd;
struct v4l2_subdev_state *state;
bool bypass;
int ret;
state = v4l2_subdev_lock_and_get_active_state(sd);
sink_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SINK);
src_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);
v4l2_subdev_unlock_state(state);
sink_info = mxc_isi_bus_format_by_code(sink_fmt->code,
MXC_ISI_PIPE_PAD_SINK);
src_info = mxc_isi_bus_format_by_code(src_fmt->code,
MXC_ISI_PIPE_PAD_SOURCE);
bypass = sink_fmt->width == src_fmt->width &&
sink_fmt->height == src_fmt->height &&
sink_info->encoding == src_info->encoding;
ret = mxc_isi_channel_acquire(pipe, irq_handler, bypass);
if (ret)
return ret;
/* Chain the channel if needed for wide resolutions. */
if (sink_fmt->width > MXC_ISI_MAX_WIDTH_UNCHAINED) {
ret = mxc_isi_channel_chain(pipe, bypass);
if (ret)
mxc_isi_channel_release(pipe);
}
return ret;
}
void mxc_isi_pipe_release(struct mxc_isi_pipe *pipe)
{
mxc_isi_channel_release(pipe);
mxc_isi_channel_unchain(pipe);
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c |
// SPDX-License-Identifier: GPL-2.0
/*
* V4L2 Capture ISI subdev driver for i.MX8QXP/QM platform
*
* ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
* used to process image from camera sensor to memory or DC
*
* Copyright (c) 2019 NXP Semiconductor
*/
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/media-bus-format.h>
#include <linux/minmax.h>
#include <linux/pm_runtime.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-subdev.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include "imx8-isi-core.h"
#include "imx8-isi-regs.h"
/* Keep the first entry matching MXC_ISI_DEF_PIXEL_FORMAT */
static const struct mxc_isi_format_info mxc_isi_formats[] = {
/* YUV formats */
{
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_YUYV,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_OUT
| MXC_ISI_VIDEO_M2M_CAP,
.isi_in_format = CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV422_1P8P,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_YUVA32,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV444_1P8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 32 },
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_NV12,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV420_2P8P,
.color_planes = 2,
.mem_planes = 1,
.depth = { 8, 16 },
.hsub = 2,
.vsub = 2,
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_NV12M,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV420_2P8P,
.mem_planes = 2,
.color_planes = 2,
.depth = { 8, 16 },
.hsub = 2,
.vsub = 2,
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_NV16,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV422_2P8P,
.color_planes = 2,
.mem_planes = 1,
.depth = { 8, 16 },
.hsub = 2,
.vsub = 1,
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_NV16M,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV422_2P8P,
.mem_planes = 2,
.color_planes = 2,
.depth = { 8, 16 },
.hsub = 2,
.vsub = 1,
.encoding = MXC_ISI_ENC_YUV,
}, {
.mbus_code = MEDIA_BUS_FMT_YUV8_1X24,
.fourcc = V4L2_PIX_FMT_YUV444M,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_YUV444_3P8P,
.mem_planes = 3,
.color_planes = 3,
.depth = { 8, 8, 8 },
.hsub = 1,
.vsub = 1,
.encoding = MXC_ISI_ENC_YUV,
},
/* RGB formats */
{
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.fourcc = V4L2_PIX_FMT_RGB565,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_OUT
| MXC_ISI_VIDEO_M2M_CAP,
.isi_in_format = CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RGB565,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RGB,
}, {
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.fourcc = V4L2_PIX_FMT_RGB24,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_OUT
| MXC_ISI_VIDEO_M2M_CAP,
.isi_in_format = CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_BGR888P,
.mem_planes = 1,
.color_planes = 1,
.depth = { 24 },
.encoding = MXC_ISI_ENC_RGB,
}, {
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.fourcc = V4L2_PIX_FMT_BGR24,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_OUT
| MXC_ISI_VIDEO_M2M_CAP,
.isi_in_format = CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RGB888P,
.mem_planes = 1,
.color_planes = 1,
.depth = { 24 },
.encoding = MXC_ISI_ENC_RGB,
}, {
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.fourcc = V4L2_PIX_FMT_XBGR32,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_OUT
| MXC_ISI_VIDEO_M2M_CAP,
.isi_in_format = CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_XRGB888,
.mem_planes = 1,
.color_planes = 1,
.depth = { 32 },
.encoding = MXC_ISI_ENC_RGB,
}, {
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.fourcc = V4L2_PIX_FMT_ABGR32,
.type = MXC_ISI_VIDEO_CAP | MXC_ISI_VIDEO_M2M_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_ARGB8888,
.mem_planes = 1,
.color_planes = 1,
.depth = { 32 },
.encoding = MXC_ISI_ENC_RGB,
},
/*
* RAW formats
*
* The ISI shifts the 10-bit and 12-bit formats left by 6 and 4 bits
* when using CHNL_IMG_CTRL_FORMAT_RAW10 or MXC_ISI_OUT_FMT_RAW12
* respectively, to align the bits to the left and pad with zeros in
* the LSBs. The corresponding V4L2 formats are however right-aligned,
* we have to use CHNL_IMG_CTRL_FORMAT_RAW16 to avoid the left shift.
*/
{
.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
.fourcc = V4L2_PIX_FMT_GREY,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y10_1X10,
.fourcc = V4L2_PIX_FMT_Y10,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y12_1X12,
.fourcc = V4L2_PIX_FMT_Y12,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_Y14_1X14,
.fourcc = V4L2_PIX_FMT_Y14,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
.fourcc = V4L2_PIX_FMT_SBGGR8,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
.fourcc = V4L2_PIX_FMT_SGBRG8,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
.fourcc = V4L2_PIX_FMT_SGRBG8,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
.fourcc = V4L2_PIX_FMT_SRGGB8,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.fourcc = V4L2_PIX_FMT_SBGGR10,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
.fourcc = V4L2_PIX_FMT_SGBRG10,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
.fourcc = V4L2_PIX_FMT_SGRBG10,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
.fourcc = V4L2_PIX_FMT_SRGGB10,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
.fourcc = V4L2_PIX_FMT_SBGGR12,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
.fourcc = V4L2_PIX_FMT_SGBRG12,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
.fourcc = V4L2_PIX_FMT_SGRBG12,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
.fourcc = V4L2_PIX_FMT_SRGGB12,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR14_1X14,
.fourcc = V4L2_PIX_FMT_SBGGR14,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG14_1X14,
.fourcc = V4L2_PIX_FMT_SGBRG14,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SGRBG14_1X14,
.fourcc = V4L2_PIX_FMT_SGRBG14,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB14_1X14,
.fourcc = V4L2_PIX_FMT_SRGGB14,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW16,
.mem_planes = 1,
.color_planes = 1,
.depth = { 16 },
.encoding = MXC_ISI_ENC_RAW,
},
/* JPEG */
{
.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
.fourcc = V4L2_PIX_FMT_MJPEG,
.type = MXC_ISI_VIDEO_CAP,
.isi_out_format = CHNL_IMG_CTRL_FORMAT_RAW8,
.mem_planes = 1,
.color_planes = 1,
.depth = { 8 },
.encoding = MXC_ISI_ENC_RAW,
}
};
const struct mxc_isi_format_info *
mxc_isi_format_by_fourcc(u32 fourcc, enum mxc_isi_video_type type)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mxc_isi_formats); i++) {
const struct mxc_isi_format_info *fmt = &mxc_isi_formats[i];
if (fmt->fourcc == fourcc && fmt->type & type)
return fmt;
}
return NULL;
}
const struct mxc_isi_format_info *
mxc_isi_format_enum(unsigned int index, enum mxc_isi_video_type type)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mxc_isi_formats); i++) {
const struct mxc_isi_format_info *fmt = &mxc_isi_formats[i];
if (!(fmt->type & type))
continue;
if (!index)
return fmt;
index--;
}
return NULL;
}
const struct mxc_isi_format_info *
mxc_isi_format_try(struct mxc_isi_pipe *pipe, struct v4l2_pix_format_mplane *pix,
enum mxc_isi_video_type type)
{
const struct mxc_isi_format_info *fmt;
unsigned int max_width;
unsigned int i;
max_width = pipe->id == pipe->isi->pdata->num_channels - 1
? MXC_ISI_MAX_WIDTH_UNCHAINED
: MXC_ISI_MAX_WIDTH_CHAINED;
fmt = mxc_isi_format_by_fourcc(pix->pixelformat, type);
if (!fmt)
fmt = &mxc_isi_formats[0];
pix->width = clamp(pix->width, MXC_ISI_MIN_WIDTH, max_width);
pix->height = clamp(pix->height, MXC_ISI_MIN_HEIGHT, MXC_ISI_MAX_HEIGHT);
pix->pixelformat = fmt->fourcc;
pix->field = V4L2_FIELD_NONE;
if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) {
pix->colorspace = MXC_ISI_DEF_COLOR_SPACE;
pix->ycbcr_enc = MXC_ISI_DEF_YCBCR_ENC;
pix->quantization = MXC_ISI_DEF_QUANTIZATION;
pix->xfer_func = MXC_ISI_DEF_XFER_FUNC;
}
if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
if (pix->quantization == V4L2_QUANTIZATION_DEFAULT) {
bool is_rgb = fmt->encoding == MXC_ISI_ENC_RGB;
pix->quantization =
V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb, pix->colorspace,
pix->ycbcr_enc);
}
if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT)
pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
pix->num_planes = fmt->mem_planes;
for (i = 0; i < fmt->color_planes; ++i) {
struct v4l2_plane_pix_format *plane = &pix->plane_fmt[i];
unsigned int bpl;
/* The pitch must be identical for all planes. */
if (i == 0)
bpl = clamp(plane->bytesperline,
pix->width * fmt->depth[0] / 8,
65535U);
else
bpl = pix->plane_fmt[0].bytesperline;
plane->bytesperline = bpl;
plane->sizeimage = plane->bytesperline * pix->height;
if (i >= 1)
plane->sizeimage /= fmt->vsub;
}
/*
* For single-planar pixel formats with multiple color planes,
* concatenate the size of all planes and clear all planes but the
* first one.
*/
if (fmt->color_planes != fmt->mem_planes) {
for (i = 1; i < fmt->color_planes; ++i) {
struct v4l2_plane_pix_format *plane = &pix->plane_fmt[i];
pix->plane_fmt[0].sizeimage += plane->sizeimage;
plane->bytesperline = 0;
plane->sizeimage = 0;
}
}
return fmt;
}
/* -----------------------------------------------------------------------------
* videobuf2 queue operations
*/
static void mxc_isi_video_frame_write_done(struct mxc_isi_pipe *pipe,
u32 status)
{
struct mxc_isi_video *video = &pipe->video;
struct device *dev = pipe->isi->dev;
struct mxc_isi_buffer *next_buf;
struct mxc_isi_buffer *buf;
enum mxc_isi_buf_id buf_id;
spin_lock(&video->buf_lock);
/*
* The ISI hardware handles buffers using a ping-pong mechanism with
* two sets of destination addresses (with shadow registers to allow
* programming addresses for all planes atomically) named BUF1 and
* BUF2. Addresses can be loaded and copied to shadow registers at any
* at any time.
*
* The hardware keeps track of which buffer is being written to and
* automatically switches to the other buffer at frame end, copying the
* corresponding address to another set of shadow registers that track
* the address being written to. The active buffer tracking bits are
* accessible through the CHNL_STS register.
*
* BUF1 BUF2 | Event | Action
* | |
* | | Program initial buffers
* | | B0 in BUF1, B1 in BUF2
* | Start ISI |
* +----+ | |
* | B0 | | |
* +----+ | |
* +----+ | FRM IRQ 0 | B0 complete, BUF2 now active
* | B1 | | | Program B2 in BUF1
* +----+ | |
* +----+ | FRM IRQ 1 | B1 complete, BUF1 now active
* | B2 | | | Program B3 in BUF2
* +----+ | |
* +----+ | FRM IRQ 2 | B2 complete, BUF2 now active
* | B3 | | | Program B4 in BUF1
* +----+ | |
* +----+ | FRM IRQ 3 | B3 complete, BUF1 now active
* | B4 | | | Program B5 in BUF2
* +----+ | |
* ... | |
*
* Races between address programming and buffer switching can be
* detected by checking if a frame end interrupt occurred after
* programming the addresses.
*
* As none of the shadow registers are accessible, races can occur
* between address programming and buffer switching. It is possible to
* detect the race condition by checking if a frame end interrupt
* occurred after programming the addresses, but impossible to
* determine if the race has been won or lost.
*
* In addition to this, we need to use discard buffers if no pending
* buffers are available. To simplify handling of discard buffer, we
* need to allocate three of them, as two can be active concurrently
* and we need to still be able to get hold of a next buffer. The logic
* could be improved to use two buffers only, but as all discard
* buffers share the same memory, an additional buffer is cheap.
*/
/* Check which buffer has just completed. */
buf_id = pipe->isi->pdata->buf_active_reverse
? (status & CHNL_STS_BUF1_ACTIVE ? MXC_ISI_BUF2 : MXC_ISI_BUF1)
: (status & CHNL_STS_BUF1_ACTIVE ? MXC_ISI_BUF1 : MXC_ISI_BUF2);
buf = list_first_entry_or_null(&video->out_active,
struct mxc_isi_buffer, list);
/* Safety check, this should really never happen. */
if (!buf) {
dev_warn(dev, "trying to access empty active list\n");
goto done;
}
/*
* If the buffer that has completed doesn't match the buffer on the
* front of the active list, it means we have lost one frame end
* interrupt (or possibly a large odd number of interrupts, although
* quite unlikely).
*
* For instance, if IRQ1 is lost and we handle IRQ2, both B1 and B2
* have been completed, but B3 hasn't been programmed, BUF2 still
* addresses B1 and the ISI is now writing in B1 instead of B3. We
* can't complete B2 as that would result in out-of-order completion.
*
* The only option is to ignore this interrupt and try again. When IRQ3
* will be handled, we will complete B1 and be in sync again.
*/
if (buf->id != buf_id) {
dev_dbg(dev, "buffer ID mismatch (expected %u, got %u), skipping\n",
buf->id, buf_id);
/*
* Increment the frame count by two to account for the missed
* and the ignored interrupts.
*/
video->frame_count += 2;
goto done;
}
/* Pick the next buffer and queue it to the hardware. */
next_buf = list_first_entry_or_null(&video->out_pending,
struct mxc_isi_buffer, list);
if (!next_buf) {
next_buf = list_first_entry_or_null(&video->out_discard,
struct mxc_isi_buffer, list);
/* Safety check, this should never happen. */
if (!next_buf) {
dev_warn(dev, "trying to access empty discard list\n");
goto done;
}
}
mxc_isi_channel_set_outbuf(pipe, next_buf->dma_addrs, buf_id);
next_buf->id = buf_id;
/*
* Check if we have raced with the end of frame interrupt. If so, we
* can't tell if the ISI has recorded the new address, or is still
* using the previous buffer. We must assume the latter as that is the
* worst case.
*
* For instance, if we are handling IRQ1 and now detect the FRM
* interrupt, assume B2 has completed and the ISI has switched to BUF2
* using B1 just before we programmed B3. Unlike in the previous race
* condition, B3 has been programmed and will be written to the next
* time the ISI switches to BUF2. We can however handle this exactly as
* the first race condition, as we'll program B3 (still at the head of
* the pending list) when handling IRQ3.
*/
status = mxc_isi_channel_irq_status(pipe, false);
if (status & CHNL_STS_FRM_STRD) {
dev_dbg(dev, "raced with frame end interrupt\n");
video->frame_count += 2;
goto done;
}
/*
* The next buffer has been queued successfully, move it to the active
* list, and complete the current buffer.
*/
list_move_tail(&next_buf->list, &video->out_active);
if (!buf->discard) {
list_del_init(&buf->list);
buf->v4l2_buf.sequence = video->frame_count;
buf->v4l2_buf.vb2_buf.timestamp = ktime_get_ns();
vb2_buffer_done(&buf->v4l2_buf.vb2_buf, VB2_BUF_STATE_DONE);
} else {
list_move_tail(&buf->list, &video->out_discard);
}
video->frame_count++;
done:
spin_unlock(&video->buf_lock);
}
static void mxc_isi_video_free_discard_buffers(struct mxc_isi_video *video)
{
unsigned int i;
for (i = 0; i < video->pix.num_planes; i++) {
struct mxc_isi_dma_buffer *buf = &video->discard_buffer[i];
if (!buf->addr)
continue;
dma_free_coherent(video->pipe->isi->dev, buf->size, buf->addr,
buf->dma);
buf->addr = NULL;
}
}
static int mxc_isi_video_alloc_discard_buffers(struct mxc_isi_video *video)
{
unsigned int i, j;
/* Allocate memory for each plane. */
for (i = 0; i < video->pix.num_planes; i++) {
struct mxc_isi_dma_buffer *buf = &video->discard_buffer[i];
buf->size = PAGE_ALIGN(video->pix.plane_fmt[i].sizeimage);
buf->addr = dma_alloc_coherent(video->pipe->isi->dev, buf->size,
&buf->dma, GFP_DMA | GFP_KERNEL);
if (!buf->addr) {
mxc_isi_video_free_discard_buffers(video);
return -ENOMEM;
}
dev_dbg(video->pipe->isi->dev,
"discard buffer plane %u: %zu bytes @%pad (CPU address %p)\n",
i, buf->size, &buf->dma, buf->addr);
}
/* Fill the DMA addresses in the discard buffers. */
for (i = 0; i < ARRAY_SIZE(video->buf_discard); ++i) {
struct mxc_isi_buffer *buf = &video->buf_discard[i];
buf->discard = true;
for (j = 0; j < video->pix.num_planes; ++j)
buf->dma_addrs[j] = video->discard_buffer[j].dma;
}
return 0;
}
static int mxc_isi_video_validate_format(struct mxc_isi_video *video)
{
const struct v4l2_mbus_framefmt *format;
const struct mxc_isi_format_info *info;
struct v4l2_subdev_state *state;
struct v4l2_subdev *sd = &video->pipe->sd;
int ret = 0;
state = v4l2_subdev_lock_and_get_active_state(sd);
info = mxc_isi_format_by_fourcc(video->pix.pixelformat,
MXC_ISI_VIDEO_CAP);
format = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);
if (format->code != info->mbus_code ||
format->width != video->pix.width ||
format->height != video->pix.height) {
dev_dbg(video->pipe->isi->dev,
"%s: configuration mismatch, 0x%04x/%ux%u != 0x%04x/%ux%u\n",
__func__, format->code, format->width, format->height,
info->mbus_code, video->pix.width, video->pix.height);
ret = -EINVAL;
}
v4l2_subdev_unlock_state(state);
return ret;
}
static void mxc_isi_video_return_buffers(struct mxc_isi_video *video,
enum vb2_buffer_state state)
{
struct mxc_isi_buffer *buf;
spin_lock_irq(&video->buf_lock);
while (!list_empty(&video->out_active)) {
buf = list_first_entry(&video->out_active,
struct mxc_isi_buffer, list);
list_del_init(&buf->list);
if (buf->discard)
continue;
vb2_buffer_done(&buf->v4l2_buf.vb2_buf, state);
}
while (!list_empty(&video->out_pending)) {
buf = list_first_entry(&video->out_pending,
struct mxc_isi_buffer, list);
list_del_init(&buf->list);
vb2_buffer_done(&buf->v4l2_buf.vb2_buf, state);
}
while (!list_empty(&video->out_discard)) {
buf = list_first_entry(&video->out_discard,
struct mxc_isi_buffer, list);
list_del_init(&buf->list);
}
INIT_LIST_HEAD(&video->out_active);
INIT_LIST_HEAD(&video->out_pending);
INIT_LIST_HEAD(&video->out_discard);
spin_unlock_irq(&video->buf_lock);
}
static void mxc_isi_video_queue_first_buffers(struct mxc_isi_video *video)
{
unsigned int discard;
unsigned int i;
lockdep_assert_held(&video->buf_lock);
/*
* Queue two ISI channel output buffers. We are not guaranteed to have
* any buffer in the pending list when this function is called from the
* system resume handler. Use pending buffers as much as possible, and
* use discard buffers to fill the remaining slots.
*/
/* How many discard buffers do we need to queue first ? */
discard = list_empty(&video->out_pending) ? 2
: list_is_singular(&video->out_pending) ? 1
: 0;
for (i = 0; i < 2; ++i) {
enum mxc_isi_buf_id buf_id = i == 0 ? MXC_ISI_BUF1
: MXC_ISI_BUF2;
struct mxc_isi_buffer *buf;
struct list_head *list;
list = i < discard ? &video->out_discard : &video->out_pending;
buf = list_first_entry(list, struct mxc_isi_buffer, list);
mxc_isi_channel_set_outbuf(video->pipe, buf->dma_addrs, buf_id);
buf->id = buf_id;
list_move_tail(&buf->list, &video->out_active);
}
}
static inline struct mxc_isi_buffer *to_isi_buffer(struct vb2_v4l2_buffer *v4l2_buf)
{
return container_of(v4l2_buf, struct mxc_isi_buffer, v4l2_buf);
}
int mxc_isi_video_queue_setup(const struct v4l2_pix_format_mplane *format,
const struct mxc_isi_format_info *info,
unsigned int *num_buffers,
unsigned int *num_planes, unsigned int sizes[])
{
unsigned int i;
if (*num_planes) {
if (*num_planes != info->mem_planes)
return -EINVAL;
for (i = 0; i < info->mem_planes; ++i) {
if (sizes[i] < format->plane_fmt[i].sizeimage)
return -EINVAL;
}
return 0;
}
*num_planes = info->mem_planes;
for (i = 0; i < info->mem_planes; ++i)
sizes[i] = format->plane_fmt[i].sizeimage;
return 0;
}
void mxc_isi_video_buffer_init(struct vb2_buffer *vb2, dma_addr_t dma_addrs[3],
const struct mxc_isi_format_info *info,
const struct v4l2_pix_format_mplane *pix)
{
unsigned int i;
for (i = 0; i < info->mem_planes; ++i)
dma_addrs[i] = vb2_dma_contig_plane_dma_addr(vb2, i);
/*
* For single-planar pixel formats with multiple color planes, split
* the buffer into color planes.
*/
if (info->color_planes != info->mem_planes) {
unsigned int size = pix->plane_fmt[0].bytesperline * pix->height;
for (i = 1; i < info->color_planes; ++i) {
unsigned int vsub = i > 1 ? info->vsub : 1;
dma_addrs[i] = dma_addrs[i - 1] + size / vsub;
}
}
}
int mxc_isi_video_buffer_prepare(struct mxc_isi_dev *isi, struct vb2_buffer *vb2,
const struct mxc_isi_format_info *info,
const struct v4l2_pix_format_mplane *pix)
{
unsigned int i;
for (i = 0; i < info->mem_planes; i++) {
unsigned long size = pix->plane_fmt[i].sizeimage;
if (vb2_plane_size(vb2, i) < size) {
dev_err(isi->dev, "User buffer too small (%ld < %ld)\n",
vb2_plane_size(vb2, i), size);
return -EINVAL;
}
vb2_set_plane_payload(vb2, i, size);
}
return 0;
}
static int mxc_isi_vb2_queue_setup(struct vb2_queue *q,
unsigned int *num_buffers,
unsigned int *num_planes,
unsigned int sizes[],
struct device *alloc_devs[])
{
struct mxc_isi_video *video = vb2_get_drv_priv(q);
return mxc_isi_video_queue_setup(&video->pix, video->fmtinfo,
num_buffers, num_planes, sizes);
}
static int mxc_isi_vb2_buffer_init(struct vb2_buffer *vb2)
{
struct mxc_isi_buffer *buf = to_isi_buffer(to_vb2_v4l2_buffer(vb2));
struct mxc_isi_video *video = vb2_get_drv_priv(vb2->vb2_queue);
mxc_isi_video_buffer_init(vb2, buf->dma_addrs, video->fmtinfo,
&video->pix);
return 0;
}
static int mxc_isi_vb2_buffer_prepare(struct vb2_buffer *vb2)
{
struct mxc_isi_video *video = vb2_get_drv_priv(vb2->vb2_queue);
return mxc_isi_video_buffer_prepare(video->pipe->isi, vb2,
video->fmtinfo, &video->pix);
}
static void mxc_isi_vb2_buffer_queue(struct vb2_buffer *vb2)
{
struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb2);
struct mxc_isi_buffer *buf = to_isi_buffer(v4l2_buf);
struct mxc_isi_video *video = vb2_get_drv_priv(vb2->vb2_queue);
spin_lock_irq(&video->buf_lock);
list_add_tail(&buf->list, &video->out_pending);
spin_unlock_irq(&video->buf_lock);
}
static void mxc_isi_video_init_channel(struct mxc_isi_video *video)
{
struct mxc_isi_pipe *pipe = video->pipe;
mxc_isi_channel_get(pipe);
mutex_lock(video->ctrls.handler.lock);
mxc_isi_channel_set_alpha(pipe, video->ctrls.alpha);
mxc_isi_channel_set_flip(pipe, video->ctrls.hflip, video->ctrls.vflip);
mutex_unlock(video->ctrls.handler.lock);
mxc_isi_channel_set_output_format(pipe, video->fmtinfo, &video->pix);
}
static int mxc_isi_vb2_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct mxc_isi_video *video = vb2_get_drv_priv(q);
unsigned int i;
int ret;
/* Initialize the ISI channel. */
mxc_isi_video_init_channel(video);
spin_lock_irq(&video->buf_lock);
/* Add the discard buffers to the out_discard list. */
for (i = 0; i < ARRAY_SIZE(video->buf_discard); ++i) {
struct mxc_isi_buffer *buf = &video->buf_discard[i];
list_add_tail(&buf->list, &video->out_discard);
}
/* Queue the first buffers. */
mxc_isi_video_queue_first_buffers(video);
/* Clear frame count */
video->frame_count = 0;
spin_unlock_irq(&video->buf_lock);
ret = mxc_isi_pipe_enable(video->pipe);
if (ret)
goto error;
return 0;
error:
mxc_isi_channel_put(video->pipe);
mxc_isi_video_return_buffers(video, VB2_BUF_STATE_QUEUED);
return ret;
}
static void mxc_isi_vb2_stop_streaming(struct vb2_queue *q)
{
struct mxc_isi_video *video = vb2_get_drv_priv(q);
mxc_isi_pipe_disable(video->pipe);
mxc_isi_channel_put(video->pipe);
mxc_isi_video_return_buffers(video, VB2_BUF_STATE_ERROR);
}
static const struct vb2_ops mxc_isi_vb2_qops = {
.queue_setup = mxc_isi_vb2_queue_setup,
.buf_init = mxc_isi_vb2_buffer_init,
.buf_prepare = mxc_isi_vb2_buffer_prepare,
.buf_queue = mxc_isi_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = mxc_isi_vb2_start_streaming,
.stop_streaming = mxc_isi_vb2_stop_streaming,
};
/* -----------------------------------------------------------------------------
* V4L2 controls
*/
static inline struct mxc_isi_video *ctrl_to_isi_video(struct v4l2_ctrl *ctrl)
{
return container_of(ctrl->handler, struct mxc_isi_video, ctrls.handler);
}
static int mxc_isi_video_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct mxc_isi_video *video = ctrl_to_isi_video(ctrl);
switch (ctrl->id) {
case V4L2_CID_ALPHA_COMPONENT:
video->ctrls.alpha = ctrl->val;
break;
case V4L2_CID_VFLIP:
video->ctrls.vflip = ctrl->val;
break;
case V4L2_CID_HFLIP:
video->ctrls.hflip = ctrl->val;
break;
}
return 0;
}
static const struct v4l2_ctrl_ops mxc_isi_video_ctrl_ops = {
.s_ctrl = mxc_isi_video_s_ctrl,
};
static int mxc_isi_video_ctrls_create(struct mxc_isi_video *video)
{
struct v4l2_ctrl_handler *handler = &video->ctrls.handler;
int ret;
v4l2_ctrl_handler_init(handler, 3);
v4l2_ctrl_new_std(handler, &mxc_isi_video_ctrl_ops,
V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
v4l2_ctrl_new_std(handler, &mxc_isi_video_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(handler, &mxc_isi_video_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
if (handler->error) {
ret = handler->error;
v4l2_ctrl_handler_free(handler);
return ret;
}
video->vdev.ctrl_handler = handler;
return 0;
}
static void mxc_isi_video_ctrls_delete(struct mxc_isi_video *video)
{
v4l2_ctrl_handler_free(&video->ctrls.handler);
}
/* -----------------------------------------------------------------------------
* V4L2 ioctls
*/
static int mxc_isi_video_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MXC_ISI_DRIVER_NAME, sizeof(cap->driver));
strscpy(cap->card, MXC_ISI_CAPTURE, sizeof(cap->card));
return 0;
}
static int mxc_isi_video_enum_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
const struct mxc_isi_format_info *fmt;
unsigned int index = f->index;
unsigned int i;
if (f->mbus_code) {
/*
* If a media bus code is specified, only enumerate formats
* compatible with it.
*/
for (i = 0; i < ARRAY_SIZE(mxc_isi_formats); i++) {
fmt = &mxc_isi_formats[i];
if (fmt->mbus_code != f->mbus_code)
continue;
if (index == 0)
break;
index--;
}
if (i == ARRAY_SIZE(mxc_isi_formats))
return -EINVAL;
} else {
/* Otherwise, enumerate all formatS. */
if (f->index >= ARRAY_SIZE(mxc_isi_formats))
return -EINVAL;
fmt = &mxc_isi_formats[f->index];
}
f->pixelformat = fmt->fourcc;
f->flags |= V4L2_FMT_FLAG_CSC_COLORSPACE | V4L2_FMT_FLAG_CSC_YCBCR_ENC
| V4L2_FMT_FLAG_CSC_QUANTIZATION | V4L2_FMT_FLAG_CSC_XFER_FUNC;
return 0;
}
static int mxc_isi_video_g_fmt(struct file *file, void *fh,
struct v4l2_format *f)
{
struct mxc_isi_video *video = video_drvdata(file);
f->fmt.pix_mp = video->pix;
return 0;
}
static int mxc_isi_video_try_fmt(struct file *file, void *fh,
struct v4l2_format *f)
{
struct mxc_isi_video *video = video_drvdata(file);
mxc_isi_format_try(video->pipe, &f->fmt.pix_mp, MXC_ISI_VIDEO_CAP);
return 0;
}
static int mxc_isi_video_s_fmt(struct file *file, void *priv,
struct v4l2_format *f)
{
struct mxc_isi_video *video = video_drvdata(file);
struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
if (vb2_is_busy(&video->vb2_q))
return -EBUSY;
video->fmtinfo = mxc_isi_format_try(video->pipe, pix, MXC_ISI_VIDEO_CAP);
video->pix = *pix;
return 0;
}
static int mxc_isi_video_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
struct mxc_isi_video *video = video_drvdata(file);
struct media_device *mdev = &video->pipe->isi->media_dev;
struct media_pipeline *pipe;
int ret;
if (vb2_queue_is_busy(&video->vb2_q, file))
return -EBUSY;
/*
* Get a pipeline for the video node and start it. This must be done
* here and not in the queue .start_streaming() handler, so that
* pipeline start errors can be reported from VIDIOC_STREAMON and not
* delayed until subsequent VIDIOC_QBUF calls.
*/
mutex_lock(&mdev->graph_mutex);
ret = mxc_isi_pipe_acquire(video->pipe, &mxc_isi_video_frame_write_done);
if (ret) {
mutex_unlock(&mdev->graph_mutex);
return ret;
}
pipe = media_entity_pipeline(&video->vdev.entity) ? : &video->pipe->pipe;
ret = __video_device_pipeline_start(&video->vdev, pipe);
if (ret) {
mutex_unlock(&mdev->graph_mutex);
goto err_release;
}
mutex_unlock(&mdev->graph_mutex);
/* Verify that the video format matches the output of the subdev. */
ret = mxc_isi_video_validate_format(video);
if (ret)
goto err_stop;
/* Allocate buffers for discard operation. */
ret = mxc_isi_video_alloc_discard_buffers(video);
if (ret)
goto err_stop;
ret = vb2_streamon(&video->vb2_q, type);
if (ret)
goto err_free;
video->is_streaming = true;
return 0;
err_free:
mxc_isi_video_free_discard_buffers(video);
err_stop:
video_device_pipeline_stop(&video->vdev);
err_release:
mxc_isi_pipe_release(video->pipe);
return ret;
}
static void mxc_isi_video_cleanup_streaming(struct mxc_isi_video *video)
{
lockdep_assert_held(&video->lock);
if (!video->is_streaming)
return;
mxc_isi_video_free_discard_buffers(video);
video_device_pipeline_stop(&video->vdev);
mxc_isi_pipe_release(video->pipe);
video->is_streaming = false;
}
static int mxc_isi_video_streamoff(struct file *file, void *priv,
enum v4l2_buf_type type)
{
struct mxc_isi_video *video = video_drvdata(file);
int ret;
ret = vb2_ioctl_streamoff(file, priv, type);
if (ret)
return ret;
mxc_isi_video_cleanup_streaming(video);
return 0;
}
static int mxc_isi_video_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
struct mxc_isi_video *video = video_drvdata(file);
const struct mxc_isi_format_info *info;
unsigned int max_width;
unsigned int h_align;
unsigned int v_align;
if (fsize->index)
return -EINVAL;
info = mxc_isi_format_by_fourcc(fsize->pixel_format, MXC_ISI_VIDEO_CAP);
if (!info)
return -EINVAL;
h_align = max_t(unsigned int, info->hsub, 1);
v_align = max_t(unsigned int, info->vsub, 1);
max_width = video->pipe->id == video->pipe->isi->pdata->num_channels - 1
? MXC_ISI_MAX_WIDTH_UNCHAINED
: MXC_ISI_MAX_WIDTH_CHAINED;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise.min_width = ALIGN(MXC_ISI_MIN_WIDTH, h_align);
fsize->stepwise.min_height = ALIGN(MXC_ISI_MIN_HEIGHT, v_align);
fsize->stepwise.max_width = ALIGN_DOWN(max_width, h_align);
fsize->stepwise.max_height = ALIGN_DOWN(MXC_ISI_MAX_HEIGHT, v_align);
fsize->stepwise.step_width = h_align;
fsize->stepwise.step_height = v_align;
/*
* The width can be further restricted due to line buffer sharing
* between pipelines when scaling, but we have no way to know here if
* the scaler will be used.
*/
return 0;
}
static const struct v4l2_ioctl_ops mxc_isi_video_ioctl_ops = {
.vidioc_querycap = mxc_isi_video_querycap,
.vidioc_enum_fmt_vid_cap = mxc_isi_video_enum_fmt,
.vidioc_try_fmt_vid_cap_mplane = mxc_isi_video_try_fmt,
.vidioc_s_fmt_vid_cap_mplane = mxc_isi_video_s_fmt,
.vidioc_g_fmt_vid_cap_mplane = mxc_isi_video_g_fmt,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_streamon = mxc_isi_video_streamon,
.vidioc_streamoff = mxc_isi_video_streamoff,
.vidioc_enum_framesizes = mxc_isi_video_enum_framesizes,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/* -----------------------------------------------------------------------------
* Video device file operations
*/
static int mxc_isi_video_open(struct file *file)
{
struct mxc_isi_video *video = video_drvdata(file);
int ret;
ret = v4l2_fh_open(file);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(video->pipe->isi->dev);
if (ret) {
v4l2_fh_release(file);
return ret;
}
return 0;
}
static int mxc_isi_video_release(struct file *file)
{
struct mxc_isi_video *video = video_drvdata(file);
int ret;
ret = vb2_fop_release(file);
if (ret)
dev_err(video->pipe->isi->dev, "%s fail\n", __func__);
mutex_lock(&video->lock);
mxc_isi_video_cleanup_streaming(video);
mutex_unlock(&video->lock);
pm_runtime_put(video->pipe->isi->dev);
return ret;
}
static const struct v4l2_file_operations mxc_isi_video_fops = {
.owner = THIS_MODULE,
.open = mxc_isi_video_open,
.release = mxc_isi_video_release,
.poll = vb2_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = vb2_fop_mmap,
};
/* -----------------------------------------------------------------------------
* Suspend & resume
*/
void mxc_isi_video_suspend(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_video *video = &pipe->video;
if (!video->is_streaming)
return;
mxc_isi_pipe_disable(pipe);
mxc_isi_channel_put(pipe);
spin_lock_irq(&video->buf_lock);
/*
* Move the active buffers back to the pending or discard list. We must
* iterate the active list backward and move the buffers to the head of
* the pending list to preserve the buffer queueing order.
*/
while (!list_empty(&video->out_active)) {
struct mxc_isi_buffer *buf =
list_last_entry(&video->out_active,
struct mxc_isi_buffer, list);
if (buf->discard)
list_move(&buf->list, &video->out_discard);
else
list_move(&buf->list, &video->out_pending);
}
spin_unlock_irq(&video->buf_lock);
}
int mxc_isi_video_resume(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_video *video = &pipe->video;
if (!video->is_streaming)
return 0;
mxc_isi_video_init_channel(video);
spin_lock_irq(&video->buf_lock);
mxc_isi_video_queue_first_buffers(video);
spin_unlock_irq(&video->buf_lock);
return mxc_isi_pipe_enable(pipe);
}
/* -----------------------------------------------------------------------------
* Registration
*/
int mxc_isi_video_register(struct mxc_isi_pipe *pipe,
struct v4l2_device *v4l2_dev)
{
struct mxc_isi_video *video = &pipe->video;
struct v4l2_pix_format_mplane *pix = &video->pix;
struct video_device *vdev = &video->vdev;
struct vb2_queue *q = &video->vb2_q;
int ret = -ENOMEM;
video->pipe = pipe;
mutex_init(&video->lock);
spin_lock_init(&video->buf_lock);
pix->width = MXC_ISI_DEF_WIDTH;
pix->height = MXC_ISI_DEF_HEIGHT;
pix->pixelformat = MXC_ISI_DEF_PIXEL_FORMAT;
pix->colorspace = MXC_ISI_DEF_COLOR_SPACE;
pix->ycbcr_enc = MXC_ISI_DEF_YCBCR_ENC;
pix->quantization = MXC_ISI_DEF_QUANTIZATION;
pix->xfer_func = MXC_ISI_DEF_XFER_FUNC;
video->fmtinfo = mxc_isi_format_try(video->pipe, pix, MXC_ISI_VIDEO_CAP);
memset(vdev, 0, sizeof(*vdev));
snprintf(vdev->name, sizeof(vdev->name), "mxc_isi.%d.capture", pipe->id);
vdev->fops = &mxc_isi_video_fops;
vdev->ioctl_ops = &mxc_isi_video_ioctl_ops;
vdev->v4l2_dev = v4l2_dev;
vdev->minor = -1;
vdev->release = video_device_release_empty;
vdev->queue = q;
vdev->lock = &video->lock;
vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE
| V4L2_CAP_IO_MC;
video_set_drvdata(vdev, video);
INIT_LIST_HEAD(&video->out_pending);
INIT_LIST_HEAD(&video->out_active);
INIT_LIST_HEAD(&video->out_discard);
memset(q, 0, sizeof(*q));
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
q->io_modes = VB2_MMAP | VB2_DMABUF;
q->drv_priv = video;
q->ops = &mxc_isi_vb2_qops;
q->mem_ops = &vb2_dma_contig_memops;
q->buf_struct_size = sizeof(struct mxc_isi_buffer);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->min_buffers_needed = 2;
q->lock = &video->lock;
q->dev = pipe->isi->dev;
ret = vb2_queue_init(q);
if (ret)
goto err_free_ctx;
video->pad.flags = MEDIA_PAD_FL_SINK;
vdev->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
ret = media_entity_pads_init(&vdev->entity, 1, &video->pad);
if (ret)
goto err_free_ctx;
ret = mxc_isi_video_ctrls_create(video);
if (ret)
goto err_me_cleanup;
ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
if (ret)
goto err_ctrl_free;
ret = media_create_pad_link(&pipe->sd.entity,
MXC_ISI_PIPE_PAD_SOURCE,
&vdev->entity, 0,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret)
goto err_video_unreg;
return 0;
err_video_unreg:
video_unregister_device(vdev);
err_ctrl_free:
mxc_isi_video_ctrls_delete(video);
err_me_cleanup:
media_entity_cleanup(&vdev->entity);
err_free_ctx:
return ret;
}
void mxc_isi_video_unregister(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_video *video = &pipe->video;
struct video_device *vdev = &video->vdev;
mutex_lock(&video->lock);
if (video_is_registered(vdev)) {
video_unregister_device(vdev);
mxc_isi_video_ctrls_delete(video);
media_entity_cleanup(&vdev->entity);
}
mutex_unlock(&video->lock);
}
| linux-master | drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c |
// SPDX-License-Identifier: GPL-2.0
/*
* i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
*
* Copyright 2018-2019 NXP
*/
#include <linux/delay.h>
#include <media/videobuf2-core.h>
#include "mxc-jpeg-hw.h"
#define print_wrapper_reg(dev, base_address, reg_offset)\
internal_print_wrapper_reg(dev, (base_address), #reg_offset,\
(reg_offset))
#define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\
int val;\
val = readl((base_address) + (reg_offset));\
dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\
}
void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc)
{
dev_dbg(dev, " MXC JPEG NEXT_DESCPT_PTR 0x%x\n",
desc->next_descpt_ptr);
dev_dbg(dev, " MXC JPEG BUF_BASE0 0x%x\n", desc->buf_base0);
dev_dbg(dev, " MXC JPEG BUF_BASE1 0x%x\n", desc->buf_base1);
dev_dbg(dev, " MXC JPEG LINE_PITCH %d\n", desc->line_pitch);
dev_dbg(dev, " MXC JPEG STM_BUFBASE 0x%x\n", desc->stm_bufbase);
dev_dbg(dev, " MXC JPEG STM_BUFSIZE %d\n", desc->stm_bufsize);
dev_dbg(dev, " MXC JPEG IMGSIZE %x (%d x %d)\n", desc->imgsize,
desc->imgsize >> 16, desc->imgsize & 0xFFFF);
dev_dbg(dev, " MXC JPEG STM_CTRL 0x%x\n", desc->stm_ctrl);
}
void print_cast_status(struct device *dev, void __iomem *reg,
unsigned int mode)
{
dev_dbg(dev, "CAST IP status regs:\n");
print_wrapper_reg(dev, reg, CAST_STATUS0);
print_wrapper_reg(dev, reg, CAST_STATUS1);
print_wrapper_reg(dev, reg, CAST_STATUS2);
print_wrapper_reg(dev, reg, CAST_STATUS3);
print_wrapper_reg(dev, reg, CAST_STATUS4);
print_wrapper_reg(dev, reg, CAST_STATUS5);
print_wrapper_reg(dev, reg, CAST_STATUS6);
print_wrapper_reg(dev, reg, CAST_STATUS7);
print_wrapper_reg(dev, reg, CAST_STATUS8);
print_wrapper_reg(dev, reg, CAST_STATUS9);
print_wrapper_reg(dev, reg, CAST_STATUS10);
print_wrapper_reg(dev, reg, CAST_STATUS11);
print_wrapper_reg(dev, reg, CAST_STATUS12);
print_wrapper_reg(dev, reg, CAST_STATUS13);
if (mode == MXC_JPEG_DECODE)
return;
print_wrapper_reg(dev, reg, CAST_STATUS14);
print_wrapper_reg(dev, reg, CAST_STATUS15);
print_wrapper_reg(dev, reg, CAST_STATUS16);
print_wrapper_reg(dev, reg, CAST_STATUS17);
print_wrapper_reg(dev, reg, CAST_STATUS18);
print_wrapper_reg(dev, reg, CAST_STATUS19);
}
void print_wrapper_info(struct device *dev, void __iomem *reg)
{
dev_dbg(dev, "Wrapper regs:\n");
print_wrapper_reg(dev, reg, GLB_CTRL);
print_wrapper_reg(dev, reg, COM_STATUS);
print_wrapper_reg(dev, reg, BUF_BASE0);
print_wrapper_reg(dev, reg, BUF_BASE1);
print_wrapper_reg(dev, reg, LINE_PITCH);
print_wrapper_reg(dev, reg, STM_BUFBASE);
print_wrapper_reg(dev, reg, STM_BUFSIZE);
print_wrapper_reg(dev, reg, IMGSIZE);
print_wrapper_reg(dev, reg, STM_CTRL);
}
void mxc_jpeg_enable_irq(void __iomem *reg, int slot)
{
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
writel(0xF0C, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
}
void mxc_jpeg_disable_irq(void __iomem *reg, int slot)
{
writel(0x0, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
}
void mxc_jpeg_sw_reset(void __iomem *reg)
{
/*
* engine soft reset, internal state machine reset
* this will not reset registers, however, it seems
* the registers may remain inconsistent with the internal state
* so, on purpose, at least let GLB_CTRL bits clear after this reset
*/
writel(GLB_CTRL_SFT_RST, reg + GLB_CTRL);
}
void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg, u8 extseq)
{
dev_dbg(dev, "CAST Encoder CONFIG...\n");
/*
* "Config_Mode" enabled, "Config_Mode auto clear enabled",
*/
if (extseq)
writel(0xb0, reg + CAST_MODE);
else
writel(0xa0, reg + CAST_MODE);
/* all markers and segments */
writel(0x3ff, reg + CAST_CFG_MODE);
}
void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg, u8 extseq)
{
dev_dbg(dev, "CAST Encoder GO...\n");
/*
* "GO" enabled, "GO bit auto clear" enabled
*/
if (extseq)
writel(0x150, reg + CAST_MODE);
else
writel(0x140, reg + CAST_MODE);
}
void mxc_jpeg_enc_set_quality(struct device *dev, void __iomem *reg, u8 quality)
{
dev_dbg(dev, "CAST Encoder Quality %d...\n", quality);
/* quality factor */
writel(quality, reg + CAST_QUALITY);
}
void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg)
{
dev_dbg(dev, "CAST Decoder GO...\n");
writel(MXC_DEC_EXIT_IDLE_MODE, reg + CAST_CTRL);
}
int mxc_jpeg_enable(void __iomem *reg)
{
u32 regval;
writel(GLB_CTRL_JPG_EN, reg + GLB_CTRL);
regval = readl(reg);
return regval;
}
void mxc_jpeg_enable_slot(void __iomem *reg, int slot)
{
u32 regval;
regval = readl(reg + GLB_CTRL);
writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);
}
void mxc_jpeg_set_l_endian(void __iomem *reg, int le)
{
u32 regval;
regval = readl(reg + GLB_CTRL);
regval &= ~GLB_CTRL_L_ENDIAN(1); /* clear */
writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */
}
void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc, u32 bufsize)
{
desc->stm_bufsize = bufsize;
}
void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h)
{
desc->imgsize = w << 16 | h;
}
void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch)
{
desc->line_pitch = line_pitch;
}
void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot)
{
writel(desc | MXC_NXT_DESCPT_EN,
reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));
}
void mxc_jpeg_clr_desc(void __iomem *reg, int slot)
{
writel(0, reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));
}
| linux-master | drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* V4L2 driver for the JPEG encoder/decoder from i.MX8QXP/i.MX8QM application
* processors.
*
* The multi-planar buffers API is used.
*
* Baseline and extended sequential jpeg decoding is supported.
* Progressive jpeg decoding is not supported by the IP.
* Supports encode and decode of various formats:
* YUV444, YUV422, YUV420, BGR, ABGR, Gray
* YUV420 is the only multi-planar format supported.
* Minimum resolution is 64 x 64, maximum 8192 x 8192.
* To achieve 8192 x 8192, modify in defconfig: CONFIG_CMA_SIZE_MBYTES=320
* The alignment requirements for the resolution depend on the format,
* multiple of 16 resolutions should work for all formats.
* Special workarounds are made in the driver to support NV12 1080p.
* When decoding, the driver detects image resolution and pixel format
* from the jpeg stream, by parsing the jpeg markers.
*
* The IP has 4 slots available for context switching, but only slot 0
* was fully tested to work. Context switching is not used by the driver.
* Each driver instance (context) allocates a slot for itself, but this
* is postponed until device_run, to allow unlimited opens.
*
* The driver submits jobs to the IP by setting up a descriptor for the
* used slot, and then validating it. The encoder has an additional descriptor
* for the configuration phase. The driver expects FRM_DONE interrupt from
* IP to mark the job as finished.
*
* The decoder IP has some limitations regarding the component ID's,
* but the driver works around this by replacing them in the jpeg stream.
*
* A module parameter is available for debug purpose (jpeg_tracing), to enable
* it, enable dynamic debug for this module and:
* echo 1 > /sys/module/mxc_jpeg_encdec/parameters/jpeg_tracing
*
* This is inspired by the drivers/media/platform/samsung/s5p-jpeg driver
*
* Copyright 2018-2019 NXP
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/irqreturn.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/pm_domain.h>
#include <linux/string.h>
#include <media/v4l2-jpeg.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include <media/v4l2-event.h>
#include <media/videobuf2-dma-contig.h>
#include "mxc-jpeg-hw.h"
#include "mxc-jpeg.h"
static const struct mxc_jpeg_fmt mxc_formats[] = {
{
.name = "JPEG",
.fourcc = V4L2_PIX_FMT_JPEG,
.subsampling = -1,
.nc = -1,
.mem_planes = 1,
.comp_planes = 1,
.flags = MXC_JPEG_FMT_TYPE_ENC,
},
{
.name = "BGR", /*BGR packed format*/
.fourcc = V4L2_PIX_FMT_BGR24,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 3,
.depth = 24,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
.is_rgb = 1,
},
{
.name = "BGR 12bit", /*12-bit BGR packed format*/
.fourcc = V4L2_PIX_FMT_BGR48_12,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 3,
.depth = 36,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
.is_rgb = 1,
},
{
.name = "ABGR", /* ABGR packed format */
.fourcc = V4L2_PIX_FMT_ABGR32,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 4,
.depth = 32,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
.is_rgb = 1,
},
{
.name = "ABGR 12bit", /* 12-bit ABGR packed format */
.fourcc = V4L2_PIX_FMT_ABGR64_12,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 4,
.depth = 48,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
.is_rgb = 1,
},
{
.name = "YUV420", /* 1st plane = Y, 2nd plane = UV */
.fourcc = V4L2_PIX_FMT_NV12M,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_420,
.nc = 3,
.depth = 12, /* 6 bytes (4Y + UV) for 4 pixels */
.mem_planes = 2,
.comp_planes = 2, /* 1 plane Y, 1 plane UV interleaved */
.h_align = 4,
.v_align = 4,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
},
{
.name = "YUV420", /* 1st plane = Y, 2nd plane = UV */
.fourcc = V4L2_PIX_FMT_NV12,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_420,
.nc = 3,
.depth = 12, /* 6 bytes (4Y + UV) for 4 pixels */
.mem_planes = 1,
.comp_planes = 2, /* 1 plane Y, 1 plane UV interleaved */
.h_align = 4,
.v_align = 4,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
},
{
.name = "YUV420 12bit", /* 1st plane = Y, 2nd plane = UV */
.fourcc = V4L2_PIX_FMT_P012M,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_420,
.nc = 3,
.depth = 18, /* 6 x 12 bits (4Y + UV) for 4 pixels */
.mem_planes = 2,
.comp_planes = 2, /* 1 plane Y, 1 plane UV interleaved */
.h_align = 4,
.v_align = 4,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
},
{
.name = "YUV420 12bit", /* 1st plane = Y, 2nd plane = UV */
.fourcc = V4L2_PIX_FMT_P012,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_420,
.nc = 3,
.depth = 18, /* 6 x 12 bits (4Y + UV) for 4 pixels */
.mem_planes = 1,
.comp_planes = 2, /* 1 plane Y, 1 plane UV interleaved */
.h_align = 4,
.v_align = 4,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
},
{
.name = "YUV422", /* YUYV */
.fourcc = V4L2_PIX_FMT_YUYV,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_422,
.nc = 3,
.depth = 16,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 4,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
},
{
.name = "YUV422 12bit", /* YUYV */
.fourcc = V4L2_PIX_FMT_Y212,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_422,
.nc = 3,
.depth = 24,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 4,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
},
{
.name = "YUV444", /* YUVYUV */
.fourcc = V4L2_PIX_FMT_YUV24,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 3,
.depth = 24,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
},
{
.name = "YUV444 12bit", /* YUVYUV */
.fourcc = V4L2_PIX_FMT_YUV48_12,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444,
.nc = 3,
.depth = 36,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
},
{
.name = "Gray", /* Gray (Y8/Y12) or Single Comp */
.fourcc = V4L2_PIX_FMT_GREY,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY,
.nc = 1,
.depth = 8,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 8,
},
{
.name = "Gray 12bit", /* Gray (Y8/Y12) or Single Comp */
.fourcc = V4L2_PIX_FMT_Y012,
.subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY,
.nc = 1,
.depth = 12,
.mem_planes = 1,
.comp_planes = 1,
.h_align = 3,
.v_align = 3,
.flags = MXC_JPEG_FMT_TYPE_RAW,
.precision = 12,
},
};
#define MXC_JPEG_NUM_FORMATS ARRAY_SIZE(mxc_formats)
static const int mxc_decode_mode = MXC_JPEG_DECODE;
static const int mxc_encode_mode = MXC_JPEG_ENCODE;
static const struct of_device_id mxc_jpeg_match[] = {
{
.compatible = "nxp,imx8qxp-jpgdec",
.data = &mxc_decode_mode,
},
{
.compatible = "nxp,imx8qxp-jpgenc",
.data = &mxc_encode_mode,
},
{ },
};
/*
* default configuration stream, 64x64 yuv422
* split by JPEG marker, so it's easier to modify & use
*/
static const unsigned char jpeg_soi[] = {
0xFF, 0xD8
};
static const unsigned char jpeg_app0[] = {
0xFF, 0xE0,
0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00,
0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x01,
0x00, 0x00
};
static const unsigned char jpeg_app14[] = {
0xFF, 0xEE,
0x00, 0x0E, 0x41, 0x64, 0x6F, 0x62, 0x65,
0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const unsigned char jpeg_dqt[] = {
0xFF, 0xDB,
0x00, 0x84, 0x00, 0x10, 0x0B, 0x0C, 0x0E,
0x0C, 0x0A, 0x10, 0x0E, 0x0D, 0x0E, 0x12,
0x11, 0x10, 0x13, 0x18, 0x28, 0x1A, 0x18,
0x16, 0x16, 0x18, 0x31, 0x23, 0x25, 0x1D,
0x28, 0x3A, 0x33, 0x3D, 0x3C, 0x39, 0x33,
0x38, 0x37, 0x40, 0x48, 0x5C, 0x4E, 0x40,
0x44, 0x57, 0x45, 0x37, 0x38, 0x50, 0x6D,
0x51, 0x57, 0x5F, 0x62, 0x67, 0x68, 0x67,
0x3E, 0x4D, 0x71, 0x79, 0x70, 0x64, 0x78,
0x5C, 0x65, 0x67, 0x63, 0x01, 0x11, 0x12,
0x12, 0x18, 0x15, 0x18, 0x2F, 0x1A, 0x1A,
0x2F, 0x63, 0x42, 0x38, 0x42, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63
};
static const unsigned char jpeg_dqt_extseq[] = {
0xFF, 0xDB,
0x01, 0x04,
0x10,
0x00, 0x80, 0x00, 0x58, 0x00, 0x60, 0x00, 0x70,
0x00, 0x60, 0x00, 0x50, 0x00, 0x80, 0x00, 0x70,
0x00, 0x68, 0x00, 0x70, 0x00, 0x90, 0x00, 0x88,
0x00, 0x80, 0x00, 0x98, 0x00, 0xC0, 0x01, 0x40,
0x00, 0xD0, 0x00, 0xC0, 0x00, 0xB0, 0x00, 0xB0,
0x00, 0xC0, 0x01, 0x88, 0x01, 0x18, 0x01, 0x28,
0x00, 0xE8, 0x01, 0x40, 0x01, 0xD0, 0x01, 0x98,
0x01, 0xE8, 0x01, 0xE0, 0x01, 0xC8, 0x01, 0x98,
0x01, 0xC0, 0x01, 0xB8, 0x02, 0x00, 0x02, 0x40,
0x02, 0xE0, 0x02, 0x70, 0x02, 0x00, 0x02, 0x20,
0x02, 0xB8, 0x02, 0x28, 0x01, 0xB8, 0x01, 0xC0,
0x02, 0x80, 0x03, 0x68, 0x02, 0x88, 0x02, 0xB8,
0x02, 0xF8, 0x03, 0x10, 0x03, 0x38, 0x03, 0x40,
0x03, 0x38, 0x01, 0xF0, 0x02, 0x68, 0x03, 0x88,
0x03, 0xC8, 0x03, 0x80, 0x03, 0x20, 0x03, 0xC0,
0x02, 0xE0, 0x03, 0x28, 0x03, 0x38, 0x03, 0x18,
0x11,
0x00, 0x88, 0x00, 0x90, 0x00, 0x90, 0x00, 0xC0,
0x00, 0xA8, 0x00, 0xC0, 0x01, 0x78, 0x00, 0xD0,
0x00, 0xD0, 0x01, 0x78, 0x03, 0x18, 0x02, 0x10,
0x01, 0xC0, 0x02, 0x10, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
0x03, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x18,
};
static const unsigned char jpeg_sof_maximal[] = {
0xFF, 0xC0,
0x00, 0x14, 0x08, 0x00, 0x40, 0x00, 0x40,
0x04, 0x01, 0x11, 0x00, 0x02, 0x11, 0x01,
0x03, 0x11, 0x01, 0x04, 0x11, 0x01
};
static const unsigned char jpeg_sof_extseq[] = {
0xFF, 0xC1,
0x00, 0x14, 0x08, 0x00, 0x40, 0x00, 0x40,
0x04, 0x01, 0x11, 0x00, 0x02, 0x11, 0x01,
0x03, 0x11, 0x01, 0x04, 0x11, 0x01
};
static const unsigned char jpeg_dht[] = {
0xFF, 0xC4,
0x01, 0xA2, 0x00, 0x00, 0x01, 0x05, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
0x09, 0x0A, 0x0B, 0x10, 0x00, 0x02, 0x01,
0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05,
0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01,
0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61,
0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91,
0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15,
0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72,
0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19,
0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A,
0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A,
0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85,
0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93,
0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A,
0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6,
0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4,
0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3,
0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA,
0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A,
0x0B, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04,
0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04,
0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02,
0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06,
0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13,
0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52,
0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16,
0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43,
0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A,
0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85,
0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93,
0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A,
0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6,
0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4,
0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
0xF6, 0xF7, 0xF8, 0xF9, 0xFA
};
static const unsigned char jpeg_dht_extseq[] = {
0xFF, 0xC4,
0x02, 0x2a, 0x00, 0x00, 0x01, 0x05, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02,
0x04, 0x03, 0x05, 0x05, 0x02, 0x03, 0x02,
0x00, 0x00, 0xbf, 0x01, 0x02, 0x03, 0x00,
0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41,
0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71,
0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, 0x23,
0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a,
0x16, 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26,
0x27, 0x28, 0x29, 0x2a, 0x34, 0x35, 0x36,
0x37, 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45,
0x46, 0x47, 0x48, 0x49, 0x4a, 0x53, 0x54,
0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x63,
0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a,
0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4,
0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2,
0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9,
0xba, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, 0xd5,
0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
0xea, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6,
0xf7, 0xf8, 0xf9, 0xfa, 0x0b, 0x0c, 0x0d,
0x0e, 0x1b, 0x1c, 0x1d, 0x1e, 0x2b, 0x2c,
0x2d, 0x2e, 0x3b, 0x3c, 0x3d, 0x3e, 0x4b,
0x4c, 0x4d, 0x4e, 0x5b, 0x5c, 0x5d, 0x5e,
0x6b, 0x6c, 0x6d, 0x6e, 0x7b, 0x7c, 0x7d,
0x7e, 0x8b, 0x8c, 0x8d, 0x8e, 0x9b, 0x9c,
0x9d, 0x9e, 0xab, 0xac, 0xad, 0xae, 0xbb,
0xbc, 0xbd, 0xbe, 0xcb, 0xcc, 0xcd, 0xce,
0xdb, 0xdc, 0xdd, 0xde, 0xeb, 0xec, 0xed,
0xee, 0xfb, 0xfc, 0xfd, 0xfe, 0x01, 0x00,
0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00,
0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
0x0d, 0x0e, 0x0f, 0x11, 0x00, 0x02, 0x01,
0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05,
0x02, 0x03, 0x02, 0x00, 0x00, 0xbf, 0x01,
0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61,
0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91,
0xa1, 0x08, 0x23, 0x42, 0xb1, 0xc1, 0x15,
0x52, 0xd1, 0xf0, 0x24, 0x33, 0x62, 0x72,
0x82, 0x09, 0x0a, 0x16, 0x17, 0x18, 0x19,
0x1a, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a,
0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a,
0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76,
0x77, 0x78, 0x79, 0x7a, 0x83, 0x84, 0x85,
0x86, 0x87, 0x88, 0x89, 0x8a, 0x92, 0x93,
0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a,
0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8,
0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4,
0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9,
0xda, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6,
0xe7, 0xe8, 0xe9, 0xea, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa,
0x0b, 0x0c, 0x0d, 0x0e, 0x1b, 0x1c, 0x1d,
0x1e, 0x2b, 0x2c, 0x2d, 0x2e, 0x3b, 0x3c,
0x3d, 0x3e, 0x4b, 0x4c, 0x4d, 0x4e, 0x5b,
0x5c, 0x5d, 0x5e, 0x6b, 0x6c, 0x6d, 0x6e,
0x7b, 0x7c, 0x7d, 0x7e, 0x8b, 0x8c, 0x8d,
0x8e, 0x9b, 0x9c, 0x9d, 0x9e, 0xab, 0xac,
0xad, 0xae, 0xbb, 0xbc, 0xbd, 0xbe, 0xcb,
0xcc, 0xcd, 0xce, 0xdb, 0xdc, 0xdd, 0xde,
0xeb, 0xec, 0xed, 0xee, 0xfb, 0xfc, 0xfd,
0xfe,
};
static const unsigned char jpeg_dri[] = {
0xFF, 0xDD,
0x00, 0x04, 0x00, 0x20
};
static const unsigned char jpeg_sos_maximal[] = {
0xFF, 0xDA,
0x00, 0x0C, 0x04, 0x01, 0x00, 0x02, 0x11, 0x03,
0x11, 0x04, 0x11, 0x00, 0x3F, 0x00
};
static const unsigned char jpeg_image_red[] = {
0xFC, 0x5F, 0xA2, 0xBF, 0xCA, 0x73, 0xFE, 0xFE,
0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00,
0x28, 0xA0, 0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02,
0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00, 0x28,
0xA0, 0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A,
0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00, 0x28, 0xA0,
0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00,
0x28, 0xA0, 0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02,
0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00, 0x28,
0xA0, 0x02, 0x8A, 0x00, 0x28, 0xA0, 0x02, 0x8A,
0x00, 0x28, 0xA0, 0x02, 0x8A, 0x00
};
static const unsigned char jpeg_eoi[] = {
0xFF, 0xD9
};
struct mxc_jpeg_src_buf {
/* common v4l buffer stuff -- must be first */
struct vb2_v4l2_buffer b;
struct list_head list;
/* mxc-jpeg specific */
bool dht_needed;
bool jpeg_parse_error;
const struct mxc_jpeg_fmt *fmt;
int w;
int h;
};
static inline struct mxc_jpeg_src_buf *vb2_to_mxc_buf(struct vb2_buffer *vb)
{
return container_of(to_vb2_v4l2_buffer(vb),
struct mxc_jpeg_src_buf, b);
}
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-3)");
static unsigned int hw_timeout = 2000;
module_param(hw_timeout, int, 0644);
MODULE_PARM_DESC(hw_timeout, "MXC JPEG hw timeout, the number of milliseconds");
static void mxc_jpeg_bytesperline(struct mxc_jpeg_q_data *q, u32 precision);
static void mxc_jpeg_sizeimage(struct mxc_jpeg_q_data *q);
static void _bswap16(u16 *a)
{
*a = ((*a & 0x00FF) << 8) | ((*a & 0xFF00) >> 8);
}
static void print_mxc_buf(struct mxc_jpeg_dev *jpeg, struct vb2_buffer *buf,
unsigned long len)
{
unsigned int plane_no;
u32 dma_addr;
void *vaddr;
unsigned long payload;
if (debug < 3)
return;
for (plane_no = 0; plane_no < buf->num_planes; plane_no++) {
payload = vb2_get_plane_payload(buf, plane_no);
if (len == 0)
len = payload;
dma_addr = vb2_dma_contig_plane_dma_addr(buf, plane_no);
vaddr = vb2_plane_vaddr(buf, plane_no);
v4l2_dbg(3, debug, &jpeg->v4l2_dev,
"plane %d (vaddr=%p dma_addr=%x payload=%ld):",
plane_no, vaddr, dma_addr, payload);
print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1,
vaddr, len, false);
}
}
static inline struct mxc_jpeg_ctx *mxc_jpeg_fh_to_ctx(struct v4l2_fh *fh)
{
return container_of(fh, struct mxc_jpeg_ctx, fh);
}
static int enum_fmt(const struct mxc_jpeg_fmt *mxc_formats, int n,
struct v4l2_fmtdesc *f, u32 type)
{
int i, num = 0;
for (i = 0; i < n; ++i) {
if (mxc_formats[i].flags == type) {
/* index-th format of searched type found ? */
if (num == f->index)
break;
/* Correct type but haven't reached our index yet,
* just increment per-type index
*/
++num;
}
}
/* Format not found */
if (i >= n)
return -EINVAL;
f->pixelformat = mxc_formats[i].fourcc;
return 0;
}
static const struct mxc_jpeg_fmt *mxc_jpeg_find_format(u32 pixelformat)
{
unsigned int k;
for (k = 0; k < MXC_JPEG_NUM_FORMATS; k++) {
const struct mxc_jpeg_fmt *fmt = &mxc_formats[k];
if (fmt->fourcc == pixelformat)
return fmt;
}
return NULL;
}
static enum mxc_jpeg_image_format mxc_jpeg_fourcc_to_imgfmt(u32 fourcc)
{
switch (fourcc) {
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y012:
return MXC_JPEG_GRAY;
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_Y212:
return MXC_JPEG_YUV422;
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV12M:
case V4L2_PIX_FMT_P012:
case V4L2_PIX_FMT_P012M:
return MXC_JPEG_YUV420;
case V4L2_PIX_FMT_YUV24:
case V4L2_PIX_FMT_YUV48_12:
return MXC_JPEG_YUV444;
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_BGR48_12:
return MXC_JPEG_BGR;
case V4L2_PIX_FMT_ABGR32:
case V4L2_PIX_FMT_ABGR64_12:
return MXC_JPEG_ABGR;
default:
return MXC_JPEG_INVALID;
}
}
static struct mxc_jpeg_q_data *mxc_jpeg_get_q_data(struct mxc_jpeg_ctx *ctx,
enum v4l2_buf_type type)
{
if (V4L2_TYPE_IS_OUTPUT(type))
return &ctx->out_q;
return &ctx->cap_q;
}
static void mxc_jpeg_addrs(struct mxc_jpeg_desc *desc,
struct vb2_buffer *raw_buf,
struct vb2_buffer *jpeg_buf, int offset)
{
int img_fmt = desc->stm_ctrl & STM_CTRL_IMAGE_FORMAT_MASK;
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(raw_buf->vb2_queue);
struct mxc_jpeg_q_data *q_data;
q_data = mxc_jpeg_get_q_data(ctx, raw_buf->type);
desc->buf_base0 = vb2_dma_contig_plane_dma_addr(raw_buf, 0);
desc->buf_base1 = 0;
if (img_fmt == STM_CTRL_IMAGE_FORMAT(MXC_JPEG_YUV420)) {
if (raw_buf->num_planes == 2)
desc->buf_base1 = vb2_dma_contig_plane_dma_addr(raw_buf, 1);
else
desc->buf_base1 = desc->buf_base0 + q_data->sizeimage[0];
}
desc->stm_bufbase = vb2_dma_contig_plane_dma_addr(jpeg_buf, 0) +
offset;
}
static bool mxc_jpeg_is_extended_sequential(const struct mxc_jpeg_fmt *fmt)
{
if (!fmt || !(fmt->flags & MXC_JPEG_FMT_TYPE_RAW))
return false;
if (fmt->precision > 8)
return true;
return false;
}
static void notify_eos(struct mxc_jpeg_ctx *ctx)
{
const struct v4l2_event ev = {
.type = V4L2_EVENT_EOS
};
dev_dbg(ctx->mxc_jpeg->dev, "Notify app event EOS reached");
v4l2_event_queue_fh(&ctx->fh, &ev);
}
static void notify_src_chg(struct mxc_jpeg_ctx *ctx)
{
const struct v4l2_event ev = {
.type = V4L2_EVENT_SOURCE_CHANGE,
.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
};
dev_dbg(ctx->mxc_jpeg->dev, "Notify app event SRC_CH_RESOLUTION");
v4l2_event_queue_fh(&ctx->fh, &ev);
}
static int mxc_get_free_slot(struct mxc_jpeg_slot_data *slot_data)
{
if (!slot_data->used)
return slot_data->slot;
return -1;
}
static bool mxc_jpeg_alloc_slot_data(struct mxc_jpeg_dev *jpeg)
{
struct mxc_jpeg_desc *desc;
struct mxc_jpeg_desc *cfg_desc;
void *cfg_stm;
if (jpeg->slot_data.desc)
goto skip_alloc; /* already allocated, reuse it */
/* allocate descriptor for decoding/encoding phase */
desc = dma_alloc_coherent(jpeg->dev,
sizeof(struct mxc_jpeg_desc),
&jpeg->slot_data.desc_handle,
GFP_ATOMIC);
if (!desc)
goto err;
jpeg->slot_data.desc = desc;
/* allocate descriptor for configuration phase (encoder only) */
cfg_desc = dma_alloc_coherent(jpeg->dev,
sizeof(struct mxc_jpeg_desc),
&jpeg->slot_data.cfg_desc_handle,
GFP_ATOMIC);
if (!cfg_desc)
goto err;
jpeg->slot_data.cfg_desc = cfg_desc;
/* allocate configuration stream */
cfg_stm = dma_alloc_coherent(jpeg->dev,
MXC_JPEG_MAX_CFG_STREAM,
&jpeg->slot_data.cfg_stream_handle,
GFP_ATOMIC);
if (!cfg_stm)
goto err;
jpeg->slot_data.cfg_stream_vaddr = cfg_stm;
skip_alloc:
jpeg->slot_data.used = true;
return true;
err:
dev_err(jpeg->dev, "Could not allocate descriptors for slot %d", jpeg->slot_data.slot);
return false;
}
static void mxc_jpeg_free_slot_data(struct mxc_jpeg_dev *jpeg)
{
/* free descriptor for decoding/encoding phase */
dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc),
jpeg->slot_data.desc,
jpeg->slot_data.desc_handle);
/* free descriptor for encoder configuration phase / decoder DHT */
dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc),
jpeg->slot_data.cfg_desc,
jpeg->slot_data.cfg_desc_handle);
/* free configuration stream */
dma_free_coherent(jpeg->dev, MXC_JPEG_MAX_CFG_STREAM,
jpeg->slot_data.cfg_stream_vaddr,
jpeg->slot_data.cfg_stream_handle);
jpeg->slot_data.used = false;
}
static void mxc_jpeg_check_and_set_last_buffer(struct mxc_jpeg_ctx *ctx,
struct vb2_v4l2_buffer *src_buf,
struct vb2_v4l2_buffer *dst_buf)
{
if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src_buf)) {
dst_buf->flags |= V4L2_BUF_FLAG_LAST;
v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx);
notify_eos(ctx);
ctx->header_parsed = false;
}
}
static void mxc_jpeg_job_finish(struct mxc_jpeg_ctx *ctx, enum vb2_buffer_state state, bool reset)
{
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
mxc_jpeg_check_and_set_last_buffer(ctx, src_buf, dst_buf);
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, state);
v4l2_m2m_buf_done(dst_buf, state);
mxc_jpeg_disable_irq(reg, ctx->slot);
jpeg->slot_data.used = false;
if (reset)
mxc_jpeg_sw_reset(reg);
}
static u32 mxc_jpeg_get_plane_size(struct mxc_jpeg_q_data *q_data, u32 plane_no)
{
const struct mxc_jpeg_fmt *fmt = q_data->fmt;
u32 size;
int i;
if (plane_no >= fmt->mem_planes)
return 0;
if (fmt->mem_planes == fmt->comp_planes)
return q_data->sizeimage[plane_no];
if (plane_no < fmt->mem_planes - 1)
return q_data->sizeimage[plane_no];
size = q_data->sizeimage[fmt->mem_planes - 1];
/* Should be impossible given mxc_formats. */
if (WARN_ON_ONCE(fmt->comp_planes > ARRAY_SIZE(q_data->sizeimage)))
return size;
for (i = fmt->mem_planes; i < fmt->comp_planes; i++)
size += q_data->sizeimage[i];
return size;
}
static irqreturn_t mxc_jpeg_dec_irq(int irq, void *priv)
{
struct mxc_jpeg_dev *jpeg = priv;
struct mxc_jpeg_ctx *ctx;
void __iomem *reg = jpeg->base_reg;
struct device *dev = jpeg->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mxc_jpeg_src_buf *jpeg_src_buf;
enum vb2_buffer_state buf_state;
u32 dec_ret, com_status;
unsigned long payload;
struct mxc_jpeg_q_data *q_data;
enum v4l2_buf_type cap_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
unsigned int slot;
spin_lock(&jpeg->hw_lock);
com_status = readl(reg + COM_STATUS);
slot = COM_STATUS_CUR_SLOT(com_status);
dev_dbg(dev, "Irq %d on slot %d.\n", irq, slot);
ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev);
if (WARN_ON(!ctx))
goto job_unlock;
if (slot != ctx->slot) {
/* TODO investigate when adding multi-instance support */
dev_warn(dev, "IRQ slot %d != context slot %d.\n",
slot, ctx->slot);
goto job_unlock;
}
if (!jpeg->slot_data.used)
goto job_unlock;
dec_ret = readl(reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
writel(dec_ret, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS)); /* w1c */
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
if (!dst_buf || !src_buf) {
dev_err(dev, "No source or destination buffer.\n");
goto job_unlock;
}
jpeg_src_buf = vb2_to_mxc_buf(&src_buf->vb2_buf);
if (dec_ret & SLOT_STATUS_ENC_CONFIG_ERR) {
u32 ret = readl(reg + CAST_STATUS12);
dev_err(dev, "Encoder/decoder error, dec_ret = 0x%08x, status=0x%08x",
dec_ret, ret);
mxc_jpeg_clr_desc(reg, slot);
mxc_jpeg_sw_reset(reg);
buf_state = VB2_BUF_STATE_ERROR;
goto buffers_done;
}
if (!(dec_ret & SLOT_STATUS_FRMDONE))
goto job_unlock;
if (jpeg->mode == MXC_JPEG_ENCODE &&
ctx->enc_state == MXC_JPEG_ENC_CONF) {
q_data = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
ctx->enc_state = MXC_JPEG_ENCODING;
dev_dbg(dev, "Encoder config finished. Start encoding...\n");
mxc_jpeg_enc_set_quality(dev, reg, ctx->jpeg_quality);
mxc_jpeg_enc_mode_go(dev, reg, mxc_jpeg_is_extended_sequential(q_data->fmt));
goto job_unlock;
}
if (jpeg->mode == MXC_JPEG_DECODE && jpeg_src_buf->dht_needed) {
jpeg_src_buf->dht_needed = false;
dev_dbg(dev, "Decoder DHT cfg finished. Start decoding...\n");
goto job_unlock;
}
if (jpeg->mode == MXC_JPEG_ENCODE) {
payload = readl(reg + MXC_SLOT_OFFSET(slot, SLOT_BUF_PTR));
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
dev_dbg(dev, "Encoding finished, payload size: %ld\n",
payload);
} else {
q_data = mxc_jpeg_get_q_data(ctx, cap_type);
payload = mxc_jpeg_get_plane_size(q_data, 0);
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
vb2_set_plane_payload(&dst_buf->vb2_buf, 1, 0);
if (q_data->fmt->mem_planes == 2) {
payload = mxc_jpeg_get_plane_size(q_data, 1);
vb2_set_plane_payload(&dst_buf->vb2_buf, 1, payload);
}
dev_dbg(dev, "Decoding finished, payload size: %ld + %ld\n",
vb2_get_plane_payload(&dst_buf->vb2_buf, 0),
vb2_get_plane_payload(&dst_buf->vb2_buf, 1));
}
/* short preview of the results */
dev_dbg(dev, "src_buf preview: ");
print_mxc_buf(jpeg, &src_buf->vb2_buf, 32);
dev_dbg(dev, "dst_buf preview: ");
print_mxc_buf(jpeg, &dst_buf->vb2_buf, 32);
buf_state = VB2_BUF_STATE_DONE;
buffers_done:
mxc_jpeg_job_finish(ctx, buf_state, false);
spin_unlock(&jpeg->hw_lock);
cancel_delayed_work(&ctx->task_timer);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
return IRQ_HANDLED;
job_unlock:
spin_unlock(&jpeg->hw_lock);
return IRQ_HANDLED;
}
static int mxc_jpeg_fixup_sof(struct mxc_jpeg_sof *sof,
u32 fourcc,
u16 w, u16 h)
{
int sof_length;
const struct mxc_jpeg_fmt *fmt = mxc_jpeg_find_format(fourcc);
if (fmt)
sof->precision = fmt->precision;
else
sof->precision = 8; /* TODO allow 8/12 bit precision*/
sof->height = h;
_bswap16(&sof->height);
sof->width = w;
_bswap16(&sof->width);
switch (fourcc) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV12M:
case V4L2_PIX_FMT_P012:
case V4L2_PIX_FMT_P012M:
sof->components_no = 3;
sof->comp[0].v = 0x2;
sof->comp[0].h = 0x2;
break;
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_Y212:
sof->components_no = 3;
sof->comp[0].v = 0x1;
sof->comp[0].h = 0x2;
break;
case V4L2_PIX_FMT_YUV24:
case V4L2_PIX_FMT_YUV48_12:
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_BGR48_12:
default:
sof->components_no = 3;
break;
case V4L2_PIX_FMT_ABGR32:
case V4L2_PIX_FMT_ABGR64_12:
sof->components_no = 4;
break;
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y012:
sof->components_no = 1;
break;
}
sof_length = 8 + 3 * sof->components_no;
sof->length = sof_length;
_bswap16(&sof->length);
return sof_length; /* not swaped */
}
static int mxc_jpeg_fixup_sos(struct mxc_jpeg_sos *sos,
u32 fourcc)
{
int sos_length;
u8 *sof_u8 = (u8 *)sos;
switch (fourcc) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV12M:
case V4L2_PIX_FMT_P012:
case V4L2_PIX_FMT_P012M:
sos->components_no = 3;
break;
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_Y212:
sos->components_no = 3;
break;
case V4L2_PIX_FMT_YUV24:
case V4L2_PIX_FMT_YUV48_12:
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_BGR48_12:
default:
sos->components_no = 3;
break;
case V4L2_PIX_FMT_ABGR32:
case V4L2_PIX_FMT_ABGR64_12:
sos->components_no = 4;
break;
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y012:
sos->components_no = 1;
break;
}
sos_length = 6 + 2 * sos->components_no;
sos->length = sos_length;
_bswap16(&sos->length);
/* SOS ignorable bytes, not so ignorable after all */
sof_u8[sos_length - 1] = 0x0;
sof_u8[sos_length - 2] = 0x3f;
sof_u8[sos_length - 3] = 0x0;
return sos_length; /* not swaped */
}
static unsigned int mxc_jpeg_setup_cfg_stream(void *cfg_stream_vaddr,
u32 fourcc,
u16 w, u16 h)
{
/*
* There is a hardware issue that first 128 bytes of configuration data
* can't be loaded correctly.
* To avoid this issue, we need to write the configuration from
* an offset which should be no less than 0x80 (128 bytes).
*/
unsigned int offset = 0x80;
u8 *cfg = (u8 *)cfg_stream_vaddr;
struct mxc_jpeg_sof *sof;
struct mxc_jpeg_sos *sos;
const struct mxc_jpeg_fmt *fmt = mxc_jpeg_find_format(fourcc);
if (!fmt)
return 0;
memcpy(cfg + offset, jpeg_soi, ARRAY_SIZE(jpeg_soi));
offset += ARRAY_SIZE(jpeg_soi);
if (fmt->is_rgb) {
memcpy(cfg + offset, jpeg_app14, sizeof(jpeg_app14));
offset += sizeof(jpeg_app14);
} else {
memcpy(cfg + offset, jpeg_app0, sizeof(jpeg_app0));
offset += sizeof(jpeg_app0);
}
if (mxc_jpeg_is_extended_sequential(fmt)) {
memcpy(cfg + offset, jpeg_dqt_extseq, sizeof(jpeg_dqt_extseq));
offset += sizeof(jpeg_dqt_extseq);
memcpy(cfg + offset, jpeg_sof_extseq, sizeof(jpeg_sof_extseq));
} else {
memcpy(cfg + offset, jpeg_dqt, sizeof(jpeg_dqt));
offset += sizeof(jpeg_dqt);
memcpy(cfg + offset, jpeg_sof_maximal, sizeof(jpeg_sof_maximal));
}
offset += 2; /* skip marker ID */
sof = (struct mxc_jpeg_sof *)(cfg + offset);
offset += mxc_jpeg_fixup_sof(sof, fourcc, w, h);
if (mxc_jpeg_is_extended_sequential(fmt)) {
memcpy(cfg + offset, jpeg_dht_extseq, sizeof(jpeg_dht_extseq));
offset += sizeof(jpeg_dht_extseq);
} else {
memcpy(cfg + offset, jpeg_dht, sizeof(jpeg_dht));
offset += sizeof(jpeg_dht);
}
memcpy(cfg + offset, jpeg_dri, sizeof(jpeg_dri));
offset += sizeof(jpeg_dri);
memcpy(cfg + offset, jpeg_sos_maximal, sizeof(jpeg_sos_maximal));
offset += 2; /* skip marker ID */
sos = (struct mxc_jpeg_sos *)(cfg + offset);
offset += mxc_jpeg_fixup_sos(sos, fourcc);
memcpy(cfg + offset, jpeg_image_red, sizeof(jpeg_image_red));
offset += sizeof(jpeg_image_red);
memcpy(cfg + offset, jpeg_eoi, sizeof(jpeg_eoi));
offset += sizeof(jpeg_eoi);
return offset;
}
static void mxc_jpeg_config_dec_desc(struct vb2_buffer *out_buf,
struct mxc_jpeg_ctx *ctx,
struct vb2_buffer *src_buf,
struct vb2_buffer *dst_buf)
{
enum v4l2_buf_type cap_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
struct mxc_jpeg_q_data *q_data_cap;
enum mxc_jpeg_image_format img_fmt;
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
unsigned int slot = ctx->slot;
struct mxc_jpeg_desc *desc = jpeg->slot_data.desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data.desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle;
dma_addr_t cfg_stream_handle = jpeg->slot_data.cfg_stream_handle;
unsigned int *cfg_size = &jpeg->slot_data.cfg_stream_size;
void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr;
struct mxc_jpeg_src_buf *jpeg_src_buf;
jpeg_src_buf = vb2_to_mxc_buf(src_buf);
/* setup the decoding descriptor */
desc->next_descpt_ptr = 0; /* end of chain */
q_data_cap = mxc_jpeg_get_q_data(ctx, cap_type);
desc->imgsize = q_data_cap->w_adjusted << 16 | q_data_cap->h_adjusted;
img_fmt = mxc_jpeg_fourcc_to_imgfmt(q_data_cap->fmt->fourcc);
desc->stm_ctrl &= ~STM_CTRL_IMAGE_FORMAT(0xF); /* clear image format */
desc->stm_ctrl |= STM_CTRL_IMAGE_FORMAT(img_fmt);
desc->stm_ctrl |= STM_CTRL_BITBUF_PTR_CLR(1);
if (mxc_jpeg_is_extended_sequential(jpeg_src_buf->fmt))
desc->stm_ctrl |= STM_CTRL_PIXEL_PRECISION;
else
desc->stm_ctrl &= ~STM_CTRL_PIXEL_PRECISION;
desc->line_pitch = q_data_cap->bytesperline[0];
mxc_jpeg_addrs(desc, dst_buf, src_buf, 0);
mxc_jpeg_set_bufsize(desc, ALIGN(vb2_plane_size(src_buf, 0), 1024));
print_descriptor_info(jpeg->dev, desc);
if (!jpeg_src_buf->dht_needed) {
/* validate the decoding descriptor */
mxc_jpeg_set_desc(desc_handle, reg, slot);
return;
}
/*
* if a default huffman table is needed, use the config descriptor to
* inject a DHT, by chaining it before the decoding descriptor
*/
*cfg_size = mxc_jpeg_setup_cfg_stream(cfg_stream_vaddr,
V4L2_PIX_FMT_YUYV,
MXC_JPEG_MIN_WIDTH,
MXC_JPEG_MIN_HEIGHT);
cfg_desc->next_descpt_ptr = desc_handle | MXC_NXT_DESCPT_EN;
cfg_desc->buf_base0 = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
cfg_desc->buf_base1 = 0;
cfg_desc->imgsize = MXC_JPEG_MIN_WIDTH << 16;
cfg_desc->imgsize |= MXC_JPEG_MIN_HEIGHT;
cfg_desc->line_pitch = MXC_JPEG_MIN_WIDTH * 2;
cfg_desc->stm_ctrl = STM_CTRL_IMAGE_FORMAT(MXC_JPEG_YUV422);
cfg_desc->stm_ctrl |= STM_CTRL_BITBUF_PTR_CLR(1);
cfg_desc->stm_bufbase = cfg_stream_handle;
cfg_desc->stm_bufsize = ALIGN(*cfg_size, 1024);
print_descriptor_info(jpeg->dev, cfg_desc);
/* validate the configuration descriptor */
mxc_jpeg_set_desc(cfg_desc_handle, reg, slot);
}
static void mxc_jpeg_config_enc_desc(struct vb2_buffer *out_buf,
struct mxc_jpeg_ctx *ctx,
struct vb2_buffer *src_buf,
struct vb2_buffer *dst_buf)
{
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
unsigned int slot = ctx->slot;
struct mxc_jpeg_desc *desc = jpeg->slot_data.desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data.desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle;
void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr;
struct mxc_jpeg_q_data *q_data;
enum mxc_jpeg_image_format img_fmt;
int w, h;
q_data = mxc_jpeg_get_q_data(ctx, src_buf->vb2_queue->type);
jpeg->slot_data.cfg_stream_size =
mxc_jpeg_setup_cfg_stream(cfg_stream_vaddr,
q_data->fmt->fourcc,
q_data->crop.width,
q_data->crop.height);
/* chain the config descriptor with the encoding descriptor */
cfg_desc->next_descpt_ptr = desc_handle | MXC_NXT_DESCPT_EN;
cfg_desc->buf_base0 = jpeg->slot_data.cfg_stream_handle;
cfg_desc->buf_base1 = 0;
cfg_desc->line_pitch = 0;
cfg_desc->stm_bufbase = 0; /* no output expected */
cfg_desc->stm_bufsize = 0x0;
cfg_desc->imgsize = 0;
cfg_desc->stm_ctrl = STM_CTRL_CONFIG_MOD(1);
cfg_desc->stm_ctrl |= STM_CTRL_BITBUF_PTR_CLR(1);
desc->next_descpt_ptr = 0; /* end of chain */
/* use adjusted resolution for CAST IP job */
w = q_data->crop.width;
h = q_data->crop.height;
v4l_bound_align_image(&w, w, MXC_JPEG_MAX_WIDTH, q_data->fmt->h_align,
&h, h, MXC_JPEG_MAX_HEIGHT, q_data->fmt->v_align, 0);
mxc_jpeg_set_res(desc, w, h);
mxc_jpeg_set_line_pitch(desc, q_data->bytesperline[0]);
mxc_jpeg_set_bufsize(desc, ALIGN(vb2_plane_size(dst_buf, 0), 1024));
img_fmt = mxc_jpeg_fourcc_to_imgfmt(q_data->fmt->fourcc);
if (img_fmt == MXC_JPEG_INVALID)
dev_err(jpeg->dev, "No valid image format detected\n");
desc->stm_ctrl = STM_CTRL_CONFIG_MOD(0) |
STM_CTRL_IMAGE_FORMAT(img_fmt);
desc->stm_ctrl |= STM_CTRL_BITBUF_PTR_CLR(1);
if (mxc_jpeg_is_extended_sequential(q_data->fmt))
desc->stm_ctrl |= STM_CTRL_PIXEL_PRECISION;
else
desc->stm_ctrl &= ~STM_CTRL_PIXEL_PRECISION;
mxc_jpeg_addrs(desc, src_buf, dst_buf, 0);
dev_dbg(jpeg->dev, "cfg_desc:\n");
print_descriptor_info(jpeg->dev, cfg_desc);
dev_dbg(jpeg->dev, "enc desc:\n");
print_descriptor_info(jpeg->dev, desc);
print_wrapper_info(jpeg->dev, reg);
print_cast_status(jpeg->dev, reg, MXC_JPEG_ENCODE);
/* validate the configuration descriptor */
mxc_jpeg_set_desc(cfg_desc_handle, reg, slot);
}
static const struct mxc_jpeg_fmt *mxc_jpeg_get_sibling_format(const struct mxc_jpeg_fmt *fmt)
{
int i;
for (i = 0; i < MXC_JPEG_NUM_FORMATS; i++) {
if (mxc_formats[i].subsampling == fmt->subsampling &&
mxc_formats[i].nc == fmt->nc &&
mxc_formats[i].precision == fmt->precision &&
mxc_formats[i].is_rgb == fmt->is_rgb &&
mxc_formats[i].fourcc != fmt->fourcc)
return &mxc_formats[i];
}
return NULL;
}
static bool mxc_jpeg_compare_format(const struct mxc_jpeg_fmt *fmt1,
const struct mxc_jpeg_fmt *fmt2)
{
if (fmt1 == fmt2)
return true;
if (mxc_jpeg_get_sibling_format(fmt1) == fmt2)
return true;
return false;
}
static bool mxc_jpeg_source_change(struct mxc_jpeg_ctx *ctx,
struct mxc_jpeg_src_buf *jpeg_src_buf)
{
struct device *dev = ctx->mxc_jpeg->dev;
struct mxc_jpeg_q_data *q_data_cap;
if (!jpeg_src_buf->fmt)
return false;
q_data_cap = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
if (mxc_jpeg_compare_format(q_data_cap->fmt, jpeg_src_buf->fmt))
jpeg_src_buf->fmt = q_data_cap->fmt;
if (q_data_cap->fmt != jpeg_src_buf->fmt ||
q_data_cap->w != jpeg_src_buf->w ||
q_data_cap->h != jpeg_src_buf->h) {
dev_dbg(dev, "Detected jpeg res=(%dx%d)->(%dx%d), pixfmt=%c%c%c%c\n",
q_data_cap->w, q_data_cap->h,
jpeg_src_buf->w, jpeg_src_buf->h,
(jpeg_src_buf->fmt->fourcc & 0xff),
(jpeg_src_buf->fmt->fourcc >> 8) & 0xff,
(jpeg_src_buf->fmt->fourcc >> 16) & 0xff,
(jpeg_src_buf->fmt->fourcc >> 24) & 0xff);
/*
* set-up the capture queue with the pixelformat and resolution
* detected from the jpeg output stream
*/
q_data_cap->w = jpeg_src_buf->w;
q_data_cap->h = jpeg_src_buf->h;
q_data_cap->fmt = jpeg_src_buf->fmt;
q_data_cap->w_adjusted = q_data_cap->w;
q_data_cap->h_adjusted = q_data_cap->h;
q_data_cap->crop.left = 0;
q_data_cap->crop.top = 0;
q_data_cap->crop.width = jpeg_src_buf->w;
q_data_cap->crop.height = jpeg_src_buf->h;
/*
* align up the resolution for CAST IP,
* but leave the buffer resolution unchanged
*/
v4l_bound_align_image(&q_data_cap->w_adjusted,
q_data_cap->w_adjusted, /* adjust up */
MXC_JPEG_MAX_WIDTH,
q_data_cap->fmt->h_align,
&q_data_cap->h_adjusted,
q_data_cap->h_adjusted, /* adjust up */
MXC_JPEG_MAX_HEIGHT,
q_data_cap->fmt->v_align,
0);
/* setup bytesperline/sizeimage for capture queue */
mxc_jpeg_bytesperline(q_data_cap, jpeg_src_buf->fmt->precision);
mxc_jpeg_sizeimage(q_data_cap);
notify_src_chg(ctx);
ctx->source_change = 1;
}
return ctx->source_change ? true : false;
}
static int mxc_jpeg_job_ready(void *priv)
{
struct mxc_jpeg_ctx *ctx = priv;
return ctx->source_change ? 0 : 1;
}
static void mxc_jpeg_device_run_timeout(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct mxc_jpeg_ctx *ctx = container_of(dwork, struct mxc_jpeg_ctx, task_timer);
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
unsigned long flags;
spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags);
if (ctx->mxc_jpeg->slot_data.used) {
dev_warn(jpeg->dev, "%s timeout, cancel it\n",
ctx->mxc_jpeg->mode == MXC_JPEG_DECODE ? "decode" : "encode");
mxc_jpeg_job_finish(ctx, VB2_BUF_STATE_ERROR, true);
v4l2_m2m_job_finish(ctx->mxc_jpeg->m2m_dev, ctx->fh.m2m_ctx);
}
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
}
static void mxc_jpeg_device_run(void *priv)
{
struct mxc_jpeg_ctx *ctx = priv;
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
struct device *dev = jpeg->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
unsigned long flags;
struct mxc_jpeg_q_data *q_data_cap, *q_data_out;
struct mxc_jpeg_src_buf *jpeg_src_buf;
spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags);
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
if (!src_buf || !dst_buf) {
dev_err(dev, "Null src or dst buf\n");
goto end;
}
q_data_cap = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
if (!q_data_cap)
goto end;
q_data_out = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
if (!q_data_out)
goto end;
src_buf->sequence = q_data_out->sequence++;
dst_buf->sequence = q_data_cap->sequence++;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
jpeg_src_buf = vb2_to_mxc_buf(&src_buf->vb2_buf);
if (q_data_cap->fmt->mem_planes != dst_buf->vb2_buf.num_planes) {
dev_err(dev, "Capture format %s has %d planes, but capture buffer has %d planes\n",
q_data_cap->fmt->name, q_data_cap->fmt->mem_planes,
dst_buf->vb2_buf.num_planes);
jpeg_src_buf->jpeg_parse_error = true;
}
if (jpeg_src_buf->jpeg_parse_error) {
mxc_jpeg_check_and_set_last_buffer(ctx, src_buf, dst_buf);
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
return;
}
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE) {
if (ctx->source_change || mxc_jpeg_source_change(ctx, jpeg_src_buf)) {
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
return;
}
}
mxc_jpeg_enable(reg);
mxc_jpeg_set_l_endian(reg, 1);
ctx->slot = mxc_get_free_slot(&jpeg->slot_data);
if (ctx->slot < 0) {
dev_err(dev, "No more free slots\n");
goto end;
}
if (!mxc_jpeg_alloc_slot_data(jpeg)) {
dev_err(dev, "Cannot allocate slot data\n");
goto end;
}
mxc_jpeg_enable_slot(reg, ctx->slot);
mxc_jpeg_enable_irq(reg, ctx->slot);
if (jpeg->mode == MXC_JPEG_ENCODE) {
dev_dbg(dev, "Encoding on slot %d\n", ctx->slot);
ctx->enc_state = MXC_JPEG_ENC_CONF;
mxc_jpeg_config_enc_desc(&dst_buf->vb2_buf, ctx,
&src_buf->vb2_buf, &dst_buf->vb2_buf);
/* start config phase */
mxc_jpeg_enc_mode_conf(dev, reg,
mxc_jpeg_is_extended_sequential(q_data_out->fmt));
} else {
dev_dbg(dev, "Decoding on slot %d\n", ctx->slot);
print_mxc_buf(jpeg, &src_buf->vb2_buf, 0);
mxc_jpeg_config_dec_desc(&dst_buf->vb2_buf, ctx,
&src_buf->vb2_buf, &dst_buf->vb2_buf);
mxc_jpeg_dec_mode_go(dev, reg);
}
schedule_delayed_work(&ctx->task_timer, msecs_to_jiffies(hw_timeout));
end:
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
}
static int mxc_jpeg_decoder_cmd(struct file *file, void *priv,
struct v4l2_decoder_cmd *cmd)
{
struct v4l2_fh *fh = file->private_data;
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
unsigned long flags;
int ret;
ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, cmd);
if (ret < 0)
return ret;
if (!vb2_is_streaming(v4l2_m2m_get_src_vq(fh->m2m_ctx)))
return 0;
spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags);
ret = v4l2_m2m_ioctl_decoder_cmd(file, priv, cmd);
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
if (ret < 0)
return ret;
if (cmd->cmd == V4L2_DEC_CMD_STOP &&
v4l2_m2m_has_stopped(fh->m2m_ctx)) {
notify_eos(ctx);
ctx->header_parsed = false;
}
if (cmd->cmd == V4L2_DEC_CMD_START &&
v4l2_m2m_has_stopped(fh->m2m_ctx))
vb2_clear_last_buffer_dequeued(&fh->m2m_ctx->cap_q_ctx.q);
return 0;
}
static int mxc_jpeg_encoder_cmd(struct file *file, void *priv,
struct v4l2_encoder_cmd *cmd)
{
struct v4l2_fh *fh = file->private_data;
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
unsigned long flags;
int ret;
ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
if (ret < 0)
return ret;
if (!vb2_is_streaming(v4l2_m2m_get_src_vq(fh->m2m_ctx)) ||
!vb2_is_streaming(v4l2_m2m_get_dst_vq(fh->m2m_ctx)))
return 0;
spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags);
ret = v4l2_m2m_ioctl_encoder_cmd(file, fh, cmd);
spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags);
if (ret < 0)
return 0;
if (cmd->cmd == V4L2_ENC_CMD_STOP &&
v4l2_m2m_has_stopped(fh->m2m_ctx))
notify_eos(ctx);
if (cmd->cmd == V4L2_ENC_CMD_START &&
v4l2_m2m_has_stopped(fh->m2m_ctx))
vb2_clear_last_buffer_dequeued(&fh->m2m_ctx->cap_q_ctx.q);
return 0;
}
static int mxc_jpeg_queue_setup(struct vb2_queue *q,
unsigned int *nbuffers,
unsigned int *nplanes,
unsigned int sizes[],
struct device *alloc_ctxs[])
{
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(q);
struct mxc_jpeg_q_data *q_data = NULL;
int i;
q_data = mxc_jpeg_get_q_data(ctx, q->type);
if (!q_data)
return -EINVAL;
/* Handle CREATE_BUFS situation - *nplanes != 0 */
if (*nplanes) {
if (*nplanes != q_data->fmt->mem_planes)
return -EINVAL;
for (i = 0; i < *nplanes; i++) {
if (sizes[i] < mxc_jpeg_get_plane_size(q_data, i))
return -EINVAL;
}
return 0;
}
/* Handle REQBUFS situation */
*nplanes = q_data->fmt->mem_planes;
for (i = 0; i < *nplanes; i++)
sizes[i] = mxc_jpeg_get_plane_size(q_data, i);
return 0;
}
static int mxc_jpeg_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(q);
struct mxc_jpeg_q_data *q_data = mxc_jpeg_get_q_data(ctx, q->type);
int ret;
v4l2_m2m_update_start_streaming_state(ctx->fh.m2m_ctx, q);
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE && V4L2_TYPE_IS_CAPTURE(q->type))
ctx->source_change = 0;
dev_dbg(ctx->mxc_jpeg->dev, "Start streaming ctx=%p", ctx);
q_data->sequence = 0;
ret = pm_runtime_resume_and_get(ctx->mxc_jpeg->dev);
if (ret < 0) {
dev_err(ctx->mxc_jpeg->dev, "Failed to power up jpeg\n");
return ret;
}
return 0;
}
static void mxc_jpeg_stop_streaming(struct vb2_queue *q)
{
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(q);
struct vb2_v4l2_buffer *vbuf;
dev_dbg(ctx->mxc_jpeg->dev, "Stop streaming ctx=%p", ctx);
/* Release all active buffers */
for (;;) {
if (V4L2_TYPE_IS_OUTPUT(q->type))
vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
else
vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (!vbuf)
break;
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
}
if (V4L2_TYPE_IS_OUTPUT(q->type) || !ctx->source_change)
v4l2_m2m_update_stop_streaming_state(ctx->fh.m2m_ctx, q);
if (V4L2_TYPE_IS_OUTPUT(q->type) &&
v4l2_m2m_has_stopped(ctx->fh.m2m_ctx)) {
notify_eos(ctx);
ctx->header_parsed = false;
}
pm_runtime_put_sync(&ctx->mxc_jpeg->pdev->dev);
}
static int mxc_jpeg_valid_comp_id(struct device *dev,
struct mxc_jpeg_sof *sof,
struct mxc_jpeg_sos *sos)
{
int valid = 1;
int i;
/*
* there's a limitation in the IP that the component IDs must be
* between 0..4, if they are not, let's patch them
*/
for (i = 0; i < sof->components_no; i++)
if (sof->comp[i].id > MXC_JPEG_MAX_COMPONENTS) {
valid = 0;
dev_err(dev, "Component %d has invalid ID: %d",
i, sof->comp[i].id);
}
if (!valid)
/* patch all comp IDs if at least one is invalid */
for (i = 0; i < sof->components_no; i++) {
dev_warn(dev, "Component %d ID patched to: %d",
i, i + 1);
sof->comp[i].id = i + 1;
sos->comp[i].id = i + 1;
}
return valid;
}
static bool mxc_jpeg_match_image_format(const struct mxc_jpeg_fmt *fmt,
const struct v4l2_jpeg_header *header)
{
if (fmt->subsampling != header->frame.subsampling ||
fmt->nc != header->frame.num_components ||
fmt->precision != header->frame.precision)
return false;
/*
* If the transform flag from APP14 marker is 0, images that are
* encoded with 3 components have RGB colorspace, see Recommendation
* ITU-T T.872 chapter 6.5.3 APP14 marker segment for colour encoding
*/
if (header->frame.subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_444) {
u8 is_rgb = header->app14_tf == V4L2_JPEG_APP14_TF_CMYK_RGB ? 1 : 0;
if (is_rgb != fmt->is_rgb)
return false;
}
return true;
}
static u32 mxc_jpeg_get_image_format(struct device *dev,
const struct v4l2_jpeg_header *header)
{
int i;
u32 fourcc = 0;
for (i = 0; i < MXC_JPEG_NUM_FORMATS; i++) {
if (mxc_jpeg_match_image_format(&mxc_formats[i], header)) {
fourcc = mxc_formats[i].fourcc;
break;
}
}
if (fourcc == 0) {
dev_err(dev,
"Could not identify image format nc=%d, subsampling=%d, precision=%d\n",
header->frame.num_components,
header->frame.subsampling,
header->frame.precision);
return fourcc;
}
return fourcc;
}
static void mxc_jpeg_bytesperline(struct mxc_jpeg_q_data *q, u32 precision)
{
/* Bytes distance between the leftmost pixels in two adjacent lines */
if (q->fmt->fourcc == V4L2_PIX_FMT_JPEG) {
/* bytesperline unused for compressed formats */
q->bytesperline[0] = 0;
q->bytesperline[1] = 0;
} else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_420) {
/* When the image format is planar the bytesperline value
* applies to the first plane and is divided by the same factor
* as the width field for the other planes
*/
q->bytesperline[0] = q->w_adjusted * DIV_ROUND_UP(precision, 8);
q->bytesperline[1] = q->bytesperline[0];
} else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_422) {
q->bytesperline[0] = q->w_adjusted * DIV_ROUND_UP(precision, 8) * 2;
q->bytesperline[1] = 0;
} else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_444) {
q->bytesperline[0] = q->w_adjusted * DIV_ROUND_UP(precision, 8) * q->fmt->nc;
q->bytesperline[1] = 0;
} else {
/* grayscale */
q->bytesperline[0] = q->w_adjusted * DIV_ROUND_UP(precision, 8);
q->bytesperline[1] = 0;
}
}
static void mxc_jpeg_sizeimage(struct mxc_jpeg_q_data *q)
{
if (q->fmt->fourcc == V4L2_PIX_FMT_JPEG) {
/* if no sizeimage from user, assume worst jpeg compression */
if (!q->sizeimage[0])
q->sizeimage[0] = 6 * q->w * q->h;
q->sizeimage[1] = 0;
if (q->sizeimage[0] > MXC_JPEG_MAX_SIZEIMAGE)
q->sizeimage[0] = MXC_JPEG_MAX_SIZEIMAGE;
/* jpeg stream size must be multiple of 1K */
q->sizeimage[0] = ALIGN(q->sizeimage[0], 1024);
} else {
q->sizeimage[0] = q->bytesperline[0] * q->h_adjusted;
q->sizeimage[1] = 0;
if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_420)
q->sizeimage[1] = q->sizeimage[0] / 2;
}
}
static int mxc_jpeg_parse(struct mxc_jpeg_ctx *ctx, struct vb2_buffer *vb)
{
struct device *dev = ctx->mxc_jpeg->dev;
struct mxc_jpeg_q_data *q_data_out;
struct mxc_jpeg_q_data *q_data_cap;
u32 fourcc;
struct v4l2_jpeg_header header;
struct mxc_jpeg_sof *psof = NULL;
struct mxc_jpeg_sos *psos = NULL;
struct mxc_jpeg_src_buf *jpeg_src_buf = vb2_to_mxc_buf(vb);
u8 *src_addr = (u8 *)vb2_plane_vaddr(vb, 0);
u32 size = vb2_get_plane_payload(vb, 0);
int ret;
memset(&header, 0, sizeof(header));
ret = v4l2_jpeg_parse_header((void *)src_addr, size, &header);
if (ret < 0) {
dev_err(dev, "Error parsing JPEG stream markers\n");
return ret;
}
/* if DHT marker present, no need to inject default one */
jpeg_src_buf->dht_needed = (header.num_dht == 0);
q_data_out = mxc_jpeg_get_q_data(ctx,
V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
if (q_data_out->w == 0 && q_data_out->h == 0) {
dev_warn(dev, "Invalid user resolution 0x0");
dev_warn(dev, "Keeping resolution from JPEG: %dx%d",
header.frame.width, header.frame.height);
} else if (header.frame.width != q_data_out->w ||
header.frame.height != q_data_out->h) {
dev_err(dev,
"Resolution mismatch: %dx%d (JPEG) versus %dx%d(user)",
header.frame.width, header.frame.height,
q_data_out->w, q_data_out->h);
}
q_data_out->w = header.frame.width;
q_data_out->h = header.frame.height;
if (header.frame.width > MXC_JPEG_MAX_WIDTH ||
header.frame.height > MXC_JPEG_MAX_HEIGHT) {
dev_err(dev, "JPEG width or height should be <= 8192: %dx%d\n",
header.frame.width, header.frame.height);
return -EINVAL;
}
if (header.frame.width < MXC_JPEG_MIN_WIDTH ||
header.frame.height < MXC_JPEG_MIN_HEIGHT) {
dev_err(dev, "JPEG width or height should be > 64: %dx%d\n",
header.frame.width, header.frame.height);
return -EINVAL;
}
if (header.frame.num_components > V4L2_JPEG_MAX_COMPONENTS) {
dev_err(dev, "JPEG number of components should be <=%d",
V4L2_JPEG_MAX_COMPONENTS);
return -EINVAL;
}
/* check and, if necessary, patch component IDs*/
psof = (struct mxc_jpeg_sof *)header.sof.start;
psos = (struct mxc_jpeg_sos *)header.sos.start;
if (!mxc_jpeg_valid_comp_id(dev, psof, psos))
dev_warn(dev, "JPEG component ids should be 0-3 or 1-4");
q_data_cap = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
if (q_data_cap->fmt && mxc_jpeg_match_image_format(q_data_cap->fmt, &header))
fourcc = q_data_cap->fmt->fourcc;
else
fourcc = mxc_jpeg_get_image_format(dev, &header);
if (fourcc == 0)
return -EINVAL;
jpeg_src_buf->fmt = mxc_jpeg_find_format(fourcc);
jpeg_src_buf->w = header.frame.width;
jpeg_src_buf->h = header.frame.height;
ctx->header_parsed = true;
if (!v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx))
mxc_jpeg_source_change(ctx, jpeg_src_buf);
return 0;
}
static void mxc_jpeg_buf_queue(struct vb2_buffer *vb)
{
int ret;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct mxc_jpeg_src_buf *jpeg_src_buf;
if (V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type) &&
vb2_is_streaming(vb->vb2_queue) &&
v4l2_m2m_dst_buf_is_last(ctx->fh.m2m_ctx)) {
struct mxc_jpeg_q_data *q_data;
q_data = mxc_jpeg_get_q_data(ctx, vb->vb2_queue->type);
vbuf->field = V4L2_FIELD_NONE;
vbuf->sequence = q_data->sequence++;
v4l2_m2m_last_buffer_done(ctx->fh.m2m_ctx, vbuf);
notify_eos(ctx);
ctx->header_parsed = false;
return;
}
if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
goto end;
/* for V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE */
if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE)
goto end;
jpeg_src_buf = vb2_to_mxc_buf(vb);
jpeg_src_buf->jpeg_parse_error = false;
ret = mxc_jpeg_parse(ctx, vb);
if (ret)
jpeg_src_buf->jpeg_parse_error = true;
end:
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static int mxc_jpeg_buf_out_validate(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
vbuf->field = V4L2_FIELD_NONE;
return 0;
}
static int mxc_jpeg_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct mxc_jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct mxc_jpeg_q_data *q_data = NULL;
struct device *dev = ctx->mxc_jpeg->dev;
unsigned long sizeimage;
int i;
vbuf->field = V4L2_FIELD_NONE;
q_data = mxc_jpeg_get_q_data(ctx, vb->vb2_queue->type);
if (!q_data)
return -EINVAL;
for (i = 0; i < q_data->fmt->mem_planes; i++) {
sizeimage = mxc_jpeg_get_plane_size(q_data, i);
if (vb2_plane_size(vb, i) < sizeimage) {
dev_err(dev, "plane %d too small (%lu < %lu)",
i, vb2_plane_size(vb, i), sizeimage);
return -EINVAL;
}
}
if (V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type)) {
vb2_set_plane_payload(vb, 0, 0);
vb2_set_plane_payload(vb, 1, 0);
}
return 0;
}
static const struct vb2_ops mxc_jpeg_qops = {
.queue_setup = mxc_jpeg_queue_setup,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.buf_out_validate = mxc_jpeg_buf_out_validate,
.buf_prepare = mxc_jpeg_buf_prepare,
.start_streaming = mxc_jpeg_start_streaming,
.stop_streaming = mxc_jpeg_stop_streaming,
.buf_queue = mxc_jpeg_buf_queue,
};
static int mxc_jpeg_queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq)
{
struct mxc_jpeg_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->buf_struct_size = sizeof(struct mxc_jpeg_src_buf);
src_vq->ops = &mxc_jpeg_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->mxc_jpeg->lock;
src_vq->dev = ctx->mxc_jpeg->dev;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->ops = &mxc_jpeg_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->mxc_jpeg->lock;
dst_vq->dev = ctx->mxc_jpeg->dev;
ret = vb2_queue_init(dst_vq);
return ret;
}
static void mxc_jpeg_set_default_params(struct mxc_jpeg_ctx *ctx)
{
struct mxc_jpeg_q_data *out_q = &ctx->out_q;
struct mxc_jpeg_q_data *cap_q = &ctx->cap_q;
struct mxc_jpeg_q_data *q[2] = {out_q, cap_q};
int i;
if (ctx->mxc_jpeg->mode == MXC_JPEG_ENCODE) {
out_q->fmt = mxc_jpeg_find_format(MXC_JPEG_DEFAULT_PFMT);
cap_q->fmt = mxc_jpeg_find_format(V4L2_PIX_FMT_JPEG);
} else {
out_q->fmt = mxc_jpeg_find_format(V4L2_PIX_FMT_JPEG);
cap_q->fmt = mxc_jpeg_find_format(MXC_JPEG_DEFAULT_PFMT);
}
for (i = 0; i < 2; i++) {
q[i]->w = MXC_JPEG_DEFAULT_WIDTH;
q[i]->h = MXC_JPEG_DEFAULT_HEIGHT;
q[i]->w_adjusted = MXC_JPEG_DEFAULT_WIDTH;
q[i]->h_adjusted = MXC_JPEG_DEFAULT_HEIGHT;
q[i]->crop.left = 0;
q[i]->crop.top = 0;
q[i]->crop.width = MXC_JPEG_DEFAULT_WIDTH;
q[i]->crop.height = MXC_JPEG_DEFAULT_HEIGHT;
mxc_jpeg_bytesperline(q[i], q[i]->fmt->precision);
mxc_jpeg_sizeimage(q[i]);
}
}
static int mxc_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct mxc_jpeg_ctx *ctx =
container_of(ctrl->handler, struct mxc_jpeg_ctx, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_JPEG_COMPRESSION_QUALITY:
ctx->jpeg_quality = ctrl->val;
break;
default:
dev_err(ctx->mxc_jpeg->dev, "Invalid control, id = %d, val = %d\n",
ctrl->id, ctrl->val);
return -EINVAL;
}
return 0;
}
static const struct v4l2_ctrl_ops mxc_jpeg_ctrl_ops = {
.s_ctrl = mxc_jpeg_s_ctrl,
};
static void mxc_jpeg_encode_ctrls(struct mxc_jpeg_ctx *ctx)
{
v4l2_ctrl_new_std(&ctx->ctrl_handler, &mxc_jpeg_ctrl_ops,
V4L2_CID_JPEG_COMPRESSION_QUALITY, 1, 100, 1, 75);
}
static int mxc_jpeg_ctrls_setup(struct mxc_jpeg_ctx *ctx)
{
int err;
v4l2_ctrl_handler_init(&ctx->ctrl_handler, 2);
if (ctx->mxc_jpeg->mode == MXC_JPEG_ENCODE)
mxc_jpeg_encode_ctrls(ctx);
if (ctx->ctrl_handler.error) {
err = ctx->ctrl_handler.error;
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
return err;
}
err = v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
if (err)
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
return err;
}
static int mxc_jpeg_open(struct file *file)
{
struct mxc_jpeg_dev *mxc_jpeg = video_drvdata(file);
struct video_device *mxc_vfd = video_devdata(file);
struct device *dev = mxc_jpeg->dev;
struct mxc_jpeg_ctx *ctx;
int ret = 0;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
if (mutex_lock_interruptible(&mxc_jpeg->lock)) {
ret = -ERESTARTSYS;
goto free;
}
v4l2_fh_init(&ctx->fh, mxc_vfd);
file->private_data = &ctx->fh;
v4l2_fh_add(&ctx->fh);
ctx->mxc_jpeg = mxc_jpeg;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(mxc_jpeg->m2m_dev, ctx,
mxc_jpeg_queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
ret = PTR_ERR(ctx->fh.m2m_ctx);
goto error;
}
ret = mxc_jpeg_ctrls_setup(ctx);
if (ret) {
dev_err(ctx->mxc_jpeg->dev, "failed to setup mxc jpeg controls\n");
goto err_ctrls_setup;
}
ctx->fh.ctrl_handler = &ctx->ctrl_handler;
mxc_jpeg_set_default_params(ctx);
ctx->slot = -1; /* slot not allocated yet */
INIT_DELAYED_WORK(&ctx->task_timer, mxc_jpeg_device_run_timeout);
if (mxc_jpeg->mode == MXC_JPEG_DECODE)
dev_dbg(dev, "Opened JPEG decoder instance %p\n", ctx);
else
dev_dbg(dev, "Opened JPEG encoder instance %p\n", ctx);
mutex_unlock(&mxc_jpeg->lock);
return 0;
err_ctrls_setup:
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
error:
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
mutex_unlock(&mxc_jpeg->lock);
free:
kfree(ctx);
return ret;
}
static int mxc_jpeg_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MXC_JPEG_NAME " codec", sizeof(cap->driver));
strscpy(cap->card, MXC_JPEG_NAME " codec", sizeof(cap->card));
cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
return 0;
}
static int mxc_jpeg_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
struct mxc_jpeg_q_data *q_data = mxc_jpeg_get_q_data(ctx, f->type);
if (ctx->mxc_jpeg->mode == MXC_JPEG_ENCODE) {
return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f,
MXC_JPEG_FMT_TYPE_ENC);
} else if (!ctx->header_parsed) {
return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f,
MXC_JPEG_FMT_TYPE_RAW);
} else {
/* For the decoder CAPTURE queue, only enumerate the raw formats
* supported for the format currently active on OUTPUT
* (more precisely what was propagated on capture queue
* after jpeg parse on the output buffer)
*/
int ret = -EINVAL;
const struct mxc_jpeg_fmt *sibling;
switch (f->index) {
case 0:
f->pixelformat = q_data->fmt->fourcc;
ret = 0;
break;
case 1:
sibling = mxc_jpeg_get_sibling_format(q_data->fmt);
if (sibling) {
f->pixelformat = sibling->fourcc;
ret = 0;
}
break;
default:
break;
}
return ret;
}
}
static int mxc_jpeg_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
u32 type = ctx->mxc_jpeg->mode == MXC_JPEG_DECODE ? MXC_JPEG_FMT_TYPE_ENC :
MXC_JPEG_FMT_TYPE_RAW;
int ret;
ret = enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, type);
if (ret)
return ret;
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE)
f->flags = V4L2_FMT_FLAG_DYN_RESOLUTION;
return 0;
}
static u32 mxc_jpeg_get_fmt_type(struct mxc_jpeg_ctx *ctx, u32 type)
{
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE)
return V4L2_TYPE_IS_OUTPUT(type) ? MXC_JPEG_FMT_TYPE_ENC : MXC_JPEG_FMT_TYPE_RAW;
else
return V4L2_TYPE_IS_CAPTURE(type) ? MXC_JPEG_FMT_TYPE_ENC : MXC_JPEG_FMT_TYPE_RAW;
}
static u32 mxc_jpeg_get_default_fourcc(struct mxc_jpeg_ctx *ctx, u32 type)
{
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE)
return V4L2_TYPE_IS_OUTPUT(type) ? V4L2_PIX_FMT_JPEG : MXC_JPEG_DEFAULT_PFMT;
else
return V4L2_TYPE_IS_CAPTURE(type) ? V4L2_PIX_FMT_JPEG : MXC_JPEG_DEFAULT_PFMT;
}
static u32 mxc_jpeg_try_fourcc(struct mxc_jpeg_ctx *ctx, u32 fourcc)
{
const struct mxc_jpeg_fmt *sibling;
struct mxc_jpeg_q_data *q_data_cap;
if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE)
return fourcc;
if (!ctx->header_parsed)
return fourcc;
q_data_cap = &ctx->cap_q;
if (q_data_cap->fmt->fourcc == fourcc)
return fourcc;
sibling = mxc_jpeg_get_sibling_format(q_data_cap->fmt);
if (sibling && sibling->fourcc == fourcc)
return sibling->fourcc;
return q_data_cap->fmt->fourcc;
}
static int mxc_jpeg_try_fmt(struct v4l2_format *f,
struct mxc_jpeg_ctx *ctx, struct mxc_jpeg_q_data *q_data)
{
const struct mxc_jpeg_fmt *fmt;
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct v4l2_plane_pix_format *pfmt;
u32 fourcc = f->fmt.pix_mp.pixelformat;
u32 w = (pix_mp->width < MXC_JPEG_MAX_WIDTH) ?
pix_mp->width : MXC_JPEG_MAX_WIDTH;
u32 h = (pix_mp->height < MXC_JPEG_MAX_HEIGHT) ?
pix_mp->height : MXC_JPEG_MAX_HEIGHT;
int i;
fmt = mxc_jpeg_find_format(fourcc);
if (!fmt || fmt->flags != mxc_jpeg_get_fmt_type(ctx, f->type)) {
dev_warn(ctx->mxc_jpeg->dev, "Format not supported: %c%c%c%c, use the default.\n",
(fourcc & 0xff),
(fourcc >> 8) & 0xff,
(fourcc >> 16) & 0xff,
(fourcc >> 24) & 0xff);
fourcc = mxc_jpeg_get_default_fourcc(ctx, f->type);
fmt = mxc_jpeg_find_format(fourcc);
if (!fmt)
return -EINVAL;
f->fmt.pix_mp.pixelformat = fourcc;
}
q_data->fmt = fmt;
memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved));
pix_mp->field = V4L2_FIELD_NONE;
pix_mp->num_planes = fmt->mem_planes;
pix_mp->pixelformat = fmt->fourcc;
q_data->w = w;
q_data->h = h;
q_data->w_adjusted = w;
q_data->h_adjusted = h;
v4l_bound_align_image(&q_data->w_adjusted,
w, /* adjust upwards*/
MXC_JPEG_MAX_WIDTH,
fmt->h_align,
&q_data->h_adjusted,
h, /* adjust upwards*/
MXC_JPEG_MAX_HEIGHT,
fmt->v_align,
0);
for (i = 0; i < pix_mp->num_planes; i++) {
pfmt = &pix_mp->plane_fmt[i];
q_data->bytesperline[i] = pfmt->bytesperline;
q_data->sizeimage[i] = pfmt->sizeimage;
}
/* calculate bytesperline & sizeimage */
mxc_jpeg_bytesperline(q_data, fmt->precision);
mxc_jpeg_sizeimage(q_data);
/* adjust user format according to our calculations */
for (i = 0; i < pix_mp->num_planes; i++) {
pfmt = &pix_mp->plane_fmt[i];
memset(pfmt->reserved, 0, sizeof(pfmt->reserved));
pfmt->bytesperline = q_data->bytesperline[i];
pfmt->sizeimage = mxc_jpeg_get_plane_size(q_data, i);
}
/* fix colorspace information to sRGB for both output & capture */
pix_mp->colorspace = V4L2_COLORSPACE_SRGB;
pix_mp->ycbcr_enc = V4L2_YCBCR_ENC_601;
pix_mp->xfer_func = V4L2_XFER_FUNC_SRGB;
/*
* this hardware does not change the range of the samples
* but since inside JPEG the YUV quantization is full-range,
* this driver will always use full-range for the raw frames, too
*/
pix_mp->quantization = V4L2_QUANTIZATION_FULL_RANGE;
if (fmt->flags == MXC_JPEG_FMT_TYPE_RAW) {
q_data->crop.left = 0;
q_data->crop.top = 0;
q_data->crop.width = q_data->w;
q_data->crop.height = q_data->h;
}
pix_mp->width = q_data->w_adjusted;
pix_mp->height = q_data->h_adjusted;
return 0;
}
static int mxc_jpeg_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
struct device *dev = jpeg->dev;
struct mxc_jpeg_q_data tmp_q;
if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) {
dev_err(dev, "TRY_FMT with Invalid type: %d\n", f->type);
return -EINVAL;
}
if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE && V4L2_TYPE_IS_CAPTURE(f->type))
f->fmt.pix_mp.pixelformat = mxc_jpeg_try_fourcc(ctx, f->fmt.pix_mp.pixelformat);
return mxc_jpeg_try_fmt(f, ctx, &tmp_q);
}
static int mxc_jpeg_try_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
struct device *dev = jpeg->dev;
struct mxc_jpeg_q_data tmp_q;
if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) {
dev_err(dev, "TRY_FMT with Invalid type: %d\n", f->type);
return -EINVAL;
}
return mxc_jpeg_try_fmt(f, ctx, &tmp_q);
}
static void mxc_jpeg_s_parsed_fmt(struct mxc_jpeg_ctx *ctx, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct mxc_jpeg_q_data *q_data_cap;
if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE || !V4L2_TYPE_IS_CAPTURE(f->type))
return;
if (!ctx->header_parsed)
return;
q_data_cap = mxc_jpeg_get_q_data(ctx, f->type);
pix_mp->pixelformat = mxc_jpeg_try_fourcc(ctx, pix_mp->pixelformat);
pix_mp->width = q_data_cap->w;
pix_mp->height = q_data_cap->h;
}
static int mxc_jpeg_s_fmt(struct mxc_jpeg_ctx *ctx,
struct v4l2_format *f)
{
struct vb2_queue *vq;
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
if (vb2_is_busy(vq)) {
v4l2_err(&jpeg->v4l2_dev, "queue busy\n");
return -EBUSY;
}
mxc_jpeg_s_parsed_fmt(ctx, f);
return mxc_jpeg_try_fmt(f, ctx, mxc_jpeg_get_q_data(ctx, f->type));
}
static int mxc_jpeg_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
return mxc_jpeg_s_fmt(mxc_jpeg_fh_to_ctx(priv), f);
}
static int mxc_jpeg_s_fmt_vid_out(struct file *file, void *priv,
struct v4l2_format *f)
{
int ret;
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
struct vb2_queue *dst_vq;
struct mxc_jpeg_q_data *q_data_cap;
enum v4l2_buf_type cap_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
struct v4l2_format fc;
ret = mxc_jpeg_s_fmt(mxc_jpeg_fh_to_ctx(priv), f);
if (ret)
return ret;
if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE)
return 0;
dst_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, cap_type);
if (!dst_vq)
return -EINVAL;
if (vb2_is_busy(dst_vq))
return 0;
q_data_cap = mxc_jpeg_get_q_data(ctx, cap_type);
if (q_data_cap->w == f->fmt.pix_mp.width && q_data_cap->h == f->fmt.pix_mp.height)
return 0;
memset(&fc, 0, sizeof(fc));
fc.type = cap_type;
fc.fmt.pix_mp.pixelformat = q_data_cap->fmt->fourcc;
fc.fmt.pix_mp.width = f->fmt.pix_mp.width;
fc.fmt.pix_mp.height = f->fmt.pix_mp.height;
return mxc_jpeg_s_fmt_vid_cap(file, priv, &fc);
}
static int mxc_jpeg_g_fmt_vid(struct file *file, void *priv,
struct v4l2_format *f)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv);
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
struct device *dev = jpeg->dev;
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct mxc_jpeg_q_data *q_data = mxc_jpeg_get_q_data(ctx, f->type);
int i;
if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) {
dev_err(dev, "G_FMT with Invalid type: %d\n", f->type);
return -EINVAL;
}
pix_mp->pixelformat = q_data->fmt->fourcc;
pix_mp->width = q_data->w;
pix_mp->height = q_data->h;
pix_mp->field = V4L2_FIELD_NONE;
if (q_data->fmt->flags == MXC_JPEG_FMT_TYPE_RAW) {
pix_mp->width = q_data->w_adjusted;
pix_mp->height = q_data->h_adjusted;
}
/* fix colorspace information to sRGB for both output & capture */
pix_mp->colorspace = V4L2_COLORSPACE_SRGB;
pix_mp->ycbcr_enc = V4L2_YCBCR_ENC_601;
pix_mp->xfer_func = V4L2_XFER_FUNC_SRGB;
pix_mp->quantization = V4L2_QUANTIZATION_FULL_RANGE;
pix_mp->num_planes = q_data->fmt->mem_planes;
for (i = 0; i < pix_mp->num_planes; i++) {
pix_mp->plane_fmt[i].bytesperline = q_data->bytesperline[i];
pix_mp->plane_fmt[i].sizeimage = mxc_jpeg_get_plane_size(q_data, i);
}
return 0;
}
static int mxc_jpeg_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
struct mxc_jpeg_q_data *q_data_cap;
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
return -EINVAL;
q_data_cap = mxc_jpeg_get_q_data(ctx, s->type);
switch (s->target) {
case V4L2_SEL_TGT_COMPOSE:
case V4L2_SEL_TGT_COMPOSE_DEFAULT:
s->r = q_data_cap->crop;
break;
case V4L2_SEL_TGT_COMPOSE_PADDED:
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
s->r.left = 0;
s->r.top = 0;
s->r.width = q_data_cap->w_adjusted;
s->r.height = q_data_cap->h_adjusted;
break;
default:
return -EINVAL;
}
return 0;
}
static int mxc_jpeg_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
struct mxc_jpeg_q_data *q_data_out;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return -EINVAL;
q_data_out = mxc_jpeg_get_q_data(ctx, s->type);
switch (s->target) {
case V4L2_SEL_TGT_CROP_DEFAULT:
case V4L2_SEL_TGT_CROP_BOUNDS:
s->r.left = 0;
s->r.top = 0;
s->r.width = q_data_out->w;
s->r.height = q_data_out->h;
break;
case V4L2_SEL_TGT_CROP:
s->r = q_data_out->crop;
break;
default:
return -EINVAL;
}
return 0;
}
static int mxc_jpeg_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE)
return mxc_jpeg_dec_g_selection(file, fh, s);
else
return mxc_jpeg_enc_g_selection(file, fh, s);
}
static int mxc_jpeg_s_selection(struct file *file, void *fh, struct v4l2_selection *s)
{
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(fh);
struct mxc_jpeg_q_data *q_data_out;
if (ctx->mxc_jpeg->mode != MXC_JPEG_ENCODE)
return -ENOTTY;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
return -EINVAL;
if (s->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
q_data_out = mxc_jpeg_get_q_data(ctx, s->type);
if (s->r.left || s->r.top)
return -EINVAL;
if (s->r.width > q_data_out->w || s->r.height > q_data_out->h)
return -EINVAL;
q_data_out->crop.left = 0;
q_data_out->crop.top = 0;
q_data_out->crop.width = s->r.width;
q_data_out->crop.height = s->r.height;
return 0;
}
static int mxc_jpeg_subscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_EOS:
return v4l2_event_subscribe(fh, sub, 0, NULL);
case V4L2_EVENT_SOURCE_CHANGE:
return v4l2_src_change_event_subscribe(fh, sub);
case V4L2_EVENT_CTRL:
return v4l2_ctrl_subscribe_event(fh, sub);
default:
return -EINVAL;
}
}
static const struct v4l2_ioctl_ops mxc_jpeg_ioctl_ops = {
.vidioc_querycap = mxc_jpeg_querycap,
.vidioc_enum_fmt_vid_cap = mxc_jpeg_enum_fmt_vid_cap,
.vidioc_enum_fmt_vid_out = mxc_jpeg_enum_fmt_vid_out,
.vidioc_try_fmt_vid_cap_mplane = mxc_jpeg_try_fmt_vid_cap,
.vidioc_try_fmt_vid_out_mplane = mxc_jpeg_try_fmt_vid_out,
.vidioc_s_fmt_vid_cap_mplane = mxc_jpeg_s_fmt_vid_cap,
.vidioc_s_fmt_vid_out_mplane = mxc_jpeg_s_fmt_vid_out,
.vidioc_g_fmt_vid_cap_mplane = mxc_jpeg_g_fmt_vid,
.vidioc_g_fmt_vid_out_mplane = mxc_jpeg_g_fmt_vid,
.vidioc_g_selection = mxc_jpeg_g_selection,
.vidioc_s_selection = mxc_jpeg_s_selection,
.vidioc_subscribe_event = mxc_jpeg_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
.vidioc_decoder_cmd = mxc_jpeg_decoder_cmd,
.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
.vidioc_encoder_cmd = mxc_jpeg_encoder_cmd,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
};
static int mxc_jpeg_release(struct file *file)
{
struct mxc_jpeg_dev *mxc_jpeg = video_drvdata(file);
struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(file->private_data);
struct device *dev = mxc_jpeg->dev;
mutex_lock(&mxc_jpeg->lock);
if (mxc_jpeg->mode == MXC_JPEG_DECODE)
dev_dbg(dev, "Release JPEG decoder instance on slot %d.",
ctx->slot);
else
dev_dbg(dev, "Release JPEG encoder instance on slot %d.",
ctx->slot);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
kfree(ctx);
mutex_unlock(&mxc_jpeg->lock);
return 0;
}
static const struct v4l2_file_operations mxc_jpeg_fops = {
.owner = THIS_MODULE,
.open = mxc_jpeg_open,
.release = mxc_jpeg_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct v4l2_m2m_ops mxc_jpeg_m2m_ops = {
.job_ready = mxc_jpeg_job_ready,
.device_run = mxc_jpeg_device_run,
};
static void mxc_jpeg_detach_pm_domains(struct mxc_jpeg_dev *jpeg)
{
int i;
for (i = 0; i < jpeg->num_domains; i++) {
if (jpeg->pd_link[i] && !IS_ERR(jpeg->pd_link[i]))
device_link_del(jpeg->pd_link[i]);
if (jpeg->pd_dev[i] && !IS_ERR(jpeg->pd_dev[i]))
dev_pm_domain_detach(jpeg->pd_dev[i], true);
jpeg->pd_dev[i] = NULL;
jpeg->pd_link[i] = NULL;
}
}
static int mxc_jpeg_attach_pm_domains(struct mxc_jpeg_dev *jpeg)
{
struct device *dev = jpeg->dev;
struct device_node *np = jpeg->pdev->dev.of_node;
int i;
int ret;
jpeg->num_domains = of_count_phandle_with_args(np, "power-domains",
"#power-domain-cells");
if (jpeg->num_domains < 0) {
dev_err(dev, "No power domains defined for jpeg node\n");
return jpeg->num_domains;
}
if (jpeg->num_domains == 1) {
/* genpd_dev_pm_attach() attach automatically if power domains count is 1 */
jpeg->num_domains = 0;
return 0;
}
jpeg->pd_dev = devm_kmalloc_array(dev, jpeg->num_domains,
sizeof(*jpeg->pd_dev), GFP_KERNEL);
if (!jpeg->pd_dev)
return -ENOMEM;
jpeg->pd_link = devm_kmalloc_array(dev, jpeg->num_domains,
sizeof(*jpeg->pd_link), GFP_KERNEL);
if (!jpeg->pd_link)
return -ENOMEM;
for (i = 0; i < jpeg->num_domains; i++) {
jpeg->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
if (IS_ERR(jpeg->pd_dev[i])) {
ret = PTR_ERR(jpeg->pd_dev[i]);
goto fail;
}
jpeg->pd_link[i] = device_link_add(dev, jpeg->pd_dev[i],
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME);
if (!jpeg->pd_link[i]) {
ret = -EINVAL;
goto fail;
}
}
return 0;
fail:
mxc_jpeg_detach_pm_domains(jpeg);
return ret;
}
static int mxc_jpeg_probe(struct platform_device *pdev)
{
struct mxc_jpeg_dev *jpeg;
struct device *dev = &pdev->dev;
int dec_irq;
int ret;
int mode;
const struct of_device_id *of_id;
of_id = of_match_node(mxc_jpeg_match, dev->of_node);
if (!of_id)
return -ENODEV;
mode = *(const int *)of_id->data;
jpeg = devm_kzalloc(dev, sizeof(struct mxc_jpeg_dev), GFP_KERNEL);
if (!jpeg)
return -ENOMEM;
mutex_init(&jpeg->lock);
spin_lock_init(&jpeg->hw_lock);
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(&pdev->dev, "No suitable DMA available.\n");
goto err_irq;
}
jpeg->base_reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(jpeg->base_reg))
return PTR_ERR(jpeg->base_reg);
ret = of_property_read_u32_index(pdev->dev.of_node, "slot", 0, &jpeg->slot_data.slot);
if (ret)
jpeg->slot_data.slot = 0;
dev_info(&pdev->dev, "choose slot %d\n", jpeg->slot_data.slot);
dec_irq = platform_get_irq(pdev, 0);
if (dec_irq < 0) {
ret = dec_irq;
goto err_irq;
}
ret = devm_request_irq(&pdev->dev, dec_irq, mxc_jpeg_dec_irq,
0, pdev->name, jpeg);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq %d (%d)\n",
dec_irq, ret);
goto err_irq;
}
jpeg->pdev = pdev;
jpeg->dev = dev;
jpeg->mode = mode;
/* Get clocks */
ret = devm_clk_bulk_get_all(&pdev->dev, &jpeg->clks);
if (ret < 0) {
dev_err(dev, "failed to get clock\n");
goto err_clk;
}
jpeg->num_clks = ret;
ret = mxc_jpeg_attach_pm_domains(jpeg);
if (ret < 0) {
dev_err(dev, "failed to attach power domains %d\n", ret);
return ret;
}
/* v4l2 */
ret = v4l2_device_register(dev, &jpeg->v4l2_dev);
if (ret) {
dev_err(dev, "failed to register v4l2 device\n");
goto err_register;
}
jpeg->m2m_dev = v4l2_m2m_init(&mxc_jpeg_m2m_ops);
if (IS_ERR(jpeg->m2m_dev)) {
dev_err(dev, "failed to register v4l2 device\n");
ret = PTR_ERR(jpeg->m2m_dev);
goto err_m2m;
}
jpeg->dec_vdev = video_device_alloc();
if (!jpeg->dec_vdev) {
dev_err(dev, "failed to register v4l2 device\n");
ret = -ENOMEM;
goto err_vdev_alloc;
}
if (mode == MXC_JPEG_ENCODE)
snprintf(jpeg->dec_vdev->name,
sizeof(jpeg->dec_vdev->name),
"%s-enc", MXC_JPEG_NAME);
else
snprintf(jpeg->dec_vdev->name,
sizeof(jpeg->dec_vdev->name),
"%s-dec", MXC_JPEG_NAME);
jpeg->dec_vdev->fops = &mxc_jpeg_fops;
jpeg->dec_vdev->ioctl_ops = &mxc_jpeg_ioctl_ops;
jpeg->dec_vdev->minor = -1;
jpeg->dec_vdev->release = video_device_release;
jpeg->dec_vdev->lock = &jpeg->lock; /* lock for ioctl serialization */
jpeg->dec_vdev->v4l2_dev = &jpeg->v4l2_dev;
jpeg->dec_vdev->vfl_dir = VFL_DIR_M2M;
jpeg->dec_vdev->device_caps = V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_M2M_MPLANE;
if (mode == MXC_JPEG_ENCODE) {
v4l2_disable_ioctl(jpeg->dec_vdev, VIDIOC_DECODER_CMD);
v4l2_disable_ioctl(jpeg->dec_vdev, VIDIOC_TRY_DECODER_CMD);
} else {
v4l2_disable_ioctl(jpeg->dec_vdev, VIDIOC_ENCODER_CMD);
v4l2_disable_ioctl(jpeg->dec_vdev, VIDIOC_TRY_ENCODER_CMD);
}
ret = video_register_device(jpeg->dec_vdev, VFL_TYPE_VIDEO, -1);
if (ret) {
dev_err(dev, "failed to register video device\n");
goto err_vdev_register;
}
video_set_drvdata(jpeg->dec_vdev, jpeg);
if (mode == MXC_JPEG_ENCODE)
v4l2_info(&jpeg->v4l2_dev,
"encoder device registered as /dev/video%d (%d,%d)\n",
jpeg->dec_vdev->num, VIDEO_MAJOR,
jpeg->dec_vdev->minor);
else
v4l2_info(&jpeg->v4l2_dev,
"decoder device registered as /dev/video%d (%d,%d)\n",
jpeg->dec_vdev->num, VIDEO_MAJOR,
jpeg->dec_vdev->minor);
platform_set_drvdata(pdev, jpeg);
pm_runtime_enable(dev);
return 0;
err_vdev_register:
video_device_release(jpeg->dec_vdev);
err_vdev_alloc:
v4l2_m2m_release(jpeg->m2m_dev);
err_m2m:
v4l2_device_unregister(&jpeg->v4l2_dev);
err_register:
mxc_jpeg_detach_pm_domains(jpeg);
err_irq:
err_clk:
return ret;
}
#ifdef CONFIG_PM
static int mxc_jpeg_runtime_resume(struct device *dev)
{
struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev);
int ret;
ret = clk_bulk_prepare_enable(jpeg->num_clks, jpeg->clks);
if (ret < 0) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
return 0;
}
static int mxc_jpeg_runtime_suspend(struct device *dev)
{
struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(jpeg->num_clks, jpeg->clks);
return 0;
}
#endif
#ifdef CONFIG_PM_SLEEP
static int mxc_jpeg_suspend(struct device *dev)
{
struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev);
v4l2_m2m_suspend(jpeg->m2m_dev);
return pm_runtime_force_suspend(dev);
}
static int mxc_jpeg_resume(struct device *dev)
{
struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_force_resume(dev);
if (ret < 0)
return ret;
v4l2_m2m_resume(jpeg->m2m_dev);
return ret;
}
#endif
static const struct dev_pm_ops mxc_jpeg_pm_ops = {
SET_RUNTIME_PM_OPS(mxc_jpeg_runtime_suspend,
mxc_jpeg_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(mxc_jpeg_suspend, mxc_jpeg_resume)
};
static void mxc_jpeg_remove(struct platform_device *pdev)
{
struct mxc_jpeg_dev *jpeg = platform_get_drvdata(pdev);
mxc_jpeg_free_slot_data(jpeg);
pm_runtime_disable(&pdev->dev);
video_unregister_device(jpeg->dec_vdev);
v4l2_m2m_release(jpeg->m2m_dev);
v4l2_device_unregister(&jpeg->v4l2_dev);
mxc_jpeg_detach_pm_domains(jpeg);
}
MODULE_DEVICE_TABLE(of, mxc_jpeg_match);
static struct platform_driver mxc_jpeg_driver = {
.probe = mxc_jpeg_probe,
.remove_new = mxc_jpeg_remove,
.driver = {
.name = "mxc-jpeg",
.of_match_table = mxc_jpeg_match,
.pm = &mxc_jpeg_pm_ops,
},
};
module_platform_driver(mxc_jpeg_driver);
MODULE_AUTHOR("Zhengyu Shen <[email protected]>");
MODULE_AUTHOR("Mirela Rabulea <[email protected]>");
MODULE_DESCRIPTION("V4L2 driver for i.MX8 QXP/QM JPEG encoder/decoder");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Video IP Core
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <[email protected]>
* Laurent Pinchart <[email protected]>
*/
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/media/xilinx-vip.h>
#include "xilinx-vip.h"
/* -----------------------------------------------------------------------------
* Helper functions
*/
static const struct xvip_video_format xvip_video_formats[] = {
{ XVIP_VF_YUV_422, 8, NULL, MEDIA_BUS_FMT_UYVY8_1X16,
2, V4L2_PIX_FMT_YUYV },
{ XVIP_VF_YUV_444, 8, NULL, MEDIA_BUS_FMT_VUY8_1X24,
3, V4L2_PIX_FMT_YUV444 },
{ XVIP_VF_RBG, 8, NULL, MEDIA_BUS_FMT_RBG888_1X24,
3, 0 },
{ XVIP_VF_MONO_SENSOR, 8, "mono", MEDIA_BUS_FMT_Y8_1X8,
1, V4L2_PIX_FMT_GREY },
{ XVIP_VF_MONO_SENSOR, 8, "rggb", MEDIA_BUS_FMT_SRGGB8_1X8,
1, V4L2_PIX_FMT_SRGGB8 },
{ XVIP_VF_MONO_SENSOR, 8, "grbg", MEDIA_BUS_FMT_SGRBG8_1X8,
1, V4L2_PIX_FMT_SGRBG8 },
{ XVIP_VF_MONO_SENSOR, 8, "gbrg", MEDIA_BUS_FMT_SGBRG8_1X8,
1, V4L2_PIX_FMT_SGBRG8 },
{ XVIP_VF_MONO_SENSOR, 8, "bggr", MEDIA_BUS_FMT_SBGGR8_1X8,
1, V4L2_PIX_FMT_SBGGR8 },
{ XVIP_VF_MONO_SENSOR, 12, "mono", MEDIA_BUS_FMT_Y12_1X12,
2, V4L2_PIX_FMT_Y12 },
};
/**
* xvip_get_format_by_code - Retrieve format information for a media bus code
* @code: the format media bus code
*
* Return: a pointer to the format information structure corresponding to the
* given V4L2 media bus format @code, or ERR_PTR if no corresponding format can
* be found.
*/
const struct xvip_video_format *xvip_get_format_by_code(unsigned int code)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(xvip_video_formats); ++i) {
const struct xvip_video_format *format = &xvip_video_formats[i];
if (format->code == code)
return format;
}
return ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(xvip_get_format_by_code);
/**
* xvip_get_format_by_fourcc - Retrieve format information for a 4CC
* @fourcc: the format 4CC
*
* Return: a pointer to the format information structure corresponding to the
* given V4L2 format @fourcc. If not found, return a pointer to the first
* available format (V4L2_PIX_FMT_YUYV).
*/
const struct xvip_video_format *xvip_get_format_by_fourcc(u32 fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(xvip_video_formats); ++i) {
const struct xvip_video_format *format = &xvip_video_formats[i];
if (format->fourcc == fourcc)
return format;
}
return &xvip_video_formats[0];
}
EXPORT_SYMBOL_GPL(xvip_get_format_by_fourcc);
/**
* xvip_of_get_format - Parse a device tree node and return format information
* @node: the device tree node
*
* Read the xlnx,video-format, xlnx,video-width and xlnx,cfa-pattern properties
* from the device tree @node passed as an argument and return the corresponding
* format information.
*
* Return: a pointer to the format information structure corresponding to the
* format name and width, or ERR_PTR if no corresponding format can be found.
*/
const struct xvip_video_format *xvip_of_get_format(struct device_node *node)
{
const char *pattern = "mono";
unsigned int vf_code;
unsigned int i;
u32 width;
int ret;
ret = of_property_read_u32(node, "xlnx,video-format", &vf_code);
if (ret < 0)
return ERR_PTR(ret);
ret = of_property_read_u32(node, "xlnx,video-width", &width);
if (ret < 0)
return ERR_PTR(ret);
if (vf_code == XVIP_VF_MONO_SENSOR)
of_property_read_string(node, "xlnx,cfa-pattern", &pattern);
for (i = 0; i < ARRAY_SIZE(xvip_video_formats); ++i) {
const struct xvip_video_format *format = &xvip_video_formats[i];
if (format->vf_code != vf_code || format->width != width)
continue;
if (vf_code == XVIP_VF_MONO_SENSOR &&
strcmp(pattern, format->pattern))
continue;
return format;
}
return ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(xvip_of_get_format);
/**
* xvip_set_format_size - Set the media bus frame format size
* @format: V4L2 frame format on media bus
* @fmt: media bus format
*
* Set the media bus frame format size. The width / height from the subdevice
* format are set to the given media bus format. The new format size is stored
* in @format. The width and height are clamped using default min / max values.
*/
void xvip_set_format_size(struct v4l2_mbus_framefmt *format,
const struct v4l2_subdev_format *fmt)
{
format->width = clamp_t(unsigned int, fmt->format.width,
XVIP_MIN_WIDTH, XVIP_MAX_WIDTH);
format->height = clamp_t(unsigned int, fmt->format.height,
XVIP_MIN_HEIGHT, XVIP_MAX_HEIGHT);
}
EXPORT_SYMBOL_GPL(xvip_set_format_size);
/**
* xvip_clr_or_set - Clear or set the register with a bitmask
* @xvip: Xilinx Video IP device
* @addr: address of register
* @mask: bitmask to be set or cleared
* @set: boolean flag indicating whether to set or clear
*
* Clear or set the register at address @addr with a bitmask @mask depending on
* the boolean flag @set. When the flag @set is true, the bitmask is set in
* the register, otherwise the bitmask is cleared from the register
* when the flag @set is false.
*
* Fox example, this function can be used to set a control with a boolean value
* requested by users. If the caller knows whether to set or clear in the first
* place, the caller should call xvip_clr() or xvip_set() directly instead of
* using this function.
*/
void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set)
{
u32 reg;
reg = xvip_read(xvip, addr);
reg = set ? reg | mask : reg & ~mask;
xvip_write(xvip, addr, reg);
}
EXPORT_SYMBOL_GPL(xvip_clr_or_set);
/**
* xvip_clr_and_set - Clear and set the register with a bitmask
* @xvip: Xilinx Video IP device
* @addr: address of register
* @clr: bitmask to be cleared
* @set: bitmask to be set
*
* Clear a bit(s) of mask @clr in the register at address @addr, then set
* a bit(s) of mask @set in the register after.
*/
void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set)
{
u32 reg;
reg = xvip_read(xvip, addr);
reg &= ~clr;
reg |= set;
xvip_write(xvip, addr, reg);
}
EXPORT_SYMBOL_GPL(xvip_clr_and_set);
int xvip_init_resources(struct xvip_device *xvip)
{
struct platform_device *pdev = to_platform_device(xvip->dev);
xvip->iomem = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xvip->iomem))
return PTR_ERR(xvip->iomem);
xvip->clk = devm_clk_get(xvip->dev, NULL);
if (IS_ERR(xvip->clk))
return PTR_ERR(xvip->clk);
clk_prepare_enable(xvip->clk);
return 0;
}
EXPORT_SYMBOL_GPL(xvip_init_resources);
void xvip_cleanup_resources(struct xvip_device *xvip)
{
clk_disable_unprepare(xvip->clk);
}
EXPORT_SYMBOL_GPL(xvip_cleanup_resources);
/* -----------------------------------------------------------------------------
* Subdev operations handlers
*/
/**
* xvip_enum_mbus_code - Enumerate the media format code
* @subdev: V4L2 subdevice
* @sd_state: V4L2 subdev state
* @code: returning media bus code
*
* Enumerate the media bus code of the subdevice. Return the corresponding
* pad format code. This function only works for subdevices with fixed format
* on all pads. Subdevices with multiple format should have their own
* function to enumerate mbus codes.
*
* Return: 0 if the media bus code is found, or -EINVAL if the format index
* is not valid.
*/
int xvip_enum_mbus_code(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct v4l2_mbus_framefmt *format;
/* Enumerating frame sizes based on the active configuration isn't
* supported yet.
*/
if (code->which == V4L2_SUBDEV_FORMAT_ACTIVE)
return -EINVAL;
if (code->index)
return -EINVAL;
format = v4l2_subdev_get_try_format(subdev, sd_state, code->pad);
code->code = format->code;
return 0;
}
EXPORT_SYMBOL_GPL(xvip_enum_mbus_code);
/**
* xvip_enum_frame_size - Enumerate the media bus frame size
* @subdev: V4L2 subdevice
* @sd_state: V4L2 subdev state
* @fse: returning media bus frame size
*
* This function is a drop-in implementation of the subdev enum_frame_size pad
* operation. It assumes that the subdevice has one sink pad and one source
* pad, and that the format on the source pad is always identical to the
* format on the sink pad. Entities with different requirements need to
* implement their own enum_frame_size handlers.
*
* Return: 0 if the media bus frame size is found, or -EINVAL
* if the index or the code is not valid.
*/
int xvip_enum_frame_size(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
struct v4l2_mbus_framefmt *format;
/* Enumerating frame sizes based on the active configuration isn't
* supported yet.
*/
if (fse->which == V4L2_SUBDEV_FORMAT_ACTIVE)
return -EINVAL;
format = v4l2_subdev_get_try_format(subdev, sd_state, fse->pad);
if (fse->index || fse->code != format->code)
return -EINVAL;
if (fse->pad == XVIP_PAD_SINK) {
fse->min_width = XVIP_MIN_WIDTH;
fse->max_width = XVIP_MAX_WIDTH;
fse->min_height = XVIP_MIN_HEIGHT;
fse->max_height = XVIP_MAX_HEIGHT;
} else {
/* The size on the source pad is fixed and always identical to
* the size on the sink pad.
*/
fse->min_width = format->width;
fse->max_width = format->width;
fse->min_height = format->height;
fse->max_height = format->height;
}
return 0;
}
EXPORT_SYMBOL_GPL(xvip_enum_frame_size);
| linux-master | drivers/media/platform/xilinx/xilinx-vip.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Xilinx MIPI CSI-2 Rx Subsystem
*
* Copyright (C) 2016 - 2020 Xilinx, Inc.
*
* Contacts: Vishal Sagar <[email protected]>
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/v4l2-subdev.h>
#include <media/media-entity.h>
#include <media/mipi-csi2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#include "xilinx-vip.h"
/* Register register map */
#define XCSI_CCR_OFFSET 0x00
#define XCSI_CCR_SOFTRESET BIT(1)
#define XCSI_CCR_ENABLE BIT(0)
#define XCSI_PCR_OFFSET 0x04
#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
#define XCSI_CSR_OFFSET 0x10
#define XCSI_CSR_PKTCNT GENMASK(31, 16)
#define XCSI_CSR_SPFIFOFULL BIT(3)
#define XCSI_CSR_SPFIFONE BIT(2)
#define XCSI_CSR_SLBF BIT(1)
#define XCSI_CSR_RIPCD BIT(0)
#define XCSI_GIER_OFFSET 0x20
#define XCSI_GIER_GIE BIT(0)
#define XCSI_ISR_OFFSET 0x24
#define XCSI_IER_OFFSET 0x28
#define XCSI_ISR_FR BIT(31)
#define XCSI_ISR_VCXFE BIT(30)
#define XCSI_ISR_WCC BIT(22)
#define XCSI_ISR_ILC BIT(21)
#define XCSI_ISR_SPFIFOF BIT(20)
#define XCSI_ISR_SPFIFONE BIT(19)
#define XCSI_ISR_SLBF BIT(18)
#define XCSI_ISR_STOP BIT(17)
#define XCSI_ISR_SOTERR BIT(13)
#define XCSI_ISR_SOTSYNCERR BIT(12)
#define XCSI_ISR_ECC2BERR BIT(11)
#define XCSI_ISR_ECC1BERR BIT(10)
#define XCSI_ISR_CRCERR BIT(9)
#define XCSI_ISR_DATAIDERR BIT(8)
#define XCSI_ISR_VC3FSYNCERR BIT(7)
#define XCSI_ISR_VC3FLVLERR BIT(6)
#define XCSI_ISR_VC2FSYNCERR BIT(5)
#define XCSI_ISR_VC2FLVLERR BIT(4)
#define XCSI_ISR_VC1FSYNCERR BIT(3)
#define XCSI_ISR_VC1FLVLERR BIT(2)
#define XCSI_ISR_VC0FSYNCERR BIT(1)
#define XCSI_ISR_VC0FLVLERR BIT(0)
#define XCSI_ISR_ALLINTR_MASK (0xc07e3fff)
/*
* Removed VCXFE mask as it doesn't exist in IER
* Removed STOP state irq as this will keep driver in irq handler only
*/
#define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\
~(XCSI_ISR_STOP | XCSI_ISR_VCXFE))
#define XCSI_SPKTR_OFFSET 0x30
#define XCSI_SPKTR_DATA GENMASK(23, 8)
#define XCSI_SPKTR_VC GENMASK(7, 6)
#define XCSI_SPKTR_DT GENMASK(5, 0)
#define XCSI_SPKT_FIFO_DEPTH 31
#define XCSI_VCXR_OFFSET 0x34
#define XCSI_VCXR_VCERR GENMASK(23, 0)
#define XCSI_VCXR_FSYNCERR BIT(1)
#define XCSI_VCXR_FLVLERR BIT(0)
#define XCSI_CLKINFR_OFFSET 0x3C
#define XCSI_CLKINFR_STOP BIT(1)
#define XCSI_DLXINFR_OFFSET 0x40
#define XCSI_DLXINFR_STOP BIT(5)
#define XCSI_DLXINFR_SOTERR BIT(1)
#define XCSI_DLXINFR_SOTSYNCERR BIT(0)
#define XCSI_MAXDL_COUNT 0x4
#define XCSI_VCXINF1R_OFFSET 0x60
#define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)
#define XCSI_VCXINF1R_LINECOUNT_SHIFT 16
#define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)
#define XCSI_VCXINF2R_OFFSET 0x64
#define XCSI_VCXINF2R_DT GENMASK(5, 0)
#define XCSI_MAXVCX_COUNT 16
/*
* Sink pad connected to sensor source pad.
* Source pad connected to next module like demosaic.
*/
#define XCSI_MEDIA_PADS 2
#define XCSI_DEFAULT_WIDTH 1920
#define XCSI_DEFAULT_HEIGHT 1080
#define XCSI_VCX_START 4
#define XCSI_MAX_VC 4
#define XCSI_MAX_VCX 16
#define XCSI_NEXTREG_OFFSET 4
/* There are 2 events frame sync and frame level error per VC */
#define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2)
/**
* struct xcsi2rxss_event - Event log structure
* @mask: Event mask
* @name: Name of the event
*/
struct xcsi2rxss_event {
u32 mask;
const char *name;
};
static const struct xcsi2rxss_event xcsi2rxss_events[] = {
{ XCSI_ISR_FR, "Frame Received" },
{ XCSI_ISR_VCXFE, "VCX Frame Errors" },
{ XCSI_ISR_WCC, "Word Count Errors" },
{ XCSI_ISR_ILC, "Invalid Lane Count Error" },
{ XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" },
{ XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" },
{ XCSI_ISR_SLBF, "Streamline Buffer Full Error" },
{ XCSI_ISR_STOP, "Lane Stop State" },
{ XCSI_ISR_SOTERR, "SOT Error" },
{ XCSI_ISR_SOTSYNCERR, "SOT Sync Error" },
{ XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" },
{ XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" },
{ XCSI_ISR_CRCERR, "CRC Error" },
{ XCSI_ISR_DATAIDERR, "Data Id Error" },
{ XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" },
{ XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" },
{ XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" },
{ XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" },
{ XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" },
{ XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" },
{ XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" },
{ XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" }
};
#define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events)
/*
* This table provides a mapping between CSI-2 Data type
* and media bus formats
*/
static const u32 xcsi2dt_mbus_lut[][2] = {
{ MIPI_CSI2_DT_YUV422_8B, MEDIA_BUS_FMT_UYVY8_1X16 },
{ MIPI_CSI2_DT_YUV422_10B, MEDIA_BUS_FMT_UYVY10_1X20 },
{ MIPI_CSI2_DT_RGB444, 0 },
{ MIPI_CSI2_DT_RGB555, 0 },
{ MIPI_CSI2_DT_RGB565, 0 },
{ MIPI_CSI2_DT_RGB666, 0 },
{ MIPI_CSI2_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 },
{ MIPI_CSI2_DT_RAW6, 0 },
{ MIPI_CSI2_DT_RAW7, 0 },
{ MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 },
{ MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 },
{ MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 },
{ MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 },
{ MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 },
{ MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 },
{ MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 },
{ MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 },
{ MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 },
{ MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 },
{ MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 },
{ MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 },
{ MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_Y12_1X12 },
{ MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 },
{ MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 },
{ MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 },
{ MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 },
{ MIPI_CSI2_DT_RAW20, 0 },
};
/**
* struct xcsi2rxss_state - CSI-2 Rx Subsystem device structure
* @subdev: The v4l2 subdev structure
* @format: Active V4L2 formats on each pad
* @default_format: Default V4L2 format
* @events: counter for events
* @vcx_events: counter for vcx_events
* @dev: Platform structure
* @rsubdev: Remote subdev connected to sink pad
* @rst_gpio: reset to video_aresetn
* @clks: array of clocks
* @iomem: Base address of subsystem
* @max_num_lanes: Maximum number of lanes present
* @datatype: Data type filter
* @lock: mutex for accessing this structure
* @pads: media pads
* @streaming: Flag for storing streaming state
* @enable_active_lanes: If number of active lanes can be modified
* @en_vcx: If more than 4 VC are enabled
*
* This structure contains the device driver related parameters
*/
struct xcsi2rxss_state {
struct v4l2_subdev subdev;
struct v4l2_mbus_framefmt format;
struct v4l2_mbus_framefmt default_format;
u32 events[XCSI_NUM_EVENTS];
u32 vcx_events[XCSI_VCX_NUM_EVENTS];
struct device *dev;
struct v4l2_subdev *rsubdev;
struct gpio_desc *rst_gpio;
struct clk_bulk_data *clks;
void __iomem *iomem;
u32 max_num_lanes;
u32 datatype;
/* used to protect access to this struct */
struct mutex lock;
struct media_pad pads[XCSI_MEDIA_PADS];
bool streaming;
bool enable_active_lanes;
bool en_vcx;
};
static const struct clk_bulk_data xcsi2rxss_clks[] = {
{ .id = "lite_aclk" },
{ .id = "video_aclk" },
};
static inline struct xcsi2rxss_state *
to_xcsi2rxssstate(struct v4l2_subdev *subdev)
{
return container_of(subdev, struct xcsi2rxss_state, subdev);
}
/*
* Register related operations
*/
static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr)
{
return ioread32(xcsi2rxss->iomem + addr);
}
static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
u32 value)
{
iowrite32(value, xcsi2rxss->iomem + addr);
}
static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
u32 clr)
{
xcsi2rxss_write(xcsi2rxss, addr,
xcsi2rxss_read(xcsi2rxss, addr) & ~clr);
}
static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
u32 set)
{
xcsi2rxss_write(xcsi2rxss, addr, xcsi2rxss_read(xcsi2rxss, addr) | set);
}
/*
* This function returns the nth mbus for a data type.
* In case of error, mbus code returned is 0.
*/
static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
if (xcsi2dt_mbus_lut[i][0] == dt) {
if (n-- == 0)
return xcsi2dt_mbus_lut[i][1];
}
}
return 0;
}
/* This returns the data type for a media bus format else 0 */
static u32 xcsi2rxss_get_dt(u32 mbus)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
if (xcsi2dt_mbus_lut[i][1] == mbus)
return xcsi2dt_mbus_lut[i][0];
}
return 0;
}
/**
* xcsi2rxss_soft_reset - Does a soft reset of the MIPI CSI-2 Rx Subsystem
* @state: Xilinx CSI-2 Rx Subsystem structure pointer
*
* Core takes less than 100 video clock cycles to reset.
* So a larger timeout value is chosen for margin.
*
* Return: 0 - on success OR -ETIME if reset times out
*/
static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state)
{
u32 timeout = 1000; /* us */
xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
while (xcsi2rxss_read(state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) {
if (timeout == 0) {
dev_err(state->dev, "soft reset timed out!\n");
return -ETIME;
}
timeout--;
udelay(1);
}
xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
return 0;
}
static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state)
{
if (!state->rst_gpio)
return;
/* minimum of 40 dphy_clk_200M cycles */
gpiod_set_value_cansleep(state->rst_gpio, 1);
usleep_range(1, 2);
gpiod_set_value_cansleep(state->rst_gpio, 0);
}
static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state)
{
unsigned int i;
for (i = 0; i < XCSI_NUM_EVENTS; i++)
state->events[i] = 0;
for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++)
state->vcx_events[i] = 0;
}
/* Print event counters */
static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
{
struct device *dev = state->dev;
unsigned int i;
for (i = 0; i < XCSI_NUM_EVENTS; i++) {
if (state->events[i] > 0) {
dev_info(dev, "%s events: %d\n",
xcsi2rxss_events[i].name,
state->events[i]);
}
}
if (state->en_vcx) {
for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
if (state->vcx_events[i] > 0) {
dev_info(dev,
"VC %d Frame %s err vcx events: %d\n",
(i / 2) + XCSI_VCX_START,
i & 1 ? "Sync" : "Level",
state->vcx_events[i]);
}
}
}
}
/**
* xcsi2rxss_log_status - Logs the status of the CSI-2 Receiver
* @sd: Pointer to V4L2 subdevice structure
*
* This function prints the current status of Xilinx MIPI CSI-2
*
* Return: 0 on success
*/
static int xcsi2rxss_log_status(struct v4l2_subdev *sd)
{
struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
struct device *dev = xcsi2rxss->dev;
u32 reg, data;
unsigned int i, max_vc;
mutex_lock(&xcsi2rxss->lock);
xcsi2rxss_log_counters(xcsi2rxss);
dev_info(dev, "***** Core Status *****\n");
data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET);
dev_info(dev, "Short Packet FIFO Full = %s\n",
data & XCSI_CSR_SPFIFOFULL ? "true" : "false");
dev_info(dev, "Short Packet FIFO Not Empty = %s\n",
data & XCSI_CSR_SPFIFONE ? "true" : "false");
dev_info(dev, "Stream line buffer full = %s\n",
data & XCSI_CSR_SLBF ? "true" : "false");
dev_info(dev, "Soft reset/Core disable in progress = %s\n",
data & XCSI_CSR_RIPCD ? "true" : "false");
/* Clk & Lane Info */
dev_info(dev, "******** Clock Lane Info *********\n");
data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET);
dev_info(dev, "Clock Lane in Stop State = %s\n",
data & XCSI_CLKINFR_STOP ? "true" : "false");
dev_info(dev, "******** Data Lane Info *********\n");
dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n");
reg = XCSI_DLXINFR_OFFSET;
for (i = 0; i < XCSI_MAXDL_COUNT; i++) {
data = xcsi2rxss_read(xcsi2rxss, reg);
dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i,
data & XCSI_DLXINFR_SOTERR ? "true" : "false",
data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false",
data & XCSI_DLXINFR_STOP ? "true" : "false");
reg += XCSI_NEXTREG_OFFSET;
}
/* Virtual Channel Image Information */
dev_info(dev, "********** Virtual Channel Info ************\n");
dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n");
if (xcsi2rxss->en_vcx)
max_vc = XCSI_MAX_VCX;
else
max_vc = XCSI_MAX_VC;
reg = XCSI_VCXINF1R_OFFSET;
for (i = 0; i < max_vc; i++) {
u32 line_count, byte_count, data_type;
/* Get line and byte count from VCXINFR1 Register */
data = xcsi2rxss_read(xcsi2rxss, reg);
byte_count = data & XCSI_VCXINF1R_BYTECOUNT;
line_count = data & XCSI_VCXINF1R_LINECOUNT;
line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT;
/* Get data type from VCXINFR2 Register */
reg += XCSI_NEXTREG_OFFSET;
data = xcsi2rxss_read(xcsi2rxss, reg);
data_type = data & XCSI_VCXINF2R_DT;
dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count,
byte_count, data_type);
/* Move to next pair of VC Info registers */
reg += XCSI_NEXTREG_OFFSET;
}
mutex_unlock(&xcsi2rxss->lock);
return 0;
}
static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local)
{
struct media_pad *remote;
remote = media_pad_remote_pad_first(local);
if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
return NULL;
return media_entity_to_v4l2_subdev(remote->entity);
}
static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
{
int ret = 0;
/* enable core */
xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
ret = xcsi2rxss_soft_reset(state);
if (ret) {
state->streaming = false;
return ret;
}
/* enable interrupts */
xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
xcsi2rxss_write(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
xcsi2rxss_set(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
state->streaming = true;
state->rsubdev =
xcsi2rxss_get_remote_subdev(&state->pads[XVIP_PAD_SINK]);
ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1);
if (ret) {
/* disable interrupts */
xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
/* disable core */
xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
state->streaming = false;
}
return ret;
}
static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state)
{
v4l2_subdev_call(state->rsubdev, video, s_stream, 0);
/* disable interrupts */
xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
/* disable core */
xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
state->streaming = false;
}
/**
* xcsi2rxss_irq_handler - Interrupt handler for CSI-2
* @irq: IRQ number
* @data: Pointer to device state
*
* In the interrupt handler, a list of event counters are updated for
* corresponding interrupts. This is useful to get status / debug.
*
* Return: IRQ_HANDLED after handling interrupts
*/
static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)
{
struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
struct device *dev = state->dev;
u32 status;
status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK;
xcsi2rxss_write(state, XCSI_ISR_OFFSET, status);
/* Received a short packet */
if (status & XCSI_ISR_SPFIFONE) {
u32 count = 0;
/*
* Drain generic short packet FIFO by reading max 31
* (fifo depth) short packets from fifo or till fifo is empty.
*/
for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
u32 spfifostat, spkt;
spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET);
dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET);
spfifostat &= XCSI_ISR_SPFIFONE;
if (!spfifostat)
break;
xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat);
}
}
/* Short packet FIFO overflow */
if (status & XCSI_ISR_SPFIFOF)
dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
/*
* Stream line buffer full
* This means there is a backpressure from downstream IP
*/
if (status & XCSI_ISR_SLBF) {
dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
/* disable interrupts */
xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
/* disable core */
xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
/*
* The IP needs to be hard reset before it can be used now.
* This will be done in streamoff.
*/
/*
* TODO: Notify the whole pipeline with v4l2_subdev_notify() to
* inform userspace.
*/
}
/* Increment event counters */
if (status & XCSI_ISR_ALLINTR_MASK) {
unsigned int i;
for (i = 0; i < XCSI_NUM_EVENTS; i++) {
if (!(status & xcsi2rxss_events[i].mask))
continue;
state->events[i]++;
dev_dbg_ratelimited(dev, "%s: %u\n",
xcsi2rxss_events[i].name,
state->events[i]);
}
if (status & XCSI_ISR_VCXFE && state->en_vcx) {
u32 vcxstatus;
vcxstatus = xcsi2rxss_read(state, XCSI_VCXR_OFFSET);
vcxstatus &= XCSI_VCXR_VCERR;
for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
if (!(vcxstatus & BIT(i)))
continue;
state->vcx_events[i]++;
}
xcsi2rxss_write(state, XCSI_VCXR_OFFSET, vcxstatus);
}
}
return IRQ_HANDLED;
}
/**
* xcsi2rxss_s_stream - It is used to start/stop the streaming.
* @sd: V4L2 Sub device
* @enable: Flag (True / False)
*
* This function controls the start or stop of streaming for the
* Xilinx MIPI CSI-2 Rx Subsystem.
*
* Return: 0 on success, errors otherwise
*/
static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)
{
struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
int ret = 0;
mutex_lock(&xcsi2rxss->lock);
if (enable == xcsi2rxss->streaming)
goto stream_done;
if (enable) {
xcsi2rxss_reset_event_counters(xcsi2rxss);
ret = xcsi2rxss_start_stream(xcsi2rxss);
} else {
xcsi2rxss_stop_stream(xcsi2rxss);
xcsi2rxss_hard_reset(xcsi2rxss);
}
stream_done:
mutex_unlock(&xcsi2rxss->lock);
return ret;
}
static struct v4l2_mbus_framefmt *
__xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,
struct v4l2_subdev_state *sd_state,
unsigned int pad, u32 which)
{
switch (which) {
case V4L2_SUBDEV_FORMAT_TRY:
return v4l2_subdev_get_try_format(&xcsi2rxss->subdev,
sd_state, pad);
case V4L2_SUBDEV_FORMAT_ACTIVE:
return &xcsi2rxss->format;
default:
return NULL;
}
}
/**
* xcsi2rxss_init_cfg - Initialise the pad format config to default
* @sd: Pointer to V4L2 Sub device structure
* @sd_state: Pointer to sub device state structure
*
* This function is used to initialize the pad format with the default
* values.
*
* Return: 0 on success
*/
static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
struct v4l2_mbus_framefmt *format;
unsigned int i;
mutex_lock(&xcsi2rxss->lock);
for (i = 0; i < XCSI_MEDIA_PADS; i++) {
format = v4l2_subdev_get_try_format(sd, sd_state, i);
*format = xcsi2rxss->default_format;
}
mutex_unlock(&xcsi2rxss->lock);
return 0;
}
/**
* xcsi2rxss_get_format - Get the pad format
* @sd: Pointer to V4L2 Sub device structure
* @sd_state: Pointer to sub device state structure
* @fmt: Pointer to pad level media bus format
*
* This function is used to get the pad format information.
*
* Return: 0 on success
*/
static int xcsi2rxss_get_format(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
mutex_lock(&xcsi2rxss->lock);
fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
fmt->pad,
fmt->which);
mutex_unlock(&xcsi2rxss->lock);
return 0;
}
/**
* xcsi2rxss_set_format - This is used to set the pad format
* @sd: Pointer to V4L2 Sub device structure
* @sd_state: Pointer to sub device state structure
* @fmt: Pointer to pad level media bus format
*
* This function is used to set the pad format. Since the pad format is fixed
* in hardware, it can't be modified on run time. So when a format set is
* requested by application, all parameters except the format type is saved
* for the pad and the original pad format is sent back to the application.
*
* Return: 0 on success
*/
static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
struct v4l2_mbus_framefmt *__format;
u32 dt;
mutex_lock(&xcsi2rxss->lock);
/*
* Only the format->code parameter matters for CSI as the
* CSI format cannot be changed at runtime.
* Ensure that format to set is copied to over to CSI pad format
*/
__format = __xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
fmt->pad, fmt->which);
/* only sink pad format can be updated */
if (fmt->pad == XVIP_PAD_SOURCE) {
fmt->format = *__format;
mutex_unlock(&xcsi2rxss->lock);
return 0;
}
/*
* RAW8 is supported in all datatypes. So if requested media bus format
* is of RAW8 type, then allow to be set. In case core is configured to
* other RAW, YUV422 8/10 or RGB888, set appropriate media bus format.
*/
dt = xcsi2rxss_get_dt(fmt->format.code);
if (dt != xcsi2rxss->datatype && dt != MIPI_CSI2_DT_RAW8) {
dev_dbg(xcsi2rxss->dev, "Unsupported media bus format");
/* set the default format for the data type */
fmt->format.code = xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype,
0);
}
*__format = fmt->format;
mutex_unlock(&xcsi2rxss->lock);
return 0;
}
/*
* xcsi2rxss_enum_mbus_code - Handle pixel format enumeration
* @sd: pointer to v4l2 subdev structure
* @cfg: V4L2 subdev pad configuration
* @code: pointer to v4l2_subdev_mbus_code_enum structure
*
* Return: -EINVAL or zero on success
*/
static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd);
u32 dt, n;
int ret = 0;
/* RAW8 dt packets are available in all DT configurations */
if (code->index < 4) {
n = code->index;
dt = MIPI_CSI2_DT_RAW8;
} else if (state->datatype != MIPI_CSI2_DT_RAW8) {
n = code->index - 4;
dt = state->datatype;
} else {
return -EINVAL;
}
code->code = xcsi2rxss_get_nth_mbus(dt, n);
if (!code->code)
ret = -EINVAL;
return ret;
}
/* -----------------------------------------------------------------------------
* Media Operations
*/
static const struct media_entity_operations xcsi2rxss_media_ops = {
.link_validate = v4l2_subdev_link_validate
};
static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = {
.log_status = xcsi2rxss_log_status,
};
static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {
.s_stream = xcsi2rxss_s_stream
};
static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {
.init_cfg = xcsi2rxss_init_cfg,
.get_fmt = xcsi2rxss_get_format,
.set_fmt = xcsi2rxss_set_format,
.enum_mbus_code = xcsi2rxss_enum_mbus_code,
.link_validate = v4l2_subdev_link_validate_default,
};
static const struct v4l2_subdev_ops xcsi2rxss_ops = {
.core = &xcsi2rxss_core_ops,
.video = &xcsi2rxss_video_ops,
.pad = &xcsi2rxss_pad_ops
};
static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)
{
struct device *dev = xcsi2rxss->dev;
struct device_node *node = dev->of_node;
struct fwnode_handle *ep;
struct v4l2_fwnode_endpoint vep = {
.bus_type = V4L2_MBUS_CSI2_DPHY
};
bool en_csi_v20, vfb;
int ret;
en_csi_v20 = of_property_read_bool(node, "xlnx,en-csi-v2-0");
if (en_csi_v20)
xcsi2rxss->en_vcx = of_property_read_bool(node, "xlnx,en-vcx");
xcsi2rxss->enable_active_lanes =
of_property_read_bool(node, "xlnx,en-active-lanes");
ret = of_property_read_u32(node, "xlnx,csi-pxl-format",
&xcsi2rxss->datatype);
if (ret < 0) {
dev_err(dev, "missing xlnx,csi-pxl-format property\n");
return ret;
}
switch (xcsi2rxss->datatype) {
case MIPI_CSI2_DT_YUV422_8B:
case MIPI_CSI2_DT_RGB444:
case MIPI_CSI2_DT_RGB555:
case MIPI_CSI2_DT_RGB565:
case MIPI_CSI2_DT_RGB666:
case MIPI_CSI2_DT_RGB888:
case MIPI_CSI2_DT_RAW6:
case MIPI_CSI2_DT_RAW7:
case MIPI_CSI2_DT_RAW8:
case MIPI_CSI2_DT_RAW10:
case MIPI_CSI2_DT_RAW12:
case MIPI_CSI2_DT_RAW14:
break;
case MIPI_CSI2_DT_YUV422_10B:
case MIPI_CSI2_DT_RAW16:
case MIPI_CSI2_DT_RAW20:
if (!en_csi_v20) {
ret = -EINVAL;
dev_dbg(dev, "enable csi v2 for this pixel format");
}
break;
default:
ret = -EINVAL;
}
if (ret < 0) {
dev_err(dev, "invalid csi-pxl-format property!\n");
return ret;
}
vfb = of_property_read_bool(node, "xlnx,vfb");
if (!vfb) {
dev_err(dev, "operation without VFB is not supported\n");
return -EINVAL;
}
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
XVIP_PAD_SINK, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep) {
dev_err(dev, "no sink port found");
return -EINVAL;
}
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
fwnode_handle_put(ep);
if (ret) {
dev_err(dev, "error parsing sink port");
return ret;
}
dev_dbg(dev, "mipi number lanes = %d\n",
vep.bus.mipi_csi2.num_data_lanes);
xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes;
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
XVIP_PAD_SOURCE, 0,
FWNODE_GRAPH_ENDPOINT_NEXT);
if (!ep) {
dev_err(dev, "no source port found");
return -EINVAL;
}
fwnode_handle_put(ep);
dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n",
xcsi2rxss->en_vcx ? "enabled" : "disabled",
xcsi2rxss->max_num_lanes,
xcsi2rxss->enable_active_lanes ? "dynamic" : "static",
xcsi2rxss->datatype);
return 0;
}
static int xcsi2rxss_probe(struct platform_device *pdev)
{
struct v4l2_subdev *subdev;
struct xcsi2rxss_state *xcsi2rxss;
int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
struct device *dev = &pdev->dev;
int irq, ret;
xcsi2rxss = devm_kzalloc(dev, sizeof(*xcsi2rxss), GFP_KERNEL);
if (!xcsi2rxss)
return -ENOMEM;
xcsi2rxss->dev = dev;
xcsi2rxss->clks = devm_kmemdup(dev, xcsi2rxss_clks,
sizeof(xcsi2rxss_clks), GFP_KERNEL);
if (!xcsi2rxss->clks)
return -ENOMEM;
/* Reset GPIO */
xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, "video-reset",
GPIOD_OUT_HIGH);
if (IS_ERR(xcsi2rxss->rst_gpio))
return dev_err_probe(dev, PTR_ERR(xcsi2rxss->rst_gpio),
"Video Reset GPIO not setup in DT\n");
ret = xcsi2rxss_parse_of(xcsi2rxss);
if (ret < 0)
return ret;
xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xcsi2rxss->iomem))
return PTR_ERR(xcsi2rxss->iomem);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_threaded_irq(dev, irq, NULL,
xcsi2rxss_irq_handler, IRQF_ONESHOT,
dev_name(dev), xcsi2rxss);
if (ret) {
dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret);
return ret;
}
ret = clk_bulk_get(dev, num_clks, xcsi2rxss->clks);
if (ret)
return ret;
/* TODO: Enable/disable clocks at stream on/off time. */
ret = clk_bulk_prepare_enable(num_clks, xcsi2rxss->clks);
if (ret)
goto err_clk_put;
mutex_init(&xcsi2rxss->lock);
xcsi2rxss_hard_reset(xcsi2rxss);
xcsi2rxss_soft_reset(xcsi2rxss);
/* Initialize V4L2 subdevice and media entity */
xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
/* Initialize the default format */
xcsi2rxss->default_format.code =
xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 0);
xcsi2rxss->default_format.field = V4L2_FIELD_NONE;
xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB;
xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH;
xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT;
xcsi2rxss->format = xcsi2rxss->default_format;
/* Initialize V4L2 subdevice and media entity */
subdev = &xcsi2rxss->subdev;
v4l2_subdev_init(subdev, &xcsi2rxss_ops);
subdev->dev = dev;
strscpy(subdev->name, dev_name(dev), sizeof(subdev->name));
subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
subdev->entity.ops = &xcsi2rxss_media_ops;
v4l2_set_subdevdata(subdev, xcsi2rxss);
ret = media_entity_pads_init(&subdev->entity, XCSI_MEDIA_PADS,
xcsi2rxss->pads);
if (ret < 0)
goto error;
platform_set_drvdata(pdev, xcsi2rxss);
ret = v4l2_async_register_subdev(subdev);
if (ret < 0) {
dev_err(dev, "failed to register subdev\n");
goto error;
}
return 0;
error:
media_entity_cleanup(&subdev->entity);
mutex_destroy(&xcsi2rxss->lock);
clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
err_clk_put:
clk_bulk_put(num_clks, xcsi2rxss->clks);
return ret;
}
static void xcsi2rxss_remove(struct platform_device *pdev)
{
struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev);
struct v4l2_subdev *subdev = &xcsi2rxss->subdev;
int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
v4l2_async_unregister_subdev(subdev);
media_entity_cleanup(&subdev->entity);
mutex_destroy(&xcsi2rxss->lock);
clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
clk_bulk_put(num_clks, xcsi2rxss->clks);
}
static const struct of_device_id xcsi2rxss_of_id_table[] = {
{ .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", },
{ }
};
MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table);
static struct platform_driver xcsi2rxss_driver = {
.driver = {
.name = "xilinx-csi2rxss",
.of_match_table = xcsi2rxss_of_id_table,
},
.probe = xcsi2rxss_probe,
.remove_new = xcsi2rxss_remove,
};
module_platform_driver(xcsi2rxss_driver);
MODULE_AUTHOR("Vishal Sagar <[email protected]>");
MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/xilinx/xilinx-csi2rxss.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Video DMA
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <[email protected]>
* Laurent Pinchart <[email protected]>
*/
#include <linux/dma/xilinx_dma.h>
#include <linux/lcm.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include "xilinx-dma.h"
#include "xilinx-vip.h"
#include "xilinx-vipp.h"
#define XVIP_DMA_DEF_WIDTH 1920
#define XVIP_DMA_DEF_HEIGHT 1080
/* Minimum and maximum widths are expressed in bytes */
#define XVIP_DMA_MIN_WIDTH 1U
#define XVIP_DMA_MAX_WIDTH 65535U
#define XVIP_DMA_MIN_HEIGHT 1U
#define XVIP_DMA_MAX_HEIGHT 8191U
/* -----------------------------------------------------------------------------
* Helper functions
*/
static struct v4l2_subdev *
xvip_dma_remote_subdev(struct media_pad *local, u32 *pad)
{
struct media_pad *remote;
remote = media_pad_remote_pad_first(local);
if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
return NULL;
if (pad)
*pad = remote->index;
return media_entity_to_v4l2_subdev(remote->entity);
}
static int xvip_dma_verify_format(struct xvip_dma *dma)
{
struct v4l2_subdev_format fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct v4l2_subdev *subdev;
int ret;
subdev = xvip_dma_remote_subdev(&dma->pad, &fmt.pad);
if (subdev == NULL)
return -EPIPE;
ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt);
if (ret < 0)
return ret == -ENOIOCTLCMD ? -EINVAL : ret;
if (dma->fmtinfo->code != fmt.format.code ||
dma->format.height != fmt.format.height ||
dma->format.width != fmt.format.width ||
dma->format.colorspace != fmt.format.colorspace)
return -EINVAL;
return 0;
}
/* -----------------------------------------------------------------------------
* Pipeline Stream Management
*/
/**
* xvip_pipeline_start_stop - Start ot stop streaming on a pipeline
* @pipe: The pipeline
* @start: Start (when true) or stop (when false) the pipeline
*
* Walk the entities chain starting at the pipeline output video node and start
* or stop all of them.
*
* Return: 0 if successful, or the return value of the failed video::s_stream
* operation otherwise.
*/
static int xvip_pipeline_start_stop(struct xvip_pipeline *pipe, bool start)
{
struct xvip_dma *dma = pipe->output;
struct media_entity *entity;
struct media_pad *pad;
struct v4l2_subdev *subdev;
int ret;
entity = &dma->video.entity;
while (1) {
pad = &entity->pads[0];
if (!(pad->flags & MEDIA_PAD_FL_SINK))
break;
pad = media_pad_remote_pad_first(pad);
if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
break;
entity = pad->entity;
subdev = media_entity_to_v4l2_subdev(entity);
ret = v4l2_subdev_call(subdev, video, s_stream, start);
if (start && ret < 0 && ret != -ENOIOCTLCMD)
return ret;
}
return 0;
}
/**
* xvip_pipeline_set_stream - Enable/disable streaming on a pipeline
* @pipe: The pipeline
* @on: Turn the stream on when true or off when false
*
* The pipeline is shared between all DMA engines connect at its input and
* output. While the stream state of DMA engines can be controlled
* independently, pipelines have a shared stream state that enable or disable
* all entities in the pipeline. For this reason the pipeline uses a streaming
* counter that tracks the number of DMA engines that have requested the stream
* to be enabled.
*
* When called with the @on argument set to true, this function will increment
* the pipeline streaming count. If the streaming count reaches the number of
* DMA engines in the pipeline it will enable all entities that belong to the
* pipeline.
*
* Similarly, when called with the @on argument set to false, this function will
* decrement the pipeline streaming count and disable all entities in the
* pipeline when the streaming count reaches zero.
*
* Return: 0 if successful, or the return value of the failed video::s_stream
* operation otherwise. Stopping the pipeline never fails. The pipeline state is
* not updated when the operation fails.
*/
static int xvip_pipeline_set_stream(struct xvip_pipeline *pipe, bool on)
{
int ret = 0;
mutex_lock(&pipe->lock);
if (on) {
if (pipe->stream_count == pipe->num_dmas - 1) {
ret = xvip_pipeline_start_stop(pipe, true);
if (ret < 0)
goto done;
}
pipe->stream_count++;
} else {
if (--pipe->stream_count == 0)
xvip_pipeline_start_stop(pipe, false);
}
done:
mutex_unlock(&pipe->lock);
return ret;
}
static int xvip_pipeline_validate(struct xvip_pipeline *pipe,
struct xvip_dma *start)
{
struct media_pipeline_pad_iter iter;
unsigned int num_inputs = 0;
unsigned int num_outputs = 0;
struct media_pad *pad;
/* Locate the video nodes in the pipeline. */
media_pipeline_for_each_pad(&pipe->pipe, &iter, pad) {
struct xvip_dma *dma;
if (pad->entity->function != MEDIA_ENT_F_IO_V4L)
continue;
dma = to_xvip_dma(media_entity_to_video_device(pad->entity));
if (dma->pad.flags & MEDIA_PAD_FL_SINK) {
pipe->output = dma;
num_outputs++;
} else {
num_inputs++;
}
}
/* We need exactly one output and zero or one input. */
if (num_outputs != 1 || num_inputs > 1)
return -EPIPE;
pipe->num_dmas = num_inputs + num_outputs;
return 0;
}
static void __xvip_pipeline_cleanup(struct xvip_pipeline *pipe)
{
pipe->num_dmas = 0;
pipe->output = NULL;
}
/**
* xvip_pipeline_cleanup - Cleanup the pipeline after streaming
* @pipe: the pipeline
*
* Decrease the pipeline use count and clean it up if we were the last user.
*/
static void xvip_pipeline_cleanup(struct xvip_pipeline *pipe)
{
mutex_lock(&pipe->lock);
/* If we're the last user clean up the pipeline. */
if (--pipe->use_count == 0)
__xvip_pipeline_cleanup(pipe);
mutex_unlock(&pipe->lock);
}
/**
* xvip_pipeline_prepare - Prepare the pipeline for streaming
* @pipe: the pipeline
* @dma: DMA engine at one end of the pipeline
*
* Validate the pipeline if no user exists yet, otherwise just increase the use
* count.
*
* Return: 0 if successful or -EPIPE if the pipeline is not valid.
*/
static int xvip_pipeline_prepare(struct xvip_pipeline *pipe,
struct xvip_dma *dma)
{
int ret;
mutex_lock(&pipe->lock);
/* If we're the first user validate and initialize the pipeline. */
if (pipe->use_count == 0) {
ret = xvip_pipeline_validate(pipe, dma);
if (ret < 0) {
__xvip_pipeline_cleanup(pipe);
goto done;
}
}
pipe->use_count++;
ret = 0;
done:
mutex_unlock(&pipe->lock);
return ret;
}
/* -----------------------------------------------------------------------------
* videobuf2 queue operations
*/
/**
* struct xvip_dma_buffer - Video DMA buffer
* @buf: vb2 buffer base object
* @queue: buffer list entry in the DMA engine queued buffers list
* @dma: DMA channel that uses the buffer
*/
struct xvip_dma_buffer {
struct vb2_v4l2_buffer buf;
struct list_head queue;
struct xvip_dma *dma;
};
#define to_xvip_dma_buffer(vb) container_of(vb, struct xvip_dma_buffer, buf)
static void xvip_dma_complete(void *param)
{
struct xvip_dma_buffer *buf = param;
struct xvip_dma *dma = buf->dma;
spin_lock(&dma->queued_lock);
list_del(&buf->queue);
spin_unlock(&dma->queued_lock);
buf->buf.field = V4L2_FIELD_NONE;
buf->buf.sequence = dma->sequence++;
buf->buf.vb2_buf.timestamp = ktime_get_ns();
vb2_set_plane_payload(&buf->buf.vb2_buf, 0, dma->format.sizeimage);
vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE);
}
static int
xvip_dma_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct xvip_dma *dma = vb2_get_drv_priv(vq);
/* Make sure the image size is large enough. */
if (*nplanes)
return sizes[0] < dma->format.sizeimage ? -EINVAL : 0;
*nplanes = 1;
sizes[0] = dma->format.sizeimage;
return 0;
}
static int xvip_dma_buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct xvip_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
struct xvip_dma_buffer *buf = to_xvip_dma_buffer(vbuf);
buf->dma = dma;
return 0;
}
static void xvip_dma_buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct xvip_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
struct xvip_dma_buffer *buf = to_xvip_dma_buffer(vbuf);
struct dma_async_tx_descriptor *desc;
dma_addr_t addr = vb2_dma_contig_plane_dma_addr(vb, 0);
u32 flags;
if (dma->queue.type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
dma->xt.dir = DMA_DEV_TO_MEM;
dma->xt.src_sgl = false;
dma->xt.dst_sgl = true;
dma->xt.dst_start = addr;
} else {
flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
dma->xt.dir = DMA_MEM_TO_DEV;
dma->xt.src_sgl = true;
dma->xt.dst_sgl = false;
dma->xt.src_start = addr;
}
dma->xt.frame_size = 1;
dma->sgl[0].size = dma->format.width * dma->fmtinfo->bpp;
dma->sgl[0].icg = dma->format.bytesperline - dma->sgl[0].size;
dma->xt.numf = dma->format.height;
desc = dmaengine_prep_interleaved_dma(dma->dma, &dma->xt, flags);
if (!desc) {
dev_err(dma->xdev->dev, "Failed to prepare DMA transfer\n");
vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);
return;
}
desc->callback = xvip_dma_complete;
desc->callback_param = buf;
spin_lock_irq(&dma->queued_lock);
list_add_tail(&buf->queue, &dma->queued_bufs);
spin_unlock_irq(&dma->queued_lock);
dmaengine_submit(desc);
if (vb2_is_streaming(&dma->queue))
dma_async_issue_pending(dma->dma);
}
static int xvip_dma_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct xvip_dma *dma = vb2_get_drv_priv(vq);
struct xvip_dma_buffer *buf, *nbuf;
struct xvip_pipeline *pipe;
int ret;
dma->sequence = 0;
/*
* Start streaming on the pipeline. No link touching an entity in the
* pipeline can be activated or deactivated once streaming is started.
*
* Use the pipeline object embedded in the first DMA object that starts
* streaming.
*/
pipe = to_xvip_pipeline(&dma->video) ? : &dma->pipe;
ret = video_device_pipeline_start(&dma->video, &pipe->pipe);
if (ret < 0)
goto error;
/* Verify that the configured format matches the output of the
* connected subdev.
*/
ret = xvip_dma_verify_format(dma);
if (ret < 0)
goto error_stop;
ret = xvip_pipeline_prepare(pipe, dma);
if (ret < 0)
goto error_stop;
/* Start the DMA engine. This must be done before starting the blocks
* in the pipeline to avoid DMA synchronization issues.
*/
dma_async_issue_pending(dma->dma);
/* Start the pipeline. */
xvip_pipeline_set_stream(pipe, true);
return 0;
error_stop:
video_device_pipeline_stop(&dma->video);
error:
/* Give back all queued buffers to videobuf2. */
spin_lock_irq(&dma->queued_lock);
list_for_each_entry_safe(buf, nbuf, &dma->queued_bufs, queue) {
vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_QUEUED);
list_del(&buf->queue);
}
spin_unlock_irq(&dma->queued_lock);
return ret;
}
static void xvip_dma_stop_streaming(struct vb2_queue *vq)
{
struct xvip_dma *dma = vb2_get_drv_priv(vq);
struct xvip_pipeline *pipe = to_xvip_pipeline(&dma->video);
struct xvip_dma_buffer *buf, *nbuf;
/* Stop the pipeline. */
xvip_pipeline_set_stream(pipe, false);
/* Stop and reset the DMA engine. */
dmaengine_terminate_all(dma->dma);
/* Cleanup the pipeline and mark it as being stopped. */
xvip_pipeline_cleanup(pipe);
video_device_pipeline_stop(&dma->video);
/* Give back all queued buffers to videobuf2. */
spin_lock_irq(&dma->queued_lock);
list_for_each_entry_safe(buf, nbuf, &dma->queued_bufs, queue) {
vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);
list_del(&buf->queue);
}
spin_unlock_irq(&dma->queued_lock);
}
static const struct vb2_ops xvip_dma_queue_qops = {
.queue_setup = xvip_dma_queue_setup,
.buf_prepare = xvip_dma_buffer_prepare,
.buf_queue = xvip_dma_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = xvip_dma_start_streaming,
.stop_streaming = xvip_dma_stop_streaming,
};
/* -----------------------------------------------------------------------------
* V4L2 ioctls
*/
static int
xvip_dma_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
{
struct v4l2_fh *vfh = file->private_data;
struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
cap->capabilities = dma->xdev->v4l2_caps | V4L2_CAP_STREAMING |
V4L2_CAP_DEVICE_CAPS;
strscpy(cap->driver, "xilinx-vipp", sizeof(cap->driver));
strscpy(cap->card, dma->video.name, sizeof(cap->card));
snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%pOFn:%u",
dma->xdev->dev->of_node, dma->port);
return 0;
}
/* FIXME: without this callback function, some applications are not configured
* with correct formats, and it results in frames in wrong format. Whether this
* callback needs to be required is not clearly defined, so it should be
* clarified through the mailing list.
*/
static int
xvip_dma_enum_format(struct file *file, void *fh, struct v4l2_fmtdesc *f)
{
struct v4l2_fh *vfh = file->private_data;
struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
if (f->index > 0)
return -EINVAL;
f->pixelformat = dma->format.pixelformat;
return 0;
}
static int
xvip_dma_get_format(struct file *file, void *fh, struct v4l2_format *format)
{
struct v4l2_fh *vfh = file->private_data;
struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
format->fmt.pix = dma->format;
return 0;
}
static void
__xvip_dma_try_format(struct xvip_dma *dma, struct v4l2_pix_format *pix,
const struct xvip_video_format **fmtinfo)
{
const struct xvip_video_format *info;
unsigned int min_width;
unsigned int max_width;
unsigned int min_bpl;
unsigned int max_bpl;
unsigned int width;
unsigned int align;
unsigned int bpl;
/* Retrieve format information and select the default format if the
* requested format isn't supported.
*/
info = xvip_get_format_by_fourcc(pix->pixelformat);
pix->pixelformat = info->fourcc;
pix->field = V4L2_FIELD_NONE;
/* The transfer alignment requirements are expressed in bytes. Compute
* the minimum and maximum values, clamp the requested width and convert
* it back to pixels.
*/
align = lcm(dma->align, info->bpp);
min_width = roundup(XVIP_DMA_MIN_WIDTH, align);
max_width = rounddown(XVIP_DMA_MAX_WIDTH, align);
width = rounddown(pix->width * info->bpp, align);
pix->width = clamp(width, min_width, max_width) / info->bpp;
pix->height = clamp(pix->height, XVIP_DMA_MIN_HEIGHT,
XVIP_DMA_MAX_HEIGHT);
/* Clamp the requested bytes per line value. If the maximum bytes per
* line value is zero, the module doesn't support user configurable line
* sizes. Override the requested value with the minimum in that case.
*/
min_bpl = pix->width * info->bpp;
max_bpl = rounddown(XVIP_DMA_MAX_WIDTH, dma->align);
bpl = rounddown(pix->bytesperline, dma->align);
pix->bytesperline = clamp(bpl, min_bpl, max_bpl);
pix->sizeimage = pix->bytesperline * pix->height;
if (fmtinfo)
*fmtinfo = info;
}
static int
xvip_dma_try_format(struct file *file, void *fh, struct v4l2_format *format)
{
struct v4l2_fh *vfh = file->private_data;
struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
__xvip_dma_try_format(dma, &format->fmt.pix, NULL);
return 0;
}
static int
xvip_dma_set_format(struct file *file, void *fh, struct v4l2_format *format)
{
struct v4l2_fh *vfh = file->private_data;
struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
const struct xvip_video_format *info;
__xvip_dma_try_format(dma, &format->fmt.pix, &info);
if (vb2_is_busy(&dma->queue))
return -EBUSY;
dma->format = format->fmt.pix;
dma->fmtinfo = info;
return 0;
}
static const struct v4l2_ioctl_ops xvip_dma_ioctl_ops = {
.vidioc_querycap = xvip_dma_querycap,
.vidioc_enum_fmt_vid_cap = xvip_dma_enum_format,
.vidioc_g_fmt_vid_cap = xvip_dma_get_format,
.vidioc_g_fmt_vid_out = xvip_dma_get_format,
.vidioc_s_fmt_vid_cap = xvip_dma_set_format,
.vidioc_s_fmt_vid_out = xvip_dma_set_format,
.vidioc_try_fmt_vid_cap = xvip_dma_try_format,
.vidioc_try_fmt_vid_out = xvip_dma_try_format,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
};
/* -----------------------------------------------------------------------------
* V4L2 file operations
*/
static const struct v4l2_file_operations xvip_dma_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = video_ioctl2,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
};
/* -----------------------------------------------------------------------------
* Xilinx Video DMA Core
*/
int xvip_dma_init(struct xvip_composite_device *xdev, struct xvip_dma *dma,
enum v4l2_buf_type type, unsigned int port)
{
char name[16];
int ret;
dma->xdev = xdev;
dma->port = port;
mutex_init(&dma->lock);
mutex_init(&dma->pipe.lock);
INIT_LIST_HEAD(&dma->queued_bufs);
spin_lock_init(&dma->queued_lock);
dma->fmtinfo = xvip_get_format_by_fourcc(V4L2_PIX_FMT_YUYV);
dma->format.pixelformat = dma->fmtinfo->fourcc;
dma->format.colorspace = V4L2_COLORSPACE_SRGB;
dma->format.field = V4L2_FIELD_NONE;
dma->format.width = XVIP_DMA_DEF_WIDTH;
dma->format.height = XVIP_DMA_DEF_HEIGHT;
dma->format.bytesperline = dma->format.width * dma->fmtinfo->bpp;
dma->format.sizeimage = dma->format.bytesperline * dma->format.height;
/* Initialize the media entity... */
dma->pad.flags = type == V4L2_BUF_TYPE_VIDEO_CAPTURE
? MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&dma->video.entity, 1, &dma->pad);
if (ret < 0)
goto error;
/* ... and the video node... */
dma->video.fops = &xvip_dma_fops;
dma->video.v4l2_dev = &xdev->v4l2_dev;
dma->video.queue = &dma->queue;
snprintf(dma->video.name, sizeof(dma->video.name), "%pOFn %s %u",
xdev->dev->of_node,
type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? "output" : "input",
port);
dma->video.vfl_type = VFL_TYPE_VIDEO;
dma->video.vfl_dir = type == V4L2_BUF_TYPE_VIDEO_CAPTURE
? VFL_DIR_RX : VFL_DIR_TX;
dma->video.release = video_device_release_empty;
dma->video.ioctl_ops = &xvip_dma_ioctl_ops;
dma->video.lock = &dma->lock;
dma->video.device_caps = V4L2_CAP_STREAMING;
if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
dma->video.device_caps |= V4L2_CAP_VIDEO_CAPTURE;
else
dma->video.device_caps |= V4L2_CAP_VIDEO_OUTPUT;
video_set_drvdata(&dma->video, dma);
/* ... and the buffers queue... */
/* Don't enable VB2_READ and VB2_WRITE, as using the read() and write()
* V4L2 APIs would be inefficient. Testing on the command line with a
* 'cat /dev/video?' thus won't be possible, but given that the driver
* anyway requires a test tool to setup the pipeline before any video
* stream can be started, requiring a specific V4L2 test tool as well
* instead of 'cat' isn't really a drawback.
*/
dma->queue.type = type;
dma->queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
dma->queue.lock = &dma->lock;
dma->queue.drv_priv = dma;
dma->queue.buf_struct_size = sizeof(struct xvip_dma_buffer);
dma->queue.ops = &xvip_dma_queue_qops;
dma->queue.mem_ops = &vb2_dma_contig_memops;
dma->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC
| V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
dma->queue.dev = dma->xdev->dev;
ret = vb2_queue_init(&dma->queue);
if (ret < 0) {
dev_err(dma->xdev->dev, "failed to initialize VB2 queue\n");
goto error;
}
/* ... and the DMA channel. */
snprintf(name, sizeof(name), "port%u", port);
dma->dma = dma_request_chan(dma->xdev->dev, name);
if (IS_ERR(dma->dma)) {
ret = PTR_ERR(dma->dma);
if (ret != -EPROBE_DEFER)
dev_err(dma->xdev->dev, "no VDMA channel found\n");
goto error;
}
dma->align = 1 << dma->dma->device->copy_align;
ret = video_register_device(&dma->video, VFL_TYPE_VIDEO, -1);
if (ret < 0) {
dev_err(dma->xdev->dev, "failed to register video device\n");
goto error;
}
return 0;
error:
xvip_dma_cleanup(dma);
return ret;
}
void xvip_dma_cleanup(struct xvip_dma *dma)
{
if (video_is_registered(&dma->video))
video_unregister_device(&dma->video);
if (!IS_ERR_OR_NULL(dma->dma))
dma_release_channel(dma->dma);
media_entity_cleanup(&dma->video.entity);
mutex_destroy(&dma->lock);
mutex_destroy(&dma->pipe.lock);
}
| linux-master | drivers/media/platform/xilinx/xilinx-dma.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Test Pattern Generator
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <[email protected]>
* Laurent Pinchart <[email protected]>
*/
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/xilinx-v4l2-controls.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include "xilinx-vip.h"
#include "xilinx-vtc.h"
#define XTPG_CTRL_STATUS_SLAVE_ERROR (1 << 16)
#define XTPG_CTRL_IRQ_SLAVE_ERROR (1 << 16)
#define XTPG_PATTERN_CONTROL 0x0100
#define XTPG_PATTERN_MASK (0xf << 0)
#define XTPG_PATTERN_CONTROL_CROSS_HAIRS (1 << 4)
#define XTPG_PATTERN_CONTROL_MOVING_BOX (1 << 5)
#define XTPG_PATTERN_CONTROL_COLOR_MASK_SHIFT 6
#define XTPG_PATTERN_CONTROL_COLOR_MASK_MASK (0xf << 6)
#define XTPG_PATTERN_CONTROL_STUCK_PIXEL (1 << 9)
#define XTPG_PATTERN_CONTROL_NOISE (1 << 10)
#define XTPG_PATTERN_CONTROL_MOTION (1 << 12)
#define XTPG_MOTION_SPEED 0x0104
#define XTPG_CROSS_HAIRS 0x0108
#define XTPG_CROSS_HAIRS_ROW_SHIFT 0
#define XTPG_CROSS_HAIRS_ROW_MASK (0xfff << 0)
#define XTPG_CROSS_HAIRS_COLUMN_SHIFT 16
#define XTPG_CROSS_HAIRS_COLUMN_MASK (0xfff << 16)
#define XTPG_ZPLATE_HOR_CONTROL 0x010c
#define XTPG_ZPLATE_VER_CONTROL 0x0110
#define XTPG_ZPLATE_START_SHIFT 0
#define XTPG_ZPLATE_START_MASK (0xffff << 0)
#define XTPG_ZPLATE_SPEED_SHIFT 16
#define XTPG_ZPLATE_SPEED_MASK (0xffff << 16)
#define XTPG_BOX_SIZE 0x0114
#define XTPG_BOX_COLOR 0x0118
#define XTPG_STUCK_PIXEL_THRESH 0x011c
#define XTPG_NOISE_GAIN 0x0120
#define XTPG_BAYER_PHASE 0x0124
#define XTPG_BAYER_PHASE_RGGB 0
#define XTPG_BAYER_PHASE_GRBG 1
#define XTPG_BAYER_PHASE_GBRG 2
#define XTPG_BAYER_PHASE_BGGR 3
#define XTPG_BAYER_PHASE_OFF 4
/*
* The minimum blanking value is one clock cycle for the front porch, one clock
* cycle for the sync pulse and one clock cycle for the back porch.
*/
#define XTPG_MIN_HBLANK 3
#define XTPG_MAX_HBLANK (XVTC_MAX_HSIZE - XVIP_MIN_WIDTH)
#define XTPG_MIN_VBLANK 3
#define XTPG_MAX_VBLANK (XVTC_MAX_VSIZE - XVIP_MIN_HEIGHT)
/**
* struct xtpg_device - Xilinx Test Pattern Generator device structure
* @xvip: Xilinx Video IP device
* @pads: media pads
* @npads: number of pads (1 or 2)
* @has_input: whether an input is connected to the sink pad
* @formats: active V4L2 media bus format for each pad
* @default_format: default V4L2 media bus format
* @vip_format: format information corresponding to the active format
* @bayer: boolean flag if TPG is set to any bayer format
* @ctrl_handler: control handler
* @hblank: horizontal blanking control
* @vblank: vertical blanking control
* @pattern: test pattern control
* @streaming: is the video stream active
* @vtc: video timing controller
* @vtmux_gpio: video timing mux GPIO
*/
struct xtpg_device {
struct xvip_device xvip;
struct media_pad pads[2];
unsigned int npads;
bool has_input;
struct v4l2_mbus_framefmt formats[2];
struct v4l2_mbus_framefmt default_format;
const struct xvip_video_format *vip_format;
bool bayer;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *hblank;
struct v4l2_ctrl *vblank;
struct v4l2_ctrl *pattern;
bool streaming;
struct xvtc_device *vtc;
struct gpio_desc *vtmux_gpio;
};
static inline struct xtpg_device *to_tpg(struct v4l2_subdev *subdev)
{
return container_of(subdev, struct xtpg_device, xvip.subdev);
}
static u32 xtpg_get_bayer_phase(unsigned int code)
{
switch (code) {
case MEDIA_BUS_FMT_SRGGB8_1X8:
return XTPG_BAYER_PHASE_RGGB;
case MEDIA_BUS_FMT_SGRBG8_1X8:
return XTPG_BAYER_PHASE_GRBG;
case MEDIA_BUS_FMT_SGBRG8_1X8:
return XTPG_BAYER_PHASE_GBRG;
case MEDIA_BUS_FMT_SBGGR8_1X8:
return XTPG_BAYER_PHASE_BGGR;
default:
return XTPG_BAYER_PHASE_OFF;
}
}
static void __xtpg_update_pattern_control(struct xtpg_device *xtpg,
bool passthrough, bool pattern)
{
u32 pattern_mask = (1 << (xtpg->pattern->maximum + 1)) - 1;
/*
* If the TPG has no sink pad or no input connected to its sink pad
* passthrough mode can't be enabled.
*/
if (xtpg->npads == 1 || !xtpg->has_input)
passthrough = false;
/* If passthrough mode is allowed unmask bit 0. */
if (passthrough)
pattern_mask &= ~1;
/* If test pattern mode is allowed unmask all other bits. */
if (pattern)
pattern_mask &= 1;
__v4l2_ctrl_modify_range(xtpg->pattern, 0, xtpg->pattern->maximum,
pattern_mask, pattern ? 9 : 0);
}
static void xtpg_update_pattern_control(struct xtpg_device *xtpg,
bool passthrough, bool pattern)
{
mutex_lock(xtpg->ctrl_handler.lock);
__xtpg_update_pattern_control(xtpg, passthrough, pattern);
mutex_unlock(xtpg->ctrl_handler.lock);
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Video Operations
*/
static int xtpg_s_stream(struct v4l2_subdev *subdev, int enable)
{
struct xtpg_device *xtpg = to_tpg(subdev);
unsigned int width = xtpg->formats[0].width;
unsigned int height = xtpg->formats[0].height;
bool passthrough;
u32 bayer_phase;
if (!enable) {
xvip_stop(&xtpg->xvip);
if (xtpg->vtc)
xvtc_generator_stop(xtpg->vtc);
xtpg_update_pattern_control(xtpg, true, true);
xtpg->streaming = false;
return 0;
}
xvip_set_frame_size(&xtpg->xvip, &xtpg->formats[0]);
if (xtpg->vtc) {
struct xvtc_config config = {
.hblank_start = width,
.hsync_start = width + 1,
.vblank_start = height,
.vsync_start = height + 1,
};
unsigned int htotal;
unsigned int vtotal;
htotal = min_t(unsigned int, XVTC_MAX_HSIZE,
v4l2_ctrl_g_ctrl(xtpg->hblank) + width);
vtotal = min_t(unsigned int, XVTC_MAX_VSIZE,
v4l2_ctrl_g_ctrl(xtpg->vblank) + height);
config.hsync_end = htotal - 1;
config.hsize = htotal;
config.vsync_end = vtotal - 1;
config.vsize = vtotal;
xvtc_generator_start(xtpg->vtc, &config);
}
/*
* Configure the bayer phase and video timing mux based on the
* operation mode (passthrough or test pattern generation). The test
* pattern can be modified by the control set handler, we thus need to
* take the control lock here to avoid races.
*/
mutex_lock(xtpg->ctrl_handler.lock);
xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_MASK, xtpg->pattern->cur.val);
/*
* Switching between passthrough and test pattern generation modes isn't
* allowed during streaming, update the control range accordingly.
*/
passthrough = xtpg->pattern->cur.val == 0;
__xtpg_update_pattern_control(xtpg, passthrough, !passthrough);
xtpg->streaming = true;
mutex_unlock(xtpg->ctrl_handler.lock);
/*
* For TPG v5.0, the bayer phase needs to be off for the pass through
* mode, otherwise the external input would be subsampled.
*/
bayer_phase = passthrough ? XTPG_BAYER_PHASE_OFF
: xtpg_get_bayer_phase(xtpg->formats[0].code);
xvip_write(&xtpg->xvip, XTPG_BAYER_PHASE, bayer_phase);
if (xtpg->vtmux_gpio)
gpiod_set_value_cansleep(xtpg->vtmux_gpio, !passthrough);
xvip_start(&xtpg->xvip);
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Pad Operations
*/
static struct v4l2_mbus_framefmt *
__xtpg_get_pad_format(struct xtpg_device *xtpg,
struct v4l2_subdev_state *sd_state,
unsigned int pad, u32 which)
{
switch (which) {
case V4L2_SUBDEV_FORMAT_TRY:
return v4l2_subdev_get_try_format(&xtpg->xvip.subdev,
sd_state, pad);
case V4L2_SUBDEV_FORMAT_ACTIVE:
return &xtpg->formats[pad];
default:
return NULL;
}
}
static int xtpg_get_format(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct xtpg_device *xtpg = to_tpg(subdev);
fmt->format = *__xtpg_get_pad_format(xtpg, sd_state, fmt->pad,
fmt->which);
return 0;
}
static int xtpg_set_format(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct xtpg_device *xtpg = to_tpg(subdev);
struct v4l2_mbus_framefmt *__format;
u32 bayer_phase;
__format = __xtpg_get_pad_format(xtpg, sd_state, fmt->pad, fmt->which);
/* In two pads mode the source pad format is always identical to the
* sink pad format.
*/
if (xtpg->npads == 2 && fmt->pad == 1) {
fmt->format = *__format;
return 0;
}
/* Bayer phase is configurable at runtime */
if (xtpg->bayer) {
bayer_phase = xtpg_get_bayer_phase(fmt->format.code);
if (bayer_phase != XTPG_BAYER_PHASE_OFF)
__format->code = fmt->format.code;
}
xvip_set_format_size(__format, fmt);
fmt->format = *__format;
/* Propagate the format to the source pad. */
if (xtpg->npads == 2) {
__format = __xtpg_get_pad_format(xtpg, sd_state, 1,
fmt->which);
*__format = fmt->format;
}
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Operations
*/
static int xtpg_enum_frame_size(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
struct v4l2_mbus_framefmt *format;
format = v4l2_subdev_get_try_format(subdev, sd_state, fse->pad);
if (fse->index || fse->code != format->code)
return -EINVAL;
/* Min / max values for pad 0 is always fixed in both one and two pads
* modes. In two pads mode, the source pad(= 1) size is identical to
* the sink pad size */
if (fse->pad == 0) {
fse->min_width = XVIP_MIN_WIDTH;
fse->max_width = XVIP_MAX_WIDTH;
fse->min_height = XVIP_MIN_HEIGHT;
fse->max_height = XVIP_MAX_HEIGHT;
} else {
fse->min_width = format->width;
fse->max_width = format->width;
fse->min_height = format->height;
fse->max_height = format->height;
}
return 0;
}
static int xtpg_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
struct xtpg_device *xtpg = to_tpg(subdev);
struct v4l2_mbus_framefmt *format;
format = v4l2_subdev_get_try_format(subdev, fh->state, 0);
*format = xtpg->default_format;
if (xtpg->npads == 2) {
format = v4l2_subdev_get_try_format(subdev, fh->state, 1);
*format = xtpg->default_format;
}
return 0;
}
static int xtpg_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
return 0;
}
static int xtpg_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct xtpg_device *xtpg = container_of(ctrl->handler,
struct xtpg_device,
ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_TEST_PATTERN:
xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_MASK, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_CROSS_HAIRS:
xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_CROSS_HAIRS, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_MOVING_BOX:
xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_MOVING_BOX, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_COLOR_MASK:
xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_COLOR_MASK_MASK,
ctrl->val <<
XTPG_PATTERN_CONTROL_COLOR_MASK_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_STUCK_PIXEL:
xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_STUCK_PIXEL, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_NOISE:
xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_NOISE, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_MOTION:
xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
XTPG_PATTERN_CONTROL_MOTION, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_MOTION_SPEED:
xvip_write(&xtpg->xvip, XTPG_MOTION_SPEED, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW:
xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
XTPG_CROSS_HAIRS_ROW_MASK,
ctrl->val << XTPG_CROSS_HAIRS_ROW_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN:
xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
XTPG_CROSS_HAIRS_COLUMN_MASK,
ctrl->val << XTPG_CROSS_HAIRS_COLUMN_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_ZPLATE_HOR_START:
xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
XTPG_ZPLATE_START_MASK,
ctrl->val << XTPG_ZPLATE_START_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED:
xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
XTPG_ZPLATE_SPEED_MASK,
ctrl->val << XTPG_ZPLATE_SPEED_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_ZPLATE_VER_START:
xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
XTPG_ZPLATE_START_MASK,
ctrl->val << XTPG_ZPLATE_START_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED:
xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
XTPG_ZPLATE_SPEED_MASK,
ctrl->val << XTPG_ZPLATE_SPEED_SHIFT);
return 0;
case V4L2_CID_XILINX_TPG_BOX_SIZE:
xvip_write(&xtpg->xvip, XTPG_BOX_SIZE, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_BOX_COLOR:
xvip_write(&xtpg->xvip, XTPG_BOX_COLOR, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH:
xvip_write(&xtpg->xvip, XTPG_STUCK_PIXEL_THRESH, ctrl->val);
return 0;
case V4L2_CID_XILINX_TPG_NOISE_GAIN:
xvip_write(&xtpg->xvip, XTPG_NOISE_GAIN, ctrl->val);
return 0;
}
return 0;
}
static const struct v4l2_ctrl_ops xtpg_ctrl_ops = {
.s_ctrl = xtpg_s_ctrl,
};
static const struct v4l2_subdev_core_ops xtpg_core_ops = {
};
static const struct v4l2_subdev_video_ops xtpg_video_ops = {
.s_stream = xtpg_s_stream,
};
static const struct v4l2_subdev_pad_ops xtpg_pad_ops = {
.enum_mbus_code = xvip_enum_mbus_code,
.enum_frame_size = xtpg_enum_frame_size,
.get_fmt = xtpg_get_format,
.set_fmt = xtpg_set_format,
};
static const struct v4l2_subdev_ops xtpg_ops = {
.core = &xtpg_core_ops,
.video = &xtpg_video_ops,
.pad = &xtpg_pad_ops,
};
static const struct v4l2_subdev_internal_ops xtpg_internal_ops = {
.open = xtpg_open,
.close = xtpg_close,
};
/*
* Control Config
*/
static const char *const xtpg_pattern_strings[] = {
"Passthrough",
"Horizontal Ramp",
"Vertical Ramp",
"Temporal Ramp",
"Solid Red",
"Solid Green",
"Solid Blue",
"Solid Black",
"Solid White",
"Color Bars",
"Zone Plate",
"Tartan Color Bars",
"Cross Hatch",
"None",
"Vertical/Horizontal Ramps",
"Black/White Checker Board",
};
static struct v4l2_ctrl_config xtpg_ctrls[] = {
{
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_CROSS_HAIRS,
.name = "Test Pattern: Cross Hairs",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = false,
.max = true,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_MOVING_BOX,
.name = "Test Pattern: Moving Box",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = false,
.max = true,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_COLOR_MASK,
.name = "Test Pattern: Color Mask",
.type = V4L2_CTRL_TYPE_BITMASK,
.min = 0,
.max = 0xf,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_STUCK_PIXEL,
.name = "Test Pattern: Stuck Pixel",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = false,
.max = true,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_NOISE,
.name = "Test Pattern: Noise",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = false,
.max = true,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_MOTION,
.name = "Test Pattern: Motion",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = false,
.max = true,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_MOTION_SPEED,
.name = "Test Pattern: Motion Speed",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 8) - 1,
.step = 1,
.def = 4,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW,
.name = "Test Pattern: Cross Hairs Row",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 12) - 1,
.step = 1,
.def = 0x64,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN,
.name = "Test Pattern: Cross Hairs Column",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 12) - 1,
.step = 1,
.def = 0x64,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_ZPLATE_HOR_START,
.name = "Test Pattern: Zplate Horizontal Start Pos",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 16) - 1,
.step = 1,
.def = 0x1e,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED,
.name = "Test Pattern: Zplate Horizontal Speed",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 16) - 1,
.step = 1,
.def = 0,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_ZPLATE_VER_START,
.name = "Test Pattern: Zplate Vertical Start Pos",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 16) - 1,
.step = 1,
.def = 1,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED,
.name = "Test Pattern: Zplate Vertical Speed",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 16) - 1,
.step = 1,
.def = 0,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_BOX_SIZE,
.name = "Test Pattern: Box Size",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 12) - 1,
.step = 1,
.def = 0x32,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_BOX_COLOR,
.name = "Test Pattern: Box Color(RGB)",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 24) - 1,
.step = 1,
.def = 0,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH,
.name = "Test Pattern: Stuck Pixel threshold",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 16) - 1,
.step = 1,
.def = 0,
.flags = V4L2_CTRL_FLAG_SLIDER,
}, {
.ops = &xtpg_ctrl_ops,
.id = V4L2_CID_XILINX_TPG_NOISE_GAIN,
.name = "Test Pattern: Noise Gain",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = (1 << 8) - 1,
.step = 1,
.def = 0,
.flags = V4L2_CTRL_FLAG_SLIDER,
},
};
/* -----------------------------------------------------------------------------
* Media Operations
*/
static const struct media_entity_operations xtpg_media_ops = {
.link_validate = v4l2_subdev_link_validate,
};
/* -----------------------------------------------------------------------------
* Power Management
*/
static int __maybe_unused xtpg_pm_suspend(struct device *dev)
{
struct xtpg_device *xtpg = dev_get_drvdata(dev);
xvip_suspend(&xtpg->xvip);
return 0;
}
static int __maybe_unused xtpg_pm_resume(struct device *dev)
{
struct xtpg_device *xtpg = dev_get_drvdata(dev);
xvip_resume(&xtpg->xvip);
return 0;
}
/* -----------------------------------------------------------------------------
* Platform Device Driver
*/
static int xtpg_parse_of(struct xtpg_device *xtpg)
{
struct device *dev = xtpg->xvip.dev;
struct device_node *node = xtpg->xvip.dev->of_node;
struct device_node *ports;
struct device_node *port;
unsigned int nports = 0;
bool has_endpoint = false;
ports = of_get_child_by_name(node, "ports");
if (ports == NULL)
ports = node;
for_each_child_of_node(ports, port) {
const struct xvip_video_format *format;
struct device_node *endpoint;
if (!of_node_name_eq(port, "port"))
continue;
format = xvip_of_get_format(port);
if (IS_ERR(format)) {
dev_err(dev, "invalid format in DT");
of_node_put(port);
return PTR_ERR(format);
}
/* Get and check the format description */
if (!xtpg->vip_format) {
xtpg->vip_format = format;
} else if (xtpg->vip_format != format) {
dev_err(dev, "in/out format mismatch in DT");
of_node_put(port);
return -EINVAL;
}
if (nports == 0) {
endpoint = of_get_next_child(port, NULL);
if (endpoint)
has_endpoint = true;
of_node_put(endpoint);
}
/* Count the number of ports. */
nports++;
}
if (nports != 1 && nports != 2) {
dev_err(dev, "invalid number of ports %u\n", nports);
return -EINVAL;
}
xtpg->npads = nports;
if (nports == 2 && has_endpoint)
xtpg->has_input = true;
return 0;
}
static int xtpg_probe(struct platform_device *pdev)
{
struct v4l2_subdev *subdev;
struct xtpg_device *xtpg;
u32 i, bayer_phase;
int ret;
xtpg = devm_kzalloc(&pdev->dev, sizeof(*xtpg), GFP_KERNEL);
if (!xtpg)
return -ENOMEM;
xtpg->xvip.dev = &pdev->dev;
ret = xtpg_parse_of(xtpg);
if (ret < 0)
return ret;
ret = xvip_init_resources(&xtpg->xvip);
if (ret < 0)
return ret;
xtpg->vtmux_gpio = devm_gpiod_get_optional(&pdev->dev, "timing",
GPIOD_OUT_HIGH);
if (IS_ERR(xtpg->vtmux_gpio)) {
ret = PTR_ERR(xtpg->vtmux_gpio);
goto error_resource;
}
xtpg->vtc = xvtc_of_get(pdev->dev.of_node);
if (IS_ERR(xtpg->vtc)) {
ret = PTR_ERR(xtpg->vtc);
goto error_resource;
}
/* Reset and initialize the core */
xvip_reset(&xtpg->xvip);
/* Initialize V4L2 subdevice and media entity. Pad numbers depend on the
* number of pads.
*/
if (xtpg->npads == 2) {
xtpg->pads[0].flags = MEDIA_PAD_FL_SINK;
xtpg->pads[1].flags = MEDIA_PAD_FL_SOURCE;
} else {
xtpg->pads[0].flags = MEDIA_PAD_FL_SOURCE;
}
/* Initialize the default format */
xtpg->default_format.code = xtpg->vip_format->code;
xtpg->default_format.field = V4L2_FIELD_NONE;
xtpg->default_format.colorspace = V4L2_COLORSPACE_SRGB;
xvip_get_frame_size(&xtpg->xvip, &xtpg->default_format);
bayer_phase = xtpg_get_bayer_phase(xtpg->vip_format->code);
if (bayer_phase != XTPG_BAYER_PHASE_OFF)
xtpg->bayer = true;
xtpg->formats[0] = xtpg->default_format;
if (xtpg->npads == 2)
xtpg->formats[1] = xtpg->default_format;
/* Initialize V4L2 subdevice and media entity */
subdev = &xtpg->xvip.subdev;
v4l2_subdev_init(subdev, &xtpg_ops);
subdev->dev = &pdev->dev;
subdev->internal_ops = &xtpg_internal_ops;
strscpy(subdev->name, dev_name(&pdev->dev), sizeof(subdev->name));
v4l2_set_subdevdata(subdev, xtpg);
subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
subdev->entity.ops = &xtpg_media_ops;
ret = media_entity_pads_init(&subdev->entity, xtpg->npads, xtpg->pads);
if (ret < 0)
goto error;
v4l2_ctrl_handler_init(&xtpg->ctrl_handler, 3 + ARRAY_SIZE(xtpg_ctrls));
xtpg->vblank = v4l2_ctrl_new_std(&xtpg->ctrl_handler, &xtpg_ctrl_ops,
V4L2_CID_VBLANK, XTPG_MIN_VBLANK,
XTPG_MAX_VBLANK, 1, 100);
xtpg->hblank = v4l2_ctrl_new_std(&xtpg->ctrl_handler, &xtpg_ctrl_ops,
V4L2_CID_HBLANK, XTPG_MIN_HBLANK,
XTPG_MAX_HBLANK, 1, 100);
xtpg->pattern = v4l2_ctrl_new_std_menu_items(&xtpg->ctrl_handler,
&xtpg_ctrl_ops, V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(xtpg_pattern_strings) - 1,
1, 9, xtpg_pattern_strings);
for (i = 0; i < ARRAY_SIZE(xtpg_ctrls); i++)
v4l2_ctrl_new_custom(&xtpg->ctrl_handler, &xtpg_ctrls[i], NULL);
if (xtpg->ctrl_handler.error) {
dev_err(&pdev->dev, "failed to add controls\n");
ret = xtpg->ctrl_handler.error;
goto error;
}
subdev->ctrl_handler = &xtpg->ctrl_handler;
xtpg_update_pattern_control(xtpg, true, true);
ret = v4l2_ctrl_handler_setup(&xtpg->ctrl_handler);
if (ret < 0) {
dev_err(&pdev->dev, "failed to set controls\n");
goto error;
}
platform_set_drvdata(pdev, xtpg);
xvip_print_version(&xtpg->xvip);
ret = v4l2_async_register_subdev(subdev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register subdev\n");
goto error;
}
return 0;
error:
v4l2_ctrl_handler_free(&xtpg->ctrl_handler);
media_entity_cleanup(&subdev->entity);
xvtc_put(xtpg->vtc);
error_resource:
xvip_cleanup_resources(&xtpg->xvip);
return ret;
}
static void xtpg_remove(struct platform_device *pdev)
{
struct xtpg_device *xtpg = platform_get_drvdata(pdev);
struct v4l2_subdev *subdev = &xtpg->xvip.subdev;
v4l2_async_unregister_subdev(subdev);
v4l2_ctrl_handler_free(&xtpg->ctrl_handler);
media_entity_cleanup(&subdev->entity);
xvip_cleanup_resources(&xtpg->xvip);
}
static SIMPLE_DEV_PM_OPS(xtpg_pm_ops, xtpg_pm_suspend, xtpg_pm_resume);
static const struct of_device_id xtpg_of_id_table[] = {
{ .compatible = "xlnx,v-tpg-5.0" },
{ }
};
MODULE_DEVICE_TABLE(of, xtpg_of_id_table);
static struct platform_driver xtpg_driver = {
.driver = {
.name = "xilinx-tpg",
.pm = &xtpg_pm_ops,
.of_match_table = xtpg_of_id_table,
},
.probe = xtpg_probe,
.remove_new = xtpg_remove,
};
module_platform_driver(xtpg_driver);
MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
MODULE_DESCRIPTION("Xilinx Test Pattern Generator Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/xilinx/xilinx-tpg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Video Timing Controller
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <[email protected]>
* Laurent Pinchart <[email protected]>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "xilinx-vip.h"
#include "xilinx-vtc.h"
#define XVTC_CONTROL_FIELD_ID_POL_SRC (1 << 26)
#define XVTC_CONTROL_ACTIVE_CHROMA_POL_SRC (1 << 25)
#define XVTC_CONTROL_ACTIVE_VIDEO_POL_SRC (1 << 24)
#define XVTC_CONTROL_HSYNC_POL_SRC (1 << 23)
#define XVTC_CONTROL_VSYNC_POL_SRC (1 << 22)
#define XVTC_CONTROL_HBLANK_POL_SRC (1 << 21)
#define XVTC_CONTROL_VBLANK_POL_SRC (1 << 20)
#define XVTC_CONTROL_CHROMA_SRC (1 << 18)
#define XVTC_CONTROL_VBLANK_HOFF_SRC (1 << 17)
#define XVTC_CONTROL_VSYNC_END_SRC (1 << 16)
#define XVTC_CONTROL_VSYNC_START_SRC (1 << 15)
#define XVTC_CONTROL_ACTIVE_VSIZE_SRC (1 << 14)
#define XVTC_CONTROL_FRAME_VSIZE_SRC (1 << 13)
#define XVTC_CONTROL_HSYNC_END_SRC (1 << 11)
#define XVTC_CONTROL_HSYNC_START_SRC (1 << 10)
#define XVTC_CONTROL_ACTIVE_HSIZE_SRC (1 << 9)
#define XVTC_CONTROL_FRAME_HSIZE_SRC (1 << 8)
#define XVTC_CONTROL_SYNC_ENABLE (1 << 5)
#define XVTC_CONTROL_DET_ENABLE (1 << 3)
#define XVTC_CONTROL_GEN_ENABLE (1 << 2)
#define XVTC_STATUS_FSYNC(n) ((n) << 16)
#define XVTC_STATUS_GEN_ACTIVE_VIDEO (1 << 13)
#define XVTC_STATUS_GEN_VBLANK (1 << 12)
#define XVTC_STATUS_DET_ACTIVE_VIDEO (1 << 11)
#define XVTC_STATUS_DET_VBLANK (1 << 10)
#define XVTC_STATUS_LOCK_LOSS (1 << 9)
#define XVTC_STATUS_LOCK (1 << 8)
#define XVTC_ERROR_ACTIVE_CHROMA_LOCK (1 << 21)
#define XVTC_ERROR_ACTIVE_VIDEO_LOCK (1 << 20)
#define XVTC_ERROR_HSYNC_LOCK (1 << 19)
#define XVTC_ERROR_VSYNC_LOCK (1 << 18)
#define XVTC_ERROR_HBLANK_LOCK (1 << 17)
#define XVTC_ERROR_VBLANK_LOCK (1 << 16)
#define XVTC_IRQ_ENABLE_FSYNC(n) ((n) << 16)
#define XVTC_IRQ_ENABLE_GEN_ACTIVE_VIDEO (1 << 13)
#define XVTC_IRQ_ENABLE_GEN_VBLANK (1 << 12)
#define XVTC_IRQ_ENABLE_DET_ACTIVE_VIDEO (1 << 11)
#define XVTC_IRQ_ENABLE_DET_VBLANK (1 << 10)
#define XVTC_IRQ_ENABLE_LOCK_LOSS (1 << 9)
#define XVTC_IRQ_ENABLE_LOCK (1 << 8)
/*
* The following registers exist in two blocks, one at 0x0020 for the detector
* and one at 0x0060 for the generator.
*/
#define XVTC_DETECTOR_OFFSET 0x0020
#define XVTC_GENERATOR_OFFSET 0x0060
#define XVTC_ACTIVE_SIZE 0x0000
#define XVTC_ACTIVE_VSIZE_SHIFT 16
#define XVTC_ACTIVE_VSIZE_MASK (0x1fff << 16)
#define XVTC_ACTIVE_HSIZE_SHIFT 0
#define XVTC_ACTIVE_HSIZE_MASK (0x1fff << 0)
#define XVTC_TIMING_STATUS 0x0004
#define XVTC_TIMING_STATUS_ACTIVE_VIDEO (1 << 2)
#define XVTC_TIMING_STATUS_VBLANK (1 << 1)
#define XVTC_TIMING_STATUS_LOCKED (1 << 0)
#define XVTC_ENCODING 0x0008
#define XVTC_ENCODING_CHROMA_PARITY_SHIFT 8
#define XVTC_ENCODING_CHROMA_PARITY_MASK (3 << 8)
#define XVTC_ENCODING_CHROMA_PARITY_EVEN_ALL (0 << 8)
#define XVTC_ENCODING_CHROMA_PARITY_ODD_ALL (1 << 8)
#define XVTC_ENCODING_CHROMA_PARITY_EVEN_EVEN (2 << 8)
#define XVTC_ENCODING_CHROMA_PARITY_ODD_EVEN (3 << 8)
#define XVTC_ENCODING_VIDEO_FORMAT_SHIFT 0
#define XVTC_ENCODING_VIDEO_FORMAT_MASK (0xf << 0)
#define XVTC_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0)
#define XVTC_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0)
#define XVTC_ENCODING_VIDEO_FORMAT_RGB (2 << 0)
#define XVTC_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0)
#define XVTC_POLARITY 0x000c
#define XVTC_POLARITY_ACTIVE_CHROMA_POL (1 << 5)
#define XVTC_POLARITY_ACTIVE_VIDEO_POL (1 << 4)
#define XVTC_POLARITY_HSYNC_POL (1 << 3)
#define XVTC_POLARITY_VSYNC_POL (1 << 2)
#define XVTC_POLARITY_HBLANK_POL (1 << 1)
#define XVTC_POLARITY_VBLANK_POL (1 << 0)
#define XVTC_HSIZE 0x0010
#define XVTC_HSIZE_MASK (0x1fff << 0)
#define XVTC_VSIZE 0x0014
#define XVTC_VSIZE_MASK (0x1fff << 0)
#define XVTC_HSYNC 0x0018
#define XVTC_HSYNC_END_SHIFT 16
#define XVTC_HSYNC_END_MASK (0x1fff << 16)
#define XVTC_HSYNC_START_SHIFT 0
#define XVTC_HSYNC_START_MASK (0x1fff << 0)
#define XVTC_F0_VBLANK_H 0x001c
#define XVTC_F0_VBLANK_HEND_SHIFT 16
#define XVTC_F0_VBLANK_HEND_MASK (0x1fff << 16)
#define XVTC_F0_VBLANK_HSTART_SHIFT 0
#define XVTC_F0_VBLANK_HSTART_MASK (0x1fff << 0)
#define XVTC_F0_VSYNC_V 0x0020
#define XVTC_F0_VSYNC_VEND_SHIFT 16
#define XVTC_F0_VSYNC_VEND_MASK (0x1fff << 16)
#define XVTC_F0_VSYNC_VSTART_SHIFT 0
#define XVTC_F0_VSYNC_VSTART_MASK (0x1fff << 0)
#define XVTC_F0_VSYNC_H 0x0024
#define XVTC_F0_VSYNC_HEND_SHIFT 16
#define XVTC_F0_VSYNC_HEND_MASK (0x1fff << 16)
#define XVTC_F0_VSYNC_HSTART_SHIFT 0
#define XVTC_F0_VSYNC_HSTART_MASK (0x1fff << 0)
#define XVTC_FRAME_SYNC_CONFIG(n) (0x0100 + 4 * (n))
#define XVTC_FRAME_SYNC_V_START_SHIFT 16
#define XVTC_FRAME_SYNC_V_START_MASK (0x1fff << 16)
#define XVTC_FRAME_SYNC_H_START_SHIFT 0
#define XVTC_FRAME_SYNC_H_START_MASK (0x1fff << 0)
#define XVTC_GENERATOR_GLOBAL_DELAY 0x0104
/**
* struct xvtc_device - Xilinx Video Timing Controller device structure
* @xvip: Xilinx Video IP device
* @list: entry in the global VTC list
* @has_detector: the VTC has a timing detector
* @has_generator: the VTC has a timing generator
* @config: generator timings configuration
*/
struct xvtc_device {
struct xvip_device xvip;
struct list_head list;
bool has_detector;
bool has_generator;
struct xvtc_config config;
};
static LIST_HEAD(xvtc_list);
static DEFINE_MUTEX(xvtc_lock);
static inline void xvtc_gen_write(struct xvtc_device *xvtc, u32 addr, u32 value)
{
xvip_write(&xvtc->xvip, XVTC_GENERATOR_OFFSET + addr, value);
}
/* -----------------------------------------------------------------------------
* Generator Operations
*/
int xvtc_generator_start(struct xvtc_device *xvtc,
const struct xvtc_config *config)
{
int ret;
if (!xvtc->has_generator)
return -ENXIO;
ret = clk_prepare_enable(xvtc->xvip.clk);
if (ret < 0)
return ret;
/* We don't care about the chroma active signal, encoding parameters are
* not important for now.
*/
xvtc_gen_write(xvtc, XVTC_POLARITY,
XVTC_POLARITY_ACTIVE_CHROMA_POL |
XVTC_POLARITY_ACTIVE_VIDEO_POL |
XVTC_POLARITY_HSYNC_POL | XVTC_POLARITY_VSYNC_POL |
XVTC_POLARITY_HBLANK_POL | XVTC_POLARITY_VBLANK_POL);
/* Hardcode the polarity to active high, as required by the video in to
* AXI4-stream core.
*/
xvtc_gen_write(xvtc, XVTC_ENCODING, 0);
/* Configure the timings. The VBLANK and VSYNC signals assertion and
* deassertion are hardcoded to the first pixel of the line.
*/
xvtc_gen_write(xvtc, XVTC_ACTIVE_SIZE,
(config->vblank_start << XVTC_ACTIVE_VSIZE_SHIFT) |
(config->hblank_start << XVTC_ACTIVE_HSIZE_SHIFT));
xvtc_gen_write(xvtc, XVTC_HSIZE, config->hsize);
xvtc_gen_write(xvtc, XVTC_VSIZE, config->vsize);
xvtc_gen_write(xvtc, XVTC_HSYNC,
(config->hsync_end << XVTC_HSYNC_END_SHIFT) |
(config->hsync_start << XVTC_HSYNC_START_SHIFT));
xvtc_gen_write(xvtc, XVTC_F0_VBLANK_H, 0);
xvtc_gen_write(xvtc, XVTC_F0_VSYNC_V,
(config->vsync_end << XVTC_F0_VSYNC_VEND_SHIFT) |
(config->vsync_start << XVTC_F0_VSYNC_VSTART_SHIFT));
xvtc_gen_write(xvtc, XVTC_F0_VSYNC_H, 0);
/* Enable the generator. Set the source of all generator parameters to
* generator registers.
*/
xvip_write(&xvtc->xvip, XVIP_CTRL_CONTROL,
XVTC_CONTROL_ACTIVE_CHROMA_POL_SRC |
XVTC_CONTROL_ACTIVE_VIDEO_POL_SRC |
XVTC_CONTROL_HSYNC_POL_SRC | XVTC_CONTROL_VSYNC_POL_SRC |
XVTC_CONTROL_HBLANK_POL_SRC | XVTC_CONTROL_VBLANK_POL_SRC |
XVTC_CONTROL_CHROMA_SRC | XVTC_CONTROL_VBLANK_HOFF_SRC |
XVTC_CONTROL_VSYNC_END_SRC | XVTC_CONTROL_VSYNC_START_SRC |
XVTC_CONTROL_ACTIVE_VSIZE_SRC |
XVTC_CONTROL_FRAME_VSIZE_SRC | XVTC_CONTROL_HSYNC_END_SRC |
XVTC_CONTROL_HSYNC_START_SRC |
XVTC_CONTROL_ACTIVE_HSIZE_SRC |
XVTC_CONTROL_FRAME_HSIZE_SRC | XVTC_CONTROL_GEN_ENABLE |
XVIP_CTRL_CONTROL_REG_UPDATE);
return 0;
}
EXPORT_SYMBOL_GPL(xvtc_generator_start);
int xvtc_generator_stop(struct xvtc_device *xvtc)
{
if (!xvtc->has_generator)
return -ENXIO;
xvip_write(&xvtc->xvip, XVIP_CTRL_CONTROL, 0);
clk_disable_unprepare(xvtc->xvip.clk);
return 0;
}
EXPORT_SYMBOL_GPL(xvtc_generator_stop);
struct xvtc_device *xvtc_of_get(struct device_node *np)
{
struct device_node *xvtc_node;
struct xvtc_device *found = NULL;
struct xvtc_device *xvtc;
if (!of_property_present(np, "xlnx,vtc"))
return NULL;
xvtc_node = of_parse_phandle(np, "xlnx,vtc", 0);
if (xvtc_node == NULL)
return ERR_PTR(-EINVAL);
mutex_lock(&xvtc_lock);
list_for_each_entry(xvtc, &xvtc_list, list) {
if (xvtc->xvip.dev->of_node == xvtc_node) {
found = xvtc;
break;
}
}
mutex_unlock(&xvtc_lock);
of_node_put(xvtc_node);
if (!found)
return ERR_PTR(-EPROBE_DEFER);
return found;
}
EXPORT_SYMBOL_GPL(xvtc_of_get);
void xvtc_put(struct xvtc_device *xvtc)
{
}
EXPORT_SYMBOL_GPL(xvtc_put);
/* -----------------------------------------------------------------------------
* Registration and Unregistration
*/
static void xvtc_register_device(struct xvtc_device *xvtc)
{
mutex_lock(&xvtc_lock);
list_add_tail(&xvtc->list, &xvtc_list);
mutex_unlock(&xvtc_lock);
}
static void xvtc_unregister_device(struct xvtc_device *xvtc)
{
mutex_lock(&xvtc_lock);
list_del(&xvtc->list);
mutex_unlock(&xvtc_lock);
}
/* -----------------------------------------------------------------------------
* Platform Device Driver
*/
static int xvtc_parse_of(struct xvtc_device *xvtc)
{
struct device_node *node = xvtc->xvip.dev->of_node;
xvtc->has_detector = of_property_read_bool(node, "xlnx,detector");
xvtc->has_generator = of_property_read_bool(node, "xlnx,generator");
return 0;
}
static int xvtc_probe(struct platform_device *pdev)
{
struct xvtc_device *xvtc;
int ret;
xvtc = devm_kzalloc(&pdev->dev, sizeof(*xvtc), GFP_KERNEL);
if (!xvtc)
return -ENOMEM;
xvtc->xvip.dev = &pdev->dev;
ret = xvtc_parse_of(xvtc);
if (ret < 0)
return ret;
ret = xvip_init_resources(&xvtc->xvip);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, xvtc);
xvip_print_version(&xvtc->xvip);
xvtc_register_device(xvtc);
return 0;
}
static void xvtc_remove(struct platform_device *pdev)
{
struct xvtc_device *xvtc = platform_get_drvdata(pdev);
xvtc_unregister_device(xvtc);
xvip_cleanup_resources(&xvtc->xvip);
}
static const struct of_device_id xvtc_of_id_table[] = {
{ .compatible = "xlnx,v-tc-6.1" },
{ }
};
MODULE_DEVICE_TABLE(of, xvtc_of_id_table);
static struct platform_driver xvtc_driver = {
.driver = {
.name = "xilinx-vtc",
.of_match_table = xvtc_of_id_table,
},
.probe = xvtc_probe,
.remove_new = xvtc_remove,
};
module_platform_driver(xvtc_driver);
MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
MODULE_DESCRIPTION("Xilinx Video Timing Controller Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/xilinx/xilinx-vtc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Video IP Composite Device
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <[email protected]>
* Laurent Pinchart <[email protected]>
*/
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <media/v4l2-async.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include "xilinx-dma.h"
#include "xilinx-vipp.h"
#define XVIPP_DMA_S2MM 0
#define XVIPP_DMA_MM2S 1
/**
* struct xvip_graph_entity - Entity in the video graph
* @asd: subdev asynchronous registration information
* @entity: media entity, from the corresponding V4L2 subdev
* @subdev: V4L2 subdev
*/
struct xvip_graph_entity {
struct v4l2_async_connection asd; /* must be first */
struct media_entity *entity;
struct v4l2_subdev *subdev;
};
static inline struct xvip_graph_entity *
to_xvip_entity(struct v4l2_async_connection *asd)
{
return container_of(asd, struct xvip_graph_entity, asd);
}
/* -----------------------------------------------------------------------------
* Graph Management
*/
static struct xvip_graph_entity *
xvip_graph_find_entity(struct xvip_composite_device *xdev,
const struct fwnode_handle *fwnode)
{
struct xvip_graph_entity *entity;
struct v4l2_async_connection *asd;
list_for_each_entry(asd, &xdev->notifier.done_list, asc_entry) {
entity = to_xvip_entity(asd);
if (entity->asd.match.fwnode == fwnode)
return entity;
}
return NULL;
}
static int xvip_graph_build_one(struct xvip_composite_device *xdev,
struct xvip_graph_entity *entity)
{
u32 link_flags = MEDIA_LNK_FL_ENABLED;
struct media_entity *local = entity->entity;
struct media_entity *remote;
struct media_pad *local_pad;
struct media_pad *remote_pad;
struct xvip_graph_entity *ent;
struct v4l2_fwnode_link link;
struct fwnode_handle *ep = NULL;
int ret = 0;
dev_dbg(xdev->dev, "creating links for entity %s\n", local->name);
while (1) {
/* Get the next endpoint and parse its link. */
ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode,
ep);
if (ep == NULL)
break;
dev_dbg(xdev->dev, "processing endpoint %p\n", ep);
ret = v4l2_fwnode_parse_link(ep, &link);
if (ret < 0) {
dev_err(xdev->dev, "failed to parse link for %p\n",
ep);
continue;
}
/* Skip sink ports, they will be processed from the other end of
* the link.
*/
if (link.local_port >= local->num_pads) {
dev_err(xdev->dev, "invalid port number %u for %p\n",
link.local_port, link.local_node);
v4l2_fwnode_put_link(&link);
ret = -EINVAL;
break;
}
local_pad = &local->pads[link.local_port];
if (local_pad->flags & MEDIA_PAD_FL_SINK) {
dev_dbg(xdev->dev, "skipping sink port %p:%u\n",
link.local_node, link.local_port);
v4l2_fwnode_put_link(&link);
continue;
}
/* Skip DMA engines, they will be processed separately. */
if (link.remote_node == of_fwnode_handle(xdev->dev->of_node)) {
dev_dbg(xdev->dev, "skipping DMA port %p:%u\n",
link.local_node, link.local_port);
v4l2_fwnode_put_link(&link);
continue;
}
/* Find the remote entity. */
ent = xvip_graph_find_entity(xdev, link.remote_node);
if (ent == NULL) {
dev_err(xdev->dev, "no entity found for %p\n",
link.remote_node);
v4l2_fwnode_put_link(&link);
ret = -ENODEV;
break;
}
remote = ent->entity;
if (link.remote_port >= remote->num_pads) {
dev_err(xdev->dev, "invalid port number %u on %p\n",
link.remote_port, link.remote_node);
v4l2_fwnode_put_link(&link);
ret = -EINVAL;
break;
}
remote_pad = &remote->pads[link.remote_port];
v4l2_fwnode_put_link(&link);
/* Create the media link. */
dev_dbg(xdev->dev, "creating %s:%u -> %s:%u link\n",
local->name, local_pad->index,
remote->name, remote_pad->index);
ret = media_create_pad_link(local, local_pad->index,
remote, remote_pad->index,
link_flags);
if (ret < 0) {
dev_err(xdev->dev,
"failed to create %s:%u -> %s:%u link\n",
local->name, local_pad->index,
remote->name, remote_pad->index);
break;
}
}
fwnode_handle_put(ep);
return ret;
}
static struct xvip_dma *
xvip_graph_find_dma(struct xvip_composite_device *xdev, unsigned int port)
{
struct xvip_dma *dma;
list_for_each_entry(dma, &xdev->dmas, list) {
if (dma->port == port)
return dma;
}
return NULL;
}
static int xvip_graph_build_dma(struct xvip_composite_device *xdev)
{
u32 link_flags = MEDIA_LNK_FL_ENABLED;
struct device_node *node = xdev->dev->of_node;
struct media_entity *source;
struct media_entity *sink;
struct media_pad *source_pad;
struct media_pad *sink_pad;
struct xvip_graph_entity *ent;
struct v4l2_fwnode_link link;
struct device_node *ep = NULL;
struct xvip_dma *dma;
int ret = 0;
dev_dbg(xdev->dev, "creating links for DMA engines\n");
while (1) {
/* Get the next endpoint and parse its link. */
ep = of_graph_get_next_endpoint(node, ep);
if (ep == NULL)
break;
dev_dbg(xdev->dev, "processing endpoint %pOF\n", ep);
ret = v4l2_fwnode_parse_link(of_fwnode_handle(ep), &link);
if (ret < 0) {
dev_err(xdev->dev, "failed to parse link for %pOF\n",
ep);
continue;
}
/* Find the DMA engine. */
dma = xvip_graph_find_dma(xdev, link.local_port);
if (dma == NULL) {
dev_err(xdev->dev, "no DMA engine found for port %u\n",
link.local_port);
v4l2_fwnode_put_link(&link);
ret = -EINVAL;
break;
}
dev_dbg(xdev->dev, "creating link for DMA engine %s\n",
dma->video.name);
/* Find the remote entity. */
ent = xvip_graph_find_entity(xdev, link.remote_node);
if (ent == NULL) {
dev_err(xdev->dev, "no entity found for %pOF\n",
to_of_node(link.remote_node));
v4l2_fwnode_put_link(&link);
ret = -ENODEV;
break;
}
if (link.remote_port >= ent->entity->num_pads) {
dev_err(xdev->dev, "invalid port number %u on %pOF\n",
link.remote_port,
to_of_node(link.remote_node));
v4l2_fwnode_put_link(&link);
ret = -EINVAL;
break;
}
if (dma->pad.flags & MEDIA_PAD_FL_SOURCE) {
source = &dma->video.entity;
source_pad = &dma->pad;
sink = ent->entity;
sink_pad = &sink->pads[link.remote_port];
} else {
source = ent->entity;
source_pad = &source->pads[link.remote_port];
sink = &dma->video.entity;
sink_pad = &dma->pad;
}
v4l2_fwnode_put_link(&link);
/* Create the media link. */
dev_dbg(xdev->dev, "creating %s:%u -> %s:%u link\n",
source->name, source_pad->index,
sink->name, sink_pad->index);
ret = media_create_pad_link(source, source_pad->index,
sink, sink_pad->index,
link_flags);
if (ret < 0) {
dev_err(xdev->dev,
"failed to create %s:%u -> %s:%u link\n",
source->name, source_pad->index,
sink->name, sink_pad->index);
break;
}
}
of_node_put(ep);
return ret;
}
static int xvip_graph_notify_complete(struct v4l2_async_notifier *notifier)
{
struct xvip_composite_device *xdev =
container_of(notifier, struct xvip_composite_device, notifier);
struct xvip_graph_entity *entity;
struct v4l2_async_connection *asd;
int ret;
dev_dbg(xdev->dev, "notify complete, all subdevs registered\n");
/* Create links for every entity. */
list_for_each_entry(asd, &xdev->notifier.done_list, asc_entry) {
entity = to_xvip_entity(asd);
ret = xvip_graph_build_one(xdev, entity);
if (ret < 0)
return ret;
}
/* Create links for DMA channels. */
ret = xvip_graph_build_dma(xdev);
if (ret < 0)
return ret;
ret = v4l2_device_register_subdev_nodes(&xdev->v4l2_dev);
if (ret < 0)
dev_err(xdev->dev, "failed to register subdev nodes\n");
return media_device_register(&xdev->media_dev);
}
static int xvip_graph_notify_bound(struct v4l2_async_notifier *notifier,
struct v4l2_subdev *subdev,
struct v4l2_async_connection *asc)
{
struct xvip_graph_entity *entity = to_xvip_entity(asc);
entity->entity = &subdev->entity;
entity->subdev = subdev;
return 0;
}
static const struct v4l2_async_notifier_operations xvip_graph_notify_ops = {
.bound = xvip_graph_notify_bound,
.complete = xvip_graph_notify_complete,
};
static int xvip_graph_parse_one(struct xvip_composite_device *xdev,
struct fwnode_handle *fwnode)
{
struct fwnode_handle *remote;
struct fwnode_handle *ep = NULL;
int ret = 0;
dev_dbg(xdev->dev, "parsing node %p\n", fwnode);
while (1) {
struct xvip_graph_entity *xge;
ep = fwnode_graph_get_next_endpoint(fwnode, ep);
if (ep == NULL)
break;
dev_dbg(xdev->dev, "handling endpoint %p\n", ep);
remote = fwnode_graph_get_remote_port_parent(ep);
if (remote == NULL) {
ret = -EINVAL;
goto err_notifier_cleanup;
}
fwnode_handle_put(ep);
/* Skip entities that we have already processed. */
if (remote == of_fwnode_handle(xdev->dev->of_node) ||
xvip_graph_find_entity(xdev, remote)) {
fwnode_handle_put(remote);
continue;
}
xge = v4l2_async_nf_add_fwnode(&xdev->notifier, remote,
struct xvip_graph_entity);
fwnode_handle_put(remote);
if (IS_ERR(xge)) {
ret = PTR_ERR(xge);
goto err_notifier_cleanup;
}
}
return 0;
err_notifier_cleanup:
v4l2_async_nf_cleanup(&xdev->notifier);
fwnode_handle_put(ep);
return ret;
}
static int xvip_graph_parse(struct xvip_composite_device *xdev)
{
struct xvip_graph_entity *entity;
struct v4l2_async_connection *asd;
int ret;
/*
* Walk the links to parse the full graph. Start by parsing the
* composite node and then parse entities in turn. The list_for_each
* loop will handle entities added at the end of the list while walking
* the links.
*/
ret = xvip_graph_parse_one(xdev, of_fwnode_handle(xdev->dev->of_node));
if (ret < 0)
return 0;
list_for_each_entry(asd, &xdev->notifier.waiting_list, asc_entry) {
entity = to_xvip_entity(asd);
ret = xvip_graph_parse_one(xdev, entity->asd.match.fwnode);
if (ret < 0) {
v4l2_async_nf_cleanup(&xdev->notifier);
break;
}
}
return ret;
}
static int xvip_graph_dma_init_one(struct xvip_composite_device *xdev,
struct device_node *node)
{
struct xvip_dma *dma;
enum v4l2_buf_type type;
const char *direction;
unsigned int index;
int ret;
ret = of_property_read_string(node, "direction", &direction);
if (ret < 0)
return ret;
if (strcmp(direction, "input") == 0)
type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
else if (strcmp(direction, "output") == 0)
type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
else
return -EINVAL;
of_property_read_u32(node, "reg", &index);
dma = devm_kzalloc(xdev->dev, sizeof(*dma), GFP_KERNEL);
if (dma == NULL)
return -ENOMEM;
ret = xvip_dma_init(xdev, dma, type, index);
if (ret < 0) {
dev_err(xdev->dev, "%pOF initialization failed\n", node);
return ret;
}
list_add_tail(&dma->list, &xdev->dmas);
xdev->v4l2_caps |= type == V4L2_BUF_TYPE_VIDEO_CAPTURE
? V4L2_CAP_VIDEO_CAPTURE : V4L2_CAP_VIDEO_OUTPUT;
return 0;
}
static int xvip_graph_dma_init(struct xvip_composite_device *xdev)
{
struct device_node *ports;
struct device_node *port;
int ret = 0;
ports = of_get_child_by_name(xdev->dev->of_node, "ports");
if (ports == NULL) {
dev_err(xdev->dev, "ports node not present\n");
return -EINVAL;
}
for_each_child_of_node(ports, port) {
ret = xvip_graph_dma_init_one(xdev, port);
if (ret) {
of_node_put(port);
break;
}
}
of_node_put(ports);
return ret;
}
static void xvip_graph_cleanup(struct xvip_composite_device *xdev)
{
struct xvip_dma *dmap;
struct xvip_dma *dma;
v4l2_async_nf_unregister(&xdev->notifier);
v4l2_async_nf_cleanup(&xdev->notifier);
list_for_each_entry_safe(dma, dmap, &xdev->dmas, list) {
xvip_dma_cleanup(dma);
list_del(&dma->list);
}
}
static int xvip_graph_init(struct xvip_composite_device *xdev)
{
int ret;
/* Init the DMA channels. */
ret = xvip_graph_dma_init(xdev);
if (ret < 0) {
dev_err(xdev->dev, "DMA initialization failed\n");
goto done;
}
v4l2_async_nf_init(&xdev->notifier, &xdev->v4l2_dev);
/* Parse the graph to extract a list of subdevice DT nodes. */
ret = xvip_graph_parse(xdev);
if (ret < 0) {
dev_err(xdev->dev, "graph parsing failed\n");
goto done;
}
if (list_empty(&xdev->notifier.waiting_list)) {
dev_err(xdev->dev, "no subdev found in graph\n");
ret = -ENOENT;
goto done;
}
/* Register the subdevices notifier. */
xdev->notifier.ops = &xvip_graph_notify_ops;
ret = v4l2_async_nf_register(&xdev->notifier);
if (ret < 0) {
dev_err(xdev->dev, "notifier registration failed\n");
goto done;
}
ret = 0;
done:
if (ret < 0)
xvip_graph_cleanup(xdev);
return ret;
}
/* -----------------------------------------------------------------------------
* Media Controller and V4L2
*/
static void xvip_composite_v4l2_cleanup(struct xvip_composite_device *xdev)
{
v4l2_device_unregister(&xdev->v4l2_dev);
media_device_unregister(&xdev->media_dev);
media_device_cleanup(&xdev->media_dev);
}
static int xvip_composite_v4l2_init(struct xvip_composite_device *xdev)
{
int ret;
xdev->media_dev.dev = xdev->dev;
strscpy(xdev->media_dev.model, "Xilinx Video Composite Device",
sizeof(xdev->media_dev.model));
xdev->media_dev.hw_revision = 0;
media_device_init(&xdev->media_dev);
xdev->v4l2_dev.mdev = &xdev->media_dev;
ret = v4l2_device_register(xdev->dev, &xdev->v4l2_dev);
if (ret < 0) {
dev_err(xdev->dev, "V4L2 device registration failed (%d)\n",
ret);
media_device_cleanup(&xdev->media_dev);
return ret;
}
return 0;
}
/* -----------------------------------------------------------------------------
* Platform Device Driver
*/
static int xvip_composite_probe(struct platform_device *pdev)
{
struct xvip_composite_device *xdev;
int ret;
xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
if (!xdev)
return -ENOMEM;
xdev->dev = &pdev->dev;
INIT_LIST_HEAD(&xdev->dmas);
ret = xvip_composite_v4l2_init(xdev);
if (ret < 0)
return ret;
ret = xvip_graph_init(xdev);
if (ret < 0)
goto error;
platform_set_drvdata(pdev, xdev);
dev_info(xdev->dev, "device registered\n");
return 0;
error:
xvip_composite_v4l2_cleanup(xdev);
return ret;
}
static void xvip_composite_remove(struct platform_device *pdev)
{
struct xvip_composite_device *xdev = platform_get_drvdata(pdev);
xvip_graph_cleanup(xdev);
xvip_composite_v4l2_cleanup(xdev);
}
static const struct of_device_id xvip_composite_of_id_table[] = {
{ .compatible = "xlnx,video" },
{ }
};
MODULE_DEVICE_TABLE(of, xvip_composite_of_id_table);
static struct platform_driver xvip_composite_driver = {
.driver = {
.name = "xilinx-video",
.of_match_table = xvip_composite_of_id_table,
},
.probe = xvip_composite_probe,
.remove_new = xvip_composite_remove,
};
module_platform_driver(xvip_composite_driver);
MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
MODULE_DESCRIPTION("Xilinx Video IP Composite Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/platform/xilinx/xilinx-vipp.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 BayLibre, SAS
* Author: Neil Armstrong <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/bitfield.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/reset.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include "ge2d-regs.h"
#define GE2D_NAME "meson-ge2d"
#define DEFAULT_WIDTH 128
#define DEFAULT_HEIGHT 128
#define DEFAULT_STRIDE 512
#define MAX_WIDTH 8191
#define MAX_HEIGHT 8191
/*
* Missing features:
* - Scaling
* - Simple 1/2 vertical scaling
* - YUV input support
* - Source global alpha
* - Colorspace conversion
*/
struct ge2d_fmt {
u32 fourcc;
bool alpha;
bool le;
unsigned int depth;
unsigned int hw_fmt;
unsigned int hw_map;
};
struct ge2d_frame {
struct vb2_v4l2_buffer *buf;
/* Image Format */
struct v4l2_pix_format pix_fmt;
/* Crop */
struct v4l2_rect crop;
/* Image format */
const struct ge2d_fmt *fmt;
};
struct ge2d_ctx {
struct v4l2_fh fh;
struct meson_ge2d *ge2d;
struct ge2d_frame in;
struct ge2d_frame out;
struct v4l2_ctrl_handler ctrl_handler;
unsigned long sequence_out, sequence_cap;
/* Control values */
u32 hflip;
u32 vflip;
u32 xy_swap;
};
struct meson_ge2d {
struct v4l2_device v4l2_dev;
struct v4l2_m2m_dev *m2m_dev;
struct video_device *vfd;
struct device *dev;
struct regmap *map;
struct clk *clk;
/* vb2 queue lock */
struct mutex mutex;
struct ge2d_ctx *curr;
};
#define FMT(_fourcc, _alpha, _depth, _map) \
{ \
.fourcc = _fourcc, \
.alpha = (_alpha), \
.depth = (_depth), \
.hw_fmt = GE2D_FORMAT_ ## _depth ## BIT, \
.hw_map = GE2D_COLOR_MAP_ ## _map, \
}
/* TOFIX Handle the YUV input formats */
static const struct ge2d_fmt formats[] = {
/* FOURCC Alpha HW FMT HW MAP */
FMT(V4L2_PIX_FMT_XRGB32, false, 32, BGRA8888),
FMT(V4L2_PIX_FMT_RGB32, true, 32, BGRA8888),
FMT(V4L2_PIX_FMT_ARGB32, true, 32, BGRA8888),
FMT(V4L2_PIX_FMT_RGBX32, false, 32, ABGR8888),
FMT(V4L2_PIX_FMT_RGBA32, true, 32, ABGR8888),
FMT(V4L2_PIX_FMT_BGRX32, false, 32, RGBA8888),
FMT(V4L2_PIX_FMT_BGRA32, true, 32, RGBA8888),
FMT(V4L2_PIX_FMT_BGR32, true, 32, ARGB8888),
FMT(V4L2_PIX_FMT_ABGR32, true, 32, ARGB8888),
FMT(V4L2_PIX_FMT_XBGR32, false, 32, ARGB8888),
FMT(V4L2_PIX_FMT_RGB24, false, 24, BGR888),
FMT(V4L2_PIX_FMT_BGR24, false, 24, RGB888),
FMT(V4L2_PIX_FMT_XRGB555X, false, 16, ARGB1555),
FMT(V4L2_PIX_FMT_ARGB555X, true, 16, ARGB1555),
FMT(V4L2_PIX_FMT_RGB565, false, 16, RGB565),
FMT(V4L2_PIX_FMT_RGBX444, false, 16, RGBA4444),
FMT(V4L2_PIX_FMT_RGBA444, true, 16, RGBA4444),
FMT(V4L2_PIX_FMT_XRGB444, false, 16, ARGB4444),
FMT(V4L2_PIX_FMT_ARGB444, true, 16, ARGB4444),
};
#define NUM_FORMATS ARRAY_SIZE(formats)
static const struct ge2d_fmt *find_fmt(struct v4l2_format *f)
{
unsigned int i;
for (i = 0; i < NUM_FORMATS; i++) {
if (formats[i].fourcc == f->fmt.pix.pixelformat)
return &formats[i];
}
/*
* TRY_FMT/S_FMT should never return an error when the requested format
* is not supported. Drivers should always return a valid format,
* preferably a format that is as widely supported by applications as
* possible.
*/
return &formats[0];
}
static struct ge2d_frame *get_frame(struct ge2d_ctx *ctx,
enum v4l2_buf_type type)
{
switch (type) {
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
return &ctx->in;
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
return &ctx->out;
default:
/* This should never happen, warn and return OUTPUT frame */
dev_warn(ctx->ge2d->dev, "%s: invalid buffer type\n", __func__);
return &ctx->in;
}
}
static void ge2d_hw_start(struct meson_ge2d *ge2d)
{
struct ge2d_ctx *ctx = ge2d->curr;
u32 reg;
/* Reset */
regmap_update_bits(ge2d->map, GE2D_GEN_CTRL1,
GE2D_SOFT_RST, GE2D_SOFT_RST);
regmap_update_bits(ge2d->map, GE2D_GEN_CTRL1,
GE2D_SOFT_RST, 0);
usleep_range(100, 200);
/* Implement CANVAS for non-AXG */
regmap_write(ge2d->map, GE2D_SRC1_BADDR_CTRL,
(vb2_dma_contig_plane_dma_addr(&ctx->in.buf->vb2_buf, 0) + 7) >> 3);
regmap_write(ge2d->map, GE2D_SRC1_STRIDE_CTRL,
(ctx->in.pix_fmt.bytesperline + 7) >> 3);
regmap_write(ge2d->map, GE2D_SRC2_BADDR_CTRL,
(vb2_dma_contig_plane_dma_addr(&ctx->out.buf->vb2_buf, 0) + 7) >> 3);
regmap_write(ge2d->map, GE2D_SRC2_STRIDE_CTRL,
(ctx->out.pix_fmt.bytesperline + 7) >> 3);
regmap_write(ge2d->map, GE2D_DST1_BADDR_CTRL,
(vb2_dma_contig_plane_dma_addr(&ctx->out.buf->vb2_buf, 0) + 7) >> 3);
regmap_write(ge2d->map, GE2D_DST1_STRIDE_CTRL,
(ctx->out.pix_fmt.bytesperline + 7) >> 3);
regmap_write(ge2d->map, GE2D_GEN_CTRL0, 0);
regmap_write(ge2d->map, GE2D_GEN_CTRL1,
FIELD_PREP(GE2D_INTERRUPT_CTRL, 2) |
FIELD_PREP(GE2D_SRC2_BURST_SIZE_CTRL, 3) |
FIELD_PREP(GE2D_SRC1_BURST_SIZE_CTRL, 0x3f));
regmap_write(ge2d->map, GE2D_GEN_CTRL2,
GE2D_SRC1_LITTLE_ENDIAN |
GE2D_SRC2_LITTLE_ENDIAN |
GE2D_DST_LITTLE_ENDIAN |
FIELD_PREP(GE2D_DST1_COLOR_MAP, ctx->out.fmt->hw_map) |
FIELD_PREP(GE2D_DST1_FORMAT, ctx->out.fmt->hw_fmt) |
FIELD_PREP(GE2D_SRC2_COLOR_MAP, ctx->out.fmt->hw_map) |
FIELD_PREP(GE2D_SRC2_FORMAT, ctx->out.fmt->hw_fmt) |
FIELD_PREP(GE2D_SRC1_COLOR_MAP, ctx->in.fmt->hw_map) |
FIELD_PREP(GE2D_SRC1_FORMAT, ctx->in.fmt->hw_fmt));
regmap_write(ge2d->map, GE2D_GEN_CTRL3,
GE2D_DST1_ENABLE);
regmap_write(ge2d->map, GE2D_SRC1_CLIPY_START_END,
FIELD_PREP(GE2D_START, ctx->in.crop.top) |
FIELD_PREP(GE2D_END, ctx->in.crop.top + ctx->in.crop.height - 1));
regmap_write(ge2d->map, GE2D_SRC1_CLIPX_START_END,
FIELD_PREP(GE2D_START, ctx->in.crop.left) |
FIELD_PREP(GE2D_END, ctx->in.crop.left + ctx->in.crop.width - 1));
regmap_write(ge2d->map, GE2D_SRC2_CLIPY_START_END,
FIELD_PREP(GE2D_START, ctx->out.crop.top) |
FIELD_PREP(GE2D_END, ctx->out.crop.top + ctx->out.crop.height - 1));
regmap_write(ge2d->map, GE2D_SRC2_CLIPX_START_END,
FIELD_PREP(GE2D_START, ctx->out.crop.left) |
FIELD_PREP(GE2D_END, ctx->out.crop.left + ctx->out.crop.width - 1));
regmap_write(ge2d->map, GE2D_DST_CLIPY_START_END,
FIELD_PREP(GE2D_START, ctx->out.crop.top) |
FIELD_PREP(GE2D_END, ctx->out.crop.top + ctx->out.crop.height - 1));
regmap_write(ge2d->map, GE2D_DST_CLIPX_START_END,
FIELD_PREP(GE2D_START, ctx->out.crop.left) |
FIELD_PREP(GE2D_END, ctx->out.crop.left + ctx->out.crop.width - 1));
regmap_write(ge2d->map, GE2D_SRC1_Y_START_END,
FIELD_PREP(GE2D_END, ctx->in.pix_fmt.height - 1));
regmap_write(ge2d->map, GE2D_SRC1_X_START_END,
FIELD_PREP(GE2D_END, ctx->in.pix_fmt.width - 1));
regmap_write(ge2d->map, GE2D_SRC2_Y_START_END,
FIELD_PREP(GE2D_END, ctx->out.pix_fmt.height - 1));
regmap_write(ge2d->map, GE2D_SRC2_X_START_END,
FIELD_PREP(GE2D_END, ctx->out.pix_fmt.width - 1));
regmap_write(ge2d->map, GE2D_DST_Y_START_END,
FIELD_PREP(GE2D_END, ctx->out.pix_fmt.height - 1));
regmap_write(ge2d->map, GE2D_DST_X_START_END,
FIELD_PREP(GE2D_END, ctx->out.pix_fmt.width - 1));
/* Color, no blend, use source color */
reg = GE2D_ALU_DO_COLOR_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
COLOR_FACTOR_SRC_COLOR);
if (ctx->in.fmt->alpha && ctx->out.fmt->alpha)
/* Take source alpha */
reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
COLOR_FACTOR_SRC_ALPHA);
else if (!ctx->out.fmt->alpha)
/* Set alpha to 0 */
reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_SET,
COLOR_FACTOR_ZERO);
else
/* Keep original alpha */
reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
COLOR_FACTOR_DST_ALPHA);
regmap_write(ge2d->map, GE2D_ALU_OP_CTRL, reg);
/* Start */
regmap_write(ge2d->map, GE2D_CMD_CTRL,
(ctx->xy_swap ? GE2D_DST_XY_SWAP : 0) |
(ctx->hflip ? GE2D_SRC1_Y_REV : 0) |
(ctx->vflip ? GE2D_SRC1_X_REV : 0) |
GE2D_CBUS_CMD_WR);
}
static void device_run(void *priv)
{
struct ge2d_ctx *ctx = priv;
struct meson_ge2d *ge2d = ctx->ge2d;
ge2d->curr = ctx;
ctx->in.buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
ctx->out.buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
ge2d_hw_start(ge2d);
}
static irqreturn_t ge2d_isr(int irq, void *priv)
{
struct meson_ge2d *ge2d = priv;
u32 intr;
regmap_read(ge2d->map, GE2D_STATUS0, &intr);
if (!(intr & GE2D_GE2D_BUSY)) {
struct vb2_v4l2_buffer *src, *dst;
struct ge2d_ctx *ctx = ge2d->curr;
ge2d->curr = NULL;
src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
src->sequence = ctx->sequence_out++;
dst->sequence = ctx->sequence_cap++;
dst->timecode = src->timecode;
dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
dst->flags = src->flags;
v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
v4l2_m2m_job_finish(ge2d->m2m_dev, ctx->fh.m2m_ctx);
}
return IRQ_HANDLED;
}
static const struct v4l2_m2m_ops ge2d_m2m_ops = {
.device_run = device_run,
};
static int ge2d_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
struct ge2d_frame *f = get_frame(ctx, vq->type);
if (*nplanes)
return sizes[0] < f->pix_fmt.sizeimage ? -EINVAL : 0;
sizes[0] = f->pix_fmt.sizeimage;
*nplanes = 1;
return 0;
}
static int ge2d_buf_prepare(struct vb2_buffer *vb)
{
struct ge2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct ge2d_frame *f = get_frame(ctx, vb->vb2_queue->type);
vbuf->field = V4L2_FIELD_NONE;
vb2_set_plane_payload(vb, 0, f->pix_fmt.sizeimage);
return 0;
}
static void ge2d_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct ge2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
static int ge2d_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
if (V4L2_TYPE_IS_OUTPUT(vq->type))
ctx->sequence_out = 0;
else
ctx->sequence_cap = 0;
return 0;
}
static void ge2d_stop_streaming(struct vb2_queue *vq)
{
struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
struct vb2_v4l2_buffer *vbuf;
for (;;) {
if (V4L2_TYPE_IS_OUTPUT(vq->type))
vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
else
vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (!vbuf)
break;
v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
}
}
static const struct vb2_ops ge2d_qops = {
.queue_setup = ge2d_queue_setup,
.buf_prepare = ge2d_buf_prepare,
.buf_queue = ge2d_buf_queue,
.start_streaming = ge2d_start_streaming,
.stop_streaming = ge2d_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int
queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
{
struct ge2d_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->ops = &ge2d_qops;
src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->ge2d->mutex;
src_vq->dev = ctx->ge2d->v4l2_dev.dev;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->ops = &ge2d_qops;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->ge2d->mutex;
dst_vq->dev = ctx->ge2d->v4l2_dev.dev;
return vb2_queue_init(dst_vq);
}
static int
vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
{
strscpy(cap->driver, GE2D_NAME, sizeof(cap->driver));
strscpy(cap->card, GE2D_NAME, sizeof(cap->card));
strscpy(cap->bus_info, "platform:" GE2D_NAME, sizeof(cap->bus_info));
return 0;
}
static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f)
{
const struct ge2d_fmt *fmt;
if (f->index >= NUM_FORMATS)
return -EINVAL;
fmt = &formats[f->index];
f->pixelformat = fmt->fourcc;
return 0;
}
static int vidioc_g_selection(struct file *file, void *priv,
struct v4l2_selection *s)
{
struct ge2d_ctx *ctx = priv;
struct ge2d_frame *f;
bool use_frame = false;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
f = get_frame(ctx, s->type);
switch (s->target) {
case V4L2_SEL_TGT_COMPOSE_DEFAULT:
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
break;
case V4L2_SEL_TGT_CROP_DEFAULT:
case V4L2_SEL_TGT_CROP_BOUNDS:
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
break;
case V4L2_SEL_TGT_COMPOSE:
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
use_frame = true;
break;
case V4L2_SEL_TGT_CROP:
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
use_frame = true;
break;
default:
return -EINVAL;
}
if (use_frame) {
s->r = f->crop;
} else {
s->r.left = 0;
s->r.top = 0;
s->r.width = f->pix_fmt.width;
s->r.height = f->pix_fmt.height;
}
return 0;
}
static int vidioc_s_selection(struct file *file, void *priv,
struct v4l2_selection *s)
{
struct ge2d_ctx *ctx = priv;
struct meson_ge2d *ge2d = ctx->ge2d;
struct ge2d_frame *f;
int ret = 0;
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
f = get_frame(ctx, s->type);
switch (s->target) {
case V4L2_SEL_TGT_COMPOSE:
/*
* COMPOSE target is only valid for capture buffer type, return
* error for output buffer type
*/
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
break;
case V4L2_SEL_TGT_CROP:
/*
* CROP target is only valid for output buffer type, return
* error for capture buffer type
*/
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
break;
/*
* bound and default crop/compose targets are invalid targets to
* try/set
*/
default:
return -EINVAL;
}
if (s->r.top < 0 || s->r.left < 0) {
v4l2_err(&ge2d->v4l2_dev,
"doesn't support negative values for top & left.\n");
return -EINVAL;
}
if (s->r.left + s->r.width > f->pix_fmt.width ||
s->r.top + s->r.height > f->pix_fmt.height) {
v4l2_err(&ge2d->v4l2_dev, "unsupported rectangle value.\n");
return -EINVAL;
}
f->crop = s->r;
return ret;
}
static void vidioc_setup_cap_fmt(struct ge2d_ctx *ctx, struct v4l2_pix_format *f)
{
struct ge2d_frame *frm_out = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
*f = frm_out->pix_fmt;
if (ctx->xy_swap) {
f->width = frm_out->pix_fmt.height;
f->height = frm_out->pix_fmt.width;
}
}
static int vidioc_try_fmt_cap(struct file *file, void *priv, struct v4l2_format *f)
{
const struct ge2d_fmt *fmt = find_fmt(f);
struct ge2d_ctx *ctx = priv;
struct v4l2_pix_format fmt_cap;
vidioc_setup_cap_fmt(ctx, &fmt_cap);
fmt_cap.pixelformat = fmt->fourcc;
fmt_cap.bytesperline = max(f->fmt.pix.bytesperline,
ALIGN((fmt_cap.width * fmt->depth) >> 3, 8));
fmt_cap.sizeimage = max(f->fmt.pix.sizeimage,
fmt_cap.height * fmt_cap.bytesperline);
f->fmt.pix = fmt_cap;
return 0;
}
static int vidioc_s_fmt_cap(struct file *file, void *priv, struct v4l2_format *f)
{
struct ge2d_ctx *ctx = priv;
struct meson_ge2d *ge2d = ctx->ge2d;
struct vb2_queue *vq;
struct ge2d_frame *frm;
int ret = 0;
/* Adjust all values accordingly to the hardware capabilities
* and chosen format.
*/
ret = vidioc_try_fmt_cap(file, priv, f);
if (ret)
return ret;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (vb2_is_busy(vq)) {
v4l2_err(&ge2d->v4l2_dev, "queue (%d) bust\n", f->type);
return -EBUSY;
}
frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
frm->pix_fmt = f->fmt.pix;
frm->fmt = find_fmt(f);
f->fmt.pix.pixelformat = frm->fmt->fourcc;
/* Reset crop settings */
frm->crop.left = 0;
frm->crop.top = 0;
frm->crop.width = frm->pix_fmt.width;
frm->crop.height = frm->pix_fmt.height;
return 0;
}
static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct ge2d_ctx *ctx = priv;
struct vb2_queue *vq;
struct ge2d_frame *frm;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (!vq)
return -EINVAL;
frm = get_frame(ctx, f->type);
f->fmt.pix = frm->pix_fmt;
f->fmt.pix.pixelformat = frm->fmt->fourcc;
return 0;
}
static int vidioc_try_fmt_out(struct file *file, void *priv, struct v4l2_format *f)
{
const struct ge2d_fmt *fmt = find_fmt(f);
f->fmt.pix.field = V4L2_FIELD_NONE;
f->fmt.pix.pixelformat = fmt->fourcc;
if (f->fmt.pix.width > MAX_WIDTH)
f->fmt.pix.width = MAX_WIDTH;
if (f->fmt.pix.height > MAX_HEIGHT)
f->fmt.pix.height = MAX_HEIGHT;
f->fmt.pix.bytesperline = max(f->fmt.pix.bytesperline,
ALIGN((f->fmt.pix.width * fmt->depth) >> 3, 8));
f->fmt.pix.sizeimage = max(f->fmt.pix.sizeimage,
f->fmt.pix.height * f->fmt.pix.bytesperline);
return 0;
}
static int vidioc_s_fmt_out(struct file *file, void *priv, struct v4l2_format *f)
{
struct ge2d_ctx *ctx = priv;
struct meson_ge2d *ge2d = ctx->ge2d;
struct vb2_queue *vq;
struct ge2d_frame *frm, *frm_cap;
int ret = 0;
/* Adjust all values accordingly to the hardware capabilities
* and chosen format.
*/
ret = vidioc_try_fmt_out(file, priv, f);
if (ret)
return ret;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
if (vb2_is_busy(vq)) {
v4l2_err(&ge2d->v4l2_dev, "queue (%d) bust\n", f->type);
return -EBUSY;
}
frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
frm_cap = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
frm->pix_fmt = f->fmt.pix;
frm->fmt = find_fmt(f);
f->fmt.pix.pixelformat = frm->fmt->fourcc;
/* Reset crop settings */
frm->crop.left = 0;
frm->crop.top = 0;
frm->crop.width = frm->pix_fmt.width;
frm->crop.height = frm->pix_fmt.height;
/* Propagate settings to capture */
vidioc_setup_cap_fmt(ctx, &frm_cap->pix_fmt);
return 0;
}
static const struct v4l2_ioctl_ops ge2d_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_cap,
.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
.vidioc_g_fmt_vid_out = vidioc_g_fmt,
.vidioc_try_fmt_vid_out = vidioc_try_fmt_out,
.vidioc_s_fmt_vid_out = vidioc_s_fmt_out,
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_g_selection = vidioc_g_selection,
.vidioc_s_selection = vidioc_s_selection,
};
static int ge2d_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct ge2d_ctx *ctx = container_of(ctrl->handler, struct ge2d_ctx,
ctrl_handler);
struct v4l2_pix_format fmt;
struct vb2_queue *vq;
switch (ctrl->id) {
case V4L2_CID_HFLIP:
ctx->hflip = ctrl->val;
break;
case V4L2_CID_VFLIP:
ctx->vflip = ctrl->val;
break;
case V4L2_CID_ROTATE:
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
if (vb2_is_busy(vq))
return -EBUSY;
if (ctrl->val == 90) {
ctx->hflip = 0;
ctx->vflip = 1;
ctx->xy_swap = 1;
} else if (ctrl->val == 180) {
ctx->hflip = 1;
ctx->vflip = 1;
ctx->xy_swap = 0;
} else if (ctrl->val == 270) {
ctx->hflip = 1;
ctx->vflip = 0;
ctx->xy_swap = 1;
} else {
ctx->hflip = 0;
ctx->vflip = 0;
ctx->xy_swap = 0;
}
vidioc_setup_cap_fmt(ctx, &fmt);
/*
* If the rotation parameter changes the OUTPUT frames
* parameters, take them in account
*/
ctx->out.pix_fmt = fmt;
break;
}
return 0;
}
static const struct v4l2_ctrl_ops ge2d_ctrl_ops = {
.s_ctrl = ge2d_s_ctrl,
};
static int ge2d_setup_ctrls(struct ge2d_ctx *ctx)
{
struct meson_ge2d *ge2d = ctx->ge2d;
v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
V4L2_CID_ROTATE, 0, 270, 90, 0);
if (ctx->ctrl_handler.error) {
int err = ctx->ctrl_handler.error;
v4l2_err(&ge2d->v4l2_dev, "%s failed\n", __func__);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
return err;
}
return 0;
}
static const struct ge2d_frame def_frame = {
.pix_fmt = {
.width = DEFAULT_WIDTH,
.height = DEFAULT_HEIGHT,
.bytesperline = DEFAULT_STRIDE,
.sizeimage = DEFAULT_STRIDE * DEFAULT_HEIGHT,
.field = V4L2_FIELD_NONE,
},
.crop.width = DEFAULT_WIDTH,
.crop.height = DEFAULT_HEIGHT,
.fmt = &formats[0],
};
static int ge2d_open(struct file *file)
{
struct meson_ge2d *ge2d = video_drvdata(file);
struct ge2d_ctx *ctx = NULL;
int ret = 0;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->ge2d = ge2d;
/* Set default formats */
ctx->in = def_frame;
ctx->out = def_frame;
if (mutex_lock_interruptible(&ge2d->mutex)) {
kfree(ctx);
return -ERESTARTSYS;
}
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ge2d->m2m_dev, ctx, &queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
ret = PTR_ERR(ctx->fh.m2m_ctx);
mutex_unlock(&ge2d->mutex);
kfree(ctx);
return ret;
}
v4l2_fh_init(&ctx->fh, video_devdata(file));
file->private_data = &ctx->fh;
v4l2_fh_add(&ctx->fh);
ge2d_setup_ctrls(ctx);
/* Write the default values to the ctx struct */
v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
ctx->fh.ctrl_handler = &ctx->ctrl_handler;
mutex_unlock(&ge2d->mutex);
return 0;
}
static int ge2d_release(struct file *file)
{
struct ge2d_ctx *ctx =
container_of(file->private_data, struct ge2d_ctx, fh);
struct meson_ge2d *ge2d = ctx->ge2d;
mutex_lock(&ge2d->mutex);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
kfree(ctx);
mutex_unlock(&ge2d->mutex);
return 0;
}
static const struct v4l2_file_operations ge2d_fops = {
.owner = THIS_MODULE,
.open = ge2d_open,
.release = ge2d_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct video_device ge2d_videodev = {
.name = "meson-ge2d",
.fops = &ge2d_fops,
.ioctl_ops = &ge2d_ioctl_ops,
.minor = -1,
.release = video_device_release,
.vfl_dir = VFL_DIR_M2M,
.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
};
static const struct regmap_config meson_ge2d_regmap_conf = {
.reg_bits = 8,
.val_bits = 32,
.reg_stride = 4,
.max_register = GE2D_SRC2_STRIDE_CTRL,
};
static int ge2d_probe(struct platform_device *pdev)
{
struct reset_control *rst;
struct video_device *vfd;
struct meson_ge2d *ge2d;
void __iomem *regs;
int ret = 0;
int irq;
if (!pdev->dev.of_node)
return -ENODEV;
ge2d = devm_kzalloc(&pdev->dev, sizeof(*ge2d), GFP_KERNEL);
if (!ge2d)
return -ENOMEM;
ge2d->dev = &pdev->dev;
mutex_init(&ge2d->mutex);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
ge2d->map = devm_regmap_init_mmio(ge2d->dev, regs,
&meson_ge2d_regmap_conf);
if (IS_ERR(ge2d->map))
return PTR_ERR(ge2d->map);
irq = platform_get_irq(pdev, 0);
ret = devm_request_irq(ge2d->dev, irq, ge2d_isr, 0,
dev_name(ge2d->dev), ge2d);
if (ret < 0) {
dev_err(ge2d->dev, "failed to request irq\n");
return ret;
}
rst = devm_reset_control_get(ge2d->dev, NULL);
if (IS_ERR(rst)) {
dev_err(ge2d->dev, "failed to get core reset controller\n");
return PTR_ERR(rst);
}
ge2d->clk = devm_clk_get(ge2d->dev, NULL);
if (IS_ERR(ge2d->clk)) {
dev_err(ge2d->dev, "failed to get clock\n");
return PTR_ERR(ge2d->clk);
}
reset_control_assert(rst);
udelay(1);
reset_control_deassert(rst);
ret = clk_prepare_enable(ge2d->clk);
if (ret) {
dev_err(ge2d->dev, "Cannot enable ge2d sclk: %d\n", ret);
return ret;
}
ret = v4l2_device_register(&pdev->dev, &ge2d->v4l2_dev);
if (ret)
goto disable_clks;
vfd = video_device_alloc();
if (!vfd) {
v4l2_err(&ge2d->v4l2_dev, "Failed to allocate video device\n");
ret = -ENOMEM;
goto unreg_v4l2_dev;
}
*vfd = ge2d_videodev;
vfd->lock = &ge2d->mutex;
vfd->v4l2_dev = &ge2d->v4l2_dev;
video_set_drvdata(vfd, ge2d);
ge2d->vfd = vfd;
platform_set_drvdata(pdev, ge2d);
ge2d->m2m_dev = v4l2_m2m_init(&ge2d_m2m_ops);
if (IS_ERR(ge2d->m2m_dev)) {
v4l2_err(&ge2d->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(ge2d->m2m_dev);
goto rel_vdev;
}
ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
if (ret) {
v4l2_err(&ge2d->v4l2_dev, "Failed to register video device\n");
goto rel_m2m;
}
v4l2_info(&ge2d->v4l2_dev, "Registered %s as /dev/%s\n",
vfd->name, video_device_node_name(vfd));
return 0;
rel_m2m:
v4l2_m2m_release(ge2d->m2m_dev);
rel_vdev:
video_device_release(ge2d->vfd);
unreg_v4l2_dev:
v4l2_device_unregister(&ge2d->v4l2_dev);
disable_clks:
clk_disable_unprepare(ge2d->clk);
return ret;
}
static void ge2d_remove(struct platform_device *pdev)
{
struct meson_ge2d *ge2d = platform_get_drvdata(pdev);
video_unregister_device(ge2d->vfd);
v4l2_m2m_release(ge2d->m2m_dev);
v4l2_device_unregister(&ge2d->v4l2_dev);
clk_disable_unprepare(ge2d->clk);
}
static const struct of_device_id meson_ge2d_match[] = {
{
.compatible = "amlogic,axg-ge2d",
},
{},
};
MODULE_DEVICE_TABLE(of, meson_ge2d_match);
static struct platform_driver ge2d_drv = {
.probe = ge2d_probe,
.remove_new = ge2d_remove,
.driver = {
.name = "meson-ge2d",
.of_match_table = meson_ge2d_match,
},
};
module_platform_driver(ge2d_drv);
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_DESCRIPTION("Amlogic 2D Graphic Acceleration Unit");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/platform/amlogic/meson-ge2d/ge2d.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Hantro VPU codec driver
*
* Copyright (C) 2018 Collabora, Ltd.
* Copyright 2018 Google LLC.
* Tomasz Figa <[email protected]>
*
* Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-vmalloc.h>
#include "hantro_v4l2.h"
#include "hantro.h"
#include "hantro_hw.h"
#define DRIVER_NAME "hantro-vpu"
int hantro_debug;
module_param_named(debug, hantro_debug, int, 0644);
MODULE_PARM_DESC(debug,
"Debug level - higher value produces more verbose messages");
void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
{
struct v4l2_ctrl *ctrl;
ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
return ctrl ? ctrl->p_cur.p : NULL;
}
dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
{
struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
struct vb2_buffer *buf;
buf = vb2_find_buffer(q, ts);
if (!buf)
return 0;
return hantro_get_dec_buf_addr(ctx, buf);
}
static const struct v4l2_event hantro_eos_event = {
.type = V4L2_EVENT_EOS
};
static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
enum vb2_buffer_state result)
{
struct vb2_v4l2_buffer *src, *dst;
src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
if (WARN_ON(!src))
return;
if (WARN_ON(!dst))
return;
src->sequence = ctx->sequence_out++;
dst->sequence = ctx->sequence_cap++;
if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) {
dst->flags |= V4L2_BUF_FLAG_LAST;
v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event);
v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx);
}
v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
result);
}
static void hantro_job_finish(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
enum vb2_buffer_state result)
{
pm_runtime_mark_last_busy(vpu->dev);
pm_runtime_put_autosuspend(vpu->dev);
clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
hantro_job_finish_no_pm(vpu, ctx, result);
}
void hantro_irq_done(struct hantro_dev *vpu,
enum vb2_buffer_state result)
{
struct hantro_ctx *ctx =
v4l2_m2m_get_curr_priv(vpu->m2m_dev);
/*
* If cancel_delayed_work returns false
* the timeout expired. The watchdog is running,
* and will take care of finishing the job.
*/
if (cancel_delayed_work(&vpu->watchdog_work)) {
if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
ctx->codec_ops->done(ctx);
hantro_job_finish(vpu, ctx, result);
}
}
void hantro_watchdog(struct work_struct *work)
{
struct hantro_dev *vpu;
struct hantro_ctx *ctx;
vpu = container_of(to_delayed_work(work),
struct hantro_dev, watchdog_work);
ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
if (ctx) {
vpu_err("frame processing timed out!\n");
ctx->codec_ops->reset(ctx);
hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
}
}
void hantro_start_prepare_run(struct hantro_ctx *ctx)
{
struct vb2_v4l2_buffer *src_buf;
src_buf = hantro_get_src_buf(ctx);
v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
&ctx->ctrl_handler);
if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
hantro_postproc_enable(ctx);
else
hantro_postproc_disable(ctx);
}
}
void hantro_end_prepare_run(struct hantro_ctx *ctx)
{
struct vb2_v4l2_buffer *src_buf;
if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
hantro_postproc_enable(ctx);
else
hantro_postproc_disable(ctx);
}
src_buf = hantro_get_src_buf(ctx);
v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
&ctx->ctrl_handler);
/* Kick the watchdog. */
schedule_delayed_work(&ctx->dev->watchdog_work,
msecs_to_jiffies(2000));
}
static void device_run(void *priv)
{
struct hantro_ctx *ctx = priv;
struct vb2_v4l2_buffer *src, *dst;
int ret;
src = hantro_get_src_buf(ctx);
dst = hantro_get_dst_buf(ctx);
ret = pm_runtime_resume_and_get(ctx->dev->dev);
if (ret < 0)
goto err_cancel_job;
ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
if (ret)
goto err_cancel_job;
v4l2_m2m_buf_copy_metadata(src, dst, true);
if (ctx->codec_ops->run(ctx))
goto err_cancel_job;
return;
err_cancel_job:
hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
}
static const struct v4l2_m2m_ops vpu_m2m_ops = {
.device_run = device_run,
};
static int
queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
{
struct hantro_ctx *ctx = priv;
int ret;
src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->ops = &hantro_queue_ops;
src_vq->mem_ops = &vb2_dma_contig_memops;
/*
* Driver does mostly sequential access, so sacrifice TLB efficiency
* for faster allocation. Also, no CPU access on the source queue,
* so no kernel mapping needed.
*/
src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
DMA_ATTR_NO_KERNEL_MAPPING;
src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->dev->vpu_mutex;
src_vq->dev = ctx->dev->v4l2_dev.dev;
src_vq->supports_requests = true;
ret = vb2_queue_init(src_vq);
if (ret)
return ret;
dst_vq->bidirectional = true;
dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
/*
* The Kernel needs access to the JPEG destination buffer for the
* JPEG encoder to fill in the JPEG headers.
*/
if (!ctx->is_encoder)
dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->ops = &hantro_queue_ops;
dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer);
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->dev->vpu_mutex;
dst_vq->dev = ctx->dev->v4l2_dev.dev;
return vb2_queue_init(dst_vq);
}
static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
{
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
if (sps->chroma_format_idc > 1)
/* Only 4:0:0 and 4:2:0 are supported */
return -EINVAL;
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
if (sps->bit_depth_luma_minus8 != 0)
/* Only 8-bit is supported */
return -EINVAL;
} else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) {
const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
/* Only 8-bit and 10-bit are supported */
return -EINVAL;
} else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {
const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;
/* We only support profile 0 */
if (dec_params->profile != 0)
return -EINVAL;
} else if (ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE) {
const struct v4l2_ctrl_av1_sequence *sequence = ctrl->p_new.p_av1_sequence;
if (sequence->bit_depth != 8 && sequence->bit_depth != 10)
return -EINVAL;
}
return 0;
}
static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct hantro_ctx *ctx;
ctx = container_of(ctrl->handler,
struct hantro_ctx, ctrl_handler);
vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
switch (ctrl->id) {
case V4L2_CID_JPEG_COMPRESSION_QUALITY:
ctx->jpeg_quality = ctrl->val;
break;
default:
return -EINVAL;
}
return 0;
}
static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct hantro_ctx *ctx;
ctx = container_of(ctrl->handler,
struct hantro_ctx, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_STATELESS_VP9_FRAME: {
int bit_depth = ctrl->p_new.p_vp9_frame->bit_depth;
if (ctx->bit_depth == bit_depth)
return 0;
return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC);
}
default:
return -EINVAL;
}
return 0;
}
static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct hantro_ctx *ctx;
ctx = container_of(ctrl->handler,
struct hantro_ctx, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_STATELESS_HEVC_SPS: {
const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
int bit_depth = sps->bit_depth_luma_minus8 + 8;
if (ctx->bit_depth == bit_depth)
return 0;
return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC);
}
default:
return -EINVAL;
}
return 0;
}
static int hantro_av1_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct hantro_ctx *ctx;
ctx = container_of(ctrl->handler,
struct hantro_ctx, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_STATELESS_AV1_SEQUENCE:
{
int bit_depth = ctrl->p_new.p_av1_sequence->bit_depth;
bool need_postproc = HANTRO_AUTO_POSTPROC;
if (ctrl->p_new.p_av1_sequence->flags
& V4L2_AV1_SEQUENCE_FLAG_FILM_GRAIN_PARAMS_PRESENT)
need_postproc = HANTRO_FORCE_POSTPROC;
if (ctx->bit_depth == bit_depth &&
ctx->need_postproc == need_postproc)
return 0;
return hantro_reset_raw_fmt(ctx, bit_depth, need_postproc);
}
default:
return -EINVAL;
}
return 0;
}
static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
.try_ctrl = hantro_try_ctrl,
};
static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
.s_ctrl = hantro_jpeg_s_ctrl,
};
static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = {
.s_ctrl = hantro_vp9_s_ctrl,
};
static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
.try_ctrl = hantro_try_ctrl,
.s_ctrl = hantro_hevc_s_ctrl,
};
static const struct v4l2_ctrl_ops hantro_av1_ctrl_ops = {
.try_ctrl = hantro_try_ctrl,
.s_ctrl = hantro_av1_s_ctrl,
};
#define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \
V4L2_JPEG_ACTIVE_MARKER_COM | \
V4L2_JPEG_ACTIVE_MARKER_DQT | \
V4L2_JPEG_ACTIVE_MARKER_DHT)
static const struct hantro_ctrl controls[] = {
{
.codec = HANTRO_JPEG_ENCODER,
.cfg = {
.id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
.min = 5,
.max = 100,
.step = 1,
.def = 50,
.ops = &hantro_jpeg_ctrl_ops,
},
}, {
.codec = HANTRO_JPEG_ENCODER,
.cfg = {
.id = V4L2_CID_JPEG_ACTIVE_MARKER,
.max = HANTRO_JPEG_ACTIVE_MARKERS,
.def = HANTRO_JPEG_ACTIVE_MARKERS,
/*
* Changing the set of active markers/segments also
* messes up the alignment of the JPEG header, which
* is needed to allow the hardware to write directly
* to the output buffer. Implementing this introduces
* a lot of complexity for little gain, as the markers
* enabled is already the minimum required set.
*/
.flags = V4L2_CTRL_FLAG_READ_ONLY,
},
}, {
.codec = HANTRO_MPEG2_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
},
}, {
.codec = HANTRO_MPEG2_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_MPEG2_PICTURE,
},
}, {
.codec = HANTRO_MPEG2_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
},
}, {
.codec = HANTRO_VP8_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_VP8_FRAME,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_SPS,
.ops = &hantro_ctrl_ops,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_PPS,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_H264_START_CODE,
.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
},
}, {
.codec = HANTRO_H264_DECODER,
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
.menu_skip_mask =
BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
}
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_START_CODE,
.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_SPS,
.ops = &hantro_hevc_ctrl_ops,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_PPS,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
},
}, {
.codec = HANTRO_HEVC_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
},
}, {
.codec = HANTRO_VP9_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_VP9_FRAME,
.ops = &hantro_vp9_ctrl_ops,
},
}, {
.codec = HANTRO_VP9_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
},
}, {
.codec = HANTRO_AV1_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_AV1_FRAME,
},
}, {
.codec = HANTRO_AV1_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
.dims = { V4L2_AV1_MAX_TILE_COUNT },
},
}, {
.codec = HANTRO_AV1_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
.ops = &hantro_av1_ctrl_ops,
},
}, {
.codec = HANTRO_AV1_DECODER,
.cfg = {
.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
},
},
};
static int hantro_ctrls_setup(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
int allowed_codecs)
{
int i, num_ctrls = ARRAY_SIZE(controls);
v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
for (i = 0; i < num_ctrls; i++) {
if (!(allowed_codecs & controls[i].codec))
continue;
v4l2_ctrl_new_custom(&ctx->ctrl_handler,
&controls[i].cfg, NULL);
if (ctx->ctrl_handler.error) {
vpu_err("Adding control (%d) failed %d\n",
controls[i].cfg.id,
ctx->ctrl_handler.error);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
return ctx->ctrl_handler.error;
}
}
return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
}
/*
* V4L2 file operations.
*/
static int hantro_open(struct file *filp)
{
struct hantro_dev *vpu = video_drvdata(filp);
struct video_device *vdev = video_devdata(filp);
struct hantro_func *func = hantro_vdev_to_func(vdev);
struct hantro_ctx *ctx;
int allowed_codecs, ret;
/*
* We do not need any extra locking here, because we operate only
* on local data here, except reading few fields from dev, which
* do not change through device's lifetime (which is guaranteed by
* reference on module from open()) and V4L2 internal objects (such
* as vdev and ctx->fh), which have proper locking done in respective
* helper functions used here.
*/
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->dev = vpu;
if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
ctx->is_encoder = true;
} else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
ctx->is_encoder = false;
} else {
ret = -ENODEV;
goto err_ctx_free;
}
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
if (IS_ERR(ctx->fh.m2m_ctx)) {
ret = PTR_ERR(ctx->fh.m2m_ctx);
goto err_ctx_free;
}
v4l2_fh_init(&ctx->fh, vdev);
filp->private_data = &ctx->fh;
v4l2_fh_add(&ctx->fh);
hantro_reset_fmts(ctx);
ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
if (ret) {
vpu_err("Failed to set up controls\n");
goto err_fh_free;
}
ctx->fh.ctrl_handler = &ctx->ctrl_handler;
return 0;
err_fh_free:
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
err_ctx_free:
kfree(ctx);
return ret;
}
static int hantro_release(struct file *filp)
{
struct hantro_ctx *ctx =
container_of(filp->private_data, struct hantro_ctx, fh);
/*
* No need for extra locking because this was the last reference
* to this file.
*/
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
kfree(ctx);
return 0;
}
static const struct v4l2_file_operations hantro_fops = {
.owner = THIS_MODULE,
.open = hantro_open,
.release = hantro_release,
.poll = v4l2_m2m_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = v4l2_m2m_fop_mmap,
};
static const struct of_device_id of_hantro_match[] = {
#ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
{ .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, },
{ .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
{ .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
{ .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
{ .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
#endif
#ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
{ .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_SUNXI
{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_hantro_match);
static int hantro_register_entity(struct media_device *mdev,
struct media_entity *entity,
const char *entity_name,
struct media_pad *pads, int num_pads,
int function, struct video_device *vdev)
{
char *name;
int ret;
entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
if (function == MEDIA_ENT_F_IO_V4L) {
entity->info.dev.major = VIDEO_MAJOR;
entity->info.dev.minor = vdev->minor;
}
name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
entity_name);
if (!name)
return -ENOMEM;
entity->name = name;
entity->function = function;
ret = media_entity_pads_init(entity, num_pads, pads);
if (ret)
return ret;
ret = media_device_register_entity(mdev, entity);
if (ret)
return ret;
return 0;
}
static int hantro_attach_func(struct hantro_dev *vpu,
struct hantro_func *func)
{
struct media_device *mdev = &vpu->mdev;
struct media_link *link;
int ret;
/* Create the three encoder entities with their pads */
func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
&func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
&func->vdev);
if (ret)
return ret;
func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
ret = hantro_register_entity(mdev, &func->proc, "proc",
func->proc_pads, 2, func->id,
&func->vdev);
if (ret)
goto err_rel_entity0;
func->sink_pad.flags = MEDIA_PAD_FL_SINK;
ret = hantro_register_entity(mdev, &func->sink, "sink",
&func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
&func->vdev);
if (ret)
goto err_rel_entity1;
/* Connect the three entities */
ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret)
goto err_rel_entity2;
ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret)
goto err_rm_links0;
/* Create video interface */
func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
0, VIDEO_MAJOR,
func->vdev.minor);
if (!func->intf_devnode) {
ret = -ENOMEM;
goto err_rm_links1;
}
/* Connect the two DMA engines to the interface */
link = media_create_intf_link(&func->vdev.entity,
&func->intf_devnode->intf,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (!link) {
ret = -ENOMEM;
goto err_rm_devnode;
}
link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (!link) {
ret = -ENOMEM;
goto err_rm_devnode;
}
return 0;
err_rm_devnode:
media_devnode_remove(func->intf_devnode);
err_rm_links1:
media_entity_remove_links(&func->sink);
err_rm_links0:
media_entity_remove_links(&func->proc);
media_entity_remove_links(&func->vdev.entity);
err_rel_entity2:
media_device_unregister_entity(&func->sink);
err_rel_entity1:
media_device_unregister_entity(&func->proc);
err_rel_entity0:
media_device_unregister_entity(&func->vdev.entity);
return ret;
}
static void hantro_detach_func(struct hantro_func *func)
{
media_devnode_remove(func->intf_devnode);
media_entity_remove_links(&func->sink);
media_entity_remove_links(&func->proc);
media_entity_remove_links(&func->vdev.entity);
media_device_unregister_entity(&func->sink);
media_device_unregister_entity(&func->proc);
media_device_unregister_entity(&func->vdev.entity);
}
static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
{
const struct of_device_id *match;
struct hantro_func *func;
struct video_device *vfd;
int ret;
match = of_match_node(of_hantro_match, vpu->dev->of_node);
func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
if (!func) {
v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
return -ENOMEM;
}
func->id = funcid;
vfd = &func->vdev;
vfd->fops = &hantro_fops;
vfd->release = video_device_release_empty;
vfd->lock = &vpu->vpu_mutex;
vfd->v4l2_dev = &vpu->v4l2_dev;
vfd->vfl_dir = VFL_DIR_M2M;
vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
vfd->ioctl_ops = &hantro_ioctl_ops;
snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
vpu->encoder = func;
} else {
vpu->decoder = func;
v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);
v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);
}
video_set_drvdata(vfd, vpu);
ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
if (ret) {
v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
return ret;
}
ret = hantro_attach_func(vpu, func);
if (ret) {
v4l2_err(&vpu->v4l2_dev,
"Failed to attach functionality to the media device\n");
goto err_unreg_dev;
}
v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
vfd->num);
return 0;
err_unreg_dev:
video_unregister_device(vfd);
return ret;
}
static int hantro_add_enc_func(struct hantro_dev *vpu)
{
if (!vpu->variant->enc_fmts)
return 0;
return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
}
static int hantro_add_dec_func(struct hantro_dev *vpu)
{
if (!vpu->variant->dec_fmts)
return 0;
return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
}
static void hantro_remove_func(struct hantro_dev *vpu,
unsigned int funcid)
{
struct hantro_func *func;
if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
func = vpu->encoder;
else
func = vpu->decoder;
if (!func)
return;
hantro_detach_func(func);
video_unregister_device(&func->vdev);
}
static void hantro_remove_enc_func(struct hantro_dev *vpu)
{
hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
}
static void hantro_remove_dec_func(struct hantro_dev *vpu)
{
hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
}
static const struct media_device_ops hantro_m2m_media_ops = {
.req_validate = vb2_request_validate,
.req_queue = v4l2_m2m_request_queue,
};
static int hantro_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct hantro_dev *vpu;
int num_bases;
int i, ret;
vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
if (!vpu)
return -ENOMEM;
vpu->dev = &pdev->dev;
vpu->pdev = pdev;
mutex_init(&vpu->vpu_mutex);
spin_lock_init(&vpu->irqlock);
match = of_match_node(of_hantro_match, pdev->dev.of_node);
vpu->variant = match->data;
/*
* Support for nxp,imx8mq-vpu is kept for backwards compatibility
* but it's deprecated. Please update your DTS file to use
* nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
*/
if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
dev_warn(&pdev->dev, "%s compatible is deprecated\n",
match->compatible);
INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
sizeof(*vpu->clocks), GFP_KERNEL);
if (!vpu->clocks)
return -ENOMEM;
if (vpu->variant->num_clocks > 1) {
for (i = 0; i < vpu->variant->num_clocks; i++)
vpu->clocks[i].id = vpu->variant->clk_names[i];
ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
vpu->clocks);
if (ret)
return ret;
} else {
/*
* If the driver has a single clk, chances are there will be no
* actual name in the DT bindings.
*/
vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(vpu->clocks[0].clk))
return PTR_ERR(vpu->clocks[0].clk);
}
vpu->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
if (IS_ERR(vpu->resets))
return PTR_ERR(vpu->resets);
num_bases = vpu->variant->num_regs ?: 1;
vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
sizeof(*vpu->reg_bases), GFP_KERNEL);
if (!vpu->reg_bases)
return -ENOMEM;
for (i = 0; i < num_bases; i++) {
vpu->reg_bases[i] = vpu->variant->reg_names ?
devm_platform_ioremap_resource_byname(pdev, vpu->variant->reg_names[i]) :
devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vpu->reg_bases[i]))
return PTR_ERR(vpu->reg_bases[i]);
}
vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
/**
* TODO: Eventually allow taking advantage of full 64-bit address space.
* Until then we assume the MSB portion of buffers' base addresses is
* always 0 due to this masking operation.
*/
ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
return ret;
}
vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
for (i = 0; i < vpu->variant->num_irqs; i++) {
const char *irq_name;
int irq;
if (!vpu->variant->irqs[i].handler)
continue;
if (vpu->variant->num_irqs > 1) {
irq_name = vpu->variant->irqs[i].name;
irq = platform_get_irq_byname(vpu->pdev, irq_name);
} else {
/*
* If the driver has a single IRQ, chances are there
* will be no actual name in the DT bindings.
*/
irq_name = "default";
irq = platform_get_irq(vpu->pdev, 0);
}
if (irq < 0)
return irq;
ret = devm_request_irq(vpu->dev, irq,
vpu->variant->irqs[i].handler, 0,
dev_name(vpu->dev), vpu);
if (ret) {
dev_err(vpu->dev, "Could not request %s IRQ.\n",
irq_name);
return ret;
}
}
if (vpu->variant->init) {
ret = vpu->variant->init(vpu);
if (ret) {
dev_err(&pdev->dev, "Failed to init VPU hardware\n");
return ret;
}
}
pm_runtime_set_autosuspend_delay(vpu->dev, 100);
pm_runtime_use_autosuspend(vpu->dev);
pm_runtime_enable(vpu->dev);
ret = reset_control_deassert(vpu->resets);
if (ret) {
dev_err(&pdev->dev, "Failed to deassert resets\n");
goto err_pm_disable;
}
ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
if (ret) {
dev_err(&pdev->dev, "Failed to prepare clocks\n");
goto err_rst_assert;
}
ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
if (ret) {
dev_err(&pdev->dev, "Failed to register v4l2 device\n");
goto err_clk_unprepare;
}
platform_set_drvdata(pdev, vpu);
vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
if (IS_ERR(vpu->m2m_dev)) {
v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(vpu->m2m_dev);
goto err_v4l2_unreg;
}
vpu->mdev.dev = vpu->dev;
strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
media_device_init(&vpu->mdev);
vpu->mdev.ops = &hantro_m2m_media_ops;
vpu->v4l2_dev.mdev = &vpu->mdev;
ret = hantro_add_enc_func(vpu);
if (ret) {
dev_err(&pdev->dev, "Failed to register encoder\n");
goto err_m2m_rel;
}
ret = hantro_add_dec_func(vpu);
if (ret) {
dev_err(&pdev->dev, "Failed to register decoder\n");
goto err_rm_enc_func;
}
ret = media_device_register(&vpu->mdev);
if (ret) {
v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
goto err_rm_dec_func;
}
return 0;
err_rm_dec_func:
hantro_remove_dec_func(vpu);
err_rm_enc_func:
hantro_remove_enc_func(vpu);
err_m2m_rel:
media_device_cleanup(&vpu->mdev);
v4l2_m2m_release(vpu->m2m_dev);
err_v4l2_unreg:
v4l2_device_unregister(&vpu->v4l2_dev);
err_clk_unprepare:
clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
err_rst_assert:
reset_control_assert(vpu->resets);
err_pm_disable:
pm_runtime_dont_use_autosuspend(vpu->dev);
pm_runtime_disable(vpu->dev);
return ret;
}
static void hantro_remove(struct platform_device *pdev)
{
struct hantro_dev *vpu = platform_get_drvdata(pdev);
v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
media_device_unregister(&vpu->mdev);
hantro_remove_dec_func(vpu);
hantro_remove_enc_func(vpu);
media_device_cleanup(&vpu->mdev);
v4l2_m2m_release(vpu->m2m_dev);
v4l2_device_unregister(&vpu->v4l2_dev);
clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
reset_control_assert(vpu->resets);
pm_runtime_dont_use_autosuspend(vpu->dev);
pm_runtime_disable(vpu->dev);
}
#ifdef CONFIG_PM
static int hantro_runtime_resume(struct device *dev)
{
struct hantro_dev *vpu = dev_get_drvdata(dev);
if (vpu->variant->runtime_resume)
return vpu->variant->runtime_resume(vpu);
return 0;
}
#endif
static const struct dev_pm_ops hantro_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
};
static struct platform_driver hantro_driver = {
.probe = hantro_probe,
.remove_new = hantro_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = of_hantro_match,
.pm = &hantro_pm_ops,
},
};
module_platform_driver(hantro_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Alpha Lin <[email protected]>");
MODULE_AUTHOR("Tomasz Figa <[email protected]>");
MODULE_AUTHOR("Ezequiel Garcia <[email protected]>");
MODULE_DESCRIPTION("Hantro VPU codec driver");
| linux-master | drivers/media/platform/verisilicon/hantro_drv.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Hantro VPU HEVC codec driver
*
* Copyright (C) 2020 Safran Passenger Innovations LLC
*/
#include "hantro_hw.h"
#include "hantro_g2_regs.h"
#define G2_ALIGN 16
static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
{
return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
}
static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
{
size_t cr_offset = hantro_hevc_chroma_offset(ctx);
return ALIGN((cr_offset * 3) / 2, G2_ALIGN);
}
static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
u16 *p = (u16 *)((u8 *)ctx->hevc_dec.tile_sizes.cpu);
unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;
unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;
unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
unsigned int max_log2_ctb_size, ctb_size;
bool tiles_enabled, uniform_spacing;
u32 no_chroma = 0;
tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);
hantro_reg_write(vpu, &g2_tile_e, tiles_enabled);
max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
sps->log2_diff_max_min_luma_coding_block_size;
pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
(1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;
pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)
>> max_log2_ctb_size;
ctb_size = 1 << max_log2_ctb_size;
vpu_debug(1, "Preparing tile sizes buffer for %dx%d CTBs (CTB size %d)\n",
pic_width_in_ctbs, pic_height_in_ctbs, ctb_size);
if (tiles_enabled) {
unsigned int i, j, h;
vpu_debug(1, "Tiles enabled! %dx%d\n", num_tile_cols, num_tile_rows);
hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);
hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);
/* write width + height for each tile in pic */
if (!uniform_spacing) {
u32 tmp_w = 0, tmp_h = 0;
for (i = 0; i < num_tile_rows; i++) {
if (i == num_tile_rows - 1)
h = pic_height_in_ctbs - tmp_h;
else
h = pps->row_height_minus1[i] + 1;
tmp_h += h;
if (i == 0 && h == 1 && ctb_size == 16)
no_chroma = 1;
for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {
tmp_w += pps->column_width_minus1[j] + 1;
*p++ = pps->column_width_minus1[j] + 1;
*p++ = h;
if (i == 0 && h == 1 && ctb_size == 16)
no_chroma = 1;
}
/* last column */
*p++ = pic_width_in_ctbs - tmp_w;
*p++ = h;
}
} else { /* uniform spacing */
u32 tmp, prev_h, prev_w;
for (i = 0, prev_h = 0; i < num_tile_rows; i++) {
tmp = (i + 1) * pic_height_in_ctbs / num_tile_rows;
h = tmp - prev_h;
prev_h = tmp;
if (i == 0 && h == 1 && ctb_size == 16)
no_chroma = 1;
for (j = 0, prev_w = 0; j < num_tile_cols; j++) {
tmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;
*p++ = tmp - prev_w;
*p++ = h;
if (j == 0 &&
(pps->column_width_minus1[0] + 1) == 1 &&
ctb_size == 16)
no_chroma = 1;
prev_w = tmp;
}
}
}
} else {
hantro_reg_write(vpu, &g2_num_tile_rows, 1);
hantro_reg_write(vpu, &g2_num_tile_cols, 1);
/* There's one tile, with dimensions equal to pic size. */
p[0] = pic_width_in_ctbs;
p[1] = pic_height_in_ctbs;
}
if (no_chroma)
vpu_debug(1, "%s: no chroma!\n", __func__);
}
static int compute_header_skip_length(struct hantro_ctx *ctx)
{
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
int skip = 0;
if (pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT)
/* size of pic_output_flag */
skip++;
if (sps->flags & V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE)
/* size of pic_order_cnt_lsb */
skip += 2;
if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
/* size of pic_order_cnt_lsb */
skip += sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
/* size of short_term_ref_pic_set_sps_flag */
skip++;
if (decode_params->short_term_ref_pic_set_size)
/* size of st_ref_pic_set( num_short_term_ref_pic_sets ) */
skip += decode_params->short_term_ref_pic_set_size;
else if (sps->num_short_term_ref_pic_sets > 1)
skip += fls(sps->num_short_term_ref_pic_sets - 1);
skip += decode_params->long_term_ref_pic_set_size;
}
return skip;
}
static void set_params(struct hantro_ctx *ctx)
{
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
struct hantro_dev *vpu = ctx->dev;
u32 min_log2_cb_size, max_log2_ctb_size, min_cb_size, max_ctb_size;
u32 pic_width_in_min_cbs, pic_height_in_min_cbs;
u32 pic_width_aligned, pic_height_aligned;
u32 partial_ctb_x, partial_ctb_y;
hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);
hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);
hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx));
min_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
max_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size;
hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);
hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);
min_cb_size = 1 << min_log2_cb_size;
max_ctb_size = 1 << max_log2_ctb_size;
pic_width_in_min_cbs = sps->pic_width_in_luma_samples / min_cb_size;
pic_height_in_min_cbs = sps->pic_height_in_luma_samples / min_cb_size;
pic_width_aligned = ALIGN(sps->pic_width_in_luma_samples, max_ctb_size);
pic_height_aligned = ALIGN(sps->pic_height_in_luma_samples, max_ctb_size);
partial_ctb_x = !!(sps->pic_width_in_luma_samples != pic_width_aligned);
partial_ctb_y = !!(sps->pic_height_in_luma_samples != pic_height_aligned);
hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);
hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);
hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);
hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);
hantro_reg_write(vpu, &g2_pic_width_4x4,
(pic_width_in_min_cbs * min_cb_size) / 4);
hantro_reg_write(vpu, &g2_pic_height_4x4,
(pic_height_in_min_cbs * min_cb_size) / 4);
hantro_reg_write(vpu, &hevc_max_inter_hierdepth,
sps->max_transform_hierarchy_depth_inter);
hantro_reg_write(vpu, &hevc_max_intra_hierdepth,
sps->max_transform_hierarchy_depth_intra);
hantro_reg_write(vpu, &hevc_min_trb_size,
sps->log2_min_luma_transform_block_size_minus2 + 2);
hantro_reg_write(vpu, &hevc_max_trb_size,
sps->log2_min_luma_transform_block_size_minus2 + 2 +
sps->log2_diff_max_min_luma_transform_block_size);
hantro_reg_write(vpu, &g2_tempor_mvp_e,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) &&
!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC));
hantro_reg_write(vpu, &g2_strong_smooth_e,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));
hantro_reg_write(vpu, &g2_asym_pred_e,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
hantro_reg_write(vpu, &g2_sao_e,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
hantro_reg_write(vpu, &g2_sign_data_hide,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));
if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {
hantro_reg_write(vpu, &g2_cu_qpd_e, 1);
hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);
} else {
hantro_reg_write(vpu, &g2_cu_qpd_e, 0);
hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
}
hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
hantro_reg_write(vpu, &g2_slice_hdr_ext_e,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));
hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);
hantro_reg_write(vpu, &g2_slice_chqp_present,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));
hantro_reg_write(vpu, &g2_weight_bipr_idc,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));
hantro_reg_write(vpu, &g2_transq_bypass,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));
hantro_reg_write(vpu, &g2_list_mod_e,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));
hantro_reg_write(vpu, &g2_entropy_sync_e,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));
hantro_reg_write(vpu, &g2_cabac_init_present,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
hantro_reg_write(vpu, &g2_idr_pic_e,
!!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC));
hantro_reg_write(vpu, &hevc_parallel_merge,
pps->log2_parallel_merge_level_minus2 + 2);
hantro_reg_write(vpu, &g2_pcm_filt_d,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
hantro_reg_write(vpu, &g2_pcm_e,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED));
if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
hantro_reg_write(vpu, &g2_max_pcm_size,
sps->log2_diff_max_min_pcm_luma_coding_block_size +
sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
hantro_reg_write(vpu, &g2_min_pcm_size,
sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
hantro_reg_write(vpu, &g2_bit_depth_pcm_y,
sps->pcm_sample_bit_depth_luma_minus1 + 1);
hantro_reg_write(vpu, &g2_bit_depth_pcm_c,
sps->pcm_sample_bit_depth_chroma_minus1 + 1);
} else {
hantro_reg_write(vpu, &g2_max_pcm_size, 0);
hantro_reg_write(vpu, &g2_min_pcm_size, 0);
hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);
hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);
}
hantro_reg_write(vpu, &g2_start_code_e, 1);
hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);
hantro_reg_write(vpu, &g2_weight_pred_e,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));
hantro_reg_write(vpu, &g2_cabac_init_present,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
hantro_reg_write(vpu, &g2_const_intra_e,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));
hantro_reg_write(vpu, &g2_transform_skip,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));
hantro_reg_write(vpu, &g2_out_filtering_dis,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));
hantro_reg_write(vpu, &g2_filt_ctrl_pres,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));
hantro_reg_write(vpu, &g2_dependent_slice,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));
hantro_reg_write(vpu, &g2_filter_override,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));
hantro_reg_write(vpu, &g2_refidx0_active,
pps->num_ref_idx_l0_default_active_minus1 + 1);
hantro_reg_write(vpu, &g2_refidx1_active,
pps->num_ref_idx_l1_default_active_minus1 + 1);
hantro_reg_write(vpu, &g2_apf_threshold, 8);
}
static void set_ref_pic_list(struct hantro_ctx *ctx)
{
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
struct hantro_dev *vpu = ctx->dev;
const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
u32 list0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
u32 list1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
static const struct hantro_reg ref_pic_regs0[] = {
hevc_rlist_f0,
hevc_rlist_f1,
hevc_rlist_f2,
hevc_rlist_f3,
hevc_rlist_f4,
hevc_rlist_f5,
hevc_rlist_f6,
hevc_rlist_f7,
hevc_rlist_f8,
hevc_rlist_f9,
hevc_rlist_f10,
hevc_rlist_f11,
hevc_rlist_f12,
hevc_rlist_f13,
hevc_rlist_f14,
hevc_rlist_f15,
};
static const struct hantro_reg ref_pic_regs1[] = {
hevc_rlist_b0,
hevc_rlist_b1,
hevc_rlist_b2,
hevc_rlist_b3,
hevc_rlist_b4,
hevc_rlist_b5,
hevc_rlist_b6,
hevc_rlist_b7,
hevc_rlist_b8,
hevc_rlist_b9,
hevc_rlist_b10,
hevc_rlist_b11,
hevc_rlist_b12,
hevc_rlist_b13,
hevc_rlist_b14,
hevc_rlist_b15,
};
unsigned int i, j;
/* List 0 contains: short term before, short term after and long term */
j = 0;
for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list0); i++)
list0[j++] = decode_params->poc_st_curr_before[i];
for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list0); i++)
list0[j++] = decode_params->poc_st_curr_after[i];
for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list0); i++)
list0[j++] = decode_params->poc_lt_curr[i];
/* Fill the list, copying over and over */
i = 0;
while (j < ARRAY_SIZE(list0))
list0[j++] = list0[i++];
j = 0;
for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list1); i++)
list1[j++] = decode_params->poc_st_curr_after[i];
for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list1); i++)
list1[j++] = decode_params->poc_st_curr_before[i];
for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list1); i++)
list1[j++] = decode_params->poc_lt_curr[i];
i = 0;
while (j < ARRAY_SIZE(list1))
list1[j++] = list1[i++];
for (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
hantro_reg_write(vpu, &ref_pic_regs0[i], list0[i]);
hantro_reg_write(vpu, &ref_pic_regs1[i], list1[i]);
}
}
static int set_ref(struct hantro_ctx *ctx)
{
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *vb2_dst;
struct hantro_decoded_buffer *dst;
size_t cr_offset = hantro_hevc_chroma_offset(ctx);
size_t mv_offset = hantro_hevc_motion_vectors_offset(ctx);
u32 max_ref_frames;
u16 dpb_longterm_e;
static const struct hantro_reg cur_poc[] = {
hevc_cur_poc_00,
hevc_cur_poc_01,
hevc_cur_poc_02,
hevc_cur_poc_03,
hevc_cur_poc_04,
hevc_cur_poc_05,
hevc_cur_poc_06,
hevc_cur_poc_07,
hevc_cur_poc_08,
hevc_cur_poc_09,
hevc_cur_poc_10,
hevc_cur_poc_11,
hevc_cur_poc_12,
hevc_cur_poc_13,
hevc_cur_poc_14,
hevc_cur_poc_15,
};
unsigned int i;
max_ref_frames = decode_params->num_poc_lt_curr +
decode_params->num_poc_st_curr_before +
decode_params->num_poc_st_curr_after;
/*
* Set max_ref_frames to non-zero to avoid HW hang when decoding
* badly marked I-frames.
*/
max_ref_frames = max_ref_frames ? max_ref_frames : 1;
hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);
hantro_reg_write(vpu, &g2_filter_over_slices,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));
hantro_reg_write(vpu, &g2_filter_over_tiles,
!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
/*
* Write POC count diff from current pic.
*/
for (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {
char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt_val;
hantro_reg_write(vpu, &cur_poc[i], poc_diff);
}
if (i < ARRAY_SIZE(cur_poc)) {
/*
* After the references, fill one entry pointing to itself,
* i.e. difference is zero.
*/
hantro_reg_write(vpu, &cur_poc[i], 0);
i++;
}
/* Fill the rest with the current picture */
for (; i < ARRAY_SIZE(cur_poc); i++)
hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);
set_ref_pic_list(ctx);
/* We will only keep the reference pictures that are still used */
hantro_hevc_ref_init(ctx);
/* Set up addresses of DPB buffers */
dpb_longterm_e = 0;
for (i = 0; i < decode_params->num_active_dpb_entries &&
i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt_val);
if (!luma_addr)
return -ENOMEM;
chroma_addr = luma_addr + cr_offset;
mv_addr = luma_addr + mv_offset;
if (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
}
vb2_dst = hantro_get_dst_buf(ctx);
dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
if (!luma_addr)
return -ENOMEM;
if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))
return -EINVAL;
chroma_addr = luma_addr + cr_offset;
mv_addr = luma_addr + mv_offset;
hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr);
hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);
hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);
}
hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
return 0;
}
static void set_buffers(struct hantro_ctx *ctx)
{
struct vb2_v4l2_buffer *src_buf;
struct hantro_dev *vpu = ctx->dev;
dma_addr_t src_dma;
u32 src_len, src_buf_len;
src_buf = hantro_get_src_buf(ctx);
/* Source (stream) buffer. */
src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);
hantro_reg_write(vpu, &g2_stream_len, src_len);
hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
hantro_reg_write(vpu, &g2_strm_start_offset, 0);
hantro_reg_write(vpu, &g2_write_mvs_e, 1);
hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);
}
static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
const struct v4l2_ctrl_hevc_scaling_matrix *sc = ctrls->scaling;
const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
u8 *p = ((u8 *)ctx->hevc_dec.scaling_lists.cpu);
unsigned int scaling_list_enabled;
unsigned int i, j, k;
scaling_list_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
hantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled);
if (!scaling_list_enabled)
return;
for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_16x16); i++)
*p++ = sc->scaling_list_dc_coef_16x16[i];
for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_32x32); i++)
*p++ = sc->scaling_list_dc_coef_32x32[i];
/* 128-bit boundary */
p += 8;
/* write scaling lists column by column */
for (i = 0; i < 6; i++)
for (j = 0; j < 4; j++)
for (k = 0; k < 4; k++)
*p++ = sc->scaling_list_4x4[i][4 * k + j];
for (i = 0; i < 6; i++)
for (j = 0; j < 8; j++)
for (k = 0; k < 8; k++)
*p++ = sc->scaling_list_8x8[i][8 * k + j];
for (i = 0; i < 6; i++)
for (j = 0; j < 8; j++)
for (k = 0; k < 8; k++)
*p++ = sc->scaling_list_16x16[i][8 * k + j];
for (i = 0; i < 2; i++)
for (j = 0; j < 8; j++)
for (k = 0; k < 8; k++)
*p++ = sc->scaling_list_32x32[i][8 * k + j];
hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
}
int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
int ret;
hantro_g2_check_idle(vpu);
/* Prepare HEVC decoder context. */
ret = hantro_hevc_dec_prepare_run(ctx);
if (ret)
return ret;
/* Configure hardware registers. */
set_params(ctx);
/* set reference pictures */
ret = set_ref(ctx);
if (ret)
return ret;
set_buffers(ctx);
prepare_tile_info_buffer(ctx);
prepare_scaling_list_buffer(ctx);
hantro_end_prepare_run(ctx);
hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE);
hantro_reg_write(vpu, &g2_clk_gate_e, 1);
/* Don't disable output */
hantro_reg_write(vpu, &g2_out_dis, 0);
/* Don't compress buffers */
hantro_reg_write(vpu, &g2_ref_compress_bypass, 1);
/* Bus width and max burst */
hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);
hantro_reg_write(vpu, &g2_max_burst, 16);
/* Swap */
hantro_reg_write(vpu, &g2_strm_swap, 0xf);
hantro_reg_write(vpu, &g2_dirmv_swap, 0xf);
hantro_reg_write(vpu, &g2_compress_swap, 0xf);
/* Start decoding! */
vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT);
return 0;
}
| linux-master | drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c |
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